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  Barrel shifter for a microprocessorRelated Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Processing Architecture, Microprocessor Or Multichip Or Multimodule Processor Having Sequential Program ControlThe Patent Description & Claims data below is from USPTO Patent Application 20050289323. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATION(S) [0001] This application claims priority to provisional application No. 60/572,238 filed May 19, 2004, entitled "Microprocessor Architecture," hereby incorporated by reference in its entirety. FIELD OF THE INVENTION [0002] This invention relates generally to microprocessor architecture and more specifically to a design for a rotation and shifting logic element of a microprocessor. BACKGROUND OF THE INVENTION [0003] Data within a computer or other digital circuit is typically organized into one or more standard data sizes, referred to as data words. For example, a very common data word size contains 32 bits of binary data (zeros and ones). The size of the data word affects precision and/or resolution of the information contained within the digital circuit, with larger data sizes allowing greater precision and/or resolution because they can represent more values. Larger data words, however, require larger digital circuits to manipulate the data, leading to greater cost and complexity. In addition to manipulating data of a maximum data size, many digital circuits also allow data of smaller, evenly divided sizes to be manipulated. For example, a digital circuit with a maximum data word size of 32 bits might also manipulate 8-bit or 16-bit data. A data operand that is half the size of the maximum data word is typically called a half-word. When the extra precision is not required, manipulating smaller data operands may provide advantages such as requiring less memory to store the data or allowing multiple data operands to be manipulated simultaneously by the same circuit. [0004] Two manipulation operations that have proven to be useful when working with digital data are rotation and shifting. The bits of data within a data word are arranged in a fixed order, typically from most significant bit (MSB) in the leftmost position to least significant bit (LSB) in the rightmost position. The rotation operation takes a data word as an input operand and rearranges the order of the bits within that data word by moving bit values to the left or the right by a number of bit positions which may be fixed or may be specified by a second input operand. When rotating to the left, bit values that are moved past the MSB bit position are inserted into the right side bit positions which have been left vacant by the other bits being moved to the left. When rotating to the right, bits that are moved past the LSB bit position are inserted into the left side bit positions in the same manner. For example, consider a 32-bit data word: [0005] 0101 0001 0000 0000 0000 0000 1010 1110 [0006] An instruction to rotate this data word left by four bits results in the new value: [0007] 0001 0000 0000 0000 0000 1010 1110 0101 [0008] Since the values of the bits that are being rotated out the top or bottom of the data word are wrapped around and inserted at the other end of the data word, no bit values are lost. [0009] The second operation, shifting, also takes a data word as an input operand and rearranges the order of the bits within that data word by moving bit values to the left or the right by a number of bit positions which may be fixed or may be specified by a second input operand. A shift operation, however, discards the bit values that are moved past the MSB or LSB bit positions. The bit positions that are left empty by the shift operation are filled with a fixed value, most commonly either with all 0s or all 1s. As an example, consider a 32-bit data word: [0010] 0101 0001 0000 0000 0000 0000 1010 1110 [0011] An instruction to shift this word left by four bits results in the new value: [0012] 0001 0000 0000 0000 0000 1010 1110 0000 [0013] It is also common when shifting to the right to use the value of the input at the MSB bit position to fill the bit positions that are left empty. For signed binary numbers, this has the property of ensuring that the number keeps the same sign. [0014] As noted above, shifting and rotation are manipulation functions frequently performed in the execution stage of a microprocessor pipeline. Most microprocessors employ a logic unit known as a barrel shifter for effecting bitwise shifts of binary numbers. Barrel shifters permit shifting of an N bit word either to the left or to the right by 0, 1, 2, . . . N-1 bits. As noted above, a typical 32-bit barrel shifter will consist of a series of multiplexers. Referring to FIG. 1, a conventional right and left barrel shifter structure 100 is shown. In order to permit bi-directional shifting, duplicative hardware is used in parallel, with one side performing leftward shifts and the other performing rightward shifts. A single 5-bit control line will tell each stage of the multiplexer to effect a shift. In this manner, any combination of shifts between 0 and 31 bits may be effected by enabling various combinations of the 5 multiplexer stages. For example, a nine-bit shift would have a control signal of 01001, enabling the 1.sup.st and the 4.sup.th multiplexers while disabling the others. One of the parallel shifters will perform a right directional shift while the other performs a left directional shift. Selection logic at the output of the last of each parallel multiplexer will select the appropriate result. [0015] The conventional barrel shifter is effective at shifting, however, it is a less than ideal solution because the redundant hardware structure occupies extra space on the chip, consumes additional power and complicates the hardware design. The hardware complexity of this 32-bit barrel shifter can be characterised by the number of 2:1 multiplexers required to implement its functionalities. In this case, 5 stages each of 32 2:1 multiplexers are required resulting in 160 2:1 multiplexers. In general, the number of 2:1 multiplexers required to implement an N-bit barrel shifter, where N is a positive integer and a power of 2, is N log.sub.2(N). As noted above, a typical processor needs two such barrel shifters to implement both left and right shifts. In the case of a 32-bit processor, this requires 320 2:1 multiplexers. With two such barrel shifters working in parallel on the same input data, the rotation operation can also be implemented with additional logic to compute the effective shift distance required in each shifter and then combining the results of the shift operations. This can be illustrated by way of an example of rotating a 32-bit number to the right by 4 bit positions. In this case, the right shifter has to shift the input data by 4 bit positions and the left shifter has to shift the input data by 28 bit positions. The rotation result can then be obtained by combining the two shifter outputs using the bitwise logical OR operation. In general, to rotate the input data by D bit positions, where D is a non-negative integer less than the data word length N, a shift distance of D is applied to the shifter of the same direction as the rotation and a shift distance of (N-D) is applied to the shifter of the opposite direction. In a processor that supports negative shift distance, further additional logic is required to compute the absolute value of a negative shift distance and apply it to the shifter with a shift direction opposite to the specified one. [0016] It should be appreciated that the description herein of various advantages and disadvantages associated with known apparatus, methods, and materials is not intended to limit the scope of the invention to their exclusion. Indeed, various embodiments of the invention may include one or more of the known apparatus, methods, and materials without suffering from their disadvantages. [0017] As background to the techniques discussed herein, the following references are incorporated herein by reference: U.S. Pat. No. 6,862,563 issued Mar. 1, 2005 entitled "Method And Apparatus For Managing The Configuration And Functionality Of A Semiconductor Design" (Hakewill et al.); U.S. Ser. No. 10/423,745 filed Apr. 25, 2003, entitled "Apparatus and Method for Managing Integrated Circuit Designs"; and U.S. Ser. No. 10/651,560 filed Aug. 29, 2003, entitled "Improved Computerized Extension Apparatus and Methods", all assigned to the assignee of the present invention. SUMMARY OF THE INVENTION [0018] Thus, there exists a need for a barrel shifter that ameliorates and/or eliminates one or more of the above noted problems. In particular, there exists a need for a barrel shifter with reduced power consumption, improved performance and/or reduction of silicon footprint as compared with conventional barrel shifter devices. [0019] In various embodiments, this is accomplished through a microprocessor architecture that utilizes a barrel shifter characterized by reduction in complexity, reduced power consumption and enhanced capability over conventional barrel shifter designs. In various exemplary embodiments, the barrel shifter comprises a 64 bit right-shifting barrel shifter capable of right and left directional shifts of a 32 bit input with positive or negative shift distance. In various exemplary embodiments, a right shift of n bits (n<32) is equivalent to a negative left shift of 32-n bits, and a left shift by n bits is equivalent to a negative right shift of 32-n bits. In various exemplary embodiments, the barrel shifter is comprised of a 5 series oriented multiplexers, each shifting by a distance of 1, 2, 4, 8, 16 and 32 bits respectively. The barrel shifter also takes advantage of the fact that all bits between the bit length of the multiplexer stage and the 64.sup.th bit are zero. As a result, no hardware is necessary to keep track of these bits. Thus, five series multiplexers having lengths of 33, 35, 39, 47 and 63 bits respectively can be employed having a reduced hardware footprint as compared to five 64-bit multiplexers or dual 32 bit multiplexers as are typically employed. Such a barrel shifter also permits rotation functions with minimal additional hardware logic. [0020] At least one embodiment of the invention provides a barrel shifter comprising a 2N bit shifter having an upper N bit portion for receiving an N bit input and an lower N bit portion, wherein an X-bit right shift, X<N of a number yields an X bit right shift in the upper portion and an N-X bit left shift in the lower portion of the 2N bit barrel shifter, and further wherein N is an integer power of 2. Continue reading... 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