| Ball grid array copper balancing -> Monitor Keywords |
|
|
 
Ball grid array copper balancingRelated Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, To Form Ohmic Contact To Semiconductive Material, Forming Solder Contact Or Bonding PadBall grid array copper balancing description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070184644, Ball grid array copper balancing. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATION(S) [0001] This application is a divisional of U.S. application Ser. No. 10/610,317 filed Jun. 30, 2003, which is incorporated herein by references. FIELD OF THE INVENTION [0002] The present invention is related to ball grid array packages. More specifically, the present invention relates to methods and apparatus for ball grid array copper balancing. BACKGROUND OF THE INVENTION [0003] The semiconductor industry has seen tremendous advances in technology in recent years that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second), to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die, and on the exterior of the semiconductor packages that receive the die for connecting the packaged device to external systems, such as a printed circuit board. [0004] Ball grid array (BGA) packages are now used in many applications to provide the necessary number of external electrical connections on the die and on the exterior surface of the semiconductor packages. A BGA is a surface-mount chip package that uses a grid of solder balls for connectors. BGAs are available in both plastic and ceramic carriers. BGAs are noted for their compact size, high lead count and low inductance, that allows lower voltages to be used. BGA chips are easier to align to the printed circuit board, since the leads, which are called "solder balls" or "solder bumps," are farther apart than leaded packages. The bonding pads are also located on the side of the die nearest the transistors and other circuit devices formed in the die. As a result, the electrical path to the pad is shorter than the electrical path associated with other packaging techniques. Connection to the package is made when the chip is flipped over and soldered. As a result, the ball grid array packaged dies are commonly referred to as "flip chips" in the industry. Each bump connects to a corresponding package inner lead. In some instances, the packages are also referred to as "Area Grid Array" packages or Chip Size Packages (CSPs). [0005] A typical BGA package is characterized by a large number of solder balls or bumps disposed in an array on a surface of the package. It is not uncommon to have hundreds of solder balls or bumps in an array. The BGA package is assembled to a matching array of conductive pads. The pads are connected to other devices within a substrate or circuitry on a circuit board. Heat is applied to reflow the leads (solder balls or bumps) on the package, thereby wetting the pads on the substrates and, once cooled, forming electrical connections between the package and the semiconductor device contained in the package and the substrate. [0006] Certain designs, for example communication and wireless LDI (Low Density Interconnect) packages, often need less than the maximum number of leads (bumps or balls) available or allowed on a die. As a result, the die will have depopulated BGA lands. Areas of depopulated lands are generally referred to as voided areas. Leads (bumps or balls) corresponding to the depopulated area of the die are also not provided on the package. As a result, the package also has a void or voided areas. The package also has a lesser amount of copper than a package which mates with a die that uses all the leads (bumps or solder balls). The voids generally result in less copper on the exterior layers, as well as between layers and within layers of the package having less than the maximum number of leads (balls or bumps) for the BGA. In some designs, the depopulation includes a significant percentage of the array. The result of the depopulation of a significant percentage of the array is a copper balance mismatch within a layer or layers of the package, and a copper balance mismatch between layers of the package. Copper imbalance in a substrate design can result in failures of the die and package. [0007] Other types of packages also may have depopulated areas and have copper imbalances as well. There are many other types of packages including pin grid arrays, bump grid arrays, dual in line packages (DIPs), quad flat packs, gull wing surface mount, and other packages for dies. [0008] Currently, copper imbalances are corrected by adding a copper mesh covering a portion or the entire area of the package devoid of copper. These current solutions use a significant amount of the surface area and hinder the designer when routing actual electrical paths within a layer or between layers of the package or die. BRIEF DESCRIPTION OF THE DRAWINGS [0009] The invention is pointed out with particularity in the appended claims. However, a more complete understanding of the present invention may be derived by referring to the detailed description when considered in connection with the figures, wherein like reference numbers refer to similar items throughout the figures, and: [0010] FIG. 1 illustrates a side view of an electronic package that includes a carrier and a die that incorporates an embodiment of this invention. [0011] FIG. 2 illustrates a bottom view of an electronic package that includes a portion of an array of input pads and output pads, according to an embodiment of the invention. [0012] FIG. 3 illustrates a bottom view of an electronic package that includes a completed array, including input pads, output pads, and electrically isolated pads, according to an embodiment of this invention. [0013] FIG. 4 illustrates a cross-sectional view of an electrically isolated pad along line 4-4 in FIG. 3, according to an embodiment of the invention. [0014] FIG. 5 illustrates a bottom view of an electronic package that includes a portion of an array of various input pads, output pads, isolated pads and attached vias, according to an embodiment of the invention. [0015] FIG. 6 illustrates a top view of an electronic package that includes a portion of an array of various input pads, output pads, and attached vias, according to an embodiment of the invention. [0016] FIG. 7 is a top view of an electronic package that includes a completed array, including input pads, output pads, a metallization layer, and electrically isolated pads, metallization layer and attached vias, according to an embodiment of this invention. [0017] FIG. 8 illustrates a bottom view of an electronic package that includes a completed array, including input pads, output pads, a metallization layer, and electrically isolated pads, metallization layer and attached vias, according to an embodiment of this invention. [0018] FIG. 9 is a flow diagram of a method for forming an electronic device according to an embodiment of this invention. [0019] FIG. 10 is a flow diagram of a method for forming an electronic device according to another embodiment of this invention. [0020] The description set out herein illustrates the various embodiments of the invention and such description is not intended to be construed as limiting in any manner. Continue reading about Ball grid array copper balancing... Full patent description for Ball grid array copper balancing Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Ball grid array copper balancing patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Ball grid array copper balancing or other areas of interest. ### Previous Patent Application: Methods of forming metal layers using multi-layer lift-off patterns Next Patent Application: Active area bonding compatible high current structures Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Ball grid array copper balancing patent info. IP-related news and info Results in 0.14237 seconds Other interesting Feshpatents.com categories: Qualcomm , Schering-Plough , Schlumberger , Seagate , Siemens , Texas Instruments , 174 |
 * Protect your Inventions * US Patent Office filing 
PATENT INFO |
|
