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  Balanced sense amplifier circuitsUSPTO Application #: 20080025114Title: Balanced sense amplifier circuits Abstract: Structures and methods are disclosed for operating Balanced Sense Amplifier Circuits. The structure comprises a reading circuit, which includes a first transistor and a second transistor. The first and second transistors comprise (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode and a second transistor gate electrode, respectively. The structure also comprises a control circuit, which is electrically coupled to the first and second transistor bodies. The structure further comprises a testing circuit, which is electrically coupled to the control circuit and the first and second transistors of the reading circuit. The testing circuit is capable of determining whether strengths of the first and second transistors are different. In response to the testing circuit determining that the strengths of the first and second transistors are different, the control circuit is capable of adjusting the voltage of the first transistor body. (end of abstract)
Agent: Schmeiser, Olsen & Watts - Latham, NY, US Inventors: Vinod Ramadurai, Daryl Michael Seitzer USPTO Applicaton #: 20080025114 - Class: 365189150 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20080025114. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a continuation application claiming priority to Ser. No. 11/275,539, filed Jan. 12, 2006. BACKGROUND OF THE INVENTION [0002] 1. Technical Field [0003] The present invention relates to sense amplifier circuits, and more specifically, to the sense amplifier circuits (sense amp circuits) that can be adjusted to be balanced. [0004] 2. Related Art [0005] Due to process variation typical sense amplifier circuits often have mismatched devices, because the typical sense amplifier circuits often are unbalanced, resulting in read errors. Therefore, there is a need for sense amplifier circuits that can be adjusted to be balanced. SUMMARY OF THE INVENTION [0006] The present invention provides a digital circuit, comprising (a) a reading circuit, which includes a first transistor and a second transistor, wherein the first and second transistors comprise: (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode and a second transistor gate electrode, respectively; (b) a control circuit, which is electrically coupled to the first and second transistor bodies; and (c) a testing circuit, which is electrically coupled to the control circuit and the enable device of the reading circuit, wherein the testing circuit is capable of determining whether (i) strengths of the first and second transistors are different or (ii) the first and second transistors are of equal strength, and wherein, in response to the testing circuit determining that the strengths of the first and second transistors are different, the control circuit is capable of adjusting the voltage of the first or second transistor body. [0007] The present invention also provides a circuit adjusting method, comprising providing a digital circuit, which includes (a) a reading circuit, which includes a first transistor and a second transistor, wherein the first and second transistors comprise: (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode and a second transistor gate electrode, respectively, (b) a control circuit, which is electrically coupled to the first and second transistor bodies, respectively, and (c) a testing circuit, which is electrically coupled to the control circuit and the first and second transistors of the reading circuit; using the testing circuit to determine, for a first balanced determination round, whether strengths of the first and second transistors are different; and in response to the testing circuit determining that the strengths of the first and second transistors are different, using the testing circuit to cause the control circuit to adjust the voltage of the first transistor body for a first time [0008] The present invention also provides a memory device, comprising (a) a memory cell array comprising N columns, wherein N is a positive integer greater than 1; (b) N sense amp circuits, wherein the N sense amp circuits are electrically coupled one-to-one to the N columns of the memory cell array, each of the N sense amp circuits comprising a first transistor and a second transistor, wherein the first and second transistors include: (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode and a second transistor gate electrode, respectively; (c) N control circuits, wherein the N control circuits are electrically coupled one-to-one to the N sense amp circuits, and wherein each of the N control circuits is electrically coupled to the first and second transistor bodies of the respective sense amp circuit; and (d) N testing circuits, wherein the N testing circuits are electrically coupled one-to-one to the N control circuits and the N sense amp circuits, wherein each of the N testing circuits is capable of determining whether (i) strengths of the first and second transistors of the respective sense amp circuit are different or (ii) the first and second transistors of the respective sense amp circuit are of equal strength, and wherein, in response to the testing circuit determining that the strengths of the first and second transistors of the respective sense amp circuit are different, the respective control circuit is capable of adjusting the voltage of the first transistor body of the respective sense amp circuit. [0009] The present invention provides sense amplifier circuits that can be adjusted to be balanced. BRIEF DESCRIPTION OF THE DRAWINGS [0010] FIG. 1 shows a block diagram of a memory device, in accordance with embodiments of the present invention. [0011] FIG. 2 shows a detail configuration of the memory device of FIG. 1, in accordance with embodiments of the present invention. [0012] FIGS. 3 and 4 show flowcharts that illustrate a sense amp adjustment operation for adjusting a sense amp of the memory device of FIG. 2, in accordance with embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION [0013] FIG. 1 illustrates a block diagram of a memory device 100, in accordance with embodiments of the present invention. Illustratively, the memory device 100 comprises a cell array 110, sense amp circuits 120 which are electrically coupled to the cell array 110, controller circuits 130 which are electrically coupled to the sense amp circuits 120, and testing circuits 140 which provide control signals to the sense amp circuits 120, and the controller circuits 130. More specifically, in one embodiment, the testing circuits 140 send sense amp enable signals 142 to the sense amp circuits 120. In one embodiment, the testing circuits 140 also send SEL0 signals 144 and SEL1 signals 146 to the controller circuits 130. [0014] FIG. 2 illustrates a detail configuration of the memory device 100 of FIG. 1, in accordance with embodiments of the present invention. Illustratively, the cell array 110 comprises multiple word lines (e.g., word lines 220a and 220b). In one embodiment, the cell array 110 also comprises multiple bit line pairs (e.g., a bit line pair 230a, 230b). In one embodiment, the bit line pair 230a, 230b comprises two bit lines 230a and 230b (also called a bit line true (BLT) 230a and a bit line complement (BLC) 230b). The cell array 110 further comprises multiple cells (e.g., cells 210a and 210b) which are arranged in columns and rows. All cells of a same row are connected to a same word line and all cells of a same column are connected to a sense amp circuit via a bit line pair. Although the cell array 110 may have many rows and columns, only two rows and three columns of the cell array 110 are shown in FIG. 2. It should be noted that each row of the cell array 110 may comprise many cells. For illustration, only three cells of a same row are shown in FIG. 2. In one embodiment, the cell 210a can store one bit of information which can be a 0 or a 1. [0015] In one embodiment, each of the cell columns of the cell array 110 is electrically coupled to a sense amp circuit of the sense amp circuits 120 via a bit line pair. Although the sense amp circuits 120 of FIG. 1 may comprise multiple sense amp circuits, only the sense amp circuit 120a is shown in FIG. 2. In one embodiment, the sense amp circuit 120a comprises five transistors M1, M2, M3, M4, and M5. In one embodiment, the transistors M1 and M2 are pFETs (P channel Field Effect Transistor) and the transistors M3 and M4 are nFETs (N channel Field Effect Transistor). In one embodiment, the transistor M5 (also called an enable transistor M5) plays the role of a lock to enable the sense amp circuit 120a. In one embodiment, the transistors M1 and M3 are coupled in series between Vdd and a source/drain electrode of the enable transistor M5. The gate electrodes of the transistors M1 and M3 are tied together to node A and connected to a bit line true (BLT) 240a. In one embodiment, the bit line true 240a is electrically coupled to the bit line true 230a via a switching circuit (not shown). This switching circuit allows the sense amp circuit 120a to connect to the cell 210a and the content of the cell 210a is read. In one embodiment, the transistor M1 is connected with the transistor M3 to form an inverter circuit M1+M3, whose input is node A, and whose output is node B. In one embodiment, the transistors M2 and M4 are coupled in series between Vdd and a source/drain electrode of the enable transistor M5. The gate electrodes of the transistors M2 and M4 are tied together to node B and connected to a bit line complement (BLC) 240b. In one embodiment, the bit line complement 240b is electrically coupled to the bit line complement 230b via the switching circuit (not shown). In one embodiment, the transistor M2 is connected with the transistor M4 to form an inverter circuit M2+M4, whose input is node B, and whose output is node A. As a result, the two inverters M1+M3 and M2+M4 are a cross coupled to form a latch (or a bit register) which can store one bit of information (0 or 1). [0016] In the embodiments described above, each of the cell columns is electrically coupled to a sense amp circuit. In an alternative embodiment, multiple cell columns are electrically coupled to a sense amp circuit. [0017] Assume that the cell 210a is selected. The function of the sense amp circuit 120a is to receive the content of the selected cell 210a via the bit line pair 230a,230b. Then the sense amp circuit 110 amplifies the content of the selected cell 210a and sends it to an output circuit (not shown) through lines OUTPUT1 and OUTPUT2. Because of the construction of the sense amp circuit 210a, the voltages of node A and node B are at different logic. More specifically, if one of the voltages of node A and node B is 0V, then the sense amp circuit 110 causes the other to be 5V. In one embodiment, node A of the sense amp circuit 120a being at 0V and node B of the sense amp circuit 120a being at 5V mean that the sense amp circuit 120a reads a 0 from the cell 210a, whereas the node A of the sense amp circuit 120a being at 5V and the node B of the sense amp circuit 120a being at 0V mean that the sense amp circuit 120a reads a 1 from the cell 210a. In one embodiment, the structure and operation of the other sense amp circuits of the sense amp circuits 120 are similar to the structure and operation of the sense amp circuit 120a. [0018] In one embodiment, each of the sense amp circuits 120 is electrically coupled to a controller circuit of the controller circuits 130. Although the controller circuits 130 of FIG. 1 may comprise multiple controller circuits, only a controller circuit 130a is shown in FIG. 2. In one embodiment, the controller circuit 130a comprises a MUX (multiplexer) 250. Illustratively, the MUX 250 comprises output signals OUT1 and OUT2; input signals V1, V2, and GND (0V); and control signals SEL0, SEL1, and ENABLE. In one embodiment, the output signals OUT1 and OUT2 of the controller circuit 130a are connected to the bodies of the transistors M3 and M4, respectively. In one embodiment, the inputs of the MUX 250 are voltage signals V1, V2, and a ground signal GND wherein V2>V1>0V. [0019] In the embodiments described above, the output signals OUT1 and OUT2 of the controller circuit 130a are connected to the bodies of the transistors M3 and M4, respectively. In an alternative embodiment, the output signals OUT1 and OUT2 of the controller circuit 130a are connected to the bodies of the transistors M1 and M2, respectively. In yet another alternative embodiment, the MUX 250 comprises four output signals OUT1, OUT2, OUT3, and OUT4 which are connected to the bodies of the transistors M1, M2, M3, and M4, respectively. [0020] In one embodiment, the function of the controller circuit 130a of FIG. 2 is to provide appropriate voltages to the bodies of the transistor M3 and M4 via the output signals OUT1 and OUT2, respectively. Each of the output signals OUT1 and OUT2 can be the voltage of V1, V2, or GND (also called strength adjusting voltages). In one embodiment, if the control signal ENABLE is at the voltage of low level, both the output signals OUT1 and OUT2 receive the voltage of GND. In one embodiment, if the control signal ENABLE is at the voltage of high level, the MUX 250 receives the control signals SEL0 and SEL1 (binary bit signals) to provide 4 cases of pair of voltages (0 and V1), (0 and V2), (V1 and 0), and (V2 and 0) to the output signals OUT1 and OUT2, respectively. The structure and operation of the other controller circuits of the controller circuits 130 are similar to the structure and operation of the controller circuit 130a. Continue reading... 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