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Array transformation in a behavioral synthesis tool

The present invention relates generally to behavioral synthesis tools for creating integrated circuits, and more particularly relates to behavioral synthesis tools that provide for improved packing of arrays to memory.

With the proliferation of data-intensive applications, such as sound, image and video processing, the memory subsystem has become an important focus of electronic system design. More than three-quarters of a data-intensive system can be made up of storage components, making the memory subsystem the most crucial part of the design of an integrated circuit. Most of these systems need to be high-speed due to the large amounts of data involved and must be designed carefully to avoid a solution that is larger than expected.

The design of an integrated circuit no longer begins with a circuit diagram. Instead, it begins with a software program that describes the behavior or functionality of a circuit. This software program is a source code description that defines an algorithm to be performed with limited implementation details. Designers direct behavioral synthesis tools to convert the source code description into a register transfer level (RTL) description. The RTL description is used to ultimately generate a netlist that includes a list of components in the circuit and the interconnections between the components. This netlist is used to create the physical integrated circuit.

Arrays provide a powerful and convenient method for modeling the behavior of memories in source code descriptions. That is, behavioral descriptions are used to manipulate groups of data in an abstract manner using arrays. These arrays are, under the control of the designer, packed to memory. Behavioral synthesis tools automatically construct the logic to control the memory, freeing the designer to explore architectures using different memories with different characteristics (e.g., synchronous versus asynchronous, single port versus dual port), and make intelligent decisions about an appropriate implementation for a design.

To pack arrays to a memory, the designer must specifically assign the variables representing the arrays to a memory in source code and specify the type of memory and other memory parameters. This is accomplished using a set of attributes or directives. For example, Synopsis® tools use a “pragma” statement.

After the designer designates the details of memory allocation in the source code description (using pragma statements or other directives), the designer runs the source code description through the synthesis tool. The synthesis tool generates a report that the designer can use to analyze the performance of the circuit. For example, the user can examine the speed and area of the circuit to determine whether the current memory allocation is acceptable. If the memory allocation is not acceptable, the designer must return to an editor, re-edit the source code description to change the details of memory allocation, and run the source code description through the synthesis tool again. Such a technique for modifying the memory allocation is time consuming and inefficient and gives the designer only a limited amount of options for designating how memory will be allocated.

It is desirable, therefore, to provide a method and synthesis tool that allows a designer to modify memory resources more quickly and simply as well as provide the designer with more advanced options for specifying how arrays will be packed to memory.

Methods, systems, and behavioral synthesis tools are provided that allow a designer to change the format of how an array is packed to memory during the memory packing process when converting a source code description of a circuit to an RTL description. The designer can write a source code description at the algorithmic level describing the behavior of the circuit to be designed. The designer then uses a behavioral synthesis tool to generate a number of different architectural designs using synthesis techniques. Each design can implement differing memory allocation by allowing the designer to change a number of different constraints such as whether to use RAMs vs. registers, which type of RAM to use, how many memories to use, whether to use on or off-chip memory, etc. The designer is also provided the ability to transform the layout format of the arrays in the source code description such that the designer can quickly and easily control the packing of the arrays into the chosen memories. These constraints can be changed either using a graphical user interface, changing constraints within the behavioral synthesis tool, or by manually manipulating the source code description. The behavioral synthesis tool then creates a report for each design to analyze the performance of the circuit. For example, the designer can examine and compare the speed and area of the circuits created from each of the designs to determine whether the memory performance and size are acceptable.

A source code file having a description of the hardware is read into a database within the behavioral synthesis tool. The behavioral synthesis tool analyzes the source code description and generates a data structure associated with the source code description. The designer can then modify a number of constraints dictating the details of memory allocation such as type of memory, number of memories, memory size, etc. Thus, rather than having to re-edit the source code description, the designer can change these memory constraints interactively and dynamically during the memory packing process to control how arrays are packed into memory. Once the designer is satisfied with the design, an RTL description is produced from the data structure.

A number of additional options for packing arrays into memory are provided by the behavioral synthesis tool to the designer so that the designer may select one of a plurality of array layout formats during the memory packing process. Providing the designer the ability to transform the layout of arrays dynamically allows the designer a fast, efficient method of customizing the memory allocation of the circuit to be synthesized.

Further features and advantages of the invention will become apparent with reference to the following detailed description and accompanying drawings.

FIG. 1 is a block diagram of a system for allowing interactive memory allocation.

FIG. 2 is a detailed diagram illustrating a design flow for creating an integrated circuit using the system of FIG. 1.

FIG. 3 is an illustration of directly packing an array to a memory.

FIG. 4(a) is an illustration of packing multiple words of an array into a single word of a memory.

FIG. 4(b) is another illustration of packing multiple words of an array into a single word of a memory.