| Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates -> Monitor Keywords |
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  Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gatesUSPTO Application #: 20060194397Title: Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates Abstract: In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is deposited. A polysilicon layer is deposited. The polysilicon layer, the gate dielectric layer and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations (STI). A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to the top surface of the polysilicon layer to complete the STI. A photoresist layer is deposited and patterned to form a feature mask for planned polysilicon gates. The patterning is by a single exposure using an AAPSM mask. Unwanted features in the photoresist pattern that are caused by phase conflicts overlie the STI. The polysilicon layer is etched to form the polysilicon gates. (end of abstract) Agent: Saile Ackerman LLC - Poughkeepsie, NY, US Inventors: Lay Cheng Choo, James Meng Yong Lee, Lap Chan USPTO Applicaton #: 20060194397 - Class: 438296000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Including Isolation Structure, Dielectric Isolation Formed By Grooving And Refilling With Dielectric Material The Patent Description & Claims data below is from USPTO Patent Application 20060194397. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This is a Divisional application of U.S. patent application Ser. No. 10/135,071, filed on Apr. 20, 2002, which is herein incorporated by reference in its entirety, and assigned to a common assignee. BACKGROUND OF THE INVENTION [0002] (1) Field of the Invention [0003] The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of using an alternating aperture phase shift mask to fabricate sub 0.18 micron polysilicon gate transistors. [0004] (2) Description of the Prior Art [0005] Device shrinkage requires photolithographic enhancements to extend the capabilities of the processes. One such enhancement is the use of phase shift masks. Phase shifting masks are used when the desired feature size of an integrated circuit layer is on the same order of magnitude as the wavelength of light used in the photolithographic process. [0006] In a typical photolithographic mask, layer features, or traces, are formed on the mask in an opaque material such as chrome. This chrome layer is formed overlying a transparent quartz substrate. Light is shown through this mask to expose a photosensitive material, commonly photoresist, as defined by the mask pattern. After the photoresist is developed, the photoresist will reflect a copy or a reverse copy of the mask pattern. [0007] As the pattern features approach the wavelength of the exposure light and the limits of the photolithographic equipment alignment and repeatability, it is increasingly difficult to successfully transfer the pattern features. In practice, it is found that the current 248 nanometer lithographic tools cannot reliably create patterns below 0.15 microns. [0008] One approach to extending the capability of the current lithographic technology is the application of phase shifting masks. In a phase shifting mask, an additional component is added to the chrome and quartz system. Either through the application of an additional transparent layer or the through the removal of a portion of the quartz layer to a specific depth, the optical properties are changed in a part of the transparent (not covered by chrome) sections of the mask. Specifically, when light of the lithographic wavelength is shown through the mask, a phase shift is created between light waves that pass through the phase shifted area and the light waves that pass through the non-phase shifted area. By shifting the phase of the light by 180 degrees, nodes, or cancellations of energy will occur at opaque boundaries between the phase shifted and non-phase shifted areas. This principle is used to create more sharply defined boundary conditions during the photolithographic exposure. Sharper definition leads to improved pattern transfer. [0009] The phase shifted mask principle has been applied using an alternating aperture phase shift mask (AAPSM) approach. In AAPSM, the transparent mask sections are alternated between 0 degrees (non-shifted) and 180 degrees (shifted). The resolution limit of periodic line patterns can be improved by a factor of two using AAPSM. However, application of AAPSM to random lines is limited and made difficult due to phase conflicts at direct boundaries between phases where no opaque line separates the phase areas. Techniques that have been employed to eliminate these problems include utilizing a multiphase boundary (such as 60 degrees steps) and using a binary trimming mask to expose the unwanted areas. The use of multiphase AAPSM causes problems in mask fabrication and cause space constraints. [0010] The use of the prior art binary trim mask method is illustrated beginning in FIG. 1. A cross section of a prior art device is shown. A semiconductor substrate 10 is provided. Shallow trench isolations (STI) 14 are formed in the semiconductor substrate 10. The STI 14 separate and isolate active areas. A gate oxide layer 18 is formed overlying the semiconductor substrate 10 and the STI regions 14. A polysilicon layer 22 overlies the gate oxide 18. Note that the top surfaces of the STI regions 14 are co-planar with the top surface of the semiconductor substrate 10. [0011] Referring now to FIG. 2, a top view of a planned memory cell 38 is shown. In this cell, two p-well active areas 30 and two n-well active areas 32 are shown. Polysilicon traces 34 overlie the active areas 30, 32 to form transistors 36. Six transistors are formed in the memory cell. Note that the polysilicon layer 34 also provides common connectivity for the cell. [0012] Referring now to FIG. 3, a first mask 39 used for the first step of patterning the planned polysilicon traces is shown. Chrome traces 42 are formed with the minimum lithographic width L1 for the typical process. This mask represents the binary image of the layout of the polysilicon layer for the cell. Non chrome areas are transparent. For example, the minimum width L1 is 0.18 microns. This same minimum width L1 is used even in the transistor areas 36. Following the application of a photoresist layer overlying the polysilicon layer 22 of FIG. 1, a first exposure is performed using the chrome mask 39 of FIG. 3. Following the first exposure, the photoresist is not developed. [0013] Referring now to FIG. 4, a second mask 41 is shown. This mask utilizes an alternating aperture phase shift mask (AAPSM) approach. The second mask 41 is a dark field mask so that most of the area is chrome 51 with openings 46, 50. Non-phase shifting areas 46 are formed parallel to phase shifting areas 50. Both the non-phase shifting areas 46 and the phase shifting areas 50 allow light passage. Both non-phase shifting areas 46 and phase shifting areas 50 overlap the chrome pattern of the first mask 39 of FIG. 3. The space L2 between the non-phase shifting areas 46 and the phase shifting areas 50 is smaller than the minimum width L1 of the chrome mask 39. In the art, the minimum space L2 between phase areas is between about 0.09 microns and 0.15 microns. This second mask 41 is used in a second exposure of the photoresist and acts a trim mask because the second exposure trims back some of the unexposed photoresist. The presence of the non-phase shifting areas 46 and the phase shifting areas 50 allows a narrower line width to be formed in the photoresist. [0014] Referring now to FIG. 5, the top view of the resulting memory cell 47 is shown. After the second exposure step, the photoresist layer is developed. The polysilicon layer is etched to form traces 54. Note that the polysilicon layer 54 is narrower in the gate regions where it overlies the active areas for the p-well 30 and n-well 32. The two mask AAPSM sequence allows shorter gate length transistors to be formed. [0015] Referring to FIG. 6, a cross sectional view of the finished prior art device is shown. [0016] There are three drawbacks to the process of the prior art. First, this process requires two masking steps that must be very carefully aligned. This is both expensive and time consuming. Second, because the polysilicon layer 54 is used as both the interconnecting layer and the gate layer, the memory cell must be made relatively large. The polysilicon layer 54 connectivity points must be sufficiently spaced from the active areas 30, 32 so that parasitic transistors are not created. Third, if the first and second masking steps are not perfectly aligned, open or high resistivity connections can be created. [0017] Referring now to FIG. 7, a representative top view of a transistor created in the prior process is shown. The polysilicon layer 54 overlies the p-well active area 30 to form a transistor. A misalignment between the first chrome mask 39 and the second phase shifting mask 41 has caused the connectivity section of the polysilicon to be offset 58 from the gate. Though this is not an open circuit, the offset will cause a larger than normal gate resistance that will diminish device performance. [0018] Several prior art approaches concern methods to create or to use phase shifting masks in the manufacture of integrated circuits. U.S. Pat. No. 5,468,578 to Rolfson teaches a process to form alternate aperture phase shift masks (AAPSM) where two E-beam writes are used. A four step method is disclosed to: (1) identify phase conflict areas in the mask data; (2) connect together adjacent planned transparent areas in phase conflict locations; (3) deposit and pattern opaque material to form transparent areas; and (4) phase shifting areas by either etching down transparent areas or by adding phase shifting material in every other transparent opening and in all connecting areas. U.S. Pat. No. 5,670,281 to Dai discloses a method to form phase shift masks that eliminates bridging problems due to phase conflicts at the ends of parallel features. Fine tips, that is, triangle shaped ends, are used to eliminate phase conflict problems. Methods for forming 180 degree phase shift material using either subtraction of transparent material or addition and patterning of a phase shift layer are disclosed. U.S. Pat. No. 5,935,740 to Pierrat discloses a process to form alternate aperture phase shift masks where multiple layers of light transmitting, phase shifting material are used. Each phase shifting layer is optimized to shift the incident light 60 degrees. By patterning the phase shifting layers, complementary phase shifting patterns are created in adjacent circuit areas. U.S. Pat. No. 5,582,939 to Pierrat teaches a process to form phase shift masks where bump defects in the phase shifting material are removed. SUMMARY OF THE INVENTION [0019] A principal object of the present invention is to provide an effective and very manufacturable method of fabricating a polysilicon gate transistor in the manufacture of integrated circuits. [0020] A further object of the present invention is to provide a method of a fabricating polysilicon gate transistor where an alternating aperture phase shift mask (AAPSM) is used to pattern the polysilicon gates. [0021] A yet further object of the present invention is to provide a method of fabricating a polysilicon gate transistor where an alternating aperture phase shift mask (AAPSM) is used to pattern the polysilicon gates using a single alignment and exposure step. [0022] Another yet further object of the present invention is to provide a method of fabricating a polysilicon gate transistor where an alternating aperture phase shift mask (AAPSM) is used to pattern the polysilicon gates where unwanted pattern features in the lithographic process caused by phase conflicts fall over shallow trench isolation (STI) regions and are therefore not transferred to the polysilicon layer. Continue reading... Full patent description for Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. 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