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  Apparatus to improve bandwidth for circuits having multiple memory controllersUSPTO Application #: 20060236007Title: Apparatus to improve bandwidth for circuits having multiple memory controllers Abstract: An apparatus for improving bandwidth for circuits having a plurality of memory controllers employing a first memory controller, a second memory controller, a first busy read output signal circuit, a first busy write output signal circuit, a second busy read output signal circuit, and a second busy write output signal circuit. The first busy read output signal indicates when the first memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the first memory controller. The first busy write output signal indicates when the first memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the first memory controller. The second busy read output signal indicates when the second memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the second memory controller. The second busy write output signal indicates when the second memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the second memory controller. (end of abstract)
Agent: Schneck & Schneck - San Jose, CA, US Inventor: Eric Matulik USPTO Applicaton #: 20060236007 - Class: 710107000 (USPTO) Related Patent Categories: Electrical Computers And Digital Data Processing Systems: Input/output, Intrasystem Connection (e.g., Bus And Bus Transaction Processing), Bus Access Regulation The Patent Description & Claims data below is from USPTO Patent Application 20060236007. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001] The present invention relates to memory controllers. More specifically, the present invention relates to control circuits for multiple memory controllers. BACKGROUND ART [0002] An integrated micro-controller device includes a microprocessor, on-chip memories, an interface with external memories including an external bus interface (EBI) used to run application software, a number of standard peripheral modules configured to communicate with the external devices such as an universal asynchronous receiver/transmitter (UART), a serial peripheral interface (SPI), a parallel I/O chip (PIO), or a universal serial bus (USB), and modules to generate interruptions like an interrupt controller, or a timer. [0003] The EBI generates signals required to drive external memories such as a static RAM (SRAM) memory controller; a flash memory controller; a burst flash memory controller; a synchronous dynamic RAM (SD-SDRAM) memory controller; a double date rate synchronous memory controller (DDR-SDRAM); a reduced latency dynamic RAM memory controller, an EEPROM, or a read only memory (ROM). Typically, these signals, like chip select signals, and/or control signals (read/write, enable, strobe) are transmitted using a control bus, an address bus, and/or a data bus. In some types of applications, a micro-controller utilizes an external bus interface (EBI). If this is the case, an EBI may drive several memory devices of different types, like SDRAM, SRAM, and flash, at the same time by generating the corresponding signals for each memory it targets. [0004] The EBI module is often connected on the internal system bus as a slave executing the actions required by the microprocessor which acts as a master in a simplified architecture. The master is able to read/write data from/into the internal memory (RAM) or external memories. Internal memories are often faster than external memory but smaller. Usually, a set of data that requires fast access time (such as interrupt handler software, or any set of data which size is small enough) resides at on-chip memories. When a master sets the internal address bus to a value targeting an on-chip memory (for example, a SRAM), the address decoder asserts the internal selection signal. The EBI is not selected in this case. On the other hand, a large set of data that can be processed at a slower access time, resides at the external memory. When the master starts an access to/from an external memory, the address decoder asserts the internal selection signal. The EBI modules translate the system bus waveforms protocol into the targeted memory waveform protocol. [0005] In this type of prior art architecture, when an external memory requires more than one system bus clock cycle to be accessed, the EBI asserts the "wait" signal to indicate the master that no other access is possible. As a result, the master postpones its next access whatever the destination of the new access is. For example, if the next access target is the external memory, it will postponed because of the wait state which has been asserted to prevent an access to the external bus. [0006] This architecture becomes especially burdensome when several masters are connected on a single system bus to a plurality of slave devices because all of the masters will be put in wait states. In another multiple system bus architecture, where there is a single master per system bus, the master, having initiated the transfer of data, will not be allowed to process any transfer of data to or from other slaves. [0007] FIG. 1 depicts a prior art system architecture 10 with a micro-controller 12 connected to different types of external memories, such as a static RAM (SRAM) memory 14 and a synchronous dynamic RAM (SDRAM) memory by utilizing an external bus interface (EBI) (not shown). If this is the case, the EBI may drive several memory devices of different types, like SRAM 14 and SDRAM 16 by generating the corresponding signals for each memory it targets. [0008] A common port mapping for the EBI includes a single address bus 18, a bi-directional data bus and different control signals. The "chip selects" signals are unique for each memory device. For instance, the chipsel_sram signal 22 is used to select the SRAM memory device 14, whereas the chipsel_sdram signal 24 is utilized to select the SDRAM memory device 16. Each type of memory device requires other specific control signals, like a byte enable signal (not shown) for SRAM 14, and a bank addressing signal (not shown) for SDRAM 16. As it is well known to those skillful in the art, the data transfer cannot occur at the same time on more than one external memory device. Therefore, each control signal output of the micro-controller should have multiple functions to accommodate the needs of different memory devices. [0009] FIG. 2 illustrates a basic prior art micro-controller architecture 40 in more details. The EBI module 42 is often connected on the internal system bus (including an internal address bus 46, an internal data bus 50, an internal read data bus 48, and an internal write data bus 44) as a slave, that is EBI executes the actions required by the microprocessor 52 which acts as a master in a simplified architecture. [0010] In this master-slave model, the master (microprocessor 52) is able to read/write data from/into the internal memory, like ROM, or SRAM on-chip memories 54, or to read/write data from/to the External memories (not shown). An internal memory is in most cases faster than an external memory, but has a lesser data capacity. Therefore, the data that requires a fast access time, such as an interrupt handler software, or any data which size is small enough, is targeted into on-chip memories. [0011] When the master (microprocessor 52) sets the internal address bus 46 to a value targeting an on-chip memory 54 (for example, the SRAM memory), the address decoder 56 asserts the internal "sel_intram" internal selection signal 58. The EBI 42 is not selected in this case. [0012] On the other hand, a large set of data that accepts a slower access time can be stored in the external memory. If this is the case, when the master (microprocessor 52) starts an access to/from an external memory, the address decoder 56 asserts the internal "sel_ebi" selection signal 60 via the EBI module 42 that translates the system bus waveforms protocol into the targeted external memory waveform protocol. When an external memory (not shown) requires more than one system bus clock cycle to be accessed, the EBI 42 asserts the "wait" signal (not shown) to indicate the master (microprocessor 52) that no other access to any kind of destination device is possible. If this is the case, the master (microprocessor 52) postpones its next access to any other device. [0013] Thus, in this prior art system bus architecture where a single system bus is allocated for the master, the master that initiated the transfer to any type of device that requires more than one system bus clock cycle to be accessed will not be allowed to process any transfer to any other device until the first transfer is completed. [0014] This situation is exacerbated in the prior art multiple system bus architecture where several masters are connected via a single system bus to several slaves because all the masters will be put in wait states even if a single master has initiated the transfer to any type of device that requires more than one system bus clock cycle to be accessed. [0015] FIG. 3 illustrates a prior art architecture 70 wherein the EBI has several sub-modules, including a SRAM memory controller 72, and a SDRAM memory controller 74. The "Sel_ebi" signal 60 of FIG. 2 includes a plurality of selection signals, whereas each memory controller is assigned its own selection signal. For instance, the SDRAM memory controller 74 is assigned the selection signal "sel_extsdram" 78, and the SRAM memory controller 72 is assigned the selection signal "sel_extsram" 76. The multiplexers MUX1 80 and MUX2 82 are required to share the external address bus 84 and the external data bus 86. If the SRAM memory (not shown) is selected, the "external address bus" 84 is driven by the SRAM controller 72. The multiplexer MUX3 88 allows the SRAM memory controller 72 and the SDRAM memory controller 74 to share the internal read data bus 90. [0016] The generation of "wait" signal 92 is performed at each memory controller level, taking into account the specific characteristics of the memory being driven and at the EBI level where it is necessary to collect all the memory controllers wait information and report a single signal. This is the function of 2_input OR gate 94. [0017] FIG. 4 depicts prior art waveforms for a system including a read access to an external memory requiring one wait state and requiring roughly one clock cycle to release the data bus after the external memory has been de-selected. [0018] The time required to completely release the data bus after the external memory de-selection is called "time data float" (TDF). The EBI asserts the wait signal 116 for three wait cycles 122, though D1 Data value 120 on the EBI data bus 112 is available after only one wait cycle. This is done to prevent any other transfer on EBI until the EBI data bus 112 is released, i.e. until time T2 126 on the system bus clock 102. The wait signal is asserted for the wait period 122 equal to the time data float period TDF. Therefore the next access to external memory cannot start before T2 126. According to the EBI address bus waveform 110 of FIG. 4, the next access starts at the time T3 128, whereas T3=T1+4. Thus, it takes a long time in the prior art to start the next access to the external memory following the initial read access. SUMMARY OF THE INVENTION [0019] To address the shortcomings of the art, the present invention provides an apparatus for improving a bandwidth for circuits having multiple memory controllers by generating a plurality of busy signals that are configured to indicate when the next external access to the data bus is allowed, thus improving the data throughput. [0020] One aspect of the present invention is directed to an apparatus featuring a data bus, a memory controller, a first output signal circuit, and a second output signal circuit. The first output signal is configured to indicate when the memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the memory controller, whereas the second output signal is configured to indicate when the memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the memory controller. Continue reading... Full patent description for Apparatus to improve bandwidth for circuits having multiple memory controllers Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Apparatus to improve bandwidth for circuits having multiple memory controllers patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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