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  Apparatus for evaluating amount of charge, method for fabricating the same, and method for evaluating amount of chargeRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), With Permanent Threshold Adjustment (e.g., Depletion Mode), With Gate Insulator Containing Specified Permanent ChargeThe Patent Description & Claims data below is from USPTO Patent Application 20050263833. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] The present invention relates to an apparatus for evaluating an amount of charge on a semiconductor device and to a method for evaluating an amount of charge on a semiconductor device by using the apparatus. [0002] In the process of fabricating a semiconductor device, charging of the semiconductor device leads to the degradation of reliability and performance thereof. To prevent this, a method for accurately measuring the charging of a semiconductor substrate or a semiconductor device, which occurs in the fabrication process therefor, is necessary. [0003] However, no prior art technology has heretofore provided a method which allows direct measurement of an amount of charge on a semiconductor device and only a method which estimates an amount of charge supposed to have been accumulated in a semiconductor device during the fabrication process therefor is existing. The following is two examples of such an indirect method of estimating an amount of charge. [0004] The first example is a method disclosed in Japanese Laid-Open Patent Publication No. HEI 10-270519 using a MOS capacitor. In accordance with the method, a MOS capacitor having a structure in which a gate insulating film is sandwiched between a semiconductor substrate and an upper electrode is produced and subjected to a target process for which an amount of charge is to be evaluated. Then, a leakage current between the gate (upper electrode) and substrate of the MOS capacitor is measured and an amount of charge accumulated in the semiconductor device is estimated from the result of the measurement. The method uses the experimental fact that a gate leakage current varies depending on a total amount of charge that has flown through the gate as stress. When the charge is accumulated in the MOS capacitor by the specified process, the charge escapes toward the substrate. Since the charge that has passed through the gate insulating film upon the escape toward the substrate forms fixed charge or an interface state in the insulating film, the characteristics of the gate insulating film change so that the leakage current between the gate and the substrate also changes. [0005] The second example is a method disclosed in Japanese Laid-Open Patent Publication No. HEI 05-90374. In accordance with the method, a transistor is produced and subjected to a target process for which an amount of charge is to be evaluated. Then, the current-voltage characteristic of the transistor is measured and an amount of charge accumulated in the semiconductor device is estimated from the difference between current values before and after the process. The method also positively uses the experimental fact that the charge forms fixed charge and an interface state upon passing through the gate insulating film, similarly to the first method, to examine a change in the quality of the gate insulating film based on a drain saturation current Idsat during the operation of the transistor and thereby indirectly examine an amount of charge. [0006] In accordance with each of the foregoing charge-amount estimating methods, the charge produced in the process of fabricating a semiconductor device is evaluated indirectly as the degradation of the gate oxide film so that it is difficult to accurately measure an amount of charge sufficiently quantitatively. [0007] In addition, each of the methods requires an extra step of fabricating the device or the like so that it is difficult to evaluate an amount of charge easily and conveniently. Moreover, the conventional methods are also disadvantageous in that they cannot directly measure the present amount of charge on the semiconductor device. SUMMARY OF THE INVENTION [0008] It is therefore an object of the present invention to provide an apparatus and method for evaluating an amount of charge which allows easy and convenient quantitative evaluation of an amount of charge on a semiconductor device. [0009] A first apparatus for evaluating an amount of charge according to the present invention comprises: a substrate having a substantially intrinsic undoped silicon layer; p-type regions dotted as discrete islands in the undoped silicon layer; and a first insulating layer provided over the undoped silicon layer and the p-type regions. [0010] In the arrangement, positive charge produced during a process such as ion implantation or etching performed with respect to the apparatus for evaluating an amount of charge is accumulated in the p-type regions from a potential viewpoint. By performing wet etching, an amount of charge produced by a specified process on the apparatus for evaluating an amount of charge can be calculated based on the principle of anodization. In particular, the positive charge is retained till the measurement of the amount of charge so that the amount of charge is evaluated quantitatively. [0011] A second insulating layer is provided in a region of the substrate located below the undoped silicon layer. Since the positive charge accumulated in the p-type regions is less likely to leak downwardly in the arrangement, more precise evaluation of the amount of charge can be performed. [0012] Preferably, the second insulating layer has a thickness not less than 1 nm and not more than 500 nm. In particular, the thickness of the second insulating layer which is not less than 1 nm has made the positive charge retained in the p-type regions less likely to leak downward by tunneling. [0013] Preferably, the undoped silicon layer has a thickness not less than 10 nm and not more than 10 .mu.m. Preferably, a concentration of an impurity contained in the p-type regions is not less than 1.times.10.sup.16 cm.sup.-3 and not more than 1.times.10.sup.23 cm.sup.-3. Since the concentration of the impurity contained in the p-type regions is not less than 1.times.10.sup.16 cm.sup.-3, wet etching of the p-type regions is performed effectively. [0014] Preferably, a concentration of an impurity contained in the undoped silicon layer is not more than 1.times.10.sup.15 cm.sup.-3. [0015] The first insulating film has a thickness not less than 1 nm and not more than 500 nm. The arrangement prevents the charge accumulated in the p-type regions from leaking toward the upper surface and allows induction and accumulation of positive charge in the p-type regions after the target process for which an amount of charge is to be evaluated. [0016] A third insulating layer composed of an insulating material is further provided on a back surface of the semiconductor substrate. The arrangement allows even evaluation of an amount of charge using the back-surface scrubbing process. [0017] Preferably, the third insulating layer has a thickness not less than 1 nm and not more than 500 nm. [0018] The apparatus further comprises: a conductor film on the first insulating layer. By dry etching the conductor film, it becomes possible to estimate damage caused by a plasma during the dry etching of a gate electrode. [0019] A second apparatus for evaluating an amount of charge according to the present invention comprises: a substrate having a silicon layer; p-type regions each surrounded by the silicon layer, having a valence band edge potential higher than that of the silicon layer, and composed of silicon containing a p-type impurity; and a first insulating layer provided over the silicon layer and the p-type regions. [0020] If an amount of charge resulting from a certain process is to be evaluated, the arrangement allows confinement and accumulation of positive charge produced by the process in the p-type regions. If etching is performed by using a hydrofluoric acid or the like with the positive charge confined and accumulated in the p-type regions, the amount of charge resulting from the process can be calculated quantitatively from an amount of etching in each of the p-type regions in an easy and convenient manner. [0021] A region of the substrate located under the silicon layer is provided with a second insulating layer. In the arrangement, positive charge accumulated in the p-type regions is less likely to leak downward so that an amount of charge is evaluated more precisely. [0022] A third apparatus for evaluating an amount of charge according to the present invention comprises: a substrate having a first insulating layer; p-type regions dotted as discrete islands in the insulating layer and composed of silicon containing a p-type impurity; and a second insulating layer provided over the first insulating layer and the p-type regions. In the arrangement, the charge accumulated in the p-type regions is less likely to leak not only downwardly but also laterally so that an amount of charge is evaluated more precisely. Continue reading... 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