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  Apparatus and methods for adjusting performance characteristics of circuitry in programmable logic devicesThe Patent Description & Claims data below is from USPTO Patent Application 20060202713. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation-in-part application of U.S. patent application Ser. No. 11/006,420, titled "Apparatus and Methods for Adjusting Performance Characteristics of Programmable Logic Devices," Attorney Docket No. ALTR:042, filed on Dec. 7, 2004, and incorporated here in its entirety. TECHNICAL FIELD [0002] The inventive concepts relate generally to adjusting the performance of programmable logic devices (PLDs). More particularly, the invention concerns adjusting the supply voltage/power consumption of PLDs, as well as noise reduction and isolation in PLDs. BACKGROUND [0003] PLDs are ubiquitous electronic devices that provide flexibility to not only designers, but also end-users. During the design cycle of an electronic circuit or system, a designer may perform a relatively large number of design iterations by simply re-programming the PLD for each design. Thus, the length and expense of the design cycle decreases compared to other alternatives. Similarly, the end-user may have a desired level of control over the functionality of a design that includes PLD(s). By programming the PLD(s) in the field or even on a real-time basis, the user can change the way the circuit or system behaves. [0004] To accommodate increasingly complex designs, modern PLDs include a relatively large number of transistors. Furthermore, users demand ever higher performance, which results in larger operating frequencies. Consequently, the power consumption, power dissipation, die temperatures and, hence, power density (power dissipation in various circuits or blocks), of PLDs has tended to increase. The upward march of the power density, however, may make PLDs design and implementation impractical or failure-prone. A need exists for PLDs that feature adjustable performance, such as adjustable power consumption in various PLD blocks and circuits. SUMMARY [0005] The disclosed concepts relate to the management and control of power consumption, the provision of power to various blocks and circuits in PLDs, and the performance of those blocks and circuits and therefore the PLD overall. In one illustrative embodiment, a PLD includes at least one IP block and at least one PLD circuit. The PLD further includes a power management circuit. The power management circuit is configured to control the power provided to the PLD circuit and the at least one IP block. [0006] In another exemplary embodiment, a method of adjusting performance of a PLD includes determining whether the PLD meets a performance characteristic, and adjusting a body bias level of at least a part of the PLD to a prescribed or desired level, according to whether the PLD meets the performance characteristic. The method also includes determining whether the PLD meets another performance characteristic, and characterizing the PLD depending on whether the PLD fails to meet that performance characteristic. [0007] In a third exemplary embodiment, a method of adjusting performance of a PLD that is used to implement a user's design. The PLD includes a set of IP blocks. The method includes determining whether all IP blocks in the set of IP blocks are used, and selectively disabling provision of power to any unused IP blocks. The method further includes determining whether the user's design is to meet performance specifications of a standard, and controlling a level of power provided to at least one of the IP blocks, depending on whether the user's design should meet the performance specifications of the standard. [0008] In a fourth exemplary embodiment, a method of adjusting performance of a PLD includes sorting the PLD according to its performance capability, and determining whether any circuit blocks in the PLD inhibit the PLD from meeting desired performance characteristics. The method further includes adjusting a body bias level within the PLD if the any circuit blocks in the PLD inhibit the PLD from meeting the desired performance characteristics. [0009] Moreover, in a fifth illustrative embodiment, a method of adjusting performance of a PLD during operation of the PLD includes monitoring at least one performance characteristics of the PLD, and determining whether the at least one performance characteristic of the PLD exceeds a desired performance characteristic. The method further includes disabling power to at least one IP block within the PLD if the at least one performance characteristic of the PLD exceeds the desired performance characteristic. BRIEF DESCRIPTION OF THE DRAWINGS [0010] The appended drawings illustrate only exemplary embodiments of the invention and therefore should not be considered as limiting its scope. Persons of ordinary skill in the art who have the benefit of the description of the invention appreciate that the disclosed inventive concepts lend themselves to other equally effective embodiments. In the drawings, the same numeral designators used in more than one drawing denote the same, similar, or equivalent functionality, components, or blocks. [0011] FIG. 1 shows a general block diagram of a PLD according to an illustrative embodiment of the invention. [0012] FIG. 2 illustrates a floor-plan of a PLD according to an exemplary embodiment of the invention. [0013] FIG. 3 depicts a block diagram of an exemplary embodiment of programmable logic in a PLD according to the invention. [0014] FIG. 4 shows a circuit arrangement for adjusting the supply voltage of a desired circuit in a PLD according to an exemplary embodiment of the invention. [0015] FIG. 5 illustrates another circuit arrangement for adjusting the supply voltage of a desired circuit in a PLD according to an exemplary embodiment of the invention. [0016] FIG. 6 depicts a circuit arrangement for reducing the noise level in a PLD according to an exemplary embodiment of the invention. [0017] FIG. 7 shows another circuit arrangement for reducing the noise level in a PLD according to an exemplary embodiment of the invention. [0018] FIG. 8 illustrates an arrangement for providing a flexible mechanism for adjusting the performance of the various parts of a PLD according to an exemplary embodiment of the invention. [0019] FIGS. 9A-9C depict circuit arrangements for distributing and generating power supply voltages in PLDs according to exemplary embodiments of the invention. Continue reading... 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