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  Apparatus and method to trace high performance multi-issue processorsUSPTO Application #: 20070089095Title: Apparatus and method to trace high performance multi-issue processors Abstract: A system and method for program counter and data tracing in a multi-issue processor is disclosed. Instructions are traced in program sequence order. In one embodiment instructions are traced in graduation order from a reorder buffer. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core. (end of abstract) Agent: Cooley Godward Kronish LLP - Palo Alto, CA, US Inventors: Radhika Thekkath, Franz Treue, Soren Kragh, Vidya Rajagopalan USPTO Applicaton #: 20070089095 - Class: 717128000 (USPTO) Related Patent Categories: Data Processing: Software Development, Installation, And Management, Software Program Development Tool (e.g., Integrated Case Tool Or Stand-alone Development Tool), Testing Or Debugging, Monitoring Program Execution, Tracing The Patent Description & Claims data below is from USPTO Patent Application 20070089095. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates generally to on-chip debugging, and more specifically to program counter (PC) and data tracing in embedded processor systems. BACKGROUND OF THE INVENTION [0002] Computer systems process information according to a program that includes a sequence of instructions defined by an application program or an operating system. Typically, a program counter provides a series of memory addresses that are used by the processor for fetching instructions stored in the associated memory. In this process, the processor conveys the memory address to the memory over an address bus, and the memory responds over an instruction/data bus with the instruction stored in the addressed memory location. The instructions stored in the memory constitute the program to be executed. [0003] Program development relies heavily on the verification of the instructions stored in memory as well as their corresponding execution. Typically, these debug efforts are supported by instruction tracing tools that generate a listing of executed instructions during the execution of a program. [0004] The increased control and flexibility in the generation of tracing data is particularly important for the embedded processor industry In the embedded processor industry, specialized on-chip circuitry is often combined with a processor core. However, high performance processors may include features that make it difficult to trace sequential execution of a program. For example, a multi-issue processor may have out-of-order (OOO) dynamic scheduling, deep pipelines, multi-latency pipelines, or support of outstanding load misses. SUMMARY [0005] Broadly speaking, embodiments of the present invention include an apparatus, system, method, computer program product, and data signal embodied in a transmission medium for tracing multi-issue processors in program sequence order. In one embodiment, tracing instructions from a multi-issue processor includes: monitoring a reorder buffer having a graduation cycle for graduating instructions in program order and transmitting trace data for the instructions in graduation order for each graduation cycle along with information that enables a determination of program execution of the instructions. The trace data may be transmitted using a trace interface having a plurality of trace buses. In one embodiment, one or more rules are used to assign trace data to the trace buses to facilitate another element reconstructing the program sequence. [0006] One benefit of the present invention is that it facilitates tracing a complex multi-issue microprocessor having one or more features that may disrupt sequential execution of instructions, such as deep pipelines, multi-latency pipelines, multiple outstanding load misses, out-of-order (OOO) instructions, or superscalarity. BRIEF DESCRIPTION OF THE FIGURES [0007] FIG. 1 illustrates a tracing system according to an embodiment of the present invention. [0008] FIGS. 2 and 3 illustrate aspects of tracing a single instruction pipeline according to an embodiment of the present invention. [0009] FIG. 4 illustrates a portion of a multi-issue processor tracing apparatus according to an embodiment of the present invention. [0010] FIG. 5 illustrates an embodiment of a present invention in which a trace interface includes a plurality of trace slots. [0011] FIG. 6 is a flow chart illustrating one embodiment of a rule that trace generation logic may use to assign trace buses to graduating instructions, [0012] FIG. 7 is a flow chart illustrating an embodiment of a rule that trace generation logic may use in which data associated with an instruction is traced out on the same trace slot. [0013] FIG. 8 illustrates a method of coordinating an end time signal for the case that data from a plurality of graduating instructions are traced out on a plurality of trace buses. [0014] FIG. 9 is a timing diagram for a single instruction pipeline illustrating signals in an exemplary trace interface, [0015] FIG. 10 is a table illustrating a method of tracing instructions in instruction order according to the graduation cycle of a reorder buffer. [0016] FIG. 11 is a table illustrating an exemplary program sequence. [0017] FIG. 12 illustrates the corresponding instruction complete signals for the program sequence of FIG. 11. [0018] FIG. 13 illustrates the trace bus data signals and end point signals associated with FIGS. 11-12. [0019] FIG. 14 illustrates an exemplary data sequence reconstructed from the signals of FIGS. 12-13. DETAILED DESCRIPTION Continue reading... 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