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07/19/07 | 28 views | #20070168790 | Prev - Next | USPTO Class 714 | About this Page  714 rss/xml feed  monitor keywords

Apparatus and method for reducing test resources in testing drams

USPTO Application #: 20070168790
Title: Apparatus and method for reducing test resources in testing drams
Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.
(end of abstract)
USPTO Applicaton #: 20070168790 - Class: 714724000 (USPTO)
Related Patent Categories: Error Detection/correction And Fault Detection/recovery, Pulse Or Data Error Handling, Digital Logic Testing

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Previous Patent Application:
Device and method capable of verifying program operation of non-volatile memory and method card including the same
Next Patent Application:
Circuit and method for testing embedded phase-locked loop circuit
Industry Class:
Error detection/correction and fault detection/recovery

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