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Apparatus and method for reducing test resources in testing dramsRelated Patent Categories: Error Detection/correction And Fault Detection/recovery, Pulse Or Data Error Handling, Digital Logic TestingApparatus and method for reducing test resources in testing drams description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070168790, Apparatus and method for reducing test resources in testing drams. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] This present application is a continuation of U.S. patent application Ser. No. 10/853,573, filed on May 25, 2004, which is a continuation of U.S. patent application Ser. No. 09/653,112, filed on Aug. 31, 2000, now U.S. Pat. No. 6,854,079, which is a continuation-in-part application of U.S. patent application Ser. No. 09/454,808, filed on Dec. 3, 1999, now U.S. Pat. No. 6,530,045, issued on Mar. 4, 2003, each of which is hereby incorporated herein by reference in its entirety. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention relates generally to semiconductor wafer testing and more particularly to an apparatus and method for reducing the pin count necessary to test Rambus dynamic random access memory (RDRAM). [0004] 2. Description of the Related Art [0005] Rambus DRAM (RDRAM) is a general-purpose, high-performance, packet-oriented dynamic random-access memory (DRAM) device suitable for use in a broad range of applications, including computer memory, graphics, video, and other applications. FIG. 1 schematically illustrates an RDRAM device 10 interconnected with a central processing unit (CPU) 11 as part of a typical computer system. The RDRAM device 10 receives clock signals 12, control logic signal 14 and address information 16 from the CPU 11 via a controller 20. Data 17 is written to and read from the RDRAM 10. [0006] FIG. 2 is a block diagram illustrating one 144 Mbit RDRAM configuration in the normal mode. The RDRAM comprises two major blocks: a "core" block 18 comprising banks 22, sense amps 24 and I/O gating 26 similar to those found in other types of DRAM devices, and a control logic block in normal mode 19 which permits an external controller 20 to access the core 18. The RDRAM core 18 is internally configured as 32 banks 22. Each bank 22 has 32,768 144-bit storage locations. [0007] FIG. 3 is a diagram indicating that each of the banks 22 is organized as 512 rows 28 by 64 columns 30 by 144 bits 32. The 144 bits 32 in each column 30 are serially multiplexed onto the RDRAM's I/O pins as eight 18-bit words 34. The most significant bits 17-9 are communicated on I/O pins DQA <8:0>, and the least significant bits 8-0 are communicated on the I/O pins DQB <8:0>. The nine bits on each set of pins are output or input on successive clock edges so that the bits in the eight words are transferred on eight clock edges. [0008] The control logic block 19 in FIG. 2 receives the CMD, SCK, SIO0, and SIO1 strobes that supply the RDRAM configuration information to the controller 10, and that select the operating modes of the RDRAM device 10. The CFM, CFMN, CTM and CTMN pins generate the internal clocks used to transmit read data, receive write data, and receive the row and column pins used to manage the transfer of data between the banks 22 and the sense amps 24 of the RDRAM 10. [0009] Address information 16 is passed to the RDRAM device 10 from the CPU 11 via eight RQ pins 36 as illustrated in FIG. 4. The RQ pins 36 are divided into two groups. Three ROW pins 38 are de-multiplexed into row packets 40 that manage the transfer of data between the banks 22 and the sense amps 24. Five COL pins 42 are de-multiplexed into column packets 44 and manage the transfer of data between the data pins and the sense amps 24 of the RDRAM 10. More detailed information on the operation of RDRAM can be found in Reference A, Direct RDRAM Preliminary Information, Document DL0059 Version 0.9 by Rambus Inc. which is incorporated herein by reference. [0010] Semiconductor chips, such as an RDRAM device 10, contain circuit elements formed in the semiconductor layers which make up the integrated circuits. FIGS. 5A and 5B illustrate a semiconductor chip with exposed bonding pads 46 made of metal, such as aluminum or the like that are formed as terminals of integrated circuits. In normal operation, the control signals 14, the address signals 16, and the data 17 are exchanged with the CPU 11 through connections at these bonding pads 46. [0011] In the manufacturing process, a large number of semiconductor chips, each having a predetermined circuit pattern, are formed on a semiconductor wafer 48 such as that shown in FIG. 6. FIG. 6 illustrates the semiconductor wafer 48 prior to being diced into individual semiconductor chips. Although FIG. 6 only shows a relatively small number of semiconductor chips on the wafer, one skilled in the art will appreciate that many semiconductor chips can be cut from a single wafer. The semiconductor chips 10 are subjected to electrical characteristic tests while they are on the wafer 48 through the use of a testing apparatus, e.g., a wafer probe 50 having a plurality of pins 52. Note that only the head of the wafer probe 50 is shown in FIG. 6. Wafer probe testing is commonly used to quality sort individual semiconductor chips before they are diced from the wafer 48. The primary goal of wafer probe testing is to identify and mark for easy discrimination defective chips early in the manufacturing process. Wafer testing significantly improves manufacturing efficiency and product quality by detecting defects at the earliest possible stages in the manufacturing and assembly process. In some circumstances, wafer probe testing provides information to enable certain defects to be corrected. [0012] FIG. 7 shows a plurality of the conductive pins 52 of the wafer probe 50 of FIG. 6. The pins have respective tip ends 54 positionally adjusted to align with the bonding pads 48 of the RDRAM device 10 to be tested. A wafer probe 50 has a limited number of pins 52 (e.g., 100 pins) available to supply the test signals to the RDRAM device 10 in the wafer 48. The RDRAM devices 10 could be tested in their normal mode, but this would require in excess of 40 pins 52 on the wafer probe 50 to test each chip 10. Others have recognized the benefits of creating a special test mode that enables a semiconductor chip such as an RDRAM device 10 to be tested with fewer pins. Therefore, one skilled in the art will recognize that it is not required to have a pin 52 for every bonding pad 48 on the chip 10. However, prior testing methodology for RDRAM devices 10 requires at least 34 pins 52 on the wafer probe 50 to test each RDRAM device 10. Consequently, the 100 pin wafer probe is restricted to test, at most, two semiconductor chips at one time. As a result, the production time and chip costs are negatively impacted by this limitation. [0013] As set forth above, the prior art method of wafer testing RDRAM chips requires 34 pins 52 to test each RDRAM device 10, of which 18 pins are address and data pins. Following this method, the first operation in selecting the address on the RDRAM core entails precharging the bank 22. Precharging is necessary because adjacent banks 22 share the same sense amps 24 and cannot, therefore be simultaneously activated. Precharging a particular bank 22 deactivates the particular bank and prepares that bank 22 and the sense amps 24 for subsequent activation. For example, when the row 28 in the particular bank 22 is activated, the two adjacent sense amps 24 are connected to or associated with that bank 22, and therefore are not available for use by the two adjacent banks. Precharging the bank 22 also automatically causes the two adjacent banks to be precharged, thereby ensuring that adjacent banks are not activated at the same time. [0014] Selecting one of the 32 banks 22 to precharge requires five address bits to specify the bank address. These address bits are provided in a first control signal. The next operation in selecting an address is activating a row 28 in a selected bank using a second control signal. This operation requires nine address bits to select one of the 512 rows 28, and five address bits to select one of the 32 banks 22, for a total of 14 address bits. The next operation reads a column 30 in an open bank using a third control signal. This operation requires five bank bits. This operation also requires six column bits to select one of the 64 columns 30. [0015] Reducing the number of address bits required to specify the address location to be tested reduces the number of pin connection 52 required on the wafer probe 50 to test each individual RDRAM device 10. Reducing the required number of pin connection 52 therefore allows more devices 10 to be tested at the same time, thus permitting an important reduction in production time and chip costs. As chip sizes continue to decrease, there is a corresponding increase in the number of chips on each semiconductor wafer to be tested. Therefore, the ability to test an increased number of devices at the same time grows in importance. SUMMARY OF THE INVENTION [0016] The invention comprises a method of testing computer memory devices, such as Rambus DRAM. The method requires fewer pin connections to test each chip on a semiconductor wafer than previously known methods. The test is performed on a semiconductor wafer using a wafer probe. The number of pins required is reduced by using a trailing edge of a precharge clock to latch the bank address, thus eliminating the need to perform this function on a later step. In combination with such use of the precharge clock's trailing edge, the number of pins required is further reduced by dividing the chip to be tested into a plurality of array cores and compressing the output data so that only one data pin per array core is required. By reducing the pin count, more DRAMs can be tested at the same time, thus reducing the overall test cost and time for testing a complete wafer. BRIEF DESCRIPTION OF THE DRAWINGS [0017] FIG. 1 is a block diagram illustrating a RDRAM device as part of a computer system. [0018] FIG. 2 is a functional block diagram illustrating the RDRAM chip configuration in the normal mode. [0019] FIG. 3 is a conceptual drawing illustrating the RDRAM bank configured in rows, columns, words, and bits in the normal mode. [0020] FIG. 4 is a conceptual drawing illustrating RQ pins delivering the address information of FIGS. 1 and 2. Continue reading about Apparatus and method for reducing test resources in testing drams... Full patent description for Apparatus and method for reducing test resources in testing drams Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Apparatus and method for reducing test resources in testing drams patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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