| Apparatus and method for overload protection of electronic circuitry -> Monitor Keywords |
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  Apparatus and method for overload protection of electronic circuitryThe Patent Description & Claims data below is from USPTO Patent Application 20080062603. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001]Embodiments of the present invention relate to digital and mixed signal circuit testers. More specifically, embodiments of the present invention are related to the protection of automatic test equipment interfaces against distortion by devices under test. BACKGROUND ART [0002]The use of automatic test equipment (ATE) to test digital circuits of a device under test (DUT) is an important part of manufacturing. Integrated circuit manufacturers routinely perform both logic and parametric tests on integrated circuits with the ATE. For example, logic tests stimulate various terminals of the DUT with input logic signals while monitoring various output signals by the ATE in response to the input logic signal stimulus to determine if the output signals exhibit expected logic patterns. Parametric tests measure analog characteristics of the DUT at its terminals. [0003]When testing power devices, different levels of power are applied to the DUT. Specifically, various power sources are coupled to specific circuit terminals of the DUT. The ATE is capable of testing for power at expected circuit terminals of the DUT. That is, the ATE is designed to handle the power levels at those circuit terminals. In addition, various other sensitive precision measurement options provided by the ATE are coupled to other terminals of the DUT. That is, the ATE is also monitoring other circuit terminals (e.g., low voltage bus signal) that are not expected to have high power levels. [0004]In the case of testing a defective DUT, the power applied to some DUT circuit terminals may be provided improperly to the circuit terminals handling sensitive precision measurement options. For example, there may be a direct short circuit from the circuit terminal handling high power to the circuit terminal handling the sensitive precision measurement options. As such, the higher power levels are improperly conducted to those circuit terminals handling precision measurement options. These improperly introduced higher power levels would damage the ATE. [0005]Prior Art FIGS. 1A, 1B, and 1C illustrate three solutions for preventing higher power levels from damaging an ATE. Each of these prior art solutions are ineffective from fully protecting the ATE from unexpected external stresses, such as higher voltages and current. [0006]Prior Art FIG. 1A discloses a circuit 100A that provides a clamp circuitry 110 for performing a voltage clamp. The clamp circuitry 100 includes a clamping diode 111 and a clamping diode 112. Specifically, clamping diode 111 prevents the input voltage signal at node 119 from rising above one diode voltage drop (e.g., 0.7 volts) above the high voltage clamp level (V.sub.chigh). Also, clamping diode 112 prevents the input voltage signal at node 119 from falling below one diode voltage drop below the low voltage clamp level (v.sub.clow). [0007]However, clamping diodes 111 and 112 are associated with incompatible capacitances and leakage currents. In order for the clamp circuitry 110 to be able to withstand large power fluctuations, the diodes 111 and 112 would have to be prohibitively large. However, these larger diodes 111 and 112 are associated with larger capacitances and leakage currents which are not compatible with the ATE associated with ATE pin 115. As such, the circuit 100A is not suitable for providing overload protection. [0008]Prior Art FIG. 1B discloses a circuit 100B that includes the clamp circuitry 110 of FIG. 1A. Circuit 100B also includes a melting fuse 120 preventing the diodes 111 and 112 from being destroyed. The melting fuse 120 will melt when a higher than expected voltage is applied across its terminals. As such, the melting fuse 120 creates an open circuit that protects diodes 111 and 112 and the ATE associated with ATE pin 115 from the higher voltage. However, the melting fuse 120 is normally too slow to protect the ATE. In addition, after the melting fuse 120 has been melted, the interface with the ATE pin 115 is rendered inoperable. [0009]Prior Art FIG. 1C discloses a circuit 100C that includes the clamp circuitry 110 of FIG. 1A. Instead of the melting fuse 120 of FIG. 1B, the circuit 100C includes a positive temperature coefficient (PTC) resistor 130. The PTC resistor 130 acts to protect the ATE associated with ATE pin 115 from higher voltages by creating an open circuit. In addition, once the fail condition is removed, the PTC resistor 130 will reset back to its original state. [0010]However, several problems are associated with the PTC resistor 130. For instance, the PTC resistor 130 is also normally too slow to protect the ATE. Also, the series resistance is unacceptably high or unstable for use in interfacing with the ATE. Further, the PTC resistor 130 used for overload protection is not normally available for higher voltages (e.g., 100 volts). In addition, the PTC resistor 130 changes characteristics each time it acts to open the circuit to the ATE pin 115 due to high voltages. For example, the resistance of the PTC resistor 130 will increase each time it acts to open the circuit. As such, the PTC resistor 130 is limited in the number of times it can be used to provide overload protection in order ensure consistent operation of the PTC resistor 130 when protecting the ATE associated with the ATE pin 115. SUMMARY OF THE INVENTION [0011]An apparatus and method for overload protection circuit. The apparatus includes a current limiting circuit that is coupled to a first node. A switching element is coupled in series to the current limiting circuit and to a second node. A voltage measurement circuit is coupled to the first and second nodes and is used for measuring a voltage across the first and second nodes. A control mechanism is coupled to the voltage measurement circuit and the switching element. The control mechanism opens the switching element when the voltage exceeds a predetermined value. BRIEF DESCRIPTION OF THE DRAWINGS [0012]The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the invention: [0013]Prior Art FIG. 1A is a circuit diagram of a voltage clamp circuit. [0014]Prior Art FIG. 1B is a circuit diagram of a voltage clamp circuit including a melting fuse. [0015]Prior Art FIG. 1C is a circuit diagram of a voltage clamp circuit including a positive temperature coefficient resistor. [0016]FIG. 2 is a circuit diagram illustrating a protection circuit including an overload protection circuit capable of limiting current, in accordance with one embodiment of the present invention. [0017]FIG. 3 is a circuit diagram of a uni-directional overload protection circuit of FIG. 2, in accordance with one embodiment of the present invention. [0018]FIG. 4 is a circuit diagram illustrating a bi-directional overload protection circuit of FIG. 2, in accordance with one embodiment of the present invention. [0019]FIG. 5 is a flow diagram illustrating steps in a method for providing overload protection, in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION Continue reading... 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