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  Apparatus and method for dynamic control of double gate devicesUSPTO Application #: 20070035981Title: Apparatus and method for dynamic control of double gate devices Abstract: An apparatus for implementing dynamic control of a double gate semiconductor device includes a first switch configured to selectively couple a first gate input of the double gate device to a second gate input of the double gate device, and a second switch configured to selectively couple the second gate input of the double gate device to a selected voltage so as to adjust the threshold voltage of the double gate device. (end of abstract)
Agent: Cantor Colburn LLP - IBM Fishkill - Bloomfield, CT, US Inventors: Alper Buyuktosunoglu, Omer Dokumaci USPTO Applicaton #: 20070035981 - Class: 365129000 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20070035981. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND [0001] The present invention relates generally to integrated circuit devices, and, more particularly, to an apparatus and method for implementing dynamic control of double gate devices. [0002] Complementary metal-oxide-semiconductor (CMOS) technology is the predominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits today. Performance enhancement between generations of devices is generally achieved by reducing the size of the device, resulting in an enhancement in device speed. This is generally referred to as device "scaling." As conventional MOSFETs are scaled to channel lengths below 100 nm, certain problems arise. In particular, interactions between the source and drain of the MOSFET degrade the ability of the gate to control whether the device is on or off. This phenomenon is also referred to as a "short channel effect." [0003] Silicon-on-insulator (SOI) MOSFETs are formed with an insulator (typically, but not limited to, silicon dioxide) below the device active region, as opposed to conventional bulk MOSFETs, which are formed directly on silicon substrates, and hence have silicon below the active region. SOI is advantageous in one respect since it reduces unwanted coupling between the source and the drain of the MOSFET through the region below the channel. However, as device size is scaled even further, this approach also becomes increasingly difficult, since the distance between the source and drain is further reduced, leading to reduced gate control and increased short channel effects. [0004] More recently, double gate devices have emerged as an alternative to conventional single gate CMOS devices for substantially increasing device performance. One specific type of double gate device is what is referred to as a "FinFET," which includes a channel formed in a vertical fin that is controlled by a self-aligned double gate. The fin may be made thin enough such that the two gates can together control the entire fully depleted channel. Although it is a double gate structure, the FinFET is similar to existing planar MOSFET with respect to layout and fabrication techniques. Thus, a FinFET provides a range of channel lengths, CMOS compatibility, and large packing density compared to other double gate structures. [0005] Notwithstanding the advantages of such newer types of device structures, power consumption still remains as one of the limiting factors in the overall chip design. For example, the scaling down of threshold voltage and gate oxide thickness results in a rapid increase in the amount of standby (leakage) power consumed. However, the critical dimensions of the devices fabrication processes have scaled faster than the ability to control parameters such as static power consumption. Accordingly, the constant search for new device structures, coupled with the difficulty in controlling device parameters, has resulted in significant variations across a semiconductor device. This variability in turn makes it more difficult to verify the power consumption, timing and functionality of a design before it can be implemented and manufactured. [0006] In the case of single gate structures, threshold voltage control has been proposed through back-gate biasing to achieve high circuit performance during active periods, and low leakage current during idle periods by means of an extra gate. This technique also provides control through the back-gate body biasing to make devices more robust against design variations. In addition, it is well known that the threshold voltage of a single gate, SOI transistor threshold voltage may be dynamically changed by applying a voltage to a backgate located below the BOX (buried oxide) layer. However, there is presently no known method or structure for dynamically altering the threshold voltage of a double gate device such as a FinFET transistor. [0007] In a FinFET, the first and second gates may be operated independently with respect to one other. Thus, one gate could be used for the control signal while the other gate is used to adjust the threshold voltage. In this case, however, the FinFET is essentially operating in a single gate mode with a backgate attached thereto. The problem therefore lies in configuring a device that may be maintained in the double gate mode of operation (i.e., the first and second gates connected to each other) when maximum device speed is desired, but that also has the capability of having its threshold voltage adjusted when low power operation and mitigation of design variations are desired. SUMMARY [0008] The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by an apparatus for implementing dynamic control of a double gate semiconductor device. In an exemplary embodiment, the apparatus includes a first switch configured to selectively couple a first gate input of the double gate device to a second gate input of the double gate device, and a second switch configured to selectively couple the second gate input of the double gate device to a selected voltage so as to adjust the threshold voltage of the double gate device. [0009] In another embodiment, a method for implementing dynamic control of a double gate semiconductor device includes configuring a first switch for selectively coupling a first gate input of the double gate device to a second gate input of the double gate device, and configuring a second switch for selectively coupling the second gate input of the double gate device to a selected voltage so as to adjust the threshold voltage of the double gate device. [0010] In still another embodiment, an apparatus for implementing dynamic control of a plurality of double gate semiconductor devices includes a first plurality of switches configured to selectively couple a first gate input of a corresponding double gate device to a second gate input thereof, and a second switch configured to selectively couple the second gate input of each of the plurality of double gate devices to a selected voltage so as to adjust the threshold voltage of the double gate devices. BRIEF DESCRIPTION OF THE DRAWINGS [0011] Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures: [0012] FIG. 1 is a schematic block diagram of an apparatus for dynamically controlling a double gate device, in accordance with an embodiment of the invention; [0013] FIG. 2 is a schematic diagram of an exemplary implementation of the apparatus of FIG. 1, wherein the double gate device is p-type; [0014] FIG. 3 is a schematic diagram of another exemplary implementation of the apparatus of FIG. 1, wherein the double gate device is n-type; and [0015] FIG. 4 is a schematic diagram of an apparatus for implementing dynamic control of double gate devices, in accordance with a further embodiment of the invention. DETAILED DESCRIPTION [0016] Disclosed herein is an apparatus and method for dynamically controlling a double gate device by selectively switching the double gate device between a double gate mode of operation (normal operation) and a backgate bias mode (standby, low power mode). In an exemplary embodiment, the double gate devices include finFET architectures such that realization of the dynamic switching does not result in additional complexity to the fabrication process, nor is a new device design needed for the double gate devices. [0017] Briefly stated, the present embodiments provide a control structure for double gate devices that maintains the double gate operation when maximum speed is desired, and that adjusts the threshold voltage of the double gate device when low power operation or mitigation of design variations is desired. To this end, the present disclosure introduces a pair of control switches connected to gate inputs of a double gate device. More specifically, a first switch is configured to selectively connect to both gate inputs of the double gate device together, while a second switch is configured to selectively connect one of the gate inputs to a (variable) biasing voltage. [0018] In a normal operation mode, the first switch connects both gate inputs of the double gate device to one another for achieving maximum speed. Simultaneously, the second switch isolates the double gate device from the biasing voltage. When low power operation and/or mitigation of design variability are desired, the first switch is turned off and the second switch is on. This results in one of the gate terminals of the double gate device to be coupled to the biasing voltage that changes the threshold voltage of device, thus achieving the requirements of low power operation. [0019] FIG. 1 is a schematic block diagram illustrating an apparatus 100 for dynamically controlling the operation of a double gate device, in accordance with an embodiment of the invention. As is shown, a double gate device 102 (e.g., a finFET) includes first and second gate inputs 104 and 106. A first switch 108, through a control signal CTRL selectively couples the gate inputs 104 and 106 together in a normal mode of operation for maximum speed. In other words, the input signal ("input") to the double gate device is coupled to both the first and second gate inputs 104 and 106 in a normal operation mode. At the same time, the control signal CTRL deactivates a second switch 110 such that the second gate input 106 of the double gate device is not coupled to the variable biasing voltage. [0020] In contrast, for low power operation and/or mitigation of design variability, the first switch 108 is deactivated while the second switch 110 is activated through the control signal CTRL. This results in the isolation of the first and second gate inputs 104, 106, with respect to one another. The input signal is coupled only to the first gate input 104, while the variable voltage is now coupled to the second gate input 106 so as to alter the voltage threshold of the double gate device 102. Continue reading... Full patent description for Apparatus and method for dynamic control of double gate devices Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Apparatus and method for dynamic control of double gate devices patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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