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07/27/06 | 35 views | #20060168430 | Prev - Next | USPTO Class 712 | About this Page  712 rss/xml feed  monitor keywords

Apparatus and method for concealing switch latency

USPTO Application #: 20060168430
Title: Apparatus and method for concealing switch latency
Abstract: An multi-threading processor is provided. The multi-threading processor includes a front end module, an execution module coupled to the front end module, and a state module coupled to both the front end module and the execution module. The processor also includes a switch logic module, which is coupled to the state module. The switch logic module detects switching events and mispredicted branches and conceals switch latency by attempting to schedule switches to other software threads during the latencies of the mispredicted branches. (end of abstract)
Agent: Blakely Sokoloff Taylor & Zafman - Los Angeles, CA, US
Inventors: Udo Walterscheidt, Thomas E. Willis
USPTO Applicaton #: 20060168430 - Class: 712228000 (USPTO)
Related Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Processing Control, Context Preserving (e.g., Context Swapping, Checkpointing, Register Windowing

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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)

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