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Alternate sampling integratorAlternate sampling integrator description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070171114, Alternate sampling integrator. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND SECTION [0001] Many embodiments of the disclosure relate generally to electronic integrator circuits, and more particularly, to such circuits utilizing multiple sampling capacitors. [0002] Electronic integrator circuits are devices which produce an electronic output signal which is proportional to the integral of the input signals that they receive. Such devices generally have use in mixed signal applications, for example, in analog-to-digital converters (ADCs); however, such devices also have use in a wide variety of other applications as well. Generally, in such applications, the integrator circuit is used to approximate the mathematical process of integration, that is, sample and integrate an input analog signal over a given period of time. [0003] A commonly known integrator circuit 10 is shown in FIG. 1. As illustrated, the circuit 10 is a switched-capacitor integrator. The circuit 10 involves a number of electrical components including an operational amplifier 12 and two capacitors, a sampling capacitor 14 and an integrating capacitor 16. In addition, a number of switches, 18, 20, 22, and 24, are used to provide an integrating operation. As is known, the switches 18, 20, 22, and 24 are typically operated in distinct phases. For example, in a first phase or sampling phase, switches 18 and 22 are closed while switches 20 and 24 are open. As such, the back end of the sampling capacitor 14 is electrically connected to the input voltage 26 while the front end of the sampling capacitor 14 is grounded. The sampling capacitor 14 is subsequently charged during such sampling phase via the input voltage 26. During a subsequent phase or integrating phase, switches 20 and 24 are closed while switches 18 and 22 are open. In turn, the back end of the sampling capacitor 14 is grounded while the front end of the sampling capacitor 14 is electrically connected to the operational amplifier 12 and the integrating capacitor 16. The voltage on the sampling capacitor 14 is generally discharged to the integrating capacitor 16 via the operational amplifier 12 during such integrating phase. [0004] As shown, since the positive input of the operational amplifier 12 is connected to ground, the voltage at the negative input of the amplifier 12 will almost be the same as the voltage at ground (e.g., virtual ground). In turn, when the input impedance of the operational amplifier 12 is high, the current flowing from the sampling capacitor 14 is generally found to be the same as the current observed flowing through the integrating capacitor 16. As such, the charge placed across the integrating capacitor 16 is generally the same as what is discharged from the sampling capacitor 14. In turn, the voltage gain of the integrator circuit 10 generally equals the ratio between the capacitance of the sampling capacitor 14 and the capacitance of the integrating capacitor 16. [0005] As is generally known, when the output of the integrator circuit 10 of FIG. 1 is electrically coupled to an input of a comparator (not shown), the comparator output following the integrating phase of the integrator circuit 10 can be used in controlling subsequent input reference voltage (not shown) to the integrating capacitor 16. The change of the output voltage of the integrator circuit 10 in the end of a clock cycle will be the input voltage 26 added to either a positive or negative reference voltage, depending on the prior output of the comparator. [0006] As is to be appreciated from the above discussion involving prior art integrator circuit 10, the sampling and integrating phases are distinct. The speed of the integrator circuit 10 can often be limited by these two phases. For example, further sampling by the sampling capacitor 14 during a subsequent sampling phase can only begin after the sampling capacitor 14 is fully discharged and the operational amplifier 12 is stabilized, ending the integrating phase. Likewise, further integration by the integrating capacitor 16 can only begin after the sampling capacitor 14 again is charged, ending the sampling phase. In summary, the integrating phase is only started after completion of the sampling phase, and vice versa. [0007] Expanding on the above, if a multi-stage circuit is designed with multiple integrator stages (each stage including an integrator circuit, e.g., as shown in FIG. 1), the operation of the multi-stage circuit can be negatively impacted by the distinct sampling and integrating phases of each integrator stage. In such circuits, a sampling capacitor of a subsequent stage integrator acts as a load on an operational amplifier of a previous stage. Therefore, the operational amplifier of the previous stage needs time to be stabilized before being sampled by the subsequent stage. This is because the output of the operational amplifier (of the previous stage) can be disturbed via a sudden connection to the sampling capacitor (of the subsequent stage). Sufficient time is, therefore, often needed before the voltage sampled by such sampling capacitor is stabilized. Often, if the sampling period begins prior to such stabilization, the multi-circuit can be found to provide erroneous output. SUMMARY [0008] Certain embodiments of the invention relate to apparatus involving an alternate sampling integrator circuit that can concurrently sample and integrate signals received at an input. The circuit may include multiple sampling capacitors, an operational amplifier, and multiple switches. The switches switch the capacitors between a sampling mode and an integration mode. [0009] In some embodiments, an integrator is provided, comprising circuitry including an operational amplifier and first and second sampling capacitors. The capacitors are positioned along separate signal paths and each in series with an analog signal input and an input of the operational amplifier. The circuitry is configured to concurrently sample and integrate signals received at the analog signal input. [0010] In other embodiments, an integrator is provided, comprising a switched capacitor sampling network having an input for receiving an analog signal. A first portion of the sampling network is in a sampling mode during a first phase of a clock and is in an integrating mode during a second phase of the clock. A second portion of the sampling network is in the integrating mode during the first phase of the clock and is in the sampling mode during the second phase of the clock. [0011] In other embodiments, an integrator circuit is provided, comprising an operational amplifier and first and second sampling capacitors positioned along separate signal paths and each in series with an analog signal input and an input of the operational amplifier. The first and second sampling capacitors sample signals received at the analog input, the operational amplifier integrates signals received at the first input, and the signal paths alternate oppositely between sampling and integrating modes of operation. BRIEF DESCRIPTION OF THE DRAWINGS [0012] FIG. 1 is an exemplary prior art integrator circuit. [0013] FIG. 2 is an integrator circuit in accordance with certain embodiments of the invention. [0014] FIG. 3 is a part of an ADC circuit including the integrator circuit of FIG. 2. [0015] FIG. 4 is an exemplary feedback circuit of the partial ADC circuit of FIG. 3 in accordance with certain embodiments of the invention. [0016] FIG. 5 is a time diagram for the partial ADC circuit of FIGS. 3 and 4. [0017] FIG. 6 is a further integrator circuit in accordance with certain embodiments of the invention. [0018] FIG. 7 is a part of an ADC circuit including the integrator circuit of FIG. 6. [0019] FIG. 8 is an exemplary feedback circuit of the partial ADC circuit of FIG. 7 in accordance with certain embodiments of the invention. [0020] FIG. 9 is a time diagram for the partial ADC circuit of FIGS. 7 and 8. [0021] FIG. 10 is a block diagram of a multi-order, multi-stage circuit with each stage including the integrator circuit of either FIG. 2 or FIG. 6 in accordance with certain embodiments of the invention. Continue reading about Alternate sampling integrator... Full patent description for Alternate sampling integrator Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Alternate sampling integrator patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Alternate sampling integrator or other areas of interest. ### Previous Patent Application: Gate driver, and thin film transistor substrate and liquid crystal display having the same Next Patent Application: Time-interleaved analog-to-digital converter and high speed signal processing system using the same Industry Class: Coded data generation or conversion ### FreshPatents.com Support Thank you for viewing the Alternate sampling integrator patent info. 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