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Ajay Bhatia patents

Recent patents with Ajay Bhatia listed as an inventor - additional entries may be under other spellings.

Ajay Bhatia - Related organizations: Apple Inc. patents

Voltage regulation for data retention in a volatile memory

08/13/15 - 20150228312 - A system, a voltage regulator and a method for regulating power are disclosed, wherein the system may include a processor, a voltage regulator circuit, and a memory unit. The voltage regulator circuit may be configured to generate a first power supply voltage provided to the memory unit. The voltage regulator
Inventors: Ajay Bhatia, Michael Dreesen

Global write driver for memory array structure

08/13/15 - 20150227456 - A system for storing data in a memory may include circuitry that may receive an address, a command and data. The circuitry may also determine a type of the command and generate a read control or write control signal dependent upon the type. The system may also include a plurality
Inventors: Ajay Bhatia, Michael Dreesen

Low leakage address decoder

08/13/15 - 20150227186 - A system and method for managing power in a memory, wherein the system may include a processor and a memory unit coupled to the processor. The memory unit may initialize an address decoder into a first power mode. In response to receiving a command and an address corresponding to a
Inventors: Ajay Bhatia, Michael Dreesen

Memory array voltage source controller for retention and write assist

06/19/14 - 20140169075 - A voltage source controller for a memory array includes an input coupled to a voltage source, an output coupled to one or more memory cells of a memory array, where the output is configured to provide a cell source voltage to the memory cells. The controller also includes a switch
Inventors: Ajay Bhatia, Hang Huang

Low voltage register file cell structure

04/24/14 - 20140112429 - A register file cell structure to enable lower voltage writes is disclosed. In one embodiment, a register file includes a state element made up of two cross-coupled inverters. Each of the inverters includes a p-channel metal oxide semiconductor (PMOS) transistor having a source terminal coupled to a virtual voltage node.
Inventors: Ajay Bhatia, Greg M. Hess, Sanjay P. Zambare

### Ajay Bhatia patent invention listings

The bibliographic references displayed about Ajay Bhatia's patents are for a recent sample of Ajay Bhatia's publicly published patent applications. The inventor/author may have additional bibliographic citations listed at the is not associated or affiliated in any way with the author/inventor or the United States Patent/Trademark Office but is providing this non-comprehensive sample listing for educational and research purposes using public bibliographic data published and disseminated from the United States Patent/Trademark Office public datafeed. This information is also available for free on the website. If Ajay Bhatia filed recent patent applications under another name, spelling or location then those applications could be listed on an alternate page. If no bibliographic references are listed here, it is possible there are no recent filings or there is a technical issue with the listing--in that case, we recommend doing a search on the website.


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