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  Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resistUSPTO Application #: 20060166416Title: Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resist Abstract: A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks. (end of abstract) Agent: Delio & Peterson, LLC - New Haven, CT, US Inventors: Timothy J. Dalton, Wesley C. Natzle, Paul W. Pastel, Richard S. Wise, Hongwen Yan, Ying Zhang USPTO Applicaton #: 20060166416 - Class: 438153000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, On Insulating Substrate Or Layer (e.g., Tft, Etc.), Having Insulated Gate, Combined With Electrical Device Not On Insulating Substrate Or Layer, Complementary Field Effect Transistors The Patent Description & Claims data below is from USPTO Patent Application 20060166416. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] This invention relates to the making of electronic components such as integrated circuit semiconductor devices, and in particular, to methods for providing more uniform and more consistent reactive ion etching techniques when pattern factors change, particularly when etching doped gate stacks. [0003] 2. Description of Related Art [0004] Fabrication of integrated circuit devices typically requires numerous processing steps to deposit and pattern multiple layers of conducting and insulating materials. One of these processing steps includes dry etching. In a typical dry etch process, reactive species are first generated in a plasma. The species then diffuse to the substrate surface being etched, where they are adsorbed. A chemical reaction occurs, and a volatile by-product is formed. The by-product is then desorbed from the surface and diffused into the bulk of the gas. [0005] RIE is one such type of dry etching that is often used to selectively etch a substrate on which desired features of an integrated circuit have been patterned using a process such as photo-lithography. RIE combines a physical basis (ion) and chemically reactive radicals to remove material from a surface of a semiconductor device to produce the desired features. RIE processing involves introducing a process gas into a chamber to generate a plasma, which is used to create an etch gas. This etch gas etches the substrate and creates volatile etch byproduct compounds which are typically evacuated from the chamber. [0006] Essentially all RIE processes are carried out on patterned substrates comprising at least two materials. One is a material to be etched, and the other is a material that masks the material to be etched. In processes that rely predominantly on the physical mechanism of sputtering, the strongly directional nature of the incident energetic ions allows substrate material to be removed in an anisotropic manner (i.e., essentially vertical etch profiles are produced). Unfortunately, such material removal mechanisms are also non-selective against masking material and the varying materials underlying the layers being etched, such that, these materials may also be consumed during the patterning of the unmasked material. It is also inevitable in certain material combinations that the reaction products from the mask material, or the reaction products from the material to be etched, can interact with the plasma and impact the etch rate or profile. These various etching/masking material combinations on wafers interacting with the plasma are sources of profile and etch rate variations. [0007] For example, there are a number of prior art references which discuss the etching of structures containing gate stacks having silicon, doped silicon, polysilicon or doped polysilicon layers using a variety of etch chemistries. These structures can be RIE etched using either a hard mask or a photo resist mask material (i.e., a soft mask). However, where a hard mask is used alone to etch the various etching/masking material combinations, serious problems can occur due to undercutting of doped regions of the gate stacks. Thus, trends have leaned towards the use of photo resist soft mask materials, such as a hydrocarbon containing photo resist mask material, with or without the addition of a hard mask. [0008] It has been found that the hydrocarbon containing photo resist material often plays a roll in the etch chemistry. In particular, as the structure is etched, the RIE etch chemistry consumes the hydrocarbon containing photo resist mask material, in addition to the desired etching materials, such that hydrocarbon containing species desorb from the surface of the photo resist mask material and diffuse into the bulk RIE etch chemistry. These hydrocarbon containing species form passivation layers on sidewalls of the gate stack layers to prevent the lateral etching thereof during the RIE process. [0009] However, this process of relying on the photo resist material as an active part of the etch chemistry is undesirable as it is highly dependent upon the amount of hydrocarbons contained within the photo resist material. Further, as the pattern factors differ of the varying patterns etched into the photo resist material across the structure being etched, the local production of hydrocarbons may vary with proximity to masked areas. This results in varying amounts of hydrocarbons desorbing from the various masked structures across the structure, which can ultimately lead to the problem of microloading (i.e., having greater concentrations of hydrocarbons in certain areas of the structure as compared to other areas thereof). These microloading factors can deleteriously impact both etch rates and etch profiles to varying degrees across the structure being etched (known in the industry as through-pitch variation), as well as cause undesirable profile differences in the gate stacks, substantial part to part variation, and even alteration of the photo resist material itself. Through-pitch variations in etch profiles substantially degrades the transistor performance. [0010] Accordingly, a need continues to exist in the art for providing more uniform and more consistent reactive ion etching techniques when pattern factors change across the structure to be etched. SUMMARY OF THE INVENTION [0011] Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide uniform and consistent reactive ion etching techniques when pattern factors change across the structure to be etched. [0012] It is another object of the present invention to provide improved reactive ion etching techniques that take into account the impact of local photo resist consumption on etch rates and/or etch profiles. [0013] A further object of the invention is to provide improved reactive ion etching techniques that compensate or accommodate for pattern factor differences across the structure to be etched. [0014] It is yet another object of the present invention to provide improved reactive ion etching techniques that avoid the problems associated with microloading including, but not limited to, deleteriously affects on both etch rates and etch profiles, through-pitch variation in critical dimension, substantial part to part variation, and substantial alteration of the photo resist material itself. [0015] Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification. [0016] The above and other objects, which will be apparent to those skilled in art, are achieved in the present invention, which is directed to in a first aspect a method for etching gate stacks on a semiconductor wafer. The method includes providing a semiconductor wafer having a gate stack layer within a processing chamber and flowing an etchant into the processing chamber. An overload amount of a ballast gas is added within the processing chamber to form a substantially homogeneous etchant across the semiconductor wafer. In so doing, the homogeneous etchant has a higher concentration of the ballast gas as compared to the etchant. A gate stack is then etched into the gate stack layer by contacting the gate stack layer with the substantially homogeneous etchant. Simultaneously, a passivation layer is deposited over all exposed surfaces during the etching using the ballast gas within the substantially homogeneous etchant to provide substantially uniform etching results. [0017] In this aspect of the invention, the ballast gas may be a carbon containing gas having a chemical formula C.sub.xH.sub.y, wherein x is an integer ranging from 1 to 10, and y is an integer ranging from 2 to 22. Alternatively, the ballast gas may be a carbon containing gas having a chemical formula C.sub.xH.sub.yA, wherein x is an integer ranging from 1 to 10, y is an integer ranging from 0 to 21, and A represents at least one additional substituent selected from the group consisting of O, N, S, P, F, Cl, Br, I, or combinations thereof. [0018] In another aspect, the invention is directed to a method for etching gate stacks on a semiconductor wafer. The method includes providing a semiconductor wafer that has a patterned photo resist layer over a gate stack layer within a processing chamber, and flowing an etchant into such processing chamber. The etchant is contacted to the semiconductor wafer to generate a reaction by-product that is diffused throughout the etchant at varying concentrations across the semiconductor wafer. A ballast gas is then added within the processing chamber to equilibrate the varying concentrations of the reaction by-product and provide a substantially homogeneous etchant across the semiconductor wafer. A gate stack is etched in the ate stack layer using the patterned photo resist layer by contacting the gate stack layer with the substantially homogeneous etchant, while simultaneously depositing a passivation layer over all exposed surfaces during the etching to provide substantially uniform etching results. [0019] The gate stack layer may be either a dual gate stack layer or a uniformly pre-doped region. It may be composed of a material such as, silicon, doped silicon, polysilicon, doped polysilicon, germanium, silicon germanium, silicon germanium carbon, mixtures thereof, alloys thereof or multilayers thereof. Optionally, a hard mask layer may reside between the photo resist layer and the gate stack layer. [0020] The etchant may be a halogen-based plasma in the presence of an oxygen gas, a halogen-based plasma in the presence of a nitrogen gas, or mixtures thereof. In this aspect, the reaction by-product may be gaseous by-products desorbed from a surface of the photo resist layer, gaseous particles desorbed from a surface of the gate stack layer, or both. As such, the ballast gas and the reaction by-product may be identical gases or they may be equivalent to one another. This ballast gas may be either overloaded into the processing chamber, or it may be added to the processing chamber in an amount sufficient to compensate for varying patterns of the patterned photo resist layer residing across the semiconductor wafer, and the varying amounts of the reaction by-product desorbed from the varying patterned photo resist layer and diffused at varying concentrations throughout the etchant. [0021] Wherein the patterned photo resist layer is a patterned hydrocarbon containing resist layer, upon contact with the etchant, it is hydrocarbon containing species that are desorbed from the patterned hydrocarbon containing resist layer and diffused throughout the etchant at varying concentrations across the semiconductor wafer. As such, the ballast gas is a carbon containing ballast gas added to the processing chamber to equilibrate the varying concentrations of the hydrocarbon containing species throughout such etchant. The carbon containing ballast gas may have a chemical formula C.sub.xH.sub.y, wherein x is an integer ranging from 1 to 10, and y is an integer ranging from 2 to 22. Alternatively, the carbon containing ballast gas may have a chemical formula C.sub.xH.sub.yA, wherein x is an integer ranging from 1 to 10, y is an integer ranging from 0 to 21, and A represents at least one additional substituent selected from the group consisting of O, N, S, P, F, Cl, Br, I, or combinations thereof. [0022] In another aspect, the invention is directed to a chemical composition for etching gate stacks on a semiconductor wafer. The composition includes an etchant having desorbed hydrocarbon containing species diffused at varying concentrations throughout the etchant, and a carbon containing ballast gas added to the etchant. This carbon containing ballast gas is added to the etchant such that it equilibrates the varying concentrations of the hydrocarbon containing species throughout the etchant to provide a substantially homogeneous etchant. The ballast gas may have a chemical formula C.sub.xH.sub.y, or it may have a chemical formula C.sub.xH.sub.yA. Continue reading... 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