Active solid-state devices (e.g., transistors, solid-state diodes) patents - Monitor Patents
FreshPatents.com Logo    FreshPatents.com icons
Monitor Keywords Patent Organizer File a Provisional Patent Browse Inventors Browse Industry Browse Agents



USPTO Class 257  |  Browse by Industry: Previous - Next | All     monitor keywords
Recent  |  14:  | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan |  | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn |  | 2008 | 2007 |

Active solid-state devices (e.g., transistors, solid-state diodes)

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
11/13/2014 > 242 patent applications in 104 patent subcategories.

20140332747 - Memristor based on a mixed metal oxide: The present invention relates to micro- and nano-electronics devices based on non-conventional materials. Such memristor devices with stable and reproducible characteristics can be used in the production of computer systems based on the analog architecture of artificial neural networks. The device in question consists of an active layer situated between... Agent:

20140332746 - Single crystal high dielectric constant material and method for making same: The invention provides a stable oxide material system for a capacitor, electronic device or a memory device having an effective high-k value with an effective zero alpha while exhibiting low leakage current density. The stable oxide material comprises Mx-Si1-xO2, wherein the elements M & Si are mixed such that the... Agent:

20140332751 - Memory cells, methods of programming memory cells, and methods of forming memory cells: Some embodiments include methods of programming a memory cell. A plurality of charge carriers may be moved within the memory cell, with an average charge across the moving charge carriers having an absolute value greater than 2. Some embodiments include methods of forming and programming an ionic-transport-based memory cell. A... Agent:

20140332749 - Semiconductor device and method of manufacturing same: A semiconductor device includes: a transistor on a main surface side of a semiconductor substrate; and a resistance change element on a back-surface side of the semiconductor substrate, wherein the transistor includes a low-resistance section in the semiconductor substrate, the low-resistance section extending to the back surface of the semiconductor... Agent: Sony Corporation

20140332748 - Three dimensional resistive memory: A memory device includes a stack of layers comprising a plurality of alternating layers of continuous electrically conductive material word line layers with layers of continuous electrically insulating material. A plurality of vias vertically extend through the stack of layers and a vertical bit line is disposed within each via.... Agent: Seagate Technology LLC

20140332750 - Transistors, memory cells and semiconductor constructions: Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate,... Agent:

20140332752 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes a plurality of series-coupled fixed resistance elements, a plurality of reference cell transistors, and reference word lines coupled to gates of the reference cell transistors, a first reference data line coupled to one end of a resistance path in which a plurality of fixed... Agent:

20140332753 - Nano field-effect vacuum tube and fabrication method thereof: A method is provided for fabricating a nano field-effect vacuum tube. The method includes providing a substrate having an insulating layer and a sacrificial layer; and forming a sacrificial line, a source sacrificial layer and a drain sacrificial layer. The method also includes forming a trench in the insulating layer;... Agent: Semiconductor Manufacturing International (shanghai) Corporation

20140332754 - Semiconductor light-emitting device: The present invention presents a solid-state semiconductor light emitting device with reduced forward voltage and improved quantum efficiency. The light emitting device is characterized by its multiple-quantum-well active-region with opposite composition grading in the quantum barriers and quantum wells along the device epitaxy direction.... Agent: Qingdao Jason Electric Co., Ltd.

20140332755 - Diode barrier infrared detector devices and superlattice barrier structures: Diode barrier infrared detector devices and superlattice barrier structures are disclosed. In one embodiment, a diode barrier infrared detector device includes a first contact layer, an absorber layer adjacent to the first contact layer, and a barrier layer adjacent to the absorber layer, and a second contact layer adjacent to... Agent: L-3 Communications Cincinnati Electronics Corporation

20140332756 - Nitride semiconductor light-emitting device and method of manufacturing the same: A nitride semiconductor light-emitting device is formed of an n-type nitride semiconductor layer, a trigger layer, a V-pit expanding layer, a light-emitting layer, and a p-type nitride semiconductor layer provided in this order. The light-emitting layer has a V-pit formed therein. The trigger layer is made of a nitride semiconductor... Agent:

20140332757 - Graphene photodetector: A set of buried electrodes are embedded in a dielectric material layer, and a graphene layer having a doping of a first conductivity type are formed thereupon. A first upper electrode is formed over a center portion of each buried electrode. Second upper electrodes are formed in regions that do... Agent: International Business Machines Corporation

20140332782 - Adhesive film: An adhesive film, a method for preparing an adhesive film, and an organic electronic device are provided. According to the adhesive film in exemplary embodiments of the present invention, fluidity of an adhesive can be controlled in the case of applying the adhesive between objects to be subsequently adhered to... Agent:

20140332770 - Chip on film including different wiring pattern, flexible display device including the same, and method of manufacturing flexible display device: A chip on film for a flexible display device is disclosed. In one aspect, the chip on film includes a base film, a semiconductor chip provided to the base film, and a wire part provided to the base film and electrically connected to the semiconductor chip. The wire part includes... Agent: Samsung Display Co., Ltd.

20140332787 - Compound for optoelectronic device, organic light-emitting diode including same, and display device including organic light-emitting diode: Disclosed are a compound for an organic optoelectronic device, an organic light emitting diode including the same, and a display device including the organic light emitting diode. The compound for an organic optoelectronic device represented by a combination of the following Chemical Formula 1 and Chemical Formula 2 provides an... Agent:

20140332793 - Compound for organic electric element, organic electric element comprising the same and electronic device thereof: A compound represented by Formula 1. An organic electric element includes a first electrode, a second electrode, and an organic material layer between the first electrode and the second electrode. The organic material layer includes the compound. When the organic electric element includes the compound in an organic material layer,... Agent:

20140332790 - Display: c

20140332778 - Display device: A display device includes a thin film transistor substrate including transistors each controlling the amount of light emission of each pixel and a counter substrate arranged to be placed over the thin film transistor substrate. The thin film transistor substrate includes an insulating substrate as a base material, a circuit... Agent: Japan Display Inc.

20140332781 - Display device: A display device comprising including a plurality of pixels arranged in the shape of a matrix above a substrate, and a plurality of thin film transistors arranged corresponding to each of the plurality of pixel having an organic EL layer, the device comprising; a planarized film covering the thin film... Agent: Japan Display Inc.

20140332774 - Display device and manufacturing method thereof: d

20140332758 - Donor-acceptor compounds with nitrogen containing polyaromatics as the acceptor: wherein X1 to X12 is independently selected from the group consisting of C—R and N, wherein at least one of X1 to X12 is N, wherein each R is independently selected from the group consisting of hydrogen, deuterium, halide, alkyl, cycloalkyl, heteroalkyl, arylalkyl, alkoxy, aryloxy, amino, silyl, alkenyl, cycloalkenyl, heteroalkenyl,... Agent: Universal Display Corporation

20140332797 - Electro luminescent display panel and electronic apparatus: An EL display panel having a pixel structure corresponding to an active-matrix drive system, the EL display panel including a current supply line configured to be connected to a plurality of pixel circuits in common, line width of an intersection part of the current supply line with a signal line... Agent: Sony Corporation

20140332759 - Electrode, an electronic device, and a method for manufacturing an optoelectronic device: According to various embodiments, an electrode may include at least one layer including a chemical compound including aluminum and titanium.... Agent: Infineon Technologies Dresden Gmbh

20140332773 - Light-extraction element and light-emitting device: The invention provides a light-extraction element, comprising a light-diffusion layer which including a resin; and a plurality of raspberry-like particles uniformly dispersed in the resin, wherein the raspberry-like particles feature a surface with a plurality of round bumps, and the plurality of raspberry-like particles are composed of a material having... Agent: Industrial Technology Research Institute

20140332766 - Magneto resistive element, digitizer sensing panel including the same, display device including the same, and method of manufacturing the same: Provided are a magneto resistive element and a method of manufacturing the same, and in particular, a magneto resistive element and a method of manufacturing the same that may be applied to a digitizer sensing panel. The magneto resistive element includes a substrate, a first electrode disposed on the substrate,... Agent: Samsung Display Co., Ltd.

20140332776 - Manufacturing method of metal wire and thin transistor array panel, and organic light emitting diode display: A manufacturing method of a wire including: forming a lower layer on a substrate; forming a middle layer on the lower layer; forming an upper layer on the middle layer; forming, exposing, and developing a photoresist layer on the upper layer to form a photoresist pattern; and etching the upper... Agent: Samsung Display Co., Ltd.

20140332798 - Materials and methods for oled microcavities and buffer layers: The present teachings provide methods for forming organic layers for an organic light-emitting device (OLED) using an inkjet printing or thermal printing process. The method can further use one or more additional processes, such as vacuum thermal evaporation (VTE), to create an OLED stack. OLED stack structures are also provided... Agent:

20140332765 - Method of manufacturing organic light emitting display panel: A method of manufacturing an organic light emitting display panel is disclosed. The method may include forming a thin film layer using an open mask. The open mask may include forming a half-etching portion disposed over at least a portion of a non-display area. The non-display area may include a... Agent: Samsung Display Co., Ltd.

20140332785 - Method of preparing organic light-emitting device, substrate for transiting inorganic layer, and organic light-emitting device: A method of preparing an organic light-emitting device having excellent sealing characteristics against external environment and flexibility.... Agent:

20140332779 - Oled device and manufacturing method thereof and display panel applying the same: An organic light emitting device relates to a WOLED based Top emission organic light emitting device and the manufacturing method thereof and a display panel which applies the organic emitting device. In the organic light emitting device, a plurality of emitting units are formed on a substrate and isolated respectively;... Agent: Everdisplay Optronics (shanghai) Limited

20140332780 - Oled lighting device with short tolerant structure: An OLED panel having a plurality of OLED circuit elements is provided. Each OLED circuit element may include a fuse or other component that can be ablated or otherwise opened to render the component essentially non-conductive. Each OLED circuit element may comprise a pixel that may include a first electrode,... Agent: Universal Display Corporation

20140332796 - Organic electroluminescence device and method for manufacture thereof: An organic electroluminescence device (100, 200) comprises a substrate (110), an anode (130), a light emitting layer (160) and a cathode (190) stacked sequentially. The anode (130) comprises a light transmittance increased layer (131), a conductive layer (132) and a hole injection auxiliary layer (133) stacked on the substrate (110)... Agent: Shenzhen Ocean's King Lighting Engineering Co., Ltd

20140332762 - Organic electroluminescent display: An organic electroluminescent display is disclosed. The organic electroluminescent display includes a substrate having a pixel region and a non-pixel region, a first electrode disposed on the pixel region, an organic light emitting layer disposed on the first electrode and capable of generating light, a second electrode disposed on the... Agent: Samsung Display Co., Ltd.

20140332786 - Organic electroluminescent display device and circularly polarizing plate: The objective of the present invention is to provide: a circularly polarizing plate which comprises a λ/4 retardation film and has excellent visibility, excellent durability (resistance to image unevenness) and excellent resistance to panel deterioration (flatness) after storage in a high-temperature high-humidity environment for a long period of time; and... Agent:

20140332792 - Organic electroluminescent element material and organic electroluminescent element using same: Provided is an organic electroluminescent device (organic EL device) with improved luminous efficiency, sufficiently ensured driving stability, and a simple construction. The organic electroluminescent device includes an anode, an organic layer, and a cathode laminated on a substrate, in which at least one organic layer selected from the group consisting... Agent:

20140332789 - Organic electronic device: o

20140332791 - Organic electronic material, ink composition, and organic electronic element:

20140332794 - Organic light emitting device and method of producing: The invention relates to an organic light emitting device, in a layered structure, comprising a substrate, a bottom electrode, a top electrode, wherein the bottom electrode is closer to the substrate than the top electrode, an electrically active region, the electrically active region comprising one or more organic layers and... Agent:

20140332784 - Organic light emitting device, display unit, and device comprising a display unit: An organic light emitting device includes, in order an anode, an organic layer comprising a light-emitting layer, and a cathode. The anode is a laminated structure comprising in order: a first anode layer comprising a metal compound or a conductive oxide; a second anode layer that is a reflective layer;... Agent:

20140332768 - Organic light emitting diode display: A display includes a switching transistor connected to a scan line and data line, a driving transistor connected to the switching transistor, a storage capacitor between a voltage line and the driving transistor, and an organic light emitting diode connected to the driving transistor. The data line and voltage line... Agent: Samsung Display Co., Ltd.

20140332769 - Organic light emitting diode display: An organic light emitting diode (OLED) display with electrostatic discharges protection is disclosed. One inventive aspect includes a substrate including a pixel area and a peripheral area, an organic light emitting diode (OLED) formed at the pixel area, a driving circuit formed at the peripheral area, a shield layer formed... Agent: Samsung Display Co., Ltd.

20140332771 - Organic light emitting diode display: An organic light emitting diode (OLED) display is provided. The OLED displayer includes a capacitor electrode disposed on a substrate. An insulation layer is disposed on the capacitor electrode. A first active layer is disposed on the insulation layer. The first active layer includes a first doped area, a second... Agent: Samsung Display Co., Ltd.

20140332764 - Organic light emitting display: An organic light emitting diode (“OLED”) display includes: a substrate including a plurality of pixel areas; a plurality of switching transistors and a plurality of driving transistors on the substrate; and an organic light emitting element respectively connected to a switching transistor and a driving transistor among the plurality of... Agent: Samsung Display Co., Ltd.

20140332761 - Organic light-emitting display apparatus and photo mask for manufacturing same: An organic light-emitting display apparatus including a switching thin film transistor (TFT) on a substrate, wherein the switching TFT is electrically coupled to a scan line and a data line, a driving TFT electrically coupled to the switching TFT, the driving TFT including a driving semiconductor layer, and an organic... Agent:

20140332763 - Organic luminescence display and method of manufacturing the same: According to an aspect of the present invention, an organic luminescence display includes a substrate, a first electrode on the substrate, a pixel defining layer on the first electrode and partially exposing the first electrode, an auxiliary layer on the pixel defining layer, an organic layer on the first electrode... Agent: Samsung Display Co., Ltd.

20140332760 - Organic semiconductor transistor with epoxy-based organic resin planarization layer: A method is provided for forming an epoxy-based planarization layer overlying an organic semiconductor (OSC) film. Generally, the method forms a fluoropolymer passivation layer overlying the OSC layer. A photopatternable adhesion layer is formed overlying the fluoropolymer passivation layer, and patterned. A photopatternable planarization layer, comprising an epoxy-based organic resin,... Agent: Sharp Laboratories Of America, Inc.

20140332783 - Phenyl and fluorenyl substituted phenyl-pyrazole complexes of lr: m

20140332777 - Phosphorescent host material and organic light-emitting device including the same: Provided are a phosphorescent host material and an organic light-emitting device including the same. An emission material layer according to the inventive concept includes the phosphorescent host material and a phosphorescent dopant material. The phosphorescent host material has higher triplet energy than the phosphorescent dopant material. Thus, the light-emitting efficiency... Agent: Electronics And Telecommunications Research Institute

20140332775 - Pixel circuit and display apparatus using the same: A pixel circuit includes one organic light emitting diode, five first transistors and two capacitors. The first and third transistors have terminals coupled to a first voltage. The second transistor has two terminals coupled to another terminal of the first transistor and a second voltage through the organic light emitting... Agent: Au Optronics Corp

20140332788 - Polymeric electroluminescent device and method for preparing same: The present invention relates to a polymeric electroluminescent device and a method for preparing the same. The device comprises a conductive anode substrate, a hole injecting layer, a hole transportation layer, an electron barrier layer, a light-emitting layer, an electron transportation layer, an electron injecting layer and a cathode laminated... Agent: Shenzhen Ocean's King Lighting Engineering Co., Ltd.

20140332772 - Styrl-based compound and organic light emitting diode comprising the same: A styryl-based compound represented by Formula 1 below is disclosed. An organic light-emitting diode including the styryl-based compound is also disclosed.... Agent: Samsung Display Co., Ltd.

20140332767 - Thin film transistor and organic light emitting diode display including the same: A thin film transistor is disclosed. The thin film transistor may include a semiconductor formed on a substrate, a gate insulating layer formed on the semiconductor, a gate electrode formed on the gate insulating layer and including a plurality of branches overlapping the semiconductor, an interlayer insulating layer at least... Agent: Samsung Display Co., Ltd.

20140332795 - Transparent anode for an oled: positioned between each silver layer and the mixed tin zinc oxide layer or layers closest thereto is (d) a layer made of silicon nitride or made of silica, optionally doped with a metal. There is also provided It also relates to an an organic light-emitting diode device containing such an... Agent:

20140332804 - Analog circuit and semiconductor device: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor... Agent:

20140332803 - Light-emitting device: Disclosed is a light emitting device. The light emitting device includes a light emitting semiconductor layer including a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer and a second conductive semiconductor layer on the active layer. A passivation layer is disposed on a surface of... Agent: Lg Innotek Co., Ltd.

20140332799 - Semiconductor device: A semiconductor device includes a substrate, a gate electrode, an insulating layer, a source electrode, a drain electrode, a semiconductor channel layer, a first passivation layer and a second passivation layer. The gate is formed on the substrate. The insulating layer covers the gate electrode. The source electrode and the... Agent: Au Optronics Corporation

20140332802 - Semiconductor device: In a semiconductor device which conducts multilevel writing operation and a driving method thereof, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel... Agent:

20140332805 - Semiconductor device: A semiconductor device having a novel structure is provided. The semiconductor device includes a first p-type transistor, a second n-type transistor, a third transistor, and a fourth transistor. One of a source and a drain of the third transistor is connected to a wiring supplying first potential, and the other... Agent:

20140332806 - Semiconductor device: One object is to provide a new semiconductor device whose standby power is sufficiently reduced. The semiconductor device includes a first power supply terminal, a second power supply terminal, a switching transistor using an oxide semiconductor material and an integrated circuit. The first power supply terminal is electrically connected to... Agent:

20140332809 - Semiconductor device: With a combination of a transistor including an oxide semiconductor material and a transistor including a semiconductor material other than an oxide semiconductor, a semiconductor device with a novel structure in which data can be retained for a long time and does not have a limitation on the number of... Agent:

20140332800 - Semiconductor device and manufacturing method thereof: To provide a semiconductor device having a structure with which the device can be easily manufactured even if the size is decreased and which can suppress a decrease in electrical characteristics caused by the decrease in the size, and a manufacturing method thereof. A source electrode layer and a drain... Agent: Semiconductor Energy Laboratory Co., Ltd.

20140332807 - Semiconductor device and manufacturing method thereof: When a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are stacked and a source and drain electrode layers are provided in contact with the oxide semiconductor film is manufactured, after the formation of the gate electrode layer... Agent:

20140332801 - Semiconductor device and method for manufacturing the same: A bottom-gate transistor with a short channel length and a method for manufacturing the transistor are provided. A bottom-gate transistor with a short channel length in which portions of a source electrode and a drain electrode which are proximate to a channel formation region are thinner than other portions thereof... Agent:

20140332808 - Semiconductor device and method for manufacturing the same: A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. In a semiconductor device including a bottom-gate transistor in which an insulating layer functioning as a channel protective film is provided over an oxide semiconductor film, elements contained in an etching gas can be prevented... Agent:

20140332813 - Semiconductor device: A device comprises a semiconductor chip including an edge elongated in a first direction. A plurality of first pads is formed on the semiconductor chip. The first pads are substantially equal in length in the first direction to each other. A second pad is formed on the semiconductor chip. The... Agent:

20140332811 - Semiconductor device with bond and probe pads: A semiconductor die has an active face with an arrangement of I/O pads around its edges. The I/O pads include bond pads and probe pads. Two types of I/O pads are provided and the two types of pads are arranged in a staggered arrangement around the edges of the die.... Agent:

20140332810 - Temporary liquid thermal interface material for surface tension adhesion and thermal control: An assembly including a liquid thermal interface material for surface tension adhesion and thermal control used during electrical/thermal test of a 3D wafer and methods of use. The method includes temporarily attaching a thinned wafer to a carrier wafer by applying a non-adhesive material therebetween and pressing the thinned wafer... Agent: International Business Machines Corporation

20140332812 - Wafer and system and method for testing the wafer: A wafer is provided. The wafer includes at least one field. The field includes at least one chip, and at least one test chip that generates power using a wireless signal, that provides power to the chip, that tests performance of the chip, and that corrects performance of the chip... Agent: Electronics And Telecommunications Research Institute

20140332814 - Methods for the synthesis of arrays of thin crystal grains of layered semiconductors sns2 and sns at designed locations: Methods of producing arrays of thin crystal grains of layered semiconductors, including the creation of stable atomic-layer-thick to micron-thick membranes of crystalline semiconductors by chemical vapor deposition.... Agent: The University Of Houston System

20140332815 - Semiconductor device including finfet and diode having reduced defects in depletion region: A semiconductor device comprises a first substrate portion and a second substrate portion disposed a distance away from the first substrate portion. The first substrate portion includes a first active semiconductor layer defining at least one semiconductor fin and a first polycrystalline layer formed directly on the fin. The first... Agent: International Business Machines Corporation

20140332816 - Semiconductor device: A semiconductor device includes a first insulating film formed on a memory cell region of the semiconductor substrate, a first polysilicon layer formed on the first insulating film, and memory cell transistors formed on the first polysilicon layer, each including a charge storage layer, an inter-electrode insulating film and a... Agent: Kabushiki Kaisha Toshiba

20140332819 - Display device and method for manufacturing the same: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle... Agent:

20140332818 - Low temperature polysilicon film, thin film transistor, manufacturing method thereof and display panel: A low temperature polysilicon film and a manufacturing method thereof, a thin film transistor and a manufacturing method thereof and a display panel are provided. The manufacturing method of the low temperature polysilicon film includes crystallizing a nano-silicon thin film to form the low temperature polysilicon film.... Agent:

20140332817 - Thin film transistor, thin film transistor array substrate, and method for making the same: The present invention provides a thin film transistor including a first drain electrode, a second drain electrode, a first source electrode, and a second source electrode, wherein the first drain electrode and the first source electrode jointly define a first U-shaped channel facing toward a first direction. Wherein the second... Agent: Shenzhen China Star Optoelectronics Technology Co., Ltd.

20140332820 - Flip light emitting diode chip and method of fabricating the same: A method of fabricating a light emitting diode device comprises depositing conductive material to cover a portion of surface of a conductive and reflective layer to form a first contact pad, and surfaces between adjacent first trenches to form a second contact pad; and depositing a first passivation layer over... Agent: Starlite Led Inc

20140332823 - Schottky barrier diode: A Schottky barrier diode is provided with: an n-type semiconductor layer including Ga2O3-based compound semiconductors with n-type conductivity; and a Schottky electrode layer which is in Schottky-contact with the n-type semiconductor layer. An n−-type semiconductor layer, which has a relatively low electron carrier concentration and is brought into Schottky-contact with... Agent:

20140332821 - Semiconductor device, light emitting device using the same, and light emitting device package including the same: A semiconductor device includes a silicon substrate, an initial buffer layer disposed on the silicon substrate, a transition layer disposed on the initial buffer layer, and a device structure disposed on the transition layer. The transition layer includes at least one of AlxGa1-xN (where 0<x<1) layers provided on the initial... Agent: Lg Innotek Co., Ltd.

20140332822 - Semiconductor device, light emitting device using the same, and light emitting device package including the same: A normally off nitride-based transistor may include a source electrode and a drain electrode, a channel layer serving as a charge transfer path between the source electrode and the drain electrode, and a gate electrode that controls charge transfer of the channel layer. The channel layer may have a junction... Agent: Seoul Semiconductor Co., Ltd.

20140332824 - Semiconductor structure with different fins of finfets: A semiconductor structure for forming FinFETs is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the FinFETs on the substrate, and a plurality of even fins of the FinFETs on the substrate between the odd fins of the FinFETs. The odd fins of the... Agent:

20140332825 - Circuitry configurable based on device orientation: The present disclosure is directed to circuitry configurable based on device orientation. Example circuitry may comprise at least one device location and configurable conductors. The at least one device location may include at least two conductive pads onto which a device may be populated by a manufacturing process. The configurable... Agent: Osram Sylvania Inc.

20140332827 - Display panel and sealing process thereof: A display panel and a sealing process are provided. The display panel has a display area and a non-display area; the sealing process includes following steps. A first substrate having a pixel array in the display area is provided. An absorption material layer is formed in the non-display area of... Agent: Au Optronics Corporation

20140332828 - Enhanced light output from a led containing laminate: A laminate capable of emitting light comprises a reflective layer. The reflective layer increases the amount of light output from the laminate. A lighting apparatus containing the improved laminate is also provided.... Agent:

20140332826 - Thin film transistor substrate and display apparatus: A thin film transistor (TFT) substrate comprises a substrate, a plurality of pixel electrodes, a gate layer, an active layer, a first source layer and a second source layer, and a drain layer. The pixel electrodes are disposed on the substrate. The gate layer is disposed on the substrate. The... Agent: Innolux Corporation

20140332832 - Display unit: A display unit includes a plurality of light emitting devices, each of the light emitting devices including a function layer including at least an organic layer is sandwiched between a first electrode and a second electrode, and which have a resonator structure for resonating light by using a space between... Agent:

20140332829 - Light source module: A light source module includes a light guide element, at least one light-emitting element, and a quantum dot element. The light guide element has a light incident surface and a light exiting surface. The light-emitting element is disposed at the light incident surface for providing a first color light. The... Agent:

20140332830 - Light source module and electronic device: A light source module and an electronic device are provided. The light source module includes a light guiding plate, at least one light-emitting element and a quantum dot element. The light guiding plate has a light incident surface and a light emitting surface. The at least one light-emitting element is... Agent: Htc Corporation

20140332831 - Light-emitting panel, light-emitting device, and method for manufacturing the light-emitting panel: A light-emitting panel can be manufactured in which a first light-emitting element emits light having high brightness and a pale color and causing less eyestrain even in the case of long time, a second light-emitting element emits light of a bright red color, a third light-emitting element emits green light,... Agent:

20140332833 - Substrate having hetero-structure, method for manufacturing the same and nitride semiconductor light emitting device using the same: Provided is a hetero-substrate that may include a base substrate, a buffer layer disposed on the base substrate, and a first semiconductor layer disposed on the buffer layer, the first semiconductor layer including a nitride semiconductor. A defect blocking layer is disposed on the first semiconductor layer. The defect blocking... Agent:

20140332837 - Light emitting apparatus: Provided is a light emitting apparatus. The light emitting apparatus includes a substrate; a light emitting device on the substrate; a fluorescent layer formed on the substrate and the light emitting device to surround the light emitting device; an encapsulant resin layer formed on the substrate and the fluorescent layer... Agent: Lg Innotek Co., Ltd.

20140332838 - Light emitting devices having light coupling layers with recessed electrodes: A light emitting device comprises a first layer of an n-type semiconductor material, a second layer of a p-type semiconductor material, and an active layer between the first layer and the second layer. A light coupling structure is disposed adjacent to one of the first layer and the second layer.... Agent: ManutiusIPInc.

20140332835 - Light emitting element, light emitting device and electronic apparatus: [In formula (1), A indicates a hydrogen atom, an alkyl group, an aryl group which may have a substituent, an arylamino group, or a triaryl amine, and B indicates a hydrogen atom, an alkyl group, an aryl group which may have a substituent, an arylamino group, or a triaryl amine,... Agent: Seiko Epson Corporation

20140332836 - Semiconductor light emitting device: Disclosed is a semiconductor light emitting device. The semiconductor light emitting device includes a plurality of compound semiconductor layers including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; a pad on the plurality of compound semiconductor layers; an electrode layer under the plurality of... Agent:

20140332834 - Substrate for an opto-electric device: An opto-electric device has a substrate comprised of metal or plastic. The substrate in an uncoated condition has an average surface roughness Rz of 150 nm to 1500 nm. A dielectric coating coats the substrate and a non-thermally curable coating is directly on the dielectric coating. An electrode is on... Agent:

20140332839 - Light emitting device package: A light emitting device package includes a body having a cavity therein and first and second recesses inside the cavity of the body. The first and second electrode layers are provided in the first and second recesses, and a light emitting device is provided on the first and second electrode... Agent: Lg Innotek Co., Ltd.

20140332840 - Semiconductor light emitting device and fabrication method of the semiconductor light emitting device: A semiconductor light emitting device which can control of current density and can optimize current density and in which a rise in luminosity is possible, and a fabrication method of the semiconductor light emitting device are provided. The semiconductor light emitting device including: a semiconductor substrate structure including a semiconductor... Agent: Rohm Co., Ltd.

20140332841 - High voltage breakover diode having comparable forward breakover and reverse breakdown voltages: In a first embodiment, an ultra-fast breakover diode has a turn on time TON that is less than 0.3 microseconds, where the forward breakover voltage is greater than +400 volts and varies less than one percent per ten degrees Celsius change. In a second embodiment, a breakover diode has a... Agent: Ixys Corporation

20140332842 - Packaged overvoltage protection circuit for triggering thyristors: In a first embodiment, an ultra-fast breakover diode has a turn on time TON that is less than 0.3 microseconds, where the forward breakover voltage is greater than +400 volts and varies less than one percent per ten degrees Celsius change. In a second embodiment, a breakover diode has a... Agent: Ixys Corporation

20140332843 - Junction-isolated blocking voltage structures with integrated protection structures: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type... Agent:

20140332844 - A process method and structure for high voltage mosfets: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom... Agent:

20140332845 - Topside structures for an insulated gate bipolar transistor (igbt) device to achieve improved device perforemances: This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at... Agent:

20140332846 - Transistor-type protection device, semiconductor integrated circuit, and manufacturing method of the same: A transistor-type protection device includes: a semiconductor substrate; a well including a first-conductivity-type semiconductor formed in the semiconductor substrate; a source region including a second-conductivity-type semiconductor formed in the well; a gate electrode formed above the well via a gate insulating film at one side of the source region; a... Agent:

20140332847 - Composite one-piece igbt device and producing method thereof: A composite one-piece IGBT power device is disclosed to solve a problem that existing devices' turning-on/off speed is not high enough. The composite one-piece IGBT device of the present invention comprises at least two IGBT devices. Drift regions of the at least two IGBT devices connect with each other and... Agent:

20140332848 - Low-bandgap, monolithic, multi-bandgap, optoelectronic devices: Low bandgap, monolithic, multi-bandgap, optoelectronic devices (10), including PV converters, photodetectors, and LED's, have lattice-matched (LM), double-heterostructure (DH), low-bandgap GaInAs(P) subcells (22, 24) including those that are lattice-mismatched (LMM) to InP, grown on an InP substrate (26) by use of at least one graded lattice constant transition layer (20) of... Agent: Alliance For Sustainable Energy, LLC

20140332850 - Epitaxial growth of crystalline material: A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be... Agent:

20140332849 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a silicon substrate, an initial buffer layer disposed on the silicon substrate and including aluminum nitride (AlN), and a semiconductor device layer disposed on the initial buffer layer and including a semiconductor compound. There is no SiN between the initial buffer layer and the silicon substrate,... Agent: Lg Innotek Co., Ltd.

20140332852 - Non-planar semiconductor device having group iii-v material active region with multi-dielectric gate stack: Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the... Agent:

20140332851 - Reduced short channel effect of iii-v field effect transistor via oxidizing aluminum-rich underlayer: In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present... Agent: International Business Machines Corporation

20140332853 - Method and apparatus for reduced parasitics and improved multi-finger transistor thermal impedance: A transistor, a method and an apparatus for forming multiple connections to a transistor for reduced gate (FET/HEMT) or base (BJT/HBT) parasitics, and improved multi-finger transistor thermal impedance. Providing for a method and an apparatus that reduces a transistor's parasitics and reduces a transistor's thermal impedance, resulting in higher device... Agent:

20140332854 - Stress release structures for metal electrodes of semiconductor devices: This invention teaches stress release metal electrodes for gate, drain and source in a field effect transistor and stress release metal electrodes for emitter, base and collector in a bipolar transistor. Due to the large difference in the thermal expansion coefficients between semiconductor materials and metal electrodes, significant strain and... Agent:

20140332855 - Reduced short channel effect of iii-v field effect transistor via oxidizing aluminum-rich underlayer: In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present... Agent: International Business Machines Corporation

20140332856 - Vertical electronic fuse: An electronic fuse structure including a first Mx metal comprising a conductive cap, an Mx+1 metal located above the Mx metal, wherein the Mx+1 metal does not comprise a conductive cap, and a via, wherein the via electrically connects the Mx metal to the Mx+1 metal in a vertical orientation.... Agent:

20140332857 - Junction gate field-effect transistor (jfet), semiconductor device and method of manufacturing: A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The... Agent:

20140332858 - Junction gate field-effect transistor (jfet), semiconductor device having jfet and method of manufacturing: A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140332861 - Fin structure with varying isolation thickness: Semiconductor fins having isolation regions of different thicknesses on the same integrated circuit are disclosed. Nitride spacers protect the lower portion of some fins, while other fins do not have spacers on the lower portion. The exposed lower portion of the fins are oxidized to provide isolation regions of different... Agent: International Business Machines Corporation

20140332864 - Method for providing a gate metal layer of a transistor device and associated transistor: A method includes providing a dummy gate structure on a substrate. The dummy gate structure includes a gate dielectric layer and a dummy gate electrode layer, and is laterally defined by inner sidewalls of a set of spacers. The method also includes laterally embedding the dummy gate structure, removing the... Agent: Imec

20140332859 - Self-aligned wrapped-around structure: An embodiment vertical wrapped-around structure and method of making. An embodiment method of making a self-aligned vertical structure-all-around device including forming a spacer around an exposed portion of a semiconductor column projecting from a structure layer, forming a photoresist over a protected portion of the structure layer and a first... Agent:

20140332865 - Semiconductor device: A semiconductor device includes a substrate having an edge, a semiconductor layer provided on a substrate, an electrode pad provided on the semiconductor layer, an inorganic insulating film having a first opening through which an upper surface of the electrode pad is exposed, and a resin film provided on the... Agent: Sumitomo Electric Device Innovations, Inc.

20140332866 - Semiconductor device: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface... Agent:

20140332867 - Semiconductor device and manufacturing method thereof: It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is... Agent:

20140332863 - Semiconductor device and method of manufacturing the same: Provided are a semiconductor device and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an active fin on a substrate; oxidizing a portion of the active fin to form an insulating pattern between the active fin and the substrate; forming a first gate... Agent: Samsung Electronics Co., Ltd.

20140332860 - Stacked carbon-based fets: Methods and systems for forming stacked transistors. Such methods include forming a lower channel layer on a substrate; forming a pair of vertically aligned gate regions over the lower channel layer; forming a pair of vertically aligned source regions and a pair of vertically aligned drain regions on the lower... Agent: International Business Machines Corporation

20140332862 - Stacked carbon-based fets: Stacked transistor devices include a lower channel layer formed on a substrate; a pair of vertically aligned source regions formed over the lower channel layer, where the pair of source regions are separated by an insulator; a pair of vertically aligned drain regions formed on the lower channel layer, where... Agent: International Business Machines Corporation

20140332868 - Semiconductor device and manufacturing method thereof: A method for manufacturing semiconductor devices includes following steps. A substrate having a pixel region and a periphery region defined thereon is provided, and at least a transistor is formed in the pixel region. A blocking layer is formed on the substrate, and the blocking layer includes a first opening... Agent: United Microelectronics Corp.

20140332869 - Solid-state image pickup device: A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion... Agent:

20140332870 - Spin transistor, and semiconductor device, memory device, microprocessor, processor, system, data storage system and memory system including the spin transistor: A spin transistor includes a source electrode, including a magnetic material, is disposed in a substrate. A drain electrode, including a magnetic material is disposed in the substrate and is spaced apart from the source electrode in a first direction. A gate electrode is interposed between the source electrode and... Agent: Sk Hynix Inc.

20140332872 - Semiconductor device and method for forming the same: A semiconductor device includes a semiconductor substrate including a pad region and a peripheral region, a first buffer layer formed to include a capacitor over the semiconductor substrate in the pad region, a second buffer layer formed to include a first contact pad over the first buffer layer, and a... Agent: Sk Hynix Inc.

20140332871 - Semiconductor device having jumper pattern and blocking pattern: A semiconductor device includes a substrate having a transistor area, a gate structure disposed on the transistor area of the substrate, a first interlayer insulating layer covering the gate structure, a blocking pattern disposed on the first interlayer insulating layer, and a jumper pattern disposed on the blocking pattern. The... Agent: Samsung Electronics Co., Ltd.

20140332873 - Semiconductor device: A semiconductor device includes at least one channel layer, insulating layers stacked on top of one another while surrounding the at least one channel layer, first grooves and second grooves alternately interposed between the insulating layers, wherein the first groves have a greater width than the second grooves having a... Agent: Sk Hynix Inc.

20140332874 - Semiconductor devices: A semiconductor device includes a substrate, a first poly-silicon pattern on the substrate, a metal pattern on the first poly-silicon pattern, and an interface layer between the first poly-silicon pattern and the metal pattern. The interface layer may include at least one selected from the group of a metal-silicon oxynitride... Agent:

20140332876 - High voltage gate formation: Embodiments described herein generally relate to methods of manufacturing charge-trapping memory by patterning the high voltage gates before other gates are formed. One advantage of such an approach is that a thin poly layer may be used to form memory and low voltage gates while protecting high voltage gates from... Agent:

20140332875 - Vertical memory devices and method of manufacturing the same: A method of manufacturing a vertical memory device is disclosed. In the method, a plurality of insulation layers and a plurality of first sacrificial layers are alternately stacked on a substrate. A plurality of holes is formed through the plurality of insulation layers and first sacrificial layers. A plasma treatment... Agent:

20140332877 - Semiconductor device: A switching component includes a control element and an integrated circuit. The integrated circuit includes a first transistor element and a second transistor element electrically connected in parallel to the first transistor element. The first transistor element includes first transistors, gate electrodes of which are disposed in first trenches in... Agent:

20140332878 - Semiconductor device and a manufacturing method of the same: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one... Agent:

20140332879 - Power semiconductor device with reduced on-resistance and increased breakdown voltage: In one implementation, a power semiconductor device includes an active region and a termination region. A depletion trench finger extends from the active region and ends in the termination region. An arched depletion trench surrounds the depletion trench finger in the termination region, the arched depletion trench enables one or... Agent: International Rectifier Corporation

20140332880 - Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation: Embodiments of a manufacturing process for recessed gate devices on silicon-on-insulator (SOI) substrate with self-aligned lateral isolation are described. This allows the creation of true in-pitch recessed gate devices without requiring an extra isolation dimension. A lateral isolation trench is formed between pairs of recessed gate devices by etching the... Agent: Micron Technology, Inc.

20140332881 - Semiconductor device: A semiconductor device includes a transistor array, including first transistors and second transistors. Gate electrodes of the first transistors are disposed in first trenches in a first main surface of a semiconductor substrate, and gate electrodes of the second transistors are disposed in second trenches in the first main surface.... Agent:

20140332882 - Trench junction barrier controlled schottky: A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top... Agent:

20140332884 - High voltage device: A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to... Agent:

20140332883 - Semiconductor device having dummy gate and gate: A fin-shaped active region is defined on a substrate. First and second gate electrodes crossing the fin-shaped active region are arranged. A dummy gate electrode is formed between the first and second gate electrodes. A first drain region is formed between the first gate electrode and the dummy gate electrode.... Agent: Samsung Electronics Co., Ltd.

20140332885 - Trench transistor having a doped semiconductor region: A lateral trench transistor has a semiconductor body having a source region, a source contact, a body region, a drain region, and a gate trench, in which a gate electrode which is isolated from the semiconductor body is embedded. A heavily doped semiconductor region is provided within the body region... Agent:

20140332886 - Single poly plate low on resistance extended drain metal oxide semiconductor device: A semiconductor device, in particular, an extended drain metal oxide semiconductor (ED-MOS) device, defined by a doped shallow drain implant in a drift region. For example, an extend drain n-channel metal oxide semiconductor (ED-NMOS) device is defined by an n doped shallow drain (NDD) implant in the drift region. The... Agent: Macronix International Co., Ltd.

20140332888 - Semiconductor device including finfet structures with varied epitaxial regions, related method and design structure: A semiconductor device including a substrate; a FINFET disposed on the substrate, the FINFET including: a set of epitaxial regions disposed in a source/drain region on a set of fins, the set of epitaxial regions including: a first epitaxial region on a first inner surface of a first outer fin,... Agent: International Business Machines Corporation

20140332887 - Silicon-on-insulator integrated circuits with local oxidation of silicon and methods for fabricating the same: Silicon-on-insulator integrated circuits with local oxidation of silicon and methods for fabricating the same are provided. An integrated circuit includes a semiconductor substrate and a plurality of shallow trench isolation (STI) regions, each extending at least a first depth below an upper surface of the semiconductor substrate. The STI regions... Agent: Globalfoundries Singapore Pte. Ltd.

20140332890 - Stringer-free gate electrode for a suspended semiconductor fin: At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin. The amount of the etched portions of the insulator is selected such that a metallic gate electrode layer fills the entire gap between the... Agent: International Business Machines Corporation

20140332891 - Structure and method for reducing floating body effect of soi mosfets: The present invention generally relates to a semiconductor structure and method, and more specifically, to a structure and method for reducing floating body effect of silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). An integrated circuit (IC) structure includes an SOI substrate and at least one MOSFET... Agent:

20140332889 - Thin film transistor array panel and method for manufacturing the same: A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a... Agent: Samsung Display Co., Ltd.

20140332892 - Stringer-free gate electrode for a suspended semiconductor fin: At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin. The amount of the etched portions of the insulator is selected such that a metallic gate electrode layer fills the entire gap between the... Agent: International Business Machines Corporation

20140332893 - Integrated circuit device having defined gate spacing and method of designing and fabricating thereof: A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (√{square root over (W*W+L*L)})/10. The second gate structure is a... Agent:

20140332894 - Non-volatile memory devices having air gaps and methods of manufacturing the same: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second... Agent:

20140332895 - Random number generation device: A random number generation device includes: a first source region; a first drain region; a first channel region provided between the first source region and the first drain region; a first insulating film provided on the first channel region; and a first gate electrode provided on the first insulating film.... Agent: Kabushiki Kaisha Toshiba

20140332897 - Low noise and high performance lsi device: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be... Agent:

20140332896 - Semiconductor device and method for forming the same: A semiconductor device includes: a first active region defined by a recess contained in a device isolation film of a semiconductor substrate belonging to a first region and a second region, in a peripheral region including the first region, the second region, and a third region; a second active region... Agent:

20140332898 - Fanout line structure ofarray substrate and display panel: A fanout line structure of an array substrate includes a plurality of fanout lines arranged on a fanout area of the array substrate, where resistance value of the fanout line is dependent on length of the fanout line. Each of the fanout lines comprises a first conducting film. Resistance values... Agent: Shenzhen China Star Optoelectronics Technology Co., Ltd

20140332899 - Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle: Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a... Agent:

20140332903 - Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same: A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of... Agent: International Business Machines Corporation

20140332900 - Low extension resistance iii-v compound fin field effect transistor: A gate stack including a gate dielectric and a gate electrode is formed over at least one compound semiconductor fin provided on an insulating substrate. The at least one compound semiconductor fin is thinned employing the gate stack as an etch mask. Source/drain extension regions are epitaxially deposited on physically... Agent: International Business Machines Corporation

20140332902 - Novel method to tune narrow width effect with raised s/d structure: A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle.... Agent:

20140332901 - Semiconductor device with notched gate: A semiconductor device includes a semiconductor substrate, a body region disposed in the semiconductor substrate and having a first conductivity type, a source region disposed in the semiconductor substrate adjacent the body region and having a second conductivity type, a drain region disposed in the semiconductor substrate, having the second... Agent: Freescale Semiconductor, Inc.

20140332904 - System and methods for converting planar design to finfet design: A FinFET structure layout includes a semiconductor substrate comprising a plurality of FinFET active areas, and a plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a gate having a gate length parallel to the semiconductor substrate and... Agent:

20140332905 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device includes forming a gate dielectric layer comprising an oxide, and at least one conductive layer on a substrate, forming a mask on the conductive layer and patterning the at least one conductive layer by etching the at least one conductive layer using the... Agent:

20140332906 - High-voltage transistor device and production method: A body region (3) with a first type of electric conductivity is arranged at the upper surface (10) of a substrate (1) in a well (2), wherein a portion of the well that is not occupied by the body region has a second type of conductivity opposite the first type... Agent:

20140332907 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device uses an aluminum alloy, rather than aluminum, for a metal gate. Therefore, the surface of the high-k metal gate after the CMP is aluminum alloy rather than pure aluminum, which can greatly reduce defects,... Agent:

20140332908 - Chip package and method for forming the same: A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is... Agent:

20140332909 - Integrated chip with micro-electro-mechanical system and integrated circuit mounted therein and method for manufacturing the same: The invention relates to an integrated chip with an MEMS and an integrated circuit mounted therein and a method for manufacturing the same. The method includes the steps of: S1: providing a first chip, wherein the first chip comprises a first substrate, an MEMS component layer formed on the first... Agent: Memsensing Microsystems (suzhou, China) Co., Ltd.

20140332911 - Capacitive micro-machined transducer and method of manufacturing the same: The present invention relates to a method of manufacturing a capacitive micro- machined transducer (100), in particular a CMUT, the method comprising depositing a first electrode layer (10) on a substrate (1), depositing a first dielectric film (20) on the first electrode layer (10), depositing a sacrificial layer (30) on... Agent:

20140332912 - Chip package and a method of manufacturing the same: In various embodiments, a method for manufacturing a chip package is provided. The method includes arranging a chip over a substrate, the chip including a microphone structure and an opening to the microphone structure; and encapsulating the chip with encapsulation material such that the opening is kept at least partially... Agent:

20140332910 - Microelectromechanical device and a method of manufacturing: A microelectromechanical device that comprises a wafer plate, a group of one or more wafer connector elements, and an electrical distribution layer between them. For reduced device thickness, the wafer plate comprises at least two dies and bonding material that bonds the at least two dies alongside each other to... Agent: Murata Manufacturing Co., Ltd.

20140332913 - Micro-electro-mechanical system (mems) structures and design structures: Dummy Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a bumper extending from a Micro-Electro-Mechanical System (MEMS) beam structure provided within a cavity structure. The method further includes forming a dummy landing structure on an opposing side of the cavity structure from... Agent: International Business Machines Corporation

20140332915 - Direct graphene growth on metal oxides by molecular epitaxy: Direct growth of graphene on Co3O4(111) at 1000 K was achieved by molecular beam epitaxy from a graphite source. Auger spectroscopy shows a characteristic sp2 carbon lineshape, at average carbon coverages from 0.4-3 monolayers. Low energy electron diffraction (LEED) indicates (111) ordering of the sp2 carbon film with a lattice... Agent: University Of North Texas

20140332914 - Magnatoresistive structure and method for forming the same: A magnetoresistive structure includes a substrate and a patterned stack structure. The substrate has a back surface and a front surface having a step portion. The patterned stack structure is on the step portion of the front surface and comprises a magnetoresistive layer, a conductive cap layer and a dielectric... Agent: Voltafield Technology Corp.

20140332916 - Memory element and memory device: There is disclosed an information storage element including a first layer including a ferromagnetic layer with a magnetization direction perpendicular to a film face; an insulation layer coupled to the first layer; and a second layer coupled to the insulation layer opposite the first layer, the second layer including a... Agent:

20140332917 - Magnetic-field sensing device: Apparatus and associated methods may relate to Magneto-Resistive Sensing Devices (MRSDs). In accordance with an exemplary embodiment, an MRSD comprises an underlying semiconductor device and a magneto-resistive sensor. In some exemplary embodiments, the semiconductor device is processed through most of a standard process flow. After the standard process flow, in... Agent: Honeywell International, Inc.

20140332918 - Enhancing the performance of light sensors that receive light signals from an integrated waveguide: The light sensor and waveguide are positioned on a base such that a light signal guided by the waveguide is received at the light sensor. The waveguide includes a taper configured such that a ratio of a width of the waveguide at a first location in the taper:the width of... Agent: Kotura, Inc.

20140332919 - Termination design for nanotube mosfet: A termination structure for a semiconductor power device includes a plurality of termination groups formed in a lightly doped epitaxial layer of a first conductivity type over a heavily doped semiconductor substrate of a second conductivity type. Each termination group includes a trench formed in the lightly doped epitaxial layer... Agent:

20140332921 - Semiconductor devices having a trench isolation layer and methods of fabricating the same: Semiconductor devices including a trench isolation layer are provided. The semiconductor device includes a substrate having a trench therein, a liner insulation layer that covers a bottom surface and sidewalls of the trench and includes micro trenches located at bottom inner corners of the liner insulation layer, a first isolating... Agent:

20140332920 - Shallow trench isolation: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure includes an upper insulating portion and a lower insulating portion, where the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second... Agent:

20140332923 - E-fuse with hybrid metallization: An e-fuse structure including a fuse link having a first region made of a first conductor and a second region made of a second conductor. The first conductor and the second conductor are in the same wiring level. The first conductor has a higher electrical resistance than the second conductor.... Agent: International Business Machines Corporation

20140332924 - E-fuse with hybrid metallization: A structure including a first interconnect including a first line overlying a first via and a second interconnect including a second line overlying a second via. The first line and the second line are co-planar. The first interconnect comprises a first conductor, the first conductor comprises a metal silicide including... Agent: International Business Machines Corporation

20140332922 - Programmable electrical fuse with temperature gradient between anode and cathode: In some examples, a programmable electrical fuse includes at least one structural feature that increases a thermal gradient between an anode and a cathode of the programmable electrical fuse. For example, a device may include a semiconductor substrate, an electrically insulating layer overlying the semiconductor substrate, and a programmable electrical... Agent: Honeywell International Inc.

20140332925 - Composite reconstituted wafer structures: A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behaviour of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials... Agent:

20140332926 - Composite reconstituted wafer structures: A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behaviour of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials... Agent:

20140332927 - Self-aligned bipolar junction transistor having self-planarizing isolation raised base structures: A collector region is formed between insulating shallow trench isolation regions within a substrate. A base material is epitaxially grown on the collector region and the shallow trench isolation regions. The base material forms a base region on the collector region and extrinsic base regions on the shallow trench isolation... Agent: International Business Machines Corporation

20140332928 - Digital semiconductor variable capacitor: A novel semiconductor variable capacitor is presented. The semiconductor structure is simple and is based on a semiconductor variable capacitor with MOS compatible structure suitable for integrated circuits, which has at least three terminals, one of which is used to modulate the capacitance value between the other two terminals of... Agent:

20140332929 - Forming semiconductor chip connections: Various embodiments include semiconductor structures. In one embodiment, the semiconductor structure includes a chip having a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.... Agent: International Business Machines Corporation

20140332930 - Integrated circuit device and configuration method thereof: An integrated circuit device comprises N stacked first integrated circuit chips each of which includes a first circuit and N stacked second integrated circuit chips each of which includes a second circuit. The N stacked second integrated circuit chips are stacked on the N stacked first integrated circuit chips. A... Agent: Canon Kabushiki Kaisha

20140332931 - Compensation devices: Methods, apparatuses and devices related to the manufacturing of compensation devices are provided. In some cases, an n/p-codoped layer is deposited for calibration purposes to minimize a net doping concentration. In other cases, alternatingly n- and p-doped layers are then deposited. In other embodiments, an n/p-codoped layer is deposited in... Agent:

20140332932 - Shallow trench and fabrication method: Various embodiments provide shallow trenches and fabrication methods. In an exemplary method, a semiconductor substrate can be provided. A mask layer can be provided on the semiconductor substrate. An etch-cleaning process can be performed. The etch-cleaning process can include etching the semiconductor substrate to form a shallow trench by one... Agent: Semiconductor Manufacturing International (shanghai) Corporation

20140332933 - Semiconductor structure and method for forming the same: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate; and a plurality of convex structures formed on a surface of the substrate and arranged in a longitudinal direction of the substrate, each convex structure having a top surface, a bottom surface... Agent:

20140332934 - Substrates for semiconductor devices: A method of manufacturing a composite substrate for a semiconductor device, the method comprising: selecting a substrate wafer comprising: a first layer of single crystal material suitable for epitaxial growth of a compound semiconductor thereon and having a thickness of 100 μm or less;a second layer having a thickness of... Agent:

20140332935 - Mgo-based coating for electrically insulating semiconductive substrates and production method thereof: The present invention relates to a magnesium oxide-based (MgO) inorganic coating intended to electrically insulate semiconductive substrates such as silicon carbide (SiC), and to a method for producing such an insulating coating. The method of the invention comprises the steps of preparing a treatment solution of at least one hydrolysable... Agent:

20140332936 - Package arrangement and method of forming the same: In various embodiments, a package arrangement may be provided. The package arrangement may include at least one chip. The package arrangement may further include encapsulation material at least partially encapsulating the chip. The package arrangement may also include a redistribution structure over a first side of the chip. The package... Agent: Infineon Technologies Ag

20140332937 - Workpiece with semiconductor chips, semiconductor device and method for producing a workpiece with semiconductor chips: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at... Agent:

20140332938 - Microelectronic devices and methods for manufacturing microelectronic devices: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. One such method includes forming a plurality of apertures in a substrate with the apertures arranged in an array, and, after forming the apertures, attaching the substrate to a lead frame having a plurality of pads with the apertures... Agent: Micron Technology, Inc.

20140332939 - Dual lead frame semiconductor package and method of manufacture: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection... Agent: Siliconix Electronic Co., Ltd.

20140332940 - Quad flat no-lead integrated circuit package and method for manufacturing the package: s

20140332941 - System, method and apparatus for leadless surface mounted semiconductor package: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is... Agent: Freescale Semiconductor, Inc.

20140332943 - Barrel-plating quad flat no-lead (qfn) packaging structures and method for manufacturing the same: A barrel-plating quad flat no-lead (QFN) package structure and a method for manufacturing the same. The method includes: providing a metal substrate for a plurality of QFN components; forming a first photoresist film on a top surface of the substrate; forming a plating pattern in the first photoresist film; forming... Agent: Jiangsu Changjiang Electronics Technology Co., Ltd.

20140332942 - Method of manufacturing semiconductor device and semiconductor device: Reliability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes a step of arranging a plurality of semiconductor chips next to each other over a chip mounting surface of a die pad. Further, the method of manufacturing a semiconductor device includes a step of electrically... Agent: Renesas Electronics Corporation

20140332944 - Resin-encapsulated semiconductor device and its manufacturing method: A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device (100) comprises a semiconductor chip (1) including a silicon substrate, a die pad (10) to which the semiconductor chip (1) is secured through a first solder layer (2), a resin-encapsulating layer (30)... Agent:

20140332945 - Method of etching a wafer: A method of etching a plurality of cavities in a wafer provides a wafer having a patterned hard mask layer. The patterned hard mask has open areas defining locations for first cavities and second cavities. A mask is applied to cover the patterned hard mask layer. The mask is etched... Agent:

20140332946 - Semiconductor package and stacked semiconductor package having the same: A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends... Agent:

20140332947 - Packages and methods for packaging: Packaged integrated devices and methods of forming the same are provided. In one embodiment, a packaged integrated device includes a package substrate, a package lid, and an integrated circuit or microelectromechanical systems (MEMS) device. The package lid is mounted to a first surface of the package substrate using an epoxy,... Agent: Analog Devices, Inc.

20140332949 - Method for creating a selective solder seal interface for an integrated circuit cooling system: A method for forming cooling channels in an interface for soldering to a semiconductor structure. The method includes: forming a metal seed layer on a surface of a substrate; patterning the metal seed layer into a patterned, plating seed layer covering portions of the substrate and exposing other portions of... Agent: Raytheon Company

20140332950 - Semiconductor device: A semiconductor device includes a cooling portion, which is made of ceramic or resin and includes a mounting surface, a metal circuit board, which is mounted on the mounting surface of the cooling portion and includes an element mounting surface, and a semiconductor element mounted on the element mounting surface... Agent: Kabushiki Kaisha Toyota Jidoshokki

20140332951 - Semiconductor device: A semiconductor device includes an insulating substrate with a conductive pattern including an insulating substrate, a conductive pattern formed on a front surface of the insulating substrate, and a rear heat-sink formed on a back surface of the insulating substrate; a semiconductor chip joined on the conductive pattern through joining... Agent:

20140332948 - Thermal management in 2.5 d semiconductor packaging: Lower semiconductor dies in 2.5 D semiconductor packaging configurations can be cooled by thermally coupling the lower semiconductor dies to a heat sink positioned above the interposer, to an upper semiconductor die, to a heat sink affixed beneath a substrate, or to free-flowing air circulating above the interposer or beneath... Agent: Futurewei Technologies, Inc.

20140332953 - Chip arrangement, and method for forming a chip arrangement: A chip arrangement may include: a chip including a plurality of electrical nets, wherein each electrical net includes at least one bonding pad; and a plurality of pillars formed on the at least one bonding pad of a majority of the plurality of electrical nets, wherein the plurality of pillars... Agent: Infineon Technologies Ag

20140332955 - Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof: A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die... Agent:

20140332954 - Semiconductor device: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of... Agent:

20140332952 - Semiconductor structure and method for testing the same: A semiconductor structure comprising a substrate, a dielectric layer, a conductor post, a first conductive layer structure and a second conductive layer structure is provided. The substrate comprises an opening structure. The dielectric layer is disposed on a sidewall of the opening structure. The conductor structure is disposed in the... Agent: United Microelectronics Corp.

20140332956 - Integrated circuit package with spatially varied solder resist opening dimension: An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of... Agent:

20140332957 - Semiconductor package and manufacturing method thereof: The present disclosure relates to a semiconductor package and a manufacturing method thereof The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body,... Agent: Advanced Semiconductor Engineering, Inc.

20140332958 - Method for manufacturing dummy gate in gate-last process and dummy gate in gate-last process: A method for manufacturing a dummy gate in a gate-last process is provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing... Agent:

20140332961 - Cu/cumn barrier layer and fabricating method thereof: In the present invention, the pure Cu film is deposited on the CuMn film and the Mn atoms are induced to diffuse within the dielectric layer. The barrier properties of this self-forming barrier are sensitive to the thickness, the annealing temperature, the annealing time and the impurity concentration of itself.... Agent: National Cheng Kung University

20140332962 - Device and method for reducing contact resistance of a metal: A structure for an integrated circuit with reduced contact resistance is disclosed. The structure includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the cap layer, and a trench embedded in the dielectric layer. The trench includes a TaN layer deposited on a side... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140332960 - Interconnect structures containing nitrided metallic residues: A metal cap is formed on an exposed upper surface of a conductive structure that is embedded within an interconnect dielectric material. During the formation of the metal cap, metallic residues simultaneously form on an exposed upper surface of the interconnect dielectric material. A thermal nitridization process or plasma nitridation... Agent: International Business Machines Corporation

20140332959 - Method of manufacturing semiconductor device and semiconductor device: A method of manufacturing a semiconductor device includes: a groove portion formation step of forming a groove portion in a base; a barrier layer formation step of forming a barrier layer that covers at least an inner wall surface of the groove portion; a seed layer formation step of forming... Agent: Ulvac, Inc.

20140332963 - Interconnect with hybrid metallization: An electronic interconnect structure having a hybridized metal structure near regions of high operating temperature on an integrated circuit, and methods of making the same. The hybridized metal structure features at least two different metals in a single metallization level. The first metal is in a region of high operating... Agent: International Business Machines Corporation

20140332964 - Interconnect structures containing nitrided metallic residues: A metal cap is formed on an exposed upper surface of a conductive structure that is embedded within an interconnect dielectric material. During the formation of the metal cap, metallic residues simultaneously form on an exposed upper surface of the interconnect dielectric material. A thermal nitridization process or plasma nitridation... Agent: International Business Machines Corporation

20140332965 - High performance refractory metal / copper interconnects to eliminate electromigration: An interconnect structure and method of making the same. A preferred interconnect structure has a first interconnect including a first dual damascene via and narrow line and a second interconnect at the same level as the first including a second dual damascene via and wider line. The first and second... Agent: International Business Machines Corporation

20140332967 - Bit cell with double patterened metal layer structures: An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure... Agent:

20140332968 - Chip package: A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal... Agent:

20140332969 - Chip package and method for forming the same: A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess... Agent:

20140332972 - Composite reconstituted wafer structures: A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behaviour of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials... Agent:

20140332966 - Epoxy-amine underfill materials for semiconductor packages: Epoxy-amine underfill materials for semiconductor packages and semiconductor packages having an epoxy-amine underfill material are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon. A semiconductor package substrate has a surface with a plurality of contact pads thereon. A plurality... Agent:

20140332971 - Method and layout of an integrated circuit: An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140332970 - Semiconductor device and method forming patterns with spaced pads in trim region: In a semiconductor device, parallel first and second conductive lines having a unit width extend from a memory cell region into a connection region. A trim region in the connection region includes pads respectively connected to the first and second conductive lines but are separated by a width much greater... Agent:

20140332979 - Architecture of spare wiring structures for improved engineering change orders: An integrated circuit includes a substrate having a plurality of electronic devices, a plurality of interconnect layers disposed on one or both sides of the substrate, and a plurality of active electrically conductive interconnect layer structures. The plurality of interconnect layers include horizontal interconnect and vertical-interconnect-access (VIA) layers. The plurality... Agent: Blackcomb Design Automation Inc.

20140332973 - Inline measurement of through-silicon via depth: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and... Agent: International Business Machines Corporation

20140332981 - Low-stress vias: A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define... Agent:

20140332980 - Methods of forming 3-d circuits with integrated passive devices: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the... Agent: Invensas Corporation

20140332975 - Multichip integration with through silicon via (tsv) die embedded in package: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as... Agent:

20140332978 - Optical wiring substrate, manufacturing method of optical wiring substrate and optical module: An optical wiring substrate includes a first conductor layer including a metal, a second conductor layer including a metal and arranged parallel to the first conductor layer, an insulation layer disposed to insulate the first conductor layer from the second conductor layer, and an electronic component including a photoelectric conversion... Agent: Hitachi Metals, Ltd.

20140332974 - Providing a void-free filled interconnect structure in a layer of a package substrate: Embodiments of the present disclosure are directed towards techniques and configurations for providing void-free filled interconnect structures in a dielectric layer of a package assembly. In one embodiment, the method for providing a void-free filled interconnect structure may include forming a through hole through a layer of a package substrate,... Agent:

20140332977 - Semiconductor device: A semiconductor device includes a metal pad formed over a semiconductor substrate; a dummy metal pad spaced apart from the metal pad by an open region; and a Polymide Isoindro Quirazorindione (PIQ) layer formed to cover the open region and to define a pad open region by exposing a center... Agent: Sk Hynix Inc.

20140332976 - Semiconductor package and fabrication method thereof: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first... Agent: Siliconware Precision Industries Co., Ltd.

20140332983 - Stacked chip package and method for forming the same: A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the... Agent:

20140332982 - Stacked packages and microelectronic assemblies incorporating the same: A microelectronic assembly includes units superposed on one another to form at least one stack having a vertical direction. Each unit includes one or more microelectronic devices and has top and bottom surfaces. Top unit terminals are exposed at the top surfaces and bottom unit terminals are exposed at the... Agent: Tessera, Inc.

20140332984 - Adhesive composition, process for producing the same, adhesive film using the same, substrate for mounting semiconductor and semiconductor device: Disclosed is an adhesive composition which includes (a) an epoxy resin, (b) a curing agent and (c) a polymer compound incompatible with said epoxy resin, and further optionally includes (d) a filler and/or (e) a curing accelerator. Also disclosed are a process for producing an adhesive composition, including mixing (a)... Agent:

20140332985 - Chip package and manufacturing method thereof: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad... Agent:

20140332986 - Semiconductor device and method of forming adhesive material to secure semiconductor die to carrier in wlcsp: A semiconductor device is made by providing a temporary carrier and providing a semiconductor die having a plurality of bumps formed on its active surface. An adhesive material is deposited as a plurality of islands or bumps on the carrier or active surface of the semiconductor die. The adhesive layer... Agent:

20140332987 - Curable resin composition and cured product thereof: Provided is a curable resin composition capable of forming a cured product which has excellent heat resistance, transparency, and flexibility and particularly excels in reflow resistance and barrier properties to a corrosive gas. The curable resin composition includes a ladder-type polyorganosilsesquioxane and an isocyanurate compound such as a triglycidyl isocyanurate... Agent:

  
  
  
Previous industry: Fences
Next industry: Railway mail delivery


######

RSS FEED for 20141113: xml
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.

######

Thank you for viewing Active solid-state devices (e.g., transistors, solid-state diodes) patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Active solid-state devices (e.g., transistors, solid-state diodes) patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Active solid-state devices (e.g., transistors, solid-state diodes) patents we recommend signing up for free keyword monitoring by email.



Results in 1.07402 seconds

PATENT INFO