Active solid-state devices (e.g., transistors, solid-state diodes) inventions

20080099752 - Carbon filament memory and fabrication method: An integrated circuit is described, including a memory element including a first carbon layer rich in a first carbon material and a second carbon layer rich in a second carbon material. The memory element stores information by reversibly forming a conductive channel in the second carbon layer, wherein the conductive... Agent: Slater & Matsil LLP

20080099753 - Phase change memory devices having dual lower electrodes and methods of fabricating the same: A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked... Agent: Marger Johnson & Mccollom, P.C.

20080099755 - Gallium nitride-based device and method: A gallium nitride-based device has a first GaN layer and a type II quantum well active region over the GaN layer. The type II quantum well active region comprises at least one InGaN layer and at least one GaNAs layer comprising 1.5 to 8% As concentration. The type II quantum... Agent: Philip D. Freedman PC

20080099754 - Method for providing a nanoscale, high electron mobility transistor (hemt) on insulator: A method and resulting high electron mobility transistor comprised of a substrate and a relaxed silicon-germanium layer formed over the substrate. A dopant layer is formed within the relaxed silicon-germanium layer. The dopant layer contains carbon and/or boron and has a full-width half-maximum (FWHM) thickness value of less than approximately... Agent: Schneck & Schneck

20080099757 - Organic field effect transistor and semiconductor device: It is an object to provide an organic field effect transistor including an electrode which can reduce an energy barrier at an interface between a conductive layer and a semiconductor layer, and a semiconductor device including the organic field effect transistor. A composite layer containing an organic compound and an... Agent: Eric Robinson

20080099758 - Organic polymer semiconductor, method of preparing the same, and ambipolar organic thin film transistor using the same: Disclosed are an organic polymer semiconductor, an ambipolar organic thin film transistor using the same, an electronic device comprising the ambipolar organic thin film transistor and methods of fabricating the same. Example embodiments relate to an organic polymer semiconductor, which may include an aromatic ring derivative having p-type semiconductor properties... Agent: Harness, Dickey & Pierce, P.L.C

20080099760 - Picture element driving circuit of display panel and display device using the same: The present invention provides a picture element driving circuit of an active matrix display device, with a configuration of no through-holes, including two or more FETs. A display device of the present invention has a structure in which a first field-effect transistor and a second field-effect transistor are provided, insulation... Agent: Stanley P. Fisher Reed Smith LLP

20080099756 - Semiconductor memory with organic selection transistor: An integrated semiconductor memory with a cell array is disclosed. In one embodiment the memory includes a multiplicity of memory cells arranged in rows and columns. In at least one memory cell, an organic selection transistor is integrated in a stack arrangement above an organic storage element.... Agent: Dicke, Billig & Czaja

20080099762 - Differential voltage defectivity monitoring circuit: A circuit uses a differential voltage response to identify fabrication process defects that would result if an IC design is fabricated (without re-designing to correct such defects). The circuit includes two stacks, whose respective outputs may be compared by a comparator, and comparator's output used to determine defectivity. In some... Agent: Silicon Valley Patent Group LLP

20080099761 - Test structure for opc-related shorts between lines in a semiconductor device: OPC results may be efficiently evaluated on the basis of a test structure containing a plurality of line features with opposing end portions. Thus, for different line parameters, the effect of OPC may be determined for a given critical tip-to-tip distance by determining the leakage behavior of the test assemblies,... Agent: Williams, Morgan & Amerson

20080099764 - Array substrate for liquid crystal display device and method of fabricating the same: An array substrate for an LCD device includes a gate line crossing a data line to define a pixel region. A thin film transistor (TFT) includes a gate electrode connected to the gate line, insulating and active layers on the gate electrode, a source electrode connected to the data line,... Agent: Brinks Hofer Gilson & Lione

20080099763 - Display panel: The invention discloses a display panel. A substrate comprising a chip bonding region and a cut cross-section is provided. A first conductive layer is disposed on the chip bonding region. An insulating layer is disposed on the substrate between the first conductive layer and the cut cross-section, covering a sidewall... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080099765 - Thin film transistor substrate and fabricating method thereof: A thin film transistor substrate and fabricating method thereof, the thin film transistor substrate including a substrate, a gate line and a gate electrode, each including a metal adhesion layer and a Cu alloy layer disposed on the substrate, an active layer and an ohmic contact layer disposed over the... Agent: Cantor Colburn, LLP

20080099770 - Integrated heat spreaders for light emitting devices (leds) and related assemblies: A light emitting device (LED) assembly may include an electrically insulating substrate and a thermally conductive layer on a surface of the insulating substrate. A light emitting device may be on the thermally conductive layer so that the thermally conductive layer is between the light emitting device and the electrically... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080099771 - Light emitting diode and wafer level package method, wafer level bonding method thereof, and circuit structure for wafer level package: This invention discloses a light emitting diode, a wafer level package method, a wafer level bonding method, and a circuit structure for a wafer level package. The light emitting diode includes a package carrier, a conducting material, at least one light emitting diode structure and a package material. The package... Agent: Rosenberg, Klein & Lee

20080099772 - Light emitting diode matrix: A light source includes a light emitting diode (LED) module having a continuous substrate, a layer of n-type semiconductor material formed above the substrate, and a layer of p-type semiconductor material formed above the n-type semiconductor material. A p-n junction is formed between the p-type and n-type semiconductor materials. The... Agent: Fish & Richardson PC

20080099775 - Light emitting diode module and apparatus thereof: A light emitting diode (LED) module employs a one-piece integrated column heat conductive electrode to carry at least one LED chip, so as to quickly remove the heat generated by the LED chip while emitting light. The LED module includes at least one LED chip, a column heat conductive electrode,... Agent: Seyfarth Shaw LLP

20080099774 - Method for high-volume production of light emitting diodes with attached lenses: A method for high-volume production of light emitting diodes with attached lenses involves providing pre-fabricated lenses, wherein the pre-fabricated lenses are held by a common transfer structure, simultaneously attaching the pre-fabricated lenses to respective ones of light emitting diodes, and releasing the pre-fabricated lenses from the common transfer structure. In... Agent: Kathy Manke Avago Technologies Limited

20080099776 - Nitride semiconductor light emitting device and method of manufacturing the same: There are provided a nitride semiconductor light emitting device and a method of manufacturing the same, the device including: a first conductivity type nitride semiconductor layer formed on a substrate; an active layer formed on the first conductivity type nitride semiconductor layer; a second conductivity type nitride semiconductor layer formed... Agent: Mcdermott Will & Emery LLP

20080099778 - Led package structure for increasing light-emitting effiency and method of packaging the same: An LED package structure for increasing light-emitting efficiency includes: a substrate unit, and a plurality of fluorescence colloid units, LED units, conductive units and opaque units. The substrate unit has a main body and a plurality of through holes passing through the main body. Each fluorescence colloid unit is received... Agent: Rosenberg, Klein & Lee

20080099777 - Light-emitting devices and related systems: Light-emitting devices can include a package that supports one or more light-emitting die (e.g., light-emitting diode die, laser diode die) and which can ensure mechanically stability, can facilitate electrical and/or thermal coupling with light-emitting die, and can manipulate the manner by which light generated by the die is emitted out... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.C.

20080099779 - Smd diode holding structure and package thereof: An SMD diode holding structure includes a plastic and a plurality of metal holders. Two ends of the plastic from a function area and a notch. The metal holder has a base portion and a connecting pin portion. The top and bottom surfaces of the base portion are exposed to... Agent: Rosenberg, Klein & Lee

20080099759 - Manufacturing method of semiconductor device and semiconductor device: A method of manufacturing a semiconductor device includes steps of forming a gate electrode over a light-transmitting substrate, forming a gate insulating layer containing an inorganic material over the gate electrode and the substrate, forming an organic layer containing a photopolymerizable reactive group over the gate insulating layer, polymerizing selectively... Agent: Nixon Peabody, LLP

20080099766 - Switching device for a pixel electrode: The invention discloses a switching device for a pixel electrode of display device. The switching device comprises a gate formed on a substrate; a gate-insulating layer formed on the gate; a first buffer layer formed between the substrate and the gate and/or between the gate and the gate-insulating layer, wherein... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080099767 - Gan related compound semiconductor element and process for producing the same and device having the same: A GaN related compound semiconductor element includes: a channel layer made of a GaN related compound semiconductor; and a source layer and a drain layer, which are disposed in a manner of sandwiching the channel layer. The source layer includes two adjacent ridge portions which are formed by selective growth.... Agent: Cantor Colburn, LLP

20080099768 - Diamond transistor and method of manufacture thereof: A method of manufacturing a transistor, typically a MESFET, includes providing a substrate including single crystal diamond material having a growth surface on which further layers of diamond material can be deposited. The substrate is preferably formed by a CVD process and has high purity. The growth surface has a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080099769 - Production of an integrated circuit including electrical contact on sic: Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on... Agent: Dicke, Billig & Czaja

20080099773 - Light emitting diode: In a light emitting diode, a light-emitting region is including an active layer provided between a first conductivity type cladding layer formed on the semiconductor substrate and a second conductivity type cladding layer. A transparent conductive film made of a metal oxide is located over the light-emitting region. A layer... Agent: Foley And Lardner LLP Suite 500

20080099780 - Method for producing group iii - group v vertical light-emitting diodes: A method of producing one or more vertical light-emitting diode (VLED) dies having a light-emitting diode (LED) stack comprising Group III-Group V combinations of elements (e.g., GaN, AlN, InN, AlGaN, InGaN, and InAlGaN) and a metal substrate is provided. The techniques include forming an InGaN or InAlGaN interface layer above... Agent: Patterson & Sheridan, L.L.P.

20080099781 - Method of manufacturing iii group nitride semiconductor thin film and method of manufacturing iii group nitride semiconductor device using the same: A method of manufacturing a III group nitride semiconductor thin film and a method of manufacturing a nitride semiconductor light emitting device employing the III group nitride semiconductor thin film manufacturing method, the III group nitride semiconductor thin film manufacturing method including: growing a first nitride single crystal on a... Agent: Mcdermott Will & Emery LLP

20080099782 - Nitride semiconductor light emitting diode: Provided is a nitride semiconductor light emitting diode (LED) including a substrate; an n-type nitride semiconductor layer formed on the substrate; an active layer formed on a portion of the n-type nitride semiconductor layer; a p-type nitride semiconductor layer formed on the active layer; a p-type contact layer formed on... Agent: Mcdermott Will & Emery LLP

20080099783 - Semiconductor integrated circuit and method for manufacturing the same: A semiconductor integrated circuit includes a power transistor formed on a semiconductor substrate, a plurality of first metal patterns and a plurality of second metal patterns which are formed right above the power transistor and function as a first electrode and as a second electrode of the power transistor, respectively,... Agent: Mcdermott Will & Emery LLP

20080099784 - Array quad flat no-lead package and method of forming same: An array QFN package (10) includes a first semiconductor package (12) and a lead frame (14) having a plurality of leads (16). A first IC die (22) is attached on a first side to the first semiconductor package (12) and is electrically connected to the leads (16) of the lead... Agent: Freescale Semiconductor, Inc. Law Department

20080099785 - Defect reduction using aspect ratio trapping: Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls.... Agent: Goodwin Procter LLP Patent Administrator

20080099786 - Low noise and high performance lsi device, layout and manufacturing method: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be... Agent: Mills & Onello LLP

20080099788 - Semiconductor device and method for manufacturing the same: The external base electrode has a two-layered structure where a p-type polysilicon film doped with a medium concentration of boron is laminated on a p-type polysilicon film doped with a high concentration of boron. Therefore, since the p-type polysilicon film doped with a high concentration of boron is in contact... Agent: Miles & Stockbridge PC

20080099787 - Semiconductor structure and method of manufacture: A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first... Agent: Greenblum & Bernstein, P.L.C

20080099789 - Self-aligned method of forming a semiconductor memory array of floating gate memory cells with source side erase, and a memory array made thereby: A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a substrate of semiconductor material having a first conductivity type, source and drain regions formed in the substrate, a block of conductive material disposed over and electrically connected to... Agent: Dla Piper US LLP

20080099790 - Layout structure: A layout structure is provided with a conducting line extending in a conducting line direction, the conducting line being arranged within a substrate area, a fill element being arranged within the substrate area at a predetermined distance from the conducting line, the fill element having a fill element axis extending... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080099791 - Memory cell device with circumferentially-extending memory element: A memory cell device, including a memory material switchable between electrical property states by the application of energy, has bottom and top electrode members and a dielectric material between the two. The bottom and top electrode members have outer, circumferentially-extending surfaces aligned with one another. A memory element, comprising the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080099792 - Memory devices and methods of fabricating the same: Memory devices include a semiconductor substrate and a plurality of wordlines on the semiconductor substrate. A ground select line is on the semiconductor substrate on a first side of the wordlines and a string select line is on the semiconductor substrate on a second side of the wordlines. The wordlines... Agent: Myers Bigel Sibley & Sajovec

20080099793 - Photodiode module and apparatus including multiple photodiode modules: Various embodiments of the present invention are directed to a photodiode module including a structure configured to selectively couple light to a dielectric-surface mode of a photonic crystal of the photodiode module. In one embodiment of the present invention, a photodiode module includes a semiconductor structure having a p-region and... Agent: Hewlett Packard Company

20080099794 - Semiconductor device comprising nmos and pmos transistors with embedded si/ge material for creating tensile and compressive strain: By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer... Agent: J. Mike Amerson, Williams, Morgan & Amerson, P.C.

20080099795 - Finfet transistor and circuit: A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated... Agent: Schmeiser, Olsen & Watts

20080099796 - Device with patterned semiconductor electrode structure and method of manufacture: A method of forming a semiconductor device can include forming a first layer of semiconductor material in contact with a first area of a substrate. The first area can be adjacent to at least one electrical isolation structure that extends into the substrate and has a top portion extending above... Agent: Bradley T. Sako Haverstock & Owens, LLP

20080099797 - Method and device for sensing radiation: A device is disclosed for sensing radiation, having a gate region and a substrate, wherein one of the gate region and the substrate is configured as an input for radiation. A channel region, connecting a source region and a drain region of the transistor device is provided. The device is... Agent: Darryl G. Walker

20080099798 - Methods and devices for amplifying a signal: A junction field effect transistor (JFET) device is disclosed for amplifying an input signal. The JFET device includes a first gate region and a substrate/well/bulk region that may form a second gate region. The JFET device also includes a first source/drain region and a second source/drain region. The first source/drain... Agent: Darryl G. Walker

20080099800 - Integrated matching network and method for manufacturing integrated matching networks: An integrated matching network and method for manufacturing an integrated matching network are provided. The method includes forming (405) a first die on a substrate, forming (410) a second die on the substrate, and forming (415) a metallization layer on the first and second dies. The second die has a... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080099799 - Micropad for bonding and a method therefor: A semiconductor process is taught for performing electroless plating of copper overlying at least a portion of a layer comprising cobalt, nickel, or both cobalt and nickel. The cobalt and/or nickel comprising layer may be formed using electroless plating. For some embodiments, a tin layer is then formed overlying the... Agent: Freescale Semiconductor, Inc. Law Department

20080099801 - Metal-oxide-semiconductor transistor and method of forming the same: A method of manufacturing a MOS transistor device. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next,... Agent: North America Intellectual Property Corporation

20080099802 - Transmission line transistor: A transistor comprises a gate, a source, and a drain. The gate is configured as a gate transmission line having a first characteristic impedance, and has an input at a first end thereof, and an output at a second end thereof. The source is configured as a source transmission line... Agent: Kathy Manke Avago Technologies Limited

20080099804 - Image sensor having curved micro-mirrors over the sensing photodiode and method for fabricating: The invention involves the integration of curved micro-mirrors over a photodiode active area (collection area) in a CMOS image sensor (CIS) process. The curved micro-mirrors reflect light that has passed through the collection area back into the photo diode. The curved micro-mirrors are best implemented in a backside illuminated device... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080099803 - Thin film transistor: A thin film transistor is disclosed comprising comprises a substrate, a dielectric layer, and a semiconductor layer. The semiconductor layer, which is crystalline zinc oxide preferentially oriented with the c-axis perpendicular to the plane of the dielectric layer or substrate, is prepared by liquid depositing a zinc oxide nanodisk composition.... Agent: Fay Sharpe / Xerox - Rochester

20080099805 - Cmos imaging sensor: A CMOS image sensor and active pixel cell design that provides an output signal representing an incident illumination light level that is adapted for time domain analysis. Thus, the noise sources associated with charge integration and the contribution of dark current to it, is avoided. The active pixel cell design... Agent: Scully, Scott, Murphy & Presser, P.C.

20080099806 - Image sensor having heterojunction bipolar transistor and method of fabricating the same: Provided are image sensor having a heterojunction bipolar transistor (HBT) and a method of fabricating the same. The image sensor is fabricated by use of silicon-germanium bipolar junction transistor complementary metal oxide semiconductor (SiGe BiCMOS) technology. In the image sensor, a PD employs a floating-base-type SiGe HBT unlike a pn-junction-based... Agent: Ladas & Parry LLP

20080099807 - Low-voltage image sensor and method of driving transfer transistor thereof: Provided are a low-voltage image sensor and a method of driving a transfer transistor thereof, which are obtained by changing the structure and driving method of a typical transfer transistor of a 4-transistor CMOS transistor, and can eliminate the influence of a voltage or physical structure of a diffusion node... Agent: Ladas & Parry LLP

20080099808 - One transistor dram cell structure and method for forming: A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a Schottky diode junction with the body... Agent: Freescale Semiconductor, Inc. Law Department

20080099809 - Semiconductor device having a capacitance element and method of manufacturing the same: A dielectric film is formed by depositing an amorphous strontium oxide film to a thickness of one to several atomic layers on a first electrode layer, then depositing an amorphous titanium oxide film to a thickness of one to several atomic layers on the amorphous strontium oxide film, and then... Agent: Sughrue Mion, PLLC

20080099810 - Semiconductor device and semiconductor device manufacturing method: A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080099811 - Single transistor memory device having source and drain insulating regions and method of fabricating the same: A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both... Agent: Volentine & Whitt PLLC

20080099812 - Semiconductor device: A semiconductor device in which a DRAM and a SRAM are mixedly mounted is provided. The DRAM and the SRAM have a stack-type structure in which a bitline is formed below a capacitive element. A cross couple connection of the SRAM is formed in a layer or below the layer... Agent: Sughrue Mion, PLLC

20080099813 - Semiconductor device and semiconductor device manufacturing method: A semiconductor device including a semiconductor substrate having a logic formation region in which a memory device is formed and a logic formation region in which a logic device is formed; a first impurity region formed in an upper surface of said semiconductor substrate in the logic formation region; a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080099814 - Integrated circuit and method for production: An array of vertical transistor cells formed in a substrate for selecting one of a plurality of memory cells by selecting a word line and a bit line is disclosed. In one embodiment, for minimizing the area of a cell and reducing complexity in production a plurality of parallel insulating... Agent: Dicke, Billig & Czaja

20080099815 - Semiconductor device having a vertical transistor and method for manufacturing the same: A semiconductor device having a vertical transistor comprises a silicon substrate; a drain region, a channel region and a source region vertically stacked on the silicon substrate; a buried type bit line formed under the drain region in the silicon substrate to contact with the drain region and to extend... Agent: Townsend And Townsend And Crew, LLP

20080099816 - Memory cell and method for forming the same: A semiconductor memory cell structure having 4F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080099817 - Method for obtaining extreme selectivity of metal nitrides and metal oxides: Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H2F2. The etchant can be used to selectively remove metal nitride layers relative to doped or undoped oxides, tungsten, polysilicon, and titanium nitride.... Agent: Knobbe Martens Olson & Bear LLP

20080099818 - Non-volatile memory and manufacturing method and erasing method thereof: A non-volatile memory is provided, including a control gate, a floating gate, a gate oxide layer, a source region, a drain region, a first dielectric layer, a second dielectric layer, and an erase gate. The control gate is disposed in a substrate. The floating gate comprising a coupling part and... Agent: Jianq Chyun Intellectual Property Office

20080099819 - Nonvolatile semiconductor storage apparatus and method for manufacturing the same: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage apparatus including: a substrate; a columnar semiconductor disposed perpendicular to the substrate; a charge storage laminated film disposed around the columnar semiconductor; a first conductor layer that is in contact with the charge storage laminated... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080099824 - Flash memory device and method of fabricating the same: A flash memory device and a method of fabricating the same are provided. The flash memory device may include an isolation layer provided in a semiconductor substrate to define an active region. A floating gate may be provided on the active region. The floating gate may be spaced a first... Agent: Harness, Dickey & Pierce, P.L.C

20080099821 - Flash memory device and method of manufacturing the same: A method of manufacturing semiconductor devices includes providing a semiconductor substrate including first active areas and isolation areas alternately arranged to be parallel to each other and second active areas connecting the first active areas to each other. A tunnel insulating layer, a charge storage layer, and an isolation mask... Agent: Townsend And Townsend And Crew, LLP

20080099820 - Growth of metallic nanodots using specific precursors: A technique to form metallic nanodots in a two-step process involving: (1) reacting a silicon-containing gas precursor (e.g., silane) to form silicon nuclei over a dielectric film layer; and (2) using a metal precursor to form metal nanodots where the metal nanodots use the silicon nuclei from step (1) as... Agent: Schneck & Schneck

20080099823 - Non-volatile memory device and method of manufacturing the same: A method of manufacturing a non-volatile memory device includes forming a trench using the shallow trench isolation (STI) method; forming a first insulating layer on a semiconductor device including the trench; forming a conductive layer on the semiconductor device including the trench; etching the conductive layer to form a conductive... Agent: Townsend And Townsend And Crew, LLP

20080099822 - Nonvolatile memory devices and methods of fabricating the same: A nonvolatile memory device may include a semiconductor substrate, a floating gate electrode on the semiconductor substrate that includes an acute-angled tip at an upper end, and a control gate electrode insulated from the floating gate electrode and facing at least a portion of the floating gate electrode, wherein an... Agent: Lee & Morse, P.C.

20080099825 - Nonvolatile semiconductor memory device and method of producing the same: A nonvolatile semiconductor memory device includes a semiconductor substrate having a principal surface, memory transistors, and selection transistors. Each of the memory transistors has a floating gate and a control gate that are formed by lamination with each other on the principal surface. Each of the selection transistors has a... Agent: Mcdermott Will & Emery LLP

20080099830 - Cylindrical channel charge trapping devices with effectively high coupling ratios: A memory cell comprising: a source region and a drain region separated by a semiconductor channel region, the channel region having a channel surface having an area A1 including a first cylindrical region, a first dielectric structure on the channel surface, a dielectric charge trapping structure on the first dielectric... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080099827 - Modifiable gate stack memory element: An apparatus and method for storing information are provided, including using a transistor having a channel, a gate oxide layer, a gate electrode, and a modifiable gate stack layer. The on-resistance of the transistor is changed by causing a non-charge-storage based physical change in the modifiable gate stack layer, to... Agent: Slater & Matsil LLP

20080099829 - Mosfet devices and systems with nitrided gate insulators and methods for forming: A nonvolatile read-only memory having a thin nitrided tunnel insulator surface with a charge blocking insulator over the nitrided surface is presented. The tunnel insulator may be formed of a metal oxide, a metal oxycarbide, a semiconductor oxide, or oxycarbide. The dielectric structure may be formed by nitridation of a... Agent: Schwegman, Lundberg & Woessner, P.A.

20080099826 - Non-volatile memory cells having a polysilicon-containing, multi-layer insulating structure, memory arrays including the same and methods of operating the same: Memory cells including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region; a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure... Agent: Akin Gump LLP - Silicon Valley

20080099831 - Semiconductor memory device and method for the same: The first and second charge storing units are configured by stacking layers in order from bottom oxide films 41a, 41b to charge storing nitride films 42a, 42b to top oxide films 43a, 43b, respectively. At the same time, the distance between the first main electrode and the charge storing nitride... Agent: Rabin & Berdo, PC

20080099828 - Semiconductor structure, semiconductor memory device and method of manufacturing the same: A semiconductor memory device includes a semiconductor substrate, first conductive lines, second conductive lines, and memory cells. The second conductive lines include doped regions within the substrate and have a ratio of depth to width that is greater than unity. A semiconductor structure comprises a semiconductor substrate, a doped region... Agent: Edell, Shapiro & Finnan, LLC

20080099832 - Nrom frabrication method: A method of fabricating an oxide-nitride-oxide (ONO) layer in a memory cell to retain charge well in the nitride layer includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer and oxidizing a top oxide layer, thereby causing oxygen to be introduced into the... Agent: Empk & Shiloh, LLP

20080099833 - Mos transistor suppressing short channel effect and method of fabricating the same: A MOS transistor suppressing a short channel effect includes a substrate, a first diffusion region and a second diffusion region separated from each other by a channel region in an upper portion of the substrate, a gate insulating layer including a first gate insulating layer disposed on a surface of... Agent: Townsend And Townsend And Crew, LLP

20080099835 - Exposure mask and method for forming a gate using the same: An exposure mask and a method for forming a gate using the same are provided. A recess is formed by using a recess exposure mask with an isolated light transmitting pattern so that the recess may be formed only on an active region, and an edge of the active region... Agent: Marshall, Gerstein & Borun LLP

20080099834 - Transistor, an inverter and a method of manufacturing the same: An inverter which is at least partially formed in a semiconductor substrate includes a first transistor with a first channel and a second transistor with a second channel, wherein each of the first and second transistors is formed as a FinFET with ridge shaped channels. The first and second gate... Agent: Edell , Shapiro & Finnan , LLC

20080099836 - Semiconductor device and manufacturing method of the same: A trench is formed so as to reach a p−-type epitaxial layer from an upper surface of a source region. A gate electrode is formed so as to bury the trench. Each of body contact trenches is formed away from the gate electrode. A body contact region is formed at... Agent: Miles & Stockbridge PC

20080099837 - Semiconductor device: This semiconductor device an epitaxial layer of a first conductivity type formed on a surface of the first semiconductor layer, and a base layer of a second conductivity type formed on a surface of the epitaxial layer. A diffusion layer of a first conductivity type is selectively formed in the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080099838 - Semiconductor apparatus using back-side high-withstand-voltage integrated circuit: A semiconductor apparatus includes an electroconductive member; a switching device electrically connected to the electroconductive member on the electroconductive member and having a withstand voltage between a front side and a back side as a first withstand voltage; a back-side high-withstand-voltage integrated circuit provided on the electroconductive member separately from... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080099841 - Method and structure for reducing soi device floating body effects without junction leakage: A method of reducing silicon-on-insulator (SOI) floating body effects in a semiconductor device includes forming a buried insulator layer over a substrate material; forming a crystalline SOI layer over the buried insulator layer; forming a gate conductor over the SOI layer; and performing an angled implant of the semiconductor device... Agent: Cantor Colburn LLP - IBM Fishkill

20080099842 - Single walled carbon nanotubes coated with dielectric substance and tft using thereof: The present invention relates to a technology for printing a thin film transistor (TFT) using single walled carbon nanotubes coated with dielectric substance having a thickness of several nm and thus capable of improving significantly a low on/off ratio of an existing single walled carbon nanotube TFT.... Agent: The Webb Law Firm, P.C.

20080099843 - Structure of thin film transistor: A structure of a thin film transistor (TFT) is provided. A substrate has a first surface and a second surface opposite to each other, in which the first surface has a patterned mask layer. A patterned first electrode layer is disposed on the second surface of the substrate and has... Agent: Jianq Chyun Intellectual Property Office

20080099840 - System and method for providing a nanoscale, highly selective, and thermally resilient boron etch-stop: A method for forming an etch-stop layer and a resulting structure fabricated therefrom. The etch-stop layer has a semiconductor layer having a first surface and a boron layer formed below the first surface of the semiconductor layer. The boron layer has a full-width half-maximum (FWHM) thickness value of less than... Agent: Schneck & Schneck

20080099839 - Ultra-thin oxide bonding for s1 to s1 dual orientation bonding: A multi-layered substrate with bulk substrate characteristics and processes for the fabrication of such substrates are herein disclosed. The multi-layered substrate can include a first layer, a second layer and an interfacial layer therebetween. The first and second layers can be silicon, germanium, or any other suitable material of the... Agent: Blakely Sokoloff Taylor & Zafman

20080099844 - Multiple layer and cyrstal plane orientation semiconductor substrate: A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer,... Agent: Schmeiser, Olsen & Watts

20080099846 - Semiconductor device and its manufacture method: A semiconductor device has a first MOS transistor formed on first active region of the first conductivity type, having first gate electrode structure, first source/drain regions, recesses formed in the first source/drain regions, and semiconductor buried regions buried and grown on the recesses for applying stress to the channel under... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080099845 - Sub-lithographic gate length transistor using self-assembling polymers: A semiconductor structure including at least one transistor located on a surface of a semiconductor substrate, wherein the at least one transistor has a sub-lithographic channel length, is provided. Also provided is a method to form such a semiconductor structure using self-assembling block copolymer that can be placed at a... Agent: Scully, Scott, Murphy & Presser, P.C.

20080099847 - Integrated circuits and methods of forming a field effect transistor: Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and... Agent: Mark Matkin Wells St. John P.s.

20080099848 - Method and apparatus for electrostatic discharge protection having a stable breakdown voltage and low snapback voltage: Electrostatic discharge (ESD) protection is provided for an integrated circuit. Snap back from a lower initial critical voltage and critical current is provided, as compared to contemporary designs. A dynamic region having doped regions is formed on a substrate, interconnects contacting the dynamic region. The dynamic region includes an Nwell... Agent: Delphi Technologies, Inc.

20080099849 - Method of manufacturing a semiconductor device having a multi-channel type mos transistor: In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate patterns and single crystalline silicon patterns that are alternately stacked with each other. A source/drain layer is formed on a sidewall of the active channel pattern.... Agent: Marger Johnson & Mccollom, P.C.

20080099850 - Semiconductor device including a fin field effect transistor and method of manufacturing the same: In a fin field effect transistor (Fin FET)and a method of manufacturing the Fin FET, the Fin FET includes an active pattern inside which insulating layer patterns are formed, an isolation layer pattern enclosing a sidewall of the active pattern such that an opening exposing a sidewall of the active... Agent: Harness, Dickey & Pierce, P.L.C

20080099851 - Semiconductor devices with dual-metal gate structures and fabrication methods thereof: Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080099852 - Integrated semiconductor device and method of manufacturing an integrated semiconductor device: An integrated semiconductor device includes at least one transistor. A first and a second source/drain diffusion region are arranged in a doped well. A contact structure is arranged on or above the substrate surface and abuts the lateral sidewall of a gate electrode isolation and electrically contacts the first source/drain... Agent: Slater & Matsil LLP

20080099853 - Thin film transistor and fabrication method thereof: A thin film transistor including a substrate, a first buffer layer, a gate, a gate insulation layer, a channel layer, a source and a drain is provided. The first buffer layer is disposed on the substrate and the first buffer is a silicide. The gate covers a portion of the... Agent: Jianq Chyun Intellectual Property Office

20080099855 - Semiconductor device and method of fabricating the same: A protective film (56) having a water/hydrogen blocking function is formed so as to cover the periphery of a pad electrode (54a) while being electrically isolated from the pad electrode. A material selected in the embodiment for composing the protective film is a highly moisture-proof material having a water/hydrogen blocking... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080099854 - Semiconductor integrated circuit device and process for manufacturing the same: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080099856 - Method of fabricating semiconductor device having multiple gate dielectric layers and semiconductor device fabricated thereby: A method of fabricating a semiconductor device having multiple gate dielectric layers and a semiconductor device fabricated thereby, in which the method includes forming an isolation layer defining first and second active regions in a semiconductor substrate. A passivation layer is formed on the substrate having the isolation layer. A... Agent: F. Chau & Associates, LLC

20080099858 - Semiconductor device and manfacturing method of the same: After forming a fin portion to be active region, openings are formed at portions corresponding to channel portions in a gate dielectric film 22 and a silicon nitride film 23 which cover the fin portion. Exposed surfaces of the silicon substrate 21 in the openings are oxidized to form oxide... Agent: Young & Thompson

20080099857 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes a first and a second field-effect transistors having a gate electrode formed as a ring shape, a drain diffusion layer formed inside the gate electrode and a source diffusion layer formed outside the gate electrode and a substrate potential diffusion layer or a well... Agent: Foley And Lardner LLP Suite 500

20080099859 - Method of manufacturing semiconductor device having of spacer gate structure: In a case of using a silicon nitride film as an offset spacer for forming an extension region of a transistor, an oxide protective surface is formed by oxygen plasma processing on the surface of the silicon nitride film.... Agent: Mcginn Intellectual Property Law Group, PLLC

20080099860 - Semiconductor array and method for manufacturing a semiconductor array: a semiconductor Array and method for Manufacturing a semiconductor array is provided that includes a substrate, an element layer of a single-crystal semiconductor material, an isolation layer that is formed between the substrate and the element layer and isolates the element layer from the substrate, a number of elements that... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20080099861 - Sensor device package having thermally compliant die pad: A sensor device and a method of forming thereof comprises a die pad having an inner portion and an outer portion. The outer portion is made of steel, aluminum or other metal and is adapted to mount the die pad to a support structure having a first coefficient of thermal... Agent: Thelen Reid Brown Raysman & Steiner LLP

20080099862 - Physical quantity sensor and method for manufacturing the same: A method for manufacturing a physical quantity sensor includes: forming a sensor element in a first wafer; stacking a support substrate, a connection layer and a cap layer in this order so that a second wafer is prepared; bonding the cap layer of the second wafer to the first wafer... Agent: Posz Law Group, PLC

20080099863 - Elevated bipolar transistor structure: A semiconductor structure includes a substrate; an isolation structure in the substrate, wherein the isolation structure defines a region therein; a first semiconductor region having at least a portion in the region defined by the isolation structure, wherein the first semiconductor region is of a first conductivity type; a second... Agent: Slater & Matsil, L.L.P.

20080099864 - Chip package, method of making same and digital camera module using the package: A digital camera module (100) includes a chip package (110) and a lens module (130), mounted on the chip package, for forming a focused image on the chip package. The chip package includes a supporter (112), a chip (114), a plurality of wires (116), a main adhesive (118), and a... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang J

20080099865 - Image sensor: Embodiments relate to an image sensor and a method for manufacturing an image sensor. According to embodiments, a transistor structure may be manufactured on a semiconductor substrate, and an insulating layer covering the transistor structure may be formed. The insulating layer may be patterned to form a first via that... Agent: Sherr & Nourse, PLLC

20080099866 - Image sensing module and method for packaging the same: An image sensing module and a method for packaging the same are disclosed. Meanwhile, the packaging method includes the steps of a) providing a substrate; b) forming plural passive devices on the substrate; c) adhering a chip on the substrate and bonding thereon; d) providing a ring frame, wherein the... Agent: Bacon & Thomas, PLLC

20080099867 - Solid-state imaging device and electronic device: A solid-state imaging device including a number of pixels each having a photoelectric converting portion and arranged one-dimensionally or in a two-dimensional matrix is provided. The solid-state imaging device includes a peripheral wiring portion with a multilayer stricture provided around at least part of the photoelectric converting portion in each... Agent: Sonnenschein Nath & Rosenthal LLP

20080099868 - Photoelectric conversion device, image sensor, and method for manufacturing photoelectric conversion device: A photoelectric conversion device includes a photoelectric conversion layer that is stacked on a semiconductor substrate and that has first, second, and third photoelectric conversion regions, and first, second, and third dividing regions. The first dividing region is formed at a predetermined depth from a surface of the photoelectric conversion... Agent: Rabin & Berdo, PC

20080099869 - Two-dimensional image detecting apparatus and method for manufacturing the same: The present invention provides a two-dimensional image detecting apparatus including a mold structure which apparatus can be applied to mammography, and a manufacturing method thereof. The manufacturing method includes: a conversion layer formation step of forming a conversion layer (3) on an active matrix substrate (2); a counter substrate formation... Agent: Nixon & Vanderhye, PC

20080099870 - Method of manufacturing a photodiode array with through-wafer vias: A method for manufacturing a photodiode array includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has a first layer of a first conductivity proximate the first main surface and a second layer of a second conductivity proximate the second main... Agent: Panitch Schwarze Belisario & Nadel LLP

20080099871 - Front-side illuminated, back-side contact double-sided pn-junction photodiode arrays: The present invention is a photodiode detector array for use in computerized tomography (CT) and non-CT applications. Specifically, the present invention is a high-density photodiode arrays, with low dark current, low capacitance, high signal to noise ratio, high speed, and low crosstalk that can be fabricated on relatively large substrate... Agent: Hazim Hamied Ansari

20080099872 - Inductive load driving circuit: The objective of this invention is to provide a photodiode which has high sensitivity even to light with a wavelength in the blue region while maintaining the high-frequency characterstics. The n type second semiconductor layer (13) containing an n type electroconductive impurity at a low concentration is formed directly or... Agent: Texas Instruments Incorporated

20080099873 - Semiconductor device, design method and structure: A semiconductor device can include at least a first diffusion region formed by doping a semiconductor substrate and at least a second diffusion region formed by doping the semiconductor substrate that is separated from the first diffusion region by an isolation region. At least a first conductive line can comprise... Agent: Bradley T. Sako Haverstock & Owens, LLP

20080099874 - Semiconductor integrated circuit capable of realizing reduction in size: In a semiconductor integrated circuit in which an element isolating insulation film is provided on a substrate, an isolated Si region in the substrate is a shape composed of straight lines which form four sides and circular arcs which form four corners. Further, the adjacent Si regions share element isolating... Agent: Cantor Colburn, LLP

20080099875 - Structure of strained silicon on insulator and method of manufacturing the same: Provided is a strained SOI structure and a method of manufacturing the strained SOI structure. The strained SOI structure includes an insulating substrate, a SiO2 layer formed on the insulating substrate, and a strained silicon layer formed on the SiO2 layer.... Agent: Buchanan, Ingersoll & Rooney PC

20080099876 - Manufacturing method of semiconductor device and semiconductor device: The present invention provides a method of manufacturing a semiconductor device, which comprises steps of forming a plurality of wirings on a first insulting film formed on a semiconductor substrate so as to adjoin one another, forming a second insulating film on the first insulating film by a plasma CVD... Agent: Rabin & Berdo, PC

20080099877 - Damage propagation barrier and method of forming: A conductor-filled damage propagation barrier is formed extending into a low-k dielectric layer between a fuse and an adjacent circuit element for preventing propagation of damage during a fuse blow operation. Conductor material filling the damage propagation barrier is formed from the same conductor layer as that used to form... Agent: Ibm Microelectronics Intellectual Property Law

20080099878 - Semiconductor device and manufacturing method of the same: It is an object of the present invention to provide a high-performance and high reliable semiconductor device and to provide a technique of manufacturing the semiconductor device at low cost with high yield. The semiconductor device is manufactured by steps of forming a first conductive layer, forming a first liquid-repellent... Agent: Eric Robinson

20080099879 - Capacitor pairs with improved mismatch performance: A semiconductor device includes a first capacitor comprising a plurality of first unit capacitors interconnected to each other, each having a first unit capacitance; and a second capacitor comprising a plurality of second unit capacitors interconnected to each other, each having a second unit capacitance, wherein the first unit capacitors... Agent: Slater & Matsil, L.L.P.

20080099880 - Method, system and design structure for symmetrical capacitor: Methods, articles and design structures for capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the... Agent: Driggs, Hogg, Daugherty & Del Zoppo Co., L.p.a.

20080099881 - Semiconductor for macro and micro frequency tuning, and antenna and frequency tuning circuit having the semiconductor: A semiconductor element for macro and micro frequency tuning, and an antenna and a frequency tuning circuit having the semiconductor element, are provided. The semiconductor element includes first and second semiconductors which have a same polarity, a third semiconductor which has a polarity opposite to the polarity of the first... Agent: Sughrue Mion, PLLC

20080099882 - System and method for providing a nanoscale, highly selective, and thermally resilient carbon etch-stop: A method for forming an etch-stop layer and a resulting structure fabricated therefrom. The etch-stop layer is a silicon-germanium layer having a ratio of silicon to germanium of about 50:1 or less, a boron layer formed within the silicon-germanium layer where the boron layer has a full-width half-maximum (FWHM) thickness... Agent: Schneck & Schneck

20080099883 - Semiconductor storage device, semiconductor device, and manufacturing method therefor: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal... Agent: Young & Thompson

20080099884 - Staggered guard ring structure: Embodiments of the present invention provide staggered guard ring structures for stopping cracks from propagating during a dicing operation or by suffering mechanical stress after packaging. In one embodiment, a guard ring structure may comprise staggered metal bars, each of which extends into the ILD underneath it. In one embodiment,... Agent: SprinkleIPLaw Group

20080099886 - Semiconductor element, semiconductor device and mounting board: A semiconductor element capable of reducing noises of a circuit propagating to another circuit through a seal ring is provided. A semiconductor element includes, on a surface of a semiconductor substrate: a plurality of circuits; a ring-shaped seal ring surrounding the plurality of circuits; and wiring connecting between the seal... Agent: Rader Fishman & Grauer PLLC

20080099885 - Semiconductor package and methods of manufacturing the same: A semiconductor package includes a semiconductor chip having first and second pads, a first insulation layer pattern formed on the semiconductor chip and having first and second openings that expose the first and the second pads, respectively, a first conductive layer pattern elongated along the first insulation layer pattern from... Agent: Marger Johnson & Mccollom, P.C.

20080099887 - Multi-ground shielding semiconductor package, method of fabricating the package, and method of preventing noise using multi-ground shielding: Provided are a multi-ground shielding semiconductor package including analog and digital circuit blocks and capable of preventing a coupling problem between the analog and digital circuit blocks caused by high frequency noise. A method of fabricating the multi-ground shielding semiconductor package, and a method of preventing noise in the multi-ground... Agent: Marger Johnson & Mccollom, P.C.

20080099888 - Semiconductor device, method of manufacturing the same: A semiconductor device is disclosed that includes an interposer and a semiconductor chip. The interposer includes a Si substrate; multiple through vias provided through an insulating material in corresponding through holes passing through the Si substrate; a thin film capacitor provided on a first main surface of the Si substrate... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080099889 - Semiconductor device and method for manufacturing same: When a metal cap film is provided on an electric fuse, the break-ability of the electric fuse is reduced. A semiconductor device 1 includes interconnects 10, an electric fuse 20 and metal cap films 30. Both of the interconnects 10 and the electric fuse 20 are composed of Cu. The... Agent: Young & Thompson

20080099890 - Ball grid array package structure: A ball grid array package structure includes: a substrate having at least one chip bearing area on its upper surface and a plurality of electrical-connecting points on its lower surface; a plurality of chips are arranged on the chip bearing area and electrically connected with those electrical-connecting points; a plurality... Agent: Birch Stewart Kolasch & Birch

20080099891 - Semiconductor device and method of manufacturing the same: A semiconductor device including: a semiconductor element 1, a heat conductor 91 opposed to the main surface of the semiconductor element 1, and a sealing resin 6 for sealing at least a part of the semiconductor element 1 and a part of the heat conductor 91, the heat conductor 91... Agent: Steptoe & Johnson LLP

20080099892 - Stacked chip packaging with heat sink structure: A stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, in which the die pad is provided between the inner leads and is vertically distant from... Agent: Reed Smith LLP

20080099893 - Connecting a plurality of bond pads and/or inner leads with a single bond wire: An integrated circuit device comprising an integrated circuit die having a plurality of bond pads that are selectively connected to a plurality of inner leads of a leadframe. At least two bond pads are connected to at least one of the inner leads, and/or at least two inner leads are... Agent: Baker Botts, LLP

20080099894 - Semiconductor device and a method of manufacturing the same: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The... Agent: Miles & Stockbridge PC

20080099895 - Semiconductor package and method of forming wire loop of semiconductor package: Provided are a semiconductor package and a method of forming a wire loop of the semiconductor package. The semiconductor package includes: at least one semiconductor chip; a lead frame including a plurality of leads; and a plurality of wire loops, the wire loops connecting an electrode pad of the semiconductor... Agent: Drinker Biddle & Reath LLP Attn: Patent Docket Dept.

20080099896 - Stacked chip package structure with leadframe having inner leads with transfer pad: The present invention provides a stacked chip package structure with leadframe having inner leads with transfer pad, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the... Agent: Reed Smith LLP

20080099897 - Bondwire utilized for coulomb counting and safety circuits: A sense resistor and integrated circuit package combination is disclosed. A package lead frame is provided having a plurality of landing zones associated therewith and a die mounting area for mounting of a die thereon. The die has a plurality of bond pads associated therewith, with a first bond wire... Agent: Howison & Arnott, L.l.p

20080099898 - Die-up integrated circuit package with grounded stiffener: A printed circuit substrate is disposed on a bottom side of a stiffener. An IC die is disposed on a top side of the stiffener. The die is electrically connected onto the printed circuit substrate by wire bonding through an open slot in the stiffener. The die is not wire... Agent: Stephen B. Ackerman

20080099899 - Methods and apparatus for a quad flat no-lead (qfn) package: Methods and apparatus are provided for decreasing the size of Quad Flat No-Lead (QFN) packages (300, 400) down to chip-scale packages. Such QFN packages include a first semiconductor chip (310, 410), a plurality of recessed leads (306, 406, 408, 411) having mold lock features, and a mold material 340, 440... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080099901 - Package substrate with inserted discrete capacitors: A package substrate (16) for electrically connecting an integrated circuit (12) to a printed circuit board (14) includes a core (222c), a patterned conductive layer (220c), a plurality of spaced apart, discrete capacitors (230), and an insulating layer (222b). The patterned conductive layer (220c) is positioned on the core (222c).... Agent: Roeder & Broder LLP

20080099900 - Wafer-level fabrication of lidded chips with electrodeposited dielectric coating: A method is provided for fabricating a unit including a semiconductor element such as a sensor unit, e.g., for optical imaging. A semiconductor element has plurality of conductive features exposed at the front surface and semiconductive or conductive material exposed at least one of the front and rear surfaces. At... Agent: Tessera Lerner David Et Al.

20080099902 - Insertion-type semiconductor device and fabrication method thereof: The present invention provides an insertion-type semiconductor device and a fabrication method thereof, including the steps of: mounting a chip on a BGA substrate and performing a packaging molding process; providing an electrical connecting board formed with a plurality of electrical terminals thereon for allowing the packaged substrate to electrically... Agent: Edwards Angell Palmer & Dodge LLP

20080099903 - Stacked chip package, embedded chip package and fabricating method thereof: An embedded chip package includes a substrate, a semiconductor structure, an encapsulating material layer and a plurality of conductive vias. Herein the substrate includes at least a dielectric layer and at least a patterned circuit layer disposed on the dielectric layer. The semiconductor structure is disposed on the substrate and... Agent: Jianq Chyun Intellectual Property Office

20080099904 - Structure of package on package and method for fabricating the same: A structure of a package on package and a method for fabricating the same are provided. The structure of the package on package includes a first package, a second package and a plurality of pins. The first package includes a first substrate and a first chip disposed thereon. The second... Agent: Bacon & Thomas, PLLC

20080099905 - Method and apparatus of power ring positioning to minimize crosstalk: A method and/or an apparatus of power ring positioning to minimize crosstalk are disclosed. In one embodiment, a method includes generating an array of fingers between a power ring and a die, applying a signal wire between a bond pad of the die and a particular finger of the array... Agent: Lsi Corporation

20080099906 - Electronic apparatus with busbar assembly and electronic component mounted thereon by soldering: In an electronic apparatus, a busbar assembly is composed of busbars made of at least one previously selected metal material. Each of the busbars has one surface. A solder joint is made of an alloy of previously selected metal materials and placed on the one surface of at least one... Agent: Oliff & Berridge, PLC

20080099907 - Wafer-level fabrication of lidded chips with electrodeposited dielectric coating: A method is provided for fabricating a unit including a semiconductor element such as a sensor unit, e.g., for optical imaging. A semiconductor element has plurality of conductive features exposed at the front surface and semiconductive or conductive material exposed at at least one of the front and rear surfaces.... Agent: Tessera Lerner David Et Al.

20080099908 - Systems, devices, components and methods for hermetically sealing electronic modules and packages: Disclosed are various embodiments of systems, devices and methods for forming an hermetic seal between a lid and a submount for an electronics module or package. At least one thieving pad is connected to a metallized ring formed about or near the circumference of an upper surface of the submount.... Agent: Kathy Manke Avago Technologies Limited

20080099909 - Wafer stacked package having vertical heat emission path and method of fabricating the same: A wafer stacked semiconductor package (WSP) having a vertical heat emission path and a method of fabricating the same are provided. The WSP comprises a substrate on which semiconductor chips are mounted; a plurality of semiconductor chips stacked vertically on the substrate; a cooling through-hole formed vertically in the plurality... Agent: Marger Johnson & Mccollom, P.C.

20080099910 - Flip-chip semiconductor package with encapsulant retaining structure and strip: An integrated circuit package includes an encapsulant retention structure located adjacent to a die on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the die. The retention structure placed on the substrate may also serve as a substrate stiffener... Agent: Advanced Micro Devices, Inc. C/o Vedder Price P.C.

20080099911 - Multilayer wiring substrate mounted with electronic component and method for manufacturing the same: A multilayer wiring substrate mounted with an electronic component includes an electronic component, a core material layer having a first opening for accommodating the electronic component, a resin layer which is formed on one surface of the core material layer and which has a second opening greater than the first... Agent: Drinker Biddle & Reath (dc)

20080099913 - Metallization layer stack without a terminal aluminum metal layer: By directly forming an underbump metallization layer on a contact region of the last metallization layer, the formation of any other terminal metals, such as aluminum and corresponding adhesion/barrier layers, may be avoided. Consequently, the thermal and electrical behavior of the resulting bump structure may be improved, while process complexity... Agent: Williams, Morgan & Amerson

20080099914 - Mounting structure, electro-optical device, electronic apparatus, and method of producing the mounting structure: A semiconductor device includes a bump electrode including a bump made of resin, a base layer disposed on the bump, and a conductive surface layer disposed on the base layer. The base layer has ductility lower than that of the conductive surface layer and includes base regions which are spaced... Agent: Harness, Dickey & Pierce, P.L.C

20080099912 - Packaging with base layers comprising alloy 42: A semiconductor packaging structure is provided. The structure includes a base layer comprising alloy 42; die attached on a first side of the base layer; and an interconnect structure on the die, wherein the interconnect structure comprises vias and conductive lines connected to the die.... Agent: Slater & Matsil, L.L.P.

20080099915 - Semiconductor device and a method of manufacturing the same: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The... Agent: Miles & Stockbridge PC

20080099916 - Bonding structure and method of fabricating the same: A bonding structure including a first substrate, a second substrate, a non-conductive adhesive layer, and ball-shaped spacers is provided. The first substrate has first bonding pads. The second substrate is disposed on one side of the first substrate, and includes second bonding pads and compliant bumps disposed on the second... Agent: Jianq Chyun Intellectual Property Office

20080099917 - Packaged microelectronic devices and methods for packaging microelectronic devices: Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second side opposite the first side includes forming a recess in a substrate,... Agent: Perkins Coie LLP Patent-sea

20080099918 - Semiconductor device including a porous low-k material layer stack with reduced uv sensitivity: By forming a cap layer on a dielectric barrier layer of a low-k dielectric material stack, the interaction of UV radiation during the generation of pores in the low-k dielectric material may be significantly reduced. In some illustrative embodiments, the cap layer may comprise titanium oxide and/or vanadium oxide which... Agent: Williams, Morgan & Amerson

20080099920 - Multi-stage curing of low k nano-porous films: Embodiments in accordance with the present invention relate to multi-stage curing processes for chemical vapor deposited low K materials. In certain embodiments, a combination of electron beam irradiation and thermal exposure steps may be employed to control selective outgassing of porogens incorporated into the film, resulting in the formation of... Agent: Townsend And Townsend And Crew LLP / Amat

20080099921 - Semiconductor device and method of fabricating the same: A semiconductor device includes a semiconductor substrate including an impurity diffusion region within an upper surface thereof, an insulating film formed on an upper surface of the impurity diffusion region, and a contact plug formed in the insulating film so that the contact plug contacts the impurity diffusion region. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080099919 - Semiconductor device including copper interconnect and method for manufacturing the same: Semiconductor device includes a semiconductor element, a copper interconnect electrically connected to the semiconductor element, a barrier layer containing metal capable of suppressing diffusion and oxidation of copper and continuously covers top and side surfaces of the copper interconnect, and an adhesive layer formed on a top surface of the... Agent: Cantor Colburn, LLP

20080099922 - Circuit device and manufacturing method thereof: A first insulating layer is formed on a front surface of a rectangular circuit board. Conductive patterns having a predetermined shape are formed on a front surface of the first insulating layer. A semiconductor element and a chip element are electrically connected to the conductive patterns by use of solder... Agent: Fish & Richardson P.C.

20080099923 - Dual damascene integration of ultra low dielectric constant porous materials: A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion... Agent: Paul D. Greeley Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20080099924 - Silicon wafer having through-wafer vias with a predetermined geometric shape: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. A trench of a predetermined geometric shape is formed in the semiconductor substrate at the first main surface. The trench extends to a first depth position in the... Agent: Panitch Schwarze Belisario & Nadel LLP

20080099927 - semiconductor package manufacturing method and semiconductor apparatus: Provided is a semiconductor package manufacturing method. The method comprises forming a metal circuit pattern on a substrate; connecting an integrated circuit unit to the metal circuit pattern; forming a resin on the substrate, the metal circuit pattern and the integrated circuit unit; and removing the substrate.... Agent: George C. Beck Foley & Lardner LLP, Washington Harbour

20080099925 - Solder pillar bumping and a method of making the same: A method of forming flip chip bumps includes forming a plurality of metallization pads on a die. In another step, a structured layer having pores is formed on the die and metallization pads where the pads on the die are exposed through the pores. In yet another step, the die... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080099926 - Semiconductor device: Provided is a semiconductor device that can reduce the resistance in a horizontal direction of a substrate. A current path in a horizontal direction of a substrate is formed in a direction along a short side of the substrate (chip). For example, adopted is a layout in which an element... Agent: Morrison & Foerster LLP

20080099928 - Low fabrication cost, high performance, high reliability chip scale package: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is... Agent: Mou-shiung Lin

20080099929 - Mixed-scale electronic interfaces: Certain embodiments of the present invention are directed to a method of fabricating a mixed-scale electronic interface. A substrate is provided with a first set of conductive elements. A first layer of nanowires may be formed over the first set of conductive elements. A number of channels may be formed,... Agent: Hewlett Packard Company

20080099930 - Semiconductor device: The present invention provides a semiconductor device which is applied to, for example, a WCSP (Wafer Level Chip Size Package) and comprises a semiconductor chip having a high-frequency circuit block, a plurality of electrode pads formed on the semiconductor chip, posts disposed between the high-frequency circuit block and the electrode... Agent: Rabin & Berdo, PC