Active solid-state devices (e.g., transistors, solid-state diodes) inventions

20090278107 - Phase change memory device: The phase change memory device includes a first electrode and a second electrode and a first phase change material pattern and a second phase change material pattern interposed between the first electrode and the second electrode, wherein the first and second phase change material patterns have respectively different electrical characteristics.... Agent: Lee & Morse, P.C.

20090278109 - Confinement techniques for non-volatile resistive-switching memories: Confinment techniques for non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. A resistive switching memory element described herein includes a first electrode adjacent to an interlayer dielectric, a spacer over at... Agent: Legal Department

20090278110 - Non-volatile resistive-switching memories formed using anodization: Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide.... Agent: Legal Department

20090278108 - Phase change memory device having phase change material layer containing phase change nano particles and method of fabricating the same: A phase change memory device including a phase change material layer having phase change nano particles and a method of fabricating the same are provided. The phase change memory device may include a first electrode and a second electrode facing each other, a phase change material layer containing phase change... Agent: Harness, Dickey & Pierce, P.L.C

20090278111 - Resistive changing device: A device that incorporates teachings of the present disclosure may include, for example, a memory array having a first array of nanotubes, a second array of nanotubes, and a resistive change material located between the first and second array of nanotubes. Other embodiments are disclosed.... Agent: Akerman Senterfitt

20090278112 - Methods for etching carbon nano-tube films for use in non-volatile memories: Memory cells, and methods of forming such memory cells are provided that include a steering element coupled to a carbon-based reversible resistivity-switching material. In particular embodiments, methods in accordance with this invention etch a carbon nano-tube (“CNT”) film formed over a substrate, the methods including coating the substrate with a... Agent: Dugan & Dugan, PC

20090278113 - Nitride semiconductor light emitting device: There is provided a nitride semiconductor light emitting device. A nitride semiconductor light emitting device according to an aspect of the invention may include: an n-type nitride semiconductor layer provided on a substrate; an active layer provided on the n-type nitride semiconductor layer, and including quantum barrier layers and quantum... Agent: Mcdermott Will & Emery LLP

20090278114 - Control of carbon nanotube diameter using cvd or pecvd growth: The diameter of carbon nanotubes grown by chemical vapor deposition is controlled independent of the catalyst size by controlling the residence time of reactive gases in the reactor.... Agent: Connolly Bove Lodge & Hutz LLP

20090278118 - Benzofluoranthene compound and organic light-emitting device using the compound: e

20090278115 - Nitrogen-containing heterocyclic derivative and organic electroluminescence element using the same: A novel nitrogen-containing heterocyclic derivative having a specific structure and an organic electroluminescence device comprising an anode, a cathode and an organic thin film layer which comprises a single layer or a plurality of layers comprising at least a light emitting layer and is disposed between the anode and the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090278119 - Oled display with extended lifetime: The present invention relates to an organic light-emitting diode which has a light-emitting layer C which comprises at least one hole-conducting material CA and at least one phosphorescence emitter CB, to mixtures comprising at least one carbene complex in combination with at least one hole-conducting material or in combination with... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090278117 - Organic thin film transistor, method of manufacturing the same, and biosensor using the transistor: An organic thin film transistor (OTFT), a method of manufacturing the same, and a biosensor using the OTFT are provided. The OTFT includes a gate electrode, a gate insulating layer, source and drain electrodes, and an organic semiconductor layer disposed on a substrate and further includes an interface layer formed... Agent: Rabin & Berdo, PC

20090278116 - Transistor, organic semiconductor device, and method for manufacture of the transistor or device: The invention provides a process for production of a transistor and an organic semiconductor element which allows satisfactory formation of active layers on desired surfaces, even if the active layers are organic semiconductor compound-containing active layers imparted with prescribed properties beforehand. A preferred mode of the process for production of... Agent: Sughrue Mion, PLLC

20090278122 - Amorphous oxide and thin film transistor: The present invention relates to an amorphous oxide and a thin film transistor using the amorphous oxide. In particular, the present invention provides an amorphous oxide having an electron carrier concentration less than 1018/cm3, and a thin film transistor using such an amorphous oxide. In a thin film transistor having... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090278121 - System for displaying images and fabrication method thereof: A system for displaying images includes a thin film transistor array substrate including a substrate with thin film transistors array and at least one light-sensing element containing an amorphous silicon layer formed on the substrate, wherein the light-sensing element has a current flow direction perpendicular to the substrate.... Agent: Liu & Liu

20090278120 - Thin film transistor: There is provided a thin film transistor (TFT) capable of improving electron mobility and minimizing the occurrence of hysteresis due to traps. The TFT includes a channel layer and a gate insulating layer, wherein the channel layer is made of an oxide semiconductor. In the TFT, the gate insulating layer... Agent: Fenwick & West LLP

20090278124 - Scribe based bond pads for integrated circuits: An apparatus including a semiconductor substrate is disclosed. A first semiconductor die is disposed on the semiconductor substrate. A first bond out pad is disposed on the semiconductor substrate adjacent to the first semiconductor die. A first sawn semiconductor die is disposed on the semiconductor substrate adjacent to the first... Agent: Schwegman, Lundberg & Woessner / Atmel

20090278123 - Testing wiring structure and method for forming the same: The invention provides a testing wiring structure of a thin film transistor (TFT) motherboard for applying signals to a plurality of signal lines in a pixel region on the motherboard and a method for forming the same. The testing wiring structure comprises a gate layer metallic testing wiring and a... Agent: Ladas & Parry LLP

20090278125 - Crystalline semiconductor films, growth of such films and devices including such films: The present invention describes an approach to grow highly crystalline semiconductor films, multilayers of semiconductor thin films on foreign substrate such as glass, quartz. Specifically, The film were grown by first forming crystalline seeds, and transferring the seeds onto the substrate, and growing continuous semiconductor film through epitaxial growth... Agent: Xiangfeng Duan

20090278126 - Metal line substrate, thin film transistor substrate and method of forming the same: A metal line substrate and a method of fabricating thereof, the metal line substrate including an insulating layer and a capping layer disposed on an insulating substrate, a trench defined by the insulating layer and the capping layer disposed on the insulating substrate, a seed layer pattern disposed on the... Agent: Cantor Colburn, LLP

20090278130 - Array substrate, liquid crystal display panel having the same and liquid crystal display device having the same: In an array substrate, an LCD panel having the same and an LCD device having the same, the array substrate may include an insulating substrate, a switching element (e.g., a transistor such as a TFT), a main pixel portion, a coupling capacitor and a sub-pixel portion. The switching element may... Agent: Haynes And Boone, LLPIPSection

20090278129 - Liquid crystal display device and method of fabricating the same: A liquid crystal display device includes a gate line and a data line crossing each other to define a pixel region on a substrate, a gate electrode connected to the gate line, a gate insulating layer on the gate electrode, an active layer on the gate insulating layer, source and... Agent: Holland & Knight LLP

20090278128 - Thin film transistor array panel and manufacturing method of the same: A thin film transistor array panel includes a substrate; a gate electrode formed on the substrate; a data line formed on the substrate; a gate insulating layer formed on the data line and the gate electrode, and having a first contact hole exposing the gate electrode, and a second contact... Agent: Cantor Colburn, LLP

20090278127 - Thin-film transistor and method of manufacturing the same: In one embodiment, a thin-film transistor (TFT) includes a gate electrode, a semiconductor pattern, first and second electrodes and a protective layer. The semiconductor pattern is formed on the gate electrode, and includes a first semiconductor layer deposited at a first deposition speed and a second semiconductor layer deposited at... Agent: Haynes And Boone, LLPIPSection

20090278132 - Array substrate of liquid crystal display device having thin film transistor on color filter and method of fabricating the same: An array substrate of a liquid crystal display device having a color filter on a gate metal layer, and a data metal layer formed on the color filter. First a gate insulating layer is formed on the gate metal layer to protect and a second gate insulating layer is formed... Agent: F. Chau & Associates, LLC

20090278134 - Semiconductor device and method of manufacturing the semiconductor device: In a semiconductor device according to the present invention, an insulator layer on a substrate is provided with a trench. A gate electrode is formed in the trench so that an upper surface of the gate electrode is approximately flush with an upper surface of the insulator layer. On the... Agent: Birch Stewart Kolasch & Birch

20090278131 - Thin film transistor array arrangement, organic light emitting display device having the same, and manufacturing method thereof: A thin film transistor (TFT) array arrangement, an organic light emitting display device that includes the TFT array arrangement and a method of making the TFT array arrangement and the organic light emitting display device. The method seeks to reduce the number of masks used in the making of the... Agent: Robert E. Bushnell & Law Firm

20090278133 - Thin film transistor array panel and method for manufacturing the same, and liquid crystal display: A thin film transistor array panel includes a substrate, a first thin film transistor formed on the substrate, a color filter formed on the first thin film transistor and having a through hole, a capping layer formed on the color filter and having an opening, and a pixel electrode formed... Agent: F. Chau & Associates, LLC

20090278135 - Thin film transistor, method of manufacturing the same, and display device using the same: Disclosed herein is a thin film transistor, including: a gate electrode; a crystallized semiconductor layer formed through a gate insulating film on the gate electrode; and a drain electrode and a source electrode provided on both end sides of the crystallized semiconductor layer, respectively, and provided through impurity doped layers... Agent: Sonnenschein Nath & Rosenthal LLP

20090278136 - Process for growth of low dislocation density gan: High quality free standing GaN is obtained using a new modification of the Epitaxial Lateral Overgrowth technology in which 3D islands or features are created only by tuning the growth parameters. Smoothing these islands (2D growth) is achieved thereafter by setting growth conditions producing enhanced lateral growth. The repetition of... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090278137 - Semiconductor devices with non-punch-through semiconductor channels having enhanced conduction and methods of making: Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs),... Agent: Morris Manning Martin LLP

20090278138 - Laminated structure and image display device: A laminated structure includes a wettability variable layer formed on a substrate, including a material whose critical surface tension varies by receiving energy so that high and low surface energy regions are formed; a conductive layer formed in one of the high surface energy regions; and an insulating layer formed... Agent: Cooper & Dunham, LLP

20090278139 - Light-emitting diode package assembly: An electrical device containing multiple light emitting diode (LED) dies each having respective first and second connectors suitable to receive current through the LED die. A common base layer of a first electrically conductive material has cavities into which at least one LED die is mounted with its second connector... Agent: The Tpl Group

20090278140 - Manufacturing method of semiconductor device: A manufacturing method of a semiconductor device comprises the steps of: providing a substrate; forming a plurality of grooves on the substrate by photolithograph etching or laser engraving, wherein the plurality of grooves divides a surface of the substrate into a plurality of mesas and the substrate is a patterned... Agent: Wpat, PC Intellectual Property Attorneys

20090278141 - Light-emitting devices and displays with improved performance: Light-emitting devices and displays with improved performance are disclosed. A light-emitting device includes an emissive material disposed between a first electrode, and a second electrode. Various embodiments include a device having a peak external quantum efficiency of at least about 2.2%; a device that emits light having a CIE color... Agent: Qd Vision, Inc.

20090278142 - Light-emitting diode display and method for manufacturing the same: A method for manufacturing a light-emitting diode display is provided. The method includes pre-fixing first, second, and third light-emitting diodes on a light emitting unit production substrate to produce light-emitting units each including first, second, and third light-emitting diodes, first electrodes of the first, second, and third light-emitting diodes being... Agent: K&l Gates LLP

20090278143 - Semiconductor light emitting device: A plurality of transistors are formed on a substrate in a plurality of columns. Each transistor has a first conductivity type region and second conductivity type regions provided on both sides thereof in a column direction, and has an active layer on the side of each second conductivity type region... Agent: Rabin & Berdo, PC

20090278155 - Backlight device for liquid crystal display including a plurality of light emitting diodes within their own concaves aligned in a straight line within a larger concave: A semiconductor light emitting device of the present invention includes a plurality of light emitting elements, a package body for storing the light emitting elements, wiring patterns being electrically connected to the light emitting elements, and Au wires for electrically connecting the light emitting elements and the wiring patterns, the... Agent: Morrison & Foerster LLP

20090278154 - Led module and method of manufacturing the same: Provided are a light emitting diode (LED) module and a method of manufacturing the same. The LED module may include a package housing including an inner space, a light-emitting chip in the inner space of the package housing, a phosphor layer including a fluorescent material and converting light emitted from... Agent: Harness, Dickey & Pierce, P.L.C

20090278153 - Light emitting device: Provided is a light emitting device. The light emitting device comprises a package body, a plurality of electrodes, a light emitting diode, and a lens. The package body comprises a trench. The plurality of electrodes is disposed on and/or in the package body. The light emitting diode is disposed on... Agent: Birch Stewart Kolasch & Birch

20090278149 - Light emitting diode: An LED (20) includes a base (24), a chip (21) and an encapsulation (22) made of a transparent material. The base has a concave depression (240). The chip is mounted on a bottom of the concave depression. The first encapsulation is received in the depression for sealing the chip. The... Agent: PCe Industry, Inc. Att. Steven Reiss

20090278152 - Light emitting diode and package method thereof: A light emitting diode comprises a sheet-like package body, a barricade, a light emitting diode die, and fluorescent filler. The sheet-like package body has a die-bonding region. The barricade is a transparent wall that is disposed on the die-bonding region, and is integrated with the sheet-like package body or is... Agent: Wpat, PC Intellectual Property Attorneys

20090278151 - Light emitting diode packages, light emitting diode systems and methods of manufacturing the same: In a method of forming an LED semiconductor device, and in an LED semiconductor device, an LED is provided on a substrate. A first encapsulant material layer is provided on the LED, and the first encapsulant material layer is firstly annealed. A luminescence conversion material layer is provided on the... Agent: Mills & Onello LLP

20090278148 - Light-emitting diode and method for fabrication thereof: A transparent-substrate light-emitting diode (10) has a light-emitting layer (133) made of a compound semiconductor, wherein the area (A) of a light-extracting surface having formed thereon a first electrode (15) and a second electrode (16) differing in polarity from the first electrode (15), the area (B) of a light-emitting layer... Agent: Sughrue Mion, PLLC

20090278150 - Method for forming metal electrode, method for manufacturing semiconductor light emitting elements and nitride based compound semiconductor light emitting elements: A method for forming a metal electrode and a method for manufacturing semiconductor light emitting elements include providing a substrate having a semiconductor layer formed thereon; forming a bonding metal layer and a reflective metal layer on the semiconductor layer; and forming a metal electrode by layer inversion of the... Agent: H.c. Park & Associates, PLC

20090278156 - Molded chip fabrication method and apparatus: A light emitting diode (LED) is disclosed comprising a plurality of semiconductor layers with a first contact on the bottom surface of the semiconductor layers and a second contact on the top surface of the semiconductor layer. A coating is included that comprises a cured binder and a conversion material... Agent: Koppel, Patrick, Heybl & Dawson

20090278144 - Nitride semiconductor light emitting device: There is provided a nitride semiconductor light emitting device having a light reflection layer capable of preventing reflectivity from lowering and luminance from lowering due to deterioration of quality of an active layer. A nitride semiconductor laser includes at least a light emitting layer forming portion (3) provided on a... Agent: Rabin & Berdo, PC

20090278146 - Phosphor illumination optics for led light sources: Devices and methods for collecting and distributing light from a light emitting diode (LED) emitter onto a phosphor layer to produce substantially white light are provided. The devices may include a reflective cavity with a reflective material, surrounding the reflective cavity, with a reflective side of the reflective material facing... Agent: Oliff & Berridge, PLC

20090278145 - Semiconductor light emitting device and method for manufacturing the same: A semiconductor light emitting device 1 includes a supporting substrate 2 and a semiconductor stack 6 including an MQW active layer 13 emitting light and an n-GaN layer 14 at the top. In the upper surface of the n-GaN layer 14 of the semiconductor attack 6, a plurality of conical... Agent: Rabin & Berdo, PC

20090278147 - Semiconductor light-emitting device: Disclosed is a semiconductor light-emitting device having improved light-extraction efficiency. Specifically disclosed is a semiconductor light-emitting device (1) comprising a semiconductor light-emitting element (10), a phosphor layer (11) which is so formed as to cover at least a part of the semiconductor light-emitting element (10), and an outer layer (12)... Agent: Hamre, Schumann, Mueller & Larson P.C.

20090278158 - Gallium nitride based compound semiconductor light-emitting device and method of manufacturing the same: The present invention provides a gallium nitride based compound semiconductor light-emitting device having high light emission efficiency and a low driving voltage Vf. The gallium nitride based compound semiconductor light-emitting device includes a p-type semiconductor layer, and a transparent conductive oxide film that includes dopants and is formed on the... Agent: Sughrue Mion, PLLC

20090278162 - Low temperature co-fired ceramic (ltcc) tape compositions, light-emitting diode (led) modules, lighting devices and methods of forming thereof: The present invention provides LTCC (low temperature co-fired ceramic) tape compositions and demonstrates the use of said LTCC tape(s) in the formation of Light-Emitting Diode (LED) chip carriers and modules for various lighting applications. The present invention also provides for the use of (LTCC) tape and LED modules in the... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20090278157 - Method for the production of a semiconductor component comprising a planar contact, and semiconductor component: In a method for producing a semiconductor component, in particular a semiconductor structure having a surface structure or topography which is produced by means of electronic components (2) on a substrate (1), at least one electronic component (2) is applied to a substrate (1), and an isolation layer (3) is... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090278161 - Method of fabricating vertical structure leds: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate,... Agent: Mckenna Long & Aldridge LLP

20090278160 - Radiation emitting semiconductor device: The present invention provides a radiation emitting semiconductor device, which comprises an active layer for emitting radiation, a p-type conductive layer, a transparent conductive layer, and a non-p-type ohmic contact layer. The p-type conductive layer is formed on the active layer. The transparent conductive layer is formed on the p-type... Agent: Wpat, PC Intellectual Property Attorneys

20090278159 - Semiconductor chip package structure without substrates for achieving face-up electrical connection without using a wire-bonding process and method for making the same: A semiconductor chip package structure without substrates for achieving face-up electrical connection without using a wire-bonding process includes a package unit, a semiconductor chip, a first insulative unit, a first conductive unit, a second conductive unit, and a second insulative unit. The package unit has a central receiving groove for... Agent: Rosenberg, Klein & Lee

20090278163 - Light-emitting device and manufacturing method of the same: A light-emitting device (1) is provided having a current blocking layer (9) of buried structure, a portion of the current blocking layer (9) having an oxygen concentration higher than that of a light-emitting layer, the current blocking layer being of a thickness of not less than 5 nm and not... Agent: Masao Yoshimura, Chen Yoshimura LLP

20090278164 - Gan-based semiconductor light-emitting device and method for the fabrication thereof: A GaN-based semiconductor light-emitting device 1 includes a stacked body 10A having the component layers 12 that include an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer each formed of a GaN-based semiconductor, sequentially stacked and provided as an uppermost layer with a first bonding layer 14... Agent: Sughrue Mion, PLLC

20090278165 - Light emitting device and fabrication method therefor: A light emitting device (LED) structure formed on a Group IV-based semiconductor substrate is provided. The LED structure includes a Group IV-based substrate, an AlN nucleation layer formed on the Group IV-based substrate, a GaN epitaxial layer formed on the AlN nucleation layer, a distributed Bragg reflector (DBR) multi-layer structure... Agent: Haverstock & Owens LLP

20090278166 - Semiconductor device: A semiconductor device in which both an IGBT element region and a diode element region exist in the same semiconductor substrate includes a low lifetime region, which is formed in at least a part of a drift layer within the diode element region and shortens the lifetime of holes. A... Agent: Kenyon & Kenyon LLP

20090278167 - Semiconductor device including a plurality of chips and method of manufacturing semiconductor device: A semiconductor device includes a first chip and a second chip. The first chip includes a first conductivity type channel power MOSFET. The second chip includes a second conductivity type channel power MOSFET. The first chip and the second chip are integrated in such a manner that a second-surface drain... Agent: Posz Law Group, PLC

20090278168 - Structure of silicon controlled rectifier: A silicon controlled rectifier structure is provided in a substrate having a first conductive type. A well region formed within the substrate has a second conductive type. A first dopant region formed within the substrate and the well region has the first conductive type. A second dopant region formed within... Agent: J C Patents

20090278169 - Semiconductor device and method of manufacturing the same: A semiconductor device includes: a semiconductor base; a hetero semiconductor region which is in contact with the semiconductor base and which has a band gap different from that of the semiconductor base; a first electrode connected to the hetero semiconductor region; and a second electrode forming an ohmic contact to... Agent: Foley And Lardner LLP Suite 500

20090278170 - Semiconductor device and manufacturing method thereof: A method for manufacturing a semiconductor device includes providing a substrate having at least a gate structure formed thereon, forming LDDs in the substrate respectively at two side of the gate structure and a spacer at sidewalls of the gate structure, forming a source/drain in the substrate at two side... Agent: North America Intellectual Property Corporation

20090278172 - Gan based semiconductor element: The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron... Agent: Kubotera & Associates, LLC

20090278171 - High linearity doped-channel fet: A high linearity doped-channel FET, comprises a substrate, a buffer layer, a channel layer and a cap layer stacked downwardly thereon. The cap layer has a source region, a drain region with a distance apart from the source region and a gate region formed by removing part of the cap... Agent: Bacon & Thomas, PLLC

20090278173 - Memory device interconnects and method of manufacturing: An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090278174 - Pixel structure of solid-state image sensor: A pixel structure of a solid-state image sensor in which residual electrons in a photodiode is reduced and which has a first-stage gate that is arranged adjacent to the photodiode and controls read-out of electrons generated in the photodiode, a second-stage gate that is adjacent to the first-stage gate on... Agent: Birch Stewart Kolasch & Birch

20090278175 - Method for forming extended gate field effect transistor (egfet) based sensor and the sensor therefrom: The invention provides a method for forming an extended gate field effect transistor (EGFET) based sensor, including: (a) providing a substrate; (b) forming a sensing film including titanium dioxide, ruthenium doped titanium dioxide or ruthenium oxide on the substrate; and (c) forming a conductive wire extended from the sensing film... Agent: Quintero Law Office, PC

20090278176 - High current density power field effect transistor: An ultra-short channel hybrid power field effect transistor (FET) device lets current flow from bulk silicon without npn parasitic. This device does not have body but still have body diode with low forward voltage at high current rating. The device includes a JFET component, a first accumulation MOSFET disposed adjacent... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20090278177 - Semiconductor devices with non-punch-through semiconductor channels having enhanced conduction and methods of making: Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs),... Agent: Morris Manning Martin LLP

20090278179 - Chip scale surface mount package for semiconductor device and process of fabricating the same: A semiconductor package has contacts on both sides of the dice on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice expose the metal plate without extending through the metal plate. A metal layer may be formed on... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20090278178 - Semiconductor device and method for fabricating the same: Disclosed is a semiconductor device which includes a MIS FET on a surface of a substrate, an insulating film on the substrate to cover the MIS FET, an opening that gets to an impurity diffusing region formed in the insulating film, another opening that gets to a gate electrode or... Agent: Nec Corporation Of America

20090278180 - Cmos image sensor with asymmetric well structure of source follower: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the... Agent: Turocy & Watson, LLP

20090278181 - Solid-state image sensor and manufacturing method thereof: A solid-state image sensor includes: a trench isolation region; a photodiode region for converting incident light to signal charges and accumulating the signal charges therein; a floating diffusion region for accumulating the signal charges of the photodiode region; a gate electrode formed over the element formation region located between the... Agent: Mcdermott Will & Emery LLP

20090278182 - Spin injector: A spin injector for use in a microelectronic device such as a field effect transistor (FET) is disclosed. The spin injector includes an array of ferromagnetic elements disposed within a semiconductor. The ferromagnetic elements within the array are arranged and spaced with respect to one another in a close arrangement... Agent: VistaIPLaw Group LLP

20090278183 - Semiconductor device with channel of fin structure and method for manufacturing the same: Provided are a semiconductor device with a channel of a FIN structure and a method for manufacturing the same. In the method, a device isolation layer defining an active region is formed on a semiconductor substrate. A recess trench with a first width is formed in the active region, and... Agent: Marshall, Gerstein & Borun LLP

20090278184 - Nonvolatile semiconductor memory device in which decrease in coupling ratio of memory cells is suppressed: A first insulation film is formed on a semiconductor substrate. A first gate electrode is formed on the first insulation film. A second insulation film is formed on an upper surface and a side surface of the first gate electrode. A second gate electrode is formed on the second insulation... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090278185 - Device structures for a memory cell of a non-volatile random access memory and design structures for a non-volatile random access memory: Device and design structures for memory cells in a non-volatile random access memory (NVRAM). The device structure includes a semiconductor body in direct contact with the insulating layer, a control gate electrode, and a floating gate electrode in direct contact with the insulating layer. The semiconductor body includes a source,... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090278186 - Double gate transistor and method of manufacturing same: A double gate transistor on a semiconductor substrate (2) includes a first diffusion region (S2), a second diffusion region (S3), and a double gate (FG, CG). The first and second diffusion regions (S2, S3) are arranged in the substrate spaced by a channel region (CR). The double gate includes a... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090278188 - Non-volatile semiconductor memory device: To reduce the writing and erasing voltages of a memory transistor without increasing the area of a memory cell, and to reduce the area of a memory cell without increasing the writing and erasing voltages. The memory cell includes a memory transistor having a first island-shaped semiconductor region, a floating... Agent: Nixon Peabody, LLP

20090278190 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090278191 - Nonvolatile semiconductor memory device in which decrease in coupling ratio of memory cells is suppressed: A first insulation film is formed on a semiconductor substrate. A first gate electrode is formed on the first insulation film. A second insulation film is formed on an upper surface and a side surface of the first gate electrode. A second gate electrode is formed on the second insulation... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090278187 - Semiconductor device and manufacturing method of semiconductor device: A semiconductor device of an aspect of the present invention includes a semiconductor substrate, two diffusion layers provided in the semiconductor substrate, a gate insulating film provided on a channel region between the two diffusion layers, and a gate electrode which is composed of a stack of a plurality of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090278189 - Semiconductor device with resistor and method of fabricating same: A semiconductor device includes a cell array region disposed on a semiconductor substrate and comprising a first cell gate pattern, a cell semiconductor pattern disposed on the first cell gate pattern, and a second cell gate pattern disposed on the cell semiconductor pattern. The semiconductor device also includes a peripheral... Agent: Volentine & Whitt PLLC

20090278194 - Capacitorless one-transistor semiconductor memory device having improved data retention abilities and operation characteristics: A capacitorless one transistor (1T) semiconductor device whose data storage abilities are increased and leakage current is reduced is provided. The capacitor-less 1T semiconductor device includes a buried insulating layer formed on a substrate, an active region formed on the buried insulating layer and including a source region, a drain... Agent: Lee & Morse, P.C.

20090278193 - Nonvolatile semiconductor memory device and method of manufacturing the same: A nonvolatile semiconductor memory device includes a first stack unit with a first selection transistor and a second selection transistor formed on a semiconductor substrate and a second stack unit with first insulating layers and first conductive layers stacked alternately on the upper surface of the first stack unit. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090278192 - Semiconductor device: A semiconductor device includes a tunnel insulation layer pattern, a charge trapping layer pattern, a blocking layer pattern and a gate structure. The tunnel insulation layer pattern is formed on a substrate. The charge trapping layer pattern is formed on the tunnel insulation layer pattern. The blocking layer pattern is... Agent: Volentine & Whitt PLLC

20090278195 - Semiconductor memory device provided with stacked layer gate including charge accumulation layer and control gate, and manufacturing method thereof: A semiconductor memory device includes a memory cell transistor and a first MOS transistor. The memory cell transistor includes a first insulating film, a second insulating film, a control gate electrode, and a first diffusion layer. The first insulating film formed on the first active region. The second insulating film... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090278196 - Finfets having dielectric punch-through stoppers: A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate... Agent: Slater & Matsil, L.L.P.

20090278198 - Deep source electrode mosfet: A power semiconductor device that includes a plurality of source trenches that extend to a depth below the gate electrodes and a termination region that includes a termination trench that is as deep as the source trenches.... Agent: Farjami & Farjami LLP

20090278197 - Mis field effect transistor and method for manufacturing the same: The MIS field-effect transistor includes: a substrate; a nitride semiconductor multilayer structure portion formed on the substrate, including a first group III-V nitride semiconductor layer of a first conductivity type, a second group III-V nitride semiconductor layer of a second conductivity type stacked thereon and a third group III-V nitride... Agent: Rabin & Berdo, PC

20090278199 - Method for preventing gate oxide damage of a trench mosfet during wafer processing while adding an esd protection module atop: e

20090278200 - Transistor, semiconductor device and manufacturing method thereof: An ON resistance of a trench gate type transistor and a withstand voltage of a planar type transistor are optimized at the same time. Each of first and second regions of a semiconductor layer is formed by epitaxial growth on each of first and second regions of a semiconductor substrate,... Agent: Morrison & Foerster LLP

20090278201 - Enhanced stress-retention silicon-on-insulator devices and methods of fabricating enhanced stress retention silicon-on-insulator devices: Field effect transistor and methods of fabricating field effect transistors. The field effect transistors includes: a semiconductor substrate; a silicon oxide layer on the substrate; a stiffening layer on the silicon oxide layer; a single crystal silicon layer on the stiffening layer; a source and a drain on opposite sides... Agent: Schmeiser, Olsen & Watts

20090278202 - Soi device with improved storage capacity and method for manufacturing the s: An SOI device includes an SOI substrate composed of a stack structure of a silicon substrate, a buried oxide layer, and a silicon layer. Grooves are defined in the silicon layer each exposing the buried oxide layer. A barrier layer is formed on the lower portion of the sidewall of... Agent: Ladas & Parry LLP

20090278203 - Semiconductor device and manufacturing method thereof: It is an object to reduce the effect of a characteristic of the edge portion of a channel forming region in a semiconductor film, on a transistor characteristic. An island-like semiconductor film is formed over a substrate, and a conductive film forming a gate electrode provided over the island-like semiconductor... Agent: Eric Robinson

20090278204 - Semiconductor device: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and... Agent: Miles & Stockbridge PC

20090278205 - High voltage bicmos device and method for manufacturing the same: A high voltage BICMOS device and a method for manufacturing the same, which may improve the reliability of the device by securing a distance between adjacent DUF regions, are provided. The high voltage BICMOS device includes: a reverse diffusion under field (DUF) region formed by patterning a predetermined region of... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090278206 - High-frequency switching transistor and high-frequency circuit: A switching transistor includes a substrate having a substrate dopant concentration and a barrier region bordering on the substrate, having a first conductivity type and having a barrier region dopant concentration that is higher than the substrate dopant concentration. A source region is embedded in the barrier region, and has... Agent: Maginot, Moor & Beck

20090278207 - Electromigration-complaint high performance fet layout: An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level... Agent: Ryan, Mason & Lewis, LLP

20090278208 - Semiconductor integrated circuit device and method of fabricating the same: A semiconductor integrated circuit device with higher integration density and a method of fabricating the same are provided. The semiconductor integrated circuit device may include trench isolation regions in a semiconductor substrate that define an active region and a gate pattern that is used for a higher voltage and formed... Agent: Harness, Dickey & Pierce, P.L.C

20090278210 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating... Agent: Mcdermott Will & Emery LLP

20090278209 - Semiconductor device and method of fabrication: A semiconductor device includes a gate electrode provided on a semiconductor region with a gate insulating film being interposed therebetween, extension diffusion layers provided in regions on both sides of the gate electrode of the semiconductor region, a first-conductivity type first impurity being diffused in the extension diffusion layers, and... Agent: Mcdermott Will & Emery LLP

20090278211 - Composite dielectric thin film, capacitor and field effect transistor using the same, and each fabrication method thereof: a composite dielectric thin film capable of high dielectric constant, low leakage current characteristics, and high dielectric breakdown voltage while being deposited at a room temperature, a capacitor and a field effect transistor (FET) using the same, and their fabrication methods. The composite dielectric thin film is deposited at a... Agent: Ostrolenk Faber Gerb & Soffen

20090278213 - Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array: Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon... Agent: Cantor Colburn LLP-ibm Europe

20090278212 - Integrated device: An integrated device including a sensor and the like formed on a γ-alumina layer epitaxially grown on a silicon substrate is provided at low cost. This integrated device includes: a silicon substrate; a first function area formed on a γ-alumina film epitaxially grown on a portion of the silicon substrate;... Agent: Frommer Lawrence & Haug

20090278215 - Electronic device, system, and method comprising differential sensor mems devices and drilled substrates: Electronic device which comprises a substrate provided with at least one passing opening, a MEMS device with function of differential sensor provided with a first and a second surface and of the type comprising at least one portion sensitive to chemical and/or physical variations of fluids present in correspondence with... Agent: Graybeal Jackson LLP

20090278214 - Microelectromechanical systems encapsulation process: An encapsulated MEMS process including a high-temperature anti-stiction coating that is stable under processing steps at temperatures over 450 C is described. The coating is applied after device release but before sealing vents in the encapsulation layer. Alternatively, an anti-stiction coating may be applied to released devices directly before encapsulation.... Agent: Courtney Staniford & Gregory LLP

20090278216 - Mems sensor: An MEMS sensor is described. The MEMS sensor may include a substrate, a lower thin film provided in contact with a surface of the substrate, and an upper thin film opposed to the lower thin film at an interval on the side opposite to the substrate.... Agent: Rabin & Berdo, PC

20090278217 - Mems device: A micro-electrical-mechanical device comprises: a transducer arrangement having at least a membrane being mounted with respect to a substrate; and electrical interface means for relating electrical signals to movement of the membrane; in which the transducer arrangement comprises stress alleviating formations which at least partially decouple the membrane from expansion... Agent: Dickstein Shapiro LLP

20090278218 - Magnetoresistive element: A magnetoresistive element is disclosed, wherein the magnetoresistive element is composed of a synthetic anti-ferromagnetic (SAF) structure that may include a first pinned layer, an intermediate layer, and a second pinned layer; and a Cr layer between the first pinned layer and the intermediate layer and/or the second pinned layer... Agent: Harness, Dickey & Pierce, P.L.C

20090278220 - Image sensor and fabricting method thereof: An image sensor includes the steps of forming a sublayer including a photodiode, a transistor and a metal line on a substrate, forming a pattern layer on the sublayer to be overlapped with the photodiode and to having a curved surface, and forming a combined color filter and microlens on... Agent: Mckenna Long & Aldridge LLP

20090278219 - Microelectronic devices having an emi shield and associated systems and methods: Microelectronic devices having an EMI shield, systems including such microelectronic devices, and methods for manufacturing such microelectronic devices. One embodiment of a microelectronic device comprises an imaging system comprising a microelectronic die, an optics assembly, and an electromagnetic interference (EMI) shield. The microelectronic die includes an image sensor, processing components... Agent: Kramer Levin Naftalis & Frankel LLP

20090278221 - Semiconductor device: A semiconductor device that attenuates light to the circuit element area is provided. The semiconductor device includes light-sensitive element area formed on substrate and a circuit element area formed on the substrate. Additionally, a multilayer wiring area is formed on circuit element area. A Tantalum film (which is generally made... Agent: Texas Instruments Incorporated

20090278222 - Integrated circuit with uniform polysilicon perimeter density, method and design structure: Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090278224 - Methods of forming an amorphous silicon thin film: A method for forming an amorphous silicon thin film is disclosed. In some embodiments, a method includes loading a substrate into a reaction chamber; and conducting a plurality of deposition cycles on the substrate. Each of at least two of the cycles includes: supplying a silicon precursor to the reaction... Agent: Knobbe Martens Olson & Bear LLP

20090278223 - Process for producing siliceous film and substrate with the siliceous film produced by the process: An objective of the present invention is to provide a process for producing a siliceous film which has a uniform quality independently of sites and in both the inside and outside of the grooves and is free from voids and cracks in the inside of the grooves. A substrate with... Agent: Az Electronic Materials Usa Corp. Attention: Industrial Property Dept.

20090278225 - Semiconductor device and method for isolating the same: The present invention relates to a semiconductor device and a method for isolating the same. The semiconductor device includes: a silicon substrate provided with a trench including at least one silicon pillar at a bottom portion of the trench, wherein the silicon pillar become sidewalls of micro trenches; and a... Agent: Mannava & Kang, P.C.

20090278226 - Structure for conductive liner for rad hard total dose immunity and structure thereof: The invention relates to a design structure, and more particularly, to a design structure for a conductive liner for rad hard total dose immunity and a structure thereof. The structure includes at least one shallow trench isolation structure having oxide material and formed in an SIO. A dielectric liner is... Agent: Greenblum & Bernstein, P.L.C

20090278227 - Isolation trench structure: Among structures, methods, devices, and systems for isolation trenches, a semiconductor device is provided that includes a substrate and an isolation trench structure. One such isolation trench structure includes a first isolation trench portion associated with a surface of the substrate and having a first pair of opposing sidewalls that... Agent: Brooks, Cameron & Huebsch , PLLC

20090278228 - Design structure for interconnect structure containing various capping materials for electrical fuse and other related applications: A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different... Agent: Greenblum & Bernstein, P.L.C

20090278229 - Efficient interconnect structure for electrical fuse applications: A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes... Agent: Scully, Scott, Murphy & Presser, P.C.

20090278232 - Ruthenium silicide diffusion barrier layers and methods of forming same: A method for use in the fabrication of integrated circuits includes providing a substrate assembly having a surface. A diffusion barrier layer is formed over at least a portion of the surface. The diffusion barrier layer is formed of RuSix, where x is in the range of about 0.01 to... Agent: Mueting, Raasch & Gebhardt, P.A.

20090278231 - Semiconductor device and method for fabricating the same: The semiconductor device comprises a first insulation film 26 formed over a semiconductor substrate 10, first conductor plug 32 buried in a first contact hole 28a formed down to a source/drain diffused layer 22, a capacitor 44 formed over the first insulation film 26, a first hydrogen diffusion preventing film... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090278230 - Semiconductor device and method of manufacturing the same: A semiconductor device has a substrate, an insulating interlayer, an interconnect as one example of an electro-conductive pattern, a through-electrode, and a bump as one example of a connection terminal, wherein the insulating interlayer is positioned up above the surface of the substrate, the interconnect is positioned on the surface... Agent: Mcginn Intellectual Property Law Group, PLLC

20090278234 - (al, ga, in)n-based compound semiconductor and method of fabricating the same: Disclosed are a (Al, Ga, In)N-based compound semiconductor device and a method of fabricating the same. The (Al, Ga, In)N-based compound semiconductor device of the present invention comprises a substrate; a (Al, Ga, In)N-based compound semiconductor layer grown on the substrate; and an electrode formed of at least one material... Agent: H.c. Park & Associates, PLC

20090278233 - Bonded intermediate substrate and method of making same: A method includes growing a first epitaxial layer of III-nitride material, forming a damaged region by implanting ions into an exposed surface of the first epitaxial layer, and growing a second epitaxial layer of III-nitride material on the exposed surface of the first epitaxial layer. A level of defects present... Agent: Foley And Lardner LLP Suite 500

20090278235 - Manufacturing method of semiconductor device, and semiconductor device: Provided is a manufacturing method of a semiconductor device, which is capable of realizing fine-pitch patterns and thus improving stabilization of patterning precision. The manufacturing method of the semiconductor device comprises forming a first photoresist pattern in a predetermined region on a substrate, depositing a thin film on the surface... Agent: Brundidge & Stanger, P.C.

20090278236 - Semiconductor device, wafer structure and method for fabricating semiconductor device: A photo-resist used in photolithography in a microfabrication process may be formed uniformly even if trenches for separating semiconductor devices are formed before the microfabrication process. The two parallel trenches are formed between neighboring element forming regions in a p-type semiconductor layer containing a plurality of arrayed element forming regions... Agent: Turocy & Watson, LLP

20090278237 - Through substrate via including variable sidewall profile: A microelectronic structure, such as a semiconductor structure, and a method for fabricating the microelectronic structure, include an aperture within a substrate. Into the aperture is located and formed a via. The via may include a through substrate via. The aperture includes, progressing sequentially contiguously at least partially through the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090278238 - Tsvs having chemically exposed tsv tips for integrated circuit devices: A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material... Agent: Texas Instruments Incorporated

20090278239 - Silicon wafer and production method thereof: In a silicon wafer having an oxygen precipitate layer, a depth of DZ layer ranging from a wafer surface to an oxygen precipitate layer is 2 to 10 μm and an oxygen precipitate concentration of the oxygen precipitate layer is not less than 5×107 precipitates/cm3.... Agent: Townsend And Townsend And Crew, LLP

20090278240 - Semiconductor apparatus: Disclosed is a semiconductor apparatus that prevents diffusion of materials of a magnetic film during the process for manufacturing the semiconductor apparatus. The semiconductor apparatus includes: a substrate; a semiconductor device formed on a principal surface of the substrate and including an interconnect layer; a magnetic shielding film of a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090278244 - Ic device having low resistance tsv comprising ground connection: A semiconductor device includes an integrated circuit (IC) die including a substrate, and at least one through substrate via (TSV) that extends through the substrate to a protruding integral tip that includes sidewalls and a distal end. The protruding integral tip has a tip height between 1 and 50 μm.... Agent: Texas Instruments Incorporated

20090278245 - Packaged electronic devices with face-up die having tsv connection to leads and die pad: A packaged electronic device includes a leadframe including a die pad, a first, second, and third lead pin surrounding the die pad. An IC die is assembled in a face-up configuration on the lead frame. The IC die includes a substrate having an active top surface and a bottom surface,... Agent: Texas Instruments Incorporated

20090278241 - Semiconductor die package including die stacked on premolded substrate including die: A semiconductor die package. The semiconductor includes a premolded substrate. The premolded substrate includes (i) a leadframe structure, (ii) a first semiconductor die comprising a first die surface and a second die surface, attached to the leadframe structure, and (iii) a molding material covering at least a portion of the... Agent: Townsend And Townsend And Crew, LLP

20090278242 - Stacked type chip package structure: A stacked type chip package structure including a lead frame, a chip package, a second chip, and a second molding compound is provided. The lead frame includes a plurality of first leads and second leads insulated from one another. The first leads have a first upper surface, and the second... Agent: J C Patents

20090278243 - Stacked type chip package structure and method for fabricating the same: A stacked type chip package structure including a chip carrier, a first chip, a second chip, a third chip, and an insulating material is provided. The chip carrier includes two die pads and a plurality of leads surrounding the die pads. The first chip and the second chip are disposed... Agent: J C Patents

20090278247 - Bonding pad sharing method applied to multi-chip module and apparatus thereof: A multi-chip module (MCM) includes a first die and a second die. The first die supports a plurality of predetermined functions. The second die is coupled to the first die and comprises at least an option pad configured for a bonding option. The first die performs a predetermined function according... Agent: North America Intellectual Property Corporation

20090278246 - Semiconductor device: A plurality of LSI chips (1) are stacked on an interposer (2). Signal coils (1b) for signal transmission are formed on the circuit formation surfaces of LSI chips (1) that are formed using silicon substrates (1a). The signal coils (1b) connect to circuits formed in the LAI chips (1). Through-holes... Agent: Sughrue Mion, PLLC

20090278249 - Printed circuit board and method thereof and a solder ball land and method thereof: A printed circuit board and method thereof and a solder ball land and method thereof. The example printed circuit board (PCB) may include a first solder ball land having a first surface treatment portion configured for a first type of resistance and a second solder ball land having a second... Agent: Harness, Dickey & Pierce, P.L.C

20090278248 - Semiconductor device and method of fabrication: A semiconductor device includes a first die pad, a first semiconductor chip provided on the first die pad, a second die pad, a second semiconductor chip provided on the second die pad, and a sealing resin made of a first resin material, sealing the first die pad, the first semiconductor... Agent: Mcdermott Will & Emery LLP

20090278250 - Method of semiconductor packaging and/or a semiconductor package: The method includes forming a leadframe. The leadframe is directly bonded to the semiconductor chip. The leadframe is flexed and/or compressed in a mold cavity. The compressed leadframe and the chip are molded into a package.... Agent: Slater & Matsil LLP

20090278251 - Pad structure for 3d integrated circuit: This invention discloses an I/O pad structure in an integrated circuit (IC) which comprises a first vertical region in the IC including a top metal layer and one or more semiconductor devices formed thereunder, the top metal layer in the first vertical region serving as a first pad, the semiconductor... Agent: K & L Gates LLPIPDocketing

20090278252 - Semiconductor device and method for manufacturing semiconductor device: To reduce defects of a semiconductor device, such as defects in shape and characteristic due to external stress and electrostatic discharge. To provide a highly reliable semiconductor device. In addition, to increase manufacturing yield of a semiconductor device by reducing the above defects in the manufacturing process. The semiconductor device... Agent: Eric Robinson

20090278253 - Semi-finished package and method for making a package: The present invention relates to a semi-finished package and a method for making a package. The semi-finished package includes a carrier and at least one molding compound. The molding compound is disposed on a surface of the carrier, and has a body and a plurality of outer protrusions. The outer... Agent: Mccracken & Frank LLP

20090278254 - Dielectric materials and methods for integrated circuit applications: An integrated circuit device is provided having a substrate and areas of electrically insulating and electrically conductive material, where the electrically insulating material is a hybrid organic-inorganic material that requires no or minimal CMP and which can withstand subsequent processing steps at temperatures of 450° C. or more.... Agent: Kubovcik & Kubovcik

20090278255 - Semiconductor device: A semiconductor device includes a substrate having external connection terminals, and a semiconductor chip mounted over a semiconductor-chip mounting portion of the substrate. The external connection terminals are formed by sequentially forming an electroless nickel plating layer, an electroless gold plating layer, and an electrolytic gold plating layer on a... Agent: Mcdermott Will & Emery LLP

20090278256 - Semiconductor package enhancing variation of movability at ball terminals: A semiconductor package with enhanced mobility of ball terminals is revealed. A chip is attached to the substrate by a die-attaching material where the substrate has at least a stepwise depression on the covered surface to make the substrate thickness be stepwise decreased from a central line of the die-attaching... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090278257 - Method to assemble structures from nano-materials: Numerous embodiments of a method to assemble nano-materials on a platform are described. In one embodiment, a nano-material is functionalized with a first bondable group. The functionalized nano-material is disposed on an assembly platform having an electrode to form a first layer. Additional layers of the nano-material may be formed... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090278258 - Interconnect structure with a mushroom-shaped oxide capping layer and method for fabricating same: An interconnect structure is provided that includes a dielectric material 52′ having a dielectric constant of 4.0 or less and including a plurality of conductive features 56 embedded therein. The dielectric material 52′ has an upper surface 52r that is located beneath an upper surface of each of the plurality... Agent: Scully, Scott, Murphy & Presser, P.C.

20090278259 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device includes an insulation film formed above a semiconductor substrate, a conductor containing Cu formed in the insulation film, and a layer film formed between the insulation film and the conductor and formed of a first metal film containing Ti and a second metal film different from the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090278260 - Redundancy design with electro-migration immunity and method of manufacture: An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, a design structure of the IC interconnect and a method of manufacture of the IC interconnect is provided. The structure has electro-migration immunity and redundancy of design, which includes a plurality of wires laid... Agent: Greenblum & Bernstein, P.L.C

20090278261 - Semiconductor device and method for fabricating the same: An interlayer insulating film is formed on the upper surface of a semiconductor substrate, and lower-level interconnects are formed in the interlayer insulating film. A liner insulating film is formed on the upper surfaces of the interlayer insulating film and lower-level interconnects. An interlayer insulating film is formed on the... Agent: Mcdermott Will & Emery LLP

20090278262 - Multi-chip package including component supporting die overhang and system including same: A microelectronic package and a system including the package. The package includes: a substrate; a stack of dice electrically and mechanically bonded to the substrate, the stack including a second level die and a first level die between the substrate and the second level die, the second level die defining... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090278263 - Reliability wcsp layouts: An integrated circuit device includes a functional circuit die with a patterned rewiring layer defining a first rewiring pad and one or more second rewiring pads on opposite sides of a neutral point of the die. The device also includes at least one dielectric layer having bump opening features over... Agent: Texas Instruments Incorporated

20090278264 - Semiconductor chip bump connection apparatus and method: Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and... Agent: Timothy M Honeycutt Attorney At Law

20090278265 - Electronic component and resin packaging method for electronic component: An electronic component, in which the outer perimeter portion of a component (2) is surrounded with a first sealing resin (4), a second sealing resin (3) is filled within the periphery of the first sealing resin (4), the component (2) and a board (1) are electrically connected by a wire... Agent: Steptoe & Johnson LLP

20090272959 - Non-volatile resistive-switching memories: Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set... Agent: Legal Department

20090272958 - Resistive memory: An integrated circuit including a memory cell and method of manufacturing the integrated circuit are described. The memory cell includes a diode and a resistive memory element coupled to the diode. The resistive memory element includes a thin oxide storage layer that uses multiple resistance levels to store more than... Agent: Slater & Matsil, L.L.P.

20090272960 - Non-volatile resistive oxide memory cells, and methods of forming non-volatile resistive oxide memory cells: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The first conductive electrode has an elevationally outermost surface and opposing laterally outermost edges at the elevationally outermost surface in one planar cross section. Multi-resistive... Agent: Wells St. John P.s.

20090272962 - Reduction of forming voltage in semiconductor devices: This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (RRAM) that use techniques to provide a memory device with more predictable operation. In particular, forming voltage required by particular designs may be reduced through... Agent: Marc P Schuyler- Im

20090272961 - Surface treatment to improve resistive-switching characteristics: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters.... Agent: Marc P Schuyler- Im

20090272964 - Light-emitting device and method for manufacturing the same: A light-emitting device and the method for making the same is disclosed. The light-emitting device is a semiconductor device, comprising a growth substrate, an n-type semiconductor layer, a quantum well active layer and a p-type semiconductor layer. It combines the holographic and the quantum well interdiffusion (QWI) to form a... Agent: Bacon & Thomas, PLLC

20090272963 - Surface light emitting element: l

20090272965 - Selective high-k dielectric film deposition for semiconductor device: Embodiments of the present invention describe a method of fabricating a III-V quantum well transistor with low current leakage and high on-to-off current ratio. A hydrophobic mask having an opening is formed on a semiconductor film. The opening exposes a portion on the semiconductor film where a dielectric layer is... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090272968 - Material for a thin and low-conductive functional layer for an oled and production method therefor: The invention relates to a material for applying thin organic layers having a conductivity that can be set in a defined manner. The material comprises at least one mixture consisting of two different fractions of a functional polymer, preferably in a solvent, and is applied, for example, in the form... Agent: Fish & Richardson PC

20090272969 - Method of patterning an organic thin film, an organic thin film transistor, a method of manufacturing an organic thin film transistor, and an organic electroluminescene display device having the organic thin film transistor: Provided is a method of patterning an organic thin film which can prevent surface damage of an organic semiconductor layer. Also, an organic thin film transistor that can reduce an off-current and can prevent surface damage of the organic semiconductor layer and a method of manufacturing the organic thin film... Agent: Knobbe Martens Olson & Bear LLP

20090272966 - Organic transistor and active matrix display: An organic transistor is disclosed that has an organic semiconductor layer patterned with high resolution. The organic transistor includes a gate electrode, a gate insulting film, a source electrode, a drain electrode, and an organic semiconductor layer formed of an organic semiconductor material. The gate electrode, the gate insulting film,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090272967 - Pentacene-carbon nanotube composite, method of forming the composite, and semiconductor device including the composite: A composite material includes a carbon nanotube, and plural pentacene molecules bonded to the carbon nanotube. A method of forming the composite layer, includes depositing on a substrate a dispersion of soluble pentacene precursor and carbon nanotubes, heating the dispersion to remove solvent from the dispersion, heating the substrate to... Agent: Mcginn Intellectual Property Law Group, PLLC

20090272970 - Field-effect transistor: Provided is a field-effect transistor including an active layer and a gate insulating film, wherein the active layer includes an amorphous oxide layer containing an amorphous region and a crystalline region, and the crystalline region is in the vicinity of or in contact with an interface between the amorphous oxide... Agent: Fitzpatrick Cella Harper & Scinto

20090272971 - Light emitting device having a pluralilty of light emitting cells and package mounting the same: Disclosed is a light emitting device having a plurality of light emitting cells and a package having the same mounted thereon. The light emitting device includes a plurality of light emitting cells which are formed on a substrate and each of which has an N-type semiconductor layer and a P-type... Agent: H.c. Park & Associates, PLC

20090272972 - Zno based semiconductor light emitting device and its manufacture method: A ZnO based semiconductor light emitting device includes: a first semiconductor layer containing ZnO1-x1Sx1; a second semiconductor layer formed above the first semiconductor layer and containing ZnO1-x2Sx2; and a third semiconductor layer formed above the second semiconductor layer and containing ZnO1-x3Sx3, wherein an S composition x1 of the first semiconductor... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090272974 - Interposer chip and multi-chip package having the interposer chip: An interposer chip may include an insulating substrate, conductive patterns, and a test pattern. The conductive patterns may be formed on the insulating substrate. Further, the conductive patterns may be electrically connected to conductive wires. The test pattern may be connected to the conductive patterns. A test current for testing... Agent: Harness, Dickey & Pierce, P.L.C

20090272973 - Semiconductor wafer including semiconductor chips divided by scribe line and process-monitor electrode pads formed on scribe line: The present invention discloses a semiconductor wafer having a scribe line dividing the semiconductor wafer into a matrix of plural semiconductor chips. The semiconductor wafer includes a polysilicon layer, a poly-metal interlayer insulation film formed on the polysilicon layer, and a first metal wiring layer formed on the poly-metal interlayer... Agent: Cooper & Dunham, LLP

20090272975 - Poly-crystalline layer structure for light-emitting diodes: A structure and method for a light-emitting diode are presented. A preferred embodiment comprises a substrate with a conductive, poly-crystalline, silicon-containing layer over the substrate. A first contact layer is epitaxially grown, using the conductive, poly-crystalline, silicon-containing layer as a nucleation layer. An active layer is formed over the first... Agent: Slater & Matsil, L.L.P.

20090272976 - Method for producing nmos and pmos devices in cmos processing: A method for producing one or more nMOSFET devices and one or more pMOSFET devices on the same semiconductor substrate is disclosed. In one aspect, the method relates to the use of a single activation anneal that serves for both Si NMOS and Ge pMOS. By use of a solid... Agent: Knobbe Martens Olson & Bear LLP

20090272977 - Pixel structure of a thin film transistor liquid crystal display and fabricating method thereof: A method of fabricating a pixel structure of a thin film transistor liquid crystal display is provided. A transparent conductive layer and a first metallic layer are sequentially formed over a substrate. The first metallic layer and the transparent conductive layer are patterned to form a gate pattern and a... Agent: J C Patents

20090272978 - Image display system and manufacturing method thereof: An image display system and manufacturing method are disclosed. According to the present invention, the image display system comprises a substrate, a switching TFT, a driving TFT, a photo sensor and a capacitor. A buffer layer is formed on a substrate. A separation layer is formed in a first area... Agent: Lowe Hauptman Ham & Berner, LLP

20090272979 - Active matrix electronic array device: An active matrix device has an array (54) of device elements, each of which comprises at least one thin film transistor (34). A thin film conductive heater element arrangement (10) is provided over a substrate of the device, and the semiconductor islands of the thin film transistors are provided over... Agent: Joe Mckinney Muncy Birch, Stewart, Kolash & Birch, LLP

20090272981 - Display substrate and method of manufacturing the same: A display substrate includes a gate electrode, a gate insulating layer, and a semiconductor layer that are sequentially formed on a substrate. Also, the display substrate includes a color filter layer formed on the substrate and exposing a portion of the semiconductor layer, and source and drain electrodes that each... Agent: H.c. Park & Associates, PLC

20090272980 - Thin film transistor array panel and manufacturing method of the same: A semiconductor including a channel, a data line including a source electrode, a drain electrode, and a pixel area definition member is formed on a gate insulating layer, and a passivation layer is deposited on the data line, the pixel area definition member, and the channel of the semiconductor. A... Agent: Haynes And Boone, LLPIPSection

20090272984 - Silicon carbide on diamond substrates and related devices and methods: A high power, wide-bandgap device is disclosed that exhibits reduced junction temperature and higher power density during operation and improved reliability at a rated power density. The device includes a diamond substrate for providing a heat sink with a thermal conductivity greater than silicon carbide, a single crystal silicon carbide... Agent: Summa, Additon & Ashe, P.A.

20090272983 - Silicon carbide semiconductor device and method for manufacturing the same: A silicon carbide semiconductor device includes: a semiconductor substrate having a silicon carbide substrate, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; a trench penetrating the second and the third semiconductor layers to reach the first semiconductor layer; a channel layer on a sidewall and... Agent: Posz Law Group, PLC

20090272982 - Trench gate type semiconductor device and method of producing the same: A method of producing a trench gate type MOSFET is provided in which each intersection trench is formed as a two-stage trench structure. A gate trench is backfilled with a mask material and the mask material is then patterned to form a mask used for forming each intersection trench. The... Agent: Rossi, Kimms & Mcdowell LLP.

20090272986 - Led module, and led chain containing the same: The present invention discloses an LED module comprising: a waterproof enclosure; an LED accommodated in the waterproof enclosure; a wire for coupling the LED module with other LED modules and a driver; and a radiating unit set in the bottom of the waterproof enclosure and exposed to the external environment.... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090272987 - Structure of led of high heat-conducting efficiency: A structure of LED of high heat-conducting efficiency is to provide a copper substrate having a plurality of indentations. An insulating layer is formed on the surface of the substrate and the bottom of the indentations. Meanwhile, a set of metallic circuits is formed on the insulating layer of the... Agent: Hdls Patent & Trademark Services

20090272985 - White led lamp and backlight using the same, and liquid crystal display device using the backlight: A white LED lamp 1 according to the present invention comprises an LED chip 2 having a luminescence wavelength of not less than 360 nm and not more than 440 nm, and a light emitting part excitable upon exposure to light from the LED chip 2 to emit white light... Agent: Harness, Dickey & Pierce, P.L.C

20090272989 - Light emitting device having stacked multiple leds: A light emitting device and method of producing the same is disclosed. The light emitting device includes a heterostructure having a plurality of light emitting diodes (LEDs) stacked one on top of another.... Agent: Arent Fox LLP

20090272990 - Light mixing apparatus for light emitting diode: A light mixing apparatus of a light emitting diode (LED) is installed on a light emitting surface of the LED. The light emitted from the LED is mixed by a light mixing module of the light mixing apparatus uniformly for adjusting the light output angle. After the angle increases, the... Agent: Hdls Patent & Trademark Services

20090272988 - Multi-chip module single package structure for semiconductor: The invention is to provide a semiconductor light-emitting device package structure. The semiconductor light-emitting device package structure includes a substrate, N sub-mounts and N semiconductor light-emitting die modules, where N is a positive integer lager than or equal to 2. Each of the sub-mounts is embedded on the substrate and... Agent: Juan Carlos A. Marquez C/o Stites & Harbison PLLC

20090272991 - Light emitting diode having alingap active layer and method of fabricating the same: A light emitting diode having an AlInGaP active layer and a method of fabricating the same are disclosed. The light emitting diode includes a substrate. A plurality of light emitting cells are positioned to be spaced apart from one another, wherein each of the light emitting cells has a first... Agent: H.c. Park & Associates, PLC

20090272993 - Semiconductor light emitting device: A semiconductor light emitting device comprises a first nitride semiconductor layer comprising a plurality of concave portions, a reflector in at least one of the concave portions of the first nitride semiconductor layer, and a second nitride semiconductor layer on the first nitride semiconductor layer.... Agent: Birch Stewart Kolasch & Birch

20090272992 - Semiconductor light-emitting device and process for producing the same: A semiconductor light emitting device of the present invention includes a substrate (1), an n-GaN layer (2) supported by the substrate (1), a p-GaN layer (7) which is located farther from the substrate (1) than the n-GaN layer (2) is, an active layer (4) formed between the n-GaN layer (2)... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20090272994 - Semiconductor light emitting device: The embodiment discloses a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, a first electrode formed under the first conductive semiconductor layer and comprising a... Agent: Birch Stewart Kolasch & Birch

20090272996 - Encapsulation for phosphor-converted white light emitting diode: An improved light emitting device, especially a phosphor-converted white light device, wherein the light extraction efficiency and the color temperature distribution uniformity are improved by the introduction of both nanoparticles and light scattering particles proximate to the light source. Nanoparticles having a high index of refraction are dispersed throughout a... Agent: Koppel, Patrick, Heybl & Dawson

20090272997 - Led structure to increase brightness: A light emitting semiconductor device comprising an LED having an emission aperture located on a surface of the LED and the emission aperture has a size that is smaller than a surface area of the LED where the emission aperture is formed. The device further includes a reflector surrounding both... Agent: Arent Fox LLP

20090273000 - Light emitting device and method of manufacturing same: A light emitting device according to the present invention comprises board 2 having electrode 3b formed on the surface thereof, light emitting element 1 mounted on the surface of board 2, wire 4 for electrically connecting light emitting element 1 with electrode 3b, and reflector 11b formed on the surface... Agent: Mcginn Intellectual Property Law Group, PLLC

20090272998 - Optoelectronic semiconductor chip comprising a wavelength conversion substance, and optoelectronic semiconductor component comprising such a semiconductor chip, and method for producing the optoelectronic semiconductor chip: A semiconductor chip comprises: a semiconductor body which comprises a semiconductor layer sequence suitable for emitting electromagnetic radiation of a first wavelength range from its front side; and a first wavelength-converting layer on at least one first partial region of the front side of the semiconductor body with a first... Agent: Fish & Richardson PC

20090272999 - Organic element and manufacturing method thereof: An organic EL display panel having a functional layer with a uniform film thickness is provided. The organic EL display panel of the present invention contains an anode electrode set on a substrate; line-state banks set on the substrate on which the anode electrode is set and defining a line-state... Agent: Greenblum & Bernstein, P.L.C

20090272995 - Resin composition for optical semiconductor element encapsulation, and optical semiconductor device produced by using the same: An epoxy resin composition for optical semiconductor element encapsulation includes an epoxy resin (Component (A)) mainly containing an epoxy compound represented by a specific structural formula (1), a curing agent (Component (B)), and at least one of an oxynitride phosphor and a nitride phosphor (Component (C)). Therefore, the phosphor component... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090273004 - Chip package structure and method of making the same: A chip package structure and method thereof uses a semiconductor substrate as a package substrate, which improve heat dissipation. Also, the chip package structure is incorporated with a planarization structure, which renders the chip and the package substrate a substantially planar surface, thereby making formation of a planar patterned conductive... Agent: North America Intellectual Property Corporation

20090273002 - Led package structure and fabrication method: System and method for packaging an LED is presented. A preferred embodiment includes a plurality of thermal vias located through the packaging substrate to effectively transfer heat away from the LED, and are preferably formed along with conductive vias that extend through the packaging substrate. The thermal vias are preferably... Agent: Slater & Matsil, L.L.P.

20090273003 - Light emitting device and method for manufacturing the same: A light emitting device comprises a second electrode layer; a second conductivity-type semiconductor layer on the second electrode layer; a current blocking layer comprising an oxide of the second conductivity-type semiconductor layer; an active layer on the second conductivity-type semiconductor layer; a first conductivity-type semiconductor layer on the active layer;... Agent: Birch Stewart Kolasch & Birch

20090273005 - Opto-electronic package structure having silicon-substrate and method of forming the same: Disclosed herein is a structure of opto-electronic package having a Si-substrate. The Si-substrates are manufactured in batch utilizing the micro-electromechanical processes or the semiconductor processes, so that these Si-substrates are made with great precision and full of varieties. Based on the material characteristic of the Si-substrate, and the configuration of... Agent: North America Intellectual Property Corporation

20090273001 - Wire bonding to connect electrodes: A light emitting apparatus includes a semiconductor layer having an electrode with two traces physically separated from one another. The light emitting apparatus further includes a wire bond electrically connecting the two traces.... Agent: Arent Fox LLP

20090273006 - Bidirectional silicon-controlled rectifier: The present invention discloses a bidirectional silicon-controlled rectifier, wherein the conventional field oxide layer, which separates an anode structure from a cathode structure, is replaced by a field oxide layer having floating gates, a virtual gate or a virtual active region. Thus, the present invention can reduce or escape from... Agent: Rosenberg, Klein & Lee

20090273007 - Method of testing an integrated circuit die, and an integrated circuit die: In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter:... Agent: Dla Piper LLP (us )

20090273008 - Image sensor and method for manufacturing the same: In a solid state imaging device, and a method of manufacture thereof, the efficiency of the transfer of available photons to the photo-receiving elements is increased beyond that which is currently available. Enhanced anti-reflection layer configurations, and methods of manufacture thereof, are provided that allow for such increased efficiency. They... Agent: Mills & Onello LLP

20090273009 - Integrated cmos porous sensor: A single chip wireless sensor (1) comprises a microcontroller (2) connected by a transmit/receive interface (3) to a wireless antenna (4). The microcontroller (2) is also connected to an 8 kB RAM (5), a USB interface (6), an RS232 interface (8), 64 kB flash memory (9), and a 32 kHz... Agent: Jacobson Holman PLLC

20090273011 - Metal-oxide-semiconductor device including an energy filter: A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from... Agent: Ryan, Mason & Lewis, LLP

20090273010 - Removal of impurities from semiconductor device layers: A method for removing impurities from at least one semiconductor device layer during manufacturing of a semiconductor device is disclosed. The semiconductor device layer has a compound semiconductor material and/or germanium. Each heating process performed during the manufacturing of the semiconductor device after provision of the semiconductor device layer has... Agent: Knobbe Martens Olson & Bear LLP

20090273012 - High voltage tolerant metal-oxide-semiconductor device: A method for increasing a voltage tolerance of a MOS device having a first capacitance value associated therewith is provided. The method includes the steps of: connecting at least a first capacitor in series with the MOS device, the first capacitor having a first capacitance value associated therewith, the first... Agent: Ryan, Mason & Lewis, LLP

20090273013 - Method of forming a split gate memory device and apparatus: A split-gate memory device has a select gate having a first work function overlying a first portion of a substrate. A control gate having a second work function overlies a second portion of the substrate proximate the first portion. When the majority carriers of the split-gate memory device are electrons,... Agent: Freescale Semiconductor, Inc. Law Department

20090273014 - Nonvolatile semiconductor memory device: Each of a memory gate, a control gate, a source diffusion layer, and a drain diffusion layer is connected to a control circuit for controlling potential, and the control circuit operates so as to supply a first potential to the memory gate, a second potential to the control gate, a... Agent: Miles & Stockbridge PC

20090273016 - Nanocrystal formation using atomic layer deposition and resulting apparatus: Nanocrystal structures formed using atomic layer deposition (ALD) processes are useful in the formation of integrated circuits such as memory devices. Rather than continuing the ALD process until a continuous layer is formed, the ALD process is halted prematurely to leave a discontinuous formation of nanocrystals which are then capped... Agent: Leffert Jay & Polglaze, P.A.

20090273015 - Non-volatile memory cell: This document discloses non-volatile memory cells and methods of manufacturing the same. The non-volatile memory cells are self-aligned and have a reduced tunnel window area that is within an active region of a substrate. The tunnel window area can be reduced using mask openings without optical proximity correction that define... Agent: Fish & Richardson P.C.

20090273017 - Method for forming trenches on a surface of a semiconductor substrate: A method for forming trenches on a surface of a semiconductor substrate is described. The method may include: etching a first plurality of trenches into the surface of the semiconductor substrate; filling the first plurality of trenches with at least one material; and etching a second plurality of trenches into... Agent: Coats & Bennett/qimonda

20090273019 - Memory device transistors: Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET transistor gate dielectric smiling, or bird's beaks, are adjustable by re-oxidation processing. An additional re-oxidation process is performed by opening a poly-silicon layer prior to forming an inter-poly oxide dielectric... Agent: Schwegman, Lundberg & Woessner/micron

20090273018 - Nonvolatile memory device with multiple blocking layers and method of fabricating the same: A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blocking layer, wherein the first blocking layer... Agent: Lowe Hauptman Ham & Berner, LLP

20090273020 - Sonos flash memory: A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) flash memory, comprising: preparing a silicon substrate including a silicon oxide-silicon nitride-silicon oxide (ONO) layer, a first polysilicon layer and a first etch stop layer in sequence; etching the first etch stop layer along a direction of bit line; selectively etching the first... Agent: Squire, Sanders & Dempsey L.L.P.

20090273021 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a semiconductor substrate, a tunnel insulating film on the semiconductor substrate, a charge storage layer on the tunnel insulating film, a block insulating film on the charge storage layer, and a control gate electrode on the block insulating film, the charge storage layer including a plurality... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090273022 - Conductive hard mask to protect patterned features during trench etch: A monolithic three dimensional memory array is formed by a method that includes forming a first memory level above a substrate by i) forming a plurality of first substantially parallel conductors extending in a first direction, ii) forming first pillars above the first conductors, each first pillar comprising a first... Agent: Dugan & Dugan, PC

20090273023 - Segmented pillar layout for a high-voltage vertical transistor: In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor... Agent: The Law Offices Of Bradley J. Bereznak

20090273024 - Method for producing a transistor component having a field plate: A method for producing a transistor component having a field plate. One embodiment includes providing a semiconductor body having a first side, and including a first trench extending into the semiconductor body. A field plate dielectric layer is produced on the first side and at uncovered areas of the first... Agent: Dicke, Billig & Czaja

20090273025 - Semiconductor device and method for manufacturing the same: Disclosed herein are a semiconductor device and a method for manufacturing the same. The method includes forming a gate structure using a carbon nano tube (CNT). In order to prevent reduction of the gate resistance and the short channel effect, a CNT gate having a grown CNT pattern with a... Agent: Marshall, Gerstein & Borun LLP

20090273026 - Trench-gate ldmos structures: MOSFET devices for RF applications that use a trench-gate in place of the lateral gate conventionally used in lateral MOSFET devices. A trench-gate provides devices with a single, short channel for high frequency gain. Embodiments of the present invention provide devices with an asymmetric oxide in the trench gate, as... Agent: Townsend And Townsend And Crew, LLP

20090273027 - Power ic device and method for manufacturing same: In a power IC device, a surface layer channel CMOS transistor and a trench power MOS transistor are formed on the same chip. In one embodiment, a source region of the trench power MOS transistor is arranged at the same level as a gate electrode of the surface layer channel... Agent: Harness, Dickey & Pierce, P.L.C

20090273028 - Short channel lateral mosfet and method:

20090273029 - High voltage ldmos transistor and method: An LDMOS transistor structure and methods of making the same are provided. The structure includes a gate electrode extended on an upper boundary of an extension dielectric region that separates the gate electrode from the drain region of the LDMOS transistor. Moreover, at an area close to an edge of... Agent: Slater & Matsil, L.L.P.

20090273030 - Semiconductor device with a trench isolation and method of manufacturing trenches in a semiconductor body: A low cost integration method for a plurality of deep isolation trenches on the same chip is provided. The trenches have an additional n-type or p-type doped region surrounding the trench—silicon interface. Providing such variations of doping the trench interface is achieved by using implantation masking layers or doped glass... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090273031 - Semiconductor device: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a major surface of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the major surface of the first semiconductor... Agent: Patterson & Sheridan, L.L.P.

20090273032 - Ldmos device and method for manufacturing the same: Provided is a LDMOS device and method for manufacturing. The LDMOS device includes a second conductive type buried layer formed in a first conductive type substrate. A first conductive type first well is formed in the buried layer and a field insulator with a gate insulating layer at both sides... Agent: Jeff Lloyd Saliwanchik Lloyd & Saliwanchik

20090273033 - Electrostatic discharge protection circuit: An ESD protection circuit including a substrate of a first conductivity type, an annular well region of a second conductivity type, two first regions of the first conductivity type and at least one transistor of the second conductivity type is provided. The annular well region is disposed in the substrate.... Agent: J C Patents

20090273034 - Source/drain carbon implant and rta anneal, pre-sige deposition: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a... Agent: Slater & Matsil, L.L.P.

20090273036 - Method for reducing defects of gate of cmos devices during cleaning processes by modifying a parasitic pn junction: By incorporating nitrogen into the P-doped regions and N-doped regions of the gate electrode material prior to patterning the gate electrode structure, yield losses due to reactive wet chemical cleaning processes may be significantly reduced.... Agent: Williams, Morgan & Amerson

20090273035 - Method for selectively removing a spacer in a dual stress liner approach: By integrating a spacer removal process into the sequence for patterning a first stress-inducing material during a dual stress liner approach, the sidewall spacer structure for one type of transistor may be maintained, without requiring additional lithography steps.... Agent: Williams, Morgan & Amerson

20090273037 - Semiconductor integrated circuit device and manufacturing method thereof: After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film (10)... Agent: Miles & Stockbridge PC

20090273039 - Semiconductor device: A semiconductor device in which potential is uniformly controlled and in which the influence of noise is reduced. A p-type well region is formed beneath a surface of a p-type Si substrate. n-type MOS transistors are formed on the p-type well region. An n-type well region is formed in the... Agent: Fujitsu Patent Center C/o Cpa Global

20090273038 - Semiconductor device and a method of manufacturing the same: A technique is provided which permits formation within a single chip both a field effect transistor of high reliability capable of suppressing the occurrence of a crystal defect and a field effect transistor of a high integration degree. In a mask ROM section having an element isolation region with an... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090273040 - High performance schottky-barrier-source asymmetric mosfets: The present invention, in one embodiment, provides a semiconductor device including a semiconducting body including a schottky barrier region at a first end of the semiconducting body, a drain dopant region at the second end of the semiconducting body, and a channel positioned between the schottky barrier region and the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090273042 - Metal high dielectric constant transistor with reverse-t gate: A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric constant material, a second... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.

20090273041 - Transistor with high-k dielectric sidewall spacer: A transistor is provided that includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.

20090273043 - Micro-electro-mechanical system device and method for making same: According to the present invention, a micro-electro-mechanical system (MEMS) device comprises: a thin film structure including at least a metal layer and a protection layer deposited in any order; and a protrusion connected under the thin film structure. A preferred thin film structure includes at least a lower protection layer,... Agent: Global Patents

20090273045 - Magnetic memory device and method of fabricating the same: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed... Agent: F. Chau & Associates, LLC

20090273044 - Semiconductor device, memory module, and method of manufacturing a semiconductor device: According to one embodiment of the present invention, a semiconductor device is provided including a semiconductor chip. The semiconductor chip is at least partly surrounded by a surrounding structure. The semiconductor chip further includes a magneto-resistive memory cell. A shielding layer is disposed between the semiconductor chip and the surrounding... Agent: Slater & Matsil, L.L.P.

20090273048 - Image-sensing chip package module adapted to dual-side soldering: An image-sensing chip package module adapted to dual-side soldering includes three substrates, an image-sensing chip and a filter lens. The three substrates are stacked together by pressing (using adhesive as adhesion medium), and the image-sensing chip is electrically connected to the top side of the top substrate and the bottom... Agent: Rosenberg, Klein & Lee

20090273046 - Process for producing solid-state image sensing device, solid-state image sensing device and camera: In the formation of a multilayer interference filter that is included in a solid-state imaging device, at the outset, a titanium dioxide layer (401), a silicon dioxide layer (402), a titanium dioxide layer (403), and a spacer layer are successively laminated on an interlayer insulation film (304) to form a... Agent: Mcdermott Will & Emery LLP

20090273047 - Solid state imaging device and manufacturing method thereof: To a transparent substrate (20) on which a plurality of spacers (5) are formed, an infrared cut filter (IRCF) substrate (27) is attached. The IRCF substrate (27) has a coefficient of thermal expansion smaller than the transparent substrate (20) and approximately equal to a wafer (31). Next, the transparent substrate... Agent: Birch Stewart Kolasch & Birch

20090273049 - Wdm signal detector: A detector includes a light detecting layer and a grating structure. The light detecting layer, which can be a photodiode, has an optical mode that resonates in the light detecting layer, and the grating structure is positioned to interact with the optical mode. The grating structure further couples incident light... Agent: Hewlett-packard Company Intellectual Property Administration

20090273050 - Photoelectric conversion device and method of producing the same, and method of producing line image sensor ic: A plurality of line image sensor ICs 110 are formed to be arranged in X, Y directions with gaps therebetween on a semiconductor substrate 101. The gaps between the line image sensor ICs 110 become scribe lines 102X, 102Y. A pattern of dummy interconnects 120 is formed in a region... Agent: Brinks Hofer Gilson & Lione/seiko Instruments Inc.

20090273051 - Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same: Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch... Agent: Wells St. John P.s.

20090273052 - Reducing device performance drift caused by large spacings between action regions: A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a... Agent: Slater & Matsil, L.L.P.

20090273053 - Semiconductor device including analog circuitry having a plurality of devices of reduced mismatch: In an analog circuit portion, a systematic mismatch between a plurality of circuit elements may be reduced in view of a technology gradient by appropriately positioning the unit devices of the circuit elements so as to obtain a similar response of the circuit elements with respect to the gradient. For... Agent: Williams, Morgan & Amerson

20090273055 - Fuse structure: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the... Agent: Slater & Matsil, L.L.P.

20090273054 - Non-volatile memory device and method of fabricating the same: A non-volatile memory device and methods of fabricating the device according to example embodiments involve a stacked layer structure. The non-volatile memory device may include at least one first horizontal electrode including a first sidewall and a second sidewall; at least one second horizontal electrode including a third sidewall and... Agent: Harness, Dickey & Pierce, P.L.C

20090273056 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate, and an electrical fuse provided on the semiconductor substrates. The electrical fuse includes a first fuse link and a second fuse link mutually connected in series, a first current inlet/outlet terminal (first terminal) and a second current inlet/outlet terminal (second terminal) respectively provided... Agent: Young & Thompson

20090273058 - Electrical components for microelectronic devices and methods of forming the same: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying... Agent: Perkins Coie LLP Patent-sea

20090273057 - Method, apparatus, and system for low temperature deposition and irradiation annealing of thin film capacitor: Some embodiments of the invention include thin film capacitors formed in a package substrate of an integrated circuit package. At least one of the thin film capacitors includes a first electrode layer, a second electrode layer, and a dielectric layer between the first and second electrode layers. Each of the... Agent: Schwegman, Lundberg & Woessner/intel

20090273059 - Semiconductor integrated circuit having polysilicon members: A semiconductor integrated circuit includes a substrate, an oxide layer formed on an upper surface of the substrate, a plurality of polysilicon members arranged at constant intervals in a matrix on an upper surface of the oxide layer and including at least one first polysilicon member and a plurality of... Agent: Arent Fox LLP

20090273060 - Group iii nitride crystal and method for surface treatment thereof, group iii nitride stack and manufacturing method thereof, and group iii nitride semiconductor device and manufacturing method thereof: A method for surface treatment of a group III nitride crystal includes the steps of lapping a surface of a group III nitride crystal using a hard abrasive grain with a Mohs hardness higher than 7, and abrasive-grain-free polishing the lapped surface of the group III nitride crystal using a... Agent: Drinker Biddle & Reath (dc)

20090273061 - Semiconductor substrate, semiconductor device, and method for manufacturing the semiconductor substrate: A double-structure silicon on insulator (SOI) substrate with a silicon layer, an insulation film (silicon oxide film), a silicon layer, and an insulation film in this order from the side of the surface. The upper-layer insulation film is formed so as to have a uniform distribution of depth while the... Agent: Sonnenschein Nath & Rosenthal LLP

20090273062 - Semiconductor package heat spreader: A semiconductor heat spreader from a unitary metallic plate is provided. The unitary metallic plate is formed into a panel, channel walls, at least two feet, and at least one external reversing bend. The channel walls depend from the panel to define a channel between the channel walls and the... Agent: Law Offices Of Mikio Ishimaru

20090273063 - Semiconductor device: One embodiment provides a semiconductor device including a carrier, a first chip attached to the carrier, a structured dielectric coupled to the chip and to the carrier, and a conducting element electrically connected with the chip and extending over a portion of the structured dielectric. The conducting element includes a... Agent: Dicke, Billig & Czaja

20090273064 - Semiconductor device and inspection method therefor: A semiconductor device includes a circuit block formed in a peripheral edge portion of a semiconductor chip, a circuit block pad formed on the circuit block providing an electrical connection for said circuit block, and a bonding pad laterally offset from the circuit block and the circuit block pad, the... Agent: Mcginn Intellectual Property Law Group, PLLC

20090273065 - Interconnection of lead frame to die utilizing flip chip process: Embodiments in accordance with the present invention relate to techniques which avoid the problems of deformation in the shape of a solder connection in a flip chip package, resulting from solder reflow. In one embodiment, a solder-repellent surface is created adjacent to the solder to constrain the reflow and thereby... Agent: Townsend And Townsend And Crew, LLP

20090273066 - Semiconductor device and method: An electronic device and fabrication of an electronic device. One embodiment provides applying a paste including electrically conductive particles to a surface of a semiconductor wafer. The semiconductor wafer is singulated with the electrically conductive particles for obtaining a plurality of semiconductor chips. At least one of the plurality of... Agent: Dicke, Billig & Czaja

20090273067 - Multi-chip discrete devices in semiconductor packages: Semiconductor packages that contain multiple dies containing discrete devices and methods for making such devices are described. The semiconductor package contains both a first die containing transistor and second die containing a diode. The interconnect lead of the semiconductor package is connected to the bond pad of the transistor. At... Agent: Kenneth E. Horton Kirton & Mcconkle

20090273068 - 3-d integrated circuit lateral heat dissipation: By filling an air gap between tiers of a stacked IC device with a thermally conductive material, heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the... Agent: Qualcomm Incorporated

20090273069 - Low profile chip scale stacking system and method: The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of... Agent: Fish & Richardson P.C.

20090273071 - Ic chip mounting package and process for manufacturing the same: In one embodiment of the present invention, an IC chip mounting package is arranged such that an IC chip and a film base member are connected via an interposer, and a section in which the IC chip, the film base member, and the interposer are connected is sealed with sealing... Agent: Harness, Dickey & Pierce, P.L.C

20090273070 - Liquid resin composition for electronic components and electronic component device: The invention relates to a liquid resin composition for electronic components which is used in sealing of electronic components, comprising a liquid epoxy resin, a curing agent containing a liquid aromatic amine, and an inorganic filler, and further comprising at least one member selected from a hardening accelerator, silicone polymer... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090273074 - Bond wire loop for high speed noise isolation: Semiconductor dies embodying electronic circuits are enclosed and protected within a package. To electrically access the die, the package includes external electrical leads which in turn connect to internal bond wires. The bond wires electrically connect the package to the die. As die density and circuit complexity increase, bond wire... Agent: Weide & Miller - Mindspeed

20090273073 - Connecting structure for flip-chip semiconductor package, build-up layer material, sealing resin composition, and circuit board: The invention provides a connecting structure for a flip-chip semiconductor package in which cracking and delamination are inhibited or reduced to improve reliability, and in which the potential range of designs is expanded for the inner circuitry of circuit boards and the inductance is reduced. The invention is a connecting... Agent: Smith, Gambrell & Russell

20090273072 - Semiconductor device and method for manufacturing the same: Disclosed is a semiconductor device eliminated of the effect of an adhesive used in assembling upon the semiconductor chip. According to the semiconductor device, the semiconductor device includes a board, a semiconductor chip provided on and contacting with the board, and a plurality of wires each having both ends firmly... Agent: Sughrue Mion, PLLC

20090273075 - Semiconductor device and manufacturing of the semiconductor device: A semiconductor device. In one embodiment the device includes a carrier. A first material is deposited on the carrier. The first material has an elastic modulus of less than 100 MPa. A semiconductor chip is placed over the first material. A second material is deposited on the semiconductor chip, the... Agent: Dicke, Billig & Czaja

20090273076 - Tape for heat dissipating member, chip on film type semiconductor package including heat dissipating member, and elctronic apparatus including the same: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface... Agent: Harness, Dickey & Pierce, P.L.C

20090273077 - Multi-lid semiconductor package: A multi-lid semiconductor package includes one or more die disposed on a substrate, an interconnect disposed on the substrate, one or more die lids, a die thermal interface between the one or more die and the corresponding die lid or lids, one or more substrate lids, and a substrate interface... Agent: Osha Liang L.L.P./sun

20090273080 - Display device and manufacturing method of the same: A display device includes a drive circuit chip, and a substrate on which the drive circuit chip is mounted. The drive circuit chip includes a semiconductor substrate, an insulation layer, a first conductive layer and a second conductive layer formed of metal between the semiconductor substrate and the insulation layer,... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090273078 - Electronic packages: Assemblies involving integrated circuit dies (e.g. packaged integrated circuits) and packaged dies electrically connected to circuit boards at times mechanically fail at conducting pads used for electrical interconnection. Such failure is mitigated by underlying appropriate pads with a compliant region having specific characteristics.... Agent: Mendelsohn, Drucker, & Associates, P.C.

20090273079 - Semiconductor package having passive component bumps: A semiconductor package includes contact bumps configured as passive circuit components. One or more contact bumps of the semiconductor package may be formed or configured as pull-up resistors, pull-down resistors, capacitors or inductors.... Agent: Warren A. Sklar (soer) Renner, Otto, Boisselle & Sklar, LLP

20090273081 - Pad cushion structure and method of fabrication for pb-free c4 integrated circuit chip joining: A controlled collapse chip connection (C4) method and integrated circuit structure for lead (Pb)-free solder balls with stress relief to the underlying insulating layers of the integrated circuit chip by deposing soft thick insulating cushions beneath the solder balls and connecting the metallization of the integrated circuit out-of-contact of the... Agent: Edward W. Brown

20090273082 - Methods and designs for localized wafer thinning: Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no... Agent: Kenneth E. Horton Kirton & Mcconkle

20090273083 - Electrically conductive fluid interconnects for integrated circuit devices: Disclosed are embodiments of an electrically conductive fluid interconnect for coupling an integrated circuit (IC) device to a substrate. The IC device may be coupled to the substrate in a socketless manner or using a socket. The electrically conductive fluid interconnect may include, for example, a metal, an electrically conductive... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090273085 - Cusin/sin diffusion barrier for copper in integrated-circuit devices: The present invention relates to an integrated-circuit device that has at least one Copper-containing feature in a dielectric layer, and a diffusion-barrier layer stack arranged between the feature and the dielectric layer. The integrated-circuit device of the invention has a diffusion-barrier layer stack, which comprises, in a direction from the... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090273084 - Optically transparent wires for secure circuits and methods of making same: A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive... Agent: Schmeiser, Olsen & Watts

20090273086 - Method of reducing erosion of a metal cap layer during via patterning in semiconductor devices: During the patterning of via openings in sophisticated metallization systems of semi-conductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may be established to redistribute material of the underlying metal region to exposed sidewall portions of the conductive cap layer, thereby establishing a... Agent: Williams, Morgan & Amerson

20090273087 - Closed-loop sputtering controlled to enhance electrical characteristics in deposited layer: This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with metal oxide deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of a desired electrical property as a function of cathode... Agent: Marc P. Schuyler

20090273089 - Method for manufacturing semiconductor device and semiconductor device: A semiconductor device in which a conductor of a bit line may be made as large in thickness as possible to reduce resistance of the bit line and to reduce capacitance across the neighboring bit lines. The device includes a first interlayer film having a first contact metal part accommodated... Agent: Mcginn Intellectual Property Law Group, PLLC

20090273091 - Semiconductor device and metal line fabrication method of the same: Embodiments relate to a method for forming a wiring in a semiconductor device, that may include laminating a conductive layer for wiring formation on a semiconductor substrate, forming a photoresist layer pattern on the conductive layer, performing primary dry etching for the conductive layer after employing the photoresist layer pattern... Agent: Sherr & Vaughn, PLLC

20090273088 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device includes forming a metal word line additionally over a vertical transistor to obtain a multi-layered structure, thereby preventing degradation of the operating speed of the semiconductor device by preventing an increase of resistance of a damascene word line that connects a surrounding gate... Agent: Marshall, Gerstein & Borun LLP

20090273090 - Semiconductor device and method for manufacturing the same: Embodiments relate to a semiconductor device and a method for manufacturing the same. Embodiments may include forming a lower porous oxide layer on a semiconductor substrate having a conductive layer, forming a pyrolytic polymer layer on the lower porous oxide layer, forming an upper porous oxide layer on the pyrolytic... Agent: Sherr & Vaughn, PLLC

20090273092 - Semiconductor module having an interconnection structure: In a method for manufacturing a semiconductor module, a metal layer is formed on a support substrate. Then, first conductive posts and a first insulating layer are formed on the metal layer. The first insulating layer surrounds the sides of the first conductive posts. Then, second conductive posts are formed... Agent: Young & Thompson

20090273093 - Planar packageless semiconductor structure with via and coplanar contacts: A semiconductor device includes a substrate having a first side and a second side and an epitaxial layer disposed over the second side. The device also includes a conductive via extending through the epitaxial layer to the second side and comprising a conductive contact; and a bond pad disposed over... Agent: Kathy Manke Avago Technologies Limited

20090273096 - High density memory device manufacturing using isolated step pads: An electronic device includes multiple IC dies stacked in an offset stacking arrangement on a substrate. Each IC die includes electrically isolated step pads that facilitates transmitting a dedicated signal between a (beginning) substrate bonding pad and a selected (terminal) contact pad of any die by way of short bonding... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way

20090273094 - Integrated circuit package on package system: An integrated circuit package on package system including: forming a first substrate assembly; forming a second substrate, having an auxiliary access port, supported by the first substrate assembly; exposing an integrated circuit die through the auxiliary access port; and coupling an external integrated circuit on the second substrate.... Agent: Law Offices Of Mikio Ishimaru

20090273095 - Rectangular-shaped controlled collapse chip connection: A rectangular-shaped controlled collapse chip connection (C4) is described. In one embodiment, there is a semiconductor chip package that comprises a semiconductor chip package substrate and a semiconductor chip having a plurality of rectangular-shaped C4 contacts attached thereto that connect the semiconductor chip to the semiconductor chip package substrate. The... Agent: Hoffman Warnick LLC

20090273098 - Enhanced architectural interconnect options enabled with flipped die on a multi-chip package: A particular chip is designed having a first variant (front side connected chip) of the chip and a second variant (back side connected chip). The first variant of the chip is attached to a carrier. The second variant of the chip is attached to the carrier inverted relative to the... Agent: Robert R. Williams IBM Corporation

20090273097 - Semiconductor component with contact pad: A structure and method of forming low cost bond pads is described. In one embodiment, the invention includes depositing an insulating layer over a last metal line of a substrate and forming an opening in the insulating layer. A colloid is printed over the insulating layer and fills the opening... Agent: Slater & Matsil, L.L.P.

20090273101 - Apparatus and method for preventing configurable system-on-a-chip integrated circuits from becoming i/o limited: An integrated circuit containing multiple modules coupled to a pad via a multiplexer. The modules are selectively coupled to the pad by the multiplexer to provide integrated circuit function flexibility with a limited number of pads. A multiplexer select signal determines which module or clock circuit is coupled by the... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090273100 - Integrated circuit having interleaved gridded features, mask set and method for printing: A method (300) for fabricating an integrated circuit includes the step of providing a substrate having a semiconductor surface (305). For at least one masking level (e.g. gate electrode, contact or via) of the integrated circuit, a mask pattern for the masking level is partitioned into a first mask and... Agent: Texas Instruments Incorporated

20090273099 - Semiconductor integrated circuit: On a semiconductor chip in a semiconductor integrated circuit, a plurality of circuit cells each of which has a pad are formed along a first chip side of the semiconductor chip. Among the plurality of circuit cells, one or more circuit cells at least in the vicinity of an end... Agent: Mcdermott Will & Emery LLP

20090273102 - Semiconductor substrate and method for manufacturing the same: A trench 11 is formed in an alignment region of an N+-type substrate 1. This trench 11 is used to leave voids 3 after the formation of an N−-type layer 2. Then, the voids 3 formed in the N+-type substrate 1 can be used as an alignment mark. Thus, such... Agent: Duane Morris LLP - Ny Patent Department

20090267042 - Integrated circuit and method of manufacturing an integrated circuit: According to one embodiment of the present invention, an integrated circuit including a plurality of resistance changing memory cells is provided. Each memory cell includes: a semiconductor substrate; a select device arranged within the semiconductor substrate; and a memory element being arranged above the semiconductor substrate. The select device is... Agent: Slater & Matsil, L.L.P.

20090267043 - Phase change memory device resistant to stack pattern collapse and a method for manufacturing the same: A phase change memory device resistant to stack pattern collapse is presented. The phase change memory device includes a silicon substrate, switching elements, heaters, stack patterns, bit lines and word lines. The silicon substrate has a plurality of active areas. The switching elements are connected to the active areas. The... Agent: Ladas & Parry LLP

20090267046 - Memory structure with a programmable resistive element and its manufacturing process: A memory structure has an access transistor connected in series with a programmable resistive element, wherein the programmable resistive element comprises on a semiconductor substrate; an insulated layer with a cavity comprising: a first layer lining the lateral surfaces and the bottom of the said cavity and impermeable to the... Agent: Seed Intellectual Property Law Group PLLC

20090267044 - Phase change memory device having a bent heater and method for manufacturing the same: A phase change memory device includes heaters which are formed in their respective memory cells and vertically positioned stack patterns having phase change layers and top electrodes which are formed to come into contact with the heaters. The heaters have horizontal cross-sectional bent shapes which can have any number of... Agent: Ladas & Parry LLP

20090267045 - Phase change memory device having heaters and method for manufacturing the same: A phase change memory device includes switching elements formed on a substrate that includes a cell region and a peripheral region. Heat sinks are formed on the switching elements. Heaters are formed on the heat sink and a phase change layer is formed on the heaters.... Agent: Ladas & Parry LLP

20090267047 - Semiconductor memory device and manufacturing method thereof: The present invention can promote the large capacity, high performance and high reliability of a semiconductor memory device by realizing high-performance of both the semiconductor device and a memory device when the semiconductor memory device is manufactured by stacking a memory device such as ReRAM or the phase change memory... Agent: Miles & Stockbridge PC

20090267050 - Method of preparing cadmium sulfide nanocrystals emitting light at multiple wavelengths, and cadmium sulfide nanocrystals prepared by the method: A cadmium sulfide nanocrystal, wherein the cadmium sulfide nanocrystal shows maximum luminescence peaks at two or more wavelengths and most of the atoms constituting the nanocrystal are present at the surface of the nanocrystal to form defects.... Agent: Cantor Colburn, LLP

20090267049 - Plasmon enhanced nanowire light emitting diode: A nanowire light emitting diode (LED) and method of emitting light employ a plasmonic mode. The nanowire LED includes a nanowire having a semiconductor junction, a shell layer coaxially surrounding the nanowire, and an insulating layer, which is plasmonically thin, isolating the shell layer from the nanowire. The shell layer... Agent: Hewlett-packard Company Intellectual Property Administration

20090267048 - Semiconductor light emitting element: Light extraction efficiency of a semiconductor light-emitting element is improved. A buffer layer, an n-type GaN layer, an InGaN emission layer, and a p-type GaN layer are laminated on a sapphire substrate in a semiconductor light-emitting element. A ZnO layer functioning as a transparent electrode is provided on the p-type... Agent: Cantor Colburn, LLP

20090267051 - Method of preparing quantum dot-inorganic matrix composites: A method for preparing a quantum dot-inorganic matrix composite includes preparing an inorganic matrix precursor solution containing one or more quantum dot precursors, spin-coating the precursor solution on a substrate to form an inorganic matrix thin film, and heating the inorganic matrix thin film to form an inorganic matrix, while... Agent: Cantor Colburn, LLP

20090267052 - Layer transfer of low defect sige using an etch-back process: A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one... Agent: Scully, Scott, Murphy & Presser, P.C.

20090267053 - Carbon-nanotube based opto-electric device: A carbon nano-tube based photoelectric device includes a substrate and a carbon nanotube (CNT) over the substrate. The CNT comprises a first end and a second end, wherein the CNT has a CNT work function. A high work-function electrode over the substrate is in electric contact with the first end... Agent: Xin Wen

20090267054 - Apparatus, method and system for reconfigurable circuitry: The present invention relates to reconfigurable circuitry, and more particularly to the reconfiguration of the characteristics of materials used in the formation of electronic circuitry as the result of applied external influences. Exemplary embodiments of the present invention provide an apparatuses, methods, electronic devices and computer program products that include... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20090267061 - Carbonyl-functionalized thiophene compounds and related device structures: Carbonyl-functionalized oligo/polythiophene compounds, and related semiconductor components and related device structures.... Agent: K&l Gates LLP

20090267056 - Memory cell: A memory cell comprising a metal-insulator-semiconductor (MIS) structure is disclosed using a homogeneous carrier trapping layer interposed between a semiconductor layer and the gate electrode of a transistor structure so that the operation voltage is reduced and the manufacturing is simplified with lowered cost. The MIS structure comprises: a gate... Agent: Wpat, PC

20090267057 - Organic field-effect transistor for sensing applications: Field-effect transistor comprising a gate electrode layer, a first dielectric layer, a source electrode, a drain electrode, an organic semiconductor and a second dielectric layer, wherein the first dielectric layer is located on the gate electrode layer, the source electrode, the drain electrode and the organic semiconductor are located above... Agent: Philips Intellectual Property & Standards

20090267059 - Organic light emitting device: An organic light emitting device is disclosed. The organic light emitting device includes a substrate, a display positioned on the substrate, and a dummy pattern positioned at an edge of the display. The display includes a plurality of subpixels each including a first electrode, an emissive unit including at least... Agent: Birch Stewart Kolasch & Birch

20090267060 - Polymer wrapped carbon nanotube near-infrared photoactive devices: A photoactive device includes a photoactive region disposed between and electrically connected to two electrodes where the photoactive region includes a first organic photoactive layer comprising a first donor material and a second organic photoactive layer comprising a first acceptor material. The first donor material contains photoactive polymer-wrapped carbon nanotubes... Agent: Duane Morris LLP - Princeton

20090267058 - Solution-processed inorganic films for organic thin film transistors: A method for fabricating a sol-gel film composition for use in a thin film transistor is disclosed. The method BB includes fabricating the sol-gel dielectric composition by solution processing at a temperature in the range 60° C. to 225° C. The sol-gel film made by the method, and an organic... Agent: Dickstein Shapiro LLP

20090267055 - Transistor, method for manufacturing same, and semiconductor device comprising such transistor: m

20090267065 - Semiconductor light emitting element and method for manufacturing the same: A ZnO-based semiconductor light emitting element includes a ZnO-based semiconductor layer formed on a rectangular sapphire A-plane substrate having a principal surface lying in the A-plane {11-20}. The substrate has a thickness of 50 to 200 μm and is surrounded by two parallel first side edges forming an angle in... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090267063 - Semiconductor light-emitting device and method of manufacturing the same: Disclosed is a semiconductor light-emitting device wherein a pn junction is formed by forming, as a p-type layer (11), a semiconductor thin film which is composed of a ZnO compound doped with nitrogen on an n-type ZnO bulk single crystal substrate (10) whose resistance is lowered by being doped with... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090267064 - Semiconductor thin film and method for manufacturing same, and thin film transistor: The present invention provides a semiconductor thin film which can be manufactured at a relatively low temperature even on a flexible resin substrate. As a semiconductor thin film having a low carrier concentration, a high Hall mobility and a large energy band gap, an amorphous film containing zinc oxide and... Agent: Millen, White, Zelano & Branigan, P.C.

20090267062 - Zinc oxide based compound semiconductor device: There is provided a zinc oxide based compound semiconductor device which, even when a semiconductor device is formed by forming a lamination portion having a hetero junction of ZnO based compound semiconductor layers, does not cause any rise in a drive voltage while ensuring p-type doping, and, at the same... Agent: Rabin & Berdo, PC

20090267066 - Photoelectric conversion device and method for manufacturing the same: To provide a photoelectric conversion device with improved photoelectric conversion characteristics and cost competitiveness. A photoelectric conversion device including a semiconductor junction has a semiconductor layer in which a needle-like crystal is made to grow over an impurity semiconductor layer. The impurity semiconductor layer is formed of a microcrystalline semiconductor... Agent: Fish & Richardson P.C.

20090267069 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a p-type TFT having a first semiconductor layer, and an n-type TFT having a second semiconductor layer. A tilted portion, which is widened toward the insulating substrate side, is formed in at least a part of an outer edge portion of the first semiconductor layer. A... Agent: Birch Stewart Kolasch & Birch

20090267067 - Thin film transistor: A thin film transistor has a gate electrode; a gate insulating layer provided so as to cover the gate electrode layer; a pair of impurity semiconductor layers forming source and drain regions which is provided so that at least part of each of them overlaps the gate electrode layer and... Agent: Nixon Peabody, LLP

20090267068 - Thin film transistor: The thin film transistor includes a gate insulating layer covering a gate electrode, over a substrate having an insulating surface; a semiconductor layer forming a channel formation region, in which a plurality of crystal regions is included in an amorphous structure; an impurity semiconductor layer imparting one conductivity type which... Agent: Nixon Peabody, LLP

20090267072 - Electro-optical device and method for manufacturing the same: Using thin film transistors (TFTs), an active matrix circuit, a driver circuit for driving the active matrix circuit or the like are formed on one substrate. Circuits such as a central processing unit (CPU) and a memory, necessary to drive an electric device, are formed using single crystalline semiconductor integrated... Agent: Eric Robinson

20090267070 - Multilayer image sensor structure for reducing crosstalk: An image sensor pixel includes a substrate, an epitaxial layer, and a light collection region. The substrate is doped to have a first conductivity type. The epitaxial layer is disposed over the substrate and doped to have a second conductivity type opposite of the first conductivity type. The light collection... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090267071 - Pixel layout structure for raising capability of detecting amorphous silicon residue defects and method for manufacturing the same: Disclosed is a pixel layout structure capable of increasing the capability of detecting amorphous silicon (a-Si) residue defects and a method for manufacturing the same. Wherein, an a-Si dummy layer is disposed on either one side or both sides of each data line. The design of such an a-Si dummy... Agent: Sinorica, LLC

20090267073 - Semiconductor device and method of manufacturing the same: The present invention improves the aperture ratio of a pixel of a reflection-type display device or a reflection type display device without increasing the number of masks and without using a blackmask. A pixel electrode (167) is arranged so as to partially overlap a source wiring (137) for shielding the... Agent: Fish & Richardson P.C.

20090267076 - El display device and method for manufacturing the same: Plurality of pixels (102) are arranged on the substrate. Each of the pixels (102) is provided with an EL element which utilizes as a cathode a pixel electrode (105) connected to a current control TFT (104). On a counter substrate (110), a light shielding film (112) is disposed at the... Agent: Cook Alex Ltd

20090267075 - Oganic thin film transistor and pixel structure and method for manufacturing the same and display panel: A method of manufacturing an organic thin film transistor is described. A patterned insulating layer having an opening therein is formed on a substrate. A gate is formed in the opening of the insulating layer, and a gate insulating layer is formed on the gate. A conductive material layer is... Agent: Jianq Chyun Intellectual Property Office

20090267074 - Organic light emitting display device and method of manufacturing the same: A organic light emitting display device includes a thin film transistor (TFT) having a gate electrode, a source electrode and a drain electrode which are insulated from the gate electrode, and a semiconductor layer which is insulated from the gate electrode and which contacts each of the source electrode and... Agent: Stein Mcewen, LLP

20090267077 - Semiconductor element, organic transistor, light-emitting device, and electronic device: It is an object of the present invention to provide an organic transistor having a low drive voltage. It is also another object of the present invention to provide an organic transistor, in which light emission can be obtained, which can be manufactured simply and easily. According to an organic... Agent: Fish & Richardson P.C.

20090267078 - Enhancement mode iii-n hemts: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the... Agent: Fish & Richardson P.C.

20090267079 - Externally configurable integrated circuits: A die comprising two or more active electronic components is provided. The active electronic components are capable of being interconnected using interconnections external to the die. The die may be encased within a package, and the active electronic components may be interconnected using interconnections external to the package. By interconnecting... Agent: Wolf Greenfield & Sacks, P.C.

20090267080 - Semiconductor device: It includes: a semiconductor element (2) placed on a substrate (1); peripheral circuit sections (30) and (40) placed on the substrate (1) and connected with the semiconductor element (2); an electrode (30e) provided in the peripheral circuit section (30) and grounded; an electrode (30s) for grounding connected to a metal... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267082 - Semiconductor device and manufacturing method of the same: A semiconductor device includes: a semiconductor element having a first surface and a second surface; a first electrode disposed on the first surface of the element; a second electrode disposed on the second surface of the element; and an insulation film covers a part of the first electrode, the first... Agent: Posz Law Group, PLC

20090267081 - Semiconductor device and method for fabrication thereof: A semiconductor device includes a substrate formed of a single crystal. a silicon carbide layer disposed on a surface of the single crystal substrate and an intermediate layer disposed on a surface of the silicon carbide layer and formed of a Group III nitride semiconductor, wherein the silicon carbide layer... Agent: Sughrue Mion, PLLC

20090267083 - Trenched substrate for crystal growth and wafer bonding: A substrate for a light emitting diode (LED) can have one or more trenches formed therein so as to mitigate stress build up within the substrate due to mismatched thermal coefficients of expansion between the substrate and layers of material, e.g., semiconductor material, formed thereon. In this manner, the likelihood... Agent: Haynes And Boone, LLPIPSection

20090267084 - Integrated circuit with wireless connection: An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and... Agent: Edell, Shapiro & Finnan, LLC

20090267085 - Led package having an array of light emitting cells coupled in series: Disclosed is a light emitting diode (LED) package having an array of light emitting cells coupled in series. The LED package comprises a package body and an LED chip mounted on the package body. The LED chip has an array of light emitting cells coupled in series. Since the LED... Agent: H.c. Park & Associates, PLC

20090267089 - Light emitting device having light emitting elements: A light-emitting device operating on a high drive voltage and a small drive current. LEDs (1) are two-dimensionally formed on an insulating substrate (10) of e.g., sapphire monolithically and connected in series to form an LED array. Two such LED arrays are connected to electrodes (32) in inverse parallel. Air-bridge... Agent: H.c. Park & Associates, PLC

20090267087 - Low resistance wiring structure and liquid crystal display device using the same: A low-resistance wiring structure and a liquid crystal display are disclosed. The liquid crystal display includes a first substrate; a thin film transistor (TFT) formed on the first substrate and formed of a gate wiring, a data wiring and a semiconductor layer; and a second substrate attached to the first... Agent: Brinks Hofer Gilson & Lione

20090267088 - Systems, devices and methods of broadband light sources with tunable spectrum: Broadband light source systems, devices, and methods with a tunable spectrum are described by multiplexing a plurality of light sources, such as LEDs, with thin-film filters or diffraction gratings. A plurality of light sources with different or same wavelengths are multiplexed together to construct a combined broadband light source. A... Agent: Intellectual Equity

20090267086 - Thermal management for led: A method and system for removing heat from an LED facilitates the fabrication of LEDs having enhanced brightness. A thermally conductive interposer can be attached to the top of the LED. Heat can flow through the top of the LED and into the interposer. The interposer can carry the heat... Agent: Haynes And Boone, LLPIPSection

20090267090 - Color mixing light emitting diode device: An exemplary color mixing light emitting diode (LED) device includes a substrate, LED dies, an encapsulating body, and a light mixing structure. The substrate has a main surface. The LED dies are arranged adjacent the main surface of the substrate. The light mixing structure is arranged adjacent an outer portion... Agent: PCe Industry, Inc. Att. Steven Reiss

20090267091 - Semiconductor light emitting device: A semiconductor light emitting device includes a substrate 11 including a group III-V nitride semiconductor; a first-conductivity-type layer 12 formed on the substrate 11, the first-conductivity-type layer including a plurality of group III-V nitride semiconductor layers of first conductivity type; an active layer 13 formed on the first semiconductor layer... Agent: Mcdermott Will & Emery LLP

20090267101 - Display including light emitting element, beam condensing element and diffusing element: A display includes pixels each of which contains a light emitting element and which are arranged in a matrix form, a light transmitting insulating layer which includes a back surface facing the light emitting element and a front surface as a light output surface, a beam-condensing element which is arranged... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267099 - Led light source and chromaticity adjustment method for led light source: There is provided an LED light source whose chromaticity can be adjusted easily without changing its outer shape and suffering damage in the process of chromaticity adjustment. An LED light source includes an LED device, a fluorescent material that absorbs and wavelength-converts a portion of light emitted from the LED... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090267093 - Light emitting device: A light emitting device includes a light emitting diode chip, a heat conductive plate mounting thereon the light emitting diode chip, a sub-mount member disposed between said light emitting diode chip and said heat conductive plate, a dielectric substrate stacked on the heat conductive plate and being formed with a... Agent: Greenblum & Bernstein, P.L.C

20090267094 - Light emitting diode and method for manufacturing the same: The present invention relates to a light emitting diode and a method for manufacturing the same. The light emitting diode includes a base, a light emitting chip on the base, a light permeable encapsulation encapsulating the light emitting chip to the base. The encapsulation defines a plurality of apertures extending... Agent: PCe Industry, Inc. Att. Steven Reiss

20090267102 - Light emitting diode package structure and method for fabricating the same: A light emitting diode (LED) package structure includes a carrier, a first protrusion, a LED chip, and an adhesion layer. The first protrusion is disposed on the carrier and has a first opening to expose the carrier. The LED chip is disposed in the first opening on the carrier, and... Agent: Jianq Chyun Intellectual Property Office

20090267092 - Light-emitting device: A light-emitting device of the present invention includes: a semiconductor layer 1 including a light-emitting layer 12; a recess/projection portion 14 including recesses and projections formed in a pitch larger than a wavelength of light emitted from the light-emitting layer 12, the recess/projection portion 14 being formed in a whole... Agent: Greenblum & Bernstein, P.L.C

20090267095 - Light-emitting device with reflection layer and structure of the reflection layer: The present invention provides a light-emitting device with a reflection layer and the structure of the reflection layer. The reflection layer comprises a variety of dielectric materials. The reflection layer includes a plurality of dielectric layers. The materials of the plurality of dielectric layers have two or more types with... Agent: Wei-kang Cheng

20090267096 - Luminous devices, packages and systems containing the same, and fabricating methods thereof: The present invention is directed to a vertical-type luminous device and high through-put methods of manufacturing the luminous device. These luminous devices can be utilized in a variety of luminous packages, which can be placed in luminous systems. The luminous devices are designed to maximize light emitting efficiency and/or thermal... Agent: Mills & Onello LLP

20090267097 - Method of fabricating photoelectric device of group iii nitride semiconductor and structure thereof: A method of fabricating a photoelectric device of Group III nitride semiconductor comprises the steps of: forming a first Group III nitride semiconductor layer on a surface of an original substrate; forming a patterned epitaxial-blocking layer on the first Group III nitride semiconductor layer; forming a second Group III nitride... Agent: Wpat, PC Intellectual Property Attorneys

20090267100 - Nitride-based semiconductor device and method of manufacturing the same: A nitride-based semiconductor device includes a substrate, a first step portion formed on a main surface side of a first side end surface of the substrate, a second step portion formed on the main surface side of a second side end surface substantially parallel to the first side end surface... Agent: Ditthavong Mori & Steiner, P.C.

20090267098 - Semiconductor light emitting device: Disclosed is a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer comprising a plurality of recesses on the active layer.... Agent: Birch Stewart Kolasch & Birch

20090267103 - Gallium nitride-based compound semiconductor light-emitting device and production method thereof: The invention provides a gallium nitride based compound semiconductor light emitting device with excellent light extracting efficiency and its production method. A light emitting device, obtained from a gallium nitride based compound semiconductor, includes a substrate; a n-type semiconductor layer 13, a light emitting layer 14, and a p-type semiconductor... Agent: Sughrue Mion, PLLC

20090267105 - Led device with embedded top electrode: An LED device and a method of manufacturing, including an embedded top electrode, are presented. The LED device includes an LED structure and a top electrode. The LED structure includes layers disposed on a substrate, including an active light-emitting region. A top layer of the LED structure is a top... Agent: Slater & Matsil, L.L.P.

20090267108 - Light emitting diode chip package and method of making the same: The LED chip package of the present invention uses a semiconductor substrate as package substrate, which improves heat dissipation. Also, the LED chip package is incorporated with a planarization structure, which renders the LED chip and the substrate a substantially planar surface, thereby making formation of a planar patterned conductive... Agent: North America Intellectual Property Corporation

20090267104 - Light-emitting diode package: An LED package including a lead-frame, at least an LED chip and an encapsulant is provided. The lead-frame has a roughened surface, the LED chip is disposed on the lead-frame and electrically connected to the lead-frame, and the roughened surface is suitable to scatter the light emitted from the LED... Agent: Jianq Chyun Intellectual Property Office

20090267107 - Optoelectronic semiconductor component: An optoelectronic semiconductor component includes a basic body, at least one semiconductor chip arranged thereon, and an encapsulation embedding the at least one semiconductor chip and composed of a radiation-transmissive material with scattering particles. A radiation-transmissive covering layer with an absorber is applied to the encapsulation.... Agent: Slater & Matsil, L.L.P.

20090267106 - Semiconductor light emitting device: Embodiments provides a semiconductor light emitting device, which comprises a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, a second conductive semiconductor layer under the active layer, a second electrode layer under the second conductive semiconductor layer, an insulator on one side of the second... Agent: Birch Stewart Kolasch & Birch

20090267109 - Compound semiconductor light-emitting device and method for manufacturing the same: A compound semiconductor light-emitting device which includes an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer, that are made of a compound semiconductor, formed on a substrate, the n-type semiconductor layer and the p-type semiconductor layer are stacked so as to interpose the light-emitting layer therebetween, a... Agent: Sughrue Mion, PLLC

20090267110 - Integrated low leakage schottky diode: An integrated low leakage Schottky diode has a Schottky barrier junction proximate one side of an MOS gate with one end of a drift region on an opposite side of the gate. Below the Schottky metal and the gate oxide is a RESURF structure of an N− layer over a... Agent: Hiscock & Barclay, LLP

20090267111 - Mosfet with integrated field effect rectifier: A modified MOSFET structure comprises an integrated field effect rectifier connected between the source and drain of the MOSFET to shunt current during switching of the MOSFET. The integrated FER provides faster switching of the MOSFET due to the absence of injected carriers during switching while also decreasing the level... Agent: Law Offices Of James E. Eakin

20090267112 - Semiconductor device and method of forming a semiconductor device: A semiconductor device arrangement comprises a semiconductor device and an injector device. The semiconductor device comprises a first current electrode region of a first conductivity type, a second current electrode region of the first conductivity type, a drift region between the first and the second current electrode regions, and at... Agent: Freescale Semiconductor, Inc. Law Department

20090267114 - Field effect transistor: A field effect transistor 100 includes a group III-V nitride semiconductor layer structure containing a hetero junction, a source electrode 105 and a drain electrode 106 formed on the group III-V nitride semiconductor layer structure to be spaced apart from each other; a gate electrode 110 arranged between the source... Agent: Young & Thompson

20090267113 - Semiconductor device and method of manufacturing the same: A semiconductor device has a semiconductor base of a first conductivity type; a hetero semiconductor region in contact with the semiconductor base; a gate electrode adjacent to a portion of a junction between the hetero semiconductor region and the semiconductor base across a gate insulating film; a source electrode connected... Agent: Foley And Lardner LLP Suite 500

20090267115 - Club extension to a t-gate high electron mobility transistor: A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer... Agent: Carmen Patti Law Group , LLC

20090267116 - Wide bandgap transistors with multiple field plates: A transistor comprising a plurality of active semiconductor layers on a substrate, with source and drain electrodes in contact with the semiconductor layers. A gate is formed between the source and drain electrodes and on the plurality of semiconductor layers. A plurality of field plates are arranged over the semiconductor... Agent: Koppel, Patrick, Heybl & Dawson

20090267117 - Enhanced stress for transistors: A transistor disposed on a substrate includes a gate, spacers on gate sidewalls, and diffusion regions adjacent to the gate. Silicide contacts on the diffusion regions are displaced from the spacers by a distance G. Stressors may be provided in the diffusion region to induce a first stress in the... Agent: HorizonIPPte Ltd

20090267118 - Method for forming carbon silicon alloy (csa) and structures thereof: Methods for forming carbon silicon alloy (CSA) and structures thereof are disclosed. The method provides improvement in substitutionality and deposition rate of carbon in epitaxially grown carbon silicon alloy layers (i.e., substituted carbon in Si lattice). In one embodiment of the disclosed method, a carbon silicon alloy layer is epitaxially... Agent: Hoffman Warnick LLC

20090267119 - Semiconductor device and method of manufacturing semiconductor device: The semiconductor device includes a silicon substrate having a channel region, a gate electrode formed over the channel region, buried semiconductor regions formed in a surface of the silicon substrate on both sides of the gate electrode, for applying to the surface of the silicon substrate a first stress in... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090267120 - Image detection apparatus and methods: MOS imaging pixels are described. The MOS imaging pixels may comprise bootstrapped source followers, having their bodies connected to their sources. The source followers of the MOS imaging pixels may be used to buffer a signal indicative of an amount of radiation incident on the pixel. MOS imagers are also... Agent: Wolf Greenfield & Sacks, P.C.

20090267121 - Solid-state image pickup device: A solid-state image pickup device is provided which includes a substrate; a transistor formed on the substrate; a photoelectric conversion element including a first electrode connected to a drain or a source of the transistor, a semiconductor layer stacked on the first electrode, and a second electrode stacked on the... Agent: Oliff & Berridge, PLC

20090267123 - Semiconductor device: A semiconductor device includes: a semiconductor substrate; a plurality of transistors on the semiconductor substrate, each of the transistors has a source and drain region; an interlayer insulating film on the semiconductor substrate and the plurality of transistors; and at least three capacitors on the interlayer insulation film, each of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267122 - Semiconductor device and method of manufacturing the semiconductor device: A semiconductor device has a substrate, an insulator, an yttrium oxide film, a ferroelectric film (STN film), and an upper electrode.... Agent: Foley And Lardner LLP Suite 500

20090267124 - Integrated circuit having efficiently packed decoupling capacitors: An integrated circuit includes a substrate having a semiconducting surface (605) and a plurality of standard cells arranged in a plurality of rows including at least a first row (610) and a second row (615) immediately above the first row. The first row (610) include at least a first decap... Agent: Texas Instruments Incorporated

20090267125 - Semiconductor device and method of manufacturing the same: An isolation region comprises a step structure comprising a step surface that is perpendicular to a depth direction, an upper isolation region and a lower isolation region. An RC transistor is enclosed by the isolation region.... Agent: Young & Thompson

20090267126 - Recess channel transistor: A recess channel transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate, which defines an active area; a gate trench in the active area, wherein the gate trench includes a round lower portion; a recessed gate embedded in the gate trench with a spherical gate portion... Agent: North America Intellectual Property Corporation

20090267127 - Single poly nvm devices and arrays: A single-poly non-volatile memory includes a PMOS select transistor (210) formed with a select gate (212), and P+ source and drain regions (211, 213) formed in a shared n-well region (240), a serially connected PMOS floating gate transistor (220) formed with part of a p-type floating gate layer (222) and... Agent: Hamilton & Terrile, LLP - Freescale

20090267128 - Three dimensional stacked nonvolatile semiconductor memory: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267129 - Dielectric multilayer structures of microelectronic devices and methods for fabricating the same: A dielectric multilayer structure of a microelectronic device, in which a leakage current characteristic and a dielectric constant are improved, is provided in an embodiment. The dielectric multilayer structure includes a lower dielectric layer, which is made of amorphous silicate (M1-xSixOy) or amorphous silicate nitride (M1-xSixOyNz), and an upper dielectric... Agent: Marger Johnson & Mccollom, P.C.

20090267132 - Gate structures in semiconductor devices: A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion preventing layer pattern on the metal ohmic layer pattern, an amorphous layer pattern on the diffusion preventing layer... Agent: Myers Bigel Sibley & Sajovec

20090267131 - Nonvolatile semiconductor memory device and method of manufacturing the same: To reduce capacitance between each adjacent two word lines in a semiconductor memory device, a first insulating film is formed, with a first gate insulating film thereunder, in an interstice between gates respectively of each adjacent two memory transistors, and in an interstice between a gate of a selective transistor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267130 - Structure and process integration for flash storage element and dual conductor complementary mosfets: A method is provided for simultaneously fabricating a flash storage element, an NFET and a PFET having metal gates with different workfunctions. A first gate metal layer of the NFET having a first workfunction is deposited simultaneously with a first metal layer for forming the floating gate of the flash... Agent: International Business Machines Corporation Dept. 18g

20090267133 - Flash memory device and method for fabricating the same: A flash memory device includes a source region formed in an active region of a semiconductor substrate; a recessed region formed in the active region on either side of the source region, the recessed region including a recess surface having sidewalls; floating gates formed at the sidewalls of the recess... Agent: Mckenna Long & Aldridge LLP

20090267137 - Method of manufacturing semiconductor device having notched gate mosfet: Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized... Agent: Mills & Onello LLP

20090267135 - Non-volatile semiconductor storage device and method of manufacturing the same: A non-volatile semiconductor storage device includes a first layer and a second layer. The first layer includes: a plurality of first conductive layers extending in parallel to a substrate and laminated in a direction perpendicular to the substrate; a first insulation layer formed on an upper layer of the plurality... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267134 - Nonvolatile semiconductor memory apparatus: A nonvolatile semiconductor memory apparatus includes: a memory element including: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate located between the source region and the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090267136 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device having a memory cell region and a peripheral circuit region, and a method of manufacturing such a semiconductor memory device, are proposed, in which trench grooves are formed to be shallow in the memory cell region in order to improve the yield, and trench grooves are... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267138 - Semiconductor device and method for manufacturing the same: A charge trap type non-volatile memory device has memory cells formed on a silicon substrate at a predetermined interval via an element isolation trench along a first direction in which word lines extend. Each of the memory cells has a tunnel insulating film formed on the silicon substrate, a charge... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090267139 - Three dimensional stacked nonvolatile semiconductor memory: A three dimensional stacked nonvolatile semiconductor memory according to examples of the present invention includes a memory cell array comprised of first and second blocks disposed side by side and a driver disposed between the first and second blocks. At least two conductive layers having the same structure as that... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267140 - Mosfet structure with guard ring: A trench Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) structure with guard ling, includes: a substrate including an epi layer region on the top thereof a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which are connected to respective... Agent: Birch Stewart Kolasch & Birch

20090267141 - Method for fabricating silicon carbide vertical mosfet devices: A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a... Agent: General Electric Company Global Research

20090267142 - Semiconductor device and method of manufacturing same: A semiconductor device according to the present invention includes a plurality of trenches, a plurality of gate electrodes, a plurality of diffusion Layers, an insulating film, an electrode layer, a plurality of first concave portions and a plurality second concave portions formed in the electrode layer, a solder layer, and... Agent: Young & Thompson

20090267143 - Trenched mosfet with guard ring and channel stop: A trenched MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with a guard ring and a channel stop, including: a substrate including an epi layer region on the top thereof; a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which... Agent: Birch Stewart Kolasch & Birch

20090267144 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: an n-type first well diffusion layer; an n-type second well diffusion layer; a p-type source diffusion layer; a p-type third well diffusion layer; a p-type drain diffusion layer; a gate insulating film; a gate electrode; a device isolation insulating film; and a buffer layer. The buffer... Agent: Mcdermott Will & Emery LLP

20090267145 - Mosfet device having dual interlevel dielectric thickness and method of making same: A method of forming a metal-oxide-semiconductor (MOS) device includes the following steps: forming a semiconductor layer of a first conductivity type having source and drain regions of a second conductivity type, a channel region and a lightly-doped drain region formed therein; forming a gate over the channel region proximate an... Agent: Texas Instruments Incorporated

20090267146 - Structure and method for semiconductor power devices: A semiconductor device includes a semiconductor-on-insulator region on a substrate. The semiconductor-on-insulator region includes a first semiconductor region overlying a dielectric region. The device includes an MOS transistor and a bipolar transistor. The MOS transistor has a drain region, a body region, and a source region in the first semiconductor... Agent: Townsend And Townsend And Crew, LLP

20090267147 - Esd protected rf transistor: The electronic device comprising a RF transistor (100) that is designed for a fundamental RF frequency and that is integrated with an electrostatic protection structure (250) with a further transistor (200). The transistors are suitably MOS transistors, with a gate, source and drain electrodes, and wherein the sources are coupled... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090267148 - Semiconductor integrated circuit devices: A semiconductor integrated circuit device may include: a substrate that includes a high-voltage device region and a low-voltage device region defined on the substrate; a first buried impurity layer formed in at least a portion of the high-voltage device region and coupled to a first voltage; a second buried impurity... Agent: Harness, Dickey & Pierce, P.L.C

20090267153 - Localized spacer for a multi-gate transistor: In one embodiment, the present invention includes a double gate transistor having a silicon fin formed on a buried oxide layer and first and second insulation layers formed on a portion of the silicon fin, where at least the second insulation layer has a pair of portions extending onto respective... Agent: Trop, Pruner & Hu, P.C.

20090267150 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device comprises: forming a gate pattern over a silicon active region and an insulating layer, which form a semiconductor substrate; removing the silicon active region exposed between the gate patterns; and filling a space between the gate patterns to form a plug.... Agent: Marshall, Gerstein & Borun LLP

20090267152 - Semiconductor device and method of manufacturing a semiconductor device: A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an... Agent: Larson Newman & Abel, LLP

20090267151 - Semiconductor device, electronic device, and manufacturing method thereof: To provide a semiconductor device in which resistance of a source region and a drain region of a thin film transistor is reduced and a short channel effect is suppressed, and a manufacturing method thereof. The semiconductor device includes a gate electrode which is formed over a first semiconductor layer... Agent: Nixon Peabody, LLP

20090267149 - Source/drain junction for high performance mosfet formed by selective epi process: In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched silicon layer. Source (S) and drain (D), as well as S/D extension features may similarly... Agent: International Business Machines Corporation Dept. 18g

20090267154 - Mos comprising substrate potential elevating circuitry for esd protection: An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p-layer (38) includes functional circuitry (24) formed on the p-layer (38) including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (24). At least one ESD protection cell (30; in more detail... Agent: Texas Instruments Incorporated

20090267155 - Semiconductor device and method for manufacturing the same: A semiconductor device has a semiconductor substrate, a semiconductor fin which is formed on the semiconductor substrate, which has a long side direction and a short side direction, and which has a carbon-containing silicon film including an impurity and a silicon film formed on the carbon-containing silicon film, a gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267156 - Device structures including dual-depth trench isolation regions and design structures for a static random access memory: Device structures and design structures for a static random access memory. The device structure includes a well of a first conductivity type in a semiconductor layer, first and second deep trench isolation regions in the semiconductor layer that laterally bound a device region in the well, and first and second... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090267157 - Method or manufacturing a semiconductor device and semiconductor device obtained by using such a method: The invention relates to a method of manufacturing a semiconductor device (10) comprising a semiconductor body (2) provided with a field effect transistor (3), wherein a polycrystalline silicon region (5) with a metal layer (6) deposited thereon is transformed into a metal suicide gate electrode (3D) so as to form... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090267159 - Semiconductor device: A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267158 - Semiconductor device and manufacturing process therefor: There is provided a semiconductor device in which deviation in a work function is prevented by a gate electrode having a uniform composition and which has excellent operation properties by effectively controlling a Vth. The semiconductor device comprises an NMOS transistor and a PMOS transistor with a common line electrode,... Agent: Young & Thompson

20090267160 - Semiconductor device and method for manufacturing the same: A semiconductor device comprises an anti-fuse element. The anti-fuse element includes a semiconductor substrate, a first gate insulating film, a first gate electrode, a high-concentration impurity region formed in the semiconductor substrate under the first gate electrode, and first source/drain regions provided in the semiconductor substrate on both sides of... Agent: Sughrue Mion, PLLC

20090267161 - Increasing body dopant uniformity in multi-gate transistor devices: Techniques and structures for increasing body dopant uniformity in multi-gate transistor devices are generally described. In one example, an electronic device includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate... Agent: Cool Patent, P.C. C/o Cpa Global

20090267162 - Method of manufacturing semiconductor device and semiconductor device: A method of manufacturing a semiconductor device comprises: forming a gate insulator on a substrate, the gate insulator including a high-dielectric film in whole or part; forming a first metal film on the gate insulator; forming a second metal film on the first metal film; and forming a reaction film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090267163 - Semiconductor device: According to the present invention, a semiconductor device having a field effect transistor is provided. The field effect transistor comprises a gate insulating film 2 formed on a semiconductor layer 1 and a gate electrode 5 formed on the gate insulating film 2. The gate insulating film 2 has a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090267164 - Method of manufacturing a semiconductor sensor device and semiconductor sensor device: The invention relates to a method of manufacturing a semiconductor sensor device (10) for sensing a substance comprising a plurality of mutually parallel mesa-shaped semiconductor regions (1) which are formed on a surface of a semiconductor body (11) and which are connected at a first end to a first electrically... Agent: Philips Intellectual Property & Standards

20090267166 - Method of manufacturing a device with a cavity: The invention relates to a micro-device with a cavity (50), the micro-device comprising a substrate (10, 110), the method comprising steps of: A) providing the substrate (10, 110), having a surface and comprising a sacrificial oxide region (20, 107, 115) at the surface ( ); B) covering the sacrificial oxide... Agent: David M. O Ell Haynes And Boone, LLP

20090267165 - Wafer level package structure, and sensor device obtained from the same package structure: A wafer level package structure with a plurality of compact sensors such as acceleration sensors and gyro sensors is provided. This package structure is composed of a semiconductor wafer with plural sensor units, and a pair of package wafers bonded to both surfaces of the semiconductor wafer. Each of the... Agent: Cheng Law Group, PLLC

20090267167 - Dual-face fluid components: A fluid component includes at least one substrate of a material that can be etched and an etch stop layer for said material means for detecting the properties of a fluid and/or for activating said fluid and provided on a first side of said etch stop layer and means for... Agent: Nixon Peabody LLP

20090267168 - Electret capacitor type composite sensor: An electret capacitor type composite sensor is constituted by a casing 11, an electrode 12, a hole portion (which is a sound hole and also a light introduction hole) 22, a spacer 31, a vibration plate 41 having light transmissibility, a vibration plate ring 42, a printed board 6 and... Agent: Mcdermott Will & Emery LLP

20090267169 - Semiconductor photodetector: A semiconductor photodetector includes a semiconductor substrate of a first conductivity type, a light absorption layer of the first conductivity type on the semiconductor substrate and absorbing light, a diffraction grating layer on the light absorption layer and including a diffraction grating diffracting light, a first light transmissive layer of... Agent: Leydig Voit & Mayer, Ltd

20090267170 - Apparatus and method for using spacer paste to package an image sensor: A packaged image sensor assembly utilizes a spacer paste to control the height of a transparent window above an image sensor die to provide safe wire bond clearance. A dam structure is used to control the height of the transparent window. The dam may be formed either entirely from spacer... Agent: Curtis A. Vock Lathrop & Gage LLP

20090267172 - Method of manufacturing an image sensing micromodule: A method of manufacturing a micromodule including the steps of: producing an integrated circuit on an active face of a chip made of a semi-conductive material, making a via passing through the chip, electrically linked to the integrated circuit, and inserting the chip into a box comprising a cavity and... Agent: Seed Intellectual Property Law Group PLLC

20090267171 - Pre-encapsulated cavity interposer: A pre-encapsulated cavity interposer, a pre-encapsulated frame, for a semiconductor device.... Agent: Trask Britt, P.C./ Micron Technology

20090267173 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device includes a plurality of semiconductor integrated circuits bonded to a structure body in which a fibrous body is impregnated with an organic resin. The plurality of semiconductor integrated circuits are provided at openings formed in the structure body and each include a photoelectric conversion element, a light-transmitting... Agent: Eric Robinson

20090267174 - Semiconductor device with a charge carrier compensation structure in a semiconductor body and method for its production: A semiconductor device with a charge carrier compensation structure in a semiconductor body and to a method for its production. The semiconductor body includes drift zones of a first conduction type and charge compensation zones of a second conduction type complementing the first conduction type. The drift zones include a... Agent: Dicke, Billig & Czaja

20090267175 - Double patterning techniques and structures: Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor substrate, forming a first integrated circuit (IC) pattern in the first photoresist, the first IC pattern comprising one or more trench structures, protecting the first IC pattern in the... Agent: Cool Patent, P.C. C/o Cpa Global

20090267176 - A method for forming a multi-layer shallow trench isolation structure in a semiconductor device: The disclosure describes a multi-layer shallow trench isolation structure in a semiconductor device. The shallow trench isolation structure may include a first void-free, doped oxide layer in the shallow trench, and a second void-free layer above the first doped oxide layer. The first layer may be formed by vapor deposition... Agent: Haynes And Boone, LLPIPSection

20090267177 - Semiconductor device and method of fabricating the same: A semiconductor device includes a semiconductor substrate including a semiconductor region surrounded with an element isolation region, a first insulating film formed on the semiconductor region, a pair of resistance elements located at the semiconductor region, each resistance element including a first conductive film formed on the first insulating film,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267178 - Device structures for active devices fabricated using a semiconductor-on-insulator substrate and design structures for a radiofrequency integrated circuit: Device structure for active devices fabricated in a semiconductor-on-insulator (SOI) substrate and design structures for a radiofrequency integrated circuit. The device structure includes a first isolation region in the semiconductor layer that extends from a top surface of a semiconductor layer to a first depth, a second isolation region in... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090267181 - Semiconductor device and manufacturing method thereof: A semiconductor device with a fuse 3a to be cut for a circuit modification, of which passivation film coating the uppermost wiring layer is formed in a two-layer structure including a first insulating film 11 with high filling capability and a second insulating film 12 blocking penetration of moisture or... Agent: Mcdermott Will & Emery LLP

20090267180 - Semiconductor device having a reduced fuse thickness and method for manufacturing the same: A semiconductor device that has a reduced fuse thickness without compromising the bondability of an associated pad and a method for manufacturing the same is described. The semiconductor device includes a pad and a fuse formed on a planar level. The pad and fuse are formed using a metal according... Agent: Ladas & Parry LLP

20090267179 - System for power performance optimization of multicore processor chip: A system in one embodiment includes a multiprocessor chip comprising a plurality of cores; a plurality of power circuits, each power circuit being coupled to one of the cores; and an electrically programmable fuse in each power circuit. Each electrically programmable fuse further comprises a first electrode coupled to the... Agent: Zilka-kotab, PC- Ibms

20090267182 - Method of increasing the quality factor of an inductor in a seimiconductor device: A method of fabricating an inductor (70) in a silicon substrate (10), wherein an Argon implantation step (84) is performed after the resist layer (82) has been deposited and the polysilicon layer (30) has been etched, but before the resist layer (82) is stripped and the polysilicon annealed. Thus, an... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090267184 - Metal-insulator-metal (mim) capacitor structure and methods of fabricating same: A Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit improve capacitance density in a MIM capacitor structure by utilizing a sidewall spacer extending along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090267185 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes forming a wiring layer in a first insulating layer, forming a second insulating layer over the first insulating layer, forming a first conductive layer over the second insulating layer, forming a dielectric layer on the first conductive layer, forming a second conductive... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090267183 - Through-substrate power-conducting via with embedded capacitance: When integrated circuits are mounted on a substrate, little space is often available for the required large number of bypass capacitors. A novel substrate structure therefore includes many closely spaced through-holes that extend from a first surface of the substrate to a second surface of the substrate. Each through-hole includes... Agent: Imperium Patent Works

20090267186 - Semiconductor structure including trench capacitor and trench resistor: A structure and a method for fabrication of the structure use a capacitor trench for a trench capacitor and a resistor trench for a trench resistor. The structure is typically a semiconductor structure. In a first instance, the capacitor trench has a linewidth dimension narrower than the resistor trench. The... Agent: Scully, Scott, Murphy & Presser, P.C.

20090267187 - Method for manufacturing an energy storage device and structure therefor: An energy storage device such as a metal-insulator-metal capacitor and a method for manufacturing the energy storage device. The metal-insulator-metal capacitor includes an insulating material positioned between a bottom electrode or bottom plate and a top electrode or top plate. The surface area of the bottom electrode is greater than... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20090267188 - Gallium nitride material processing and related device structures: Gallium nitride material devices and related processes are described. In some embodiments, an N-face of the gallium nitride material region is exposed by removing an underlying region.... Agent: Wolf Greenfield & Sacks, P.C.

20090267189 - Photo-patterned carbon electronics: A system is provided for the manufacture of carbon based electrical components including, an ultraviolet light source; a substrate receiving unit whereby a substrate bearing a first layer of carbon based semiconductor is received and disposed beneath the ultraviolet light source; a mask disposed between the ultraviolet light source and... Agent: Bae Systems

20090267190 - Freestanding iii-nitride single-crystal substrate and method of manufacturing semiconductor device utilizing the substrate: Freestanding III-nitride single-crystal substrates whose average dislocation density is not greater than 5×105 cm−2 and that are fracture resistant, and a method of manufacturing semiconductor devices utilizing such freestanding III-nitride single-crystal substrates are made available. The freestanding III-nitride single-crystal substrate includes one or more high-dislocation-density regions (20h), and a plurality... Agent: Judge Patent Associates

20090267191 - Semiconductor device and process for producing the same: A device and a device manufacturing process. First, a gettering layer is formed on the bottom surface of a silicon substrate. Gates having a MOS structure are then formed on the principal surface of the silicon substrate, and the gettering layer is removed. According to this manufacturing method, the formation... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267192 - Cmp methods avoiding edge erosion and related wafer: Methods of avoiding chemical mechanical polish (CMP) edge erosion and a related wafer are disclosed. In one embodiment, the method includes providing a wafer; forming a first material across the wafer; forming a second material at an outer edge region of the wafer, leaving a central region of the wafer... Agent: Hoffman Warnick LLC

20090267193 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a semiconductor substrate, a circuit region on the semiconductor substrate, a plurality of metal wires formed in the circuit region on the semiconductor device and a seal ring region surrounding the circuit region. A distance L between an outer periphery of the circuit region and an... Agent: Townsend And Townsend And Crew, LLP

20090267194 - Semiconductor chip having tsv (through silicon via) and stacked assembly including the chips: A semiconductor chip having through silicon vias (TSV) and a stacked assembly including the chip are revealed. The chip has a plurality of first and second bonding pads disposed on two opposing surfaces of a semiconductor substrate respectively. Through hole vertically penetrate through the semiconductor substrate and the first and... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090267195 - Semiconductor element and method for manufacturing semiconductor element: A semiconductor device of present invention comprises a layered structure including a cladding layer with a first conductivity, an active layer, and a cladding layer with a second conductivity which are successively grown on a semiconductor substrate of (001) orientation, and an embedding layer covering both side surfaces of the... Agent: Young & Thompson

20090267196 - High performance 3d fet structures, and methods for forming the same using preferential crystallographic etching: The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used... Agent: Scully, Scott, Murphy & Presser, P.C.

20090267197 - Semiconductor device for preventing the leaning of storage nodes and method for manufacturing the same: A semiconductor device for preventing the leaning of storage nodes and a method of manufacturing the same is described. The semiconductor device includes support patterns that are formed to support a plurality of cylinder type storage nodes. The support patterns are formed of a BN layer and have a hexagonal... Agent: Ladas & Parry LLP

20090267198 - Semiconductor device, method for manufacturing semiconductor device and apparatus for manufacturing semiconductor: The present invention provides a multilayer wiring technology by which high adhesiveness and high insulation reliability between wirings are obtained, while maintaining effective low capacitance between wirings. A semiconductor device is characterized in that a first insulating film is an insulating film formed of at least one layer which contains... Agent: Young & Thompson

20090267199 - Isolation layer having a bilayer structure for a semiconductor device and method for forming the same: An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer... Agent: Ladas & Parry LLP

20090267200 - Method for manufacturing a semiconductor substrate including laser annealing: A method for manufacturing a semiconductor device by laser annealing. One embodiment provides a semiconductor substrate having a first surface and a second surface. The second surface is arranged opposite to the first surface. A first dopant is introduced into the semiconductor substrate at the second surface such that its... Agent: Dicke, Billig & Czaja

20090267201 - Vertical transmission structure: A vertical transmission structure for high frequency transmission lines includes a conductive axial core and a conductive structure surrounding the conductive axial core. The vertical transmission structure is applied to a high-frequency flip chip package for reducing the possibility of underfill from coming in contact with the conductive axial core.... Agent: Eschweiler & Associates LLC National City Bank Building

20090267202 - Semiconductor package: A semiconductor package includes a semiconductor chip, a number of pads, a number of lead bars and an encapsulation material. The semiconductor chip has an upper surface and an opposite bottom surface. Area of the upper surface exceeds that of the bottom surface. The pads are mounted on the upper... Agent: PCe Industry, Inc. Att. Steven Reiss

20090267203 - Multi-chip package for reducing test time: A multi-chip package is provided. The multi-chip package includes semiconductor chips. The multi-chip package receives selection signals for selecting two or more chips in response to the selection signals. Any number of chips may be simultaneously selected for a test and the test time can be reduced.... Agent: Marger Johnson & Mccollom, P.C.

20090267204 - Edge seal for a semiconductor device and method therefor: In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed... Agent: Mr. Jerry Chruma Semiconductor Components Industries, L.L.C.

20090267210 - Integrated circuit package and manufacturing method thereof: An integrated circuit package and a manufacturing method thereof are provided. The package includes a die pad, a plurality of first and second contact pads, a first die, a second die and a molding compound. The contact pads adjacent to at least one side of the die pad are arranged... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090267209 - Semiconductor device: At a semiconductor device, an integrated circuit including an optoelectronic conversion device is formed on a front face of a sensor chip. A rewiring layer, which leads from pad electrodes, and post electrodes, on the rewiring layer, are formed on the sensor chip. At least a portion of surroundings of... Agent: Rabin & Berdo, PC

20090267207 - Semiconductor device and manufacturing method thereof: A semiconductor package having a molding unit that seals bonding wires connected to electrode pads of a semiconductor chip is provided with through electrode units comprising bonding wires embedded therein and penetrating the molding unit. A leading end of the respective through electrode units is exposed from an upper surface... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090267208 - Semiconductor package having chip selection through electrodes and stacked semiconductor package having the same: A stacked semiconductor package includes a plurality of stacked semiconductor chips each having a circuit unit, a data pad, and a chip selection pad. The plurality of stacked semiconductor chips also includes a plurality of chip selection through electrodes. The chip selection through electrodes penetrate the chip selection pads and... Agent: Ladas & Parry LLP

20090267206 - Stacked semiconductor package: A stacked semiconductor package includes a circuit board with a number of pads disposed thereon, and a number of package units stacked on the circuit board. Each of the package units includes a substrate, a chip, an anisotropic conductive layer, and a number of conductive elements. The substrate has a... Agent: PCe Industry, Inc. Att. Steven Reiss

20090267211 - Wafer level package and method of fabricating the same: Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the... Agent: Marger Johnson & Mccollom, P.C.

20090267205 - Zero-reflow tsop stacking: The present invention mechanically integrates a flexible printed circuit pre-disposed with solder and flux and two or more leaded integrated circuit packages into an assembly that does not require a solder reflow process prior to the reflow cycle to attach the assembly to a printed circuit module. Each IC device... Agent: Paul Goodwin

20090267212 - Semiconductor device: The invention offers technology for suppressing damage to semiconductor devices due to temperature changes. When flip-chip mounting a silicon chip on a buildup type multilayer substrate having a structure with a thinned core, a core having a small coefficient of thermal expansion is used in the multilayer substrate, and the... Agent: Sheldon Mak Rose & Anderson PC

20090267213 - Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip... Agent: Saile Ackerman LLC

20090267214 - Electronic circuit device and method for manufacturing same: The electronic circuit device of the present invention includes at least one semiconductor element, a plurality of external connection terminals, a connecting conductor for electrically connecting semiconductor element and external connection terminals, and an insulating resin for covering the semiconductor element and supporting the connecting conductor integrally, in which the... Agent: Wenderoth, Lind & Ponack L.L.P.

20090267215 - Power module substrate, method for manufacturing power module substrate, and power module: Disclosed is a power module having improved joint reliability. Specifically disclosed is a power module including a power module substrate wherein a circuit layer is brazed on the front surface of a ceramic substrate, a metal layer is brazed on the rear surface of the ceramic substrate and a semiconductor... Agent: Darby & Darby P.C.

20090267218 - Heat extraction from packaged semiconductor chips, scalable with chip area: A semiconductor device (100A) with plastic encapsulation compound (102) and metal sheets (103a and 104) on both surfaces, acting as heat spreaders. One or more thermal conductors (103a) of preferably uniform height connect one sheet (103b) and the chip surface (101a); the number of conductors is scalable with the chip... Agent: Texas Instruments Incorporated

20090267216 - Inkjet printed leadframes: Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate adapted for high temperature processing, and an attach pad and contact regions that are inkjet printed to the thin substrate using a metallic nanoink.... Agent: Beyer Law Group LLP/ Nsc

20090267217 - Semiconductor device: A semiconductor device (20) in which a semiconductor element (2) is mounted on one of a front side and a back side of a wiring board (3), and a plurality of lands (9) (23) for external connection are provided on the other side of the wiring board, the land (9)... Agent: Steptoe & Johnson LLP

20090267219 - Ultra-thin chip packaging: A packaging method involves attaching a first chip to a stable base, forming contact pads at locations on the stable base, applying a medium onto the stable base such that it electrically insulates sides of the first chip, forming electrical paths on the medium, attaching a second chip to the... Agent: Foley & Lardner LLP

20090267220 - 3-d stacking of active devices over passive devices: Single-die or multi-die packaged modules that incorporate three-dimensional integration of active devices with discrete passive devices to create a package structure that allows active devices (such as, silicon or gallium-arsenide devices) to share the same footprint area as an array of passive surface mount components. In one example, a module... Agent: Lando & Anastasi, LLP

20090267221 - Semiconductor device: An antenna formed on one surface side of a silicon substrate and a semiconductor element provided on the other surface side of the silicon substrate are electrically connected to each other by means of a through via penetrating the silicon substrate. A wiring board is formed separately from the silicon... Agent: Drinker Biddle & Reath (dc)

20090267222 - Low voltage drop and high thermal performance ball grid array package: An integrated circuit (IC) package is provided. The IC package includes a substantially planar substrate having a plurality of contact pads on a first surface electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate, an IC die having a first... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090267223 - Mems package having formed metal lid: A hermetic MEMS device (100) comprising a carrier (110) having a surface (111) including a device (101) and an attachment stripe (122), the stripe spaced from the device and surrounding the device; a metallic foil (102) having a central bulge portion (103) and a peripheral rim portion (104) meeting the... Agent: Texas Instruments Incorporated

20090267224 - Circuit device including rotated stacked die: In a particular embodiment, a circuit device includes a first die coupled to a circuit substrate and having a substantially planar surface. The first die includes electrical contacts distributed on the substantially planar surface adjacent to at least three edges of the first die. The circuit device further includes a... Agent: Schwegman, Lundberg & Woessner, P.A.

20090267225 - Semiconductor device and method for manufacturing the same: In a semiconductor integrated circuit sandwiched between a pair of a first impact resistance layer and a second impact resistance layer, an impact diffusion layer is provided between the semiconductor integrated circuit and the second impact resistance layer. By provision of the impact resistance layer against the external stress and... Agent: Eric Robinson

20090267226 - High-contrast laser mark on substrate surfaces: As part of a first configured laser operation, a smooth, more reflective marking area is formed at a surface of a substrate (e.g., integral heat spreader, or IHS). In a second configured laser operation, a mark is formed at the surface of the substrate within the marking area. The mark... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090267229 - Chip package structure: A chip package structure is provided. The chip package structure comprises different layers of leads electrically connected to different circuits of a chip. The chip package structure comprises a chip and a flexible substrate layer. The chip has an active surface, a plurality of first pads, and a plurality of... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090267228 - Intermetallic diffusion block device and method of manufacture: One embodiment of the present invention is directed to an under bump metallurgy material. The under bump metallurgy material of this embodiment includes an adhesion layer and a conduction layer formed on top of the adhesion layer. The under bump metallurgy material of this embodiment also includes a barrier layer... Agent: Cantor Colburn LLP - IBM Fishkill

20090267230 - Package structure for integrated circuit device and method of the same: The present invention discloses a package structure for an integrated circuit device and method for manufacturing the same. The method includes providing a wafer with multiple integrated circuit devices; providing an extendable substrate having a first surface supporting the wafer; forming multiple anti-elongation layers on a second surface of the... Agent: Snell & Wilmer L.L.P. (main)

20090267227 - Plastic ball grid array ruggedization: A method and product which provides a thin metal or ceramic plate to the top of a plastic grid array (PGA) as a stiffener to maintain its flatness over temperature during a column attach process, and the columns are used for attachment to circuit boards or other circuit devices. These... Agent: Burns & Levinson, LLP

20090267231 - Method of forming a semiconductor device having an etch stop layer and related device: In one embodiment, a lower interlayer dielectric layer, and first and second landing pads penetrating the lower interlayer dielectric layer are formed on a substrate. Interconnection patterns covering the second landing pads are formed on the lower interlayer dielectric layer. An etch stop layer is formed over the interconnection patterns.... Agent: Marger Johnson & Mccollom, P.C.

20090267233 - Bonded semiconductor structure and method of making the same: A bonded semiconductor structure static random access memory circuit includes a support substrate which carries a first horizontally oriented transistor, and an interconnect region which includes a conductive line. The memory circuit includes a donor substrate which includes a semiconductor layer stack coupled to a donor substrate body region through... Agent: Schmeiser Olsen & Watts

20090267232 - Method of manufacturing an integrated circuit: An integrated circuit (100) is provided that comprises a substrate (140) of silicon and an interconnect (130) in a through-hole extending from the first to the second side of the substrate. The interconnect is coupled to a metallisation layer (120) on the first side of the substrate and is provided... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090267235 - Reduced inductance interconnect for enhanced microwave and millimeter-wave systems: According to one embodiment of the present invention, a microwave or millimeter wave module includes a dielectric layer having a pocket formed substantially through the dielectric layer. The dielectric is attached to a metal substrate. The pocket has substantially vertical sidewalls. An integrated circuit is disposed in the pocket. Opposing... Agent: Baker Botts LLP

20090267234 - Semiconductor device and method of manufacturing a semiconductor device: The invention relates to a semiconductor device comprising a substrate (1) and at least one interconnect layer located at a surface of the substrate (1), the interconnect layer comprising a first wire (20″) and a second wire (20′) which are located in the interconnect layer, the first wire (20″) having... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090267237 - Method for manufacturing a semiconductor device: A method for manufacturing a semiconductor device includes forming an insulation film over a semiconductor substrate having a conduction layer; forming a trench pattern over the insulation film; etching an upper portion of the insulation film by using the trench pattern as a mask to form a trench; removing the... Agent: Sherr & Vaughn, PLLC

20090267236 - Through-hole via on saw streets: A semiconductor device is manufactured by, first, providing a wafer designated with a saw street guide. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies.... Agent: Robert D. Atkins

20090267238 - Bridges for interconnecting interposers in multi-chip integrated circuits: A structure and a method for forming the same. The structure includes a substrate, a first interposer on the substrate, a second interposer on the substrate, and a first bridge. The first and second interposers are electrically connected to the substrate. The first bridge is electrically connected to the first... Agent: Schmeiser, Olsen & Watts

20090267239 - Positive photosensitive resin composition: A photosensitive resin composition comprising parts by mass of polycondensate (A) having a structure resulting from dehydration condensation between one or two or more tetracarboxylic acid dianhydride and one or two or more armatic diamines having mutually ortho-positioned amino and phenolic hydroxyl groups and 1 to 100 parts by mass... Agent: Greenblum & Bernstein, P.L.C

20090267240 - Method of manufacturing an overlay mark: A method of manufacturing an overlay mark is provided. Two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, and two second Y-direction isolation structures are formed in a substrate, where the first X-direction isolation structures and the first Y-direction isolation structures are arranged to... Agent: J C Patents

20090267241 - Substrate with check mark and method of inspecting position accuracy of conductive glue dispensed on the substrate: The invention relates to a substrate with a check mark and a method of inspecting position accuracy of conductive glue dispensed on the substrate. The method is implemented on the substrate having at least one transfer pad and at least one check mark arranged near the border of the transfer... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090261312 - Integrated circuit including an array of low resistive vertical diodes and method: An integrated circuit including an array of low resistive vertical diodes and method. One embodiment provides an array of diodes at least partially formed in a substrate for selecting one of a plurality of memory cells. A diode is coupled to a word line. The word line includes a straight-lined... Agent: Dicke, Billig & Czaja

20090261313 - Memory cell having a buried phase change region and method for fabricating the same: Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a width less than that of the base portion. A dielectric surrounds the bottom electrode... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090261314 - Non-volatile memory device and method of fabricating the same: Provided are a non-volatile memory device that may be configured in a stacked structure and may be more easily highly integrated, and a method of fabricating the non-volatile memory device. At least one first electrode and at least one second electrode are provided. The at least one second electrode may... Agent: Harness, Dickey & Pierce, P.L.C

20090261316 - Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication: A resistance variable memory cell and method of forming the same. The memory cell includes a first electrode and at least one layer of resistance variable material in contact with the first electrode. A first, second electrode is in contact with a first portion of the at least one layer... Agent: Dickstein Shapiro LLP

20090261315 - Semiconductor integrated circuit device and method for fabricating the same: A semiconductor integrated circuit device including: a semiconductor substrate on which a circuit is formed; a plurality of functional device arrays stacked on the semiconductor substrate; and vertical wirings so disposed outside of the functional device arrays as to couple the signal lines of the functional device arrays to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090261317 - Enhancement of light emission efficiency by tunable surface plasmons: An apparatus (275) and method of making a light emitting apparatus The light emitting apparatus (275) has a light emitting diode layer (285) and a stack of metal layers and dielectric layers (296) The metal layers may alternate with the dielectric layers The thickness of one or more metal layers... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP

20090261318 - Semiconductor light emitting device: Embodiments provide a semiconductor light emitting device which comprises a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, and a semiconductor layer on the second conductive semiconductor layer, and comprising a plurality of a semiconductor structures... Agent: Birch Stewart Kolasch & Birch

20090261319 - Josephson quantum computing device and integrated circuit using such devices: A Josephson quantum computing device and an integrated circuit using Josephson quantum computing devices which can realize a NOT gate operation controlled with 2 bits will be provided. The Josephson quantum computing device (1) comprises: a superconducting ring member (10) having a π-junction (6) and a 0-junction (7); and a... Agent: Masao Yoshimura, Chen Yoshimura LLP

20090261322 - Full-color organic light emitting diode display device and method of fabricating the same: A full-color organic light emitting diode display device and a method of fabricating the same. The display device includes a substrate having red, green and blue light emitting regions, a first electrode on the substrate, an organic layer on the first electrode and including red, green and blue light emitting... Agent: Christie, Parker & Hale, LLP

20090261320 - Laminated structure, electronic element using the same, manufacturing method therefor, electronic element array, and display unit: A disclosed laminated structure includes a substrate; a wettability varying layer formed on the substrate, the wettability varying layer including a material whose critical surface tension is changed by receiving energy; and an electrode layer formed on the wettability varying layer, the electrode layer forming a pattern based on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090261323 - N,n'-di(arylalkyl)-substituted naphthalene-based tetracarboxylic diimide compounds as n-type semiconductor materials for thin film transistors: A thin film transistor comprises a layer of organic semiconductor material comprising a tetracarboxylic diimide naphthalene-based compound having, attached to each of the imide nitrogen atoms, a substituted or unsubstituted arylalkyl moiety. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said... Agent: Raymond L. Owens Patent Legal Staff

20090261324 - Organic light emitting diode and display using the same: An organic light emitting diode comprising a pair of electrodes and a stack including a hole transport layer, a light emitting layer, and an electron transport layer, the stack being intermediate between the electrodes, the light emitting layer being of a material having hole mobility and electron mobility equal to... Agent: Sughrue-265550

20090261321 - Quinoid systems as organic semiconductors: A semiconducting layer comprising a non-polymeric quinoid heteroacene compound of the formula (I) wherein X stands for O, S or NR, each of R, R1, R2, R3, R4, R5, R6, R7, R8 being independently selected from hydrogen and an organic residue, or 2 or more thereof together forming one or... Agent: Joann Villamizar Ciba Corporation/patent Department

20090261325 - Semiconductor device and method for manufacturing the same: A metallic oxide semiconductor device with high performance and small variations. It is a field effect transistor using a metallic oxide film for the channel, which includes a channel region and a source region and comprises a drain region with a lower oxygen content than the channel region in the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090261326 - Die testing using top surface test pads: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within... Agent: Texas Instruments Incorporated

20090261327 - Process for the simultaneous deposition of crystalline and amorphous layers with doping: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and... Agent: Eschweiler & Associates LLC

20090261329 - Display device: Provided is a display device using a TFT serving as a switching element, in which image deterioration of the display device is prevented by suppressing a photo leakage current to be small, and in particular, in which a density of defects which become positive fixed charges by light present in... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090261331 - Low temperature thin film transistor process, device property, and device stability improvement: A method and apparatus for forming a thin film transistor is provided. A gate dielectric layer is formed, which may be a bilayer, the first layer deposited at a low rate and the second deposited at a high rate. In some embodiments, the first dielectric layer is a silicon rich... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090261330 - Thin film transistor and manufacturing method thereof: It is an object to control quality of a microcrystalline semiconductor film or a semiconductor film including crystal grains so that operation characteristics of a semiconductor element typified by a TFT can be improved. It is another object to improve characteristics of a semiconductor element typified by a TFT by... Agent: Nixon Peabody, LLP

20090261328 - Thin film transistor and method for manufacturing the same: Disclosed is a thin film transistor which includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode; a semiconductor layer which functions as a channel formation region; and a semiconductor layer including an impurity element imparting one conductivity type. The semiconductor layer exists in... Agent: Nixon Peabody, LLP

20090261333 - Display substrate and method of manufacturing the same: A display substrate includes a signal line, a thin-film transistor (“TFT”), a key pattern, a light-blocking pattern, a color filter, a pixel electrode and an alignment key. The signal line and the key pattern are formed on a substrate. The TFT is electrically connected to the signal line. The light-blocking... Agent: Cantor Colburn, LLP

20090261334 - Liquid crystal display device: A thin film transistor substrate of fringe field switching type and a fabricating method thereof for simplifying a process are disclosed. In the thin film transistor substrate of fringe field switching type, a gate line has a multiple-layer structure and includes a transparent conductive layer. A data line crosses the... Agent: Mckenna Long & Aldridge LLP

20090261335 - Pixel unit structure of self-illumination display with low-reflection: A self-illumination display is provided, including a first substrate, a light-absorbing structure, a filter layer, a driving circuit unit, and a self-illumination unit. The light-absorbing structure and the filter layer are juxtaposedly disposed over the first substrate. The driving circuit unit is disposed over and shielded by the light-absorbing structure.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090261332 - Thin film transistor array panel, fabricating method thereof and flat panel display having the same: A thin film transistor array panel includes a substrate, a gate line disposed on the substrate and having a gate electrode, a gate insulating layer disposed on the gate line, a data line disposed on the gate insulating layer and crossing the gate line, a source electrode connected to the... Agent: H.c. Park & Associates, PLC

20090261336 - Array substrate for display device and method of manufacturing the same: An array substrate includes a substrate, a data line formed on the substrate, a passivation layer formed on the data line, a gate line including a gate electrode and a capacitor line formed on the passivation layer, a gate insulation layer formed on the gate electrode and the capacitor line,... Agent: Haynes And Boone, LLPIPSection

20090261338 - Active matrix substrate, display device, and television receiver: An active matrix substrate includes a plurality of transistors. A source electrode is connected with a data signal line, and a drain electrode is connected with a pixel electrode in each transistor. The source electrode is located on a semiconductor layer, and at least a portion of the drain electrode... Agent: Sharp Kabushiki Kaisha C/o Keating & Bennett, LLP

20090261342 - Array substrate of thin film transistor liquid crystal display and method of manufacturing the same: An embodiment of the invention provides an array substrate of a thin film transistor liquid crystal display comprising a gate line and a data line formed on a base substrate, a pixel electrode formed in a pixel region defined by intersecting of the gate line and data line, and a... Agent: Ladas & Parry LLP

20090261340 - Display substrate, liquid crystal display device having the same and method of manufacturing a display substrate: A display substrate includes; a gate line disposed on a substrate, a first insulating layer disposed on the substrate including the gate line, the first insulating layer including an opening part extended in a direction crossing the gate line, a data line disposed on the first insulating layer and an... Agent: Cantor Colburn, LLP

20090261339 - Gate driver on array of a display and method of making device of a display: In a method of making device of a display, an insulating layer, a semiconductor layer, an ohmic contact layer, a second conductive layer, and a photoresist pattern are consecutively formed on a first conductive structure. The photoresist pattern includes a first thickness region, and a second thickness region outside the... Agent: North America Intellectual Property Corporation

20090261341 - Organic light emitting display and method of manufacturing the same: An organic light emitting display includes a pixel part adapted to generate a light and a metal oxide layer. The metal oxide layer is formed by oxidation of a metal layer combined with oxygen of gas or humidity in an inner space of the organic light emitting display. Accordingly, gas... Agent: Haynes And Boone, LLPIPSection

20090261337 - Semiconductor device: It is an object to provide a transistor having a new multigate structure in which operating characteristics and reliability are improved. In a transistor having a multigate structure, which includes two gate electrodes electrically connected to each other and a semiconductor layer including two channel regions connected in series formed... Agent: Nixon Peabody, LLP

20090261343 - High-density nonvolatile memory and methods of making the same: Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first... Agent: Dugan & Dugan, PC

20090261344 - Relaxation of a strained layer using a molten layer: A method for making a crystalline wafer, in which an interface layer is associated with a support substrate. A first layer is associated with the interface layer in a strained state. The interface layer is melted sufficiently to substantially uncouple the first layer from the support substrate to relax the... Agent: Winston & Strawn LLP Patent Department

20090261346 - Integrating cmos and optical devices on a same chip: An integrated circuit structure includes a semiconductor substrate having a first surface region and a second surface region, wherein the first surface region and the second surface region have different surface orientations; a semiconductor device formed at a surface of the first surface region; and a group-III nitride layer over... Agent: Slater & Matsil, L.L.P.

20090261345 - Method for manufacturing compliant substrate, compliant substrate manufactured thereby, gallium nitride based compound semiconductor device having the compliant substrate and manufacturing method thereof: A compliant substrate having a reduced stress, a method for manufacturing the same having a reduced manufacturing time, a gallium nitride based compound semiconductor device including the compliant substrate and a method for manufacturing the same are disclosed. The compliant substrate is manufactured by heating a substrate and a group... Agent: The Nath Law Group

20090261347 - Diamond semiconductor element and process for producing the same: In a conventional diamond semiconductor element, because of high density of crystal defects, it is impossible to reflect the natural physical properties peculiar to a diamond, such as high thermal conductivity, high breakdown field strength, high-frequency characteristics and the like, in the transistor characteristics. By slightly shifting surface orientation of... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090261348 - Semiconductor device and semiconductor device manufacturing method: In a semiconductor device using a SiC substrate, a Junction Termination Edge (JTE) layer is hardly affected by fixed charge so that a stable dielectric strength is obtained. A semiconductor device according to a first aspect of the present invention includes a SiC epi-layer having n type conductivity, an impurity... Agent: Leydig Voit & Mayer, Ltd

20090261349 - Semiconductor device with strained channel and method of fabricating the same: A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the... Agent: Lowe Hauptman Ham & Berner, LLP

20090261351 - Silicon carbide devices having smooth channels: Power devices are provided including a p-type conductivity well region and a buried p+ conductivity region in the p-type conductivity well region. An n+ conductivity region is provided on the buried p+ conductivity region. A channel region of the power device is provided adjacent the buried p+ conductivity region and... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090261350 - Silicon carbide semiconductor device including deep layer: A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench sandwiched by each of the base region to the drift layer, a channel... Agent: Posz Law Group, PLC

20090261352 - Light emitting module: A light emitting module includes a dielectric substrate, a solar cell unit, a metal pattern layer, light emitting units, and a power storage component. The dielectric substrate has a first surface and a second surface opposite to the first surface. The solar cell unit is positioned on the first surface.... Agent: PCe Industry, Inc. Att. Steven Reiss

20090261353 - Production of self-organized pin-type nanostructures, and the rather extensive applications thereof: The invention relates to methods and devices comprising a nanostructure (2;4,4a) for improving the optical behavior of components and apparatuses and/or improving the behavior of sensors by increasing the active surface area. The nanostructure (2) is produced by means of a special RIE etching process, can be modified regarding the... Agent: Stevens & Showalter LLP

20090261354 - Organic light emitting element and organic light emitting device: The present invention relates to an organic light emitting element and an organic light emitting device including the same. An impurity layer close to an electrode is doped with a small amount, and an impurity layer for a p-n junction is doped with a large amount, such that a high... Agent: H.c. Park & Associates, PLC

20090261358 - Emission tuning methods and devices fabricated utilizing methods: A method for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs, typically on a wafer, and coating the LEDs with a conversion material so that at least some light from the LEDs passes through the conversion material and is converted. The light emission from the LED... Agent: Koppel, Patrick, Heybl & Dawson

20090261359 - Semiconductor device and fabrication method thereof: Regions 106 which can be regarded as being monocrystalline are formed locally by irradiating with laser light, and at least the channel-forming region 112 is constructed using these regions. With thin-film transistors which have such a construction it is possible to obtain characteristics which are similar to those which employ... Agent: Eric Robinson

20090261357 - Solid state light sheet and bare die semiconductor circuits with series connected bare die circuit elements: An electronically active sheet includes a bottom substrate having a bottom electrically conductive surface. A top substrate having a top electrically conductive surface is disposed facing the bottom electrically conductive surface. An electrical insulator separates the bottom electrically conductive surface from the top electrically conductive surface. At least one bare... Agent: Michaud-duffy Group LLP

20090261356 - Sub-mount, light emitting diode package and manufacturing method thereof: A sub-mount, a light emitting diode package, and a method of manufacturing thereof are disclosed. A sub-mount, on which multiple light emitting diodes are mounted, can include a multiple number of metal bodies on which the light emitting diodes are respectively mounted, and an oxide wall interposed between the metal... Agent: Staas & Halsey LLP

20090261355 - Thin film transistor: To provide: a thin film transistor which can be operated with a low threshold and has a high transistor withstand voltage; a production method of the thin film transistor; and a semiconductor device, an active matrix substrate, and a display device, each including such a thin film transistor. The present... Agent: Nixon & Vanderhye, PC

20090261360 - Light-emitting element, display device, and electronic apparatus: A light-emitting element includes a cathode, an anode, a first light-emitting layer that is disposed between the cathode and the anode and that emits light of a first color, a second light-emitting layer that is disposed between the first light-emitting layer and the cathode and that emits light of a... Agent: Oliff & Berridge, PLC

20090261362 - 4h-polytype gallium nitride-based semiconductor device on a 4h-polytype substrate: 4H—InGaAlN alloy based optoelectronic and electronic devices on non-polar face are formed on 4H—AlN or 4H—AlGaN on (11-20) a-face 4H—SiC substrates. Typically, non polar 4H—AlN is grown on 4H—SiC (11-20) by molecular beam epitaxy (MBE). Subsequently, III-V nitride device layers are grown by metal organic chemical vapor deposition (MOCVD) with... Agent: Mcdermott Will & Emery LLP

20090261361 - Iii-nitride light emitting device with double heterostructure light emmitting region: A III-nitride light emitting layer is disposed between an n-type region and a p-type region in a double heterostructure. At least a portion of the III-nitride light emitting layer has a graded composition.... Agent: Philips Intellectual Property & Standards

20090261363 - Group-iii nitride epitaxial layer on silicon substrate: A semiconductor device includes a silicon substrate; silicon faceted structures formed on a top surface of the silicon substrate; and a group-III nitride layer over the silicon faceted structures. The silicon faceted structures are separated from each other, and have a repeated pattern.... Agent: Slater & Matsil, L.L.P.

20090261364 - Fluorescent substance: A fluorescent substance characterized by comprising a base crystal composed of a compound represented by the formula: M1aM2bNc wherein M1 is at least one element selected from the group consisting of Mg, Ca, Sr, Ba and Zn; M2 is at least one element selected from the group consisting of Al,... Agent: Fitch, Even, Tabin & Flannery

20090261368 - Led chip package structure using a substrate as a lampshade and method for making the same: An LED chip package structure using a substrate as a lampshade includes a substrate unit and a light-emitting unit. The substrate unit has a substrate body with a lampshade shape. The light-emitting unit has a plurality of light-emitting elements electrically disposed on an inner surface of the substrate body. Therefore,... Agent: Rosenberg, Klein & Lee

20090261371 - Light-emitting device: An embodiment of the invention concerns a light-emitting device with an adjustable, time-variable luminance. This is achieved through electrically conductive tracks that are applied to the first electrode area. The conductive tracks are driven in a time-variable manner with different levels of electrical power.... Agent: Slater & Matsil, L.L.P.

20090261369 - Light-emitting device and manufacturing method thereof: A first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked in this order (a thin-film stacked body); first etching is performed to expose the first conductive film and form at least a pattern of the thin-film stacked body;... Agent: Fish & Richardson P.C.

20090261373 - Low optical loss electrode structures for leds: An electrode structure is disclosed for enhancing the brightness and/or efficiency of an LED. The electrode structure can have a metal electrode and an optically transmissive thick dielectric material formed intermediate the electrode and a light emitting semiconductor material. The electrode and the thick dielectric cooperate to reflect light from... Agent: Haynes And Boone, LLPIPSection

20090261367 - Optical erase memory structure: A method for providing an optical erase memory structure including: forming a metal-insulator-metal memory cell; positioning a light emitting diode adjacent to the metal-insulator-metal memory cell; and emitting a light emission from the light emitting diode for erasing the metal-insulator-metal memory cell.... Agent: Law Offices Of Mikio Ishimaru

20090261366 - Optoelectronic component: An optoelectronic component with a semiconductor body that comprises an active semiconductor layer sequence is disclosed, which is suitable for generating electromagnetic radiation of a first wavelength that is emitted from a front face of the semiconductor body. The component also comprises a first wavelength conversion substance following the semiconductor... Agent: Fish & Richardson PC

20090261365 - Optoelectronic componet which emits electromagnetic radiation, and method for production of an optoelectronic component: An optoelectronic component comprising a housing and a luminescence diode chip arranged in the housing is specified, which component emits a useful radiation. The housing has a housing material which is transmissive to the useful radiation and which is admixed with radiation-absorbing particles in a targeted manner for setting a... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090261370 - Semiconductor light emitting device: Disclosed is a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, a second conductive semiconductor layer under the active layer, a second electrode layer under the second conductive semiconductor layer, and a transmissive conductive... Agent: Birch Stewart Kolasch & Birch

20090261372 - Semiconductor light emitting device and method for fabricating the same: A semiconductor light emitting device is composed of a blue light emitting diode, a red light emitting layer grown epitaxially on the blue light emitting diode, and an insulating material containing a YAG fluorescent material. The red light emitting layer is made of, e.g., undoped In0.4Ga0.6N having a forbidden band... Agent: Greenblum & Bernstein, P.L.C

20090261374 - High output power light emitting device and packaged used therefor: An object of the present invention is to provide a light emitting device that has high output power and long service life where a package is suppressed from discoloring due to heat generation. The light emitting device 1 of the present invention contains a light emitting element 10, a package... Agent: Birch Stewart Kolasch & Birch

20090261375 - Package-base structure of luminescent diode and fabricating process thereof: A package-base structure of a luminescent diode and its fabricating process. The package-base structure includes a substrate having thereon a holding space; an insulating layer extending from a bottom surface of the holding space to the bottom of the substrate; an through hole defined in the insulating layer; and a... Agent: Kirton And Mcconkie

20090261377 - Method for bonding semiconductor structure with substrate and high efficiency photonic device manufactured by using the same method: A method for bonding a semiconductor structure with a substrate and a high efficiency photonic device manufactured by using the same method are disclosed. The method comprises steps of: providing a semiconductor structure and a substrate; forming a composite bonding layer on the semiconductor structure; and bonding the substrate with... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090261376 - Nitride semiconductor light emitting diode and method of fabricating the same: The present invention provides a light emitting diode comprising a substrate: a nitride semiconductor layer formed on the substrate; an ITO mask pattern formed on the nitride semiconductor layer; an N-type semiconductor layer formed through lateral growth on the nitride semiconductor layer and the ITO mask pattern; and a P-type... Agent: H.c. Park & Associates, PLC

20090261378 - Devices with adjustable dual-polarity trigger - and holding-voltage/current for high level of electrostatic discharge protection in sub-micron mixed signal cmos/bicmos integrated: Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1—N2—P2—N1//N1—P3—N3—P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A... Agent: Mh2 Technology Law Group, LLP

20090261379 - Semiconductor device with a semiconductor body and method for its production: A semiconductor device includes an active region with a vertical drift path of a first conduction type and with a near-surface lateral well of a second, complementary conduction type. In addition, the semiconductor device has an edge region surrounding the active region. This edge region has a variable lateral doping... Agent: Dicke, Billig & Czaja

20090261381 - Cmos transistor using germanium condensation and method of fabricating the same: Provided is a CMOS transistor formed using Ge condensation and a method of fabricating the same. The CMOS transistor may include an insulating layer, a silicon layer on the insulating layer and including a p-MOS transistor region and an n-MOS transistor region, a first gate insulating layer and a first... Agent: Harness, Dickey & Pierce, P.L.C

20090261382 - Compound semiconductor substrate for a field effect transistor: o

20090261380 - Transistors having asymetric strained source/drain portions: A semiconductor structure. The structure includes (a) a fin region having (i) a first source/drain portion having a first surface and a third surface, wherein the first and third surfaces are (A) parallel to each other and (B) not coplanar, (ii) a second source/drain portion having a second surface and... Agent: Schmeiser, Olsen & Watts

20090261383 - Optical device having strained buried channel: Provided is an optical device having a strained buried channel area. The optical device includes: a semiconductor substrate of a first conductive type; a gate insulating layer formed on the semiconductor substrate; a gate of a second conductive type opposite to the first conductive type, formed on the gate insulating... Agent: Ampacc Law Group

20090261384 - Gallium nitride high electron mobility transistor having inner field-plate for high power applications: A gallium nitride high electron mobility transistor, in which an inner field-plate is disposed between the gate and drain of the high electron mobility transistor, so that an electric field is distributed between gate and drain regions to reduce a peak value and to reduce gate leakage current while maintaining... Agent: Bachman & Lapointe, P.C.

20090261385 - Bipolar transistor with enhanced base transport: A bipolar transistor includes a base layer design and a method for fabricating such a bipolar transistor that employ a built-in accelerating field focused on a base region adjacent to a collector, where minority carrier transport is otherwise retarded. The accelerating field of the base layer includes on average, a... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20090261386 - Semiconductor integrated circuit device and method of arranging wirings in the semiconductor integrated circuit device: A semiconductor integrated circuit device includes a first component, a second component, a plurality of first, second and third contacts, and a plurality of signal lines having a plurality of first wires, and connecting the first and second component, each of the first wires having a first, second, third and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090261387 - Cmos integrated process for fabricating monocrystalline silicon micromechanical elements by porous silicon micromachining: The invention relates to a process for fabricating a monocrystalline Si-micromechanical element integrated with a CMOS circuit element within the CMOS technology, wherein a domain of second conducting property is formed within a substrate of first conducting property, here the second conducting property is reverse with respect to the first... Agent: Davidson Berquist Jackson & Gowdey LLP

20090261390 - semiconductor memory device and a method of manufacturing the same: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090261391 - Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a... Agent: Trop, Pruner & Hu, P.C.

20090261389 - Composition for oxide semiconductor thin film, field effect transistor using the composition, and method of fabricating the transistor: A composition for an oxide semiconductor thin film, a field effect transistor (FET) using the composition, and a method of fabricating the FET are provided. The composition includes an aluminum oxide, a zinc oxide, and a tin oxide. The thin film formed of the composition remains in amorphous phase at... Agent: Rabin & Berdo, PC

20090261388 - Dice by grind for back surface metallized dies: Semiconductor device processing and methods for dicing a semiconductor wafer into a plurality of individual dies that can have back surface metallization are described. The methods comprise providing a wafer with pre-diced streets in the wafer's front surface, applying a sidewall masking mechanism to the front surface of the wafer... Agent: Kenneth E. Horton Kirton & Mcconkle

20090261392 - Solid-state imaging device and method of manufacturing the same and electronic apparatus: A solid-state imaging device is provided. The solid-state imaging device includes a pixel section, a peripheral circuit section, a silicide blocking layer formed in the pixel section except for part or whole of an area above an isolation portion in the pixel section, and a metal-silicided transistor formed in the... Agent: Sonnenschein Nath & Rosenthal LLP

20090261393 - Composite transfer gate and fabrication thereof: A composite transfer gate is described, which is disposed over a semiconductor substrate between an electron reservoir and a floating node in the semiconductor substrate. The composite transfer gate includes at least one N-type portion and a P-type portion that are arranged laterally.... Agent: J C Patents

20090261394 - Method and system for creating photosensitive array with integrated backplane: A method of fabricating a photoactive array having an integrated backplane is provided. The layers of the device may be stamped or deposited on a planar or a curved substrate, such as a semispherical or ellipsoidal substrate. Each metal layer may be stamped using an elastomeric stamp and a vacuum... Agent: Townsend And Townsend And Crew, LLP

20090261395 - Integrated circuit including a ferroelectric memory cell and method of manufacturing the same: A method for manufacturing an integrated circuit including a ferroelectric memory cell is disclosed. One embodiment of the method includes: forming a amorphous oxide layer over a carrier, the amorphous layer including: O and any of the group of: Hf, Zr and (Hf,Zr), forming a covering layer on the amorphous... Agent: Edell, Shapiro & Finnan, LLC

20090261396 - Semiconductor structure and method of manufacture: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.... Agent: Hvvi Semiconductors, Inc.

20090261397 - Integrated circuit with floating-gate electrodes including a transition metal and corresponding manufacturing method: An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes... Agent: Coats & Bennett/qimonda

20090261398 - Non-volatile memory with sidewall channels and raised source/drain regions: A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions... Agent: Vierra Magen/sandisk Corporation

20090261399 - Nonvolatile semiconductor memory device and manufacturing method thereof: A nonvolatile semiconductor memory device includes a semiconductor substrate of a first conductivity type, a pair of source and drain diffusion regions of a second conductivity type oppositely formed on a surface of the semiconductor substrate, and a stacked structure having a gate insulating film, a charge accumulation film, an... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090261400 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a tunnel insulating film formed on a semiconductor substrate, a charge storage insulating film formed on the tunnel insulating film and including at least two separated low oxygen concentration portions and a high oxygen concentration portion positioned between the adjacent low oxygen concentration portions and having... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090261402 - Method and structure for a semiconductor charge storage device: A semiconductor charge storage device includes a semiconductor substrate having a surface region. The semiconductor substrate is characterized by a first conductivity type. A charge trapping material overlies and is in contact with at least a portion of the surface region of the semiconductor substrate. The charge trapping material is... Agent: Townsend And Townsend And Crew, LLP

20090261401 - Non-volatile memory cell and method of fabricating the same: A non-volatile memory cell is described, including a semiconductor substrate, two separate charge trapping structures on the substrate, first spacers at least on the opposite sidewalls of the two charge trapping structures, a gate dielectric layer on the substrate between the two charge trapping structures, a gate on the two... Agent: North America Intellectual Property Corporation

20090261404 - Non-volatile memory device: A non-volatile memory device having a SONOS structure and a manufacturing method thereof, where a conductive layer is formed between a charge trap layer and a blocking insulation layer of the SONOS structure. Therefore, when a voltage is applied to a gate, the conductive layer undergoes voltage distributions. Accordingly, a... Agent: Marshall, Gerstein & Borun LLP

20090261405 - Non-volatile memory devices: Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping... Agent: Myers Bigel Sibley & Sajovec

20090261403 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a memory cell transistor including a first lower insulating film provided on a semiconductor substrate, a first intermediate insulating film provided on the first lower insulating film, a first upper insulating film provided on the first intermediate insulating film, and a first gate electrode provided on... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090261406 - Use of silicon-rich nitride in a flash memory device: A flash memory cell includes a charge storage element that includes at least a first layer and a second layer. One of the layers includes silicon-rich silicon nitride and the other layer includes silicon nitride. More specifically, the ratio of silicon-to-nitrogen in the first layer is greater than the ratio... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090261407 - Semiconductor device and manufacturing method of the same: Disclosed is a semiconductor device. The semiconductor device includes a first gate formed in a trench of a semiconductor substrate, a first gate oxide layer on the semiconductor substrate including the first gate, a first epitaxial layer on the first gate oxide layer, first source and drain regions in the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090261408 - Semiconductor device and method of forming the same: A semiconductor device includes a semiconductor substrate, a first diffusion region, a gate insulating film, a gate electrode, a second diffusion region and a contact plug. The semiconductor substrate includes a base and at least a pillar. The first diffusion region is disposed in the base. The gate insulating film... Agent: Young & Thompson

20090261409 - Semiconductor devices for high power application: Semiconductor devices for high voltage application are presented. A high power semiconductor device includes a first type doped semiconductor substrate and a second type doped epitaxial layer deposited thereon. A first type doped body region is disposed in the second type doped epitaxial layer. A heavily doped drain region is... Agent: Quintero Law Office, PC

20090261410 - Dmos transistor: This invention provides a DMOS transistor that has a reduced ON resistance and is prevented from deterioration in strength against an electrostatic discharge. An edge portion of a source layer of the DMOS transistor is disposed so as to recede from an inner corner portion of a gate electrode. A... Agent: Morrison & Foerster LLP

20090261411 - Integrated circuit including a body transistor and method: An integrated circuit including a floating body transistor and method. One embodiment provides a transistor including a body region formed in a first portion and a first and a second source/drain region formed in a second and a third portion. The body region is formed in a semiconductor substrate. The... Agent: Dicke, Billig & Czaja

20090261413 - Mosfet and manufacturing method thereof: The present invention provides a MOSFET capable of improving the basic performance of a transistor such as saturation current characteristics, input follow-up and an offleak current at high levels, and a manufacturing method thereof. The MOSFET comprises a semiconductor layer, a gate electrode formed over the semiconductor layer through a... Agent: Volentine & Whitt PLLC

20090261412 - Semiconductor device and manufacturing method of the same: A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a <100> direction on a (100) silicon substrate. A compressive stress... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090261414 - Semiconductor device and method for manufacturing the same: An object is to improve water resistance and reliability of a semiconductor device by reducing the degree of peeling of a film. In a semiconductor device, a first inorganic insulating layer, a semiconductor element layer, a second inorganic insulating layer, an organic insulating layer, and a third inorganic insulating layer... Agent: Cook Alex Ltd

20090261415 - Fully-depleted low-body doping field effect transistor (fet) with reverse short channel effects (sce) induced by self-aligned edge back-gate(s): Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090261416 - Integrated mems device and control circuit: An integrated circuit includes a silicon-on-insulator (SOI) substrate including a buried oxide layer positioned between a top-side silicon layer and a bottom-side silicon layer. A micro-electromechanical system (MEMS) device is integrated into the top-side silicon layer. A semiconductor layer is formed over the bottom-side silicon layer. A control circuit is... Agent: Dicke, Billig & Czaja

20090261417 - Trig modulation electrostatic discharge (esd) protection devices: Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first... Agent: Quintero Law Office, PC

20090261418 - Insulated gate semiconductor device: A protection diode group includes multiple protection diodes connected to each other in parallel. A total junction area average of the protection diode group is set to a value large enough to guarantee a desired electrostatic discharge tolerance. By setting the total junction area average to be equal to a... Agent: Morrison & Foerster LLP

20090261420 - Recess gate transistor: A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to... Agent: F. Chau & Associates, LLC

20090261419 - Semiconductor device having assist features and manufacturing method thereof: A semiconductor device having assist features and manufacturing method thereof includes a substrate having at least an active region and a peripheral region defined thereon. The semiconductor device also includes a plurality of assist features positioned in the peripheral region, or in the active region with a dotted line pattern.... Agent: North America Intellectual Property Corporation

20090261421 - Semiconductor structure and method of manufacture: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.... Agent: Hvvi Semiconductors, Inc.

20090261422 - Cell structure of semiconductor device: A cell structure of a semiconductor device includes an active region, having a concave portion, and an inactive region that defines the active region. A gate pattern in the active region is arranged perpendicular to the active region. A landing pad on the active region and the inactive region contacts... Agent: Volentine & Whitt PLLC

20090261424 - Method for fabricating a dual workfunction semiconductor device and the device made thereof: A dual workfunction semiconductor device and a device made thereof is disclosed. In one aspect, the device includes a first gate stack in a first region and a second gate stack in a second region. The first gate stack has a first effective workfunction, and the second gate stack has... Agent: Knobbe Martens Olson & Bear LLP

20090261423 - Semiconductor device and method for manufacturing same: A semiconductor device includes a fin field effect transistor configured to include at least a first fin and a second fin. Threshold voltage of the first fin and threshold voltage of the second fin are different from each other in the fin field effect transistor.... Agent: Sonnenschein Nath & Rosenthal LLP

20090261425 - Finfets single-sided implant formation: A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are parallel to the fins and... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090261426 - Lateral diffusion field effect transistor with drain region self-aligned to gate electrode: A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be... Agent: Scully, Scott, Murphy & Presser, P.C.

20090261427 - Mos p-n junction diode device and method for manufacturing the same: A MOS P-N junction diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. The method for... Agent: Wpat, PC

20090261428 - Mos p-n junction schottky diode device and method for manufacturing the same: A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic... Agent: Wpat, PC

20090261429 - Transistor and method for manufacturing thereof: A transistor includes a gate insulating layer over a semiconductor substrate; a first insulating layer on both sides of the gate insulating layer; first spacers over the first insulating layer and being spaced apart from each other; and a gate conductive plug between the first spacers. A method for manufacturing... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090261430 - Physical quantity sensor and method for manufacturing the same: A physical quantity sensor includes: a sensor substrate including a first support substrate, a first insulation film and a first semiconductor layer, which are stacked in this order; a cap substrate including a second support substrate disposed on the first semiconductor layer, and has a P conductive type; and multiple... Agent: Posz Law Group, PLC

20090261432 - Interconnection system on a plane adjacent to a solid-state device structure: An interconnection system is provided for a solid-state device. The solid-state that includes, a first layer, multiple devices and a first face. A second layer is bonded to the first face at a bonded face of the second layer that faces the first face. Electrically conductive bonds are between the... Agent: Goodwin Procter LLP Attn: Patent Administrator

20090261431 - Pre-released structure device:

20090261435 - Magnetic memory element and magnetic memory device: A magnetic memory element having a layer structure containing a fixing layer (pinned layer: PL) having a magnetization direction fixed unidirectionally, a nonmagnetic dielectric layer (TN1) in contact with the fixing layer (PL), and a memory layer (free layer: FL) having a first surface in contact with the nonmagnetic dielectric... Agent: Mcdermott Will & Emery LLP

20090261436 - Negative-resistance device with the use of magneto-resistive effect: A magneto-resistive device has a magnetic free layer (33), a magnetic pinned layer (31) having a magnetic moment larger than that of the magnetic free layer, and an intermediate layer (32) provided between the magnetic free layer and the magnetic pinned layer. The negative-resistance device is characterized in that the... Agent: Fitzpatrick Cella Harper & Scinto

20090261433 - One-mask mtj integration for stt mram: A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit includes providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and at least a first metal interconnect. Over the first interlevel dielectric layer and the first metal interconnect, magnetic... Agent: Qualcomm Incorporated

20090261434 - Stt mram magnetic tunnel junction architecture and integration: A magnetic tunnel junction (MTJ) device for a magnetic random access memory (MRAM) in a semiconductor back-end-of-line (BEOL) process flow includes a first metal interconnect for communicating with at least one control device and a first electrode for coupling to the first metal interconnect through a via formed in a... Agent: Qualcomm Incorporated

20090261437 - Two mask mtj integration for stt mram: A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer containing an exposed first interconnect metallization, a first electrode, a fixed magnetization layer, a tunneling barrier layer, a free magnetization layer and a second electrode.... Agent: Qualcomm Incorporated

20090261438 - Visible-range semiconductor nanowire-based photosensor and method for manufacturing the same: A semiconductor nanowire-based photosensor includes a substrate, at least a top surface of the substrate being formed of an insulator, two electrodes spaced at a predetermined interval apart from each other on the substrate, metal catalyst layers disposed respectively on the two electrodes, and visible-range semiconductor nanowires grown from the... Agent: Renner Otto Boisselle & Sklar, LLP

20090261439 - Microlens array and image sensing device using the same: A microlens array is provided, including a base layer with a plurality of first microlenses formed over a first region thereof, wherein the first microlenses are formed with a first height. A plurality of second microlenses are formed over a second region of the base layer, wherein the second region... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090261440 - Microlens unit and image sensor: In a microlens unit (MSU), at least part of the edges of microlenses (MS) (convex lenses MS[BG]) supported on elevations (BG) overlap with trenches (DH) in a direction (VV) perpendicular to the surface of a flattening film (31).... Agent: Edwards Angell Palmer & Dodge LLP

20090261441 - Optical semiconductor device: An optical semiconductor device includes a light-receiving element on a semiconductor substrate of a first conductivity type, the light-receiving element including a light-receiving portion for converting incident light to an electrical current signal and performing a current amplification. The light-receiving portion includes: a semiconductor layer formed on the semiconductor substrate... Agent: Mcdermott Will & Emery LLP

20090261442 - Nonequilibrium photodetectors with single carrier species barriers: A photosensitive diode has an active region defining a majority carrier of a first conductivity type and a minority carrier of a second conductivity type. An extraction region is disposed on a first side of the active region and extracts minority carriers from the active region. It also has majority... Agent: Momkus Mccluskey, LLC

20090261443 - Shared-pixel-type image sensor and method of fabricating the same: A shared-pixel-type image sensor including a shared floating diffusion region formed in a semiconductor substrate; first and second adjacent photoelectric conversion regions sharing the floating diffusion region; two transmission elements that alternately transfer electric charges accumulated in the first and second photoelectric conversion regions to the shared floating diffusion region,... Agent: F. Chau & Associates, LLC

20090261444 - Semiconductor device: A wiring electrically connected to a terminal to which a high power supply potential is applied and a wiring electrically connected to a terminal to which a low power supply potential is applied are formed adjacent to each other and are formed so as to surround the integrated circuit. Thus,... Agent: Nixon Peabody, LLP

20090261445 - Infrared detector and infrared solid-state imaging device: The infrared detector which comprises a first PN junction diode and a second PN junction diode which are formed in a silicon layer formed apart from a support substrate, the silicon layer having a P-type first region and an N-type second region, wherein the first PN junction diode is composed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090261447 - Semiconductor integrated circuit: Signal lines (13) and (14) to be used for supplying a signal between an analog circuit and a digital circuit are provided in different regions from power-ground lines (11) and (12) to be used for supplying a power to the analog circuit and the digital circuit in such a manner... Agent: Connolly Bove Lodge & Hutz LLP

20090261446 - Semiconductor structure and method of manufacture: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.... Agent: Hvvi Semiconductors, Inc.

20090261448 - Method of forming shallow trench isolation structures for integrated circuits: A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is... Agent: HorizonIPPte Ltd

20090261449 - Method for manufacturing soi substrate and semiconductor device: An object is to provide an SOI substrate with excellent characteristics even in the case where a single crystal semiconductor substrate having crystal defects is used. Another object is to provide a semiconductor device using such an SOI substrate. A single crystal semiconductor layer is formed by an epitaxial growth... Agent: Eric Robinson

20090261450 - Electrical fuse structure and method: An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer.... Agent: Slater & Matsil, L.L.P.

20090261451 - Circuit protection device including resistor and fuse element: An integral circuit protection device includes a substrate disposed between first and second terminals. The substrate is composed of a resistive material. A first conductive layer is disposed on a first surface of the substrate and in electrical contact with the first terminal. A second conductive layer is disposed on... Agent: K&l Gates LLP

20090261453 - Air gap in integrated circuit inductor fabrication: A semiconductor device, such as an inductor, is formed with an air gap. A first level has an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures. An inter-level dielectric layer is formed over the first level. An extraction... Agent: Texas Instruments Incorporated

20090261452 - Semiconductor device including an inductor element: An inductor element is formed in a spiral shape so as to have a plurality of windings which cross each other three-dimensionally at least in one intersection on a substrate. Each of the plurality of windings is formed by a first wiring formed on the substrate with a first insulating... Agent: Mcdermott Will & Emery LLP

20090261454 - Capacitor in semiconductor device and method of fabricating the same: A capacitor includes a bottom electrode, a dielectric layer and a top electrode over a substrate. A RuXTiYOZ film is included in at least one of the bottom and top electrodes, where x, y and z are positive real numbers. A method of fabricating the capacitor through a sequential formation... Agent: Lowe Hauptman Ham & Berner, LLP

20090261456 - Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafers: A multiplicity of silicon wafers polished at least on their front sides are provided and successively coated individually in an epitaxy reactor by a procedure whereby one of the wafers is placed on a susceptor in the epitaxy reactor, is pretreated under a hydrogen atmosphere at a first hydrogen flow... Agent: Brooks Kushman P.C.

20090261455 - Method for the production of a component structure: A method for the production of a component structure. On embodiment provides a semiconductor body having a first side. A first trench and a second trench are produced, which extend into the semiconductor body proceeding from the first side and are arranged at a distance from one another in a... Agent: Dicke, Billig & Czaja

20090261457 - Die stacking with an annular via having a recessed socket: A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a variety of electronic systems. In an embodiment, a die stack includes a conductive pillar on the top of a die inserted... Agent: Schwegman, Lundberg & Woessner/micron

20090261458 - Through-electrode, circuit board having a through-electrode, semiconductor package having a through-electrode, and stacked semiconductor package having the semiconductor chip or package having a through-electrode: A stacked semiconductor package includes a first semiconductor package having a first semiconductor chip having a first pad and a through-hole passing through a the portion corresponding to the pad; a second semiconductor package disposed over the first semiconductor package, and including a second semiconductor chip having a second pad... Agent: Ladas & Parry LLP

20090261459 - Semiconductor device having a floating body with increased size and method for manufacturing the same: A semiconductor device with a silicon on insulator substrate having a stacked structure including a silicon substrate, a filled oxide layer, and a silicon layer is provided with a fin pattern formed in the direction of the channel width in a gate forming region of the silicon layer. The fin... Agent: Ladas & Parry LLP

20090261460 - Wafer level integration package: A semiconductor package has a first conductive layer formed on a top surface of a substrate. A conductive via is formed between the first conductive layer and a bottom surface of the substrate. A semiconductor component is mounted to the substrate and electrically connected to the first electrical contact pad.... Agent: Robert D. Atkins

20090261461 - Semiconductor package with lead intrusions: Semiconductor packages comprising a plurality of lead fingers containing a lead intrusion at the edge of the lead fingers are described. The semiconductor packages comprise an integrated circuit chip that is connected to a die pad and is electrically connected to multiple lead fingers. One or more of the lead... Agent: Kenneth E. Horton Kirton & Mcconkle

20090261462 - Semiconductor package with stacked die assembly: This application relates to semiconductor packages comprising stacked die assemblies. In some cases, the stacked dies comprise a first die containing gate driver IC that is stacked on a first surface of a second IC die. A second surface of the second IC die can be bumped for connection to... Agent: Kenneth E. Horton Kirton & Mcconkle

20090261463 - Chip mounting device and chip package array: A chip mounting device includes at least one chip mounting unit and at least one side rail configured beside the chip mounting unit. The chip mounting unit includes a die pad and a plurality of conductive contacts. The side rail includes at least one identifying element. A chip package array... Agent: Rosenberg, Klein & Lee

20090261464 - Getter formed by laser-treatment and methods of making same: The present disclosure relates to methods of treating a silicon substrate with an ultra-fast laser to create a getter material for example in a substantially enclosed MEMS package. In an embodiment, the laser treating comprises irradiating the silicon surface with a plurality of laser pulses adding gettering microstructure to the... Agent: Pepper Hamilton LLP

20090261465 - Semiconductor device and its manufacturing method: A semiconductor device includes a substrate having a substrate wiring, a semiconductor chip provided on the substrate, a first electrical conductor electrically connecting the semiconductor chip and the substrate wiring, and an electrically conductive pad provided on the substrate. The semiconductor device further includes a wiring member electrically connected to... Agent: Mcdermott Will & Emery LLP

20090261466 - Semiconductor device and method of forming vertical interconnect structure using stud bumps: A semiconductor device is made by forming a conductive layer over a temporary carrier. The conductive layer includes a wettable pad. A stud bump is formed over the wettable pad. The stud bump can be a stud bump or stacked bumps. A semiconductor die is mounted to the carrier. An... Agent: Robert D. Atkins

20090261467 - Semiconductor device: A semiconductor device including a semiconductor chip having a plurality of electrodes on one surface thereof in a thickness direction, a resin layer overlapping the one chip surface to provide a rectangular mounting surface, a plurality of metal posts in the resin layer, where the metal posts are electrically connected... Agent: Rabin & Berdo, PC

20090261468 - Semiconductor module: A semiconductor module. One embodiment provides at least two semiconductor chips placed on a carrier. The at least two semiconductor chips are then covered with a molding material to form a molded body. The molded body is thinned until the at least two semiconductor chips are exposed. Then, the carrier... Agent: Dicke, Billig & Czaja

20090261469 - Semiconductor package and method for manufacturing the same: Manufacturing a semiconductor package includes preparing a semiconductor chip having a top surface with bumps electrically connected to bonding pads, a bottom surface opposite to the top surface and side surfaces joining the top surface to the bottom surface. The bottom surface of the semiconductor chip is attached to a... Agent: Ladas & Parry LLP

20090261470 - Chip package: A chip package comprising a carrier, a chip, a plurality of first conductive elements, an encapsulation, and a conductive film is provided. The carrier has a carrying surface and a back surface opposite to the carrying surface. Furthermore, the carrier has a plurality of common contacts in the periphery of... Agent: J C Patents

20090261471 - Rf power transistor package: An RF power transistor package with a rectangular ceramic base can house one or more dies affixed to an upper surface of the ceramic base. Source leads attached to the ceramic base extend from at least opposite sides of the rectangular base beneath a periphery of a non-conductive cover overlying... Agent: Marger Johnson & Mccollom, P.C.

20090261472 - Power semiconductor module with pressure element and method for fabricating a power semiconductor module with a pressure element: The invention relates to a power semiconductor module comprising at least one power semiconductor chip, and comprising a pressure apparatus which exerts a pressure on the top side of the power semiconductor chip when the power semiconductor module is fixed to a heat sink. In addition, a bonding wire which... Agent: Coats & Bennett/infineon Technologies

20090261473 - Low fabrication cost, fine pitch and high reliability solder bump: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about... Agent: Mou-shiung Lin

20090261474 - Wafer level package having a stress relief spacer and manufacturing method thereof: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes... Agent: Mills & Onello LLP

20090261475 - Method for fabricating a metal interconnection using a dual damascene process and resulting semiconductor device: A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower interconnections, wherein widths of the trenches are greater than widths of the via holes, and metal interconnections formed by burying metal thin films... Agent: Sherr & Vaughn, PLLC

20090261476 - Semiconductor device and manufacturing method thereof: A semiconductor device and a manufacturing method thereof are disclosed. The method includes the steps of providing a carrier board having conductive circuits disposed thereon and a plurality of chips with active surfaces having solder pads disposed thereon, wherein conductive bumps are disposed on the solder pads; mounting chips on... Agent: Edwards Angell Palmer & Dodge LLP

20090261477 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device including a trench and a contact hole filled with a copper line, a diffusion barrier layer formed in inner walls of the trench and the contact hole, and a seed-copper layer formed on and/or over the diffusion barrier layer. The surface roughness of... Agent: Sherr & Vaughn, PLLC

20090261478 - Semiconductor device and method for manufacturing the same: The present invention constitutes a semiconductor device wherein a Ni-containing metal silicide layer is formed on a semiconductor substrate and its uppermost surface is nitrided. According to this structure, a dangling bond of silicon existing in the metal silicide layer and nitrogen are bonded by nitridation of the uppermost surface... Agent: Mcdermott Will & Emery LLP

20090261479 - Methods for pitch reduction: An integrated circuit described herein includes a substrate and a plurality of lines overlying the substrate. The lines define a plurality of first trenches and a plurality of second trenches. The plurality of first trenches extend into the substrate a distance different than that of the plurality of second trenches.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090261480 - Integrated circuit and method of fabricating the same: An article including a substrate having a blind hole formed therein, wherein the blind hole is defined by a floor and a sidewall and a solder connection is provided. The solder connection may couple a first contact pad to a second contact pad. The first contact pad may cover a... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090261481 - Wafer level package and method of fabricating the same: Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal... Agent: Rabin & Berdo, PC

20090261483 - Adhesive composition, adhesive composition for circuit connection, connected body semiconductor device: An adhesive composition containing: (a) a thermoplastic resin; (b) a radical-polymerizable compound including two or more (meth)acryloyl groups; (c) a curing agent that generates a radical by photoirradiation of 150 to 750 nm and/or heating at 80 to 200° C.; and (d) a liquid rubber having a viscosity of 10... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090261482 - Semiconductor package and method of making same: A semiconductor package (20) includes an organic substrate (24) and a semiconductor die subassembly (22). A method (50) for making the semiconductor package (20) entails providing (52) the organic substrate (24) having an opening (26) and electrical contacts (36). The subassembly (22) is formed by producing (64) a semiconductor die... Agent: Meschkow & Gresham, P.L.C

20090261484 - Liquid resin composition, semi-conductor device, and process of fabricating the same: A liquid resin composition for use as a sealing resin which reduces wear on a dicing blade or grinder employed for signularization or grinding. The liquid resin composition includes hollow and/or porous particles as a filler, and is adapted in use to be applied on a substrate constituting a semi-conductor... Agent: Cheng Law Group, PLLC