Active solid-state devices (e.g., transistors, solid-state diodes) inventions

20090267042 - Integrated circuit and method of manufacturing an integrated circuit: According to one embodiment of the present invention, an integrated circuit including a plurality of resistance changing memory cells is provided. Each memory cell includes: a semiconductor substrate; a select device arranged within the semiconductor substrate; and a memory element being arranged above the semiconductor substrate. The select device is... Agent: Slater & Matsil, L.L.P.

20090267043 - Phase change memory device resistant to stack pattern collapse and a method for manufacturing the same: A phase change memory device resistant to stack pattern collapse is presented. The phase change memory device includes a silicon substrate, switching elements, heaters, stack patterns, bit lines and word lines. The silicon substrate has a plurality of active areas. The switching elements are connected to the active areas. The... Agent: Ladas & Parry LLP

20090267046 - Memory structure with a programmable resistive element and its manufacturing process: A memory structure has an access transistor connected in series with a programmable resistive element, wherein the programmable resistive element comprises on a semiconductor substrate; an insulated layer with a cavity comprising: a first layer lining the lateral surfaces and the bottom of the said cavity and impermeable to the... Agent: Seed Intellectual Property Law Group PLLC

20090267044 - Phase change memory device having a bent heater and method for manufacturing the same: A phase change memory device includes heaters which are formed in their respective memory cells and vertically positioned stack patterns having phase change layers and top electrodes which are formed to come into contact with the heaters. The heaters have horizontal cross-sectional bent shapes which can have any number of... Agent: Ladas & Parry LLP

20090267045 - Phase change memory device having heaters and method for manufacturing the same: A phase change memory device includes switching elements formed on a substrate that includes a cell region and a peripheral region. Heat sinks are formed on the switching elements. Heaters are formed on the heat sink and a phase change layer is formed on the heaters.... Agent: Ladas & Parry LLP

20090267047 - Semiconductor memory device and manufacturing method thereof: The present invention can promote the large capacity, high performance and high reliability of a semiconductor memory device by realizing high-performance of both the semiconductor device and a memory device when the semiconductor memory device is manufactured by stacking a memory device such as ReRAM or the phase change memory... Agent: Miles & Stockbridge PC

20090267050 - Method of preparing cadmium sulfide nanocrystals emitting light at multiple wavelengths, and cadmium sulfide nanocrystals prepared by the method: A cadmium sulfide nanocrystal, wherein the cadmium sulfide nanocrystal shows maximum luminescence peaks at two or more wavelengths and most of the atoms constituting the nanocrystal are present at the surface of the nanocrystal to form defects.... Agent: Cantor Colburn, LLP

20090267049 - Plasmon enhanced nanowire light emitting diode: A nanowire light emitting diode (LED) and method of emitting light employ a plasmonic mode. The nanowire LED includes a nanowire having a semiconductor junction, a shell layer coaxially surrounding the nanowire, and an insulating layer, which is plasmonically thin, isolating the shell layer from the nanowire. The shell layer... Agent: Hewlett-packard Company Intellectual Property Administration

20090267048 - Semiconductor light emitting element: Light extraction efficiency of a semiconductor light-emitting element is improved. A buffer layer, an n-type GaN layer, an InGaN emission layer, and a p-type GaN layer are laminated on a sapphire substrate in a semiconductor light-emitting element. A ZnO layer functioning as a transparent electrode is provided on the p-type... Agent: Cantor Colburn, LLP

20090267051 - Method of preparing quantum dot-inorganic matrix composites: A method for preparing a quantum dot-inorganic matrix composite includes preparing an inorganic matrix precursor solution containing one or more quantum dot precursors, spin-coating the precursor solution on a substrate to form an inorganic matrix thin film, and heating the inorganic matrix thin film to form an inorganic matrix, while... Agent: Cantor Colburn, LLP

20090267052 - Layer transfer of low defect sige using an etch-back process: A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one... Agent: Scully, Scott, Murphy & Presser, P.C.

20090267053 - Carbon-nanotube based opto-electric device: A carbon nano-tube based photoelectric device includes a substrate and a carbon nanotube (CNT) over the substrate. The CNT comprises a first end and a second end, wherein the CNT has a CNT work function. A high work-function electrode over the substrate is in electric contact with the first end... Agent: Xin Wen

20090267054 - Apparatus, method and system for reconfigurable circuitry: The present invention relates to reconfigurable circuitry, and more particularly to the reconfiguration of the characteristics of materials used in the formation of electronic circuitry as the result of applied external influences. Exemplary embodiments of the present invention provide an apparatuses, methods, electronic devices and computer program products that include... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20090267061 - Carbonyl-functionalized thiophene compounds and related device structures: Carbonyl-functionalized oligo/polythiophene compounds, and related semiconductor components and related device structures.... Agent: K&l Gates LLP

20090267056 - Memory cell: A memory cell comprising a metal-insulator-semiconductor (MIS) structure is disclosed using a homogeneous carrier trapping layer interposed between a semiconductor layer and the gate electrode of a transistor structure so that the operation voltage is reduced and the manufacturing is simplified with lowered cost. The MIS structure comprises: a gate... Agent: Wpat, PC

20090267057 - Organic field-effect transistor for sensing applications: Field-effect transistor comprising a gate electrode layer, a first dielectric layer, a source electrode, a drain electrode, an organic semiconductor and a second dielectric layer, wherein the first dielectric layer is located on the gate electrode layer, the source electrode, the drain electrode and the organic semiconductor are located above... Agent: Philips Intellectual Property & Standards

20090267059 - Organic light emitting device: An organic light emitting device is disclosed. The organic light emitting device includes a substrate, a display positioned on the substrate, and a dummy pattern positioned at an edge of the display. The display includes a plurality of subpixels each including a first electrode, an emissive unit including at least... Agent: Birch Stewart Kolasch & Birch

20090267060 - Polymer wrapped carbon nanotube near-infrared photoactive devices: A photoactive device includes a photoactive region disposed between and electrically connected to two electrodes where the photoactive region includes a first organic photoactive layer comprising a first donor material and a second organic photoactive layer comprising a first acceptor material. The first donor material contains photoactive polymer-wrapped carbon nanotubes... Agent: Duane Morris LLP - Princeton

20090267058 - Solution-processed inorganic films for organic thin film transistors: A method for fabricating a sol-gel film composition for use in a thin film transistor is disclosed. The method BB includes fabricating the sol-gel dielectric composition by solution processing at a temperature in the range 60° C. to 225° C. The sol-gel film made by the method, and an organic... Agent: Dickstein Shapiro LLP

20090267055 - Transistor, method for manufacturing same, and semiconductor device comprising such transistor: m

20090267065 - Semiconductor light emitting element and method for manufacturing the same: A ZnO-based semiconductor light emitting element includes a ZnO-based semiconductor layer formed on a rectangular sapphire A-plane substrate having a principal surface lying in the A-plane {11-20}. The substrate has a thickness of 50 to 200 μm and is surrounded by two parallel first side edges forming an angle in... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090267063 - Semiconductor light-emitting device and method of manufacturing the same: Disclosed is a semiconductor light-emitting device wherein a pn junction is formed by forming, as a p-type layer (11), a semiconductor thin film which is composed of a ZnO compound doped with nitrogen on an n-type ZnO bulk single crystal substrate (10) whose resistance is lowered by being doped with... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090267064 - Semiconductor thin film and method for manufacturing same, and thin film transistor: The present invention provides a semiconductor thin film which can be manufactured at a relatively low temperature even on a flexible resin substrate. As a semiconductor thin film having a low carrier concentration, a high Hall mobility and a large energy band gap, an amorphous film containing zinc oxide and... Agent: Millen, White, Zelano & Branigan, P.C.

20090267062 - Zinc oxide based compound semiconductor device: There is provided a zinc oxide based compound semiconductor device which, even when a semiconductor device is formed by forming a lamination portion having a hetero junction of ZnO based compound semiconductor layers, does not cause any rise in a drive voltage while ensuring p-type doping, and, at the same... Agent: Rabin & Berdo, PC

20090267066 - Photoelectric conversion device and method for manufacturing the same: To provide a photoelectric conversion device with improved photoelectric conversion characteristics and cost competitiveness. A photoelectric conversion device including a semiconductor junction has a semiconductor layer in which a needle-like crystal is made to grow over an impurity semiconductor layer. The impurity semiconductor layer is formed of a microcrystalline semiconductor... Agent: Fish & Richardson P.C.

20090267069 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a p-type TFT having a first semiconductor layer, and an n-type TFT having a second semiconductor layer. A tilted portion, which is widened toward the insulating substrate side, is formed in at least a part of an outer edge portion of the first semiconductor layer. A... Agent: Birch Stewart Kolasch & Birch

20090267067 - Thin film transistor: A thin film transistor has a gate electrode; a gate insulating layer provided so as to cover the gate electrode layer; a pair of impurity semiconductor layers forming source and drain regions which is provided so that at least part of each of them overlaps the gate electrode layer and... Agent: Nixon Peabody, LLP

20090267068 - Thin film transistor: The thin film transistor includes a gate insulating layer covering a gate electrode, over a substrate having an insulating surface; a semiconductor layer forming a channel formation region, in which a plurality of crystal regions is included in an amorphous structure; an impurity semiconductor layer imparting one conductivity type which... Agent: Nixon Peabody, LLP

20090267072 - Electro-optical device and method for manufacturing the same: Using thin film transistors (TFTs), an active matrix circuit, a driver circuit for driving the active matrix circuit or the like are formed on one substrate. Circuits such as a central processing unit (CPU) and a memory, necessary to drive an electric device, are formed using single crystalline semiconductor integrated... Agent: Eric Robinson

20090267070 - Multilayer image sensor structure for reducing crosstalk: An image sensor pixel includes a substrate, an epitaxial layer, and a light collection region. The substrate is doped to have a first conductivity type. The epitaxial layer is disposed over the substrate and doped to have a second conductivity type opposite of the first conductivity type. The light collection... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090267071 - Pixel layout structure for raising capability of detecting amorphous silicon residue defects and method for manufacturing the same: Disclosed is a pixel layout structure capable of increasing the capability of detecting amorphous silicon (a-Si) residue defects and a method for manufacturing the same. Wherein, an a-Si dummy layer is disposed on either one side or both sides of each data line. The design of such an a-Si dummy... Agent: Sinorica, LLC

20090267073 - Semiconductor device and method of manufacturing the same: The present invention improves the aperture ratio of a pixel of a reflection-type display device or a reflection type display device without increasing the number of masks and without using a blackmask. A pixel electrode (167) is arranged so as to partially overlap a source wiring (137) for shielding the... Agent: Fish & Richardson P.C.

20090267076 - El display device and method for manufacturing the same: Plurality of pixels (102) are arranged on the substrate. Each of the pixels (102) is provided with an EL element which utilizes as a cathode a pixel electrode (105) connected to a current control TFT (104). On a counter substrate (110), a light shielding film (112) is disposed at the... Agent: Cook Alex Ltd

20090267075 - Oganic thin film transistor and pixel structure and method for manufacturing the same and display panel: A method of manufacturing an organic thin film transistor is described. A patterned insulating layer having an opening therein is formed on a substrate. A gate is formed in the opening of the insulating layer, and a gate insulating layer is formed on the gate. A conductive material layer is... Agent: Jianq Chyun Intellectual Property Office

20090267074 - Organic light emitting display device and method of manufacturing the same: A organic light emitting display device includes a thin film transistor (TFT) having a gate electrode, a source electrode and a drain electrode which are insulated from the gate electrode, and a semiconductor layer which is insulated from the gate electrode and which contacts each of the source electrode and... Agent: Stein Mcewen, LLP

20090267077 - Semiconductor element, organic transistor, light-emitting device, and electronic device: It is an object of the present invention to provide an organic transistor having a low drive voltage. It is also another object of the present invention to provide an organic transistor, in which light emission can be obtained, which can be manufactured simply and easily. According to an organic... Agent: Fish & Richardson P.C.

20090267078 - Enhancement mode iii-n hemts: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the... Agent: Fish & Richardson P.C.

20090267079 - Externally configurable integrated circuits: A die comprising two or more active electronic components is provided. The active electronic components are capable of being interconnected using interconnections external to the die. The die may be encased within a package, and the active electronic components may be interconnected using interconnections external to the package. By interconnecting... Agent: Wolf Greenfield & Sacks, P.C.

20090267080 - Semiconductor device: It includes: a semiconductor element (2) placed on a substrate (1); peripheral circuit sections (30) and (40) placed on the substrate (1) and connected with the semiconductor element (2); an electrode (30e) provided in the peripheral circuit section (30) and grounded; an electrode (30s) for grounding connected to a metal... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267082 - Semiconductor device and manufacturing method of the same: A semiconductor device includes: a semiconductor element having a first surface and a second surface; a first electrode disposed on the first surface of the element; a second electrode disposed on the second surface of the element; and an insulation film covers a part of the first electrode, the first... Agent: Posz Law Group, PLC

20090267081 - Semiconductor device and method for fabrication thereof: A semiconductor device includes a substrate formed of a single crystal. a silicon carbide layer disposed on a surface of the single crystal substrate and an intermediate layer disposed on a surface of the silicon carbide layer and formed of a Group III nitride semiconductor, wherein the silicon carbide layer... Agent: Sughrue Mion, PLLC

20090267083 - Trenched substrate for crystal growth and wafer bonding: A substrate for a light emitting diode (LED) can have one or more trenches formed therein so as to mitigate stress build up within the substrate due to mismatched thermal coefficients of expansion between the substrate and layers of material, e.g., semiconductor material, formed thereon. In this manner, the likelihood... Agent: Haynes And Boone, LLPIPSection

20090267084 - Integrated circuit with wireless connection: An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and... Agent: Edell, Shapiro & Finnan, LLC

20090267085 - Led package having an array of light emitting cells coupled in series: Disclosed is a light emitting diode (LED) package having an array of light emitting cells coupled in series. The LED package comprises a package body and an LED chip mounted on the package body. The LED chip has an array of light emitting cells coupled in series. Since the LED... Agent: H.c. Park & Associates, PLC

20090267089 - Light emitting device having light emitting elements: A light-emitting device operating on a high drive voltage and a small drive current. LEDs (1) are two-dimensionally formed on an insulating substrate (10) of e.g., sapphire monolithically and connected in series to form an LED array. Two such LED arrays are connected to electrodes (32) in inverse parallel. Air-bridge... Agent: H.c. Park & Associates, PLC

20090267087 - Low resistance wiring structure and liquid crystal display device using the same: A low-resistance wiring structure and a liquid crystal display are disclosed. The liquid crystal display includes a first substrate; a thin film transistor (TFT) formed on the first substrate and formed of a gate wiring, a data wiring and a semiconductor layer; and a second substrate attached to the first... Agent: Brinks Hofer Gilson & Lione

20090267088 - Systems, devices and methods of broadband light sources with tunable spectrum: Broadband light source systems, devices, and methods with a tunable spectrum are described by multiplexing a plurality of light sources, such as LEDs, with thin-film filters or diffraction gratings. A plurality of light sources with different or same wavelengths are multiplexed together to construct a combined broadband light source. A... Agent: Intellectual Equity

20090267086 - Thermal management for led: A method and system for removing heat from an LED facilitates the fabrication of LEDs having enhanced brightness. A thermally conductive interposer can be attached to the top of the LED. Heat can flow through the top of the LED and into the interposer. The interposer can carry the heat... Agent: Haynes And Boone, LLPIPSection

20090267090 - Color mixing light emitting diode device: An exemplary color mixing light emitting diode (LED) device includes a substrate, LED dies, an encapsulating body, and a light mixing structure. The substrate has a main surface. The LED dies are arranged adjacent the main surface of the substrate. The light mixing structure is arranged adjacent an outer portion... Agent: PCe Industry, Inc. Att. Steven Reiss

20090267091 - Semiconductor light emitting device: A semiconductor light emitting device includes a substrate 11 including a group III-V nitride semiconductor; a first-conductivity-type layer 12 formed on the substrate 11, the first-conductivity-type layer including a plurality of group III-V nitride semiconductor layers of first conductivity type; an active layer 13 formed on the first semiconductor layer... Agent: Mcdermott Will & Emery LLP

20090267101 - Display including light emitting element, beam condensing element and diffusing element: A display includes pixels each of which contains a light emitting element and which are arranged in a matrix form, a light transmitting insulating layer which includes a back surface facing the light emitting element and a front surface as a light output surface, a beam-condensing element which is arranged... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267099 - Led light source and chromaticity adjustment method for led light source: There is provided an LED light source whose chromaticity can be adjusted easily without changing its outer shape and suffering damage in the process of chromaticity adjustment. An LED light source includes an LED device, a fluorescent material that absorbs and wavelength-converts a portion of light emitted from the LED... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090267093 - Light emitting device: A light emitting device includes a light emitting diode chip, a heat conductive plate mounting thereon the light emitting diode chip, a sub-mount member disposed between said light emitting diode chip and said heat conductive plate, a dielectric substrate stacked on the heat conductive plate and being formed with a... Agent: Greenblum & Bernstein, P.L.C

20090267094 - Light emitting diode and method for manufacturing the same: The present invention relates to a light emitting diode and a method for manufacturing the same. The light emitting diode includes a base, a light emitting chip on the base, a light permeable encapsulation encapsulating the light emitting chip to the base. The encapsulation defines a plurality of apertures extending... Agent: PCe Industry, Inc. Att. Steven Reiss

20090267102 - Light emitting diode package structure and method for fabricating the same: A light emitting diode (LED) package structure includes a carrier, a first protrusion, a LED chip, and an adhesion layer. The first protrusion is disposed on the carrier and has a first opening to expose the carrier. The LED chip is disposed in the first opening on the carrier, and... Agent: Jianq Chyun Intellectual Property Office

20090267092 - Light-emitting device: A light-emitting device of the present invention includes: a semiconductor layer 1 including a light-emitting layer 12; a recess/projection portion 14 including recesses and projections formed in a pitch larger than a wavelength of light emitted from the light-emitting layer 12, the recess/projection portion 14 being formed in a whole... Agent: Greenblum & Bernstein, P.L.C

20090267095 - Light-emitting device with reflection layer and structure of the reflection layer: The present invention provides a light-emitting device with a reflection layer and the structure of the reflection layer. The reflection layer comprises a variety of dielectric materials. The reflection layer includes a plurality of dielectric layers. The materials of the plurality of dielectric layers have two or more types with... Agent: Wei-kang Cheng

20090267096 - Luminous devices, packages and systems containing the same, and fabricating methods thereof: The present invention is directed to a vertical-type luminous device and high through-put methods of manufacturing the luminous device. These luminous devices can be utilized in a variety of luminous packages, which can be placed in luminous systems. The luminous devices are designed to maximize light emitting efficiency and/or thermal... Agent: Mills & Onello LLP

20090267097 - Method of fabricating photoelectric device of group iii nitride semiconductor and structure thereof: A method of fabricating a photoelectric device of Group III nitride semiconductor comprises the steps of: forming a first Group III nitride semiconductor layer on a surface of an original substrate; forming a patterned epitaxial-blocking layer on the first Group III nitride semiconductor layer; forming a second Group III nitride... Agent: Wpat, PC Intellectual Property Attorneys

20090267100 - Nitride-based semiconductor device and method of manufacturing the same: A nitride-based semiconductor device includes a substrate, a first step portion formed on a main surface side of a first side end surface of the substrate, a second step portion formed on the main surface side of a second side end surface substantially parallel to the first side end surface... Agent: Ditthavong Mori & Steiner, P.C.

20090267098 - Semiconductor light emitting device: Disclosed is a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer comprising a plurality of recesses on the active layer.... Agent: Birch Stewart Kolasch & Birch

20090267103 - Gallium nitride-based compound semiconductor light-emitting device and production method thereof: The invention provides a gallium nitride based compound semiconductor light emitting device with excellent light extracting efficiency and its production method. A light emitting device, obtained from a gallium nitride based compound semiconductor, includes a substrate; a n-type semiconductor layer 13, a light emitting layer 14, and a p-type semiconductor... Agent: Sughrue Mion, PLLC

20090267105 - Led device with embedded top electrode: An LED device and a method of manufacturing, including an embedded top electrode, are presented. The LED device includes an LED structure and a top electrode. The LED structure includes layers disposed on a substrate, including an active light-emitting region. A top layer of the LED structure is a top... Agent: Slater & Matsil, L.L.P.

20090267108 - Light emitting diode chip package and method of making the same: The LED chip package of the present invention uses a semiconductor substrate as package substrate, which improves heat dissipation. Also, the LED chip package is incorporated with a planarization structure, which renders the LED chip and the substrate a substantially planar surface, thereby making formation of a planar patterned conductive... Agent: North America Intellectual Property Corporation

20090267104 - Light-emitting diode package: An LED package including a lead-frame, at least an LED chip and an encapsulant is provided. The lead-frame has a roughened surface, the LED chip is disposed on the lead-frame and electrically connected to the lead-frame, and the roughened surface is suitable to scatter the light emitted from the LED... Agent: Jianq Chyun Intellectual Property Office

20090267107 - Optoelectronic semiconductor component: An optoelectronic semiconductor component includes a basic body, at least one semiconductor chip arranged thereon, and an encapsulation embedding the at least one semiconductor chip and composed of a radiation-transmissive material with scattering particles. A radiation-transmissive covering layer with an absorber is applied to the encapsulation.... Agent: Slater & Matsil, L.L.P.

20090267106 - Semiconductor light emitting device: Embodiments provides a semiconductor light emitting device, which comprises a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, a second conductive semiconductor layer under the active layer, a second electrode layer under the second conductive semiconductor layer, an insulator on one side of the second... Agent: Birch Stewart Kolasch & Birch

20090267109 - Compound semiconductor light-emitting device and method for manufacturing the same: A compound semiconductor light-emitting device which includes an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer, that are made of a compound semiconductor, formed on a substrate, the n-type semiconductor layer and the p-type semiconductor layer are stacked so as to interpose the light-emitting layer therebetween, a... Agent: Sughrue Mion, PLLC

20090267110 - Integrated low leakage schottky diode: An integrated low leakage Schottky diode has a Schottky barrier junction proximate one side of an MOS gate with one end of a drift region on an opposite side of the gate. Below the Schottky metal and the gate oxide is a RESURF structure of an N− layer over a... Agent: Hiscock & Barclay, LLP

20090267111 - Mosfet with integrated field effect rectifier: A modified MOSFET structure comprises an integrated field effect rectifier connected between the source and drain of the MOSFET to shunt current during switching of the MOSFET. The integrated FER provides faster switching of the MOSFET due to the absence of injected carriers during switching while also decreasing the level... Agent: Law Offices Of James E. Eakin

20090267112 - Semiconductor device and method of forming a semiconductor device: A semiconductor device arrangement comprises a semiconductor device and an injector device. The semiconductor device comprises a first current electrode region of a first conductivity type, a second current electrode region of the first conductivity type, a drift region between the first and the second current electrode regions, and at... Agent: Freescale Semiconductor, Inc. Law Department

20090267114 - Field effect transistor: A field effect transistor 100 includes a group III-V nitride semiconductor layer structure containing a hetero junction, a source electrode 105 and a drain electrode 106 formed on the group III-V nitride semiconductor layer structure to be spaced apart from each other; a gate electrode 110 arranged between the source... Agent: Young & Thompson

20090267113 - Semiconductor device and method of manufacturing the same: A semiconductor device has a semiconductor base of a first conductivity type; a hetero semiconductor region in contact with the semiconductor base; a gate electrode adjacent to a portion of a junction between the hetero semiconductor region and the semiconductor base across a gate insulating film; a source electrode connected... Agent: Foley And Lardner LLP Suite 500

20090267115 - Club extension to a t-gate high electron mobility transistor: A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer... Agent: Carmen Patti Law Group , LLC

20090267116 - Wide bandgap transistors with multiple field plates: A transistor comprising a plurality of active semiconductor layers on a substrate, with source and drain electrodes in contact with the semiconductor layers. A gate is formed between the source and drain electrodes and on the plurality of semiconductor layers. A plurality of field plates are arranged over the semiconductor... Agent: Koppel, Patrick, Heybl & Dawson

20090267117 - Enhanced stress for transistors: A transistor disposed on a substrate includes a gate, spacers on gate sidewalls, and diffusion regions adjacent to the gate. Silicide contacts on the diffusion regions are displaced from the spacers by a distance G. Stressors may be provided in the diffusion region to induce a first stress in the... Agent: HorizonIPPte Ltd

20090267118 - Method for forming carbon silicon alloy (csa) and structures thereof: Methods for forming carbon silicon alloy (CSA) and structures thereof are disclosed. The method provides improvement in substitutionality and deposition rate of carbon in epitaxially grown carbon silicon alloy layers (i.e., substituted carbon in Si lattice). In one embodiment of the disclosed method, a carbon silicon alloy layer is epitaxially... Agent: Hoffman Warnick LLC

20090267119 - Semiconductor device and method of manufacturing semiconductor device: The semiconductor device includes a silicon substrate having a channel region, a gate electrode formed over the channel region, buried semiconductor regions formed in a surface of the silicon substrate on both sides of the gate electrode, for applying to the surface of the silicon substrate a first stress in... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090267120 - Image detection apparatus and methods: MOS imaging pixels are described. The MOS imaging pixels may comprise bootstrapped source followers, having their bodies connected to their sources. The source followers of the MOS imaging pixels may be used to buffer a signal indicative of an amount of radiation incident on the pixel. MOS imagers are also... Agent: Wolf Greenfield & Sacks, P.C.

20090267121 - Solid-state image pickup device: A solid-state image pickup device is provided which includes a substrate; a transistor formed on the substrate; a photoelectric conversion element including a first electrode connected to a drain or a source of the transistor, a semiconductor layer stacked on the first electrode, and a second electrode stacked on the... Agent: Oliff & Berridge, PLC

20090267123 - Semiconductor device: A semiconductor device includes: a semiconductor substrate; a plurality of transistors on the semiconductor substrate, each of the transistors has a source and drain region; an interlayer insulating film on the semiconductor substrate and the plurality of transistors; and at least three capacitors on the interlayer insulation film, each of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267122 - Semiconductor device and method of manufacturing the semiconductor device: A semiconductor device has a substrate, an insulator, an yttrium oxide film, a ferroelectric film (STN film), and an upper electrode.... Agent: Foley And Lardner LLP Suite 500

20090267124 - Integrated circuit having efficiently packed decoupling capacitors: An integrated circuit includes a substrate having a semiconducting surface (605) and a plurality of standard cells arranged in a plurality of rows including at least a first row (610) and a second row (615) immediately above the first row. The first row (610) include at least a first decap... Agent: Texas Instruments Incorporated

20090267125 - Semiconductor device and method of manufacturing the same: An isolation region comprises a step structure comprising a step surface that is perpendicular to a depth direction, an upper isolation region and a lower isolation region. An RC transistor is enclosed by the isolation region.... Agent: Young & Thompson

20090267126 - Recess channel transistor: A recess channel transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate, which defines an active area; a gate trench in the active area, wherein the gate trench includes a round lower portion; a recessed gate embedded in the gate trench with a spherical gate portion... Agent: North America Intellectual Property Corporation

20090267127 - Single poly nvm devices and arrays: A single-poly non-volatile memory includes a PMOS select transistor (210) formed with a select gate (212), and P+ source and drain regions (211, 213) formed in a shared n-well region (240), a serially connected PMOS floating gate transistor (220) formed with part of a p-type floating gate layer (222) and... Agent: Hamilton & Terrile, LLP - Freescale

20090267128 - Three dimensional stacked nonvolatile semiconductor memory: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267129 - Dielectric multilayer structures of microelectronic devices and methods for fabricating the same: A dielectric multilayer structure of a microelectronic device, in which a leakage current characteristic and a dielectric constant are improved, is provided in an embodiment. The dielectric multilayer structure includes a lower dielectric layer, which is made of amorphous silicate (M1-xSixOy) or amorphous silicate nitride (M1-xSixOyNz), and an upper dielectric... Agent: Marger Johnson & Mccollom, P.C.

20090267132 - Gate structures in semiconductor devices: A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion preventing layer pattern on the metal ohmic layer pattern, an amorphous layer pattern on the diffusion preventing layer... Agent: Myers Bigel Sibley & Sajovec

20090267131 - Nonvolatile semiconductor memory device and method of manufacturing the same: To reduce capacitance between each adjacent two word lines in a semiconductor memory device, a first insulating film is formed, with a first gate insulating film thereunder, in an interstice between gates respectively of each adjacent two memory transistors, and in an interstice between a gate of a selective transistor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267130 - Structure and process integration for flash storage element and dual conductor complementary mosfets: A method is provided for simultaneously fabricating a flash storage element, an NFET and a PFET having metal gates with different workfunctions. A first gate metal layer of the NFET having a first workfunction is deposited simultaneously with a first metal layer for forming the floating gate of the flash... Agent: International Business Machines Corporation Dept. 18g

20090267133 - Flash memory device and method for fabricating the same: A flash memory device includes a source region formed in an active region of a semiconductor substrate; a recessed region formed in the active region on either side of the source region, the recessed region including a recess surface having sidewalls; floating gates formed at the sidewalls of the recess... Agent: Mckenna Long & Aldridge LLP

20090267137 - Method of manufacturing semiconductor device having notched gate mosfet: Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized... Agent: Mills & Onello LLP

20090267135 - Non-volatile semiconductor storage device and method of manufacturing the same: A non-volatile semiconductor storage device includes a first layer and a second layer. The first layer includes: a plurality of first conductive layers extending in parallel to a substrate and laminated in a direction perpendicular to the substrate; a first insulation layer formed on an upper layer of the plurality... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267134 - Nonvolatile semiconductor memory apparatus: A nonvolatile semiconductor memory apparatus includes: a memory element including: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate located between the source region and the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090267136 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device having a memory cell region and a peripheral circuit region, and a method of manufacturing such a semiconductor memory device, are proposed, in which trench grooves are formed to be shallow in the memory cell region in order to improve the yield, and trench grooves are... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267138 - Semiconductor device and method for manufacturing the same: A charge trap type non-volatile memory device has memory cells formed on a silicon substrate at a predetermined interval via an element isolation trench along a first direction in which word lines extend. Each of the memory cells has a tunnel insulating film formed on the silicon substrate, a charge... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090267139 - Three dimensional stacked nonvolatile semiconductor memory: A three dimensional stacked nonvolatile semiconductor memory according to examples of the present invention includes a memory cell array comprised of first and second blocks disposed side by side and a driver disposed between the first and second blocks. At least two conductive layers having the same structure as that... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267140 - Mosfet structure with guard ring: A trench Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) structure with guard ling, includes: a substrate including an epi layer region on the top thereof a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which are connected to respective... Agent: Birch Stewart Kolasch & Birch

20090267141 - Method for fabricating silicon carbide vertical mosfet devices: A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a... Agent: General Electric Company Global Research

20090267142 - Semiconductor device and method of manufacturing same: A semiconductor device according to the present invention includes a plurality of trenches, a plurality of gate electrodes, a plurality of diffusion Layers, an insulating film, an electrode layer, a plurality of first concave portions and a plurality second concave portions formed in the electrode layer, a solder layer, and... Agent: Young & Thompson

20090267143 - Trenched mosfet with guard ring and channel stop: A trenched MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with a guard ring and a channel stop, including: a substrate including an epi layer region on the top thereof; a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which... Agent: Birch Stewart Kolasch & Birch

20090267144 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: an n-type first well diffusion layer; an n-type second well diffusion layer; a p-type source diffusion layer; a p-type third well diffusion layer; a p-type drain diffusion layer; a gate insulating film; a gate electrode; a device isolation insulating film; and a buffer layer. The buffer... Agent: Mcdermott Will & Emery LLP

20090267145 - Mosfet device having dual interlevel dielectric thickness and method of making same: A method of forming a metal-oxide-semiconductor (MOS) device includes the following steps: forming a semiconductor layer of a first conductivity type having source and drain regions of a second conductivity type, a channel region and a lightly-doped drain region formed therein; forming a gate over the channel region proximate an... Agent: Texas Instruments Incorporated

20090267146 - Structure and method for semiconductor power devices: A semiconductor device includes a semiconductor-on-insulator region on a substrate. The semiconductor-on-insulator region includes a first semiconductor region overlying a dielectric region. The device includes an MOS transistor and a bipolar transistor. The MOS transistor has a drain region, a body region, and a source region in the first semiconductor... Agent: Townsend And Townsend And Crew, LLP

20090267147 - Esd protected rf transistor: The electronic device comprising a RF transistor (100) that is designed for a fundamental RF frequency and that is integrated with an electrostatic protection structure (250) with a further transistor (200). The transistors are suitably MOS transistors, with a gate, source and drain electrodes, and wherein the sources are coupled... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090267148 - Semiconductor integrated circuit devices: A semiconductor integrated circuit device may include: a substrate that includes a high-voltage device region and a low-voltage device region defined on the substrate; a first buried impurity layer formed in at least a portion of the high-voltage device region and coupled to a first voltage; a second buried impurity... Agent: Harness, Dickey & Pierce, P.L.C

20090267153 - Localized spacer for a multi-gate transistor: In one embodiment, the present invention includes a double gate transistor having a silicon fin formed on a buried oxide layer and first and second insulation layers formed on a portion of the silicon fin, where at least the second insulation layer has a pair of portions extending onto respective... Agent: Trop, Pruner & Hu, P.C.

20090267150 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device comprises: forming a gate pattern over a silicon active region and an insulating layer, which form a semiconductor substrate; removing the silicon active region exposed between the gate patterns; and filling a space between the gate patterns to form a plug.... Agent: Marshall, Gerstein & Borun LLP

20090267152 - Semiconductor device and method of manufacturing a semiconductor device: A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an... Agent: Larson Newman & Abel, LLP

20090267151 - Semiconductor device, electronic device, and manufacturing method thereof: To provide a semiconductor device in which resistance of a source region and a drain region of a thin film transistor is reduced and a short channel effect is suppressed, and a manufacturing method thereof. The semiconductor device includes a gate electrode which is formed over a first semiconductor layer... Agent: Nixon Peabody, LLP

20090267149 - Source/drain junction for high performance mosfet formed by selective epi process: In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched silicon layer. Source (S) and drain (D), as well as S/D extension features may similarly... Agent: International Business Machines Corporation Dept. 18g

20090267154 - Mos comprising substrate potential elevating circuitry for esd protection: An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p-layer (38) includes functional circuitry (24) formed on the p-layer (38) including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (24). At least one ESD protection cell (30; in more detail... Agent: Texas Instruments Incorporated

20090267155 - Semiconductor device and method for manufacturing the same: A semiconductor device has a semiconductor substrate, a semiconductor fin which is formed on the semiconductor substrate, which has a long side direction and a short side direction, and which has a carbon-containing silicon film including an impurity and a silicon film formed on the carbon-containing silicon film, a gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267156 - Device structures including dual-depth trench isolation regions and design structures for a static random access memory: Device structures and design structures for a static random access memory. The device structure includes a well of a first conductivity type in a semiconductor layer, first and second deep trench isolation regions in the semiconductor layer that laterally bound a device region in the well, and first and second... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090267157 - Method or manufacturing a semiconductor device and semiconductor device obtained by using such a method: The invention relates to a method of manufacturing a semiconductor device (10) comprising a semiconductor body (2) provided with a field effect transistor (3), wherein a polycrystalline silicon region (5) with a metal layer (6) deposited thereon is transformed into a metal suicide gate electrode (3D) so as to form... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090267159 - Semiconductor device: A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267158 - Semiconductor device and manufacturing process therefor: There is provided a semiconductor device in which deviation in a work function is prevented by a gate electrode having a uniform composition and which has excellent operation properties by effectively controlling a Vth. The semiconductor device comprises an NMOS transistor and a PMOS transistor with a common line electrode,... Agent: Young & Thompson

20090267160 - Semiconductor device and method for manufacturing the same: A semiconductor device comprises an anti-fuse element. The anti-fuse element includes a semiconductor substrate, a first gate insulating film, a first gate electrode, a high-concentration impurity region formed in the semiconductor substrate under the first gate electrode, and first source/drain regions provided in the semiconductor substrate on both sides of... Agent: Sughrue Mion, PLLC

20090267161 - Increasing body dopant uniformity in multi-gate transistor devices: Techniques and structures for increasing body dopant uniformity in multi-gate transistor devices are generally described. In one example, an electronic device includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate... Agent: Cool Patent, P.C. C/o Cpa Global

20090267162 - Method of manufacturing semiconductor device and semiconductor device: A method of manufacturing a semiconductor device comprises: forming a gate insulator on a substrate, the gate insulator including a high-dielectric film in whole or part; forming a first metal film on the gate insulator; forming a second metal film on the first metal film; and forming a reaction film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090267163 - Semiconductor device: According to the present invention, a semiconductor device having a field effect transistor is provided. The field effect transistor comprises a gate insulating film 2 formed on a semiconductor layer 1 and a gate electrode 5 formed on the gate insulating film 2. The gate insulating film 2 has a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090267164 - Method of manufacturing a semiconductor sensor device and semiconductor sensor device: The invention relates to a method of manufacturing a semiconductor sensor device (10) for sensing a substance comprising a plurality of mutually parallel mesa-shaped semiconductor regions (1) which are formed on a surface of a semiconductor body (11) and which are connected at a first end to a first electrically... Agent: Philips Intellectual Property & Standards

20090267166 - Method of manufacturing a device with a cavity: The invention relates to a micro-device with a cavity (50), the micro-device comprising a substrate (10, 110), the method comprising steps of: A) providing the substrate (10, 110), having a surface and comprising a sacrificial oxide region (20, 107, 115) at the surface ( ); B) covering the sacrificial oxide... Agent: David M. O Ell Haynes And Boone, LLP

20090267165 - Wafer level package structure, and sensor device obtained from the same package structure: A wafer level package structure with a plurality of compact sensors such as acceleration sensors and gyro sensors is provided. This package structure is composed of a semiconductor wafer with plural sensor units, and a pair of package wafers bonded to both surfaces of the semiconductor wafer. Each of the... Agent: Cheng Law Group, PLLC

20090267167 - Dual-face fluid components: A fluid component includes at least one substrate of a material that can be etched and an etch stop layer for said material means for detecting the properties of a fluid and/or for activating said fluid and provided on a first side of said etch stop layer and means for... Agent: Nixon Peabody LLP

20090267168 - Electret capacitor type composite sensor: An electret capacitor type composite sensor is constituted by a casing 11, an electrode 12, a hole portion (which is a sound hole and also a light introduction hole) 22, a spacer 31, a vibration plate 41 having light transmissibility, a vibration plate ring 42, a printed board 6 and... Agent: Mcdermott Will & Emery LLP

20090267169 - Semiconductor photodetector: A semiconductor photodetector includes a semiconductor substrate of a first conductivity type, a light absorption layer of the first conductivity type on the semiconductor substrate and absorbing light, a diffraction grating layer on the light absorption layer and including a diffraction grating diffracting light, a first light transmissive layer of... Agent: Leydig Voit & Mayer, Ltd

20090267170 - Apparatus and method for using spacer paste to package an image sensor: A packaged image sensor assembly utilizes a spacer paste to control the height of a transparent window above an image sensor die to provide safe wire bond clearance. A dam structure is used to control the height of the transparent window. The dam may be formed either entirely from spacer... Agent: Curtis A. Vock Lathrop & Gage LLP

20090267172 - Method of manufacturing an image sensing micromodule: A method of manufacturing a micromodule including the steps of: producing an integrated circuit on an active face of a chip made of a semi-conductive material, making a via passing through the chip, electrically linked to the integrated circuit, and inserting the chip into a box comprising a cavity and... Agent: Seed Intellectual Property Law Group PLLC

20090267171 - Pre-encapsulated cavity interposer: A pre-encapsulated cavity interposer, a pre-encapsulated frame, for a semiconductor device.... Agent: Trask Britt, P.C./ Micron Technology

20090267173 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device includes a plurality of semiconductor integrated circuits bonded to a structure body in which a fibrous body is impregnated with an organic resin. The plurality of semiconductor integrated circuits are provided at openings formed in the structure body and each include a photoelectric conversion element, a light-transmitting... Agent: Eric Robinson

20090267174 - Semiconductor device with a charge carrier compensation structure in a semiconductor body and method for its production: A semiconductor device with a charge carrier compensation structure in a semiconductor body and to a method for its production. The semiconductor body includes drift zones of a first conduction type and charge compensation zones of a second conduction type complementing the first conduction type. The drift zones include a... Agent: Dicke, Billig & Czaja

20090267175 - Double patterning techniques and structures: Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor substrate, forming a first integrated circuit (IC) pattern in the first photoresist, the first IC pattern comprising one or more trench structures, protecting the first IC pattern in the... Agent: Cool Patent, P.C. C/o Cpa Global

20090267176 - A method for forming a multi-layer shallow trench isolation structure in a semiconductor device: The disclosure describes a multi-layer shallow trench isolation structure in a semiconductor device. The shallow trench isolation structure may include a first void-free, doped oxide layer in the shallow trench, and a second void-free layer above the first doped oxide layer. The first layer may be formed by vapor deposition... Agent: Haynes And Boone, LLPIPSection

20090267177 - Semiconductor device and method of fabricating the same: A semiconductor device includes a semiconductor substrate including a semiconductor region surrounded with an element isolation region, a first insulating film formed on the semiconductor region, a pair of resistance elements located at the semiconductor region, each resistance element including a first conductive film formed on the first insulating film,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267178 - Device structures for active devices fabricated using a semiconductor-on-insulator substrate and design structures for a radiofrequency integrated circuit: Device structure for active devices fabricated in a semiconductor-on-insulator (SOI) substrate and design structures for a radiofrequency integrated circuit. The device structure includes a first isolation region in the semiconductor layer that extends from a top surface of a semiconductor layer to a first depth, a second isolation region in... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090267181 - Semiconductor device and manufacturing method thereof: A semiconductor device with a fuse 3a to be cut for a circuit modification, of which passivation film coating the uppermost wiring layer is formed in a two-layer structure including a first insulating film 11 with high filling capability and a second insulating film 12 blocking penetration of moisture or... Agent: Mcdermott Will & Emery LLP

20090267180 - Semiconductor device having a reduced fuse thickness and method for manufacturing the same: A semiconductor device that has a reduced fuse thickness without compromising the bondability of an associated pad and a method for manufacturing the same is described. The semiconductor device includes a pad and a fuse formed on a planar level. The pad and fuse are formed using a metal according... Agent: Ladas & Parry LLP

20090267179 - System for power performance optimization of multicore processor chip: A system in one embodiment includes a multiprocessor chip comprising a plurality of cores; a plurality of power circuits, each power circuit being coupled to one of the cores; and an electrically programmable fuse in each power circuit. Each electrically programmable fuse further comprises a first electrode coupled to the... Agent: Zilka-kotab, PC- Ibms

20090267182 - Method of increasing the quality factor of an inductor in a seimiconductor device: A method of fabricating an inductor (70) in a silicon substrate (10), wherein an Argon implantation step (84) is performed after the resist layer (82) has been deposited and the polysilicon layer (30) has been etched, but before the resist layer (82) is stripped and the polysilicon annealed. Thus, an... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090267184 - Metal-insulator-metal (mim) capacitor structure and methods of fabricating same: A Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit improve capacitance density in a MIM capacitor structure by utilizing a sidewall spacer extending along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090267185 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes forming a wiring layer in a first insulating layer, forming a second insulating layer over the first insulating layer, forming a first conductive layer over the second insulating layer, forming a dielectric layer on the first conductive layer, forming a second conductive... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090267183 - Through-substrate power-conducting via with embedded capacitance: When integrated circuits are mounted on a substrate, little space is often available for the required large number of bypass capacitors. A novel substrate structure therefore includes many closely spaced through-holes that extend from a first surface of the substrate to a second surface of the substrate. Each through-hole includes... Agent: Imperium Patent Works

20090267186 - Semiconductor structure including trench capacitor and trench resistor: A structure and a method for fabrication of the structure use a capacitor trench for a trench capacitor and a resistor trench for a trench resistor. The structure is typically a semiconductor structure. In a first instance, the capacitor trench has a linewidth dimension narrower than the resistor trench. The... Agent: Scully, Scott, Murphy & Presser, P.C.

20090267187 - Method for manufacturing an energy storage device and structure therefor: An energy storage device such as a metal-insulator-metal capacitor and a method for manufacturing the energy storage device. The metal-insulator-metal capacitor includes an insulating material positioned between a bottom electrode or bottom plate and a top electrode or top plate. The surface area of the bottom electrode is greater than... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20090267188 - Gallium nitride material processing and related device structures: Gallium nitride material devices and related processes are described. In some embodiments, an N-face of the gallium nitride material region is exposed by removing an underlying region.... Agent: Wolf Greenfield & Sacks, P.C.

20090267189 - Photo-patterned carbon electronics: A system is provided for the manufacture of carbon based electrical components including, an ultraviolet light source; a substrate receiving unit whereby a substrate bearing a first layer of carbon based semiconductor is received and disposed beneath the ultraviolet light source; a mask disposed between the ultraviolet light source and... Agent: Bae Systems

20090267190 - Freestanding iii-nitride single-crystal substrate and method of manufacturing semiconductor device utilizing the substrate: Freestanding III-nitride single-crystal substrates whose average dislocation density is not greater than 5×105 cm−2 and that are fracture resistant, and a method of manufacturing semiconductor devices utilizing such freestanding III-nitride single-crystal substrates are made available. The freestanding III-nitride single-crystal substrate includes one or more high-dislocation-density regions (20h), and a plurality... Agent: Judge Patent Associates

20090267191 - Semiconductor device and process for producing the same: A device and a device manufacturing process. First, a gettering layer is formed on the bottom surface of a silicon substrate. Gates having a MOS structure are then formed on the principal surface of the silicon substrate, and the gettering layer is removed. According to this manufacturing method, the formation... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090267192 - Cmp methods avoiding edge erosion and related wafer: Methods of avoiding chemical mechanical polish (CMP) edge erosion and a related wafer are disclosed. In one embodiment, the method includes providing a wafer; forming a first material across the wafer; forming a second material at an outer edge region of the wafer, leaving a central region of the wafer... Agent: Hoffman Warnick LLC

20090267193 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a semiconductor substrate, a circuit region on the semiconductor substrate, a plurality of metal wires formed in the circuit region on the semiconductor device and a seal ring region surrounding the circuit region. A distance L between an outer periphery of the circuit region and an... Agent: Townsend And Townsend And Crew, LLP

20090267194 - Semiconductor chip having tsv (through silicon via) and stacked assembly including the chips: A semiconductor chip having through silicon vias (TSV) and a stacked assembly including the chip are revealed. The chip has a plurality of first and second bonding pads disposed on two opposing surfaces of a semiconductor substrate respectively. Through hole vertically penetrate through the semiconductor substrate and the first and... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090267195 - Semiconductor element and method for manufacturing semiconductor element: A semiconductor device of present invention comprises a layered structure including a cladding layer with a first conductivity, an active layer, and a cladding layer with a second conductivity which are successively grown on a semiconductor substrate of (001) orientation, and an embedding layer covering both side surfaces of the... Agent: Young & Thompson

20090267196 - High performance 3d fet structures, and methods for forming the same using preferential crystallographic etching: The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used... Agent: Scully, Scott, Murphy & Presser, P.C.

20090267197 - Semiconductor device for preventing the leaning of storage nodes and method for manufacturing the same: A semiconductor device for preventing the leaning of storage nodes and a method of manufacturing the same is described. The semiconductor device includes support patterns that are formed to support a plurality of cylinder type storage nodes. The support patterns are formed of a BN layer and have a hexagonal... Agent: Ladas & Parry LLP

20090267198 - Semiconductor device, method for manufacturing semiconductor device and apparatus for manufacturing semiconductor: The present invention provides a multilayer wiring technology by which high adhesiveness and high insulation reliability between wirings are obtained, while maintaining effective low capacitance between wirings. A semiconductor device is characterized in that a first insulating film is an insulating film formed of at least one layer which contains... Agent: Young & Thompson

20090267199 - Isolation layer having a bilayer structure for a semiconductor device and method for forming the same: An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer... Agent: Ladas & Parry LLP

20090267200 - Method for manufacturing a semiconductor substrate including laser annealing: A method for manufacturing a semiconductor device by laser annealing. One embodiment provides a semiconductor substrate having a first surface and a second surface. The second surface is arranged opposite to the first surface. A first dopant is introduced into the semiconductor substrate at the second surface such that its... Agent: Dicke, Billig & Czaja

20090267201 - Vertical transmission structure: A vertical transmission structure for high frequency transmission lines includes a conductive axial core and a conductive structure surrounding the conductive axial core. The vertical transmission structure is applied to a high-frequency flip chip package for reducing the possibility of underfill from coming in contact with the conductive axial core.... Agent: Eschweiler & Associates LLC National City Bank Building

20090267202 - Semiconductor package: A semiconductor package includes a semiconductor chip, a number of pads, a number of lead bars and an encapsulation material. The semiconductor chip has an upper surface and an opposite bottom surface. Area of the upper surface exceeds that of the bottom surface. The pads are mounted on the upper... Agent: PCe Industry, Inc. Att. Steven Reiss

20090267203 - Multi-chip package for reducing test time: A multi-chip package is provided. The multi-chip package includes semiconductor chips. The multi-chip package receives selection signals for selecting two or more chips in response to the selection signals. Any number of chips may be simultaneously selected for a test and the test time can be reduced.... Agent: Marger Johnson & Mccollom, P.C.

20090267204 - Edge seal for a semiconductor device and method therefor: In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed... Agent: Mr. Jerry Chruma Semiconductor Components Industries, L.L.C.

20090267210 - Integrated circuit package and manufacturing method thereof: An integrated circuit package and a manufacturing method thereof are provided. The package includes a die pad, a plurality of first and second contact pads, a first die, a second die and a molding compound. The contact pads adjacent to at least one side of the die pad are arranged... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090267209 - Semiconductor device: At a semiconductor device, an integrated circuit including an optoelectronic conversion device is formed on a front face of a sensor chip. A rewiring layer, which leads from pad electrodes, and post electrodes, on the rewiring layer, are formed on the sensor chip. At least a portion of surroundings of... Agent: Rabin & Berdo, PC

20090267207 - Semiconductor device and manufacturing method thereof: A semiconductor package having a molding unit that seals bonding wires connected to electrode pads of a semiconductor chip is provided with through electrode units comprising bonding wires embedded therein and penetrating the molding unit. A leading end of the respective through electrode units is exposed from an upper surface... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090267208 - Semiconductor package having chip selection through electrodes and stacked semiconductor package having the same: A stacked semiconductor package includes a plurality of stacked semiconductor chips each having a circuit unit, a data pad, and a chip selection pad. The plurality of stacked semiconductor chips also includes a plurality of chip selection through electrodes. The chip selection through electrodes penetrate the chip selection pads and... Agent: Ladas & Parry LLP

20090267206 - Stacked semiconductor package: A stacked semiconductor package includes a circuit board with a number of pads disposed thereon, and a number of package units stacked on the circuit board. Each of the package units includes a substrate, a chip, an anisotropic conductive layer, and a number of conductive elements. The substrate has a... Agent: PCe Industry, Inc. Att. Steven Reiss

20090267211 - Wafer level package and method of fabricating the same: Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the... Agent: Marger Johnson & Mccollom, P.C.

20090267205 - Zero-reflow tsop stacking: The present invention mechanically integrates a flexible printed circuit pre-disposed with solder and flux and two or more leaded integrated circuit packages into an assembly that does not require a solder reflow process prior to the reflow cycle to attach the assembly to a printed circuit module. Each IC device... Agent: Paul Goodwin

20090267212 - Semiconductor device: The invention offers technology for suppressing damage to semiconductor devices due to temperature changes. When flip-chip mounting a silicon chip on a buildup type multilayer substrate having a structure with a thinned core, a core having a small coefficient of thermal expansion is used in the multilayer substrate, and the... Agent: Sheldon Mak Rose & Anderson PC

20090267213 - Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip... Agent: Saile Ackerman LLC

20090267214 - Electronic circuit device and method for manufacturing same: The electronic circuit device of the present invention includes at least one semiconductor element, a plurality of external connection terminals, a connecting conductor for electrically connecting semiconductor element and external connection terminals, and an insulating resin for covering the semiconductor element and supporting the connecting conductor integrally, in which the... Agent: Wenderoth, Lind & Ponack L.L.P.

20090267215 - Power module substrate, method for manufacturing power module substrate, and power module: Disclosed is a power module having improved joint reliability. Specifically disclosed is a power module including a power module substrate wherein a circuit layer is brazed on the front surface of a ceramic substrate, a metal layer is brazed on the rear surface of the ceramic substrate and a semiconductor... Agent: Darby & Darby P.C.

20090267218 - Heat extraction from packaged semiconductor chips, scalable with chip area: A semiconductor device (100A) with plastic encapsulation compound (102) and metal sheets (103a and 104) on both surfaces, acting as heat spreaders. One or more thermal conductors (103a) of preferably uniform height connect one sheet (103b) and the chip surface (101a); the number of conductors is scalable with the chip... Agent: Texas Instruments Incorporated

20090267216 - Inkjet printed leadframes: Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate adapted for high temperature processing, and an attach pad and contact regions that are inkjet printed to the thin substrate using a metallic nanoink.... Agent: Beyer Law Group LLP/ Nsc

20090267217 - Semiconductor device: A semiconductor device (20) in which a semiconductor element (2) is mounted on one of a front side and a back side of a wiring board (3), and a plurality of lands (9) (23) for external connection are provided on the other side of the wiring board, the land (9)... Agent: Steptoe & Johnson LLP

20090267219 - Ultra-thin chip packaging: A packaging method involves attaching a first chip to a stable base, forming contact pads at locations on the stable base, applying a medium onto the stable base such that it electrically insulates sides of the first chip, forming electrical paths on the medium, attaching a second chip to the... Agent: Foley & Lardner LLP

20090267220 - 3-d stacking of active devices over passive devices: Single-die or multi-die packaged modules that incorporate three-dimensional integration of active devices with discrete passive devices to create a package structure that allows active devices (such as, silicon or gallium-arsenide devices) to share the same footprint area as an array of passive surface mount components. In one example, a module... Agent: Lando & Anastasi, LLP

20090267221 - Semiconductor device: An antenna formed on one surface side of a silicon substrate and a semiconductor element provided on the other surface side of the silicon substrate are electrically connected to each other by means of a through via penetrating the silicon substrate. A wiring board is formed separately from the silicon... Agent: Drinker Biddle & Reath (dc)

20090267222 - Low voltage drop and high thermal performance ball grid array package: An integrated circuit (IC) package is provided. The IC package includes a substantially planar substrate having a plurality of contact pads on a first surface electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate, an IC die having a first... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090267223 - Mems package having formed metal lid: A hermetic MEMS device (100) comprising a carrier (110) having a surface (111) including a device (101) and an attachment stripe (122), the stripe spaced from the device and surrounding the device; a metallic foil (102) having a central bulge portion (103) and a peripheral rim portion (104) meeting the... Agent: Texas Instruments Incorporated

20090267224 - Circuit device including rotated stacked die: In a particular embodiment, a circuit device includes a first die coupled to a circuit substrate and having a substantially planar surface. The first die includes electrical contacts distributed on the substantially planar surface adjacent to at least three edges of the first die. The circuit device further includes a... Agent: Schwegman, Lundberg & Woessner, P.A.

20090267225 - Semiconductor device and method for manufacturing the same: In a semiconductor integrated circuit sandwiched between a pair of a first impact resistance layer and a second impact resistance layer, an impact diffusion layer is provided between the semiconductor integrated circuit and the second impact resistance layer. By provision of the impact resistance layer against the external stress and... Agent: Eric Robinson

20090267226 - High-contrast laser mark on substrate surfaces: As part of a first configured laser operation, a smooth, more reflective marking area is formed at a surface of a substrate (e.g., integral heat spreader, or IHS). In a second configured laser operation, a mark is formed at the surface of the substrate within the marking area. The mark... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090267229 - Chip package structure: A chip package structure is provided. The chip package structure comprises different layers of leads electrically connected to different circuits of a chip. The chip package structure comprises a chip and a flexible substrate layer. The chip has an active surface, a plurality of first pads, and a plurality of... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090267228 - Intermetallic diffusion block device and method of manufacture: One embodiment of the present invention is directed to an under bump metallurgy material. The under bump metallurgy material of this embodiment includes an adhesion layer and a conduction layer formed on top of the adhesion layer. The under bump metallurgy material of this embodiment also includes a barrier layer... Agent: Cantor Colburn LLP - IBM Fishkill

20090267230 - Package structure for integrated circuit device and method of the same: The present invention discloses a package structure for an integrated circuit device and method for manufacturing the same. The method includes providing a wafer with multiple integrated circuit devices; providing an extendable substrate having a first surface supporting the wafer; forming multiple anti-elongation layers on a second surface of the... Agent: Snell & Wilmer L.L.P. (main)

20090267227 - Plastic ball grid array ruggedization: A method and product which provides a thin metal or ceramic plate to the top of a plastic grid array (PGA) as a stiffener to maintain its flatness over temperature during a column attach process, and the columns are used for attachment to circuit boards or other circuit devices. These... Agent: Burns & Levinson, LLP

20090267231 - Method of forming a semiconductor device having an etch stop layer and related device: In one embodiment, a lower interlayer dielectric layer, and first and second landing pads penetrating the lower interlayer dielectric layer are formed on a substrate. Interconnection patterns covering the second landing pads are formed on the lower interlayer dielectric layer. An etch stop layer is formed over the interconnection patterns.... Agent: Marger Johnson & Mccollom, P.C.

20090267233 - Bonded semiconductor structure and method of making the same: A bonded semiconductor structure static random access memory circuit includes a support substrate which carries a first horizontally oriented transistor, and an interconnect region which includes a conductive line. The memory circuit includes a donor substrate which includes a semiconductor layer stack coupled to a donor substrate body region through... Agent: Schmeiser Olsen & Watts

20090267232 - Method of manufacturing an integrated circuit: An integrated circuit (100) is provided that comprises a substrate (140) of silicon and an interconnect (130) in a through-hole extending from the first to the second side of the substrate. The interconnect is coupled to a metallisation layer (120) on the first side of the substrate and is provided... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090267235 - Reduced inductance interconnect for enhanced microwave and millimeter-wave systems: According to one embodiment of the present invention, a microwave or millimeter wave module includes a dielectric layer having a pocket formed substantially through the dielectric layer. The dielectric is attached to a metal substrate. The pocket has substantially vertical sidewalls. An integrated circuit is disposed in the pocket. Opposing... Agent: Baker Botts LLP

20090267234 - Semiconductor device and method of manufacturing a semiconductor device: The invention relates to a semiconductor device comprising a substrate (1) and at least one interconnect layer located at a surface of the substrate (1), the interconnect layer comprising a first wire (20″) and a second wire (20′) which are located in the interconnect layer, the first wire (20″) having... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090267237 - Method for manufacturing a semiconductor device: A method for manufacturing a semiconductor device includes forming an insulation film over a semiconductor substrate having a conduction layer; forming a trench pattern over the insulation film; etching an upper portion of the insulation film by using the trench pattern as a mask to form a trench; removing the... Agent: Sherr & Vaughn, PLLC

20090267236 - Through-hole via on saw streets: A semiconductor device is manufactured by, first, providing a wafer designated with a saw street guide. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies.... Agent: Robert D. Atkins

20090267238 - Bridges for interconnecting interposers in multi-chip integrated circuits: A structure and a method for forming the same. The structure includes a substrate, a first interposer on the substrate, a second interposer on the substrate, and a first bridge. The first and second interposers are electrically connected to the substrate. The first bridge is electrically connected to the first... Agent: Schmeiser, Olsen & Watts

20090267239 - Positive photosensitive resin composition: A photosensitive resin composition comprising parts by mass of polycondensate (A) having a structure resulting from dehydration condensation between one or two or more tetracarboxylic acid dianhydride and one or two or more armatic diamines having mutually ortho-positioned amino and phenolic hydroxyl groups and 1 to 100 parts by mass... Agent: Greenblum & Bernstein, P.L.C

20090267240 - Method of manufacturing an overlay mark: A method of manufacturing an overlay mark is provided. Two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, and two second Y-direction isolation structures are formed in a substrate, where the first X-direction isolation structures and the first Y-direction isolation structures are arranged to... Agent: J C Patents

20090267241 - Substrate with check mark and method of inspecting position accuracy of conductive glue dispensed on the substrate: The invention relates to a substrate with a check mark and a method of inspecting position accuracy of conductive glue dispensed on the substrate. The method is implemented on the substrate having at least one transfer pad and at least one check mark arranged near the border of the transfer... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090261312 - Integrated circuit including an array of low resistive vertical diodes and method: An integrated circuit including an array of low resistive vertical diodes and method. One embodiment provides an array of diodes at least partially formed in a substrate for selecting one of a plurality of memory cells. A diode is coupled to a word line. The word line includes a straight-lined... Agent: Dicke, Billig & Czaja

20090261313 - Memory cell having a buried phase change region and method for fabricating the same: Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a width less than that of the base portion. A dielectric surrounds the bottom electrode... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090261314 - Non-volatile memory device and method of fabricating the same: Provided are a non-volatile memory device that may be configured in a stacked structure and may be more easily highly integrated, and a method of fabricating the non-volatile memory device. At least one first electrode and at least one second electrode are provided. The at least one second electrode may... Agent: Harness, Dickey & Pierce, P.L.C

20090261316 - Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication: A resistance variable memory cell and method of forming the same. The memory cell includes a first electrode and at least one layer of resistance variable material in contact with the first electrode. A first, second electrode is in contact with a first portion of the at least one layer... Agent: Dickstein Shapiro LLP

20090261315 - Semiconductor integrated circuit device and method for fabricating the same: A semiconductor integrated circuit device including: a semiconductor substrate on which a circuit is formed; a plurality of functional device arrays stacked on the semiconductor substrate; and vertical wirings so disposed outside of the functional device arrays as to couple the signal lines of the functional device arrays to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090261317 - Enhancement of light emission efficiency by tunable surface plasmons: An apparatus (275) and method of making a light emitting apparatus The light emitting apparatus (275) has a light emitting diode layer (285) and a stack of metal layers and dielectric layers (296) The metal layers may alternate with the dielectric layers The thickness of one or more metal layers... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP

20090261318 - Semiconductor light emitting device: Embodiments provide a semiconductor light emitting device which comprises a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, and a semiconductor layer on the second conductive semiconductor layer, and comprising a plurality of a semiconductor structures... Agent: Birch Stewart Kolasch & Birch

20090261319 - Josephson quantum computing device and integrated circuit using such devices: A Josephson quantum computing device and an integrated circuit using Josephson quantum computing devices which can realize a NOT gate operation controlled with 2 bits will be provided. The Josephson quantum computing device (1) comprises: a superconducting ring member (10) having a π-junction (6) and a 0-junction (7); and a... Agent: Masao Yoshimura, Chen Yoshimura LLP

20090261322 - Full-color organic light emitting diode display device and method of fabricating the same: A full-color organic light emitting diode display device and a method of fabricating the same. The display device includes a substrate having red, green and blue light emitting regions, a first electrode on the substrate, an organic layer on the first electrode and including red, green and blue light emitting... Agent: Christie, Parker & Hale, LLP

20090261320 - Laminated structure, electronic element using the same, manufacturing method therefor, electronic element array, and display unit: A disclosed laminated structure includes a substrate; a wettability varying layer formed on the substrate, the wettability varying layer including a material whose critical surface tension is changed by receiving energy; and an electrode layer formed on the wettability varying layer, the electrode layer forming a pattern based on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090261323 - N,n'-di(arylalkyl)-substituted naphthalene-based tetracarboxylic diimide compounds as n-type semiconductor materials for thin film transistors: A thin film transistor comprises a layer of organic semiconductor material comprising a tetracarboxylic diimide naphthalene-based compound having, attached to each of the imide nitrogen atoms, a substituted or unsubstituted arylalkyl moiety. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said... Agent: Raymond L. Owens Patent Legal Staff

20090261324 - Organic light emitting diode and display using the same: An organic light emitting diode comprising a pair of electrodes and a stack including a hole transport layer, a light emitting layer, and an electron transport layer, the stack being intermediate between the electrodes, the light emitting layer being of a material having hole mobility and electron mobility equal to... Agent: Sughrue-265550

20090261321 - Quinoid systems as organic semiconductors: A semiconducting layer comprising a non-polymeric quinoid heteroacene compound of the formula (I) wherein X stands for O, S or NR, each of R, R1, R2, R3, R4, R5, R6, R7, R8 being independently selected from hydrogen and an organic residue, or 2 or more thereof together forming one or... Agent: Joann Villamizar Ciba Corporation/patent Department

20090261325 - Semiconductor device and method for manufacturing the same: A metallic oxide semiconductor device with high performance and small variations. It is a field effect transistor using a metallic oxide film for the channel, which includes a channel region and a source region and comprises a drain region with a lower oxygen content than the channel region in the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090261326 - Die testing using top surface test pads: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within... Agent: Texas Instruments Incorporated

20090261327 - Process for the simultaneous deposition of crystalline and amorphous layers with doping: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and... Agent: Eschweiler & Associates LLC

20090261329 - Display device: Provided is a display device using a TFT serving as a switching element, in which image deterioration of the display device is prevented by suppressing a photo leakage current to be small, and in particular, in which a density of defects which become positive fixed charges by light present in... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090261331 - Low temperature thin film transistor process, device property, and device stability improvement: A method and apparatus for forming a thin film transistor is provided. A gate dielectric layer is formed, which may be a bilayer, the first layer deposited at a low rate and the second deposited at a high rate. In some embodiments, the first dielectric layer is a silicon rich... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090261330 - Thin film transistor and manufacturing method thereof: It is an object to control quality of a microcrystalline semiconductor film or a semiconductor film including crystal grains so that operation characteristics of a semiconductor element typified by a TFT can be improved. It is another object to improve characteristics of a semiconductor element typified by a TFT by... Agent: Nixon Peabody, LLP

20090261328 - Thin film transistor and method for manufacturing the same: Disclosed is a thin film transistor which includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode; a semiconductor layer which functions as a channel formation region; and a semiconductor layer including an impurity element imparting one conductivity type. The semiconductor layer exists in... Agent: Nixon Peabody, LLP

20090261333 - Display substrate and method of manufacturing the same: A display substrate includes a signal line, a thin-film transistor (“TFT”), a key pattern, a light-blocking pattern, a color filter, a pixel electrode and an alignment key. The signal line and the key pattern are formed on a substrate. The TFT is electrically connected to the signal line. The light-blocking... Agent: Cantor Colburn, LLP

20090261334 - Liquid crystal display device: A thin film transistor substrate of fringe field switching type and a fabricating method thereof for simplifying a process are disclosed. In the thin film transistor substrate of fringe field switching type, a gate line has a multiple-layer structure and includes a transparent conductive layer. A data line crosses the... Agent: Mckenna Long & Aldridge LLP

20090261335 - Pixel unit structure of self-illumination display with low-reflection: A self-illumination display is provided, including a first substrate, a light-absorbing structure, a filter layer, a driving circuit unit, and a self-illumination unit. The light-absorbing structure and the filter layer are juxtaposedly disposed over the first substrate. The driving circuit unit is disposed over and shielded by the light-absorbing structure.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090261332 - Thin film transistor array panel, fabricating method thereof and flat panel display having the same: A thin film transistor array panel includes a substrate, a gate line disposed on the substrate and having a gate electrode, a gate insulating layer disposed on the gate line, a data line disposed on the gate insulating layer and crossing the gate line, a source electrode connected to the... Agent: H.c. Park & Associates, PLC

20090261336 - Array substrate for display device and method of manufacturing the same: An array substrate includes a substrate, a data line formed on the substrate, a passivation layer formed on the data line, a gate line including a gate electrode and a capacitor line formed on the passivation layer, a gate insulation layer formed on the gate electrode and the capacitor line,... Agent: Haynes And Boone, LLPIPSection

20090261338 - Active matrix substrate, display device, and television receiver: An active matrix substrate includes a plurality of transistors. A source electrode is connected with a data signal line, and a drain electrode is connected with a pixel electrode in each transistor. The source electrode is located on a semiconductor layer, and at least a portion of the drain electrode... Agent: Sharp Kabushiki Kaisha C/o Keating & Bennett, LLP

20090261342 - Array substrate of thin film transistor liquid crystal display and method of manufacturing the same: An embodiment of the invention provides an array substrate of a thin film transistor liquid crystal display comprising a gate line and a data line formed on a base substrate, a pixel electrode formed in a pixel region defined by intersecting of the gate line and data line, and a... Agent: Ladas & Parry LLP

20090261340 - Display substrate, liquid crystal display device having the same and method of manufacturing a display substrate: A display substrate includes; a gate line disposed on a substrate, a first insulating layer disposed on the substrate including the gate line, the first insulating layer including an opening part extended in a direction crossing the gate line, a data line disposed on the first insulating layer and an... Agent: Cantor Colburn, LLP

20090261339 - Gate driver on array of a display and method of making device of a display: In a method of making device of a display, an insulating layer, a semiconductor layer, an ohmic contact layer, a second conductive layer, and a photoresist pattern are consecutively formed on a first conductive structure. The photoresist pattern includes a first thickness region, and a second thickness region outside the... Agent: North America Intellectual Property Corporation

20090261341 - Organic light emitting display and method of manufacturing the same: An organic light emitting display includes a pixel part adapted to generate a light and a metal oxide layer. The metal oxide layer is formed by oxidation of a metal layer combined with oxygen of gas or humidity in an inner space of the organic light emitting display. Accordingly, gas... Agent: Haynes And Boone, LLPIPSection

20090261337 - Semiconductor device: It is an object to provide a transistor having a new multigate structure in which operating characteristics and reliability are improved. In a transistor having a multigate structure, which includes two gate electrodes electrically connected to each other and a semiconductor layer including two channel regions connected in series formed... Agent: Nixon Peabody, LLP

20090261343 - High-density nonvolatile memory and methods of making the same: Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first... Agent: Dugan & Dugan, PC

20090261344 - Relaxation of a strained layer using a molten layer: A method for making a crystalline wafer, in which an interface layer is associated with a support substrate. A first layer is associated with the interface layer in a strained state. The interface layer is melted sufficiently to substantially uncouple the first layer from the support substrate to relax the... Agent: Winston & Strawn LLP Patent Department

20090261346 - Integrating cmos and optical devices on a same chip: An integrated circuit structure includes a semiconductor substrate having a first surface region and a second surface region, wherein the first surface region and the second surface region have different surface orientations; a semiconductor device formed at a surface of the first surface region; and a group-III nitride layer over... Agent: Slater & Matsil, L.L.P.

20090261345 - Method for manufacturing compliant substrate, compliant substrate manufactured thereby, gallium nitride based compound semiconductor device having the compliant substrate and manufacturing method thereof: A compliant substrate having a reduced stress, a method for manufacturing the same having a reduced manufacturing time, a gallium nitride based compound semiconductor device including the compliant substrate and a method for manufacturing the same are disclosed. The compliant substrate is manufactured by heating a substrate and a group... Agent: The Nath Law Group

20090261347 - Diamond semiconductor element and process for producing the same: In a conventional diamond semiconductor element, because of high density of crystal defects, it is impossible to reflect the natural physical properties peculiar to a diamond, such as high thermal conductivity, high breakdown field strength, high-frequency characteristics and the like, in the transistor characteristics. By slightly shifting surface orientation of... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090261348 - Semiconductor device and semiconductor device manufacturing method: In a semiconductor device using a SiC substrate, a Junction Termination Edge (JTE) layer is hardly affected by fixed charge so that a stable dielectric strength is obtained. A semiconductor device according to a first aspect of the present invention includes a SiC epi-layer having n type conductivity, an impurity... Agent: Leydig Voit & Mayer, Ltd

20090261349 - Semiconductor device with strained channel and method of fabricating the same: A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the... Agent: Lowe Hauptman Ham & Berner, LLP

20090261351 - Silicon carbide devices having smooth channels: Power devices are provided including a p-type conductivity well region and a buried p+ conductivity region in the p-type conductivity well region. An n+ conductivity region is provided on the buried p+ conductivity region. A channel region of the power device is provided adjacent the buried p+ conductivity region and... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090261350 - Silicon carbide semiconductor device including deep layer: A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench sandwiched by each of the base region to the drift layer, a channel... Agent: Posz Law Group, PLC

20090261352 - Light emitting module: A light emitting module includes a dielectric substrate, a solar cell unit, a metal pattern layer, light emitting units, and a power storage component. The dielectric substrate has a first surface and a second surface opposite to the first surface. The solar cell unit is positioned on the first surface.... Agent: PCe Industry, Inc. Att. Steven Reiss

20090261353 - Production of self-organized pin-type nanostructures, and the rather extensive applications thereof: The invention relates to methods and devices comprising a nanostructure (2;4,4a) for improving the optical behavior of components and apparatuses and/or improving the behavior of sensors by increasing the active surface area. The nanostructure (2) is produced by means of a special RIE etching process, can be modified regarding the... Agent: Stevens & Showalter LLP

20090261354 - Organic light emitting element and organic light emitting device: The present invention relates to an organic light emitting element and an organic light emitting device including the same. An impurity layer close to an electrode is doped with a small amount, and an impurity layer for a p-n junction is doped with a large amount, such that a high... Agent: H.c. Park & Associates, PLC

20090261358 - Emission tuning methods and devices fabricated utilizing methods: A method for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs, typically on a wafer, and coating the LEDs with a conversion material so that at least some light from the LEDs passes through the conversion material and is converted. The light emission from the LED... Agent: Koppel, Patrick, Heybl & Dawson

20090261359 - Semiconductor device and fabrication method thereof: Regions 106 which can be regarded as being monocrystalline are formed locally by irradiating with laser light, and at least the channel-forming region 112 is constructed using these regions. With thin-film transistors which have such a construction it is possible to obtain characteristics which are similar to those which employ... Agent: Eric Robinson

20090261357 - Solid state light sheet and bare die semiconductor circuits with series connected bare die circuit elements: An electronically active sheet includes a bottom substrate having a bottom electrically conductive surface. A top substrate having a top electrically conductive surface is disposed facing the bottom electrically conductive surface. An electrical insulator separates the bottom electrically conductive surface from the top electrically conductive surface. At least one bare... Agent: Michaud-duffy Group LLP

20090261356 - Sub-mount, light emitting diode package and manufacturing method thereof: A sub-mount, a light emitting diode package, and a method of manufacturing thereof are disclosed. A sub-mount, on which multiple light emitting diodes are mounted, can include a multiple number of metal bodies on which the light emitting diodes are respectively mounted, and an oxide wall interposed between the metal... Agent: Staas & Halsey LLP

20090261355 - Thin film transistor: To provide: a thin film transistor which can be operated with a low threshold and has a high transistor withstand voltage; a production method of the thin film transistor; and a semiconductor device, an active matrix substrate, and a display device, each including such a thin film transistor. The present... Agent: Nixon & Vanderhye, PC

20090261360 - Light-emitting element, display device, and electronic apparatus: A light-emitting element includes a cathode, an anode, a first light-emitting layer that is disposed between the cathode and the anode and that emits light of a first color, a second light-emitting layer that is disposed between the first light-emitting layer and the cathode and that emits light of a... Agent: Oliff & Berridge, PLC

20090261362 - 4h-polytype gallium nitride-based semiconductor device on a 4h-polytype substrate: 4H—InGaAlN alloy based optoelectronic and electronic devices on non-polar face are formed on 4H—AlN or 4H—AlGaN on (11-20) a-face 4H—SiC substrates. Typically, non polar 4H—AlN is grown on 4H—SiC (11-20) by molecular beam epitaxy (MBE). Subsequently, III-V nitride device layers are grown by metal organic chemical vapor deposition (MOCVD) with... Agent: Mcdermott Will & Emery LLP

20090261361 - Iii-nitride light emitting device with double heterostructure light emmitting region: A III-nitride light emitting layer is disposed between an n-type region and a p-type region in a double heterostructure. At least a portion of the III-nitride light emitting layer has a graded composition.... Agent: Philips Intellectual Property & Standards

20090261363 - Group-iii nitride epitaxial layer on silicon substrate: A semiconductor device includes a silicon substrate; silicon faceted structures formed on a top surface of the silicon substrate; and a group-III nitride layer over the silicon faceted structures. The silicon faceted structures are separated from each other, and have a repeated pattern.... Agent: Slater & Matsil, L.L.P.

20090261364 - Fluorescent substance: A fluorescent substance characterized by comprising a base crystal composed of a compound represented by the formula: M1aM2bNc wherein M1 is at least one element selected from the group consisting of Mg, Ca, Sr, Ba and Zn; M2 is at least one element selected from the group consisting of Al,... Agent: Fitch, Even, Tabin & Flannery

20090261368 - Led chip package structure using a substrate as a lampshade and method for making the same: An LED chip package structure using a substrate as a lampshade includes a substrate unit and a light-emitting unit. The substrate unit has a substrate body with a lampshade shape. The light-emitting unit has a plurality of light-emitting elements electrically disposed on an inner surface of the substrate body. Therefore,... Agent: Rosenberg, Klein & Lee

20090261371 - Light-emitting device: An embodiment of the invention concerns a light-emitting device with an adjustable, time-variable luminance. This is achieved through electrically conductive tracks that are applied to the first electrode area. The conductive tracks are driven in a time-variable manner with different levels of electrical power.... Agent: Slater & Matsil, L.L.P.

20090261369 - Light-emitting device and manufacturing method thereof: A first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked in this order (a thin-film stacked body); first etching is performed to expose the first conductive film and form at least a pattern of the thin-film stacked body;... Agent: Fish & Richardson P.C.

20090261373 - Low optical loss electrode structures for leds: An electrode structure is disclosed for enhancing the brightness and/or efficiency of an LED. The electrode structure can have a metal electrode and an optically transmissive thick dielectric material formed intermediate the electrode and a light emitting semiconductor material. The electrode and the thick dielectric cooperate to reflect light from... Agent: Haynes And Boone, LLPIPSection

20090261367 - Optical erase memory structure: A method for providing an optical erase memory structure including: forming a metal-insulator-metal memory cell; positioning a light emitting diode adjacent to the metal-insulator-metal memory cell; and emitting a light emission from the light emitting diode for erasing the metal-insulator-metal memory cell.... Agent: Law Offices Of Mikio Ishimaru

20090261366 - Optoelectronic component: An optoelectronic component with a semiconductor body that comprises an active semiconductor layer sequence is disclosed, which is suitable for generating electromagnetic radiation of a first wavelength that is emitted from a front face of the semiconductor body. The component also comprises a first wavelength conversion substance following the semiconductor... Agent: Fish & Richardson PC

20090261365 - Optoelectronic componet which emits electromagnetic radiation, and method for production of an optoelectronic component: An optoelectronic component comprising a housing and a luminescence diode chip arranged in the housing is specified, which component emits a useful radiation. The housing has a housing material which is transmissive to the useful radiation and which is admixed with radiation-absorbing particles in a targeted manner for setting a... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090261370 - Semiconductor light emitting device: Disclosed is a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, a second conductive semiconductor layer under the active layer, a second electrode layer under the second conductive semiconductor layer, and a transmissive conductive... Agent: Birch Stewart Kolasch & Birch

20090261372 - Semiconductor light emitting device and method for fabricating the same: A semiconductor light emitting device is composed of a blue light emitting diode, a red light emitting layer grown epitaxially on the blue light emitting diode, and an insulating material containing a YAG fluorescent material. The red light emitting layer is made of, e.g., undoped In0.4Ga0.6N having a forbidden band... Agent: Greenblum & Bernstein, P.L.C

20090261374 - High output power light emitting device and packaged used therefor: An object of the present invention is to provide a light emitting device that has high output power and long service life where a package is suppressed from discoloring due to heat generation. The light emitting device 1 of the present invention contains a light emitting element 10, a package... Agent: Birch Stewart Kolasch & Birch

20090261375 - Package-base structure of luminescent diode and fabricating process thereof: A package-base structure of a luminescent diode and its fabricating process. The package-base structure includes a substrate having thereon a holding space; an insulating layer extending from a bottom surface of the holding space to the bottom of the substrate; an through hole defined in the insulating layer; and a... Agent: Kirton And Mcconkie

20090261377 - Method for bonding semiconductor structure with substrate and high efficiency photonic device manufactured by using the same method: A method for bonding a semiconductor structure with a substrate and a high efficiency photonic device manufactured by using the same method are disclosed. The method comprises steps of: providing a semiconductor structure and a substrate; forming a composite bonding layer on the semiconductor structure; and bonding the substrate with... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090261376 - Nitride semiconductor light emitting diode and method of fabricating the same: The present invention provides a light emitting diode comprising a substrate: a nitride semiconductor layer formed on the substrate; an ITO mask pattern formed on the nitride semiconductor layer; an N-type semiconductor layer formed through lateral growth on the nitride semiconductor layer and the ITO mask pattern; and a P-type... Agent: H.c. Park & Associates, PLC

20090261378 - Devices with adjustable dual-polarity trigger - and holding-voltage/current for high level of electrostatic discharge protection in sub-micron mixed signal cmos/bicmos integrated: Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1—N2—P2—N1//N1—P3—N3—P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A... Agent: Mh2 Technology Law Group, LLP

20090261379 - Semiconductor device with a semiconductor body and method for its production: A semiconductor device includes an active region with a vertical drift path of a first conduction type and with a near-surface lateral well of a second, complementary conduction type. In addition, the semiconductor device has an edge region surrounding the active region. This edge region has a variable lateral doping... Agent: Dicke, Billig & Czaja

20090261381 - Cmos transistor using germanium condensation and method of fabricating the same: Provided is a CMOS transistor formed using Ge condensation and a method of fabricating the same. The CMOS transistor may include an insulating layer, a silicon layer on the insulating layer and including a p-MOS transistor region and an n-MOS transistor region, a first gate insulating layer and a first... Agent: Harness, Dickey & Pierce, P.L.C

20090261382 - Compound semiconductor substrate for a field effect transistor: o

20090261380 - Transistors having asymetric strained source/drain portions: A semiconductor structure. The structure includes (a) a fin region having (i) a first source/drain portion having a first surface and a third surface, wherein the first and third surfaces are (A) parallel to each other and (B) not coplanar, (ii) a second source/drain portion having a second surface and... Agent: Schmeiser, Olsen & Watts

20090261383 - Optical device having strained buried channel: Provided is an optical device having a strained buried channel area. The optical device includes: a semiconductor substrate of a first conductive type; a gate insulating layer formed on the semiconductor substrate; a gate of a second conductive type opposite to the first conductive type, formed on the gate insulating... Agent: Ampacc Law Group

20090261384 - Gallium nitride high electron mobility transistor having inner field-plate for high power applications: A gallium nitride high electron mobility transistor, in which an inner field-plate is disposed between the gate and drain of the high electron mobility transistor, so that an electric field is distributed between gate and drain regions to reduce a peak value and to reduce gate leakage current while maintaining... Agent: Bachman & Lapointe, P.C.

20090261385 - Bipolar transistor with enhanced base transport: A bipolar transistor includes a base layer design and a method for fabricating such a bipolar transistor that employ a built-in accelerating field focused on a base region adjacent to a collector, where minority carrier transport is otherwise retarded. The accelerating field of the base layer includes on average, a... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20090261386 - Semiconductor integrated circuit device and method of arranging wirings in the semiconductor integrated circuit device: A semiconductor integrated circuit device includes a first component, a second component, a plurality of first, second and third contacts, and a plurality of signal lines having a plurality of first wires, and connecting the first and second component, each of the first wires having a first, second, third and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090261387 - Cmos integrated process for fabricating monocrystalline silicon micromechanical elements by porous silicon micromachining: The invention relates to a process for fabricating a monocrystalline Si-micromechanical element integrated with a CMOS circuit element within the CMOS technology, wherein a domain of second conducting property is formed within a substrate of first conducting property, here the second conducting property is reverse with respect to the first... Agent: Davidson Berquist Jackson & Gowdey LLP

20090261390 - semiconductor memory device and a method of manufacturing the same: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090261391 - Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a... Agent: Trop, Pruner & Hu, P.C.

20090261389 - Composition for oxide semiconductor thin film, field effect transistor using the composition, and method of fabricating the transistor: A composition for an oxide semiconductor thin film, a field effect transistor (FET) using the composition, and a method of fabricating the FET are provided. The composition includes an aluminum oxide, a zinc oxide, and a tin oxide. The thin film formed of the composition remains in amorphous phase at... Agent: Rabin & Berdo, PC

20090261388 - Dice by grind for back surface metallized dies: Semiconductor device processing and methods for dicing a semiconductor wafer into a plurality of individual dies that can have back surface metallization are described. The methods comprise providing a wafer with pre-diced streets in the wafer's front surface, applying a sidewall masking mechanism to the front surface of the wafer... Agent: Kenneth E. Horton Kirton & Mcconkle

20090261392 - Solid-state imaging device and method of manufacturing the same and electronic apparatus: A solid-state imaging device is provided. The solid-state imaging device includes a pixel section, a peripheral circuit section, a silicide blocking layer formed in the pixel section except for part or whole of an area above an isolation portion in the pixel section, and a metal-silicided transistor formed in the... Agent: Sonnenschein Nath & Rosenthal LLP

20090261393 - Composite transfer gate and fabrication thereof: A composite transfer gate is described, which is disposed over a semiconductor substrate between an electron reservoir and a floating node in the semiconductor substrate. The composite transfer gate includes at least one N-type portion and a P-type portion that are arranged laterally.... Agent: J C Patents

20090261394 - Method and system for creating photosensitive array with integrated backplane: A method of fabricating a photoactive array having an integrated backplane is provided. The layers of the device may be stamped or deposited on a planar or a curved substrate, such as a semispherical or ellipsoidal substrate. Each metal layer may be stamped using an elastomeric stamp and a vacuum... Agent: Townsend And Townsend And Crew, LLP

20090261395 - Integrated circuit including a ferroelectric memory cell and method of manufacturing the same: A method for manufacturing an integrated circuit including a ferroelectric memory cell is disclosed. One embodiment of the method includes: forming a amorphous oxide layer over a carrier, the amorphous layer including: O and any of the group of: Hf, Zr and (Hf,Zr), forming a covering layer on the amorphous... Agent: Edell, Shapiro & Finnan, LLC

20090261396 - Semiconductor structure and method of manufacture: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.... Agent: Hvvi Semiconductors, Inc.

20090261397 - Integrated circuit with floating-gate electrodes including a transition metal and corresponding manufacturing method: An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes... Agent: Coats & Bennett/qimonda

20090261398 - Non-volatile memory with sidewall channels and raised source/drain regions: A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions... Agent: Vierra Magen/sandisk Corporation

20090261399 - Nonvolatile semiconductor memory device and manufacturing method thereof: A nonvolatile semiconductor memory device includes a semiconductor substrate of a first conductivity type, a pair of source and drain diffusion regions of a second conductivity type oppositely formed on a surface of the semiconductor substrate, and a stacked structure having a gate insulating film, a charge accumulation film, an... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090261400 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a tunnel insulating film formed on a semiconductor substrate, a charge storage insulating film formed on the tunnel insulating film and including at least two separated low oxygen concentration portions and a high oxygen concentration portion positioned between the adjacent low oxygen concentration portions and having... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090261402 - Method and structure for a semiconductor charge storage device: A semiconductor charge storage device includes a semiconductor substrate having a surface region. The semiconductor substrate is characterized by a first conductivity type. A charge trapping material overlies and is in contact with at least a portion of the surface region of the semiconductor substrate. The charge trapping material is... Agent: Townsend And Townsend And Crew, LLP

20090261401 - Non-volatile memory cell and method of fabricating the same: A non-volatile memory cell is described, including a semiconductor substrate, two separate charge trapping structures on the substrate, first spacers at least on the opposite sidewalls of the two charge trapping structures, a gate dielectric layer on the substrate between the two charge trapping structures, a gate on the two... Agent: North America Intellectual Property Corporation

20090261404 - Non-volatile memory device: A non-volatile memory device having a SONOS structure and a manufacturing method thereof, where a conductive layer is formed between a charge trap layer and a blocking insulation layer of the SONOS structure. Therefore, when a voltage is applied to a gate, the conductive layer undergoes voltage distributions. Accordingly, a... Agent: Marshall, Gerstein & Borun LLP

20090261405 - Non-volatile memory devices: Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping... Agent: Myers Bigel Sibley & Sajovec

20090261403 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a memory cell transistor including a first lower insulating film provided on a semiconductor substrate, a first intermediate insulating film provided on the first lower insulating film, a first upper insulating film provided on the first intermediate insulating film, and a first gate electrode provided on... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090261406 - Use of silicon-rich nitride in a flash memory device: A flash memory cell includes a charge storage element that includes at least a first layer and a second layer. One of the layers includes silicon-rich silicon nitride and the other layer includes silicon nitride. More specifically, the ratio of silicon-to-nitrogen in the first layer is greater than the ratio... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090261407 - Semiconductor device and manufacturing method of the same: Disclosed is a semiconductor device. The semiconductor device includes a first gate formed in a trench of a semiconductor substrate, a first gate oxide layer on the semiconductor substrate including the first gate, a first epitaxial layer on the first gate oxide layer, first source and drain regions in the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090261408 - Semiconductor device and method of forming the same: A semiconductor device includes a semiconductor substrate, a first diffusion region, a gate insulating film, a gate electrode, a second diffusion region and a contact plug. The semiconductor substrate includes a base and at least a pillar. The first diffusion region is disposed in the base. The gate insulating film... Agent: Young & Thompson

20090261409 - Semiconductor devices for high power application: Semiconductor devices for high voltage application are presented. A high power semiconductor device includes a first type doped semiconductor substrate and a second type doped epitaxial layer deposited thereon. A first type doped body region is disposed in the second type doped epitaxial layer. A heavily doped drain region is... Agent: Quintero Law Office, PC

20090261410 - Dmos transistor: This invention provides a DMOS transistor that has a reduced ON resistance and is prevented from deterioration in strength against an electrostatic discharge. An edge portion of a source layer of the DMOS transistor is disposed so as to recede from an inner corner portion of a gate electrode. A... Agent: Morrison & Foerster LLP

20090261411 - Integrated circuit including a body transistor and method: An integrated circuit including a floating body transistor and method. One embodiment provides a transistor including a body region formed in a first portion and a first and a second source/drain region formed in a second and a third portion. The body region is formed in a semiconductor substrate. The... Agent: Dicke, Billig & Czaja

20090261413 - Mosfet and manufacturing method thereof: The present invention provides a MOSFET capable of improving the basic performance of a transistor such as saturation current characteristics, input follow-up and an offleak current at high levels, and a manufacturing method thereof. The MOSFET comprises a semiconductor layer, a gate electrode formed over the semiconductor layer through a... Agent: Volentine & Whitt PLLC

20090261412 - Semiconductor device and manufacturing method of the same: A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a <100> direction on a (100) silicon substrate. A compressive stress... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090261414 - Semiconductor device and method for manufacturing the same: An object is to improve water resistance and reliability of a semiconductor device by reducing the degree of peeling of a film. In a semiconductor device, a first inorganic insulating layer, a semiconductor element layer, a second inorganic insulating layer, an organic insulating layer, and a third inorganic insulating layer... Agent: Cook Alex Ltd

20090261415 - Fully-depleted low-body doping field effect transistor (fet) with reverse short channel effects (sce) induced by self-aligned edge back-gate(s): Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090261416 - Integrated mems device and control circuit: An integrated circuit includes a silicon-on-insulator (SOI) substrate including a buried oxide layer positioned between a top-side silicon layer and a bottom-side silicon layer. A micro-electromechanical system (MEMS) device is integrated into the top-side silicon layer. A semiconductor layer is formed over the bottom-side silicon layer. A control circuit is... Agent: Dicke, Billig & Czaja

20090261417 - Trig modulation electrostatic discharge (esd) protection devices: Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first... Agent: Quintero Law Office, PC

20090261418 - Insulated gate semiconductor device: A protection diode group includes multiple protection diodes connected to each other in parallel. A total junction area average of the protection diode group is set to a value large enough to guarantee a desired electrostatic discharge tolerance. By setting the total junction area average to be equal to a... Agent: Morrison & Foerster LLP

20090261420 - Recess gate transistor: A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to... Agent: F. Chau & Associates, LLC

20090261419 - Semiconductor device having assist features and manufacturing method thereof: A semiconductor device having assist features and manufacturing method thereof includes a substrate having at least an active region and a peripheral region defined thereon. The semiconductor device also includes a plurality of assist features positioned in the peripheral region, or in the active region with a dotted line pattern.... Agent: North America Intellectual Property Corporation

20090261421 - Semiconductor structure and method of manufacture: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.... Agent: Hvvi Semiconductors, Inc.

20090261422 - Cell structure of semiconductor device: A cell structure of a semiconductor device includes an active region, having a concave portion, and an inactive region that defines the active region. A gate pattern in the active region is arranged perpendicular to the active region. A landing pad on the active region and the inactive region contacts... Agent: Volentine & Whitt PLLC

20090261424 - Method for fabricating a dual workfunction semiconductor device and the device made thereof: A dual workfunction semiconductor device and a device made thereof is disclosed. In one aspect, the device includes a first gate stack in a first region and a second gate stack in a second region. The first gate stack has a first effective workfunction, and the second gate stack has... Agent: Knobbe Martens Olson & Bear LLP

20090261423 - Semiconductor device and method for manufacturing same: A semiconductor device includes a fin field effect transistor configured to include at least a first fin and a second fin. Threshold voltage of the first fin and threshold voltage of the second fin are different from each other in the fin field effect transistor.... Agent: Sonnenschein Nath & Rosenthal LLP

20090261425 - Finfets single-sided implant formation: A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are parallel to the fins and... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090261426 - Lateral diffusion field effect transistor with drain region self-aligned to gate electrode: A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be... Agent: Scully, Scott, Murphy & Presser, P.C.

20090261427 - Mos p-n junction diode device and method for manufacturing the same: A MOS P-N junction diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. The method for... Agent: Wpat, PC

20090261428 - Mos p-n junction schottky diode device and method for manufacturing the same: A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic... Agent: Wpat, PC

20090261429 - Transistor and method for manufacturing thereof: A transistor includes a gate insulating layer over a semiconductor substrate; a first insulating layer on both sides of the gate insulating layer; first spacers over the first insulating layer and being spaced apart from each other; and a gate conductive plug between the first spacers. A method for manufacturing... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090261430 - Physical quantity sensor and method for manufacturing the same: A physical quantity sensor includes: a sensor substrate including a first support substrate, a first insulation film and a first semiconductor layer, which are stacked in this order; a cap substrate including a second support substrate disposed on the first semiconductor layer, and has a P conductive type; and multiple... Agent: Posz Law Group, PLC

20090261432 - Interconnection system on a plane adjacent to a solid-state device structure: An interconnection system is provided for a solid-state device. The solid-state that includes, a first layer, multiple devices and a first face. A second layer is bonded to the first face at a bonded face of the second layer that faces the first face. Electrically conductive bonds are between the... Agent: Goodwin Procter LLP Attn: Patent Administrator

20090261431 - Pre-released structure device:

20090261435 - Magnetic memory element and magnetic memory device: A magnetic memory element having a layer structure containing a fixing layer (pinned layer: PL) having a magnetization direction fixed unidirectionally, a nonmagnetic dielectric layer (TN1) in contact with the fixing layer (PL), and a memory layer (free layer: FL) having a first surface in contact with the nonmagnetic dielectric... Agent: Mcdermott Will & Emery LLP

20090261436 - Negative-resistance device with the use of magneto-resistive effect: A magneto-resistive device has a magnetic free layer (33), a magnetic pinned layer (31) having a magnetic moment larger than that of the magnetic free layer, and an intermediate layer (32) provided between the magnetic free layer and the magnetic pinned layer. The negative-resistance device is characterized in that the... Agent: Fitzpatrick Cella Harper & Scinto

20090261433 - One-mask mtj integration for stt mram: A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit includes providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and at least a first metal interconnect. Over the first interlevel dielectric layer and the first metal interconnect, magnetic... Agent: Qualcomm Incorporated

20090261434 - Stt mram magnetic tunnel junction architecture and integration: A magnetic tunnel junction (MTJ) device for a magnetic random access memory (MRAM) in a semiconductor back-end-of-line (BEOL) process flow includes a first metal interconnect for communicating with at least one control device and a first electrode for coupling to the first metal interconnect through a via formed in a... Agent: Qualcomm Incorporated

20090261437 - Two mask mtj integration for stt mram: A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer containing an exposed first interconnect metallization, a first electrode, a fixed magnetization layer, a tunneling barrier layer, a free magnetization layer and a second electrode.... Agent: Qualcomm Incorporated

20090261438 - Visible-range semiconductor nanowire-based photosensor and method for manufacturing the same: A semiconductor nanowire-based photosensor includes a substrate, at least a top surface of the substrate being formed of an insulator, two electrodes spaced at a predetermined interval apart from each other on the substrate, metal catalyst layers disposed respectively on the two electrodes, and visible-range semiconductor nanowires grown from the... Agent: Renner Otto Boisselle & Sklar, LLP

20090261439 - Microlens array and image sensing device using the same: A microlens array is provided, including a base layer with a plurality of first microlenses formed over a first region thereof, wherein the first microlenses are formed with a first height. A plurality of second microlenses are formed over a second region of the base layer, wherein the second region... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090261440 - Microlens unit and image sensor: In a microlens unit (MSU), at least part of the edges of microlenses (MS) (convex lenses MS[BG]) supported on elevations (BG) overlap with trenches (DH) in a direction (VV) perpendicular to the surface of a flattening film (31).... Agent: Edwards Angell Palmer & Dodge LLP

20090261441 - Optical semiconductor device: An optical semiconductor device includes a light-receiving element on a semiconductor substrate of a first conductivity type, the light-receiving element including a light-receiving portion for converting incident light to an electrical current signal and performing a current amplification. The light-receiving portion includes: a semiconductor layer formed on the semiconductor substrate... Agent: Mcdermott Will & Emery LLP

20090261442 - Nonequilibrium photodetectors with single carrier species barriers: A photosensitive diode has an active region defining a majority carrier of a first conductivity type and a minority carrier of a second conductivity type. An extraction region is disposed on a first side of the active region and extracts minority carriers from the active region. It also has majority... Agent: Momkus Mccluskey, LLC

20090261443 - Shared-pixel-type image sensor and method of fabricating the same: A shared-pixel-type image sensor including a shared floating diffusion region formed in a semiconductor substrate; first and second adjacent photoelectric conversion regions sharing the floating diffusion region; two transmission elements that alternately transfer electric charges accumulated in the first and second photoelectric conversion regions to the shared floating diffusion region,... Agent: F. Chau & Associates, LLC

20090261444 - Semiconductor device: A wiring electrically connected to a terminal to which a high power supply potential is applied and a wiring electrically connected to a terminal to which a low power supply potential is applied are formed adjacent to each other and are formed so as to surround the integrated circuit. Thus,... Agent: Nixon Peabody, LLP

20090261445 - Infrared detector and infrared solid-state imaging device: The infrared detector which comprises a first PN junction diode and a second PN junction diode which are formed in a silicon layer formed apart from a support substrate, the silicon layer having a P-type first region and an N-type second region, wherein the first PN junction diode is composed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090261447 - Semiconductor integrated circuit: Signal lines (13) and (14) to be used for supplying a signal between an analog circuit and a digital circuit are provided in different regions from power-ground lines (11) and (12) to be used for supplying a power to the analog circuit and the digital circuit in such a manner... Agent: Connolly Bove Lodge & Hutz LLP

20090261446 - Semiconductor structure and method of manufacture: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.... Agent: Hvvi Semiconductors, Inc.

20090261448 - Method of forming shallow trench isolation structures for integrated circuits: A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is... Agent: HorizonIPPte Ltd

20090261449 - Method for manufacturing soi substrate and semiconductor device: An object is to provide an SOI substrate with excellent characteristics even in the case where a single crystal semiconductor substrate having crystal defects is used. Another object is to provide a semiconductor device using such an SOI substrate. A single crystal semiconductor layer is formed by an epitaxial growth... Agent: Eric Robinson

20090261450 - Electrical fuse structure and method: An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer.... Agent: Slater & Matsil, L.L.P.

20090261451 - Circuit protection device including resistor and fuse element: An integral circuit protection device includes a substrate disposed between first and second terminals. The substrate is composed of a resistive material. A first conductive layer is disposed on a first surface of the substrate and in electrical contact with the first terminal. A second conductive layer is disposed on... Agent: K&l Gates LLP

20090261453 - Air gap in integrated circuit inductor fabrication: A semiconductor device, such as an inductor, is formed with an air gap. A first level has an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures. An inter-level dielectric layer is formed over the first level. An extraction... Agent: Texas Instruments Incorporated

20090261452 - Semiconductor device including an inductor element: An inductor element is formed in a spiral shape so as to have a plurality of windings which cross each other three-dimensionally at least in one intersection on a substrate. Each of the plurality of windings is formed by a first wiring formed on the substrate with a first insulating... Agent: Mcdermott Will & Emery LLP

20090261454 - Capacitor in semiconductor device and method of fabricating the same: A capacitor includes a bottom electrode, a dielectric layer and a top electrode over a substrate. A RuXTiYOZ film is included in at least one of the bottom and top electrodes, where x, y and z are positive real numbers. A method of fabricating the capacitor through a sequential formation... Agent: Lowe Hauptman Ham & Berner, LLP

20090261456 - Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafers: A multiplicity of silicon wafers polished at least on their front sides are provided and successively coated individually in an epitaxy reactor by a procedure whereby one of the wafers is placed on a susceptor in the epitaxy reactor, is pretreated under a hydrogen atmosphere at a first hydrogen flow... Agent: Brooks Kushman P.C.

20090261455 - Method for the production of a component structure: A method for the production of a component structure. On embodiment provides a semiconductor body having a first side. A first trench and a second trench are produced, which extend into the semiconductor body proceeding from the first side and are arranged at a distance from one another in a... Agent: Dicke, Billig & Czaja

20090261457 - Die stacking with an annular via having a recessed socket: A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a variety of electronic systems. In an embodiment, a die stack includes a conductive pillar on the top of a die inserted... Agent: Schwegman, Lundberg & Woessner/micron

20090261458 - Through-electrode, circuit board having a through-electrode, semiconductor package having a through-electrode, and stacked semiconductor package having the semiconductor chip or package having a through-electrode: A stacked semiconductor package includes a first semiconductor package having a first semiconductor chip having a first pad and a through-hole passing through a the portion corresponding to the pad; a second semiconductor package disposed over the first semiconductor package, and including a second semiconductor chip having a second pad... Agent: Ladas & Parry LLP

20090261459 - Semiconductor device having a floating body with increased size and method for manufacturing the same: A semiconductor device with a silicon on insulator substrate having a stacked structure including a silicon substrate, a filled oxide layer, and a silicon layer is provided with a fin pattern formed in the direction of the channel width in a gate forming region of the silicon layer. The fin... Agent: Ladas & Parry LLP

20090261460 - Wafer level integration package: A semiconductor package has a first conductive layer formed on a top surface of a substrate. A conductive via is formed between the first conductive layer and a bottom surface of the substrate. A semiconductor component is mounted to the substrate and electrically connected to the first electrical contact pad.... Agent: Robert D. Atkins

20090261461 - Semiconductor package with lead intrusions: Semiconductor packages comprising a plurality of lead fingers containing a lead intrusion at the edge of the lead fingers are described. The semiconductor packages comprise an integrated circuit chip that is connected to a die pad and is electrically connected to multiple lead fingers. One or more of the lead... Agent: Kenneth E. Horton Kirton & Mcconkle

20090261462 - Semiconductor package with stacked die assembly: This application relates to semiconductor packages comprising stacked die assemblies. In some cases, the stacked dies comprise a first die containing gate driver IC that is stacked on a first surface of a second IC die. A second surface of the second IC die can be bumped for connection to... Agent: Kenneth E. Horton Kirton & Mcconkle

20090261463 - Chip mounting device and chip package array: A chip mounting device includes at least one chip mounting unit and at least one side rail configured beside the chip mounting unit. The chip mounting unit includes a die pad and a plurality of conductive contacts. The side rail includes at least one identifying element. A chip package array... Agent: Rosenberg, Klein & Lee

20090261464 - Getter formed by laser-treatment and methods of making same: The present disclosure relates to methods of treating a silicon substrate with an ultra-fast laser to create a getter material for example in a substantially enclosed MEMS package. In an embodiment, the laser treating comprises irradiating the silicon surface with a plurality of laser pulses adding gettering microstructure to the... Agent: Pepper Hamilton LLP

20090261465 - Semiconductor device and its manufacturing method: A semiconductor device includes a substrate having a substrate wiring, a semiconductor chip provided on the substrate, a first electrical conductor electrically connecting the semiconductor chip and the substrate wiring, and an electrically conductive pad provided on the substrate. The semiconductor device further includes a wiring member electrically connected to... Agent: Mcdermott Will & Emery LLP

20090261466 - Semiconductor device and method of forming vertical interconnect structure using stud bumps: A semiconductor device is made by forming a conductive layer over a temporary carrier. The conductive layer includes a wettable pad. A stud bump is formed over the wettable pad. The stud bump can be a stud bump or stacked bumps. A semiconductor die is mounted to the carrier. An... Agent: Robert D. Atkins

20090261467 - Semiconductor device: A semiconductor device including a semiconductor chip having a plurality of electrodes on one surface thereof in a thickness direction, a resin layer overlapping the one chip surface to provide a rectangular mounting surface, a plurality of metal posts in the resin layer, where the metal posts are electrically connected... Agent: Rabin & Berdo, PC

20090261468 - Semiconductor module: A semiconductor module. One embodiment provides at least two semiconductor chips placed on a carrier. The at least two semiconductor chips are then covered with a molding material to form a molded body. The molded body is thinned until the at least two semiconductor chips are exposed. Then, the carrier... Agent: Dicke, Billig & Czaja

20090261469 - Semiconductor package and method for manufacturing the same: Manufacturing a semiconductor package includes preparing a semiconductor chip having a top surface with bumps electrically connected to bonding pads, a bottom surface opposite to the top surface and side surfaces joining the top surface to the bottom surface. The bottom surface of the semiconductor chip is attached to a... Agent: Ladas & Parry LLP

20090261470 - Chip package: A chip package comprising a carrier, a chip, a plurality of first conductive elements, an encapsulation, and a conductive film is provided. The carrier has a carrying surface and a back surface opposite to the carrying surface. Furthermore, the carrier has a plurality of common contacts in the periphery of... Agent: J C Patents

20090261471 - Rf power transistor package: An RF power transistor package with a rectangular ceramic base can house one or more dies affixed to an upper surface of the ceramic base. Source leads attached to the ceramic base extend from at least opposite sides of the rectangular base beneath a periphery of a non-conductive cover overlying... Agent: Marger Johnson & Mccollom, P.C.

20090261472 - Power semiconductor module with pressure element and method for fabricating a power semiconductor module with a pressure element: The invention relates to a power semiconductor module comprising at least one power semiconductor chip, and comprising a pressure apparatus which exerts a pressure on the top side of the power semiconductor chip when the power semiconductor module is fixed to a heat sink. In addition, a bonding wire which... Agent: Coats & Bennett/infineon Technologies

20090261473 - Low fabrication cost, fine pitch and high reliability solder bump: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about... Agent: Mou-shiung Lin

20090261474 - Wafer level package having a stress relief spacer and manufacturing method thereof: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes... Agent: Mills & Onello LLP

20090261475 - Method for fabricating a metal interconnection using a dual damascene process and resulting semiconductor device: A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower interconnections, wherein widths of the trenches are greater than widths of the via holes, and metal interconnections formed by burying metal thin films... Agent: Sherr & Vaughn, PLLC

20090261476 - Semiconductor device and manufacturing method thereof: A semiconductor device and a manufacturing method thereof are disclosed. The method includes the steps of providing a carrier board having conductive circuits disposed thereon and a plurality of chips with active surfaces having solder pads disposed thereon, wherein conductive bumps are disposed on the solder pads; mounting chips on... Agent: Edwards Angell Palmer & Dodge LLP

20090261477 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device including a trench and a contact hole filled with a copper line, a diffusion barrier layer formed in inner walls of the trench and the contact hole, and a seed-copper layer formed on and/or over the diffusion barrier layer. The surface roughness of... Agent: Sherr & Vaughn, PLLC

20090261478 - Semiconductor device and method for manufacturing the same: The present invention constitutes a semiconductor device wherein a Ni-containing metal silicide layer is formed on a semiconductor substrate and its uppermost surface is nitrided. According to this structure, a dangling bond of silicon existing in the metal silicide layer and nitrogen are bonded by nitridation of the uppermost surface... Agent: Mcdermott Will & Emery LLP

20090261479 - Methods for pitch reduction: An integrated circuit described herein includes a substrate and a plurality of lines overlying the substrate. The lines define a plurality of first trenches and a plurality of second trenches. The plurality of first trenches extend into the substrate a distance different than that of the plurality of second trenches.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090261480 - Integrated circuit and method of fabricating the same: An article including a substrate having a blind hole formed therein, wherein the blind hole is defined by a floor and a sidewall and a solder connection is provided. The solder connection may couple a first contact pad to a second contact pad. The first contact pad may cover a... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090261481 - Wafer level package and method of fabricating the same: Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal... Agent: Rabin & Berdo, PC

20090261483 - Adhesive composition, adhesive composition for circuit connection, connected body semiconductor device: An adhesive composition containing: (a) a thermoplastic resin; (b) a radical-polymerizable compound including two or more (meth)acryloyl groups; (c) a curing agent that generates a radical by photoirradiation of 150 to 750 nm and/or heating at 80 to 200° C.; and (d) a liquid rubber having a viscosity of 10... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090261482 - Semiconductor package and method of making same: A semiconductor package (20) includes an organic substrate (24) and a semiconductor die subassembly (22). A method (50) for making the semiconductor package (20) entails providing (52) the organic substrate (24) having an opening (26) and electrical contacts (36). The subassembly (22) is formed by producing (64) a semiconductor die... Agent: Meschkow & Gresham, P.L.C

20090261484 - Liquid resin composition, semi-conductor device, and process of fabricating the same: A liquid resin composition for use as a sealing resin which reduces wear on a dicing blade or grinder employed for signularization or grinding. The liquid resin composition includes hollow and/or porous particles as a filler, and is adapted in use to be applied on a substrate constituting a semi-conductor... Agent: Cheng Law Group, PLLC

20090256127 - Compounds for depositing tellurium-containing films: Disclosed herein are tellurium metal-organic precursors and methods for depositing tellurium-containing films on a substrate.... Agent: Air Liquide Intellectual Property

20090256128 - Nonvolatile data storage, semicoductor memory device including nonvolatile data storage and method of forming the same: A data storage and a semiconductor memory device including the same are provided, the data storage including a lower electrode, a first discharge prevention layer stacked on the lower electrode, a phase-transition layer on the first discharge prevention layer, a second discharge prevention layer stacked on the phase-transition layer, and... Agent: Harness, Dickey & Pierce, P.L.C

20090256131 - Memory cell that employs a selectively fabricated carbon nano-tube reversible resistance-switching element formed over a bottom conductor and methods of forming the same: In some aspects, a method of fabricating a memory cell is provided that includes: (1) fabricating a first conductor above a substrate; (2) selectively fabricating a carbon nano-tube (“CNT”) material above the first conductor by: (a) fabricating a CNT seeding layer on the first conductor, wherein the CNT seeding layer... Agent: Dugan & Dugan, PC

20090256130 - Memory cell that employs a selectively fabricated carbon nano-tube reversible resistance-switching element, and methods of forming the same: In some aspects, a method of fabricating a memory cell is provided that includes fabricating a steering element above a substrate, and fabricating a reversible-resistance switching element coupled to the steering element by fabricating a carbon nano-tube (“CNT”) seeding layer by depositing a silicon-germanium layer above the substrate, patterning and... Agent: Dugan & Dugan, PC

20090256132 - Memory cell that includes a carbon-based memory element and methods of forming the same: In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more... Agent: Dugan & Dugan, PC

20090256129 - Sidewall structured switchable resistor cell: A method of making a memory device includes forming a first conductive electrode, forming an insulating structure over the first conductive electrode, forming a resistivity switching element on a sidewall of the insulating structure, forming a second conductive electrode over the resistivity switching element, and forming a steering element in... Agent: Sandisk Corporation C/o Foley & Lardner LLP

20090256133 - Multiple layer resistive memory: A resistive memory cell may be composed of four stacked layers. Each layer may be sandwiched by electrodes. Connections may be formed from each of four directions around the stack, for example, aligned with each of four edges where the resistive layers are rectangular.... Agent: Trop, Pruner & Hu, P.C.

20090256134 - Process for fabricating nanowire arrays: A process is provided for etching a silicon-containing substrate to form nanowire arrays. In this process, one deposits nanoparticles and a metal film onto the substrate in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not... Agent: Mintz, Levin, Cohn, Ferris, Glovsky And Popeo, P.c

20090256135 - Thermal electron emitter and thermal electron emission device using the same: A thermal electron emitter includes at least one carbon nanotube twisted wire and a plurality of electron emission particles mixed with the twisted wire. The carbon nanotube twisted wire comprises a plurality of carbon nanotubes. A work function of the electron emission particles is lower than the work function of... Agent: PCe Industry, Inc. Att. Steven Reiss

20090256136 - Microresonator systems and methods of fabricating the same: Various embodiments of the present invention are related to microresonator systems that can be used as a laser, a modulator, and a photodetector and to methods for fabricating the microresonator systems. In one embodiment, a microdisk comprises: a top layer; a bottom layer; an intermediate layer having at least one... Agent: Hewlett-packard Company Intellectual Property Administration

20090256140 - Light-detecting device structure: A light-detecting device structure comprises a substrate, a vertical organic light-emitting transistor and a light-detecting unit, wherein the vertical organic light-emitting transistor is disposed at a first location on the substrate, and the light-detecting unit is disposed at a second location on the substrate, in which the first and the... Agent: Juan Carlos A. Marquez C/o Stites & Harbison PLLC

20090256144 - Method for manufacturing organic transistor and organic transistor: A method of producing an organic transistor which can form directly an organic semiconductor layer in pattern by simple processes and can produce an organic transistor excellent in transistor characteristics. The method includes: forming a hydrophobic/hydrophilic pattern substrate, in which a hydrophobic/hydrophilic pattern substrate is formed by using a hydrophobic... Agent: Ladas & Parry LLP

20090256137 - N-type semiconductor materials in thin film transistors and electronic devices: A thin film transistor comprises a layer of organic semiconductor that comprises an N,N′-1,4,5,8-naphthalenetetracarboxylic acid diimide having at least one cycloalkyl group having a fluorinated substituent at its 4-position that adopts an equatorial orientation in the trans configuration of the cycloalkyl group and an axial orientation in the cis configuration... Agent: Eastman Kodak Company Patent Legal Staff

20090256143 - Oligothiophene-arylene derivatives and organic thin film transistors using the same: An oligothiophene-arylene derivative wherein an arylene having n-type semiconductor characteristics is introduced into an oligothiophene having p-type semiconductor characteristics, thereby simultaneously exhibiting both p-type and n-type semiconductor characteristics. Further, an organic thin film transistor using the oligothiophene-arylene derivative.... Agent: Buchanan, Ingersoll & Rooney PC

20090256141 - Organic photosensitive optoelectronic devices containing tetra-azaporphyrins: Embodiments of the present invention provide an organic photosensitive optoelectronic device comprising at least one tetra-azaporphyrin compound of formula (I) are disclosed herein.... Agent: Mcdermott Will & Emery LLP

20090256138 - Organic thin film transistor: b

20090256142 - Organic thin film transistor and method for manufacturing same: Disclosed are an organic thin film transistor exhibiting a high switching current value even when a distance (channel length) between source and the drain electrodes is large, and a manufacturing method thereof. The organic thin film transistor of the invention comprises a substrate, a gate electrode, a gate insulating layer,... Agent: Lucas & Mercanti, LLP

20090256145 - Organic thin film transistor and organic thin film light-emitting transistor: An organic thin film transistor including a substrate having thereon at least three terminals of a gate electrode, a source electrode and a drain electrode, an insulator layer and an organic semiconductor layer, with a current between a source and a drain being controlled upon application of a voltage to... Agent: Millen, White, Zelano & Branigan, P.C.

20090256139 - Thin-film transistors: A thin film transistor having a semiconducting layer with improved flexibility and/or mobility is disclosed. The semiconducting layer comprises a semiconducting polymer and insulating polymer. Methods for forming and using such thin-film transistors are also disclosed.... Agent: Fay Sharpe / Xerox - Rochester

20090256146 - Semiconductor substrate with solid phase epitaxial regrowth with reduced depth of doping profile and method of producing same: Method of producing a semiconductor device, comprising: a) providing a semiconductor substrate, b) providing an insulating layer on a top surface of the semiconductor substrate, c) making an amorphous layer in a top layer of said semiconductor substrate by a suitable implant, d) implanting a dopant into said semiconductor substrate... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090256147 - Thin film transistor and method of manufacturing the same: A thin film transistor, including a transparent channel pattern, a transparent gate insulating layer in contact with the channel pattern, a passivation film pattern disposed on the channel pattern, a source/drain coupled to the channel pattern through a via hole in the passivation film pattern, and a gate facing the... Agent: Lee & Morse, P.C.

20090256148 - Zinc oxide light emitting diode: Provided is a zinc oxide light emitting diode having improved optical characteristics. The zinc oxide light emitting diode includes an n-type semiconductor layer, a zinc oxide active layer formed on the n-type semiconductor layer, a p-type semiconductor layer formed on the active layer, an anode in electrical contact with the... Agent: Occhiuti Rohlicek & Tsao, LLP

20090256149 - Structure for measuring body pinch resistance of high density trench mosfet array: o

20090256150 - Thin film transistor array panel and method for manufacturing the same: A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate; a first signal line and a second signal line disposed on the substrate; a switching thin film transistor connected to the first signal line and the second signal line, and comprising a... Agent: Cantor Colburn, LLP

20090256151 - Display substrate and method of manufacturing the same: A display substrate comprises a substrate; a source electrode arranged on the substrate; a drain electrode arranged on the substrate and spaced from the source electrode; a semiconductor layer arranged on the source electrode and the drain electrode; an insulating layer arranged on the semiconductor layer; and a gate electrode... Agent: Haynes And Boone, LLPIPSection

20090256152 - Pixel structure for transflective lcd panel: A pixel structure for a transflective LCD having a transparent region and a reflective region is provided. The pixel structure includes a transparent substrate, a TFT, at least one reflective structure, a passivation layer, a pixel electrode and a reflective layer. The TFT is disposed in a reflective region of... Agent: J C Patents

20090256153 - Thin film transistor matrix device and method for fabricating the same: A method for fabricating a thin film transistor matrix device which includes forming a transparent insulating substrate, arranging a plurality of thin film transistors on the substrate in a matrix, arranging a plurality of picture element electrodes on the substrate in a matrix and connecting the picture element electrodes to... Agent: Greer, Burns & Crain

20090256154 - Flexible substrate, method of fabricating the same, and thin film transistor using the same: Ef representing Young's modulus of the buffer layer, vf representing Poisson's ratio of the buffer layer, αf representing a coefficient of thermal expansion of the buffer layer, and αs representing the predetermined coefficient of thermal expansion of the metal substrate.... Agent: Lee & Morse, P.C.

20090256158 - Array substrate of liquid crystal display device and method of manufacturing the same: An array substrate comprising a base substrate, a common electrode, a gate line, a data line, a thin film transistor, a passivation layer and a pixel electrode of “” shape. The thin film transistor comprises a gate electrode, an active layer, a source electrode and a drain electrode; the gate... Agent: Ladas & Parry LLP

20090256157 - Display device and manufacturing method of display device: A display device includes a first substrate on which a semiconductor circuit is formed. A second substrate is disposed over the first substrate to include a first electrode formed on a first surface to perform image displaying, and a second electrode exposed to a second surface and bonded to the... Agent: Cooper & Dunham, LLP

20090256156 - Hybrid imaging sensor with approximately equal potential photodiodes: A hybrid MOS or CMOS image sensor. The sensor includes photon-sensing elements comprised of an array of photo-sensing regions deposited in the form of separate islands on or in a substrate. Pixel circuitry is created on and/or in the substrate at or near the edge of or beneath the photon-sensing... Agent: Trex Enterprises Corp.

20090256155 - Thin film transistor array panel and method for manufacturing the same: A thin film transistor panel includes a substrate, a gate line extending in a first direction on the substrate, a data line disposed on the substrate, the data line crossing the gate line with an insulation layer therebetween and extending in a second direction, a thin film transistor including a... Agent: H.c. Park & Associates, PLC

20090256159 - Gan semiconductor device: This invention discloses a GaN semiconductor device comprising a substrate; a metal-rich nitride compound thin film on the substrate; a buffer layer formed on the metal-rich nitride compound thin film, and a semiconductor stack layer on the buffer layer wherein the metal-dominated nitride compound thin film covers a partial upper... Agent: Bacon & Thomas, PLLC

20090256162 - Method for producing semi-insulating resistivity in high purity silicon carbide crystals: A method is disclosed for producing high quality semi-insulating silicon carbide crystals in the absence of relevant amounts of deep level trapping elements. The invention includes the steps of heating a silicon carbide crystal having a first concentration of point defects to a temperature that thermodynamically increases the number of... Agent: Summa, Additon & Ashe, P.A.

20090256161 - Power conversion apparatus: In the case where a chip is made of wide band gap semiconductor, a power conversion apparatus is obtained in which a component having a low heat resistant temperature is prevented from receiving thermal damage by heat generated at the chip. In a configuration including: a chip portion (20) including... Agent: Birch Stewart Kolasch & Birch

20090256160 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device is provided. A gate structure is formed on a substrate. A first dopant implantation and a first strain atom implantation are performed. Thereafter, spacers are formed on sidewalls of the gate structure. A second dopant implantation and a second strain atom implantation are... Agent: Portal Ipr Office Chun-ming Shih

20090256164 - Active device array substrate and method for fabricating the same: An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090256163 - Leds using single crystalline phosphor and methods of fabricating same: Methods for fabricating LED chips from a wafer and devices fabricated using the methods with one method comprising depositing LED epitaxial layers on an LED growth wafer to form a plurality of LEDs on the growth wafer. A single crystalline phosphor is bonded over at least some the plurality of... Agent: Koppel, Patrick, Heybl & Dawson

20090256165 - Method of growing an active region in a semiconductor device using molecular beam epitaxy: A method of making an (Al, Ga, In)N semiconductor device having a substrate and an active region is provided. The method includes growing the active region using a combination of (i) plasma-assisted molecular beam epitaxy; and (ii) molecular beam epitaxy with a gas including nitrogen-containing molecules in which the nitrogen-containing... Agent: Mark D. Saralino ( Sharp ) Renner, Otto, Boisselle & Sklar, LLP

20090256169 - Deposition substrate and method for manufacturing light-emitting device: The deposition substrate of the present invention includes a light-transmitting substrate having a first region and a second region. In the first region, a first heat-insulating layer transmitting light is provided over the light-transmitting substrate, a light absorption layer is provided over the first heat-insulating layer, and a first organic... Agent: Cook Alex Ltd

20090256168 - Display element, manufacturing method of the same and display device: A display element including: a first electrode; an auxiliary wiring formed on the periphery of the first electrode in such a manner as to be insulated from the first electrode; an insulating portion having first and second openings, the first opening adapted to expose the first electrode, and the second... Agent: Sonnenschein Nath & Rosenthal LLP

20090256167 - Light-emitting device: A light-emitting device (1) is disclosed, which comprises a radiation source (2), an inorganic layer (3) comprising a luminescent material (4); and a scattering layer (5) comprising scattering particles (6). The scattering layer (5) is located between the radiation source (2) and the inorganic layer (3), which is composed of... Agent: Philips Intellectual Property And Standards

20090256166 - Semiconductor light-emitting device: A semiconductor light-emitting device 10 has a semiconductor chip 12 for emitting light having a wavelength in blue to ultraviolet regions, and a sealing portion 16 formed in at least a partial region on a passage path on which the light is passed. The sealing portion 16 includes a sealing... Agent: Mcdermott Will & Emery LLP

20090256170 - Semiconductor light emitting element and method for manufacturing same: A semiconductor light emitter (A) includes an n-type semiconductor layer (2), a p-type semiconductor layer (4), and an active layer (3) between these two layers (2, 4). The light emitter (A) further includes an n-side electrode (5) on the n-type layer (2) and a p-side electrode (6) on the p-type... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20090256171 - Resin composition for sealing light-emitting device and lamp: A resin composition for sealing a light-emitting device of the present invention includes a silsesquioxane resin including two or more oxetanyl groups, a cationic polymerization initiator and a metal oxide fine particle. Furthermore, a lamp of the present invention includes a package equipped with a sealing member, an electrode exposed... Agent: Sughrue Mion, PLLC

20090256172 - Method of laser annealing semiconductor layer and semiconductor devices produced thereby: A laser annealing method includes forming a nitrogen-doped layer on a semiconductor layer, the nitrogen-doped layer having a nitrogen concentration of at least 3×1020 atoms/cc, irradiating a first area of the nitrogen-doped layer in a low oxygen environment with a laser beam and irradiating a second area of the nitrogen-doped... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090256173 - Complementary field effect transistors having embedded silicon source and drain regions: A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of... Agent: International Business Machines Corporation Dept. 18g

20090256174 - Device structures for a high voltage junction field effect transistor manufactured using a hybrid orientation technology wafer and design structures for a high voltage integrated circuit: Device structures for a high voltage junction field effect transistor and design structures for a high voltage integrated circuit. The device structure is manufactured using a hybrid orientation technology wafer with a first semiconductor layer with a first crystalline orientation, a second semiconductor layer with a second crystalline orientation, and... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090256175 - Method of doping transistor comprising carbon nanotube, method of controlling position of doping ion, and transistors using the same: Provided are a method of doping a carbon nanotube (CNT) of a field effect transistor and a method of controlling the position of doping ions. The method may include providing a source, a drain, the CNT as a channel between the source and the drain, and a gate, applying a... Agent: Harness, Dickey & Pierce, P.L.C

20090256176 - Solid-state imaging apparatus: A solid-state imaging apparatus, controlling a potential on a semiconductor substrate for an electronic shutter operation, includes: a first semiconductor region of the first conductivity type for forming a photoelectric conversion region; a second semiconductor region of the first conductivity type, formed separately from the photoelectric conversion region, for accumulating... Agent: Fitzpatrick Cella Harper & Scinto

20090256177 - Semiconductor device including an ohmic layer: In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to... Agent: Harness, Dickey & Pierce, P.L.C

20090256178 - Semiconductor device having misfets and manufacturing method thereof: A semiconductor device includes a dielectric film and gate electrode that are stacked on a substrate, sidewalls formed to cover the side surfaces of the electrode and dielectric film, and SiGe films formed to sandwich the sidewalls, electrode and dielectric film, filled in portions separated from the sidewalls, having upper... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090256179 - Image sensor: Embodiments relate to and image sensor. In embodiments, the image sensor may include a semiconductor substrate, a photodiode region, a gate electrode, a dummy gate, and an interlayer dielectric layer. The semiconductor substrate includes a field oxide layer. The photodiode region may be formed on the semiconductor substrate. The gate... Agent: Sherr & Vaughn, PLLC

20090256181 - Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines: A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as... Agent: Knobbe Martens Olson & Bear LLP

20090256182 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device includes a memory cell portion and a peripheral circuit portion. The memory cell portion includes a pillar capacitor with a lower electrode, a dielectric film, and an upper electrode sequentially formed on a side surface of a first insulating portion which is parallel to a predetermined... Agent: Young & Thompson

20090256180 - Standard cell having compensation capacitance: A standard cell includes a capacity element which is made up of a first well diffusion layer into which a first conductive impurity is diffused in a region from a surface of a substrate to a predetermined depth, an insulation film which is provided on the first well diffusion layer,... Agent: Mcginn Intellectual Property Law Group, PLLC

20090256183 - Single gate nonvolatile memory cell with transistor and capacitor: A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090256184 - Single gate nonvolatile memory cell with transistor and capacitor: A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090256185 - Metallized conductive strap spacer for soi deep trench capacitor: A conductive strap spacer is formed within a buried strap cavity above an inner electrode recessed below a top surface of a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A portion of the conductive strap spacer is metallized by reacting with a metal to form a strap metal semiconductor... Agent: Scully, Scott, Murphy & Presser, P.C.

20090256187 - Semiconductor device having vertical pillar transistors and method for manufacturing the same: A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a single surface of lower portions of the silicon pillars, and drain areas of the vertical pillar transistors are connected with one another.... Agent: Ladas & Parry LLP

20090256186 - Split gate non-volatile memory cell: A non-volatile memory (NVM) cell comprising a layer of discrete charge storing elements, a control gate, and a select gate is provided. The control gate has a first sidewall with a lower portion being at least a first angle 10 degrees away from 90 degrees with respect to substrate. Further,... Agent: Freescale Semiconductor, Inc. Law Department

20090256188 - Method for manufacturing semiconductor device and the semiconductor device: A method for manufacturing a semiconductor device which includes: alternately supplying a silicon source and an oxidant to deposit a silicon oxide film on a surface of a semiconductor substrate, wherein the silicon source is supplied under a supply condition where an adsorption amount of molecules of the silicon source... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090256190 - Semiconductor device and manufacturing method thereof: According to an aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate; active areas with island-like shapes formed on the semiconductor substrate; an element isolation area surrounding the active areas and including an element isolation groove formed on the semiconductor substrate and an element... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090256189 - Two bit u-shaped memory structure and method of making the same: A memory structure includes: a substrate; a control gate positioned on the substrate; floating gates positioned at two sides of the control gate, wherein the floating gates have a U-shaped bottom embedded in the substrate; a first dielectric layer positioned between the control gate and the substrate; a second dielectric... Agent: North America Intellectual Property Corporation

20090256191 - Split gate non-volatile memory cell with improved endurance and method therefor: A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlying a first portion of the channel region.... Agent: Freescale Semiconductor, Inc. Law Department

20090256192 - Nonvolatile semiconductor memory device and method of manufacturing the same: In a nonvolatile semiconductor memory device where a tunnel insulating film, a charge storage layer, a blocking insulating film, and a control gate are stacked one on top of another on a semiconductor substrate, with an element isolation insulating film buried between adjacent cells, a barrier layer composed of at... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090256193 - Semiconductor device and a method of manufacturing the same: In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is... Agent: Miles & Stockbridge PC

20090256195 - Semiconductor device and method of manufacturing the same: A semiconductor device in which current flows in a vertical direction includes a structure that decreases resistance between a source electrode and a drain electrode along with a current path at a position different from a position having highest electric field intensity between the source electrode and the drain electrode.... Agent: Young & Thompson

20090256194 - Semiconductor device with reduced resistance of bit lines and method for manufacturing the same: A semiconductor device comprises buried bit lines which are formed to be brought into contact with drain areas of vertical pillar transistors. The buried bit lines are arranged along a first direction in a silicon substrate. The buried bit lines are formed of epi-silicon to reduce the resistance of the... Agent: Ladas & Parry LLP

20090256197 - Semiconductor device and manufacturing method thereof: Provided is a technology, in a semiconductor device having a power MISFET and a Schottky barrier diode on one semiconductor substrate, capable of suppressing a drastic increase in the on-resistance of the power MISFET while making the avalanche breakdown voltage of the Schottky barrier diode greater than that of the... Agent: Mattingly & Malur, P.C.

20090256198 - Semiconductor devices having line type active regions and methods of fabricating the same: In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line... Agent: Mills & Onello LLP

20090256196 - Three-dimensional semiconductor device structures and methods: A three-dimensional semiconductor device structure includes a first semiconductor device and a second semiconductor device bonded together using a patterned conductive layer according to an embodiment of the invention. The first semiconductor device includes a first plurality of terminals on its front side, and the second semiconductor device includes a... Agent: Townsend And Townsend And Crew, LLP

20090256199 - lateral metal oxide semiconductor drain extension design: A semiconductor device comprising source and drain regions and insulating region and a plate structure. The source and drain regions are on or in a semiconductor substrate. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a... Agent: Texas Instruments Incorporated

20090256200 - Disconnected dpw structures for improving on-state performance of mos devices: A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second HVW region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first HVW region; a gate dielectric extending... Agent: Slater & Matsil, L.L.P.

20090256201 - Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods: A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20090256202 - Semiconductor-on-insulator device structures with a body-to-substrate connection for enhanced electrostatic discharge protection, and design structures for such semiconductor-on-insulator device structures: Semiconductor-on-insulator device structures with enhanced electrostatic discharge protection, and design structures for an integrated circuit with device structures exhibiting enhanced electrostatic discharge protection. A device is formed in a body region of a device layer of a semiconductor-on-insulator substrate, which is bounded by an inner peripheral sidewall of an annular... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090256203 - Top gate thin film transistor with independent field control for off-current suppression: A bottom-contacted top gate (TG) thin film transistor (TFT) with independent field control for off-current suppression is provided, along with an associated fabrication method. The method provides a substrate, and forms source and drain regions overlying the substrate, each having a channel interface top surface. A channel is interposed between... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20090256205 - 2-t sram cell structure and method: The present invention, in one embodiment, provides a memory device including a substrate including at least one device region; a first field effect transistor having a first threshold voltage and a second field effect transistor having a second threshold voltage, the second field effect transistor including a second active region... Agent: Scully, Scott, Murphy & Presser, P.C.

20090256204 - Soi transistor with merged lateral bipolar transistor: A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned between the source region and the drain region. The source-side lateral... Agent: Carey, Rodriguez, Greenberg & Paul, LLP

20090256206 - P-channel germanium on insulator (goi) one transistor memory cell: According to one exemplary embodiment, a p-channel germanium on insulator (GOI) one transistor memory cell comprises a buried oxide (BOX) layer formed over a bulk substrate, and a gate formed over a gate dielectric layer situated over a germanium layer formed over the buried oxide (BOX) layer. A source region... Agent: Farjami & Farjami LLP

20090256207 - Finfet devices from bulk semiconductor and methods for manufacturing the same: Disclosed herein is a transistor comprising a first fin having a first gate electrode disposed across the first fin; the gate electrode contacting opposing surfaces of the fin; and a planar oxide layer having a second gate electrode disposed across the planar oxide layer to form a planar metal oxide... Agent: Cantor Colburn LLP - IBM Fishkill

20090256208 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device according to one embodiment includes: forming a fin and a film on a semiconductor substrate, the film being located at least either on the fin or under the fin and on the semiconductor substrate; forming a gate electrode so as to sandwich both... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090256209 - Gate structure of semiconductor device: A gate structure of a semiconductor device comprising a silicon substrate having a field oxide film, a plurality of gates formed by sequentially stacking a first gate dielectric film, a first gate conductive film, and a gate silicide film on the silicon substrate. a thermal oxide film formed on a... Agent: Marshall, Gerstein & Borun LLP

20090256210 - Semiconductor device and fabrication method of the semiconductor device: It includes: a source electrode (21) formed on a semiconductor layer (12); a drain electrode (23) formed on the semiconductor layer (12); a gate electrode (22) formed between the source electrode (21) and the drain electrode (23); an insulating film (24) formed on the semiconductor layer (12) and the gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090256211 - Metal gate compatible flash memory gate stack: A first gate stack comprising two stacked gate electrodes in a first device region, a second gate stack comprising a metal gate electrode in a second device region, and a third gate stack comprising a semiconductor gate electrode in a third device region are formed by forming and removing portions... Agent: Scully, Scott, Murphy & Presser, P.C.

20090256212 - Lateral drain-extended mosfet having channel along sidewall of drain extension dielectric: An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the... Agent: Texas Instruments Incorporated

20090256213 - Structure and method for manufacturing device with a v-shape channel nmosfet: A CMOS structure includes a v-shape surface in an nMOSFET region. The v-shape surface has an orientation in a (100) plane and extends into a Si layer in the nMOSFET region. The nMOSFET gate dielectric layer is a high-k material, such as Hf02. The nMOSFET has a metal gate layer,... Agent: International Business Machines Corporation Dept. 18g

20090256214 - Semiconductor device and associated methods: A semiconductor device and process of fabricating the same, the semiconductor device including a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a gate electrode having sidewalls, on the gate insulating layer, first spacers on the sidewalls of the gate electrode, a source/drain region in the semiconductor substrate,... Agent: Lee & Morse, P.C.

20090256215 - Gated metal oxide sensor: An apparatus for sensing an analyte gas is provided. The apparatus may include a signal amplifier that may include a thin film transistor that may include a semiconducting film that may include a metal oxide capable of chemical interaction with the analyte gas, such as carbon monoxide. The apparatus may... Agent: Fish & Richardson P.C.

20090256216 - Wafer level csp sensor: An electronics package has a wafer level chip scale package (WLCSP) die substrate containing electronic circuits. Through-silicon vias through the die substrate electrically connect the electronic circuits to the bottom surface of the die substrate. A package sensor is coupled to the die substrate for sensing an environmental parameter. A... Agent: Sunstein Kann Murphy & Timbers LLP

20090256217 - Carbon nanotube memory cells having flat bottom electrode contact surface: The present invention is directed to structures and methods of fabricating nanotube electromechanical memory cells having a bottom electrode with a substantially planar contact surface. The bottom electrode is configured so that during the operation of the memory cell the nanotube crossbar of the cell can make contact with a... Agent: Wilmerhale/boston

20090256218 - Mems device having a layer movable at asymmetric rates: A microelectromechanical (MEMS) device includes a substrate and a movable layer mechanically coupled to the substrate. The movable layer moves from a first position to a second position at a first rate and from the second position to the first position at a second rate faster than the first rate.... Agent: Knobbe, Martens, Olson & Bear, LLP

20090256219 - Method for manufacturing a semiconductor component, as well as a semiconductor component, in a particular a diaphragm sensor: A method for producing a micromechanical diaphragm sensor includes providing a semiconductor substrate having a first region, a diaphragm, and a cavity that is located at least partially below the diaphragm. Above at least one part of the first region, a second region is generated in or on the surface... Agent: Kenyon & Kenyon LLP

20090256220 - Low switching current mtj element for ultra-high stt-ram and a method for making the same: A STT-RAM MTJ that minimizes spin-transfer magnetization switching current (Jc) while achieving a high dR/R is disclosed. The MTJ has a MgO tunnel barrier formed by natural oxidation to achieve a low RA, and a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel layer to minimize Jc0. There is... Agent: Saile Ackerman LLC

20090256221 - Method for making very small isolated dots on substrates: A method for forming very small isolated dots of a target material, e.g., a ferromagnetic material or phase change material, on a substrate includes providing a substrate having a layer of the target material disposed on a surface thereof, etching the layer of target material so as to form a... Agent: Haynes And Boone, LLPIPSection

20090256224 - Integrated circuit comprising mirrors buried at different depths: A semiconductor structure including a first active area under which is buried a first reflective layer and a least one second active area under which is buried a second reflective layer, wherein the upper surface of the second reflective layer is closer to the upper surface of the structure than... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20090256227 - Method of fabricating back-illuminated imaging sensors using a bump bonding technique: A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate, and resulting imaging device is disclosed. The method for manufacturing the imaging device includes the steps of providing a substrate comprising an insulator layer, and an epitaxial layer substantially overlying the insulator layer; fabricating at least one... Agent: Patent Docket Administrator Lowenstein Sandler P.C.

20090256228 - Micro-lenses for cmos imagers and method for manufacturing micro-lenses: A micro-lens and a method for forming the micro-lens is provided. A micro-lens includes a substrate and lens material located within the substrate, the substrate having a recessed area serving as a mold for the lens material. The recessed can be shaped such that the lens material corrects for optical... Agent: Dickstein Shapiro LLP

20090256222 - Packaging method of image sensing device: A packaging method for an image sensing device is disclosed. The packaging method includes the steps of a) providing an annular dam on a substrate; b) mounting an image sensing module, having a light-receiving region exposed, inside the annular dam on the substrate; c) connecting the image sensing module and... Agent: Bacon & Thomas, PLLC

20090256223 - Photodiode array: A photodiode array 1 has a plurality of photodetector channels 10 which are formed on an n-type substrate 2 having an n-type semiconductor layer 12, with a light to be detected being incident to the plurality of photodetector channels 10. The photodiode array 1 comprises: a p−-type semiconductor layer 13... Agent: Drinker Biddle & Reath (dc)

20090256225 - Solid-state image capturing device, manufacturing method of the solid-state image capturing device, and electronic information device: A solid-state image capturing device according to the present invention includes: a photoelectrical conversion section formed in a semiconductor substrate or in a substrate area provided on a substrate; a first transparent film provided on the photoelectrical conversion section; and a lens provided at a position above the first transparent... Agent: Edwards Angell Palmer & Dodge LLP

20090256226 - Solid-state imaging device, production method thereof, and electronic device: Disclosed is a solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel... Agent: Sonnenschein Nath & Rosenthal LLP

20090256229 - Semiconductor package, method for manufacturing the same, semiconductor module, and electronic device: In a camera module (1) of the present invention, a lens member (20) is attached to a semiconductor package (10). The semiconductor package (10) includes: an image sensor (11) mounted on a wiring board (13); and a wire 15 through which the wiring board (13) is electrically connected to the... Agent: Edwards Angell Palmer & Dodge LLP

20090256230 - Photoelectric conversion apparatus and imaging system using the photoelectric conversion apparatus: In a photoelectric conversion apparatus including a charge holding portion, a part of an element isolation region contacting with a semiconductor region constituting the charge holding portion extends from a reference surface including the light receiving surface of a photoelectric conversion element into a semiconductor substrate at a level equal... Agent: Fitzpatrick Cella Harper & Scinto

20090256231 - Unipolar semiconductor photodetector with suppressed dark current and method for producing the same: A photo-detector with a reduced G-R noise comprises two n-type narrow bandgap layers surrounding a middle barrier layer having an energy bandgap at least equal to the sum of the bandgaps of the two narrow bandgap layers. Under the flat band conditions the conduction band edge of each narrow bandgap... Agent: Venable LLP

20090256232 - Semiconductor device and fabrication method for the same: The semiconductor device includes: memory cells each having a first multilayer electrode including a first lower electrode made of a first conductive film and a first upper electrode made of a second conductive film formed one on the other with a first interface film therebetween; and a diode having a... Agent: Mcdermott Will & Emery LLP

20090256233 - Isolation structure in memory device and method for fabricating the isolation structure: An isolation structure in a memory device and a method for fabricating the isolation structure. In the method, a first trench is formed in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. A liner layer comprising a silicon nitride... Agent: Marshall, Gerstein & Borun LLP

20090256234 - Semiconductor device and method for producing the same: A semiconductor device is configured that a high-withstand voltage semiconductor device and logic circuits are integrated on a single chip and that a high-withstand voltage high-potential island including the high-potential-side logic circuit is separated using multiple partition walls enclosing therearound. The semiconductor device is provided with a multi-trench separation region... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090256235 - Semiconductor device: A semiconductor device (200) includes: an electrical fuse (100) including: a lower layer interconnect (120) formed on a substrate; a via (130) provided on the lower layer interconnect (120) so as to be connected to the lower layer interconnect (120); and an upper layer interconnect (110) provided on the via... Agent: Mcginn Intellectual Property Law Group, PLLC

20090256236 - Mems-topped integrated circuit with a stress relief layer and method of forming the circuit: The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer and... Agent: Law Office Of Mark C. Pickering

20090256238 - Capacitor of semiconductor device and method of fabricating the same: Disclosed are a capacitor of a semiconductor device and a method of fabricating the same. The capacitor includes a capacitor top electrode, a capacitor bottom electrode aligned with a bottom surface and three lateral sides of the capacitor top electrode, and a capacitor insulating layer between the capacitor top electrode... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090256237 - Semiconductor device, manufacturing method thereof, and data processing system: A miniaturized semiconductor device is provided by reducing the design thickness of a wiring line protecting film covering the surface of a wiring layer, and reducing the distance between the wiring layer and via plugs formed by a self-aligning process. Dummy mask layers extending in the same layout pattern as... Agent: Young & Thompson

20090256239 - Capacitor, chip comprising the capacitor, and method for producing the capacitor: A capacitor is described which includes a substrate with a doped area of the substrate forming a first electrode of a first capacitor. A plurality of trenches is arranged in the doped area of the substrate, the plurality of trenches forming a second electrode of the capacitor. An electrically insulating... Agent: Slater & Matsil LLP

20090256240 - Method for producing group iii-nitride wafers and group iii-nitride wafers: The present invention discloses a production method for group III nitride ingots or pieces such as wafers. To solve the coloration problem in the wafers grown by the ammonothermal method, the present invention composed of the following steps; growth of group III nitride ingots by the ammonothermal method, slicing of... Agent: Morrison & Foerster LLP

20090256241 - Thin silicon wafer and method of manufacturing the same: A method of manufacturing a thin silicon wafer by slicing a silicon single crystal includes: a thinning step S3 of polishing a rear surface of the silicon wafer to reduce the thickness of the silicon wafer after a device structure is formed on a front surface of the silicon wafer;... Agent: Greenblum & Bernstein, P.L.C

20090256242 - Method of forming an electronic device including forming a charge storage element in a trench of a workpiece: A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the... Agent: Larson Newman & Abel, LLP

20090256243 - Low k interconnect dielectric using surface transformation: Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement of at least one void formed within the solid structure... Agent: Schwegman, Lundberg & Woessner/micron

20090256244 - Semiconductor device packages with electromagnetic interference shielding: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the... Agent: Cooley Godward Kronish LLP Attn: Patent Group

20090256246 - Semiconductor packaging techniques: A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20090256245 - Stacked micro-module packages, systems using the same, and methods of making the same: Semiconductor die packages, methods of making said packages, and systems using said packages are disclosed. An exemplary package comprising at least one semiconductor die disposed on one surface of a leadframe and electrically coupled to at least one conductive region of the leadframe, and at least one passive electrical component... Agent: Townsend And Townsend And Crew, LLP

20090256247 - Semiconductor device and method including first and second carriers: A semiconductor device and method. One embodiment provides an integral array of first carriers and an integral array of second carries connected to the integral array of first carriers. First semiconductor chips are arranged on the integral array of first carriers. The integral array of second carriers is arranged over... Agent: Dicke, Billig & Czaja

20090256248 - Configuration terminal for integrated devices and method for configuring an integrated device: A configuration terminal for integrated devices includes a first and a second portion structurally independent and connected to respective first and second terminals and it has at least one contact terminal suitable to be selectively connected to such first and second terminals. Also a method configures an integrated device that... Agent: Seed Intellectual Property Law Group PLLC

20090256249 - Stacked, interconnected semiconductor package: An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.... Agent: Vierra Magen/sandisk Corporation

20090256250 - Semiconductor device and programming method: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090256251 - Electronic device packages and methods of formation: Provided are electronic device packages and their methods of formation. The electronic device packages include an electronic device mounted on a substrate, a conductive via and a locally thinned region in the substrate. The invention finds application, for example, in the electronics industry for hermetic packages containing an electronic device... Agent: Jonathan D. Baskin Rohm And Haas Electronic Materials LLC

20090256252 - Semiconductor die packages with multiple integrated substrates, systems using the same, and methods using the same: An exemplary semiconductor die package is disclosed having one or more semiconductor dice disposed on a first substrate, one or more packaged electrical components disposed on a second substrate that is electrical coupled to the first substrate, and an electrically insulating material disposed over portions of the substrates. The first... Agent: Townsend And Townsend And Crew, LLP

20090256253 - Continuously referencing signals over multiple layers in laminate packages: A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the voltage reference. A reference plane adjustment engine analyzes a... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090256254 - Wafer level interconnection and method: A semiconductor assembly includes a semiconductor wafer including backside contact pads coupled to respective contact regions of different signal types and insulation separating the backside contact regions by signal type. The semiconductor assembly further includes metallization situated over at least a portion of the insulation and interconnecting the backside contact... Agent: General Electric Company Global Research

20090256255 - Composite interconnect: A composite interconnect system includes a plurality of carbon nanotubes, a plurality of solder balls and standoff balls disposed on a first device to provide a connection to a second device. A die-attached substrate includes a substrate and one or more die disposed on the substrate by a die-attach composite... Agent: Osha Liang L.L.P./sun

20090256256 - Electronic device and method of manufacturing same: This application relates to a semiconductor device comprising an array of contact elements soldered to only one surface, wherein the array defines a predetermined pitch length, wherein the contact elements comprise a spherically shaped element and wherein the contact elements protrude from the only one surface by more than 60... Agent: Infineon Technologies Ag Patent Department

20090256257 - Final via structures for bond pad-solder ball interconnections: A structure and a method for forming the same. The structure includes a first dielectric layer, an electrically conductive bond pad on the first dielectric layer, and a second dielectric layer on top of the first dielectric layer and the electrically conductive bond pad. The electrically conductive bond pad is... Agent: Schmeiser, Olsen & Watts

20090256258 - Semiconductor chip with integrated via: An integrated circuit with a substrate with a lower and an upper surface is described. A via extends between the upper and the lower surface of the substrate. The via contains a conductive filling material that comprises carbon.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090256259 - Semiconductor device and method for manufacturing the same: A semiconductor device has a first interlayer insulating film formed on a semiconductor substrate, a first plug and a second plug embedded in holes formed to open the first interlayer insulating film, a capacitor formed on the first interlayer insulating film so as to connect to the first plug, a... Agent: Knobbe Martens Olson & Bear LLP

20090256260 - Semiconductor device: A semiconductor device including a semiconductor element and a functional member fixed thereto with an adhesive film is provided, where the performance or reliability degradation due to moisture entered by way of the adhesive film itself or the interfaces between the adhesive film and members adjacent thereto can be suppressed... Agent: Griffin & Szipl, PC

20090256261 - Semiconductor device and manufacturing method thereof: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties... Agent: Miles & Stockbridge PC

20090256262 - Semiconductor devices including porous insulators: Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed therethrough. The voids may be defined by shells of microcapsules. The voids impart the dielectric materials with reduced dielectric constants and, thus, increased electrical insulation properties.... Agent: Trask Britt, P.C./ Micron Technology

20090256263 - Structure and method for hybrid tungsten copper metal contact: The present invention in one embodiment provides a method of forming an interconnect comprising, providing a interlevel dielectric layer atop a substrate, the interlevel dielectric layer including at least one tungsten (W) stud extending from an upper surface of the interlevel dielectric to the substrate; recessing an upper surface of... Agent: Scully, Scott, Murphy & Presser, P.C.

20090256264 - Semiconductor structure and method of making the same: A semiconductor device is provided. An amorphous silicon layer that acts as a UV blocking layer replaces a conventional silicon-rich oxide (SRO) layer or the super silicon-rich oxide (SSRO) layer. By doing this, the process window is increased. In addition, silicon nitride sidewall spacer is formed inside the contact hole... Agent: North America Intellectual Property Corporation

20090256265 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes a plurality of contact layers located between two lines running in parallel in a first direction. Each of the contact layers has a structure in which an upper contact and a lower contact are coupled together. The plurality of contact layers are arranged zigzag... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090256266 - Apparatus and method for a chip assembly including a frequency extending device: A chip assembly includes a chip, a paddle, an interface layer, a frequency extending device, and lands. The chip has contacts. The interface layer is disposed between the chip and the paddle. The frequency extending device has at least a conductive layer and a dielectric layer. The conductive layer has... Agent: Mcdermott Will & Emery LLP

20090256267 - Integrated circuit package-on-package system with central bond wires: An integrated circuit package-on-package system includes: providing a base substrate having a central opening; attaching a bottom die below the base substrate partially covering the central opening, the bottom die connected through the central opening to a top surface of the base substrate; attaching a top die above the base... Agent: Law Offices Of Mikio Ishimaru

20090256268 - Partially underfilled solder grid arrays: An electronic device and a method of forming the device. The device including a module having opposite top surface and bottom surfaces; a first set of pads on the top surface of the module and a second set of pads on the bottom surface of the module substrate, wires within... Agent: Schmeiser, Olsen & Watts

20090250676 - Liquid crystalline organic semiconductor material, and semiconductor element or information recording medium using the same: P

20090250678 - Nonvolatile memory apparatus, nonvolatile memory element, and nonvolatile element array: A nonvolatile memory apparatus comprises a first electrode (111), a second electrode (112), a variable resistance layer (113) which is disposed between the electrodes, a resistance value of the variable resistance layer reversibly varying between a plurality of resistance states based on an electric signal applied between the electrodes, a... Agent: Mcdermott Will & Emery LLP

20090250679 - Phase-change memory device and method of fabricating the same: A phase-change memory device includes a lower electrode; and at least two phase-change memory cells sharing the lower electrode. Another phase-change memory device includes a heating layer having a smaller contact area with a phase-change material layer and a greater contact area with a PN diode structure.... Agent: Lowe Hauptman Ham & Berner, LLP

20090250677 - Reducing drift in chalcogenide devices: Chalcogenide materials conventionally used in chalcogenide memory devices and ovonic threshold switches may exhibit a tendency called drift, wherein threshold voltage or resistance changes with time. By providing a compensating material which exhibits an opposing tendency, the drift may be compensated. The compensating material may be mixed into a chalcogenide,... Agent: Trop, Pruner & Hu, P.C.

20090250680 - Semiconductor integrated circuit device: With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising... Agent: Mattingly & Malur, P.C.

20090250681 - Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Insulative material is deposited over the first electrode. An opening is formed into the insulative material over the first electrode. The opening includes sidewalls and... Agent: Wells St. John P.s.

20090250682 - Phase change memory device: Provided is a phase change memory device. The phase change memory device includes a first electrode and a second electrode. A phase change material pattern is interposed between the first and second electrodes. A phase change auxiliary pattern is in contact with at least one side of the phase change... Agent: Myers Bigel Sibley & Sajovec

20090250685 - Light emitting device: Disclosed are a light emitting device. The light emitting device includes a first conductive semiconductor layer, a light emitting layer, a protective layer, a nano-layer and a second conductive semiconductor layer. The light emitting layer is formed on the first conductive semiconductor layer. The protective layer is formed on the... Agent: Birch Stewart Kolasch & Birch

20090250684 - Light emitting semiconductor: A semiconductor element is disclosed having a layered body of a first conductivity type, a light emitting layer, a layered body of a second conductivity type, a constriction layer having a constriction hole, and a first electrode having a lighting hole, a second electrode positioned such that charge traveling between... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20090250686 - Method for fabrication of semipolar (al, in, ga, b)n based light emitting diodes: A yellow Light Emitting Diode (LED) with a peak emission wavelength in the range 560-580 nm is disclosed. The LED is grown on one or more III-nitride-based semipolar planes and an active layer of the LED is composed of indium (In) containing single or multi-quantum well structures. The LED quantum... Agent: Gates & Cooper LLP Howard Hughes Center

20090250683 - Nitride-based semiconductor light emitting element: The purpose of the present invention is to obtain a nitride-based semiconductor light emitting element capable of improving light emission efficiency by reducing sheet resistance and a forward voltage of a translucent electrode including indium cerium oxide. The nitride-based semiconductor light emitting element of the present invention is has a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090250687 - Semiconductor device and method to control the state of a semiconductor device and to manufacture the same: A semiconductor device includes a conduct structure to which are arranged contacts for a source and a drain, a resonance region including at least two barrier regions, at least one resonator between the barrier regions and a control electrode and which resonance region is arranged between the contacts. The conduct... Agent: Fildes & Outland, P.C.

20090250688 - Molecular quantum interference apparatus and applications of same: A molecular quantum interference device for use in molecular electronics. In one embodiment, the device includes a molecular quantum interference unit having a first terminal group and a second terminal group between which quantum interference affects electrical conduction, a molecular spacer having a first terminal group and a second terminal... Agent: Morris Manning Martin LLP

20090250689 - Nanowire: A method comprises applying a first electric field pulse to a nanowire comprising a channel and a charge trapping region configured to control conductivity of the channel, the first electric field pulse having a first polarity and a relatively large magnitude of integral of electric field during the pulse and,... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20090250690 - Organic thin film transistor substrate and method of manufacturing the same: In an organic thin film transistor (TFT) substrate, the organic TFT substrate includes gate lines, data lines, a gate electrode, a source electrode, a drain electrode, a gate insulating layer, an organic semiconductor layer, and an organic protective layer. The gate and data lines are insulated from each other and... Agent: H.c. Park & Associates, PLC

20090250691 - Phase change memory element and method for forming the same: A phase change memory and method for fabricating the same are provided. The phase change memory element includes: a substrate; rectangle-shaped dielectric patterns formed on the substrate and parallel with each other; electric conductive patterns partially covering a first sidewall and the top surface of the dielectric pattern and the... Agent: Quintero Law Office, PC

20090250692 - Radiation detector with asymmetric contacts: A room temperature radiation detector is made from a semi-insulating Cd1-xZnxTe crystal, where 0≦x≦1, having a first electrode made of Pt or Au on one surface of the crystal and a second electrode of Al, Ti or In on another surface of the crystal. In use of the crystal to... Agent: The Webb Law Firm, P.C.

20090250694 - Semiconductor device, manufacturing method of semiconductor device, and display device: A semiconductor device includes a substrate and a channel region which is formed above the substrate by printing, wherein a relationship L≧2a is satisfied where L is a channel length of the channel region and a is a minimum dimension among pattern dimensions and inter-pattern dimensions in the same layer... Agent: Sughrue-265550

20090250695 - Semiconductor device, manufacturing method of semiconductor device, display device, and manufacturing method of display device: A semiconductor device includes a substrate and a semiconductor layer having a channel region, the channel region is made from an oxide semiconductor which satisfies Vc/Va>4 where Vc is a volume ratio of a crystalline component and Va is a volume ratio of a non-crystalline component.... Agent: Sughrue-265550

20090250693 - Thin film transistor, display device, including the same, and associated methods: A thin film transistor (TFT), including a substrate, a gate electrode on the substrate, an oxide semiconductor layer including a channel region, a source region, and a drain region, a gate insulating layer between the gate electrode and the oxide semiconductor layer, and source and drain electrodes in contact with... Agent: Lee & Morse, P.C.

20090250696 - Near natural breakdown device: A semiconductor device includes a semiconductor region wherein the semiconductor region is a forced or non-forced Near Natural breakdown region, which is completely depleted when a predetermined voltage having a magnitude less than or equal to the breakdown voltage of a non-Natural breakdown (for example, Zener breakdown and Avalanche breakdown)... Agent: Haynes And Boone, LLPIPSection

20090250698 - Fabrication management system: With the evolution of technology, there is a continual demand for enhanced speed, capacity and efficiency. A modular, chip testing system associated with a single chip on a wafer is described. This system includes a performance structure for measuring chip performance during a testing period; a power structure for measuring... Agent: Texas Instruments Incorporated

20090250697 - Semiconductor device and manufacturing method therefor: Methods for detecting a void in an element portion of a semiconductor device having an element portion and a void detection structure are disclosed. As a part of the method, an insulating film is formed on a substrate, a plurality of holes is formed in the insulating film, and a... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090250699 - Electromagnetic wave detecting element: The present invention provides an electromagnetic wave detecting element that can suppress occurrence of cracking at a substrate peripheral portion, and occurrence of breakage of lead-out wires. An interlayer insulating film is formed so as to cover TFT switches on a substrate. An interlayer insulating film is formed so as... Agent: Moss & Burke, PLLC

20090250700 - Crystalline semiconductor stripe transistor: A transistor with crystalline semiconductor stripes and an associated fabrication process are provided. The method provides a substrate, and deposits a semiconductor layer overlying the substrate. The semiconductor layer is irradiated using a scanning step-and-repeat laser annealing process, which agglomerates portions of the semiconductor layer. In response to cooling agglomerated... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20090250701 - Circuit board, electronic device, and method for producing circuit board: The present invention provides a circuit board which can improve characteristics of a circuit element, an electronic device, and a method for producing a circuit board. The method for producing a circuit board of the present invention is a method for producing a circuit board including one or more polysilicon... Agent: Nixon & Vanderhye, PC

20090250704 - Semiconductor device and method of fabricating the same: An active matrix display device having a pixel structure in which pixel electrodes, gate wirings and source wirings are suitably arranged in the pixel portions to realize a high numerical aperture without increasing the number of masks or the number of steps. The device comprises a gate electrode and a... Agent: Fish & Richardson P.C.

20090250703 - Semiconductor device and method of manufacturing the same: It is provided a contacting method when a plurality of films to be peeled are laminating. Reduction of total layout area, miniaturization of a module, weight reduction, thinning, narrowing a frame of a display device, or the like can be realized by sequentially laminating a plurality of films to be... Agent: Eric Robinson

20090250702 - Static-tolerant display apparatus: A display apparatus includes a thin film transistor having a top-gate structure and a storage capacitor that are arranged on a first substrate. An upper electrode of the storage capacitor has a size larger than a size of a lower electrode, so as to cover an entire surface of the... Agent: Haynes And Boone, LLPIPSection

20090250705 - Silicon carbide semiconductor device comprising silicon carbide layer and method of manufacturing the same: A p base ohmic contact of a silicon carbide semiconductor device consists of a p++ layer formed by high-concentration ion implantation and a metal electrode. Since the high-concentration ion implantation performed at the room temperature significantly degrades the crystal of the p++ layer to cause a process failure, a method... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090250706 - Light activated silicon controlled switch: The present invention provides an optically triggered switch and a method of forming the optically triggered switch. The optically triggered switch includes a silicon layer having at least one trench formed therein and at least one silicon diode formed in the silicon layer. The switch also includes a first thyristor... Agent: Williams, Morgan & Amerson

20090250707 - Multi-chip assembly with optically coupled die: Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die... Agent: Intel Corporation C/o Cpa Global

20090250708 - Thin-film photodiode and display device: A thin-film photodiode has a substrate, a thin-film element formed on the substrate and a micro lens formed above the thin-film element. The thin-film element includes a first semiconductor layer of p-type semiconductor formed on the substrate, a second semiconductor layer formed in contact with the first semiconductor layer on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090250709 - Led package and light source device using same: An exemplary LED package includes a dielectric plate, a heat conductor, a first planar electrode and a second planar electrode, a LED chip, and metal wires. The dielectric plate comprises a receiving groove defined therein. The heat conductor is positioned in the dielectric plate opposite to the receiving groove, and... Agent: PCe Industry, Inc. Att. Steven Reiss

20090250710 - Semiconductor light emitting devices including multiple semiconductor light emitting elements in a substrate cavity: Semiconductor light emitting devices include a substrate having a cavity, multiple light emitting devices in the cavity and remote phosphor layers, scattering layers and/or lenses for the light emitting devices.... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090250712 - Light emitting device: A light emitting device is provided, which includes a light-emitting structure and a magnetic material. The light-emitting structure has an exciting binding energy of a bandgap. The magnetic material is coupled with the light-emitting structure to produce a magnetic field in the light-emitting structure. The exciting binding energy may be... Agent: Jianq Chyun Intellectual Property Office

20090250711 - Substrate for forming light-emitting layer, light emitter and light-emitting substance: 4 for forming light-emitting layer comprises a substrate single-crystal substrate 1, and an oriented fine crystal layer 3 being formed on the single-crystal substrate 4. One of the crystal axes of respective crystals, which constitute the oriented microcrystal layer 3, is oriented in a specific direction with respect to the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090250715 - Led transparent brick: An LED transparent brick comprises a transparent brick body, a photo catalyst layer, a connecting layer, a light reflection layer and one or more ultraviolet LEDs. The photo catalyst layer is placed at a first surface of the transparent brick body, and the connecting layer combines the transparent brick body... Agent: Wpat, PC Intellectual Property Attorneys

20090250717 - Light emitting device: A light emitting device includes a light emitting element having at least two electrodes disposed at the side of the light output surface thereof, and a base member having a recess and lead portions corresponding to the electrodes, the light emitting element being mounted on the base member and received... Agent: Jianq Chyun Intellectual Property Office

20090250716 - Light emitting devices having roughened/reflective contacts and methods of fabricating same: Light emitting devices include an active region of semiconductor material and a first contact on the active region. The first contact is configured such that photons emitted by the active region pass through the first contact. A photon absorbing wire bond pad is provided on the first contact. The wire... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090250713 - Reflective contact for a semiconductor light emitting device: A light emitting device includes a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region. A contact is formed on the semiconductor structure, the contact comprising a reflective metal in direct contact with the semiconductor structure and an additional metal or semi-metal disposed... Agent: Patent Law Group LLP

20090250714 - White light emitting diode and lighting apparatus using the same: Provided is a white LED including a substrate having a reflecting body provided thereon; an LED chip mounted on the substrate; a fluorescence reflecting layer formed on the LED chip; and a phosphor layer formed on the fluorescence reflecting layer and having a higher refractive index than the fluorescence reflecting... Agent: Mcdermott Will & Emery LLP

20090250718 - Light emitting diode and method for producing the same: A method for producing an LED includes steps of: providing a base (22), a chip body (21) and a die (40), wherein the base has a concave depression (23) defined therein and the die has a bottom wall (43) with an even surface having a surface roughness not smaller than... Agent: PCe Industry, Inc. Att. Steven Reiss

20090250719 - Nitride compound semiconductor device and semiconductor laser: A nitride semiconductor device includes a semiconductor substrate composed of gallium nitride, and a stack which is provided on the semiconductor substrate and includes at least one nitride semiconductor layer containing aluminum, wherein substrate thickness T of the semiconductor substrate and a sum S of products of proportions of aluminum... Agent: Rabin & Berdo, PC

20090250720 - Transient voltage suppressor and methods: Transient voltage suppressor and method for manufacturing the transient voltage suppressor having a dopant or carrier concentration in a portion of a gate region near a Zener region that is different from a dopant concentration in a portion of a gate region that is away from the Zener region.... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20090250721 - Electrical surge protective apparatus: Disclosed is an electrical surge protective apparatus comprising: a base region containing impurities of a first conductivity type; a first semiconductor region containing impurities of a second conductivity type; a second semiconductor region containing impurities of the same conductivity type as that of the second conductivity type; and a high... Agent: Young & Thompson

20090250722 - Method for forming a compound semi-conductor thin-film: A method is provided for fabricating a thin film semiconductor device. The method includes providing a plurality of raw semiconductor materials. The raw semiconductor materials undergo a pre-reacting process to form a homogeneous compound semiconductor target material. The compound semiconductor target material is deposited onto a substrate to form a... Agent: Mayer & Williams PC

20090250723 - Electronic device and heterojunction fet: In an electronic device of the present invention a gate Schottky electrode is formed on an active layer constructed of a GaN layer and an AlGaN layer, and a source ohmic electrode and a drain ohmic electrode are further formed on both sides of the gate Schottky electrode on the... Agent: Birch Stewart Kolasch & Birch

20090250724 - Bipolar transistor and method of making such a transistor: A bipolar transistor is formed on a heavily doped silicon substrate (1). An epitaxially grown collector (12) is formed on the substrate (1) and comprises silicon containing germanium at least at the top of the collector (12). An epitaxial base (13) is formed on the collector (12) to have the... Agent: Thompson Hine L.L.P. Intellectual Property Group

20090250725 - Ohmic metal contact protection using an encapsulation layer: A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality... Agent: Ladas & Parry

20090250726 - Low vt antifuse device: A one time programmable memory cell having an anti-fuse device with a low threshold voltage independent of core circuit process manufacturing technology is presented. A two transistor memory cell having a pass transistor and an anti-fuse device, or a single transistor memory cell having a dual thickness gate oxide, are... Agent: Borden Ladner Gervais LLP Anne Kinsman

20090250727 - Super junction semiconductor device: In the specification and drawing a super junction semiconductor device is disclosed. The super junction semiconductor device comprises a P-type layer, a N+ substrate, a N-type layer, a silicon dioxide layer and a P+ layer. The N+ substrate is disposed under the P-type layer. The N-type layer is disposed on... Agent: Chih Feng Yeh Brian M. Mcinnis

20090250728 - Solid state imaging device and method of manufacturing the same: A solid state imaging device has a plurality of photodetector parts 11 arranged in matrix, a plurality of vertical charge transfer electrodes 13 that read out signal charge from the photodetector parts and transfer the signal charge in the vertical direction, and a first light-shielding film 5 that shields the... Agent: Hamre, Schumann, Mueller & Larson P.C.

20090250729 - Capacitive micromachined ultrasonic transducer and manufacturing method: The integrated circuit/transducer device of the preferred embodiment includes a substrate, a complementary-metal-oxide-semiconductor (CMOS) circuit that is fabricated on the substrate, and a capacitive micromachined ultrasonic transducer (cMUT) element that is also fabricated on the substrate. The CMOS circuit and cMUT element are fabricated during the same foundry process and... Agent: Schox PLC

20090250730 - Microwave semiconductor device using compound semiconductor and method for manufacturing the same: An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090250731 - Field-effect transistor structure and fabrication method thereof: A field-effect transistor (FET) structure is provided. The FET structure includes a gate substrate, a dielectric layer, conductive electrodes, and a carbon nanotube (CNT). The gate substrate is made of a conductive material. The dielectric layer is disposed on the substrate. The conductive electrodes are disposed on the dielectric layer,... Agent: J.c. Patents

20090250732 - Semiconductor device and method of fabricating the same: In a method of fabricating a semiconductor device on a substrate having thereon a conductive layer, the conductive layer is patterned to form a plurality of opened regions. A gate insulation layer is formed on a sidewall of each of the opened regions. A pillar pattern is formed in each... Agent: Lowe Hauptman Ham & Berner, LLP

20090250733 - Pixel sensor with reduced image lag: A tensile-stress-generating structure is formed above a gate electrode in a CMOS image sensor to apply a normal tensile stress between a charge collection well of a photodiode, which is also a source region of a transfer transistor, and a floating drain in the direction connecting the source region and... Agent: Scully, Scott, Murphy & Presser, P.C.

20090250734 - Pixel with asymmetric transfer gate channel doping: A pixel including a substrate of a first conductivity type and having a surface, a photodetector of a second conductivity type that is opposite the first conductivity type, a floating diffusion region of the second conductivity type, a transfer region between the photodetector and the floating diffusion, a gate positioned... Agent: Ratnerprestia

20090250735 - Semiconductor memory: A semiconductor memory according to an embodiment of the present invention including first and second adjacent bit lines extending in a first direction and provided in the same interconnect layer, an active provided in a memory cell array, a first and second adjacent word lines extending in a second direction... Agent: Knobbe Martens Olson & Bear LLP

20090250737 - Secure memory device of the one-time programmable type: The integrated circuit includes a memory device of the irreversibly electrically programmable type. This device includes several memory cells, each memory cell having a dielectric zone positioned between a first electrode and a second electrode. Each memory cell is further associated with an access transistor. At least one first electrically... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20090250736 - Semiconductor device: In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from... Agent: Lee & Morse, P.C.

20090250738 - Simultaneous buried strap and buried contact via formation for soi deep trench capacitor: A node dielectric, an inner electrode, and a buried strap cavity are formed in the deep trench in an SOI substrate. A buried layer contact cavity is formed by lithographic methods. The buried strap cavity and the buried layer contact cavity are filled simultaneously by deposition of a conductive material,... Agent: Scully, Scott, Murphy & Presser, P.C.

20090250739 - Device structures with a hyper-abrupt p-n junction, methods of forming a hyper-abrupt p-n junction, and design structures for an integrated circuit: Device structures with hyper-abrupt p-n junctions, methods of forming hyper-abrupt p-n junctions, and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090250740 - Semiconductor device and method of manufacturing the same: A semiconductor device has a semiconductor substrate in which a plurality of device regions and a plurality of device isolation regions are alternately formed to extend in a first direction; and a plurality of contact plugs formed on the semiconductor substrate, connected to the device regions and arranged on the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090250741 - Semiconductor device and gate structure having a composite dielectric layer and methods of manufacturing the same: A semiconductor device and/or gate structure having a composite dielectric layer and methods of manufacturing the same is provided. In the semiconductor device, gate structure, and methods provided, a first conductive layer may be formed on a substrate. A native oxide layer formed on the first conductive layer may be... Agent: Harness, Dickey & Pierce, P.L.C

20090250742 - Neuron device: A neuron device includes: a semiconductor layer; source and drain regions formed in the semiconductor layer at a distance from each other; a protection film formed on an upper face of the semiconductor layer; a channel region formed in the semiconductor layer between the source region and the drain region;... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090250743 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device has side surfaces of neighboring bit lines that do not face each other to reduce a capacitance of a parasitic capacitor formed between adjacent bit lines. The semiconductor memory device includes contact plugs formed on a semiconductor substrate. Each contact plug is disposed between gate patterns.... Agent: Townsend And Townsend And Crew, LLP

20090250745 - Memory devices and methods of forming and operating the same: A memory device, including a first ground selection transistor, a first string selection transistor, and first memory cell transistors disposed in series between the first ground selection transistor and the first string selection transistor, wherein the first ground selection transistor and the first memory cell transistors have a same structure.... Agent: Lee & Morse, P.C.

20090250746 - Nor-type flash memory cell array and method for manufacturing the same: Disclosed is a non-volatile (e.g., NOR type flash) memory cell array and a method for manufacturing the same. The memory cell array includes a plurality of isolation layers on a semiconductor substrate, parallel to a bit line and defining an active device area, a plurality of common source areas in... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090250744 - Semiconductor memory device and manufacturing method therefor: A semiconductor memory device has a cover film (5), between a memory cell (gate electrode 4, and source and drain regions 2a and 2b) and an interlayer insulating film (6), the cover film covering the memory cell, wherein the cover film (5) has a hydrogen storage film (5a) that is... Agent: Mcginn Intellectual Property Law Group, PLLC

20090250747 - Non-volatile memory devices having a multi-layered charge storage layer: A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap... Agent: Myers Bigel Sibley & Sajovec

20090250748 - Semiconductor device and method of fabricating the same: A semiconductor device and method of fabricating the same includes preparing a substrate, forming a plurality of conductive layer patterns on the substrate, forming a gate insulation layer on sidewalls of the conductive layer patterns, forming a pillar neck pattern between the conductive layer patterns, forming a pillar head over... Agent: Lowe Hauptman Ham & Berner, LLP

20090250749 - Methods of forming asymmetric recesses and gate structures that fill such recesses and related methods of forming semiconductor devices that include such recesses and gate structures: In a method of forming an asymmetric recess, an asymmetric recessed gate structure filling the asymmetric recess, a method of forming the asymmetric recessed gate structure, a semiconductor device having the asymmetric recessed gate structure and a method of manufacturing the semiconductor device, a semiconductor substrate is etched to form... Agent: Myers Bigel Sibley & Sajovec

20090250750 - Trench gate power mosfet: A trench gate power MOSFET (1) of the present invention includes an n-type epitaxial layer (12), gates (18) and MOSFET cells. The gate (18) is disposed in a trench (14) formed in a surface of the n-type epitaxial layer (12). The MOSFET cell is formed on the surface of the... Agent: Lowe Hauptman Ham & Berner, LLP

20090250751 - Mos device with low on-resistance: Some of the embodiments of the present disclosure provide a metal oxide semiconductor (MOS) device comprising a drain region, a gate region surrounding the drain region and formed in a loop around the drain region, a plurality of source regions arranged around the gate region, wherein each source region is... Agent: Schwabe, Williamson & Wyatt, P.C.

20090250752 - Methods of fabricating semiconductor device having a metal gate pattern: A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to... Agent: Harness, Dickey & Pierce, P.L.C

20090250753 - Semiconductor device and method of fabricating the same: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed on the semiconductor substrate with a gate insulating layer intervening... Agent: Hiscock & Barclay, LLP

20090250756 - N-type schottky barrier tunnel transistor and manufacturing method thereof: An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090250754 - Partially depleted silicon-on-insulator metal oxide semiconductor device: A partially depleted silicon-on-insulator metal oxide semiconductor (PD-SOI MOS) device is provided. The PD-SOI MOS device includes a gate structure on a silicon-on-insulator substrate, source and drain regions in the silicon-on-insulator substrate beside the gate structure and a silicon dislocation leakage path in an interface of the source region and... Agent: J C Patents, Inc.

20090250755 - Semiconductor device: A transistor capable of adjusting a threshold value is obtained by adjusting an impurity concentration of a silicon substrate supporting an SOI layer and by controlling a thickness of a buried insulating layer formed on a surface of the silicon substrate in contact with the SOI layer.... Agent: Foley And Lardner LLP Suite 500

20090250757 - Semiconductor device and method for manufacturing same: There is provided a semiconductor device having excellent device characteristics and reliability in which Vth values of an nMOS transistor and a pMOS transistor are controlled to be values necessary for a low-power device. The semiconductor device includes a pMOS transistor and an nMOS transistor formed by using an SOI... Agent: Young & Thompson

20090250758 - Manufacturing method of semiconductor device, evaluation method of semiconductor device, and semiconductor device: A semiconductor element formed over the same substrate as a TFT, includes a semiconductor film having an impurity region; an insulating film formed over the semiconductor film; an electrode divided into a plurality of parts over the insulating film by spacing a distance a in a first direction (channel width... Agent: Fish & Richardson P.C.

20090250759 - Semiconductor device: A breakdown voltage of a clamp diode can be reduced while a leakage current is suppressed. A P− type diffusion layer is formed in a surface of an N− type semiconductor layer. An N+ type diffusion layer is formed in a surface of the P− type diffusion layer. A P+... Agent: Morrison & Foerster LLP

20090250760 - Methods of forming high-k/metal gates for nfets and pfets: Methods of forming high-k/metal gates for an NFET and PFET and a related structure are disclosed. One method includes recessing a PFET region; forming a first high-k dielectric layer and a first metal layer over the substrate; removing the first high-k dielectric layer and the first metal over the NFET... Agent: Hoffman Warnick LLC

20090250761 - Semiconductor device with transistors and its manufacturing method: A semiconductor device includes a semiconductor substrate, a first transistor including a first gate electrode, a first diffusion region, and a second diffusion region respectively formed above the semiconductor substrate, second transistor including a second gate electrode, the first diffusion region, and a third diffusion region respectively formed above the... Agent: Mcginn Intellectual Property Law Group, PLLC

20090250763 - Integrated circuit including a first channel and a second channel: An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first area and a second area. The first area is stress engineered to provide enhanced mobility in a first channel that has a first width. The second area is stress engineered to provide enhanced mobility in a... Agent: Spryip, LLC Ifx

20090250762 - Integrated circuit system employing sacrificial spacers: An integrated circuit system that includes: providing a substrate including a first device and a second device; configuring the first device and the second device to include a first spacer, a first liner made from a first dielectric layer, and a second spacer made from a sacrificial spacer material; forming... Agent: Law Offices Of Mikio Ishimaru

20090250764 - Stressed dielectric layer with stable stress: An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric layer is disposed over the substrate and the transistor. At least one of the isolation... Agent: HorizonIPPte Ltd

20090250765 - Low on resistance cmos \"wave\" transistor for integrated circuit applications: In one embodiment of the present invention an array of power transistors on a semiconductor chip has repeating patterns of two “wave” gates which have alternating longer and shorter horizontal sections which are offset mirror images of each other together with a third straight horizontal section. Alternating source and drain... Agent: Hiscock & Barclay, LLP

20090250767 - Ed inverter circuit and integrate circuit element including the same: A second semiconductor layer of a second nitride-based compound semiconductor with a wider bandgap formed on a first semiconductor layer of a first nitride-based compound semiconductor with a smaller bandgap includes an opening, on which a gate insulating layer is formed at a portion exposed through the opening. A first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090250768 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device according to the present invention includes: a first transistor formed on a semiconductor substrate 11, the first transistor including a first gate-insulating film 14a that is oxynitrided; and a second transistor including a second gate-insulating film 14b formed on the semiconductor substrate 11 and a barrier... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090250766 - Work function based voltage reference: A voltage reference is created from an operational amplifier circuit having two substantially identical P-channel metal oxide semiconductor (P-MOS) transistors with each one having a different gate dopant. The different gate dopants result in different threshold voltages for each of the two otherwise substantially identical P-MOS transistors. The difference between... Agent: King & Spalding LLP

20090250769 - Semiconductor device having multiple fin heights: A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist... Agent: Slater & Matsil, L.L.P.

20090250770 - Integration of a sense fet into a discrete power mosfet: A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common substrate. The main FET and each of the sense FETs include a source terminal,... Agent: Joshua D. Isenberg Jdi Patent

20090250771 - Mosfet and production method of semiconductor device: To provide a MOSFET which is increased in substrate bias effect γ without increasing parasitic capacitance and junction leak current, the MOSFET includes: a gate electrode (104) formed on a semiconductor substrate (101) and an insulating film (103); a sidewall insulating film (106) covering the side surface of the gate... Agent: Mcginn Intellectual Property Law Group, PLLC

20090250772 - Field effect transistor and method of manufacture: A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source... Agent: Greenblum & Bernstein, P.L.C

20090250774 - Gate structure: A gate structure includes a gate insulation layer pattern, a gate electrode, a first spacer and a protecting layer pattern. The gate insulation layer pattern is on a substrate. The gate electrode is on the gate insulation layer pattern, the gate electrode including a lower portion having a first width,... Agent: Mills & Onello LLP

20090250773 - Semiconductor device: A semiconductor device includes a first metal region, a plurality of vias, a plurality of second metal regions, a plurality of openings and a third metal region. The first metal region conducts source/drain current. The second metal regions are electrically connected to the first metal region through the vias for... Agent: Rabin & Berdo, PC

20090250775 - Magnetic device with integrated magneto-resistive stack: This magnetic device integrates a magneto-resistive stack, the stack comprising at least two layers made out of a ferromagnetic material, separated from each other by a layer of non-magnetic material; and means for causing an electron current to flow perpendicular to the plane of the layers, with at least one... Agent: Burr & Brown

20090250776 - Magnetic memory device: There is provided a magnetic memory device stable in write characteristics. The magnetic memory device has a recording layer. The planar shape of the recording layer has the maximum length in the direction of the easy-axis over a primary straight line along the easy-axis, and is situated over a length... Agent: Mcdermott Will & Emery LLP

20090250777 - Image sensor and image sensor manufacturing method: In an upper waveguide structure (14), a width (W1) of the upper portion is larger than a width (W2) of the lower portion. The upper waveguide structure (14) has a side face (14a) which obliquely extends from an edge portion (14b) of the upper face to an edge portion (14c)... Agent: Cowan Liebowitz & Latman P.C. John J Torrente

20090250778 - Photoelectric conversion device, imaging system, photoelectric conversion device designing method, and photoelectric conversion device manufacturing method: A photoelectric conversion device comprises a plurality of photoelectric conversion units, a first antireflection portion including a first insulation film which has a first refractive index and a second insulation film which has a second refractive index, and a second antireflection portion including an element isolation portion which includes an... Agent: Fitzpatrick Cella Harper & Scinto

20090250779 - Solid-state imaging device and manufacturing method thereof: A solid-state imaging device in the present invention includes plural photoelectric conversion elements, plural wiring layers, and plural optical waveguide regions each corresponding to and arranged over one of the plural photoelectric conversion elements. A top end of each of the plural optical waveguide regions is higher than a top... Agent: Greenblum & Bernstein, P.L.C

20090250780 - High fill-factor laser-treated semiconductor device on bulk material with single side contact scheme: The present disclosure provides systems and methods for configuring and constructing a single photo detector or array of photo detectors with all fabrications circuitry on a single side and an architecture that enables the laser step to be the final step or a late step in the fabrication process. Both... Agent: Pepper Hamilton LLP

20090250781 - Power semiconductor device: The present invention relates to a power semiconductor device comprising a switching power semiconductor element, and a free wheeling diode in anti-parallel connection to the switching power semiconductor element. The power semiconductor is characterized in that a reverse electrode of the switching power semiconductor element and a reverse electrode of... Agent: Mcdermott Will & Emery LLP

20090250782 - Subgroundrule space for improved metal high-k device: The present invention provides a semiconducting device including a substrate including at least one semiconducting region and isolation regions; a gate structure atop the substrate having a gate dielectric layer positioned on the semiconducting region and a metal layer atop the gate dielectric layer, the gate structure having a width... Agent: Scully, Scott, Murphy & Presser, P.C.

20090250783 - Semiconductor device having an annular guard ring: A semiconductor chip 100 includes a logic unit and an analog unit 153. Furthermore, the semiconductor chip 100 includes a silicon substrate 101; a first insulating film 123 to a sixth insulating film 143 formed on the silicon substrate 101; and an annular seal ring 105 consisting of a first... Agent: Young & Thompson

20090250784 - Structure and method for elimination of process-related defects in poly/metal plate capacitors: An integrated circuit includes silicon layer (2) supported by a bottom oxide layer (3), a shallow trench oxide (4) in the shallow trench (30), and a polycrystalline silicon layer (5) on the shallow trench oxide. A deep trench oxide (25) extending from the shallow trench oxide to the bottom oxide... Agent: Texas Instruments Incorporated

20090250785 - Methods of forming a shallow base region of a bipolar transistor: The disclosed subject matter provides a method of forming a bipolar transistor. The method includes depositing a first insulating layer over a first layer of material that is doped with a dopant of a first type. The first layer is formed over a substrate. The method also includes modifying a... Agent: Williams, Morgan & Amerson

20090250786 - Fuse part of semiconductor device and method of fabricating the same: A fuse part of a semiconductor device includes an insulation layer over a substrate, and a fuse over the insulation layer, wherein the fuse includes a plurality of blowing pads for irradiating a laser beam and the plurality of blowing pads have laser coordinates different from one another.... Agent: Lowe Hauptman Ham & Berner, LLP

20090250788 - Semiconductor device: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction, a plurality of second interconnections each adjacent to the first interconnection located at an edge of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090250787 - Semiconductor storage device and manufacturing method of the same: A semiconductor storage device includes: a first conductive adhesive layer selectively formed over a semiconductor substrate; an insulating film formed on the semiconductor substrate to cover the first conductive adhesive layer and having an opening exposing a central part of the first conductive adhesive layer; and a capacitive element including... Agent: Mcdermott Will & Emery LLP

20090250789 - Methods of counter-doping collector regions in bipolar transistors: The present invention provides a method of forming a bipolar transistor. The method includes doping a silicon layer with a first type of dopant and performing a first implant process to implant dopant of a second type opposite the first type in the silicon layer. The implanted dopant has a... Agent: Williams, Morgan & Amerson

20090250790 - Nitride semiconductor wafer and method of processing nitride semiconductor wafer: Circular nitride wafers having a diameter larger than 45 mm are made and polished. Gross-polishing polishes the nitride wafers in a pressureless state with pressure less than 60 g/cm2 by lifting up the upper turntable for remedying distortion. Distortion height H at a center is reduced to H≦12 μm. Minute-polishing... Agent: Mcdermott Will & Emery LLP

20090250791 - Crystalline semiconductor stripes: Crystalline semiconductor stripes and an associated fabrication process are provided. The method provides an insulator substrate, and deposits a semiconductor layer overlying the insulator substrate. The semiconductor layer is irradiated using a scanning step-and-repeat laser annealing process, which agglomerates portions of the semiconductor layer. In response to cooling agglomerated semiconductor... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20090250792 - Curing low-k dielectrics for improving mechanical strength: An integrated circuit structure including reflective metal pads is provided. The integrated circuit structure includes a semiconductor substrate; a first low-k dielectric layer overlying the semiconductor substrate, wherein the first low-k dielectric layer is a top low-k dielectric layer; a second low-k dielectric layer immediately underlying the first low-k dielectric... Agent: Slater & Matsil, L.L.P.

20090250793 - Bpsg film deposition with undoped capping: Semiconductor devices containing a CVD BPSG layer and an undoped CVD oxide cap layer are described. The cap layer can be any silicon oxide material with a thickness between about 50 Å and about 350 Å. The cap layer may be formed using a low temperature CVD process that is... Agent: Kenneth E. Horton Kirton & Mcconkle

20090250797 - multi-chip package: A lead frame assembly includes at least one die paddle. The die paddle includes a first landing area for receiving a first semiconductor chip and a second landing area for receiving a second semiconductor chip. One or more steps are provided between the first landing area and the second landing... Agent: Edell , Shapiro & Finnan , LLC

20090250798 - Integrated circuit package system with interconnect support: An integrated circuit package system with interconnect support is provided including providing an integrated circuit, forming an electrical interconnect on the integrated circuit, forming a contact pad having a chip support, and coupling the integrated circuit to the contact pad by the electrical interconnect, with the integrated circuit on the... Agent: Law Offices Of Mikio Ishimaru

20090250795 - Leadframe for packaged electronic device with enhanced mold locking capability: A packaged electronic device (20) includes a die pad (30), leads (32) arranged around the die pad (30), and a die (24) attached to an upper surface (34) of the die pad (30) and electrically connected to the leads (32). A packaging material (28) encapsulates the die pad (30), the... Agent: Meschkow & Gresham, P.L.C

20090250794 - Method of forming a semiconductor package and structure therefor: In one embodiment, a semiconductor package is formed to include a leadframe that includes a plurality of die attach areas for attaching a semiconductor die to the leadframe. The leadframe is positioned to overlie another leadframe that forms some of the external terminals or leads of the package.... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20090250796 - Semiconductor device package having features formed by stamping: Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations... Agent: Townsend And Townsend And Crew, LLP

20090250799 - Power semiconductor module comprising an explosion protection system: A power semiconductor module for energy distribution, includes at least one power semiconductor, connection terminals for connecting the power semiconductor module, and a housing, in which protection from explosion is ensured in the module even in the event of electric arcs. Therefore, each power semiconductor and each connection terminal is... Agent: Lerner Greenberg Stemer LLP

20090250801 - Semiconductor device: A semiconductor device in which a plurality of semiconductor elements are stacked, yet realizing high speed operation of the semiconductor elements. The semiconductor device is provided with semiconductor packages, and a spacer. The semiconductor packages are stacked, with the spacer interposed therebetween. The semiconductor packages have, respectively, package boards, and... Agent: Mcginn Intellectual Property Law Group, PLLC

20090250800 - Semiconductor device and manufacturing method therefor: A semiconductor device is provided that includes a semiconductor chip and a resin section that molds the semiconductor chip and has a first through-hole. A through electrode that is electrically coupled to the semiconductor chip, extends through the resin section, and extends between a top edge and a bottom edge... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090250802 - Multilayer wiring substrate, semiconductor package, and methods of manufacturing semiconductor package: A multilayer wiring substrate included in the semiconductor package includes: a first insulating layer and a second insulating layer, in which wiring layers are respectively provided on the upper and the lower surfaces; and; a core layer provided between the first insulating layer and the second insulating layer. The first... Agent: Mcginn Intellectual Property Law Group, PLLC

20090250803 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a chip, a laminated wiring structure formed integrally with the chip, a frame disposed to surround the chip and made of a material having stiffness, and a sealing resin formed to bury therein the frame and at least the periphery of the side surface of the... Agent: Kratz, Quintos & Hanson, LLP

20090250804 - Leadframe-based ic-package with supply-reference comb: An IC package includes a leadframe-diepad (112) and a supply-reference comb (114) for interconnecting a die (110) and the package I/O pins (124) in a manner that facilitates substantially ideal EMC performance. The leadframe-diepad includes a diepad-finger (118) and an elongated portion. The leadframe-diepad and the diepad-finger are connected to... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090250805 - Heat dissipation for integrated circuit: A packaged integrated circuit having a thermal pathway to exhaust heat from the integrated circuit. The integrated circuit is disposed on a package substrate, with an encapsulant disposed around the integrated circuit. A heat sink is disposed at least partially within the encapsulant, with at least a portion of one... Agent: Lng/lsi Joint Customer C/o Luedeka, Neely & Graham, P.C.

20090250807 - Electronic component and method for its production: An electronic component includes a number of leads and at least one cooling element. The bottom surface of the cooling element is exposed and the material of the cooling element is different from the material of the leads. At least one semiconductor chip is provided on the cooling element. An... Agent: Edell , Shapiro & Finnan , LLC

20090250806 - Semiconductor package using an active type heat-spreading element: A semiconductor package includes a carrier, a chip, a stiffener, a heat spreader and an active type heat-spreading element. The chip and the stiffener are disposed on the carrier. The heat spreader is disposed on the stiffener and includes a through opening. The active type heat-spreading element is disposed on... Agent: Lowe Hauptman Ham & Berner, LLP

20090250808 - Reliability improvement in a compound semiconductor mmic: A semiconductor package (M) includes a semiconductor substrate layer (100) having a first side or upper surface (120) and a second side or lower surface or backplane (104) opposite the first side (120). A heat producing active area (102) is formed associated with the first side (120) of the semiconductor... Agent: Marsteller & Associates, P. C.

20090250810 - Integrated circuit packaging system with warpage control system and method of manufacture thereof: A method of manufacture of an integrated circuit packaging system is provided including: providing a substrate; and placing a patterned layer over the substrate for substantially removing crying warpage from the substrate.... Agent: Law Offices Of Mikio Ishimaru

20090250809 - Semiconductor package having thermal stress canceller member: A semiconductor package includes a package-substrate, a first cavity formed on a first main surface of the package substrate, a first semiconductor chip mounted on the bottom surface of the first cavity, a first resin layer filled into the first cavity, and a thermal stress canceller member mounted on the... Agent: Mcginn Intellectual Property Law Group, PLLC

20090250812 - Flip-chip mounting substrate and flip-chip mounting method: A solder resist and a central pad to which a central Au bump provided on a semiconductor chip is flip-chip bonded are formed on a substrate main body. In a flip-chip mounting substrate where an underfill resin is provided after the semiconductor chip is mounted, a central opening portion for... Agent: Rankin, Hill & Clark LLP

20090250813 - Integrated circuit solder bumping system: An integrated circuit solder bumping system provides a substrate and forms a redistribution layer on the substrate. An insulation layer is formed on the redistribution layer. The insulation layer has a plurality of openings therethrough. A first UBM layer of titanium is deposited on the insulation layer and in the... Agent: Law Offices Of Mikio Ishimaru

20090250811 - Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask: A semiconductor device has a semiconductor die with an die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die over the substrate so that the bump material is disposed between... Agent: Robert D. Atkins

20090250814 - Flip chip interconnection structure having void-free fine pitch and method thereof: A semiconductor device is made by providing a semiconductor die having a contact pad, forming a circular solder bump on the contact pad, providing a substrate having a trace line, disposing a non-circular solder resist opening over the trace line, placing the solder bump in proximity to the trace line,... Agent: Robert D. Atkins

20090250815 - Surface treatment for selective metal cap applications: Interconnect structures in which a noble metal-containing cap layer is present directly on a non-recessed surface of a conductive material which is embedded within a low k dielectric material are provided. It has been determined that by forming a hydrophobic surface on a low k dielectric material prior to metal... Agent: Scully, Scott, Murphy & Presser, P.C.

20090250817 - Method of fabricating semiconductor device and semiconductor device: A method of fabricating a semiconductor device according to embodiments includes forming a resist film above an object to be etched, the resist film having a pattern with notches provided in the vicinity of corners having an angle of less than 180 degrees on an opening side, and dry etching... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090250816 - Ultra-thin diffusion-barrier layer for cu metallization: Diffusion barrier layer is required during copper metallization in IC processing to prevent Cu from diffusion into the contacting silicon material and reacting to form copper silicide, which consumes Cu and deteriorates electrical conduction. With decreasing feature sizes of IC devices, such as those smaller than 90 nano-meter (nm), the... Agent: Lowe Hauptman Ham & Berner, LLP

20090250818 - Via electromigration improvement by changing the via bottom geometric profile: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal... Agent: Law Offices Of Mikio Ishimaru

20090250820 - Configurable non-volatile logic structure for characterizing an integrated circuit device: An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes a number of MLR cells and includes a parity circuit having... Agent: William L. Paradice, Iii

20090250819 - Metal line of semiconductor device and method of forming the same: The invention relates to a metal line of a semiconductor device and a method of forming the same. According to a method of forming a metal line of a semiconductor device in accordance with an aspect of the invention, a semiconductor substrate in which contact plugs are formed within contact... Agent: Marshall, Gerstein & Borun LLP

20090250821 - Corrosion resistant via connections in semiconductor substrates and methods of making same: Devices and methods for protecting the metal within a via in a semiconductor substrate from corrosion are provided. Specifically, embodiments of the present invention relate to disposing a corrosion resistant metal layer within a recess formed in a semiconductor substrate such that the metal subsequently deposited within the via will... Agent: Fletcher Yoder (micron Technology, Inc.)

20090250822 - Multi-chip stack package: A multi-chip stack package comprising a first wiring substrate, a first chip, a second wiring substrate, and a second chip is provided. The first wiring substrate is with a front side and a rear side. The first chip is disposed on the front side of the first wiring substrate and... Agent: Jianq Chyun Intellectual Property Office

20090250823 - Electronic modules and methods for forming the same: Electronic modules are formed by encapsulating microelectronic dies within cavities in a substrate.... Agent: Goodwin Procter LLP Patent Administrator

20090250824 - Method and apparatus to reduce pin voids: A semiconductor package comprises a substrate that utilizes one or more pins to form external interconnects. The pins are bonded to bonding pads on the substrate by solder. The pins may each has a pin head that may have a bonding surface, wherein the bonding surface may comprises a center... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090250825 - Process for producing acid anhydride-based epoxy resin curing agent, acid anhydride-based epoxy resin composition, and cured product and optical semiconductor device using the same: The present invention relates to a process for producing an acid anhydride-based epoxy resin curing agent, an acid anhydride-based epoxy resin curing agent, an epoxy resin composition, and a cured product and optical semiconductor device using the same. The process for producing an acid anhydride-based epoxy resin curing agent according... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090250826 - Process for manufacturing semiconductor device and semiconductor device manufactured by such process: A process for manufacturing a semiconductor device that inhibits deterioration in the quality of the semiconductor device and a semiconductor device manufactured on such manufacturing process are presented. An operation of determining time-variation of water content in the resin substrate 11 (processing S1); an operation of coupling the semiconductor element... Agent: Mcginn Intellectual Property Law Group, PLLC