|Active solid-state devices (e.g., transistors, solid-state diodes) patents - Monitor Patents|
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Active solid-state devices (e.g., transistors, solid-state diodes) October categorized by USPTO classification 10/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 10/28/2010 > patent applications in patent subcategories. categorized by USPTO classification
20100270527 - Phase-change memory device and method of manufacturing the phase-change memory device: A phase-change memory device has a plurality of first wiring lines; a plurality of memory cells that are provided on the plurality of first wiring lines; a plurality of second wiring lines that are provided on the plurality of memory cells, respectively; and an interlayer insulating film that is formed... Agent: Turocy & Watson, LLP
20100270528 - Resistive random access memory device and method of same: Disclosed are a resistive random access memory device (ReRAM) and a method for manufacturing the same. The ReRAM includes a cell array including a metal oxide nanowire formed inside a micropore array of a porous template, a first electrode electrically connected to an upper protrusion of the metal oxide nanowire,... Agent: Hayes Soloway P.C.
20100270529 - Integrated circuit 3d phase change memory array and manufacturing method: A 3D phase change memory device is based on an array of electrode pillars and a plurality of electrode planes that intersect the electrode pillars at interface regions that include memory elements that comprise a programmable phase change memory element and a threshold switching element. The electrode pillars can be... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100270530 - Semiconductor nanowire sensor device and method for manufacturing the same: A method for manufacturing a biosensor device is provided. The method involves forming a silicon nanowire channel with a line width of several nanometers to several tens of nanometers using a typical photolithography process, and using the channel to manufacture a semiconductor nanowire sensor device. The method includes etching a... Agent: Ampacc Law Group
20100270531 - Gan based light emitters with band-edge aligned carrier blocking layers: Band-edge aligned carrier blocking layers are introduced into wurtzite or zinc blende Gallium Nitride based diode laser and LEDs in order to prevent thermionic emission and the overflow of carriers at elevated operating temperatures. These blocking layers are located in the direct vicinity of the active zone of the light... Agent: Ashmeet K Samal
20100270532 - Nitride semi-conductor light emitting device: A nitride semi-conductor light emitting device has a p-type nitride semi-conductor layer 7, an n-type nitride semi-conductor layer 3, and a light emission layer 6 which is interposed between the p-type nitride semi-conductor layer 7 and the n-type nitride semi-conductor layer 3. The light emission layer 6 has a quantum... Agent: Cheng Law Group, PLLC
20100270534 - Electronic device using quantum dot: The electronic device comprising the ferromagnetic micro magnet (10) disposed in the vicinity of the quantum dots (8, 9) of a plurality of aligned semiconductor quantum dots, wherein a strong magnetic field is applied so as to induce electron spin resonance (ESR), and the layout of the ferromagnetic micro magnet... Agent: Bacon & Thomas, PLLC
20100270533 - Zno-based semiconductor element: Provided is a ZnO-based semiconductor device capable of achieving easier conversion into p-type by alleviating the self-compensation effect and by preventing donor impurities from mixing in. The ZnO-based semiconductor device includes a MgxZn1-xO substrate (0≦x≦1) having such a principal surface that: a projection axis obtained by projecting a normal line... Agent: Rabin & Berdo, PC
20100270535 - Electronic device including an electrically polled superlattice and related methods: A method for making an electronic device may include forming a selectively polable superlattice comprising a plurality of stacked groups of layers. Each group of layers of the selectively polable superlattice may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.
20100270536 - Concentric gate nanotube transistor devices: Single-walled carbon nanotube transistor devices, and associated methods of making such devices include a porous structure for the single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another material. Electrodes for source and drain of a transistor are provided at opposite ends of the single-walled carbon nanotube... Agent: Aka Chan LLP
20100270543 - Biomolecule-based electronic device: The present invention relates to a biomolecule-based electronic device in which the biomolecule with redox potential is directly immobilized on the substrate. The present invention enables to excellently exhibit the capability of a protein-based bio-memory device in which it is preferable to use the substrate on which cysteine-introduced recombinant proteins... Agent: Clark & Elbing LLP
20100270540 - Iridium complex containing carbazole-substituted pyridine and phenyl derivatives as main ligand and organic light-emitting diodes containing the same: The present invention relates to a novel iridium complex into which carbazole-substituted pyridine derivatives and various substituents-substituted phenyl derivatives are introduced as main ligand and a electrophosphorescence diode containing the same as a dopant of a light-emitting layer. When the iridium complex according to the present invention is applied to... Agent: The Webb Law Firm, P.C.
20100270545 - Light-emitting device using voltage switchable dielectric material: A voltage switchable dielectric material (VSD) material as part of a light-emitting component, including LEDs and OLEDs.... Agent: Mahamedi Paradice Kreisman LLP
20100270546 - Light-emitting device using voltage switchable dielectric material: A voltage switchable dielectric material (VSD) material as part of a light-emitting component, including LEDs and OLEDs.... Agent: Mahamedi Paradice Kreisman LLP
20100270537 - Optoelectronic devices and organic compounds used therein: a light emitting-layer; and an anode; wherein R1 and R2 are independently at each occurrence, hydrogen, a C1-C20 aliphatic radical, a C3-C20 aromatic radical, or a C3-C20 cycloaliphatic radical; R3 is H or alkyl; a and b are, independently at each occurrence 0, or an integer ranging from 1 to... Agent: General Electric Company Global Research
20100270539 - Organic el element and organic el material-containing solution: An organic EL device (1) includes an anode (3), a cathode (4) and an organic thin-film layer (5) provided between the anode (3) and the cathode (4). The organic thin-film layer (5) includes a single-layered mixed-color emitting layer (51) for providing mixed-color emission. The mixed-color emitting layer (51) contains a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100270538 - Organic light emitting display device and method of manufacturing the same: Provided are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device includes a substrate; at least one thin film transistor including a gate electrode including a metal oxide layer and a metal layer, a semiconductor layer including source/drain regions and... Agent: Robert E. Bushnell & Law Firm
20100270544 - Polymer light emitting element, method for manufacturing the same and polymer light emitting display device: A polymer light emitting element having a large light releasing surface, a high light emitting efficiency and a long life, a polymer light emitting display device and planar light source, as well as a method for manufacturing the polymer light emitting element are provided. The polymer light emitting element is... Agent: Sughrue Mion, PLLC
20100270542 - Solution processable organic semiconductors: Semiconductor devices, methods of making semiconductor devices, and coating compositions that can be used to provide a semiconductor layer within a semiconductor device are described. The coating compositions include a small molecule semiconductor, an insulating polymer, and an organic solvent that can dissolve both the small molecule semiconductor material and... Agent: 3m Innovative Properties Company
20100270541 - System for display images and fabrication method thereof: A system for displaying images including a display panel and a fabrication method thereof are provided. The display panel includes a substrate having a first, second and third areas, a first patterned semiconductor layer disposed over the first area of the substrate, a first insulating layer covering the first patterned... Agent: Liu & Liu
20100270547 - Semiconductor device: Semiconductor devices having at least one barrier layer with a wide energy band gap are disclosed. In some embodiments, a semiconductor device includes at least one active layer composed of a first compound, and at least one barrier layer composed of a second compound and disposed on at least one... Agent: Workman Nydegger 1000 Eagle Gate Tower
20100270549 - Semiconductor device and method of providing electrostatic discharge protection for integrated passive devices: A semiconductor device has an integrated passive device (IPD) formed over a substrate. The IPD can be a metal-insulator-metal capacitor or an inductor formed as a coiled conductive layer. A signal interconnect structure is formed over the first side or backside of the substrate. The signal interconnect structure is electrically... Agent: Robert D. Atkins
20100270548 - Semiconductor element and method of making same: A semiconductor element includes a substrate including gallium oxide and having a predetermined plane direction, and a semiconductor layer formed on the substrate, in which, the semiconductor element is in chip form and further includes a first end face formed along a cleaved surface of the substrate and a second... Agent: Mcginn Intellectual Property Law Group, PLLC
20100270551 - Bottom gate thin film transistor and active array substrate: A bottom gate thin film transistor and an active array substrate are provided. The bottom gate thin film transistor includes a gate, a gate insulation layer, a semiconductor layer, a plurality of sources and a plurality of drains. The gate insulation layer is disposed on the gate. The semiconductor layer... Agent: Jianq Chyun Intellectual Property Office
20100270553 - Liquid crystal display and method for manufacturing the same: The present invention provides a thin film transistor having high performance in a liquid crystal display, and a manufacturing method of a liquid crystal display according to an exemplary embodiment of the present invention that includes: forming a gate line including a gate electrode on a substrate; forming a gate... Agent: H.c. Park & Associates, PLC
20100270554 - Method of reforming a metal pattern, array substrate, and method of manufacturing the array substrate: A method of reforming a metal pattern for improving the productivity and reliability of a manufacturing process, an array substrate and a method of manufacturing the array substrate are disclosed. In the method, a first wiring pattern is formed on an insulation substrate. The first wiring pattern is removed. A... Agent: H.c. Park & Associates, PLC
20100270550 - Pixel structure and the method of forming the same: A pixel structure includes a drain shielding extension portion disposed on a floating semiconductor layer, wherein the floating semiconductor layer is formed together with a thin-film transistor channel layer. Therefore, the total thickness of the floating semiconductor layer and the drain shielding extension portion is increased, such that the distance... Agent: North America Intellectual Property Corporation
20100270556 - Tft lcd array substrate and manufacturing method thereof: A TFT LCD array substrate and a manufacturing method thereof. The TFT LCD array substrate comprises a substrate. A gate line and a gate electrode that is formed integrally with the gate line are formed on the substrate. A first insulating layer and a semiconductor layer are formed sequentially on... Agent: Hasse & Nesbitt LLC
20100270555 - Thin film transistor array panel: A thin film transistor array panel includes: first and second gate lines disposed on a substrate and separated from each other; a data line intersecting the first and second gate lines; first and second thin film transistors connected to the first gate line and the data line; a third thin... Agent: Cantor Colburn, LLP
20100270552 - Thin film transistor substrate and method of manufacturing the same: A protrusion of dry-etched pattern of a thin film transistor substrate generated due to a difference between isotropy of wet etching and anisotropy of dry etching is removed by forming a plating part on a surface of the wet etched pattern through an electroless plating method. If the plating part... Agent: Innovation Counsel LLP
20100270558 - Fabricating method of polycrystalline silicon thin film, polycrystalline silicon thin film fabricated using the same: Provided are a method of fabricating a polycrystalline silicon thin film using high temperature heat generated by Joule heating induced by application of an electrical field to a conductive layer, which can ensure process stability at high temperature and thus processing time can be reduced and a polycrystalline silicon thin... Agent: Cantor Colburn, LLP
20100270557 - Methods of producing high uniformity in thin film transistor devices fabricated on laterally crystallized thin films: Methods of producing high uniformity in thin film transistor devices fabricated on laterally crystallized thin films are described. A thin film transistor (TFT) includes a channel area disposed in a crystalline substrate, which has grain boundaries that are approximately parallel with each other and are spaced apart with approximately equal... Agent: Wilmerhale/columbia University
20100270559 - Field effect transistor and process for manufacturing same: A field effect transistor includes: a channel layer 103 containing GaN or InGaN; a first electron-supplying layer 104 disposed over the channel layer 103 and containing InxAlyGa1-x-yN (0≦x<1, 0<y<1, 0<x+y<1); a first etch stop layer 105 disposed over the first electron-supplying layer 104 and containing indium aluminum nitride (InAlN); and... Agent: Mr. Jackson Chen
20100270560 - System and method for emitter layer shaping: Embodiments of an LED disclosed has an emitter layer shaped to a controlled depth or height relative to a substrate of the LED to maximize the light output of the LED and to achieve a desired intensity distribution. In some embodiments, the exit face of the LED may be selected... Agent: SprinkleIPLaw Group
20100270561 - Method for manufacturing a cubic silicon carbide single crystal thin film and semiconductor device based on the cubic silicon carbide single crystal thin film: A cubic silicon carbide single crystal thin film is manufactured by a method. A sacrificial layer is formed on a surface of a substrate. A cubic semiconductor layer is formed on the sacrificial layer, the cubic semiconductor layer having at least a surface of cubic crystal structure. A cubic silicon... Agent: Rabin & Berdo, PC
20100270562 - Semiconductor wafer, semiconductor thin film, and method for manufacturing semiconductor thin film devices: A method for manufacturing a semiconductor thin film device includes: forming a buffer layer on an Si (111) substrate and a single crystal semiconductor layer on the buffer layer; forming an island including the semiconductor layer, buffer layer, and a portion of the substrate; forming a coating layer on the... Agent: Rabin & Berdo, PC
20100270564 - Led package and backlight unit using the same: The invention relates to an LED package having a large beam angle of light emitted from an LED, simplifying a shape of a lens and an assembly process, and to a backlight unit using the same. The LED package includes a housing with a seating recess formed therein and at... Agent: Mcdermott Will & Emery LLP
20100270563 - Method of manufacturing semiconductor device, semiconductor device, active matrix device, electro-optical device, and electronic apparatus: A method of manufacturing a semiconductor device includes: forming, on one surface of a substrate, source electrodes and drain electrodes, a semiconductor layer provided between the source electrodes and the drain electrodes, and a gate insulator layer provided to cover a surface of the semiconductor layer; forming an insulator layer... Agent: Oliff & Berridge, PLC
20100270565 - Semiconductor light-emitting device and method of fabricating the same: The invention provides a semiconductor light-emitting device package structure. The semiconductor light-emitting device package structure includes a substrate, N sub-mounts, and N semiconductor light-emitting die modules, wherein N is a positive integer lager than or equal to 1. Each of the sub-mounts is embedded on the substrate and exposed partially.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100270566 - Light emitting device with selective reflection function: A light emitting device with selective reflection function being applied to general light emitting device and AC-type light emitting device is revealed. The light emitting device includes at least one vertical light emitting unit, at least one selective reflection layer and a phosphor layer. The selective reflection layer is disposed... Agent: Sinorica, LLC
20100270567 - Lighting device: A light emission package includes multiple colored solid state emitters each having a different non-white dominant wavelength in the visible range, and at least one lumiphor arranged to receive emissions from at least one other solid state emitter, with each emitter arranged on or adjacent to a common submount. The... Agent: Intellectual Property / Technology Law
20100270568 - Light emitting device and method of fabricating the same: A light emitting device comprises a light emitting layer section having a double heterostructure of an n-type cladding layer, an active layer and a p-type cladding layer, each composed of AlGaInP stacked in this order. Supposing a bonding object layer having a first main surface side as p type and... Agent: Arent Fox LLP
20100270573 - Light emitting device, light emitting device package, and lighting system including the same: Provided are a light emitting device, a light emitting device package, and a lighting system including the light emitting device and the light emitting device package. The light emitting device includes a light emitting structure, a dielectric, a second electrode layer, a semiconductor region, and a first electrode. The light... Agent: Ked & Associates, LLP
20100270570 - Light emitting element: The present invention provides a light emitting element comprising a first substrate, a light emitting unit disposed on the first substrate, at least a selective reflection layer disposed on an emitting side of the light emitting unit so that a light of a first color emitted from the light emitting... Agent: Sinorica, LLC
20100270569 - Optoelectronic component: The invention relates to an optoelectronic component having at least one semi-conductor body (1) that has an active area (2) for producing electromagnetic radiation and a housing (4) that has a filter element (5) which is arranged downstream from the active area (2) in the direction of radiation. The filter... Agent: Fish & Richardson PC
20100270572 - Photonic crystal led: A semiconductor light emitting diode (1, LED), comprising a first and a second electrode (40, 11) for applying a voltage across an active region (4) for generation of light, a light emitting surface (6), and a plurality of photonic crystals (101, 102). Further, at least two photonic crystals (101, 102)... Agent: Philips Intellectual Property & Standards
20100270574 - Silicone coated light-emitting diode: A silicone coated light-emitting diode and the method for making the silicone coated light-emitting diode.... Agent: K&l Gates LLP
20100270571 - Slim led package: Disclosed herein is a slim LED package. The slim LED package includes first and second lead frames separated from each other, a chip mounting recess formed on one upper surface region of the first lead frame by reducing a thickness of the one upper surface region below other upper surface... Agent: H.c. Park & Associates, PLC
20100270575 - Ac led package structure: An AC LED package structure includes a heat-sink slug, an AC LED module, a positive-electrode frame, a negative-electrode frame, and an insulation submount. The AC LED module is electrically connected with the positive-electrode frame and the negative-electrode frame, respectively. The insulation submount is interposed between the AC LED module and... Agent: Bacon & Thomas, PLLC
20100270579 - Light emitting device package and lighting system including the same: Provided are a light emitting device (LED) package and a lighting system including the same. The LED package comprises a package body comprising a recess in an upper portion thereof, and an LED chip provided in the recess of the package body.... Agent: Ked & Associates, LLP
20100270578 - Light emitting diode chip with overvoltage protection: A light emitting diode chip includes a device for protection against overvoltages, e.g., an ESD protection device. The ESD protection device is integrated into a carrier, on which the semiconductor layer sequence of the light emitting diode chip is situated, and is based on a specific doping of specific regions... Agent: Slater & Matsil, L.L.P.
20100270576 - Light emitting diode package: There is provided a light emitting diode package, including a package body including a recess portion having a housing space and a lead frame mounted on the recess portion to be exposed; a light emitting diode chip mounted to be electrically connected to the lead frame; and a position indicator... Agent: Mcdermott Will & Emery LLP
20100270577 - Plastic component for a lighting systems: The invention relates to a plastic component for use in a lighting system, the plastic component comprising a semi-aromatic polyamide (X) comprising repeat units derived from aliphatic diamines and dicarboxylic acids wherein: (a) the aliphatic diamines consist a mixture of 10-70 mole % of a short chain aliphatic diamine with... Agent: Nixon & Vanderhye, PC
20100270582 - Coated light-emitting diode: The present invention relates to a coated light-emitting diode and the method for making the coated light-emitting diode.... Agent: K&l Gates LLP
20100270581 - Optical semiconductor package sealing resin material: An optical semiconductor package sealing resin material used to seal an optical semiconductor chip in a semiconductor package includes a thermosetting epoxy composition and a hydrophobic smectite clay mineral. The hydrophobic smectite clay mineral is hydrophobized by subjecting a hydrophilic smectite clay mineral to an intercalation reaction with an alkylammonium... Agent: Oliff & Berridge, PLC
20100270580 - Substrate based light source package with electrical leads: A light source and method for making the same are disclosed. The light source includes a base member and a lead structure. The lead structure is attached to the base member such that the lead structure extends beyond the base member and has an opening for accessing a surface of... Agent: The Law Offices Of Calvin B. Ward
20100270583 - Manufacturing method of nitride semi-conductor layer, and a nitride semi-conductor light emitting device with its manufacturing method: In a process of fabricating a nitride nitride semi-conductor layer of AlaGabIn(1-a-b)N (0<a<1, 0<b<1, 1−a−b>0), the AlGaInN layer is grown at a growth rate less than 0.09 μm/h according to the metal organic vapor phase epitaxy (MOPVE) method. The AlGaInN layer fabricated by the process in the present invention exhibits... Agent: Cheng Law Group, PLLC
20100270584 - Semiconductor switching device with gate connection: The present disclosure provides a semiconductor switching device including a substrate having deposited thereon a cathode, an anode and a gate of the semiconductor switching device, and a connection means for electrically connecting the cathode in the gate of the semiconductor switching device to an external circuit unit. The connection... Agent: Buchanan, Ingersoll & Rooney PC
20100270585 - Method for manufacturing a reverse-conducting insulated gate bipolar transistor: A reverse-conducting insulated gate bipolar transistor includes a wafer of first conductivity type with a second layer of a second conductivity type and a third layer of the first conductivity type. A fifth electrically insulating layer partially covers these layers. An electrically conductive fourth layer is electrically insulated from the... Agent: Buchanan, Ingersoll & Rooney PC
20100270587 - Reverse-conducting semiconductor device and method for manufacturing such a reverse-conducting semiconductor device: A reverse-conducting semiconductor device (RC-IGBT) including a freewheeling diode and an insulated gate bipolar transistor (IGBT), and a method for making the RC-IGBT are provided. A wafer has first and second sides emitter and collector sides of the IGBT, respectively. At least one layer of a first or second conductivity... Agent: Buchanan, Ingersoll & Rooney PC
20100270586 - Wide band gap semiconductor device: A semiconductor device having high reliability and high load short circuit withstand capability while maintaining a low ON resistance is provided, by using a WBG semiconductor as a switching element of an inverter circuit. In the semiconductor device for application to a switching element of an inverter circuit, a band... Agent: Rossi, Kimms & Mcdowell LLP.
20100270588 - Formulations for voltage switchable dielectric material having a stepped voltage response and methods for making the same: Formulations for voltage switchable dielectric materials include two or more different types of semiconductive materials uniformly dispersed within a dielectric matrix material. The semiconductive materials are selected to have different bandgap energies in order to provide the voltage switchable dielectric material with a stepped voltage response. The semiconductive materials can... Agent: Carr & Ferrell LLP
20100270589 - Photodetectors converting optical signal into electrical signal: Provided is a photodetector converting an optical signal into an electrical signal. The photodetector includes: a plurality of semiconductor layers sequentially stacked on a substrate; a plurality of photoelectric conversion units formed in the semiconductor layers, respectively, and having different spectral sensitivities from each other; and buffer layers interposed between... Agent: Ampacc Law Group
20100270590 - Ald of silicon films on germanium: The use of atomic layer deposition (ALD) to form a semiconductor structure of a silicon film on a germanium substrate is disclosed. An example embodiment includes a tantalum nitride gate electrode on a hafnium dioxide gate dielectric on the silicon film (TaN/HfO2/Si/Ge), which produces a reliable high dielectric constant (high... Agent: Schwegman, Lundberg & Woessner/micron
20100270591 - High-electron mobility transistor: Disclosed are high electron mobility transistors (HEMTs). In some embodiments, a HEMT includes a channel layer composed of a first compound semiconductor material and one or more barrier layers disposed on either one side or both sides of the channel layer and composed of a second compound semiconductor material.... Agent: Workman Nydegger 1000 Eagle Gate Tower
20100270592 - Semiconductor device: Semiconductor devices having at least one barrier layer with a wide energy band gap are disclosed. In some embodiments, a semiconductor device includes at least one active layer, and at least one barrier layer disposed on at least one surface of the at least one active layer. The at least... Agent: Workman Nydegger 1000 Eagle Gate Tower
20100270593 - Integrated circuit 3d memory array and manufacturing method: A 3D memory device is based on an array of electrode pillars and a plurality of electrode planes that intersect the electrode pillars at interface regions that include memory elements that comprise a programmable element and a rectifier. The electrode pillars can be selected using two-dimensional decoding, and the plurality... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100270594 - Image sensor: An image sensor according to the present invention includes a second conductivity type first impurity region provided on a surface of a first conductivity type semiconductor substrate for constituting a transfer channel for signal charges, a charge increasing portion provided on the first impurity region for increasing the amount of... Agent: Ditthavong Mori & Steiner, P.C.
20100270595 - Device for detection of a gas or gas mixture and method for manufacturing such a device: A device for detecting a gas or gas mixture has a first and a second gas sensor. The first gas sensor is a MOSFET, which comprises a first source, a first drain, a first channel zone disposed between the latter elements, and a first gas sensitive layer capacitively coupled to... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20100270596 - Mems sensor, method of manufacturing mems sensor, and electronic apparatus: A MEMS sensor includes: a substrate; a fixed electrode portion formed in the substrate; a movable weight portion formed above the fixed electrode portion via a gap; a movable electrode portion formed in the movable weight portion and disposed so as to face the fixed electrode portion; a supporting portion;... Agent: Harness, Dickey & Pierce, P.L.C
20100270597 - Method and apparatus for placing transistors in proximity to through-silicon vias: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP
20100270598 - Method for forming highly strained source/drain trenches: A multi-step etching process produces trench openings in a silicon substrate that are immediately adjacent transistor structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the... Agent: Duane Morris LLP (tsmc)IPDepartment
20100270600 - Semiconductor integrated circuit device and method of designing the same: A method of designing a semiconductor integrated circuit device includes: arranging standard cells constituting a MISFET; analyzing an operation timing and/or power consumption of the arranged standard cells; identifying one of the standard cells that is desired to have improved properties as a cell of interest based on the obtained... Agent: SprinkleIPLaw Group
20100270599 - Transistor structure with high reliability and method for manufacturing the same: A transistor structure with high reliability includes a substrate unit, a solid ozone boundary layer, a gate oxide layer and a gate electrode. In addition, the substrate unit has a substrate body, a source electrode exposed on a top surface of the substrate body, and a drain electrode exposed on... Agent: Rosenberg, Klein & Lee
20100270601 - Semiconductor device having reduced single bit fails and a method of manufacture thereof: One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The... Agent: Texas Instruments Incorporated
20100270603 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises gates comprising a first conductive layer, landing plug contacts formed adjacent to the gate and formed of a second conductive layer, a bit line formed over the landing plug contacts and formed of a third conductive layer, and storage electrode contacts formed over the landing plug... Agent: Ampacc Law Group
20100270602 - Semiconductor memory device and method for manufacturing the same: A semiconductor memory device and a method for manufacturing the same are disclosed, which reduce parasitic capacitance generated between a storage node contact and a bit line of a high-integration semiconductor device. A method for manufacturing a semiconductor memory device includes forming a buried word line in an active region... Agent: Ampacc Law Group
20100270604 - Non-volatile memories and methods of fabrication thereof: Non-volatile memories and methods of fabrication thereof are described. In one embodiment, a method of fabricating a semiconductor device includes forming an oxide layer over a semiconductor substrate, and exposing the oxide layer to a first nitridation step to form a first nitrogen rich region. The first nitrogen rich region... Agent: Slater & Matsil, L.L.P.
20100270605 - Nonvolatile memory cell and method for fabricating the same: A nonvolatile memory cell and a method for fabricating the same can secure stable operational reliability as well as reducing a cell size. The nonvolatile memory cell includes a drain region formed in a substrate, a source region formed in the substrate to be separated from the drain region, a... Agent: Morgan Lewis & Bockius LLP
20100270607 - Nonvolatile semiconductor memory device and method for manufacturing the same: It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100270606 - Nonvolatile semiconductor memory device and method of forming the same: A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100270608 - Integrated circuits and fabrication using sidewall nitridation processes: Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A... Agent: Vierra Magen/sandisk Corporation
20100270609 - Modification of charge trap silicon nitride with oxygen plasma: A flash memory device comprises a substrate comprising silicon with a silicon dioxide layer thereon. A silicon-oxygen-nitrogen layer is on the silicon dioxide layer, and the silicon-oxygen-nitrogen layer comprises a shaped concentration level profile of oxygen through the thickness of the layer. A blocking dielectric layer is on the silicon-oxygen-nitrogen... Agent: Ashok K. Janah
20100270610 - Nrom flash memory devices on ultrathin silicon: An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on... Agent: Leffert Jay & Polglaze, P.A.
20100270611 - Semiconductor device including a mos transistor and production method therefor: It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; a bottom doped region formed in contact with a lower part of the semiconductor pillar; a first gate formed around a sidewall of the semiconductor pillar through a first dielectric film therebetween; and a... Agent: Brinks Hofer Gilson & Lione
20100270612 - Method for producing a vertical transistor component: A method for producing a vertical transistor component includes providing a semiconductor substrate, applying an auxiliary layer to the semiconductor substrate, and patterning the auxiliary layer for the purpose of producing at least one trench which extends as far as the semiconductor substrate and which has opposite sidewalls. The method... Agent: Maginot, Moor & Beck
20100270613 - Method for manufacturing semiconductor device, and semiconductor device: In a transistor region, a source interconnect layer and a gate electrode are buried in trenches. A source extending region is provided adjacent to the transistor region or in the transistor region, and a source interconnect layer is designed to protrude from the upper end of a trench. This source... Agent: Mcginn Intellectual Property Law Group, PLLC
20100270614 - Process for manufacturing devices for power applications in integrated circuits: An embodiment method for forming a MOS transistor for power applications in a substrate of semiconductor material, said method being integrated in a process for manufacturing integrated circuits which uses an STI technique for forming the insulating regions. The method includes the phases of forming an insulating element on a... Agent: Graybeal Jackson LLP
20100270615 - Method for increasing breaking down voltage of lateral diffused metal oxide semiconductor transistor: A lateral diffused metal oxide semiconductor transistor is disclosed. A p-type bulk is disposed on a substrate. An n-type well region is disposed in the p-type bulk. A plurality of field oxide layers are disposed on the p-type bulk and the n-type well region. A gate structure is disposed on... Agent: Quintero Law Office, PC
20100270616 - Semiconductor device and method of manufacturing the same: There is provided a semiconductor device in which the degradation of electric characteristics can be inhibited. A semiconductor substrate has a main surface, and a trench in the main surface. A buried insulating film is buried in the trench. The trench has one wall surface and the other wall surface... Agent: Mcdermott Will & Emery LLP
20100270617 - Nanowire electronic devices and method for producing the same: The present invention is directed to an electrical device that comprises a first and a second fiber having a core of thermoelectric material embedded in an electrically insulating material, and a conductor. The first fiber is doped with a first type of impurity, while the second fiber is doped with... Agent: Foley And Lardner LLP Suite 500
20100270618 - Production method of semiconductor device and semiconductor device: e
20100270619 - Fin field effect transistor having low leakage current and method of manufacturing the finfet: Provided is a fin field effect transistor (FinFET) having low leakage current and a method of manufacturing the same. The FinFET includes: a bulk silicon substrate; a fence-shaped body formed by patterning the substrate; an insulating layer formed on a surface of the substrate to a first height of the... Agent: The Nath Law Group
20100270621 - Semiconductor device and method of manufacturing the semiconductor device: A semiconductor device includes: a FinFET (Fin Field Effect Transistor); and a PlanarFET (Planar Field Effect Transistor). The FinFET is provided on a chip. The PlanarFET is provided on the chip. A second gate insulating layer of the PlanarFET is thicker than a first gate insulating layer of the FinFET.... Agent: Mcginn Intellectual Property Law Group, PLLC
20100270622 - Semiconductor device having a strain inducing sidewall spacer and a method of manufacture therefor: The present invention provides a method for manufacturing a semiconductor device as well as a semiconductor device. The method, among other steps, may include forming a gate structure over a substrate, and forming a strain inducing sidewall spacer proximate a sidewall of the gate structure, the strain inducing sidewall configured... Agent: Texas Instruments Incorporated
20100270620 - System and method for constructing shielded seebeck temperature difference sensor: An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor... Agent: Slater & Matsil, L.L.P.
20100270624 - Reduced-step cmos processes for low cost radio frequency identification devices: Reduced-step CMOS processes for low-cost integrated circuits (ICs) and, more particularly, low-cost radio frequency identification (RFID) devices are disclosed. The CMOS processes disclosed provide sufficient device performance and reliability while reducing the number and complexity of required process steps, thereby reducing the cost for manufacturing ICs. By recognizing the particular... Agent: Lando & Anastasi, LLP
20100270623 - Semiconductor device and semiconductor device fabrication method: A semiconductor device fabrication method including: forming a gate conductor including a gate for a transistor in the first region, and a gate for a transistor in the second region, and a first film over a first stress film for covering the transistors; etching the first film from the second... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100270625 - Method of fabricating high-voltage metal oxide semiconductor transistor devices: A process of fabricating a transistor employs a relatively thicker sacrificial nitride layer that reduces the time and cost associated with chemical-mechanical polish (CMP) processes by reducing the topography associated with the transistor. The process includes forming the gate oxide region and a field oxide region on a substrate. A... Agent: Kinney & Lange, P.A.
20100270626 - Atomic layer deposition of hafnium lanthanum oxides: There is provided an improved method for depositing thin films using precursors to deposit binary oxides by atomic layer deposition (ALD) techniques. Also disclosed is an ALD method for depositing a high-k dielectric such as hafnium lanthanum oxide (HfLaO) on a substrate. Embodiments of the present invention utilize a combination... Agent: Squire Sanders & Dempsey LLP
20100270627 - Method for protecting a gate structure during contact formation: A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming at least one gate structure over the substrate; forming a plurality of doped regions in the substrate; forming an etch stop layer over the substrate; removing a first portion of the etch stop layer,... Agent: Haynes And Boone, LLPIPSection
20100270628 - Multifunction mens element and integrated method for making mos and multifunction mens: A multifunction MENS element includes a first cantilever, a second cantilever and a MENS component. The first cantilever, the second cantilever and the MENS component together form a MENS structure. The MENS component includes an inductor device.... Agent: North America Intellectual Property Corporation
20100270629 - Pressure sensor and manufacturing method thereof: The pressure sensor according to the present invention has a sensor chip having a first semiconductor layer that has an opening portion, and a second semiconductor layer, formed on the first semiconductor layer, having a recessed portion that forms a diaphragm and a base, having a pressure guiding hole that... Agent: Mcdermott Will & Emery LLP
20100270630 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a first substrate made of semiconductor and having first regions, which are insulated from each other and disposed in the first substrate; and a second substrate having electric conductivity and having second regions and insulation trenches. Each insulation trench penetrates the second substrate so that the... Agent: Posz Law Group, PLC
20100270631 - Mems microphone: A MEMS microphone (100) is disclosed comprising: a substrate (101), a membrane (102) attached to the substrate (101), and an electrode (104) attached to the substrate (101), wherein the membrane (102) and the electrode (104) have the same resonance frequency.... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100270632 - Resonator and methods of making resonators: A resonator and method of making a resonator are provided. A particular method includes etching a silicon substrate to form a resonator structure. The resonator structure includes at least one resonator beam. The method also includes converting at least a portion of the at least one resonator beam to dry... Agent: Boeing (tlg) C/o Toler Law Group
20100270633 - Nonvolatile memory device: Ferromagnetic layers have magnetizations oriented to such directions as to cancel each other, so that the net magnetization of the ferromagnetic layers is substantially zero. That is, the ferromagnetic layers are exchange-coupled with a nonmagnetic layer interposed therebetween, thereby forming an SAF structure. Since the net magnetization of the ferromagnetic... Agent: Mcdermott Will & Emery LLP
20100270634 - Semiconductor device and manufacturing method thereof: The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment is applied with reducible NH3 or H2 as pretreatment.... Agent: Mcdermott Will & Emery LLP
20100270635 - Semiconductor surface modification: Methods, systems, and devices associated with surface modifying a semiconductor material are taught. One such method includes providing a semiconductor material having a target region and providing a dopant fluid layer that is adjacent to the target region of the semiconductor material, where the dopant fluid layer includes at least... Agent: Thorpe North & Western, LLP.
20100270636 - Isolation structure for backside illuminated image sensor: A backside illuminated image sensor includes an isolation structure passing through a substrate, a sensor element formed overlying the front surface of the substrate, and a color filter formed overlying the back surface of the substrate.... Agent: Lowe Hauptman Ham & Berner, LLP (tsmc)
20100270637 - Solid-state imagining device: A solid-state imaging device includes: an imaging area in which light receiving portions are disposed; an interconnect layer disposed on the light receiving portions, the interconnect layer including metal interconnects having openings and first insulating films; inner-layer lenses formed over the interconnect layer in one-to-one relationship with the light receiving... Agent: Mcdermott Will & Emery LLP
20100270638 - Photodiodes with surface plasmon couplers: A device that includes a signal generating unit having a surface that can receive photons, a first metal structure located on the surface of the signal generating unit, and a second metal structure located on the surface of the signal generating unit. The second metal structure being spaced apart from... Agent: Workman Nydegger 1000 Eagle Gate Tower
20100270639 - Manufacturing method of soi substrate: There is provided a method of manufacturing an SOI substrate which is practicable even when a supporting substrate having a low allowable temperature limit is used. A separation layer is formed in a region at a certain depth from a surface of a semiconductor substrate, and a first heat treatment... Agent: Robinson Intellectual Property Law Office, P.C.
20100270640 - Deformable integrated circuit device: An integrated-circuit device is provided, which comprises a rigid substrate island having a main substrate surface with a circuit region circuit elements and at least one fold structure. The fold structure is attached to the substrate island and is unfoldable from a relaxed, folded state to a strained unfolded state.... Agent: Philips Intellectual Property & Standards
20100270641 - Semiconductor fuse arrangements: The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of electrically conductive links. Each of the links contacts the electrically conductive plate as a separate region relative to the other links, and the region where a link makes contact to... Agent: Wells St. John P.s.
20100270642 - Semiconductor device: A first inductor is connected to a transmission circuit. A second inductor is connected to a reception circuit, and is inductively coupled to the first inductor. At least part of the first inductor is formed with a first bonding wire. The first bonding wire has two ends connected to a... Agent: Mcginn Intellectual Property Law Group, PLLC
20100270647 - Method of fabricating semiconductor device having capacitor: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating... Agent: F. Chau & Associates, LLC
20100270644 - Methods of embedding thin-film capacitors into semiconductor packages using temporary carrier layers: Disclosed are methods of making a semiconductor package comprising at least one thin-film capacitor embedded into at least one build-up layer of said semiconductor package. A thin-film capacitor is provided wherein the thin-film capacitor has a first electrode and a second electrode separated by a dielectric. A temporary carrier layer... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center
20100270643 - Semiconductor device and layout method therefor: Provided is a semiconductor device including: an MIM capacitor that includes a lower electrode, an upper electrode, and a capacitor insulating film formed between the lower electrode and the upper electrode; a first via hole that connects to the lower electrode and extends in a normal upward direction of a... Agent: Mcginn Intellectual Property Law Group, PLLC
20100270648 - Semiconductor integrated circuit, d-a converter device, and a-d converter device: A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and... Agent: Mcdermott Will & Emery LLP
20100270645 - Thin-film capacitor structures embedded in semiconductor packages and methods of making: Provided are semiconductor packages comprising at least one thin-film capacitor attached to a printed wiring board core through build-up layers, wherein a first electrode of the thin-film capacitor comprises a thin nickel foil, a second electrode of the thin-film capacitor comprises a copper electrode, and a copper layer is formed... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center
20100270646 - Thin-film capacitor structures embedded in semiconductor packages and methods of making: Provided are semiconductor packages comprising at least one thin-film capacitor attached to a printed wiring board core through build-up layers, wherein a first electrode of the thin-film capacitor comprises a thin nickel foil, a second electrode comprises a copper electrode, and a copper layer is formed on the nickel foil.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center
20100270649 - Nitride semiconductor wafer: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide... Agent: Drinker Biddle & Reath (dc)
20100270653 - Crystalline thin-film photovoltaic structures and methods for forming the same: Methods for forming semiconductor devices include providing a textured template, forming a buffer layer over the textured template, forming a substrate layer over the buffer layer, removing the textured template, thereby exposing a surface of the buffer layer, removing oxide from the exposed surface of the buffer layer, and forming... Agent: Goodwin Procter LLP Patent Administrator
20100270652 - Double exposure technology using high etching selectivity: Ultrafine patterns with dimensions smaller than the chemical and optical limits of lithography are formed by superimposing two photoresist patterns using a double exposure technique. Embodiments include forming a first resist pattern over a target layer to be patterned, forming a protective cover layer over the first resist pattern, forming... Agent: Volpe And Koenig, P.C. Dept. Amd
20100270651 - Sapphire substrate with periodical structure: A sapphire substrate with periodical structure is disclosed, which comprises: a sapphire substrate, and at least one periodical structure formed on at least one surface of the sapphire substrate and having plural micro-cavities; wherein, the micro-cavities are arranged in an array, the micro-cavities are each in an inverted awl-shape, the... Agent: Bacon & Thomas, PLLC
20100270654 - Semiconductor device and method for manufacturing the same, dry-etching process, method for making electrical connections, and etching apparatus: A method for manufacturing a semiconductor device comprises dry-etching a thin film using a resist mask carrying patterns in which at least one of the width of each pattern and the space between neighboring two patterns ranges from 32 to 130 nm using a halogenated carbon-containing compound gas with the... Agent: Arent Fox LLP
20100270650 - Silicon substrate with periodical structure: A silicon substrate with periodical structure is disclosed, which comprises: a silicon substrate, and at least one periodical structure formed on at least one surface of the silicon substrate and having plural micro-cavities; wherein, the micro-cavities are arranged in an array, the micro-cavities are each in an inverted awl-shape or... Agent: Bacon & Thomas, PLLC
20100270655 - Integrated circuits on a wafer and method for separating integrated circuits on a wafer: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a structure applied on a surface (4) of the wafer substrate (2). The structure forms a plurality of integrated circuits (1) formed on the wafer substrate (2) and the integrated circuits (1) are separated by saw lines (6,... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100270656 - Semiconductor device and method of forming conductive pillars in recessed region of peripheral area around the device for electrical interconnection to other devices: A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A first insulating layer is formed over the die. A recessed region with angled sidewall is formed in the peripheral area. A first conductive layer is formed over the first insulating layer outside... Agent: Robert D. Atkins
20100270657 - Chip-on-board package: Provided is a chip-on-board package. The chip-on-board package may include a board, a grounding pad on a first surface of the board, the grounding pad including a body portion and at least one line portion, and at least two conductive pads on the first surface, the at least two conductive... Agent: Harness, Dickey & Pierce, P.L.C
20100270658 - Semiconductor device and method for producing same: A method is disclosed for producing a semiconductor device produced by (i) doping hydrogen ions or rare gas ions into a device substrate in which a transfer layer (16) is formed, (ii) then bonding the device substrate to a carrier target substrate, and (iii) transferring the transfer layer (16) onto... Agent: Birch Stewart Kolasch & Birch
20100270659 - Semiconductor device, method of manufacturing the same, and silane coupling agent: A semiconductor chip has devices formed on a first principal plane of a semiconductor substrate, wherein a second principal plane of the semiconductor substrate is planarized, and an organic film having plus charges on an outer side is provided on the second principal plane.... Agent: Posz Law Group, PLC
20100270660 - Semiconductor device and method for manufacturing metallic shielding plate: Provided is a semiconductor device capable of preventing a semiconductor chip from being damaged by any sharp burrs of a metallic shielding plate. The semiconductor device includes a semiconductor chip and a metallic shielding plate provided on a circuit surface of the semiconductor chip. The metallic shielding plate is disposed... Agent: Burr & Brown
20100270661 - Semiconductor device having electrical devices mounted to ipd structure and method of shielding electromagnetic interference: A semiconductor device has an IPD structure formed over a substrate. First and second electrical devices are mounted to a first surface of the IPD structure. An encapsulant is deposited over the first and second electrical devices and IPD structure. A shielding layer is formed over the encapsulant and electrically... Agent: Robert D. Atkins
20100270662 - Polysilicon drift fuse: A polysilicon resistor fuse has an elongated bow-tie body that is wider at the opposite ends relative to a narrow central portion. The opposite ends of the body of the fuse have high concentrations of N-type dopants to make them low resistance contacts. The upper portion of the central body... Agent: Hiscock & Barclay, LLP
20100270664 - Epoxy resin composition for encapsulating semiconductor device and semiconductor device using the same: An epoxy resin composition for encapsulating a semiconductor device, the epoxy resin composition including an epoxy resin, a curing agent, and one or more inorganic fillers, the one or more inorganic fillers including prismatic cristobalite, the prismatic cristobalite being present in the epoxy resin composition in an amount of about... Agent: Lee & Morse, P.C.
20100270663 - Power lead-on-chip ball grid array package: A packaging assembly (30), such as a ball grid array package, is formed which distributes power across an interior region of an integrated circuit die (52) by using an encapsulated patterned leadframe conductor (59) that is disposed over the die (52) and bonded to a plurality of bonding pads (45)... Agent: Freescale Semiconductor, Inc. Law Department
20100270665 - Leadframe: A leadframe includes a die paddle and leads, in which the back side of the die paddle has a fillister. The fillister defines a rim surrounding a recess, and the recess accommodates protrusion of fusible material. Also, a package includes such a leadframe. Also, a method for making a leadframe... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100270666 - Semiconductor device and method of manufacturing semiconductor device: The semiconductor device according to the present invention includes a semiconductor chip, a solid plate to which the semiconductor chip is bonded, and a bonding member made of a BiSn-based material interposed between the semiconductor chip and the solid plate, while the bonding member has a heat conduction path made... Agent: Rabin & Berdo, PC
20100270667 - Semiconductor package with multiple chips and substrate in metal cap: A semiconductor package includes a first semiconductor chip, a second semiconductor chip, a first substrate, a second substrate and a metal cap. The chips are electrically connected to the first substrate, the second substrate is disposed between the chips, and the chips and the second substrate are disposed within the... Agent: Dicke, Billig & Czaja
20100270668 - Dual interconnection in stacked memory and controller module: A chip package transmitting slow speed signals via edge connectors and high speed signals by means of through-silicon-vias. The edge connectors are formed in recesses formed in the sidewalls of the package.... Agent: The Tpl Group C/o Alliacense Limited LLC
20100270669 - Surface mount package with ceramic sidewalls: A package for use in encapsulating an electronic device is disclosed. The package includes a dielectric frame having first and second sides with a pair of apertures extending through the dielectric frame. These apertures are separated by a raised shelf span extending inwardly from an internal perimeter of the dielectric... Agent: Wiggin And Dana LLP Attention: Patent Docketing
20100270670 - Integrated circuit packaging system and method of manufacture thereof: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit substrate having a non-active side and an active side; forming a recess in the integrated circuit substrate from the non-active side exposing a first contact and a second contact with the first contact and the... Agent: Law Offices Of Mikio Ishimaru
20100270671 - Manipulating fill patterns during routing: A CAD tool that supports an overlay-enabling operating mode. After the overlay-enabling operating mode is entered, the layout-editing facility permits modifications to the interconnect structure of an integrated circuit that is being designed regardless of whether a particular modification interferes with an existing pattern of metal fill. For example, a... Agent: Mendelsohn, Drucker, & Associates, P.C.
20100270672 - Semiconductor device: A semiconductor device includes a conductive section formed on a semiconductor chip; and a bump electrode formed directly or indirectly on the conductive section. The conductive section includes a slit section having a thickness thinner than another portion of the conductive section. The bump electrode has a recessed section corresponds... Agent: Mcginn Intellectual Property Law Group, PLLC
20100270673 - Method for connecting two joining surfaces: The invention relates to a method for connecting two joining surfaces, particularly in the field of semiconductors, wherein at least one joining surface is produced by depositing a layer comprising 20 to 40% gold and 80 to 60% silver onto a substrate and selectively removing the silver from the deposited... Agent: Altera Law Group, LLC
20100270674 - High quality electrical contacts between integrated circuit chips: Methods and structures of connecting at least two integrated circuits in a 3D arrangement by a zigzag conductive chain are disclosed. The zigzag conductive chain, acting as a spring or self-adaptive contact structure (SACS) in a wafer bonding process, is designed to reduce bonding interface stress, to increase bonding interface... Agent: Huilong Zhu
20100270675 - Semiconductor device having damascene interconnection structure that prevents void formation between interconnections having transparent dielectric substrate: A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which includes a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the first conductive layer and the first barrier layer.... Agent: Volentine & Whitt PLLC
20100270676 - Adaptive interconnect structure: An array of contact pads on a semiconductor structure has a pitch less than twice an overlay tolerance of a bonding process employed to vertically stack semiconductor structures. A set of contact pads within the area of overlay variation for a matching contact pin may be electrically connected to an... Agent: Scully, Scott, Murphy & Presser, P.C.
20100270680 - Integrated circuit package system with offset stacking and anti-flash structure: An integrated circuit package system includes: a carrier; a device structure in an offset location over the carrier with the device structure having a bond pad and a contact pad; an electrical interconnect between the bond pad and the carrier; an anti-flash structure over the device structure with the anti-flash... Agent: Law Offices Of Mikio Ishimaru
20100270679 - Microelectronic packages fabricated at the wafer level and methods therefor: A method of making microelectronic packages includes making a subassembly by providing a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces, attaching a compliant layer to the top surface of the plate, the compliant layer having openings that are aligned with... Agent: Tessera Lerner David Et Al.
20100270681 - Optimizing application specific integrated circuit pinouts for high density interconnect printed circuit boards: Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer... Agent: Patterson & Sheridan, LLP/cisc
20100270678 - Semiconductor device: A semiconductor device including a plurality of circuits that includes a transistor, where a semiconductor layer forming the transistor includes a first contact pad, a first part that is connected to the first contact pad and that extends in a direction intersecting a short direction of a pitch with which... Agent: Canon U.s.a. Inc. Intellectual Property Division
20100270677 - Semiconductor device and method of manufacturing semiconductor device: An interconnect is provided in a first insulating layer and the upper surface of the interconnect is higher than the upper surface of the first insulating layer. An air gap is disposed between the interconnect and the first insulating layer. A second insulating layer is formed at least over the... Agent: Mcginn Intellectual Property Law Group, PLLC
20100270684 - Chip identification using top metal layer: An integrated circuit (IC) structure includes a semiconductor substrate having a plurality of memory bits including IC identification information and a plurality of alternating metal and via layers thereabove. The IC structure includes a bond pad layer formed over a top one of the metal layers. The bond pad layer... Agent: Mendelsohn, Drucker, & Associates, P.C.
20100270685 - Die bonding utilizing a patterned adhesion layer: An electronic package and method and system for forming the electronic package. The electronic package has a first substrate including a first electronic device and including through-holes extending through an entire thickness of the first substrate. The electronic package has a second substrate bonded to the first substrate, metallizations formed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100270682 - Implementing vertical airgap structures between chip metal layers: A method and structure are provided for implementing vertical airgap structures between chip metal layers. A first metal layer is formed. A first layer of silicon dioxide dielectric is deposited onto the first metal layer. A vertical air gap is etched from the first layer of silicon dioxide dielectric above... Agent: Ibm Corporation RochesterIPLaw Dept 917
20100270686 - Semiconductor device: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring... Agent: Rabin & Berdo, PC
20100270683 - Semiconductor device and method of manufacturing semiconductor device: An interconnect is provided in a first insulating layer and the upper surface of the interconnect is higher than the upper surface of the first insulating layer. An air gap is disposed between the interconnect and the first insulating layer. An etching stopper film is formed over the first insulating... Agent: Mcginn Intellectual Property Law Group, PLLC
20100270687 - Semiconductor device and manufacturing method of the same: One aspect of the present invention is a semiconductor device including: a semiconductor substrate; a first wiring that is formed on the semiconductor substrate; a second wiring that is formed to cross over the first wiring with a space interposed therebetween at a cross portion in which the first wiring... Agent: Young & Thompson
20100270688 - Multi-chip stacked package: A multi-chip stacked package primarily comprises a chip carrier, a first chip disposed on the chip carrier, a plurality of die-attaching bars, a second chip stacked on the first chip by the adhesion of the die-attaching bars, and a plurality of bonding wires electrically connecting the first chip to the... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20100270689 - Semiconductor packages and electronic systems including the same: Provided are semiconductor packages and electronic systems including the same. A substrate is provided. A plurality of semiconductor chips may be stacked the substrate, and each of them may include at least one electrode pad. At least one of the plurality of semiconductor chips may include at least one redistribution... Agent: Harness, Dickey & Pierce, P.L.C10/21/2010 > patent applications in patent subcategories. categorized by USPTO classification
20100264391 - Epi substrate with low doped epi layer and high doped si substrate layer for media growth on epi and low contact resistance to back-side substrate: The fabrication of seek-scan probe (SSP) memory devices involves processing on both-sides of a wafer. However, there are temperature restrictions on the mover circuitry side of the wafer and doping level constrains for either side of wafer. Using a low doped EPI layer on a highly doped substrate solves this... Agent: Intel Corporation C/o Cpa Global
20100264392 - Nonvolatile memory apparatus and manufacturing method thereof: A nonvolatile memory device includes via holes (12) formed at cross sections where first wires (11) cross second wires (14), respectively, and current control elements (13) each including a current control layer (13b), a first electrode layer (13a) and a second electrode layer (13c) such that the current control layer... Agent: Mcdermott Will & Emery LLP
20100264393 - Nonvolatile memory device and manufacturing method thereof: A nonvolatile memory device of the present invention comprises a substrate (1), first wires (3), first filling constituents (5) filled into first through-holes (4), respectively, second wires (11) which cross the first wires (3) perpendicularly to the first wires (3), respectively, each of the second wires (11) including a plurality... Agent: Mcdermott Will & Emery LLP
20100264395 - Phase change memory structures and methods: Methods, devices, and systems associated with phase change memory structures are described herein. One or more embodiments of the present disclosure can reduce thermal crosstalk associated with phase change memory cells, which can provide various benefits including improved data reliability and retention and decreased read and/or write times, among various... Agent: Brooks, Cameron & Huebsch , PLLC
20100264394 - Semiconductor memory and method of manufacturing the same: Disclosed herein is a semiconductor memory including: a first MOS transistor having two diffusion layers formed in a semiconductor substrate; a second MOS transistor which is formed in the semiconductor substrate and has one of the two diffusion layers of the first MOS transistor as a common diffusion layer for... Agent: Sonnenschein Nath & Rosenthal LLP
20100264396 - Ring-shaped electrode and manufacturing method for same: An electrode structure and a method for manufacturing an integrated circuit electrode includes forming a bottom electrode comprising a pipe-shaped member, filled with a conductive material such as n-doped silicon, and having a ring-shaped top surface. A disc-shaped insulating member is formed on the top of the pipe-shaped member by... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100264398 - Chemical vapor deposition method for the incorporation of nitrogen into materials including germanium and antimony: A chemical vapor deposition (CVD) method for depositing materials including germanium (Ge), antimony (Sb) and nitrogen (N) which, in some embodiments, has the ability to fill high aspect ratio openings is provided. The CVD method of the instant invention permits for the control of nitrogen-doped GeSb stoichiometry over a wide... Agent: Scully, Scott, Murphy & Presser, P.C.
20100264397 - Memristive device with a bi-metallic electrode: A memristive device having a bimetallic electrode includes a memristive matrix, a first electrode and a second electrode. The first electrode is in electrical contact with the memristive matrix and the second electrode is in electrical contact with the memristive matrix and an underlying layer. At least one of the... Agent: Hewlett-packard Company Intellectual Property Administration
20100264399 - Method of fabricating nanosized filamentary carbon devices over a relatively large-area: Nanosized filamentary carbon structures (CNTs) nucleating over a catalyzed surface may be grown in an up-right direction reaching a second surface, spaced from the first surface, without the need of applying any external voltage source bias. The growth process may be inherently self-stopping, upon reaching a significant population of grown... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.
20100264401 - Micro-pixel ultraviolet light emitting diode: An ultra-violet light-emitting diode (LED) array, 12, and method for fabricating same with an AlInGaN multiple-quantum-well active region, 500, exhibiting stable cw-powers. The LED includes a template, 10, with an ultraviolet light-emitting array structure on it. The template includes a first buffer layer, 321, then a second buffer layer, 421,... Agent: Nexsen Pruet, LLC
20100264400 - White light emitting device: A light emitting device (LED) may include a first semiconductor layer; an active layer formed on the first semiconductor layer and configured to generate first light having a first wavelength; a second semiconductor layer, formed on the active layer; and a plurality of semiconductor nano-structures arranged apart from each other... Agent: Harness, Dickey & Pierce, P.L.C
20100264402 - Use of sack geometry to implement a single qubit phase gate: An implementation of a single qubit phase gate for use in a quantum information processing scheme based on the υ=5/2 fractional quantum Hall (FQH) state is disclosed. Using sack geometry, a qubit consisting of two σ-quasiparticles. which may be isolated on respective antidots, may be separated by a constriction from... Agent: Woodcock Washburn LLP (microsoft Corporation)
20100264403 - Nanorod thin-film transitors: A method for forming an electronic switching device on a substrate, wherein the method comprises depositing the active semiconducting layer of the electronic switching device onto the substrate from a liquid dispersion of ligand-modified colloidal nanorods, and subsequently immersing the substrate into a growth solution to increase the diameter and/or... Agent: Fish & Richardson PC
20100264406 - Light emitting device material and light emitting device: A light emitting device material containing a pyrromethene compound represented by the general formula (1). It realized a luminescent element having a high luminescent efficiency and excellent color purity. Also provided is a luminescent element employing the materials.... Agent: Ratnerprestia
20100264409 - Molecular device, imaging device, photosensor, and electronic apparatus: A molecular device includes a gold electrode, cytochrome c552 or a derivative or variant thereof immobilized on the gold electrode, and an electron transfer protein coupled to the cytochrome c552 or the derivative or variant thereof. Electrons or holes, or both, are transferred through the electron transfer protein by transition... Agent: K&l Gates LLP
20100264407 - Organic el device: The organic EL device of the present invention includes an anode, a cathode (e.g., an Al layer (15)), and an organic layer 20 that is disposed between the anode and the cathode and that includes a light emitting layer 14. At least one side of the anode nearer to the... Agent: Hamre, Schumann, Mueller & Larson, P.C.
20100264404 - Organic electronic device, method for production thereof, and organic semiconductor molecule: An organic electronic device which has stable physical properties and which allows easy production is provided. The organic electronic device has a conductive path including fine particles, a first organic semiconductor molecule which has a first conductive type and binds at least two of the fine particles together, and a... Agent: K&l Gates LLP
20100264408 - Organic thin film transistors, active matrix organic optical devices and methods of making the same: A method of manufacturing an organic thin film transistor, comprising: providing a substrate comprising source and drain electrodes defining a channel region; forming a patterned layer of insulting material defining a well surrounding the channel region; depositing a protective layer in the well; subjecting exposed portions of the patterned layer... Agent: Marshall, Gerstein & Borun LLP
20100264410 - Thin film transistor and method for manufacturing thin film transistor: A method for manufacturing a thin film transistor includes the steps of covering a gate electrode patterned on a substrate with a gate insulating film, forming an organic semiconductor layer and an electrode film on the gate insulating film in that lamination order, and forming a negative type photoresist film... Agent: Sonnenschein Nath & Rosenthal LLP
20100264405 - Transition metal complexes with bridged carbene ligands and use thereof in oleds: Bridged cyclometalated carbene complexes, a process for preparing the bridged cyclometalated carbene complexes, the use of the bridged cyclometalated carbene complexes in organic light-emitting diodes, organic light-emitting diodes comprising at least one inventive bridged cyclometalated carbene complex, a light-emitting layer comprising at least one inventive bridged cyclometalated carbene complex, organic... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100264411 - Oxide semiconductor light emitting device: There is provided a ZnO based compound semiconductor light emitting device which can emit light with high efficiency and from an entire surface while using ZnO based compound semiconductor which can be expected with higher light emitting efficiency than that of a GaN based compound. On an insulating substrate (1),... Agent: Rabin & Berdo, PC
20100264412 - Semiconductor device and manufacturing method thereof: An object is to provide a transistor including an oxide layer which includes Zn and does not include a rare metal such as In or Ga. Another object is to reduce an off current and stabilize electric characteristics in the transistor including an oxide layer which includes Zn. A transistor... Agent: Robinson Intellectual Property Law Office, P.C.
20100264413 - Replacement of scribeline padframe with saw-friendly design: An integrated circuit substrate containing an electrical probe pad structure over, and on both sides of, a dicing kerf lane. The electrical probe pad structure includes metal crack arresting strips adjacent to the dicing kerf lane. A metal density between the crack arresting strips is less than 70 percent. An... Agent: Texas Instruments Incorporated
20100264414 - Semiconductor integrated circuit device and method of manufacturing same: In the current manufacturing process of LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by the voltage-application test (high-temperature and high-humidity test) in an environment of high temperature (such as an approximate range from 85 to 130° C.) and... Agent: Miles & Stockbridge PC
20100264415 - Interconnecting structure production method, and interconnecting structure: An interconnecting structure production method includes providing a substrate, forming a semiconductor layer on the substrate, forming a doped semiconductor layer on the semiconductor layer, the doped semiconductor layer containing a dopant, forming an oxide layer in a surface of the doped semiconductor layer by heating the surface of the... Agent: Scully Scott Murphy & Presser, PC
20100264416 - Semiconductor device and production method thereof: Provided is a crystalline silicon thin film semiconductor device which is capable of reducing off-state leakage current and has excellent current rising characteristics. The thin film transistor includes a semiconductor layer formed of an amorphous silicon layer and a crystalline silicon layer. A drain electrode is provided in direct contact... Agent: Fitzpatrick Cella Harper & Scinto
20100264418 - Control substrate and control substrate manufacturing method: the base layer is formed of a member whose adhesiveness to the electrode is higher than the adhesiveness of the substrate main body to an electrode when forming the electrode on a base layer side surface of the substrate main body by an application method.... Agent: Sughrue Mion, PLLC
20100264419 - Field-effect transistor: A field-effect transistor includes at least a channel layer, a gate insulating layer, a source electrode, a drain electrode, and a gate electrode, which are formed on a substrate. The channel layer is made of an amorphous oxide material that contains at least In and B, and the amorphous oxide... Agent: Fitzpatrick Cella Harper & Scinto
20100264417 - Thin-film treansistor array panel and method of fabricating the same: A thin-film transistor array panel and a manufacturing method thereof are provided for one or more embodiments. The thin-film transistor array panel may include: a substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate electrode; a source electrode and a drain electrode formed... Agent: Innovation Counsel LLP
20100264420 - Semiconductor device and manufacturing method thereof: An object is to obtain a semiconductor device with improved characteristics by reducing contact resistance of a semiconductor film with electrodes or wirings, and improving coverage of the semiconductor film and the electrodes or wirings. The present invention relates to a semiconductor device including a gate electrode over a substrate,... Agent: Husch Blackwell Sanders, LLP Husch Blackwell Sanders LLP Welsh & Katz
20100264421 - Semiconductor device and fabrication method thereof: This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719... Agent: Robinson Intellectual Property Law Office, P.C.
20100264422 - Thin film semiconductor device, display device using such thin film semiconductor device and manufacturing method thereof: A thin film semiconductor device formed as integrated circuits on an insulating substrate with bottom gate type thin film transistors stacked with gate electrodes, a gate insulating film and a semiconductor thin film in the order from below upward. The gate electrodes comprise metallic materials with thickness less than 100... Agent: Rader Fishman & Grauer PLLC
20100264423 - Thinned semiconductor components having lasered features and methods for fabricating semiconductor components using back side laser processing: A method for fabricating semiconductor components includes the steps of providing a semiconductor substrate having a circuit side, a back side and integrated circuits and circuitry on the circuit side; thinning the substrate from the back side to a selected thickness; laser processing the back side of the thinned substrate... Agent: Stephen A. Gratton Law Office Of Steve Gratton
20100264424 - Gan layer containing multilayer substrate, process for producing same, and device: A GaN layer-containing multilayer substrate employing as a substrate a single crystal that can be made to have a large diameter, a process for producing same, and a device employing the multilayer substrate. The process for producing a multilayer substrate of the present invention includes a germanium growing step of... Agent: Kratz, Quintos & Hanson, LLP
20100264425 - Transistors for replacing metal-oxide-semiconductor field-effect transistors in nanoelectronics: Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET)... Agent: Dr. William T. Ralston
20100264427 - Bipolar junction transistor guard ring structures and method of fabricating thereof: Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including... Agent: Andrews Kurth LLP
20100264426 - Diamond capacitor battery: In one embodiment, a charge storage device can include: a first node having a plurality of n-type diamond layers connected together; and a second node having a plurality of p-type diamond layers connected together, the plurality of p-type diamond layers being interleaved with the plurality of n-type diamond layers, where... Agent: Trellis Intellectual Property Law Group, PC
20100264428 - Silicon biosensor and method of manufacturing the same: A silicon biosensor and a method of manufacturing the same are provided. The silicon biosensor includes: a light emitting layer emitting light according to injected electrons and holes and changing a wavelength of the light depending on whether a biomaterial is absorbed by the light emitting layer; an electron injection... Agent: Ladas & Parry LLP
20100264429 - Light emitting device and electronic device using the same: A light emitting device and an electronic device using the same are provided. The light emitting device includes a light emitting chip having a wavelength between 460 nm and 650 nm and phosphor powders, in which the phosphor powders can be stimulated by light emitted from the chip to emit... Agent: Quintero Law Office, PC
20100264430 - Organic light emitting device: Provided is an organic light emitting device having a simple structure and enabling cost reduction. An organic light emitting device 30 of the present invention includes: an organic light emitting element 20; an electrode substrate (11, 12) including a pin connection hole (14, 15) with which the organic light emitting... Agent: Rabin & Berdo, PC
20100264432 - Light emitting device with high color rendering index and high luminescence efficiency: A light emitting device comprises two light-emitting diode (LED) groups, a group of luminophor layers, and an input terminal. The first LED group includes at least one blue LED emitting light having a dominant wavelength in a range between 400 nm and 480 nm, and the second LED group includes... Agent: Martine Penilla & Gencarella, LLP
20100264433 - System for displaying images: A system for displaying images is provided. The system includes a tandem electroluminescent device having a first electrode. N electroluminescent units are disposed on the first electrode in sequence, wherein N is an integral and not less than 2. A second electrode is disposed on the Nth electroluminescent unit. N-1interconnecting... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100264431 - Yellow light emitting diode and light emitting device having the same: An exemplary yellow light emitting diode (LED) includes a substrate, a LED die, a phosphor layer and an encapsulant. The LED die is arranged on the substrate and comprises an indium gallium aluminum nitride represented by the formula InxGayAlzN, wherein x+y+z=1, 0≦x≦1, 0≦y≦1 and 0≦z≦1. The phosphor layer is a... Agent: Altis Law Group, Inc. Attn: Steven Reiss
20100264444 - Led and method of manufacturing the same: An LED can include a pair of electrode members, and an LED chip joined to a chip mount portion disposed at the extremity of one of the pair of electrode members. The LED chip can be electrically connected to the pair of electrode members. A transparent resin portion can include... Agent: Kenealy Vaidya LLP
20100264439 - Led package structure: A light emitting diode (LED) package structure includes a substrate having a chip disposal area and a recession, a chip installed in the chip disposal area, a silicon connecting element installed at the recession, and a silicon lens disposed at a position corresponding to the recession and coupled to the... Agent: Rosenberg, Klein & Lee
20100264449 - Light emitting apparatus: A light emitting apparatus includes a light emitting device mounted on a base. First and second leads are electrically connected to the light emitting device. A first resin molding member formed of thermosetting resin covers at least partially the base and the first and second leads so that the first... Agent: Ditthavong Mori & Steiner, P.C.
20100264438 - Light emitting device: The light emitting device has a light emitting element 101, and translucent material 102 that passes incident light from the light emitting element 101 and emits that light to the outside. The sides of the translucent material 102 perimeter are inclined surfaces 107 that become wider from the upper surface... Agent: Foley And Lardner LLP Suite 500
20100264442 - Light emitting device and method of manufacturing the same: Provided are a vertical-type light emitting device and a method of manufacturing the same. The light emitting device includes a p-type semiconductor layer, an active layer, and an n-type semi-conductor layer that are stacked, a cover layer disposed on a p-type electrode layer to surround the p-type electrode layer, a... Agent: H.c. Park & Associates, PLC
20100264441 - Light emitting element and fabricating method thereof: The light emitting element includes a substrate; a first block pattern formed on the substrate; a light emitter including a first semiconductor pattern of a first conductivity type, a light emitting pattern, and a second semiconductor pattern of a second conductivity type, sequentially stacked on the substrate having the first... Agent: Harness, Dickey & Pierce, P.L.C
20100264448 - Light emtting device: Disclosed herein is a light emitting device. The light emitting device includes a light emitting diode disposed on a substrate to emit light of a first wavelength. A transparent molding part encloses the LED, a lower wavelength conversion material layer is disposed on the transparent molding part, and an upper... Agent: H.c. Park & Associates, PLC
20100264434 - Optoelectronic semiconductor chip: An optoelectronic semiconductor chip is disclosed which emits electromagnetic radiation from its front side (7) during operation, comprising a semiconductor layer sequence (1) having an active region (4) suitable for generating the electromagnetic radiation, and a separately produced TCO supporting substrate (10), which is arranged at the semiconductor layer sequence... Agent: Cohen, Pontani, Lieberman & Pavane LLP
20100264436 - Plcc package with a reflector cup surrounded by a single encapsulant: In an embodiment the invention provides a LFCC package comprising first, second and third lead frames, a light source, and an encapsulant. The first lead frame comprises two tongues and a reflector cup. The first, second and third lead frames are attached to the encapsulant. The light source is mounted... Agent: Kathy Manke Avago Technologies Limited
20100264437 - Plcc package with a reflector cup surrounded by an encapsulant: In an embodiment, the invention provides a PLCC package comprising first and second lead frames, a plastic structural body, a light source, an encapsulant, and an optical lens. The first lead frame comprises two tongues and a reflector cup. The first and second lead frames are attached to the plastic... Agent: Kathy Manke Avago Technologies Limited
20100264440 - Semiconductor light emitting device: Disclosed are a semiconductor light emitting device. The semiconductor light emitting device comprises a light emitting structure comprising a IH-V group compound semiconductor, a reflective layer comprising mediums, which are different from each other and alternately stacked under the light emitting structure, and a second electrode layer under the reflective... Agent: Birch Stewart Kolasch & Birch
20100264445 - Semiconductor light emitting device: A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of... Agent: Morrison & Foerster LLP
20100264446 - Semiconductor light emitting device: A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of... Agent: Morrison & Foerster LLP
20100264447 - Semiconductor light emitting device: A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of... Agent: Morrison & Foerster LLP
20100264443 - Semiconductor light emitting device and method for manufacturing the same: A semiconductor light emitting device having high reliability and excellent light distribution characteristics is provided. Specifically, a semiconductor light emitting device 1 is provided with an n-electrode 50, which is arranged on a light extraction surface on the side opposite to the surface whereupon a semiconductor stack 40 is mounted... Agent: Squire, Sanders & Dempsey L.L.P.
20100264435 - White light-emitting diode package structure for simplifying package process and method for making the same: A white light-emitting diode package structure for simplifying package process includes a substrate unit, a light-emitting unit, a phosphor unit and a conductive unit. The light-emitting unit is disposed on the substrate, and the light-emitting unit has a positive conductive layer and a negative conductive layer. The phosphor unit has... Agent: Rosenberg, Klein & Lee
20100264451 - Light emitting diode with high power: A light emitting diode includes a base, a dispersing member, a chip, a pole, a cover, an electrode, and a lens. The base is capable of conducting heat and insulated from electricity. The base has a first surface and a second surface opposite to the first surface. The dispersing member... Agent: Morris Manning Martin LLP
20100264450 - Light source: Embodiments of a light source are disclosed herein. An embodiment of the light source comprises a first terminal and a second terminal. The first terminal comprises a first terminal first portion and a first terminal second portion, wherein at least a portion of the first terminal second portion is located... Agent: Kathy Manke Avago Technologies Limited
20100264452 - Methods for high temperature processing of epitaxial chips: High temperature semiconducting materials in a freestanding epitaxial chip enables the use of high temperature interconnect and bonding materials. Process materials can be used which cure, fire, braze, or melt at temperatures greater than 400 degrees C. These include, but are not limited to, brazing alloys, laser welding, high-temperature ceramics... Agent: Goldeneye, Inc.
20100264453 - Semiconductor chip pad structure and method for manufacturing the same: A semiconductor chip pad structure and a method for manufacturing the same, wherein a flat area at the center of the terminal pad and a roughened area at the periphery thereof are provided by use of the mask photolithograph technique and the roughening process. The central area provides a sufficient... Agent: Rosenberg, Klein & Lee
20100264454 - Semiconductor light emitting device growing active layer on textured surface: In accordance with embodiments of the invention, at least partial strain relief in a light emitting layer of a III-nitride light emitting device is provided by configuring the surface on which at least one layer of the device grows such that the layer expands laterally and thus at least partially... Agent: Philips Intellectual Property & Standards
20100264456 - Capacitor structure in trench structures of semiconductor devices and semiconductor devices comprising capacitor structures of this type and methods for fabricating the same: A capacitor structure in trench structures of a semiconductor device includes conductive regions made of metallic and/or semiconducting materials. The conducting regions are surrounded by a dielectric and form stacked layers in the trench structure of the semiconductor device.... Agent: Edell , Shapiro & Finnan , LLC
20100264455 - Semiconductor device: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a... Agent: Rossi, Kimms & Mcdowell LLP.
20100264457 - Electrostatic discharge protection: An electrostatic discharge (ESD) protection circuit for protecting an integrated circuit (IC) having a first voltage potential, a first power supply potential and a second power supply potential. The ESD circuit includes a first NPN bipolar transistor having a first N-doped junction, a second N-doped junction and a third P-doped... Agent: Volpe And Koenig, P.C.
20100264458 - Method for manufacturing heterostructures: A method for manufacturing heterostructures for applications in the fields of electronics, optics or opto-electronics. This method includes providing a silicon oxide layer with a thickness of less than or equal to 25 nanometers on one of a donor substrate or a receiver substrate or on both substrates, heat treating... Agent: Winston & Strawn LLP Patent Department
20100264459 - Infrared sensor ic, and infrared sensor and manufacturing method thereof: An infrared sensor IC and an infrared sensor, which are extremely small and are not easily affected by electromagnetic noise and thermal fluctuation, and a manufacturing method thereof are provided. A compound semiconductor that has a small device resistance and a large electron mobility is used for a sensor (2),... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100264460 - Thick pseudomorphic nitride epitaxial layers: In various embodiments, a semiconductor device includes an aluminum nitride single-crystal substrate, a pseudomorphic strained layer disposed thereover that comprises at least one of AlN, GaN, InN, or an alloy thereof, and, disposed over the strained layer, a semiconductor layer that is lattice-mismatched to the substrate and substantially relaxed.... Agent: Goodwin Procter LLP Patent Administrator
20100264461 - N-polar aluminum gallium nitride/gallium nitride enhancement-mode field effect transistor: A novel enhancement mode field effect transistor (FET), such as a High Electron Mobility Transistors (HEMT), has an N-polar surface uses polarization fields to reduce the electron population under the gate in the N-polar orientation, has improved dispersion suppression, and low gate leakage.... Agent: Gates & Cooper LLP Howard Hughes Center
20100264462 - Semiconductor including lateral hemt: A semiconductor including a lateral HEMT and to a method for production of a lateral HEMT is disclosed. In one embodiment, the lateral HEMT has a substrate and a first layer, wherein the first layer has a semiconductor material of a first conduction type and is arranged at least partially... Agent: Dicke, Billig & Czaja
20100264463 - Semiconductor heterostructure and method for forming same: The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2 and providing a top layer over the buffer layer. In order to improve the surface roughness of... Agent: Winston & Strawn LLP Patent Department
20100264464 - Image sensor photodiode arrangement: The present invention relates to a technology for reducing dark current noise by discharging electrons accumulated on a surface of an image sensor photodiode. In an N-type or P-type photodiode, a channel is formed between the photodiode and a power voltage terminal, so that electrons (or holes) accumulated on a... Agent: Jae Y. Park
20100264465 - Sram cell with different crystal orientation than associated logic: An integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in semiconductor material with one crystal orientation and the SRAM cells are formed in a second semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic... Agent: Texas Instruments Incorporated
20100264466 - Gate self-aligned low noise jfet: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating... Agent: Texas Instruments Incorporated
20100264467 - Transistor component having a shielding structure: A transistor component having a shielding structure. One embodiment provides a source terminal, a drain terminal and control terminal. A source zone of a first conductivity type is connected to the source terminal. A drain zone of the first conductivity type is connected to the drain terminal. A drift zone... Agent: Dicke, Billig & Czaja
20100264471 - Enhancing mosfet performance with stressed wedges: The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located above the gate structure or at or near the source and drain regions. Specifically, a dielectric layer in on the MOSFET and at least one stress-inducing wedge is pressed into the dielectric layer to... Agent: Huilong Zhu
20100264468 - Method of fabrication of a finfet element: The present disclosure provides a FinFET element and method of fabricating a FinFET element. The FinFET element includes a germanium-FinFET element (e.g., a multi-gate device including a Ge-fin). In one embodiment, the method of fabrication the Ge-FinFET element includes forming silicon fins on a substrate and selectively growing an epitaxial... Agent: Haynes And Boone, LLPIPSection
20100264469 - Mosfet including epitaxial halo region: A metal oxide semiconductor field effect transistor structure and a method for fabricating the metal oxide semiconductor field effect transistor structure provide for a halo region that is physically separated from a gate dielectric. The structure and the method also provide for a halo region aperture formed horizontally and crystallographically... Agent: Scully, Scott, Murphy & Presser, P.C.
20100264470 - Nmos transistor devices and methods for fabricating same: NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include providing a substrate having a p-type silicon region and a gate stack disposed thereon, the gate stack partially defining... Agent: MoserIPLaw Group / Applied Materials, Inc.
20100264472 - Patterning method, and field effect transistors: A patterning method with a filling material with a T-shaped cross section is used as a mask during patterning to produce structures having sublithographic dimensions, such as a double-fin field effect transistor.... Agent: Brinks Hofer Gilson & Lione/infineon Infineon
20100264473 - Anti-reflection structures for cmos image sensors: Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light... Agent: Scully, Scott, Murphy & Presser, P.C.
20100264474 - Solid-state image pickup device, electronic apparatus using such solid-state image pickup device and method of manufacturing solid-state image pickup device: A back-illuminated type solid-state image pickup device (1041) includes read circuits (Tr1, Tr2) formed on one surface of a semiconductor substrate (1042) to read a signal from a photo-electric conversion element (PD) formed on the semiconductor substrate (1042), in which electric charges (e) generated in a photo-electric conversion region (1052c1)... Agent: Robert J. Depke Lewis T. Steadman
20100264476 - Ferroelectric memory and its manufacturing method: To securely prevent hydrogen from entering a ferroelectric layer of a ferroelectric memory. A first hydrogen barrier layer 5 is formed on the lower side of ferroelectric capacitors 7. Upper surfaces and side surfaces of the ferroelectric capacitors 7 are covered by a second hydrogen barrier layer. All upper electrodes... Agent: Oliff & Berridge, PLC
20100264475 - Magnetic tunnel junction transistor: A magnetic tunnel junction transistor and method of operating the same. In a particular embodiment, the magnetic tunnel junction transistor includes electrically conductive source, drain and gate electrodes. An electrically insulating material having a non-magnetoelectric region and a magnetoelectric region is positioned such that the non-magnetoelectric region is, at least... Agent: Law Office Of Ido Tuchman (yor)
20100264477 - Semiconductor devices: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment includes providing a workpiece having a first orientation and at least one second orientation. The semiconductor device is implanted with a dopant species using a first implantation process in the first orientation of the workpiece. The semiconductor device... Agent: Slater & Matsil, L.L.P.
20100264478 - Method to reduce trench capacitor leakage for random access memory device: A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a... Agent: Hitt Gaines, PC Lsi Corporation
20100264482 - Memory cells configured to allow for erasure by enhanced f-n tunneling of holes from a control gate to a charge trapping material: Memory cells including a control gate, a charge trapping material, and a charge blocking material between the control gate and the charge trapping material. The charge blocking material is configured to allow for erasure of the memory cell by enhanced F-N tunneling of holes from the control gate to the... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth
20100264481 - Nonvolatile memory devices and related methods: Nonvolatile memory devices and methods of fabricating the same are provided. A semiconductor substrate is provided having a cell field region and a high-voltage field region. Device isolation films are provided on the substrate. The device isolation films define active regions of the substrate. A cell gate-insulation film and a... Agent: Myers Bigel Sibley & Sajovec
20100264479 - Semiconductor device and a method of manufacturing the same: Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide... Agent: Miles & Stockbridge PC
20100264480 - Use of a polymer spacer and si trench in a bitline junction of a flash memory cell to improve tpd characteristics: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one... Agent: Turocy & Watson, LLP
20100264483 - Semiconductor storage device and method of manufacturing same: A semiconductor storage device and method of manufacturing same at a lower cost by without forming a photolithographic resist. Second impurity regions are arranged in such a manner that second impurity regions adjacent along the column direction are joined together. A select gate electrode is arranged into a ring shape... Agent: Sughrue Mion, PLLC
20100264484 - Semiconductor device: In a vertical transistor comprising a pillar-shaped semiconductor layer and a gate electrode formed to around the pillar-shaped semiconductor layer, it is difficult to form a transistor having a gate length greater than that of the vertical transistor. The present invention provides a semiconductor device which comprises two vertical transistors... Agent: Brinks Hofer Gilson & Lione
20100264485 - Semiconductor device and manufacturing method thereof: This invention provides a method of manufacturing a semiconductor device, which comprises the steps of: forming a first columnar semiconductor layer on a first flat semiconductor layer; forming a first semiconductor layer of a second conductive type in a lower portion of the first columnar semiconductor layer; forming a first... Agent: Brinks Hofer Gilson & Lione
20100264486 - Field plate trench mosfet transistor with graded dielectric liner thickness: An electronic device has a plurality of trenches formed in a semiconducting layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric is located... Agent: Texas Instruments Incorporated
20100264487 - Method of manufacturing a trench transistor having a heavy body region: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the... Agent: Townsend And Townsend And Crew, LLP
20100264488 - Low qgd trench mosfet integrated with schottky rectifier: An integrated circuit includes a plurality of trench MOSFET and a plurality of trench Schottky rectifier. The integrated circuit further comprises: tilt-angle implanted body dopant regions surrounding a lower portion of all trench gates sidewalls for reducing Qgd; a source dopant region disposed below a bottom surface of all trench... Agent: Bacon & Thomas, PLLC
20100264489 - Semiconductor device: A transistor contains a first semiconductor layer of a first conductivity type and a drift layer having a pillar structure in which a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type are alternately disposed in a direction parallel to a... Agent: Patterson & Sheridan, L.L.P.
20100264490 - Ldmos with self aligned vertical ldd backside drain: A field effect transistor includes a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and abutting a substrate. A well regions of a second conductivity type is disposed within the semiconductor region. The field... Agent: Townsend And Townsend And Crew, LLP
20100264491 - High breakdown voltage semiconductor device and high voltage integrated circuit: A high breakdown voltage semiconductor device, in which a semiconductor layer is formed on a semiconductor substrate across a dielectric layer, includes a drain layer on the semiconductor layer, a buffer layer formed so as to envelop the drain layer, a source layer, separated from the drain layer, and formed... Agent: Rossi, Kimms & Mcdowell LLP.
20100264492 - Semiconductor on insulator semiconductor device and method of manufacture: A semiconductor on insulator semiconductor device has metal or silicide source and drain contact regions (38, 40), activated source and drain regions (30, 32) and a body region (34). The structure may be a double gated SOI structure or a fully depleted (FD) SOI structure. A sharp intergace and low... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100264493 - Semiconductor device and manufacturing method thereof: To provide a semiconductor device which includes a P-type Si substrate, an ESD protection element, and a protected element. The ESD protection element includes a source N-type diffusion region, and a high-concentration P-type diffusion region formed from under the source N-type diffusion region to at least under part of a... Agent: Greenblum & Bernstein, P.L.C
20100264494 - Recessed channel array transistor (rcat) structures and method of formation: Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of... Agent: Cool Patent, P.C. C/o Cpa Global
20100264495 - High-k metal gate cmos: A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in... Agent: Scully, Scott, Murphy & Presser, P.C.
20100264496 - Sram memory cell provided with transistors having a vertical multichannel structure: A microelectronic device including, on a substrate, at least one element such as a SRAM memory cell; one or more first transistor(s), respectively including a number k of channels (k≧1) parallel in a direction forming a non-zero angle with the main plane of the substrate, and one or more second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100264497 - Multiple vt field-effect transistor devices: Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of... Agent: Michael J. Chang, LLC
20100264498 - Manufacturing a mems element having cantilever and cavity on a substrate: Method for manufacturing a capacitor on a substrate, the capacitor including a first electrode (5) and a second electrode (12; 25), the first and second electrodes being separated by a cavity (16; 32), the substrate including an insulating surface layer (3), the first electrode (5) being arranged on the insulating... Agent: Nixon Peabody, LLP
20100264499 - Mems device and method of fabricating the same: A MEMS device includes a chip carrier having an acoustic port extending from a first surface to a second surface of the chip carrier, a MEMS die disposed on the chip carrier to cover the acoustic port at the first surface of the chip carrier, and an enclosure bonded to... Agent: Morgan Lewis & Bockius LLP
20100264501 - Method for manufacturing magnetic storage device and magnetic storage device: Disclosed is a method for manufacturing a magnetic storage device comprising a TMR element, which comprises a step for forming an insulting film on an interlayer insulating film provided with a wiring layer, an opening formation step for forming an opening in the insulating film so that the wiring layer... Agent: Mcdermott Will & Emery LLP
20100264500 - Method of fabricating structures: A method of processing a stack, the method including depositing a fusible material on a first hardmask layer, the first hardmask layer disposed on a surface of a pre-processed stack, the pre-processed stack being disposed on at least a portion of a substrate; heating the fusible material layer to a... Agent: Campbell Nelson Whipps, LLC
20100264502 - Methods and systems of curved radiation detector fabrication: Gray tone lithography is used to form curved silicon topographies for semiconductor based solid-state imaging devices. The imagers are curved to a specific curvature and shaped directly for the specific application; such as curved focal planes. The curvature of the backside is independent from the front surface, which allows thinning... Agent: Naval Research Laboratory Associate Counsel (patents)
20100264504 - Image sensor having wave guide and method for manufacturing the same: An image sensor having a wave guide includes a semiconductor substrate formed with a photodiode and a peripheral circuit region; an anti-reflective layer formed on the semiconductor substrate; an insulation layer formed on the anti-reflective layer; a wiring layer formed on the insulation layer and connected to the semiconductor substrate;... Agent: Jae Y. Park
20100264503 - Solid-state imaging device comprising through-electrode: A solid-state imaging device includes an imaging element, an external terminal, an insulating film, a through-electrode and a first electrode. The imaging element is formed on a first major surface of a semiconductor substrate. The external terminal is formed on a second major surface opposing the first major surface of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100264505 - Photodiodes with pn junction on both front and back sides: The present invention is directed toward a dual junction photodiode semiconductor device. The photodiode has a semiconductor substrate of a first conductivity type, a first impurity region of a second conductivity type shallowly diffused on the front side of the semiconductor substrate, a second impurity region of the second conductivity... Agent: Patentmetrix
20100264506 - Light-tight silicon radiation detector: A light-tight silicon detector. The detector utilizes a silicon substrate having a sensitive volume for the detection of ionizing radiation and a rectifying contact or electrode through which the ionizing radiation may enter. A diffused or boron-implanted p+ layer may act at the rectifying electrode. A first layer of titanium... Agent: Carstens & Cahoon, LLP
20100264507 - Semiconductor device: A semiconductor device includes: a semiconductor substrate having a main surface having an element formation region, a guard ring, a guard ring electrode, a channel stopper region, a channel stopper electrode, and a field plate disposed over and insulated from the semiconductor substrate. The field plate includes a first portion... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100264508 - Semiconductor device and manufacturing method: A semiconductor device and manufacturing method is disclosed. One embodiment provides a common substrate of a first conductivity type and at least two wells of a second conductivity type. A buried high Ohmic region and at least an insulating structure is provided insulating the first well from the second well.... Agent: Dicke, Billig & Czaja
20100264509 - Enhanced transmission lines for radio frequency applications: An integrated circuit structure includes a semiconductor substrate of a first conductivity type; a depletion region in the semiconductor substrate; and a deep well region substantially enclosed by the depletion region. The deep well region is of a second conductivity type opposite the first conductivity type, and includes a first... Agent: Slater & Matsil, L.L.P.
20100264510 - Soi (silicon on insulator) structure semiconductor device and method of manufacturing the same: In a SOI structure semiconductor device using a SOI substrate, a lattice distortion layer is formed by implanting Ar ions into a silicon substrate as an active layer. The lattice distortion layer is capable of serving as a gettering site. The dose amount of Ar ions is adjusted in such... Agent: Posz Law Group, PLC
20100264511 - Providing current control over wafer borne semiconductor devices using trenches: Disclosed are methods for providing wafer parasitic current control to a semiconductor wafer (1500) having a sub-state (1520), at least one active layer (1565) and a surface layer (1510), and electrical contacts (1515) formed on said surface layer (1510). Current control can be achieved with the formation of trenches (1525)... Agent: Workman Nydegger 1000 Eagle Gate Tower
20100264513 - Integrated circuit devices including passive device shielding structures: Integrated circuit devices include a semiconductor substrate and a flux line generating passive electronic element on the semiconductor substrate. A dummy gate structure is arranged on the semiconductor substrate in a region below the passive electronic element. The dummy gate includes a plurality of segments, each segment including a first... Agent: Myers Bigel Sibley & Sajovec
20100264512 - Semiconductor device and method of forming high-frequency circuit structure and method thereof: A semiconductor device is made by providing an integrated passive device (IPD). Through-silicon vias (TSVs) are formed in the IPD. A capacitor is formed over a surface of the IPD by depositing a first metal layer over the IPD, depositing a resistive layer over the first metal layer, depositing a... Agent: Robert D. Atkins
20100264514 - Semiconductor device and a method of increasing a resistance value of an electric fuse: Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic... Agent: Antonelli, Terry, Stout & Kraus, LLP
20100264516 - Method of forming an inductor on a semiconductor wafer: A semiconductor device has a substrate with an inductor formed on its surface. First and second contact pads are formed on the substrate. A passivation layer is formed over the substrate and first and second contact pads. A protective layer is formed over the passivation layer. The protective layer is... Agent: Robert D. Atkins
20100264515 - Semiconductor device: An interconnect substrate is placed over a first inductor of a semiconductor chip and a second inductor of another semiconductor chip. The interconnect substrate includes a third inductor and a fourth inductor. The third inductor is located above the first inductor. The distance from the first inductor to the third... Agent: Mcginn Intellectual Property Law Group, PLLC
20100264517 - Nitride semiconductor device and manufacturing method thereof: It is an object of the present invention to provide a nitride semiconductor device with low parasitic resistance by lowering barrier height to reduce contact resistance at an interface of semiconductor and metal. The nitride semiconductor device includes a GaN layer, a device isolation layer, an ohmic electrode, an n-type... Agent: Greenblum & Bernstein, P.L.C
20100264519 - Gate trim process using either wet etch or dry etch appraoch to target cd for selected transistors: Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or... Agent: Turocy & Watson, LLP
20100264520 - Semiconductor module: Provided is a semiconductor module wherein a stress relaxing layer is arranged between a ceramic substrate, upon which semiconductor elements are mounted, and a cooling device on the rear side of the ceramic substrate; and the ceramic substrate, the cooling device and the stress relaxing layer are integrally formed. Furthermore,... Agent: Kenyon & Kenyon LLP
20100264518 - Wafer and method for construction, strengthening and homogenization thereof: The present invention provides a water and a method for strengthening, homogenization and construction thereof. The concave and convex portions are processed by laser or etching, and then formed at intervals on the grinding surface of the wafer. The concave and convex portions are round or polygonal shapes. With the... Agent: Egbert Law Offices
20100264521 - Semiconductor component having through wire interconnect (twi) with compressed wire: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact... Agent: Stephen A. Gratton Law Office Of Stephen A. Gratton
20100264523 - Panel, semiconductor device and method for the production thereof: A panel has a baseplate with an upper first metallic layer and a multiplicity of a vertical semiconductor components. The vertical semiconductor components in each case have a first side with a first load electrode and a control electrode and an opposite second side with a second load electrode. The... Agent: Banner & Witcoff, Ltd.
20100264522 - Semiconductor device having at least one bump without overlapping specific pad or directly contacting specific pad: A semiconductor device includes a semiconductor chip, a plurality of bumps and at least one electrically conductive component. The semiconductor chip includes an active area having electronic circuits formed therein and a plurality of pads. The plurality of bumps is placed on the semiconductor chip, wherein a location where at... Agent: North America Intellectual Property Corporation
20100264524 - Substrate for semiconductor package: A substrate for a semiconductor package includes a dielectric substrate, a circuit pattern formed on a first surface of the dielectric substrate, and an electromagnetic band gap (EGB) pattern. The EGB pattern includes multiple unit structures formed on a second surface of the dielectric substrate, where each unit structure includes... Agent: Volentine & Whitt PLLC
20100264525 - Integrated circuit package system with leaded package and method for manufacturing thereof: A method for manufacturing an integrated circuit package system includes: providing a frame; attaching a leaded package having leads adjacent the frame wherein the leads extend towards a side opposite the frame; and applying a package encapsulant over the leaded package having the leads partially exposed opposite the frame.... Agent: Law Offices Of Mikio Ishimaru
20100264526 - Semiconductor package and manufacturing method thereof: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the... Agent: Rabin & Berdo, PC
20100264527 - Stacked chip package structure with leadframe having bus bar: The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads... Agent: Sinorica, LLC
20100264528 - Quad flat pack in quad flat pack integrated circuit package system and method for manufacturing thereof: A method for manufacturing an integrated circuit package system includes: providing a base package having a first integrated circuit with an inner lead on a periphery thereof and connected thereto with interconnects, and the inner lead partially encapsulated by an inner encapsulation; mounting an outer lead on the periphery of... Agent: Law Offices Of Mikio Ishimaru
20100264529 - Integrated circuit package system with integral inner lead and paddle and method of manufacture thereof: A method of manufacture of an integrated circuit package system includes: forming a paddle, an outer lead, and an inner lead between the paddle and the outer lead; forming a non-vertical paddle edge of the paddle and a non-vertical lead edge of the inner lead facing the non-vertical paddle edge;... Agent: Law Offices Of Mikio Ishimaru
20100264531 - Manufacturing method of semiconductor device, adhesive sheet used therein, and semiconductor device obtained thereby: The present invention includes a temporary fixing step of temporarily fixing a semiconductor element on an adherend interposing an adhesive sheet therebetween, a wire-bonding step of bonding wires to the semiconductor element, and a step of sealing the semiconductor element with a sealing resin, and in which the loss elastic... Agent: Knobbe Martens Olson & Bear LLP
20100264530 - Stacked chip package structure with leadframe having bus bar: The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads... Agent: Sinorica, LLC
20100264532 - Electronic device package: Various embodiments for molding tools for moisture-resistant image sensor packaging structures and methods of assembly are disclosed. Image sensor packages of the present invention include an interposer, a housing structure formed on the interposer for surrounding an image sensor chip, and a transparent cover. The housing structure may cover substantially... Agent: Trask Britt, P.C./ Micron Technology
20100264533 - Semiconductor chip package: A semiconductor chip package is provided. The semiconductor chip package includes a lead frame having a chip carrier. A semiconductor chip is mounted on the chip carrier, having a plurality of bonding pads thereon. A package substrate has a cavity therein to accommodate the chip carrier and the semiconductor chip,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100264534 - Chip package structure and manufacturing method thereof: A chip package structure includes a circuit substrate, a chip, at least one bonding wire, and an adhesive layer. The circuit substrate has a bonding surface and at least one pad disposed on the bonding surface. The chip is disposed on the bonding surface of the circuit substrate and has... Agent: J C Patents
20100264535 - Integrated circuit package assembly and substrate processing method: An integrated circuit (IC) package assembly includes a substrate and an IC. The substrate defines a plurality of vias. Inner walls of the plurality of vias and surfaces of the substrate are coated with copper. The plurality of vias are filled with an adhesive. The copper coated on surfaces of... Agent: Altis Law Group, Inc. Attn: Steven Reiss
20100264536 - Self-healing thermal interface materials for semiconductor packages: A semiconductor package is described. The semiconductor package includes an internal housing and a semiconductor die coupled with the internal housing by a layer of self-healing thermal interface material.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20100264537 - Semiconductor arrangement: A semiconductor arrangement, in particular a power semiconductor arrangement, in which a semiconductor having a top side provided with contacts is connected to an electrical connection device formed from a film assembly wherein an underfill is provided between the connection device and the top side of the semiconductor. The underfill... Agent: Cohen, Pontani, Lieberman & Pavane LLP
20100264538 - Method for producing electrical interconnects and devices made thereof: A method for the fabrication of electrical interconnects in a substrate is disclosed. In one aspect, the method includes providing a substrate having a first main surface. The method may further include producing a ring structure in the substrate from the first main surface, which surrounds an inner pillar structure... Agent: Knobbe Martens Olson & Bear LLP
20100264542 - Dynamic pad size to reduce solder fatigue: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with... Agent: Fortkort & Houston P.C.
20100264540 - Ic package reducing wiring layers on substrate and its carrier: An IC package primarily comprises a substrate, a die-attaching layer, a chip, at least a bonding wire, and a plurality of electrical connecting components. The substrate has a top surface and a bottom surface where the top surface includes a die-attaching area for disposing the die-attaching layer. The chip is... Agent: Wpat, PC Intellectual Property Attorneys
20100264541 - Methods of fluxless micro-piercing of solder balls, and resulting devices: A method is disclosed which includes forming a layer of conductive material above a substrate, forming a masking layer above the layer of conductive material, performing a first etching process on the layer of conductive material with the masking layer in place, removing the masking layer and, after removing the... Agent: Perkins Coie LLP Patent-sea
20100264539 - Semiconductor device and method of manufacturing the same: The semiconductor device includes a wiring substrate having connection pads and a semiconductor chip having electrode pads. The semiconductor chip is mounted on the wiring substrate, and the electrode pads are connected to the connection pads via solder bumps. An underfill resin formed of a cured thermosetting resin is filled... Agent: Turocy & Watson, LLP
20100264543 - Interconnect structure: An interconnect structure and methods for forming semiconductor interconnect structures are disclosed. In one embodiment, the interconnect structure includes: a substrate including a first liner layer and a first metal layer thereover; a dielectric barrier layer over the first metal layer and the substrate; an inter-level dielectric layer over the... Agent: Hoffman Warnick LLC
20100264544 - Device including contact structure and method of forming the same: A device includes an insulating layer on a substrate having a lower conductive pattern, the insulating layer having a contact hole that penetrates the insulating layer and exposes a portion of the lower conductive pattern, a catalytic pattern having a first portion on the exposed portion of the lower conductive... Agent: Lee & Morse, P.C.
20100264545 - Metal fill structures for reducing parasitic capacitance: Vertically-staggered-level metal fill structures include inner contiguous metal fill structures and outer contiguous metal fill structures. A dielectric material portion is provided between each contiguous metal fill structure. Vertical extent of each contiguous metal fill structure is limited up to three vertically adjoining metal interconnect levels, thereby limiting the capacitance... Agent: Scully, Scott, Murphy & Presser, P.C.
20100264546 - Semiconductor device and manufacturing method thereof: The present invention provides a semiconductor device and manufacturing method of the semiconductor device which can prevent breaks in an interlayer insulation film (12) and electrode (13) that arise with bonding while maintaining bonding strength. A semiconductor element (1) mounted on a semiconductor device including an interlayer insulation film (12)... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100264547 - Semiconductor device and method for manufacturing: A first region having a first metal wiring, the first metal wiring being buried into an insulation film with a first minimum dimension, and a second region having a second metal wiring, the second metal wiring being buried in the insulation film with a second minimum dimension which is larger... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100264550 - Self-aligned contact: A self-aligned contact includes a lower contact disposed in a dielectric layer of a substrate and an upper contact disposed in the dielectric layer and directly on the lower contact, and electrically connected to the lower contact. The profile of the upper contact and the lower contact is zigzag.... Agent: Lanway Ipr Services
20100264548 - Through substrate vias: Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region (26) of a first thickness (27) proximate the front surface (23) of a substrate wafer (20, 20′) by: (i) from the front surface (23), forming comparatively shallow vias (30, 30′) of a... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)
20100264549 - Trench substrate and method of manufacturing the same: Disclosed herein are a trench substrate and a method of manufacturing the same. The trench substrate includes a base substrate, an insulating layer formed on one side or both sides of the base substrate and including trenches formed in a circuit region and a dummy region positioned at a peripheral... Agent: Blakely Sokoloff Taylor & Zafman LLP
20100264551 - Three dimensional integrated circuit integration using dielectric bonding first and through via formation last: A method of implementing three-dimensional (3D) integration of multiple integrated circuit (IC) devices includes forming a first insulating layer over a first IC device; forming a second insulating layer over a second IC device; forming a 3D, bonded IC device by aligning and bonding the first insulating layer to the... Agent: Cantor Colburn LLP - IBM Fishkill
20100264552 - Circuit device, method of manufacturing the circuit device, device mounting board and semiconductor module: A circuit device includes an insulating base provided with a resin layer mixed with a fibrous filler, bumps provided in the insulating base and functioning as electrodes for connection, a semiconductor device that is flip-chip mounted, and an underfill filling a gap between the semiconductor device and the insulating base.... Agent: Mcdermott Will & Emery LLP
20100264553 - Packaged electronic device having metal comprising self-healing die attach material: A method of assembling an electronic device and electronic packages therefrom. A die attach adhesive precursor is placed between a top surface of a workpiece and an IC die. The die attach adhesive precursor includes metal particles, a first plurality of first microcapsules having a polymerizable material inside, and a... Agent: Texas Instruments Incorporated- None available for 10/01/2010
- None available for 10/7/2010
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