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Active solid-state devices (e.g., transistors, solid-state diodes) June invention type 06/10

20100155684 - Non-volatile memory device and method of forming the same: Provided are a non-volatile memory device and a method of forming the non-volatile memory device. The non-volatile memory device includes a substrate, a lower electrode on the substrate, a diffusion barrier preventing the diffusion of a space charge on the lower electrode, a charge storage layer having a space charge... Agent: Rabin & Berdo, PC

20100155685 - Electronic component, and a method of manufacturing an electronic component: An electronic component (100), a first electrode (101), a second electrode (102), and a convertible structure (103) electrically coupled between the first electrode (101) and the second electrode (102), being convertible between at least two states by heating and having different electrical properties in different ones of the at least... Agent: Haynes And Boone, LLPIPSection

20100155688 - Electric device with nanowires comprising a phase change material: The method according to the invention is directed to manufacturing an electric device (100) according to the invention, having a body (102) with a resistor comprising a phase change material being changeable between a first phase and a second phase, the resistor having a first electrical resistance when the phase... Agent: Philips Intellectual Property & Standards

20100155686 - Memristive device: A memristive device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. At least one of the first and second electrodes is a metal oxide electrode.... Agent: Hewlett-packard Company Intellectual Property Administration

20100155687 - Method for manufacturing a resistive switching memory device and devices obtained thereof: A method for manufacturing a resistive switching memory device comprises providing a substrate comprising an electrical contact, providing on the substrate a dielectric layer comprising a trench exposing the electrical contact, and providing in the trench at least the bottom electrode and the resistive switching element of the resistive memory... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20100155690 - Cross-point cell nanoarray with anisotropic active organic layer: A cross-point cell nanoarray comprises a mechanical support substrate, first and second orders of uniformly spaced parallel electrodes separated by an electrically active organic film and orthogonally arranged to form an array of cross-point cells, individually addressable by biasing the respective opposite electrodes, by selecting them among those of the... Agent: Seed Intellectual Property Law Group PLLC

20100155689 - Quad memory cell and method of making same: A non-volatile memory device includes a first electrode, a diode steering element, at least three resistivity switching storage elements, and a second electrode. The diode steering element electrically contacts the first electrode and the at least three resistivity switching storage elements. The second electrode electrically contacts only one of the... Agent: Sandisk Corporation C/o Foley & Lardner LLP

20100155691 - Method of fabricating semiconductor oxide nanofibers for sensor and gas sensor using the same: A gas sensor for detecting environmentally harmful gases is provided. The sensor includes an insulating substrate, a metal electrode formed on the insulating substrate, and a sensing layer formed on the metal electrode and including a semiconductor oxide (Lan+1NinO3n+1(n=1,2,3)) nanofiber. Therefore, a semiconductor oxide (Lan+1NinO3n+1(n=1,2,3)) has an ABO3-type basic crystalline... Agent: Rabin & Berdo, PC

20100155692 - Nano memory, light, energy, antenna and strand-based systems and methods: An apparatus includes a first array of transistor elements; a second array of carbon nano-elements formed above or below the first array of transistor elements; and a circuit coupled to the first array to access the carbon nano elements.... Agent: Bao Q. Tran

20100155694 - Adapting short-wavelength led's for polychromatic, broadband, or \"white\" emission: An adapted LED is provided comprising a short-wavelength LED and a re-emitting semiconductor construction, wherein the re-emitting semiconductor construction comprises at least one potential well not located within a pn junction. The potential well(s) are typically quantum well(s). The adapted LED may be a white or near-white light LED. The... Agent: 3m Innovative Properties Company

20100155693 - Light emitting device having plurality of light emitting cells and method of fabricating the same: Disclosed are a light emitting device having a plurality of light emitting cells and a method of fabricating the same. The light emitting device comprises a plurality of light emitting cells positioned on a substrate to be spaced apart from one another. Each of the light emitting cells comprises a... Agent: H.c. Park & Associates, PLC

20100155695 - Light emitting device using nano size needle: A light-emitting device that improves the injection efficiency of electrons or holes by providing electrons or holes to an emitting layer using nano size needles, including a first electrode with a first polarity a second electrode with a second polarity opposite to the first polarity an emitting layer interposed between... Agent: Sughrue Mion, PLLC

20100155697 - Interfering excitations in fqhe fluids: An apparatus includes a substrate with a planar surface, a multilayer of semiconductor layers located on the planar surface, a plurality of electrodes located over the multilayer, and a dielectric layer located between the electrodes and the multilayer. The multilayer includes a 2D quantum well. A first set of the... Agent: Alcatel-lucent Usa Inc. Docket Administrator - Room 2f-192

20100155696 - Large-area nanoenabled macroelectronic substrates and uses therefor: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor... Agent: Nanosys Inc.

20100155698 - Nanoscale wires and related devices: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length,... Agent: Harvard University & Medical School C/o Wolf, Greenfield & Sacks, P.C.

20100155699 - Nitride semiconductor device: A nitride semiconductor device includes n-type and p-type nitride semiconductor layers, an active layer, the active layer having a lamination of quantum barrier layers and quantum well layers, a thermal stress control layer disposed between the n-type nitride semiconductor layer and the active layer, and formed of a material having... Agent: Mcdermott Will & Emery LLP

20100155700 - Thermoelectric cooler for semiconductor devices with tsv: This invention discloses a thermoelectric structure for cooling an integrated circuit (IC) chip, the thermoelectric structure comprises a first type superlattice layer formed on top of the IC chip connected to a first voltage, and a second type superlattice layer formed on the bottom of the IC chip connected to... Agent: K&l Gates LLPIPDocketing

20100155702 - Nanowire circuit architecture: A nanowire circuit architecture is presented. The technology comprises of nanowire transistors (8,9), and optionally nanowire capacitors (12) and nanowire resistors (11), that are integrated using two levels of interconnects only (1,2). Implementations of ring-oscillators, sample- and-hold circuits, and comparators may be realized in this nanowire circuit architecture. Circuit input... Agent: Foley And Lardner LLP Suite 500

20100155701 - Self-aligned replacement metal gate process for qwfet devices: A self-aligned replacement metal gate QWFET device comprises a III-V quantum well layer formed on a substrate, a III-V barrier layer formed on the quantum well layer, a III-V etch stop layer formed on the III-V barrier layer, a III-V source extension region formed on the III-V etch stop layer... Agent: Intel Corporation C/o Cpa Global

20100155703 - Semiconductor device and method of fabricating the same: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a single electron box including a first quantum dot, a charge storage gate on the first quantum dot, and a first gate electrode on the charge storage gate, the charge storage gate exchanging charges... Agent: Ladas & Parry LLP

20100155704 - Nitride semiconductor light emitting device and method of manufacturing the same: A nitride semiconductor light emitting device, and a method of manufacturing the same are disclosed. The nitride semiconductor light emitting device includes a substrate, an n-type nitride semiconductor layer disposed on the substrate and including a plurality of V-shaped pits in a top surface thereof, an active layer disposed on... Agent: Mcdermott Will & Emery LLP

20100155705 - Display device including organic light-emitting transistor and method of fabricating the display device: Provided are a display device, which has a longer life and can be fabricated simply relative to conventional display devices, and a method of fabricating the display device. The display device includes a substrate which includes first through third subpixel regions, first through third organic light-emitting transistors which are disposed... Agent: Haynes And Boone, LLPIPSection

20100155709 - Encapsulation for an electronic thin film device: The present invention relates to an encapsulation for an electronic thin film device, comprising a first barrier layer (108), a second barrier layer (112), and a first planarization layer (110′) for reducing the formation of pinholes in a subsequent barrier layer, said first planarization layer (110′) arranged between the first... Agent: Philips Intellectual Property & Standards

20100155710 - Forming active channel regions using enhanced drop-cast printing: An active region or channel for printed, organic or plastic electronics or polymer semiconductors, such as organic field-effect transistors (OFETs), is obtained by using an enhanced inkjet drop-cast printing technique. A two-liquid system is employed to achieve the direct growth of well-oriented organic crystals at the active region of channel.... Agent: Patterson & Sheridan, L.L.P.

20100155706 - Material for organic photoelectric device including electron transporting unit and hole transporting unit, and organic photoelectric device including the same:

20100155713 - Metal complex compound and organic electroluminescent device using same: A metal complex compound having a special structure containing metals such as iridium. An organic electroluminescence device which comprises at least one organic thin film layer sandwiched between a pair of electrode consisting of an anode and a cathode, wherein the organic thin film layer comprises the above metal complex... Agent: Steptoe & Johnson LLP

20100155712 - Organic electroluminescent device: In formula (1), L represents a linking group; A1, A2, A3, A4, A5, A6, A7, A8, A9, and A10 each independently represent a carbon atom or a nitrogen atom, provided that at least two of A1, A5, A6, and A10 each represent a carbon atom having R′; R′ represents a... Agent: Sughrue-265550

20100155714 - Organic electroluminescent device:

20100155707 - Organic field-effect transistors: An organic field-effect transistor comprising: a source region; a drain region; one or more organic semiconductor layers disposed between the source and drain regions; a gate region; and a dielectric region disposed between the organic semiconductor layer(s) and the gate region; wherein the composition of the organic semiconductor layer(s) is... Agent: Haynes And Boone, LLPIPSection

20100155711 - Organic light-emitting element and light-emitting device using the same: An organic light-emitting element includes a first electrode, a second electrode, and at least one organic compound layer disposed between the first electrode and the second electrode. The organic compound layer includes a light-emitting layer containing a light-emitting material and being configured to emit light toward the first electrode and... Agent: Canon U.s.a. Inc. Intellectual Property Division

20100155708 - Reducing defects in electronic switching devices: A technique for isolating electrodes on different layers of a multilayer electronic device across an array containing more than 100000 devices on a plastic substrate. The technique comprises depositing a bilayer of a first dielectric layer (6) of a solution-processible polymer dielectric and a layer of parylene (9) to isolate... Agent: Sughrue Mion, PLLC

20100155715 - Display substrate, and method of manufacturing the same: A display substrate according to the present invention comprises a gate line formed on a substrate. a data line, a thin film transistor connected to the gate line and the data line respectively and pixel electrode connected to the thin film transistor, wherein a channel of the thin film transistor... Agent: Cantor Colburn, LLP

20100155720 - Field-effect semiconductor device, and method of fabrication: A heterojunction field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main... Agent: Woodcock Washburn LLP

20100155722 - Memory device with band gap control: A memory device with band gap control is described. A memory cell can include a conductive oxide layer in contact with and electrically in series with an electronically insulating layer. A thickness of the electronically insulating layer is configured to increase from an initial thickness to a target thickness. The... Agent: Unity Semiconductor Corporation

20100155723 - Memory stack cladding: Examples of memory stack cladding are described, including a memory stack, comprising a first electrode formed on a substrate, a conductive metal oxide layer deposited on the first electrode, a tunnel barrier layer comprising an insulating metal oxide, the tunnel barrier layer being deposited on the conductive metal oxide layer,... Agent: Unity Semiconductor Corporation

20100155719 - Method for manufacturing semiconductor device: In a manufacturing process of a semiconductor device formed using a thin film transistor, an object is to provide a technique by which the number of photomasks can be reduced, manufacturing cost can be reduced, and improvement in productivity and reliability can be achieved. A main point is that a... Agent: Eric Robinson

20100155718 - Method of manufacturing thin film transistor, thin film transistor, and display unit: A method of manufacturing a thin film transistor capable of simplifying the steps is provided. The method of manufacturing a thin film transistor includes the steps of: forming a gate electrode and a gate insulating film sequentially on a substrate; forming an oxide semiconductor film in a shape including a... Agent: Sonnenschein Nath & Rosenthal LLP

20100155717 - Noncrystalline oxide semiconductor thin film, process for producing the noncrystalline oxide semiconductor thin film, process for producing thin-film transistor, field-effect-transistor, light emitting device, display device, and sputtering target: This invention provides an amorphous oxide semiconductor thin film, which is insoluble in a phosphoric acid-based etching solution and is soluble in an oxalic acid-based etching solution by optimizing the amounts of indium, tin, and zinc, a method of producing the amorphous oxide semiconductor thin film, etc. An image display... Agent: Millen, White, Zelano & Branigan, P.C.

20100155721 - Thin film transistor array substrate and method of fabricating the same: A thin film transistor (TFT) array substrate is provided. The thin film transistor (TFT) array substrate includes an insulating substrate, an oxide semiconductor layer formed on the insulating substrate and including an additive element, a gate electrode overlapping the oxide semiconductor layer, and a gate insulating layer interposed between the... Agent: Innovation Counsel LLP

20100155716 - Thin film transistor using boron-doped oxide semiconductor thin film and method of fabricating the same: Provided are a thin film transistor, to which a boron-doped oxide semiconductor thin film is applied as a channel layer, and a method of fabricating the same. The thin film transistor includes source and drain electrodes, a channel layer, a gate insulating layer, and a gate electrode, which are formed... Agent: Rabin & Berdo, PC

20100155724 - Flat panel display including electrostatic protection circuit: A flat panel display is disclosed. The flat panel display includes a display panel having a display area on which a plurality of pixels are formed, an inspection pad formed in a non-display area outside the display area of the display panel, an inspection switch formed in the non-display area,... Agent: Mckenna Long & Aldridge LLP

20100155725 - Insert module for a test handler: An insert module for a test handler includes an insert body and a support frame. The insert body has a receiving space for receiving a semiconductor device. The semiconductor device having connection pads protruding externally from a surface of the semiconductor device. The support frame is formed in an inner... Agent: F. Chau & Associates, LLC

20100155726 - Semiconductor integrated circuit: A semiconductor integrated circuit according to an exemplary embodiment of the present invention includes an I/O buffer provided in a semiconductor chip, single-layer pads, and multilayer pads. The single-layer pads are formed above the I/O buffer. The multilayer pads are formed above the I/O buffer separately from the single-layer pads.... Agent: Young & Thompson

20100155727 - Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.... Agent: Williams, Morgan & Amerson

20100155728 - Epitaxial wafer and method for fabricating the same: An epitaxial wafer and method for fabricating the same can prevent a bowing phenomenon of the epitaxial wafer. The epitaxial wafer includes a substrate configured to be doped in a first doping concentration; an epitaxial layer configured to be formed over a first side of the substrate and doped in... Agent: Morgan Lewis & Bockius LLP

20100155729 - Fan-out unit and thin-film transistor array substrate having the same: A fan-out unit which can control a resistance difference among channels with efficient space utilization and a thin-film transistor (TFT) array substrate having the fan-out unit are presented. The fan-out unit includes: an insulating substrate; a first wiring layer which is formed on the insulating substrate and connected to a... Agent: Innovation Counsel LLP

20100155733 - Array substrate for display device and method for fabricating the same: An array substrate for a display device and its fabrication method are disclosed. The array substrate for a display device includes: a gate wiring and a gate electrode connected to the wiring formed on a substrate; a gate insulating layer formed on the gate electrode; an active layer and a... Agent: Mckenna Long & Aldridge LLP

20100155734 - Electrophoretic display device and method of manufacturing and repairing the same: Provided is an electrophoretic display device and a method of manufacturing and repairing the electrophoretic display device. The electrophoretic display device includes: a gate line, a gate electrode, and a common electrode, separated a predetermined distance from the gate line, which are formed on a substrate; a gate insulation layer... Agent: Brinks Hofer Gilson & Lione

20100155732 - Semiconductor device and manufacturing method thereof: It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (inorganic insulating film and organic resin film) by conducting etching... Agent: Cook Alex Ltd

20100155730 - Thin film transistor display panel and manufacturing method thereof: In the manufacturing process of the thin film transistor array panel according to an exemplary embodiment of the present invention using three masks, the metal oxide semiconductor or the transparent conductive oxide is used, thereby executing an efficient lift-off process.... Agent: H.c. Park & Associates, PLC

20100155731 - Touching-type electronic paper and method for manufacturing the same: The present invention relates to a touching-type electronic paper and method for manufacturing the same. The touching-type electronic paper includes a TFT substrate and a transparent electrode substrate which are disposed as a cell. The transparent electrode substrate includes a common electrode, microcapsule electronic ink and light guiding poles as... Agent: J C Patents

20100155735 - Electrophoretic display device and method of fabricating the same: An electrophoretic display device includes a gate line on a substrate, a common line parallel to the gate line, a gate insulating layer on the gate line and the common line, a data line on the gate insulating layer, the data line crossing the gate line to define a pixel... Agent: Birch Stewart Kolasch & Birch

20100155737 - Method for manufacturing a semiconductor device: A purpose of the invention is to provide a method for leveling a semiconductor layer without increasing the number and the complication of manufacturing processes as well as without deteriorating a crystal characteristic, and a method for leveling a surface of a semiconductor layer to stabilize an interface between the... Agent: Nixon Peabody, LLP

20100155736 - Thin film transistor, method of fabricating the same, and organic light emitting diode display device having the thin film transistor: A thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device including the TFT. The TFT includes a substrate having a pixel region and a non-pixel region, a semiconductor layer, a gate insulating layer, a gate electrode, and source and drain... Agent: Stein Mcewen, LLP

20100155741 - Compound semiconductor device and manufacturing method thereof: A compound semiconductor device includes a carrier transit layer including GaN formed over a substrate; a carrier supply layer including GaN formed over the carrier transit layer; a source electrode and a drain electrode formed over the carrier supply layer; a first compound semiconductor layer including N in which a... Agent: Fujitsu Patent Center C/o Cpa Global

20100155738 - Light emitting diode and method for manufacturing same: This invention provides a light emitting diode in which a thick transparent conductive electrode is formed on an emitting side of GaN based semiconductor light emitting element, and a light emitting efficiency of the GaN semiconductor light emitting element is improved. Further, it provides a manufacturing method of the light... Agent: Frishauf, Holtz, Goodman & Chick, PC

20100155739 - Light-emitting device, method for manufacturing same, molded body and sealing member: Disclosed is a light-emitting device comprising a light-emitting element (10) composed of a gallium nitride compound semiconductor having an emission peak wavelength of not less than 430 nm; a molded body (40) provided with a recessed portion having a bottom surface on which the light-emitting element (10) is mounted and... Agent: Birch Stewart Kolasch & Birch

20100155740 - Semiconductor device and method for manufacturing semiconductor device: A cavity-containing layer having a plurality of cavities is formed on a growth substrate by carrying out in alternating fashion a plurality of cycles of a first and second growth steps of growing a group III nitride at growth rates different from each other. The semiconductor epitaxial layer is subsequently... Agent: Frishauf, Holtz, Goodman & Chick, PC

20100155742 - Light-emitting diode and light-emitting diode lamp: The present invention provides a light-emitting diode (10) including a substrate (101) made of a first conductive type silicon (Si) single crystal, a pn junction structured light-emitting section (40) composed of a III-group nitride semiconductor on the substrate, a first polarity ohmic electrode (107a) for the first conductive type semiconductor... Agent: Sughrue Mion, PLLC

20100155743 - Sic semiconductor device with self-aligned contacts, integrated circuit and manufacturing method: One aspect includes a semiconductor device with self-aligned contacts, integrated circuit and manufacturing method. One embodiment provides gate control structures. Each of the gate control structures is configured to control the conductivity of a channel region within a silicon carbide substrate by field effect. A contact hole is self-aligned to... Agent: Dicke, Billig & Czaja

20100155744 - Semiconductor nanocrystal composite: A nanocrystal composite that includes a matrix including semiconductor nanocrystals, and a barrier layer disposed on at least a portion of the surface of the matrix and including a polymer with low oxygen permeability, low moisture permeability, or both.... Agent: Cantor Colburn, LLP

20100155746 - High voltage low current surface-emitting led: A monolithic LED chip is disclosed comprising a plurality of junctions or sub-LEDs (“sub-LEDs”) mounted on a submount. The sub-LEDs are serially interconnected such that the voltage necessary to drive the sub-LEDs is dependent on the number of serially interconnected sub-LEDs and the junction voltage of the sub-LEDs. Methods for... Agent: Koppel, Patrick, Heybl & Dawson

20100155745 - Multichip light-emitting diode: A multichip light-emitting diode (LED) includes a reflective cup, a plurality of light-emitting chips and a package. The light-emitting chips are disposed in the reflective cup and emit light when driven. The package is disposed in the reflective cup and covers the light-emitting chips. The package further has a plurality... Agent: Stevens & Showalter LLP

20100155747 - Organic light emission diode display device and method of fabricating the same: An organic light emission diode (OLED) display device and a method of fabricating the same, wherein the OLED display device includes a substrate including a pixel region and a non-pixel region, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, and including a channel... Agent: Stein Mcewen, LLP

20100155748 - Aligned multiple emitter package: A multiple element emitter package is disclosed for increasing color fidelity and heat dissipation, improving current control, increasing rigidity of the package assembly. In one embodiment, the package comprises a surface-mount device a casing with a cavity extending into the interior of the casing from a first main surface is... Agent: Koppel, Patrick, Heybl & Dawson

20100155749 - Light-emitting diode (led) devices comprising nanocrystals: The present invention provides light-emitting diode (LED) devices comprises compositions and containers of hermetically sealed luminescent nanocrystals. The present invention also provides displays comprising the LED devices. Suitably, the LED devices are white light LED devices.... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20100155750 - Color correction for wafer level white leds: A method for fabricating a plurality of LED chips comprises providing a plurality of LEDs and forming a plurality of spacers each of which is on at least one of the LEDs. Coating the LEDs with a conversion material, each of the spacers reducing the amount of conversion material over... Agent: Koppel, Patrick, Heybl & Dawson

20100155751 - Light emitting diode assembly and light emitting diode display device: An exemplary light emitting diode (LED) assembly includes a cover, a substrate, a LED unit, a first electrode terminal, and a second electrode terminal. The substrate includes a first surface and a second surface on an opposite side of the substrate thereto. The substrate and the cover cooperatively define a... Agent: PCe Industry, Inc. Att. Steven Reiss

20100155752 - Semiconductor light emitting device: A semiconductor light emitting device that includes a first conductive type semiconductor layer, a first electrode, a insulating layer, and an electrode layer. The first electrode has at least one branch on the first conductive type semiconductor layer. The insulating layer is disposed on the first electrode. The electrode layer... Agent: Birch Stewart Kolasch & Birch

20100155764 - Glass-covered light-emitting element and glass-covered light-emitting device: The glass-covered light-emitting element is covered with glass, which is formed of calcined glass frit, which has a softening temperature of 600° C. or less, which has a total light transmittance of 85% or more, which a coefficient of thermal expansion of 70×10−7/° C. to 125×10−7/° C., and which has... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100155754 - Group iii nitride semiconductor light emitting device and method for producing the same: The present invention provides a group III nitride semiconductor light emitting device and a method for producing the same. The group III nitride semiconductor light emitting device comprises (a1), (b1) and (c1) in this order: (a1) an N electrode, (b1) a semiconductor multi-layer film, (c1) a transparent electric conductive oxide... Agent: Fitch, Even, Tabin & Flannery

20100155758 - Light emitting device and manufacturing method for the same: A light emitting device is provided, including a resin which can be manufactured according to a simple process and deliver a desired scattering property. The light emitting device is manufactured according to a step for mixing two or more types of immiscible liquid materials to obtain a composition containing at... Agent: Cermak Kenealy Vaidya & Nakajima LLP

20100155761 - Light emitting device having a divalent europium-activated alkaline earth metal orthosilicate phoshor: A light emitting device includes a light emitting element comprising a nitride semiconductor and a phosphor that can absorb a part of light emitted from the light emitting element and can emit light of a wavelength different from that of the absorbed light. The phosphor comprises a silicate phosphor comprising... Agent: Mcginn Intellectual Property Law Group, PLLC

20100155765 - Light emitting device having vertical structure and method for manufacturing the same: A light emitting device having a vertical structure, which includes a semiconductor layer having a first surface and a second surface, a first electrode arranged on the first surface of the semiconductor layer, a transparent conductive oxide (TCO) layer arranged on the second surface of the semiconductor layer and a... Agent: Birch Stewart Kolasch & Birch

20100155756 - Light emitting diode package and projection apparatus: A light emitting diode (LED) package including a carrier, at least one LED chip, and a light guide element is provided. The LED chip is disposed on the carrier. The light guide element including a light transmissive body, a light integration part, a reflective film, and a support part is... Agent: J C Patents

20100155759 - Light-emitting device: The light-emitting device 100 of the present invention has a first cladding layer 106; an active layer 108 formed above the first cladding layer 106; and a second cladding layer 110 formed above the active layer 108, wherein the active layer 108 has a first side surface 107, and a... Agent: Harness, Dickey & Pierce, P.L.C

20100155755 - Light-emitting diode with light-conversion layer: A method for making a lighting apparatus includes providing a substrate and disposing a light-emitting diode overlying the substrate. The light-emitting diode has a top surface oriented away from the substrate and a plurality of side surfaces. A light-conversion material is provided that includes a substantially transparent base material and... Agent: Townsend And Townsend And Crew, LLP

20100155757 - Organic light emitting diode display: The present invention relates to an OLED display, and an OLED display according to an exemplary embodiment of the present invention includes a substrate member, an OLED including a first electrode formed on the substrate member, an organic emission layer formed on the first electrode, and a second electrode formed... Agent: Robert E. Bushnell & Law Firm

20100155760 - Organic light emitting display device and method for manufacturing the same: Disclosed are an organic light emitting display device with improved yield and processing efficiency, which includes an interlayer capable of being separated into a hydrophilic region and a hydrophobic region on top of a hole injection layer in an organic light emitting device and a plurality of layers including a... Agent: Brinks Hofer Gilson & Lione

20100155753 - Phosphor, light emitting device and white light emitting diode: The present invention provides a phosphor, a lighting system and a white light emitting diode. The phosphor comprises a compound represented by the formula (1) and Eu as an activator. aM12O.bM2O.cM3O2 (1) wherein, in the formula (1), M1 is at least one selected from the group consisting of Li, Na,... Agent: Sughrue Mion, PLLC

20100155762 - Standing transparent mirrorless light emitting diode: An (Al, Ga, In)N light emitting diode (LED) in which multi-directional light can be extracted from one or more surfaces of the LED before entering a shaped optical element and subsequently being extracted to air. In particular, the (Al, Ga, In)N and transparent contact layers (such as ITO or ZnO)... Agent: Gates & Cooper LLP Howard Hughes Center

20100155763 - Systems and methods for application of optical materials to optical elements: Methods are disclosed including heating an optical element. An optical material is applied to the heated optical element to provide a conformal layer that is cured via the thermal energy in the heated optical element.... Agent: Myers Bigel Sibley & Sajovec, P.A.

20100155771 - Light emitting device: A light emitting device includes a first lead and a second lead. The first lead has a top surface which a light emitting element is mounted thereon and a bottom surface opposed to the top surface. The second lead has a lead peripheral region where a wire connected to an... Agent: Ditthavong Mori & Steiner, P.C.

20100155767 - Light emitting device using a micro-rod and method of manufacturing a light emitting device: A light emitting device using a micro-rod and a method of manufacturing a light emitting device are provided, the method includes forming a material layer on a substrate. The material layer is patterned such that a hole is formed that exposes a surface of the substrate. A core is grown... Agent: Harness, Dickey & Pierce, P.L.C

20100155766 - Light emitting diode and method for manufacturing the same: An LED includes a bowl-like substrate, three posts embedded within the substrate, an LED die bonded to a middle post, a pair of spiral gold wires interconnecting two electrodes of the LED die and two lateral posts, and an encapsulant sealing the LED die and fixed on the substrate. The... Agent: PCe Industry, Inc. Att. Steven Reiss

20100155770 - Multilayered lead frame for a semiconductor light-emitting device: A lead frame (100) for a semiconductor device is formed by applying nickel plating (102), palladium plating (103), and gold flash plating (104) substantially entirely to lead frame body (101) such as copper thin plate in this order, and further applying silver plating (105) selectively to part of an inner... Agent: Mcdermott Will & Emery LLP

20100155769 - Semiconductor chip assembly with base heat spreader and cavity in base: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a base. A cavity extends through the adhesive into the base. The semiconductor device extends into the cavity, is electrically connected to the conductive trace and is thermally connected... Agent: David M. Sigmond

20100155768 - Semiconductor chip assembly with post/base heat spreader and cavity in post: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a post and a base. The semiconductor device extends into a cavity in the post, is electrically connected to the conductive trace and is thermally connected to the heat... Agent: David M. Sigmond

20100155772 - Semiconductor light emitting device and method for manufacturing the same: Provided is a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises: a first conductive type semiconductor layer; an active layer on the first conductive type semiconductor layer; an undoped semiconductor layer on the active layer; a first delta-doped layer on the... Agent: Birch Stewart Kolasch & Birch

20100155773 - Vts insulated gate bipolar transistor: In one embodiment, a power transistor device comprises a substrate that forms a PN junction with an overlying buffer layer. The power transistor device further includes a first region, a drift region that adjoins a top surface of the buffer layer, and a body region. The body region separates the... Agent: The Law Offices Of Bradley J. Bereznak

20100155774 - Bi-directional transient voltage suppression device and forming method thereof: A bidirectional transient voltage suppression device is disclosed. The bi-directional transient voltage suppression device comprises a semiconductor die. The semiconductor die has a multi-layer structure comprising a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type, an epitaxial layer, and five diffused regions. The... Agent: Morris Manning Martin LLP

20100155775 - Design structure and method for an electrostatic discharge (esd) silicon controlled rectifier (scr) structure: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. Further, the first and the second SCRs each include at least one component commonly shared between the first... Agent: Roberts Mlotkowski Safran & Cole, P.C. Intellectual Property Department

20100155776 - Forming esd diodes and bjts using finfet compatible processes: A method of forming an electrostatic discharging (ESD) device includes forming a first and a second semiconductor fin over a substrate and adjacent to each other; epitaxially growing a semiconductor material on the first and the second semiconductor fins, wherein a first portion of the semiconductor material grown from the... Agent: Slater & Matsil, L.L.P.

20100155777 - Digital alloy absorber for photodetectors: In order to increase the spectral response range and improve the mobility of the photo-generated carriers (e.g. in an nBn photodetector), a digital alloy absorber may be employed by embedding one (or fraction thereof) to several monolayers of a semiconductor material (insert layers) periodically into a different host semiconductor material... Agent: Canady & Lortz LLP

20100155778 - Method for enhancing growth of semipolar (al,in,ga,b)n via metalorganic chemical vapor deposition: A method for enhancing growth of device-quality planar semipolar nitride semiconductor thin films via metalorganic chemical vapor deposition (MOCVD) by using an (Al, In, Ga)N nucleation layer containing at least some indium. Specifically, the method comprises loading a substrate into a reactor, heating the substrate under a flow of nitrogen... Agent: Gates & Cooper LLP Howard Hughes Center

20100155779 - Field effect transistor: In a field effect transistor, a Group III nitride semiconductor layer structure containing a hetero junction, a source electrode 101 and a drain electrode 103 formed apart from each other over the Group III nitride semiconductor layer structure, and a gate electrode 102 disposed between these electrodes, are provided. Over... Agent: Mcginn Intellectual Property Law Group, PLLC

20100155780 - Semiconductor device: An aspect of the present invention inheres in a semiconductor device includes a semiconductor region, a source electrode and a drain electrode, which are provided on a main surface of the semiconductor region, a gate electrode exhibiting normally-off characteristics, the gate electrode being provided above the main surface of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100155781 - Monolithic integrated circuit of a field-effect semiconductor device and a diode: A field-effect semiconductor device such as a HEMT or MESFET is monolithically integrated with a Schottky diode for feedback, regeneration, or protection purposes. The field-effect semiconductor device includes a main semiconductor region having formed thereon a source, a drain, and a gate between the source and the drain. Also formed... Agent: Woodcock Washburn LLP

20100155782 - Super cmos devices on a microelectronics system: A low cost IC solution is disclosed in accordance with an embodiment to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected... Agent: Sawyer Law Group, P.C.

20100155783 - Standard cell architecture and methods with variable design rules: Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at... Agent: Slater & Matsil, L.L.P.

20100155784 - Three-dimensional memory structures having shared pillar memory cells: A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end... Agent: Vierra Magen/sandisk Corporation

20100155785 - Hto offset spacers and dip off process to define junction: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a pair of first... Agent: Turocy & Watson, LLP

20100155786 - Methods and devices for forming nanostructure monolayers and devices including such monolayers: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also... Agent: Quine Intellectual Property Law Group, P.C.

20100155787 - Solid state image pickup device and manufacturing method therefor: A MOS-type solid-state image pickup device, on a semiconductor substrate, includes a photoelectric conversion unit having a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a transfer MOS transistor having a... Agent: Fitzpatrick Cella Harper & Scinto

20100155788 - Formation of a multiple crystal orientation substrate: Embodiments of the invention provide a substrate with a first layer having a first crystal orientation on a second layer having a second crystal orientation different than the first crystal orientation. The first layer may have a uniform thickness.... Agent: Intel Corporation C/o Cpa Global

20100155789 - Low noise jfet: A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by... Agent: Texas Instruments Incorporated

20100155791 - Method of fabricating semiconductor device and the semiconductor device: A method of fabricating a semiconductor device includes forming trench-like recesses in a semiconductor substrate, the recesses including one or more recesses each of which has an opening width of not more than a predetermined value, forming a first insulating film above the substrate after the recesses have been formed,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100155790 - N-fet with a highly doped source/drain and strain booster: A structure and method of making an N-FET with a highly doped source/drain and strain booster are presented. The method provides a substrate with a Ge channel region. A gate dielectric is formed over the Ge channel and a gate electrode is formed over the gate dielectric. Sacrificial gate spacers... Agent: Slater & Matsil, L.L.P.

20100155794 - Rework method of metal structure of semiconductor device: A rework method of a metal structure and devices thereof. A rework method may include forming a first metal layer over an insulating layer having a contact plug, a metal interconnection layer over a first metal layer and/or a second metal layer over a metal interconnection layer. A rework method... Agent: Sherr & Vaughn, PLLC

20100155793 - Self aligned field effect transistor structure: Provided is a self aligned filed effect transistor structure. The self aligned field effect transistor structure includes: an active region on a substrate; a U-shaped gate insulation pattern on the active region; and a gate electrode self-aligned by the gate insulation pattern and disposed in an inner space of the... Agent: Rabin & Berdo, PC

20100155795 - Semiconductor device and method for manufacturing the same: A semiconductor device according to an embodiment includes: a substrate on which a source/drain region is formed; a gate oxide that includes a first oxide formed on the substrate and implanted with fluorine impurity, and a second oxide formed on the first oxide; a gate electrode that is formed on... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20100155792 - Transparent transistor and method of manufacturing the same: Provided is a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the... Agent: Rabin & Berdo, PC

20100155797 - Cmos image sensors: CMOS image sensors and methods of manufacturing the same are provided, the CMOS image sensors include an epitaxial layer, a photodiode, a transfer transistor, CMOS transistors, first metal wirings and a second metal wiring formed on a substrate. The substrate may have a photodiode region, a floating diffusion region, an... Agent: Harness, Dickey & Pierce, P.L.C

20100155796 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate, a back side drawn electrode formed by embedding a first conductive material in a contact hole penetrating the semiconductor substrate through an insulating film formed to include a uniform thickness, used also as an alignment mark, and configured to draw out an electrode... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100155800 - Creating integrated circuit capacitance from gate array structures: Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for... Agent: Ibm Corporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20100155799 - Semiconductor device and method for manufacturing the same: A first MOS transistor includes, as a first impurity region, a pair of first source/drain regions including first portions formed in a semiconductor substrate and second portions formed so as to project upward from the first portions. A second MOS transistor includes a pair of second source/drain regions including second... Agent: Foley And Lardner LLP Suite 500

20100155798 - Semiconductor memory device including cell isolation structure using inactive transistors: Disclosed herein is a semiconductor memory device including floating body cells. The semiconductor memory device includes memory cell active regions formed on a Silicon-On Isolator (SOI) semiconductor substrate, a plurality of floating body cell transistors formed in the memory cell active regions, and inactive transistors for providing cell isolation that... Agent: Ip & T Law Firm PLC

20100155801 - Integrated circuit, 1t-1c embedded memory cell containing same, and method of manufacturing 1t-1c memory cell for embedded memory application: An integrated circuit includes a semiconducting substrate (110), electrically conductive layers (120) over the semiconducting substrate, and a capacitor (130) at least partially embedded within the semiconducting substrate such that the capacitor is entirely underneath the electrically conductive layers. A storage node voltage is on an outside layer (132) of... Agent: Intel Corporation C/o Cpa Global

20100155802 - Semiconductor device and method of forming semiconductor device: A method of forming a semiconductor device includes the following processes. First grooves are formed in a first insulating layer. A conductive material is formed which fills in each of the first grooves. A first mask is formed over the first insulating layer and the conductive material. The first mask... Agent: Mcginn Intellectual Property Law Group, PLLC

20100155803 - Method and structure for integrating capacitor-less memory cell with logic: Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate. Integrated circuits with capacitor-less memory cells formed on a surface of a logic device... Agent: Trask Britt, P.C./ Micron Technology

20100155805 - Nonvolatile semiconductor memory device and fabricating the same: There is provided a nonvolatile semiconductor memory device, including, a tunnel insulator, a floating gate electrode including a first floating gate electrode and a second floating gate electrode being constituted with a nondegenerate state semiconductor, an intergate insulating film formed to cover at least continuously an upper and a portion... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20100155806 - Semiconductor device: A semiconductor device includes an active zone doped according to a first type; a drain zone formed in the active zone and doped according to a second type; a source zone formed in the active zone and doped according to the second type; an insulated gate zone separated from the... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20100155804 - Shallow trench isolation for a memory: In some embodiments, a gate structure with a spacer on its side may be used as a mask to form self-aligned trenches in a microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in... Agent: Trop, Pruner & Hu, P.C.

20100155807 - Apparatus and methods for improved flash cell characteristics: Embodiments of an apparatus and methods for providing improved flash memory cell characteristics are generally described herein. Other embodiments may be described and claimed.... Agent: Intel Corporation C/o Cpa Global

20100155810 - Multi-layer nonvolatile memory devices having vertical charge storage regions: Some embodiments of the present invention provide nonvolatile memory devices including a plurality of intergate insulating patterns and a plurality of cell gate patterns that are alternately and vertically stacked on a substrate, an active pattern disposed on the substrate, the active pattern extending upwardly along sidewalls of the intergate... Agent: Myers Bigel Sibley & Sajovec

20100155812 - Semiconductor device and method for manufacturing the same: A non-volatile memory of a semiconductor device has a tunnel insulation film provided on the active area; a floating gate electrode provided on the tunnel insulation film; a control gate electrode provided over the floating gate electrode; and an inter-electrode insulation film provided between the floating gate electrode and the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20100155809 - Semiconductor device of common source structure and manufacturing method of semiconductor device of common source structure: A semiconductor device having a common source structure and method of manufacturing the same are provided. In one embodiment, the method includes: forming a plurality of gate lines on a semiconductor substrate, each constituted by a floating gate, a dielectric layer, and a control gate having a line form; forming... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20100155811 - Semiconductor device, method of fabricating the same and flash memory device: A semiconductor device includes a semiconductor substrate, a gate formed over the semiconductor substrate, a source region formed in the semiconductor substrate at one side of the gate, a drain region formed in the semiconductor substrate at another side of the gate, and a channel region formed between the source... Agent: Sherr & Vaughn, PLLC

20100155813 - Semiconductor memory device having stack gate structure and method for manufacturing the same: A semiconductor memory device includes select transistors, cell transistors, and cell units. The select transistors formed on a substrate and include first electrodes. The cell transistors include second electrodes with a charge storage layer and a control. The cell units including a plurality of the cell transistors connected together in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100155808 - Semiconductor memory, semiconductor memory system using the memory, and method for manufacturing quantum dot used in semiconductor memory: A semiconductor memory has a composite floating structure in which quantum dots composed of Si and coated with a Si oxide thin film are deposited on an insulating film formed on a semiconductor substrate, quantum dots coated with a high-dielectric insulating film are deposited on the quantum dots, and quantum... Agent: Foley & Lardner LLP

20100155814 - Eeprom array with well contacts: A semiconductor integrated circuit device includes a cell well, a memory cell array formed on the cell well and having a memory cell area and cell well contact area, first wiring bodies arranged in the memory cell area, and second wiring bodies arranged in the cell well contact area. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100155815 - Ammonia pre-treatment in the fabrication of a memory cell: A method of manufacturing a memory cell 200. The method comprises forming a memory stack 215. Forming the memory stack includes pre-treating an insulating layer 210 in a substantially ammonia atmosphere for a period of more than 5 minutes to thereby form a pre-treated insulating layer 310. Forming the memory... Agent: Texas Instruments Incorporated

20100155823 - Depletion mode bandgap engineered memory: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height;... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20100155820 - Flash memory device and manufacturing method of the same: A flash memory device may include a device isolation layer and an active area formed over a semiconductor substrate, a memory gate formed over the active area, and a control gate formed over the semiconductor substrate including the memory gate, wherein the active area, where a source contact is to... Agent: Sherr & Vaughn, PLLC

20100155816 - Hto offset and bl trench process for memory device to improve device performance: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the... Agent: Turocy & Watson, LLP

20100155817 - Hto offset for long leffective, better device performance: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric... Agent: Turocy & Watson, LLP

20100155819 - Method of fabricating semiconductor device and semiconductor device: A method of fabricating a semiconductor device, includes forming an element isolation trench by processing a silicon substrate and a film to be processed, and filling the element isolation trench with an insulating film by a thermal CVD method. The thermal CVD method in filling the trench is executed under... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20100155822 - Semiconductor memory device with bit line of small resistance and manufacturing method thereof: Respective bit lines running at right angles to a word line are composed of a diffusion bit line formed in a semiconductor substrate and a linear metal bit line on an upper side of the diffusion bit line. The diffusion bit line is formed in a linear pattern on a... Agent: Mcdermott Will & Emery LLP

20100155821 - Stacked non-volatile memory device and methods for fabricating the same: A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20100155818 - Vertical channel type nonvolatile memory device and method for fabricating the same: A method for fabricating, a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of... Agent: Ip & T Law Firm PLC

20100155824 - Nanocrystal memory with differential energy bands and method of formation: A method of making a semiconductor device using a semiconductor substrate includes forming a first insulating layer having a first band energy over the semiconductor substrate. A first semiconductor layer having a second band energy is formed on the first insulating layer. The first semiconductor layer is annealed to form... Agent: Freescale Semiconductor, Inc. Law Department

20100155825 - Transistor devices with nano-crystal gate structures: Embodiments of non-volatile semiconductor devices include a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises a gate dielectric substantially... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20100155826 - Non-volatile memory device and method of fabricating the same: Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a substrate and a plurality of semiconductor pillars on the substrate. A plurality of control gate electrodes may be stacked on the substrate and intersecting the plurality of semiconductor pillars. A... Agent: Harness, Dickey & Pierce, P.L.C

20100155827 - Semiconductor device having a multi-channel type mos transistor: In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate patterns and single crystalline silicon patterns that are alternately stacked with each other. A source/drain layer is formed on a sidewall of the active channel pattern.... Agent: Harness, Dickey & Pierce, P.L.C

20100155829 - Device for protecting semiconductor device from electrostatic discharge and method for fabricating the same: A device for protecting a semiconductor device from electrostatic discharge may include a high voltage first conductivity type well formed in a semiconductor substrate. A first stack region may have a first conductivity type drift region, and a first conductivity type impurity region stacked in succession in the high voltage... Agent: Sherr & Vaughn, PLLC

20100155830 - Electronic switching device: An integrated switching device has a switching IGFET connected between a pair of main terminals, a protector IGFET connected between the drain and gate electrodes of the switching IGFET, and a gate resistor connected between a main control terminal and the gate electrode of the switching IGFET. The protector IGFET... Agent: Woodcock Washburn LLP

20100155828 - Field-effect semiconductor device and method of forming the same: A semiconductor device comprises a semiconductor layer, a body region of a first conductivity type formed in the semiconductor layer and extending from a first surface of the semiconductor layer, a first region of a second conductivity type formed in the body region, and a second region of the first... Agent: Larson Newman & Abel, LLP

20100155831 - Deep trench insulated gate bipolar transistor: In one embodiment, a power transistor device comprises a substrate of a first conductivity type that forms a PN junction with an overlying buffer layer of a second conductivity type. The power transistor device further includes a first region of the second conductivity type, a drift region of the second... Agent: The Law Offices Of Bradley J. Bereznak

20100155832 - Method for fabricating semiconductor memory device: A method for manufacturing a semiconductor device comprises forming a first spacer layer at sidewalls of one or more gate electrodes, forming a trench by etching an isolation insulating layer exposed between the gate electrodes, forming a second spacer layer on sidewalls of the gate electrodes and an inner surface... Agent: Ampacc Law Group

20100155834 - Semiconductor device and a method for manufacturing the same: A semiconductor device includes a semiconductor substrate provided with an active region including a gate forming area, a source forming area and a drain forming area. A recess is formed in the gate forming area. A gate is formed over the gate forming area that is formed with the recess... Agent: Townsend And Townsend And Crew, LLP

20100155833 - Semiconductor device having vertical type mosfet and manufacturing method thereof: A method (and resultant structure) includes forming a semiconductor layer having plural stripe-like trenches, forming a gate electrode buried partially in each of the plural trenches, and introducing an impurity into the semiconductor layer by ion implantation after forming the gate electrode. The gate electrode has a buried portion formed... Agent: Mcginn Intellectual Property Law Group, PLLC

20100155835 - Castellated gate mosfet tetrode capable of fully-depleted operation: A castellated-gate MOSFET tetrode device capable of fully depleted operation is disclosed. The device includes a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed in the semiconductor substrate region, with... Agent: John J. Seliskar

20100155836 - Co-packaging approach for power converters based on planar devices, structure and method: A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a planar vertical diffused metal oxide semiconductor... Agent: Mh2 Technology Law Group, LLP

20100155837 - Single die output power stage using trench-gate low-side and ldmos high-side mosfets, structure and method: A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor... Agent: Mh2 Technology Law Group, LLP

20100155838 - Trench type mosfet device and method of manufacturing the same: A trench type Metal Oxide Silicon Field Effect Transistor (MOSFET) device and a method of manufacturing a trench type MOSFET device. A trench type MOSFET device may include a wide-trench source contact poly which may be formed on and/or over a space between deep-trench gate polys on and/or over a... Agent: Sherr & Vaughn, PLLC

20100155839 - Lateral mosfet with substrate drain connection: In one form a lateral MOSFET includes an active gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, and a non-active gate positioned above the drain... Agent: Hiscock & Barclay, LLP

20100155840 - Power mosfet and fabricating method thereof: A power MOSFET is disclosed. In the power MOSFET, an epitaxial layer doped with dopants of a first conduction type is formed on a substrate. A first trench extends downward from a first region of the top surface of the epitaxial layer, and a second trench extends downward from the... Agent: Birch Stewart Kolasch & Birch

20100155841 - Semiconductor device and method for fabricating the same: A Semiconductor device and method for fabricating the same are disclosed. The method includes implanting first conduction type impurities into a semiconductor substrate to form a first well, implanting second conduction type impurities into the first well to form a second well, implanting second conduction type impurities into the second... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20100155842 - Body contacted hybrid surface semiconductor-on-insulator devices: A portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is patterned into a semiconductor fin having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions having a doping of... Agent: Scully, Scott, Murphy & Presser, P.C.

20100155843 - Field effect transistor with alternate electrical contacts: A field effect transistor including: a support layer, a plurality of active zones based on a semiconductor, each active zone configured to form a channel and arranged between two gates adjacent to each other and consecutive, the active zones and the gates being arranged on the support layer, each gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100155844 - Semiconductor device and method for manufacturing the same: There is provided a semiconductor device having excellent device characteristics in which Vth values of an nMOS transistor and a pMOS transistor are controlled to be desired values. The semiconductor device includes a pMOS transistor and an nMOS transistor formed by using an SOI substrate. The pMOS transistor is a... Agent: Young & Thompson

20100155845 - Semiconductor integrated circuit device: A semiconductor integrated circuit device with a “PAD on I/O cell” structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor... Agent: Miles & Stockbridge PC

20100155846 - Metal-insulator-semiconductor tunneling contacts: A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.... Agent: Intel Corporation C/o Cpa Global

20100155847 - Self aligned field effect transistor structure: Provided is a self aligned field effect transistor structure. The self aligned field effect transistor structure includes: an active region pattern on a substrate; a first gate electrode and a second gate electrode facing each other with the active region pattern therebetween; and a source electrode and a drain electrode... Agent: Rabin & Berdo, PC

20100155848 - Trigate static random-access memory with independent source and drain engineering, and devices made therefrom: A static random-access memory circuit includes at least one access device including source and drain sections for a pass region, at least one pull-up device and at least one pull-down device including source-and-drain sections for a pull-down region. The static random-access memory circuit is configured with external resistivity (Rext) for... Agent: Intel Corporation C/o Cpa Global

20100155851 - Semiconductor device and method for manufacturing the same: There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100155850 - Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions: By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close... Agent: Advanced Mirco Devices, Inc. C/o Williams, Morgan & Amerson

20100155849 - Transistors with metal gate and methods for forming the same: A semiconductor device includes at least one first gate dielectric layer over a substrate. A first transition-metal oxycarbide (MCxOy) containing layer is formed over the at least one first gate dielectric layer, wherein the transition-metal (M) has an atomic percentage of about 40 at. % or more. A first gate... Agent: Birch, Stewart, Kolasch & Birch, LLP

20100155852 - Integrating diverse transistors on the same wafer: Different types of transistors, such as memory cells, higher voltage, and higher performance transistors, may be formed on the same substrate. A transistor may be formed with a first polysilicon layer covered by a dielectric. A second polysilicon layer over the dielectric may be etched to form a sidewall spacer... Agent: Trop, Pruner & Hu, P.C.

20100155853 - Multiplexer and method of manufacturing the same: A multiplexer can include a signal line arranged on a substrate and including a plurality of data wires extending in a first direction and electrically insulated from one another, where each of the data wires has at least one recess to provide at least two data wiring pieces. An address... Agent: Myers Bigel Sibley & Sajovec

20100155855 - Band edge engineered vt offset device: Band edge engineered Vt offset devices, design structures for band edge engineered Vt offset devices and methods of fabricating such structures is provided herein. The structure includes a first FET having a channel of a first compound semiconductor of first atomic proportions resulting in a first band structure and a... Agent: Roberts Mlotkowski Safran & Cole, P.C. Intellectual Property Department

20100155854 - Methods of fabricating semiconductor devices and structures thereof: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. A composition or a thickness of at least one of a plurality of... Agent: Slater & Matsil LLP

20100155856 - Transistor, a transistor arrangement and method thereof: A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor and a device isolation layer of the transistor based on the adjusted gate... Agent: Harness, Dickey & Pierce, P.L.C

20100155857 - A semiconductor device and a method of manufacturing the same and designing the same: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary... Agent: Antonelli, Terry, Stout & Kraus, LLP

20100155858 - Asymmetric extension device: The present invention discloses a semiconductor device with an asymmetric channel extension structure capable of storing charges, improving gate oxide reliability, reducing parasitic capacitance and adjusting its channel extension current or turn-on resistance. A gate dielectric is formed on the semiconductor substrate. A gate is formed on the gate dielectric.... Agent: Birch Stewart Kolasch & Birch

20100155859 - Selective silicide process: A method of self-aligned silicidation on structures having high aspect ratios involves depositing a metal oxide film using atomic layer deposition (ALD) and converting the metal oxide film to metal film in order to obtain uniform step coverage. The substrate is then annealed such that the metal in regions directly... Agent: Knobbe Martens Olson & Bear LLP

20100155860 - Two step method to create a gate electrode using a physical vapor deposited layer and a chemical vapor deposited layer: One embodiment of the present invention relates a semiconductor device formed by utilizing a two step deposition method for forming a gate electrode without causing damages to an underlying gate dielectric material. In one embodiment, a first layer of gate electrode material (first gate electrode layer) is formed onto the... Agent: Texas Instruments Incorporated

20100155861 - Microelectromechanical device with isolated microstructures and method of producing same: A microelectromechanical systems (MEMS) device (20) includes a polysilicon structural layer (46) having movable microstructures (28) formed therein and suspended above a substrate (22). Isolation trenches (56) extend through the layer (46) such that the microstructures (28) are laterally anchored to the isolation trenches (56). A sacrificial layer (22) is... Agent: Meschkow & Gresham, P.L.C

20100155862 - Package for electronic component, manufacturing method thereof and sensing apparatus: A package for electronic component comprises a rectangular package body having a flat cut surface to be abutted on a flat mounting surface of a mounting substrate, a first side surface intersecting with the flat cut surface, and a first notch part formed at a boundary between the flat cut... Agent: Drinker Biddle & Reath (dc)

20100155864 - Mems process and device: A MEMS device, for example a capacitive microphone, comprises a flexible membrane 11 that is free to move in response to pressure differences generated by sound waves. A first electrode 13 is mechanically coupled to the flexible membrane 11, and together form a first capacitive plate of the capacitive microphone... Agent: Dickstein Shapiro LLP

20100155863 - Method for manufacturing a microelectronic package comprising a silicon mems microphone: A method for manufacturing a microelectronic package comprising a silicon MEMS microphone comprises the following steps: providing a basic panel (100) having several rows of interconnected substrates (90), wherein the substrates (90) are provided with electrically conductive connection pads (31), electrically conductive tracks (33), and a grid (40) comprising tiny... Agent: Philips Intellectual Property & Standards

20100155865 - Semiconductor device and method of making the same: A semiconductor device includes a sensor portion, a cap portion, and an ion-implanted layer. The sensor portion has a sensor structure at a surface portion of a surface. The cap portion has first and second surfaces opposite to each other and includes a through electrode. The surface of the sensor... Agent: Posz Law Group, PLC

20100155866 - High temperature resistant solid state pressure sensor: A harsh environment transducer including a substrate having a first surface and a second surface, wherein the second surface is in communication with the environment. The transducer includes a device layer sensor means located on the substrate for measuring a parameter associated with the environment. The sensor means including a... Agent: Thompson Hine L.L.P. Intellectual Property Group

20100155868 - Image sensor and manufacturing method thereof: Disclosed are an image sensor and a manufacturing method thereof. The image sensor includes a circuit layer on a first surface of a semiconductor substrate, a metal interconnection layer on the circuit layer, trenches formed in a second surface of the semiconductor substrate along a boundary of a pixel, and... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20100155870 - Light guide array for an image sensor: An image sensor pixel that includes a photoelectric conversion unit supported by a substrate and an insulator adjacent to the substrate. The pixel includes a light guide that is located within an opening of the insulator and extends above the insulator such that a portion of the light guide has... Agent: Hiok Nam Tay

20100155869 - Method of manufacturing solid-state image pickup device and solid-state image pickup device: A method includes preparing a cover member; preparing an image pickup element including a substrate including a pixel region including a plurality of photo detectors on a principal surface, a first concavo-convex portion including a plurality of first convex portions configured to concentrate light on the plurality of photo detectors,... Agent: Canon U.s.a. Inc. Intellectual Property Division

20100155867 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device (1) includes a plurality of photodiodes (20) on a semiconductor substrate (11). Cathodes (22) and a common anode (21) of the plurality of photodiodes (20 (20a, 20b)) are formed so as to be electrically independent from the semiconductor substrate (11), the plurality of photodiodes (20) have the... Agent: K&l Gates LLP

20100155871 - Silicone resin composition: A silicone resin composition containing (i) a silicone resin and (ii) fine metal oxide particles without having a reactive functional group or with a protected reactive functional group on the surface thereof (fine metal oxide particles B), wherein the silicone resin is obtained by carrying out a polymerization reaction between... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100155872 - Image sensor and manufacturing method of image sensor: An image sensor includes a trench formed in a semiconductor substrate, a first reflection part formed in the trench and having an inclined, curved surface, a second reflection part formed on the first reflection part such that a remaining space of the trench is filled with the second reflection part,... Agent: Sherr & Vaughn, PLLC

20100155873 - Image sensor and method for manufacturing the same: A backside illumination (BSI) image sensor having a light receiving part at the wafer or die backside, and a manufacturing method thereof, are disclosed. The method includes polishing the light receiving part so that a super via protrudes, forming a first insulating layer to cover the protruding super via and... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20100155874 - Front side illuminated, back-side contact double-sided pn-junction photodiode arrays: The present invention is a photodiode detector array for use in computerized tomography (CT) and non-CT applications. Specifically, the present invention is a high-density photodiode arrays, with low dark current, low capacitance, high signal to noise ratio, high speed, and low crosstalk that can be fabricated on relatively large substrate... Agent: Patentmetrix

20100155875 - Semiconductor device provided with photodiode, manufacturing method thereof, and optical disc device: A semiconductor device includes: a P-type semiconductor substrate; a first P-type semiconductor layer formed on the P-type semiconductor substrate; a second P-type semiconductor layer formed on the first P-type semiconductor layer and having a lower P-type impurity concentration than the first P-type semiconductor layer; an N-type semiconductor layer, which will... Agent: Rader Fishman & Grauer PLLC

20100155876 - Junction barrier schottky (jbs) with floating islands: A Schottky diode includes a Schottky barrier and a plurality of dopant regions disposed near the Schottky barrier as floating islands to function as PN junctions for preventing a leakage current generated from a reverse voltage. At least a trench opened in a semiconductor substrate with a Schottky barrier material... Agent: Bo-in Lin

20100155877 - novel schottky diode for high speed and radio frequency application: A semiconductor diode that is disclosed. An exemplary semiconductor diode includes a portion of a semiconductor substrate including a first dopant, a first well with a Schottky region, and a second well with a second dopant; and an isolation region replacement element positioned over the semiconductor substrate and adjacent to... Agent: Haynes And Boone, LLPIPSection

20100155878 - Configuration of high-voltage semiconductor power device to achieve three dimensional charge coupling: This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on... Agent: Bo-in Lin

20100155879 - Semiconductor device: A semiconductor device is provided that comprises a semiconductor substrate comprising an active area and a peripheral region adjacent the active area and structure positioned in the peripheral region for hindering the diffusion of mobile ions from the peripheral region into the active area.... Agent: Dicke, Billig & Czaja

20100155880 - Back gate doping for soi substrates: A silicon-on-insulator (SOI) substrate comprises a base silicon substrate having a back gate region, wherein the back gate region has a first dopant concentration that is greater than 1×1017 cm−3, a nitrogen layer adjacent to the back gate region of the base silicon substrate, a BOX layer adjacent to the... Agent: Intel Corporation C/o Cpa Global

20100155881 - Forming isolation regions for integrated circuits: A substrate may have active areas at different levels separated by a mask. Along the mask may be a shallow trench isolation. Along the shallow trench isolation may be a LOCOS isolation. The shape of a substrate transition region between the levels may be tunably controlled. The shallow trench isolation... Agent: Trop, Pruner & Hu, P.C.

20100155882 - Method for bonding two substrates: The invention relates to a method for bonding two substrates by applying an activation treatment to at least one of the substrates, and performing the contacting step of the two substrates under partial vacuum. Due to the combination of the two steps, it is possible to carry out the bonding... Agent: Winston & Strawn LLP Patent Department

20100155883 - Integrated mems and ic systems and related methods: An integrated MEMS and IC system (MEMSIC), as well as related methods, are described herein. According to some embodiments, a mechanical resonating structure is coupled to an electrical circuit (e.g., field-effect transistor). For example, the mechanical resonating structure may be coupled to a gate of a transistor. In some cases,... Agent: Wolf Greenfield & Sacks, P.C.

20100155885 - Fuse corner pad for an integrated circuit: A fuse corner pad is part of an integrated circuit that includes a built-in fuse contact and a plurality of auxiliary pads. The fuse contact is a conductive metallic or metalloid structure that is connected to a fuse element. The fuse contact and fuse element are used inside of the... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20100155884 - Melting fuse of semiconductor and method for forming the same: The present invention discloses a fuse of a semiconductor device and manufacturing method thereof. The fuse of a semiconductor device of the present invention includes a first conductive pattern; and a second conductive pattern which is separated from the first conductive pattern with a given gap, wherein the first conductive... Agent: Ampacc Law Group

20100155886 - Semiconductor device: A semiconductor device is provided. The semiconductor device includes a chip having a plurality of first power voltage terminals connected in common to a first power voltage line, a plurality of second power voltage terminals connected in common with a second power voltage line, a first connection terminal, a second... Agent: Volentine & Whitt PLLC

20100155889 - Capacitor and method for fabricating the same: A capacitor includes a lower electrode; a dielectric layer formed on a predetermined portion of the lower electrode; an upper electrode formed on the dielectric layer; a hard mask pattern formed on the upper electrode; and an isolation layer having a shape of a spacer, formed on one sidewall... Agent: Morgan Lewis & Bockius LLP

20100155887 - Common plate capacitor array connections, and processes of making same: A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary... Agent: Intel Corporation C/o Cpa Global

20100155890 - Mim capacitor of semiconductor device and manufacturing method thereof: A method of manufacturing a MIM capacitor of a semiconductor device and a MIM capacitor. A MIM structure and a metal layer may be formed using a single process. A method of manufacturing a MIM capacitor may include forming a hole on and/or over a lower metal wire region. A... Agent: Sherr & Vaughn, PLLC

20100155892 - Semiconductor constructions: Some embodiments include methods of forming semiconductor constructions. Oxide is formed over a substrate, and first material is formed over the oxide. Second material is formed over the first material. The second material may be one or both of polycrystalline and amorphous silicon. A third material is formed over the... Agent: Wells St. John P.s.

20100155891 - Semiconductor device having cylindrical lower electrode of capacitor and manufacturing method thereof: To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in... Agent: Young & Thompson

20100155888 - Silicon interposer testing for three dimensional chip stack: A testing method for a silicon interposer employs a test probe and an electrically conductive glass handler. The silicon interposer includes multiple interconnects that extend between the opposed major surfaces of the interposer, namely from a test side of the interposer to a conductive glass handler side of the interposer.... Agent: Mark P. Kahler

20100155893 - Method for forming thin film resistor and terminal bond pad simultaneously: Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.... Agent: Roberts Mlotkowski Safran & Cole, P.C. Intellectual Property Department

20100155894 - Fabricating bipolar junction select transistors for semiconductor memories: A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to... Agent: Trop, Pruner & Hu, P.C.

20100155895 - Power semiconductor device: A power semiconductor device includes a P type silicon substrate; a deep N well in the P type silicon substrate; a P grade region in the deep N well; a P+ drain region in the P grade region; a first STI region in the P grade region; a second STI... Agent: North America Intellectual Property Corporation

20100155896 - High-frequency bipolar transistor and method for the production thereof: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20100155897 - Deep trench varactors: A deep trench varactor structure compatible with a deep trench capacitor structure and methods of manufacturing the same are provided. A buried plate layer is formed on a second deep trench, while the first trench is protected from formation of any buried plate layer. The inside of the deep trenches... Agent: Scully, Scott, Murphy & Presser, P.C.

20100155898 - Method for enhancing tensile stress and source/drain activiation using si:c: A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing a series of ion implantation steps at predetermined implant energies to implant carbon ions deep within the semiconductor structure to create a strain layer. The strain layer is annealed using... Agent: Varian Semiconductor Equipment Assc., Inc.

20100155899 - Etching method, etching mask and method for manufacturing semiconductor device using the same: An etching method forms a metal-fluoride layer at a temperature of 150° C. or higher at least as a part of an etching mask formed over a semiconductor layer; patterns the metal-fluoride layer; and etches the semiconductor layer using the patterned metal-fluoride layer as a mask. According to the etching... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100155900 - Fabricating a gallium nitride device with a diamond layer:

20100155901 - Fabricating a gallium nitride layer with diamond layers: In one aspect, a method includes fabricating a gallium nitride (GaN) layer with a first diamond layer having a first thermal conductivity and a second diamond layer having a second thermal conductivity greater than the first thermal conductivity. The fabricating includes using a microwave plasma chemical vapor deposition (CVD) process... Agent: Raytheon Company C/o Daly, Crowley, Mofford & Durkee, LLP

20100155902 - Manufacturing method of nitride substrate, nitride substrate, and nitride-based semiconductor device: A manufacturing method of a nitride substrate includes the steps of: preparing a ground substrate; forming a mask on the ground substrate; placing the ground substrate in a reactor, and heating the ground substrate to a temperature of 850° C. to 1100° C. In the step of heating the ground... Agent: Drinker Biddle & Reath (dc)

20100155903 - Annealed wafer and method for producing annealed wafer: An annealed wafer having enhanced gettering effects for Cu is produced by heating a silicon substrate containing a nitrogen concentration of 5×1014 to 1×1016/cm3, a carbon concentration of 1×1015 to 5×1016/cm3, and an oxygen concentration of 6×1017 to 11×1017/cm3 at a temperature of 650 to 800° C. for a time... Agent: Brooks Kushman P.C.

20100155905 - Semiconductor device and its manufacturing method: A device portion forming step includes an assisting layer forming step of forming a planarization assisting layer, which covers a plurality of conductive films, over a first planarizing layer before forming a second planarizing layer. In the assisting layer forming step, the planarization assisting layer is formed so that a... Agent: Birch Stewart Kolasch & Birch

20100155904 - Semiconductor device having cmp dummy pattern and method for manufacturing the same: A semiconductor device including a CMP dummy pattern and a method for manufacturing the same are provided. The warpage of a wafer can be prevented by forming the CMP dummy pattern in the same direction and/or at the same angle as a pattern of a cell region. Accordingly, overlay error... Agent: Ampacc Law Group

20100155906 - Semiconductor device and method of forming patterns for the semiconductor device: Provided are a method of forming patterns for a semiconductor device in which a pattern density is doubled by performing double patterning in a part of a device region while patterns having different widths are being simultaneously formed, and a semiconductor device having a structure to which the method is... Agent: Myers Bigel Sibley & Sajovec

20100155907 - Semiconductor device having an inorganic coating layer applied over a junction termination extension: A semiconductor device includes an inorganic coating layer to at least partially cover a junction termination extension.... Agent: Carlson, Gaskey & Olds/pratt & Whitney

20100155908 - Passivation structure and fabricating method thereof: A passivation structure and fabricating method thereof includes providing a chip having a main die region and a scribe line region defined thereon and a plurality of metal pads respectively positioned in the main die region and the scribe line region, forming a first patterned passivation layer having a plurality... Agent: North America Intellectual Property Corporation

20100155909 - Method to enhance charge trapping: Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be... Agent: Varian Semiconductor Equipment Assc., Inc.

20100155910 - Method for the selective antireflection coating of a semiconductor interface by a particular process implementation: The invention refers to an efficient process for selectively rendering a semiconductor surface antireflective which is part of integrated circuits. The antireflective effect is based interference effects of a simple layer or a layer system. For example, an oxide layer and super-imposed silicon nitride layer form the system, wherein the... Agent: Hunton & Williams LLP Intellectual Property Department

20100155911 - Esd protection diode in rf pads: A diode is provided. The diode includes first and second diffusion layers formed in a substrate, a first metal coupled to the first diffusion layer, and a second metal coupled to the second diffusion layer that has width that is smaller than a width of the second diffusion layer.... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20100155912 - Apparatus for shielding integrated circuit devices: A high reliability radiation shielding integrated circuit apparatus comprising a plurality of package layers; a radiation shielding lid or base coupled to the plurality of package layers; wherein the circuit die are shielded from receiving an amount of radiation greater than the total dose of tolerance of the circuit die.... Agent: Maxwell Technologies, Inc. (oplf)

20100155913 - Thermally enhanced thin semiconductor package: A semiconductor die package is disclosed. The semiconductor die package includes a semiconductor die comprising an input at a first top semiconductor die surface and an output at a second bottom semiconductor die surface. A leadframe having a first leadframe surface and a second leadframe surface opposite the first leadframe... Agent: Townsend And Townsend And Crew, LLP

20100155914 - Power module having stacked flip-chip and method of fabricating the power module: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame;... Agent: Townsend And Townsend And Crew, LLP

20100155916 - Chip package structure and the method thereof with adhering the chips to a frame and forming ubm layers: A chip package structure includes a chip-placed frame that having an adhesive layer thereon; a chip includes a plurality of pads on an active surface thereon, and is provided on the adhesive layer; a package structure is covered around the four sides of the chip-placed frame, and the height of... Agent: Sinorica, LLC

20100155915 - Stacked power converter structure and method: A power converter can include an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The power converter can further include a controller integrated circuit (IC) formed on a different die which can be electrically coupled to, and co-packaged... Agent: Mh2 Technology Law Group, LLP

20100155917 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a semiconductor element having a light receiving region or a light emitting region on which a transparent member is attached, and a plurality of electrode pads; a substrate on which the semiconductor element is provided; and a resin covering the semiconductor element and side surfaces of... Agent: Mcdermott Will & Emery LLP

20100155919 - High-density multifunctional pop-type multi-chip package structure: Provided is a high-capacity multifunctional multichip package (MCP) structure in which a multifunctional MCP capable of, for example, high-speed image processing and communications, is mounted on a high-capacity memory package capable of storing various data, e.g., moving images, pictures, or music files. The high-capacity memory package may be efficiently applied... Agent: Harness, Dickey & Pierce, P.L.C

20100155918 - Integrated circuit packaging system with package stacking and method of manufacture thereof: A method of manufacture of an integrated circuit packaging system includes: providing a stack board with a side having a connect contact next to a connect edge and a top contact next to a top edge perpendicular to the connect edge, and a bottom contact on an opposite side; mounting... Agent: Law Offices Of Mikio Ishimaru

20100155921 - Semiconductor apparatus: The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology... Agent: Miles & Stockbridge PC

20100155922 - Semiconductor device and method of forming recessed conductive vias in saw streets: A semiconductor die has an insulating material disposed in a peripheral region around the die. A blind via is formed through the gap. A conductive material is deposited in the blind via to form a conductive via. A conductive layer is formed between the conductive via and contact pad on... Agent: Robert D. Atkins

20100155920 - Stacked semiconductor package, semiconductor package module and method of manufacturing the stacked semiconductor package: Provided are a stacked-type semiconductor package using a stud bump, a semiconductor package module, and a method of fabricating the stacked-type semiconductor package. The stacked-type semiconductor package may include a first semiconductor package and a second semiconductor package stacked on the first semiconductor package. The first semiconductor package may include... Agent: Harness, Dickey & Pierce, P.L.C

20100155926 - Integrated circuit packaging system for fine pitch substrates and method of manufacture thereof: A method of manufacture of an integrated circuit packaging system includes: forming a substrate including: patterning a bonding pad on the substrate, patterning a first signal trace coupled to the bonding pad, patterning a second signal trace on the substrate, and connecting a pedestal on the second signal trace; mounting... Agent: Law Offices Of Mikio Ishimaru

20100155923 - Microball assembly methods, and packages using maskless microball assemblies: A method of forming a microball grid array includes adhering a microball precursor material to a transfer medium under conditions to reflect a selective charge pattern. The method includes transferring the microball precursor material from the transfer medium across a gap and to an integrated circuit substrate under conditions to... Agent: Intel Corporation C/o Cpa Global

20100155925 - Resin-sealed package and method of producing the same: A method of producing a resin-sealed package is provided with: providing an electronic component which has a plurality of terminals on one face, a first support member and a second support member; temporarily fixing said electronic component to a surface of said first support member by a first adhesive agent... Agent: Rankin, Hill & Clark LLP

20100155924 - Semiconductor module: A semiconductor module includes first and second sub-units, each including at least one semiconductor chip, a first contact element having a first contact side, and a second or third contact element having a second or third contact side, respectively. The semiconductor chip has opposing first and second main electrode sides.... Agent: Buchanan, Ingersoll & Rooney PC

20100155927 - Semiconductor packages with stiffening support for power delivery: Embodiments of the invention relate to semiconductor packages in which electrical power is delivered to die-side components removably installed in sockets formed between a package stiffener and an electrical conductor. To this purpose, the package stiffener and the electrical conductor may be electrically coupled to the power and ground terminals... Agent: Intel Corporation C/o Cpa Global

20100155929 - Chip-stacked package structure: A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100155928 - Semiconductor package and manufacturing method of the same: A semiconductor package includes: a wiring board; and a semiconductor device which is formed on the wiring board; wherein the semiconductor device includes: a semiconductor chip; and a penetration electrode, one end of which is fixed on one plane of the semiconductor chip, and the other end of which penetrates... Agent: Rankin, Hill & Clark LLP

20100155930 - Stackable semiconductor device assemblies: A semiconductor device assembly includes a substrate and a semiconductor die adjacent to a first surface of the substrate. The substrate also includes a second surface opposite from the first surface, an opening extending from the first surface and the second surface, contact pads on the first surface, and substrate... Agent: Trask Britt, P.C./ Micron Technology

20100155932 - Bonded semiconductor substrate including a cooling mechanism: A bonded substrate comprising two semiconductor substrates is provided. Each semiconductor substrate includes semiconductor devices. At least one through substrate via is provided between the two semiconductor substrates to provide a signal path therebetween. The bottom sides of the two semiconductor substrate are bonded by at least one bonding material... Agent: Scully, Scott, Murphy & Presser, P.C.

20100155931 - Embedded through silicon stack 3-d die in a package substrate: An integrated circuit package has a die or die stack with through silicon vias embedded in a package substrate. A method of producing an integrated circuit package embeds at least one die with a through silicon via in a package substrate. The package substrate provides a protective cover for the... Agent: Qualcomm Incorporated

20100155933 - Package for semiconductor devices: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed... Agent: Staas & Halsey LLP

20100155934 - Molding compound including a carbon nano-tube dispersion: A molding compound comprising a resin, a filler, and a carbon nano-tube dispersion is disclosed. The carbon nano-tube dispersion achieves a low average agglomeration size in the molding compound thereby providing desirable electromechanical properties and laser marking compatibility. A shallow laser mark may be formed in a mold cap with... Agent: Gerbera/bstz Blakely Sokoloff Taylor & Zafman LLP

20100155935 - Protective coating for semiconductor substrates: Methods for coating a protective material on a semiconductor substrate to protect a back surface thereof from defects are provided, by depositing a diamond-like coating (DLC) material thereon at a low temperature, e.g. between about 150° C. to about 350° C.... Agent: Intel Corporation C/o Cpa Global

20100155936 - Method of thinning a semiconductor substrate: A C4 grind tape and a laser-ablative adhesive layer are formed on a front side of a semiconductor substrate. A carrier substrate is thereafter attached to the laser-ablative adhesive layer. The back side of the semiconductor substrate is thinned by polishing or grinding, during which the carrier substrate provides mechanical... Agent: Scully, Scott, Murphy & Presser, P.C.

20100155939 - Circuit board and fabrication method thereof and chip package structure: A fabrication method of a circuit board is provided. A substrate, a top pad, a base pad electrically connecting the top pad, and a top and a base solder resist layers are provided. The top and the base pads are disposed on two opposite surfaces of the substrate, respectively. The... Agent: J C Patents

20100155938 - Face-to-face (f2f) hybrid structure for an integrated circuit: An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder... Agent: Vedder Price P.C.

20100155943 - Semiconductor chip used in flip chip process: A semiconductor chip for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to... Agent: Schmeiser, Olsen & Watts

20100155941 - Semiconductor device: A semiconductor device includes multiple electrode pads provided in an interconnection layer over a semiconductor substrate; an insulating layer provided on the interconnection layer so as to expose portions of the electrode pads; multiple conductive layers having their respective first ends connected to the exposed portions of the corresponding electrode... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20100155944 - Semiconductor device: A semiconductor device including: a semiconductor substrate including an electrode; a resin protrusion formed on the semiconductor substrate and including a plurality of first portions and a second portion disposed between two of the first portions adjacent to each other; and an interconnect electrically connected to the electrode and extending... Agent: Harness, Dickey & Pierce, P.L.C

20100155945 - Semiconductor device: A semiconductor device including: a semiconductor chip; a plurality of electrodes formed on the semiconductor chip and arranged along one side of the semiconductor chip; a resin protrusion formed on the semiconductor chip and extending in a direction which intersects the side; and a plurality of electrical connection sections formed... Agent: Harness, Dickey & Pierce, P.L.C

20100155942 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a connection electrode formed on a side of a semiconductor element substrate opposed to a bump, where the semiconductor element substrate includes a semiconductor element; a passivation layer covering the semiconductor element substrate and an end portion of the connection electrode; and a barrier metal layer... Agent: Mcdermott Will & Emery LLP

20100155940 - Semiconductor device and method of manufacturing the same: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a... Agent: Brundidge & Stanger, P.C.

20100155937 - Wafer structure with conductive bumps and fabrication method thereof: A wafer structure with conductive bumps and fabrication method thereof are disclosed herein. Conductive bumps are later converted into conductive balls. A central area and a marginal area are defined on the wafer. To achieve heights among conductive balls formed on the wafer structure, the sizes (can be but not... Agent: Rosenberg, Klein & Lee

20100155946 - Solder limiting layer for integrated circuit die copper bumps: An apparatus comprises a semiconductor substrate having a device layer, a plurality of metallization layers, a passivation layer, and a metal bump formed on the passivation layer that is electrically coupled to at least one of the metallization layers. The apparatus further includes a solder limiting layer formed on the... Agent: Intel Corporation C/o Cpa Global

20100155947 - Solder joints with enhanced electromigration resistance: Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight percent Cu and at least one dopant selected... Agent: Konrad Raynes & Victor, LLP. Attn: Int77

20100155948 - Tooling method for fabricating a semiconductor device and semiconductor devices fabricated thereof: A tooling method for fabricating semiconductor devices includes identifying two adjacent device lines having a device-to-device spacing width in an active region of a substrate, performing an operation to selectively define a first region as a region between the two adjacent device lines overlapping the active region, forming a first... Agent: North America Intellectual Property Corporation

20100155953 - Conductive oxide electrodes: Conductive oxide electrodes are described, including a bi-layer barrier structure electrically coupled with an adhesion layer, and an electrode layer, wherein the bi-layer barrier structure includes a first barrier layer electrically coupled with the adhesion layer, and a second barrier layer electrically coupled with the first barrier layer and to... Agent: Unity Semiconductor Corporation

20100155951 - Copper interconnection structure and method for forming copper interconnections: A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer, and a diffusion barrier layer formed between the insulating layer and the interconnection body. The diffusion barrier layer includes an oxide layer including manganese having a compositional ratio of... Agent: Masuvalley & Partners

20100155952 - Copper interconnection structures and semiconductor devices: A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer and a barrier layer including a metal element and copper, formed between the insulating layer and the interconnection body. An atomic concentration of the metal element in the barrier... Agent: Masuvalley & Partners

20100155950 - Implementation of a metal barrier in an integrated electronic circuit: A metal barrier is realized on top of a metal portion of a semiconductor product, by forming a metal layer on the surface of the metal portion, with this metal layer comprising a cobalt-based metal material. Then, after an optional deoxidation step, a silicidation step and a nitridation step of... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20100155949 - Low cost process flow for fabrication of metal capping layer over copper interconnects: Semiconductor devices and methods are disclosed for improving electrical connections to integrated circuits. A process flow and device with a dual/single damascene interconnect structure overlying an existing interconnect structure in a semiconductor wafer is provided. A capping layer is formed thereon that comprises nickel/palladium layers within a bond pad opening.... Agent: Texas Instruments Incorporated

20100155954 - Methods of forming low interface resistance rare earth metal contacts and structures formed thereby: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a contact opening in an inter layer dielectric (ILD) disposed on a substrate, wherein a source/drain contact area is exposed, forming a rare earth metal layer on the source/drain contact area, forming a transition... Agent: Intel Corporation C/o Cpa Global

20100155955 - Method for manufacturing system-in-package: A method of manufacturing a System In Package (SIP) and devices thereof. A method of manufacturing a SIP may include providing a first chip having a first substrate region and/or a first metal connection portion. A method of manufacturing a SIP may include providing a second chip having a second... Agent: Sherr & Vaughn, PLLC

20100155958 - Bonding pad structure and manufacturing method thereof: A bonding pad structure of a semiconductor device and a method of manufacturing the same reduce the likelihood of peel-off defects from occurring. The bonding pad structure includes a substrate, an interlayer insulation layer on the substrate, an upper wiring layer on the interlayer insulation layer, and a plurality of... Agent: Volentine & Whitt PLLC

20100155956 - Fill patterning for symmetrical circuits: A fill-placement method, according to which symmetrical fill patterns are used to insert fill tiles into one or more interconnect levels corresponding to symmetrical circuitry. The fill-placement method can be used, for example, in the fabrication of an integrated circuit having at least two complementary portions for which relatively tight... Agent: Mendelsohn, Drucker, & Associates, P.C.

20100155957 - Pad layout structure of semiconductor chip: Provided is a pad layout structure of a semiconductor chip capable of preventing lead-broken problems when packaging the semiconductor chip with a high aspect ratio in a tape carrier package (TCP). In the pad layout structure of the semiconductor chip, a plurality pads are arranged along upper, lower, left and... Agent: Jae Y. Park

20100155960 - Semiconductor device: The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like... Agent: Mcdermott Will & Emery LLP

20100155959 - Semiconductor devices having narrow conductive line patterns and related methods of forming such semiconductor devices: Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning. The semiconductor device includes a plurality of conductive lines each including a first line portion... Agent: Myers Bigel Sibley & Sajovec

20100155963 - Dummy vias for damascene process: An integrated circuit device and method of making the integrated circuit device are disclosed. An exemplary apparatus includes: a semiconductor layer; and a dielectric layer on the semiconductor layer, the dielectric layer having conductive vias and dummy vias formed therein, wherein the conductive vias and dummy vias extend varying distances... Agent: David M. O'dell Haynes And Boone, LLP

20100155961 - Micromechanical component having wafer through-plating and corresponding production method: A wafer through-plating through a semiconductor substrate and a method for producing this wafer through-plating. At least one via hole is inserted in the front side of a semiconductor substrate, in this context, in order to form the wafer through-plating using a trench etching process. The semiconductor material of the... Agent: Kenyon & Kenyon LLP

20100155962 - Semiconductor device and method for fabricating the same: A semiconductor device includes a semiconductor substrate, a diffusion region provided on a surface portion of a first surface of the semiconductor substrate, a first line provided on the first surface of the semiconductor substrate, a through-hole penetrating the semiconductor substrate in the thickness direction, and a through-hole electrode provided... Agent: Mcdermott Will & Emery LLP

20100155964 - Adhesive tape, semiconductor package and electronics: An adhesive tape electrically connecting conductive members contains a resin, a solder powder and a curing agent having flux activity, wherein the solder powder and the curing agent having flux activity are contained in the resin.... Agent: Smith, Gambrell & Russell

20100155965 - Semiconductor device: A semiconductor device includes: the mounting surface of the wiring substrate exposed from the semiconductor element is covered by a solder-resist layer, a part of the solder-resist layer covering the mounting surface of the wiring substrate at a dropping-commencing point at which dropping of a liquid-state under-filling agent filled in... Agent: Rankin, Hill & Clark LLP

20100155966 - Grid array packages: A semiconductor device assembly includes a substrate and a semiconductor die adjacent to a first surface of the substrate. The substrate also includes a second surface opposite from the first surface, an opening extending from the first surface and the second surface, contact pads on the second surface, and substrate... Agent: Trask Britt, P.C./ Micron Technology

20100155967 - Integrated circuits on a wafer and method of producing integrated circuits: Integrated circuits (Ia, Ib) on a wafer (2) comprise first and second integrated circuits (Ia, Ib) which each include an electric circuit (3). Only the first integrated circuits (Ia) comprise each at least one bump (8) not contacting their relevant electric circuits (3).... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100155968 - Overlay metrology target: In one embodiment, a metrology target for determining a relative shift between two or more successive layers of a substrate may comprise; an first structure on a first layer of a substrate and an second structure on a successive layer to the first layer of the substrate arranged to determine... Agent: Lng/kla 2 Joint Customer Number C/o Luedeka, Neely & Graham, P.C.

20100155969 - Resin paste for die bonding, method for manufacturing semiconductor device, and semiconductor device:

20100148141 - Non-volatile programmable device including phase change layer and fabricating method thereof: Provided is a non-volatile programmable device including a first terminal, a first threshold switching layer connected to part of the first terminal, a phase change layer connected to the first threshold switching layer, a second threshold switching layer connected to the phase change layer, a second terminal connected to the... Agent: Ampacc Law Group

20100148142 - Aluminum copper oxide based memory devices and methods for manufacture: Memory devices are described along with methods for manufacturing. A memory device as described herein includes a first electrode and a second electrode. The memory device further includes a diode and an anti-fuse metal-oxide memory element comprising aluminum oxide and copper oxide. The diode and the metal-oxide memory element are... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20100148143 - Nonvolatile memory element, manufacturing method thereof, and nonvolatile semiconductor apparatus using nonvolatile memory element: A nonvolatile semiconductor apparatus of the present invention comprises (103), a second electrode (105), and a resistance variable layer (104) disposed between the first electrode (103) and the second electrode (105), a resistance value of the resistance variable layer being switchable reversibly in response to an electric signal applied between... Agent: Mcdermott Will & Emery LLP

20100148144 - Semiconducting nanoparticles with surface modification: The invention relates to semiconducting nanoparticles. The nanoparticles of the invention comprise a single element or a compound of elements in one or more of groups II, III, IV, V, VI. The nanoparticles have a size in the range of 1 nm to 500 nm, and comprise from 0.1 to... Agent: John S. Pratt, Esq Kilpatrick Stockton, LLP

20100148149 - Elevated led and method of producing such: The present invention relates to light emitting diodes comprising at least one nanowire. The LED according to the invention is an upstanding nanostructure with the nanowire protruding from a substrate. A bulb with a larger diameter than the nanowire is arranged in connection to the nanowire and at an elevated... Agent: Foley And Lardner LLP Suite 500

20100148148 - Fabrication method of a light-emitting element and the light-emitting element: A fabrication method of the light emitting element and its light emitting element are disclosed herein. It utilizes the membrane forming technology to form optic films arranged in array on a substrate and then upward forming the epitaxial layer by the epitaxial lateral overgrowth (ELOG) technology so as to form... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20100148150 - Group iii nitride compound semiconductor light emitting device and manufacturing method thereof: A Group III nitride compound semiconductor light emitting device is provided which has: an n-type semiconductor layer (12); an active layer (13) of a multiple quantum well structure laminated on the n-type semiconductor layer (12); a first p-type semiconductor layer (14) that is a layer of a superlattice structure in... Agent: Sughrue Mion, PLLC

20100148151 - Light emitting devices with improved light extraction efficiency: A device includes a light emitting structure and a wavelength conversion member comprising a semiconductor. The light emitting structure is bonded to the wavelength conversion member. In some embodiments, the light emitting structure is bonded to the wavelength conversion member with an inorganic bonding material. In some embodiments, the light... Agent: Philips Intellectual Property & Standards

20100148146 - Monolithic white and full-color light emitting diodes using optically pumped multiple quantum wells: An embodiment is a method and apparatus for a white or full-color light-emitting diode. First single or multiple quantum wells (QWs) at a first wavelength are formed at an active region between a p-type layer and an n-type layer of a light-emitting diode. Multiple passive quantum wells (QWs) are formed... Agent: Parc-xerox/bstz Blakely Sokoloff Taylor & Zafman LLP

20100148147 - Monolithic white and full-color light emitting diodes using selective area growth: An embodiment is a method and apparatus for a white or full-color light-emitting diode. A first mask having a first pattern is applied over surface of an n-type layer. A first active region is grown selectively and including single or multiple quantum wells (QWs) of a first active color to... Agent: Parc-xerox/bstz Blakely Sokoloff Taylor & Zafman LLP

20100148145 - Nitride semiconductor light-emitting device: A nitride semiconductor light-emitting device according to the present invention includes a nitride based semiconductor substrate 10 and a nitride based semiconductor multilayer structure that has been formed on the semiconductor substrate 10. The multilayer structure includes an active layer 16 that produces emission and multiple semiconductor layers 12, 14... Agent: Mark D. Saralino (pan) Renner, Otto, Boisselle & Sklar, LLP

20100148152 - Electrically controlled catalytic nanowire growth: A population of nanowires can be prepared by a method involving electric field catalyzed growth and alteration based on surface charge density.... Agent: Steptoe & Johnson LLP

20100148153 - Group iii-v devices with delta-doped layer under channel region: A group III-V material device has a delta-doped region below a channel region. This may improve the performance of the device by reducing the distance between the gate and the channel region.... Agent: Intel Corporation C/o Cpa Global

20100148164 - All-organic sensor/actuator system: A sensor and/or actuator system in which functional circuitry is embedded in an all organic electromechanical transducer device is disclosed. The electromechanical transducer device exploits the behavior of a flexible sensible ionomeric material sheet as effective sensing or actuating member sandwiched between flexible organic electrodes when undergoing a deformation or... Agent: Seed Intellectual Property Law Group PLLC

20100148154 - Apparatus and semiconductor co-crystal: The invention provides a method to enforce face-to-face stacking of organic semiconductors in the solid state that employs semiconductor co-crystal formers (SCCFs), to align semiconductor building blocks (SBBs). Single-crystal X-ray analysis reveals π-orbital overlap optimal for organic semiconductor device applications.... Agent: Viksnins Harris & Padys Pllp

20100148161 - Compound for organic electroluminescent device and organic electroluminescent device: Disclosed are an organic electroluminescent device (organic EL device) which is improved in luminous efficiency, fully secured of driving stability, and of simple constitution and a compound useful for the fabrication of said organic EL device. The compound for the organic EL device has an indolocarbazole structure or a structure... Agent: Birch Stewart Kolasch & Birch

20100148162 - Compound for organic electroluminescent device and organic electroluminescent device: Disclosed are a compound for an organic electroluminescent device (organic EL device) which is improved in luminous efficiency, fully secured of driving stability, and of simple constitution and an organic EL device using said compound. The compound for an organic EL device has two indolocarbazole skeletons each of which is... Agent: Birch Stewart Kolasch & Birch

20100148165 - Light-emitting element, light-emitting device, and electronic device: A light-emitting element includes a light-emitting layer having a two-layer structure in which a first light-emitting layer containing a first light-emitting substance and a second light-emitting layer containing a second light-emitting substance, which is in contact with the first light-emitting layer, are provided between an anode and a cathode. The... Agent: Cook Alex Ltd

20100148166 - Light-emitting element, lighting device, light-emitting device, and electronic apparatus: The light-emitting element comprises a first electrode, a second electrode, and a light-emitting layer between the first electrode and the second electrode, in which a first layer, a second layer, and a third layer are stacked from the first electrode side, the first layer contains a first light-emitting substance and... Agent: Cook Alex Ltd

20100148159 - Method for forming a pattern on a substrate and electronic device formed thereby: The invention relates to a method for forming a pattern on a substrate (S) with an upper surface and a lower surface which comprises the steps of depositing a first layer (E1) of an opaque material on the upper surface of the substrate (S), depositing a photosensitive layer (R) such... Agent: Basf Performance Products LLC Patent Department

20100148156 - Method for producing nanoparticle/block copolymer composites: in which δS, δA, δB and δL represent the solubility parameters of the solvent S, the block repeating unit A, the block repeating unit B and the ligand L, respectively. According to the method, the inherent electrical, magnetic, optical, chemical and mechanical properties of the nanoparticles can be maintained or... Agent: Cantor Colburn, LLP

20100148158 - Organic compound and organic light emitting device containing the same:

20100148160 - Organic electronic devices protected by elastomeric laminating adhesive: An active organic electronic component is protected within an organic electronic device by an elastomeric laminating adhesive, which adheres the substrate and cover of the electronic device and encloses and protects the active organic component within the device. The organic electronic device has a structure comprising (a) a substrate; (b)... Agent: Henkel Corporation

20100148157 - Organic light emitting apparatus and method of manufacturing the same: Provided are an organic light emitting apparatus and a method of manufacturing the same. The organic light emitting apparatus includes: a filling material between a diode substrate on which an organic light emitting unit is formed and an encapsulation substrate; and an organic protection layer that is interposed between the... Agent: Knobbe Martens Olson & Bear LLP

20100148163 - Organic light emitting display apparatus: An organic light emitting display apparatus includes an organic light emitting diode, a photo sensor, and a light blocking portion. The light blocking portion is at at least a side of the photo sensor so that light emitted from the organic light emitting diode is not directly incident on the... Agent: Christie, Parker & Hale, LLP

20100148155 - Thin film transistor, method of forming the same and flat panel display device having the same: A thin film transistor (TFT), a method of forming the same and a flat panel display device having the same are disclosed. The TFT includes a buffer layer and a semiconductor layer which are sequentially disposed on a substrate, a gate pattern including an insulating pattern and a gate electrode... Agent: Camoriano & Associates

20100148170 - Field effect transistor and display apparatus: A field-effect transistor provided with at least a semiconductor layer and a gate electrode disposed over the above-described semiconductor layer with a gate insulating film therebetween, wherein the above-described semiconductor layer includes a first amorphous oxide semiconductor layer having at least one element selected from the group of Zn and... Agent: Canon U.s.a. Inc. Intellectual Property Division

20100148168 - Integrated circuit structure: An integrated circuit structure including a substrate, an insulating layer, a first transistor and a second transistor is provided. The insulating layer, the first transistor and the second transistor are disposed on the substrate. The first transistor includes a first gate, a first oxide semiconductor layer, a first source and... Agent: Jianq Chyun Intellectual Property Office

20100148167 - Magnetic tunnel junction stack: A magnetic tunnel junction (300) structure includes a layer (308) of iron having a thickness in the range of 1.0 to 5.0 Å disposed between a tunnel barrier (306) and a free magnetic element (310) resulting in high magnetoresistance (MR), low damping and an improved ratio Vc/Vbd of critical switching... Agent: Ingrassia Fisher & Lorenz, P.C.

20100148171 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device of the present invention has a first interconnect layer formed over the semiconductor substrate, and a semiconductor element; the first interconnect layer has an insulating layer, and a first interconnect filled in a surficial portion of the insulating layer; the semiconductor element has a semiconductor layer, a... Agent: Mcginn Intellectual Property Law Group, PLLC

20100148169 - Thin-film transistor substrate and method of fabricating the same: A thin-film transistor (TFT) substrate has improved electrical properties and reduced appearance defects and a method of fabricating the TFT substrate, are provided. The TFT substrate includes: gate wiring which is formed on a surface of an insulating substrate; oxide active layer patterns which are formed on the gate wiring... Agent: Cantor Colburn, LLP

20100148172 - Semiconductor device: A semiconductor device includes: a semiconductor chip; a plurality of electrode pads on the semiconductor chip; a wiring board fixed to the semiconductor chip; a plurality of connection pads on the wiring board; a plurality of bonding pads aligned along two sides of the wiring board; and a plurality of... Agent: Mcginn Intellectual Property Law Group, PLLC

20100148173 - Semiconductor device and fabrication method for the same: A semiconductor device includes: a semiconductor element (1) having an internal circuit (17); and electrode pads (22, 22, . . . ) provided for the semiconductor element (1). The electrode pads (22, 22, . . . ) are electrically connected to the internal circuit (17) via control portions (31) for... Agent: Mcdermott Will & Emery LLP

20100148174 - Gan epitaxial wafer and semiconductor devices, and method of manufacturing gan epitaxial wafer and semiconductor devices: A GaN epitaxial wafer manufacturing method involving the present invention includes a first GaN layer formation step of epitaxially growing a first GaN layer onto a substrate, a pit formation step, following the first GaN layer formation step, of forming pits in the front side of the substrate, and a... Agent: Judge Patent Associates

20100148175 - Thin film transistor and display device: Off current of a bottom gate thin film transistor in which a semiconductor layer is shielded from light by a gate electrode is reduced. A thin film transistor includes a gate electrode layer; a first semiconductor layer; a second semiconductor layer, provided on and in contact with the first semiconductor... Agent: Nixon Peabody, LLP

20100148177 - Display device: A display device including an inverter circuit and a switch is provided. The inverter circuit includes a first thin film transistor and a second thin film transistor which have the same conductivity type. The first thin film transistor and the second thin film transistor each include: a gate insulating layer... Agent: Nixon Peabody, LLP

20100148179 - Semiconductor device and method of manufacturing the same: A semiconductor device having a semiconductor element (a thin film transistor, a thin film diode, a photoelectric conversion element of silicon PIN junction, or a silicon resistor element) which is light-weight, flexible (bendable), and thin as a whole is provided as well as a method of manufacturing the semiconductor device.... Agent: Fish & Richardson P.C.

20100148178 - Thin film transistor and display device: A thin film transistor includes: a gate electrode layer; a first semiconductor layer; a second semiconductor layer having lower carrier mobility than the first semiconductor layer, which is provided over and in contact with the first semiconductor layer; a gate insulating layer which is provided between and in contact with... Agent: Nixon Peabody, LLP

20100148180 - Thin film transistor array panel with common bars of different widths: A gate wire and a storage electrode wire extending in a transverse direction are provided, and a data wire extending in a longitudinal direction intersects the gate wire and the storage electrode wire. A plurality of pixel electrodes and a plurality of TFTs are provided on pixel areas defined by... Agent: Innovation Counsel LLP

20100148176 - Thin film transistor display panel and manufacturing method thereof: The present invention relates to a thin film transistor array panel that includes an organic layer formed on a data line and a drain electrode disposed on a color filter. A thickness of a portion of the organic layer around a contact hole exposing a portion of the drain electrode... Agent: H.c. Park & Associates, PLC

20100148181 - Nanocrystal silicon layer structures formed using plasma deposition technique, methods of forming the same, nonvolatile memory devices having the nanocrystal silicon layer structures, and methods of fabricating the nonvolatile memory devices: Provided are nanocrystal silicon layer structures formed using a plasma deposition technique, methods of forming the same, nonvolatile memory devices including the nanocrystal silicon layer structures, and methods of fabricating the nonvolatile memory devices. A method of forming a nanocrystal silicon layer structure includes forming a buffer layer on a... Agent: Camoriano & Associates

20100148182 - Thin flim transistor substrate and manufacturing method thereof: A thin film transistor (TFT) substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion and a method of fabricating the TFT substrate. The TFT substrate includes a gate interconnection line formed on an insulating substrate, a gate insulating layer covering... Agent: Cantor Colburn, LLP

20100148185 - Flip-chip light-emitting diode device: A flip-chip light-emitting diode (LED) device is provided. The flip-chip LED device includes a substrate, an n-GaN layer, an epitaxy layer, a p-GaN layer, a first electrode, and a second electrode. The n-GaN layer is formed on a surface of the substrate. The epitaxy layer is formed on the n-GaN... Agent: Rabin & Berdo, PC

20100148184 - Gan-based field effect transistor: A GaN-based field effect transistor (MOSFET) is comprised of a channel layer comprised of p-type GaN, an electron supply layer, a surface layer having band gap energy smaller than that of said electron supply layer, sequentially laminated on a substrate, and recess section is formed by removing a part of... Agent: Turocy & Watson, LLP

20100148183 - Method of forming a carbon nanotube-based contact to semiconductor: Manufacturers encounter limitations in forming low resistance ohmic electrical contact to semiconductor material P-type Gallium Nitride (p-GaN), commonly used in photonic applications, such that the contact is highly transparent to the light emission of the device. Carbon nanotubes (CNTs) can address this problem due to their combined metallic and semiconducting... Agent: Wilmerhale/boston

20100148187 - Semiconductor device: A semiconductor device according to an embodiment includes a transistor including a gate electrode formed on a semiconductor substrate of a predetermined crystal via a gate insulating film and a source-drain region formed in the semiconductor substrate so as to have a convex portion in a direction of a gate... Agent: Turocy & Watson, LLP

20100148186 - Vertical junction field effect transistors having sloped sidewalls and methods of making: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped... Agent: Morris Manning Martin LLP

20100148188 - Laser-induced flaw formation in nitride semiconductors: An embodiment is a method and apparatus to induce flaw formation in nitride semiconductors. Regions of a thin film structure are selectively decomposed within a thin film layer at an interface with a substrate to form flaws in a pre-determined pattern within the thin film structure. The flaws locally concentrate... Agent: Parc-xerox/bstz Blakely Sokoloff Taylor & Zafman LLP

20100148189 - Light emitting diode: A LED chip including a substrate, a semiconductor device layer, a current blocking layer, a current spread layer, a first electrode and a second electrode is provided. The semiconductor device layer is disposed on the substrate. The current blocking layer is disposed on a part of the semiconductor device layer... Agent: Jianq Chyun Intellectual Property Office

20100148191 - High luminous flux warm white solid state lighting device: A high luminous flux warm white solid state lighting device with a high color rendering is disclosed. The device comprising two groups of semiconductor light emitting components to emit and excite four narrow-band spectrums of lights at high luminous efficacy, wherein the semiconductor light emitting components are directly mounted on... Agent: Harvey S. Kauget Phelps Dunbar, LLP

20100148190 - Light emitting diode with ito layer and method for fabricating the same: The present invention relates to a light emitting diode with enhanced luminance and light emitting performance due to increase in efficiency of current diffusion into an ITO layer, and a method of fabricating the light emitting diode. According to the present invention, there is manufactured at least one light emitting... Agent: H.c. Park & Associates, PLC

20100148192 - Organic light emitting diode display: An organic light emitting diode display includes: a substrate member; a pixel electrode formed on the substrate member; a pixel defining film having an opening through which the pixel electrode is exposed, and formed on the substrate member; a light absorbing layer pattern for dividing the opening into a plurality... Agent: Stein Mcewen, LLP

20100148193 - Systems and methods for packaging light-emitting diode devices: Embodiments disclosed herein provide packaged LED devices in which the majority of the emitted light comes out the top of each LED chip with very little side emissions. Because light only comes out from the top, phosphor deposition and color temperature control can be significantly simplified. A package LED may... Agent: SprinkleIPLaw Group

20100148194 - Light-emitting diode illuminating apparatus: The invention provides a light-emitting diode illuminating apparatus. The light-emitting diode illuminating apparatus includes a carrier, a substrate, a light-emitting diode chip, a heat-conducting device, and a thermal phase-change material. The carrier includes a top surface and a bottom surface. A first recess is formed on the top surface of... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100148195 - Method for improved growth of semipolar (al,in,ga,b)n: A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1-xN nucleation layer on the... Agent: Gates & Cooper LLP Howard Hughes Center

20100148196 - Led lighting fixture: A light-emitting device held on a fixture body includes an LED chip, a heat transfer plate made of a thermally conductive material on which the LED chip is mounted, a wiring board having, on one side, patterned conductors, for supplying an electric power to the LED chip and formed with... Agent: Greenblum & Bernstein, P.L.C

20100148201 - Led package: There is provided an LED package including: a body unit; an LED chip mounted onto the body unit; lead frames mounted onto the body unit and electrically connected to the LED chip; and a reflection unit having a cavity to receive the LED chip therein and reflecting light emitted from... Agent: Mcdermott Will & Emery LLP

20100148206 - Led package and method of assembling the same: An LED package is provided. The LED package includes a carrier, an LED chip, a conductive structure, a first encapsulant, a lens and a heat sink. The carrier is cup shaped and comprises a bottom portion and a lateral wall. The LED chip is received in the carrier and disposed... Agent: Quintero Law Office, PC

20100148205 - Lens, manufacturing method thereof and light emitting device package using the same: A lens and a light emitting device package formed by introducing surface mount technology (SMI) are disclosed. The lens includes a refractive portion which refracts incident light, and at least one surface mount portion, wherein a portion of the surface mount portion is formed in the refractive portion.... Agent: Ked & Associates, LLP

20100148198 - Light emitting device and method for manufacturing same: A method for manufacturing a light emitting device includes: forming a multilayer body including a light emitting layer so that a first surface thereof is adjacent to a first surface side of a translucent substrate; forming a dielectric film on a second surface side opposite to the first surface of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100148199 - Light emitting device with fine pattern: A semiconductor light emitting device includes a semiconductor light emitting structure including first and second conductivity type semiconductor layers, and an active layer disposed therebetween, first and second electrodes connected to the first and second conductivity type semiconductor layers, respectively, and a fine pattern for light extraction, formed on a... Agent: Staas & Halsey LLP

20100148200 - Light emitting diode with light conversion: An exemplary light emitting diode includes a light emitting diode chip, two optical wavelength converting layers, and an encapsulant layer. The light emitting diode chip has an light emitting surface. The light emitting diode chip is used to emit a monochromatic light from the light emitting surface. The light emitting... Agent: PCe Industry, Inc. Att. Steven Reiss

20100148204 - Light-emitting element and display device: There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer (passivation film) such as SiN provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the... Agent: Fish & Richardson P.C.

20100148197 - Selective decomposition of nitride semiconductors to enhance led light extraction: A method of texturing a surface within or immediately adjacent to a template layer of a LED is described. The method uses a texturing laser directed through a substrate to decompose and pit a semiconductor material at the surface to be textured. By texturing the surface, light trapping within the... Agent: Bever, Hoffman & Harms, LLP

20100148203 - Semiconductor light-emitting device: There is provided a semiconductor light-emitting device including a semiconductor light-emitting element, a phosphor layer disposed in a light path of a light emitted from the semiconductor light-emitting element, containing a phosphor to be excited by the light and having a cross-section in a region of a diameter which is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100148202 - Semiconductor light-emitting device and method for manufacturing the same: A semiconductor light-emitting device includes (A) a light-emitting portion obtained by laminating in sequence a first compound semiconductor layer, an active layer, and a second compound semiconductor layer; (B) a first electrode electrically connected to the first compound semiconductor layer; (C) a transparent conductive material layer formed on the second... Agent: Sonnenschein Nath & Rosenthal LLP

20100148208 - Led lighting assembly with improved heat management: The present invention provides a lighting head assembly that incorporates a high intensity LED package into an integral assembly including a heat sink and circuit board for further incorporation into other useful lighting devices. The present invention primarily includes a heat sink member that also serves as a mounting die... Agent: Barlow, Josephs & Holmes, Ltd.

20100148211 - Light emitting diode package structure: A light emitting diode (LED) package structure including a leadframe, a housing, a LED chip and a light-transmissive encapsulant is provided. The leadframe has a first electrode and a second electrode separated from each other. The housing wraps the first electrode and the second electrode and includes a recess having... Agent: Jianq Chyun Intellectual Property Office

20100148209 - Light-emitting device and electronic device: An object is to provide a light-emitting device having a structure in which an external connection portion can easily be connected and a method for manufacturing the light-emitting device. A light-emitting device includes a lower support 110, a base insulating film 112 over the lower support 110 which has a... Agent: Nixon Peabody, LLP

20100148210 - Package structure for chip and method for forming the same: An embodiment of the invention provides a package structure for chip. The package structure for chip includes: a carrier substrate having an upper surface and an opposite lower surface; a chip overlying the carrier substrate and having a first surface and an opposite second surface facing the upper surface, wherein... Agent: Liu & Liu

20100148207 - Semiconductor device, and manufacturing method thereof, and display device and its manufacturing method: A semiconductor device in which a semiconductor has good heat dissipation efficiency, a display employing such a semiconductor device and a method for manufacturing a semiconductor device. A conductive pattern providing a semiconductor-connecting terminal portion and further providing first and second external-connection terminal portion on the opposite sides of the... Agent: Smith, Gambrell & Russell

20100148212 - Method for producing group iii nitride semiconductor crystal, group iii nitride semiconductor substrate, and semiconductor light- emitting device: The method for producing a group III nitride semiconductor crystal of the invention comprises a step of preparing a seed crystal having a non-polar plane followed by growing a group III nitride semiconductor from the non-polar plane in a vapor phase, wherein the growing step includes growing the group III... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100148213 - Tunnel device: The present invention has provided a new diode and transistor by employing the characteristic of the tunnel diode. The new diode and transistor are field interacted and can be a solarcell, light sensor, thermal device, Hall device, pressure device or acoustic device which outputs self-excited multi-band waveforms with broad bandwidth.... Agent: Yen-wei Hsu

20100148215 - igbt having one or more stacked zones formed within a second layer of the igbt: An IGBT includes a first region, a second region located within the first region, a first contact coupled to the first region, a first layer arranged below the first region, a gate overlying at least a portion of the first region between the second region and the first layer and... Agent: Coats & Bennett/infineon Technologies

20100148214 - Semiconductor device internally having insulated gate bipolar transistor: The semiconductor device includes a P-type semiconductor region and an MOS transistor. MOS transistor includes a gate electrode, a collector electrode, a drain electrode, an N-type impurity region and a P-type impurity region. N-type impurity region is electrically connected to the drain electrode. P-type impurity region is electrically connected to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100148216 - Semiconductor light receiving element and method for manufacturing semiconductor light receiving element: A semiconductor light detecting element having a mesa structure comprises: a first semiconductor layer having n-type conductivity located on a semiconductor substrate, a light absorbing layer located on the first semiconductor layer, and a second semiconductor layer located on the light absorbing layer; a burying layer burying peripheries of the... Agent: Leydig Voit & Mayer, Ltd

20100148217 - Graded high germanium compound films for strained semiconductor devices: Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed.... Agent: Intel Corporation C/o Cpa Global

20100148218 - Semiconductor integrated circuit device and method for designing the same: The layout of an LSI is previously designed so that cells below pads which will be affected by stress are arranged so that the occurrence of a malfunction of the LSI which will be caused by the influence of stress is reduced or prevented. In addition to or instead of... Agent: Mcdermott Will & Emery LLP

20100148219 - Semiconductor integrated circuit device: A technique permitting reduction in size of a standard cell is provided. In a semiconductor integrated circuit device comprising a first tap formed in a first direction to supply a power-supply potential, a second tap formed in the first direction to supply a power-supply potential and positioned so as to... Agent: Miles & Stockbridge PC

20100148220 - Stack array structure for a semiconductor memory device: In a stack array structure for a semiconductor memory device, a first semiconductor layer includes a plurality of first cell strings, and a second semiconductor including a plurality of second cell strings. Bit-line contact plugs are configured to couple a bit-line to two adjacent first cell strings aligned in series... Agent: Volentine & Whitt PLLC

20100148221 - Vertical photogate (vpg) pixel structure with nanowires: An embodiment relates to a device comprising a nanowire photodiode comprising a nanowire and at least on vertical photogate operably coupled to the nanowire photodiode.... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20100148222 - Gas sensor having a field-effect transistor: A gas sensor having a field-effect transistor for detecting gases or gas mixtures is provided. The gas sensor includes a substrate having a source, drain and gate region, a gas-sensitive layer being applied on the gate region. A porous adhesive agent is provided for the adhesion of the gas-sensitive layer... Agent: Kenyon & Kenyon LLP

20100148223 - Semiconductor device and method of manufacturing the same: A semiconductor device includes an insulated-gate field-effect transistor which is disposed on a semiconductor substrate having an element formation plane in a (110) plane direction, and which has a channel length direction in a <−110> direction, and a first element isolation insulation film which is buried in a trench in... Agent: Turocy & Watson, LLP

20100148224 - Power junction field effect power transistor with highly vertical channel and uniform channel opening: A semiconductor vertical junction field effect power transistor formed by a semiconductor structure having top and bottom surfaces and including a plurality of semiconductor layers with predetermined doping concentrations and thicknesses and comprising at least a bottom layer as drain layer, a middle layer as blocking and channel layer, a... Agent: Fox Rothschild LLP Princeton Pike Corporate Center

20100148225 - Low power memory device with jfet device structures: There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory cells having a memory element and a JFET access device electrically coupled to the memory element. The memory cells may be isolated using diffusion based... Agent: Robert A. Manware Fletcher Yoder

20100148226 - Jfet device structures and methods for fabricating the same: In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source... Agent: Fletcher Yoder (micron Technology, Inc.)

20100148227 - Electronic device including an insulating layer having different thicknesses and a conductive electrode and a process of forming the same: An electronic device includes a transistor, wherein the electronic device can include a semiconductor layer having a primary surface, a channel region, a gate electrode, a source region, a conductive electrode, and an insulating layer lying between the primary surface of the semiconductor layer and the conductive electrode. The insulating... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20100148229 - Insulating resin composition: An insulating resin composition is provided. The insulating resin composition includes (A) a silicon-based polymer having either primary or secondary amine groups or both, (B) an organometallic compound, and (C) a solvent. The physicochemical properties of the insulating resin composition are maintained during processing steps for the fabrication of a... Agent: Cantor Colburn, LLP

20100148228 - Semiconductor and manufacturing method of the same: A semiconductor device includes a gate formed on a semiconductor substrate. A first junction region is formed on a first side of the gate and a second junction region formed on a second side of the gate. A bit line is formed over the gate to be electrically coupled with... Agent: Ampacc Law Group

20100148230 - Trench isolation regions in image sensors: Trenches are formed in a substrate or layer and a solid source doped with one or more dopants is deposited over the image sensor such that the solid source fills the one or more trenches and is disposed on the surface of the substrate. The surface of the image sensor... Agent: Pedro P. Hernandez, Patent Legal Staff Eastman Kodak Company

20100148231 - Elimination of glowing artifact in digital images captured by an image sensor: A source/drain region of a transistor or amplifier is formed in a substrate layer and is connected to a voltage source. A glow blocking structure is formed at least partially around the source/drain region and is disposed between the source/drain region and an imaging array of an image sensor. A... Agent: Pedro P. Hernandez Patent Legal Staff

20100148232 - Surface treatment of hydrophobic ferroelectric polymers for printing: An embodiment is a method and apparatus to treat surface of polymer for printing. Surface of a polymer having a surface energy modified for a time period to control a feature characteristic and/or provide a hysteresis behavior. A material is printed on the surface to form a circuit pattern having... Agent: Parc-xerox/bstz Blakely Sokoloff Taylor & Zafman LLP

20100148233 - Semiconductor device and method of forming semiconductor device: A semiconductor device include a semiconductor substrate comprising a substrate body, a base over the substrate body and a pillar over a first region of the base; a buried line adjacent to a side surface of the base; a first diffusion layer over a second region of the base; a... Agent: Young & Thompson

20100148235 - Semiconductor integrated circuit, standard cell, standard cell library, semiconductor integrated circuit designing method, and semiconductor integrated circuit designing equipment: A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second... Agent: Mcdermott Will & Emery LLP

20100148234 - Subresolution silicon features and methods for forming the same: Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent... Agent: Knobbe Martens Olson & Bear LLP

20100148236 - Semiconductor device and manufacturing method thereof: A semiconductor device having a 6F2 memory cell whose size is defined by a numerical value of a design rule F, wherein: lower electrodes of capacitors included in the memory cell are supported by a support film; the support film is formed as a pattern combining a first support pattern... Agent: Foley And Lardner LLP Suite 500

20100148237 - Non-volatile semiconductor storage device and method of manufacturing the same: A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100148238 - Non-volatile memory and fabricating method thereof: A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area.... Agent: Jianq Chyun Intellectual Property Office

20100148239 - Gate structure of semiconductor device and methods of forming word line structure and memory: A gate structure for a semiconductor device is provided. The gate structure includes a conductive structure. The conductive structure insulatively disposed over a substrate includes a middle portion and two spacer portions. The middle portion has a first surface and two second surfaces. The first surface is between the two... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100148240 - Semiconductor device and manufacturing method thereof: Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a first insulating layer pattern on a semiconductor substrate, a second insulating layer including fluorine on the first insulating layer pattern, a third insulating layer pattern on the second insulating layer pattern, and a polysilicon pattern... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20100148241 - Semiconductor device and method of manufacturing the same: The semiconductor device has a stacked structure in which a tunnel oxide layer, a charge trapping layer, a blocking oxide layer, and a gate electrode are sequentially formed on a silicon substrate, wherein the blocking oxide layer includes a crystalline layer disposed adjacent to the charge trapping layer and an... Agent: Cantor Colburn, LLP

20100148242 - Semiconductor device: A semiconductor device suppresses short-circuit failure between a selection gate electrode and a control gate electrode while shortening the distance between the upper portions of the selection gate electrode and the control gate electrode. The device includes an impurity region formed on both sides of a channel region of a... Agent: Young & Thompson

20100148243 - Semiconductor device and method for fabricating the same: A semiconductor device comprises an active region including a first active area to be a source/drain and a second active area to be a gate, and a device isolation region defining the active region. The first active area is obtained by growing a semiconductor substrate located between the gates as... Agent: Townsend And Townsend And Crew, LLP

20100148245 - Electronic device including a trench and a conductive structure therein: A process of forming an electronic device can include providing a workpiece comprising a substrate, including an underlying doped region, and a semiconductor layer overlying the underlying doped region, wherein the semiconductor layer has a primary surface spaced apart from the underlying doped region. The process can also include forming... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20100148244 - Semiconductor element and electrical apparatus: In a semiconductor element (20) including a field effect transistor (90), a schottky electrode (9a) and a plurality of bonding pads (12S, 12G), at least one of the plurality of bonding pads (12S, 12G) is disposed so as to be located above the schottky electrode (9a).... Agent: Mcdermott Will & Emery LLP

20100148246 - Power mosfet device structure for high frequency applications: This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the... Agent: Bo-in Lin

20100148247 - Semiconductor device: A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE... Agent: Miles & Stockbridge PC

20100148249 - Method of manufacturing a memory device: A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second... Agent: Wells St. John P.s.

20100148248 - Semiconductor device having gate trenches and manufacturing method thereof: A semiconductor device includes a first gate trench, a second gate trench, and a dummy gate trench provided in an active region extending in an X direction; and a first gate electrode, a second gate electrode, and a dummy gate electrode extending in a Y direction crossing the active region,... Agent: Sughrue Mion, PLLC

20100148250 - Metal oxide semiconductor device: A metal oxide semiconductor device comprising a substrate, at least an isolation structure, a deep N-type well, a P-type well, a gate, a plurality of N-type extension regions, an N-type drain region, an N-type source region and a P-type doped region is provided. The N-type extension regions are disposed in... Agent: J C Patents

20100148251 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a substrate on and/or over which a first conductive type well is formed; and an LDMOS device that includes a gate electrode and has a drain region formed in the substrate. The LDMOS device includes a trench formed on the substrate, a second conductive type body... Agent: Sherr & Vaughn, PLLC

20100148252 - Semiconductor device having transistor and method of manufacturing the same: One embodiment of inventive concepts exemplarily described herein may be generally characterized as a semiconductor device including an isolation region within a substrate. The isolation region may define an active region. The active region may include an edge portion that is adjacent to an interface of the isolation region and... Agent: Muir Patent Consulting, PLLC

20100148253 - High voltage semiconductor devices with schottky diodes: High voltage semiconductor devices with Schottky diodes are presented. A high voltage semiconductor device includes an LDMOS device and a Schottky diode device. The LDMOS device includes a semiconductor substrate, a P-body region in a first region of the substrate, and an N-drift region in the second region of the... Agent: Quintero Law Office, PC

20100148254 - Power semiconductor device and method of manufacturing the same: A semiconductor device and a method of manufacturing the same. The method includes preparing a semiconductor substrate having high-voltage and low-voltage device regions, forming a field insulating layer in the high-voltage device region, forming a first gate oxide layer on the semiconductor substrate, exposing the semiconductor substrate in the low-voltage... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20100148255 - Lateral high-voltage mos transistor with a resurf structure: For achieving an enhanced combination of a low on-resistance at a high break-through voltage a lateral high-voltage MOS transistor comprises a plurality of doped RESURF regions of the first conductivity type within the drift region, wherein the doped RESURF regions are separated from each other by drift region sections in... Agent: Hunton & Williams LLP Intellectual Property Department

20100148256 - Lateral diffused metal oxide semiconductor (ldmos) devices with electrostatic discharge (esd) protection capability in integrated circuit: Lateral diffused metal oxide semiconductor (LDMOS) devices with electrostatic discharge (ESD) protection capability are presented for integrated circuits. The LDMOS device includes a semiconductor substrate with an epi-layer thereon. Patterned isolations are disposed on the epi-layer, thereby defining a first active region and a second active region. An N-type double... Agent: Quintero Law Office, PC

20100148257 - Mos-fet having a channel connection, and method for the production of a mos-fet having a channel connection: A MOSFET comprising a substrate of a semiconductor material; source/drain regions, which are arranged at a distance from each other at a surface of the substrate; a gate electrode arranged above an area of the surface of the substrate between the source/drain regions, the gate electrode being electrically insulated from... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20100148258 - Semiconductor device and method of manufacturing the same: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate formed therein with a first conductive type well, and an LDMOS device formed on the substrate. The LDMOS device includes a gate electrode, gate oxides formed below the gate electrode, a source... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20100148260 - Semiconductor device including a crystal semiconductor layer, its fabrication and its operation: In one embodiment, a method of fabricating a semiconductor device having a crystalline semiconductor layer includes preparing a semiconductor substrate and forming a preliminary active pattern on the semiconductor substrate. The preliminary active pattern includes a barrier pattern and a non-single crystal semiconductor pattern. A sacrificial non-single crystal semiconductor layer... Agent: Volentine & Whitt PLLC

20100148259 - Soi substrates and soi devices, and methods for forming the same: An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried... Agent: Scully, Scott, Murphy & Presser, P.C.

20100148261 - Semiconductor device and method for producing the same: A method of the present invention includes a first planarization film formation step of forming, in at least part of a flat portion of the second regions, a first planarization film so as to have a uniform thickness; a second planarization film formation step of forming a second planarization film... Agent: Nixon & Vanderhye, PC

20100148262 - Resistors and methods of manufacture thereof: Resistors, semiconductor devices, and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a resistor includes forming a semiconductive material over a workpiece, and patterning at least the semiconductive material, forming a gate of a transistor in a first region of the workpiece and forming a... Agent: Slater & Matsil LLP

20100148264 - Electrostatic discharge protection device and method of fabricating the same: An ESD protection device including a substrate, a gate structure, a source region, a drain region and a first implanted region is provided. The gate structure includes a gate dielectric layer and a gate sequentially disposed on the substrate. The source region and the drain region are disposed in the... Agent: J C Patents

20100148265 - Esd protection device: An ESD protection device includes a substrate of a first conductivity type, a well region of a second conductivity type, a first doped region of the second conductivity type, a second doped region of the first conductivity type, a third doped region of the second conductivity type, a fourth doped... Agent: J C Patents

20100148263 - Semiconductor device structure and fabricating method thereof: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a... Agent: North America Intellectual Property Corporation

20100148267 - Semiconductor integrated circuit: A semiconductor integrated circuit includes: a well 35 of a first conductivity type formed on a substrate 37; a first external terminal 10, a second external terminal 11, and a third external terminal 12 provided above the substrate 37; a first protection circuit 20 provided on an electrical path between... Agent: Mcdermott Will & Emery LLP

20100148266 - System and method for isolated nmos-based esd clamp cell: The invention is directed to a protection circuit for protecting IC chips against ESD. An ESD protection circuit for an integrated circuit chip may comprise an isolated NMOS transistor, which may comprise an isolation region isolating a backgate from a substrate, and a first and second doped regions and a... Agent: Kenyon & Kenyon LLP

20100148268 - Insulated-gate semiconductor device: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below... Agent: Morrison & Foerster LLP

20100148269 - Tunable spacers for improved gapfill: A device that includes a substrate with an active region is disclosed. The device includes a gate disposed in the active region and tunable sidewall spacers on sidewalls of the gate. A profile of the tunable sidewall spacers includes upper and lower portions in which width of the spacers in... Agent: HorizonIPPte Ltd

20100148273 - Cmos transistors with differential oxygen content high-k dielectrics: An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An... Agent: Scully, Scott, Murphy & Presser, P.C.

20100148271 - Method for gate leakage reduction and vt shift control and complementary metal-oxide-semiconductor device: The present invention relates to a method for gate leakage reduction and Vt shift control, in which a first ion implantation is performed on PMOS region and NMOS region of a substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate, and a... Agent: North America Intellectual Property Corporation

20100148270 - Methods of channel stress engineering and structures formed thereby: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a source/drain region in an NMOS portion of a substrate, wherein the source/drain region of the NMOS portion comprises at least one dislocation, and wherein a PMOS source/drain region in a PMOS portion of... Agent: Intel Corporation C/o Cpa Global

20100148272 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a semiconductor substrate having a first region including an n-type active element and a second region including a p-type active element, an element isolation region isolating plurality of the n-type active element and plurality of the p-type active element, a first insulating film having a tensile... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20100148275 - Semiconductor device and method for fabricating the same: A semiconductor device includes a first MIS transistor formed on a first active region, and a second MIS transistor formed on a second active region. The first MIS transistor includes a first gate insulating film, and a first gate electrode including a first metal film and a first silicon film.... Agent: Mcdermott Will & Emery LLP

20100148274 - Semiconductor device and method for manufacturing same: A semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the device having: a first insulating layer and a second insulating layer; and gate electrode contact plugs. Each of the gate electrodes of the N-channel insulated gate field effect transistor and... Agent: Sonnenschein Nath & Rosenthal LLP

20100148276 - Bipolar integration without additional masking steps: The invention relates to a BiMOS semiconductor component having a semiconductor substrate wherein, in a first active region, a depletion-type MOS transistor is formed comprising additional source and drain doping regions of the first conductivity type extending in the downward direction past the depletion region into the body doping region... Agent: Hunton & Williams LLP Intellectual Property Department

20100148277 - Isolated metal plug process for use in fabricating carbon nanotube memory cells: The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a... Agent: Wilmerhale/boston

20100148279 - Semiconductor device: A semiconductor device includes a first field effect transistor and a second field effect transistor. The first field effect transistor includes a first gate electrode formed; first impurity diffused areas; and first sidewall portions. The first sidewall portions include a first lower insulation film and a first charge accumulation film.... Agent: Kazunao Kubotera Takeuchi & Kubotera, LLP

20100148278 - Semiconductor device and fabricating method thereof: A semiconductor device and fabricating method thereof are disclosed. The method includes forming a polysilicon layer on a semiconductor substrate including a high-voltage area and a low-voltage area, partially etching the polysilicon layer in the low-voltage area, forming an anti-reflective layer on the polysilicon layer to reduce a step difference... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20100148280 - Semiconductor device and method for fabricating the same: A semiconductor device includes a semiconductor substrate, a gate insulating film formed on a semiconductor substrate and containing a first element and a second element, and a gate electrode formed on the gate insulating film. The gate insulating film has a higher content of the first element in a portion... Agent: Mcdermott Will & Emery LLP

20100148281 - Semiconductor device and method for fabricating the same: A semiconductor device has a gate insulating film formed on a semiconductor substrate, a second gate electrode portion of a gate electrode including a TiN film and a polysilicon film that are successively formed on the gate insulating film, and an interlayer insulating film formed on the semiconductor substrate so... Agent: Mcdermott Will & Emery LLP

20100148282 - Wafer joining method, wafer composite, and chip: A method for joining a first wafer to at least a second wafer. The method is characterized by the following operations of depositing a sinterable bonding material on at least one of the wafers, joining the wafers, and sintering the bonding material by heating. Furthermore, a wafer composite and a... Agent: Kenyon & Kenyon LLP

20100148283 - Integrated structure of mems device and cmos image sensor device and fabricating method thereof: An integrated structure of MEMS device and CIS device and a fabricating method thereof includes providing a substrate having a CIS region and a MEMS region defined therein with a plurality of CIS devices positioned in the CIS region; performing a multilevel interconnect process to form a multilevel interconnect structure... Agent: North America Intellectual Property Corporation

20100148284 - Mems device having a movable electrode: A microelectromechanical system (MEMS) device includes a semiconductor substrate, a MEMS including a fixed electrode and a movable electrode formed on the semiconductor substrate through an insulating layer, and a well formed in the semiconductor substrate below the fixed electrode. The well is one of an n-type well and a... Agent: Harness, Dickey & Pierce, P.L.C

20100148285 - Mems component and method for production: A MEMS component includes a chip that has a rear side having a low roughness of less than one tenth of the wavelength at the center frequency of an acoustic wave propagating in the component. Metallic structures for scattering bulk acoustic waves are provided on the rear side of the... Agent: Slater & Matsil, L.L.P.

20100148286 - Contact-force sensor package and method of fabricating the same: Provided are a contact-force sensor package and a method of fabricating the same. The contact-force sensor package includes an elastic layer comprising a side that contacts a source of a contact-force; and a substrate layer adhered to the opposing side of the elastic layer from the side that contacts the... Agent: Cantor Colburn, LLP

20100148287 - Truss structure and manufacturing method thereof: A truss structure is provided. The truss structure comprises a substrate; and plural sub-truss groups disposed on the substrate, wherein each sub-truss group comprises plural VIAs; and plural metal layers interlaced with the plural VIAs, wherein the plural sub-truss groups are piled up on each other to form a 3-D... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.

20100148288 - Vertical cell edge junction magnetoelectronic device family: Magnetoelectronic devices are fabricated by joining the edge of one ferromagnetic thin film element with the top, or bottom, portion of a second ferromagnetic, or nonmagnetic, thin film element. The devices also employ a new operational geometry in which the transport of bias current is in the film plane of... Agent: Naval Research Laboratory Associate Counsel (patents)

20100148289 - Back illuminated sensor with low crosstalk: A back-illuminated image sensor includes a sensor layer having a frontside and a backside opposite the frontside. An insulating layer is situated adjacent the backside and a circuit layer is adjacent the frontside. A plurality of photodetectors of a first type conductivity convert light incident on the backside into photo-generated... Agent: Pedro P. Hernandez, Patent Legal Staff Eastman Kodak Company

20100148290 - Cmos image sensors and related devices and fabrication methods: An image sensor device includes a substrate including a light sensing, region therein and a reflective structure on a first surface of the substrate over the light sensing region. An interconnection structure having a lower reflectivity than the reflective structure is provided on the first surface of the substrate adjacent... Agent: Myers Bigel Sibley & Sajovec

20100148292 - Semiconductor device: A semiconductor device includes: a semiconductor substrate 1; a through electrode 7 extending through the semiconductor substrate 1; a diffusion layer 24 formed in a region of an upper portion of the semiconductor substrate 1 located on a side of the through electrode 7; and a diffusion layer 22 formed... Agent: Mcdermott Will & Emery LLP

20100148291 - Ultraviolet light filter layer in image sensors: An image sensor includes one or more ultraviolet (UV) light filter layers disposed between an insulating layer and a color filter array (CFA) layer. The one or more UV light filter layers reflect or absorb UV light while transmitting visible light.... Agent: Pedro P. Hernandez Panent Legal Staff

20100148293 - Miniaturized implantable sensor platform having multiple devices and sub-chips: An implantable, miniaturized platform and a method for fabricating the platform is provided, where the e platform includes a top cover plate and a bottom substrate, top cover plate including an epitaxial, Si-encased substrate and is configured to include monolithically grown devices and device contact pads, the Si-encased substrate cover... Agent: The Law Offices Of Steven Mchugh, LLC

20100148294 - Optical device and electronic devices using the same: An optical device such as an image sensor alleviates reduction in image quality caused by light reaching a peripheral circuit section other than a light receiving section. A semiconductor substrate includes an interconnect layer, a light receiving section provided with a plurality of light receiving elements on the interconnect layer,... Agent: Mcdermott Will & Emery LLP

20100148295 - Back-illuminated cmos image sensors: A semiconductor wafer includes one or more back-illuminated image sensors each formed in a portion of the semiconductor wafer. One or more thinning etch stops are formed in other portions of the semiconductor wafer.... Agent: Pedro P. Hernandez Patent Legal Staff

20100148296 - Solid state imaging device: Storage capacitors Ctd and Cts are provided alternately side by side sequentially in a row direction. Each of the storage capacitors Ctd and Cts has an electrode layer 21 constituting a signal electrode and an upper side electrode layer 23 and a lower side electrode layer 28 constituting a fixed... Agent: Oliff & Berridge, PLC

20100148297 - Semiconductor substrate for solid-state image sensing device as well as solid-state image sensing device and method for producing the same: o

20100148298 - Semiconductor device: A semiconductor device is composed of a pair of semiconductor chips (402, 404) arranged parallel on the same flat plane; a high voltage bus bar (21) bonded on the surface on the collector side of one semiconductor chip (402); a low voltage bus bar (23) connected to the surface on... Agent: Arent Fox LLP

20100148300 - Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability: An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such that it completely fills the smaller isolation trench and lines the larger isolation trench. The nitride layer is etched back to form... Agent: Dickstein Shapiro LLP

20100148299 - Method of manufacturing semiconductor device, and semiconductor device: A method of manufacturing a semiconductor device of the present invention include a step of forming, in a substrate, a first trench, and a second trench which crosses the first trench; a step of forming a film over the entire surface of the substrate so as to fill the first... Agent: Mcginn Intellectual Property Law Group, PLLC

20100148301 - Semiconductor device and manufacturing method thereof: A semiconductor device includes groove-like regions that are formed between two adjacent bit lines among a plurality of bit lines each having upper and side surfaces covered with a cap insulating film and a side-wall insulating film, respectively, a SiON film that contains more O (oxygen) than N (nitrogen) and... Agent: Young & Thompson

20100148302 - Capacitor-equipped semiconductor device: A capacitor-equipped semiconductor device includes a semiconductor chip having a plurality of electrode terminals; a sheet-like substrate at least having a film capacitor; and a mounting substrate. The mounting substrate is provided on one side thereof with chip connection terminals and ground terminals. The chip connection terminals are disposed to... Agent: Mcdermott Will & Emery LLP

20100148303 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a semiconductor substrate; an interlayer insulating film formed on the semiconductor substrate; a first inductor interconnect layer having a spiral pattern, formed to be embedded in a top portion of the interlayer insulating film; a barrier insulating film formed to cover the interlayer insulating film and... Agent: Mcdermott Will & Emery LLP

20100148306 - Capacitor and method of manufacturing the same: Disclosed are a capacitor and a method of manufacturing the same. The capacitor includes a plurality of polysilicon electrodes spaced apart from each other at a predetermined distance on a substrate, a dielectric layer between the polysilicon electrodes and having an air layer or void therein, a silicide on each... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20100148304 - Integrated circuit decoupling capacitors: Power supply decoupling capacitors are provided for integrated circuits. The decoupling capacitors may be distributed in clusters amongst powered circuit components. Each cluster may contain a number of individual capacitor cells that are connected in parallel. Each capacitor cell may contain a capacitor and a resistor connected in series with... Agent: Treyz Law Group

20100148305 - Semiconductor device and fabricating method thereof: A semiconductor device and fabricating method thereof are disclosed. The present invention includes an insulating layer on a semiconductor substrate, a contact plug in and protruding from the insulating layer, and a capacitor on the insulating layer and the exposed contact plug, having a dome shape.... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20100148307 - Semiconductor device including metal-insulator-metal capacitor arrangement: A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with... Agent: Young & Thompson

20100148308 - dopant profile control for ultrashallow arsenic dopant profiles: A method of manufacturing a semiconductor device comprises growing or depositing an implantation oxide layer, implanting a dopant, activating the dopant, and removing the implantation oxide layer after the step of activating the dopant.... Agent: Texas Instruments Incorporated

20100148309 - Method for manufacturing semiconductor device: There is provided a method for manufacturing a semiconductor device in which a selective growth mask for partially covering a growth substrate is formed on a growth substrate; a buffer layer that is thicker than the mask is formed on a non-mask part not covered by the mask on the... Agent: Frishauf, Holtz, Goodman & Chick, PC

20100148310 - Semiconductor wafer, semiconductor device using the same, and method and apparatus for producing the same: A method of processing a semiconductor wafer includes preheating the wafer to a preheating temperature that is less than a peak temperature, heating the wafer from the preheating temperature to the peak temperature at a first ramp rate that averages about 100° C. per second or more, and, immediately after... Agent: Lee & Morse, P.C.

20100148311 - Semiconductor device: Patterns provided on a surface of a substrate include an adhesion area pattern and one or more non-adhesion area patterns. A chip electrode on a backside of a semiconductor chip is attached to the adhesion area pattern by a conductive adhesive. Consequently, an area of patterns subjected to gold plating... Agent: Nixon & Vanderhye, PC

20100148312 - Reinforced smart cards & methods of making same: Reinforced smart cards with and methods of making an integrated circuit chip for smart are disclosed. In some embodiments, a method includes generally providing an integrated circuit wafer including a plurality of integrated circuits, providing a stiffener, attaching the stiffener top surface to the wafer bottom surface, and physically separating... Agent: Troutman Sanders LLP 5200 Bank Of America Plaza

20100148313 - Semiconductor apparatus and method of manufacturing the same: Disclosed herein is a semiconductor apparatus, wherein a technique for manufacturing one semiconductor region by dividing the one semiconductor region into a plurality of divisional regions in regard of a step is applied, and one-side device portions formed simultaneously by a one-side treatment conducted primarily for the divisional region on... Agent: Robert J. Depke Lewis T. Steadman

20100148314 - Semiconductor device and method for manufacuring the same: The present invention provides a semiconductor device and a method for manufacturing the same capable of inhibiting plasma damage. A semiconductor device according to one embodiment includes a protective pattern grounded to a semiconductor substrate in a scribe line area, on a wafer including a main chip area and the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20100148315 - Semiconductor wafer and a method of separating the same: A semiconductor wafer includes a plurality of predetermined separation lines extending from an upper surface to a bottom surface; and a semiconductor substrate including a plurality of chip regions segmented by the predetermined separation lines. Tensile stress is applied to regions of the semiconductor substrate provided with the predetermined separation... Agent: Mcdermott Will & Emery LLP

20100148316 - Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with tsv: A semiconductor device has a core semiconductor device with a through silicon via (TSV). The core semiconductor device includes a plurality of stacked semiconductor die and semiconductor component. An insulating layer is formed around the core semiconductor device. A conductive via is formed through the insulating layer. A first interconnect... Agent: Robert D. Atkins

20100148317 - Critical dimension reduction and roughness control: A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal... Agent: Beyer Law Group LLP

20100148319 - Substrates for high-efficiency thin-film solar cells based on crystalline templates: A three-dimensional thin-film semiconductor substrate having a plurality of ridges on the surface of the semiconductor substrate which define a base opening of an inverted pyramidal cavity and walls defining the inverted pyramidal cavity is provided. And a fabrication method for a 3-D TFSS by forming a porous silicon layer... Agent: HulseyIPIntellectual Property Lawyers, P.C.

20100148318 - Three-dimensional semiconductor template for making high efficiency thin-film solar cells: A semiconductor template having a top surface aligned along a (100) crystallographic orientation plane and an inverted pyramidal cavity defined by a plurality of walls aligned along a (111) crystallographic orientation plane. A method for manufacturing a semiconductor template by selectively removing silicon material from a silicon template to form... Agent: HulseyIPIntellectual Property Lawyers, P.C.

20100148320 - Vicinal gallium nitride substrate for high quality homoepitaxy: A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a... Agent: Intellectual Property / Technology Law

20100148321 - Micro-electro-mechanical-system device with particles blocking function and method for making same: The present invention discloses a MEMS device with particles blocking function, and a method for making the MEMS device. The MEMS device comprises: a substrate on which is formed a MEMS device region; and a particles blocking layer deposited on the substrate.... Agent: Tung & Associates / Randy W. Tung, Esq.

20100148322 - Composite substrate and method of fabricating the same: The invention specifically relates to methods of fabricating a composite substrate by providing a first insulating layer on a support substrate at a thickness of e1 and providing a second insulating layer on a source substrate at a thickness of e2, with each layer having an exposed face for bonding;... Agent: Winston & Strawn LLP Patent Department

20100148323 - Impurity introducing method using optical characteristics to determine annealing conditions: A subject of the present invention is to realize an impurity doping not to bring about a rise of a substrate temperature. Another subject of the present invention is to measure optically physical properties of a lattice defect generated by the impurity doping step to control such that subsequent steps... Agent: Pearne & Gordon LLP

20100148324 - Dual insulating layer diode with asymmetric interface state and method of fabrication: An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. The diode is a metal-insulator diode having a first metal layer, a first insulating layer, a second insulating layer and a second metal layer. At least one asymmetric interface state is provided... Agent: Vierra Magen/sandisk Corporation

20100148325 - Semiconductor dice with backside trenches filled with elastic material for improved attachment, packages using the same, and methods of making the same: Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal... Agent: Townsend And Townsend And Crew, LLP

20100148326 - Thermally enhanced electronic package: According to one embodiment, an electronic package includes a semiconductor die, a heat sink and a metallization layer interposed between the semiconductor die and the heat sink. The metallization layer attaches the semiconductor die to the heat sink. The metallization layer has a thickness of about 5 μm or less... Agent: Coats & Bennett/infineon Technologies

20100148327 - Semiconductor die package with clip interconnection: A semiconductor die package. The semiconductor die package includes a leadframe structure comprising a first lead structure comprising a die attach pad, a second lead structure, and a third lead structure. It also includes a semiconductor die comprising a first surface and a second surface. The semiconductor die is on... Agent: Townsend And Townsend And Crew, LLP

20100148328 - Power quad flat no-lead semiconductor die packages with isolated heat sink for high-voltage, high-power applications, systems using the same, and methods of making the same: Disclosed are PQFN semiconductor die packages for high-voltage, high-power applications, systems using the packages, and methods of making the packages. An exemplary package comprises a leadframe, a semiconductor die disposed on the leadframe, and a heat sink member disposed on the semiconductor die and the leadframe and integrated into the... Agent: Townsend And Townsend And Crew, LLP

20100148329 - Quad flat no lead (qfn) integrated circuit (ic) package having a modified paddle and method for designing the package: A QFN IC package is provided that has all of the advantages of the typical QFN IC package, but in addition, has a paddle that is configured to facilitate trace routing and/or via placement on the PWB or PCB on which the IC package is mounted. By configuring the paddle... Agent: Smith Frohwein Tempel Greenlee Blaha, LLC

20100148330 - Leadless package housing: A leadless package for semiconductor elements has at least two semiconductor elements which are situated on a connection region of a lead frame of the leadless package in such a way that when deformations of the semiconductor elements occur, the deformations of the semiconductor elements compensate one another.... Agent: Kenyon & Kenyon LLP

20100148331 - Semiconductor devices including semiconductor dice in laterally offset stacked arrangement: A semiconductor device assembly includes two or more dice stacked in laterally offset arrangement relative to one another. With such an arrangement, when a second semiconductor die is positioned over a first semiconductor die, bond pads of the first semiconductor die are exposed laterally beyond the second semiconductor die. The... Agent: Trask Britt, P.C./ Micron Technology

20100148332 - Semiconductor apparatus and manufacturing method thereof: A semiconductor apparatus includes a first wiring substrate, a second wiring substrate, a semiconductor chip, an adhesive layer and a molding resin. The second wiring substrate is stacked and connected on the first wiring substrate through a bump electrode. The semiconductor chip is mounted on the first wiring substrate by... Agent: Drinker Biddle & Reath (dc)

20100148333 - Packaging millimeter wave modules: A module, which in one embodiment may be a packaged millimeter waver module, includes a semiconductor lid portion; a packaging portion attached to the lid portion, wherein the packaging portion comprises a plurality of vias, a carrier portion, wherein a first semiconductor die is attached to the carrier portion, the... Agent: Freescale Semiconductor, Inc. Law Department

20100148334 - Intergrated circuit package support system: A system for supporting integrated circuit packages to prevent mechanical failure of the packages at their connection to a printed circuit board or card involves bracing the packages to the board or card, the packages may also be braced against one another. The structure is particularly well adapted to supporting... Agent: Fletcher Yoder (micron Technology, Inc.)

20100148336 - Integrated circuit packaging system having through silicon vias with partial depth metal fill regions and method of manufacture thereof: A method of manufacture of an integrated circuit packaging system includes: providing a silicon substrate having a circuitry layer; creating a partial via through the circuitry layer; filling the partial via with a plug having a bottom surface; creating a recess that is angled outward and exposes the bottom surface... Agent: Law Offices Of Mikio Ishimaru

20100148339 - Process for fabricating a semiconductor component support, support and semiconductor device: An electrical connection support for receiving a semiconductor component includes an electrical connection plate having electrical connection pads. A stand-off structure is provided over the electrical connection pads. The stand-off structure may include a supplementary layer provided on a zone of the electrical connection plate which includes the electrical connection... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20100148341 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a sensor including a sensor structure on a first side of the sensor and a periphery element surrounding the sensor structure; and a cap covering the sensor structure and having a second side bonded to the first side of the sensor. The cap includes a first... Agent: Posz Law Group, PLC

20100148340 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device includes: (a) half-dicing a semiconductor wafer including plural semiconductor chips, thereby forming dicing grooves in the semiconductor wafer, wherein each semiconductor chip includes a circuit and pads and wherein the semiconductor wafer includes: a first surface on which the circuit and the pads... Agent: Drinker Biddle & Reath (dc)

20100148335 - Semiconductor package, method of manufacturing same, semiconductor device and electronic device: A highly reliable semiconductor package in which faulty connections do not occur even when an external substrate is curved. The semiconductor package includes a semiconductor chip 1; an interposer substrate 10 arranged so as to enclose the semiconductor chip and having a first electrode pad 14, which is for connecting... Agent: Scully Scott Murphy & Presser, PC

20100148343 - Side stacking apparatus and method: A module has at least two ICs connected to each other such that they lie in different planes and are arranged as a first stack of ICs, a third IC is connected to at least one of the at least two ICs, wherein the third IC is off plane from... Agent: Foley & Lardner LLP

20100148337 - Stackable semiconductor package and process to manufacture same: In one form a stackable electrical device package has a first plurality of traces, the electrical device bonded to at least some of the first plurality of traces, a second plurality of vertical posts attached to the first plurality of traces, and encapsulation material enclosing the electrical device and sides... Agent: Hiscock & Barclay, LLP

20100148342 - Stacked semiconductor module: A stacked semiconductor module is made by stacking a second semiconductor device having a second semiconductor chip mounted to the top surface of a second semiconductor substrate above the top surface of a first semiconductor device having a first semiconductor chip mounted to a first semiconductor substrate. The top surface... Agent: Mcdermott Will & Emery LLP

20100148338 - Three dimensional semiconductor device: A 3D semiconductor device includes a conductive plate defining four sides and four recesses formed in the four sides, respectively. The conductive plate has first and second surfaces opposite to each other. A plurality of conductive leads are located in the recesses, respectively, and the conductive leads have first and... Agent: Reinhart Boerner Van Deuren P.C.

20100148347 - Chip scale package structure with can attachment: A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside... Agent: Stmicroelectronics, Inc.

20100148345 - Electronic devices including flexible electrical circuits and related methods: A packaged electronic device includes a die, a flexible circuit structure, and a barrier film disposed on the die. The die includes die circuitry and electrical contacts. The flexible circuit structure is bonded directly to the die, and includes electrical conductors encapsulated by structural layers. Each electrical conductor contacts a... Agent: The Eclipse Group LLP

20100148344 - Integrated circuit package system with input/output expansion: An integrated circuit package system includes: forming a base stacking package including: fabricating a base substrate, mounting an integrated circuit on the base substrate, positioning an input/output expansion substrate, having access ports around an inner array area, over the integrated circuit, and injecting a molding compound on the base substrate,... Agent: Law Offices Of Mikio Ishimaru

20100148351 - Method of packaging integrated circuit devices using preformed carrier: Disclosed is a method of packaging integrated circuit devices using a preformed carrier. In one illustrative embodiment, the method includes providing a carrier having a plurality of pockets formed therein, positioning an integrated circuit chip and a substrate in each of the plurality of pockets and conductively coupling the integrated... Agent: Perkins Coie LLP Patent-sea

20100148348 - Package substrate: A package substrate is disclosed. The package substrate as a printed circuit board, in which a semiconductor chip is mounted on one side thereof and the other side thereof is mounted on a main board, can include a substrate part, a first pad, which is formed on one side of... Agent: Mcdermott Will & Emery LLP

20100148350 - Semiconductor device and method for manufacturing the same: In a POP type semiconductor device comprising a second semiconductor package as an upper package stacked on a first semiconductor package as a lower package, a plurality of main surface-side lands formed on a first wiring substrate of the first semiconductor package are disposed distributively on both sides of a... Agent: Mattingly & Malur, P.C.

20100148346 - Semiconductor die package including low stress configuration: A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure... Agent: Townsend And Townsend And Crew, LLP

20100148349 - Semiconductor package having support chip and fabrication method thereof: A semiconductor package having a support chip and a fabrication method thereof. The semiconductor package includes a circuit substrate having a conductive pattern on the top surface. A first semiconductor die is attached on top of the circuit substrate. A second semiconductor die is attached on top of the first... Agent: Reinhart Boerner Van Deuren P.C.

20100148352 - Grid array packages and assemblies including the same: A semiconductor device assembly includes a substrate and a semiconductor die adjacent to a first surface of the substrate. The substrate also includes a second surface opposite from the first surface, an opening extending from the first surface and the second surface, contact pads on the second surface, and substrate... Agent: Trask Britt, P.C./ Micron Technology

20100148353 - Double-sided semiconductor device and method of forming top-side and bottom-side interconnect structures: A semiconductor device is made by forming a first active device on a first side of a semiconductor wafer. A first insulating layer is formed over the first side of the wafer. A first conductive layer is formed over the first insulating layer. A first interconnect structure is formed over... Agent: Robert D. Atkins

20100148354 - Integrated circuit packaging system having through silicon via with direct interconnects and method of manufacture thereof: A method of manufacture of an integrated circuit packaging system includes: providing a through silicon via die having an interconnect through a silicon substrate; depositing a re-distribution layer on the through silicon via die and connected to the interconnects; mounting a structure over the through silicon via die; connecting the... Agent: Law Offices Of Mikio Ishimaru

20100148355 - Integrated circuit package system employing wafer level chip scale packaging: An integrated circuit package system that includes: providing a substrate with a protective coating; attaching a labeling film to a support member in a separate process; joining the protective coating and the labeling film; and dicing the substrate, the protective coating, and the labeling film to form the integrated circuit... Agent: Law Offices Of Mikio Ishimaru

20100148356 - Stacked semiconductor device and manufacturing method thereof: A semiconductor device includes: a first substrate; a second substrate provided over the first substrate, and divided into a plurality of portions; a cooling member provided in a gap between the divided second substrate portions on the first substrate; and a third substrate provided on the second substrate portions and... Agent: Mcdermott Will & Emery LLP

20100148357 - Method of packaging integrated circuit dies with thermal dissipation capability: A method (20) of packaging integrated circuit dies (70) includes obtaining (22) a heat spreader substrate (24) having a top surface (38) with cavities (30) formed therein, each of the cavities (30) having a cavity floor (44). A surface (74) of each die (70) is attached (66) to one of... Agent: Meschkow & Gresham, P.L.C

20100148358 - Semiconductor device with a high thermal dissipation efficiency: A semiconductor device having a higher thermal dissipation efficiency includes a thermally conducting structure attached to a surface of the semiconductor device via soldering. The thermally conducting structure is essentially formed of a thermally conducting material and comprises an array of freestanding fins, studs or frames, or a grid of... Agent: Michael Buchenhorner, P.A.

20100148359 - Package on package assembly using electrically conductive adhesive material: Packages are joined together using an anisotropic conductive material that includes an electrically insulative component and a plurality of electrically conductive particles. The electrically conductive particles may complete electrical connection between inter-package connectors and bond pads that may otherwise fail. The electrically insulative component may be cured to act as... Agent: Lemoine Patent Services, PLLC

20100148361 - Semiconductor device and method for fabricating the same: A semiconductor device and a method for fabricating the same, including: a substrate having a mounting surface formed with a plurality of bonding fingers and covered with an insulating layer, the insulating layer having an opening formed therein for exposing the bonding fingers; and a chip coupled to the substrate... Agent: Edwards Angell Palmer & Dodge LLP

20100148362 - Semiconductor device and method for fabricating the same: A semiconductor device includes an electronic part including an electrode, a substrate including a substrate electrode electrically connected to the first electrode on an upper surface thereof, the first substrate electrode and the first electrode being arranged, facing each other, a connecting member configured to connect the electrode with the... Agent: Mcdermott Will & Emery LLP

20100148360 - Semiconductor device and method of forming a vertical interconnect structure for 3-d fo-wlcsp: A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die... Agent: Robert D. Atkins

20100148365 - Grid array connection device and method: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid... Agent: Schwegman, Lundberg & Woessner, P.A.

20100148364 - Semiconductor device and method for producing semiconductor device: A semiconductor device includes: a substrate having an external electrode formed thereon, the external electrode being capable of being electrically connected to an outside; and a semiconductor element having a surface electrode formed thereon, the surface electrode being made from an electrically conducting paste, the semiconductor element being mounted on... Agent: Nixon & Vanderhye, PC

20100148363 - Step cavity for enhanced drop test performance in ball grid array package: A ball grid array (BGA) package includes a substrate layer having first and second sides. A semiconductor chip is attached to the first side of the substrate layer by a dielectric adhesive layer. A plurality of solder balls are attached to the second side of the substrate layer. The solder... Agent: Stmicroelectronics, Inc.

20100148366 - Grain growth promotion layer for semiconductor interconnect structures: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the electromigration problem that is exhibited by prior art interconnect structures, are provided. In accordance with the present invention, a grain growth promotion layer, which promotes the formation of a... Agent: Scully, Scott, Murphy & Presser, P.C.

20100148367 - Semiconductor device and method for fabricating the same: A semiconductor device includes a die pad having a surface on which a first solder bonding layer is formed, and made of metal; and a semiconductor element fixed on the first solder bonding layer on the die pad by a solder material made mostly of bismuth. The first solder bonding... Agent: Mcdermott Will & Emery LLP

20100148368 - Semiconductor device: A semiconductor device where an outside connection terminal of a semiconductor element and an electrode of a wiring board are connected to each other via a conductive adhesive, the conductive adhesive includes a first conductive adhesive; and a second conductive adhesive covering the first conductive adhesive; wherein the first conductive... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20100148369 - Wire bonding method and semiconductor device: Wire bonding method for reducing height of a wire loop in a semiconductor device, including a first bonding step of bonding an initial ball formed at a tip end of a wire onto a first bonding point using a capillary, thereby forming a pressure-bonded ball; a wire pushing step of... Agent: Quinn Emanuel Urquhart Oliver & Hedges, LLP Koda/androlia

20100148370 - Through-silicon via and method for forming the same: A method for forming a through-silicon via includes the steps of defining a groove in each chip of a wafer which has a plurality of semiconductor chips; applying liquid polymer on the wafer to fill the groove; forming an insulation layer on a sidewall of the groove through patterning the... Agent: Ladas & Parry LLP

20100148372 - Integrated circuit package having reduced interconnects: A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating... Agent: Fletcher Yoder (micron Technology, Inc.)

20100148371 - Via first plus via last technique for ic interconnects: A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are... Agent: Qualcomm Incorporated

20100148376 - Flip chip mounting process and flip chip assembly: A flip chip mounting process includes the steps of supplying a resin (13) containing solder powder and a convection additive (12) onto a wiring substrate (10) having a plurality of electrode terminals (11), then bringing a semiconductor chip (20) having a plurality of connecting terminals (11) into contact with a... Agent: Wenderoth, Lind & Ponack L.L.P.

20100148374 - Method for low stress flip-chip assembly of fine-pitch semiconductor devices: A device including a first body (101) with terminals (102) on a surface (101a), each terminal having a metallic connector (110), which is shaped as a column substantially perpendicular to the surface. Preferably, the connectors have an aspect ratio of height to diameter of 2 to 1 or greater, and... Agent: Texas Instruments Incorporated

20100148373 - Stacked die parallel plate capacitor: A stacked integrated circuit having a first die with a first surface and a second die with a second surface facing the first surface, the stacked integrated circuit includes a capacitor. The capacitor is formed by a first conducting plate on a region of the first surface, a second conducting... Agent: Qualcomm Incorporated

20100148375 - Vertically tapered transmission line for optimal signal transition in high-speed multi-layer ball grid array packages: Broadly speaking, the embodiments of the present invention fill the need for methods of designing vertical transmission lines for optimal signal transition in multi-layer BGA packages. By controlling the impedance and geometry continuity of micro vias in each micro via layer in the package to follow smooth impedance and geometry... Agent: Martine Penilla & Gencarella, LLP

20100148377 - Intermediate structure of semiconductor device and method of manufacturing the same: An intermediate structure for semiconductor devices includes a wiring board, a plurality of semiconductor chips mounted on the wiring board, and a sealing body for collectively sealing the plurality of semiconductor chips and having a region with a different thickness.... Agent: Foley And Lardner LLP Suite 500

20100148378 - Thermosetting silicone resin composition, silicone resin, silicone resin sheet and use thereof: The present invention relates to a thermosetting silicone resin composition including a condensation reactable substituent group-containing silicon compound and an addition reactable substituent group-containing silicon compound; a silicone resin; a silicone resin sheet obtained from the thermosetting silicone resin composition or the silicone resin, and a use thereof.... Agent: Sughrue-265550

20100148379 - Epoxy resin composition for semiconductor encapsulation and semiconductor device produced by using the same: wherein X1 to X5, which may be the same or different, are each a hydrogen atom, an alkyl group having 1 to 9 carbon atoms, or a fluorine atom. The epoxy resin composition is an encapsulation material excellent in pot life, fluidity and curability, and has a lower chloride ion... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20100148380 - Thermosetting epoxy resin composition and semiconductor device: e

20100148381 - Semiconductor device: A semiconductor device is disclosed. One aspect provides a semiconductor device that includes a semiconductor chip including a first face and a second face opposite the first face, an encapsulant including inorganic particles encapsulating the semiconductor chip, a first metal layer attached to the first face of the semiconductor chip,... Agent: Dicke, Billig & Czaja

20100140578 - Non volatile memory cells including a composite solid electrolyte layer: Programmable metallization cells (PMC) that include a first electrode; a solid electrolyte layer including clusters of high ion conductive material dispersed in a low ion conductive material; and a second electrode, wherein either the first electrode or the second electrode is an active electrode, and wherein the solid electrolyte layer... Agent: Campbell Nelson Whipps, LLC

20100140579 - Silver-selenide/chalcogenide glass stack for resistance variable memory: The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to an embodiment of the invention a resistance variable memory element is provided having at least one silver-selenide layer in between glass layers, wherein at least one... Agent: Dickstein Shapiro LLP

20100140581 - Bottom electrode for memory device and method of forming the same: Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a metal plug. The invention can mitigate keyholes in the contacts by capping and encapsulating the conductive material used to form the contact. The exemplary cap... Agent: Dickstein Shapiro LLP

20100140580 - Phase change memory: A phase change memory is provided. The method includes forming contact plugs in a first dielectric layer. A second dielectric layer is formed overlying the first dielectric layer and a trench formed therein exposing portions of the contact plugs. A metal layer is formed over surfaces of the trench. One... Agent: Slater & Matsil, L.L.P.

20100140582 - Chalcogenide nanoionic-based radio frequency switch: A nonvolatile nanoionic switch is disclosed. A thin layer of chalcogenide glass engages a substrate and a metal selected from the group of silver and copper photo-dissolved in the chalcogenide glass. A first oxidizable electrode and a second inert electrode engage the chalcogenide glass and are spaced apart from each... Agent: Woodling, Krost And Rust

20100140583 - Phase change memory device and fabricating method therefor: A phase change memory device and fabricating method are provided. A disk-shaped phase change layer is buried within the insulating material. A center via and ring via are formed by a lithography. The center via is located in the center of the phase change layer and passes through the phase... Agent: Morris Manning Martin LLP

20100140584 - Method for producing catalyst-free single crystal silicon nanowires, nanowires produced by the method and nanodevice comprising the nanowires: Disclosed herein is a method for producing catalyst-free single crystal silicon nanowires. According to the method, nanowires can be produced in a simple and economical manner without the use of any metal catalyst. In addition, impurities contained in a metal catalyst can be prevented from being introduced into the nanowires,... Agent: Cantor Colburn, LLP

20100140585 - Quantum dot white and colored light-emitting devices: A light-emitting device comprising a population of quantum dots (QDs) embedded in a host matrix and a primary light source which causes the QDs to emit secondary light and a method of making such a device. The size distribution of the QDs is chosen to allow light of a particular... Agent: Steptoe & Johnson LLP

20100140587 - High-injection heterojunction bipolar transistor: A method for manufacturing high-injection heterojunction bipolar transistor capable of being used as a photonic device is disclosed. A sub-collector layer is formed on a substrate. A collector layer is then deposited on top of the sub-collector layer. After a base layer has been deposited on top of the collector... Agent: Bae Systems

20100140586 - Quantum dots having composition gradient shell structure and manufacturing method thereof: Provided are quantum dots having a gradual composition gradient shell structure which have an improvedluminous efficiency and optical stability, and a method of manufacturing the quantum dots in a short amount of time at low cost. In the method, the quantum dots can be manufactured in a short amount of... Agent: Sherr & Vaughn, PLLC

20100140588 - Catalyst support substrate, method for growing carbon nanotubes using the same, and transistor using carbon nanotubes: A catalyst supporting substrate includes a first region (54) which is formed on a substrate (50); and a second region (55) which is formed covering a part of the first region. The first region (54) includes a catalyst supporting portion (54a) containing a first material. The second region (55) includes... Agent: Scully Scott Murphy & Presser, PC

20100140589 - Ferroelectric tunnel fet switch and memory: A Ferroelectric tunnel FET switch as ultra-steep (abrupt) switch with subthreshold swing better than the MOSFET limit of 60 mV/decade at room temperature combining two key principles: ferroelectric gate stack and band-to-band tunneling in gated p-i-n junction, wherein the ferroelectric material included in the gate stack creates, due to dipole... Agent: Nixon & Vanderhye, PC

20100140590 - Transistor comprising carbon nanotubes functionalized with a non-fluoro containing electron deficient olefin or alkyne: The present invention is a transistor and a process for making the transistor in which the semiconductor component comprises at least one carbon nanotube functionalized by cycloaddition with a fluorinated olefin. Functionalization with the fluorinated olefin renders the carbon nanotube semiconducting.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20100140603 - Blue light emitting compound and organic light emitting diode device comprising the same: e

20100140592 - Composition comprising an indium-containing intrinsically conductive polymer: The invention relates to a composition which comprises an intrinsically conductive polymer and indium and which is particularly suitable for producing puncture injection layers in light emitting diodes. Methods for producing and using the inventive composition and electronic devices for the production thereof are also disclosed.... Agent: Swanson & Bratschun, L.L.C.

20100140591 - Electrical device fabrication from nanotube formations: A method for forming nanotube electrical devices, arrays of nanotube electrical devices, and device structures and arrays of device structures formed by the methods. Various methods of the present invention allow creation of semiconducting and/or conducting devices from readily grown SWNT carpets rather than requiring the preparation of a patterned... Agent: Winstead PC

20100140598 - Large area light emitting diode light source: The present invention relates to a LED light source comprising at least one layer of light emitting material (3), in particular organic light emitting material, sandwiched between two electrode layers (2, 4). At least one of the electrode layers (2, 4) is structured to form a pattern of electrode segments... Agent: Philips Intellectual Property & Standards

20100140607 - Light emitting element and light emitting device using the element: An object of the present invention is to provide a high-efficiency white light emitting element having a spectrum in a wide wavelength range. Another object is to provide a white light emitting element in which chromaticity of white color is hard to change over time. Still another object is to... Agent: Cook Alex Ltd

20100140602 - Organic electroluminescence device: There is provided an organic electroluminescence device comprising a pair of electrodes on a substrate and at least one organic layer containing a luminescence layer between the electrodes, the luminescence layer comprising at least 3 luminescence materials different in luminescent color, and the at least 3 luminescence materials being platinum... Agent: Solaris Intellectual Property Group, PLLC

20100140605 - Organic electroluminescence device and luminescence apparatus: The invention provides an organic EL device including a pair of electrodes and at least one luminescent layer between the pair of electrodes, the at least one luminescent layer including at least two phosphorescent materials, an electrically inert material, and a charge-transporting material, the at least two phosphorescent materials being... Agent: Solaris Intellectual Property Group, PLLC

20100140606 - Organic electroluminescence device and luminescence apparatus: The invention provides an organic EL device including a pair of electrodes and at least one luminescent layer located between the pair of electrodes, the luminescent layer including a blue phosphorescent material having a luminescence peak in a range of from 420 nm to less than 500 nm, a green... Agent: Solaris Intellectual Property Group, PLLC

20100140595 - Organic light emitting display device: An organic light emitting display device includes a first substrate, a plurality of organic light emitting devices on the first substrate, a second substrate arranged opposite and substantially parallel to the first substrate with the organic light emitting devices therebetween, a plurality of spacers between the organic light emitting devices... Agent: Christie, Parker & Hale, LLP

20100140604 - Organic light-emitting device: A light-emitting layer emits light having an emission spectrum having a primary peak in the range of wavelengths of 430 to 480 nm. The light-emitting layer contains a host compound and a dopant compound. The dopant compound has an electron affinity of 2.93 eV or more higher that is than... Agent: Canon U.s.a. Inc. Intellectual Property Division

20100140594 - Organic optoelectronic component: An organic optoelectronic component is provided, which includes a first electrode, an active layer formed on the first electrode, a second intermediate layer formed on the active layer, and a second electrode formed on the second intermediate layer, wherein the second intermediate layer is formed with a second mixture containing... Agent: Edwards Angell Palmer & Dodge LLP

20100140596 - Organic thin film transistor and method of manufacturing the same: Provided is an organic thin film transistor and method of forming the same. The organic thin film transistor can decrease threshold voltage and driving voltage by forming a thin organic dielectric layer in a lamella structure using a diblock copolymer including a hydrophilic polymer with high permittivity and a hydrophobic... Agent: Rabin & Berdo, PC

20100140597 - Organic thin film transistors comprising thienyl oligomers and their use as gaseous phase sensors: This invention pertains to gaseous analytes sensor devices comprising organic thin film transistor and, in particular sensors able to perform the enantiomeric discrimination of gaseous analytes. The organic thin films are characterized by comprising a compound of formula (I).... Agent: Hess Patent Law Firm, P.C.

20100140593 - Organic thin-film transistors: wherein M is a trivalent metal atom; each m represents the number of R substituents on the phenyl or naphthyl ring, and is independently an integer from 0 to 6; each R is independently selected from the group consisting of halogen, alkyl, substituted alkyl, alkoxy, substituted alkoxy, phenoxy, phenylthio, aryl,... Agent: Fay Sharpe / Xerox - Rochester

20100140601 - Polymer compound and method for producing the same, and light-emitting material, liquid composition, thin film, polymer light-emitting device, surface light source, display device, organic transistor and solar cell, each using the polymer compound: Disclosed is a polymer compound containing a repeating unit represented by the following general formula (1). (In the formula, Rf1 and Rg1 may be the same or different, and each represents an alkyl group having 1-12 carbon atoms or the like; Rd1 and Re1 may be the same or different,... Agent: Sughrue Mion, PLLC

20100140599 - Semiconductor device, method for manufacturing semiconductor device, and display: A semiconductor device includes an organic semiconductor layer 10 and an oxide semiconductor layer 11, and emits light.... Agent: Millen, White, Zelano & Branigan, P.C.

20100140600 - Thin film transistors incorporating interfacial conductive clusters: A field effect transistor includes a thin layer of discontinuous conductive clusters between the gate dielectric and the active layer. The active layer can include an organic semiconductor or a blend of organic semiconductor and polymer. Metals, metal oxides, predominantly non-carbon metallic materials, and/or carbon nanotubes may be used to... Agent: 3m Innovative Properties Company

20100140611 - Amorphous oxide and field effect transistor: In a field effect transistor, a channel layer of the field effect transistor is composed of an amorphous oxide including In, Zn, N and O, an atomic composition ratio of N to N and O (N/(N+O)) in the amorphous oxide is equal to or larger than 0.01 atomic percent and... Agent: Fitzpatrick Cella Harper & Scinto

20100140612 - Manufacturing method of thin film transistor using oxide semiconductor: A manufacturing method of a thin film transistor having at least a gate electrode, a gate insulation film, an oxide semiconductor layer, a first insulation film, a source electrode, a drain electrode, and a second insulation film on a substrate, including: forming the gate electrode on the substrate; forming the... Agent: Fitzpatrick Cella Harper & Scinto

20100140614 - Oxide semiconductor device and method of manufacturing the same and active matrix substrate: A phenomenon of change of a contact resistance between an oxide semiconductor and a metal depending on an oxygen content ratio in introduced gas upon depositing an oxide semiconductor film made of indium gallium zinc oxide, zinc tin oxide, or others in an oxide semiconductor thin-film transistor. A contact layer... Agent: Miles & Stockbridge PC

20100140613 - Semiconductor device: A semiconductor device includes an oxide semiconductor layer provided over a substrate having an insulating surface; a gate insulating film covering the oxide semiconductor layer; a first conductive layer and a second conductive layer laminated in this order over the gate insulating film; an insulating film covering the oxide semiconductor... Agent: Eric Robinson

20100140609 - Semiconductor device, polycrystalline semiconductor thin film, process for producing polycrystalline semiconductor thin film, field effect transistor, and process for producing field effect transistor: An object of the present invention is to provide a novel semiconductor device which is excellent in stability, uniformity, reproducibility, heat resistance, durability and the like, and can exert excellent transistor properties. The semiconductor device is a thin-film transistor, and this thin-film transistor uses, as an active layer, a polycrystalline... Agent: Millen, White, Zelano & Branigan, P.C.

20100140610 - Thin film transistor array panel and method for manufacturing the same: A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a... Agent: Haynes And Boone, LLPIPSection

20100140608 - Transistor and method of manufacturing the same: Example embodiments provide a transistor and a method of manufacturing the same. The transistor may include a channel layer formed of an oxide semiconductor and a gate having a three-dimensional structure. A plurality of the transistors may be stacked in a perpendicular direction to a substrate. At least some of... Agent: Harness, Dickey & Pierce, P.L.C

20100140615 - Active device array substrate: An active device array substrate including a substrate, a pixel array, and peripheral circuit is provided. The substrate has a display region and a peripheral region. The pixel array is disposed on the display region of the substrate, wherein the pixel array includes signal lines and pixels, each of the... Agent: Jianq Chyun Intellectual Property Office

20100140616 - Electronic device and method for manufacturing the same: Disclosed herewith is an electronic device capable of preventing the surfaces of the analyzing terminals from such external factors as oxidation, etc. so as to improve the accuracy of the analysis of the electronic device. The electronic device has plural signal lines and is to be mounted on a wiring... Agent: Mcginn Intellectual Property Law Group, PLLC

20100140617 - Semiconductor device manufacturing method and semiconductor device: A semiconductor device manufacturing method includes the steps of: forming a transistor on a surface side of a silicon layer of a silicon-on-insulator substrate, the silicon-on-insulator substrate being formed by laminating a substrate, an insulating layer, and the silicon layer; forming a first insulating film covering the transistor and a... Agent: Wolf Greenfield & Sacks, P.C.

20100140618 - Sensor and method for the manufacture thereof: A sensor includes at least one micro-patterned diode pixel that has a diode implemented in, on, or under a diaphragm, and the diaphragm in turn being implemented above a cavity. The diode is contacted via supply leads that are implemented at least in part in, on, or under the diaphragm,... Agent: Kenyon & Kenyon LLP

20100140619 - Photovoltaic device: The present invention is related to a photovoltaic device, the device comprising a first layer of a first semiconductor material of a first conductivity type, a second layer of a second semiconductor material of the opposite conductivity type of the first layer, and a third layer of a third porous... Agent: Knobbe Martens Olson & Bear LLP

20100140620 - Flat-panel display semiconductor process for efficient manufacturing: An embodiment is a method and apparatus to fabricate a flat panel display. A poly-last structure is formed for a display panel using an amorphous silicon or amorphous silicon compatible process. The poly-last structure has a channel silicon precursor. The display panel is formed from the poly-last structure using a... Agent: Parc-xerox/bstz Blakely Sokoloff Taylor & Zafman LLP

20100140623 - Array substrate for display device and method of fabricating the same: An array substrate for a display device includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode, the gate insulating layer having an organic-inorganic hybrid material; a semiconductor layer on the gate insulating layer over the gate electrode; source and drain electrodes spaced... Agent: Birch Stewart Kolasch & Birch

20100140621 - Light blocking member having variabe transmittance, display panel including the same, and manufacturing method thereof: A light blocking member having variable transmittance, a display panel including the same, and a manufacturing method thereof. A light blocking member having a variable transmittance according to one exemplary embodiment includes a polymerizable compound, a binder, and a thermochromic material that exhibits a black color at a temperature below... Agent: H.c. Park & Associates, PLC

20100140624 - Liquid crystal display device: A liquid crystal display device, includes: a gate line (14) provided as a first conductive layer to extend the gate line in a predetermined direction; a thin film transistor (13) including a gate electrode (13a) connected to the gate line (14); a first pixel electrode (12) provided as a second... Agent: Masao Yoshimura, Chen Yoshimura LLP

20100140626 - Thin film transistor array panel and method for manufacturing the same: A method for manufacturing a TFT array panel including forming a gate line having a gate electrode on a insulating layer, a gate insulating layer on the gate line, a semiconductor on the gate insulating layer, an ohmic contact on the semiconductor, a data line having a source electrode and... Agent: Innovation Counsel LLP

20100140625 - Thin film transistor array substrate structures and fabrication method thereof: A thin film transistor array substrate structure. The array substrate structure includes a thin film transistor array substrate, an organic material layer formed thereon, and a plurality of black matrices and color filter patterns disposed on the organic material layer. The invention also provides a method of fabricating the thin... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100140622 - Thin film transistor, fabricating method of thin film transistor and display device using the same: A thin film transistor comprises: a first transistor region and a second transistor region defined on a substrate; and a first transistor and a second transistor respectively disposed on the first and second transistor regions, the first transistor comprising: a first semiconductor layer having source, channel, and drain regions defined... Agent: Brinks Hofer Gilson & Lione

20100140627 - Package for semiconductor devices: A packaged semiconductor device including a semiconductor die mounted on a header of a leadframe. A plurality of spaced external conductors extends from the header and at least one of the external conductors has a bond wire post at one end thereof such that a bonding wire extends between the... Agent: Patent Docket Administrator Lowenstein Sandler PC

20100140628 - Insulated gate bipolar transistors including current suppressing layers: An insulated gate bipolar transistor (IGBT) includes a first conductivity type substrate and a second conductivity type drift layer on the substrate. The second conductivity type is opposite the first conductivity type. The IGBT further includes a current suppressing layer on the drift layer. The current suppressing layer has the... Agent: Myers Bigel Sibley & Sajovec, P.A.

20100140629 - Light-emitting diode and method for fabricating the same: The invention discloses a method for fabricating a light-emitting diode. In an embodiment of the invention, the method comprises the following steps of (a) preparing a substrate; (b) forming an epitaxial layer on the substrate, wherein the epitaxial layer has an upper surface; (c) forming a mask layer on a... Agent: Birch Stewart Kolasch & Birch

20100140630 - Method and apparatus for manufacturing led devices using laser scribing: A method of manufacturing a light-emitting device using laser scribing to improve overall light output is disclosed. Upon placing a semiconductor wafer having light emitting diode (“LED”) devices separated by streets on a wafer chuck, the process arranges a first surface of semiconductor wafer containing front sides of the LED... Agent: James M. Wu Jw Law Group

20100140631 - Display device and method for manufacturing the same: Provided are a display device in which variation in output characteristics of the photodiode is suppressed, and a method for manufacturing the display device. The display device is provided with the active matrix substrate (2) and photodiode (6). First, on a substrate of glass (12), a silicon film (8) and... Agent: Nixon & Vanderhye, PC

20100140633 - Methods for combining light emitting devices in a package and packages including combined light emitting devices: Methods of forming a light emitting device package assembly include defining a chromaticity region in a two dimensional chromaticity space, and subdividing the defined chromaticity region into at least three chromaticity subregions, providing a plurality of light emitting devices that emit light having a chromaticity that falls within at least... Agent: Myers Bigel Sibley & Sajovec, P.A.

20100140632 - Multi-electrode light emitting device: The invention relates to a broad-band light emitting diode having an active layer composed of a plurality of light emission regions of differing materials for emitting light at a plurality of wavelengths, wherein each of the emission regions of the active layer is electrically controlled by a separate electrode for... Agent: Pequignot + Myers LLC

20100140634 - Solid state emitter package including red and blue emitters: A solid state emitter package includes a principally red solid state emitter having peak emissions within 590 nm to 680 nm, a principally blue solid state emitter having peak emissions within 400 nm to 480 nm, and at least one of a common leadframe, common substrate, and common reflector, with... Agent: Intellectual Property / Technology Law

20100140635 - Composite high reflectivity layer: A high efficiency light emitting diode with a composite high reflectivity layer integral to said LED to improve emission efficiency. One embodiment of a light emitting diode (LED) chip comprises an LED and a composite high reflectivity layer integral to the LED to reflect light emitted from the active region.... Agent: Koppel, Patrick, Heybl & Dawson

20100140651 - Diffraction grating light-emitting diode: h

20100140642 - Light emitting device and method for manufacturing the same: The light emitting device of the invention comprises a first electrode, a second electrode being light transmitting, and a carrier sandwiched between the first electrode and the second electrode and containing light emitters, wherein the first electrode has a plurality of projections or a pn junction formed with a p-type... Agent: Birch Stewart Kolasch & Birch

20100140643 - Light emitting device and method of manufacturing the same: The light emitting device, and corresponding method of manufacture, the light emitting device including a second electrode layer; a second conductive type semiconductor layer formed on the second electrode layer; an active layer formed on the second conductive type semiconductor layer; a first conductive type semiconductor layer formed with a... Agent: Birch Stewart Kolasch & Birch

20100140653 - Light emitting diode structure and method for fabricating the same: The present invention discloses a light emitting diode structure and a method for fabricating the same. In the present invention, a substrate is placed in a solution to form a chemical reaction layer on carved regions; the carved region is selectively etched to form a plurality of concave zones and... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20100140637 - Light emitting diode with a dielectric mirror having a lateral configuration: A light emitting diode is disclosed that includes an active structure, a first ohmic contact on the active structure, and a transparent conductive oxide layer on the active structure opposite the first ohmic contact. The transparent conductive oxide layer has a larger footprint than said active structure. A dielectric mirror... Agent: Koppel, Patrick, Heybl & Dawson

20100140636 - Light emitting diode with improved light extraction: A light emitting diode is disclosed that includes an active region and a plurality of exterior surfaces. A light enhancement feature is present on at least portions of one of the exterior surfaces of the diode, with the light enhancement feature being selected from the group consisting of shaping and... Agent: Koppel, Patrick, Heybl & Dawson

20100140650 - Light emitting element, light emitting device using the light emitting element, and method for manufacturing light emitting element: A light emitting device includes a light emitting element, including a substrate including group III nitride compound semiconductor, a luminous layer structure including group III nitride compound semiconductor, the luminous layer structure formed on a first surface of the substrate, and an irregular surface formed on a second surface of... Agent: Mcginn Intellectual Property Law Group, PLLC

20100140639 - Optical semiconductor device and method of manufacturing optical semiconductor device: An optical semiconductor device includes a light emitting element having a first surface and a second surface, the first surface having a first electrode provided thereon, the second surface being located on the opposite side from the first surface and having a second electrode provided thereon; a first conductive member... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100140644 - Organic el display device and manufacturing method thereof: An object of the invention is to provide an organic EL display device manufacturing method that allows the reliability of the organic EL display device having undergone a defect repair process to be improved. A method for manufacturing an organic EL display device, the method including an organic EL element... Agent: Antonelli, Terry, Stout & Kraus, LLP

20100140645 - Organic electroluminescence device: Disclosed is an organic electroluminescence device containing a pair of electrodes on a substrate, two or more luminescence layers disposed between the electrodes, and an intermediate layer containing a charge transporting material and disposed between the two or more luminescence layers, each of the two or more luminescence layers contains... Agent: Solaris Intellectual Property Group, PLLC

20100140649 - Organic light emitting diode display and method of manufacturing the same: An organic light emitting diode display includes a substrate member, a plurality of pixel electrodes formed on the substrate member, an organic emission layer formed on the pixel electrodes, and a first common electrode formed on the organic emission. A transmitting layer may be formed on the first common electrode... Agent: Knobbe Martens Olson & Bear LLP

20100140640 - Semiconductor device and method for manufacturing the same: Provided is an optical semiconductor device includes: a light-emitting layer having a first main surface, a second main surface opposed to the first main surface, a first electrode and a second electrode which are formed on the second main surface; a fluorescent layer provided on the first main surface; a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100140641 - Semiconductor light emitting apparatus including semiconductor light emitting device, red phosphor and green phosphor, and image display using the semiconductor light emitting apparatus: A semiconductor light emitting apparatus including a semiconductor light emitting device, a green phosphor emitting green light and a red phosphor emitting red light is provided. The green phosphor is a rare earth activated inorganic phosphor, and the red phosphor is a semiconductor particle phosphor. The minimum among respective differences... Agent: Birch Stewart Kolasch & Birch

20100140648 - Semiconductor light emitting device and method for producing the same: A semiconductor light emitting device can be configured to maintain high luminance and to suppress the possibility of the occurrence of wire breakage with high quality and reliability. A method for producing such a semiconductor light emitting device with a high process yield is also disclosed. The semiconductor light emitting... Agent: Cermak Kenealy Vaidya & Nakajima LLP

20100140646 - Semiconductor light emitting diode: A semiconductor LED is disclosed. The semiconductor LED can include a light emitting structure, which can be composed of an N-type semiconductor layer, an active layer, and a P-type semiconductor layer stacked in said order; a transparent electrode, formed on an upper surface of the light emitting structure; and a... Agent: Mcdermott Will & Emery LLP

20100140647 - Semiconductor light emitting diode: A semiconductor LED and a method manufacturing the semiconductor LED are disclosed. The method can include: forming a light emitting structure, which includes an N-type semiconductor layer, an active layer, and a P-type semiconductor layer stacked together, on a substrate; processing a division groove in the shape of a dotted... Agent: Mcdermott Will & Emery LLP

20100140652 - Surface-textured encapsulations for use with light emitting diodes: Surface-textured encapsulations for use with light emitting diodes. In an aspect, a light emitting diode apparatus is provided that includes a light emitting diode, and an encapsulation formed upon the light emitting diode and having a surface texture configured to extract light. In an aspect, a method includes encapsulating a... Agent: Haynes And Boone, LLPIPSection

20100140638 - Thermosetting resin composition for light reflection, method for manufacturing the resin composition and optical semiconductor element mounting substrate and optical semiconductor device using the resin composition: This invention provides a heat curable resin composition for light reflection, which, after curing, can realize high reflectance in a range of visible light to near ultraviolet light, has excellent heat deterioration resistance and tablet moldability, and is less likely to cause burrs during transfer molding, and a process for... Agent: Antonelli, Terry, Stout & Kraus, LLP

20100140654 - Light emitting element module and method for sealing light emitting element: Disclosed is a method for sealing a light-emitting device wherein formation of air bubbles in a light-emitting device module can be prevented by performing no gelation after fitting of a cover member. This method also enables to seal a light-emitting device by using a gel sealing material composed of a... Agent: K&l Gates LLP

20100140656 - Semiconductor light-emitting device: The present disclosure relates to a semiconductor light-emitting device generating light by recombination of electrons and holes. The semiconductor light-emitting device includes: a first bonding electrode and a second bonding electrode supplying the current for the recombination of the electrons and holes; a first branch electrode and a second branch... Agent: Harness, Dickey, & Pierce, P.l.c

20100140655 - Transparent heat spreader for leds: A heat spreader for an LED can include a thermally conductive and optically transparent member. The bottom side of the heat spreader can be configured to attach to a light emitting side of the LED. The top and/or bottom surface of the heat spreader can have a phosphor layer formed... Agent: Haynes And Boone, LLPIPSection

20100140657 - Power semiconductor device and the method of manufacturing the same: A semiconductor device according to the invention includes n-type semiconductor substrate 1; trenches 15 formed in the surface portion of semiconductor substrate 1; a protruding semiconductor region between trenches 15; p-type base layer 2 in the protruding semiconductor region, p-type base layer 2 being positioned as deep as or shallower... Agent: Rossi, Kimms & Mcdowell LLP.

20100140658 - Method of manufacturing semiconductor device including insulated gate bipolar transistor and diode: In a method of manufacturing a semiconductor device, a semiconductor substrate of a first conductivity type having first and second surfaces is prepared. Second conductivity type impurities for forming a collector layer are implanted to the second surface using a mask that has an opening at a portion where the... Agent: Posz Law Group, PLC

20100140659 - Electrostatic discharge protection device and related circuit: An ESD protection device comprises a P-type substrate, a first substrate-triggered silicon controlled rectifiers (STSCR) disposed in the P-type substrate and a second STSCR disposed in the P-type substrate. The first STSCR comprises a first N-well, a first P-well, a first N+ diffusion region, a first P+ diffusion region, and... Agent: North America Intellectual Property Corporation

20100140660 - Semiconductor heterostructure diodes: Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to... Agent: Fish & Richardson P.C.

20100140661 - Apparatus for converting of infrared radiation into electrical current: An apparatus is described for converting infrared radiation into electric current with a photodiode which comprises two semiconductor layers (1, 2) with a heterojunction which are each connected to an electrode (3, 4) and of which one consists of a doped inorganic semiconductor. In order to ensure advantageous detection it... Agent: Collard & Roe, P.C.

20100140662 - Optical receiver and method of forming the same: Provided are an optical receiver and a method of forming the same. The optical receiver includes a lens, a photo detector, and a hetero-junction bipolar transistor. The lens is attached to a backside of a substrate. The photo detector is disposed on a top surface of the substrate. The hetero-junction... Agent: Rabin & Berdo, PC

20100140663 - Cmos compatable fabrication of power gan transistors on a <100> silicon substrate: In an AlGaN channel transistor formed on a <100> orientation silicon wafer, a hole with walls slanted at 54 degrees is etched into the silicon to provide a <111> orientation substrate surface for forming the AlGaN channel transistor.... Agent: Vollrath & Associates

20100140664 - Methods of fabricating nitride-based transistors with a cap layer and a recessed gate and related devices: An anneal of a gate recess prior to formation of a gate contact, such as a Schottky contact, may reduce gate leakage and/or provide a high quality gate contact in a semiconductor device, such as a transistor. The use of an encapsulation layer during the anneal may further reduce damage... Agent: Myers Bigel Sibley & Sajovec, P.A.

20100140665 - Gallium nitride material devices and thermal designs thereof: Gallium nitride material devices and methods associated with the devices are described. The devices may be designed to provide enhanced thermal conduction and reduced thermal resistance. The increased thermal conduction through and out of the gallium nitride devices enhances operability of the devices, including providing excellent RF operation, reliability, and... Agent: Wolf Greenfield & Sacks, P.C.

20100140666 - Semiconductor devices having l-shaped cell blocks: Semiconductor devices are provided including a plurality of L-shaped cell blocks each including,a cell array and a plurality of decoders disposed in horizontal and vertical directions of the cell array. The plurality of L-shaped cell blocks are oriented in a diagonal direction intersecting the horizontal and vertical directions. Related methods... Agent: Myers Bigel Sibley & Sajovec

20100140667 - Solid-state imaging device and manufacturing method therefor: Disclosed herein is a solid-state imaging device including a first transfer electrode portion and a second transfer electrode portion having a pattern area rate higher than that of the first transfer electrode portion. The first transfer electrode portion includes a plurality of first transfer electrodes having a single-layer structure of... Agent: Robert J. Depke Lewis T. Steadman

20100140668 - Shallow trench isolation regions in image sensors: An image sensor includes an imaging area that includes a plurality of pixels, with each pixel including a photosensitive charge storage region formed in a substrate. A passivation implantation region contiguously surrounds the side wall and bottom surfaces of each trench in the one or more trench isolation regions. A... Agent: Eastman Kodak Company Patent Legal Staff

20100140670 - Integration of mems and cmos devices on a chip: A method of forming CMOS circuitry integrated with MEMS devices includes bonding a wafer to a top surface layer having contacts formed to CMOS circuitry. A handle wafer is then removed from one of the top or bottom surfaces of the CMOS circuitry, and MEMS devices are formed in a... Agent: Honeywell/slw Patent Services

20100140669 - Microfabrication methods for forming robust isolation and packaging: Exemplary embodiments provide an electrical single-crystal silicon (SCS) isolation device and a method for manufacturing the SCS isolation device. The isolation device can include a trench isolation structure formed using a trench having sidewall dielectrics and a follow-up filling of a metal or a polymer that is conductive or nonconductive.... Agent: Mh2 Technology Law Group, LLP

20100140671 - Semiconductor device and method of manufacturing the semiconductor device: A method of manufacturing a semiconductor device includes forming silicon pillar 11 on substrate 10, forming a protective film which covers an upper end portion and a lower end portion of a side surface of silicon pillar 11, forming a constricted portion by anisotropic etching in a portion of the... Agent: Sughrue Mion, PLLC

20100140672 - Field effect transistor: A field effect transistor includes a Schottky layer; a stopper layer formed of InGaP and provided in a recess region on the Schottky layer; a cap layer provided on the stopper layer and formed of GaAs; and a barrier rising suppression region configured to suppress rising of a potential barrier... Agent: Young & Thompson

20100140674 - Mosfet with multiple fully silicided gate and method for making the same: A field-effect transistor is provided. The field-effect transistor includes a gate structure including a fully silicided gate material overlying a gate dielectric disposed on a substrate, the fully silicided gate material having an upper region and a lower region, wherein the lower region has a first lateral dimension in accordance... Agent: International Business Machines Corporation Dept. 18g

20100140673 - Printing shielded connections and circuits: An embodiment is a method and apparatus to construct a shielded cable, wire, or circuit. A first insulator layer is deposited on a first conductor or semiconductor layer. A second conductor or semiconductor layer is deposited on the first insulator layer. A second insulator layer is deposited on the first... Agent: Parc-xerox/bstz Blakely Sokoloff Taylor & Zafman LLP

20100140675 - Cmos image sensor with improved backside surface treatment: An apparatus and method for fabricating an array of backside illuminated (“BSI”) image sensors is disclosed. Front side components of the BSI image sensors are formed into a front side of the array. A dopant layer is implanted into a backside of the array. The dopant layer establishes a dopant... Agent: Blakely Sokoloff Taylor & Zafman LLP

20100140677 - Semiconductor device: A semiconductor device of the present invention has a first contact and a second contact which are located over a device isolation film so as to be opposed with each other, and have a length in the horizontal direction larger than the height; a first electro-conductive pattern located on the... Agent: Young & Thompson

20100140676 - Semiconductor devices including buried gate electrodes including bitline shoulder attack protection and methods of forming such semiconductor devices: A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, a plurality of buried gate electrodes extending below an upper surface of the active regions of the semiconductor device, a plurality of bit lines extending on the semiconductor substrate along a first direction, a... Agent: Lee & Morse, P.C.

20100140678 - Flash memory device and manufacruting method the same: A flash memory device and a method of manufacturing a flash memory device. A flash memory device may include a device isolation layer and/or an active area formed on and/or over a semiconductor substrate. A flash memory device may include a memory gate formed on and/or over an active area... Agent: Sherr & Vaughn, PLLC

20100140680 - Double polysilicon process for non-volatile memory: A process flow for creating a non-volatile memory cell, the process flow including the steps of forming a doped well in a semiconducting portion of a substrate, forming a gate dielectric layer on top of the substrate, depositing a first polysilicon layer on top of the gate dielectric layer, patterning... Agent: Lng/mosys Joint Customer C/o Luedeka, Neely & Graham, P.C.

20100140681 - Semiconductor device and method of manufacturing therefor: An active region on a semiconductor substrate is electrically isolated by trench isolation. A structure of the trench isolation is constituted of a trench; a silicon oxide film formed on the inner wall of trench; an oxidation preventive film formed between silicon oxide film and semiconductor substrate; and a filling... Agent: Mcdermott Will & Emery LLP

20100140679 - Stacked dual-gate nmos devices with antimony source-drain regions and methods for manufacturing thereof: A three-dimensional memory structure includes multiple layers of memory devices, each memory device including a dual-gate device. A dual-gate device includes an active layer between a first gate structure and a second gate structure. Each gate structure is isolated from the active layer by a dielectric layer and is located... Agent: Haynes And Boone, LLPIPSection

20100140682 - Nonvolatile semiconductor memory device and method for manufacturing the same: In a nonvolatile semiconductor memory device, a tunnel insulating layer, a charge storage layer and a charge block layer are formed on a silicon substrate in this order, and a plurality of control gate electrodes are provided above the charge block layer. Moreover, a cap layer made of silicon nitride... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100140686 - Flash memory and method of manufacturing a flash memory: A semiconductor memory which includes a semiconductor substrate, a plurality of memory cells, and a plurality of active regions disposed in the substrate between adjacent ones of the memory cells. At least two contact electrodes are disposed between adjacent ones of the memory cells and each being connected to one... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100140685 - Nonvolatile memory devices: Nonvolatile memory devices and methods of manufacturing nonvolatile memory devices are provided. The method includes patterning a bulk substrate to form an active pillar; forming a charge storage layer on a side surface of active pillar; and forming a plurality of gates connected to the active pillar, the charge storage... Agent: Myers Bigel Sibley & Sajovec

20100140684 - Nonvolatile semiconductor memory device and method for manufacturing the same: On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100140683 - Silicon nitride film and nonvolatile semiconductor memory device: Provided is a silicon nitride film which has an excellent charge storage capacity and thus is useful as a charge storage layer of a semiconductor memory device. The silicon nitride film having substantially uniform trap density in the film thickness direction has high charge storage performance. The silicon nitride film... Agent: Smith, Gambrell & Russell

20100140687 - High-voltage mos devices having gates extending into recesses of substrates: An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an... Agent: Slater & Matsil, L.L.P.

20100140688 - Semiconductor device and method of forming semiconductor device: A semiconductor device includes a first semiconductor pillar, a first insulating film covering a side face of the first semiconductor pillar, a first electrode covering the first insulating film, a second semiconductor pillar, a second insulating film covering a side face of the second semiconductor pillar, and a second electrode... Agent: Young & Thompson

20100140690 - Gate of trench type mosfet device and method for forming the gate: A gate of a trench type MOSFET device and a method of forming a gate. A gate of a trench type MOSFET device may include a gate oxide film formed on and/or over a trench type gate poly such that parasitic capacitance may be produced in a gate poly. An... Agent: Sherr & Vaughn, PLLC

20100140689 - Trench-based power semiconductor devices with increased breakdown voltage characteristics: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.... Agent: Townsend And Townsend And Crew, LLP

20100140692 - Methods of fabricating semiconductor devices having multiple channel transistors and semiconductor devices fabricated thereby: In methods of fabricating a semiconductor device having multiple channel transistors and semiconductor devices fabricated thereby, the semiconductor device includes an isolation region disposed within a semiconductor substrate and defining a first region. A plurality of semiconductor pillars self-aligned with the first region and spaced apart from each other are... Agent: Mills & Onello LLP

20100140691 - Semiconductor device and manufacturing method of semiconductor device: A semiconductor device includes a semiconductor substrate in which a first trench is formed and a second trench is formed at the middle portions of the first trench; and a first ion implantation layer that is formed on the surface of the semiconductor substrate and on the bottom of the... Agent: Sherr & Vaughn, PLLC

20100140693 - Inverted-trench grounded-source fet structure using conductive substrates, with highly doped substrates: This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by... Agent: Bo-in Lin

20100140694 - Semiconductor device having sub-surface trench charge compensation regions and method: In one embodiment, a semiconductor device is formed having sub-surface charge compensation regions in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two... Agent: Mr. Jerry Chruma Semiconductor Components Industries, L.L.C.

20100140695 - Trench-based power semiconductor devices with increased breakdown voltage characteristics: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.... Agent: Townsend And Townsend And Crew, LLP

20100140696 - Trench-based power semiconductor devices with increased breakdown voltage characteristics: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.... Agent: Townsend And Townsend And Crew, LLP

20100140697 - Trench-based power semiconductor devices with increased breakdown voltage characteristics: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.... Agent: Townsend And Townsend And Crew, LLP

20100140698 - Electronic device including a trench and a conductive structure therein and a process of forming the same: An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region,... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20100140699 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a logic device and a LDMOS device. The logic device including a first well of a first conductive type formed in the substrate, a first source region and a first drain region formed in the first well, and a first gate electrode formed over the first... Agent: Sherr & Vaughn, PLLC

20100140704 - Lateral double diffused metal oxide semiconductor device and method of making the same: An LDMOS device and method for making the same are disclosed. The LDMOS device comprises a first well, a second well, a third well, a first ion implantation region, and a second ion implantation region. The first well is in a semiconductor substrate. The second well is in the first... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20100140702 - Semiconductor device and manufacturing method thereof: A semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device may include an epitaxial layer over a semiconductor substrate, a first well region over a epitaxial layer, a first isolation layer and/or a third isolation layer at opposite sides of said first well region and/or a... Agent: Sherr & Vaughn, PLLC

20100140700 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device may include a substrate and a laterally diffused metal oxide semiconductor (LDMOS) device. A semiconductor device may include a second conductive type well formed on and/or over a substrate. An LDMOS device may include a drain... Agent: Sherr & Vaughn, PLLC

20100140703 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes a substrate having a first conductor-type, a buried layer of a second conductor-type on the substrate, a drain, and a first guard-ring on one side of the drain, a second guard-ring on one side... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20100140701 - Semiconductor device and method of manufacturing the same: A semiconductor device and a method of manufacturing the same are disclosed. The method includes forming ion impurity regions of a first conductivity type by forming a trench in a semiconductor substrate and implanting impurity ions into a lower portion of the trench at different depths; forming an oxide region... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20100140705 - Dielectric structure having lower-k and higher-k materials: An electronic device including in any sequence: (a) a semiconductor layer; and (b) a dielectric structure comprising a lower-k dielectric polymer and a higher-k dielectric polymer, wherein the lower-k dielectric polymer is in a lower concentration than the higher-k dielectric polymer in a region of the dielectric structure closest to... Agent: Fay Sharpe / Xerox - Rochester

20100140707 - Metal-gated mosfet devices having scaled gate stack thickness: Metal-oxide semiconductor field effect transistor (MOSFET) devices having metal gate stacks and techniques for improving performance thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate having a buried oxide layer at least a portion of which is configured to serve as a primary background... Agent: Michael J. Chang, LLC

20100140706 - Method of manufacturing thin film transistor and thin film transistor substrate: Provided is a method of manufacturing a thin film transistor that can improve self-alignment. In this method, a semiconductor layer comprising a first doped region, a second doped region and a channel region is formed on a sacrificial layer on a first substrate. Next, the semiconductor layer is separated from... Agent: Rabin & Berdo, PC

20100140708 - Multi-thickness semiconductor with fully depleted devices and photonic integration: Techniques are disclosed that facilitate fabrication of semiconductors including structures and devices of varying thickness. One embodiment provides a method for semiconductor device fabrication that includes thinning a region of a semiconductor wafer upon which the device is to be formed thereby defining a thin region and a thick region... Agent: Bae Systems

20100140709 - Semiconductor device structures including transistors with energy barriers adjacent to transistor channels and associated methods: A semiconductor device structure includes a transistor with an energy barrier beneath its transistor channel. The energy barrier prevents leakage of stored charge from the transistor channel into a bulk substrate. Methods for fabricating semiconductor devices that include energy barriers are also disclosed.... Agent: Trask Britt, P.C./ Micron Technology

20100140710 - Semiconductor device and manufacturing method of the same: A semiconductor device includes: a semiconductor layer; an element isolation region formed in the semiconductor layer for separation between a memory element part and a logic element part; first and second field-effect transistors formed in the memory element part and having first and second gate electrodes on a first surface... Agent: K&l Gates LLP

20100140711 - Semiconductor device and manufacturing method thereof: Generation of dislocation and increase of diffusion resistance at edge portions of source/drain regions in a CMIS are prevented. When source/drain regions in a CMIS are formed, argon is implanted to a P-well layer as a dislocation-suppressing element and nitrogen is implanted to an N-well layer as a dislocation-suppressing element... Agent: Brundidge & Stanger, P.C.

20100140712 - Electro static discharge clamping device: Electrostatic discharge clamp devices are described. In one embodiment, the semiconductor device includes a first transistor, the first transistor including a first source/drain and a second source/drain, the first source/drain coupled to a first potential node, the second source/drain coupled to a second potential node. The device further includes a... Agent: Slater & Matsil LLP

20100140713 - Transistor-type protection device and semiconductor integrated circuit: A transistor-type protection device includes: a semiconductor substrate; a well of a first-conductivity-type formed in the semiconductor substrate; a source region of a second-conductivity-type formed in the well; a gate electrode formed on the well via a gate insulating film at one side of the source region; plural drain regions... Agent: Robert J. Depke Lewis T. Steadman

20100140714 - Low loss substrate for integrated passive devices: Electronic elements (44, 44′, 44″) having an active device region (46) and integrated passive device (IPD) region (60) on a common substrate (45) preferably include a composite dielectric region (62, 62′, 62″) in the IPD region underlying the IPD (35) to reduce electromagnetic (E-M) (33) coupling to the substrate (45).... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20100140715 - Semiconductor device: A semiconductor device includes: a semiconductor region of first conductivity type provided in a semiconductor layer of first conductivity type; a first semiconductor region of second conductivity type; a second semiconductor region of second conductivity type; a third semiconductor region of second conductivity type having a lower impurity concentration than... Agent: Turocy & Watson, LLP

20100140716 - N/p metal crystal orientation for high-k metal gate vt modulation: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The... Agent: Haynes And Boone, LLPIPSection

20100140718 - Semiconductor device: A semiconductor device having a plurality of chips is reduced in size. In HSOP (semiconductor device) for driving a three-phase motor, a first semiconductor chip including a pMISFET and a second semiconductor chip including an nMISFET are mounted over each of a first tab, second tab, and third tab. The... Agent: Mattingly & Malur, P.C.

20100140717 - Tunable gate electrode work function material for transistor applications: Described herein are metal gate electrode stacks including a low resistance metal cap in contact with a metal carbonitride diffusion barrier layer, wherein the metal carbonitride diffusion barrier layer is tuned to a particular work function to also serve as a work function metal for a pMOS transistor. In an... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20100140719 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a substrate which includes an element region and an isolation region, a transistor portion which includes a gate insulating film formed on the element region, and a gate electrode having a metal film formed on the gate insulating film and a first semiconductor film formed on... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20100140720 - Semiconductor device and method of fabricating the same: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At... Agent: Myers Bigel Sibley & Sajovec

20100140721 - high frequency semiconductor device: A high frequency semiconductor device includes: a field effect transistor including gate terminal electrodes, source terminal electrodes, and a drain terminal electrode; an input circuit pattern and an output circuit pattern which are disposed adjoining of the field effect transistor; a plurality of input bonding wires configured to connect the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100140722 - Strained semiconductor device and method of making same: To form a semiconductor device, an electrode layer is formed over a semiconductor body. The electrode layer includes an amorphous portion. A liner, e.g., a stress-inducing liner, is deposited over the electrode layer. The electrode layer is annealed to recrystallize the amorphous portion of the electrode layer. The liner can... Agent: Slater & Matsil LLP

20100140723 - Nanotube and graphene semiconductor structures with varying electrical properties: Nanotube and graphene transducers are disclosed. A transducer according to the present invention can include a substrate, a plurality of semiconductive structures, one or more metal pads, and a circuit. The semiconductive structures can be nanotubes or graphene located entirely on a surface of the substrate, such that each of... Agent: Troutman Sanders LLP 5200 Bank Of America Plaza

20100140724 - Embedded microelectromechanical systems (mems) semiconductor substrate and related method of forming: An embedded MEMS semiconductor substrate is set forth and can be a starting material for subsequent semiconductor device processing. A MEMS device is formed in a semiconductor substrate, including at least one MEMS electrode and a buried silicon dioxide sacrificial layer has been applied for releasing the MEMS. A planarizing... Agent: Lisa K. Jorgenson Stmicroelectronics, Inc.

20100140725 - Pressure sensor: A piezoresistive pressure sensor is especially suitable for measuring smaller pressures and has a small linearity error. The pressure sensor is manufactured from a BESOI wafer having first and second silicon layers and an oxide layer arranged therebetween. The pressure sensor includes, formed from the first silicon layer of the... Agent: Bacon & Thomas, PLLC

20100140727 - Magnetic thin film and method of manufacturing the same, and various application devices using the same: The present invention relates to a magnetic thin film containing a L11 type Co—Pt—C alloy in which atoms are orderly arranged, and can realize an order degree excellent in regard to the L11 type Co—Pt—C alloy to achieve excellent magnetic anisotropy of the magnetic thin film. Therefore, in the various... Agent: Venable LLP

20100140726 - Method and system for providing magnetic elements having enhanced magnetic anisotropy and memories using such magnetic elements: A method and system for providing a magnetic element are described. The magnetic element includes pinned and free layers, a nonmagnetic spacer layer between the free and pinned layers, and a stability structure. The free layer is between the spacer layer and the stability structure. The free layer has a... Agent: Convergent Law Group LLP

20100140728 - Lateral overflow drain and channel stop regions in image sensors: A lateral overflow drain and a channel stop are fabricated using a double mask process. Each lateral overflow drain is formed within a respective channel stop. Due to the use of two mask layers, one edge of each lateral overflow drain is aligned, or substantially aligned, with an edge of... Agent: Eastman Kodak Company Patent Legal Staff

20100140729 - Lateral overflow drain and channel stop regions in image sensors: A lateral overflow drain and a channel stop are fabricated using a double mask process. Each lateral overflow drain is formed within a respective channel stop. Due to the use of two mask layers, one edge of each lateral overflow drain is aligned, or substantially aligned, with an edge of... Agent: Pedro P. Hernandez Patent Legal Staff

20100140730 - Semiconductor devices and systems: A semiconductor device is disclosed. The semiconductor device comprises, a first region of a first conductivity type, a second region of a second conductivity type disposed adjacent to the first region to form a p-n junction structure, a resistance modification region of the second conductivity type, and a field response... Agent: General Electric Company Global Research

20100140731 - Image sensors including photoelectric converting units having multiple impurity regions: An image sensor includes a semiconductor layer, and first and second photoelectric converting units including first and second impurity regions in the semiconductor layer that are spaced apart from each other and that are at about an equal depth in the semiconductor layer, each of the impurity regions including an... Agent: Myers Bigel Sibley & Sajovec

20100140733 - Back-side illuminated image sensor: In an example embodiment, the backside-illuminated image sensor includes a substrate including a plurality of photoelectric conversion devices being separated by a semiconductor. The backside-illuminated sensor further includes a transparent electrode layer or a metal layer formed on a surface of a substrate. As a positive bias voltage or a... Agent: Harness, Dickey & Pierce, P.L.C

20100140732 - Method and apparatus for backside illuminated image sensors using capacitively coupled readout integrated circuits: The images sensor includes a readout circuit capacitatively coupled to a memory circuit. The readout circuit includes: (i) a photon detector to receive a plurality of photons and to provide a charge signal corresponding to the received photons, (ii) a resettable integrator that is reset multiple times over a single... Agent: Snell & Wilmer L.L.P. (teledyne)

20100140734 - Electronic device and method for manufacturing thereof: An electronic device, including a substrate, a functional structure constituting a functional element formed on the substrate, and a cover structure forming a cavity portion in which the functional structure is disposed, is disclosed. In the electronic device, the cover structure includes a laminated structure of an interlayer insulating film... Agent: Oliff & Berridge, PLC

20100140735 - Nanostructures for dislocation blocking in group ii-vi semiconductor devices: A compound semiconductor workpiece with reduced defects and greater strength that uses Group II-VI semiconductor nanoislands on a substrate. Additional layers of Group II-VI semiconductor are grown on the nanoislands using MBE until the newly formed layers coalesce to form a uniform layer of a desired thickness. In an alternate... Agent: Momkus Mccluskey, LLC

20100140737 - Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures: A semiconductor wafer contains a substrate having a plurality of active devices formed thereon. An analog circuit is formed on the substrate. The analog circuit can be an inductor, metal-insulator-metal capacitor, or resistor. The inductor is made with copper. A through substrate via (TSV) is formed in the substrate. A... Agent: Robert D. Atkins

20100140736 - Semiconductor device and method of embedding integrated passive devices into the package electrically interconnected using conductive pillars: A semiconductor device has a first insulation layer formed over a sacrificial substrate. A first conductive layer is formed over the first insulating layer. Conductive pillars are formed over the first conductive layer. A pre-fabricated IPD is disposed between the conductive pillars. An encapsulant is formed around the IPD and... Agent: Robert D. Atkins

20100140738 - Semiconductor device and method of forming compact coils for high performance filter: s

20100140739 - Semiconductor device and fabricating method thereof: Disclosed is a semiconductor device which includes a substrate having an air layer or void therein, an interlayer dielectric film above the substrate, and a metal wiring having a spiral structure on the interlayer dielectric film corresponding to or over the air layer. The semiconductor device exhibits reduced parasitic capacitance... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20100140740 - Semiconductor device: A semiconductor device includes: a first capacitor including an upper electrode, a lower electrode, an intermediate electrode arranged between the upper electrode and the lower electrode, and a shield line arranged in the same layer as the intermediate electrode; and a second capacitor, including an upper electrode, a lower electrode,... Agent: Mcginn Intellectual Property Law Group, PLLC

20100140742 - Semiconductor device and method of forming thin film capacitor: A semiconductor device has a first coil structure formed over the substrate. A second coil structure is formed over the substrate adjacent to the first coil structure. A third coil structure is formed over the substrate adjacent to the second coil structure. The first and second coil structures are coupled... Agent: Robert D. Atkins

20100140743 - Semiconductor device and method of manufacturing the same: There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20100140741 - Structure of capacitor set: A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor... Agent: Jianq Chyun Intellectual Property Office

20100140744 - Methods of depositing electrically active doped crystalline si-containing films: Methods of making Si-containing films that contain relatively high levels of Group III or Group V dopants involve chemical vapor deposition using trisilane and a dopant precursor. Extremely high levels of substitutional incorporation may be obtained, including crystalline silicon films that contain at least about 3×1020 atoms cm−3 of an... Agent: Knobbe, Martens, Olson & Bear LLP

20100140745 - Pulsed selective area lateral epitaxy for growth of iii-nitride materials over non-polar and semi-polar substrates: An epitaxy procedure for growing extremely low defect density non-polar and semi-polar III-nitride layers over a base layer, and the resulting structures, is generally described. In particular, a pulsed selective area lateral overgrowth of a group III nitride layer can be achieved on a non-polar and semi-polar base layer. By... Agent: Dority & Manning, P.A.

20100140746 - Improved process for preparing cleaned surfaces of strained silicon: The present invention relates to a method of treating wafers comprising at least one surface layer of silicon-germanium (SiGe) and a layer of strained silicon (sSi) in contact with the SiGe layer, the sSi layer being exposed by etching of the SiGe layer, the method comprising the steps of: (a)... Agent: Traskbritt, P.C.

20100140748 - Integrated circuits on a wafer and methods for manufacturing integrated circuits: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a plurality of integrated circuits (1a, 1b, 1c) formed on the wafer substrate (2). Each integrated circuit (1a, 1b, 1c) comprises an electric circuit (24) and some of the integrated circuits (1b, 1c) comprise, in addition to their... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100140747 - Semiconductor devices: In a method of manufacturing a semiconductor device, a pad including at least one insulating interlayer and at least one conductive wiring may be formed in a pad area of a substrate. At least one wiring may be formed adjacent to the conductive wiring. At least one insulation layer may... Agent: Mills & Onello LLP

20100140750 - Parallel plane memory and processor coupling in a 3-d micro-architectural system: An IC device is constructed in a manner that allows for the memory and processor elements to be positioned one above the other on parallel planes of a 3-D structure. Interconnections between the memory(s) and the processor(s) are accomplished by using through substrate stacking (TSS) techniques. This arrangement provides the... Agent: Qualcomm Incorporated

20100140749 - Semiconductor device: A semiconductor device with a TSV and a shelter is provided. The semiconductor device includes a substrate, a circuit area, at least a TSV and a shelter. The circuit area and the TSV are disposed on the substrate, and the TSV penetrates through the substrate. The shelter is disposed on... Agent: North America Intellectual Property Corporation

20100140751 - Semiconductor device and method of forming a conductive via-in-via structure: A semiconductor device is made from a semiconductor wafer containing semiconductor die separated by a peripheral region. A conductive via-in-via structure is formed in the peripheral region or through an active region of the device to provide additional tensile strength. The conductive via-in-via structure includes an inner conductive via and... Agent: Robert D. Atkins

20100140752 - Semiconductor device and method of forming compliant polymer layer between ubm and conformal dielectric layer/rdl for stress relief: A semiconductor device has a first conductive layer formed over a top surface of a substrate. A first insulating layer is formed over the substrate. A first dielectric layer is formed over the first insulating layer. A second conductive layer is formed over the first conductive layer and first dielectric... Agent: Robert D. Atkins

20100140753 - Stacked semiconductor component having through wire interconnect and method of fabrication: A stacked semiconductor component includes a plurality of semiconductor substrates in a stacked array and a continuous wire extending through aligned vias on the semiconductor substrates of the stacked array in electrical contact with contacts on the semiconductor substrates. A method for fabricating the semiconductor component includes the steps of... Agent: Stephen A Gratton The Law Office Of Steve Gratton

20100140754 - Film-forming material, silicon-containing insulating film and method for forming the same: Disclosed is a silicon-containing film-forming material which contains an organosilane compound represented by the following general formula (1). (In the formula, R1-R4 may be the same or different and represent a hydrogen atom, an alkyl group having 1-4 carbon atoms, a vinyl group or a phenyl group; R5 represents an... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100140755 - Rare-earth oxides, rare-earth nitrides, rare-earth phosphides and ternary alloys: Fabrication of new forms of rare-earth oxides, rare-earth nitrides and rare-earth phosphides is disclosed. Further, ternary compounds composed of binary (rare-earth oxides, rare-earth nitrides and rare-earth phosphides) mixed with silicon and or germanium to form compound semiconductors. The presented growth techniques and material system can be applied to silicon electronics,... Agent: Fernandez & Associates, LLP

20100140756 - Apparatus for manufacturing silicon oxide thin film and method for forming the silicon oxide thin film: An object of the present invention is to provide a semiconductor thin film device which employs a silicon oxide thin film having an equivalent level of high insulating performance to those currently used in electronic devices, through a low-temperature printing process on a plastic substrate having plasticity or other types... Agent: Venable LLP

20100140758 - Integrated circuit with improved transmission line structure and electromagnetic shielding between radio frequency circuit paths: An integrated circuit is disclosed having through silicon vias spaced apart one from another and conductors, each coupled to one or more of the through silicon vias, the conductors in aggregate in use forming a segmented conductive plane maintained at a same potential and forming an electromagnetic shield.... Agent: Townsend And Townsend And Crew, LLP

20100140757 - Semiconductor package having an antenna with reduced area and method for fabricating the same: A semiconductor package includes an electromagnetic shielding member for shielding electromagnetic waves. An antenna is disposed on an upper face of the electromagnetic shielding member and includes an antenna part with a plurality of conductive particles electrically connected with each other and an insulation part disposed on the upper face... Agent: Ladas & Parry LLP

20100140760 - Alpha shielding techniques and configurations: Embodiments of the present disclosure provide an apparatus including a semiconductor die having a plurality of integrated circuit devices, a pad structure electrically coupled to at least one integrated circuit device of the plurality of integrated circuit devices via an interconnect layer, an electrically insulative layer disposed on the interconnect... Agent: Schwabe, Williamson & Wyatt, P.C.

20100140759 - Semiconductor device and method of forming a shielding layer over a semiconductor die after forming a build-up interconnect structure: A semiconductor device is made by forming a build-up interconnect structure over a substrate. A semiconductor die is mounted to the build-up interconnect structure. The semiconductor die is electrically connected to the build-up interconnect structure. A ground pad is formed on the build-up interconnect structure. An encapsulant is formed over... Agent: Robert D. Atkins

20100140761 - Quad flat package: A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe... Agent: Robert D. Atkins

20100140762 - Interconnection of lead frame to die utilizing flip chip process: Embodiments in accordance with the present invention relate to techniques which avoid the problems of deformation in the shape of a solder connection in a flip chip package, resulting from solder reflow. In one embodiment, a solder-repellent surface is created adjacent to the solder to constrain the reflow and thereby... Agent: Townsend And Townsend And Crew, LLP

20100140763 - Integrated circuit packaging system with stacked paddle and method of manufacture thereof: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle and a terminal adjacent to the package paddle; mounting a stack paddle over the package paddle with the stack paddle at a non-center offset with the package paddle; mounting a stack integrated circuit over the... Agent: Law Offices Of Mikio Ishimaru

20100140766 - Large die package structures and fabrication method therefor: A method for fabricating large die package structures is provided wherein at least portions of the leadtips of at least a plurality of leadfingers of a leadframe are electrically insulated. A die is positioned on the electrically insulated leadtips. The die is electrically connected to at least a plurality of... Agent: Law Offices Of Mikio Ishimaru

20100140765 - Leadless integrated circuit packaging system and method of manufacture thereof: A method of manufacture of a leadless integrated circuit packaging system includes: providing a substrate; patterning a die attach pad on the substrate; forming a tiered plated pad array around the die attach pad; mounting an integrated circuit die on the die attach pad; coupling an electrical interconnect between the... Agent: Law Offices Of Mikio Ishimaru

20100140764 - Wire-on-lead package system and method of manufacture thereof: A method of manufacture of a wire-on-lead package system includes: providing a die attach paddle with paddle extensions distributed along the periphery of the die attach paddle, providing leadfingers surrounding the die attach paddle, attaching a semiconductor die to the die attach paddle wherein the semiconductor die is larger than... Agent: Law Offices Of Mikio Ishimaru

20100140767 - Component stacking using pre-formed adhesive films: A method of forming integrated circuits includes laminating a patterned film including an opening onto a wafer, wherein a bottom die in the wafer is exposed through the opening. A top die is placed into the opening. The top die fits into the opening with substantially no gap between the... Agent: Slater & Matsil, L.L.P.

20100140770 - Integrated circuit packaging system having asymmetric encapsulation structures and method of manufacture thereof: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a first internal integrated circuit structure and a second internal integrated circuit structure over the substrate; connecting the first internal integrated circuit structure and the second internal integrated circuit structure to the substrate with internal... Agent: Law Offices Of Mikio Ishimaru

20100140769 - Integrated circuit packaging system using bottom flip chip die bonding and method of manufacture thereof: A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate cavity; mounting a bottom flip chip die below the substrate; mounting an internal integrated circuit die above the substrate; filling between the internal integrated circuit die and the substrate and between the bottom... Agent: Law Offices Of Mikio Ishimaru

20100140774 - Method of producing external pads on a semiconductor device, and semiconductor device: External electrical connection pads are provided on a semiconductor device. A well is formed in an outer surface for the semiconductor device to at least partially expose an internal electrical connection pad. An electrical connection tab is formed which has an internal branch extending over the internal pad, an external... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20100140775 - Semiconductor device and method for manufacturing the same: Provided are a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a circuit layer, a metal interconnection layer, and a deep via. The circuit layer is formed on a semiconductor substrate. The metal interconnection layer is formed on the circuit layer. The metal interconnection layer... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20100140772 - Semiconductor device and method of forming vertical interconnect structure in substrate for ipd and baseband circuit separated by high-resistivity molding compound: A semiconductor device is made with a conductive via formed through a top-side of the substrate. The conductive via extends vertically through less than a thickness of the substrate. An integrated passive device (IPD) is formed over the substrate. A plurality of first conductive pillars is formed over the first... Agent: Robert D. Atkins

20100140771 - Semiconductor package and method of forming z-direction conductive posts embedded in structurally protective encapsulant: A semiconductor package is made using a prefabricated post carrier including a base plate and plurality of conductive posts. A film encapsulant is disposed over the base plate of the post carrier and around the conductive posts. A semiconductor die is mounted to a temporary carrier. The post carrier and... Agent: Robert D. Atkins

20100140777 - Stacked ball grid array package module utilizing one or more interposer layers: A multilayer module comprised of stacked IC package layers is disclosed. A plurality of layers preferably having ball grid array I/O are stacked and interconnected using one or more interposer layers for the routing of electronic signals to appropriate locations in the module through angularly depending leads. The stack is... Agent: Foley & Lardner LLP

20100140773 - Stacked chip, micro-layered lead frame semiconductor package: Semiconductor packages that contain stacked chips on a micro-layered lead frame and methods for making such semiconductor packages are described. The semiconductor packages contain a full array of land pads that has been formed from a lead frame. The packages comprise multiple chips that are stacked vertically and separated by... Agent: Kenneth E. Horton Kirton & Mcconkle

20100140768 - Systems and processes for forming three-dimensional circuits: Provided are systems and processes for forming a three-dimensional circuit on a substrate. A radiation source produces a beam that is directed at a substrate having an isolating layer interposed between circuit layers. The circuit layers communicate with reach other via a seed region exhibiting a crystalline surface. At least... Agent: Peters Verny , L.L.P.

20100140776 - Triaxial through-chip connecton: A method performed on a wafer having multiple chips each including a doped semiconductor and substrate involves etching an annulus trench, metalizing an inner and an outer perimeter side wall of the annulus trench, etching a via trench into the wafer, making a length of the via trench electrically conductive,... Agent: Foley & Lardner LLP

20100140778 - Package, method of manufacturing the same and use thereof: The flexible package (100) comprises coupling means (20) for electrical coupling to an external component, a chip (30) with contact pads (32) that face the coupling means (20) and are electrically coupled thereto, and an electrically insulating encapsulation (40) encapsulating the chip (30) and being attached to the coupling means... Agent: Philips Intellectual Property & Standards

20100140782 - Printed circuit board having built-in integrated circuit package and fabrication method therefor: A Printed Circuit Board (PCB) is provided in which at least one built-in Integrated Circuit (IC) package has a plurality of conductive bumps on an IC. The plurality of conductive bumps are for external electrical connection. The IC package is accommodated within a core layer of a multi-layer PCB by... Agent: The Farrell Law Firm, LLP

20100140781 - Quad flat non-leaded package and manufacturing method thereof: A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps... Agent: J C Patents

20100140780 - Semiconductor device and method of forming an ipd beneath a semiconductor die with direct connection to external devices: A semiconductor device has a conductive layer formed on a substrate. The conductive layer has a first portion constituting contact pads and a second portion constituting an integrated passive device such as an inductor. A spacer is formed on the substrate around the second portion of the conductive layer. The... Agent: Robert D. Atkins

20100140779 - Semiconductor package with semiconductor core structure and method of forming same: A semiconductor device is made by providing a temporary carrier for supporting the semiconductor device. An integrated passive device (IPD) structure is formed over the temporary carrier. The IPD structure includes an inductor, resistor, and capacitor. Conductive posts are mounted to the IPD structure, and first semiconductor die is mounted... Agent: Robert D. Atkins

20100140784 - Accessing or interconnecting integrated circuits: Multiple integrated circuits (ICs) die, from different wafers, can be picked-and-placed, front-side planarized using a vacuum applied to a planarizing disk, and attached to each other or a substrate. The streets between the IC die can be filled, and certain techniques or fixtures allow application of monolithic semiconductor wafer processing... Agent: Schwegman, Lundberg & Woessner, P.A.

20100140783 - Semiconductor device and method of forming bond wires and stud bumps in recessed region of peripheral area around the device for electrical interconnection to other devices: A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad... Agent: Robert D. Atkins

20100140785 - Semiconductor device: A method of assembling a semiconductor device includes providing a chip attached to an elastic carrier, and supporting the elastic carrier with a stiffener. The method additionally includes removing the stiffener from the elastic carrier after attaching the elastic carrier to a board.... Agent: Dicke, Billig & Czaja

20100140787 - Semiconductor device, semiconductor package for use therein, and manufacturing method thereof: A semiconductor package includes a substrate for mounting and fixing a semiconductor chip thereon and a connecting pattern. The substrate is provided with an elongate opening formed therein. The semiconductor chip is fixed with its surface being mounted on the substrate and with its electrode being aligned within the elongate... Agent: Volentine & Whitt PLLC

20100140786 - Semiconductor power module package having external bonding area: Provided is a semiconductor power module package including a bonding area on a direct bonding cupper (DBC) board. The semiconductor power module package includes: one or more semiconductor chips; a sealing member sealing the one or more semiconductor chips; a plurality of leads electrically connected to the one or more... Agent: Cantor Colburn, LLP

20100140788 - Manufacturing fan-out wafer level packaging: Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface and a bond pad defined on the top surface, and a substrate having a cavity. An adhesive layer is positioned between a top surface of the cavity and the bottom surface of the integrated circuit,... Agent: Stmicroelectronics, Inc.

20100140790 - Chip having thermal vias and spreaders of cvd diamond: An integrated circuit chip having a heat spreader comprising CVD diamond extending along the chip support body and thermal vias extending through the support body in regions free of active devices or functional elements. The thermal vias may thermally conductive and electrically conductive or may be thermally conductive and electrically... Agent: Campbell Nelson Whipps, LLC

20100140789 - Integrated circuit packaging system with exposed terminal interconnects and method of manufacture thereof: A method of manufacture of an integrated circuit packaging system includes: providing a lead; mounting an inner package so that the lead is peripheral to the inner package, and the inner package having a connection pad; forming an exposed terminal interconnect on the connection pad; and encapsulating the inner package,... Agent: Law Offices Of Mikio Ishimaru

20100140791 - Integrated circuit packaging structure and method of making the same: The invention provides an integrated circuit packaging and method of making the same. The integrated circuit packaging includes a substrate, a semiconductor die, a heat-dissipating module, and a protection layer. The substrate has an inner circuit formed on a first surface, and an outer circuit formed on a second surface... Agent: Birch Stewart Kolasch & Birch

20100140792 - Graphite nanoplatelets for thermal and electrical applications: This disclosure concerns a procedure for bulk scale preparation of high aspect ratio, 2-dimensional nano platelets comprised of a few graphene layers, Gn. n may, for example, vary between about 2 to 10. Use of these nano platelets in applications such as thermal interface materials, advanced composites, and thin film... Agent: Knobbe Martens Olson & Bear LLP

20100140793 - Process for manufacturing contact elements for probe card assembles: A process for making contact elements for a probe card assembly includes steps of forming a first continuous trench in a substrate along a first direction, and forming simultaneously a plurality of tip structures adjacent one to another in the first continuous trench in a second direction substantially normal to... Agent: N. Kenneth Burraston Kirton & Mcconkie

20100140794 - Apparatus and method for packaging circuits: An apparatus comprises an integrated circuit die including a main body having a top layer, a bottom layer, and a peripheral edge surface extending between the top layer and the bottom layer. The integrated circuit die also includes a bond pad on the main body, an edge contact at the... Agent: Schwegman, Lundberg & Woessner/micron

20100140797 - Device mounting board and method of manufacturing the board, semiconductor module and method of manufacturing the module: A device mounting board is provided with: an insulating resin layer; a wiring layer provided on one major surface of the insulating resin layer; and a bump electrode electrically connected to the wiring layer and configured to be projected from the wiring layer toward the insulating resin layer. The bump... Agent: Mcdermott Will & Emery LLP

20100140799 - Extended redistribution layers bumped wafer: A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of... Agent: Robert D. Atkins

20100140796 - Manufacturing method of semiconductor device, and semiconductor device: A manufacturing method of a semiconductor device includes a first to fourth steps. The first step includes a step of determining an UBM (Under Bump Metal) radius of an UBM of a chip. The second step includes a step of determining a first curvature radius of a solder bump formed... Agent: Mcginn Intellectual Property Law Group, PLLC

20100140798 - Semiconductor chip bump connection apparatus and method: Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and... Agent: Timothy M Honeycutt Attorney At Law

20100140795 - Semiconductor device and method of forming conductive pillars in recessed region of peripheral area around the device for electrical interconnection to other devices: A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A first insulating layer is formed over the die. A recessed region with angled sidewall is formed in the peripheral area. A first conductive layer is formed over the first insulating layer outside... Agent: Robert D. Atkins

20100140800 - Semiconductor device, and method of manufacturing multilayer wiring board and semiconductor device: A semiconductor device includes a multilayer wiring board and a semiconductor chip mounted on the multilayer wiring board. Electrode pads of the semiconductor chip include: first electrode pads including electrode pads respectively disposed in the vicinity of corners of the back surface of the semiconductor chip; and second electrode pads... Agent: Hamre, Schumann, Mueller & Larson P.C.

20100140801 - Device: In a device acting as a semiconductor device, a first chip has a first protective layer pattern while a second chip has a second protective layer pattern which is two-dimensionally symmetrical with the first protective layer pattern to provide a reflection symmetrical relationship between the first and the second protective... Agent: Mcginn Intellectual Property Law Group, PLLC

20100140802 - Film forming method and film forming apparatus: On a surface of an object to be treated, a Mn-containing thin film or CuMn-containing alloy thin film is formed by heat treatment (CVD or ALD) by using a Mn-containing source gas (or Mn-containing source gas and a Cu-containing gas) and an oxygen-containing gas (for instance, water vapor) as a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100140803 - Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board: A method of manufacturing a semiconductor device having a transition layer, including (a) forming a wiring and a die pad on a wafer, (b) forming a thin film layer on an entire surface of the wafer obtained in the step (a), (c) forming a resist layer on the thin film... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100140804 - Dual metal interconnects for improved gap-fill, reliability, and reduced capacitance: Embodiments of apparatus and methods for forming dual metal interconnects are described herein. Other embodiments may be described and claimed.... Agent: Intel Corporation C/o Cpa Global

20100140805 - Bump structure for stacked dies: A bump structure that may be used for stacked die configurations is provided. Through-silicon vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion... Agent: Slater & Matsil, L.L.P.

20100140806 - Method for forming super contact in semiconductor device: A method for forming a super contact in a semiconductor device is disclosed. The method enables forming a barrier film selectively on the silicon substrate, leaving the metal contact exposed for perfect isolation of the metal pad from the silicon substrate after formation of the super contact.... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20100140807 - Insulating film material, multilayer wiring board and production method thereof, and semiconductor device and production method thereof: where R1 may be the same or different to each other in the unit repeated “n” times, and each represents C1-4 hydrocarbon or aromatic hydrocarbon; R2 may be the same or different to each other in the unit repeated “n” times, and each represents C1-4 hydrocarbon or aromatic hydrocarbon; n... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20100140808 - Power distribution in a vertically integrated circuit: A first through via is electrically insulated from surrounding wafer substrate material. A second through via is not electrically insulated from the surrounding wafer substrate material. This configuration is advantageous when the non-insulated via serves as the path for either Vdd or GND. By not insulating the through via, a... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20100140810 - Chip package with coplanarity controlling feature: A chip package includes a substrate, an integrated circuit proximate a top surface of the substrate, and a cap comprising encapsulant that encapsulates the integrated circuit on at least a portion of the top surface of the substrate. The chip package further includes at least one extension feature positioned on... Agent: Stmicroelectronics, Inc.

20100140809 - Integrated circuit packaging system with a protrusion on an inner stacking module and method of manufacture thereof: A method of manufacture of an integrated circuit packaging system includes: providing an inner stacking module die; encapsulating the inner stacking module die with an inner stacking module encapsulation to form an inner stacking module, the inner stacking module encapsulation having an inner stacking module protrusion having a planar protrusion... Agent: Law Offices Of Mikio Ishimaru

20100140811 - Semiconductor die interconnect formed by aerosol application of electrically conductive material: An interconnect terminal is formed on a semiconductor die by applying an electrically conductive material in an aerosol form, for example by aerosol jet printing. Also, an electrical interconnect between stacked die, or between a die and circuitry in an underlying support such as a package substrate, is formed by... Agent: Haynes Beffel & Wolfeld LLP

20100140812 - Semiconductor device: Semiconductor device 1 according to the present invention includes wiring board 8 having mounting surface 8a mounted with laminated semiconductor chips 2 and plural semiconductor chips 2 mounted on mounting surface 8a of wiring board 8. Plural semiconductor chips 2 mounted on mounting surface 8a of wiring board 8 include... Agent: Young & Thompson

20100140813 - Integrated circuit packaging system and method of manufacture thereof: A method of manufacture of an integrated circuit packaging system includes providing an integrated circuit having an active side and a non-active side; forming a channel through the integrated circuit; forming an indent, having a flange and an indent side, from a peripheral region of the non-active side; and forming... Agent: Law Offices Of Mikio Ishimaru

20100140814 - Rf device and method with trench under bond pad feature: Electronic elements (44, 44′, 44″) having an active device region (46) and bonding pad (BP) region (60) on a common substrate (45) desirably include a dielectric region underlying the BP (35) to reduce the parasitic impedance of the BP (35) and its interconnection (41) as the electronic elements (44, 44′,... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20100140815 - Semiconductor device and method of forming an interconnect structure for 3-d devices using encapsulant for structural support: A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate,... Agent: Robert D. Atkins

20100140816 - Method of forming a marker, substrate having a marker and device manufacturing method: A marker, for example an alignment marker or an overlay marker is formed in two steps. First, a pattern of two chemically distinct feature types having a pitch comparable to product features is formed. This pattern is then masked by resist in the form of the desired marker, which has... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20100133498 - Memory device and semiconductor device: A memory device has a pair of conductive layers and an organic compound having a liquid crystal property that is interposed between the pair of conductive layers. Data is recorded in the memory device by applying a first voltage to the pair of conductive layers and heating the organic compound,... Agent: Eric Robinson

20100133495 - Phase change memory devices and methods for fabricating the same: A phase change memory device is provided, including a substrate, a first dielectric layer disposed over the substrate, a first electrode disposed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, covering the first electrode, a heating electrode disposed in the second dielectric layer,... Agent: Quintero Law Office, PC

20100133499 - Resistance variable memory with temperature tolerant materials: A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb2Se3, and a metal-chalcogenide layer and methods of forming such a memory device.... Agent: Dickstein Shapiro LLP

20100133496 - Resistive random access memory: A RRAM may include a first electrode, a second electrode, and a memory resistant layer between the first and second electrodes, wherein the memory resistant layer may include a transition metal oxide doped with a metal having a high oxygen affinity. Because a RRAM includes a memory resistant layer doped... Agent: Harness, Dickey & Pierce, P.L.C

20100133497 - Semiconductor device and method for manufacturing the same: The invention includes: multiple bit lines b1 to b5 arranged in parallel to each other at a first line pitch; multiple word lines w1 to w4 arranged in parallel to each other at a second line pitch greater than the first line pitch and intersecting with bit lines b1 to... Agent: Young & Thompson

20100133494 - Use of lacunar spinels with tetrahedral aggregates of a transition element of the am4x8 type with an electronic data rewritable non volatile memory, and corresponding material: The invention relates to the use of a material that belongs to the class of lacunar spinels with tetrahedral aggregates of an AM4X8 transition element as the active material for an electronic data non-volatile memory, in which: A comprises at least one of the following elements: Ga, Ge, Zn; M... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100133500 - Memory cell having a side electrode contact: Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode, a memory element and a side electrode. The bottom electrode contacts the memory element at a first contact surface on the bottom of the memory element. The side electrode contacts the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20100133502 - Cmos-process-compatible programmable via device: Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided comprising a substrate; a dielectric layer on the substrate; a heater on at least a portion of a side of the dielectric layer opposite the substrate; a first oxide layer... Agent: Michael J. Chang, LLC

20100133501 - Switching element and method for manufacturing switching element: A switching element of the present invention utilizes electro-chemical reactions to operate, and comprises ion conductive layer 54 capable of conducting metal ions, first electrode 49 arranged in contact with the ion conductive layer, and second electrode 58 for supplying metal ions to the ion conductive layer, wherein an oxygen... Agent: Sughrue Mion, PLLC

20100133503 - Phase change memory: A phase change memory is provided, which includes a semiconductor substrate having a first conductive type, buried word lines having a second conductive type, doped semiconductor layers having the first conductive type, memory cells, metal silicide layers, and bit lines. The buried word lines are disposed in the semiconductor substrate.... Agent: J C Patents

20100133508 - Group iii nitride based quantum well light emitting device structures with an indium containing capping structure: Group III nitride based light emitting devices and methods of fabricating Group III nitride based light emitting devices are provided. The emitting devices include an n-type Group III nitride layer, a Group III nitride based active region on the n-type Group III nitride layer and comprising at least one quantum... Agent: Myers Bigel Sibley & Sajovec, P.A.

20100133504 - Light emitting devices: A new light emitting device is disclosed. The device includes a reflector, a surface layer, and a light emitting layer located there-between. The light emitting layer emits light at a wavelength λ. An optical thickness from the light emitting layer to the reflector is approximately m*λ/4, where m is a... Agent: Quintero Law Office, PC

20100133506 - Nitride semiconductor light emitting element and method for manufacturing nitride semiconductor: Provided are a nitride semiconductor light emitting element having a nitride semiconductor layered on an AlN buffer layer with improved qualities such as crystal quality and with improved light emission output, and a method of manufacturing a nitride semiconductor. An AlN buffer layer (2) is formed on a sapphire substrate... Agent: Rabin & Berdo, PC

20100133505 - Semiconductor light emitting device and fabrication method for the same: The high luminance semiconductor light emitting device comprises: a GaAs substrate structure including a GaAs layer (3), a first metal buffer layer (2) disposed on a surface of the GaAs layer, a first metal layer (1) disposed on the first metal buffer layer, and a second metal buffer layer (4)... Agent: Rabin & Berdo, PC

20100133507 - Semiconductor light emitting device and fabrication method for the same: The high luminance semiconductor light emitting device comprises: a GaAs substrate structure including a GaAs layer (3), a first metal buffer layer (2) disposed on a surface of the GaAs layer, a first metal layer (1) disposed on the first metal buffer layer, and a second metal buffer layer (4)... Agent: Rabin & Berdo, PC

20100133510 - Bio-sensor chip: Provided is a bio-sensor chip. The bio-sensor chip includes a sensing part, a board circuit part, a channel part, and a cover. In the sensing part, a target material and a detection material interact with each other to detect the target material. The board circuit part is electrically connected to... Agent: Lahive & Cockfield, LLP Floor 30, Suite 3000

20100133511 - Integrated circuits based on aligned nanotubes: Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto... Agent: Fish & Richardson, PC

20100133512 - Method for fabricating carbon nanotube transistors on a silicon or soi substrate: A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically defined single crystal silicon seed layer is converted to a single crystal silicon carbide seed layer. A single layer of graphene is formed on the top surface... Agent: Texas Instruments Incorporated

20100133509 - Semiconductor nanowire and its manufacturing method: A method for fabricating a semiconductor nanowire that has first and second regions is provided. A catalyst particle is put on a substrate. A first source gas is introduced, thereby growing the first region from the catalyst particle via a vapor-liquid-solid phase growth. A protective coating is formed on a... Agent: Greenblum & Bernstein, P.L.C

20100133513 - Nanoparticle / nanotube-based nanoelectronic devices and chemically-directed assembly thereof: According to some embodiments, the present invention provides a nanoelectronic device based on a nanostructure that may include a nanotube with first and second ends, a metallic nanoparticle attached to the first end, and an insulating nanoparticle attached to the second end. The nanoelectronic device may include additional nanostructures so... Agent: Winstead PC

20100133514 - Superconducting shielding for use with an integrated circuit for quantum computing: An integrated circuit for quantum computing may include a superconducting shield to limit magnetic field interactions.... Agent: Seed Intellectual Property Law Group PLLC

20100133519 - Arylamine compounds and electronic devices: There is provided conductive organic arylamine compounds. The compounds may be prepared as films and such films may be used as a hole transporting layer, an emissive layer or an electron transporting layer in organic light emitting devices.... Agent: Klarquist Sparkman, LLP

20100133516 - Carbon nano tube thin film transistor and display adopting the same: Provided are a flexible and transparent carbon nano tube (CNT) thin film transistor using a degradable polymer substrate, and a display adapting the CNT thin film transistor. The polymer substrate is formed of a polymer material that is naturally degraded, and a CNT channel, where a semiconductive CNT is dispersed... Agent: Buchanan, Ingersoll & Rooney PC

20100133518 - Gate insulating film forming agent for thin-film transistor: There is provided a novel gate insulating film forming material in consideration of not only initial electric properties immediately after the production of a gate insulating film, but also electric properties after other steps are performed while producing a thin-film transistor using the gate insulating film, and even reliability in... Agent: Oliff & Berridge, PLC

20100133515 - Layered devices with crosslinked polymer and methods of preparing the same: The present invention is drawn to a layered organic device, and a method of forming the same. The method includes steps of applying a first solvent-containing organic layer to a substrate and removing solvent from the first solvent-containing organic layer to form a first solidified organic layer. Additional steps include... Agent: Hewlett-packard Company Intellectual Property Administration

20100133523 - Light-emitting element, light-emitting device, electronic device, and lighting device: Light-emitting elements in which an increase of driving voltage can be suppressed are provided. Light-emitting devices whose power consumption is reduced by including such light-emitting elements are also provided. In a light-emitting element having an EL layer between an anode and a cathode, a first layer in which carriers can... Agent: Eric Robinson

20100133520 - Method for manufacturing an electrode: The present invention relates to a method for manufacturing an organic electronic device, comprising providing by electro-deposition an electrode to a surface of an electro-active material—the electro-active material comprising an organic electro-active compound—or providing said electrode to a surface of a substrate for said electro-active material, after which the electro-active... Agent: Lucas & Mercanti, LLP

20100133517 - Organic light emitting element and organic light emitting device including the same: An organic light emitting element and an organic light emitting device including the same is provided. At least one p-type or n-type overdoping layer is formed between two light emitting members forming a p-n junction in the organic light emitting element.... Agent: F. Chau & Associates, LLC

20100133521 - Organic light-emitting device and display apparatus: Provided is an organic light-emitting device having a high emission efficiency and a long lifetime. The organic light-emitting device (10) includes an anode (2), a cathode (6), and a stack body including at least a light-emitting layer (4) and interposed between the anode (2) and the cathode (6), in which... Agent: Fitzpatrick Cella Harper & Scinto

20100133526 - Organic thin film transistor and flat panel display device including the same: Provided are an organic thin film transistor providing smoother movement of holes between a source electrode or a drain electrode and a p-type organic semiconductor layer, and a flat panel display device including the organic thin film transistor. The organic thin film transistor includes a substrate, a gate electrode disposed... Agent: Knobbe Martens Olson & Bear LLP

20100133524 - Red phoshorescent compound and organic electroluminescent device using the same: o

20100133525 - Thin film transistor, display unit, and method of manufacturing thin film transistor: A thin film transistor includes: a gate electrode; a gate insulting film formed on the gate electrode; an oxide semiconductor thin film layer forming a channel region corresponding to the gate electrode on the gate insulating film; a channel protective layer that is formed at least in a region corresponding... Agent: Sonnenschein Nath & Rosenthal LLP

20100133522 - White organic light emitting device and method for manufacturing the same: The white organic light emitting device includes an anode and a cathode placed on a substrate opposite to each other, a charge generation layer formed between the anode and the cathode, a first stack of a first hole transport layer, a first light emitting layer for emitting a blue light,... Agent: Morgan Lewis & Bockius LLP

20100133528 - Capacitive gas sensor and method of fabricating the same: A capacitive gas sensor and a method of fabricating the same are provided. The capacitive gas sensor includes an insulating substrate, a metal electrode and a micro thin-film heater wire integrally formed on the same plane of the insulating substrate, and an oxide detection layer coated on the metal electrode... Agent: Rabin & Berdo, PC

20100133532 - Compound semiconductor light emitting device: There is provided a compound semiconductor light emitting device capable of optimizing strain applied to an active layer and a clad layer to minimize a piezoelectric field and spontaneous polarization in an active layer and to maximize light emission efficiency. In a compound semiconductor light emitting device having a structure... Agent: Husch Blackwell Sanders LLP

20100133533 - Display device: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes... Agent: Fish & Richardson P.C.

20100133527 - High efficiency lighting device and method for fabricating the same: The present invention discloses a high-efficiency lighting device and a method for fabricating the same. The method of the present invention comprises steps: providing an insulation substrate and sequentially forming an electrode layer and a seed layer on the insulation layer; forming a plurality of zinc oxide micro and nano... Agent: Rosenberg, Klein & Lee

20100133531 - Semiconductor device and manufacturing method thereof: A gate electrode layer over a substrate; a gate insulating layer over the gate electrode layer; a first source electrode layer and a first drain electrode layer over the gate insulating layer; an oxide semiconductor layer over the gate insulating layer; and a second source electrode layer and a second... Agent: Eric Robinson

20100133530 - Semiconductor device and method for manufacturing the same: An object is, in a thin film transistor in which an oxide semiconductor is used as an active layer, to prevent change in composition, film quality, an interface, or the like of an oxide semiconductor region serving as an active layer, and to stabilize electrical characteristics of the thin film... Agent: Eric Robinson

20100133529 - Thin light-emitting devices and fabrication methods: A light-emitting device, such as a light-emitting diode (LED), is grown on a substrate including a ZnO-based material. The structure includes a plurality of semiconductor layers and an active layer disposed between the plurality of semiconductor layers. The device is removed from the substrate or the substrate is substantially thinned... Agent: Wilmerhale/boston

20100133534 - Integrated circuit packaging system with interposer and flip chip and method of manufacture thereof: A method of manufacture of an integrated circuit packaging system includes: providing an interposer having a first side and a second side with the first side having a device contact and an interconnect contact and with the second side having a test pad; mounting an integrated circuit over the device... Agent: Law Offices Of Mikio Ishimaru

20100133535 - Semiconductor device with reduced pad pitch: A semiconductor device includes a first pad, a second pad and a third pad. The first pad and the third pad are electrically connected to each other. The first pad and the second pad are used for bonding. The second pad and the third pad are used for probing. According... Agent: Young & Thompson

20100133537 - Micro electro mechanical device and manufacturing method thereof: To manufacture a micro structure and an electric circuit included in a micro electro mechanical device over the same insulating surface in the same step. In the micro electro mechanical device, an electric circuit including a transistor and a micro structure are integrated over a substrate having an insulating surface.... Agent: Fish & Richardson P.C.

20100133536 - Microbolometer infrared detector elements and methods for forming same: Microbolometer infrared detector elements that may be formed and implemented by varying type/s of precursors used to form amorphous silicon-based microbolometer membrane material/s and/or by varying composition of the final amorphous silicon-based microbolometer membrane material/s (e.g., by adjusting alloy composition) to vary the material properties such as activation energy and... Agent: O'keefe, Egan, Peterman & Enders LLP

20100133540 - Glass substrate, display device having the same, and method of manufacturing the display device: A glass substrate includes at least one surface including an uneven surface having a difference of less than about 0.003 micrometers between a highest point and a lowest point in a section of the glass substrate, the section having a width of about 10 millimeters to about 30 millimeters, and... Agent: Cantor Colburn, LLP

20100133543 - Methods of making semiconductor-based electronic devices on a wire and articles that can be made thereby: Strands of active electronic devices (AEDs), such as field-effect transistors, are made by processing a semiconductor substrate so that it yields a number of elongate semiconductor members liberated from the starting substrate. The elongate semiconductor members are secured to wires or wire-like structures so as to form semiconductor-member-on-a-wire composites upon... Agent: Downs Rachlin Martin PLLC

20100133542 - Pixel structure and manufacturing method thereof: A method of manufacturing a pixel structure is provided. A first patterned conductive layer including a gate and a data line is formed on a substrate. A gate insulating layer is formed to cover the first patterned conductive layer and a semiconductor channel layer is formed on the gate insulating... Agent: Jianq Chyun Intellectual Property Office

20100133541 - Thin film transistor array substrate, its manufacturing method, and liquid crystal display device: In accordance with an exemplary aspect of the present invention, a thin film transistor array substrate includes a transparent insulating substrate, and a thin film transistor for pixel switching and a thin film transistor for a drive circuit formed on the transparent insulating substrate, wherein the thin film transistor for... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100133538 - Thin film transistor display panel and method of manufacturing the same: A thin film transistor array panel according to an exemplary embodiment includes a first colored member overlapping a thin film transistor and a plurality of second colored members simultaneously formed on the first colored member. Accordingly, it is possible to prevent light leakage current of the thin film transistor, to... Agent: Haynes And Boone, LLPIPSection

20100133539 - Thin-film transistor and method of manufacturing the same: Provided is a thin-film transistor (TFT) substrate. The TFT substrate includes: an insulating substrate; a semiconductor pattern which is formed on the insulating substrate, the semiconductor pattern having a top surface and a bottom surface; a source electrode and a drain electrode which are disposed on the top and bottom... Agent: Innovation Counsel LLP

20100133544 - Thin film transistor and fabricating method thereof: A thin film transistor (TFT) includes a poly-silicon island, a gate insulating layer, a gate stack layer, and a dielectric layer. The poly-silicon island includes a source region and a drain region. The gate insulating layer covers the poly-silicon island. The gate stack layer is disposed on the gate insulating... Agent: Jianq Chyun Intellectual Property Office

20100133546 - System and method for manufacturing thick and thin film devices using a donee layer cleaved from a crystalline donor: Various embodiments of fabricated crystalline-based structures for the electronics, optoelectronics and optics industries are disclosed. Each of these structures is created in part by cleaving a donee layer from a crystalline donor, such as a micaceous/lamellar mass comprising a plurality of lamelliform sheets separable from each other along relatively weak... Agent: Downs Rachlin Martin PLLC

20100133545 - Thin film transistor and method of fabricating the same: A thin film transistor includes a multi-coaxial silicon nanowire unit including a plurality of coaxial silicon nanowires on a substrate, the multi-coaxial silicon nanowire unit including a central portion and end portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain... Agent: Brinks Hofer Gilson & Lione

20100133548 - Methods for improving the quality of epitaxially-grown semiconductor materials: The invention provides methods which can be applied during the epitaxial growth of two or more layers of semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects present in one epitaxial layer are capped with a masking material. A following layer is... Agent: Winston & Strawn LLP Patent Department

20100133547 - Semiconductor sensor: A semiconductor sensor determines physical and/or chemical properties of a medium, in particular a pH sensor. The semiconductor sensor has an electronic component with a sensitive surface, said component being constructed for its part on the basis of semiconductors with a large band gap (wide-gap semiconductor). The sensitive surface is... Agent: Fay Kaplun & Marcin, LLP

20100133549 - Semiconductor devices with current shifting regions and related methods: A semiconductor device may include a semiconductor buffer layer having a first conductivity type and a semiconductor mesa having the first conductivity type on a surface of the buffer layer. In addition, a current shifting region having a second conductivity type may be provided adjacent a corner between the semiconductor... Agent: Myers Bigel Sibley & Sajovec, P.A.

20100133550 - Stable power devices on low-angle off-cut silicon carbide crystals: A silicon carbide-based power device includes a silicon carbide drift layer having a planar surface that forms an off-axis angle with a <0001> direction of less than 8°.... Agent: Myers Bigel Sibley & Sajovec, P.A.

20100133551 - High-speed optical interconnection device: Provided is a high-speed optical interconnection device. The high-speed optical interconnection device includes a first semiconductor chip, light emitters, optical detectors, and a second semiconductor chip, which are disposed on a silicon-on-insulator (SOI) substrate. The light emitters receive electrical signals from the first semiconductor chip to output optical signals. The... Agent: Rabin & Berdo, PC

20100133559 - Area light source apparatus and liquid crystal display apparatus assembly: Disclosed herein is an area light source apparatus for illuminating a liquid crystal display apparatus of the transmission type, which has a display area formed from a plurality of pixels arrayed in a two-dimensional matrix, from the back, including: a plurality of light emitting element assemblies each provided as a... Agent: Sonnenschein Nath & Rosenthal LLP

20100133558 - Flip chip type led lighting device manufacturing method: A flip chip type LED lighting device manufacturing method includes the step of providing a strip, the step of providing a submount, the step of forming a metal bonding layer on the strip or submount, the step of bonding the submount to the strip, and the step of cutting the... Agent: Rosenberg, Klein & Lee

20100133552 - Lamp type light emitting device for safety fuse: A lamp type light emitting device for safety fuse, including a substrate, an electrode layer, a chip set, a wire set, two leads and an encapsulator. The electrode layer is arranged on the substrate and includes a first T-shaped electrode, a second T-shaped electrode, a first stripe electrode and a... Agent: Hdls Patent & Trademark Services

20100133556 - Led array package covered with a highly thermal conductive plate: A light source includes a substrate, a light emitting diode on the substrate, and a phosphor layer over the light emitting diode. A plate is on the phosphor layer. An attachment member is coupled to the plate and is configured to conduct heat away from the plate.... Agent: Arent Fox LLP

20100133557 - Metal-based photonic device package module and manufacturing method thereof: A metal-based photonic device package module that is capable of greatly improving heat releasing efficiency and implementing a thin package is provided. The metal-based photonic device package module includes a metal substrate that is formed the shape of a plate, a metal oxide layer that is formed on the metal... Agent: Gifford, Krass, Sprinkle,anderson & Citkowski, P.c

20100133555 - Solid metal block semiconductor light emitting device mounting substrates: A mounting substrate for a semiconductor light emitting device includes a solid metal block having first and second opposing metal faces. The first metal face includes an insulating layer and a conductive layer on the insulating layer. The conductive layer is patterned to provide first and second conductive traces that... Agent: Myers Bigel Sibley & Sajovec, P.A.

20100133554 - Solid state lighting device: A light emission package includes at least one solid state emitter, a leadframe, and a body structure encasing a portion of the leadframe. At least one aperture is defined in an electrical lead to define multiple electrical lead segments, with at least a portion of the aperture disposed outside an... Agent: Intellectual Property / Technology Law

20100133553 - Thermally conductive structure of led and manufacturing method thereof: A thermally conductive structure of a light emitting diode (LED) includes a vapor chamber, an insulating layer, an electrically conductive layer and a plurality of LEDs. In the invention, the insulating layer is plated over a surface of the vapor chamber; the electrically conductive layer disposed on the insulating layer... Agent: Hdls Patent & Trademark Services

20100133561 - Light emitting apparatus: The present invention provides a light emitting apparatus comprising a three-color light emitting device unit including at least three light emitting diode (LED) chips for respectively emitting red, green and blue light; a white light emitting device unit including at least one blue LED chip with a fluorescent substance formed... Agent: H.c. Park & Associates, PLC

20100133560 - Light emitting device package: A light emitting device package is provided. The light emitting device package comprises a package body comprising a first cavity, and a second cavity connected to the first cavity; a first lead electrode, at least a portion of which is disposed within the second cavity; a second lead electrode, at... Agent: Birch Stewart Kolasch & Birch

20100133562 - High brightness led utilizing a roughened active layer and conformal cladding: A light emitting device and method for making the same are disclosed. The device includes an active layer disposed between first and second layers. The first layer has top and bottom surfaces. The top surface includes a first material of a first conductivity type, including a plurality of pits in... Agent: The Law Offices Of Calvin B. Ward

20100133576 - Casting for an led module: A casting adapted to carry a light emitting diode die and an anti-static die is disclosed. The casting comprises two electrodes for opposite electrodes and a wall. The light emitting diode die is mounted one of electrodes and the anti-static die is mounted on the other electrode. The wall is... Agent: Rosenberg, Klein & Lee

20100133572 - Display device and method for manufacturing the same: A display device is provided which includes: lower electrodes each have a light-reflective first metal material layer and a second metal material layer provided thereon which has a superior alkaline-solution resistance to that of the first metal material layer; an insulating pattern which is formed from a photosensitive composition material,... Agent: K&l Gates LLP

20100133563 - Illumination system comprising a radiation source and a luminescent material: An illumination system, comprising a radiation source and a luminescent material comprising at least one phosphor capable of absorbing a part of light emitted by the radiation source and emitting light of wavelength different from that of the absorbed light; wherein said at least one phosphor is a yellow red-emitting... Agent: Philips Intellectual Property & Standards

20100133565 - Lead frame, light emitting diode having the lead frame, and backlight unit having the light emitting diode: An LED includes a light-emitting chip, a metal member, and a housing. The light-emitting chip generates light. The light-emitting chip is arranged on the metal member. The housing is combined with the metal member to fix the metal member. The housing has an opening portion exposing at least a portion... Agent: H.c. Park & Associates, PLC

20100133568 - Light emitting device and method for manufacturing same: A light emitting device includes: a substrate including through electrodes; a light emitting element bonded onto the substrate and connected to the through electrodes; and a dielectric film made of a translucent inorganic material and spaced from the light emitting element so that an internal space is formed between the... Agent: Turocy & Watson, LLP

20100133574 - Light emitting device with multilayer silicon-containing encapsulant: A light emitting device that includes a light emitting diode and a multilayer encapsulant is disclosed. The multilayer encapsulant includes a first encapsulant in contact with the light emitting diode and a photopolymerizable composition in contact with the first encapsulant. The first encapsulant may be a silicone gel, silicone gum,... Agent: 3m Innovative Properties Company

20100133569 - Light emitting diode: A light emitting diode includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer, and at least one transparent conductive layer. The transparent conductive layer comprises of a carbon nanotube structure.... Agent: PCe Industry, Inc. Att. Steven Reiss

20100133571 - Light-emitting device: To provide a light emitting device easy to produce and extracting light to its outside with high efficiency, the light-emitting device 70 of the present invention includes an insulating base 10; a light-emitting element 1 mounted on a side of the base 10; and a protection element 2 mounted on... Agent: Nixon & Vanderhye, PC

20100133573 - Light-emitting element, light-emitting device, lighting device, and electronic device: An object is to provide a light-emitting element which exhibits light emission with high luminance and can be driven at low voltage. Another object is to provide a light-emitting device or an electronic device with reduced power consumption. Between an anode and a cathode, n (n is a natural number... Agent: Eric Robinson

20100133575 - Low optical loss electrode structures for leds: An electrode structure is disclosed for enhancing the brightness and/or efficiency of an LED. The electrode structure can have a metal electrode and an optically transmissive thick dielectric material formed intermediate the electrode and a light emitting semiconductor material. The electrode and the thick dielectric cooperate to reflect light from... Agent: Haynes And Boone, LLPIPSection

20100133564 - Method for producing semiconductor components and thin-film semiconductor component: The invention relates to a method for producing semiconductor components, wherein a layer composite (6) containing a semiconductor material is formed on a growth substrate (1), a flexible carrier layer is applied to the layer composite (6), the flexible carrier layer is cured to form a self-supporting carrier layer (2),... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20100133566 - Opto-electrical devices and methods of making the same: An opto-electrical device comprising: a first electrode for injecting charge carriers of a first polarity; a second electrode for injecting charge carriers of a second polarity; and a layer of organic material disposed between the first and second electrodes, the layer of organic material comprising a blend of a first... Agent: Marshall, Gerstein & Borun LLP

20100133567 - Semiconductor light emitting device and method of manufacturing the same: A semiconductor light emitting device and a method of manufacturing the same are provided. The semiconductor light emitting device comprises a first conductive semiconductor layer comprising a concave portion, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer.... Agent: Birch Stewart Kolasch & Birch

20100133570 - Semiconductor light emitting device and method of manufacturing the same: Disclosed is a semiconductor light emitting device, and a method of manufacturing the same. The semiconductor light emitting device includes a first conductivity type semiconductor layer, an active layer disposed on the top of the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer disposed on the... Agent: Mcdermott Will & Emery LLP

20100133579 - Iii-nitride semiconductor light emitting device: The present disclosure relates to a III-nitride semiconductor light-emitting device including: a plurality of III-nitride semiconductor layers having a first III-nitride semiconductor layer having a first conductivity type, a second III-nitride semiconductor layer having a second conductivity type different from the first conductivity type, and an active layer disposed between... Agent: Harness, Dickey, & Pierce, P.l.c

20100133580 - Light emitting diode package structure and conductive structure and manufacturing method thereof: A light emitting diode package structure includes a frame, a light emitting diode chip electrically coupled to the frame, an upper packing portion covering the light emitting diode chip on the frame, and a lower packing portion circumferentially disposed on the frame for fixation and next to the upper packing... Agent: Quintero Law Office, PC

20100133577 - Method for producing electronic component and electronic component: A plurality of chips disposed in a wafer on a passivated main side, having at least one chip contact surface, is provided with an insulation layer. The insulation layer has openings in the area of the at least one chip contact surface of each chip. The chip contact surfaces of... Agent: Staas & Halsey LLP

20100133578 - Solid state lighting device with improved heatsink: A solid state lighting device includes a device-scale stamped heatsink with a base portion and multiple segments or sidewalls projecting outward from the base portion, and dissipates all steady state thermal load of a solid state emitter to an ambient air environment. The heatsink is in thermal communication with one... Agent: Intellectual Property / Technology Law

20100133581 - Top contact led thermal management: An LED having enhanced heat dissipation is disclosed. For example, an LED die can have extended bond pads that are configured to enhance heat flow from an active region of the LED to a lead frame. A heat transmissive substrate can further enhance heat flow away from the LED die.... Agent: Haynes And Boone, LLPIPSection

20100133582 - Nitride semiconductor light emitting device: A nitride semiconductor light emitting device includes: a multilayer structure a plurality of nitride semiconductor layers including a light emitting layer where the multilayer structure has cavity facets facing each other; and a plurality of protective films made of dielectric materials on at least one of the cavity facets. Among... Agent: Mcdermott Will & Emery LLP

20100133583 - Semiconductor integrated circuit: Disclosed herein is a semiconductor integrated circuit including a protected circuit; and a protection element formed on the same semiconductor substrate as the protected circuit and adapted to protect the protected circuit, wherein the protection element includes two diodes having their anodes connected together to form a floating node and... Agent: Rader Fishman & Grauer PLLC

20100133585 - Growth of germanium epitaxial thin film with negative photoconductance characteristics and photodiode using the same: A method of growing a germanium (Ge) epitaxial thin film having negative photoconductance characteristics and a photodiode using the same are provided. The method of growing the germanium (Ge) epitaxial thin film includes growing a germanium (Ge) thin film on a silicon substrate at a low temperature, raising the temperature... Agent: Rabin & Berdo, PC

20100133584 - Semiconductor device structure and method of manufacture thereof: A semiconductor device structure comprising a first bulk crystal semiconductor material and a second bulk crystal semiconductor material provided on a surface of the first bulk crystal semiconductor material with or without a deliberate intermediate region, the second bulk crystal semiconductor material being a Group II-VI material dissimilar to the... Agent: Drinker Biddle & Reath Attn: Intellectual Property Group

20100133586 - Heterojunction bipolar transistor and method of forming the same: Provided are a heterojunction bipolar transistor and a method of forming the same. The method includes forming an emitter electrode on an emitter capping pattern, a base electrode on a base pattern, and a collector electrode on a subcollector pattern, the subcollector pattern, the base pattern, an emitter pattern, and... Agent: Rabin & Berdo, PC

20100133588 - Semiconductor device having dummy power line: A semiconductor device includes a plurality of circuit blocks respectively arranged both in a first direction and in a second direction that intersects the first direction. A plurality of signal lines extend in one direction of the first direction and the second direction to correspond to and extend over the... Agent: F. Chau & Associates, LLC

20100133587 - Three-dimensional architecture for integration of cmos circuits and nano-material in hybrid digital circuits: A hybrid CMOL stack enables more efficient design of CMOS logical circuits. The hybrid CMOL structure includes a first substrate having a CMOS device layer on the substrate, a first interconnect layer with interface pins over the CMOS device layer of the first substrate, a first array of nanowires connected... Agent: Heslin Rothenberg Farley & Mesiti PC

20100133589 - Analog circuit cell array and analog integrated circuit: An analog circuit cell array includes a plurality of transistor cell arranged in an array. Each of the transistor cells includes a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and... Agent: Fujitsu Patent Center C/o Cpa Global

20100133590 - Shared photodiode image sensor: An image sensor with a shared photodiode is provided. The image sensor includes at least two unit pixels, each of which includes a photodiode, a diffusion region which gathers electrons from the photodiode, a transfer transistor which connects the photodiode with the diffusion region, and a readout circuit which reads... Agent: Rabin & Berdo, PC

20100133591 - Method for passivating a field-effect transistor: The present invention relates to a method for passivating a semiconductor component having at least one chemosensitive electrode that is blinded by the application of a glass layer. The present invention also relates to a device for detecting at least one substance included in a fluid stream, including at least... Agent: Kenyon & Kenyon LLP

20100133592 - Solid-state imaging device: A plurality of pixel portions (12) are formed on a silicon substrate (11). A photoelectric converter portion (10) constituting each of the pixel portions (12) is electrically isolated by an element isolation portion (13) comprising an insulating film formed on the silicon substrate (11). The photoelectric converter portion (10) partitioned... Agent: Mcdermott Will & Emery LLP

20100133593 - Junction field effect transistor having a double gate structure and method of making same: A junction field effect transistor includes a channel region, a gate region coupled to the channel region, a well tap region coupled to the gate region and the channel region, and a well region coupled to the well tap region and the channel region. A double gate operation is achieved... Agent: Baker Botts L.L.P.

20100133595 - Field effect transistor structure with abrupt source/drain junctions: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20100133594 - Semiconductor structure and method of fabricating the same: A semiconductor structure including a substrate, a gate dielectric layer, a gate, a source region and a drain region is provided. The gate dielectric layer is disposed on the substrate. At least one recess is disposed in the substrate. The gate is disposed on the gate dielectric layer and in... Agent: North America Intellectual Property Corporation

20100133596 - Solid-state imaging device: A solid-state imaging device includes pixels arranged in a matrix on a semiconductor substrate, the pixels each including: a photodiode for photoelectric-converting an incident light beam; a readout transistor for reading out a signal charge from the photodiode; and a floating diffusion region for converting the read out signal charge... Agent: Mots Law, PLLC

20100133597 - Semiconductor memory device and manufacturing method thereof: A semiconductor memory device including a ferroelectric capacitor, the ferroelectric capacitor includes a lower electrode having a plurality of protrusions; a ferroelectric film on the lower electrode, the ferroelectric film having a plurality of protrusions engaging with the protrusions of the lower electrode; and an upper electrode on the ferroelectric... Agent: Knobbe Martens Olson & Bear LLP

20100133598 - Nonvolatile memory device and method for fabricating the same: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, and a plurality of gate electrodes. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicular to... Agent: Mills & Onello LLP

20100133599 - Nonvolatile memory device and method for fabricating the same: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory... Agent: Mills & Onello LLP

20100133601 - Semiconductor device: A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, a source and drain regions, a floating gate, and a control gate. Each of the source and drain... Agent: Eric Robinson

20100133600 - Semiconductor devices having increased sensing margin: One transistor (1-T) dynamic random access memories (DRAM) having improved sensing margins that are relatively independent of the amount of carriers stored in a body region thereof.... Agent: Harness, Dickey & Pierce, P.L.C

20100133603 - Eeprom: An EEPROM according to the present invention includes: a semiconductor layer of a first conductive type; and a first insulating film formed on the semiconductor layer. A first impurity region, a second impurity region, a third impurity region, a fourth impurity region, and a fifth impurity region of a second... Agent: Rabin & Berdo, PC

20100133602 - Non-volatile memory cell with buried select gate, and method of making same: A memory device, and method of making the same, in which a trench is formed into the surface of a semiconductor substrate. Source and drain regions define a channel region there between. The drain is formed under the trench. The channel region includes a first portion that extends along a... Agent: Dla Piper LLP (us )

20100133605 - Self aligned narrow storage elements for advanced memory device: A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface... Agent: Turocy & Watson, LLP

20100133604 - Semiconductor devices having gate structures with conductive patterns of different widths and methods of fabricating such devices: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second... Agent: Myers Bigel Sibley & Sajovec

20100133606 - Three-dimensional semiconductor memory device: A three-dimensional semiconductor memory device includes word lines and gate interlayer insulation layers that are alternatively stacked on a semiconductor substrate while extending in a horizontal direction, a vertical channel layer that faces the word lines and extends upwardly from the semiconductor substrate, and a channel pad that extends from... Agent: Mills & Onello LLP

20100133608 - Method for fabricating a semiconductor device: An embodiment of the invention provides a method for forming a semiconductor device comprising providing a substrate with a pad layer formed thereon. The pad layer and the substrate are patterned to form a plurality of trenches. A trench top insulating layer is formed in each trench. Wherein the trench... Agent: Quintero Law Office, PC

20100133609 - Methods of providing electrical isolation and semiconductor structures including same: Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having substantially vertical sidewalls. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase an effective gate length (“Leffective”)... Agent: Trask Britt, P.C./ Micron Technology

20100133607 - Recessed channel negative differential resistance-based memory cell: Disclosed herein is an improved recessed thyristor-based memory cell. The disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of the substrate, which is coupled to or comprises the enable gate of the cell. Vertically disposed around this recessed gate is a thyristor, whose anode (source;... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20100133610 - Method of forming an integrated power device and structure: In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20100133611 - Isolated transistor: A transistor is formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a... Agent: Patentability Associates

20100133612 - Electronic device with asymmetric gate strain: The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing structures as part of the gate electrode.... Agent: Schwegman, Lundberg & Woessner/micron

20100133616 - Methods of forming wiring to transistor and related transistor: Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including... Agent: Hoffman Warnick LLC

20100133615 - Multiple gate transistor having fins with a length defined by the gate electrode: The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel... Agent: Advanced Mirco Devices, Inc. C/o Williams, Morgan & Amerson

20100133614 - Multiple gate transistor having homogenously silicided fin end portions: In a multiple gate transistor, the plurality of Fins of the drain or source of the transistor are electrically connected to each other by means of a common contact element, wherein enhanced uniformity of the corresponding contact regions may be accomplished by an enhanced silicidation process sequence. For this purpose,... Agent: Williams, Morgan & Amerson

20100133613 - Semiconductor memory device and manufacturing method thereof: A semiconductor memory device includes a supporting substrate; an insulation film provided on the supporting substrate; a source layer provided on the insulation film; a drain layer provided on the insulation film; a body region provided between the source layer and the drain layer and being in an electrically floating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100133617 - Fin field effect transistor: Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium (Si1-XGeX) body region for a fully depleted Fin field effect transistor (FinFET) having a body thickness of at least 10 nanometers (nm) for a process design rule of... Agent: Brooks, Cameron & Huebsch , PLLC

20100133618 - Electrostatic discharge protection device and method for manufacturing the same: An electrostatic discharge (ESD) protection device for protecting an internal circuitry from being damaged during electrostatic discharge, and a method for manufacturing the ESD protection circuit are provided. The electrostatic discharge (ESD) protection device includes: a gate electrode over a substrate; first and second doping regions provided in the substrate... Agent: Morgan Lewis & Bockius LLP

20100133619 - Semiconductor device having a fin transistor and method for fabricating the same: A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and... Agent: Lowe Hauptman Ham & Berner, LLP

20100133620 - Reduced topography-related irregularities during the patterning of two different stress-inducing layers in the contact level of a semiconductor device: In sophisticated semiconductor devices, stress-inducing materials may be provided above the basic transistor devices without any etch control or etch stop materials, thereby enabling an efficient de-escalation of the surface topography, in particular above field regions including closely spaced polysilicon lines. Furthermore, an additional stress-inducing material may be provided on... Agent: Williams, Morgan & Amerson

20100133621 - Restricted stress regions formed in the contact level of a semiconductor device: In sophisticated semiconductor devices, an efficient stress decoupling may be accomplished between neighboring transistor elements of a densely packed device region by providing a gap or a stress decoupling region between the corresponding transistors. For example, a gap may be formed in the stress-inducing material so as to reduce the... Agent: Williams, Morgan & Amerson

20100133624 - Cmos fabrication process: Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD... Agent: Texas Instruments Incorporated

20100133623 - Semiconductor device and method for manufacturing same: A silicon oxynitride film is formed on entire surface of a semiconductor substrate, a lanthanum oxide film is formed on the silicon oxynitride film and the lanthanum oxide film is removed from a pMOS region. Then, a nitrided hafnium silicate film serving as a highly dielectric film is formed on... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20100133622 - Semiconductor device including mosfet with controlled threshold voltage, and manufacturing method of the same: Provided is a semiconductor device including an N-MOSFET and a P-MOSFET on a semiconductor substrate. The N-MOSFET is formed on the semiconductor substrate, and includes a first gate insulating film including a first high-dielectric-constant film having a higher dielectric constant than a silicon oxide film. The P-MOSFET is formed on... Agent: Mcginn Intellectual Property Law Group, PLLC

20100133625 - Semiconductor integrated circuit: A semiconductor integrated circuit having a first p-type MOS transistor; a first n-type MOS transistor; a second p-type MOS transistors; a and second n-type MOS transistors having fourth gate electrodes disposed so as to be adjacent to the second diffused regions of the first n-type MOS transistor. The semiconductor integrated... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100133626 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device according to one embodiment includes: laying out a first region, a second region, a third region and a fourth region on a semiconductor substrate by forming an element isolation region in the semiconductor substrate; forming a first insulating film on the first region... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20100133627 - Depletion-type nand flash memory: A depletion-type NAND flash memory includes a NAND string composed of a plurality of serially connected FETs, a control circuit which controls gate potentials of the plurality of FETs in a read operation, a particular potential storage, and an adjacent memory cell threshold storage, wherein each of the plurality of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100133628 - High-k gate electrode structure formed after transistor fabrication by using a spacer: During a replacement gate approach, the inverse tapering of the opening obtained after removal of the polysilicon material may be reduced by depositing a spacer layer and forming corresponding spacer elements on inner sidewalls of the opening. Consequently, the metal-containing gate electrode material and the high-k dielectric material may be... Agent: Advanced Mirco Devices, Inc. C/o Williams, Morgan & Amerson

20100133629 - Integrated sensor including sensing and processing die mounted on opposite sides of package substrate: An integrated circuit (IC) device includes a lead frame having a first and a second opposing surface and a plurality of lead fingers. A first die including a signal processor is mounted on the first surface of the lead frame while a second die is mounted on the second surface... Agent: Honeywell International Inc. Patent Services

20100133631 - Differential-pressure sensor system and corresponding production method: A differential-pressure sensor system and a corresponding production method. The differential-pressure sensor system includes: a differential-pressure sensor chip having a first pressure application region for applying a first pressure, as pressure to be detected, to the differential-pressure sensor chip, and a second pressure application region for applying a second pressure,... Agent: Kenyon & Kenyon LLP

20100133630 - Method for producing a micromechanical component having a trench structure for backside contact: A method for manufacturing a micromechanical component is proposed. In this context, at least one trench structure having a depth less than the substrate thickness is to be produced in a substrate. In addition, an insulating layer and a filler layer are produced or applied on a first side of... Agent: Kenyon & Kenyon LLP

20100133632 - Vertical hall sensor: A vertical Hall sensor which is integrated in a semiconductor chip has at least 6 electric contacts which are arranged along a straight line on the surface of the semiconductor chip. The electric contacts are wired according to a predetermined rule, namely such that when the contacts are numbered through... Agent: Mccormick, Paulding & Huber LLP

20100133633 - Beam steering element with built-in detector and system for use thereof: An all-optical cross-connect switching system provides optical switching that may reduce processing requirements by three orders of magnitude over conventional techniques by associating at least one optical detector with an optical beam steering element. In one embodiment, a first beam steering element, having a reflective surface in optical association with... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20100133634 - Production of a self-aligned cusin barrier: A semiconductor product includes a portion made of copper, a portion made of a dielectric and a self-aligned barrier between the copper portion and the dielectric portion. The self-aligned barrier includes a first copper silicide layer comprising predominantly first copper silicide molecules, and a second copper silicide layer comprising predominantly... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20100133635 - Image sensor and image sensing system including the same: The image sensor and an image sensing system including the same are provided. The image sensor includes a semiconductor substrate, a pixel array formed at a pixel area located in the semiconductor substrate and comprising a plurality of photoelectric converts, a plurality of driver circuits formed at a circuit area... Agent: Harness, Dickey & Pierce, P.L.C

20100133637 - Avalanche photodiode: An avalanche photodiode comprises: a substrate; a semiconductor layer of a first conductivity type on the substrate; and an avalanche multiplication layer, a light absorption layer, and a window layer which are sequentially formed on the semiconductor layer, wherein apart of the window layer is a region of a second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100133636 - Single photon detector and associated methods for making the same: A semiconductor device includes a semiconductor substrate, a photon avalanche detector in the semiconductor substrate. The photon avalanche detector includes an anode of a first conductivity type and a cathode of a second conductivity type. A guard ring is in the semiconductor substrate and at least partially surrounds the photon... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20100133638 - Image sensors and methods of manufacturing the same: An image sensor includes a plurality of photodiodes, a plurality of wells isolating the plurality of photodiodes from each other, and a plurality of conductive layers or conductive lines for suppressing a dark current generated at the surface of the photodiodes and in the wells in response to a bias... Agent: Harness, Dickey & Pierce, P.L.C

20100133639 - Photosensitive semiconductor component: A semiconductor component that includes a photosensitive doped semiconductor layer, in which electrical charge carriers are released during absorption of electromagnetic radiation is disclosed. The photosensitive semiconductor layer has a structured interface and at least one layer which generates an electric field for separating the released charge carriers disposed downstream... Agent: Slater & Matsil, L.L.P.

20100133641 - Image sensor and method for manufacturing the same: Provided are an image sensor and a method for manufacturing the same. The image sensor comprises a semiconductor substrate, an interconnection and an interlayer dielectric, a lower electrode layer, an image sensing device, a first via hole, a barrier pattern, a second via hole, and a metal contact. The semiconductor... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20100133640 - Packaging method and packaging structure: The invention discloses a packaging structure and packaging method. The packaging structure includes a solder bump, a pad located on a front side of a chip, and an intermediate metal layer which connects the solder bump and the pad, wherein a through hole passing from a back side of the... Agent: Wolf Greenfield & Sacks, P.C.

20100133642 - System and method for forming metal interconnection in image sensor: A method for forming a metal interconnection in an image sensor includes forming a first interlayer dielectric (ILD) layer having a contact plug over a substrate, forming a diffusion barrier layer over the first ILD layer, performing a forming gas annealing, forming a second ILD layer over the diffusion barrier... Agent: Mcandrews Held & Malloy, Ltd

20100133643 - Image sensor pixel and method thereof: A method of manufacturing a pixel of an image sensor including a protruded photodiode capable of improving photosensitivity and reducing crosstalk between neighboring pixels and a pixel of an image sensor formed using the method are provided. The pixel of the semiconductor image sensor includes a protrudedly shaped photodiode on... Agent: Cantor Colburn, LLP

20100133644 - Bottom anode schottky diode structure and method: This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom... Agent: Bo-in Lin

20100133645 - Method for stacking and interconnecting integrated circuits: A method for stacking and interconnecting integrated circuits includes providing at least two substrates; forming a trench in each substrate; filling the trench with an insulating material; forming, in each substrate, at least one conductive area; thinning each substrate until reaching at least the bottom of the trench, to obtain... Agent: Seed Intellectual Property Law Group PLLC

20100133646 - Self-aligned si rich nitride charge trap layer isolation for charge trap flash memory: A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20100133647 - Semiconductor devices and semiconductor device manufacturing methods: Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a... Agent: Harness, Dickey & Pierce, P.L.C

20100133648 - Microstructure device including a metallization structure with self-aligned air gaps between closely spaced metal lines: In sophisticated metallization systems, air gaps may be formed on the basis of a self-aligned patterning regime during which the conductive cap material of metal lines may be protected by providing one or more materials, which may subsequently be removed. Consequently, the etch behavior and the electrical characteristics of metal... Agent: Williams, Morgan & Amerson

20100133649 - Contact efuse structure, method of making a contact efuse device containing the same, and method of making a read only memory containing the same: A contact efuse structure includes a silicon layer and a contact contacting the silicon layer with one end. When a voltage is applied to the contact, a void is formed at the end of the contact, and thus the contact is open. Such structure may be utilized in an efuse... Agent: North America Intellectual Property Corporation

20100133650 - Semiconductor device: A semiconductor device includes an electric fuse formed on a substrate. The electric fuse includes: a first interconnect formed on one end side thereof; a second interconnect formed in a layer different from a layer in which the first interconnect is formed; a first via provided in contact with the... Agent: Mcginn Intellectual Property Law Group, PLLC

20100133651 - Semiconductor structure processing using multiple laterally spaced laser beam spots with joint velocity profiling: A method is used in processing structures on or within a semiconductor substrate using N series of laser pulses to obtain a throughput benefit, wherein N≧2. The structures are arranged in a plurality of substantially parallel rows extending in a generally lengthwise direction. The N series of laser pulses propagate... Agent: Electro Scientific Industries/stoel Rives, LLP

20100133653 - Integrated circuit devices including passive device shielding structures and methods of forming the same: Integrated circuit devices include a semiconductor substrate and a flux line generating passive electronic element on the semiconductor substrate. A dummy gate structure is arranged on the semiconductor substrate in a region below the passive electronic element. The dummy gate includes a plurality of segments, each segment including a first... Agent: Myers Bigel Sibley & Sajovec

20100133652 - Semiconductor device and method of manufacturing the same: Provided is a semiconductor device capable of increasing the capacitance of a capacitor, while reducing an area occupied by the capacitor and inductor on a substrate. The semiconductor device includes a first line; an interlayer insulating film that is formed on the first line and has a recess formed at... Agent: Mcginn Intellectual Property Law Group, PLLC

20100133654 - Method for manufacturing capacitor of semiconductor: The present invention relates to a method of producing a semiconductor capacitor, and more particularly, to a method of producing a semiconductor capacitor, in which an electroless plating is performed during the production of a lower electrode to form a lower electrode.... Agent: Mckenna Long & Aldridge LLP

20100133655 - Semiconductor device having a capacitance element and method of manufacturing the same: A dielectric film is formed by depositing an amorphous strontium oxide film to a thickness of one to several atomic layers on a first electrode layer, then depositing an amorphous titanium oxide film to a thickness of one to several atomic layers on the amorphous strontium oxide film, and then... Agent: Sughrue Mion, PLLC

20100133657 - Group iii nitride semiconductor substrate production method, and group iii nitride semiconductor substrate: A group III nitride semiconductor substrate production method includes preparing a bulk crystal formed of a group III nitride semiconductor single crystal. The group III nitride semiconductor single crystal has one crystalline plane and an other crystalline plane. Hardness of the other crystalline plane is smaller than hardness of the... Agent: Foley And Lardner LLP Suite 500

20100133656 - Method using multiple layer annealing cap for fabricating group iii-nitride semiconductor device structures and devices formed thereby: A method of preventing the escape of nitrogen during the activation of ion implanted dopants in a Group III-nitride semiconductor compound without damaging the Group III-nitride semiconductor comprising: depositing a first layer of another Group III-nitride that acts as an adhesion layer; depositing a second layer of a Group III-nitride... Agent: U S Army Research Laboratory Attn: Rdrl-loc-i

20100133658 - Nitride semiconductor component layer structure on a group iv substrate surface: The invention relates to nitride semiconductor component having a Group III nitride layer structure which is deposited on a substrate having a Group IV substrate surface made of a Group IV substrate material with a cubical crystal structure. The Group IV substrate surface has an elementary cell with C2 symmetry,... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20100133659 - Semiconductor device and method of manufacturing semiconductor integrated circuit chip: A semiconductor device including a plurality of circuit regions formed in a semiconductor substrate and a scribe region formed around the circuit regions for separating the respective circuit regions, the scribe region having a plurality of laminated interlayer films including a plurality of metal films and an optically-transparent insulation film... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20100133660 - Method for producing interconnect structures for integrated circuits: The present disclosure is related to method for producing a semiconductor device comprising the steps of: providing a semiconductor substrate (1), comprising active components on the surface of said substrate, depositing a top layer (2) of dielectric material on the surface of said substrate or on other dielectric layers present... Agent: Knobbe Martens Olson & Bear LLP

20100133661 - Methods for forming conductive vias in semiconductor device components: A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer, may be formed on surfaces of... Agent: Trask Britt, P.C./ Micron Technology

20100133662 - Semiconductor assemblies and methods of manufacturing such assemblies: Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of manufacturing a semiconductor device includes forming a plurality of first side trenches to an intermediate depth in a molded portion of a molded wafer having a plurality of dies... Agent: Perkins Coie LLP Patent-sea

20100133663 - Technique for the growth of planar semi-polar gallium nitride: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {10 11} gallium nitride (GaN) grown on a {100} spinel substrate miscut in... Agent: Gates & Cooper LLP Howard Hughes Center

20100133664 - Module and mounted structure using the same: A module that can not only achieve the reduction in size and manufacturing cost but also be impervious to noise due to electromagnetic waves, and a mounted structure using the same are provided. A module (1) includes a substrate (12) and a plurality of semiconductor packages (11a, 11b), each including... Agent: Hamre, Schumann, Mueller & Larson P.C.

20100133666 - Device including a semiconductor chip and metal foils: A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of... Agent: Dicke, Billig & Czaja

20100133665 - Integrated circuit packaging system with lead frame and method of manufacture thereof: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base device over the base substrate; attaching a leadframe having a leadframe pillar adjacent the base device over the base substrate; applying a base encapsulant over the base device, the base substrate, and... Agent: Law Offices Of Mikio Ishimaru

20100133667 - Power semiconductor module: A wiring process between the provided power semiconductor module and the external circuit is simple. In the power semiconductor module, a power semiconductor element and a cylindrical conductor are joined to one surface of a lead frame. An opening of the cylindrical conductor is exposed at a surface of transfer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100133668 - Semiconductor device and manufacturing method thereof: The present invention relates to a semiconductor device, and more particularly to a manufacturing method for said semiconductor device. The semiconductor device comprises a die that connects with a substrate or a lead frame via an adhesion layer, a metal layer, and/or a back metal layer. Furthermore, the adhesion layer... Agent: Rosenberg, Klein & Lee

20100133669 - Crack stopping structure and method for fabricating the same: A crack stopping structure is disclosed. The crack stopping structure includes a semiconductor substrate having a die region, a die seal ring region, and a scribe line region; a metal interconnect structure disposed on the semiconductor substrate of the scribe line region; and a plurality of dielectric layers disposed on... Agent: North America Intellectual Property Corporation

20100133670 - Top-side cooled semiconductor package with stacked interconnection plates and method: A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit... Agent: Chein-hwa S. Tsao

20100133672 - Dual-sided substate integrated circuit package including a leadframe having leads with increased thickness: An integrated circuit package includes a first non-conductive substrate having a first inner surface and a second non-conductive substrate having a second inner surface. A die having a first thickness is disposed between the first and second inner surfaces. A leadframe includes a member having a proximal end and a... Agent: Delphi Technologies, Inc Legal Staff - M/c 483-400-402

20100133671 - Flip-chip package structure and the die attach method thereof: A flip-chip package structure comprises a carrier, a block bump, and a die. The carrier is a lead frame or substrate that comprises a lead pattern side, and an electrode pin is disposed on the lead pattern side. The die comprises an active side, and a bond pad is disposed... Agent: Rosenberg, Klein & Lee

20100133673 - Flash memory card: A Flash memory card is disclosed comprising a substrate, a Flash memory die on top of the substrate, a controller die on top of the Flash memory die, and an interposer coupled to with the controller die and on top of the Flash memory die wherein the interposer results in... Agent: Sawyer Law Group, P.C.

20100133676 - A power semiconductor arrangement and a semiconductor valve provided therewith: A power semiconductor arrangement including a clamping device including a first clamping element and a second clamping element. A plurality of power semiconductor elements are stacked on each other between the first and second clamping elements of the clamping device. The first clamping element receives a clamping force in an... Agent: Venable LLP

20100133674 - Compact semiconductor package with integrated bypass capacitor and method: A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous elevation-adaptive interconnection plates for bonding and interconnecting top contact areas of the semiconductor dies with the... Agent: Chein-hwa S. Tsao

20100133675 - Package-on-package device, semiconductor package and method for manufacturing the same: A semiconductor package includes a substrate, a chip, an interposer and a molding compound. The chip is electrically connected to the upper surface of the substrate. The interposer is disposed on the chip, and electrically connected to the upper surface of the substrate. The interposer includes an embedded component and... Agent: Lowe Hauptman Ham & Berner, LLP

20100133677 - Semiconductor chip stacked body and method of manufacturing the same: A plurality of chip sealing bodies stacked on a wiring substrate with a connection terminal. The chip sealing body includes a semiconductor chip having a semiconductor integrated circuit, a pad and a conductive connecting material, and a resin sealing the semiconductor chip. The chip sealing body is shaped into a... Agent: Rankin, Hill & Clark LLP

20100133678 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device includes: a plurality of semiconductor substrates that are layered; a through electrode penetrating through a predetermined semiconductor substrate of the semiconductor substrates and electrically connected with an external terminal of the semiconductor device; a circuit element provided on the predetermined semiconductor substrate; and an electrostatic discharge protection... Agent: Oliff & Berridge, PLC

20100133679 - Compliant integrated circuit package substrate: An integrated circuit package may include a plurality of interconnects, and an integrated package substrate coupled to the plurality of interconnects and comprising an integrated circuit package substrate core. A first surface of the integrated circuit package substrate core may define a depression.... Agent: Buckley, Maschoff & Talwalkar LLC/ Intel Corporation

20100133680 - Wafer level package and method of manufacturing the same and method of reusing chip: The present invention relates to a wafer level package and a method of manufacturing the same and a method of reusing a chip and provides a wafer level package including a chip; a removable resin layer formed to surround side surfaces and a lower surface of the chip; a molding... Agent: Staas & Halsey LLP

20100133681 - Power semiconductor device: A power semiconductor device includes a power semiconductor module having cylindrical conductors which are joined to a wiring pattern so as to be substantially perpendicular to the wiring pattern and whose openings are exposed at a surface of transfer molding resin, and an insert case having a ceiling portion and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100133682 - Semiconductor device: A semiconductor device includes a semiconductor chip, an electrically insulating element separated from the semiconductor chip by a space, and encapsulation material disposed in the space. The semiconductor chip includes a first face having a contact, and the electrically insulating element defines at least one through-hole. The encapsulation material is... Agent: Dicke, Billig & Czaja

20100133684 - Power semiconductor module and manufacturing method thereof: A power semiconductor module includes: a circuit board having a metal base plate, a high thermal conductive insulating layer, and a wiring pattern; power semiconductor elements electrically connected to the wiring pattern; tubular external terminal connection bodies provided to the wiring pattern for external terminals; and a transfer mold resin... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100133683 - System and apparatus for venting electronic packages and method of making same: An apparatus and method, the apparatus includes a substrate configured to support a plurality of dielectric layers, a device coupling area positioned in the substrate, and a plurality of gas exit apertures formed through the substrate. The plurality of gas exit apertures is configured to provide venting of at least... Agent: Ge Trading & Licensing

20100133685 - Direct semiconductor contact ebullient cooling package: The semiconductor package as well as a method for making it and using it is disclosed. The semiconductor package comprises a semiconductor chip having at least one heat-generating semiconductor device and a volumetrically expandable chamber disposed to sealingly surround the semiconductor chip, the volumetrically expandable chamber filled entirely with a... Agent: Gates & Cooper LLP Howard Hughes Center

20100133686 - Chip package structure: A chip package includes a die, a pad-mounting surface on the die, a plurality of bonding pad arranged at the pad-mounting surface, at least one dielectric layer cover over the pad-mounting surface, and at least one conductive wire set in the dielectric layer. The formation of the conductive wire consists... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20100133687 - Semiconductor device with solder bump formed on high topography plated cu pads: A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating... Agent: Robert D. Atkins

20100133688 - Semiconductor integrated circuit device: In semiconductor integrated circuit devices for vehicle use or the like, in general, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding or the like using a gold wire and the like for the convenience of mounting. Such a semiconductor... Agent: Miles & Stockbridge PC

20100133689 - Copper (i) compounds useful as deposition precursors of copper thin films: Copper (I) amidinate precursors for forming copper thin films in the manufacture of semiconductor devices, and a method of depositing the copper (I) amidinate precursors on substrates using chemical vapor deposition or atomic layer deposition processes.... Agent: Intellectual Property / Technology Law

20100133692 - Process for producing silicic coating, silicic coating and semiconductor device: A silicic coating of 2.4 g/cm3 or higher density, obtained by forming a silicic coating precursor with the use of at least one type of silane compound having a photosensitive functional group and thereafter irradiating the silicic coating precursor with at least one type of light. This silicic coating can... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20100133690 - Semiconductor device: A semiconductor device includes a first interconnect 31; a second interconnect 32 which is formed in a different interconnect layer from that of the first interconnect 31, and which has a wider line width than that of the first interconnect 31; and first and second plugs 51 and 52 which... Agent: Mcdermott Will & Emery LLP

20100133691 - Thermally programmable anti-reverse engineering interconnects and methods of fabricating same: An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by... Agent: Schmeiser, Olsen & Watts

20100133694 - Metal interconnect and ic chip including metal interconnect: A metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first... Agent: Hoffman Warnick LLC

20100133693 - Semiconductor package leads having grooved contact areas: A packaged semiconductor device (100) has a first (110) and a second (111) side, the second side including a plurality of metal terminals (120) extending to the first side. Each terminal includes an oblong groove (122) extending to the first side and ending in an orifice (123) at the first... Agent: Texas Instruments Incorporated

20100133695 - Electronic circuit with embedded memory: Circuitry includes first and second circuits spaced apart by an interconnect region. The interconnect region includes a first interconnect, and the second circuit includes a stack of semiconductor layers. The first interconnect extends between the first and second circuits to provide communication therebetween. The second circuit operates as a memory... Agent: Schmeiser Olsen & Watts

20100133696 - Isolation structure for protecting dielectric layers from degradation: An integrated circuit structure includes a semiconductor substrate; and an interconnect structure overlying the semiconductor substrate. A solid metal ring is formed in the interconnect structure, with substantially no active circuit being inside the solid metal ring. The integrated circuit structure further includes a through-silicon via (TSV) having a portion... Agent: Slater & Matsil, L.L.P.

20100133697 - Low resistance through-wafer via: The present invention provides a wafer (3) comprising a through-wafer via (7) through the wafer (3) formed by a through-wafer via hole (9) and at least a first conductive coating (25). A substantially vertical sidewall (11) of the through-wafer via hole (9) except for a constriction (23) provides a reliable... Agent: Foley And Lardner LLP Suite 500

20100133702 - Method for eliminating loading effect using a via plug: Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is characterized by a first thickness. The method also includes... Agent: Townsend And Townsend And Crew, LLP

20100133699 - Microstructure device including a metallization structure with air gaps formed commonly with vias: Air gaps may be formed in a metallization layer of a microstructure device on the basis of a patterning sequence in which respective via openings are also formed. Thereafter, the via openings and the air gaps may be closed by a deposition process without significantly affecting the interior of the... Agent: Advanced Mirco Devices, Inc. C/o Williams, Morgan & Amerson

20100133700 - Performance enhancement in metallization systems of microstructure devices by incorporating grain size increasing metal features: In a sophisticated metallization system, enhanced electromigration behavior may be accomplished by incorporating electromigration barriers into metal lines after a given distance, which may be accomplished by providing an increased width in order to obtain an enhanced average grain size in the intermediate metal regions of increased lateral width. Consequently,... Agent: Williams, Morgan & Amerson

20100133701 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device includes: a plurality of external terminals; a plurality of semiconductor substrates that are layered; a through electrode penetrating through at least one of the semiconductor substrates and electrically connected with any of the external terminals; and a plurality of electrostatic discharge protection circuits provided on any one... Agent: Oliff & Berridge, PLC

20100133698 - Semiconductor device and method of manufacturing semiconductor device: A method of manufacturing a semiconductor device which enables reduction of material costs and manufacturing costs of the semiconductor device includes forming a silicon cermet film, forming a protective film that protects the silicon cermet film, making a contact hole by plasma etching of the protective film. In this method,... Agent: Young & Thompson

20100133703 - Semiconductor chip laminate and adhesive composition for semiconductor chip lamination: A semiconductor chip laminate comprises a plurality of semiconductor chips and an adhesive layer through which the plurality of semiconductor chips are laminated, wherein the adhesive layer is composed of an adhesive composition comprising an acrylic polymer (A); an epoxy resin (B); a thermal curing agent (C); and a certain... Agent: The Webb Law Firm, P.C.

20100133704 - Semiconductor device and method of forming an interposer package with through silicon vias: A semiconductor device is fabricated by providing a carrier for supporting the semiconductor device. A first semiconductor die is mounted to the carrier. The first semiconductor die has a contact pad. A first dummy die is mounted to the carrier. The first dummy die has a through-silicon via (TSV). The... Agent: Robert D. Atkins

20100133705 - Apparatus and method for reducing pitch in an integrated circuit: An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first and a second contact pad formed thereon, a first dielectric layer coupled to the electronic chip, a second dielectric layer coupled to the first dielectric layer such that a dielectric boundary lies... Agent: Ge Trading & Licensing