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Active solid-state devices (e.g., transistors, solid-state diodes) February patent applications/inventions, industry category 02/10

20100044665 - Electronic component, and a method of manufacturing an electronic component: An electronic component (100) comprising a matrix (102) and a plurality of islands (103) embedded in the matrix (102) and comprising a material which is convertible between at least two states characterized by different electrical properties, wherein the plurality of islands (103) form a continuous path (104) in the matrix... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100044668 - Hybrid mrar array structure and operation: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics... Agent: Dickstein Shapiro LLP

20100044664 - Memory devices and methods of forming the same: Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The laterally constricted portions of adjacent memory cells are vertically offset and positioned on opposite sides of the memory device. Also disclosed are memory devices having a... Agent: Trask Britt, P.C./ Micron Technology

20100044666 - Resistive memory cells and devices having asymmetrical contacts: A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater... Agent: Myers Bigel Sibley & Sajovec

20100044667 - Semiconductor devices having a planarized insulating layer: A semiconductor device includes at least one phase-change pattern disposed on a semiconductor substrate. A planarized capping layer, a planarized protecting layer, and a planarized insulating layer are sequentially stacked to surround sidewalls of the at least one phase-change pattern. An interconnection layer pattern is disposed on the planarized capping... Agent: Myers Bigel Sibley & Sajovec

20100044669 - Integrated circuit including memory cell having cup-shaped electrode interface: An integrated circuit includes a first electrode and a cup-shaped electrode interface coupled to the first electrode. The integrated circuit includes a dielectric spacer at least partially laterally enclosed by the electrode interface and a resistance changing material laterally enclosed by the spacer and contacting the electrode interface. The integrated... Agent: Dicke, Billig & Czaja

20100044671 - Methods for increasing carbon nano-tube (cnt) yield in memory devices: In some aspects, a method of forming a carbon nano-tube (CNT) memory cell is provided that includes (1) forming a first conductor; (2) forming a steering element above the first conductor; (3) forming a first conducting layer above the first conductor; (4) forming a CNT material above the first conducting... Agent: Dugan & Dugan, PC

20100044670 - Semiconductor device structures having single-crystalline switching device on conducting lines and methods thereof: A memory device includes a composite dielectric layer overlying a substrate. The composite dielectric layer includes a first dielectric layer, a bonding interface, and a second dielectric layer. The first and the second dielectric layers are bonded together at the bonding interface. A first plurality of conductive lines overlies the... Agent: Peiching Ling

20100044672 - Semiconductor memory: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of... Agent: Miles & Stockbridge PC

20100044673 - Labeling fluorescent compound: A labeling fluorescent compound which enables highly stable detection in vital labeling and has high sensitivity. The labeling fluorescent compound is characterized by being composed of inorganic fluorescent nanoparticles which have a surface modification compound disposed on the surface thereof and have an average particle diameter of 1.0-20 nm. It... Agent: Lucas & Mercanti, LLP

20100044674 - Light emitting diode having modulation doped layer: A light emitting diode (LED) having a modulation doped layer. The LED comprises an n-type contact layer, a p-type contact layer and an active region of a multiple quantum well structure having an InGaN well layer. The n-type contact layer comprises a first modulation doped layer and a second modulation... Agent: H.c. Park & Associates, PLC

20100044675 - Photovoltaic device with an up-converting quantum dot layer: A photovoltaic apparatus includes an absorber layer, and an up-converter layer positioned adjacent to the absorber layer, the up-converter layer including a plurality of quantum dots of first material in a matrix of a second material. In one example, the first material has a lower bandgap than the absorber layer,... Agent: Pietragallo Gordon Alfano Bosick & Raspanti, LLP

20100044676 - Photodetectors and photovoltaics based on semiconductor nanocrystals: A composite material is described. The composite material comprises semiconductor nanocrystals, and organic molecules that passivate the surfaces of the semiconductor nanocrystals. One or more properties of the organic molecules facilitate the transfer of charge between the semiconductor nanocrystals. A semiconductor material is described that comprises p-type semiconductor material including... Agent: Courtney Staniford & Gregory LLP

20100044677 - Photodiode array, method of manufacturing the same, and detecting device: A photodiode array includes a p-side electrode provided on each p-type region formed by selective diffusion and an n-side electrode connected to a non-growth part of an InP substrate and extends to the top surface side of an epitaxial multilayer. A wall surface of an edge at the non-growth part... Agent: Fish & Richardson P.C.

20100044679 - Method for producing carbon nanotube transistor and carbon nanotube transistor thereby: p

20100044678 - Method of placing a semiconducting nanostructure and semiconductor device including the semiconducting nanostructure: A method of placing a functionalized semiconducting nanostructure, includes functionalizing a semiconducting nanostructure including one of a nanowire and a nanocrystal, with an organic functionality including a functional group for bonding to a bonding surface, dispersing the functionalized semiconducting nanostructure in a solvent to form a dispersion, and depositing the... Agent: Mcginn Intellectual Property Law Group, PLLC

20100044680 - Novel underlayer for high performance magnetic tunneling junction mram: An MRAM structure is disclosed in which the bottom electrode has an amorphous TaN capping layer to consistently provide smooth and dense growth for AFM, pinned, tunnel barrier, and free layers in an overlying MTJ. Unlike a conventional Ta capping layer, TaN is oxidation resistant and has high resistivity to... Agent: Saile Ackerman LLC

20100044684 - Blended polymer fets: A method for forming a semiconductor body, the method comprising: forming a mixture of an organic semiconducting material and a binder material; causing the semiconducting material to at least partially solidify; and causing the binder material to crystallize in such a way as to cause the semiconducting material to at... Agent: Sughrue Mion, PLLC

20100044682 - Charge injection layer for electro-optical devices: The present invention relates to charge injection from metallic conductors to semiconductor or insulation materials based on organic or inorganic molecules and macromolecules with electrical or optical properties, and specifically to a new charge injection layer for electro-optical devices comprising a polymer with conjugated units and a salt mixed with... Agent: Ladas & Parry LLP

20100044695 - Compound for organic electroluminescent device and organic electroluminescent device: Disclosed is an organic electroluminescent device (organic EL device) which is improved in luminous efficiency, fully secured of driving stability, and of simple constitution. Also disclosed is a compound useful for the fabrication of said organic EL device. The organic electroluminescent device comprises organic layers including a light-emitting layer disposed... Agent: Birch Stewart Kolasch & Birch

20100044688 - Electroluminescent metal complex: Metal complexes of the formula I or I′ [LDH]nM[L]m (I) [LTH](M[L]p)2 (I1) wherein n is an integer 1 or 2, m and p each is an integer 1 or 2, the sum (n+m) being 2 or 3, M is a metal with an atomic weight of greater than 40 such... Agent: Ciba Corporation Patent Department

20100044694 - Ito film treated by nitrogen plasma and the organic luminescent device using the same: Disclosed are an Indium Tm Oxide (ITO) film, wherein nitrogen-containing compounds produced by reactions of nitrogen with at least one atom selected from the group consisting of In, Sn and O atoms which are constitutional elements of ITO, or deposited nitrogen-containing compounds are present on a surface of the ITO... Agent: Mckenna Long & Aldridge LLP

20100044686 - Material for an organic electroluminescence device and an organic electroluminescence device: wherein X1 is one of divalent groups represented by the following (a) to (e); Y1 to Y4 are independently a carbon atom or a nitrogen atom; and R1 to R4 are independently a hydrogen atom, an alkyl group, a substituted or unsubstituted aryl group, a substituted or unsubstituted heterocycle, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100044681 - Novel anthracene derivatives, method for preparation thereof, and organic electronic device using the same: The present invention relates to a novel anthracene derivative, a method for preparation thereof, and an organic electronic device using the same. The anthracene derivative according to the present invention can function as a hole injecting, hole transporting, electron injecting, electron transporting, or light emitting in an organic electronic device... Agent: Mckenna Long & Aldridge LLP

20100044689 - Organic el device: e

20100044690 - Organic el display device: An organic EL display device includes a first organic EL element which includes a first organic layer including a first light emission layer which emits the color of light in the first wavelength range and a hole blocking layer between a pixel electrode and a counter-electrode, a second organic EL... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100044693 - Organic el light-emitting material and organic el light-emitting element: An organic EL light-emitting material and an organic EL light-emitting element using the same are provided. Between an anode and a cathode, there are provided a hole transport layer, a light-emitting layer constituted of an organic EL light-emitting material including at least one kind of metal pyrazole complex constituted of... Agent: K&l Gates LLP

20100044687 - Organic field-effect transistors with polymeric gate dielectric and method for making same: A method for making an organic field-effect device (e.g. TFT or SC-FET device) is proposed, comprising the Steps of (a) depositing an polymeric dielectric with a repellency to detrimental molecules from Solution or from the vapor phase to form an insulating layer and (b) depositing an oligomer layer which is... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20100044691 - Organic light emitting diode display and method for manufacturing the same: Aspects of the present invention relate to an organic light emitting diode (OLED) display and a manufacturing method thereof. The OLED display includes: a substrate; pixel electrodes disposed on the substrate; a pixel defining layer disposed on the substrate, having a plurality of openings that expose the pixel electrodes; an... Agent: Stein Mcewen, LLP

20100044692 - Organic light emitting diode display and method for manufacturing the same: The present invention relates to an organic light emitting diode (OLED) display and a manufacturing method thereof. The OLED display includes a substrate member that includes a plurality of pixel areas. A thin film transistor (TFT) is formed on the substrate member and includes a gate electrode, a source electrode,... Agent: Knobbe Martens Olson & Bear LLP

20100044685 - Organic light emitting diode display and method of manufacturing the same: An organic light emitting diode display including a substrate; a light blocking layer disposed on the substrate and having a semiconductor opening; a first semiconductor pattern disposed in the semiconductor opening; a gate insulating layer disposed on the light blocking layer and the first semiconductor pattern; a first gate electrode... Agent: Cantor Colburn, LLP

20100044696 - Thin film transistor and liquid crystal display: A thin film transistor is provided. The thin film transistor includes a substrate, a gate, a source/drain, an insulating layer, and a semiconductor active layer. The gate and the source/drain are respectively deposited on the substrate and are separated by the insulating layer on the substrate. The semiconductor active layer... Agent: Jianq Chyun Intellectual Property Office

20100044683 - Use of square planar transition metal complexes as dopant: The present invention relates to the use of a square planar transition metal complex as dopant, charge injection layer, electrode material or storage material.... Agent: Sutherland Asbill & Brennan LLP

20100044703 - Amorphous oxide semiconductor, semiconductor device, and thin film transistor: e

20100044700 - Oxide semiconductor and thin film transistor including the same: Disclosed are an oxide semiconductor and a thin film transistor (TFT) including the same. The oxide semiconductor may include a lanthanoid (Ln) added to zinc oxide (ZnO) and may be used as a channel material of the TFT.... Agent: Harness, Dickey & Pierce, P.L.C

20100044702 - Semiconductor element, method for manufacturing same, and electronic device including same: A thin-film transistor (1) of the present invention includes an insulating substrate (2), a gate electrode (3) which has a predetermined shape and is formed on the insulating substrate (2), a gate insulating film (4) formed on the gate electrode (3), and a semiconductor layer (5) which is polycrystalline ZnO... Agent: Nixon & Vanderhye, PC

20100044698 - Semiconductor film composition: A semiconductor film composition includes an oxide semiconductor material. At least one polyatomic ion is incorporated into the oxide semiconductor material.... Agent: Hewlett-packard Company Intellectual Property Administration

20100044699 - Thin film transistor and method of fabricating the same: A thin film transistor (TFT) including a gate electrode, an active layer, and source and drain electrodes. The active layer includes contact regions that contact the source and drain electrodes, which are thinner than a remaining region of the active layer. The contact regions reduce the contact resistance between the... Agent: Stein Mcewen, LLP

20100044701 - Thin-film transistor fabrication process and display device: In a process for fabricating a thin-film transistor in which a gate electrode 4 is to be formed on a substrate 1, the process has the steps of forming the gate electrode 4 on the substrate 1, forming a metal oxide layer 7 in such a way as to cover... Agent: Fitzpatrick Cella Harper & Scinto

20100044697 - Bright visible wavelength luminescent nanostructures and methods of making and devices for using the same: Luminescent nanostructures (e.g., nanowires) and devices are provided which are capable of emitting bright visible light. The luminescent nanowires are most preferably in the form of a doped ZnO having a spectrally integrated ratio of visible to UV light of at least about 1000 or greater. The dopant for the... Agent: Nixon & Vanderhye, PC

20100044704 - Vertical thermoelectric structures: A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at... Agent: Texas Instruments Incorporated

20100044705 - Doped substrate to be heated: A semiconductor structure that is to be heated. The structure includes a substrate for the front face deposition of a useful layer intended to receive components for electronics, optics or optoelectronics. The structure contains doped elements that absorb infrared radiation so as to substantially increase infrared absorption by the structure... Agent: Winston & Strawn LLP Patent Department

20100044706 - Methods of forming a layer of material on a substrate and structures formed therefrom: Various structures that include at least one thin layer of an amorphous material on a supporting substrate. One structure generally has a receiving substrate, a central crystalline layer and an amorphous layer, all of which may lack any end of range point defects. Another structure includes an intermediate substrate having... Agent: Winston & Strawn LLP Patent Department

20100044707 - Thin film transistor array substrate, method for manufacturing the same and system for inspecting the substrate: Disclosed is a thin film transistor substrate and a system for inspecting the same. The thin film transistor substrate comprises gate wiring formed on an insulation substrate and including gate lines, and gate electrodes and gate pads connected to the gate lines; a gate insulation layer covering the gate wiring;... Agent: Innovation Counsel LLP

20100044710 - Active matrix substrate: In an active-matrix substrate (100) according to the present invention, a semiconductor layer (110) has a first gettering region (112) adjacent to the source region (132) of a first thin-film transistor (130), a second gettering region (114) adjacent to the drain region (146) of a second thin-film transistor (140), and... Agent: Nixon & Vanderhye, PC

20100044714 - Display device: The present invention provides an active matrix type display device having a high aperture ratio and a required auxiliary capacitor. A source line and a gate line are overlapped with part of a pixel electrode. This overlapped region functions to be a black matrix. Further, an electrode pattern made of... Agent: Fish & Richardson P.C.

20100044713 - Liquid crystal display device and electronic device provided with the same: A liquid crystal display device provided with a thin film transistor with excellent electrical characteristics and reduced off current, for which increase in manufacturing costs can be suppressed while suppressing reduction in yield. A thin film transistor includes a gate electrode provided over a substrate; a gate insulating film provided... Agent: Eric Robinson

20100044711 - Thin film transistor, active matrix substrate, and image pickup device: A thin film transistor including: source and drain electrodes, an active layer that contacts the source and drain electrodes and contains an oxide semiconductor, a gate electrode that controls current flowing between the source and drain electrodes via the active layer, a first insulating film that separates the gate electrode... Agent: Solaris Intellectual Property Group, PLLC

20100044709 - Thin film transistor, manufacturing method thereof and display device: A thin film transistor is formed by laminating a gate electrode 3, a gate insulating film(4), a channel layer(5), and source/drain layers(7),(8) on a substrate(2) in this order or in a reversed order thereof. The thin film transistor is characterized in that the source/drain layers(7), (8) contain impurities having a... Agent: Sonnenschein Nath & Rosenthal LLP

20100044708 - Thin film transistor, pixel structure and fabrication methods thereof: A fabrication method of a thin film transistor includes providing a substrate at first. Thereafter, a first gate is formed on the substrate. An insulator is then formed to cover the first gate and a portion of the substrate. After that, a channel structure is formed on the insulator above... Agent: Jianq Chyun Intellectual Property Office

20100044712 - Thin-film transistor substrate and method of manufacturing the same: A thin-film transistor substrate includes a gate line, a capacitor dielectric layer, a gate insulation layer, an active pattern, a data line, a protection layer, and a pixel electrode. The gate wiring including a gate electrode, a lower storage electrode, and a gate metal pad is disposed on a substrate.... Agent: H.c. Park & Associates, PLC

20100044716 - Pixel structure and liquid crystal display panel: A pixel structure is disclosed. The pixel structure is suitable to be disposed on a substrate and includes a first pixel electrode, a second pixel electrode and a top gate TFT. The first pixel electrode and the second pixel electrode are disposed over the substrate, wherein the first pixel electrode... Agent: Jianq Chyun Intellectual Property Office

20100044715 - Thin film transistor array substrate and method of fabricating the same: A TFT array substrate including a substrate, a plurality of pixel structures and a plurality of cutting marks is provided. The substrate has a device region and a cutting mark region. The pixel structures are disposed in the device region and each pixel structure includes a TFT, a pixel electrode... Agent: Jianq Chyun Intellectual Property Office

20100044717 - Thin film transistor panel and method of manufacturing the same: After forming a signal line including aluminum, an upper layer of an oxide layer including aluminum that covers the signal line is formed in the same chamber and by using the same sputtering target as the signal line, or a buffer layer of an oxide layer including aluminum is formed... Agent: Cantor Colburn, LLP

20100044718 - Group iii nitride articles and methods for making same: Group III (Al, Ga, In)N single crystals, articles and films useful for producing optoelectronic devices (such as light emitting diodes (LEDs), laser diodes (LDs) and photodetectors) and electronic devices (such as high electron mobility transistors (HEMTs)) composed of III-V nitride compounds, and methods for fabricating such crystals, articles and films.... Agent: Goodwin Procter LLP Patent Administrator

20100044719 - Iii-v compound semiconductor epitaxy using lateral overgrowth: A circuit structure includes a substrate; a patterned mask layer over the substrate, wherein the patterned mask layer includes a plurality of gaps; and a group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layer includes a first portion over the mask layer and second portions in the gaps,... Agent: Slater & Matsil, L.L.P.

20100044721 - Method of producing semiconductor device and semiconductor device: The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property... Agent: Venable LLP

20100044720 - Semiconductor device with a reduced band gap and process: The application relates to a semiconductor device made of silicon with regionally reduced band gap and a process for the production of same. One embodiment provides a semiconductor device including a body zone, a drain zone and a source zone. A gate extends between the source zone and the drain... Agent: Dicke, Billig & Czaja

20100044722 - Sensing module: A sensing module comprises a carrier, a sensor, a substrate, and a plurality of chips. The carrier has a carrying surface and a back surface opposite to the carrying surface. The sensor and the substrate are disposed on the carrying surface and are electrically connected to the carrier respectively. The... Agent: Hdls Patent & Trademark Services

20100044723 - Package for photoelectric wiring and lead frame: A package for a photoelectric wiring in which a pair of light emitting and receiving devices are mounted as optical devices on a lead frame having an optical waveguide in which an optical waveguide having a plurality of core portions disposed in parallel and surrounded by a cladding is mounted... Agent: Rankin, Hill & Clark LLP

20100044724 - Device for defeating reverse engineering of integrated circuits by optical means: An integrated circuit and method are provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the integrated circuit. The method prevents, in an integrated circuit, a pattern of light emitted from at least one active device in the integrated circuit from... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.

20100044725 - Device for defeating reverse engineering of integrated circuits by optical means: An integrated circuit and method are provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the integrated circuit. The method prevents, in an integrated circuit, a pattern of light emitted from at least one active device in the integrated circuit from... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.

20100044727 - Led package structure: A LED package structure includes an insulating ceramic base, whereon a first surface and a second surface are formed. The LED package structure further includes a casing disposed on the first surface of the insulating ceramic base. A hole is formed on the casing. The LED package structure further includes... Agent: North America Intellectual Property Corporation

20100044726 - Method for packaging white-light led and led device produced thereby: This invention relates to light-emitting diodes or devices (LEDs), such as LED lighting assemblies and methods of manufacturing them. More particularly, this invention relates to white-light LED lighting assemblies, devices, and components, methods for packaging white-light LEDs, and LED devices produced thereby. A method for packaging a white-light LED is... Agent: Latimer & MayberryIPLaw, LLP

20100044728 - Electroluminescent device: An electroluminescent device includes, for example, first to third optical output parts respectively corresponding to red, green, and blue colors and each having a light-emitting layer. A visibility spectrum curve has an inclination value corresponding to the first optical output part, an inclination value corresponding to the second optical output... Agent: Robert A. Zambias President

20100044729 - Warm-white light emtitting diode and its halide phosphor powder: The invention relates to a halide phosphor powder for warm-white light emitting diode, which is a kind of low-color-temperature phosphor powder of halide nitride based on garnet of rare earth oxides, uses cerium as activating agent and is characterized in that chloride (Cl−1) and nitrogen ion (N−3) are added to... Agent: Guice Patents PLLC

20100044733 - Electroluminescence element: An electroluminescence element includes: an electroluminescence substrate including a thin film transistor substrate, and a light-emitting layer provided over the thin film transistor substrate and divided by picture-element separating portions so as to correspond to unit picture elements; and a sealing substrate arranged to hermetically seal the light-emitting layer of... Agent: Sharp Kabushiki Kaisha C/o Keating & Bennett, LLP

20100044732 - Light emitting diode structure and method of forming the same: A light emitting diode structure and a light emitting diode structure forming method are provided. The light emitting diode structure includes a base, a diode chip, and a package lens. The diode chip is mounted on the base. The package lens covers the diode chip. The surface of the package... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100044735 - Light-emitting device: A light-emitting device includes a substrate (4), a light-emitting element (10) mounted on the substrate (4), a first resin (12) disposed to cover an upper portion of the light-emitting element (10), a second resin (14) disposed to cover a lower portion of the light-emitting element (10), a first phosphor (18)... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20100044739 - Light-radiating semiconductor component with a luminescence conversion element: The light-radiating semiconductor component has a radiation-emitting semiconductor body and a luminescence conversion element. The semiconductor body emits radiation in the ultraviolet, blue and/or green spectral region and the luminescence conversion element converts a portion of the radiation into radiation of a longer wavelength. This makes it possible to produce... Agent: Fish & Richardson PC

20100044734 - Manufacturing method of semiconductor light-emitting apparatus and semiconductor light-emitting apparatus: A method includes forming a light-emission operating layer on a growth substrate; forming a reflection insulating layer on the light-emission operating layer; forming opening portions in the insulating layer; forming a contact portion which has a thickness adapted to flatten the opening portions and has been embedded into the opening... Agent: Frishauf, Holtz, Goodman & Chick, PC

20100044730 - Organic light emitting diode display device and method of fabricating the same: An organic light emitting diode display device having a frit which can improve mechanical strength and adhesion between the upper substrate and the lower substrate, and a method of fabricating the same are disclosed. The organic light emitting diode display device includes a lower substrate, an organic light emitting diode... Agent: Knobbe Martens Olson & Bear LLP

20100044738 - Preparation of organic light emitting diodes by a vapour deposition method combined with vacuum lamination: A method of fabricating an organic light emitting diode (OLED) is disclosed, which reduces the formation of physical defects in the GLED, comprising the removal of dust particles from a first and a second substrates (40, 90), separately coating the first and the second substrate using a vapour deposition method... Agent: Philips Intellectual Property & Standards

20100044736 - Semiconductor apparatus and method of manufacturing same: Disclosed is a semiconductor apparatus having a sealing structure that allows high-precision detection of defects occurring in a protective film, and a method of manufacturing the same. A semiconductor apparatus 1 includes a substrate 10, a semiconductor device 14 formed on the substrate 10, and a protective film 17 for... Agent: Drinker Biddle & Reath (dc)

20100044740 - Semiconductor device: A semiconductor device with a substrate, a first electrode on the substrate, at least one of an injection layer or a transporting layer on the first electrode, an adhesion layer on the at least one of an injection layer or a transporting layer, and a second electrode on the adhesion... Agent: Ked & Associates, LLP

20100044737 - Semiconductor light emitting device: A semiconductor light emitting device (A) includes a lead frame (1) having a constant thickness, a semiconductor light emitting element (2) supported by the lead frame (1), a case (4) covering part of the lead frame (1) and a light transmitting member (5) covering the semiconductor light emitting element (2).... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20100044731 - Semiconductor light-emitting device: Such a semiconductor light-emitting device (10, 30, 40) that emitted light has small directivity of light intensity and a color tone and a light output is hardly reduced is obtained. This semiconductor light-emitting device includes a semiconductor light-emitting element (1, 31) and a thin-film light diffusion portion (8, 8a, 38,... Agent: Ditthavong Mori & Steiner, P.C.

20100044746 - Carrier and optical semiconductor device based on such a carrier: A method for providing, on a carrier (40), an insulative spacer layer (26) which is patterned such that a cavity (27) is formed which enables connection of an optical semiconductor element (41) to the intended conductor structure (22) when placed inside the cavity (27). The cavity (27) is formed such... Agent: Philips Intellectual Property & Standards

20100044743 - Flip chip light emitting diode with epitaxial strengthening layer and manufacturing method thereof: A flip chip light emitting diode with an epitaxial strengthening layer and a manufacturing method thereof are revealed. The flip chip light emitting diode with an epitaxial strengthening layer includes an epitaxial structure connected with an epitaxial strengthening layer while the manufacturing method of the flip chip light emitting diode... Agent: Sinorica, LLC

20100044744 - Light emitting diode having extensions of electrodes for current spreading: Disclosed is a light emitting diode having extensions of electrodes for improving current spreading. The light emitting diode includes a lower semiconductor layer, an upper semiconductor layer and an active layer, which are formed on a substrate. The upper semiconductor layer is located above the lower semiconductor layer such that... Agent: H.c. Park & Associates, PLC

20100044742 - Light emitting diode module: The present invention provides a light emitting diode module including an insulating layer, a first circuit pattern layer and a second circuit pattern layer which are stacked on a top surface and a bottom surface of the insulating layer respectively and have one ends protruding to an outside of the... Agent: Mcdermott Will & Emery LLP

20100044741 - Lighting device: A fighting device of the present invention includes light emitting unit 20 having a light emitting element installed on a board, and body 11 having light emitting unit 20 mounted thereon. Body 11 has graphite having anisotropic heat conductivity, and the graphite has inner wall 11c in thermal contact with... Agent: Young & Thompson

20100044745 - Optical semiconductor device module with power supply through uneven contacts: In an optical semiconductor device module constructed by an optical semiconductor device having a light emitting portion on its top surface, a mounting substrate adapted to mount the optical semiconductor device thereon, at least one wiring pattern layer formed on a front surface of the mounting substrate, and at least... Agent: Cermak Kenealy Vaidya & Nakajima LLP

20100044747 - Semiconductor light emitting device: A semiconductor light emitting device (A1) includes a substrate (1) and two electrodes (2A, 2B) formed on the substrate (1). The electrode (2A) is formed with a die bonding pad (2Aa), to which an LED chip (3) is bonded by silver paste (6). The outer edge of the die bonding... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20100044749 - Bidirectional semiconductor device, method of fabricating the same, and semiconductor device incorporating the same: A semiconductor device and a method of fabrication thereof includes a bidirectional device having a high breakdown voltage and a decreased ON voltage. An n-type extended drain region is formed in the bottom surface of each trench. A p-type offset region is formed in each split semiconductor region. First and... Agent: Rossi, Kimms & Mcdowell LLP.

20100044748 - Electrostatic discharge protection device: An ESD protection device includes a p-well with first protrudent portions, an N-well with second protrudent portions, a P-well/N-well boundary, a PMOS transistor disposed in the N-well, an NMOS transistor disposed in the P-well, first P+ diffusion regions in the first protrudent portions, first N+ diffusion regions in the second... Agent: North America Intellectual Property Corporation

20100044750 - Electrostatic protection element: An electrostatic protection element relating to the present invention comprises a P-type semiconductor and an N-type first impurity layer provided in the semiconductor substrate. The first impurity layer comprises a P-type second impurity layer functioning as a gate. The second impurity layer comprises an N-type third impurity layer functioning as... Agent: Mcdermott Will & Emery LLP

20100044751 - Enhancement mode iii-nitride device with floating gate and process for its manufacture: An enhancement mode III-Nitride device has a floating gate spaced from a drain electrode which is programmed by charges injected into the floating gate to form a permanent depletion region which interrupts the 2-DEG layer beneath the floating gate. A conventional gate is formed atop the floating gate and is... Agent: Farjami & Farjami LLP

20100044753 - Semiconductor device: A nitride semiconductor device 2 comprises a nitride semiconductor layer 10. A gate insulating film 16 is formed on the surface of the nitride semiconductor layer 10. The gate insulating film 16 includes a portion composed of an aluminum nitride film 15 and a portion composed of an insulating material... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20100044752 - Semiconductor device and manufacturing method: A metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) has a substrate in which an electron supply layer is interposed between an electron channel layer and the surface of the substrate. A pair of main electrodes are formed on the surface of the substrate. A recess is formed in the surface of... Agent: Rabin & Berdo, PC

20100044754 - Strained transistor integration for cmos: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20100044755 - Semiconductor device: A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend... Agent: Mcdermott Will & Emery LLP

20100044756 - Method of fabricating a self-aligning damascene memory structure: A method of forming a memory cell is provided, the method including forming a first pillar-shaped element comprising a first semiconductor material, forming a first mold comprising an opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the opening to form a second pillar-shaped element... Agent: Dugan & Dugan, PC

20100044757 - Semiconductor device having a contact plug and manufacturing method thereof: There is provided a semiconductor device that includes: a transistor having a gate electrode, a source region, arid a drain region; a first inter-layer insulation film covering the transistor; a first contact plug formed penetrating through the first inter-layer insulation film and connected to either the source region or the... Agent: Young & Thompson

20100044758 - Cmos with channel p-finfet and channel n-finfet having different crystalline orientations and parallel fins: An integrated circuit is fabricated with at least one p-FinFET device and at least one n-FinFET device situated parallel to each other. A first silicon layer having a first crystalline orientation is bonded to a second silicon layer having a second crystalline orientation. The first and second orientations are different... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.

20100044759 - Double-sided integrated circuit chips: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and... Agent: Schmeiser, Olsen & Watts

20100044762 - Method for forming a semiconductor device and structure thereof: A non-planar semiconductor device (10) starts with a silicon fin (42). A source of germanium (e.g. 24, 26, 28, 30, 32) is provided to the fin (42). Some embodiments may use deposition to provide germanium; some embodiments may use ion implantation (30) to provide germanium; other methods may also be... Agent: Freescale Semiconductor, Inc. Law Department

20100044760 - Self-aligned impact-ionization field effect transistor: An impact ionisation MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100044761 - Semiconductor device and methods for fabricating same: A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active... Agent: Ingrassia Fisher & Lorenz, P.C. (gf)

20100044764 - Complementary metal oxide semiconductor image sensor and method for fabricating the same: A complementary metal oxide semiconductor (CMOS) device and a method for fabricating the same are provided. The CMOS image sensor includes: a first conductive type substrate including a trench; a channel stop layer formed by using a first conductive type epitaxial layer over an inner surface of the trench; a... Agent: Mcandrews Held & Malloy, Ltd

20100044763 - Method and apparatus providing an imager with a shared power supply and readout line for pixels: A method and apparatus providing an imager with shared power supply and readout lines. A pixel array has a plurality of pixels arranged in rows and columns. Each column of the array comprises a column line coupled to receive pixel signals from the pixels in the column and selectively operated... Agent: Dickstein Shapiro LLP

20100044765 - Semiconductor device: Provided is a metal oxide semiconductor (MOS) capacitor, in which trenches (3) are formed in a charge accumulation region (6) of a p-type silicon substrate (1) to reduce a contact area between the p-type silicon substrate (1) and a lightly doped n-type well region (2), thereby reducing a leak current... Agent: Brinks Hofer Gilson & Lione/seiko Instruments Inc.

20100044766 - Method of manufacturing semiconductor device and semiconductor device: Disclosed is a semiconductor device of n-type MOSFET structure, which comprises a semiconductor substrate having a device isolation region, diffusion regions formed in the semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a F-containing NiSi layer formed on the diffusion regions and containing F atoms at a concentration... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100044767 - Structure and fabrication method for capacitors integratible with vertical replacement gate transistors: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second... Agent: Agere Lerner, David Et Al.

20100044769 - Method of manufacture of contact plug and interconnection layer of semiconductor device: A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100044768 - Reduced-edge radiation-tolerant non-volatile transistor memory cells: An edgeless one-transistor flash memory array includes transistors that have two polysilicon gate layers that overlay an active region. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach... Agent: Lewis And Roca LLP

20100044770 - Semiconductor device and method of fabricating the same: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate, forming a diffusion barrier for preventing metal diffusion over the insulation layer, forming a gate electrode layer over the diffusion barrier, forming a metal layer over the gate electrode layer, and performing a thermal treatment... Agent: Lowe Hauptman Ham & Berner, LLP

20100044771 - Zr-sn-ti-o films: A dielectric layer containing a Zr—Sn—Ti—O film and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. In an embodiment, forming the Zr—Sn—Ti—O film on a substrate includes depositing materials of the Zr—Sn—Ti—O film substantially as... Agent: Schwegman, Lundberg & Woessner/micron

20100044772 - Nonvolatile semiconductor device and method of manufacturing nonvolatile semiconductor device: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate,... Agent: Mcdermott Will & Emery LLP

20100044773 - Semiconductor memory device: An element formation region is formed in a region of a semiconductor substrate sandwiched between element isolation regions. In the element isolation regions, a silicon oxide film is filled in a trench having a predetermined depth. An erase gate electrode is formed in the element isolation region while being buried... Agent: Mcdermott Will & Emery LLP

20100044774 - Flash memory device and method of fabricating the same: Disclosed here in is a flash memory device and a method of fabricating the same. In accordance with one aspect of the invention, a flash memory device includes first contact plugs formed over a semiconductor substrate between gate patterns. Second contact plugs are formed over the semiconductor substrate between gate... Agent: Marshall, Gerstein & Borun LLP

20100044776 - Nonvolatile semiconductor memory device and method for manufacturing same: A multilayer body is formed by alternately stacking electrode films serving as control gates and dielectric films in a direction orthogonal to an upper surface of a silicon substrate. Trenches extending in the word line direction are formed in the multilayer body and a memory film is formed on an... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100044775 - Semiconductor memory device and semiconductor device: Provided is a semiconductor memory device that can retain information by trapping electric charges into a trap level in a gate insulating film. The information retention capacity is improved by restricting lateral diffusion of electric charges. The semiconductor memory device is provided with a semiconductor substrate (11), first and second... Agent: Mr. Jackson Chen

20100044779 - Memory devices capable of reducing lateral movement of charges: Memory devices is provided, the memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate... Agent: Harness, Dickey & Pierce, P.L.C

20100044778 - Non-volatile memory device and method of manufacturing same: A non-volatile memory device and a method of manufacturing the non-volatile memory device are provided. At least one first semiconductor layer and at least one second semiconductor layer are disposed. At least one control gate electrode is disposed between the at least one first semiconductor layer and the at least... Agent: Lee & Morse, P.C.

20100044777 - Reconfigurable semiconductor device: A reconfigurable semiconductor device is disclosed. The semiconductor device includes a substrate, a first insulating material formed on the substrate, two channels having different polarities, a plurality of terminal electrodes formed on the insulating material and coupled in common with the channels at their opposite ends, a second insulating material... Agent: Knobbe Martens Olson & Bear LLP

20100044782 - Integrated circuit having long and short channel metal gate devices and method of manufacture: Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate, a short channel (SC) device, and a long channel (LC) device. The short channel device includes an SC gate insulator overlying a first portion of the substrate, an SC metal gate overlying the SC... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20100044781 - Semiconductor device: To suppress short channel effects and obtain a high driving current by means of a semiconductor device having an MISFET wherein a material having high mobility and high dielectric constant, such as germanium, is used for a channel. A p-type well is formed on a surface of a p-type silicon... Agent: Mr. Jackson Chen

20100044780 - Transistor with gain variation compensation: A semiconductor device and method of making comprises providing an active device region and an isolation region, the isolation region forming a boundary with the active device region. A patterned gate material overlies the active device region between first and second portions of the boundary. The patterned gate material defines... Agent: Freescale Semiconductor, Inc. Law Department

20100044783 - Integrated circuit metal gate structure and method of fabrication: A method is provided for forming a metal gate using a gate last process. A trench is formed on a substrate. The profile of the trench is modified to provide a first width at the aperture of the trench and a second width at the bottom of the trench. The... Agent: Haynes And Boone, LLPIPSection

20100044784 - Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same: A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are... Agent: Myers Bigel Sibley & Sajovec

20100044785 - High aspect ratio trench structures with void-free fill material: A field effect transistor (FET) includes a trench extending into a semiconductor region. A conductive electrode is disposed in the trench, and the conductive electrode is insulated from the semiconductor region by a dielectric layer. The conductive electrode includes a conductive liner lining the dielectric layer along opposite sidewalls of... Agent: Townsend And Townsend And Crew, LLP

20100044786 - Semiconductor device: A semiconductor device includes: a semiconductor layer of a first conductivity type; a base region of a second conductivity type formed on a surface of the semiconductor layer of the first conductivity type; a plurality of first column regions of the second conductivity type formed in a matrix fashion in... Agent: Young & Thompson

20100044787 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device includes the following processes. A first gate trench is formed if a semiconductor substrate region. Then a first insulating film is formed to cover bottom and side surfaces of the first gate trench. Then, the first insulating film is removed to cover the... Agent: Young & Thompson

20100044788 - Semiconductor device with a charge carrier compensation structure and process: A semiconductor device with a charge carrier compensation structure. In one embodiment, the semiconductor device has a central cell field with a gate and source structure. At least one bond contact area is electrically coupled to the gate structure or the source structure. A capacitance-increasing field plate is electrically coupled... Agent: Dicke, Billig & Czaja

20100044789 - Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same: An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped... Agent: Slater & Matsil, L.L.P.

20100044790 - Semiconductor device and method of etc.: Provided is a semiconductor device which includes a metal oxide semiconductor (MOS) transistor having high driving performance and high withstanding voltage with a thick gate oxide film. In the local oxidation-of-silicon (LOCOS) offset MOS transistor having high withstanding voltage, in order to prevent a gate oxide film (6) formed on... Agent: Bruce L. Adams, Esq Adams & Wilks

20100044792 - Charged balanced devices with shielded gate trench: This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of... Agent: Bo-in Lin

20100044791 - Configurations and methods for manufacturing charge balanced devices: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the... Agent: Bo-in Lin

20100044793 - Semiconductor device having a plurality of misfets formed on a main surface of a semiconductor substrate: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings... Agent: Mattingly & Malur, P.C.

20100044794 - Asymmetric multi-gated transistor and method for forming: In one embodiment, there is an asymmetric multi-gated transistor that has a semiconductor fin with a non-uniform doping profile. A first portion of the fin has a higher doping concentration while a second portion of the fin has a lower doping concentration. In another embodiment, there is an asymmetric multi-gated... Agent: Hoffman Warnick LLC

20100044795 - Logic switch and circuits utilizing the switch: A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic... Agent: Slater & Matsil, L.L.P.

20100044796 - Depletion mode trench mosfet for improved efficiency of dc/dc converter applications: A DC-to-DC converter includes a high-side transistor and a low-side transistor wherein the high-side transistor is implemented with a high-side enhancement mode MOSFET. The low side-transistor further includes a low-side enhancement MOSFET shunted with a depletion mode transistor having a gate shorted to a source of the low-side enhancement mode... Agent: Bo-in Lin

20100044797 - Semiconductor device and method of fabricating the same: A semiconductor device with reduced contact resistance between a substrate and a plug includes a gate electrode disposed over the substrate, the plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope, a capping layer disposed between the gate electrode... Agent: Lowe Hauptman Ham & Berner, LLP

20100044799 - Method for manufacturing a p-type mos transistor, method for manufacturing a cmos-type semiconductor apparatus having the p-type mos transistor, and cmos-type semiconductor apparatus manufactured using the manufacturing method: A method for manufacturing a P-type MOS transistor includes forming a gate insulating film on the substrate, forming a gate electrode from amorphous silicon containing no impurities on the gate insulating film, performing a heat treatment for controlling the film characteristics of the amorphous silicon, depositing a nickel (Ni) layer... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20100044798 - Transistor device and a method of manufacturing the same: A transistor device is provided that includes a substrate, a first channel region formed in a first portion of the substrate and being doped with a dopant of a first type of conductivity, a second channel region formed in a second portion of the substrate and being doped with a... Agent: Haynes And Boone, LLPIPSection

20100044800 - High-k dielectric metal gate device structure: A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is... Agent: Duane Morris LLP (tsmc)IPDepartment

20100044801 - Dual metal gate corner: In view of the foregoing, disclosed herein are embodiments of an improved field effect transistor (FET) structure and a method of forming the structure. The FET structure embodiments each incorporate a unique gate structure. Specifically, this gate structure has a first section above a center portion of the FET channel... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20100044802 - Semiconductor device and manufacturing method thereof: Provided are a semiconductor device making it possible to form an element region having a dimension close to a designed dimension, restrain a phenomenon similar to gate-induced drain leakage, and further restrain compressive stress to be applied to the element region by oxidation of a conductive film; and a method... Agent: Mcdermott Will & Emery LLP

20100044803 - Sealing structure for high-k metal gate and method of making: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and... Agent: Haynes And Boone, LLPIPSection

20100044805 - Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks: A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the... Agent: Scully, Scott, Murphy & Presser, P.C.

20100044804 - Novel high-k metal gate structure and method of making: The present disclosure provides a semiconductor device that includes a semiconductor substrate, a transistor formed in the substrate, the transistor including a high-k gate dielectric formed over the substrate, the high-k gate dielectric having a first length measured from one sidewall to the other sidewall of the high-k gate dielectric,... Agent: Haynes And Boone, LLPIPSection

20100044806 - Integrated circuit metal gate structure and method of fabrication: A method of forming a gate structure is provided. The method includes providing a metal layer in the gate structure, the metal layer includes an oxygen-gettering composition. The metal layer getters oxygen from the interface layer, which may decrease the thickness of the interface layer. The gettered oxygen converts the... Agent: Haynes And Boone, LLPIPSection

20100044807 - Cmos-compatible microstructures and methods of fabrication: The present invention addresses the aims and issues of making multi layer microstructures including “metal-shell-oxide-core” structures and “oxide-shell-metal-core” structures, and mechanically constrained structures and the constraining structures using CMOS (complimentary metal-oxide-semiconductor transistors) materials and layers processed during the standard CMOS process and later released into constrained and constraining structures by... Agent: Venable LLP

20100044808 - method of manufacturing a mems element: The device (100) comprises a substrate (10) of a semiconductor material with a first and an opposite second surface (1,2) and a microelectromechanical (MEMS) element (50) which is provided with a fixed and a movable electrode (52, 51) that is present in a cavity (30). One of the electrodes (51,52)... Agent: Philips Intellectual Property & Standards

20100044811 - Integrated circuit encapsulation and method therefor: A device (12) may have a pressure sensitive portion (17) which is protected from corrosion by a pressure transmitting material (20). Pressure transmitting material (20) may also be used to transmit pressure to pressure sensitive portion (17). A masking material (22) may be used to define an opening (26) in... Agent: Freescale Semiconductor, Inc. Law Department

20100044810 - Semiconductor structural element: The semiconductor component is intended for a sensor, in particular for a pressure sensor or differential pressure sensor, and includes a semiconductor substrate (1) in or on which electronic components (3) are formed and connected. The semiconductor substrate (1) is provided with an electrically insulated layer, and a metal-containing amorphous... Agent: Panitch Schwarze Belisario & Nadel LLP

20100044809 - Sensor device packaging and method: A sensor device and a method of forming comprises a die pad receives a sensor device, such as a MEMS device. The MEMS device has a first coefficient of thermal expansion (CTE). The die pad is made of a material having a second CTE compliant with the first CTE. The... Agent: Nixon Peabody LLP

20100044812 - Stratified photodiode for high resolution cmos image sensor implemented with sti technology: A stratified photodiode for high resolution CMOS image sensors implemented with STI technology is provided. The photodiode includes a semi-conductive layer of a first conductivity type, multiple doping regions of a second conductivity type, multiple doping regions of the first conductivity type, and a pinning layer. The multiple doping regions... Agent: Mcandrews Held & Malloy, Ltd

20100044814 - Camera module and manufacturing method thereof: A camera module includes an image sensor chip module and a lens module. The image sensor chip module includes a base, an image sensor chip disposed on the base and electrically connected with the base, and a frame disposed on the base and surrounding the image sensor chip therein. The... Agent: Wpat, PC Intellectual Property Attorneys

20100044820 - Cmos image sensor and method of fabricating the same: A CMOS image sensor is disclosed. The image sensor includes a plurality of polysilicon patterns provided on a silicon epitaxial layer which correspond to the location of a plurality of photodiodes provided in a dummy pixel area, a silicide layer of metal with a high melting point provided on the... Agent: Workman Nydegger 1000 Eagle Gate Tower

20100044815 - Cmos image sensor package and camera module using same: An image sensor package includes a cover glass, a color filter layer, an image sensor chip, and a reflecting layer. The cover glass includes a first surface and a second surface at opposite sides thereof. The color filter layer is formed on the first surface of the cover glass. The... Agent: PCe Industry, Inc. Att. Steven Reiss

20100044819 - Method for manufacturing cmos image sensor having microlens therein with high photosensitivity: The method for manufacturing a CMOS image sensor is employed to prevent bridge phenomenon between adjacent microlenses by employing openings between the microlenses. The method includes the steps of: preparing a semiconductor substrate including isolation regions and photodiodes therein obtained by a predetermined process; forming an interlayer dielectric (ILD), metal... Agent: Mcandrews Held & Malloy, Ltd

20100044813 - Optically controlled read only memory: An optically controlled read only memory is disclosed. The optically controlled read only memory includes a substrate, a plurality of memory cells having optical sensors disposed on the substrate, and at least one shielding structure disposed on the optical sensor, in which the shielding structure selectively shields a portion of... Agent: North America Intellectual Property Corporation

20100044817 - Photosensitive resin composition, color filter and method of producing the same, and solid-state imaging device: A photosensitive resin composition is provided which provides a high resolution even when a pattern is formed using a low exposure intensity (in particular, less than 200 mJ/cm2) and may inhibit deterioration in pattern rectangularity during a post baking process of a post treatment. The photosensitive resin composition includes: a... Agent: Solaris Intellectual Property Group, PLLC

20100044816 - Semiconductor device and electronic apparatus using the same: A semiconductor device includes: a semiconductor substrate having an imaging region in which a plurality of photoreceptors are arranged, and a peripheral circuit region arranged around the imaging region; a plurality of microlenses formed on the imaging region; a low-refractive-index film formed on the semiconductor substrate to cover the plurality... Agent: Mcdermott Will & Emery LLP

20100044818 - Semiconductor light-receiving device: Disclosed is light-receiving device (1) comprising semiconductor substrate (101), a light-receiving layer arranged on semiconductor substrate (101), and filter layer (103) arranged between semiconductor substrate (101) and the light-receiving layer to absorb light other than reception light. First mesa (11) serving as the light-receiving layer is surrounded by third mesa... Agent: Mr. Jackson Chen

20100044821 - Semiconductor device and manufacturing method thereof: This invention offers a semiconductor device to measure a luminance for the visible wavelength range of light components and its manufacturing method which reduce its manufacturing cost. A first light-receiving element and a second light-receiving element are formed in a semiconductor substrate. Then, there is formed an arithmetic circuit that... Agent: Morrison & Foerster LLP

20100044822 - Luminous radiation colour photosensitive structure: There is described a structure which is photosensitive to the colour of a light radiation; said structure being formed by a semiconductor substrate having a first type of conductivity and the substrate is adapted to generate a different distribution of carriers upon incidence of a light radiation as the depth... Agent: Husch Blackwell Sanders, LLP Husch Blackwell Sanders LLP Welsh & Katz

20100044823 - Semiconductor photonic devices with enhanced responsivity and reduced stray light: In accordance with the invention, a photonic device comprises a semiconductor substrate including at least one circuit component comprising a metal silicide layer and an overlying layer including at least one photoresponsive component. The metal silicide layer is disposed between the circuit component and the photoresponsive component to prevent entry... Agent: Wolf Greenfield & Sacks, P.C.

20100044824 - Stratified photodiode for high resolution cmos image sensor implemented with sti technology: A stratified photodiode for high resolution CMOS image sensors implemented with STI technology is provided. The photodiode includes a semi-conductive layer of a first conductivity type, multiple doping regions of a second conductivity type, multiple doping regions of the first conductivity type, and a pinning layer. The multiple doping regions... Agent: Mcandrews Held & Malloy, Ltd

20100044825 - Semiconductor device and method for the production of a semiconductor device: In a semiconductor body, a semiconductor device has an active region with a vertical drift section of a first conduction type and a near-surface lateral well of a second, complementary conduction type. An edge region surrounding this active region comprises a variably laterally doped doping material zone (VLD zone). This... Agent: Dicke, Billig & Czaja

20100044826 - 3d integrated circuit device fabrication with precisely controllable substrate removal: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.

20100044827 - Method for making a substrate structure comprising a film and substrate structure made by same method: A method for manufacturing a substrate structure comprising a film and a substrate structure made by this method are disclosed. The method for manufacturing a substrate structure comprising a film includes the steps of: providing a target substrate; providing an initial substrate; forming an embrittlement-layer on the initial substrate; forming... Agent: Juan Carlos A. Marquez C/o Stites & Harbison PLLC

20100044829 - Method for producing soi substrate and soi substrate: The present invention is a method for producing an SOI substrate including the steps of: preparing a bond wafer and a base wafer which are composed of single crystal silicon wafers; forming an oxide film on a surface of at least one of the bond wafer and the base wafer... Agent: Oliff & Berridge, PLC

20100044830 - Method of producing an soi structure with an insulating layer of controlled thickness: The invention relates to semiconductor-on-insulator structure and its method of manufacture. This structure includes a substrate, a thin, useful surface layer and an insulating layer positioned between the substrate and surface layer. The insulating layer is at least one dielectric layer of a high k material having a permittivity that... Agent: Winston & Strawn LLP Patent Department

20100044828 - Monolithic integrated composite device having silicon integrated circuit and silicon optical device integrated thereon, and fabrication method thereof: Provided is a monolithic integrated composite device including: a silicon substrate which is partitioned into a silicon integrated circuit forming region and a silicon optical device forming region; a buried oxide layer which is formed locally in the silicon substrate of the silicon optical device forming region and isolates unit... Agent: Ampacc Law Group

20100044831 - Multi-layer film capacitor with tapered film sidewalls: A multi-layer capacitor of staggered construction is formed of one or more layers having tapered sidewall(s). The edge(s) of the capacitor film(s) can be etched to have a gentle slope, which can improve adhesion of the overlying layers and provide more uniform film thickness. The multi-layer capacitor can be used... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20100044832 - Structure of trench capacitor and method for manufacturing the same: A structure of trench capacitor and method for manufacturing the trench capacitor is provided. The collar oxide layer of the trench capacitor is formed by a thermal oxidation process. Moreover, a protective layer such as silicon nitride covers the collar oxide layer. A failure analysis of the collar oxide layer... Agent: North America Intellectual Property Corporation

20100044833 - Integrated capacitor: According to the preferred embodiment, an integrated capacitor having a comb-meander structure is provided. The integrated capacitor comprises a first comb-shaped metal pattern; a second comb-shaped metal pattern interdigitating with the first comb-shaped metal pattern; and a meandering metal pattern traversing a spacing between the first and second comb-shaped metal... Agent: North America Intellectual Property Corporation

20100044834 - Electrostatic discharge protection circuit: An electrostatic discharge (ESD) protection circuit includes a substrate, and a plurality of unit bipolar transistors formed in the substrate. Each of the plurality of unit bipolar transistors may include a first-conductivity-type buried layer formed in the substrate, a first-conductivity-type well formed over the first-conductivity-type buried layer, a second-conductivity-type well... Agent: Sherr & Vaughn, PLLC

20100044835 - Setting the dc operating current of a rail-to-rail output stage of an op-amp: In an output stage of an operational amplifier, first and second transistors each provide a collector current under quiescent conditions to first and second current sources. A resistor receives a portion of one the collector currents and produces a resistor voltage in response. An output transistor provides a quiescent current... Agent: Kenyon & Kenyon LLP

20100044836 - Process for producing localised ge0i structures, obtained by germanium condensation: The invention relates to a process for making at least one GeOI structure by germanium condensation of a SiGe layer supported by a layer of silicon oxide. The layer of silicon oxide is doped with germanium, the concentration of germanium in the layer of silicon oxide being such that it... Agent: Pearne & Gordon LLP

20100044837 - Replication and transfer of microstructures and nanostructures: A method for the duplication of microscopic patterns from a master to a substrate is disclosed, in which a replica of a topographic structure on a master is formed and transferred when needed onto a receiving substrate using one of a variety of printing or imprint techniques, and then dissolved.... Agent: Attn: Robert J. Crawford Crawford Maunu PLLC

20100044838 - Semiconductor component with marginal region: A semiconductor component having a semiconductor body includes an active region and a marginal region surrounding the active region. The marginal region extends from the active region as far as an edge of the semiconductor body. A zone composed of porous material is formed in the marginal region.... Agent: Dicke, Billig & Czaja

20100044839 - Semiconductor device and manufacturing method thereof: Provided are a semiconductor device and a method of manufacturing the same. In semiconductor devices of the conventional technologies, the chip size is increased when a breakdown voltage is increased. In the semiconductor device of this invention, an end of a pn junction interface (5) of a collector region (2)... Agent: Morrison & Foerster LLP

20100044840 - Shielded multi-layer package structures: Embodiments include shielded multi-layer packages for use with multi-chip modules and the like. A substrate (102) (e.g., chip carrier) has an adhesive layer (104), where electronic components (106, 108) are attached. An insulating layer (110) is formed over the plurality of electronic components, and a conductive encapsulant structure (115) is... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20100044841 - Semiconductor device: A semiconductor device includes a carrier, a chip attached to the carrier, a sealant vapor deposited over the chip and the carrier, and encapsulation material deposited over the sealed chip and the sealed carrier.... Agent: Dicke, Billig & Czaja

20100044843 - Advanced quad flat non-leaded package structure and manufacturing method thereof: The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The leads include first leads disposed around the die pad, second leads disposed around the first leads and at... Agent: J C Patents

20100044844 - Lead frame, resin package, semiconductor device and resin package manufacturing method: A pressure loss section H1 (H2) extends from a position corresponding to a corner of a resin package, and S1 is the minimum value of the opening area of the pressure loss section H1 (H2) perpendicular to the direction of resin flow (X axis) in the pressure loss section H1... Agent: Sughrue Mion, PLLC

20100044842 - Semiconductor device: A semiconductor device includes a carrier, a chip coupled to the carrier, a dielectric layer coupled to the carrier and the chip, and conducting elements connected to both the carrier and contacts of the chip. The chip includes a first face with a first contact spaced apart from a second... Agent: Dicke, Billig & Czaja

20100044845 - Circuit substrate, an electronic device arrangement and a manufacturing process for the circuit substrate: a via 6 connecting the electrode terminal 5 with the conductive wiring 3 formed on the base member, wherein the conductive wiring formed on either one of the front side face and the rear side face of the base member is arranged such that a surface exposed outside from the... Agent: Sughrue Mion, PLLC

20100044847 - Semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack, a semiconductor device package and an electronic apparatus including the semiconductor chip: A semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack thereof, a semiconductor device package thereof, and an electronic apparatus having the same are disclosed. The semiconductor chip comprising, a substrate including an inner semiconductor circuit, a conductive redistribution structure formed on the substrate including a... Agent: Stanzione & Kim, LLP

20100044848 - Solder joint reliability in microelectronic packaging: A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20100044849 - Stacked integrated circuit package-in-package system and method of manufacture thereof: A method of manufacture of a stacked integrated circuit package-in-package system includes forming a substrate with a top contact, mounting a first device having a first terminal over the substrate, stacking a second device having a second terminal over the first device in an offset configuration, connecting the first terminal... Agent: Law Offices Of Mikio Ishimaru

20100044846 - Three-dimensional structural semiconductor device: A semiconductor device of three-dimensional structure in which the operating frequency of a chip can be raised while preventing the chip area from increasing. The three-dimensional structure semiconductor device have a first integrated circuit including a plurality of areas formed on a first conductor layer and a first wiring layer... Agent: Foley And Lardner LLP Suite 500

20100044850 - Advanced quad flat non-leaded package structure and manufacturing method thereof: An advanced quad flat non-leaded package structure includes a carrier, a chip and a molding compound. The carrier includes a die pad and a plurality of leads. The die pad has a central portion, a peripheral portion disposed around the central portion and a plurality of connecting portions connecting the... Agent: J C Patents

20100044851 - Flip chip packages: Flip chip packages and methods of manufacturing the same are provided, the flip chip packages may include a package substrate, a semiconductor chip, conductive bumps, a ground pattern and an underfilling layer. The semiconductor chip may be over the package substrate. The conductive bumps may be between the semiconductor chip... Agent: Harness, Dickey & Pierce, P.L.C

20100044852 - Vertical stack type multi-chip package having improved grounding performance and lower semiconductor chip reliability: A vertical stack type multi-chip package is provided having improved reliability by increasing the grounding performance and preventing the decrease in reliability of the multi-chip package from moisture penetration into a lower semiconductor chip. The vertical stack type multi-chip package comprises an organic substrate having a printed circuit pattern on... Agent: Volentine & Whitt PLLC

20100044853 - System-in-package with through substrate via holes: The present invention relates to a system-in-package that comprises an integration substrate with a thickness of less than 100 micrometer and a plurality of through-substrate vias, which have an aspect ratio larger than 5. A first chip is attached to the integration substrate and arranged between the integration substrate and... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100044854 - Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device: A semiconductor device is disclosed which includes a tab (5) for use in supporting a semiconductor chip (8), a seal section (12) as formed by sealing the semiconductor chip (8) with a resin material, more than one tab suspension lead (4) for support of the tab (5), a plurality of... Agent: Mattingly & Malur, P.C.

20100044855 - Integrated thermal structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and... Agent: Heslin Rothenberg Farley & Mesiti PC

20100044856 - Electronic package with a thermal interposer and method of manufacturing the same: An electronic package includes a die including a thermal interface material through which a primary heat flux path is enabled for conducting heat from the die, an organic substrate, and a thermal interposer provided between the organic substrate and the die, the thermal interposer having an area extending beyond a... Agent: Mcginn Intellectual Property Law Group, PLLC

20100044857 - Wlcsp target and method for forming the same: The invention provides a Wafer Level Chip Size Packaging (WLCSP) target and a method for forming it. A WLCSP target is formed by recombining single chips, wafer parts each including two or more chips or half finished packaging targets which have been subjected to at least one previous step of... Agent: Wolf Greenfield & Sacks, P.C.

20100044858 - Product chips and die with a feature pattern that contains information relating to the product chip, methods for fabricating such product chips and die, and methods for reading a feature pattern from a packaged die: Product chips and die, methods for fabricating product chips, and methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20100044860 - Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer: An interconnection element can include a substrate, e.g., a connection substrate, element of a package, circuit panel or microelectronic substrate, e.g., semiconductor chip, the substrate having a plurality of metal conductive elements such as conductive pads, contacts, bond pads, traces, or the like exposed at the surface. A plurality of... Agent: Tessera Lerner David Et Al.

20100044859 - Semiconductor device and method of fabricating semiconductor device: There is provided a semiconductor device including a semiconductor substrate on which at least one electrode pad is formed, a rewiring layer connected to the electrode pad, and an encapsulation part which encapsulates the semiconductor substrate, the electrode pad being formed of a first region including a connection part connected... Agent: Rabin & Berdo, PC

20100044862 - Method of forming collapse chip connection bumps on a semiconductor substrate: A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on... Agent: Intel Corporation C/o Cpa Global

20100044863 - Semiconductor device: An inventive semiconductor device includes: a semiconductor chip; an internal pad provided on a surface of the semiconductor chip for electrical connection; a surface protective film covering the surface of the semiconductor chip and having a pad opening from which the internal pad is exposed; a stress relief layer provided... Agent: Rabin & Berdo, PC

20100044861 - Semiconductor die support in an offset die stack: A semiconductor device is disclosed including a support structure for supporting an edge of a semiconductor die that is not supported on the substrate or semiconductor die below. In embodiments, the semiconductor device may in general include a substrate having a plurality of contact pads, a first semiconductor die mounted... Agent: Vierra Magen/sandisk Corporation

20100044865 - Fabrication of a diffusion barrier cap on copper containing conductive elements: A method for fabricating a self-aligned diffusion-barrier cap on a Cu-containing conductive element in an integrated-circuit device comprises:—providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface;—depositing a metal layer on the exposed surface of conductive element;—inducing diffusion of metal from... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100044864 - Method of manufacturing semiconductor device, and semiconductor device: In the present invention, a copper seed film containing copper and a first metal element is formed in a groove formed in a first interlayer film over a semiconductor substrate. After that, a copper plating treatment is performed. After that, a first heat treatment is performed in a first atmosphere... Agent: Mcdermott Will & Emery LLP

20100044867 - Methods of post-contact back end of line through-hole via integration: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.... Agent: Larry Williams

20100044866 - Semiconductor device having via connecting between interconnects: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect... Agent: Mcdermott Will & Emery LLP

20100044868 - Semiconductor device: A semiconductor device includes an external terminal, a plurality of first interconnections, an electrode, a conductor, and a second interconnection. The first interconnections are positioned below the external terminal. The electrode is positioned at the same level as the first interconnections and is electrically connected to the external terminal through... Agent: Mcdermott Will & Emery LLP

20100044870 - Electrode connection structure of semiconductor chip, conductive member, and semiconductor device and method for manufacturing the same: An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing... Agent: Wolf Greenfield & Sacks, P.C.

20100044874 - Integrated circuit of decreased size: An integrated circuit including an insulating layer having first and second opposite surfaces. The circuit includes, in a first area, first conductive portions of a first conductive material, located in the insulating layer, flush with the first surface and continued by first vias of the first conductive material, of smaller... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20100044875 - Methods and apparatus for defining manhattan power grid structures having a reduced number of vias: A method for defining and producing a power grid structure (having stripe, rail, and via components) of an IC. The method reduces the number of vias in the power grid structure and the diagonal wiring blockage caused by the vias while still meeting design specifications. Other embodiments provide a method... Agent: Adeli & Tollen, LLP

20100044869 - Reliable interconnects: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric... Agent: HorizonIPPte Ltd

20100044873 - Semiconductor device and method of manufacturing the same: When a thin semiconductor device is formed by grinding a wafer, it has been necessary to dice the wafer into dies and process the back surfaces of the dies separately. In the invention, a wafer 2a is half-diced from the front surface thereof to form groove portions 4 therein, and... Agent: Morrison & Foerster LLP

20100044871 - Semiconductor device, display device, and electronic device: In order to attain, in a semiconductor device in which a semiconductor element is mounted, formation of a mark of a relatively large size which is easily recognizable by the naked eye or a machine, and which can apply a code system containing enough amount of information for tracing a... Agent: Harness, Dickey & Pierce, P.L.C

20100044872 - Semiconductor memory device having pads: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of... Agent: Ladas & Parry LLP

20100044876 - Conductive structures for microfeature devices and methods for fabricating microfeature devices: Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method for fabricating interposer devices having substrates includes forming a plurality of conductive sections on a first substrate in a first pattern. The method... Agent: Perkins Coie LLP Patent-sea

20100044877 - Electronic device having a chip stack: An electronic device provides a stack of semiconductor chips. A redistribution layer of a first semiconductor chip is arranged at the bottom of the stack. The redistribution layer of the first semiconductor chip comprises external pads.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20100044878 - Integrated circuit package system having cavity: An integrated circuit package system includes providing a carrier having a first side and a second side; mounting an integrated circuit over the carrier with the first side facing the integrated circuit; attaching an external interconnect to the second side; and forming an encapsulation over the integrated circuit and around... Agent: Law Offices Of Mikio Ishimaru

20100044879 - Layered chip package and method of manufacturing same: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. The plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second type.... Agent: Oliff & Berridge, PLC

20100044881 - Semiconductor device and fabrication method thereof: A semiconductor device includes: a first semiconductor element; a second semiconductor element mounted on an upper surface of the first semiconductor element via an adhesive layer; a mold resin body for overmolding the first semiconductor element and the second semiconductor element; and a first spherical filler having a diameter smaller... Agent: Mcdermott Will & Emery LLP

20100044880 - Semiconductor device and semiconductor module: A semiconductor device includes a multilayer wiring substrate having a plurality of inner wiring layers and a semiconductor chip mounted on the multilayer wiring substrate. The multilayer wiring substrate has a groove formed in the bottom surface. The groove does not reach the lowermost of the inner wiring layers.... Agent: Mcdermott Will & Emery LLP

20100044882 - Integrated circuit package system flip chip: An integrated circuit package system includes: providing a substrate having a top side with a trace conductor connected to a bottom side with a system interconnect; forming a bump ring on the substrate, the bump ring having an inner cavity area over the trace conductor and an outer bump area;... Agent: Law Offices Of Mikio Ishimaru

20100044883 - Plastic semiconductor package having improved control of dimensions: A device with a semiconductor chip assembled on a planar substrate and encapsulation compound surrounding the assembled chip and a portion of the substrate near the chip; the compound has a planar top area. The encapsulation compound has a plurality of side areas reaching from the substrate to the top... Agent: Texas Instruments Incorporated

20100044884 - Integrated circuit package employing predetermined three-dimensional solder pad surface and method for making same: An integrated circuit package employs a solder pad that includes a predetermined three dimensional surface that is adapted to receive solder. In one example, the predetermined three dimensional surface includes at least one predetermined hill or protruding portion and a valley portion, such as a lower portion, having a predetermined... Agent: Advanced Micro Devices, Inc. C/o Vedder Price P.C.

20100044885 - Semiconductor device and manufacturing method: A semiconductor device and manufacturing method. One embodiment provides at least two semiconductor chips. A dielectric material is applied to the at least two semiconductor chips to attach the at least two semiconductor chips to each other. A portion of the dielectric material is selectively removed between the at least... Agent: Dicke, Billig & Czaja

20100044886 - Semiconductor device having pairs of pads: An integrated-circuit semiconductor device includes external electrical connection pads on one face and electrical connection vias under said pads. The electrical connection vias are arranged with a defined pitch in a defined direction. Each via is respectively associated with one of a plurality of adjacent zones of the face. These... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20100044887 - Method for producing circuit substrate, and circuit substrate: The method for producing a circuit substrate of the present invention is characterized in that the circuit substrate is produced using as sheet a circuit substrate sheet including an uncured layer a part of which, the part being other than a part at which a circuit chip is disposed, is... Agent: Sughrue Mion, PLLC

20100044888 - Bis(aminophenol) derivative, process for producing same, polyamide resin, positive photosensitive resin composition, protective film, interlayer dielectric film, semiconductor device, and display element: A bis(aminophenol) derivative having substituents at positions adjacent to two amino groups is provided. The bis(aminophenol) derivative is used as a raw material of a polyamide resin for a positive-tone photosensitive resin composition. A polyamide resin comprising bis(aminophenol) and a structure derived from a carboxylic acid is also provided, the... Agent: Ditthavong Mori & Steiner, P.C.

20100044889 - electrical component and film composite laminated on the component and method for production: At least one film composite is laminated on a surface of at least one electrical component. The film composite includes at least one electrically-conducting plastic film with at least one electrically conducting conductor. The electrically-conducting plastic film has a high-ohmic resistance. This method may be used in planar large-surface electrical... Agent: Staas & Halsey LLP

20100044890 - Semiconductor substrate manufacture apparatus, semiconductor substrate manufacture method, and semiconductor substrate: [Solving Means] A semiconductor substrate manufacture apparatus includes: a tracking device (33) having a light-emitting portion (34) which applies light to a substrate surface during tracking, a light-receiving portion (35) which receives the light applied by the light-emitting portion (34) and reflected by the substrate surface, and a position detecting... Agent: Wenderoth, Lind & Ponack, L.L.P.

20100038614 - Methods of forming a phase change material, a phase change material, a phase change random access memory device including the phase change material, and a semiconductor structure including the phase change material: Methods of forming a phase change material are disclosed. The method includes forming a chalcogenide compound on a substrate and simultaneously applying a bias voltage to the substrate to alter the stoichiometry of the chalcogenide compound. In another embodiment, the method includes positioning a substrate and a deposition target having... Agent: Trask Britt, P.C./ Micron Technology

20100038616 - Nonvolatile semiconductor memory device and producing method thereof: A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100038615 - Nonvolatile storage device: An element structure for a resistance variable type nonvolatile storage device is provided in which enables a reduction in variation in operating voltage and in a leakage current in an off state of an element. The nonvolatile storage device is characterized by including a lower electrode, an upper electrode, and... Agent: Mr. Jackson Chen

20100038618 - Semiconductor device and manufacturing method thereof: The invention provides a novel memory for which process technology is relatively simple and which can store multivalued information by a small number of elements. A part of a shape of the first electrode in the first storage element is made different from a shape of the first electrode in... Agent: Eric Robinson

20100038617 - Semiconductor memory device: A semiconductor memory device having a first wiring layer which is provided on a first insulator, and which extends in a first direction, and a non-volatile memory cell which is provided in a pillar shape on the first wiring layer, and which includes a non-ohmic element and variable resistance element... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100038621 - Four-terminal reconfigurable devices: Reconfigurable devices and methods for the fabrication thereof are provided. In one aspect, a reconfigurable device is provided. The reconfigurable device comprises a substrate; a first dielectric layer on the substrate; a conductive layer recessed into at least a portion of a side of the first dielectric layer opposite the... Agent: Michael J. Chang, LLC

20100038620 - Integration methods for carbon films in two- and three-dimensional memories and memories formed therefrom: Methods of forming memory cells are disclosed which include forming a pillar above a substrate, the pillar including a steering element and a memory element, and performing one or more etches vertically through the pillar to form multiple memory cells. Memory cells formed from such methods, as well as numerous... Agent: Dugan & Dugan, PC

20100038619 - Variable resistance element, manufacturing method thereof, and electronic device: A variable resistance element includes a first conductive portion; an insulating film pattern provided on the first conductive portion; a level difference with respect to the upper surface of the first conductive portion, the level difference being formed of the insulating film pattern; a variable resistance film provided on a... Agent: Mr. Jackson Chen

20100038622 - Connectible nanotube circuit: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.... Agent: Iv - Suiter Swantz PC Llo

20100038624 - Memory device having highly integrated cell structure and method of its fabrication: In an embodiment, a memory device, with a highly integrated cell structure, includes a mold insulating layer disposed on a semiconductor substrate. At least one conductive line is disposed on the mold insulating layer. Data storage elements self-aligned with the conductive line are interposed between the conductive line and the... Agent: Volentine & Whitt PLLC

20100038623 - Methods and apparatus for increasing memory density using diode layer sharing: Methods of forming memory cells are disclosed which include forming a pillar above a substrate, the pillar including a steering element and a memory element, and performing one or more etches vertically through the memory element, but not the steering element, to form multiple memory cells that share a single... Agent: Dugan & Dugan, PC

20100038625 - Nonvolatile nanotube programmable logic devices and a nonvolatile nanotube field programmable gate array using same: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.... Agent: Wilmerhale/boston

20100038626 - Semiconductor nanoparticle aggregate, method for producing the same, and biological substance labeling agent utilizing the same: This invention provides a semiconductor nanoparticle aggregate comprising three or more types of semiconductor nanoparticles, which are different from each other in diameter, have a narrow particle size distribution, and are different from each other in maximum luminous wavelength of an emission spectrum in a wavelength region of 380 nm... Agent: Lucas & Mercanti, LLP

20100038628 - Chemical doping of nano-components: A method is provided for doping nano-components, including nanotubes, nanocrystals and nanowires, by exposing the nano-components to an organic amine-containing dopant. A method is also provided for forming a field effect transistor comprising a nano-component that has been doped using such a dopant.... Agent: Connolly Bove Lodge & Hutz LLP

20100038627 - Method for fabricating carbon nanotube transistors on a silicon or soi substrate: A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically defined single crystal silicon seed layer is converted to a single crystal silicon carbide seed layer. A single layer of graphene is formed on the top surface... Agent: Texas Instruments Incorporated

20100038629 - Anisotropic semiconductor film and method of production thereof: The present invention relates generally to the field of macro- and microelectronics with the potential for large-scale integration, optics, communications, and computer technology and particularly to the materials for these and other related fields. The present invention provides an anisotropic semiconductor film on a substrate, comprising at least one solid... Agent: Houst Consulting

20100038632 - Electroluminescent device: An OLED with a donor which is doped metal quinolate in which the metal is a transition metal in the four or five valent state.... Agent: David Silverstein AndoverIPLaw

20100038631 - Electronic device comprising semiconducting polymers:

20100038634 - Light emitting device material and light emitting device: A light emitting device material comprises a pyrene compound represented by formula (1) below. Also disclosed is a light emitting device using such a material. (R1 to R17 may be the same or different and are each selected from the group consisting of hydrogen, an alkyl group, a cycloalkyl group,... Agent: Ratnerprestia

20100038635 - Organic electroluminescent display device and manufacturing method of organic electroluminescent display device: The present invention provides a top-emission-type organic EL display device. In a top-emission-type organic EL display device which includes organic EL elements each of which is formed by stacking a reflective lower electrode, a function layer and a light-transmissive upper electrode in order, the upper electrode contains a plurality of... Agent: Stanley P. Fisher Reed Smith LLP

20100038633 - Organic light emitting diode: Provided is an organic light emitting diode including: a first electrode; a second electrode; an organic layer between the first electrode and the second electrode; and a luminous efficiency improvement layer disposed on a surface of the first electrode facing away from the organic layer or a surface of the... Agent: Robert E. Bushnell & Law Firm

20100038636 - Organic thin film transistor and method of manufacturing the same, and semiconductor device having the organic thin film transistor: There have been problems in that a dedicated apparatus is needed for a conventional method of manufacturing an organic thin film transistor and in that: a little amount of an organic semiconductor film is formed with respect to a usage amount of a material; and most of the used material... Agent: Nixon Peabody, LLP

20100038630 - Semiconducting siloxane compositions for thin film transistor devices,and making and using the same: Semiconducting siloxane compositions and methods for manufacturing and use thereof in preparing organic thin-film transistors (OTFTs) are described. The semiconducting siloxane compositions can be crosslinked products of polymeric/monomeric compositions that include silane-derivatized crosslinkable organic p-type compounds and p-type semiconducting polymers.... Agent: K&l Gates LLP

20100038637 - Composite comprising array of needle-like crystal, method for producing the same, photovoltaic conversion element, light emitting element, and capacitor: A composite of a base and an array of needle-like crystals formed on the surface of the base is provided, in which the base side and the opposite side to the base with respect to the array can be isolated in a satisfactory manner. A composite 10 includes a transparent... Agent: Hogan & Hartson L.L.P.

20100038638 - N-type doping in metal oxides and metal chalcogenides by electrochemical methods: Methods and systems for electrochemically depositing doped metal oxide and metal chalcogenide films are disclosed. An example method includes dissolving a metal precursor into a solution, adding a halogen precursor to the solution, and applying a potential between a working electrode and a counter electrode of an electrochemical cell to... Agent: Chowdhury & Georgakis, P.c

20100038639 - Semiconductor device and manufacturing method thereof: To provide a semiconductor device in which a defect or fault is not generated and a manufacturing method thereof even if a ZnO semiconductor film is used and a ZnO film to which an n-type or p-type impurity is added is used for a source electrode and a drain electrode.... Agent: Nixon Peabody, LLP

20100038640 - Array substrate and method of manufacturing the same: According to an embodiment of the invention, an array substrate includes a first test line, a second test line, a first source line group, a second source line group, a plurality of gate lines and a switching device. The first test line extends along a first direction. The second test... Agent: Innovation Counsel LLP

20100038641 - Thin film field effect transistor: A thin film field effect transistor has at least a gate electrode 2, a gate insulating layer 3, an active layer 4, a source electrode 5-1 and a drain electrode 5-2 on a substrate 1. The active layer includes an amorphous oxide semiconductor including at least In and Zn, a... Agent: Solaris Intellectual Property Group, PLLC

20100038645 - Display element and method of manufacturing the same: A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100038646 - Method of manufacturing thin film transistor, thin film transistor, and display unit: A thin film transistor having a crystalline silicon film that is formed over an insulating substrate with a gate electrode and a gate insulating film in between, and has a channel region in a region corresponding to the gate electrode; an insulating channel protective film that is selectively formed in... Agent: Sonnenschein Nath & Rosenthal LLP

20100038643 - Organic light emitting display and manufacturing method of the same: Provided are an organic light emitting display device and a method for manufacturing the same. The organic light emitting display device comprises a transistor on a substrate, a cathode on the transistor and connected to a source or a drain of the transistor, a bank layer on the cathode and... Agent: Mckenna Long & Aldridge LLP

20100038642 - Thin film transistor array panel and method of manufacturing the same: A thin film transistor (TFT) array panel includes a substrate, a first signal line disposed on the substrate, a first insulating layer disposed on the first signal line, a second signal line disposed on the first insulating layer, a second insulating layer disposed on the second signal line, the second... Agent: F. Chau & Associates, LLC

20100038644 - Thin film transistor display panel and method of manufacturing the same: A thin film transistor display panel includes an insulating substrate, gate lines and data lines disposed intersecting each other on the insulating substrate so as to be electrically insulated from each other, common lines provided on the insulating substrate in parallel to the gate lines, a gate insulating film disposed... Agent: Cantor Colburn, LLP

20100038650 - Display device and method of manufacturing the same: A display device includes first and second substrates, and first and second alignment keys. The first and second substrates have first and second display regions and first and second peripheral regions, respectively. The first alignment key is disposed in the first peripheral region of the first substrate. The first alignment... Agent: Cantor Colburn, LLP

20100038649 - Mold, manufacturing method of mold, method for forming patterns using mold, and display substrate and display device manufactured by using method for forming patterns: The present invention relates to a mold, a manufacturing method of the mold, and a method of forming patterns using the mold. The mold may include a main body having a convex portion and a recess portion, and a polymer layer formed over the main body by processing a surface... Agent: H.c. Park & Associates, PLC

20100038651 - Semiconductor device including semiconductor circuit made from semiconductor element and manufacturing method thereof: In the present invention, a semiconductor film is formed through a sputtering method, and then, the semiconductor film is crystallized. After the crystallization, a patterning step is carried out to form an active layer with a desired shape. The present invention is also characterized by forming a semiconductor film through... Agent: Eric Robinson

20100038647 - Thin film transistor array panel and manufacturing method thereof: A thin film transistor substrate according to one or more embodiments of the present invention includes a gate line formed on a substrate, a data line that is insulated from and intersects the gate line, a thin film transistor connected to the gate line and the data line, a barrier... Agent: Haynes And Boone, LLPIPSection

20100038648 - Thin film transistor array panel and method of manufacturing the same: A thin film transistor array panel including a substrate; a display area signal line; a display area thin film transistor; a peripheral area signal line; a black matrix disposed on the display area signal line, the display area thin film transistor, and the peripheral area signal line, the black matrix... Agent: Cantor Colburn, LLP

20100038652 - Light emitting element and method of making same: A light emitting element has a substrate of gallium oxides and a pn-junction formed on the substrate. The substrate is of gallium oxides represented by: (AlxInyGa(1−X−Y))2O3 where 0≦x≦1, 0≦y≦1 and 0≦x+y≦1. The pn-junction has first conductivity type substrate, and GaN system compound semiconductor thin film of second conductivity type opposite... Agent: Scully Scott Murphy & Presser, PC

20100038653 - Diamond electronic devices and methods for their manufacture: The present invention relates to a diamond electronic device comprising a functional interface between two solid materials, wherein the interface is formed by a planar first surface of a first layer of single crystal diamond and a second layer formed on the first surface of the first diamond layer, the... Agent: Bryan Cave LLP

20100038654 - Photo sensor and portable electronic apparatus: A photo sensor including a gate, a first insulator, a semiconductor layer, a first electrode pattern layer, a second electrode pattern layer, a second insulator and a transparent electrode is provided. The gate is disposed on the substrate. The first insulator covers the gate and a portion of the substrate.... Agent: Jianq Chyun Intellectual Property Office

20100038657 - Lighting apparatus: A lighting apparatus is provided with a plurality of light-emitting devices, a substrate, a blind member, and a reflector. The reflector is formed with a plurality of reflective surfaces corresponding to the light-emitting devices, individually. The shielding angle at which light emitted from that one of the light-emitting devices which... Agent: Dla Piper LLP Us

20100038656 - Nitride leds based on thick templates: Thick HVPE templates of nitrides enhance both the growth conditions and resulting device performance of LEDs, power devices, solar cells, and other electrical elements. The use of HVPE templates greater than 15 microns allows for increased incorporation of indium and/or aluminum in alloys with gallium nitride relative to a thinner... Agent: Goldeneye, Inc. Suite 233

20100038655 - Reflective layer for light-emitting diodes: A system and method for manufacturing a light-generating device is described. A preferred embodiment comprises a plurality of LEDs formed on a substrate. Each LED preferably has spacers along the sidewalls of the LED, and a reflective surface is formed on the substrate between the LEDs. The reflective surface is... Agent: Slater & Matsil, L.L.P.

20100038670 - Illumination assembly including chip-scale packaged light-emitting device: The embodiments described herein are drawn generally towards illumination assemblies including light emitting devices. In some embodiments, the illumination assemblies including chip-scale packaged light-emitting devices and optical elements.... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.C.

20100038663 - Led light recycling for luminance enhancement and angular narrowing: Some embodiments provide a luminance-enhanced light source. These embodiments include a thin-film LED mounted on a substrate and with a defined upper surface approximately hemispherically emitting light, with the upper surface being diffusely transmissive, a lower first layer of identically defined linear prismatic film separated from the upper surface by... Agent: Sinsheimer Juhnke Lebens & Mcivor, LLP

20100038666 - Lens arrangement and led display device: A lens arrangement for an LED display device includes a lens. The lens has a first lens surface and an optical axis. The optical axis penetrates the first lens surface of the lens. Furthermore, the lens arrangement includes a transparent transition body, which is firmly coupled with the lens on... Agent: Slater & Matsil, L.L.P.

20100038662 - Light emitting device and production method of same: A light emitting device, and a production method thereof, is provided having for a light source thereof a vertical geometry light emitting diode, that allows a large current to flow through the vertical geometry light emitting diode and takes into consideration the dissipation of heat occurring at that time or... Agent: Christie, Parker & Hale, LLP

20100038665 - Light-emitting device and method for manufacturing the same: A light-emitting device (1) includes a base (10), a light-emitting element (11) placed on the base (10), and a wavelength converting layer (12) that covers the light-emitting element (11). The wavelength converting layer (12) includes a wavelength converting portion (13) that converts a wavelength of light from the light-emitting element... Agent: Hamre, Schumann, Mueller & Larson P.C.

20100038661 - Light-emitting diode with non-metallic reflector: A light-emitting diode (LED) device is provided. The LED device has a substrate, a reflective structure over the substrate, and an LED structure over the reflective structure. The reflective structure is formed of non-metallic materials. In one embodiment, the reflective structure is formed of alternating layers of different non-metallic materials... Agent: Slater & Matsil, L.L.P.

20100038659 - Omnidirectional reflector: A system and method for manufacturing an LED is provided. A preferred embodiment includes a substrate with a distributed Bragg reflector formed over the substrate. A photonic crystal layer is formed over the distributed Bragg reflector to collimate the light that impinges upon the distributed Bragg reflector, thereby increasing the... Agent: Slater & Matsil, L.L.P.

20100038667 - Optoelectronic semiconductor chip and method for manufacturing a contact structure for such a chip: An optoelectronic semiconductor chip with a semiconductor body having a semiconductor layer sequence with an active region suitable for generating radiation is specified, wherein the semiconductor chip comprises a radiation-transmissive and electrically conductive contact layer arranged on a semiconductor body and electrically connected to an active region. The contact layer... Agent: Slater & Matsil, L.L.P.

20100038658 - Polymer light-emitting diode and fabrication of same by resonant infrared laser vapor deposition: A polymeric light-emitting diode (PLED) and methods of making same. In one embodiment, the PLED comprises a substrate, a layer of a first conductive material formed on a surface of the substrate, a layer of a conductive polymeric material deposited on the layer of the first conductive material, a layer... Agent: Morris Manning Martin LLP

20100038664 - Semiconductor chip and method for producing a semiconductor chip: A semiconductor chip includes a carrier and a semiconductor body, which includes a semiconductor layer sequence having an active region provided for generating radiation. The carrier has a first carrier area facing the semiconductor body and a second carrier area remote from the semiconductor body. The semiconductor body is cohesively... Agent: Slater & Matsil, L.L.P.

20100038668 - Semiconductor device and method of manufacturing the same: The invention is directed to providing a smaller semiconductor device with a lower manufacturing cost and higher reliability and a method of manufacturing the same. A light emitting element (a LED die 8) is formed on a first substrate 1. A cathode electrode 10 connected to an N type region... Agent: Morrison & Foerster LLP

20100038660 - Two-phase cooling for light-emitting devices: System, method, and apparatus for two phase cooling in light-emitting devices are disclosed. In one aspect of the present disclosure, an apparatus includes a light-emitting device and a two-phase cooling apparatus coupled to the light-emitting device. The coupling of the two-phase cooling apparatus and the light-emitting device is operatively configured... Agent: Perkins Coie LLP

20100038669 - Vertical light emitting diodes: A light emitting device (LED) employs one or more conductive multilayer reflector (CMR) structures. Each CMR is located between the light emitting region and a metal electrical contact region, thereby acting as low-loss, high-reflectivity region that masks the lossy metal contact regions away from the trapped waveguide modes. Improved optical... Agent: Renner Otto Boisselle & Sklar, LLP

20100038672 - Light emitting device and method for fabricating the same: Disclosed is a light emitting device. The light emitting device comprises a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, the second conductive semiconductor layer comprising a first area and a second area, a third conductive... Agent: Birch Stewart Kolasch & Birch

20100038671 - Light-emitting element chip, exposure device and image forming apparatus: The light-emitting element chip includes: a substrate; a light-emitting portion including plural light-emitting elements each having a first semiconductor layer that has a first conductivity type and that is stacked on the substrate, a second semiconductor layer that has a second conductivity type and that is stacked on the first... Agent: Fildes & Outland, P.C.

20100038673 - Radiation-emitting chip comprising at least one semiconductor body: A chip includes at least one semiconductor body having a radiation-emitting region, and at least one first contact region which is provided for making electrical contact with the semiconductor body and is spaced apart laterally from the radiation-emitting region. An electrically conductive first contact layer which is transmissive to the... Agent: Slater & Matsil, L.L.P.

20100038674 - Light-emitting diode with current-spreading region: A light-emitting diode (LED) device is provided. The LED device has a lower LED layer and an upper LED layer with a light-emitting layer interposed therebetween. A current blocking layer is formed in the upper LED layer such that current passing between an electrode contacting the upper LED layer flows... Agent: Slater & Matsil, L.L.P.

20100038675 - Power semiconductor devices and methods for manufacturing the same: A power semiconductor device that realizes high-speed turnoff and soft switching at the same time has an n-type main semiconductor layer that includes lightly doped n-type semiconductor layers and extremely lightly doped n-type semiconductor layers arranged alternately and repeatedly between a p-type channel layer and an n+-type field stop layer,... Agent: Rabin & Berdo, PC

20100038676 - Semiconductor devices with a field shaping region: A semiconductor device includes a semiconductor region having a pn junction and a field shaping region located adjacent the pn junction to increase the reverse breakdown voltage of the device. The field shaping region is coupled via capacitive voltage coupling regions to substantially the same voltages as are applied to... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100038677 - Semiconductor device for electrostatic discharge protection: A semiconductor device for electrostatic discharge protection is disclosed, and at least comprises a high-voltage parasite silicon controlled rectifier (HVSCR) and a diode. The HVSCR has an anode and a cathode, and the cathode of HVSCR is coupled to a ground. The diode, coupled to the HVSCR in series, also... Agent: Bacon & Thomas, PLLC

20100038678 - Photodiode with a reduced dark current and method for the production thereof: A photodiode in which a pn junction is formed between the doped region (DG) formed in the surface of a crystalline semiconductor substrate and a semiconductor layer (HS) deposited above said doped region. An additional doping (GD) is provided in the edge region of the doped zone, by means of... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20100038679 - Finfet with longitudinal stress in a channel: At least one gate dielectric, a gate electrode, and a gate cap dielectric are formed over at least one channel region of at least one semiconductor fin. A gate spacer is formed on the sidewalls of the gate electrode, exposing end portions of the fin on both sides of the... Agent: Scully, Scott, Murphy & Presser, P.C.

20100038680 - Iii-nitride semiconductor field effect transistor: Provided is a semiconductor device that can reduce the contact resistance, has a small current collapse, and can improve the pinch-off characteristic upon a high-frequency operation. A field effect transistor using a wurtzite (having (0001) as the main plane) type III-nitride semiconductor includes: a substrate (101); an undercoat layer (103)... Agent: Mr. Jackson Chen

20100038682 - Electronic devices with improved ohmic contact: In one embodiment, the disclosure relates to an electronic device successively comprising from its base to its surface: (a) a support layer, (b) a channel layer adapted to contain an electron gas, (c) a barrier layer and (d) at least one ohmic contact electrode formed by a superposition of metallic... Agent: Edwards Angell Palmer & Dodge LLP

20100038681 - Transistor: An HEMT type transistor is disclosed that is a normally off type, and in which variations in the gate threshold voltage are small. A transistor is provided with a p-type region, a barrier region, an insulation film, a gate electrode. The channel region is connected to an upper surface of... Agent: Kenyon & Kenyon LLP

20100038683 - Integrated circuit modeling, design, and fabrication based on degradation mechanisms: An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first... Agent: Texas Instruments Incorporated

20100038684 - Transistor layout for manufacturing process control: A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has a first current path (506) oriented in a first crystal direction (520). A first control gate... Agent: Texas Instruments Incorporated

20100038685 - Enhanced dislocation stress transistor: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the... Agent: Intel Corporation C/o Cpa Global

20100038687 - Selective deposition of amorphous silicon films on metal gates: A microelectronic device includes a metal gate with a metal gate upper surface. The metal gate is disposed in an interlayer dielectric first layer. The interlayer dielectric first layer also has an upper surface that is coplanar with the metal gate upper surface. A dielectric etch stop layer is disposed... Agent: Intel Corporation C/o Cpa Global

20100038686 - Soi substrates and devices on soi substrates having a silicon nitride diffusion inhibition layer and methods for fabricating: Semiconductor-on-insulator substrates and methods for fabricating semiconductor-on-insulator substrates are provided. One exemplary method comprises providing a first silicon-comprising substrate, providing a second silicon-comprising substrate, forming a first silicon nitride layer overlying the second silicon-comprising substrate, and coupling the first silicon-comprising substrate to the second silicon-comprising substrate such that the first... Agent: Ingrassia Fisher & Lorenz, P.C. (gf)

20100038688 - Cmos image sensor, method of making the same, and method of suppressing dark leakage and crosstalk for cmos image sensor: A CMOS image sensor, in which an implantation process is performed on substrate under isolation structures each disposed between two adjacent photosensor cell structures. The implantation process is a destructive implantation to form lattice effects/trap centers. No defect repair process is carried out after the implantation process is performed. The... Agent: North America Intellectual Property Corporation

20100038691 - Image sensor and method for fabricating the same: An image sensor and a method for fabricating the same are provided. The image sensor includes a first conductive type substrate including a trench formed in a predetermined portion of the first conductive type substrate, a second conductive type impurity region for use in a photodiode, formed below a bottom... Agent: Mcandrews Held & Malloy, Ltd

20100038690 - Image sensor and method of fabricating the same: An image sensor can include a gate insulation layer, a gate electrode, a photodiode, and a floating diffusion region. The gate insulation layer can be formed on and/or over a semiconductor substrate for a transfer transistor. The gate insulation layer includes a first gate insulation layer having a central opening... Agent: Sherr & Vaughn, PLLC

20100038689 - Integrating fabrication of photodetector with fabrication of cmos device on a silicon-on-insulator substrate: A method and semiconductor device for integrating the fabrication of a photodetector with the fabrication of a CMOS device on a SOI substrate. The SOI substrate is divided into two regions, a CMOS region and an optical detecting region. After the CMOS device is fabricated in the CMOS region, the... Agent: Winstead, P.C.

20100038692 - Integrating the formation of i/o and core mos devices with mos capacitors and resistors: An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device... Agent: Slater & Matsil, L.L.P.

20100038693 - Semiconductor device: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of... Agent: Miles & Stockbridge PC

20100038694 - Split-gate dram with mugfet, design structure, and method of manufacture: A semiconductor structure for a dynamic random access memory cell, the structure including: a fin of a fin-type field effect transistor (FinFET) device formed over and spaced apart from a conductive region of a substrate; a storage capacitor connected to a first end of the fin; and a back-gate at... Agent: Greenblum & Bernstein, P.L.C

20100038695 - Computing apparatus employing dynamic memory cell structures: A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater... Agent: Ryan, Mason & Lewis, LLP

20100038697 - Non-volatile two-transistor programmable logic cell and array layout: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within... Agent: Lewis And Roca LLP

20100038696 - Semiconductor device and method for making same: One or more embodiments, relate to a field effect transistor, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a gate electrode overlying a gate dielectric; and a sidewall spacer may be disposed over the substrate and laterally disposed from the gate stack, the spacer... Agent: Infineon Technologies Ag Patent Department

20100038698 - High density flash memory device , cell string fabricating method thereof: A flash memory cell string and a method of fabricating the same are provided. The flash memory cell string includes a plurality of cell devices and switching devices connected to ends of the cell devices. Each of the cell devices includes a semiconductor substrate, a tunneling insulating layer, a charge... Agent: The Nath Law Group

20100038701 - Integrated two device non-volatile memory: The non-volatile memory cell is comprised of the series integration of a fixed threshold element and a bistable element. The fixed threshold element is formed over a substrate with a gate insulator layer and an access gate having a nitride layer. The bistable element is formed adjacent to the fixed... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20100038702 - Nonvolatile memory device and methods of forming the same: Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same. The memory device may include memory cells separately formed on a channel region between impurity regions formed on a substrate. The... Agent: Harness, Dickey & Pierce, P.L.C

20100038699 - Nonvolatile semiconductor memory device and method for manufacturing same: A stacked body is formed on a silicon substrate by stacking a plurality of insulating films and a plurality of electrode films alternately and through-holes are formed to extend in the stacking direction. Next, gaps are formed between the electrode films using etching the insulating films via the through-holes. Charge... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100038700 - Semiconductor device: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first... Agent: Antonelli, Terry, Stout & Kraus, LLP

20100038703 - Non-volatile semiconductor storage device: A memory string has a semiconductor layer with a joining portion that is formed to join a plurality of columnar portions extending in a vertical direction with respect to a substrate and lower ends of the plurality of columnar portions. First conductive layers are formed in a laminated fashion to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100038704 - Nonvolatile semiconductor memory device suppressing fluctuation in threshold voltage: First and second memory cell transistors are isolated by an element isolation insulating film. A barrier insulating film covers the element isolation insulating film. The first memory cell transistor includes a first tunnel insulating film, a first charge storage layer made of an insulating film, a first block insulating film,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100038705 - Field effect device with gate electrode edge enhanced gate dielectric and method for fabrication: A semiconductor structure and a method for fabricating the semiconductor structure provide an undercut beneath a spacer that is adjacent a gate electrode within a field effect structure such as a field effect transistor structure. The undercut, which may completely or incompletely encompass the area interposed between the spacer and... Agent: Scully, Scott, Murphy & Presser, P.C.

20100038708 - Method and structure for forming a shielded gate field effect transistor: A method of forming a charge balance MOSFET includes the following steps. A substrate with an overlying epitaxial layer both of a first conductivity type, are provided. A gate trench extending through the epitaxial layer and terminating within the substrate is formed. A shield dielectric lining sidewalls and bottom surface... Agent: Townsend And Townsend And Crew, LLP

20100038706 - Semiconductor device: Provided is an ESD protection element, in which: LOCOS oxide films are formed at both ends of a gate electrode, and a conductivity type of a diffusion layer formed below one of the LOCOS oxide films which is not located on a drain side is set to a p-type, to... Agent: Brinks Hofer Gilson & Lione/seiko Instruments Inc.

20100038707 - Semiconductor device: A semiconductor device including: a semiconductor substrate; a first main electrode provided on a first main surface of said semiconductor substrate; a second main electrode provided on a second main surface of said semiconductor substrate, wherein a main current flows in a thickness direction of said semiconductor substrate; a trench... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100038709 - Vertical transistor and array with vertical transistors: A vertical transistor includes a substrate, a semiconductor structure, a gate, a gate dielectric layer, and a conductive layer. The semiconductor structure is disposed on the substrate and includes two vertical plates and a bottom plate. The bottom plate has an upper surface connected to bottoms of the two vertical... Agent: Jianq Chyun Intellectual Property Office

20100038710 - Vertical power mosfet semiconductor apparatus having separate base regions and manufacturing method thereof: A semiconductor apparatus according to the present invention includes a first semiconductor layer of a first conductive type, a low concentration base region of a second conductive type formed on the first semiconductor layer, a gate electrode formed in a trench with insulating film on an inner surface of the... Agent: Mcginn Intellectual Property Law Group, PLLC

20100038711 - Trenched mosfet with guard ring and channel stop: A trenched MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with a guard ring and a channel stop, including: a substrate including an epi layer region on the top thereof; a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which... Agent: Birch Stewart Kolasch & Birch

20100038712 - Power semiconductor device: A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part. The device includes a first semiconductor layer, and second and third semiconductor layers formed on the first semiconductor layer, and alternately arranged along a direction parallel to a surface of the... Agent: Patterson & Sheridan, L.L.P.

20100038713 - Self-aligned tunneling pocket in field-effect transistors and processes to form same: A microelectronic device includes a tunneling pocket within an asymmetrical semiconductive body including source- and drain wells. The tunneling pocket is formed by a self-aligned process by removing a dummy gate electrode from a gate spacer and by implanting the tunneling pocket into the semiconductive body or into an epitaxial... Agent: Intel Corporation C/o Cpa Global

20100038716 - Crystalline semiconductor thin film, method of fabricating the same, semiconductor device, and method of fabricating the same: There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. A catalytic element for facilitating crystallization of an amorphous semiconductor thin film is added to the amorphous semiconductor thin film, and a heat treatment is carried out to obtain... Agent: Eric Robinson

20100038714 - Device and process involving pinhole undercut area: An electronic device fabrication method including: (a) providing a dielectric region and a lower electrically conductive region, wherein the dielectric region includes a plurality of pinholes each with an entry and an exit; and (b) depositing an etchant for the lower electrically conductive region into the pinholes that undercuts the... Agent: Fay Sharpe / Xerox - Rochester

20100038717 - Semiconductor on insulator apparatus: A method and apparatus for producing a relatively thin, relatively uniform semiconductor layer which has improved carrier mobility. In an embodiment, a lattice-matched insulator layer is formed on a semiconductor substrate, and a lattice-matched semiconductor layer is formed on the insulator layer to form a relatively thin, relatively uniform semiconductor... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20100038715 - Thin body silicon-on-insulator transistor with borderless self-aligned contacts: A method for fabricating a thin-silicon-on-insulator transistor with borderless self-aligned contacts is disclosed. A gate stack is formed on a silicon layer that is above a buried oxide layer. The gate stack includes a gate oxide layer on the silicon layer and a gate electrode layer on the gate oxide... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.

20100038718 - Electro-static discharge and latchup resistant semiconductor device: The present invention relates to a semiconductor device including a substrate layer, a metal-oxide-semiconductor field-effect transistor (MOSFET), a backgate region, an isolation layer and a diode. The MOSFET includes a gate region, a source region and a drain region. The source and drain regions are embedded in the backgate region,... Agent: Kenyon & Kenyon LLP

20100038719 - Semiconductor apparatuses and methods of manufacturing the same: Disclosed are semiconductor apparatuses and methods of fabricating the same. According to the methods, the number of operations for fabricating the semiconductor apparatuses having a plurality of layers may be the same as the number of operations for fabricating a semiconductor apparatus having one layer. The semiconductor apparatuses may include... Agent: Harness, Dickey & Pierce, P.L.C

20100038721 - Method of forming a single metal that performs n work function and p work function in a high-k/metal gate process: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric over a semiconductor substrate, forming a capping layer over or under the gate dielectric, forming a metal layer over the capping layer, the metal layer having a first work function, treating a... Agent: Haynes And Boone, LLPIPSection

20100038722 - Mis transistor and cmos transistor: A MIS transistor, formed on a semiconductor substrate, assumed to comprise a semiconductor substrate (702, 910) comprising a projecting part (704, 910B) with at least two different crystal planes on the surface on a principal plane, a gate insulator (708, 920B) for covering at least a part of each of... Agent: Locke Lord Bissell & Liddell LLP Attn:IPDocketing

20100038720 - Structure, design structure and method of manufacturing dual metal gate vt roll-up structure: A structure, design structure and method of manufacturing is provided for a dual metal gate Vt roll-up structure, e.g., multi-work function metal gate. The multi-work function metal gate structure comprises a first type of metal with a first work function in a central region and a second type of metal... Agent: Greenblum & Bernstein, P.L.C

20100038723 - Self-aligned borderless contacts for high density electronic and memory device integration: A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.

20100038725 - Changing effective work function using ion implantation during dual work function metal gate integration: Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work... Agent: Hoffman Warnick LLC

20100038724 - Metal-gate high-k reference structure: Disclosed are embodiments of an integrated circuit structure that incorporates at least two field effect transistors (FETs) that have the same conductivity type and essentially identical semiconductor bodies (i.e., the same semiconductor material and, thereby the same conduction and valence band energies, the same source, drain, and channel dopant profiles,... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20100038726 - Radiation hardened device: A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a... Agent: Barnes & Thornburg LLP

20100038727 - Carbon-doped epitaxial sige: A method for forming carbon-doped epitaxial SiGe of a PMOS transistor by providing a semiconductor substrate having a PMOS transistor gate stack and recess etched active regions. The method includes forming carbon-doped epitaxial SiGe within the recess etched active regions. A PMOS transistor includes a semiconductor substrate, a PMOS transistor... Agent: Texas Instruments Incorporated

20100038728 - Field effect transistor with suppressed corner leakage through channel material band-edge modulation, design structure and method: Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20100038729 - Method of manufacturing semiconductor device and semiconductor device: A base insulating film containing hafnium and oxygen is formed on a silicon oxide (SiO2) film formed on a main surface of a substrate. Subsequently, a metal thin film thinner than the base insulating film and made of only a metal element is formed on the base insulating film, and... Agent: Miles & Stockbridge PC

20100038732 - Micro movable device: A micro movable device includes a protection cap for protecting a movable unit arranged above a semiconductor substrate and the movable unit, signal line for transmitting a high-frequency signal formed above the semiconductor substrate, and insulation layer that has projection formed to project upward from the semiconductor substrate and coated... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100038731 - Non-volatile memory device: A non-volatile memory device and method of manufacturing a non-volatile micro-electromechanical memory cell. The method comprises the first step of depositing a first layer of sacrificial material on a substrate by use of Atomic Layer Deposition The second step of the method is providing a cantilever (101) over at least... Agent: Patterson & Sheridan, L.L.P.

20100038730 - Semiconductor structures including a movable switching element, systems including same and methods of forming same: Semiconductor structures including a movable switching element having a base disposed on a conductive pad, a body extending from the base, and an end laterally adjacent and spaced apart from a conductive contact are disclosed. Upon application of a threshold voltage, the movable switching element may deform toward the conductive... Agent: Trask Britt, P.C./ Micron Technology

20100038733 - Microelectromichanical system package with strain relief bridge: A strain absorption bridge for use in a MEMS package includes a first substrate that is configured to be attachable to a circuit board. A first elastically deformable element is coupled to the first substrate and the first elastically deformable element is configured to be attachable to a MEMS device.... Agent: Fitch Even Tabin & Flannery

20100038734 - Vibration sensor and method for manufacturing the vibration sensor: A method for manufacturing a vibration sensor including forming a sacrifice layer at one part of a front surface of a semiconductor substrate of monocrystalline silicon with a material isotropically etched by an etchant for etching the semiconductor substrate, forming a thin film protective film with a material having resistance... Agent: Osha Liang L.L.P.

20100038735 - Magnet-assisted transistor devices: A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of... Agent: Intellectual Property Group Seagate Technology Files

20100038736 - Suspended germanium photodetector for silicon waveguide: A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium... Agent: Scully, Scott, Murphy & Presser, P.C.

20100038738 - Capacitive bypass: An indirect connection to and across a photodiode array. The backside contact is used as one portion which connects to a capacitor. The capacitor forms a shunt across the bulk substrate, thus shunting across the series resistance of the substrate, and reducing the series resistance.... Agent: Law Office Of Scott C Harris Inc

20100038737 - Plastic image sensor packaging for image sensors: A package for an image sensor includes a lead frame having a first surface and a second surface opposite the first surface; an image sensor mounted on the first surface of the lead frame; an optical cover spanning the first surface; and a plastic, optically transparent window in the optical... Agent: Peter P. Hernandez, Patent Legal Staff Eastman Kodak Company

20100038739 - Semiconductor device and fabrication process thereof: A semiconductor device that includes a circuit portion, a first light-shielding film and plural second light-shielding films. In the circuit portion, a plurality of wiring layers that include circuit elements are laminated. The first light-shielding film covers an uppermost layer of the wiring layers and light-shields light that is illuminated... Agent: Taft, Stettinius & Hollister LLP

20100038740 - Color image sensor with improved optical crosstalk: The invention relates to image sensors produced on a thinned silicon substrate. To limit the optical crosstalk between adjacent filters and, notably filters of different colors, the invention proposes positioning, between the adjacent filters of different colors (FR, FB, FV), a wall (20) of a material tending to reflect the... Agent: Lowe Hauptman Ham & Berner, LLP

20100038741 - Semiconductor apparatus, manufacturing method of semiconductor apparatus, and camera module: A semiconductor apparatus includes, a semiconductor substrate having first and second main surfaces and a thought hole connecting the first and second main surfaces; a first insulation layer arranged on the first main surface, and having an opening corresponding to the thought hole; a first conductive layer arranged on the... Agent: Turocy & Watson, LLP

20100038743 - Information storage system which includes a bonded semiconductor structure: An information storage system includes a bonded semiconductor structure having a memory circuit region carried by an interconnect region. The memory circuit region includes a memory control device region having a vertically oriented memory control device. The memory circuit region includes a memory device region in communication with the memory... Agent: Schmeiser Olsen & Watts

20100038742 - Semiconductor device and manufacturing method thereof: This invention is directed to offer a technology that makes it possible to form desired bump electrodes easily when the bump electrodes are to be formed at locations lowered by a step. There is formed an isolation layer 12 to isolate each of bump electrode forming regions 11. The isolation... Agent: Morrison & Foerster LLP

20100038745 - Integrated circuit structure having bottle-shaped isolation: An integrated circuit structure comprises a semiconductor substrate, a device region positioned in the semiconductor substrate, an insulating region adjacent to the device region, an isolation structure positioned in the insulating region and including a bottle portion and a neck portion filled with a dielectric material, and a dielectric layer... Agent: Wpat, PC Intellectual Property Attorneys

20100038744 - Shallow trench isolation: Shallow trench isolation methods are disclosed. In a particular embodiment, a method includes implanting oxygen under a bottom surface of a narrow trench of a silicon substrate and performing a high-temperature anneal of the silicon substrate to form a buried oxide layer. The method also includes performing an etch to... Agent: Qualcomm Incorporated

20100038746 - Semiconductor structure and method for making isolation structure therein: A method for an isolation structure is provided. First, a substrate with a shallow trench isolation is provided. Second, a patterned mask is formed on the substrate. Then, the substrate is etched using the patterned mask to respectively form a first deep trench and a second deep trench as well... Agent: North America Intellectual Property Corporation

20100038748 - Electric fuse circuit and electronic component: An electric fuse circuit is provided which has a capacitor that forms an electric fuse; a write circuit for breaking an insulating film of the capacitor, by applying a voltage to a terminal of the capacitor in response to a write signal; and at least two transistors, including a first... Agent: Arent Fox LLP

20100038747 - Electrically programmable fuse and fabrication method: An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the... Agent: Cantor Colburn LLP - IBM Fishkill

20100038749 - Contact and via interconnects using metal around dielectric pillars: An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming... Agent: Texas Instruments Incorporated

20100038752 - Modular & scalable intra-metal capacitors: An intra-metal capacitor unit cell comprises a first electrode and a second electrode formed in the same device layer. A dielectric layer separates the electrodes. The first electrode is substantially surrounded by the second electrode. Misalignment between the first and second electrodes does not substantively alter the capacitance of the... Agent: HorizonIPPte Ltd

20100038751 - Structure and method for manufacturing trench capacitance: A deep trench (DT) capacitor comprises a trench in a silicon layer, a buried plate surrounding the trench, a dielectric layer lining the trench, and a node conductor in the trench. The top surface of the poly node is higher than the surface of the silicon layer, so that it... Agent: International Business Machines Corporation Dept. 18g

20100038750 - Structure, design structure and method of manufacturing a structure having vias and high density capacitors: A semiconductor structure and design structure includes at least a first trench and a second trench having different depths arranged in a substrate, a capacitor arranged in the first trench, and a via arranged in the second trench.... Agent: Andrew M. Calderon Greenblum & Bernstein, P.L.C

20100038753 - Variable capacitor employing mems technology: When a positive voltage of V1 is applied to a drive capacitor with a braking voltage V2 at 0V, a moveable electrode moves toward the drive electrode, and a capacitance C of a tunable capacitor becomes smaller. When the braking voltage V2 is applied a lower portion brake electrode of... Agent: Rabin & Berdo, PC

20100038754 - Back-end-of-line resistive semiconductor structures: In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top... Agent: Scully, Scott, Murphy & Presser, P.C.

20100038755 - Silicon wafer with controlled distribution of embryos that become oxygen precipitates by succeeding annealing and its manufacturing method: A method for making a silicon wafer includes the steps of generating and stabilizing embryos that become oxygen precipitates by succeeding thermal annealing applied during a semiconductor device manufacturing process. In the silicon wafer, embryos are substantially removed in a denuded zone, and embryos are distributed at a relatively higher... Agent: Lowe Hauptman Ham & Berner, LLP

20100038756 - (110) oriented silicon substrate and a bonded pair of substrates comprising said (110) oriented silicon substrate: The present invention relates to method of fabricating a (110) oriented silicon substrate and to a method of fabricating a bonded pair of substrates comprising such a (110) oriented silicon substrate. The invention further relates to a silicon substrate with (110) orientation and to a bonded pair of silicon substrates... Agent: Traskbritt, P.C.

20100038757 - Silicon wafer, method for manufacturing the same and method for heat-treating the same: A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T1) of 1300° C. or more, but less than 1380° C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more,... Agent: Foley And Lardner LLP Suite 500

20100038758 - Semiconductor module with two cooling surfaces and method: A semiconductor module with two cooling surfaces and method. One embodiment includes a first carrier with a first cooling surface and a second carrier with a second cooling surface. The first cooling surface is arranged in a first plane, the second cooling surface is arranged in a second plane, at... Agent: Dicke, Billig & Czaja

20100038761 - Integrated circuit package system: An integrated circuit package system includes: mounting a first integrated circuit over a carrier; mounting an interposer, having an opening, over the first integrated circuit and the carrier with the interposer having an overhang over the carrier; connecting an internal interconnect, through the opening, between the carrier and the interposer;... Agent: Law Offices Of Mikio Ishimaru

20100038759 - Leadless package with internally extended package leads: A DFN package includes internally extended package leads. One or more package pads are physically and electrically extended from a first edge of the package to a second, opposite edge of the package. These extended package leads can terminate at the edges of the leadframe. The package pads and the... Agent: Fish & Richardson P.C.

20100038760 - Metal leadframe package with secure feature: A fabrication method for a BGA or LGA package includes a low-cost metal leadframe with internally extended leads. I/O attach lands can be placed at any location on the metal leadframe, including the center of the package. An I/O attach land can be fabricated at any position upon an extended... Agent: Fish & Richardson P.C.

20100038762 - Circuit board manufacturing method, semiconductor manufacturing apparatus, circuit board and semiconductor device: There is provided a circuit board manufacturing method that makes it possible to manufacture a next-generation semiconductor device in a stable manner and improve the yield during secondary mounting processing. A circuit board 11 with a thickness of 230 μm manufactured using a cyanate-based prepreg 12 containing a resin composition... Agent: Ditthavong Mori & Steiner, P.C.

20100038763 - Semiconductor structure with communication element: In one embodiment, a structure includes a semiconductor chip including a communication element for performing a wireless communication function where the communication element has a communication core occupying a region of the semiconductor chip, a plurality of chip pads with two of the chip pads electrically connected to the communication... Agent: Patent Law Group LLP

20100038764 - Package on package design a combination of laminate and tape substrate with back-to-back die combination: In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a bottom laminate substrate (BLS) (130) is formed to include interconnection patterns (IP) (170, 172) coupled to a plurality of conductive bumps (PCB) (130). A top substrate (TS) (140) is formed to mount a top... Agent: Texas Instruments Incorporated

20100038768 - Integrated circuit package system for package stacking and manufacturing method thereof: A stackable multi-chip package system is provided including forming an external interconnect having a base and a tip, connecting a first integrated circuit die and the base, stacking a second integrated circuit die over the first integrated circuit die in an active side to active side configuration, connecting the second... Agent: Law Offices Of Mikio Ishimaru

20100038766 - Method for forming terminal of stacked package element and method for forming stacked package: A semiconductor chip module having high degree of freedom in assignment of a circuit to each semiconductor chip and in position of a connection terminal of each semiconductor chip is provided. The present invention relates to a semiconductor chip module in which a plurality of semiconductor chips each provided on... Agent: Bacon & Thomas, PLLC

20100038767 - Semiconductor device and method of manufacturing the same: The semiconductor device includes a stacked semiconductor package in which end portions of a plurality of flexible substrates have bonded portions which are connected together by wirings and in which a plurality of semiconductor packages are electrically connected to a mother substrate via the bonded portions. In at least a... Agent: Young & Thompson

20100038765 - Semiconductor package and method for manufacturing the same: Provided is a semiconductor package and a method for fabricating the semiconductor package. The semiconductor package may include a first package having a first semiconductor chip mounted on a first substrate and a second package having a second semiconductor chip mounted on a second substrate, the second substrate being bent... Agent: Harness, Dickey & Pierce, P.L.C

20100038769 - Wafer stacked package waving bertical heat emission path and method of fabricating the same: A wafer stacked semiconductor package (WSP) having a vertical heat emission path and a method of fabricating the same are provided. The WSP comprises a substrate on which semiconductor chips are mounted; a plurality of semiconductor chips stacked vertically on the substrate; a cooling through-hole formed vertically in the plurality... Agent: Volentine & Whitt PLLC

20100038770 - Method of packaging and interconnection of integrated circuits: A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible... Agent: James Sheats

20100038771 - Integrated circuit package with open substrate: A method of manufacturing an integrated circuit package includes: forming a substrate that includes: forming a core layer, forming vias in the core layer, and forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections... Agent: Law Offices Of Mikio Ishimaru

20100038773 - Bond pad for wafer and package for cmos imager: An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seat between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect... Agent: Scully, Scott, Murphy & Presser, P.C.

20100038772 - Semiconductor package and manufacturing method thereof: A semiconductor package includes a wiring board and a semiconductor device mounted on the wiring board. At least one penetration hole extends from one surface of the semiconductor chip to an opposite surface of the semiconductor chip. A penetration electrode is situated inside the penetration hole without contacting a wall... Agent: Ipusa, P.l.l.c

20100038774 - Advanced and integrated cooling for press-packages: A heat sink for cooling at least one electronic device package is provided. The electronic device package has an upper contact surface and a lower contact surface. The heat sink comprises at least one thermally conductive material and defines multiple inlet manifolds configured to receive a coolant, multiple outlet manifolds... Agent: General Electric Company Global Research

20100038775 - Miniature electronic component for microwave applications: The invention relates to a miniature microwave component having: a microwave chip (18, 60, 140) encapsulated in an individual package (61) for surface mounting. A metal base (80) mounts the chip in the package via its rear face. The base has an aperture (82). At least two access ports are... Agent: Lowe Hauptman Ham & Berner, LLP

20100038776 - Miniature microwave package and process for fabricating the package: The invention relates to a miniature microwave package comprising a microwave chip (60) having an active face (62). The chip includes a protective lid (72) fixed to the active face, at least partially covering it, the lid including at least one recess forming, with the active face of the chip,... Agent: Lowe Hauptman Ham & Berner, LLP

20100038778 - Integrated circuit structures and fabricating methods that use voids in through holes as joining interfaces: A void that is created in a conductive electrode in a through hole that extends through an integrated circuit substrate can be used as a joining interface. For example, an integrated circuit structure includes an integrated circuit substrate having a conductive pad on a first face thereof, and a through... Agent: Myers Bigel Sibley & Sajovec

20100038777 - Method of making a sidewall-protected metallic pillar on a semiconductor substrate: A method of forming conductive pillars on a semiconductor wafer in which the conductive pillars are plated with a protecting coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP. Only the side of the conductive pillars are plated. The ends of the conductive pillars are free of... Agent: International Business Machines Corporation Dept. 18g

20100038779 - Semiconductor device: A semiconductor device includes a semiconductor chip having a first main surface having an electrode pad in an exposed state, and an interlayer insulation layer formed on the first main surface so that the electrode pad is partially exposed; a re-wiring layer including a wiring pattern having a linear portion... Agent: Kazunao Kubotera Takeuchi & Kubotera, LLP

20100038781 - Integrated circuit packaging system having a cavity: An integrated circuit packaging system includes: attaching a carrier, having a carrier top side and a carrier bottom side, and an interconnect without an active device attached to the carrier bottom side; and forming a first encapsulation, having a cavity, around the interconnect over the carrier top side with the... Agent: Law Offices Of Mikio Ishimaru

20100038780 - Underfill flow guide structures and method of using same: Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes.... Agent: Greenblum & Bernstein, P.L.C

20100038785 - Materials for adhesion enhancement of copper film on diffusion barriers: We have used the state-of-the-art computational chemistry techniques to identify adhesion promoting layer materials that provide good adhesion of copper seed layer to the adhesion promoting layer and the adhesion promoting layer to the barrier layer. We have identified factors responsible for providing good adhesion of copper layer on various... Agent: Air Products And Chemicals, Inc. Patent Department

20100038783 - Metal cap for back end of line (beol) interconnects, design structure and method of manufacture: A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal... Agent: Greenblum & Bernstein, P.L.C

20100038786 - Method for manufacturing a semiconductor device: A method for manufacturing a semiconductor device is disclosed. A semiconductor substrate such as bare silicon is provided, and a dielectric layer is formed over the semiconductor substrate. An opening is provided within the dielectric layer by removing a portion of the dielectric layer. A conformal first conductive layer is... Agent: J C Patents

20100038788 - Multi-layered metal line of semiconductor device for preventing diffusion between metal lines and method for forming the same: A multi-layered metal line of a semiconductor device includes a semiconductor substrate; a lower metal line formed on the semiconductor substrate and recessed on a surface thereof; an insulation layer formed on the semiconductor substrate including the lower metal line and having a damascene pattern for exposing a recessed portion... Agent: Ladas & Parry LLP

20100038782 - Nitrogen-containing metal cap for interconnect structures: An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A nitrogen-containing noble... Agent: Scully, Scott, Murphy & Presser, P.C.

20100038784 - Redundant barrier structure for interconnect and wiring applications, design structure and method of manufacture: A redundant diffusion barrier structure and method of fabricated is provided for interconnect and wiring applications. The structure can also be a design structure. The structure includes a first liner lining at least one of a trench and a via and a second liner deposited over the first liner. The... Agent: Greenblum & Bernstein, P.L.C

20100038787 - Semiconductor device and method of manufacturing the same: A semiconductor device has an interlayer insulating film that is formed on a semiconductor substrate and has a trench formed therein; a first diffusion barrier film formed on an inner surface of the trench; a Cu wiring layer buried in the trench with the first diffusion barrier film interposed between... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20100038789 - Conformal adhesion promoter liner for metal interconnects: A dielectric layer is patterned with at least one line trough and/or at least one via cavity. A metallic nitride liner is formed on the surfaces of the patterned dielectric layer. A metal liner is formed on the surface of the metallic nitride liner. A conformal copper nitride layer is... Agent: Scully, Scott, Murphy & Presser, P.C.

20100038790 - reliability of wide interconnects: An integrated circuit which includes a semiconductor substrate, a first metal wiring level on the semiconductor substrate which includes metal wiring lines, an interconnect wiring level on the first metal wiring level which includes a via interconnect within an interlevel dielectric, a second metal wiring level on the interconnect wiring... Agent: International Business Machines Corporation Dept. 18g

20100038791 - Resistive random access memory and method for fabricating the same: A resistive random access memory and a method for fabricating the same are provided. The method includes providing a bottom electrode formed on a substrate. A metal oxide layer is formed on the bottom electrode. An oxygen atom gettering layer is formed on the metal oxide layer. A top electrode... Agent: Quintero Law Office, PC

20100038792 - Semiconductor device: A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection... Agent: Fujitsu Patent Center C/o Cpa Global

20100038793 - Interconnect structures comprising capping layers with low dielectric constants and methods of making the same: Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first... Agent: Cantor Colburn LLP - IBM Fishkill

20100038797 - Controlling lateral distribution of air gaps in interconnects: Properties of a hard mask liner are used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack. According to one embodiment, there is provided a method in which there is defined a portion on a surface of an IC interconnect... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.

20100038796 - High aspect ratio contacts: A contact formed in accordance with a process for etching a insulating layer to produce an opening having an aspect ratio of at least 15:1 by first exposing the insulating layer to a second plasma of a second gaseous etchant comprising Ar, Xe, and combinations thereof to form an opening... Agent: Brooks, Cameron & Huebsch , PLLC

20100038798 - Method for correcting mask pattern, photomask, method for fabricating photomask, electron beam writing method for fabricating photomask, exposure method, semiconductor device, and method for fabricating semiconductor device: A method for correcting a mask pattern to be formed on a photomask used in a lithographic step of a semiconductor device fabrication process. The method includes the steps of extracting an isolated pattern having an optically isolated portion from the mask pattern and providing, in an adjacent pattern extending... Agent: Sonnenschein Nath & Rosenthal LLP

20100038795 - Method of fabricating semiconductor device and semiconductor device: A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20100038799 - Semiconductor integrated circuit device, mounting structure of semiconductor integrated circuit device, and method for manufacturing semiconductor integrated circuit device: A semiconductor integrated circuit device can be mounted on a circuit board through capacitive coupling even when being miniaturized. A passivation film disposed on a principal surface of a semiconductor substrate provided with a plurality of wirings laminated sequentially with insulating films therebetween has an opening at which at least... Agent: Murata Manufacturing Company, Ltd. C/o Keating & Bennett, LLP

20100038794 - Three dimensional nanoscale circuit interconnect and method of assembly by dielectrophoresis: An assembly of nanoelements forms a three-dimensional nanoscale circuit interconnect for use in microelectronic devices. A process for producing the circuit interconnect includes using dielectrophoresis by applying an electrical field across a gap between vertically displaced non-coplanar microelectrodes in the presence of a liquid suspension of nanoelements such as nanoparticles... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP

20100038800 - Through-silicon via structures including conductive protective layers and methods of forming the same: Through-Silicon-Via (TSV) structures can include a conductive via through a substrate extending from an upper surface of the substrate to a backside surface of the substrate opposite the upper surface, a conductive protective layer including Ni and/or Co can be at a bottom of the conductive via, and a separate... Agent: Myers Bigel Sibley & Sajovec

20100038801 - Corrosion control of stacked integrated circuits: A system and method prevent corrosive elements (or at least the oxidizing agent) from making contact with metal connections at the interface between two layers of a stacked IC device. When layers are positioned in proximity to each other, a cavity is formed at the boundary of the planar surfaces... Agent: Qualcomm Incorporated

20100038802 - Stacked semiconductor device and method: A method of stacking wafers includes: providing a first wafer including a first metal connection layer; forming a first passivation layer over the first metal connection layer; forming a first bondpad in the first passivation layer to form a first bondpad layer; providing a second wafer including second metal connection... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20100038803 - Low fabrication cost, high performance, high reliability chip scale package: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is... Agent: Mcdermott Will & Emery LLP

20100038804 - Integrated circuit package system with mold gate: An integrated circuit package system includes: providing a substrate; forming a conductive layer over the substrate; forming a mold gate layer having an organic material without polymerization over the conductive layer; and attaching an integrated circuit over the substrate adjacent the mold gate layer.... Agent: Law Offices Of Mikio Ishimaru

20100032635 - Array of low resistive vertical diodes and method of production: An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells.... Agent: Dicke, Billig & Czaja

20100032638 - Memory cell that includes a carbon-based memory element and methods of forming the same: Memory cells, and methods of forming such memory cells, are provided that include a carbon-based reversible resistivity switching material. In particular embodiments, methods in accordance with this invention form a memory cell by forming a carbon-based reversible resistance-switching material above a substrate, forming a carbon nitride layer above the carbon-based... Agent: Dugan & Dugan, PC

20100032639 - Memory cell that includes a carbon-based memory element and methods of forming the same: Memory cells, and methods of forming such memory cells, are provided that include a steering element coupled to a carbon-based reversible resistivity switching material. In particular embodiments, methods in accordance with this invention form a single layer of a carbon-based reversible resistance switching material above a substrate, wherein the single... Agent: Dugan & Dugan, PC

20100032640 - Memory cell that includes a carbon-based memory element and methods of forming the same: Memory cells, and methods of forming such memory cells, are provided that include a carbon-based reversible resistivity switching material. In particular embodiments, methods in accordance with this invention form a memory cell by forming a layer of carbon material above a substrate, forming a barrier layer above the carbon layer,... Agent: Dugan & Dugan, PC

20100032636 - Non-volatile memory cell with enhanced filament formation characteristics: Method and apparatus for constructing a non-volatile memory cell, such as a modified RRAM cell. In some embodiments, a memory cell comprises a resistive storage layer disposed between a first electrode layer and a second electrode layer. Further in some embodiments, the storage layer has a localized region of decreased... Agent: Campbell Nelson Whipps, LLC

20100032637 - Nonvolatile memory device and method of manufacturing the same: Provided is a nonvolatile memory device including a phase-change memory configured with cross-point memory cells in which memory elements formed of a phase-change material and selection elements formed with a diode are combined. A memory cell is configured with a memory element formed of a phase-change material and a selection... Agent: Miles & Stockbridge PC

20100032641 - Nonvolatile semiconductor memory apparatus and manufacturing method thereof: A nonvolatile semiconductor memory apparatus (10) of the present invention comprises a substrate (10), lower-layer electrode wires (15) provided on the substrate (11), an interlayer insulating layer (16) which is disposed on the substrate (11) including the lower-layer electrode wires (15) and is provided with contact holes at locations respectively... Agent: Mcdermott Will & Emery LLP

20100032643 - Memory cell that includes a carbon-based memory element and methods of forming the same: Memory cells, and methods of forming such memory cells, are provided that include a carbon-based reversible resistivity switching material. In particular embodiments, methods in accordance with this invention form a memory cell by (a) depositing a layer of the carbon material above a substrate; (b) doping the deposited carbon layer... Agent: Dugan & Dugan, PC

20100032642 - Method of manufacturing a resistivity changing memory cell, resistivity changing memory cell, integrated circuit, and memory module: According to an embodiment, a method of manufacturing an integrated circuit including a plurality of resistivity changing memory cells is provided. The method includes: forming a stack of layers including a resistivity changing layer, a first conductive layer, a second conductive layer, and a patterned masking layer which are stacked... Agent: Slater & Matsil, L.L.P.

20100032645 - Ac-driven light emitting device having single active layer structure and manufacturing method thereof: The present invention relates to an AC voltage-driven light emitting device having a single active layer of a core-shell structure (p-i-n structure) in which intrinsic semiconductor nanocrystals, exciton combination centers, are uniformly and isotropically distributed around p-type polymer particles, and n-type small molecular particles surround the semiconductor nanocrystals and p-type... Agent: Frommer Lawrence & Haug LLP

20100032646 - Light emitting device: A light emitting device includes: a first layer made of a semiconductor of a first conductivity type; a second layer made of a semiconductor of a second conductivity type; an active layer including a multiple quantum well provided between the first layer and the second layer, impurity concentration of the... Agent: Turocy & Watson, LLP

20100032649 - Light emitting device and reduced polarization interlayer thereof: A light emitting device (LED), in which a reduced polarization interlayer is formed between an electron blocking layer (EBL) and an active layer of the LED, is disclosed. The reduced polarization interlayer is made of AlxInyGa1-x-yN, where 0≦x≦1 and 0≦y≦1.... Agent: Wpat, PC Intellectual Property Attorneys

20100032650 - Light emitting diode having algan buffer layer and method of fabricating the same: The present invention relates to a light emitting diode having an AlxGa1-xN buffer layer and a method of fabricating the same, and more particularly, to a light emitting diode having an AlxGa1-xN buffer layer, wherein between a substrate and a GaN-based semiconductor layer, the AlxGa1-xN (0≦x≦1) buffer layer having the... Agent: H.c. Park & Associates, PLC

20100032648 - Light-emitting device: A light-emitting device with a tunneling structure and a current spreading layer is disclosed. It includes an electrically conductive permanent substrate, an adhesive layer, an epitaxial structure, a tunneling structure and a current spreading layer. The adhesive layer is on the electrically conductive permanent substrate. The epitaxial structure on the... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20100032644 - Nitride semiconductor light-emitting device and nitride semiconductor light-emitting device fabrication method: An active layer (17) is provided so as to emit light having an emission wavelength in the 440 nm to 550 nm band. A first-conductivity-type gallium nitride semiconductor region (13), the active layer (17), and a second-conductivity-type gallium nitride semiconductor region (15) are arranged along a predetermined axis (Ax). The... Agent: Judge Patent Associates

20100032647 - Utlraviolet light emitting devices and methods of fabrication: An ultraviolet light emitting semiconductor chip, its use in a LED, and methods of its fabrication are disclosed. The semiconductor chip can include a buffer layer of AlxGa1-xN, where 0<×≦1 having a thickness from about 10 μm to about 3 mm and defining apertures in the thickness of the buffer... Agent: Dority & Manning, P.A.

20100032652 - Infrared photodetector: An infrared photodetector including a layer structure of an intermediate layer, and a quantum dot layer having a narrower band gap than the intermediate layer and including a plurality of quantum dots alternately stacked, and detecting photocurrent generated when infrared radiation is applied to the layer structure to thereby detect... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20100032651 - Quantum dot infrared photodetector: A quantum dot infrared photodetector includes a quantum dot structure including intermediate layers, and a quantum dot layer sandwiched between the intermediate layers and including quantum dots whose energy potential is low for carriers, the intermediate layers and the quantum dots being formed of a III-V compound semiconductor with the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20100032653 - Carbon nanotube electric field effect transistor and process for producing the same: This invention provides a process for producing a carbon nanotube electric field effect transistor that can improve yield in channel preparation. Carbon nanotubes dispersed in a mixed acid composed of sulfuric acid and nitric acid are subjected to radical treatment with aqueous hydrogen peroxide to cut the carbon nanotubes and... Agent: The Nath Law Group

20100032655 - Field-effect transistor: i

20100032663 - Method and apparatus for simultaneous lateral and vertical patterning of molecular organic films: The disclosure relates to a method and apparatus for micro-patterning organic layers of OLEDs. The disclosed methods do not require applying pressure to the film, nor do they require heat treatment, surface treatment or fast release rate of a stamp from the substrate. The disclosed methods are particularly advantageous over... Agent: Snell & Wilmer LLP (oc)

20100032658 - Novel organic electroluminescent compounds and organic electroluminescent device using the same: The organic electroluminescent compounds according to the invention exhibit high luminous efficiency in blue color and excellent life property as a material, so that an OLED having very good operation life can be prepared therefrom.... Agent: Edwin Oh Rohm And Haas Electronic Materials LLC

20100032661 - Organic field-effect transistor: An organic field-effect transistor includes between an organic semiconductor layer (203) and a gate electrode (204) a polymer membrane (205) having a ion-conducting spatial area (206) between a channel region and the gate electrode. Due to the ion-conducting spatial area (206) a distance between the gate electrode and the organic... Agent: Young & Thompson

20100032660 - Organic thin film transistor, production method thereof, and electronic device: An organic thin film transistor is disclosed, including a substrate formed of an organic insulating layer, a first layer deposited on the substrate using a plating technique to be used for forming a source electrode and a drain electrode, a second layer of a metal material deposited covering the first... Agent: Sonnenschein Nath & Rosenthal LLP

20100032662 - Organic thin film transistors: A method of forming an organic thin film transistor comprising: providing a structure comprising source and drain electrodes with a channel region therebetween, a gate electrode, and a dielectric layer disposed between the source and drain electrodes and the gate electrode; and patterning the dielectric layer using the source and... Agent: Marshall, Gerstein & Borun LLP

20100032657 - Organic transistor: wherein R1 to R10 are independently a hydrogen atom, a halogen atom, an alkyl group which has 4 or less carbon atoms and may be substituted with a halogen atom, an alkoxyl group which has 4 or less carbon atoms and may be substituted with a halogen atom, an amino... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100032656 - Phenylcarbazole compounds, organic light emitting device comprising the phenylcarbazole compounds and flat panel display device comprising the organic light emitting device: where Ar1, Ar2, Ar3, R1, R2 and R3 are as described in the detailed description. Since the compound represented by Formula 1 or 2 has excellent electrical properties and excellent charge transport capabilities, the compound can be efficiently used as a hole injecting material, a hole transporting material, and/or an... Agent: Knobbe Martens Olson & Bear LLP

20100032659 - Semiconductor device and method of fabricating the same: A semiconductor device 1 according to one embodiment of the invention includes: a semiconductor thin film having a light incident plane 30b on which a light is incident and a photodiode portion 30a; an interlayer 62 provided above a surface of the semiconductor thin film on an opposite side of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100032654 - Semiconductor device having silane treated interface: A semiconductor device made on a polymer substrate using graphic arts printing technology uses a printable organic semiconductor. An electrode is situated on the substrate, and a dielectric layer is situated over the electrode. Another electrode(s) is situated on the dielectric layer. The exposed surfaces of the dielectric and the... Agent: Motorola, Inc.

20100032666 - Semiconductor device and manufacturing method thereof: A semiconductor device including thin film transistors having high electrical properties and reliability is proposed. Further, a method for manufacturing the semiconductor devices with mass productivity is proposed. The semiconductor device includes a thin film transistor which includes a gate electrode layer, a gate insulating layer over the gate electrode... Agent: Eric Robinson

20100032665 - Semiconductor device and method for manufacturing the same: An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer... Agent: Eric Robinson

20100032667 - Semiconductor device and method for manufacturing the same: One of the objects of the present invention is to provide a thin film transistor using an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn), in which the contact resistance between the oxide semiconductor layer and a source and drain electrodes is reduced, and to provide a... Agent: Eric Robinson

20100032668 - Semiconductor device and method for manufacturing the same: An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. A metal oxide... Agent: Eric Robinson

20100032664 - Thin film transistor substrate and a fabricating method thereof: An oxide semiconductor thin film transistor substrate includes a gate line and a gate electrode disposed on an insulating substrate, an oxide semiconductor pattern disposed adjacent to the gate electrode, a data line electrically insulated from the gate line, the data line and the gate line defining a display region,... Agent: Cantor Colburn, LLP

20100032671 - Degradation correction for finfet circuits: A pair of split-gate fin field effect transistors (finFETs) in an IC, each containing a signal gate and a control gate, in which an adjustable voltage source, preferably in the form of a digital-to-analog-converter (DAC), is connected to the control gate of one of the finFETs, is disclosed. Threshold measurement... Agent: Texas Instruments Incorporated

20100032670 - Electrical test structure to detect stress induced defects using diodes: A serpentine double gated diode array for monitoring stress induced defects is disclosed. The diode array is configured with adjacent gate segments and gate loops in close proximity to active areas to maximize a sensitivity to stress induced defects. The diode array is compatible with conventional electrical testing. Scanning capacitance... Agent: Texas Instruments Incorporated

20100032669 - Semiconductor integrated circuit capable of controlling test modes without stopping test: A semiconductor integrated circuit capable of controlling test modes without stopping testing of the semiconductor integrated circuit is presented. The semiconductor integrated circuit includes a test mode control unit configured to produce, in response to address decoding signals, a plurality of test mode signals of a first group and a... Agent: Ladas & Parry LLP

20100032672 - Bonding pad, active device array substrate and liquid crystal display panel: A bonding pad includes a metal layer, a gate insulting layer, a passivation layer, and a transparent conductive layer. The metal layer has a first metal pattern and a second metal pattern which are separated from each other. The gate insulating layer covers the metal layer, and the passivation layer... Agent: Jianq Chyun Intellectual Property Office

20100032674 - Display device: An object of the present invention is to provide a display device where small thin film transistors with a lower off current can be formed. The present invention provides a display device where thin film transistors are formed on a substrate, and in the above described thin film transistors, a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20100032673 - Liquid crystal display device: A liquid crystal display device includes a semiconductor layer which is formed of a poly-Si layer and an a-Si layer and formed above a gate electrode with a gate insulating film interposed therebetween. A source electrode or a drain electrode is formed above the semiconductor layer. An n+Si layer is... Agent: Antonelli, Terry, Stout & Kraus, LLP

20100032675 - Component comprising a thin-film transistor and cmos-transistors and methods for production: An electrical component, in the crystalline semiconductor body of which several CMOS transistors in high-voltage or low-voltage technology are formed. The individual CMOS transistors are separated from one another by insulation regions. On one insulation region, a thin-film transistor is formed, having a gate that is realized simultaneously with the... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20100032676 - Semiconductor integrated circuit device and a manufacturing method for the same: Provided is a manufacturing method for a power management semiconductor device or an analog semiconductor device both including a CMOS. According to the method, a substance having high thermal conductivity is additionally provided above a semiconductor region constituting a low impurity concentration drain region so as to expand the drain... Agent: Bruce L. Adams, Esq. Adams & Wilks

20100032677 - Display device: A display device includes gate lines; data lines; charge control lines each including a charge control voltage input pad; first and second thin film transistors (TFTs) each including control and input electrodes connected to the gate and data lines, respectively; a first liquid crystal capacitor connected to an output electrode... Agent: Cantor Colburn, LLP

20100032680 - Display device and manufacturing method thereof: Provided is a display device including: a gate electrode (GT); a semiconductor film (S) which controls a current flowing between a source electrode (ST) and a drain electrode (DT), the semiconductor film including a channel region and two impurity regions formed of regions which sandwich the channel region; two Ohmic... Agent: Antonelli, Terry, Stout & Kraus, LLP

20100032681 - Display device and manufacturing method thereof: A display device includes: a transparent substrate; gate electrodes which are stacked on the transparent substrate; semiconductor films which are stacked above the gate electrodes and constitute thin film transistors together with the gate electrodes; source electrodes and drain electrodes which are formed above the semiconductor films; an insulation film... Agent: Antonelli, Terry, Stout & Kraus, LLP

20100032678 - Light emitting display device and method for fabricating the same: A light emitting display device includes a first electrode formed at a light emitting region of a first substrate; a transparent oxide thin film of about 1 Å to about 200 Å in thickness formed on an entire surface of the first electrode at the light emitting region to substantially... Agent: Holland & Knight LLP

20100032679 - Semiconductor device and display device: A thin film transistor whose threshold voltage can be controlled and which has a favorable switching characteristic is provided. The thin film transistor includes a first gate electrode layer; a semiconductor layer; a first gate insulating layer provided between the first gate electrode layer and the semiconductor layer; source electrode... Agent: Nixon Peabody, LLP

20100032683 - Gan-based semiconductor element: The GaN-based semiconductor element 20 of the present invention comprises the buffer layer 2 formed on the sapphire (0001) substrate 1, the channel layer 3 comprised of the undoped GaN layer, and the electron supply layer 4 comprised of the undoped AlGaN layer. The buffer layer 2 is comprised of... Agent: Kubotera & Associates, LLC

20100032684 - Ion implantation for suppression of defects in annealed sige layers: A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form... Agent: Scully, Scott, Murphy & Presser, P.C.

20100032682 - Large area thin freestanding nitride layers and their use as circuit layers: Thin flat crack-free freestanding nitride layers are fabricated by laser patterning of the interface and/or opposing surface of the nitride layer. The nitride layer is substantially flat once removed from the non-native substrate. The thin flat crack free nitride layers are between 3 and 250 microns thick and can have... Agent: Goldeneye, Inc. Suite 233

20100032686 - Bipolar semiconductor device, method for producing the same, and method for controlling zener voltage: Bipolar semiconductor devices have a Zener voltage controlled very precisely in a wide range of Zener voltages (for example, from 10 to 500 V). A bipolar semiconductor device has a mesa structure and includes a silicon carbide single crystal substrate of a first conductivity type, a silicon carbide conductive layer... Agent: The Webb Law Firm, P.C.

20100032685 - Mesa termination structures for power semiconductor devices and methods of forming power semiconductor devices with mesa termination structures: An electronic device includes a drift layer having a first conductivity type, a buffer layer having a second conductivity type, opposite the first conductivity type, on the drift layer and forming a P—N junction with the drift layer, and a junction termination extension region having the second conductivity type in... Agent: Myers Bigel Sibley & Sajovec, P.A.

20100032687 - Engineered structure for high brightness solid-state light emitters: Electroluminescent (EL) light emitting structures comprises one or more active layers comprising rare earth luminescent centres in a host matrix for emitting light of a particular colour or wavelength and electrodes for application of an electric field and current injection for excitation of light emission. The host matrix is preferably... Agent: Teitelbaum & Maclean

20100032688 - Light-emitting device and method for fabricating the same: A transparent conductive semiconductor substrate 70 comprising a light emitting layer section 24 is directly bonded on one of main surfaces on a main compound semiconductor layer 50 composed of Group III-V compound semiconductor, wherein an alkali metal atom concentration on a bonded boundary surface between the main compound semiconductor... Agent: Arent Fox LLP

20100032689 - Iii-nitride compound semiconductor light emitting device: The present invention discloses a III-nitride compound semiconductor light emitting device having an n-type nitride compound semiconductor layer, an active layer grown on the n-type nitride compound semiconductor layer, for generating light by recombination of electron and hole, and a p-type nitride compound semiconductor layer grown on the active layer.... Agent: Harness, Dickey, & Pierce, P.l.c

20100032693 - Led reflecting plate and led device: A recess is formed in a land (2) of an LED reflecting plate (1) formed of a metal plate. The recess comprises a flat LED chip mounting portion (7) and a reflecting portion (8) inclined with respect to the LED chip mounting portion (7). The LED reflecting plate (1) is... Agent: Blakely Sokoloff Taylor & Zafman LLP

20100032692 - Light emitting device for ac operation: An AC light emitting device, in which a plurality of light emitting cells formed on a substrate are flip-bonded to a submount to be driven under an AC power source is disclosed. The light emitting device comprises a first serial array of light emitting cells, and a second serial array... Agent: H.c. Park & Associates, PLC

20100032690 - Light emitting device with an insulating layer: The present invention is related to a light emitting device with an insulating layer, which comprises a transparent substrate, a first light emitting unit, a second light emitting unit, an insulating layer and a conducting layer. The first light emitting unit and the second light emitting unit are set up... Agent: Sinorica, LLC

20100032691 - Light emitting device, light emitting system having the same, and fabricating method of the light emitting device and the light emitting system: A semiconductor device includes a first light emitting chip, the first light emitting chip having a first semiconductor layer, a second semiconductor layer, and a first active layer disposed therebetween, a second light emitting chip disposed on the first light emitting chip, the second light emitting chip having a third... Agent: F. Chau & Associates, LLC

20100032694 - Light emitting diode with ito layer and method for fabricating the same: The present invention relates to a light emitting diode with enhanced luminance and light emitting performance due to increase in efficiency of current diffusion into an ITO layer, and a method of fabricating the light emitting diode. According to the present invention, there is manufactured at least one light emitting... Agent: H.c. Park & Associates, PLC

20100032695 - Tunable white light based on polarization sensitive light-emitting diodes: A lighting apparatus for emitting polarized white light, which includes at least a first light source for emitting primary light comprised of one or more first wavelengths and having a first polarization direction; and at least a second light source for emitting secondary light in the first polarization direction, comprised... Agent: Gates & Cooper LLP Howard Hughes Center

20100032696 - Light-emitting diode with textured substrate: A light-emitting diode (LED) device is provided. The LED device has raised semiconductor regions formed on a substrate. LED structures are formed over the raised semiconductor regions such that bottom contact layers and active layers of the LED device are conformal layers. The top contact layer has a planar surface.... Agent: Slater & Matsil, L.L.P.

20100032703 - Edge-emitting led assembly: A light-emitting diode (LED) in accordance with the invention includes an edge-emitting LED stack having an external emitting surface from which light is emitted, and a reflective element that is located adjacent to at least one external surface of the LED stack other than the external emitting surface. The reflective... Agent: Kathy Manke Avago Technologies Limited

20100032704 - Led with current confinement structure and surface roughening: An LED having a p-type layer of material with an associated p-contact, an n-type layer of material with an associated n-contact and an active region between the p-type layer and the n-type layer, includes a confinement structure that is formed within one of the p-type layer of material and the... Agent: Koppel, Patrick, Heybl & Dawson

20100032702 - Light-emitting diode housing comprising fluoropolymer: A light-emitting diode housing comprising fluoropolymer is disclosed. The light-emitting diode housing supports a light-emitting diode chip and reflects at least a portion of the light emitted from the light-emitting diode chip.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20100032700 - Light-emitting diodes on concave texture substrate: A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the sidewalls and, optionally, along the surface of the... Agent: Slater & Matsil, L.L.P.

20100032697 - Light-emitting module: A light-emitting module (1) includes: a package (10); a base board (13) and a semiconductor multi-layered film (50) accommodated in the package (10); and a plurality of terminal portions (16) for supplying electricity to the semiconductor multi-layered film (50), wherein the package (10) includes a metallic support portion (11b) supporting... Agent: Hamre, Schumann, Mueller & Larson P.C.

20100032701 - Nitride semiconductor light emitting device and method of manufacturing the same: A nitride semiconductor light-emitting device including a reflecting layer made of a dielectric material, a transparent conductive layer, a p-type nitride semiconductor layer, a light emitting layer and an n-type nitride semiconductor layer in this order and a method of manufacturing the same are provided. The transparent conductive layer is... Agent: Harness, Dickey & Pierce, P.L.C

20100032698 - Particle for display medium and information display panel using same: In the particles for display media used for an information display panel, in which at least one group of display media are sealed between two opposed substrates, at least one of two substrates being transparent, and, in which the display media, to which an electrostatic field is applied, are made... Agent: Sughrue Mion, PLLC

20100032699 - System for high efficiency solid-state light emissions and method of manufacture: In one embodiment of the invention, a bonding material is used to bond a substitute substrate to the LED, wherein the bonding material does not including gold or tin. The bonding material preferably includes gallium (Ga), such as a combination of Ga and Al or Cu. This bonding material has... Agent: Davis Wright Tremaine LLP - San Francisco

20100032708 - Display device and manufacturing method of the same: A plurality of wires and electrodes are formed by forming a first conductive film, selectively forming a resist over the first conductive film, forming a second conductive film over the first conductive film and the resist, removing the second conductive film formed over the resist by removing the resist, forming... Agent: Nixon Peabody, LLP

20100032705 - Light emitting diode package and method of manufacturing the same: Provided is an LED package including a metal substrate that has one or more via holes formed therein; an insulating layer that is formed on a surface of the metal substrate including inner surfaces of the via holes; a plurality of metal patterns that are formed on the insulating layer... Agent: Mcdermott Will & Emery LLP

20100032707 - Semiconductor device and method for making the same: A semiconductor device includes a semiconductor element, an electrode formed on the semiconductor element, and a protective member covering the semiconductor element. The protective member is formed with a through-hole facing the electrode. In the through-hole, a wiring pattern is formed to be electrically connected to the electrode.... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20100032709 - Smd diode holding structure and package thereof: An SMD diode holding structure includes a plastic housing and a plurality of metal holders. Two ends of the plastic housing from a function area and a notch. The metal holder has a base portion and a connecting pin portion. The top and bottom surfaces of the base portion are... Agent: Rosenberg, Klein & Lee

20100032706 - Wafer level led package structure for increasing conductive area and heat-dissipating area and method for making the same: A wafer level LED package structure includes a light-emitting unit, a first conductive unit, a second conductive unit and an insulative unit. The light-emitting unit has a light-emitting body, a positive conductive layer and a negative conductive layer formed on the light-emitting body, and a first insulative layer formed between... Agent: Kile Goekjian Reed & Mcmanus

20100032710 - Deep diffused thin photodiodes: This invention comprises photodiodes, optionally organized in the form of an array, including p+ deep diffused regions or p+ and n+ deep diffused regions. More specifically, the invention permits one to fabricate thin 4 inch and 6 inch wafer using the physical support provided by a n+ deep diffused layer... Agent: Patentmetrix

20100032711 - Semiconductor device and method of manufacturing the same: A p-type region is provided on a first n-type region. A second n-type region is provided on the p-type region, spaced apart from the first n-type region by the p-type region. A gate electrode serves to form an n-channel between the first and second n-type regions. A first electrode is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100032713 - Lateral insulated gate bipolar transistor: Current density in an insulated gate bipolar transistor (L-IGBT) may be increased by adding a second gate, and the corresponding MOS transistors, to the source area, which increases the base current compared to a L-IGBT with a single MOS gate. The current density may be further increased by extending the... Agent: Texas Instruments Incorporated

20100032712 - Power semiconductor device and a method of forming a power semiconductor device: A power semiconductor device has a top surface and an opposed bottom surface below a part of which is a thick portion of semiconductor substrate. At least a portion of a drift region of the device has either no or only a thin portion of semiconductor substrate positioned thereunder. The... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20100032714 - Semiconductor device and protection circuit: In a protection circuit of an input/output terminal I/O, three types of PNP bipolar transistors are included. In a first PNP type bipolar transistor 10A, the emitter thereof is connected to the input/output terminal I/O, the base thereof is connected to a high-potential power supply terminal VDD, and the collector... Agent: Mcginn Intellectual Property Law Group, PLLC

20100032715 - Mos transistor and method for fabricating the same: A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate. Next, the spacer is thinned, and... Agent: North America Intellectual Property Corporation

20100032716 - Semiconductor device: A semiconductor device includes a substrate; a buffer layer; and a compound semiconductor layer laminated on the substrate with the buffer layer in between. The buffer layer has a dislocation density in a plane in parallel to an in-plane direction thereof, so that a volume resistivity of the buffer layer... Agent: Kubotera & Associates, LLC

20100032717 - Devices based on si/nitride structures: A nitride-based semiconductor device is provided. The nitride-base semiconductor device includes a substrate comprising one or more locally etched regions and a buffer layer comprising one or multiple InAlGaN layers on the substrate. A channel layer includes GaN on the buffer layer. A barrier layer includes one or multiple AlGaN... Agent: Gauthier & Connors, LLP

20100032718 - Iii-nitride based semiconductor structure with multiple conductive tunneling layer: A semiconductor structure includes a substrate and a conductive carrier-tunneling layer over and contacting the substrate. The conductive carrier-tunneling layer includes first group-III nitride (III-nitride) layers having a first bandgap, wherein the first III-nitride layers have a thickness less than about 5 nm; and second III-nitride layers having a second... Agent: Slater & Matsil, L.L.P.

20100032719 - Probes for scanning probe microscopy: Disclosed are probes for scanning probe microscopy comprising a semiconductor heterostructure and methods of making the probes. The semiconductor heterostructure determines the optical properties of the probe and allows for optical imaging with nanometer resolution.... Agent: Seunghun Hong Song-pa-gu, Jam-sil-dong, Asia-seon-su-chon

20100032720 - Semiconductor device and radio communication device: A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and... Agent: Antonelli, Terry, Stout & Kraus, LLP

20100032724 - Cell of semiconductor device having sub-193 nanometers-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors: A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by non-active regions. The cell includes a gate electrode level including a number of... Agent: Martine Penilla & Gencarella, LLP

20100032722 - Semiconductor device portion having gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and having at least eight transistors: A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a... Agent: Martine Penilla & Gencarella, LLP

20100032721 - Semiconductor device portion having sub-193 nanometers -sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and having equal number of pmos and nmos transistors: A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line... Agent: Martine Penilla & Gencarella, LLP

20100032723 - Semiconductor device portion having sub-wavelength-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and having at least eight transistors: A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line... Agent: Martine Penilla & Gencarella, LLP

20100032726 - Semiconductor device portion having sub-193 nanometers -sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing and having corres: A semiconductor device includes a substrate portion including a plurality of diffusion regions defined in a non-symmetrical manner relative to a virtual bisecting line. A gate electrode level region above the substrate portion includes a number of conductive features that extend in only a first parallel direction. Adjacent conductive features... Agent: Martine Penilla & Gencarella, LLP

20100032725 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each comprising a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100032727 - Border region defect reduction in hybrid orientation technology (hot) direct silicon bonded (dsb) substrates: Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides... Agent: Texas Instruments Incorporated

20100032728 - Area efficient 3d integration of low noise jfet and mos in linear bipolar cmos process: Analog ICs frequently include circuits which operate over a wide current range. At low currents, low noise is important, while IC space efficiency is important at high currents. A vertically integrated transistor made of a JFET in parallel with an MOS transistor, sharing source and drain diffused regions, and with... Agent: Texas Instruments Incorporated

20100032729 - Integration of high voltage jfet in linear bipolar cmos process: A dual channel JFET which can be integrated in an IC without adding process steps is disclosed. Pinch-off voltage is determined by lateral width of a first, vertical, channel near the source contact. Maximum drain voltage is determined by drain to gate separation and length of a second, horizontal, channel... Agent: Texas Instruments Incorporated

20100032731 - Schottky junction-field-effect-transistor (jfet) structures and methods of forming jfet structures: In accordance with an aspect of the invention, A Schottky junction field effect transistor (JFET) is created using cobalt silicide, or other Schottky material, to form the gate contact of the JFET. The structural concepts can also be applied to a standard JFET that uses N− type or P− type... Agent: Dergosits & Noah LLP (nsc) Counsel For National Semiconductor Corporation

20100032730 - Semiconductor device and method of making the same: A method of making a semiconductor device includes forming a p-type semiconductor region to an n-type semiconductor substrate in such a manner that the p-type semiconductor region is partially exposed to a top surface of the semiconductor substrate, forming a Schottky electrode of a first material in such a manner... Agent: Posz Law Group, PLC

20100032732 - Electrical antifuse having a multi-thickness dielectric layer: An electrical antifuse comprising a field effect transistor includes a gate dielectric having two gate dielectric portions. Upon application of electric field across the gate dielectric, the magnitude of the electrical field is locally enhanced at the boundary between the thick and thin gate dielectric portions due to the geometry,... Agent: Scully, Scott, Murphy & Presser, P.C.

20100032733 - Semiconductor device and manufacturing method thereof: A semiconductor device includes: a semiconductor substrate having an element formation region containing impurities of a first conductivity type; a gate electrode formed on the element formation region with a gate insulating film interposed therebetween; and a silicon alloy layer formed on a lateral side of the gate electrode in... Agent: Mcdermott Will & Emery LLP

20100032735 - Cmos image sensor and manufacturing method thereof: A CMOS image sensor includes isolation regions and a photo diode region formed in a substrate, gate electrodes formed on the substrate, impurity injection regions formed in the substrate respectively positioned between the gate electrodes and the isolation regions, silicide regions formed on upper surfaces of the gate electrodes and... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20100032734 - Miniature image sensor: An image sensor including at least one photodiode and at least one transistor formed in and on a silicon substrate, the assembly of the photodiode and of the transistor being surrounded with a heavily-doped insulating wall, wherein the silicon substrate has a crystal orientation (110).... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20100032736 - Solid-state imaging device and method for manufacturing same: In a CMOS image sensor, an N-type semiconductor layer is formed on a P-type semiconductor substrate. P-type semiconductor regions are formed in one part of the semiconductor layer over the entire length of the thickness direction of the semiconductor layer in a lattice-like shape as viewed from above to compartment... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100032738 - Magnetic memory with strain-assisted exchange coupling switch: A magnetic tunnel junction cell having a free layer and first pinned layer with perpendicular anisotropy, the cell including a coupling layer between the free layer and a second pinned layer, the coupling layer comprising a phase change material switchable from an antiferromagnetic state to a ferromagnetic state. In some... Agent: Campbell Nelson Whipps, LLC

20100032737 - Nano-magnetic memory device and method of manufacturing the device: A nano-magnetic memory device capable of writing/reading multi data in the nano-magnetic memory cell by controlling an amount of an induced current which is formed after a magnetic nanodot is perturbed and rearranged according to a word line current flowing from the first electrode through a nanowire of the nano-magnetic... Agent: Harness, Dickey & Pierce, P.L.C

20100032739 - Methods of forming vertical field effect transistors, vertical field effect transistors, and dram cells: A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at... Agent: Wells St. John P.s.

20100032740 - Semiconductor device and method of manufacturing the same: A semiconductor device that enables placement of a line or the like under a fuse without any additional step and a method of manufacturing the same are provided. The semiconductor device includes a plurality of first capacitor holes made in an insulating layer, a capacitor formed in the first capacitor... Agent: Mcginn Intellectual Property Law Group, PLLC

20100032741 - Semiconductor device and a method of manufacturing the same: A MOS capacitor MOS1 and a MOS capacitor MOS2 are coupled in series between a high potential and a low potential to form a series capacitive element. Then, a polysilicon capacitor PIP1 and a polysilicon capacitor PIP2 are coupled in parallel with the series capacitive element. Specifically, a high-concentration semiconductor... Agent: Miles & Stockbridge PC

20100032742 - Integrated circuits comprising an active transistor electrically connected to a trench capacitor by an overlying contact and methods of making: A method of forming an integrated circuit comprises: providing a semiconductor topography comprising an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench... Agent: Cantor Colburn LLP - IBM Fishkill

20100032743 - Dynamic random access memory structure, array thereof, and method of making the same: A dynamic random access memory (DRAM) structure has a stacked capacitor disposed above an upper source/drain region of a vertical transistor having a surrounding gate. The gates of each row of a memory array are electrically connected with a buried word line. Each of bit lines is disposed between two... Agent: North America Intellectual Property Corporation

20100032744 - Reduced area single poly eeprom: A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations.... Agent: Texas Instruments Incorporated

20100032745 - Semiconductor device and fabricating method thereof: A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source... Agent: Fujitsu Patent Center C/o Cpa Global

20100032746 - Use of dilute steam ambient for improvement of flash devices: The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures... Agent: Knobbe Martens Olson & Bear LLP

20100032747 - Semiconductor memory device and method for manufacturing the same: A semiconductor memory device includes a plurality of memory cell transistors each having a gate electrode section including a charge accumulation layer formed on a semiconductor substrate via a gate insulating film, a first insulating film formed using a material with a higher dielectric constant than the gate insulating film,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100032748 - Cmos thermoelectric refrigerator: A CMOS thermoelectric refrigerator made of an NMOS transistor and PMOS transistor connected in series through a cold terminal is disclosed. Active areas of the NMOS and PMOS transistors are less than 300 nanometers wide, to reduce thermal conduction between the cold terminal and the IC substrate. Drain nodes of... Agent: Texas Instruments Incorporated

20100032749 - Field-effect device and manufacturing method thereof: Embodiments relate to a field-effect transistor that includes a body region, a first source/drain region of a first conductivity type, a second source/drain region of the first conductivity type, and a pocket implant region adjacent to the first source/drain region, the pocket implant region being of a second conductivity type,... Agent: Slater & Matsil LLP

20100032750 - Power semiconductor device and method therefor: A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a... Agent: Hvvi Semiconductors, Inc.

20100032751 - Super-self-aligned trench-dmos structure and method: A semiconductor device includes a P-body layer formed in an N-epitaxial layer; a gate electrode formed in a trench in the P-body and N-epitaxial layer; a top source region formed from the P-body layer next to the gate electrode; a gate insulator disposed along a sidewall of the gate electrode... Agent: Joshua D. Isenberg Jdi Patent

20100032752 - Semiconductor device and method of manufacturing the same: Disclosed herein is a semiconductor device, including: a first semiconductor region of a first conductivity type; a second semiconductor region having pairs of first pillar regions of the first conductivity type, and second pillar regions of a second conductivity type alternately provided; a third semiconductor region of the second conductivity... Agent: Robert J. Depke Lewis T. Steadman

20100032753 - Mos transistor including extended nldd source-drain regions for improved ruggedness: A MOS transistor includes a conductive gate insulated from a semiconductor layer by a dielectric layer, first and second lightly-doped diffusion regions formed self-aligned to respective first and second edges of the conductive gate, a first diffusion region formed self-aligned to a first spacer, a second diffusion region formed a... Agent: Patent Law Group LLP

20100032757 - Bi-directional dmos with common drain: A three terminal bi-directional laterally diffused metal oxide semiconductor (LDMOS) transistor which includes two uni-directional LDMOS transistors in series sharing a common drain node, and configured such that source nodes of the uni-directional LDMOS transistors serve as source and drain terminals of the bi-directional LDMOS transistor. The source is shorted... Agent: Texas Instruments Incorporated

20100032756 - Buried floating layer structure for improved breakdown: A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion... Agent: Texas Instruments Incorporated

20100032755 - Demos transistors with sti and compensated well in drain: A drain extended MOS (DEMOS) transistor with an element of field oxide separating the drain contact from the gate, and a compensation region of opposite polarity in the drain under the gate, is disclosed. The inventive DEMOS may be fabricated in a CMOS IC without adding any process steps. Both... Agent: Texas Instruments Incorporated

20100032754 - Semiconductor device and method of manufacturing the semiconductor device: A semiconductor device includes: a high withstanding voltage transistor (128); a gate electrode (110) formed on a channel region (170); a first conductivity type source region (116a) formed on one side of the channel region (170) and a first conductivity type drain region (116b) formed on another side of the... Agent: Mcginn Intellectual Property Law Group, PLLC

20100032758 - Ldmos device for esd protection circuit: A LDMOS device for an ESD protection circuit is provided. The LDMOS device includes a substrate of a first conductivity type, a deep well region of a second conductivity type, a body region of the first conductivity type, first and second doped regions of the second conductivity type, and a... Agent: J C Patents

20100032759 - self-aligned soi schottky body tie employing sidewall silicidation: A self-aligned Silicon on Insulator (SOI) Schottky Body Tie structure includes: a source region comprising a silicide layer disposed on a top surface of the source region; a drain region comprising a silicide layer disposed on a top surface of the drain region; a gate region disposed above a channel... Agent: Michael Buchenhorner, P.A.

20100032760 - Thin-film transistor substrate and method of fabricating the same: The present invention provides a thin-film transistor (TFT) substrate, which can be fabricated simply and at reduced cost, and a method of fabricating the TFT substrate. The TFT substrate includes: an insulating substrate; gate wiring that extends on the insulating substrate in a first direction; data wiring that extends on... Agent: H.c. Park & Associates, PLC

20100032761 - Semiconductor structure including a high performance fet and a high voltage fet on a soi substrate: A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located... Agent: Scully, Scott, Murphy & Presser, P.C.

20100032762 - Stack-type semiconductor device: A stack-type semiconductor device and a method of manufacturing the same are provided. The stack-type semiconductor device includes an insulation layer on a single-crystalline substrate, a contact plug penetrating the insulation layer to contact the single-crystalline substrate, an upper semiconductor pattern including an impurity region and a gate structure positioned... Agent: Myers Bigel Sibley & Sajovec

20100032763 - Multiple-gate transistors and processes of making same: A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is... Agent: Intel Corporation C/o Cpa Global

20100032765 - Semiconductor device: A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20100032764 - Through silicon via and method of fabricating same: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer... Agent: Schmeiser, Olsen & Watts

20100032766 - Bipolar junction transistor with a reduced collector-substrate capacitance: A process for forming a bipolar junction transistor (BJT) in a semiconductor substrate and a BJT formed according to the process. A buried isolation region is formed underlying BJT structures to isolate the BJT structures from the p-type semi-conductor substrate. To reduce capacitance between a BJT subcollector and the buried... Agent: Agere Lerner, David Et Al.

20100032767 - Structure and method of latchup robustness with placement of through wafer via within cmos circuitry: A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate;... Agent: Greenblum & Bernstein, P.L.C

20100032769 - Implanted well breakdown in high voltage devices: An n-type isolation structure is disclosed which includes an n-type BISO layer in combination with a shallow n-well, in an IC. The n-type BISO layer is formed by implanting n-type dopants into a p-type IC substrate in addition to a conventional n-type buried layer (NBL), prior to growth of a... Agent: Texas Instruments Incorporated

20100032768 - Transistor of image sensor and method for manufacturing the same: A transistor of an image sensor and a method for manufacturing the same include simultaneously forming a device isolation layer at a boundary between a first conductive transistor region having a second conductive well formed therein and a second conductive transistor region having a first conductive well formed therein, and... Agent: Sherr & Vaughn, PLLC

20100032770 - Ic resistor formed with integral heatsinking structure: A resistor is formed on field oxide with a portion of the resistor body configured to overlap an active region in an integrated circuit (IC) substrate to provide heatsinking for the resistor body. In one embodiment, cooling fingers extend from the resistor body beyond the field oxide to overlap the... Agent: Texas Instruments Incorporated

20100032771 - Short-channel schottky-barrier mosfet device and manufacturing method: A MOSFET device and method of fabricating are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device structure to eliminate the requirement for halo/pocket implants and shallow source/drain extensions to control short channel effects. Additionally, the present invention... Agent: Lemaire Patent Law Firm, P.l.l.c.

20100032772 - Semiconductor device: A semiconductor device includes an element isolation film formed on a semiconductor substrate surface of one conductivity type, a gate electrode having one pair of end portions located on a boundary between an element isolation film and an element forming region, a source region and a drain region of a... Agent: Mcginn Intellectual Property Law Group, PLLC

20100032774 - Low cost high voltage power fet and fabrication: A power field effect transistor (FET) is disclosed which is fabricated in as few as six photolithographic steps and which is capable of switching current with a high voltage drain potential (e.g., up to about 50 volts). In a described n-channel metal oxide semiconductor (NMOS) embodiment, a drain node includes... Agent: Texas Instruments Incorporated

20100032773 - Semiconductor devices and methods for manufacturing a semiconductor device: In an embodiment, a semiconductor device is provided. The semiconductor device may include a first diffusion region, a second diffusion region an active region disposed between the first diffusion region and the second diffusion region, a control region disposed above the active region, a first trench isolation disposed laterally adjacent... Agent: Slater & Matsil LLP

20100032775 - Thin-film lid mems devices and methods: Thin film encapsulation devices and methods for MEMS devices and packaging are provided. For a MEMS device encapsulated by a sacrificial layer, a lid layer can be deposited over the MEMS device without touching the MEMS device. The lid layer can be patterned and etched with a distribution of release... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20100032776 - Destructor integrated circuit chip, interposer electronic device and methods: A semiconductor chip includes a first integrated circuit chip and a depression substrate attached to the integrated circuit chip, wherein the integrated circuit chip and the depression substrate define a cavity therebetween. The semiconductor chip also includes a stress sensitive material located in the cavity and a chemical located in... Agent: K&l Gates LLP

20100032777 - Magnetic memory cell construction: A magnetic tunnel junction cell having a free layer, a ferromagnetic pinned layer, and a barrier layer therebetween. The free layer has a central ferromagnetic portion and a stabilizing portion radially proximate the central ferromagnetic portion. The construction can be used for both in-plane magnetic memory cells where the magnetization... Agent: Campbell Nelson Whipps, LLC

20100032778 - Magnetic memory with separate read and write paths: Magnetic memory having separate read and write paths is disclosed. The magnetic memory unit includes a ferromagnetic strip having a first end portion with a first magnetization orientation, an opposing second end portion with a second magnetization orientation, and a middle portion between the first end portion and the second... Agent: Campbell Nelson Whipps, LLC

20100032780 - Mram with eddy current barrier: Disclosed is a magnetoresistive random access memory (“MRAM”) device comprising a plurality of layers on a substrate. The plurality of layers comprises pinning layers, flipping layers, and at least one insulating layer between the pinning layers and the flipping layers. An eddy current side wall encapsulates at least the pinning... Agent: Sughrue Mion, PLLC

20100032779 - Semiconductor device and method of manufacturing the same: This semiconductor device includes a bottom electrode formed over a semiconductor substrate, an MTJ element part formed over a part of the bottom electrode by lamination of a bottom magnetic film, an insulating film, a top magnetic film, and a top electrode in this order, and a protection film formed... Agent: Mcdermott Will & Emery LLP

20100032781 - Camera module and method of manufacturing the same: Provided is a camera module including an image sensor module including a substrate; an image sensor that is mounted on a top surface of the substrate; a ground pad that is disposed on a bottom surface of the substrate; and a sealing member that seals the image sensor mounted on... Agent: Staas & Halsey LLP

20100032782 - Image sensor and method for manufacturing the same: Disclosed are an image sensor and a method of manufacturing the same. The image sensor includes a substrate including a pixel area and a logic circuit area; an interlayer dielectric layer on the substrate and having a trench in the pixel area; and an insulating layer microlens formed in the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20100032783 - Method of fabricating back-illuminated imaging sensors: A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate, and resulting imaging device is disclosed. The method for manufacturing the imaging device includes the steps of providing a substrate comprising an insulator layer, and an epitaxial layer substantially overlying the insulator layer; forming at least one... Agent: Patent Docket Administrator Lowenstein Sandler P.C.

20100032784 - Solid-state image sensor: A solid-state image sensor (1) includes: an imaging device wafer (2A); a plurality of imaging devices (3) which are formed on the imaging device wafer (2A); a spacer (5) which surrounds the imaging devices (3) on the imaging device wafer (2A) and is joined to the imaging device wafer (2A)... Agent: Sughrue Mion, PLLC

20100032785 - Solid-state imaging device and method for manufacturing the same: A solid-state imaging device having a high sensitivity and a structure in which a miniaturized pixel is obtained, and a method for manufacturing the solid-state imaging device in which an interface is stable, a spectroscopic characteristic is excellent and which can be manufactured with a high yield ratio. The solid-state... Agent: Sonnenschein Nath & Rosenthal LLP

20100032786 - Semiconductor device and method for manufacturing the device: A semiconductor device and a method for manufacturing the device include connecting a second wafer to a first wafer, forming a hard mask layer on and/or over a backside of the second wafer, forming a hard mask pattern over the second layer and then forming a via hole by etching... Agent: Sherr & Vaughn, PLLC

20100032787 - Illumination intensity sensor and fabricating method thereof: There is provided an illumination intensity sensor including a first photodiode; a second photodiode; an insulating film, the insulating film including a first insulating film portion above the first photodiode of a first film thickness and a second insulating film portion above the second photodiode of a second film thickness... Agent: Rabin & Berdo, PC

20100032788 - Thermopile sensor and method of manufacturing same: A thermopile sensor for detection of infrared radiation in a measurement wavelength range having a sensor substrate in which a cavity is formed, a diaphragm formed on the sensor substrate above the cavity, at least one thermopile structure formed in, on, or below the diaphragm, having at least one thermopile... Agent: Kenyon & Kenyon LLP

20100032789 - Passive temperature compensation of silicon mems devices: The invention relates to MEMS devices. In one embodiment, a micro-electromechanical system (MEMS) device comprises a resonator element comprising a semiconducting material, and at least one trench formed in the resonator element and filled with a material comprising oxide. Further embodiments comprise additional devices, systems and methods.... Agent: Patterson, Thuente, Skaar & Christensen, P.A.

20100032790 - Rectifier with pn clamp regions under trenches: A structure that includes a rectifier is formed as follows. A trench is formed in a semiconductor region of a first conductivity type. A dielectric layer is formed along opposing sidewalls of the trench but is discontinuous along the bottom of the trench. A doped liner is formed over the... Agent: Townsend And Townsend And Crew, LLP

20100032791 - Semiconductor device and method of manufacturing the same: A semiconductor device includes: a first semiconductor region of a first conductivity type disposed on the side of a first electrode; and a second semiconductor region having first pillar regions of the first conductivity type and second pillar regions of a second conductivity type, the first pillar regions and the... Agent: Robert J. Depke Lewis T. Steadman

20100032792 - Semiconductor device and method of manufacturing the same: A method for manufacturing a semiconductor device includes forming an N-well and a P-well formed in a semiconductor substrate. An isolation layer may be formed in the semiconductor substrate. At least one dummy active pattern may be formed in a boundary area between the N-well and the P-well. A salicide... Agent: Sherr & Vaughn, PLLC

20100032793 - Methods for relaxation and transfer of strained layers and structures fabricated thereby: The present invention provides methods for forming at least partially relaxed strained material layers on a target substrate. The methods include forming islands of the strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment, and transferring the at least... Agent: Winston & Strawn LLP Patent Department

20100032794 - High voltage diode with reduced substrate injection: A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant... Agent: Texas Instruments Incorporated

20100032795 - Design structure for semiconductor device having radiation hardened insulators and structure thereof: A design structure is provided for a semiconductor device having radiation hardened buried insulators and isolation insulators in SOI technology. The device includes a first structure and a second structure. The first structure includes: a radiation hardened BOX layer under an active device layer; radiation hardened shallow trench isolation (STI)... Agent: Greenblum & Bernstein, P.L.C

20100032796 - Integrated circuit structure, design structure, and method having improved isolation and harmonics: Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20100032797 - Electrical fuse and semiconductor device: An electrical fuse comprises: an interconnect to be cut; and a first terminal and a second terminal which are respectively provided at both ends of the interconnect to be cut. The interconnect to be cut comprises: a first orientation film which contains copper as a main component and is oriented... Agent: Mcginn Intellectual Property Law Group, PLLC

20100032798 - Semiconductor device: The semiconductor device includes: a substrate; an electric fuse that includes a lower-layer wiring formed on the substrate, a first via provided on the lower-layer wiring and connected to the lower-layer wiring, and an upper-layer wiring provided on the first via and connected to the first via, a flowing-out portion... Agent: Mcginn Intellectual Property Law Group, PLLC

20100032802 - Assembling of electronic members on ic chip: The objective of this invention is to provide an assembling method for electronic members characterized by the fact that electronic members can be joined reliably and easily without using solder paste. The semiconductor device of the present invention has the following parts: silicon substrate 100 with circuit elements formed on... Agent: Texas Instruments Incorporated

20100032801 - Capacitor formed in interlevel dielectric layer: An capacitor is formed in an interlevel dielectric (ILD) layer of the integrated circuit (IC) by etching vertical trenches through the ILD and depositing conformal layers of a bottom electrode metal, a capacitor dielectric and a top electrode metal. The capacitor can attain a capacitance density of 20 nanofarads/mm2 in... Agent: Texas Instruments Incorporated

20100032800 - Capacitor structure: One or more embodiments relate to a semiconductor device, comprising: a substrate; and a plurality of first conductive vias, the first conductive vias electrically coupled together, each of the first conductive vias passing through the substrate; and a plurality of second conductive vias, the second conductive vias electrically coupled together,... Agent: Infineon Technologies Ag Patent Department

20100032799 - Implementing decoupling capacitors with hot-spot thermal reduction on integrated circuit chips: A method and structures are provided for implementing decoupling capacitors with hot spot thermal reduction on integrated circuit chips including silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, and an active layer carried by... Agent: Ibm Corporation RochesterIPLaw Dept 917

20100032803 - Capacitor contact formed concurrently with bond pad metallization: A method is disclosed for passivating and contacting a capacitor in an IC above a top level of interconnect metallization, without adding process steps. Passivation is accomplished by a dielectric layer, part of the IC protective overcoat, deposited directly on the capacitor, overlapping the electrode edges. Contact is made to... Agent: Texas Instruments Incorporated

20100032804 - High voltage bipolar transistor and method of fabrication: High voltage bipolar transistors built with a BiCMOS process sequence exhibit reduced gain at high current densities due to the Kirk effect. Threshold current density for the onset of the Kirk effect is reduced by the lower doping density required for high voltage operation. The widened base region at high... Agent: Texas Instruments Incorporated

20100032805 - Methods and structures for relaxation of strained layers: The present invention provides methods for relaxing a strained-material layer and structures produced by the methods. Briefly, the methods include depositing a first low-viscosity layer that includes a first compliant material on the strained-material layer, depositing a second low-viscosity layer that includes a second compliant material on the strained-material layer... Agent: Winston & Strawn LLP Patent Department

20100032806 - Epitaxial silicon wafer and production method thereof: e

20100032807 - Wafer level semiconductor module and method for manufacturing the same: A wafer level semiconductor module may include a module board and an IC chip set mounted on the module board. The IC chip set may include a plurality of IC chips having scribe lines areas between the adjacent IC chips. Each IC chip may have a semiconductor substrate having an... Agent: Harness, Dickey & Pierce, P.L.C

20100032809 - Metal wiring structure for integration with through substrate vias: An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled... Agent: Scully, Scott, Murphy & Presser, P.C.

20100032808 - Through wafer via and method of making same: A through wafer via structure. The structure includes: a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of... Agent: Schmeiser, Olsen & Watts

20100032810 - Through wafer vias and method of making same: A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through... Agent: Schmeiser, Olsen & Watts

20100032811 - Through wafer vias and method of making same: A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The structure includes, a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via... Agent: Schmeiser, Olsen & Watts

20100032812 - Method for forming silicon germanium layers at low temperatures, layers formed therewith and structures comprising such layers: A method is provided for controlling the average stress and the strain gradient in structural silicon germanium layers as used in micromachined devices. The method comprises depositing a single silicon germanium layer on a substrate and annealing a predetermined part of the deposited silicon germanium layer. The process parameters of... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20100032813 - Ic formed with densified chemical oxide layer: A semiconductor device, such as an integrated circuit, has an oxide chemically grown on a silicon surface, and densified by annealing at, e.g., 950° C. for 4 to 5 seconds in an N2 ambient, or at an equivalent thermal profile in a similarly non-oxidizing ambient. The densified chemical oxide has... Agent: Texas Instruments Incorporated

20100032814 - Circuit structures and methods with beol layers configured to block electromagnetic edge interference: Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20100032815 - Semiconductor device packages with electromagnetic interference shielding: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element disposed adjacent to a periphery of the substrate unit and at least partially extending between an upper surface and a lower surface... Agent: Cooley Godward Kronish LLP Attn: Patent Group

20100032816 - Electronic device and method of manufacturing same: This application relates to a semiconductor device, the semiconductor device comprising a metal carrier, an insulating foil partially covering the metal carrier, a first chip attached to the metal carrier over the insulating foil, and a second chip attached to the metal carrier over a region not covered by the... Agent: Infineon Technologies Ag Patent Department

20100032819 - Compact co-packaged semiconductor dies with elevation-adaptive interconnection plates: i

20100032818 - Lead frame package: A lead frame package is disclosed where transmission signals are coupled into a die from a pair of lead frames through bonding wires that are separated by no more than three times a diameter of one of the bonding wires. In some embodiments, pairs of lead frames carrying differential transmission... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20100032817 - Semiconductor device with plastic package molding compound, semiconductor chip and leadframe and method for producing the same: A semiconductor device with a plastic package molding compound, a semiconductor chip and a leadframe is disclosed. In one embodiment, the semiconductor chip is embedded in a plastic package molding compound. The upper side of the semiconductor chip and the plastic package molding compound are arranged on a leadframe. Arranged... Agent: Dicke, Billig, & Czaja, PLLC

20100032820 - Stacked memory module: Memory modules, computing systems, and methods of manufacturing memory modules are disclosed. In one embodiment, a memory module includes a substrate having a first side and a second side opposed to the first side. A plurality of pins is disposed on the first side of the substrate. A first plurality... Agent: Slater & Matsil, L.L.P.

20100032821 - Triple tier package on package system: An integrated circuit package system includes: providing a first package having a first interposer mounted over a first integrated circuit and the first integrated circuit encapsulated by a first encapsulation; and connecting a second package over the first interposer and on the first encapsulation, the second package including a second... Agent: Law Offices Of Mikio Ishimaru

20100032822 - Chip package structure: A chip package structure including a first substrate, a chip, a second substrate, a plurality of conductive wires, a plurality of solder balls and a molding compound is provided. The chip is disposed on the first substrate. The second substrate disposed on the chip has an upper surface and a... Agent: J C Patents

20100032823 - Semiconductor device and method of fabricating the same: A semiconductor device includes: a semiconductor substrate having an active area formed on a major surface of the semiconductor substrate; an interlayer insulating film and a wiring layer formed on predetermined regions of the active area; and a sealing resin film covering the interlayer insulating film, the wiring layer, and... Agent: Turocy & Watson, LLP

20100032824 - Ic package method capable of decreasing ir drop and associated ic apparatus: An IC package method capable of decreasing IR drop of a chip and associated IC apparatus is provided. The IC package method comprises forming a lead frame including a die paddle and a plurality of fingers; installing a die on the die paddle, and coupling a plurality of signal terminals... Agent: Wpat, PC Intellectual Property Attorneys

20100032825 - Flange package for a semiconductor device: In accordance with one or more embodiments, a flange package comprises a flange and an interposer having two or more fingers disposed in an interposer trench. The flange has a mold lock formed about a periphery of the interposer trench. A dielectric ring comprising a dielectric material is formed in... Agent: Hvvi Semiconductors, Inc.

20100032827 - Package structure: Disclosed is a package structure including a semiconductor chip disposed in a core board having a first surface and an opposite second surface. The package structure further includes a plurality of first and second electrode pads disposed on an active surface and an opposite inactive surface of the semiconductor chip... Agent: Edwards Angell Palmer & Dodge LLP

20100032826 - Semiconductor package, core layer material, buildup layer material, and sealing resin composition: A flip-chip semiconductor package includes a circuit board having a core layer and at least one buildup layer, a semiconductor device connected to the circuit board through a metal bump, and a cured member that is made of a sealing resin composition and enclosed between the semiconductor device and the... Agent: Ditthavong Mori & Steiner, P.C.

20100032828 - Semiconductor assembly with component attached on die back side: One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal routes being attached to the die... Agent: Law Offices Of Mikio Ishimaru

20100032831 - Bump structure foe semiconductor device: There is provided a bump structure for a semiconductor device, comprising a first metal layer, and a second metal layer electrically connected to the first metal layer so as to be integrally formed with the first metal layer, and electrically connected to electrode pads of the semi-conductor device, in which... Agent: Hosoon Lee

20100032834 - Method for forming bumps in substrates with through vias: A method for manufacturing solder bumps for through vias in a substrate having a first surface and a second surface opposed to each other. The method includes the steps of forming a blind hole extending in the substrate from the first surface for each via and filling each blind hole... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20100032832 - Semiconductor chip and semiconductor device: In this semiconductor chip 3, a table electrode 13 is interposed between a bump electrode 14 and an electrode pad 6. The table electrode 13 is formed by forming a plurality of cores 15 having a smaller Young's modulus than the bump electrode 14, on the electrode pad 6, and... Agent: Hamre, Schumann, Mueller & Larson P.C.

20100032833 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor chip of a multilayer wiring structure having an insulating film formed on a surface thereof, multiple electrode pads formed at a central part and an outer peripheral part of the insulating film, and multiple protective metal layers formed respectively on the electrode pads. The... Agent: Turocy & Watson, LLP

20100032829 - Structures and methods for improving solder bump connections in semiconductor devices: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at... Agent: Greenblum & Bernstein, P.L.C

20100032830 - Three-dimensional conducting structure and method of fabricating the same: The three-dimensional conducting structure comprises a substrate, a first redistributed conductor, a second redistributed conductor and an insulator. The substrate has an active surface, a passive surface opposite to the active one, a pad on the active surface and a through hole. The first redistributed conductor comprises a projecting portion... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100032835 - Combination via and pad structure for improved solder bump electromigration characteristics: The invention generally relates to semiconductor devices, and more particularly to structures and methods for enhancing electromigration (EM) performance in solder bumps and related structures. A semiconductor structure includes a wire comprising first and second wire segments, a pad formed over the wire, and a ball limiting metallization (BLM) layer... Agent: Greenblum & Bernstein, P.L.C

20100032836 - Enhanced reliability for semiconductor devices using dielectric encasement: A method and device for enhanced reliability for semiconductor devices using dielectric encasement is disclosed. The method and device are directed to improving the reliability of the solder joint that connects the integrated circuit (IC) chip to the substrate. The method comprises applying a layer of a photoimageable permanent dielectric... Agent: Greenberg Traurig LLP (la)

20100032838 - Amorphous carbon film, semiconductor device, film forming method, film forming apparatus and storage medium: Provided is an amorphous carbon film having a high elastic modulus and a low thermal contraction rate with a suppressed low dielectric constant, a semiconductor device including the amorphous carbon film and a technology for forming the amorphous carbon film. Since the amorphous carbon film is formed by controlling an... Agent: Pearne & Gordon LLP

20100032839 - Electrode structure, semiconductor element, and methods of manufacturing the same: According to the present invention, there is provided an electrode structure which includes: a nitride semiconductor layer; an electrode provided over the nitride semiconductor layer; and an electrode protective film provided over the electrode, wherein the nitride semiconductor layer contains a metal nitride containing Hb, Hf or Zr as a... Agent: Mr. Jackson Chen

20100032837 - Semiconductor device and semiconductor device manufacturing method: A semiconductor device according to the present invention includes: a semiconductor substrate; a first copper interconnection provided on the semiconductor substrate; an insulating layer provided over the first copper interconnection and having a hole extending therethrough to the first copper interconnection; a barrier layer composed of a tantalum-containing material and... Agent: Rabin & Berdo, PC

20100032840 - Semiconductor device with an improved solder joint: A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA... Agent: Texas Instruments Incorporated

20100032841 - Semiconductor devices and structures thereof: A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is... Agent: Slater & Matsil LLP

20100032842 - Modulated deposition process for stress control in thick tin films: A multi-layer TiN film with reduced tensile stress and discontinuous grain structure, and a method of fabricating the TiN film are disclosed. The TiN layers are formed by PVD or IMP in a nitrogen plasma. Tensile stress in a center layer of the film is reduced by increasing N2 gas... Agent: Texas Instruments Incorporated

20100032844 - Interlayer insulating film, wiring structure and electronic device and methods of manufacturing the same: A wiring structure of a semiconductor device or the like includes an interlayer insulating film having a fluorocarbon film formed on an underlayer, and a conductor buried in the interlayer insulating film. The fluorocarbon film contains nitrogen and is low in dielectric constant, excellent in reproducibility and stable.... Agent: Pearne & Gordon LLP

20100032845 - Semiconductor device having an interconnect structure and a reinforcing insulating film and method of manufacturing such device: A semiconductor device includes in an interconnect structure which includes a first interconnect made of a copper-containing metal, a first Cu silicide layer covering the upper portion of the first interconnect, a conductive first plug provided on the upper portion of the Cu silicide layer and connected to the first... Agent: Young & Thompson

20100032843 - Through silicon via layout: A system and method for forming under bump metallization layers that reduces the overall footprint of UBMs, through silicon vias, and trace lines is disclosed. A preferred embodiment comprises forming an under bump metallization layer over a plurality of through silicon vias, whereas the UBM is connected to only a... Agent: Slater & Matsil, L.L.P.

20100032846 - Ic having viabar interconnection and related method: An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a... Agent: Hoffman Warnick LLC

20100032847 - Method for forming a package-on-package structure: A method for forming a package-on-package structure is disclosed. The method comprises the step of providing a first semiconductor package. The first semiconductor package has at least one encapsulation layer formed on at least one side of the first semiconductor package. The method also involves the step of securing the... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20100032848 - Bond pad structure and method for producing same: It is described a bond pad structure and a method for producing the same, the bond pad structure (1), comprising: a substrate (3) having a surface (17) to be electrically contacted; a first isolator layer (5) contacting the surface (17) of the substrate in a first region (a); a first... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100025654 - Light-emitting diode in semiconductor material and its fabrication method: P

20100025652 - Multiple quantum-well structure, radiation-emitting semiconductor base and radiation-emitting component: A multiple quantum well structure (1) which comprises at least a first quantum well structure (2a) for generating radiation of a first wavelength (6) and at least a second quantum well structure (2b) for generating radiation of a second wavelength (7), which is greater than the first wavelength (6), and... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20100025657 - Nitride semiconductor device: A nitride semiconductor device including a light emitting device comprises a n-type region of one or more nitride semiconductor layers having n-type conductivity, a p-type region of one or more nitride semiconductor layers having p-type conductivity and an active layer between the n-type region and the p-type region. In such... Agent: Birch Stewart Kolasch & Birch

20100025655 - Photon tunneling light emitting diodes and methods: Embodiments described herein include LEDs that promote photon tunneling. One embodiment of an LED device can have a quantum well layer adapted to generate light having a wavelength, a p-doped alloy layer on a first side of the quantum well layer and an n-doped alloy layer on the other side... Agent: SprinkleIPLaw Group

20100025653 - Tunable wavelength light emitting diode: A light emitting diode and a method of fabricating a light emitting diode, the diode has a first set of multiple quantum wells (MQWs), each of the MQWs of the first set comprising a wetting layer providing nucleation sites for quantum dots (QDs) or QD-like structures in a well layer... Agent: Volpe And Koenig, P.C.

20100025656 - White light devices using non-polar or semipolar gallium containing materials and phosphors: A packaged light emitting device. The device includes a substrate member comprising a surface region and one or more light emitting diode devices overlying the surface region. In a specific embodiment, at least one of the light emitting diode device is fabricated on a semipolar or nonpolar GaN containing substrate.... Agent: Townsend And Townsend And Crew, LLP

20100025658 - Lithographic process using a nanowire mask, and nanoscale devices fabricated using the process: The disclosure pertains to a method for making a nanoscale filed effect transistor structure on a semiconductor substrate. The method comprises disposing a mask on a semiconductor upper layer of a multi-layer substrate, and removing areas of the upper layer not covered by the mask in a nanowire lithography process.... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20100025659 - Non-volatile electromechanical field effect devices and circuits using same and methods of forming same: Under one aspect, a field effect device includes a gate, a source, and a drain, with a conductive channel between the source and the drain; and a nanotube switch having a corresponding control terminal, said nanotube switch being positioned to control electrical conduction through said conductive channel. Under another aspect,... Agent: Wilmerhale/boston

20100025660 - Semiconductor devices, methods of manufacture thereof and articles comprising the same: Disclosed herein is a device comprising a source region, a drain region and a gate layer; the source region, the drain region and the gate layer being disposed on a semiconductor host; the gate layer being disposed between source and drain regions; the gate layer comprising a first gate-insulator layer;... Agent: Cantor Colburn, LLP

20100025669 - Amine-based compound, organic light emitting device comprising the amine-based compound, and flat panel display device including the organic light emitting device: The invention is directed to an amine-based compound represented by Formula 1, an organic light emitting device with an organic film including the same, and a flat panel display device including the organic light emitting device.... Agent: Christie, Parker & Hale, LLP

20100025663 - Efficient solar cells using all-organic nanocrystalline networks: An optoelectronic device and a method of fabricating a photosensitive optoelectronic device includes depositing a first organic semiconductor material on a first electrode to form a continuous first layer; depositing a layer of a second organic semiconductor material on the first layer to form a discontinuous second layer, portions of... Agent: Mcdermott Will & Emery LLP

20100025671 - Electroluminescent devices: The invention relates to an optical light emitting diode device having an electroluminescent layer and an electron transport layer, wherein the electron transport layer contains zirconium or hafnium quinolate for slowing loss of luminance at a given current density with increase of the time for which the device has been... Agent: Connolly Bove Lodge & Hutz, LLP

20100025662 - High density coupling of quantum dots to carbon nanotube surface for efficient photodetection: The present invention relates to a method of preparing a carbon nanotube-quantum dot conjugate having a high density of quantum dots (QDs) on its surface. This method involves providing a plurality of semiconductor quantum dots and providing a thiol-functionalized carbon nanotube having a plurality of terminal thiol groups on its... Agent: Nixon Peabody LLP - Patent Group

20100025661 - Luminescent material and organic electroluminescent device using the same: wherein R1 to R7 are independently hydrogen, alkyl or cycloalkyl; Ar1 is one selected from the group consisting of non-condensed aryl having 6 to 50 carbon atoms, 2-naphthyl, 9-phenanthryl, 6-chrysenyl, 2-triphenylenyl, 2-fluorenyl, 9-carbazolyl, 2-thienyl and 2-benzothienyl; and Ar2 and Ar3 are independently non-condensed aryl having 6 to 50 carbon atoms,... Agent: Wenderoth, Lind & Ponack, L.L.P.

20100025667 - Organic field effect transistor and method of manufacturing the same: The present invention discloses an organic field effect transistor and a manufacturing method thereof. The organic field effect transistor comprises a top-contact type or a bottom-contact type, and the manufacturing method thereof comprises the following steps: a substrate is provided, a metal gate is formed on the substrate, an inorganic... Agent: Hudak, Shunk & Farine, Co., L.p.a.

20100025664 - Organic light emitting diode display: An organic light-emitting diode (“OLED”) display includes a first thin film transistor disposed on a substrate; a first insulating layer disposed on the first thin film transistor; a reflective electrode disposed on the first insulating layer; a common voltage line disposed on the first insulating layer and separated from the... Agent: Cantor Colburn, LLP

20100025665 - Organic photosensitive devices using subphthalocyanine compounds: An organic photosensitive optoelectronic device, having a donor-acceptor heterojunction of a donor-like material and an acceptor-like material and methods of making such devices is provided. At least one of the donor-like material and the acceptor-like material includes a subphthalocyanine, a subporphyrin, and/or a subporphyrazine compound; and/or the device optionally has... Agent: Duane Morris LLP - Ny Patent Department

20100025670 - Organic thin film transistor and organic thin film light emitting transistor: An organic thin film transistor including a substrate having thereon at least three terminals of a gate electrode, a source electrode and a drain electrode, an insulator layer and an organic semiconductor layer, with a current between a source and a drain being controlled upon application of a voltage to... Agent: Millen, White, Zelano & Branigan, P.C.

20100025666 - Organic thin film transistor and organic thin film transistor manufacturing process:

20100025668 - Organic transistor and method for fabricating a dielectric layer of such a transistor: According to the invention, the dielectric layer comprises a layer of a first dielectric material having a dielectric permittivity of less than four in which there is formed, at least between said opposite-facing surfaces, a volume of a second material, said volume having an overall cross-section which tapers from gate... Agent: Marjama Muldoon Blasiak & Sullivan LLP

20100025672 - Thin-film laminate and organic transistor using the same: An organic transistor includes a semiconductor section that includes a thin-film laminate in which a first organic thin film and a second organic thin film are alternately stacked. The thin-film laminate includes at least two layers of the first organic thin film. The first organic thin film is a pentacene... Agent: Harness, Dickey & Pierce, P.L.C

20100025673 - Light emitting diode and method for manufacturing the same: The present invention relates to a light emitting diode (100, 109), comprising at least one p-doped structure, a plurality of n-doped zinc-oxide (ZnO) nanowires (104) arranged on the at least one p-doped structure, thereby forming a plurality of p-n junctions (107a, 107b), an insulating structure (105) arranged among the plurality... Agent: Harness, Dickey & Pierce, P.L.C

20100025674 - Oxide semiconductor and thin film transistor including the same: An oxide semiconductor and a thin film transistor (TFT) including the same. The oxide semiconductor may be obtained by adding hafnium (Hf) to gallium-indium-zinc oxide (GIZO) and may be used as a channel material of the TFT.... Agent: Harness, Dickey & Pierce, P.L.C

20100025676 - Semiconductor device and manufacturing method thereof: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is... Agent: Eric Robinson

20100025677 - Semiconductor device and manufacturing method thereof: To provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability and a manufacturing method of the semiconductor device with high mass productivity. The summary is that an inverted-staggered (bottom-gate) thin film transistor is included in which an oxide semiconductor film containing In, Ga,... Agent: Eric Robinson

20100025675 - Semiconductor device and method for manufacturing the same: In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including In, Ga, and Zn for an inverted staggered thin film transistor, variation in... Agent: Eric Robinson

20100025678 - Semiconductor device and method for manufacturing the same: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn... Agent: Eric Robinson

20100025679 - Semiconductor device and method for manufacturing the same: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer... Agent: Eric Robinson

20100025680 - Thin-film transistor and method of manufacturing the same: In a thin-film transistor comprising respective elements of: three electrodes of a source electrode, a drain electrode and a gate electrode; a channel layer; and a gate insulating film, at least the channel layer is formed by a metal oxide film including indium. Therefore, it is possible to obtain the... Agent: Sughrue Mion, PLLC

20100025681 - Ic chip package and image display device incorporating same: A liquid crystal driver mounting package in accordance with an embodiment of the present invention contains a film base material and a liquid crystal driver connected to each other via an interposer. The liquid crystal driver includes first alignment marks on its face opposite the interposer. The interposer includes second... Agent: Harness, Dickey & Pierce, P.L.C

20100025682 - Interface device for wireless testing, semiconductor device and semiconductor package including the same, and method for wirelessly testing using the same: In an interface device for wireless testing capable of testing a semiconductor chip in a non-contact manner, a semiconductor device and a semiconductor package including the same, and a method for wirelessly testing a semiconductor device using the same are provided, the interface device for wireless testing includes an interface... Agent: Mills & Onello LLP

20100025684 - Method for producing group iii nitride semiconductor layer, group iii nitride semiconductor light-emitting device, and lamp: The present invention is a method for producing a group III nitride semiconductor layer in which a single crystal group III nitride semiconductor layer (103) is formed on a substrate (101), the method including: a substrate processing step of forming, on the (0001) C-plane of the substrate (101), a plurality... Agent: Sughrue Mion, PLLC

20100025683 - Reduction of edge effects from aspect ration trapping: A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduce edge... Agent: Amberwave System Corp.

20100025685 - Method and apparatus for forming contact hole: A method of forming a contact hole in an insulating film coating amorphous Si having an irregular surface formed on an insulating substrate, for connecting the amorphous Si to a conductor film formed on the insulating film includes etching the insulating film using reactive ion etching to a depth whereat... Agent: Mcginn Intellectual Property Law Group, PLLC

20100025686 - Semiconductor device with amorphous silicon monos memory cell structure and method for manufacturing thereof: A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the... Agent: Townsend And Townsend And Crew, LLP

20100025687 - Image sensor and method for manufacturing the same: An image sensor and a method for manufacturing the same are provided. The image sensor comprises a readout circuitry, a first interlayer dielectric with an interconnection therein, a second interlayer dielectric, an image sensing device, and a contact plug. The readout circuitry is formed in a first substrate. The first... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20100025688 - Semiconductor element and display device using the same: Provided is a semiconductor element including: a semiconductor having an active layer; a gate insulating film which is in contact with the semiconductor; a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film formed over the active layer, a photosensitive organic resin... Agent: Nixon Peabody, LLP

20100025689 - Thin film transisitor array panel and manufacturing tmethod thereof: A thin film transistor array panel according to an embodiment includes: a substrate; a plurality of gate line formed on the substrate; a plurality of first capacitor electrodes formed on the substrate and separated from the gate lines; a plurality of data line intersecting the gate lines; a plurality of... Agent: Innovation Counsel LLP

20100025690 - Thin film transistor substrate and method of manufacturing the same: A thin film transistor substrate includes an insulating plate, a plurality of fan-out lines arranged on the insulating plate and including at least a pair of adjacent fan-out lines, a plurality of signal lines connected to the plurality of fan-out lines, and a plurality of thin film transistors connected to... Agent: H.c. Park & Associates, PLC

20100025692 - Pixel structure: A pixel structure formed on a substrate and electrically connected with a scan line and a data line, and including a semiconductor pattern and a pixel electrode is provided. The semiconductor pattern includes at least two channel areas, at least one doping area, a source area, and a drain area.... Agent: Jianq Chyun Intellectual Property Office

20100025691 - Semiconductor device and production method thereof: The present invention provides a semiconductor device having a high breakdown voltage and high reliability even if a gate electrode is formed to be thin. The present invention is a semiconductor device including a polycrystal semiconductor layer, a gate insulating film, and a gate electrode, stacked on an insulating substrate... Agent: Nixon & Vanderhye, PC

20100025694 - Apparatus and method for transformation of substrate: A method is disclosed for forming a layer of a wide bandgap material in a non-wide bandgap material. The method comprises providing a substrate of a non-wide bandgap material and converting a layer of the non-wide bandgap material into a layer of a wide bandgap material. An improved component such... Agent: Robert F. Frijouf Frijouf, Rust & Pyle, P.A.

20100025693 - Wide band gap semiconductor device including junction field effect transistor: A wide band gap semiconductor device has a transistor cell region, a diode forming region, an electric field relaxation region located between the transistor cell region and the diode forming region, and an outer peripheral region surrounding the transistor cell region and the diode forming region. In the transistor cell... Agent: Posz Law Group, PLC

20100025695 - Annealing method for semiconductor device with silicon carbide substrate and semiconductor device: In an atmosphere in which a silicon carbide (SiC) substrate implanted with impurities is annealed to activate the impurities, by setting a partial pressure of H2O to be not larger than 10−2 Pa, preferably not larger than 10−3 Pa, surface irregularity of the silicon carbide (SiC) substrate is controlled to... Agent: Fitzpatrick Cella Harper & Scinto

20100025696 - Process for producing a silicon carbide substrate for microelectric applications:

20100025697 - Optical module: An optical module of the present invention includes a semiconductor device, a grounded metal member for mounting the semiconductor device thereon, a substrate for mounting the grounded metal member thereon, and a lead pin fixed to and insulated from the grounded metal member and soldered to the substrate. The lead... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100025698 - Display panel and method for manufacturing the same: A display panel includes a substrate having a display area and a blank area. The blank area includes at least one of a non-metal line region and a metal-line region. The non-metal line region includes a plurality of insulating patterns and a first conductive pattern layer formed on the substrate.... Agent: Rabin & Berdo, PC

20100025699 - Light emitting diode chip package: A light emitting diode (LED) chip package is provided. The LED chip package comprises a carrier, a first LED chip, a second LED chip and an encapsulant. The first LED chip is disposed on and electrically connected to the carrier, wherein the first LED chip is adapted for emitting a... Agent: Jianq Chyun Intellectual Property Office

20100025700 - Warm white light emitting apparatus and back light module comprising the same: A warm white light emitting apparatus includes a first light emitting diode (LED)-phosphor combination to generatea base light that is white or yellowish white and a second LED-phosphor combination to generate a Color Rendering Index (CRI) adjusting light. The base light the CRI adjusting light together make a warm white... Agent: H.c. Park & Associates, PLC

20100025701 - Method of fabricating nitride-based semiconductor light-emitting device and nitride-based semiconductor light-emitting device: A nitride-based semiconductor light-emitting device capable of suppressing reduction of characteristics and a yield and method of fabricating the same is described. The method of fabricating includes the steps of forming a groove portion on a nitride-based semiconductor substrate by selectively removing a prescribed region of a second region of... Agent: Ndq&m Watchstone LLP

20100025702 - Substrate-free flip chip light emitting diode: A substrate-free LED device is provided. The LED device comprises a substrate, an epitaxial layer disposed on the substrate, a first electrode disposed on a portion of the epitaxial layer, a second electrode disposed on another portion of the epitaxial layer, and a protection layer, disposed over the epitaxial layer.... Agent: J C Patents

20100025703 - Conductive polymer compositions in opto-electrical devices: A conductive polymer composition comprising a conductive polymer in a solid polyelectrolyte.... Agent: Marshall, Gerstein & Borun LLP

20100025704 - High efficiency lighting device: A method for fabricating a high efficiency lighting device and the structure thereof are disclosed. The method includes the following steps: providing a light emitting diode structure; attaching a distributed-Bragg reflecting layer (DBR) to the light emitting diode structure by vapor deposition; and connecting the light emitting diode structure to... Agent: Snell & Wilmer L.L.P. (main)

20100025705 - High efficiency lighting device and manufacturing method thereof: A high efficiency luminous device and a manufacturing method thereof are disclosed. The high efficiency luminous device includes a LED structure, a first metal electrode, and a second metal electrode. The LED structure is for emitting light. The first metal electrode is formed on the LED structure, and the first... Agent: Snell & Wilmer L.L.P. (main)

20100025717 - Highly efficient gallium nitride based light emitting diodes via surface roughening: A gallium nitride (GaN) based light emitting diode (LED), wherein light is extracted through a nitrogen face (N-face) of the LED and a surface of the N-face is roughened into one or more hexagonal shaped cones. The roughened surface reduces light reflections occurring repeatedly inside the LED, and thus extracts... Agent: Gates & Cooper LLP Howard Hughes Center

20100025709 - Light emitting device: A light emitting device includes a light emitting element, a sealing material for sealing the light emitting element, a first filler included in the sealing material, and a second filler included in the sealing material. The second filler includes a particle diameter smaller than that of the first filler.... Agent: Mcginn Intellectual Property Law Group, PLLC

20100025714 - Light-emitting device containing a composite electroplated substrate: The application is related to a method of forming a substrate of a light-emitting diode by composite electroplating. The application illustrates a light-emitting diode comprising the following elements: a light-emitting epitaxy structure, a reflective layer disposed on the light-emitting epitaxy structure, a seed layer disposed on the reflective layer, a... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20100025716 - Lighting system: It is an object of the present invention to provide a lighting system having favorable luminance uniformity in a light-emitting region when the lighting system has large area. According to one feature of the invention, a lighting system comprises a first electrode, a second electrode, a layer containing a light-emitting... Agent: Fish & Richardson P.C.

20100025708 - Lumped plasmonic \"diode\" and lumped plasmonic \"rectifier\" for optical field rectification and lumped optical second harmonic generation: A lumped nanocircuit element design at IR and optical frequencies is provided that can effectively act as a lumped “diode” and a lumped “rectifier” for rectifying optical field displacement currents or optical electric field. The lumped nanocircuit element design can also act as a lumped second harmonic generator. The element... Agent: Woodcock Washburn LLP

20100025706 - Nanoparticle based inorganic bonding material: l

20100025711 - Optical bonding composition for led light source: An optical bonding composition and LED light source comprising the composition are disclosed, as well as a method of making the LED light source. The LED light source may comprise: an LED die; an optical element optically coupled to the LED die; and a bonding layer comprising an amorphous organopolysiloxane... Agent: 3m Innovative Properties Company

20100025707 - Optical element, radiation-emitting component and method for producing an optical element: An optical element comprising includes a base body containing a base material, and a filling body containing a filling material, wherein the filling body adheres to the base body. A radiation-emitting component and a method for producing an optical element are futhermore described.... Agent: Slater & Matsil, L.L.P.

20100025712 - Semiconductor component and associated production method: The present invention relates to a semiconductor component and an associated production method, said component emitting at least two defined wavelengths with a defined intensity ratio. It is an object of the present invention to specify an optical semiconductor component and an associated production method, said component emitting at least... Agent: Nixon Peabody LLP

20100025710 - Semiconductor device and fabrication method thereof: There is provided a semiconductor device including: a semiconductor chip having a penetrating electrode penetrating through from a first main surface of the semiconductor chip to a second main surface on the opposite side thereof, a photoreceptor portion formed on the first main surface, and a first wire at a... Agent: Rabin & Berdo, PC

20100025715 - Ultra dark polymer: A method and a material for creating an antireflective coating on an integrated circuit. A preferred embodiment comprises applying a dark polymer material on a reflective surface, curing the dark polymer material, and roughening a top surface of the dark polymer material. The roughening can be achieved by ashing the... Agent: Texas Instruments Incorporated

20100025713 - Wafer-scaled light-emitting structure: This invention discloses a wafer-scaled light-emitting structure comprising a supportive substrate; an anti-deforming layer; a bonding layer; and a light-emitting stacked layer, wherein the anti-deforming layer reduces or removes the deformation like warp caused by thinning of the substrate.... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20100025719 - Bond pad design for enhancing light extraction from led chips: An improved bond pad design for increased light extraction efficiency for use in light emitting diodes (LEDs) and LED packages. Embodiments of the present invention incorporate a structure that physically isolates the bond pads from the primary emission surface, forcing the current to flow away from the bond pads first... Agent: Koppel, Patrick, Heybl & Dawson

20100025722 - Light emitting device, its manufacturing method and its mounted substrate: A light emitting device according to the invention includes: a package including a generally quadrangular light emitting surface with a recess formed therein, a rear surface opposed to the light emitting surface, a first side surface generally orthogonal to the light emitting surface and the rear surface, and a second... Agent: Pearne & Gordon LLP

20100025721 - Optical semiconductor device module having leaf springs with different rectangularly-shaped terminals: In an optical semiconductor device module constructed by an optical semiconductor device having a light emitting portion on its top surface, a mounting substrate adapted to mount the optical semiconductor device thereon, and at least one conductive leaf spring adapted to fix the optical semiconductor device to the mounting substrate... Agent: Cermak Kenealy Vaidya & Nakajima LLP

20100025723 - Package for protecting a device from ambient substances: A package (1; 20) for protecting a device (2; 21) from ambient substances, the package comprising an enclosure surrounding the device (2; 21). The enclosure includes a multi-layer barrier (7; 24) and an internal substance binding member (14; 27) which is provided inside the enclosure to bind at least one... Agent: Philips Intellectual Property & Standards

20100025720 - Packaging structure and method for light-emitting diode: The present invention discloses a packaging structure for light-emitting diode, which comprises a grain to provide electroluminescence; a solder paste layer disposed on the bottom and perimeter of the grain to connect the grain with at least one support; and a heat-conducting layer disposed at the bottom of the grain... Agent: Guice Patents PLLC

20100025718 - Top contact led thermal management: An LED having enhanced heat dissipation is disclosed. For example, an LED die can have extended bond pads that are configured to enhance heat flow from an active region of the LED to a lead frame. A heat transmissive substrate can further enhance heat flow away from the LED die.... Agent: Haynes And Boone, LLPIPSection

20100025724 - Resin composition for led encapsulation: Disclosed is a resin composition for LED encapsulation including an organic oligosiloxane hybrid prepared by non-hydrolytic condensation of organoalkoxysilane. More particularly, the resin composition for LED encapsulation includes an organic oligosiloxane hybrid prepared by non-hydrolytic condensation of organoalkoxysilane with organosilanediol or non-hydrolytic condensation of a mixture containing organoalkoxysilane and metal... Agent: Tips Group C/o Intellevate LLC

20100025725 - Semiconductor device and method for production thereof: A semiconductor device has a drift region (20) (third semiconductor region) of an n-type (first conductivity type); a body region (50) (second semiconductor region) of a p-type (second conductivity type) provided on the drift region (20); an emitter region (60) (first semiconductor region) of the n-type formed in the top... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20100025726 - Lateral devices containing permanent charge: A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.... Agent: Groover & Associates

20100025727 - Enhanced spontaneous separation method for production of free-standing nitride thin films, substrates, and heterostructures: The present invention provides a superior method for the removal of nitride semiconductor thin films, thick films, heterostructures, and bulk material from initial substrates and/or templates. The method utilizes specially patterned mask layers between the initial substrates/templates and the nitride semiconductors to decrease adhesion between the nitride semiconductor and underlying... Agent: Black Lowe & Graham, PLLC

20100025728 - Relaxation and transfer of strained layers: The invention relates to a process for fabricating a heterostructure. This process is noteworthy in that it comprises the following steps: a) a strained crystalline thin film is deposited on, or transferred onto, an intermediate substrate; b) a strain relaxation layer, made of crystalline material capable of being plastically deformed... Agent: Traskbritt, P.C.

20100025729 - Passivated iii-v field effect structure and method: An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20100025730 - Normally-off semiconductor devices and methods of fabricating the same: Normally-off semiconductor devices are provided. A Group III-nitride buffer layer is provided. A Group III-nitride barrier layer is provided on the Group III-nitride buffer layer. A non-conducting spacer layer is provided on the Group III-nitride barrier layer. The Group III-nitride barrier layer and the spacer layer are etched to form... Agent: Myers Bigel Sibley & Sajovec, P.A.

20100025731 - Cell of semiconductor device having gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and equal number of pmos and nmos transistors: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common... Agent: Martine Penilla & Gencarella, LLP

20100025733 - Cell of semiconductor device having sub-193 nanometers-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and at least eight transistors: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in... Agent: Martine Penilla & Gencarella, LLP

20100025732 - Cell of semiconductor device having sub-wavelength-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and at least eight transistors: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common... Agent: Martine Penilla & Gencarella, LLP

20100025736 - Cell of semiconductor device having gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and at least eight transistors: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common... Agent: Martine Penilla & Gencarella, LLP

20100025735 - Cell of semiconductor device having sub-193 nanometers-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and equal number of pmos and nmos transistors: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in... Agent: Martine Penilla & Gencarella, LLP

20100025734 - Cell of semiconductor device having sub-wavelength-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and equal number of pmos and nmos transistors: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common... Agent: Martine Penilla & Gencarella, LLP

20100025737 - Field-effect transistor: A field-effect transistor according to the present invention includes a source electrode that is formed in an active region, and a drain electrode that is formed in the active region. Further, the field-effect transistor includes a gate electrode that is formed in the active region and disposed between the source... Agent: Mcginn Intellectual Property Law Group, PLLC

20100025738 - Solid-state imaging device with vertical gate electrode and method of manufacturing the same: A charge accumulation region of a first conductivity type is buried in a semiconductor substrate. A charge transfer destination diffusion layer of the first conductivity type is formed on a surface of the semiconductor substrate. A transfer gate electrode is formed on the charge accumulation region, and charge is transferred... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100025739 - Semiconductor device with large blocking voltage and method of manufacturing the same: A normally-off type junction FET in which a channel resistance is reduced without lowering its blocking voltage is provided. In a junction FET formed with using a substrate made of silicon carbide, an impurity concentration of a channel region (second epitaxial layer) is made higher than an impurity concentration of... Agent: Mattingly & Malur, P.C.

20100025745 - Method of forming a low capacitance semiconductor device and structure therefor: In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.... Agent: Mr. Jerry Chruma Semiconductor Components Industries, L.L.C.

20100025740 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device comprises forming a partial-insulated substrate comprising an insulating region located below both a channel region of a cell transistor and one of a storage node contact region and a bit line contact region, and forming a cell transistor comprising a fin region on... Agent: Marshall, Gerstein & Borun LLP

20100025744 - Semiconductor device and method of manufacturing same: A semiconductor device includes a gate electrode over a semiconductor substrate, a channel region provided in the semiconductor substrate below the gate electrode, and a strain generation layer configured to apply stress to the channel region, the strain generation layer being configured to apply greater stress in absolute value to... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20100025741 - Semiconductor memory device and method of fabricating the same: The present invention discloses a method of fabricating a semiconductor memory device including forming sequentially a gate insulating layer and a first conductive pattern on a semiconductor substrate; forming a protective layer on surfaces of the first conductive pattern and the gate insulating layer; performing an etching process to form... Agent: Marshall, Gerstein & Borun LLP

20100025742 - Transistor having a strained channel region caused by hydrogen-induced lattice deformation: A lattice distortion may be achieved by incorporating a hydrogen species into a semiconductor material, such as silicon, without destroying the lattice structure. For example, by incorporating the hydrogen species on the basis of an electron shower, a tensile strain component may be obtained in the channel of N-channel transistors.... Agent: Williams, Morgan & Amerson

20100025743 - Transistor with embedded si/ge material having enhanced boron confinement: By incorporating a diffusion hindering species at the vicinity of PN junctions of P-channel transistors comprising a silicon/germanium alloy, diffusion related non-uniformities of the PN junctions may be reduced, thereby contributing to enhanced device stability and increased overall transistor performance. The diffusion hindering species may be provided in the form... Agent: Williams, Morgan & Amerson

20100025746 - Methods, structures and systems for interconnect structures in an imager sensor device: Methods, structures and systems for a substantially non-light blocking conductive interconnect structure for an imager sensor device.... Agent: Treyz Law Group

20100025747 - Method for initializing ferroelectric memory device, ferroelectric memory device, and electronic equipment: A method for initializing a ferroelectric memory device is provided. The method includes the steps of: packaging a ferroelectric memory device having memory cells arranged in an array, each of the memory cells having a ferroelectric film disposed between a lower electrode and an upper electrode; applying a potential between... Agent: Harness, Dickey & Pierce, P.L.C

20100025748 - Semiconductor device with a dynamic gate-drain capacitance: A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer... Agent: Dicke, Billig & Czaja

20100025749 - Semiconductor device: A semiconductor device may include an isolation layer, gate electrodes, an insulating interlayer, an impurity region, a capping layer and a plug. The isolation layer may be formed in the substrate. The gate electrodes may be formed on the substrate. The insulating interlayer may be formed on the gate electrodes.... Agent: Myers Bigel Sibley & Sajovec

20100025750 - Memory and method of fabricating the same: A memory and a method of fabricating the same are provided. The memory is disposed on a substrate in which a plurality of trenches is arranged in parallel. The memory includes a gate structure and a doped region. The gate structure is disposed between the trenches. The doped region is... Agent: J C Patents

20100025751 - Semiconductor memory device and method of fabricating the same: A semiconductor memory device and a method of fabricating the same which is suitable for fabrication of a non-volatile memory, such as an EEPROM, using a polysilicon-insulator-polysilicon (PIP) process. The semiconductor memory device includes isolation layers defining a tunneling region and a read transistor region of a semiconductor substrate, a... Agent: Sherr & Vaughn, PLLC

20100025752 - Charge trap type non-volatile memory device and method for fabricating the same: There is provided a charge trap type non-volatile memory device and a method for fabricating the same, the charge trap type non-volatile memory device including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge... Agent: Lowe Hauptman Ham & Berner, LLP

20100025753 - Semiconductor device: Provided is a semiconductor device including: source-drain regions formed on a silicon substrate with a channel forming region sandwiched therebetween; a word gate electrode formed on the channel forming region via a word gate insulating film not including a charge storage layer; a control gate formed on the silicon substrate... Agent: Mr. Jackson Chen

20100025755 - Semiconductor device: In the trap type memory chip the withstanding voltage is raised up, and then the electric current for reading out is increased. There are formed on the p-type semiconductor substrate 1 a first gate lamination structure which comprises a first insulating film 11 including a trap layer, and a first... Agent: Mr. Jackson Chen

20100025754 - Semiconductor device and a method of manufacturing the same: There is provided a semiconductor device having a nonvolatile memory cell that performs memory operations by transferring a charge to/from a charge storage film, wherein the nonvolatile memory cell includes a p well formed in a principal plane of a silicon substrate, and a memory gate electrode formed over the... Agent: Miles & Stockbridge PC

20100025756 - Dual current path ldmosfet with graded pbl for ultra high voltage smart power applications: A dual current path LDMOSFET transistor (40) is provided which includes a substrate (400), a graded buried layer (401), an epitaxial drift region (404) in which a drain region (416) is formed, a first well region (406) in which a source region (412) is formed, a gate electrode (420) formed... Agent: Hamilton & Terrile, LLP - Freescale

20100025757 - Conductive structure and vertical-type pillar transistor: In a conductive structure, method of forming the conductive structure, a vertical-type pillar transistor and a method of manufacturing the vertical-type pillar transistor, the conductive structure includes a pillar provided on a substrate. A first conductive layer pattern is provided on a sidewall of the pillar, at least a portion... Agent: Mills & Onello LLP

20100025758 - Method of manufacturing high-integrated semiconductor device and semiconductor device manufactured using the same: A semiconductor device comprises a plurality of vertical transistors each comprising barrier metal layers corresponding to source/drain regions in which a conduction region is formed under a channel region having a pillar form, and a bit line comprising a metal layer to connect the plurality of vertical transistors.... Agent: Ampacc Law Group

20100025759 - Trench type semiconductor device and fabrication method for the same: The trench type semiconductor device includes a gate insulating film placed on the bottom surface and the sidewall surface of the trench formed from the surface of a first base layer; a gate electrode placed on the gate insulating film and fills up into a trench; an interlayer insulating film... Agent: Cantor Colburn, LLP

20100025760 - Semiconductor device: A semiconductor device includes a MOSFET cell having a super junction structure and a diode cell connected in parallel with the MOSFET cell and having the same plan shape as the MOSFET cell. The MOSFET cell includes an epitaxial layer of a first conductivity type formed on a semiconductor substrate,... Agent: Young & Thompson

20100025761 - Design structure, structure and method of latch-up immunity for high and low voltage integrated circuits: Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic.... Agent: Greenblum & Bernstein, P.L.C

20100025762 - Semiconductor structure and fabrication method thereof: A semiconductor fabrication process according to the present invention defines an auxiliary structure with a plurality of spaces with a predetermined line-width in the oxide layer to prevent the conductive material in the spaces from being removed by etching or defined an auxiliary structure to rise the conductive structure so... Agent: Schmeiser Olsen & Watts

20100025765 - Dual gate ldmos devices: An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20100025764 - Semiconductor device and manufacturing method thereof: Provided is a manufacturing method for an offset MOS transistor capable of operating safely even under a voltage of 50 V or higher. In the offset MOS transistor which includes a LOCOS oxide film, the LOCOS oxide film formed in a periphery of a drain diffusion layer, in which a... Agent: Brinks Hofer Gilson & Lione/seiko Instruments Inc.

20100025763 - Semiconductor on insulator devices containing permanent charge: A lateral SOI device may include a semiconductor channel region connected to a drain region by a drift region. An insulation region on the drift layer is positioned between the channel region and the drain region. Permanent charges may be embedded in the insulation region sufficient to cause inversion in... Agent: Groover & Associates

20100025766 - Transistor device and method of manufacturing such a transistor device: A transistor device (10), the transistor device (10) comprising a substrate (11, 14), a fin (3, 3A) aligned along a horizontal direction on the substrate (11, 14), a first source/drain region (4) of a first type of conductivity in the fin (3, 3A), a second source/drain region (5) of a... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100025767 - Semiconductor device: A semiconductor device includes N fins made of semiconductor regions aligned in parallel with each other in the top view plain, a gate electrode formed on both side surfaces of each of the N fins to cross the fins, source/drain layers formed in each of the N fins by sandwiching... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100025768 - Semiconductor device and manufacturing method thereof: It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is... Agent: Fish & Richardson P.C.

20100025770 - Gate dielectrics of different thickness in pmos and nmos transistors: By providing a gate dielectric material of increased thickness for P-channel transistors compared to N-channel transistors, degradation mechanisms, such as negative bias threshold voltage instability, hot carrier injection and the like, may be reduced. Due to the enhanced reliability of the P-channel transistors, overall production yield for a specified quality... Agent: Williams, Morgan & Amerson

20100025769 - Isolated high performance fet with a controllable body resistance: The present invention provides a method of controlling bias in an electrical device including providing semiconductor devices on a bulk semiconductor substrate each including an active body region that is isolated from the active body region of adjacent devices, and providing a body resistor in electrical contact with the active... Agent: Scully, Scott, Murphy & Presser, P.C.

20100025771 - Performance enhancement in pmos and nmos transistors on the basis of silicon/carbon material: A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding... Agent: Williams, Morgan & Amerson

20100025772 - Semiconductor device comprising a silicon/germanium resistor: In integrated circuits, resistors may be formed on the basis of a silicon/germanium material, thereby providing a reduced specific resistance which may allow reduced dimensions of the resistor elements. Furthermore, a reduced dopant concentration may be used which may allow an increased process window for adjusting resistance values while also... Agent: Williams, Morgan & Amerson

20100025773 - Process for producing a contact pad on a region of an integrated circuit, in particular on the electrodes of a transistor: A region is locally modified so as to create a zone that extends as far as at least part of the surface of the region and is formed from a material that can be removed selectively with respect to the material of the region. The region is then covered with... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20100025774 - Schottky barrier integrated circuit: A Schottky barrier integrated circuit is disclosed, the circuit having at least one PMOS device or at least one NMOS device, at least one of the PMOS device or NMOS device having metal source-drain contacts forming Schottky barrier or Schottky-like contacts to the semiconductor substrate. The device provides a new... Agent: Lemaire Patent Law Firm, P.l.l.c.

20100025775 - Replacement spacers for mosfet fringe capacatance reduction and processes of making same: A process includes planarizing a microelectronic device that includes a gate stack and adjacent trench contacts. The process also includes removing a gate spacer at the gate stack and replacing the gate spacer with a dielectric that results in a lowered overlap capacitance between the gate stack and an adjacent... Agent: Intel Corporation C/o Cpa Global

20100025776 - Drive current adjustment for transistors by local gate engineering: In a memory cell, the drive current capabilities of the transistors may be adjusted by locally providing an increased gate dielectric thickness and/or gate length of one or more of the transistors of the memory cell. That is, the gate length and/or the gate dielectric thickness may vary along the... Agent: Williams, Morgan & Amerson

20100025777 - Method for suppressing lattice defects in a semiconductor substrate: A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20100025778 - Transistor structure and method of making the same: A transistor includes a gate structure of HfMoN. The work function of the gate structure can be modulated by doping the HfMoN with dopants including nitride, silicon or germanium. The gate structure of HfMoN of the present invention is applicable to PMOS, NMOS or CMOS transistors.... Agent: North America Intellectual Property Corporation

20100025779 - Shallow pn junction formed by in situ doping during selective growth of an embedded semiconductor alloy by a cyclic growth/etch deposition process: A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of... Agent: Williams, Morgan & Amerson

20100025780 - Semiconductor device and method for manufacturing same: A semiconductor device of the present invention includes: a semiconductor layer; a gate insulation film provided on the semiconductor layer and including at least one of Hf and Zr; and a gate electrode provided on the gate insulation film and including a carbonitride which includes at least one of Hf... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20100025781 - Transistors with multilayered dielectric films and methods of manufacturing such transistors: Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a... Agent: Myers Bigel Sibley & Sajovec

20100025782 - Technique for reducing silicide non-uniformities in polysilicon gate electrodes by an intermediate diffusion blocking layer: Threshold variability in advanced transistor elements, as well as increased leakage currents, may be reduced by incorporating a barrier material in a polysilicon gate electrode. The barrier material results in a well-controllable and well-defined metal silicide in the polysilicon gate electrode during the silicidation sequence and during the further processing... Agent: Williams, Morgan & Amerson

20100025784 - Fibrous micro-composite material: Fibrous micro-composite materials are formed from micro fibers. The fibrous micro-composite materials are utilized as the basis for a new class of MEMS. In addition to simple fiber composites and microlaminates, fibrous hollow and/or solid braids, can be used in structures where motion and restoring forces result from deflections involving... Agent: Schwegman, Lundberg & Woessner, P.A.

20100025783 - Sensor apparatus for detecting variations in a dynamic quantity while suppressing detection deviations that are caused by bending deformation of a sensor chip: A miniaturized sensor such as a micro-accelerometer includes a sensor chip having a sensor element mounted thereon, with the sensor element being oriented with its central axes passing through the corners of the sensor chip. The corners of the sensor element are thereby located substantially apart from the corners of... Agent: Posz Law Group, PLC

20100025785 - Flip-chip interconnection through chip vias: An acoustic assembly that includes an integrated circuit package having an electrically conductive via configured to pass from an active portion of the integrated circuit package through a bottom portion of the integrated circuit package. The bottom portion is a bottom side of a substrate of the integrated circuit package.... Agent: Philips Intellectual Property & Standards

20100025786 - Method for manufacturing a diaphragm on a semiconductor substrate and micromechanical component having such a diaphragm: A method for manufacturing a diaphragm, on a semiconductor substrate, includes the method operations or tasks of a) providing a semiconductor substrate, b) producing trenches in the semiconductor substrate, webs made of semiconductor substrate remaining between the trenches, c) producing an oxide layer on the walls of the trenches with... Agent: Kenyon & Kenyon LLP

20100025792 - Image pickup apparatus, manufacturing method thereof, and mobile terminal: Degradation of a picked-up image quality occurs because of entry or a move of dust in the internal space of an image pickup apparatus. An image pickup apparatus for decreasing degradation of the image quality by capturing dust is provided. An image pickup apparatus 18 having a lens block 19... Agent: Mcdermott Will & Emery LLP

20100025790 - Image sensor and method of manufacturing the same: Disclosed are an image sensor and a method of manufacturing the same. The image sensor includes a semiconductor substrate having first and second surfaces opposite to each other, an isolation layer defining an active region while extending from the first surface toward the second surface, a photodiode in the active... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20100025789 - Imaging device, method for manufacturing the imaging device and cellular phone: An imaging device includes a lens (3), an optical filter (5), a semiconductor imaging element (4) having a light receiving section, and a tridimensional substrate (2) on which the semiconductor imaging element (4) and the optical filter (5) are mounted, wherein the tridimensional substrate (2) has an opening (14) corresponding... Agent: Pearne & Gordon LLP

20100025788 - Solid-state image capturing device, method for manufacturing the same and electronic information device: In a solid-state image capturing device having the locations of photodiodes in each pixel unit to be different according to a sequence, the light receiving sensitivity and the luminance shading characteristic are improved. A circumferential portion of a microlens 12 which is arranged above a corresponding photodiode 11 is formed... Agent: Edwards Angell Palmer & Dodge LLP

20100025791 - Solid-state imaging device and method for manufacturing same: An interconnect layer is formed on a lower face of a silicon wafer, a support substrate is adhered over a lower face of the interconnect layer, and a thickness reduction of the silicon wafer is performed from an upper face side. Next, a photodiode is formed in an upper face... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100025787 - System and method for providing a high frequency response silicon photodetector: A Silicon photodetector contains an insulating substrate having a top surface and a bottom surface. A Silicon layer is located on the top surface of the insulating substrate, where the Silicon layer contains a center region, the center region being larger in thickness than the rest of the Silicon layer.... Agent: Sheehan Phinney Bass & Green, PA C/o Peter Nieves

20100025793 - Assembly for image sensing chip and assembling method thereof: An assembly for an image sensing chip to reduce the entire thickness and an assembling method thereof are disclosed. Meanwhile, the electro-optical assembly includes an image sensing chip; and a multi-layer printed circuit board having a recess to accommodate the image sensing chip, thereby decreasing the entire electro-optical assembly in... Agent: Bacon & Thomas, PLLC

20100025795 - Image sensing device and packaging method thereof: An image sensing device and packaging method thereof is disclosed. The packaging method includes the steps of a) providing an image sensing module, having a light-receiving region exposed, on a first substrate; b) forming a plurality of first contacts around the light-receiving region on the image sensing module; c) providing... Agent: Bacon & Thomas, PLLC

20100025794 - Image sensor chip package structure and method thereof: An image sensor chip package structure includes a transparent substrate, a chip, a sealing ring, a number of conductive posts, and a number of conductive bumps. The transparent substrate has a number of through holes. The through holes pass through the transparent substrate. The chip has an active surface, an... Agent: J C Patents

20100025797 - Device comprising an ohmic via contact, and method of fabricating thereof: Device comprising an ohmic via contact, and method of fabricating thereof. A preferred embodiment comprises forming a metal layer over a substrate, forming a conductive barrier layer over the metal layer, depositing an insulating layer over the conductive barrier layer, creating an opening in the insulating layer to expose the... Agent: Texas Instruments Incorporated

20100025796 - Microchannel plate photocathode: An energy-enhanced, low-temperature growth technique is used for direct deposition of periodic table column III nitrides-based negative electron affinity (NEA) photocathodes on standard glass microchannel plates (MCPs.) As working examples, low-temperature RF plasma-assisted molecular beam epitaxy growth (MBE) of p-type GaN layers on sapphire, quartz, and glass and alumina MCPs... Agent: Kinney & Lange, P.A.

20100025798 - Apparatus comprising a single photon photodetector having reduced afterpulsing and method therefor: A single-photon detector is disclosed that provides reduced afterpulsing without some of the disadvantages for doing so in the prior art. An embodiment of the present invention provides a stimulus pulse to the active area of an avalanche photodetector to stimulate charges that are trapped in energy trap states to... Agent: Demont & Breyer, LLC

20100025799 - Wafer for backside illumination type solid imaging device, production method thereof and backside illumination type solid imaging device: A wafer for backside illumination type solid imaging device has a plurality of pixels inclusive of a photoelectric conversion device and a charge transfer transistor at its front surface side and a light receiving surface at its back surface side, wherein said wafer is a SOI wafer obtained by forming... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20100025800 - Image sensor and manufacturing method thereof: An image sensor having greatly improved physical and electrical bonding forces between a photodiode and a substrate, and a manufacturing method thereof. The image sensor includes a semiconductor substrate and readout circuitry, a dielectric layer on the semiconductor substrate, a metal line in the dielectric layer, electrically connected with the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20100025801 - Image sensor and method for manufacturing the same: An image sensor includes readout circuitry on a first substrate, a metal line electrically connected with the readout circuitry, a dielectric on the metal line, an image sensing device on the dielectric, including first and second conductivity type layers, a contact plug in a via hole penetrating the image sensing... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20100025802 - Image sensor and method for manufacturing the same: An image sensor is provided. The image sensor comprises a readout circuitry, interconnections, a first image sensing device, and a second image sensing device. The readout circuitry is disposed on a first substrate. The interconnections comprise a first interconnection and a second interconnection on the first substrate to be electrically... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20100025803 - Image sensor and method for manufacturing the same: Provided are an image sensor and a method for manufacturing the same. According to an embodiment, a semiconductor substrate is provided comprising a readout circuit. An interconnection electrically connected to the readout circuit and an interlayer dielectric are disposed over the semiconductor substrate. An image sensing unit is disposed over... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20100025806 - Semiconductor device and method of fabricating the same: In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to... Agent: Lowe Hauptman Ham & Berner, LLP

20100025805 - Semiconductor devices with extended active regions: A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of... Agent: Freescale Semiconductor, Inc. Law Department

20100025804 - Soi substrate and method for manufacturing soi substrate: On the side of a surface (the bonding surface side) of a single crystal Si substrate, a uniform ion implantation layer is formed at a prescribed depth (L) in the vicinity of the surface. The surface of the single crystal Si substrate and a surface of a transparent insulating substrate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100025807 - Discrete semiconductor device and method of forming sealed trench junction termination: A discrete semiconductor device has a substrate with a first conductivity type of semiconductor material. A first semiconductor layer is formed over the substrate. The first semiconductor layer having the first conductivity type of semiconductor material. A second semiconductor layer over the first semiconductor layer. The second semiconductor layer has... Agent: Robert D. Atkins

20100025808 - Bipolar transistor and method of fabricating the same: The invention provides a bipolar transistor with a reduced collector series resistance integrated in a trench (4, 44) of a standard CMOS shallow trench isolation region. The bipolar transistor includes a collector region (6, 34) manufactured in one fabrication step, therefore having a shorter conductive path with a reduced collector... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100025809 - Integrated circuit and method of forming sealed trench junction termination: An integrated circuit having a substrate with a first conductivity type of semiconductor material. A buried layer is formed in the substrate. The buried layer has a second conductivity type of semiconductor material. A first semiconductor layer is formed over the buried layer. The first semiconductor layer has the second... Agent: Robert D. Atkins

20100025811 - Integrated circuit with built-in heating circuitry to reverse operational degeneration: An integrated circuit device (100) includes structures (104) that exhibit performance degradation as a function of use (e.g., accumulated defects within the tunneling oxide of a Flash memory cell, or trapped charge within a charge storage layer) and heating circuitry (101) disposed in proximity to the structures to heat the... Agent: Shemwell / Rambus

20100025810 - Method and system for secure heat sink attachment on semiconductor devices with macroscopic uneven surface features: An integrated circuit package is provided. The integrated circuit package includes a heat sink, a cured silicone thermally conductive adhesive material, and a surface. The adhesive material attaches the heat sink to the surface. The surface is a surface of at least one of a substrate, a surface of an... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20100025812 - Pinched poly fuse: An electrical fuse has a region of a first conductivity type in a continuous type polysilicon of a second conductivity type that is opposite the first conductivity type. In one embodiment of the invention the PN junction between the region and the poly fuse is reverse biased.... Agent: Hiscock & Barclay, LLP

20100025818 - Integrated circuit package: An integrated circuit package is described that includes an integrated circuit die, a plurality of lower contact leads, and an insulating substrate positioned over the die and lower contact leads. The insulating substrate includes a plurality of electrically conducting upper routing traces formed on the bottom surface of the substrate.... Agent: Beyer Law Group LLP/ Nsc

20100025817 - Method of manufacturing semiconductor device and semiconductor device: A method of manufacturing a semiconductor device including a plurality of capacitors each of which has bottom electrode, dielectric layer, and top electrode includes stacking a bottom electrode layer, a dielectric layer and an top electrode layer, patterning the top electrode layer to form a plurality of top electrodes arranged... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20100025816 - Semiconductor device: A width of a region where each of the N wells is in contact with the buried P well is not more than 2 μm. A ground voltage and a power supply voltage are applied to the P well and the N well, respectively. A decoupling capacitor is formed between... Agent: Mcginn Intellectual Property Law Group, PLLC

20100025815 - Semiconductor device and method of manufacturing the same: A semiconductor device including a metallic compound Hfx1Moy1Nz1 as an electrode. The work function of the electrode can be modulated by doping the metallic compound with dopants including nitrogen, silicon or germanium. The metallic compound of the present invention is applicable to PMOS, NMOS, CMOS transistors and capacitors.... Agent: North America Intellectual Property Corporation

20100025814 - Structure for dual contact trench capacitor and structure thereof: A dual contact trench capacitor and design structure for a dual contact trench capacitor is provided. The structure includes a first plate extending from a trench and isolated from a wafer body, and a second plate extending from the trench and isolated from the wafer body and the first plate.... Agent: Greenblum & Bernstein, P.L.C

20100025813 - Structure for dual contact trench capacitor and structure therof: A dual contact trench capacitor and design structure for a dual contact trench capacitor is provided. The structure includes a first plate extending from a trench and isolated from a wafer body, and a second plate extending from the trench and isolated from the wafer body and the first plate.... Agent: Greenblum & Bernstein, P.L.C

20100025819 - Programmable precision resistor and method of programming the same: A link portion between a first electrode and a second electrode includes a semiconductor link portion and a metal semiconductor alloy link portion comprising a first metal semiconductor alloy. An electrical pulse converts the entirety of the link portion into a second metal semiconductor alloy having a lower concentration of... Agent: Scully, Scott, Murphy & Presser, P.C.

20100025820 - Semiconductor device: In a first region at a first main surface of an n type semiconductor substrate, a p base layer, an n source layer, a gate electrode and an emitter electrode are formed, and a collector electrode is formed at a second main surface, constituting an IGBT. A p layer constituting... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100025821 - Ion implanting apparatus and ion implanting method: When positively charged ions are implanted into a target substrate, charge-up damage may occur on the target substrate. In order to suppress charge-up caused by secondary electrons emitted from the target substrate when positively charged ions are implanted, a conductive member is installed at a position facing the target substrate... Agent: Pearne & Gordon LLP

20100025822 - Germanium on insulator (goi) semiconductor substrates: Germanium on insulator (GOI) semiconductor substrates are generally described. In one example, a GOI semiconductor substrate comprises a semiconductor substrate comprising an insulative surface region wherein a concentration of dopant in the insulative surface region is less than a concentration of dopant in the semiconductor substrate outside of the insulative... Agent: Cool Patent, P.C. C/o Cpa Global

20100025823 - Passivation of aluminum nitride substrates: The present invention provides methods of protecting a surface of an aluminum nitride substrate. The substrate with the protected surface can be stored for a period of time and easily activated to be in a condition ready for thin film growth or other processing. In certain embodiments, the method of... Agent: Alston & Bird LLP

20100025824 - Structure for reducing integrated circuit corner peeling: A crack prevention structure that reduces integrated circuit corner peeling and reduces cracking is disclosed. The crack prevention structure comprises a semiconductor substrate; a first plurality of dielectric layers of a first material disposed over the semiconductor substrate; a second plurality of dielectric layers of a second material different than... Agent: Haynes And Boone, LLPIPSection

20100025825 - Metal adhesion by induced surface roughness: Back side metal (BSM) delamination induced by chip dicing of silicon wafers is avoided by roughening the polished silicon surface at chip edges by etching. The Thru-Silicon-Via (TSV) structures used in 3D chip integration is masked at the back side from roughening to maintain the polished surface at the TSV... Agent: Ibm Microelectronics Intellectual Property Law

20100025826 - Field effect transistors with channels oriented to different crystal planes: An integrated circuit includes a first field effect transistor of a first carrier type and a second field effect transistor of a second, different carrier type. In a conductive state, a first channel of the first field effect transistor is oriented to one of a first set of equivalent crystal... Agent: Edell, Shapiro & Finnan, LLC

20100025827 - Semiconductor device and method of fabricating the same: A PIN diode has an n− drift layer, a p anode layer, an n buffer layer, an n+ layer, a front surface electrode and a back surface electrode. The n+ layer has an impurity concentration having a stepwise profile substantially fixed for a predetermined depth measured from a second major... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100025828 - Semiconductor device, semiconductor module, method for manufacturing semiconductor device, and lead frame: To provide a semiconductor device and a semiconductor module in which breakage of a semiconductor element due to a pressing force given from the outside is prevented. A semiconductor device according to the present invention has a configuration mainly including an island, a semiconductor element mounted on a front surface... Agent: Morrison & Foerster LLP

20100025829 - Semiconductor device: A method of manufacturing a semiconductor device includes providing a foil formed of an insulating material, where the foil includes at least one electrically conducting element, providing a chip having contact elements on a first face of the chip, and applying the foil over the contact elements of the chip.... Agent: Dicke, Billig & Czaja

20100025830 - A method for forming an etched recess package on package system: An integrated circuit package system includes: providing a die attach paddle with interconnection pads connected to a bottom surface of the die attach paddle; connecting a first device to the interconnection pads with a bond wire; connecting a lead to the interconnection pad or to the first device; encapsulating the... Agent: Law Offices Of Mikio Ishimaru

20100025831 - Method for manufacturing thin film integrated circuit device, noncontact thin film integrated circuit device and method for manufacturing the same, and idtag and coin including the noncontact thin film integrated circuit device: To provide a thin film integrated circuit which is mass produced at low cost, a method for manufacturing a thin film integrated circuit according to the invention includes the steps of: forming a peel-off layer over a substrate; forming a base film over the peel-off layer; forming a plurality of... Agent: Eric Robinson

20100025832 - Reduced stiction and mechanical memory in mems devices: A MEMS device is packaged in a process which hydrogen (H) deuterium (D) for reduced stiction. H is exchanged with D by exposing the MEMS device with a deuterium source, such as deuterium gas or heavy water vapor, optionally with the assistance of a direct or downstream plasma.... Agent: Texas Instruments Incorporated

20100025837 - Composite semiconductor device, semiconductor package and spacer sheet used in the same, and method for manufacturing composite semiconductor device: connection terminals for external connection which are formed on a lower surface of a substrate for wiring and connecting in a semiconductor package located in a lowermost part and to a production process for the same. The present invention provides a wiring and connecting method by a spacer sheet which... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100025838 - Electronic device protected against electro static discharge: An embodiment of a method for manufacturing an electronic device realized on a semiconductor substrate and protected against electro static discharge by the provision of supporting means for the electronic device to keep it far from contacts with possible sources of an ESD event during the manufacturing phases. The supporting... Agent: Graybeal Jackson LLP

20100025834 - Fan-in interposer on lead frame for an integrated circuit package on package system: An integrated circuit package on package system includes: providing a lead having a wire-bonded die with a bond wire connected thereto; mounting a fan-in interposer over the wire-bonded die and the bond wire; connecting the fan-in interposer to the lead with the bond wires; and encapsulating the wire-bonded die, bond... Agent: Law Offices Of Mikio Ishimaru

20100025835 - Integrated circuit package stacking system: An integrated circuit package stacking system includes: forming a flexible substrate by: providing an insulating material, forming a stacking pad on the insulating material, forming a coupling pad on the insulating material, and forming a trace between the stacking pad and the coupling pad; providing a package substrate; coupling an... Agent: Law Offices Of Mikio Ishimaru

20100025836 - Multi-layer package-on-package system: A package-on-package system includes: providing a bottom package module incorporating a bottom package substrate; attaching a central internal stacking module, incorporating a central interposer, on top of the bottom package module; placing a spacer on the top surface of the central internal stacking module; mounting a first top package module,... Agent: Law Offices Of Mikio Ishimaru

20100025833 - Rdl patterning with package on package system: An integrated circuit package system includes: providing an internal device; encapsulating the internal device with an encapsulation having an outer surface; and forming a redistribution line having connection points on the outer surface of the encapsulation.... Agent: Law Offices Of Mikio Ishimaru

20100025840 - Embedded inductor and method of producing thereof: A method of manufacturing an inductor embedded into a semiconductor chip package (100) is described, which method comprises providing a carrier (102; 202; 302) having, between a first side and an opposite second side, a first conductive layer (104; 503), an intermediate layer (205; 505), a second conductive layer (106;... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100025839 - Leadframe, semiconductor device, and method of manufacturing the same: A leadframe has a die pad, first marks, and second marks, and the die pad allows thereon mounting of a first semiconductor chip. The first marks indicate a mounting region for the first semiconductor chip, the second marks indicate a mounting region for the second semiconductor chip, and the first... Agent: Mcginn Intellectual Property Law Group, PLLC

20100025841 - Semiconductor device and method of designing the same: A semiconductor device contains an interposer having a square planar geometry, with length X for a first edge and length Y for a second edge orthogonal to the first edge, and a semiconductor chip and a dummy component disposed over the interposer, wherein the center of a first outer circumferential... Agent: Mcginn Intellectual Property Law Group, PLLC

20100025842 - Semiconductor module and semiconductor device: A semiconductor module includes an insulating resin layer, a wiring layer provided on one main surface S1 of the insulating layer, and bump electrodes, electrically connected to the wiring layer, which are protruded on the insulating resin layer side from the wiring layer. Element electrodes provided on a semiconductor element... Agent: Mcdermott Will & Emery LLP

20100025843 - Optical semiconductor apparatus: An optical semiconductor apparatus composed of a cap and a base, includes: a metal package including a plurality of openings penetrating through the base from outside to inside, a lead with its end portion protruding to the inside of the base and an insulator covering a side surface of the... Agent: Carrier Blackman And Associates

20100025844 - Semiconductor device and manufacturing method thereof: There is provided a low-cost semiconductor device that commercial and quality-assured (inspected) chip size packages can be stacked and has a small co-planarity value and a high mounting reliability. A semiconductor device in which a flexible circuit substrate is adhered to at least a part of a lateral side of... Agent: Mr. Jackson Chen

20100025845 - Micromechanical housing comprising at least two cavities having different internal pressure and/or different gas compositions and method for the production thereof: The present application relates to a multiple component which is to be subsequently individualized by forming components containing active structures, in addition to a corresponding component which can be used in microsystem technology systems. The multiple component and/or component comprises a flat substrate and also a flat cap structure which... Agent: Stevens & Showalter LLP

20100025846 - Metal cap with ringed projection to be welded to stem and ringed groove provided immediately inside of ringed projection and optical device having the same: An optical device with a CAN package is disclosed, where the cap is resistance-welded to the stem without causing failures due to fragments by the welding flying within the package. The cap of the invention has a flange portion to be welded to the stem. The flange portion provides a... Agent: Venable LLP

20100025847 - Semiconductor device mounted structure and semiconductor device mounted method: A recess portion is formed on a board surface at a position facing a peripheral end portion of a semiconductor device so as to place a sealing-bonding use resin partially inside the recess portion. Thereby, increases of a placement area for a fillet portion (foot spreading portion) of the sealing-bonding... Agent: Wenderoth, Lind & Ponack L.L.P.

20100025849 - Copper on organic solderability preservative (osp) interconnect and enhanced wire bonding process: A semiconductor package and a method for constructing the package are disclosed. The package includes a substrate and a die attached thereto. A first contact region is disposed on the substrate and a second contact region is disposed on the die. The first contact region, for example, comprises copper coated... Agent: HorizonIPPte Ltd

20100025848 - Method of fabricating a semiconductor device and semiconductor device: A method of fabricating a semiconductor device and semiconductor device is provided. The method provides a first layer. The first layer includes through-holes. At least one semiconductor chip is provided. The semiconductor chip includes contact elements. The semiconductor chip is placed onto the first layer with the contact elements being... Agent: Dicke, Billig & Czaja

20100025850 - Ohmic electrode structure and semiconductor element: The present invention includes an AuGeNi alloy layer (13) provided on an n-type GaAs layer; and a laminate provided on the AuGeNi alloy layer (13), the laminate being composed of a bonding metal layer (15, 17) and a barrier metal layer (16, 18) provided on the bonding metal layer (15,... Agent: Hamre, Schumann, Mueller & Larson P.C.

20100025851 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the same include forming a second copper-plated layer over a second IMD layer and inside a second aperture formed in the second IMD by an electroplating process that uses the exposed first copper-plated layer as a seed layer. With the method, the... Agent: Sherr & Vaughn, PLLC

20100025852 - Semiconductor device and method for manufacturing the same: To suppress deterioration in reliability of wiring and to reduce effective dielectric constant of wiring. In a semiconductor device, copper-containing wirings are covered by barrier insulating films, and the barrier insulating films contain a component of an organic silica containing unsaturated hydrocarbon and amorphous carbon. The copper-containing wirings are covered... Agent: Mr. Jackson Chen

20100025853 - Back-end-of-line wiring structures with integrated passive elements and design structures for a radiofrequency integrated circuit: Back-end-of-line (BEOL) wiring structures that include a passive element, such as a thin film resistor or a metal-insulator-metal capacitor, and multiple-height vias in a metallization level, as well as design structures for a radiofrequency integrated circuit. The wiring structures generally include a first metal-filled via in a dielectric layer having... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20100025854 - Polishing systems and methods for removing conductive material from microelectronic substrates: Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive... Agent: Perkins Coie LLP Patent-sea

20100025855 - Enhancing structural integrity and defining critical dimensions of metallization systems of semiconductor devices by using ald techniques: During the patterning of sophisticated metallization systems, a damaged surface portion of a sensitive low-k dielectric material may be efficiently replaced by a well-controlled dielectric material, thereby enabling an adaptation of the material characteristics and/or the layer thickness of the replacement material. Thus, established lithography and etch techniques may be... Agent: Williams, Morgan & Amerson

20100025856 - Fabrication method of a semiconductor device and a semiconductor device: A method for fabricating a semiconductor device includes the steps of (a) forming a plasma of a gas having carbon and fluorine, and forming an internal insulation film provided with a fluorine-doped carbon film formed on a substrate using the plasma; (b) forming a metal film on the internal insulation... Agent: Ipusa, P.l.l.c

20100025857 - Ic chip and design structure with through wafer vias dishing correction: An IC chip and design structure having a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV. An IC chip may include a substrate; a through wafer via (TWV) extending through at least one first dielectric layer and into the substrate; a TWV contact... Agent: Hoffman Warnick LLC

20100025859 - Method for designing semiconductor device, program therefor, and semiconductor device: A method for designing a semiconductor device includes computing a contact resistance value based on an allowable power supply voltage drop set for a second position corresponding to a given region of a second power supply line on a second wiring layer different from a first wiring layer, and computing... Agent: Fujitsu Patent Center C/o Cpa Global

20100025860 - Semiconductor device and manufacturing method of semiconductor device: m

20100025858 - Winged vias to increase overlay margin: Winged via structures to increase overlay margin are generally described. In one example, a method comprises depositing a sacrificial layer to an interlayer dielectric, the interlayer dielectric being coupled with a semiconductor substrate, forming at least one trench structure in the sacrificial layer wherein the trench structure comprises a first... Agent: Cool Patent, P.C. C/o Cpa Global

20100025861 - Hybrid-level three-dimensional mask-programmable read-only memory: A hybrid-level three-dimensional mask-programmable read-only memory (HL-3DMPROM) includes a plurality of memory sets. Within each memory set, a plurality of vertically stacked memory levels are interleaved and all adjacent memory levels share address-selection lines; between adjacent memory sets, memory levels are separated by an inter-level dielectric and do not share... Agent: Guobiao Zhang

20100025862 - Integrated circuit interconnect method and apparatus: Techniques for interconnecting an IC chip and a receiving substrate are provided. A method includes the steps of: providing the IC chip, the IC chip including at least a first connection site formed thereon; providing the receiving substrate, the receiving substrate including at least a second connection site formed thereon;... Agent: Ryan, Mason & Lewis, LLP

20100025863 - Integrated circuit interconnect method and apparatus: Techniques for interconnecting an IC chip and a receiving substrate are provided. A method includes the steps of: providing the IC chip, the IC chip including at least a first connection site formed thereon; providing the receiving substrate, the receiving substrate including at least a second connection site formed thereon;... Agent: Ryan, Mason & Lewis, LLP

20100025864 - Shielded wirebond: A wirebond interconnect structure, having ground pads and signal pads, to which wirebonds are electrically coupled, disposed on a component, is provided and includes a first coating to insulate at least the wirebonds and the signal pads with at least the ground pads exposed, and a second coating, surrounding the... Agent: Cantor Colburn LLP - IBM Rochester Division