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Active solid-state devices (e.g., transistors, solid-state diodes) November recently filed with US Patent Office 11/09

20090289240 - Non-volatile multi-bit memory with programmable capacitance: Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A first solid electrolyte cell is over the insulating layer and has a capacitance that is controllable between at... Agent: Campbell Nelson Whipps, LLC

20090289241 - Phase change memory devices and fabrication methods thereof: In a memory device, a transistor may be formed on a substrate, and a first electrode may be electrically connected thereto. A phase change material film may be vertically formed on the first electrode, and a second electrode may be formed on the phase change material film.... Agent: Harness, Dickey & Pierce, P.L.C

20090289242 - Phase change memory with tapered heater: Another embodiment of the present invention includes a phase change memory (PCM) structure configurable for use as a nonvolatile storage element. The element includes at least one bottom electrode; at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; and... Agent: Ryan, Mason & Lewis, LLP

20090289243 - Short bridge phase change memory cells and method of making: Random access memory cells having a short phase change bridge structure and methods of making the bridge structure via shadow deposition. The short bridge structure reduces the heating efficiency needed to switch the logic state of the memory cell. In one particular embodiment, the memory cell has a first electrode... Agent: Campbell Nelson Whipps, LLC

20090289244 - Semiconductor heterostructure nanowire devices: Nanowire devices comprising core-shell or segmented nanowires are provided. In these nanowire devices, strain can be used as a tool to form metallic portions in nanowires made from compound semiconductor materials, and/or to create nanowires in which embedded quantum dots experience negative hydrostatic pressure or high positive hydrostatic pressure, whereby... Agent: Foley And Lardner LLP Suite 500

20090289245 - Faceted catalytic dots for directed nanotube growth: Faceted catalytic dots are used for directing the growth of carbon nanotubes. In one example, a faceted dot is formed on a substrate for a microelectronic device. A growth promoting dopant is applied to a facet of the dot using an angled implant, and a carbon nanotube is grown on... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090289248 - Dioxaanthanthrene compound and semiconductor device: c

20090289246 - Method for producing at least one multilayer body, and multilayer body: The invention concerns a process for the production of a multi-layer body, wherein the multi-layer body includes at least two functional layers on a top side of a carrier substrate, which are structured in register relationship with each other, by a procedure whereby an underside of the carrier substrate is... Agent: Hoffmann & Baron, LLP

20090289247 - Organic-semiconductor-based infrared receiving device: An organic-semiconductor-based infrared receiving device comprises an electrode layer having a positive layer and a negative layer to form an electric field, and a transport layer located between the positive and negative layers and having a first and a second predetermined material combined in a predetermined ratio. The energy of... Agent: Oliff & Berridge, PLC

20090289252 - Light emitting element and display device using the same: An object of the invention is to provide a highly reliable light emitting element with low drive voltage and longer life than a conventional light emitting element, and a display device using the light emitting element. A light emitting element according to the invention comprises a plurality of layers which... Agent: Cook Alex Ltd

20090289251 - Nonvolatile memory device and method for manufacturing same: A nonvolatile memory device includes a plurality of component memory layers stacked on one another. Each of the plurality of component memory layers includes a first wiring, a second wiring provided non-parallel to the first wiring, and a stacked structure unit provided between the first wiring and the second wiring.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090289249 - Oxide semiconductor, thin-film transistor and method for producing the same: Disclosed is an oxide semiconductor having an amorphous structure, wherein higher mobility and reduced carrier concentration are achieved. Also disclosed are a thin film transistor, a method for producing the oxide semiconductor, and a method for producing the thin film transistor. Specifically disclosed is an oxide semiconductor which is characterized... Agent: Kanesaka Berner And Partners LLP

20090289250 - System and method for manufacturing a thin-film device: A thin-film device includes a plurality of circuit components defining an operational region of the thin-film device, an unpatterned channel portion (108, 340) disposed on the plurality of circuit components, and a patterned passivation dielectric (380,385) selectively disposed on the unpatterned channel portion (108,340) to electrically pattern an active region... Agent: Hewlett-packard Company Intellectual Property Administration

20090289253 - Semiconductor wafer and method of forming sacrificial bump pad for wafer probing during wafer sort test: A semiconductor wafer contains a plurality of semiconductor die. A plurality of interconnect bump pads is formed over the semiconductor die. A plurality of sacrificial bump pads is formed in proximity to and diagonally offset with respect to the interconnect bump pads. The sacrificial bump pads have a different diameter... Agent: Robert D. Atkins

20090289254 - Semiconductor device and method for manufacturing the same: A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in... Agent: Eric Robinson

20090289257 - Exposure mask using gray-tone pattern, manufacturing method of tft substrate using the same and liquid crystal display device having the tft substrate: Disclosed are an exposure mask capable of improving uniformity of a resist film thickness of a half film thickness part and reducing a display defect to increase a manufacturing yield, a method of manufacturing a TFT substrate using the exposure mask and a liquid crystal display comprising the TFT substrate... Agent: Young & Thompson

20090289255 - Flexible display device and manufacturing method thereof: A flexible display device adapted to prevent a disconnection of pad electrode and a line short-circuit is disclosed. The flexible display device and the manufacturing method thereof according to the present embodiments forms only the barrier film or no layer on the mother substrate in the vicinity of the cut... Agent: Brinks Hofer Gilson & Lione

20090289256 - Thin film transistor and display device including thin film transistor: A thin film transistor with favorable electric characteristics is provided, which includes a gate electrode layer; a first insulating layer covering the gate electrode layer; a pair of impurity semiconductor layers forming source and drain regions, which are provided with a distance therebetween and at least partly overlap with the... Agent: Nixon Peabody, LLP

20090289258 - Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same: A thin film transistor, a method of fabricating the same, and an organic light emitting diode display device including the same, which allow a size of a grain of a channel region to be increased, can effectively protect the channel region of a semiconductor layer at the time of etching... Agent: Robert E. Bushnell & Law Firm

20090289260 - Liquid crystal display device and method of manufacturing that: A liquid crystal display device which can reduce or eliminate a display defect is provided. The liquid crystal display device includes a first alignment film formed on one of the pair of substrates; a second alignment film formed on another of the pair of substrates; first projecting portions which are... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090289259 - Pixel structure of display panel and method of making the same: A pixel structure of a display panel is provided. The pixel structure includes a first storage capacitor formed by a pixel electrode and a common electrode pattern, and a second storage capacitor formed by an electrode pattern and the common electrode pattern. Accordingly, the storage capacitance is greatly improved without... Agent: North America Intellectual Property Corporation

20090289261 - Gallium nitride crystal substrate and method of producing same: A low-distortion gallium nitride crystal substrate including low dislocation single crystal regions (Z) having a definite c-axis and a definite a-axis, C-plane growth regions (Y) having a c-axis and a-axis parallel to the c-axis and a-axis of the low dislocation single crystal regions (Z), voluminous defect accumulating regions (H) having... Agent: Mcdermott Will & Emery LLP

20090289262 - Junction barrier schottky diodes with current surge capability: An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090289264 - Silicon carbide semiconductor device and method of manufacturing the same: An SiC semiconductor device includes a substrate, a drift layer disposed on a first surface of the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a trench penetrating the source region and the base region to the drift layer, a gate... Agent: Posz Law Group, PLC

20090289263 - System and method for emitter layer shaping: Embodiments of an LED disclosed has an emitter layer shaped to a controlled depth or height relative to a substrate of the LED to maximize the light output of the LED and to achieve a desired intensity distribution. In some embodiments, the exit face of the LED may be selected... Agent: SprinkleIPLaw Group

20090289265 - Electronic device and method of manufacturing an electronic device: An electronic device comprising at least one die stack having at least a first die (D1) comprising a first array of light emitting units (OLED) for emitting light, a second layer (D2) comprising a second array of via holes (VH) and a third die (D3) comprising a third array of... Agent: Haynes And Boone, LLPIPSection

20090289266 - Reflection type optical sensor device: Provided is a reflection type optical sensor device including: a semiconductor light source being formed by providing a light emitting region on a predetermined region of a substrate; and a photo-detection element being integrated on the same substrate as the substrate where the semiconductor light source is formed to surround... Agent: Ampacc Law Group

20090289267 - Solid state led bridge rectifier light engine: A solid-state light engine comprised of light emitting diodes (LEDs) configured into a bridge rectifier with a current limiting module coupled to the LED bridge rectifier. The light engine may be packaged for high temperature operation. Optionally, the LEDs comprise wavelength-converting phosphors with a persistence that is a multiple of... Agent: Cantor Colburn, LLP

20090289270 - Group iii nitride semiconductor multilayer structure and production method thereof: According to the invention it is possible to obtain a flat AlN crystal film seed layer with a high degree of crystallinity, and particularly, a flat AlN crystal film seed layer that is homogeneous throughout can be used even with large substrates having diameters of 100 mm and greater, in... Agent: Sughrue Mion, PLLC

20090289268 - Light emitting apparatus and semiconductor apparatus, and method for manufacturing the same: The light emitting apparatus comprises a light emitting device, a heat dissipating member that has an upper surface and a lower surface and supports the light emitting device mounted on the upper surface, first and second leads and an insulating resin that holds the first and second leads at positions... Agent: Birch Stewart Kolasch & Birch

20090289272 - Light emitting device package: Disclosed is a light emitting device package. The light emitting device package includes a semiconductor substrate comprising a first surface at a first depth from an upper surface of the semiconductor substrate and a second surface at a second depth from the first surface; and a light emitting part on... Agent: Birch Stewart Kolasch & Birch

20090289273 - Light emitting device package structure and fabricating method thereof: A light emitting device package structure is described. The light emitting device package structure includes a substrate serving as a carrier supporting a light emitting device chip. The substrate and the light emitting device chip have a chip side and a substrate side separately. A first electrode layer is disposed... Agent: Liu & Liu

20090289269 - Packaging structure of light emitting diode: The present invention discloses a light-emitting diode packaging structure, comprising a base; a chip; a first material disposed on at least one side of the chip and having a first refraction index; a second material disposed upon the chip, having a second refraction index, and separated with the first material... Agent: Guice Patents PLLC

20090289271 - Silicate-based phosphors and led lighting devices using the same: e

20090289275 - Light emitting device, package, light emitting device manufacturing method, package manufacturing method and package manufacturing die: Provided is a light emitting device wherein a resin molded body having a circular or an oval recessed section at the center suppresses generation of cracks. A light emitting device (1) is provided with a light emitting element (2); a first resin molded body (10) having a plurality of outer... Agent: Squire, Sanders & Dempsey L.L.P.

20090289274 - Package structure of light emitting diode and method of manufacturing the same: Provided are a LED package structure and a method of manufacturing the same. The LED package structure includes first and second plate-shaped auxiliary support pieces; a heat-dissipating portion formed upwardly higher than the first and second auxiliary support pieces; a plurality of auxiliary leads connected between each of the auxiliary... Agent: Mitchell P. Brook Luce, Forward, Hamilton & Scripps LLP

20090289276 - Semiconductor device: A semiconductor device is provided. On one main surface side of an n-type semiconductor substrate, a p-type diffusion region to serve as an anode of a diode is formed. A guard ring formed of a p-type diffusion region is formed to surround the anode. On the other main surface side,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090289277 - Power semiconductor device: A plurality of cell structures of a vertical power device are formed at a semiconductor substrate. One cell structure included in the plurality of cell structures and located in a central portion CR of the main surface has a lower current carrying ability than the other cell structure included in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090289278 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a collector layer of a first conductivity type; a semiconductor area of a second conductivity type formed on the collector layer; a base layer of the first conductivity type formed on the semiconductor area; an emitter layer of the second conductivity type formed in an island... Agent: Wilmerhale/dc

20090289279 - Method and apparatus for buried-channel semiconductor device: Methods and apparatus of integrating a buried-channel PMOS into a BiCMOS process. The apparatus comprises at least one bipolar transistor and at least one MOS device coupled to the at least one bipolar transistor, such that a gate of the at least one MOS device may be coupled to an... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20090289280 - Method for making transistors and the device thereof: A semiconductor process and apparatus includes forming <100> channel orientation PMOS transistors (34) with enhanced hole mobility in the channel region of a transistor by epitaxially growing a bi-axially stressed silicon germanium channel region layer (22), alone or in combination with an underlying silicon carbide layer (86), prior to forming... Agent: Hamilton & Terrile, LLP - Freescale

20090289281 - Semiconductor device and method for fabricating semiconductor device: A semiconductor device includes a plurality of bit lines repeatedly arranged with a same line width and pitch in a memory device region; a plurality of shunt lines arranged in a same layer as that of the plurality of bit lines, in parallel therewith, and with the same line width... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090289282 - Solid state imaging device and method for manufacturing the same: A solid state imaging device includes a transfer transistor for transferring signal charges generated by photoelectric conversion to a floating diffusion layer, a reset transistor for resetting a potential of the floating diffusion layer, and an amplifying transistor for outputting a signal corresponding to the potential of the floating diffusion... Agent: Mcdermott Will & Emery LLP

20090289283 - Wafer for backside illumination type solid imaging device, production method thereof and backside illumination solid imaging device: A wafer for backside illumination type solid imaging device has a plurality of pixels inclusive of a photoelectric conversion device and a charge transfer transistor at its front surface side and a light receiving surface at its back surface side, wherein said wafer is a SOI wafer obtained by forming... Agent: Townsend And Townsend And Crew, LLP

20090289284 - High shrinkage stress silicon nitride (sin) layer for nfet improvement: A method (and semiconductor device) of forming a high shrinkage stressed silicon nitride layer for use as a contact etch stop layer (CESL) or capping layer in a stress management technique (SMT) provides increased tensile stress to a channel of an nFET device to enhance carrier mobility. A spin-on polysilazane-based... Agent: Docket Clerk

20090289285 - Semiconductor device and method of fabricating the same: Provided is a semiconductor device including a transistor that has a silicide layer formed over a semiconductor substrate. The gate electrode of each transistor is composed of a polysilicon electrode and the silicide layer formed thereon. Each transistor further has source/drain impurity-diffused layers composed of low-concentration doped regions and high-concentration... Agent: Mcginn Intellectual Property Law Group, PLLC

20090289287 - Cmos image sensor and method of manufacturing the same: Disclosed herein are a CMOS image sensor and a method of manufacturing the same, which can reduce current leakage through a plug connecting a photodiode and a transfer transistor to each other, and thereby provide low dark current levels. The CMOS image sensor includes a first epitaxial layer on or... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090289286 - Cmos image sensor having improved signal eficiency and method for manufacturing the same: A CMOS image sensor and a method for manufacturing the same improves signal efficiency by reducing a dark signal, and includes a substrate having a first conductive type comprising an image area and a circuit area, a STI isolation layer in the substrate for electrical isolation within the circuit area,... Agent: Mckenna Long & Aldridge LLP

20090289289 - Dram cell with magnetic capacitor: A DRAM cell includes a substrate, a transistor, and a magnetic capacitor. The substrate is composed of semiconductor material with a main surface, the transistor is formed at the main surface, and the magnetic capacitor is formed in a metal layer. The magnetic capacitor includes a first magnetic layer, a... Agent: Chih Feng Yeh Brian M. Mcinnis

20090289288 - Integrated circuit including an insulating structure below a source/drain region and method: An integrated circuit including an insulating structure below a source/drain region and a method. One embodiment includes a memory cell with an access transistor and a storage element. A first source/drain region of the access transistor is electrically coupled to the storage element. A first insulating structure is disposed between... Agent: Dicke, Billig & Czaja

20090289290 - Non-volatile memory with programmable capacitance: Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer... Agent: Campbell Nelson Whipps, LLC

20090289291 - Soi deep trench capacitor employing a non-conformal inner spacer: A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion... Agent: Scully, Scott, Murphy & Presser, P.C.

20090289292 - Semiconductor memory device and method for forming capacitor thereof: A semiconductor device that is capable of preventing a storage node bunker defect or a defect due to loss of a barrier layer, and a method for forming a capacitor thereof. The semiconductor memory device includes a contact hole formed in an interlayer dielectric layer on a semiconductor substrate; a... Agent: Marshall, Gerstein & Borun LLP

20090289294 - Semiconductor device: The semiconductor device according to the present invention includes: a semiconductor layer; a trench dug downward from the surface of the semiconductor layer; a source region formed on the surface layer portion of the semiconductor layer adjacently to a first side of the trench in a prescribed direction; a drain... Agent: Rabin & Berdo, PC

20090289293 - Semiconductor device having tri-gate structure and manufacturing method thereof: A semiconductor device of an example of the invention comprises a memory cell and a select gate transistor provided for the memory cell. A gate electrode of the select gate transistor has a Tri-gate structure in which an upper surface of a gate insulating film formed above a channel of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090289295 - Semiconductor device and method of fabricating the same: The invention relates to semiconductor devices and a method of fabricating the same. In accordance with a method of fabricating a semiconductor device according to an aspect of the invention, a tunnel insulating layer, a first conductive layer, a dielectric layer, a second conductive layer, and a gate electrode layer... Agent: Marshall, Gerstein & Borun LLP

20090289296 - Semiconductor device and method of fabricating the same: A semiconductor device and a method of fabricating the same. In accordance with a method of fabricating a semiconductor device according to an aspect of the invention, a tunnel dielectric layer, a first conductive layer, a dielectric layer, a second conductive layer, and a gate electrode layer are sequentially stacked... Agent: Marshall, Gerstein & Borun LLP

20090289297 - Charge trap-type non-volatile memory device and method of fabricating the same: A charge trap-type non-volatile memory device, and related method, includes forming over a substrate a tunnel insulating layer, a charge trapping layer, a dielectric layer, and a conductive layer for a gate electrode; forming a gate electrode by selectively etching the conductive layer for the gate electrode; forming a spacer... Agent: Lowe Hauptman Ham & Berner, LLP

20090289298 - Self-aligned impact-ionization field effect transistor: An impact ionisation MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and... Agent: Haynes And Boone, LLPIPSection

20090289299 - High density high performance power transistor layout: A power transistor comprises a gate region, a source region, and a drain region. The gate region comprises a first line portion, a second line portion, and a third line portion. The first line portion couples to the second line portion so as to form a first V-shaped structure. The... Agent: North America Intellectual Property Corporation

20090289300 - Semiconductor device and method for producing the same: First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r1′ of the upper corner of the first fin-shaped semiconductor region located outside the first gate insulating film is greater than the... Agent: Mcdermott Will & Emery LLP

20090289301 - Laser annealing of metal oxide semiconductoron temperature sensitive substrate formations: A method of annealing a metal oxide on a temperature sensitive substrate formation includes the steps of providing a temperature sensitive substrate formation and forming a spacer layer on a surface of the temperature sensitive substrate formation. A metal oxide semiconductor device is formed on the spacer layer, the device... Agent: Robert A. Parsons

20090289303 - Method and apparatus for fabricating an ultra thin silicon on insulator: In one embodiment, the invention is a method and apparatus for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature,... Agent: Wall & Tong, LLP IBM Corporation

20090289302 - Semiconductor device and method of fabricating the same: element separation regions 120 for separating the first semiconductor element regions and the second semiconductor element regions, wherein the first semiconductor element regions are formed at the locations higher than those of the element separation regions 120 neighboring to the first semiconductor element regions.... Agent: Knobbe Martens Olson & Bear LLP

20090289304 - Co-integration of multi-gate fet with other fet devices in cmos technology: The present invention relates to a CMOS circuit device on a SOI substrate with an oriented silicon surface, comprising on a first substrate region a FET that has a FET channel region of a first conductivity type, and comprising on a second substrate region a FinFET that has a FinFET... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090289305 - Ultra-thin soi cmos with raised epitaxial source and drain and embedded sige pfet extension: A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe... Agent: Scully, Scott, Murphy & Presser, P.C.

20090289306 - Lateral oxidation with high-k dielectric liner: Disclosed are methods of making and using a high-K dielectric liner to facilitate the lateral oxidation of a high-K gate dielectric, integrated circuit structures containing the high-K dielectric liner and/or oxidized high-K gate dielectric, and other associated methods.... Agent: Turocy & Watson, LLP

20090289307 - Semiconductor device: A semiconductor device according to one embodiment includes: a semiconductor substrate having a SRAM region; an N-type element region formed in the SRAM region on the semiconductor substrate and including N-type source/drain regions; a P-type element region formed in the SRAM region on the semiconductor substrate so as to be... Agent: Turocy & Watson, LLP

20090289308 - Semiconductor device with a transistor having different source and drain lengths: A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusion regions are provided side-by-side in a... Agent: Mcdermott Will & Emery LLP

20090289309 - Method for reducing silicide defects in integrated circuits: A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the... Agent: HorizonIPPte Ltd

20090289310 - Semiconductor device and semiconductor device manufacturing method: A silicon-germanium non-formation region not formed with a silicon germanium layer and a silicon-germanium formation region formed with a silicon germanium layer are provided in a silicon chip, an internal circuit and an input/output buffer are arranged in the silicon-germanium formation region, and a pad electrode and an electrostatic protection... Agent: Turocy & Watson, LLP

20090289311 - Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error: A MISFET includes a drain diffusion layer of a first conductivity type, a source diffusion layer of the first conductivity type, a gate electrode, and a substrate/well of a second conductivity type. In the MISFET, first diffusion layers of the first conductivity type are provided at two or more positions... Agent: Mcginn Intellectual Property Law Group, PLLC

20090289312 - Semiconductor device and method of manufacturing the same: Provided is a semiconductor device including a first region, a source region, a second region, a drain region, a gate insulating layer, a field insulating layer and a gate electrode. The first region is formed in a surface area of a semiconductor substrate. The source region is formed in a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090289313 - Micro electric mechanical system device and method of producing the same: A MEMS device comprises a substrate, an island-shaped first insulating layer formed on the substrate, a second insulating film formed on the top and side surfaces of the first insulating layer and the top surface of the substrate, and having a thickness smaller than that of the first insulating layer,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090289314 - Micro-electromechanical resonance device with periodic structure: A Micro Electro Mechanical Systems resonance device includes a substrate, and an input electrode, connected to an alternating current source having an input frequency. The device also includes an output electrode, and at least one anchoring structure, connected to the substrate. The device further includes a vibratile structure connected to... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20090289315 - Semiconductor sensor and manufacturing method of sensor body for semiconductor sensor: A semiconductor sensor of which the thickness may be reduced and a method of manufacturing a sensor body for the semiconductor sensor are provided. A total length L1 of a weight portion 5 and an additional weight portion 3 as measured in an extending direction of a centerline C is... Agent: Rankin, Hill & Clark LLP

20090289316 - Optical semiconductor device: An optical semiconductor device comprises a distributed Bragg reflector layer of a first conductivity type, an optical absorption layer, and a semiconductor layer of a second conductivity type, sequentially formed on a semiconductor substrate; wherein said Bragg reflection layer of the first conductivity type has first semiconductor layers having a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090289318 - Electronics device package and fabrication method thereof: Embodiments provide an electronic device package and a method for fabricating thereof. A semiconductor chip has a substrate. A supporting brick is separated from the substrate by a certain distance. A bonding pad having a surface is disposed across the substrate and the supporting brick.... Agent: Quintero Law Office, PC

20090289317 - Packaging structure and method for fabricating the same: The present invention provides a packaging structure and a method for fabricating the same, the packaging structure includes a chip, a compatible pad provided on the chip, an intermediate metal layer electrically connecting with the compatible pad, a solder bump, and a redistribution metal layer electrically connecting with the solder... Agent: Frommer Lawrence & Haug LLP

20090289319 - Semiconductor device: A semiconductor device, that is approximately identical in package size to a semiconductor chip, such as a W-CSP, is devised to secure a wider area for sealing such as laser marking. A semiconductor substrate has a plurality of via electrodes extending from the bottom of the semiconductor substrate to top... Agent: Volentine & Whitt PLLC

20090289320 - Fast p-i-n photodetector with high responsitivity: A lateral p-i-n photodetector is provided that includes an array of vertical semiconductor nanowires of a first conductivity type that are grown over a semiconductor substrate also of the first conductivity type. Each vertically grown semiconductor nanowires of the first conductivity type is surrounded by a thick epitaxial intrinsic semiconductor... Agent: Scully, Scott, Murphy & Presser, P.C.

20090289321 - Thermal sensing and reset protection for an integrated circuit chip: There is provided a semiconductor package that includes a first semiconductor die mounted on a package substrate. The semiconductor package further includes a second semiconductor die mounted on the first semiconductor die and including a thermal sensing and reset protection circuit. The thermal sensing and reset protection circuit is configured... Agent: Farjami & Farjami LLP

20090289322 - Memory devices having a carbon nanotube: In a memory device having a carbon nanotube and a method of manufacturing the same, the memory device includes a lower electrode, an upper electrode having a first void exposing a sidewall of a diode therein, an insulating interlayer pattern having a second void exposing a portion of the lower... Agent: Myers Bigel Sibley & Sajovec

20090289323 - Apparatus for implementing multiple integrated circuits using different gate oxide thicknesses on a single integrated circuit die: An apparatus comprising plurality of functional integrated circuit blocks, each manufactured with different oxide thicknesses on a monolithic integrated circuit die, is described. Using different gate oxide thicknesses for different functional integrated circuit blocks provides reduced power consumption and increases performance in processing systems. Several embodiments comprising different combinations of... Agent: Qualcomm Incorporated

20090289324 - Mask overhang reduction or elimination after substrate etch: A method of forming IC devices includes providing a substrate and forming a patterned masking layer including at least one masked region having at least one masking layer, and a feature region bounded by the masking layer. Etching forms an etched feature in the substrate, wherein undercutting during the etching... Agent: Texas Instruments Incorporated

20090289325 - Semiconductor device with crack prevention ring: A crack prevention ring at the exterior edge of an integrated circuit prevents delamination and cracking during the separation of the integrated circuits into individual die. The crack prevention ring extends vertically into a semiconductor workpiece to at least a metallization layer of the integrated circuit. The crack prevention ring... Agent: Steven H. Slater Slater & Matsil, L.L.P.

20090289327 - Capacitor insulating film and method for forming the same, and capacitor and semiconductor device: A capacitor insulating film includes a laminated structure in which aluminum oxide films and titanium dioxide films are alternately laminated, wherein the titanium dioxide films each have a rutile crystal structure, and the ratio of the total thickness of the aluminum oxide films to the total thickness of the laminated... Agent: Mcdermott Will & Emery LLP

20090289328 - Insulation film for capacitor element, capacitor element and semiconductor device: An insulation film includes niobium, oxygen and a metal element, and the insulation film has a band gap width of larger than 4.2 eV, and at least a portion of the insulation film includes an amorphous structure.... Agent: Young & Thompson

20090289326 - Semiconductor device and method of fabricating the same: A semiconductor device, includes: a first storage node contact plug penetrating a first interlayer insulation layer and partially protruding above the first interlayer insulation layer; a second storage node contact plug contacting the first storage node contact plug that protrudes above the first interlayer insulation layer; a storage node contacting... Agent: Lowe Hauptman Ham & Berner, LLP

20090289329 - Differential varactor: A high-Q differential varactor includes reduced inner spacing dimensions between differential fingers.... Agent: Fish & Richardson P.C.

20090289330 - Group iii nitride semiconductor substrate, substrate for group iii nitride semiconductor device, and methods of making same: A III group nitride semiconductor substrate according to the present invention is fabricated by forming a metal film or metal nitride film 2′ with mesh structure in which micro voids are provided on a starting substrate 1, and growing a III group nitride semiconductor crystal layer 3 via the metal... Agent: Foley And Lardner LLP Suite 500

20090289332 - Methods for making substrates and substrates formed therefrom: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the... Agent: Winston & Strawn LLP Patent Department

20090289331 - Semiconductor chip and semiconductor device, and method of manufacturing the same: At least a part of an outer edge of a surface where a circuit forming region, for example, of a semiconductor substrate that forms a semiconductor chip is arranged (a region surrounded by a scribe line around the circuit forming region) is cut or polished, so as to form a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090289333 - Annealing a buffer layer for fabricating electronic devices on compliant substrates: A method of forming a thin-film layered electronic device over a flexible substrate comprises the steps of depositing a buffer layer over the flexible substrate, heating the substrate and buffer layer stack to a temperature at which plastic deformation of the buffer layer takes place, cooling the stack, then forming... Agent: JasIPConsulting

20090289334 - Metal gate structure and method of manufacturing same: A method of manufacturing a metal gate structure includes providing a substrate (110) having formed thereon a gate dielectric (120), a work function metal (130) adjacent to the gate dielectric, and a gate metal (140) adjacent to the work function metal; selectively forming a sacrificial capping layer (310) centered over... Agent: Intel Corporation C/o Cpa Global

20090289335 - Integrated circuit package system with shield and tie bar: An integrated circuit package system includes: providing a tie bar and a lead adjacent thereto; connecting an integrated circuit and the lead; mounting a shield over the integrated circuit with the shield connected to the tie bar; and encapsulating the integrated circuit and the shield. An integrated circuit package system... Agent: Law Offices Of Mikio Ishimaru

20090289337 - Lead frame: A lead frame comprises a die pad and leads arranged around the die pad. Through holes are provided in the die pad, and the through holes are located in the peripheries, i.e., margin area of the die pad. The through holes serve to be passed through by the metal wires... Agent: Squire, Sanders & Dempsey L.L.P.

20090289336 - Semiconductor device and method for manufacturing thereof: The present invention provides a semiconductor device including: a semiconductor chip; a lead frame provided with a recessed portion on at least one of an upper surface or a lower surface thereof, and electrically coupled to the semiconductor chip; and a resin section that molds the semiconductor chip and the... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090289338 - Semiconductor package and method for manufacturing the same: A semiconductor package includes a carrier, a chip, a stiffener and an encapsulant. The chip is disposed on the carrier. The stiffener is disposed around the chip, directly contacts the carrier, and is mounted on the carrier. The encapsulant is adapted to seal the chip and the stiffener.... Agent: Lowe Hauptman Ham & Berner, LLP

20090289339 - Semiconductor package and method for manufacturing the same: A semiconductor package includes a carrier, a chip, a stiffener and an encapsulant. The chip is disposed on the carrier. The stiffener is disposed around the chip, directly contacts the carrier, and is mounted on the carrier. The encapsulant is adapted to seal the chip and the stiffener.... Agent: Lowe Hauptman Ham & Berner, LLP

20090289341 - Semiconductor device: An object is to provide a highly reliable semiconductor device having resistance to external stress and electrostatic discharge while achieving reduction in thickness and size. Another object is to prevent defective shapes and deterioration in characteristics due to external stress or electrostatic discharge in a manufacture process to manufacture a... Agent: Eric Robinson

20090289340 - Semiconductor device and method for manufacturing the same: A conductive shield covering a semiconductor integrated circuit prevents electrostatic breakdown of the semiconductor integrated circuit (e.g., malfunction of a circuit and damage to a semiconductor element) due to electrostatic discharge. Further, with use of a pair of insulators between which the semiconductor integrated circuit is sandwiched, a highly reliable... Agent: Eric Robinson

20090289345 - Electronic device package and fabrication method thereof: An electronic device package and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor substrate containing a plurality of chips having a first surface and an opposite second surface. A plurality of conductive electrodes is disposed on the first surface and the conductive electrodes of the... Agent: Liu & Liu

20090289344 - Semiconductor device: A semiconductor device includes an insulating substrate; at least one semiconductor element mounted on a first principal surface of the insulating substrate; and a heat radiator joined through a solder member to a second principal surface of the insulating substrate opposite to the first principal surface on which the semiconductor... Agent: Kanesaka Berner And Partners LLP

20090289342 - Semiconductor device and semiconductor device manufacturing method: In an inventive semiconductor device production method, a one-side metal layer is first formed in a region located across a predetermined section line on one surface of a substrate. Further, an other-side metal layer is formed on the other surface of the substrate in a position opposed to the one-side... Agent: Rabin & Berdo, PC

20090289343 - Semiconductor package having an antenna: The present invention relates to a semiconductor package having an antenna. The semiconductor package includes a substrate, a chip, a molding compound and an antenna. The substrate has a first surface and a second surface. The chip is disposed on the first surface of the substrate, and electrically connected to... Agent: Mccracken & Frank LLP

20090289346 - Structure and manufacturing method of chip scale package: A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting... Agent: Mou-shiung Lin

20090289347 - Circuit board, lead frame, semiconductor device, and method for fabricating the same: A semiconductor device includes: an element mounting member including a first electrode; a semiconductor element mounted on the element mounting member and including a second electrode; and an interposer element mounted on the element mounting member with a first side of the interposer element facing one of a side of... Agent: Mcdermott Will & Emery LLP

20090289348 - Solution for package crosstalk minimization: A method of minimizing crosstalk in an IC package including (A) routing a first signal between first pads and a first trace layer in an congested area, (B) routing the first signal between the first and second trace layers in an non-congested area, (C) routing the first signal between the... Agent: Christopher P Maiorana, PC Lsi Corporation

20090289349 - Hermetic sealing of micro devices: An encapsulated device includes a micro device on a substrate, a micro chamber that encapsulates the micro device on the substrate; and a layer of hermetic-sealing material that provides at least some degree of hermeticity on one or more outer surfaces of the micro chamber to at least partially hermetically... Agent: Fish & Richardson P.C.

20090289350 - Semiconductor package, substrate, electronic device using such semiconductor package or substrate, and method for correcting warping of semiconductor package: Disclosed is a semiconductor package wherein a semiconductor chip is mounted on one surface of a substrate. In this semiconductor package, an inflection point forming portion made of a material having a higher coefficient of thermal expansion than the substrate is formed in a part of the substrate surface on... Agent: Sughrue Mion, PLLC

20090289353 - Covered devices in a semiconductor package: An embodiment of the present invention is a technique to fabricate a cover assembly. A cover has a base plate and sidewalls attached to perimeter of the base plate. The sidewalls have a height. A plurality of devices is attached to underside of the base plate. The devices have length... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090289351 - Semiconductor apparatus having both-side heat radiation structure and method for manufacturing the same: A semiconductor apparatus having a first surface and a second surface opposite to the first surface includes: a semiconductor chip having a front side and a backside; a first heat radiation member electrically and thermally coupled with the backside of the chip; a second heat radiation member electrically and thermally... Agent: Posz Law Group, PLC

20090289352 - Semiconductor device and a method for manufacturing the semiconductor device: A semiconductor device includes: a first substrate, having a grounding layer and holes formed therein for filling with an electroconductive material; a semiconductor chip over such first substrate; and an electroconductive heat releasing member, electrically coupled to the semiconductor chip able to release heat from the semiconductor chip. The heat... Agent: Young & Thompson

20090289354 - Electronic module: An electronic module. One embodiment includes a carrier. A first transistor is attached to the carrier. A second transistor is attached to the carrier. A first connection element includes a first planar region. The first connection element electrically connects the first transistor to the carrier. A second connection element includes... Agent: Dicke, Billig & Czaja

20090289355 - Semiconductor manufacturing apparatus and semiconductor device: A semiconductor manufacturing apparatus which performs a rapid heat treatment in which metallic thin films 11 and 12 to be metallic electrodes are formed on a top surface and a bottom surface of a silicon carbide semiconductor substrate 10, and thereafter, the silicon carbide semiconductor substrate 10 is heated. The... Agent: Foley And Lardner LLP Suite 500

20090289361 - Semiconductor device and method of manufacturing a semiconductor device: A semiconductor device includes at least a wiring board, a semiconductor chip that is mounted on one face side of the wiring board, connection pads that are formed on the one face side of the wiring board, and connect through bonding wires to electrode pads on the semiconductor chip, and... Agent: Young & Thompson

20090289358 - Semiconductor device, method of manufacturing the same, and substrate: A semiconductor device includes a substrate and a plurality of bumps. The substrate is compartmentalized into a bump-free area provided along four sides of the substrate and a bump area which is surrounded by the bump-free area. The plurality of bumps is aligned in the bump area. The plurality of... Agent: Young & Thompson

20090289357 - Semiconductor element and semiconductor device using the same: A semiconductor element includes: a substrate having an integrated circuit; and a wire connection electrode and a bump connection electrode which are provided on a same main surface of the substrate as electrodes having a same connection function to the integrated circuit. The wire connection electrode is provided in a... Agent: Mcdermott Will & Emery LLP

20090289359 - Semiconductor package and methods of manufacturing the semiconductor package: A semiconductor package and a method of manufacturing the semiconductor package are provided. A semiconductor package according to the present general inventive concept may include a base substrate having one surface on which a connection terminal is formed and a first package substrate having a molding layer covering the base... Agent: Stanzione & Kim, LLP

20090289356 - Wirebondless wafer level package with plated bumps and interconnects: A semiconductor package includes a carrier strip having a die cavity and a plurality of bump cavities. A semiconductor die is mounted in the die cavity of the carrier strip using a die attach adhesive. In one embodiment, a top surface of the semiconductor die is approximately coplanar with a... Agent: Robert D. Atkins

20090289360 - Workpiece contact pads with elevated ring for restricting horizontal movement of terminals of ic during pressing: A method of forming an electronic assembly including a plurality of IC die having bonding terminals that have a solderable material thereon and a workpiece. The workpiece includes workpiece contact pads including an elevated ring having a ring height at least 5 μm above a minimum contact pad height in... Agent: Texas Instruments Incorporated

20090289363 - Fine-pitch ball grid array package design: In one aspect, a method for configuring a ball grid array is disclosed. The method may include identifying a number of balls for use in a ball grid array, determining a number of rows and a number of columns for the ball grid array, and populating the ball grid array... Agent: Texas Instruments Incorporated

20090289362 - Low inductance ball grid array device having chip bumps on substrate vias: A high-frequency BGA device (500) with the chip (501) assembled by metal bumps (503) on an insulating substrate (502) with conductive vias (505) and metal traces (504). Chip bumps which serve the high frequency signal terminals are attached directly to the lands (510) on the vias in order to minimize... Agent: Texas Instruments Incorporated

20090289364 - Semiconductor device and a method for manufacturing the same: A semiconductor device according to the present invention includes: a semiconductor chip; a sealing resin layer formed on the semiconductor chip; and a post electrode formed in a through-hole penetrating through the sealing resin layer in a thickness direction, and having a hemispheric top surface.... Agent: Rabin & Berdo, PC

20090289368 - Interconnect structure having enhanced electromigration reliabilty and a method of fabricating same: An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner at least partially within a metal interconnect. In one embodiment, a “U-shaped” EM preventing liner is provided that abuts... Agent: Scully, Scott, Murphy & Presser, P.C.

20090289366 - Semiconductor device and manufacturing method of semiconductor device: In one aspect of the present invention, a semiconductor device may include an inter-wiring dielectric film in which a wiring trench is formed, a metal wiring layer formed in the wiring trench in the inter-wiring dielectric film, a first barrier layer formed on a side surface of the wiring trench,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090289367 - Semiconductor device and method of manufacturing the same: A copper interconnection layer is formed in an interconnection trench at a surface of an interlayer insulating film. A diffusion preventing insulating film is formed to cover the copper interconnection layer and is made of at least one of SiC and SiCN. An insulating film is formed on the copper... Agent: Mcdermott Will & Emery LLP

20090289365 - Structure and process for conductive contact integration: A semiconductor structure including a highly reliable high aspect ratio contact structure in which key-hole seam formation is eliminated is provided. The key-hole seam formation is eliminated in the present invention by providing a densified noble metal-containing liner within a high aspect ratio contact opening that is present in a... Agent: Scully, Scott, Murphy & Presser, P.C.

20090289369 - Memory device peripheral interconnects and method of manufacturing: An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the peripheral extend through the first inter-level dielectric layer to respective components. One or more vias and a plurality of dummy vias... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090289370 - Low contact resistance semiconductor devices and methods for fabricating the same: Low contact resistance semiconductor devices and methods for fabricating such semiconductor devices are provided. In accordance with one exemplary embodiment, a method comprises depositing an insulating material overlying a metal silicide region and etching a contact opening within the insulating material and exposing the metal silicide region. The contact opening... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20090289372 - Power supply network: A power supply network (2) for an integrated circuit is provided, the power supply network (2) comprising a supply grid (4); a plurality of supply pads (6), each supply pad (6) being in electrical contact with an edge of the supply grid (4); a current spreader (8) for at least... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090289373 - Semiconductor device: The present invention provides a semiconductor device capable of preventing occurrence of cracking and the like, taking a large area, where wiring and the like that function as elemental devices can be arranged, within a plurality of interlayer insulation films, and reducing production cost. The semiconductor device according to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090289374 - Semiconductor device, semiconductor device module, and method for manufacturing the semiconductor device module: A semiconductor device can include a plurality of semiconductor elements. The characteristics of each of the semiconductor elements can be easily tested during the production of the semiconductor device or when a failure occurs after the semiconductor device is mounted on a substrate, so that the quality can be well... Agent: Cermak Kenealy Vaidya & Nakajima LLP

20090289371 - Switching element and method of manufacturing the same: A switching element includes a first electrode, a second electrode, an ionic conductive portion and a buffer portion. The first electrode is configured to be available to feed metal ions. The ionic conductive portion is configured to contact the first electrode and the second electrode, and include an ionic conductor... Agent: Sughrue Mion, PLLC

20090289375 - Dual stress liner device and method: A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a process that uses the bottom overlapping layer as a stopper.... Agent: Banner & Witcoff, Ltd.

20090289376 - Light-proof chip packaging structure and method for its manufacture: The present invention discloses a light-proof chip packaging structure, which comprises an electronic substrate, at least one semiconductor chip installed on the electronic substrate, and a light-proof film. The light-proof film comprises a main portion, which is substantially conformable to cover all the non-concealed faces of the semiconductor chip. The... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090289377 - Semiconductor wafer: The present invention is a semiconductor wafer including an orientation identification mark, which is used for identifying crystal orientation, on a peripheral surface thereof, in which the orientation identification mark has a terraced structure that is concave toward an inner diameter direction of the semiconductor wafer with respect to a... Agent: Greenblum & Bernstein, P.L.C

20090289378 - Semiconductor wafer: The present invention is a semiconductor wafer including an orientation identification mark, which is used for identifying crystal orientation, on a peripheral surface thereof, in which the orientation identification mark is smoothly joined with a portion outside of the orientation identification mark on the peripheral surface, has a planar surface... Agent: Greenblum & Bernstein, P.L.C

20090289379 - Methods of manufacturing semiconductor devices and structures thereof: Methods of manufacturing semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming recesses in a first region and a second region of a workpiece. The first region of the workpiece is masked, and the recesses in the second region of... Agent: Slater & Matsil LLP

20090283735 - Carbon nano-film reversible resistance-switchable elements and methods of forming the same: Methods of forming a microelectronic structure are provided, the microelectronic structure including a first conductor, a discontinuous film of metal nanoparticles disposed on a surface above the first conductor, a carbon nano-film formed atop the surface and the discontinuous film of metal nanoparticles, and a second conductor disposed above the... Agent: Dugan & Dugan, PC

20090283736 - Nonvolatile memory element, manufacturing method thereof, and nonvolatile semiconductor apparatus using the nonvolatile memory element: A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having... Agent: Mcdermott Will & Emery LLP

20090283737 - Nonvolatile storage device and method for manufacturing same: A nonvolatile storage device having a plurality of unit memory layers, and a plurality of layer selection transistors is provided. The plurality of unit memory layers are laminated in a direction perpendicular to a layer surface of the unit memory layers. Each of the unit memory layers includes a plurality... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090283741 - Method of forming a phase changeable structure: The present invention relates to a method of forming a phase changeable structure wherein an upper electrode is formed on a phase changeable layer. A material including fluorine can be provided to the phase changeable layer and the upper electrode. The phase changeable layer can be etched to form a... Agent: Marger Johnson & Mccollom, P.C.

20090283739 - Nonvolatile storage device and method for manufacturing same: There is provided a nonvolatile storage device including a plurality of component memory layers. The plurality of component memory layers are stacked In a direction perpendicular to a layer surface. Each of the plurality of component memory layers includes a first wiring, a second wiring provided non-parallel to the first... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090283740 - Optimized solid electrolyte for programmable metallization cell devices and structures: A microelectronic programmable structure suitable for storing information and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure,... Agent: Snell & Wilmer L.L.P. (main)

20090283738 - Phase-change memory using single element semimetallic layer: Provided is a phase-change memory using a single-element semimetallic thin film. The device includes a storage node having a phase-change material layer and a switching element connected to the storage node, wherein the storage node includes a single-element semimetallic thin film which is formed between an upper electrode and a... Agent: Harness, Dickey & Pierce, P.L.C

20090283743 - Composite including nanoparticles, methods, and products including a composite: A composite comprising a first layer comprising a first material including nanoparticles dispersed therein, wherein the first material comprises a material capable of transporting charge, a second layer comprising a second material, and a backing element that is removably attached to the uppermost layer of the composite or the lowermost... Agent: Martha Ann Finnegan Qd Vision, Inc.

20090283742 - Methods and articles including nanomaterial: A method of depositing a nanomaterial onto a donor surface comprises depositing a composition comprising nanomaterial onto a donor surface from a micro-dispenser. In another aspect of the invention there is provided a method of depositing a nanomaterial onto a substrate. Methods of making a device including nanomaterial are disclosed.... Agent: Marthin Ann Finnegan Qd Vision, Inc.

20090283745 - Methods of making carbon nanotube films, layers, fabrics, ribbons, elements and articles: Methods of making carbon nanotube films, layers, fabrics, ribbons, elements and articles are disclosed. Carbon nanotube growth catalyst is applied on to a surface of a substrate. The substrate is subjected to a chemical vapor deposition of a carbon-containing gas to grow a non-woven fabric of carbon nanotubes. Portions of... Agent: Wilmerhale/boston

20090283744 - Thin film transistor: A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is electrically connected to the source electrode and the drain electrode. The gate electrode is insulated from the source electrode,... Agent: PCe Industry, Inc. Att. Steven Reiss

20090283746 - Light-emitting devices with modulation doped active layers: A semiconductor light emitting device has an n-type layer, a p-type layer, and a light-emitting active layer arranged between the p-type layer and the n-type layer, the active layer having alternating regions of doped and undoped materials. A double heterojunction light emitting device has a bulk active layer having doped... Agent: Marger Johnson & Mccollom/parc

20090283747 - Metallized silicon substrate for indium gallium nitride light emitting diode: A light emitting diode having a metallized silicon substrate including a silicon base, a buffer layer disposed on the silicon base, a metal layer disposed on the buffer layer, and light emitting layers disposed on the metal layer. The buffer layer can be AlN, and the metal layer ZrN. The... Agent: Bose Mckinney & Evans LLP

20090283749 - Quantum-well photoelectric device assembled from nanomembranes: A quantum-well photoelectric device, such as a quantum cascade laser, is constructed of monocrystalline nanoscale membranes physically removed from a substrate and mechanically assembled into a stack.... Agent: Wisconsin Alumni Research Foundation

20090283748 - Semiconductor for use in harsh environments: A gallium-nitride semiconductor apparatus may include an active region having one or more nitride-based barrier layers that are modulation-doped using a nitride-based doped layer. An active region may have at least two nitride-based barrier layers, and a nitride-based blocking layer may be disposed between the at least two barrier layers.... Agent: Cantor Colburn LLP- Baker Atlas

20090283750 - Substrate-free light emitting diode: A substrate-free light emitting diode (LED) including an epitaxy layer, a conductive supporting layer, and a first contact pad is provided. The epitaxy layer includes a first type doped semiconductor layer, a light emitting layer, and a second type doped semiconductor layer. The light emitting layer is disposed on the... Agent: Jianq Chyun Intellectual Property Office

20090283751 - Nanotubes and devices fabricated therefrom: Nanofluidic devices incorporating inorganic nanotubes fluidly coupled to channels or nanopores for supplying a fluid containing chemical or biochemical species are described. In one aspect, two channels are fluidly interconnected with a nanotube. Electrodes on opposing sides of the nanotube establish electrical contact with the fluid therein. A bias current... Agent: John P. O'banion O'banion & Ritchey LLP

20090283756 - Scalable quantum well device and method for manufacturing the same: A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well... Agent: Knobbe Martens Olson & Bear LLP

20090283752 - Thin film transistor: A thin film transistor includes a source electrode, a drain electrode, a semiconductor layer, a channel and a gate electrode. The drain electrode is spaced from the source electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The... Agent: PCe Industry, Inc. Att. Steven Reiss

20090283753 - Thin film transistor: A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is electrically connected to the source electrode and the drain electrode. The semiconductor layer comprises a plurality of carbon nanotubes.... Agent: PCe Industry, Inc. Att. Steven Reiss

20090283754 - Thin film transistor: A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is connected to the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the... Agent: PCe Industry, Inc. Att. Steven Reiss

20090283755 - Thin film transistor: A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is connected to the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the... Agent: PCe Industry, Inc. Att. Steven Reiss

20090283757 - Light-emitting element, light-emitting device, and electronic device: Disclosed is a light-emitting element with a good carrier balance and manufacturing method thereof which does not require the formation of the heterostructure. The light-emitting element includes an organic compound film containing a first organic compound as the main component (base material) between an anode and a cathode, wherein the... Agent: Cook Alex Ltd

20090283758 - Organic semiconductor, photoelectric conversion element and image device: wherein A1 represents O, S or N—R15; each of R11, R12, R13, R14 and R15 independently represents a hydrogen atom or a substituent W as defined in the specification, R11 and R12 may be linked to form a ring; B1 represents a ring structure containing at least one nitrogen atom;... Agent: Sughrue-265550

20090283761 - Method of cutting single crystals: e

20090283759 - Mos low power sensor with sacrifical membrane: A metal oxide semiconductor (MOS) device includes a substrate, a lower sacrificial membrane adjacent to the substrate, an upper thin film structure adjacent to the lower membrane, and a MOS material deposited on the upper thin film structure.... Agent: Honeywell International Inc. Patent Services

20090283762 - Semiconductor device and manufacturing method of the same: An object is to provide a semiconductor device with high aperture ratio or a manufacturing method thereof. Another object is to provide semiconductor device with low power consumption or a manufacturing method thereof. A light-transmitting conductive layer which functions as a gate electrode, a gate insulating film formed over the... Agent: Nixon Peabody, LLP

20090283760 - Semiconductor device having principal surface of polar plane and side surface at specific angle to nonpolar plane and manufacturing method of the same: A semiconductor device includes a substrate which is composed of a zinc oxide semiconductor having a hexagonal crystal structure and includes a first principal surface which is a polar plane; and four side surfaces which are adjacent to the first principal surface, the side surfaces being orthogonal to the principal... Agent: Rabin & Berdo, PC

20090283763 - Transistors, semiconductor devices and methods of manufacturing the same: A transistor having a self-align top gate structure and methods of manufacturing the same are provided. The transistor includes an oxide semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region. The transistor further includes a gate insulating layer... Agent: Harness, Dickey & Pierce, P.L.C

20090283765 - Semiconductor unit: A semiconductor unit includes a semiconductor chip, a ceramic substrate having a circuit pattern on which the semiconductor chip is mounted, and a temperature sensor for detecting a temperature. The semiconductor unit further includes a pressing member for retaining the temperature sensor by pressing against the ceramic substrate.... Agent: Woodcock Washburn LLP

20090283764 - Teg pattern for detecting void in device isolation layer and method of forming the same: Provided is a test element group (TEG) pattern for detecting a void in a device isolation layer. The TEG pattern includes active regions which are parallel to each other and extend in a first direction, a device isolation layer that separates the active regions, a first contact that is formed... Agent: Marger Johnson & Mccollom, P.C.

20090283766 - Methods for increasing film thickness during the deposition of silicon films using liquid silane materials: Embodiments in accordance with the present invention relate to the fabrication of thin (>1 μm) polycrystalline, nanocrystalline, or amorphous silicon films on a substrate. Particular embodiments utilize liquid sources of silane, including but not limited to cyclohexasilane (CHS), cyclopentasilane (CPS) or related derivatives of these compounds. In one embodiment, the... Agent: Townsend And Townsend And Crew, LLP

20090283768 - Array substrate of tft-lcd and a method for manufacturing the same: The present invention relates to an array substrate of TFT-LCD and Method for manufacturing the same. The array substrate includes: gate lines, data lines, pixel electrodes and TFTs formed on a substrate; and a grid graph formed on each of the pixel electrode to make each of the pixel electrodes... Agent: J C Patents

20090283769 - Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films: A gate wire including a plurality of gate lines and gate electrodes in the display area, and gate pads in the peripheral area is formed on a substrate having a display area and a peripheral area. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor... Agent: Haynes And Boone, LLPIPSection

20090283767 - Substrate for a display panel, a display panel having the substrate, a method of producing the substrate, and a method of producing the display panel: A substrate for a display panel by which a boundary position of divided exposure regions of elements formed by divisional exposure can be easily identified and process management and evaluation can be easily performed, a display panel having the substrate, a method of producing the substrate, and a method of... Agent: Birch Stewart Kolasch & Birch

20090283770 - Thin film transistor: A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is connected to the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the... Agent: PCe Industry, Inc. Att. Steven Reiss

20090283771 - Thin film transistor: A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is connected to the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the... Agent: PCe Industry, Inc. Att. Steven Reiss

20090283772 - Photo sensitive unit and pixel structure and liquid crystal display panel having the same: A pixel structure suitable for being disposed on a substrate is provided. The pixel structure includes a display unit and a photo sensitive unit. The display unit includes an active device and a pixel electrode. The active device is disposed on the substrate, and the pixel electrode is electrically connected... Agent: J C Patents

20090283774 - Organic light emitting display and method for making the same: An organic light emitting display and a method for making the same includes protection circuitry to avoid damage from static electricity. The display and method allow performing a lighting test during display manufacturing. The organic light emitting display includes a substrate, a display region on the transparent substrate with a... Agent: Christie, Parker & Hale, LLP

20090283773 - Production method of semiconductor device and semiconductor device: To provide a method for producing a high-performance semiconductor device by a simple and low-temperature process. The method for producing a semiconductor device, in accordance with the present invention, is a production method of a semiconductor device including a first insulating film, a semiconductor layer, and a second insulating film... Agent: Nixon & Vanderhye, PC

20090283775 - Semiconductor device: Semiconductor elements deteriorate or are destroyed due to electrostatic discharge damage. The present invention provides a semiconductor device in which a protecting means is formed in each pixel. The protecting means is provided with one or a plurality of elements selected from the group consisting of resistor elements, capacitor elements,... Agent: Eric Robinson

20090283776 - Wide band gap semiconductor device and method for producing the same: A wide band gap semiconductor device is disclosed. A first trench in a gate electrode part and a second trench in a source electrode part (Schottky diode part) are disposed so that the first and second trenches are close to each other while and the second trench is deeper than... Agent: Rossi, Kimms & Mcdowell LLP.

20090283777 - Multifaced microdevice system array: A multisurfaced microdevice system array is produced from a wafer formed of semiconductor substrate material. Sensing, controlling and actuating microdevices are fabricated at specific location on both sides of the wafer, and the wafer is diced. Each die thus created is then formed into a multisurfaced, multifaced structure having outer... Agent: Brooks Kushman P.C.

20090283778 - Electroluminescent display useful for displaying a predetermined pattern: An electroluminescent display comprising semiconductor nanocrystals, wherein the semiconductor nanocrystals are selected to emit light at a predetermined wavelength and are disposed in a predetermined pattern. In certain embodiments, semiconductor nanocrystals that emit light at different predetermined wavelengths are disposed in the display to create a predetermined multi-color pattern.... Agent: Qd Vision, Inc.

20090283779 - Light source with near field mixing: A light emitting diode (LED) component comprising a submount with an array of LED chips and a lens over the array of LED chips. A diffuser is arranged so that at least some light from the LEDs passes through the diffuser to mix the LED light in the near field.... Agent: Koppel, Patrick, Heybl & Dawson

20090283780 - Illumination system: An illumination system has a mounting substrate (4) for mounting and electrically contacting a plurality of light-emitting diodes (R, A, G, B). A first category of the light-emitting diodes (G, B) comprises a first translucent substrate (11) provided with an active layer (1) on an outer surface (13) of the... Agent: Philips Intellectual Property & Standards

20090283781 - Mini v smd: In one embodiment, a surface-mount device comprises a casing having opposed, first and second main surfaces, side surfaces, and end surfaces. A lead frame partially encased by the casing comprises (1) an electrically conductive LED chip carrier part having a surface carrying a linear array of LEDs adapted to be... Agent: Koppel, Patrick, Heybl & Dawson

20090283782 - Nitride semiconductor device: There is provided a nitride semiconductor light emitting device having a vertical type device in which a pair of electrodes is formed on both sides of a chip, by using a semiconductor substrate, and having high luminous efficiency by using MgxZn1-xO (0≦x≦0.5) as the substrate which is enable to prevent... Agent: Rabin & Berdo, PC

20090283786 - Light emitting device and electronic apparatus: A light emitting device includes: a light emitting element which includes a first electrode layer, a second electrode layer, and a light emitting function layer disposed between the first electrode and the second electrode; a reflection layer which reflects light emitted from the light emitting function layer toward the light... Agent: Oliff & Berridge, PLC

20090283785 - Light emitting diode package: There is provided a light emitting diode (LED) package in which a phosphor layer encapsulating an LED chip is formed uniformly to facilitate a process. The LED package includes: a package body having a mounting area; a holding part mounted on the mounting area to expose a portion of the... Agent: Mcdermott Will & Emery LLP

20090283783 - Optoelectronic semiconductor chip and method for producing it: An optoelectronic semiconductor chip (12) is disclosed comprising a thin-film semiconductor body (8), which comprises a semiconductor layer sequence (2, 20) having an active region (3) suitable for generating radiation, and comprising a carrier layer (7), which is formed on the semiconductor layer sequence and carries the thin-film semiconductor body.... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090283787 - Semiconductor light emitting diodes having reflective structures and methods of fabricating same: Light emitting diodes include a diode region having first and second opposing faces that include therein an n-type layer and a p-type layer, an anode contact that ohmically contacts the p-type layer and extends on the first face, and a cathode contact that ohmically contacts the n-type layer and also... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090283784 - Side-view light emitting diode: An exemplary side-view light emitting diode (LED) includes a substrate, a housing, a LED chip, a capsulation material and a reflecting layer. The housing and the substrate cooperatively form a receiving space therebetween. The LED chip is received in the receiving space and electrically connected with the substrate. The capsulation... Agent: PCe Industry, Inc. Att. Steven Reiss

20090283790 - Circuit substrate and light emitting diode package: A circuit substrate including a base layer and a plurality of lead units arranged as an array is provided, wherein the base layer has a plurality of through grooves, and the lead units are disposed on the base layer. Each of the lead units includes a common terminal and at... Agent: Jianq Chyun Intellectual Property Office

20090283788 - Light-emitting diode chip package body and method for manufacturing same: A light-emitting diode chip package body with an excellent heat dissipation performance and a low manufacturing cost, and a packaging method of the same are disclosed. A LED chip package body is provided, the LED chip package body comprising: a LED chip having an electrode-side surface and at least two... Agent: Houston Eliseeva

20090283791 - Multilayered lead frame for a semiconductor light-emitting device: A lead frame (100) for a semiconductor device is formed by applying nickel plating (102), palladium plating (103), and gold flash plating (104) substantially entirely to lead frame body (101) such as copper thin plate in this order, and further applying silver plating (105) selectively to part of an inner... Agent: Mcdermott Will & Emery LLP

20090283789 - Semiconductor light emitting device: The present disclosure relates to a semiconductor light emitting device which generates light by recombination of electrons and holes, and which includes: a first finger electrode for supplying one of the electrons and holes, a second finger electrode supplying the other of the electrons and holes, and spaced apart from... Agent: Harness, Dickey, & Pierce, P.l.c

20090283792 - Side view light emitting diode package: A side view LED package for a backlight unit includes a package body having a cavity with an inclined inner sidewall, first and second lead frames arranged in the package body, the cavity of the package body exposing a portion of at least one of the first and second lead... Agent: Mcdermott Will & Emery LLP

20090283794 - Curable resin material composition, optical material, light-emitting device, method for producing light-emitting device, and electronic device: A curable resin material composition includes an addition-polymerization-curable silicone resin material that gives a silicone resin having a glass transition temperature of 50° C. or less when cured, the addition-polymerization-curable silicone resin material including, a SiH-group-containing siloxane-based compound containing a SiH group where a silicon atom is bonded to a... Agent: K&l Gates LLP

20090283793 - Nitride semiconductor light-emitting device and production method thereof: Disclosed is a semiconductor device which is improved in output power efficiency since reflection by the substrate is reduced. This semiconductor device is also excellent in strength characteristics of a supporting substrate. Also disclosed is a method for producing such a semiconductor device. Specifically disclosed is a nitride semiconductor device... Agent: Sughrue Mion, PLLC

20090283795 - Method for producing group iii nitride semiconductor light emitting device, group iii nitride semiconductor light emitting device, and lamp: Provided is a method in which a buffer layer 12 composed of a group III nitride compound is laminated on a substrate 11 and then an n-type semiconductor layer 14 provided with an underlying layer 14a, a light emitting layer 15, and an p-type semiconductor layer 16 are sequentially laminated... Agent: Sughrue Mion, PLLC

20090283797 - Semiconductor device: There is provided a semiconductor device in which an amount of fluctuations in output capacitance and feedback capacitance is reduced. In a trench-type insulated gate semiconductor device, a width of a portion of an electric charge storage layer in a direction along which a gate electrode and a dummy gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090283796 - Semiconductor device and method for forming the same: A bipolar high voltage/power semiconductor device having a low voltage terminal and a high voltage terminal is disclosed. The bipolar high voltage/power semiconductor is a vertical insulated gate bipolar transistor with injection efficiency adjustment formed by highly doped n+ islands in a p+ anode layer. The device has a vertical... Agent: Wpat, PC Intellectual Property Attorneys

20090283798 - Semiconductor device and manufacturing method thereof: A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the... Agent: Posz Law Group, PLC

20090283799 - Reduced free-charge carrier lifetime device: According to one embodiment, a semiconductor device comprises a body of a first conductivity type having a source region and a channel, the body being in contact with a top contact layer. The device also comprises a gate arranged adjacent the channel and a drift zone of a second conductivity... Agent: Coats & Bennett/infineon Technologies

20090283800 - Photoelectrochemical etching of p-type semiconductor heterostructures: A method for photoelectrochemical (PEC) etching of a p-type semiconductor layer simply and efficiently, by providing a driving force for holes to move towards a surface of a p-type cap layer to be etched, wherein the p-type cap layer is on a heterostructure and the heterostructure provides the driving force... Agent: Gates & Cooper LLP Howard Hughes Center

20090283801 - Bipolar transistor with low resistance base contact and method of making the same: Embodiments of the present invention provide a bipolar transistor with low resistance base contact and method of manufacturing the same. The bipolar transistor includes an emitter, a collector, and an intrinsic base between the emitter and the collector. The intrinsic base extends laterally to an extrinsic base. The extrinsic base... Agent: Greenblum & Bernstein, P.L.C

20090283802 - Heterojunction bipolar transistor device with electrostatic discharge ruggedness: A heterojunction bipolar transistor (HBT) device and system having electrostatic discharge ruggedness, and methods for making the same, are disclosed. An HBT device having electrostatic discharge ruggedness may include one or more emitter fingers including an emitter layer, a transition layer formed over the emitter layer, and an emitter cap... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20090283803 - Electromechanical memory array using nanotube ribbons and method for making same: Electromechanical circuits, such as memory cells, and methods for making same are disclosed. The circuits include a structure having electrically conductive traces and supports extending from a surface of the substrate, and nanotube ribbons suspended by the supports that cross the electrically conductive traces, wherein each ribbon comprises one or... Agent: Wilmerhale/boston

20090283804 - Solid-state image sensor, solid-state image sensing device, and method of producing the same: It is an object to provide a CCD solid-state image sensor, in which an area of a read channel is reduced and a rate of a surface area of a light receiving portion (photodiode) to an area of one pixel is increased. There is provided a solid-state image sensor, including:... Agent: Brinks Hofer Gilson & Lione

20090283805 - Biosensor containing ruthenium, measurement using the same and the application thereof: A biosensor containing ruthenium, measurement using the same, and the application thereof. The biosensor comprises an extended gate field effect transistor (EGFET) structure, including a metal oxide semiconductor field effect transistor (MOSFET), a sensing unit comprising a substrate, a layer comprising ruthenium on the substrate, and a metal wire connecting... Agent: Quintero Law Office, PC

20090283806 - Mosfet with asymmetrical extension implant: A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20090283807 - Anti-reflection structures for cmos image sensors: Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light... Agent: Scully, Scott, Murphy & Presser, P.C.

20090283808 - Photo sensor: A photo sensor has an insulator layer for covering a diode stack, and the insulator layer is made of photoresist to reduce a side leakage current.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090283809 - Image sensor structure and integrated lens module thereof: An image sensor structure and an integrated lens module thereof are provided. In the image sensor structure with the integrated lens module, the image sensor structure comprises a chip and a lens module. The chip has light-sensing elements, first conducting pads, and a conducting channel. The light-sensing elements are electrically... Agent: Juan Carlos A. Marquez C/o Stites & Harbison PLLC

20090283810 - Integrated circuit arrangements with esd-resistant capacitor and corresponding method of production: A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20090283811 - Flash memory device and methods of forming the same: A flash memory device and/or methods of forming the flash memory device are provided, the flash memory device including a charge storage gate, a gate pattern over the charge storage gate, and a charge storage metal layer disposed between a side surface of the charge storage gate and the gate... Agent: Harness, Dickey & Pierce, P.L.C

20090283812 - Nonvolatile semiconductor memory device and manufacturing method thereof: An object is to suppress reading error even in the case where writing and erasing are repeatedly performed. Further, another object is to reduce writing voltage and erasing voltage while increase in the area of a memory transistor is suppressed. A floating gate and a control gate are provided with... Agent: Nixon Peabody, LLP

20090283813 - Nonvolatile semiconductor memory device and method for fabricating nonvolatile semiconductor memory device: According to an aspect of the present invention, there is provided a method for fabricating a nonvolatile semiconductor memory device including a memory cell being formed in a first region of a semiconductor substrate and a periphery circuit being formed in a second region of the semiconductor substrate, including forming... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090283814 - Single-poly non-volatile memory cell: A non-volatile memory cell includes an ion well of a semiconductor substrate; a first half-transistor having a firs select gate, a first diffusion region in the ion well, and a first gate dielectric layer between the first select gate and the ion well; a second half-transistor disposed adjacent to the... Agent: North America Intellectual Property Corporation

20090283815 - Semiconductor device including nonvolatile memory and method for fabricating the same: A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090283816 - Band engineered high-k tunnel oxides for non-volatile memory: A non-volatile memory cell that has a charge source region, a charge storage region, and a crested tunnel barrier layer that has a potential energy profile which peaks between the charge source region and the charge storage region. The tunnel barrier layer has multiple high-K dielectric materials, either as individual... Agent: Campbell Nelson Whipps, LLC

20090283818 - Flash memory device and method of fabricating the same: A flash memory device includes an isolation layer formed on an isolation region of a semiconductor substrate, a tunnel insulating layer formed on an active region of the semiconductor substrate, a first conductive layer formed over the tunnel insulating layer, a dielectric layer formed on the first conductive layer and... Agent: Marshall, Gerstein & Borun LLP

20090283817 - Floating gate structures: Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with... Agent: Cool Patent, P.C. C/o Cpa Global

20090283820 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes a memory cell array having a cell transistor and a selective transistor provided on a semiconductor substrate. The cell transistor includes a tunnel insulation film, a charge accumulation layer, a block insulation film, and a gate electrode on the substrate. The charge accumulation layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090283821 - Nonvolatile memory and manufacturing method thereof: Isolation trenches are formed in the main surface of a semiconductor substrate, and isolation regions. are embedded in these trenches. First insulating films, charge storage layers, a second insulating film, and a control gate are formed on the main surface of the semiconductor substrate sectioned by the isolation regions. Shielding... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090283819 - Nonvolatile semiconductor memory device and method for manufacturing same: A nonvolatile semiconductor memory device includes: a substrate; a plurality of dielectric films and electrode films which are alternately stacked on the substrate and have a through hole penetrating in the stacking direction; a semiconductor pillar formed inside the through hole; and a charge storage layer provided at least between... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090283822 - Non-volatile memory structure and method for preparing the same: A non-volatile memory structure includes a substrate having two doped regions, a charge-trapping structure positioned substantially between the two doped regions, and a conductive structure positioned on the charge-trapping structure, wherein the charge-trapping structure includes a silicon-oxy-nitride layer and metallic nano-dots embedded in the silicon-oxy-nitride layer. The non-volatile memory structure... Agent: Wpat, PC Intellectual Property Attorneys

20090283823 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device includes: a semiconductor layer; a first conductivity type region of a first conductivity type formed in a base layer portion of the semiconductor layer; a body region of a second conductivity type formed in the semiconductor layer to be in contact with the first conductivity type region;... Agent: Rabin & Berdo, PC

20090283824 - Cool impact-ionization transistor and method for making same: In one embodiment, the disclosure relates to a low-power semiconductor switching device, having a substrate supporting thereon a semiconductor body; a source electrode coupled to the semiconductor body at a source interface region; a drain electrode coupled to the semiconductor body at a drain interface region; a gate oxide film... Agent: Snell & Wilmer L.L.P. (grumman)

20090283825 - High speed orthogonal gate edmos device and fabrication: An orthogonal gate extended drain MOSFET (EDMOS) structure provides a low gate-to-drain capacitance (CGD) and exhibits increased reliability. It has a gate electrode that is folded into the shallow trench isolation (STI) oxide region. Horizontal and vertical gate electrode segments provide gate control. It accommodates both high voltage devices and... Agent: Vern Maine & Associates

20090283826 - Semiconductor device and method of forming high voltage soi lateral double diffused mosfet with shallow trench insulator: A semiconductor device has a buried oxide layer formed over a substrate. An active silicon layer is formed over the buried oxide layer. A drain region is formed in the active silicon layer. An LDD drift region is formed in the active silicon layer adjacent to the drain region. The... Agent: Robert D. Atkins

20090283827 - Formation of a mosfet using an angled implant: A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary... Agent: Texas Instruments Incorporated

20090283828 - Reduced floating body effect without impact on performance-enhancing stress: A method, gated device and design structure are presented for providing reduced floating body effect (FBE) while not impacting performance enhancing stress. One method includes forming damage in a portion of a substrate adjacent to a gate; removing a portion of the damaged portion to form a trench, leaving another... Agent: Hoffman Warnick LLC

20090283830 - Dual metal gate self-aligned integration: A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method... Agent: Scully, Scott, Murphy & Presser, P.C.

20090283829 - Finfet with a v-shaped channel: A fin-type field effect transistor (finFET) structure comprises a substrate having a planar upper surface, an elongated fin on the planar upper surface of the substrate (wherein the length and the height of the fin are greater that the width of the fin) and an elongated gate conductor on the... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090283831 - Electrostatic discharge (esd) protection applying high voltage lightly doped drain (ldd) cmos technologies: An electrostatic discharge (ESD) protection circuit includes a triggering diode that includes a junction between a P-grade (PG) region and an N-well. The PG region has a dopant profile equivalent to a P-drain dopant profile of a PMOS transistor having a breakdown voltage represented by V whereby the triggering diode... Agent: Bo-in Lin

20090283832 - Semiconductor device: A semiconductor device, which is connected to a protected device and protects a protected device, includes a semiconductor layer provided on an insulating film; a plurality of source layers which is formed in the semiconductor layer and extends in a first direction; a plurality of drain layers which is formed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090283833 - Integrated circuits having a contact structure having an elongate structure and methods for manufacturing the same: In an embodiment, an integrated circuit is provided. The integrated circuit may include an active area extending along a first direction corresponding to a current flow direction through the active area, a contact structure having an elongate structure. The contact structure may be electrically coupled with the active area. Furthermore,... Agent: Slater & Matsil, L.L.P.

20090283835 - Method for fabricating a dual workfunction semiconductor device and the device made thereof: A method for manufacturing a dual workfunction semiconductor device and the device made thereof are disclosed. In one aspect, the method includes manufacturing a first transistor in a first region and a second transistor in a second region of a substrate, the first transistor including a first gate stack, the... Agent: Knobbe Martens Olson & Bear LLP

20090283834 - Semiconductor device and manufacturing method thereof: A MOS semiconductor device including MOSFETs each of which has a gate portion formed on a semiconductor substrate and source/drain regions includes sidewall insulating films formed on the side portions of the gate portions in the gate length direction, alloy layers formed on the source/drain regions, taper adjusting insulating films... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090283836 - Cmos structure including protective spacers and method of forming thereof: The present invention provides a semiconductor device includes a substrate including a semiconducting region and isolation regions, a gate structure including a high-k gate dielectric layer atop the semiconducting region of the substrate and a metal gate conductor layer atop the high-k gate dielectric; protective nitride spacers enclosing the high-k... Agent: Scully, Scott, Murphy & Presser, P.C.

20090283838 - Fabrication of self-aligned cmos structure: A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of... Agent: Innovation Interface, LLC

20090283839 - Semiconductor device and semiconductor substrate: In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a... Agent: Mattingly & Malur, P.C.

20090283837 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is elevated or recessed with respect to a top... Agent: Slater & Matsil LLP

20090283840 - Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor: A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously... Agent: Scully, Scott, Murphy & Presser, P.C.

20090283841 - Schottky device: An integrated circuit structure has a metal silicide layer formed on an n-type well region, a p-type guard ring formed on the n-type well region and encircling the metal silicide layer. The outer portion of the metal silicide layer extends to overlap the inner edge of the guard ring, and... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20090283842 - Semiconductor device and method of fabricating the same: A semiconductor device according to one embodiment includes: a semiconductor substrate comprising first and second transistor regions that are isolated by an element isolation region; a first impurity diffusion suppression layer formed on the semiconductor substrate in the first transistor region; a second impurity diffusion suppression layer formed on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090283843 - Nmos transistor including extended nldd-drain for improved ruggedness: A MOS transistor includes a conductive gate insulated from a semiconductor layer by a first dielectric layer, lightly-doped source/drain regions being formed self-aligned to respective first and second edges of the conductive gate, a source region being formed self-aligned to a first spacer, a drain region being formed a first... Agent: Patent Law Group LLP

20090283844 - Process of fabricating microfluidic device chips and chips formed thereby: A process for fabricating multiple microfluidic device chips. The process includes fabricating multiple micromachined tubes in a semiconductor device wafer. The tubes are fabricated so that each tube has an internal fluidic passage and an inlet and outlet thereto defined in a surface of the device wafer. The device wafer... Agent: Hartman & Hartman, P.C.

20090283845 - Sensing apparatus with packaging material as sensing protection layer and method of manufacturing the same: A sensing apparatus includes a holding substrate, a sensing chip and a protection layer. The sensing chip is mounted on the holding substrate and electrically connected to the holding substrate. The sensing chip has a sensing region and a non-sensing region other than the sensing region. The sensing region senses... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090283846 - Backside controlled mems capacitive sensor and interface and method: Described herein is the sense element assembly for a capacitive pressure sensor and method for creating same that has increased sensitivity despite the parasitic capacitance that is created. The capacitive sensor element assembly, comprises a first semiconductive layer, and a first conductive layer, a first dielectric layer into which a... Agent: Jeffer, Mangels, Butler & Marmaro, LLP

20090283847 - Semiconductor package including through-hole electrode and light-transmitting substrate: An imaging element is formed on the first main surface of a semiconductor substrate. An external terminal is formed on the second main surface of the semiconductor substrate. A through-hole electrode is formed in a through hole formed in the semiconductor substrate. A first electrode pad is formed on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090283848 - Photodiode assembly with improved electrostatic discharge damage threshold: A photodiode with an improved electrostatic damage threshold is disclosed. A Zener or an avalanche diode is connected in parallel to a photodiode. Both diodes are integrated into the same photodiode housing. The diodes can be mounted on a common header or onto each other. An avalanche photodiode and an... Agent: Pequignot + Myers LLC

20090283849 - Image sensor and method for manufacturing the same: Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a substrate provided with a transistor circuit, first and second interconnections separated from each other on the substrate, a first conductive-type conductive layer formed at side surfaces of the first interconnection, a second conductive-type... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090283850 - Optical sensor and method of making the same: An optical sensor includes a silicon-rich dielectric photosensitive device and a read-out device. The silicon-rich dielectric photosensitive device includes a first electrode, a second electrode, and a photosensitive silicon-rich dielectric layer disposed therebetween. The photosensitive silicon-rich dielectric layer includes a plurality of nanocrystalline silicon crystals therein. The read-out device is... Agent: North America Intellectual Property Corporation

20090283851 - Novel schottky diode for high speed and radio frequency application: A semiconductor diode that eliminates leakage current and reduces parasitic resistance is disclosed. The semiconductor diode comprises a semiconductor substrate; a semiconductor layer disposed on the semiconductor substrate, wherein the semiconductor layer includes a first dopant and a first well with a Schottky region; and a polysilicon device positioned above... Agent: Haynes And Boone, LLPIPSection

20090283852 - Stress-inducing structures, methods, and materials: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.... Agent: Slater & Matsil LLP

20090283853 - Programmable devices and methods of manufacture thereof: Programmable devices, methods of manufacture thereof, and methods of programming devices are disclosed. In one embodiment, a programmable device includes a link and at least one first contact coupled to a first end of the link. The at least one first contact is adjacent a portion of a top surface... Agent: Slater & Matsil LLP

20090283854 - Design structure and method for buried inductors for ultra-high resistivity wafers for soi/rf sige applications: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high resistivity substrate and a buried inductor formed directly in the high resistivity substrate and devoid of an insulating layer therebetween.... Agent: Greenblum & Bernstein, P.L.C

20090283855 - Semiconductor device and process for manufacturing the same: An inductor having a helicoidal shape is provided on an insulation film formed on a semiconductor substrate. A conductive thin layer (a plating layer) is provided on a surface of the inductor. A conductivity of the conductive thin layer is higher than that of the inductor. According to the constitution,... Agent: Mcdermott Will & Emery LLP

20090283859 - Integrated circuit arrangements with esd-resistant capacitor and corresponding method of production: A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20090283856 - Method for fabricating a semiconductor capacitpr device: A method for fabricating a semiconductor capacitor includes a substrate having thereon a carbon electrode. A transitional barrier layer is then deposited on the carbon electrode layer. Thereafter, a metal oxide layer is deposited on the transitional barrier layer, which reacts with the underlying transitional barrier layer to form a... Agent: North America Intellectual Property Corporation

20090283857 - Method of manufacturing capacitor of semiconductor device: A method for manufacturing a semiconductor device includes sequentially forming an insulating layer and a metal layer over a semiconductor substrate, forming a photoresist pattern over the metal layer and etching the metal layer using the photoresist pattern as an etching mask to form a metal line pattern, subjecting the... Agent: Sherr & Vaughn, PLLC

20090283858 - Scalable integrated circuit high density capacitors: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to form the capacitors. The capacitors use different metallization patterns to form the metal... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090283860 - High precision semiconductor chip and a method to construct the semiconductor chip: An embodiment for manufacturing an electronic circuit forms at least one first structure on a semiconductor substrate, determines at least one electrically defined characteristic of the at least one first structure, selects a reticle corresponding to the measured characteristic, and forms at least one additional structure on the semiconductor substrate... Agent: Stmicroelectronics, Inc.

20090283861 - Semiconductor device, method for manufacturing semiconductor device, and power amplifier element: A semiconductor device is presented, which includes a semiconductor substrate with a high concentration impurity of a first type conductivity and an epitaxial layer with a low concentration impurity provided on the semiconductor substrate, where a trench coupled to the semiconductor substrate is provided in the epitaxial layer with the... Agent: Sughrue Mion, PLLC

20090283862 - Semiconductor device having insulated gate bipolar transistor: One of the aspects of the present invention is to provide a semiconductor device, which includes a semiconductor layer of a first conductive type having first and second surfaces. The semiconductor layer includes a base region of a second conductive type formed in the first surface and an emitter region... Agent: Mcdermott Will & Emery LLP

20090283863 - Semiconductor device having insulated gate bipolar transistor: One of the aspects of the present invention is to provide a semiconductor device, which includes a semiconductor layer of a first conductive type having first and second surfaces. The semiconductor layer includes a base region of a second conductive type formed in the first surface and an emitter region... Agent: Mcdermott Will & Emery LLP

20090283864 - Semiconductor device: In order to reduce a device area, a bipolar transistor using temperature characteristics of a forward voltage generated between an emitter and a base has a structure in which a high concentration second conductivity type impurity region for a base electrode and a high concentration first conductivity type impurity region... Agent: Bruce L. Adams, Esq Adams & Wilks

20090283865 - Electrochemical method to make high quality doped crystalline compound semiconductors: A process for fabricating doped crystalline semiconductors is provided using layer by layer deposition of semiconductors and the corresponding dopants.... Agent: Connolly Bove Lodge & Hutz LLP

20090283866 - Semiconductor substrate and a method of manufacturing the same: The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as... Agent: Slater & Matsil LLP

20090283867 - Integration structure of semiconductor circuit and microprobe sensing elements and method for fabricating the same: The present invention discloses an integration structure of a semiconductor circuit and microprobe sensing elements and a method for fabricating the same. In the method of the present invention, a semiconductor circuit is fabricated on one surface of a semiconductor substrate, and the other surface of the semiconductor substrate is... Agent: Rosenberg, Klein & Lee

20090283868 - Structure replication through ultra thin layer transfer: Methods and apparatus for forming a product from ultra thin layers of a base material are disclosed. Some embodiments provide a process that allows one to structure a silicon base material, like the ingot, and to transfer this structure into a respective silicon process step. Some embodiments provide a process... Agent: Ibm Corporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20090283869 - Scribe line structure for wafer dicing and method of making the same: The scribe line structure for wafer dicing according to the present invention includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and an upper one of the metal structures has a lower metal density than a lower one of the metal structures. In another... Agent: North America Intellectual Property Corporation

20090283870 - Semiconductor device and method of conforming conductive vias between insulating layers in saw streets: A semiconductor device is made by disposing a plurality of semiconductor die on a carrier and creating a gap between each of the semiconductor die. A first insulating material is deposited in the gap. A portion of the first insulating material is removed. A conductive layer is formed over the... Agent: Robert D. Atkins

20090283872 - Package structure of three-dimensional stacking dice and method for manufacturing the same: This invention provides a package structure of three-dimensional stacking dice and its manufacturing method. This invention employs the Through-Silicon-Vias (TSVs) technology to establish vertical electrical connection of the three-dimensional stacking dice and a redistribution layer between a blind hole-on-pad and a vertical through hole formed by the TSVs technology to... Agent: Birch Stewart Kolasch & Birch

20090283871 - System, structure, and method of manufacturing a semiconductor substrate stack: A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact... Agent: Slater & Matsil, L.L.P.

20090283873 - Method for forming self-alignment insulation structure: A method for forming a self-align insulation of a passing gate is disclosed. First, a substrate is provided. A deep trench filled with silicon material and a shallow trench isolation adjacent to the deep trench are formed in the substrate. A patterned pad oxide and a patterned hard mask are... Agent: North America Intellectual Property Corporation

20090283874 - Semiconductor device manufacturing method and semiconductor device: Disclosed is a semiconductor device manufacturing method in which a silicon nitride film is formed to cover an n-channel transistor formed on a semiconductor substrate and to apply a tensile stress in a channel length direction to a channel of the n-channel transistor, the method includes: forming a first-layer silicon... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090283875 - Self-supported film and silicon wafer obtained by sintering: Self-supported film and silicon wafer obtained by sintering. A silicon wafer for a photovoltaic cell is produced by a debinding step of a self-supported film formed of at least one main thin layer comprising at least 50% volume of silicon particles, devoid of silicon oxide and encapsulated in a polymer... Agent: Oliff & Berridge, PLC

20090283876 - Electromagnetic interference shield for semiconductors using a continuous or near-continuous peripheral conducting seal and a conducting lid: A semiconductor package structure including a conductive adhesive material which is used to form an electromagnetic interference shield-forming Faraday cage. The Faraday cage incorporates a module lid as the top surface thereof, the conductive material as the sides and a laminate ground plane(s) or substrate as its bottom. Also disclosed... Agent: Scully, Scott, Murphy & Presser, P.C.

20090283877 - Semiconductor device and manufacturing method thereof: A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface... Agent: Birch, Stewart, Kolasch & Birch, LLP

20090283878 - Lead-on-chip semiconductor package and leadframe for the package: A LOC semiconductor package with the leadframe for the package is revealed. The LOC semiconductor package primarily comprises a plurality of leadframe's leads, at least a tie bar, a chip, and an encapsulant encapsulating the components mentioned above. Each lead has a bonding finger. The tie bar has a dummy... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090283880 - Semiconductor chip package assembly with deflection- resistant leadfingers: The invention relates to leadframes and semiconductor chip package assemblies using leadframes, and to methods for their assembly. A disclosed embodiment of the invention includes a semiconductor package leadframe with a chip mounting surface for receiving a semiconductor chip and a plurality of leadfingers. The leadfingers have a proximal end... Agent: Texas Instruments Incorporated

20090283879 - Semiconductor device and method: A chip carrier includes first, second and third layers with the second layer situated between the first and third layers. The first and third layers are formed of a first material and the second layer is formed of a second material. The second layer has a plurality of holes extending... Agent: Dicke, Billig & Czaja

20090283884 - Lead frame, semiconductor package including the same, and method of manufacturing the lead frame and the semiconductor package: Provided are a lead frame, a semiconductor package, and a method of manufacturing the lead frame and the semiconductor package. The lead frame includes: a die pad on which a semiconductor chip is installable; a plurality of lead patterns formed around a circumference of the die pad; an insulating organic... Agent: Sughrue Mion, PLLC

20090283882 - Qfn semiconductor package and fabrication method thereof: A quad flat non-lead (QFN) semiconductor package includes a die attach pad having a recessed area; a semiconductor die mounted inside the recessed area of the die attach pad; at least one row of inner terminal leads disposed adjacent to the die attach pad; first wires bonding respective said inner... Agent: North America Intellectual Property Corporation

20090283881 - Semiconductor chip package structure for achieving face-down electrical connection without using a wire-bonding process and method for making the same: A semiconductor chip package structure for achieving face-down electrical connection without using a wire-bonding process includes a package unit, a semiconductor chip, a substrate unit, a first insulative unit, a first conductive unit, a second conductive unit, and a second insulative unit. The semiconductor chip has a plurality of conductive... Agent: Rosenberg, Klein & Lee

20090283883 - Semiconductor device using lead frame: A semiconductor device includes: a semiconductor chip configured to process a signal in a radio frequency band; two conductive antenna connection pins connected with two external antenna conductors, respectively; an island for the semiconductor chip to be mounted thereon; a suspending pin connected with the island; and an antenna connection... Agent: Foley And Lardner LLP Suite 500

20090283886 - Ic card: The present invention includes an IC card that can realize high function without increasing the size of an IC chip, and that can realize cost reduction. The IC card has a first single crystal integrated circuit, a second integrated circuit, and a display device. The second integrated circuit and the... Agent: Eric Robinson

20090283885 - Semiconductor device and a method of manufacturing the same: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the... Agent: Miles & Stockbridge PC

20090283887 - Optical semiconductor device: An optical semiconductor device of the present invention includes a semiconductor chip (11) having an optical element (12) formed on a surface of the semiconductor chip; and a transparent member (13) directly secured on the semiconductor chip (11) with a transparent adhesive (25) so as to cover the optical element... Agent: Steptoe & Johnson LLP

20090283889 - Integrated circuit package system: An integrated circuit package system includes: providing a heat spreader; attaching an upper substrate to the heat spreader, the upper substrate having an upper through-opening provided therein; attaching a top semiconductor die to the heat spreader through the upper through-opening, the top semiconductor die having a top die interconnect to... Agent: Law Offices Of Mikio Ishimaru

20090283888 - Package system incorporating a flip-chip assembly: A package system including providing a first semiconductor die; mounting a second semiconductor die on the first semiconductor die using an inter-die interconnect to form a flip-chip assembly; and attaching the flip-chip assembly on a package substrate with a contact pad, a test connection, a z-bond pad, and a die... Agent: Law Offices Of Mikio Ishimaru

20090283890 - Semiconductor multi-package module including tape substrate land grid array package stacked over ball grid array package: A single metal layer tape substrate includes a patterned metal layer affixed to a patterned dielectric layer. The dielectric layer is patterned to provide openings exposing lands and bond sites on bond fingers on the land side of the metal layer. The metal layer is patterned to provide circuit traces... Agent: Law Offices Of Mikio Ishimaru

20090283892 - Design method of semiconductor package substrate: When the impedance of a first circuit is deviated from a standard value, a second circuit is designed for generating a second reflected wave to cancel a first reflected wave generated by the first circuit. Individual structural parts in a transmission line are intentionally designed to be deviated from a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090283891 - Elastically deformable integrated-circuit device: The present invention relates to an integrated-circuit device comprising a multitude of separate rigid substrate islands (202 to 208) with circuit elements, a respective substrate island being connected to respective neighbor substrate islands by respective elastically deformable connections 210 to 222), which contain at least one respective signaling layer that... Agent: Philips Intellectual Property & Standards

20090283893 - Integrated circuit package system with slotted die paddle and method of manufacture thereof: A method of manufacture of an integrated circuit package system including: providing a selective slot die paddle having selective slots and edge pieces around the perimeter; providing extended leads protruding into the selective slots; mounting an integrated circuit die on the selective slot die paddle; and coupling bond wires between... Agent: Law Offices Of Mikio Ishimaru

20090283894 - Semiconductor chip package and printed circuit board having through interconnections: A semiconductor chip package includes a signal interconnection penetrating a semiconductor chip and transmitting a signal to the semiconductor chip and a power interconnection and a ground interconnection penetrating the semiconductor and supplying power and ground to the semiconductor chip. The power interconnection and the ground interconnection are arranged to... Agent: Stanzione & Kim, LLP

20090283896 - Package structure and method: A semiconductor die has a surface and an active region on the surface. A thick-film coating is applied to the surface of the semiconductor die to cover only a portion or entire of the active region before the semiconductor die is cut from a wafer. The thick-film coating reduces the... Agent: Rosenberg, Klein & Lee

20090283895 - Semiconductor device and method for manufacturing the same: A semiconductor device including a metal frame having a penetrating opening; a semiconductor chip provided in the opening; an insulating layer provided on the upper surface of the metal frame such that the insulating layer covers the upper surface, which is the circuit-formed surface of the semiconductor chip; an interconnect... Agent: Sughrue Mion, PLLC

20090283897 - Semiconductor package, method for manufacturing a semiconductor package, an electronic device, method for manufacturing an electronic device: A semiconductor package including a substrate with a semiconductor device mounted on the substrate and a resin member sealing the substrate and semiconductor device. The resin member includes a first surface and a second surface located on the other side of the first surface and a plurality of leads electrically... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090283898 - Disabling electrical connections using pass-through 3d interconnects and associated systems and methods: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated... Agent: Perkins Coie LLP Patent-sea

20090283899 - Semiconductor device: According to one embodiment of the present invention, a semiconductor device is provided, that includes a semiconductor carrier; a cavity formed within the semiconductor carrier, the cavity extending from the top surface of the semiconductor carrier into the semiconductor carrier; and at least one semiconductor chip provided within the cavity.... Agent: Slater & Matsil, L.L.P.

20090283900 - Semiconductor device and manufacturing method for semiconductor device: A semiconductor device comprises: (a) a wiring board having front surface lands disposed on a front surface and rear surface lands disposed on a rear surface; (b) a semiconductor chip formed with an integrated circuit and electrode terminals electrically connected to the integrated circuit; and (c) a sealing resin that... Agent: Steptoe & Johnson LLP

20090283901 - Semiconductor device and multilayer wiring board: A gas or an insulating material having a relative dielectric constant of not more than 2.5 on average is interposed between a first wiring layer and a second wiring layer included in a multilayer wiring structure. Between a wiring of the first wiring layer and a wiring of the second... Agent: Foley And Lardner LLP Suite 500

20090283902 - Semiconductor package structures having liquid coolers integrated with first level chip package modules: Semiconductor package structures are provided which are designed to have liquid coolers integrally packaged with first level chip modules. In particular, apparatus for integrally packaging a liquid cooler device within a first level chip package structure include structures in which a liquid cooler device is thermally coupled directly to the... Agent: F. Chau & Associates, LLC

20090283903 - Bump with multiple vias for semiconductor package and fabrication method thereof, and semiconductor package utilizing the same: A bump for a semiconductor package forms a polymer layer having multiple vias on an electrode pad above a semiconductor chip to increase an electrical contact area between the electrode pad and a metal bump. Further, the bump forms a polymer layer having multiple vias on a redistribution electrode pad... Agent: Marger Johnson & Mccollom, P.C.

20090283905 - Conductive structure of a chip: A conductive structure of a chip is provided. The conductive structure comprises a ground layer, a dielectric layer, a redistribution layer, an under bump metal and a solder bump. The ground layer electrically connects to the ground pad of the chip, while the dielectric layer overlays the ground layer. Thus,... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090283904 - Flipchip bump patterns for efficient i-mesh power distribution schemes: Disclosed is a flipchip scheme where power and ground bumps are arranged in a striped configuration. Specifically, there are a plurality of lines of power bumps, and a plurality of lines of ground bumps. Each line of power bumps is interconnected by a mesh core power bus, and each line... Agent: Lsi Corporation

20090283906 - Semiconductor device, method for mounting semiconductor device, and mounting structure of semiconductor device: A semiconductor device of the present invention includes a semiconductor substrate on which an electrode and a Cu bump are stacked, and on the electrode and the Cu bump, a metal bump layer is provided, in which (i) a solder layer via which the semiconductor device is bonded and electrically... Agent: Nixon & Vanderhye, PC

20090283907 - Low-resistance interconnects and methods of making same: Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present invention relate to disposing a conductive material in a trench without disposing a resistive barrier material between the conductive material and the sidewalls of the trench so that the... Agent: Michael G. Fletcher Fletcher Yoder

20090283908 - Metal line of semiconductor device and method for forming the same: A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate and a metal line forming region is formed in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer, and the diffusion layer... Agent: Ladas & Parry LLP

20090283910 - Semiconductor device and fabrication method thereof: A semiconductor device includes: a metal-containing compound layer on a semiconductor substrate; a dielectric film on the semiconductor substrate and the metal-containing compound layer; a contact hole penetrating through the dielectric film to reach the metal-containing compound layer; a contact plug in the contact hole. The semiconductor device further includes... Agent: Mcdermott Will & Emery LLP

20090283909 - Semiconductor device and manufacturing method thereof: There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface... Agent: Mcdermott Will & Emery LLP

20090283911 - Backend interconnect scheme with middle dielectric layer having improved strength: An integrated circuit structure includes a first, a second and a third metallization layer. The first metallization layer includes a first dielectric layer having a first k value; and first metal lines in the first dielectric layer. The second metallization layer is over the first metallization layer, and includes a... Agent: Slater & Matsil, L.L.P.

20090283912 - Damascene wiring fabrication methods incorporating dielectric cap etch process with hard mask retention: Methods for fabricating metal wiring layers of a semiconductor device are provided where damascene interconnect structures are formed in a BEOL process that incorporates a dielectric cap-open-first process to achieve hard mask retention and to control the gouging of a buffer oxide layer to prevent exposure of underlying features protected... Agent: Keusey, Tutunjian & Bitetto, P.C.

20090283913 - Semiconductor device and method for fabricating semiconductor device: A semiconductor device includes: a copper (Cu) wire having a first region and a second region in which densities of silicon (Si) and oxygen (O) atoms are higher than in the first region; a compound film that is selectively formed on the Cu wire and contains Cu and Si; and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090283914 - Silicon interposer and method for manufacturing the same: A method for manufacturing a silicon interposer, includes a step of forming a protection film on a surface, on which an element portion is formed, of a silicon wafer, a step of forming open holes according to planar arrangements of through holes which pass through the silicon wafer in a... Agent: Rankin, Hill & Clark LLP

20090283915 - Oversized contacts and vias in layout defined by linearly constrained topology: A rectangular-shaped interlevel connection layout structure is defined to electrically connect a first layout structure in a first chip level with a second layout structure in a second chip level. The rectangular-shaped interlevel connection layout structure is defined by an as-drawn cross-section having at least one dimension larger than a... Agent: Martine Penilla & Gencarella, LLP

20090283916 - Chip structure and method of reworking chip: A method of reworking a chip includes providing a first chip and a second chip. The first and second chips have at least one first module and at least one second module, respectively. The first and second modules electrically connect with each other. The first module of the first chip... Agent: J C Patents

20090283918 - Semiconductor chip package structure: A semiconductor chip package structure is described. The semiconductor chip package structure comprises a first chip, which is operated through a first power connection, having a central region and a marginal region. The first chip comprises a plurality of first and second power bonding pads disposed in a marginal region... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090283917 - Systems and methods for vertical stacked semiconductor devices: Systems and methods fabricate a vertically stacked multi-chip semiconductor device assembly. An exemplary assembly is fabricated by forming a first semiconductor device in a first semiconductor device layer with a first connector located at a first surface of the first semiconductor device layer; forming a second semiconductor device in a... Agent: Honeywell International Inc. Patent Services

20090283919 - Semiconductor package featuring flip-chip die sandwiched between metal layers: Embodiments in accordance with the present invention relate to flip-chip packages for semiconductor devices, which feature a die sandwiched between metal layers. One metal layer comprises portions of the lead frame configured to be in electrical and thermal communication with various pads on a first surface of the die (e.g.... Agent: Townsend And Townsend And Crew, LLP

20090283920 - Ball-bump bonded ribbon-wire interconnect: A ball-bump bonded ribbon-wire interconnect has a ball-bump attached to an integrated circuit's bond pad. A ribbon-wire has one end attached to the ball-bump and its opposing end attached to a substrate's metallized surface. The ribbon-wire may be wider than the ball-bump, and the ball-bump may separate the ribbon-wire from... Agent: Thomas F. Lenihan Tektronix, Inc.

20090283921 - Contact layout structure: A contact layout structure includes a substrate having at least a first region defined thereon, plural sets of first contact layouts positioned along a predetermined direction in the first region, and a plurality of second contact layouts positioned in the first region. Each set of the first contact layout has... Agent: North America Intellectual Property Corporation

20090283922 - Integrating high stress cap layer in high-k metal gate transistor: In some embodiments an etchstop layer is deposited over a transistor that has been encapsulated by a high-K film, a silicon nitride is deposited over the deposited etchstop layer, the silicon nitride is removed, and the etchstop layer is removed. Other embodiments are described and claimed.... Agent: Intel Corporation C/o Cpa Global

20090278107 - Phase change memory device: The phase change memory device includes a first electrode and a second electrode and a first phase change material pattern and a second phase change material pattern interposed between the first electrode and the second electrode, wherein the first and second phase change material patterns have respectively different electrical characteristics.... Agent: Lee & Morse, P.C.

20090278109 - Confinement techniques for non-volatile resistive-switching memories: Confinment techniques for non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. A resistive switching memory element described herein includes a first electrode adjacent to an interlayer dielectric, a spacer over at... Agent: Legal Department

20090278110 - Non-volatile resistive-switching memories formed using anodization: Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide.... Agent: Legal Department

20090278108 - Phase change memory device having phase change material layer containing phase change nano particles and method of fabricating the same: A phase change memory device including a phase change material layer having phase change nano particles and a method of fabricating the same are provided. The phase change memory device may include a first electrode and a second electrode facing each other, a phase change material layer containing phase change... Agent: Harness, Dickey & Pierce, P.L.C

20090278111 - Resistive changing device: A device that incorporates teachings of the present disclosure may include, for example, a memory array having a first array of nanotubes, a second array of nanotubes, and a resistive change material located between the first and second array of nanotubes. Other embodiments are disclosed.... Agent: Akerman Senterfitt

20090278112 - Methods for etching carbon nano-tube films for use in non-volatile memories: Memory cells, and methods of forming such memory cells are provided that include a steering element coupled to a carbon-based reversible resistivity-switching material. In particular embodiments, methods in accordance with this invention etch a carbon nano-tube (“CNT”) film formed over a substrate, the methods including coating the substrate with a... Agent: Dugan & Dugan, PC

20090278113 - Nitride semiconductor light emitting device: There is provided a nitride semiconductor light emitting device. A nitride semiconductor light emitting device according to an aspect of the invention may include: an n-type nitride semiconductor layer provided on a substrate; an active layer provided on the n-type nitride semiconductor layer, and including quantum barrier layers and quantum... Agent: Mcdermott Will & Emery LLP

20090278114 - Control of carbon nanotube diameter using cvd or pecvd growth: The diameter of carbon nanotubes grown by chemical vapor deposition is controlled independent of the catalyst size by controlling the residence time of reactive gases in the reactor.... Agent: Connolly Bove Lodge & Hutz LLP

20090278118 - Benzofluoranthene compound and organic light-emitting device using the compound: e

20090278115 - Nitrogen-containing heterocyclic derivative and organic electroluminescence element using the same: A novel nitrogen-containing heterocyclic derivative having a specific structure and an organic electroluminescence device comprising an anode, a cathode and an organic thin film layer which comprises a single layer or a plurality of layers comprising at least a light emitting layer and is disposed between the anode and the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090278119 - Oled display with extended lifetime: The present invention relates to an organic light-emitting diode which has a light-emitting layer C which comprises at least one hole-conducting material CA and at least one phosphorescence emitter CB, to mixtures comprising at least one carbene complex in combination with at least one hole-conducting material or in combination with... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090278117 - Organic thin film transistor, method of manufacturing the same, and biosensor using the transistor: An organic thin film transistor (OTFT), a method of manufacturing the same, and a biosensor using the OTFT are provided. The OTFT includes a gate electrode, a gate insulating layer, source and drain electrodes, and an organic semiconductor layer disposed on a substrate and further includes an interface layer formed... Agent: Rabin & Berdo, PC

20090278116 - Transistor, organic semiconductor device, and method for manufacture of the transistor or device: The invention provides a process for production of a transistor and an organic semiconductor element which allows satisfactory formation of active layers on desired surfaces, even if the active layers are organic semiconductor compound-containing active layers imparted with prescribed properties beforehand. A preferred mode of the process for production of... Agent: Sughrue Mion, PLLC

20090278122 - Amorphous oxide and thin film transistor: The present invention relates to an amorphous oxide and a thin film transistor using the amorphous oxide. In particular, the present invention provides an amorphous oxide having an electron carrier concentration less than 1018/cm3, and a thin film transistor using such an amorphous oxide. In a thin film transistor having... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090278121 - System for displaying images and fabrication method thereof: A system for displaying images includes a thin film transistor array substrate including a substrate with thin film transistors array and at least one light-sensing element containing an amorphous silicon layer formed on the substrate, wherein the light-sensing element has a current flow direction perpendicular to the substrate.... Agent: Liu & Liu

20090278120 - Thin film transistor: There is provided a thin film transistor (TFT) capable of improving electron mobility and minimizing the occurrence of hysteresis due to traps. The TFT includes a channel layer and a gate insulating layer, wherein the channel layer is made of an oxide semiconductor. In the TFT, the gate insulating layer... Agent: Fenwick & West LLP

20090278124 - Scribe based bond pads for integrated circuits: An apparatus including a semiconductor substrate is disclosed. A first semiconductor die is disposed on the semiconductor substrate. A first bond out pad is disposed on the semiconductor substrate adjacent to the first semiconductor die. A first sawn semiconductor die is disposed on the semiconductor substrate adjacent to the first... Agent: Schwegman, Lundberg & Woessner / Atmel

20090278123 - Testing wiring structure and method for forming the same: The invention provides a testing wiring structure of a thin film transistor (TFT) motherboard for applying signals to a plurality of signal lines in a pixel region on the motherboard and a method for forming the same. The testing wiring structure comprises a gate layer metallic testing wiring and a... Agent: Ladas & Parry LLP

20090278125 - Crystalline semiconductor films, growth of such films and devices including such films: The present invention describes an approach to grow highly crystalline semiconductor films, multilayers of semiconductor thin films on foreign substrate such as glass, quartz. Specifically, The film were grown by first forming crystalline seeds, and transferring the seeds onto the substrate, and growing continuous semiconductor film through epitaxial growth... Agent: Xiangfeng Duan

20090278126 - Metal line substrate, thin film transistor substrate and method of forming the same: A metal line substrate and a method of fabricating thereof, the metal line substrate including an insulating layer and a capping layer disposed on an insulating substrate, a trench defined by the insulating layer and the capping layer disposed on the insulating substrate, a seed layer pattern disposed on the... Agent: Cantor Colburn, LLP

20090278130 - Array substrate, liquid crystal display panel having the same and liquid crystal display device having the same: In an array substrate, an LCD panel having the same and an LCD device having the same, the array substrate may include an insulating substrate, a switching element (e.g., a transistor such as a TFT), a main pixel portion, a coupling capacitor and a sub-pixel portion. The switching element may... Agent: Haynes And Boone, LLPIPSection

20090278129 - Liquid crystal display device and method of fabricating the same: A liquid crystal display device includes a gate line and a data line crossing each other to define a pixel region on a substrate, a gate electrode connected to the gate line, a gate insulating layer on the gate electrode, an active layer on the gate insulating layer, source and... Agent: Holland & Knight LLP

20090278128 - Thin film transistor array panel and manufacturing method of the same: A thin film transistor array panel includes a substrate; a gate electrode formed on the substrate; a data line formed on the substrate; a gate insulating layer formed on the data line and the gate electrode, and having a first contact hole exposing the gate electrode, and a second contact... Agent: Cantor Colburn, LLP

20090278127 - Thin-film transistor and method of manufacturing the same: In one embodiment, a thin-film transistor (TFT) includes a gate electrode, a semiconductor pattern, first and second electrodes and a protective layer. The semiconductor pattern is formed on the gate electrode, and includes a first semiconductor layer deposited at a first deposition speed and a second semiconductor layer deposited at... Agent: Haynes And Boone, LLPIPSection

20090278132 - Array substrate of liquid crystal display device having thin film transistor on color filter and method of fabricating the same: An array substrate of a liquid crystal display device having a color filter on a gate metal layer, and a data metal layer formed on the color filter. First a gate insulating layer is formed on the gate metal layer to protect and a second gate insulating layer is formed... Agent: F. Chau & Associates, LLC

20090278134 - Semiconductor device and method of manufacturing the semiconductor device: In a semiconductor device according to the present invention, an insulator layer on a substrate is provided with a trench. A gate electrode is formed in the trench so that an upper surface of the gate electrode is approximately flush with an upper surface of the insulator layer. On the... Agent: Birch Stewart Kolasch & Birch

20090278131 - Thin film transistor array arrangement, organic light emitting display device having the same, and manufacturing method thereof: A thin film transistor (TFT) array arrangement, an organic light emitting display device that includes the TFT array arrangement and a method of making the TFT array arrangement and the organic light emitting display device. The method seeks to reduce the number of masks used in the making of the... Agent: Robert E. Bushnell & Law Firm

20090278133 - Thin film transistor array panel and method for manufacturing the same, and liquid crystal display: A thin film transistor array panel includes a substrate, a first thin film transistor formed on the substrate, a color filter formed on the first thin film transistor and having a through hole, a capping layer formed on the color filter and having an opening, and a pixel electrode formed... Agent: F. Chau & Associates, LLC

20090278135 - Thin film transistor, method of manufacturing the same, and display device using the same: Disclosed herein is a thin film transistor, including: a gate electrode; a crystallized semiconductor layer formed through a gate insulating film on the gate electrode; and a drain electrode and a source electrode provided on both end sides of the crystallized semiconductor layer, respectively, and provided through impurity doped layers... Agent: Sonnenschein Nath & Rosenthal LLP

20090278136 - Process for growth of low dislocation density gan: High quality free standing GaN is obtained using a new modification of the Epitaxial Lateral Overgrowth technology in which 3D islands or features are created only by tuning the growth parameters. Smoothing these islands (2D growth) is achieved thereafter by setting growth conditions producing enhanced lateral growth. The repetition of... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090278137 - Semiconductor devices with non-punch-through semiconductor channels having enhanced conduction and methods of making: Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs),... Agent: Morris Manning Martin LLP

20090278138 - Laminated structure and image display device: A laminated structure includes a wettability variable layer formed on a substrate, including a material whose critical surface tension varies by receiving energy so that high and low surface energy regions are formed; a conductive layer formed in one of the high surface energy regions; and an insulating layer formed... Agent: Cooper & Dunham, LLP

20090278139 - Light-emitting diode package assembly: An electrical device containing multiple light emitting diode (LED) dies each having respective first and second connectors suitable to receive current through the LED die. A common base layer of a first electrically conductive material has cavities into which at least one LED die is mounted with its second connector... Agent: The Tpl Group

20090278140 - Manufacturing method of semiconductor device: A manufacturing method of a semiconductor device comprises the steps of: providing a substrate; forming a plurality of grooves on the substrate by photolithograph etching or laser engraving, wherein the plurality of grooves divides a surface of the substrate into a plurality of mesas and the substrate is a patterned... Agent: Wpat, PC Intellectual Property Attorneys

20090278141 - Light-emitting devices and displays with improved performance: Light-emitting devices and displays with improved performance are disclosed. A light-emitting device includes an emissive material disposed between a first electrode, and a second electrode. Various embodiments include a device having a peak external quantum efficiency of at least about 2.2%; a device that emits light having a CIE color... Agent: Qd Vision, Inc.

20090278142 - Light-emitting diode display and method for manufacturing the same: A method for manufacturing a light-emitting diode display is provided. The method includes pre-fixing first, second, and third light-emitting diodes on a light emitting unit production substrate to produce light-emitting units each including first, second, and third light-emitting diodes, first electrodes of the first, second, and third light-emitting diodes being... Agent: K&l Gates LLP

20090278143 - Semiconductor light emitting device: A plurality of transistors are formed on a substrate in a plurality of columns. Each transistor has a first conductivity type region and second conductivity type regions provided on both sides thereof in a column direction, and has an active layer on the side of each second conductivity type region... Agent: Rabin & Berdo, PC

20090278155 - Backlight device for liquid crystal display including a plurality of light emitting diodes within their own concaves aligned in a straight line within a larger concave: A semiconductor light emitting device of the present invention includes a plurality of light emitting elements, a package body for storing the light emitting elements, wiring patterns being electrically connected to the light emitting elements, and Au wires for electrically connecting the light emitting elements and the wiring patterns, the... Agent: Morrison & Foerster LLP

20090278154 - Led module and method of manufacturing the same: Provided are a light emitting diode (LED) module and a method of manufacturing the same. The LED module may include a package housing including an inner space, a light-emitting chip in the inner space of the package housing, a phosphor layer including a fluorescent material and converting light emitted from... Agent: Harness, Dickey & Pierce, P.L.C

20090278153 - Light emitting device: Provided is a light emitting device. The light emitting device comprises a package body, a plurality of electrodes, a light emitting diode, and a lens. The package body comprises a trench. The plurality of electrodes is disposed on and/or in the package body. The light emitting diode is disposed on... Agent: Birch Stewart Kolasch & Birch

20090278149 - Light emitting diode: An LED (20) includes a base (24), a chip (21) and an encapsulation (22) made of a transparent material. The base has a concave depression (240). The chip is mounted on a bottom of the concave depression. The first encapsulation is received in the depression for sealing the chip. The... Agent: PCe Industry, Inc. Att. Steven Reiss

20090278152 - Light emitting diode and package method thereof: A light emitting diode comprises a sheet-like package body, a barricade, a light emitting diode die, and fluorescent filler. The sheet-like package body has a die-bonding region. The barricade is a transparent wall that is disposed on the die-bonding region, and is integrated with the sheet-like package body or is... Agent: Wpat, PC Intellectual Property Attorneys

20090278151 - Light emitting diode packages, light emitting diode systems and methods of manufacturing the same: In a method of forming an LED semiconductor device, and in an LED semiconductor device, an LED is provided on a substrate. A first encapsulant material layer is provided on the LED, and the first encapsulant material layer is firstly annealed. A luminescence conversion material layer is provided on the... Agent: Mills & Onello LLP

20090278148 - Light-emitting diode and method for fabrication thereof: A transparent-substrate light-emitting diode (10) has a light-emitting layer (133) made of a compound semiconductor, wherein the area (A) of a light-extracting surface having formed thereon a first electrode (15) and a second electrode (16) differing in polarity from the first electrode (15), the area (B) of a light-emitting layer... Agent: Sughrue Mion, PLLC

20090278150 - Method for forming metal electrode, method for manufacturing semiconductor light emitting elements and nitride based compound semiconductor light emitting elements: A method for forming a metal electrode and a method for manufacturing semiconductor light emitting elements include providing a substrate having a semiconductor layer formed thereon; forming a bonding metal layer and a reflective metal layer on the semiconductor layer; and forming a metal electrode by layer inversion of the... Agent: H.c. Park & Associates, PLC

20090278156 - Molded chip fabrication method and apparatus: A light emitting diode (LED) is disclosed comprising a plurality of semiconductor layers with a first contact on the bottom surface of the semiconductor layers and a second contact on the top surface of the semiconductor layer. A coating is included that comprises a cured binder and a conversion material... Agent: Koppel, Patrick, Heybl & Dawson

20090278144 - Nitride semiconductor light emitting device: There is provided a nitride semiconductor light emitting device having a light reflection layer capable of preventing reflectivity from lowering and luminance from lowering due to deterioration of quality of an active layer. A nitride semiconductor laser includes at least a light emitting layer forming portion (3) provided on a... Agent: Rabin & Berdo, PC

20090278146 - Phosphor illumination optics for led light sources: Devices and methods for collecting and distributing light from a light emitting diode (LED) emitter onto a phosphor layer to produce substantially white light are provided. The devices may include a reflective cavity with a reflective material, surrounding the reflective cavity, with a reflective side of the reflective material facing... Agent: Oliff & Berridge, PLC

20090278145 - Semiconductor light emitting device and method for manufacturing the same: A semiconductor light emitting device 1 includes a supporting substrate 2 and a semiconductor stack 6 including an MQW active layer 13 emitting light and an n-GaN layer 14 at the top. In the upper surface of the n-GaN layer 14 of the semiconductor attack 6, a plurality of conical... Agent: Rabin & Berdo, PC

20090278147 - Semiconductor light-emitting device: Disclosed is a semiconductor light-emitting device having improved light-extraction efficiency. Specifically disclosed is a semiconductor light-emitting device (1) comprising a semiconductor light-emitting element (10), a phosphor layer (11) which is so formed as to cover at least a part of the semiconductor light-emitting element (10), and an outer layer (12)... Agent: Hamre, Schumann, Mueller & Larson P.C.

20090278158 - Gallium nitride based compound semiconductor light-emitting device and method of manufacturing the same: The present invention provides a gallium nitride based compound semiconductor light-emitting device having high light emission efficiency and a low driving voltage Vf. The gallium nitride based compound semiconductor light-emitting device includes a p-type semiconductor layer, and a transparent conductive oxide film that includes dopants and is formed on the... Agent: Sughrue Mion, PLLC

20090278162 - Low temperature co-fired ceramic (ltcc) tape compositions, light-emitting diode (led) modules, lighting devices and methods of forming thereof: The present invention provides LTCC (low temperature co-fired ceramic) tape compositions and demonstrates the use of said LTCC tape(s) in the formation of Light-Emitting Diode (LED) chip carriers and modules for various lighting applications. The present invention also provides for the use of (LTCC) tape and LED modules in the... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20090278157 - Method for the production of a semiconductor component comprising a planar contact, and semiconductor component: In a method for producing a semiconductor component, in particular a semiconductor structure having a surface structure or topography which is produced by means of electronic components (2) on a substrate (1), at least one electronic component (2) is applied to a substrate (1), and an isolation layer (3) is... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090278161 - Method of fabricating vertical structure leds: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate,... Agent: Mckenna Long & Aldridge LLP

20090278160 - Radiation emitting semiconductor device: The present invention provides a radiation emitting semiconductor device, which comprises an active layer for emitting radiation, a p-type conductive layer, a transparent conductive layer, and a non-p-type ohmic contact layer. The p-type conductive layer is formed on the active layer. The transparent conductive layer is formed on the p-type... Agent: Wpat, PC Intellectual Property Attorneys

20090278159 - Semiconductor chip package structure without substrates for achieving face-up electrical connection without using a wire-bonding process and method for making the same: A semiconductor chip package structure without substrates for achieving face-up electrical connection without using a wire-bonding process includes a package unit, a semiconductor chip, a first insulative unit, a first conductive unit, a second conductive unit, and a second insulative unit. The package unit has a central receiving groove for... Agent: Rosenberg, Klein & Lee

20090278163 - Light-emitting device and manufacturing method of the same: A light-emitting device (1) is provided having a current blocking layer (9) of buried structure, a portion of the current blocking layer (9) having an oxygen concentration higher than that of a light-emitting layer, the current blocking layer being of a thickness of not less than 5 nm and not... Agent: Masao Yoshimura, Chen Yoshimura LLP

20090278164 - Gan-based semiconductor light-emitting device and method for the fabrication thereof: A GaN-based semiconductor light-emitting device 1 includes a stacked body 10A having the component layers 12 that include an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer each formed of a GaN-based semiconductor, sequentially stacked and provided as an uppermost layer with a first bonding layer 14... Agent: Sughrue Mion, PLLC

20090278165 - Light emitting device and fabrication method therefor: A light emitting device (LED) structure formed on a Group IV-based semiconductor substrate is provided. The LED structure includes a Group IV-based substrate, an AlN nucleation layer formed on the Group IV-based substrate, a GaN epitaxial layer formed on the AlN nucleation layer, a distributed Bragg reflector (DBR) multi-layer structure... Agent: Haverstock & Owens LLP

20090278166 - Semiconductor device: A semiconductor device in which both an IGBT element region and a diode element region exist in the same semiconductor substrate includes a low lifetime region, which is formed in at least a part of a drift layer within the diode element region and shortens the lifetime of holes. A... Agent: Kenyon & Kenyon LLP

20090278167 - Semiconductor device including a plurality of chips and method of manufacturing semiconductor device: A semiconductor device includes a first chip and a second chip. The first chip includes a first conductivity type channel power MOSFET. The second chip includes a second conductivity type channel power MOSFET. The first chip and the second chip are integrated in such a manner that a second-surface drain... Agent: Posz Law Group, PLC

20090278168 - Structure of silicon controlled rectifier: A silicon controlled rectifier structure is provided in a substrate having a first conductive type. A well region formed within the substrate has a second conductive type. A first dopant region formed within the substrate and the well region has the first conductive type. A second dopant region formed within... Agent: J C Patents

20090278169 - Semiconductor device and method of manufacturing the same: A semiconductor device includes: a semiconductor base; a hetero semiconductor region which is in contact with the semiconductor base and which has a band gap different from that of the semiconductor base; a first electrode connected to the hetero semiconductor region; and a second electrode forming an ohmic contact to... Agent: Foley And Lardner LLP Suite 500

20090278170 - Semiconductor device and manufacturing method thereof: A method for manufacturing a semiconductor device includes providing a substrate having at least a gate structure formed thereon, forming LDDs in the substrate respectively at two side of the gate structure and a spacer at sidewalls of the gate structure, forming a source/drain in the substrate at two side... Agent: North America Intellectual Property Corporation

20090278172 - Gan based semiconductor element: The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron... Agent: Kubotera & Associates, LLC

20090278171 - High linearity doped-channel fet: A high linearity doped-channel FET, comprises a substrate, a buffer layer, a channel layer and a cap layer stacked downwardly thereon. The cap layer has a source region, a drain region with a distance apart from the source region and a gate region formed by removing part of the cap... Agent: Bacon & Thomas, PLLC

20090278173 - Memory device interconnects and method of manufacturing: An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090278174 - Pixel structure of solid-state image sensor: A pixel structure of a solid-state image sensor in which residual electrons in a photodiode is reduced and which has a first-stage gate that is arranged adjacent to the photodiode and controls read-out of electrons generated in the photodiode, a second-stage gate that is adjacent to the first-stage gate on... Agent: Birch Stewart Kolasch & Birch

20090278175 - Method for forming extended gate field effect transistor (egfet) based sensor and the sensor therefrom: The invention provides a method for forming an extended gate field effect transistor (EGFET) based sensor, including: (a) providing a substrate; (b) forming a sensing film including titanium dioxide, ruthenium doped titanium dioxide or ruthenium oxide on the substrate; and (c) forming a conductive wire extended from the sensing film... Agent: Quintero Law Office, PC

20090278176 - High current density power field effect transistor: An ultra-short channel hybrid power field effect transistor (FET) device lets current flow from bulk silicon without npn parasitic. This device does not have body but still have body diode with low forward voltage at high current rating. The device includes a JFET component, a first accumulation MOSFET disposed adjacent... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20090278177 - Semiconductor devices with non-punch-through semiconductor channels having enhanced conduction and methods of making: Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs),... Agent: Morris Manning Martin LLP

20090278179 - Chip scale surface mount package for semiconductor device and process of fabricating the same: A semiconductor package has contacts on both sides of the dice on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice expose the metal plate without extending through the metal plate. A metal layer may be formed on... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20090278178 - Semiconductor device and method for fabricating the same: Disclosed is a semiconductor device which includes a MIS FET on a surface of a substrate, an insulating film on the substrate to cover the MIS FET, an opening that gets to an impurity diffusing region formed in the insulating film, another opening that gets to a gate electrode or... Agent: Nec Corporation Of America

20090278180 - Cmos image sensor with asymmetric well structure of source follower: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the... Agent: Turocy & Watson, LLP

20090278181 - Solid-state image sensor and manufacturing method thereof: A solid-state image sensor includes: a trench isolation region; a photodiode region for converting incident light to signal charges and accumulating the signal charges therein; a floating diffusion region for accumulating the signal charges of the photodiode region; a gate electrode formed over the element formation region located between the... Agent: Mcdermott Will & Emery LLP

20090278182 - Spin injector: A spin injector for use in a microelectronic device such as a field effect transistor (FET) is disclosed. The spin injector includes an array of ferromagnetic elements disposed within a semiconductor. The ferromagnetic elements within the array are arranged and spaced with respect to one another in a close arrangement... Agent: VistaIPLaw Group LLP

20090278183 - Semiconductor device with channel of fin structure and method for manufacturing the same: Provided are a semiconductor device with a channel of a FIN structure and a method for manufacturing the same. In the method, a device isolation layer defining an active region is formed on a semiconductor substrate. A recess trench with a first width is formed in the active region, and... Agent: Marshall, Gerstein & Borun LLP

20090278184 - Nonvolatile semiconductor memory device in which decrease in coupling ratio of memory cells is suppressed: A first insulation film is formed on a semiconductor substrate. A first gate electrode is formed on the first insulation film. A second insulation film is formed on an upper surface and a side surface of the first gate electrode. A second gate electrode is formed on the second insulation... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090278185 - Device structures for a memory cell of a non-volatile random access memory and design structures for a non-volatile random access memory: Device and design structures for memory cells in a non-volatile random access memory (NVRAM). The device structure includes a semiconductor body in direct contact with the insulating layer, a control gate electrode, and a floating gate electrode in direct contact with the insulating layer. The semiconductor body includes a source,... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090278186 - Double gate transistor and method of manufacturing same: A double gate transistor on a semiconductor substrate (2) includes a first diffusion region (S2), a second diffusion region (S3), and a double gate (FG, CG). The first and second diffusion regions (S2, S3) are arranged in the substrate spaced by a channel region (CR). The double gate includes a... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090278188 - Non-volatile semiconductor memory device: To reduce the writing and erasing voltages of a memory transistor without increasing the area of a memory cell, and to reduce the area of a memory cell without increasing the writing and erasing voltages. The memory cell includes a memory transistor having a first island-shaped semiconductor region, a floating... Agent: Nixon Peabody, LLP

20090278190 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090278191 - Nonvolatile semiconductor memory device in which decrease in coupling ratio of memory cells is suppressed: A first insulation film is formed on a semiconductor substrate. A first gate electrode is formed on the first insulation film. A second insulation film is formed on an upper surface and a side surface of the first gate electrode. A second gate electrode is formed on the second insulation... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090278187 - Semiconductor device and manufacturing method of semiconductor device: A semiconductor device of an aspect of the present invention includes a semiconductor substrate, two diffusion layers provided in the semiconductor substrate, a gate insulating film provided on a channel region between the two diffusion layers, and a gate electrode which is composed of a stack of a plurality of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090278189 - Semiconductor device with resistor and method of fabricating same: A semiconductor device includes a cell array region disposed on a semiconductor substrate and comprising a first cell gate pattern, a cell semiconductor pattern disposed on the first cell gate pattern, and a second cell gate pattern disposed on the cell semiconductor pattern. The semiconductor device also includes a peripheral... Agent: Volentine & Whitt PLLC

20090278194 - Capacitorless one-transistor semiconductor memory device having improved data retention abilities and operation characteristics: A capacitorless one transistor (1T) semiconductor device whose data storage abilities are increased and leakage current is reduced is provided. The capacitor-less 1T semiconductor device includes a buried insulating layer formed on a substrate, an active region formed on the buried insulating layer and including a source region, a drain... Agent: Lee & Morse, P.C.

20090278193 - Nonvolatile semiconductor memory device and method of manufacturing the same: A nonvolatile semiconductor memory device includes a first stack unit with a first selection transistor and a second selection transistor formed on a semiconductor substrate and a second stack unit with first insulating layers and first conductive layers stacked alternately on the upper surface of the first stack unit. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090278192 - Semiconductor device: A semiconductor device includes a tunnel insulation layer pattern, a charge trapping layer pattern, a blocking layer pattern and a gate structure. The tunnel insulation layer pattern is formed on a substrate. The charge trapping layer pattern is formed on the tunnel insulation layer pattern. The blocking layer pattern is... Agent: Volentine & Whitt PLLC

20090278195 - Semiconductor memory device provided with stacked layer gate including charge accumulation layer and control gate, and manufacturing method thereof: A semiconductor memory device includes a memory cell transistor and a first MOS transistor. The memory cell transistor includes a first insulating film, a second insulating film, a control gate electrode, and a first diffusion layer. The first insulating film formed on the first active region. The second insulating film... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090278196 - Finfets having dielectric punch-through stoppers: A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate... Agent: Slater & Matsil, L.L.P.

20090278198 - Deep source electrode mosfet: A power semiconductor device that includes a plurality of source trenches that extend to a depth below the gate electrodes and a termination region that includes a termination trench that is as deep as the source trenches.... Agent: Farjami & Farjami LLP

20090278197 - Mis field effect transistor and method for manufacturing the same: The MIS field-effect transistor includes: a substrate; a nitride semiconductor multilayer structure portion formed on the substrate, including a first group III-V nitride semiconductor layer of a first conductivity type, a second group III-V nitride semiconductor layer of a second conductivity type stacked thereon and a third group III-V nitride... Agent: Rabin & Berdo, PC

20090278199 - Method for preventing gate oxide damage of a trench mosfet during wafer processing while adding an esd protection module atop: e

20090278200 - Transistor, semiconductor device and manufacturing method thereof: An ON resistance of a trench gate type transistor and a withstand voltage of a planar type transistor are optimized at the same time. Each of first and second regions of a semiconductor layer is formed by epitaxial growth on each of first and second regions of a semiconductor substrate,... Agent: Morrison & Foerster LLP

20090278201 - Enhanced stress-retention silicon-on-insulator devices and methods of fabricating enhanced stress retention silicon-on-insulator devices: Field effect transistor and methods of fabricating field effect transistors. The field effect transistors includes: a semiconductor substrate; a silicon oxide layer on the substrate; a stiffening layer on the silicon oxide layer; a single crystal silicon layer on the stiffening layer; a source and a drain on opposite sides... Agent: Schmeiser, Olsen & Watts

20090278202 - Soi device with improved storage capacity and method for manufacturing the s: An SOI device includes an SOI substrate composed of a stack structure of a silicon substrate, a buried oxide layer, and a silicon layer. Grooves are defined in the silicon layer each exposing the buried oxide layer. A barrier layer is formed on the lower portion of the sidewall of... Agent: Ladas & Parry LLP

20090278203 - Semiconductor device and manufacturing method thereof: It is an object to reduce the effect of a characteristic of the edge portion of a channel forming region in a semiconductor film, on a transistor characteristic. An island-like semiconductor film is formed over a substrate, and a conductive film forming a gate electrode provided over the island-like semiconductor... Agent: Eric Robinson

20090278204 - Semiconductor device: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and... Agent: Miles & Stockbridge PC

20090278205 - High voltage bicmos device and method for manufacturing the same: A high voltage BICMOS device and a method for manufacturing the same, which may improve the reliability of the device by securing a distance between adjacent DUF regions, are provided. The high voltage BICMOS device includes: a reverse diffusion under field (DUF) region formed by patterning a predetermined region of... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090278206 - High-frequency switching transistor and high-frequency circuit: A switching transistor includes a substrate having a substrate dopant concentration and a barrier region bordering on the substrate, having a first conductivity type and having a barrier region dopant concentration that is higher than the substrate dopant concentration. A source region is embedded in the barrier region, and has... Agent: Maginot, Moor & Beck

20090278207 - Electromigration-complaint high performance fet layout: An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level... Agent: Ryan, Mason & Lewis, LLP

20090278208 - Semiconductor integrated circuit device and method of fabricating the same: A semiconductor integrated circuit device with higher integration density and a method of fabricating the same are provided. The semiconductor integrated circuit device may include trench isolation regions in a semiconductor substrate that define an active region and a gate pattern that is used for a higher voltage and formed... Agent: Harness, Dickey & Pierce, P.L.C

20090278210 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating... Agent: Mcdermott Will & Emery LLP

20090278209 - Semiconductor device and method of fabrication: A semiconductor device includes a gate electrode provided on a semiconductor region with a gate insulating film being interposed therebetween, extension diffusion layers provided in regions on both sides of the gate electrode of the semiconductor region, a first-conductivity type first impurity being diffused in the extension diffusion layers, and... Agent: Mcdermott Will & Emery LLP

20090278211 - Composite dielectric thin film, capacitor and field effect transistor using the same, and each fabrication method thereof: a composite dielectric thin film capable of high dielectric constant, low leakage current characteristics, and high dielectric breakdown voltage while being deposited at a room temperature, a capacitor and a field effect transistor (FET) using the same, and their fabrication methods. The composite dielectric thin film is deposited at a... Agent: Ostrolenk Faber Gerb & Soffen

20090278213 - Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array: Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon... Agent: Cantor Colburn LLP-ibm Europe

20090278212 - Integrated device: An integrated device including a sensor and the like formed on a γ-alumina layer epitaxially grown on a silicon substrate is provided at low cost. This integrated device includes: a silicon substrate; a first function area formed on a γ-alumina film epitaxially grown on a portion of the silicon substrate;... Agent: Frommer Lawrence & Haug

20090278215 - Electronic device, system, and method comprising differential sensor mems devices and drilled substrates: Electronic device which comprises a substrate provided with at least one passing opening, a MEMS device with function of differential sensor provided with a first and a second surface and of the type comprising at least one portion sensitive to chemical and/or physical variations of fluids present in correspondence with... Agent: Graybeal Jackson LLP

20090278214 - Microelectromechanical systems encapsulation process: An encapsulated MEMS process including a high-temperature anti-stiction coating that is stable under processing steps at temperatures over 450 C is described. The coating is applied after device release but before sealing vents in the encapsulation layer. Alternatively, an anti-stiction coating may be applied to released devices directly before encapsulation.... Agent: Courtney Staniford & Gregory LLP

20090278216 - Mems sensor: An MEMS sensor is described. The MEMS sensor may include a substrate, a lower thin film provided in contact with a surface of the substrate, and an upper thin film opposed to the lower thin film at an interval on the side opposite to the substrate.... Agent: Rabin & Berdo, PC

20090278217 - Mems device: A micro-electrical-mechanical device comprises: a transducer arrangement having at least a membrane being mounted with respect to a substrate; and electrical interface means for relating electrical signals to movement of the membrane; in which the transducer arrangement comprises stress alleviating formations which at least partially decouple the membrane from expansion... Agent: Dickstein Shapiro LLP

20090278218 - Magnetoresistive element: A magnetoresistive element is disclosed, wherein the magnetoresistive element is composed of a synthetic anti-ferromagnetic (SAF) structure that may include a first pinned layer, an intermediate layer, and a second pinned layer; and a Cr layer between the first pinned layer and the intermediate layer and/or the second pinned layer... Agent: Harness, Dickey & Pierce, P.L.C

20090278220 - Image sensor and fabricting method thereof: An image sensor includes the steps of forming a sublayer including a photodiode, a transistor and a metal line on a substrate, forming a pattern layer on the sublayer to be overlapped with the photodiode and to having a curved surface, and forming a combined color filter and microlens on... Agent: Mckenna Long & Aldridge LLP

20090278219 - Microelectronic devices having an emi shield and associated systems and methods: Microelectronic devices having an EMI shield, systems including such microelectronic devices, and methods for manufacturing such microelectronic devices. One embodiment of a microelectronic device comprises an imaging system comprising a microelectronic die, an optics assembly, and an electromagnetic interference (EMI) shield. The microelectronic die includes an image sensor, processing components... Agent: Kramer Levin Naftalis & Frankel LLP

20090278221 - Semiconductor device: A semiconductor device that attenuates light to the circuit element area is provided. The semiconductor device includes light-sensitive element area formed on substrate and a circuit element area formed on the substrate. Additionally, a multilayer wiring area is formed on circuit element area. A Tantalum film (which is generally made... Agent: Texas Instruments Incorporated

20090278222 - Integrated circuit with uniform polysilicon perimeter density, method and design structure: Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090278224 - Methods of forming an amorphous silicon thin film: A method for forming an amorphous silicon thin film is disclosed. In some embodiments, a method includes loading a substrate into a reaction chamber; and conducting a plurality of deposition cycles on the substrate. Each of at least two of the cycles includes: supplying a silicon precursor to the reaction... Agent: Knobbe Martens Olson & Bear LLP

20090278223 - Process for producing siliceous film and substrate with the siliceous film produced by the process: An objective of the present invention is to provide a process for producing a siliceous film which has a uniform quality independently of sites and in both the inside and outside of the grooves and is free from voids and cracks in the inside of the grooves. A substrate with... Agent: Az Electronic Materials Usa Corp. Attention: Industrial Property Dept.

20090278225 - Semiconductor device and method for isolating the same: The present invention relates to a semiconductor device and a method for isolating the same. The semiconductor device includes: a silicon substrate provided with a trench including at least one silicon pillar at a bottom portion of the trench, wherein the silicon pillar become sidewalls of micro trenches; and a... Agent: Mannava & Kang, P.C.

20090278226 - Structure for conductive liner for rad hard total dose immunity and structure thereof: The invention relates to a design structure, and more particularly, to a design structure for a conductive liner for rad hard total dose immunity and a structure thereof. The structure includes at least one shallow trench isolation structure having oxide material and formed in an SIO. A dielectric liner is... Agent: Greenblum & Bernstein, P.L.C

20090278227 - Isolation trench structure: Among structures, methods, devices, and systems for isolation trenches, a semiconductor device is provided that includes a substrate and an isolation trench structure. One such isolation trench structure includes a first isolation trench portion associated with a surface of the substrate and having a first pair of opposing sidewalls that... Agent: Brooks, Cameron & Huebsch , PLLC

20090278228 - Design structure for interconnect structure containing various capping materials for electrical fuse and other related applications: A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different... Agent: Greenblum & Bernstein, P.L.C

20090278229 - Efficient interconnect structure for electrical fuse applications: A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes... Agent: Scully, Scott, Murphy & Presser, P.C.

20090278232 - Ruthenium silicide diffusion barrier layers and methods of forming same: A method for use in the fabrication of integrated circuits includes providing a substrate assembly having a surface. A diffusion barrier layer is formed over at least a portion of the surface. The diffusion barrier layer is formed of RuSix, where x is in the range of about 0.01 to... Agent: Mueting, Raasch & Gebhardt, P.A.

20090278231 - Semiconductor device and method for fabricating the same: The semiconductor device comprises a first insulation film 26 formed over a semiconductor substrate 10, first conductor plug 32 buried in a first contact hole 28a formed down to a source/drain diffused layer 22, a capacitor 44 formed over the first insulation film 26, a first hydrogen diffusion preventing film... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090278230 - Semiconductor device and method of manufacturing the same: A semiconductor device has a substrate, an insulating interlayer, an interconnect as one example of an electro-conductive pattern, a through-electrode, and a bump as one example of a connection terminal, wherein the insulating interlayer is positioned up above the surface of the substrate, the interconnect is positioned on the surface... Agent: Mcginn Intellectual Property Law Group, PLLC

20090278234 - (al, ga, in)n-based compound semiconductor and method of fabricating the same: Disclosed are a (Al, Ga, In)N-based compound semiconductor device and a method of fabricating the same. The (Al, Ga, In)N-based compound semiconductor device of the present invention comprises a substrate; a (Al, Ga, In)N-based compound semiconductor layer grown on the substrate; and an electrode formed of at least one material... Agent: H.c. Park & Associates, PLC

20090278233 - Bonded intermediate substrate and method of making same: A method includes growing a first epitaxial layer of III-nitride material, forming a damaged region by implanting ions into an exposed surface of the first epitaxial layer, and growing a second epitaxial layer of III-nitride material on the exposed surface of the first epitaxial layer. A level of defects present... Agent: Foley And Lardner LLP Suite 500

20090278235 - Manufacturing method of semiconductor device, and semiconductor device: Provided is a manufacturing method of a semiconductor device, which is capable of realizing fine-pitch patterns and thus improving stabilization of patterning precision. The manufacturing method of the semiconductor device comprises forming a first photoresist pattern in a predetermined region on a substrate, depositing a thin film on the surface... Agent: Brundidge & Stanger, P.C.

20090278236 - Semiconductor device, wafer structure and method for fabricating semiconductor device: A photo-resist used in photolithography in a microfabrication process may be formed uniformly even if trenches for separating semiconductor devices are formed before the microfabrication process. The two parallel trenches are formed between neighboring element forming regions in a p-type semiconductor layer containing a plurality of arrayed element forming regions... Agent: Turocy & Watson, LLP

20090278237 - Through substrate via including variable sidewall profile: A microelectronic structure, such as a semiconductor structure, and a method for fabricating the microelectronic structure, include an aperture within a substrate. Into the aperture is located and formed a via. The via may include a through substrate via. The aperture includes, progressing sequentially contiguously at least partially through the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090278238 - Tsvs having chemically exposed tsv tips for integrated circuit devices: A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material... Agent: Texas Instruments Incorporated

20090278239 - Silicon wafer and production method thereof: In a silicon wafer having an oxygen precipitate layer, a depth of DZ layer ranging from a wafer surface to an oxygen precipitate layer is 2 to 10 μm and an oxygen precipitate concentration of the oxygen precipitate layer is not less than 5×107 precipitates/cm3.... Agent: Townsend And Townsend And Crew, LLP

20090278240 - Semiconductor apparatus: Disclosed is a semiconductor apparatus that prevents diffusion of materials of a magnetic film during the process for manufacturing the semiconductor apparatus. The semiconductor apparatus includes: a substrate; a semiconductor device formed on a principal surface of the substrate and including an interconnect layer; a magnetic shielding film of a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090278244 - Ic device having low resistance tsv comprising ground connection: A semiconductor device includes an integrated circuit (IC) die including a substrate, and at least one through substrate via (TSV) that extends through the substrate to a protruding integral tip that includes sidewalls and a distal end. The protruding integral tip has a tip height between 1 and 50 μm.... Agent: Texas Instruments Incorporated

20090278245 - Packaged electronic devices with face-up die having tsv connection to leads and die pad: A packaged electronic device includes a leadframe including a die pad, a first, second, and third lead pin surrounding the die pad. An IC die is assembled in a face-up configuration on the lead frame. The IC die includes a substrate having an active top surface and a bottom surface,... Agent: Texas Instruments Incorporated

20090278241 - Semiconductor die package including die stacked on premolded substrate including die: A semiconductor die package. The semiconductor includes a premolded substrate. The premolded substrate includes (i) a leadframe structure, (ii) a first semiconductor die comprising a first die surface and a second die surface, attached to the leadframe structure, and (iii) a molding material covering at least a portion of the... Agent: Townsend And Townsend And Crew, LLP

20090278242 - Stacked type chip package structure: A stacked type chip package structure including a lead frame, a chip package, a second chip, and a second molding compound is provided. The lead frame includes a plurality of first leads and second leads insulated from one another. The first leads have a first upper surface, and the second... Agent: J C Patents

20090278243 - Stacked type chip package structure and method for fabricating the same: A stacked type chip package structure including a chip carrier, a first chip, a second chip, a third chip, and an insulating material is provided. The chip carrier includes two die pads and a plurality of leads surrounding the die pads. The first chip and the second chip are disposed... Agent: J C Patents

20090278247 - Bonding pad sharing method applied to multi-chip module and apparatus thereof: A multi-chip module (MCM) includes a first die and a second die. The first die supports a plurality of predetermined functions. The second die is coupled to the first die and comprises at least an option pad configured for a bonding option. The first die performs a predetermined function according... Agent: North America Intellectual Property Corporation

20090278246 - Semiconductor device: A plurality of LSI chips (1) are stacked on an interposer (2). Signal coils (1b) for signal transmission are formed on the circuit formation surfaces of LSI chips (1) that are formed using silicon substrates (1a). The signal coils (1b) connect to circuits formed in the LAI chips (1). Through-holes... Agent: Sughrue Mion, PLLC

20090278249 - Printed circuit board and method thereof and a solder ball land and method thereof: A printed circuit board and method thereof and a solder ball land and method thereof. The example printed circuit board (PCB) may include a first solder ball land having a first surface treatment portion configured for a first type of resistance and a second solder ball land having a second... Agent: Harness, Dickey & Pierce, P.L.C

20090278248 - Semiconductor device and method of fabrication: A semiconductor device includes a first die pad, a first semiconductor chip provided on the first die pad, a second die pad, a second semiconductor chip provided on the second die pad, and a sealing resin made of a first resin material, sealing the first die pad, the first semiconductor... Agent: Mcdermott Will & Emery LLP

20090278250 - Method of semiconductor packaging and/or a semiconductor package: The method includes forming a leadframe. The leadframe is directly bonded to the semiconductor chip. The leadframe is flexed and/or compressed in a mold cavity. The compressed leadframe and the chip are molded into a package.... Agent: Slater & Matsil LLP

20090278251 - Pad structure for 3d integrated circuit: This invention discloses an I/O pad structure in an integrated circuit (IC) which comprises a first vertical region in the IC including a top metal layer and one or more semiconductor devices formed thereunder, the top metal layer in the first vertical region serving as a first pad, the semiconductor... Agent: K & L Gates LLPIPDocketing

20090278252 - Semiconductor device and method for manufacturing semiconductor device: To reduce defects of a semiconductor device, such as defects in shape and characteristic due to external stress and electrostatic discharge. To provide a highly reliable semiconductor device. In addition, to increase manufacturing yield of a semiconductor device by reducing the above defects in the manufacturing process. The semiconductor device... Agent: Eric Robinson

20090278253 - Semi-finished package and method for making a package: The present invention relates to a semi-finished package and a method for making a package. The semi-finished package includes a carrier and at least one molding compound. The molding compound is disposed on a surface of the carrier, and has a body and a plurality of outer protrusions. The outer... Agent: Mccracken & Frank LLP

20090278254 - Dielectric materials and methods for integrated circuit applications: An integrated circuit device is provided having a substrate and areas of electrically insulating and electrically conductive material, where the electrically insulating material is a hybrid organic-inorganic material that requires no or minimal CMP and which can withstand subsequent processing steps at temperatures of 450° C. or more.... Agent: Kubovcik & Kubovcik

20090278255 - Semiconductor device: A semiconductor device includes a substrate having external connection terminals, and a semiconductor chip mounted over a semiconductor-chip mounting portion of the substrate. The external connection terminals are formed by sequentially forming an electroless nickel plating layer, an electroless gold plating layer, and an electrolytic gold plating layer on a... Agent: Mcdermott Will & Emery LLP

20090278256 - Semiconductor package enhancing variation of movability at ball terminals: A semiconductor package with enhanced mobility of ball terminals is revealed. A chip is attached to the substrate by a die-attaching material where the substrate has at least a stepwise depression on the covered surface to make the substrate thickness be stepwise decreased from a central line of the die-attaching... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090278257 - Method to assemble structures from nano-materials: Numerous embodiments of a method to assemble nano-materials on a platform are described. In one embodiment, a nano-material is functionalized with a first bondable group. The functionalized nano-material is disposed on an assembly platform having an electrode to form a first layer. Additional layers of the nano-material may be formed... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090278258 - Interconnect structure with a mushroom-shaped oxide capping layer and method for fabricating same: An interconnect structure is provided that includes a dielectric material 52′ having a dielectric constant of 4.0 or less and including a plurality of conductive features 56 embedded therein. The dielectric material 52′ has an upper surface 52r that is located beneath an upper surface of each of the plurality... Agent: Scully, Scott, Murphy & Presser, P.C.

20090278259 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device includes an insulation film formed above a semiconductor substrate, a conductor containing Cu formed in the insulation film, and a layer film formed between the insulation film and the conductor and formed of a first metal film containing Ti and a second metal film different from the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090278260 - Redundancy design with electro-migration immunity and method of manufacture: An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, a design structure of the IC interconnect and a method of manufacture of the IC interconnect is provided. The structure has electro-migration immunity and redundancy of design, which includes a plurality of wires laid... Agent: Greenblum & Bernstein, P.L.C

20090278261 - Semiconductor device and method for fabricating the same: An interlayer insulating film is formed on the upper surface of a semiconductor substrate, and lower-level interconnects are formed in the interlayer insulating film. A liner insulating film is formed on the upper surfaces of the interlayer insulating film and lower-level interconnects. An interlayer insulating film is formed on the... Agent: Mcdermott Will & Emery LLP

20090278262 - Multi-chip package including component supporting die overhang and system including same: A microelectronic package and a system including the package. The package includes: a substrate; a stack of dice electrically and mechanically bonded to the substrate, the stack including a second level die and a first level die between the substrate and the second level die, the second level die defining... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090278263 - Reliability wcsp layouts: An integrated circuit device includes a functional circuit die with a patterned rewiring layer defining a first rewiring pad and one or more second rewiring pads on opposite sides of a neutral point of the die. The device also includes at least one dielectric layer having bump opening features over... Agent: Texas Instruments Incorporated

20090278264 - Semiconductor chip bump connection apparatus and method: Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and... Agent: Timothy M Honeycutt Attorney At Law

20090278265 - Electronic component and resin packaging method for electronic component: An electronic component, in which the outer perimeter portion of a component (2) is surrounded with a first sealing resin (4), a second sealing resin (3) is filled within the periphery of the first sealing resin (4), the component (2) and a board (1) are electrically connected by a wire... Agent: Steptoe & Johnson LLP

20090272959 - Non-volatile resistive-switching memories: Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set... Agent: Legal Department

20090272958 - Resistive memory: An integrated circuit including a memory cell and method of manufacturing the integrated circuit are described. The memory cell includes a diode and a resistive memory element coupled to the diode. The resistive memory element includes a thin oxide storage layer that uses multiple resistance levels to store more than... Agent: Slater & Matsil, L.L.P.

20090272960 - Non-volatile resistive oxide memory cells, and methods of forming non-volatile resistive oxide memory cells: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The first conductive electrode has an elevationally outermost surface and opposing laterally outermost edges at the elevationally outermost surface in one planar cross section. Multi-resistive... Agent: Wells St. John P.s.

20090272962 - Reduction of forming voltage in semiconductor devices: This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (RRAM) that use techniques to provide a memory device with more predictable operation. In particular, forming voltage required by particular designs may be reduced through... Agent: Marc P Schuyler- Im

20090272961 - Surface treatment to improve resistive-switching characteristics: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters.... Agent: Marc P Schuyler- Im

20090272964 - Light-emitting device and method for manufacturing the same: A light-emitting device and the method for making the same is disclosed. The light-emitting device is a semiconductor device, comprising a growth substrate, an n-type semiconductor layer, a quantum well active layer and a p-type semiconductor layer. It combines the holographic and the quantum well interdiffusion (QWI) to form a... Agent: Bacon & Thomas, PLLC

20090272963 - Surface light emitting element: l

20090272965 - Selective high-k dielectric film deposition for semiconductor device: Embodiments of the present invention describe a method of fabricating a III-V quantum well transistor with low current leakage and high on-to-off current ratio. A hydrophobic mask having an opening is formed on a semiconductor film. The opening exposes a portion on the semiconductor film where a dielectric layer is... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090272968 - Material for a thin and low-conductive functional layer for an oled and production method therefor: The invention relates to a material for applying thin organic layers having a conductivity that can be set in a defined manner. The material comprises at least one mixture consisting of two different fractions of a functional polymer, preferably in a solvent, and is applied, for example, in the form... Agent: Fish & Richardson PC

20090272969 - Method of patterning an organic thin film, an organic thin film transistor, a method of manufacturing an organic thin film transistor, and an organic electroluminescene display device having the organic thin film transistor: Provided is a method of patterning an organic thin film which can prevent surface damage of an organic semiconductor layer. Also, an organic thin film transistor that can reduce an off-current and can prevent surface damage of the organic semiconductor layer and a method of manufacturing the organic thin film... Agent: Knobbe Martens Olson & Bear LLP

20090272966 - Organic transistor and active matrix display: An organic transistor is disclosed that has an organic semiconductor layer patterned with high resolution. The organic transistor includes a gate electrode, a gate insulting film, a source electrode, a drain electrode, and an organic semiconductor layer formed of an organic semiconductor material. The gate electrode, the gate insulting film,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090272967 - Pentacene-carbon nanotube composite, method of forming the composite, and semiconductor device including the composite: A composite material includes a carbon nanotube, and plural pentacene molecules bonded to the carbon nanotube. A method of forming the composite layer, includes depositing on a substrate a dispersion of soluble pentacene precursor and carbon nanotubes, heating the dispersion to remove solvent from the dispersion, heating the substrate to... Agent: Mcginn Intellectual Property Law Group, PLLC

20090272970 - Field-effect transistor: Provided is a field-effect transistor including an active layer and a gate insulating film, wherein the active layer includes an amorphous oxide layer containing an amorphous region and a crystalline region, and the crystalline region is in the vicinity of or in contact with an interface between the amorphous oxide... Agent: Fitzpatrick Cella Harper & Scinto

20090272971 - Light emitting device having a pluralilty of light emitting cells and package mounting the same: Disclosed is a light emitting device having a plurality of light emitting cells and a package having the same mounted thereon. The light emitting device includes a plurality of light emitting cells which are formed on a substrate and each of which has an N-type semiconductor layer and a P-type... Agent: H.c. Park & Associates, PLC

20090272972 - Zno based semiconductor light emitting device and its manufacture method: A ZnO based semiconductor light emitting device includes: a first semiconductor layer containing ZnO1-x1Sx1; a second semiconductor layer formed above the first semiconductor layer and containing ZnO1-x2Sx2; and a third semiconductor layer formed above the second semiconductor layer and containing ZnO1-x3Sx3, wherein an S composition x1 of the first semiconductor... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090272974 - Interposer chip and multi-chip package having the interposer chip: An interposer chip may include an insulating substrate, conductive patterns, and a test pattern. The conductive patterns may be formed on the insulating substrate. Further, the conductive patterns may be electrically connected to conductive wires. The test pattern may be connected to the conductive patterns. A test current for testing... Agent: Harness, Dickey & Pierce, P.L.C

20090272973 - Semiconductor wafer including semiconductor chips divided by scribe line and process-monitor electrode pads formed on scribe line: The present invention discloses a semiconductor wafer having a scribe line dividing the semiconductor wafer into a matrix of plural semiconductor chips. The semiconductor wafer includes a polysilicon layer, a poly-metal interlayer insulation film formed on the polysilicon layer, and a first metal wiring layer formed on the poly-metal interlayer... Agent: Cooper & Dunham, LLP

20090272975 - Poly-crystalline layer structure for light-emitting diodes: A structure and method for a light-emitting diode are presented. A preferred embodiment comprises a substrate with a conductive, poly-crystalline, silicon-containing layer over the substrate. A first contact layer is epitaxially grown, using the conductive, poly-crystalline, silicon-containing layer as a nucleation layer. An active layer is formed over the first... Agent: Slater & Matsil, L.L.P.

20090272976 - Method for producing nmos and pmos devices in cmos processing: A method for producing one or more nMOSFET devices and one or more pMOSFET devices on the same semiconductor substrate is disclosed. In one aspect, the method relates to the use of a single activation anneal that serves for both Si NMOS and Ge pMOS. By use of a solid... Agent: Knobbe Martens Olson & Bear LLP

20090272977 - Pixel structure of a thin film transistor liquid crystal display and fabricating method thereof: A method of fabricating a pixel structure of a thin film transistor liquid crystal display is provided. A transparent conductive layer and a first metallic layer are sequentially formed over a substrate. The first metallic layer and the transparent conductive layer are patterned to form a gate pattern and a... Agent: J C Patents

20090272978 - Image display system and manufacturing method thereof: An image display system and manufacturing method are disclosed. According to the present invention, the image display system comprises a substrate, a switching TFT, a driving TFT, a photo sensor and a capacitor. A buffer layer is formed on a substrate. A separation layer is formed in a first area... Agent: Lowe Hauptman Ham & Berner, LLP

20090272979 - Active matrix electronic array device: An active matrix device has an array (54) of device elements, each of which comprises at least one thin film transistor (34). A thin film conductive heater element arrangement (10) is provided over a substrate of the device, and the semiconductor islands of the thin film transistors are provided over... Agent: Joe Mckinney Muncy Birch, Stewart, Kolash & Birch, LLP

20090272981 - Display substrate and method of manufacturing the same: A display substrate includes a gate electrode, a gate insulating layer, and a semiconductor layer that are sequentially formed on a substrate. Also, the display substrate includes a color filter layer formed on the substrate and exposing a portion of the semiconductor layer, and source and drain electrodes that each... Agent: H.c. Park & Associates, PLC

20090272980 - Thin film transistor array panel and manufacturing method of the same: A semiconductor including a channel, a data line including a source electrode, a drain electrode, and a pixel area definition member is formed on a gate insulating layer, and a passivation layer is deposited on the data line, the pixel area definition member, and the channel of the semiconductor. A... Agent: Haynes And Boone, LLPIPSection

20090272984 - Silicon carbide on diamond substrates and related devices and methods: A high power, wide-bandgap device is disclosed that exhibits reduced junction temperature and higher power density during operation and improved reliability at a rated power density. The device includes a diamond substrate for providing a heat sink with a thermal conductivity greater than silicon carbide, a single crystal silicon carbide... Agent: Summa, Additon & Ashe, P.A.

20090272983 - Silicon carbide semiconductor device and method for manufacturing the same: A silicon carbide semiconductor device includes: a semiconductor substrate having a silicon carbide substrate, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; a trench penetrating the second and the third semiconductor layers to reach the first semiconductor layer; a channel layer on a sidewall and... Agent: Posz Law Group, PLC

20090272982 - Trench gate type semiconductor device and method of producing the same: A method of producing a trench gate type MOSFET is provided in which each intersection trench is formed as a two-stage trench structure. A gate trench is backfilled with a mask material and the mask material is then patterned to form a mask used for forming each intersection trench. The... Agent: Rossi, Kimms & Mcdowell LLP.

20090272986 - Led module, and led chain containing the same: The present invention discloses an LED module comprising: a waterproof enclosure; an LED accommodated in the waterproof enclosure; a wire for coupling the LED module with other LED modules and a driver; and a radiating unit set in the bottom of the waterproof enclosure and exposed to the external environment.... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090272987 - Structure of led of high heat-conducting efficiency: A structure of LED of high heat-conducting efficiency is to provide a copper substrate having a plurality of indentations. An insulating layer is formed on the surface of the substrate and the bottom of the indentations. Meanwhile, a set of metallic circuits is formed on the insulating layer of the... Agent: Hdls Patent & Trademark Services

20090272985 - White led lamp and backlight using the same, and liquid crystal display device using the backlight: A white LED lamp 1 according to the present invention comprises an LED chip 2 having a luminescence wavelength of not less than 360 nm and not more than 440 nm, and a light emitting part excitable upon exposure to light from the LED chip 2 to emit white light... Agent: Harness, Dickey & Pierce, P.L.C

20090272989 - Light emitting device having stacked multiple leds: A light emitting device and method of producing the same is disclosed. The light emitting device includes a heterostructure having a plurality of light emitting diodes (LEDs) stacked one on top of another.... Agent: Arent Fox LLP

20090272990 - Light mixing apparatus for light emitting diode: A light mixing apparatus of a light emitting diode (LED) is installed on a light emitting surface of the LED. The light emitted from the LED is mixed by a light mixing module of the light mixing apparatus uniformly for adjusting the light output angle. After the angle increases, the... Agent: Hdls Patent & Trademark Services

20090272988 - Multi-chip module single package structure for semiconductor: The invention is to provide a semiconductor light-emitting device package structure. The semiconductor light-emitting device package structure includes a substrate, N sub-mounts and N semiconductor light-emitting die modules, where N is a positive integer lager than or equal to 2. Each of the sub-mounts is embedded on the substrate and... Agent: Juan Carlos A. Marquez C/o Stites & Harbison PLLC

20090272991 - Light emitting diode having alingap active layer and method of fabricating the same: A light emitting diode having an AlInGaP active layer and a method of fabricating the same are disclosed. The light emitting diode includes a substrate. A plurality of light emitting cells are positioned to be spaced apart from one another, wherein each of the light emitting cells has a first... Agent: H.c. Park & Associates, PLC

20090272993 - Semiconductor light emitting device: A semiconductor light emitting device comprises a first nitride semiconductor layer comprising a plurality of concave portions, a reflector in at least one of the concave portions of the first nitride semiconductor layer, and a second nitride semiconductor layer on the first nitride semiconductor layer.... Agent: Birch Stewart Kolasch & Birch

20090272992 - Semiconductor light-emitting device and process for producing the same: A semiconductor light emitting device of the present invention includes a substrate (1), an n-GaN layer (2) supported by the substrate (1), a p-GaN layer (7) which is located farther from the substrate (1) than the n-GaN layer (2) is, an active layer (4) formed between the n-GaN layer (2)... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20090272994 - Semiconductor light emitting device: The embodiment discloses a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, a first electrode formed under the first conductive semiconductor layer and comprising a... Agent: Birch Stewart Kolasch & Birch

20090272996 - Encapsulation for phosphor-converted white light emitting diode: An improved light emitting device, especially a phosphor-converted white light device, wherein the light extraction efficiency and the color temperature distribution uniformity are improved by the introduction of both nanoparticles and light scattering particles proximate to the light source. Nanoparticles having a high index of refraction are dispersed throughout a... Agent: Koppel, Patrick, Heybl & Dawson

20090272997 - Led structure to increase brightness: A light emitting semiconductor device comprising an LED having an emission aperture located on a surface of the LED and the emission aperture has a size that is smaller than a surface area of the LED where the emission aperture is formed. The device further includes a reflector surrounding both... Agent: Arent Fox LLP

20090273000 - Light emitting device and method of manufacturing same: A light emitting device according to the present invention comprises board 2 having electrode 3b formed on the surface thereof, light emitting element 1 mounted on the surface of board 2, wire 4 for electrically connecting light emitting element 1 with electrode 3b, and reflector 11b formed on the surface... Agent: Mcginn Intellectual Property Law Group, PLLC

20090272998 - Optoelectronic semiconductor chip comprising a wavelength conversion substance, and optoelectronic semiconductor component comprising such a semiconductor chip, and method for producing the optoelectronic semiconductor chip: A semiconductor chip comprises: a semiconductor body which comprises a semiconductor layer sequence suitable for emitting electromagnetic radiation of a first wavelength range from its front side; and a first wavelength-converting layer on at least one first partial region of the front side of the semiconductor body with a first... Agent: Fish & Richardson PC

20090272999 - Organic element and manufacturing method thereof: An organic EL display panel having a functional layer with a uniform film thickness is provided. The organic EL display panel of the present invention contains an anode electrode set on a substrate; line-state banks set on the substrate on which the anode electrode is set and defining a line-state... Agent: Greenblum & Bernstein, P.L.C

20090272995 - Resin composition for optical semiconductor element encapsulation, and optical semiconductor device produced by using the same: An epoxy resin composition for optical semiconductor element encapsulation includes an epoxy resin (Component (A)) mainly containing an epoxy compound represented by a specific structural formula (1), a curing agent (Component (B)), and at least one of an oxynitride phosphor and a nitride phosphor (Component (C)). Therefore, the phosphor component... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090273004 - Chip package structure and method of making the same: A chip package structure and method thereof uses a semiconductor substrate as a package substrate, which improve heat dissipation. Also, the chip package structure is incorporated with a planarization structure, which renders the chip and the package substrate a substantially planar surface, thereby making formation of a planar patterned conductive... Agent: North America Intellectual Property Corporation

20090273002 - Led package structure and fabrication method: System and method for packaging an LED is presented. A preferred embodiment includes a plurality of thermal vias located through the packaging substrate to effectively transfer heat away from the LED, and are preferably formed along with conductive vias that extend through the packaging substrate. The thermal vias are preferably... Agent: Slater & Matsil, L.L.P.

20090273003 - Light emitting device and method for manufacturing the same: A light emitting device comprises a second electrode layer; a second conductivity-type semiconductor layer on the second electrode layer; a current blocking layer comprising an oxide of the second conductivity-type semiconductor layer; an active layer on the second conductivity-type semiconductor layer; a first conductivity-type semiconductor layer on the active layer;... Agent: Birch Stewart Kolasch & Birch

20090273005 - Opto-electronic package structure having silicon-substrate and method of forming the same: Disclosed herein is a structure of opto-electronic package having a Si-substrate. The Si-substrates are manufactured in batch utilizing the micro-electromechanical processes or the semiconductor processes, so that these Si-substrates are made with great precision and full of varieties. Based on the material characteristic of the Si-substrate, and the configuration of... Agent: North America Intellectual Property Corporation

20090273001 - Wire bonding to connect electrodes: A light emitting apparatus includes a semiconductor layer having an electrode with two traces physically separated from one another. The light emitting apparatus further includes a wire bond electrically connecting the two traces.... Agent: Arent Fox LLP

20090273006 - Bidirectional silicon-controlled rectifier: The present invention discloses a bidirectional silicon-controlled rectifier, wherein the conventional field oxide layer, which separates an anode structure from a cathode structure, is replaced by a field oxide layer having floating gates, a virtual gate or a virtual active region. Thus, the present invention can reduce or escape from... Agent: Rosenberg, Klein & Lee

20090273007 - Method of testing an integrated circuit die, and an integrated circuit die: In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter:... Agent: Dla Piper LLP (us )

20090273008 - Image sensor and method for manufacturing the same: In a solid state imaging device, and a method of manufacture thereof, the efficiency of the transfer of available photons to the photo-receiving elements is increased beyond that which is currently available. Enhanced anti-reflection layer configurations, and methods of manufacture thereof, are provided that allow for such increased efficiency. They... Agent: Mills & Onello LLP

20090273009 - Integrated cmos porous sensor: A single chip wireless sensor (1) comprises a microcontroller (2) connected by a transmit/receive interface (3) to a wireless antenna (4). The microcontroller (2) is also connected to an 8 kB RAM (5), a USB interface (6), an RS232 interface (8), 64 kB flash memory (9), and a 32 kHz... Agent: Jacobson Holman PLLC

20090273011 - Metal-oxide-semiconductor device including an energy filter: A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from... Agent: Ryan, Mason & Lewis, LLP

20090273010 - Removal of impurities from semiconductor device layers: A method for removing impurities from at least one semiconductor device layer during manufacturing of a semiconductor device is disclosed. The semiconductor device layer has a compound semiconductor material and/or germanium. Each heating process performed during the manufacturing of the semiconductor device after provision of the semiconductor device layer has... Agent: Knobbe Martens Olson & Bear LLP

20090273012 - High voltage tolerant metal-oxide-semiconductor device: A method for increasing a voltage tolerance of a MOS device having a first capacitance value associated therewith is provided. The method includes the steps of: connecting at least a first capacitor in series with the MOS device, the first capacitor having a first capacitance value associated therewith, the first... Agent: Ryan, Mason & Lewis, LLP

20090273013 - Method of forming a split gate memory device and apparatus: A split-gate memory device has a select gate having a first work function overlying a first portion of a substrate. A control gate having a second work function overlies a second portion of the substrate proximate the first portion. When the majority carriers of the split-gate memory device are electrons,... Agent: Freescale Semiconductor, Inc. Law Department

20090273014 - Nonvolatile semiconductor memory device: Each of a memory gate, a control gate, a source diffusion layer, and a drain diffusion layer is connected to a control circuit for controlling potential, and the control circuit operates so as to supply a first potential to the memory gate, a second potential to the control gate, a... Agent: Miles & Stockbridge PC

20090273016 - Nanocrystal formation using atomic layer deposition and resulting apparatus: Nanocrystal structures formed using atomic layer deposition (ALD) processes are useful in the formation of integrated circuits such as memory devices. Rather than continuing the ALD process until a continuous layer is formed, the ALD process is halted prematurely to leave a discontinuous formation of nanocrystals which are then capped... Agent: Leffert Jay & Polglaze, P.A.

20090273015 - Non-volatile memory cell: This document discloses non-volatile memory cells and methods of manufacturing the same. The non-volatile memory cells are self-aligned and have a reduced tunnel window area that is within an active region of a substrate. The tunnel window area can be reduced using mask openings without optical proximity correction that define... Agent: Fish & Richardson P.C.

20090273017 - Method for forming trenches on a surface of a semiconductor substrate: A method for forming trenches on a surface of a semiconductor substrate is described. The method may include: etching a first plurality of trenches into the surface of the semiconductor substrate; filling the first plurality of trenches with at least one material; and etching a second plurality of trenches into... Agent: Coats & Bennett/qimonda

20090273019 - Memory device transistors: Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET transistor gate dielectric smiling, or bird's beaks, are adjustable by re-oxidation processing. An additional re-oxidation process is performed by opening a poly-silicon layer prior to forming an inter-poly oxide dielectric... Agent: Schwegman, Lundberg & Woessner/micron

20090273018 - Nonvolatile memory device with multiple blocking layers and method of fabricating the same: A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blocking layer, wherein the first blocking layer... Agent: Lowe Hauptman Ham & Berner, LLP

20090273020 - Sonos flash memory: A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) flash memory, comprising: preparing a silicon substrate including a silicon oxide-silicon nitride-silicon oxide (ONO) layer, a first polysilicon layer and a first etch stop layer in sequence; etching the first etch stop layer along a direction of bit line; selectively etching the first... Agent: Squire, Sanders & Dempsey L.L.P.

20090273021 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a semiconductor substrate, a tunnel insulating film on the semiconductor substrate, a charge storage layer on the tunnel insulating film, a block insulating film on the charge storage layer, and a control gate electrode on the block insulating film, the charge storage layer including a plurality... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090273022 - Conductive hard mask to protect patterned features during trench etch: A monolithic three dimensional memory array is formed by a method that includes forming a first memory level above a substrate by i) forming a plurality of first substantially parallel conductors extending in a first direction, ii) forming first pillars above the first conductors, each first pillar comprising a first... Agent: Dugan & Dugan, PC

20090273023 - Segmented pillar layout for a high-voltage vertical transistor: In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor... Agent: The Law Offices Of Bradley J. Bereznak

20090273024 - Method for producing a transistor component having a field plate: A method for producing a transistor component having a field plate. One embodiment includes providing a semiconductor body having a first side, and including a first trench extending into the semiconductor body. A field plate dielectric layer is produced on the first side and at uncovered areas of the first... Agent: Dicke, Billig & Czaja

20090273025 - Semiconductor device and method for manufacturing the same: Disclosed herein are a semiconductor device and a method for manufacturing the same. The method includes forming a gate structure using a carbon nano tube (CNT). In order to prevent reduction of the gate resistance and the short channel effect, a CNT gate having a grown CNT pattern with a... Agent: Marshall, Gerstein & Borun LLP

20090273026 - Trench-gate ldmos structures: MOSFET devices for RF applications that use a trench-gate in place of the lateral gate conventionally used in lateral MOSFET devices. A trench-gate provides devices with a single, short channel for high frequency gain. Embodiments of the present invention provide devices with an asymmetric oxide in the trench gate, as... Agent: Townsend And Townsend And Crew, LLP

20090273027 - Power ic device and method for manufacturing same: In a power IC device, a surface layer channel CMOS transistor and a trench power MOS transistor are formed on the same chip. In one embodiment, a source region of the trench power MOS transistor is arranged at the same level as a gate electrode of the surface layer channel... Agent: Harness, Dickey & Pierce, P.L.C

20090273028 - Short channel lateral mosfet and method:

20090273029 - High voltage ldmos transistor and method: An LDMOS transistor structure and methods of making the same are provided. The structure includes a gate electrode extended on an upper boundary of an extension dielectric region that separates the gate electrode from the drain region of the LDMOS transistor. Moreover, at an area close to an edge of... Agent: Slater & Matsil, L.L.P.

20090273030 - Semiconductor device with a trench isolation and method of manufacturing trenches in a semiconductor body: A low cost integration method for a plurality of deep isolation trenches on the same chip is provided. The trenches have an additional n-type or p-type doped region surrounding the trench—silicon interface. Providing such variations of doping the trench interface is achieved by using implantation masking layers or doped glass... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090273031 - Semiconductor device: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a major surface of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the major surface of the first semiconductor... Agent: Patterson & Sheridan, L.L.P.

20090273032 - Ldmos device and method for manufacturing the same: Provided is a LDMOS device and method for manufacturing. The LDMOS device includes a second conductive type buried layer formed in a first conductive type substrate. A first conductive type first well is formed in the buried layer and a field insulator with a gate insulating layer at both sides... Agent: Jeff Lloyd Saliwanchik Lloyd & Saliwanchik

20090273033 - Electrostatic discharge protection circuit: An ESD protection circuit including a substrate of a first conductivity type, an annular well region of a second conductivity type, two first regions of the first conductivity type and at least one transistor of the second conductivity type is provided. The annular well region is disposed in the substrate.... Agent: J C Patents

20090273034 - Source/drain carbon implant and rta anneal, pre-sige deposition: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a... Agent: Slater & Matsil, L.L.P.

20090273036 - Method for reducing defects of gate of cmos devices during cleaning processes by modifying a parasitic pn junction: By incorporating nitrogen into the P-doped regions and N-doped regions of the gate electrode material prior to patterning the gate electrode structure, yield losses due to reactive wet chemical cleaning processes may be significantly reduced.... Agent: Williams, Morgan & Amerson

20090273035 - Method for selectively removing a spacer in a dual stress liner approach: By integrating a spacer removal process into the sequence for patterning a first stress-inducing material during a dual stress liner approach, the sidewall spacer structure for one type of transistor may be maintained, without requiring additional lithography steps.... Agent: Williams, Morgan & Amerson

20090273037 - Semiconductor integrated circuit device and manufacturing method thereof: After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film (10)... Agent: Miles & Stockbridge PC

20090273039 - Semiconductor device: A semiconductor device in which potential is uniformly controlled and in which the influence of noise is reduced. A p-type well region is formed beneath a surface of a p-type Si substrate. n-type MOS transistors are formed on the p-type well region. An n-type well region is formed in the... Agent: Fujitsu Patent Center C/o Cpa Global

20090273038 - Semiconductor device and a method of manufacturing the same: A technique is provided which permits formation within a single chip both a field effect transistor of high reliability capable of suppressing the occurrence of a crystal defect and a field effect transistor of a high integration degree. In a mask ROM section having an element isolation region with an... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090273040 - High performance schottky-barrier-source asymmetric mosfets: The present invention, in one embodiment, provides a semiconductor device including a semiconducting body including a schottky barrier region at a first end of the semiconducting body, a drain dopant region at the second end of the semiconducting body, and a channel positioned between the schottky barrier region and the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090273042 - Metal high dielectric constant transistor with reverse-t gate: A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric constant material, a second... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.

20090273041 - Transistor with high-k dielectric sidewall spacer: A transistor is provided that includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.

20090273043 - Micro-electro-mechanical system device and method for making same: According to the present invention, a micro-electro-mechanical system (MEMS) device comprises: a thin film structure including at least a metal layer and a protection layer deposited in any order; and a protrusion connected under the thin film structure. A preferred thin film structure includes at least a lower protection layer,... Agent: Global Patents

20090273045 - Magnetic memory device and method of fabricating the same: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed... Agent: F. Chau & Associates, LLC

20090273044 - Semiconductor device, memory module, and method of manufacturing a semiconductor device: According to one embodiment of the present invention, a semiconductor device is provided including a semiconductor chip. The semiconductor chip is at least partly surrounded by a surrounding structure. The semiconductor chip further includes a magneto-resistive memory cell. A shielding layer is disposed between the semiconductor chip and the surrounding... Agent: Slater & Matsil, L.L.P.

20090273048 - Image-sensing chip package module adapted to dual-side soldering: An image-sensing chip package module adapted to dual-side soldering includes three substrates, an image-sensing chip and a filter lens. The three substrates are stacked together by pressing (using adhesive as adhesion medium), and the image-sensing chip is electrically connected to the top side of the top substrate and the bottom... Agent: Rosenberg, Klein & Lee

20090273046 - Process for producing solid-state image sensing device, solid-state image sensing device and camera: In the formation of a multilayer interference filter that is included in a solid-state imaging device, at the outset, a titanium dioxide layer (401), a silicon dioxide layer (402), a titanium dioxide layer (403), and a spacer layer are successively laminated on an interlayer insulation film (304) to form a... Agent: Mcdermott Will & Emery LLP

20090273047 - Solid state imaging device and manufacturing method thereof: To a transparent substrate (20) on which a plurality of spacers (5) are formed, an infrared cut filter (IRCF) substrate (27) is attached. The IRCF substrate (27) has a coefficient of thermal expansion smaller than the transparent substrate (20) and approximately equal to a wafer (31). Next, the transparent substrate... Agent: Birch Stewart Kolasch & Birch

20090273049 - Wdm signal detector: A detector includes a light detecting layer and a grating structure. The light detecting layer, which can be a photodiode, has an optical mode that resonates in the light detecting layer, and the grating structure is positioned to interact with the optical mode. The grating structure further couples incident light... Agent: Hewlett-packard Company Intellectual Property Administration

20090273050 - Photoelectric conversion device and method of producing the same, and method of producing line image sensor ic: A plurality of line image sensor ICs 110 are formed to be arranged in X, Y directions with gaps therebetween on a semiconductor substrate 101. The gaps between the line image sensor ICs 110 become scribe lines 102X, 102Y. A pattern of dummy interconnects 120 is formed in a region... Agent: Brinks Hofer Gilson & Lione/seiko Instruments Inc.

20090273051 - Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same: Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch... Agent: Wells St. John P.s.

20090273052 - Reducing device performance drift caused by large spacings between action regions: A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a... Agent: Slater & Matsil, L.L.P.

20090273053 - Semiconductor device including analog circuitry having a plurality of devices of reduced mismatch: In an analog circuit portion, a systematic mismatch between a plurality of circuit elements may be reduced in view of a technology gradient by appropriately positioning the unit devices of the circuit elements so as to obtain a similar response of the circuit elements with respect to the gradient. For... Agent: Williams, Morgan & Amerson

20090273055 - Fuse structure: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the... Agent: Slater & Matsil, L.L.P.

20090273054 - Non-volatile memory device and method of fabricating the same: A non-volatile memory device and methods of fabricating the device according to example embodiments involve a stacked layer structure. The non-volatile memory device may include at least one first horizontal electrode including a first sidewall and a second sidewall; at least one second horizontal electrode including a third sidewall and... Agent: Harness, Dickey & Pierce, P.L.C

20090273056 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate, and an electrical fuse provided on the semiconductor substrates. The electrical fuse includes a first fuse link and a second fuse link mutually connected in series, a first current inlet/outlet terminal (first terminal) and a second current inlet/outlet terminal (second terminal) respectively provided... Agent: Young & Thompson

20090273058 - Electrical components for microelectronic devices and methods of forming the same: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying... Agent: Perkins Coie LLP Patent-sea

20090273057 - Method, apparatus, and system for low temperature deposition and irradiation annealing of thin film capacitor: Some embodiments of the invention include thin film capacitors formed in a package substrate of an integrated circuit package. At least one of the thin film capacitors includes a first electrode layer, a second electrode layer, and a dielectric layer between the first and second electrode layers. Each of the... Agent: Schwegman, Lundberg & Woessner/intel

20090273059 - Semiconductor integrated circuit having polysilicon members: A semiconductor integrated circuit includes a substrate, an oxide layer formed on an upper surface of the substrate, a plurality of polysilicon members arranged at constant intervals in a matrix on an upper surface of the oxide layer and including at least one first polysilicon member and a plurality of... Agent: Arent Fox LLP

20090273060 - Group iii nitride crystal and method for surface treatment thereof, group iii nitride stack and manufacturing method thereof, and group iii nitride semiconductor device and manufacturing method thereof: A method for surface treatment of a group III nitride crystal includes the steps of lapping a surface of a group III nitride crystal using a hard abrasive grain with a Mohs hardness higher than 7, and abrasive-grain-free polishing the lapped surface of the group III nitride crystal using a... Agent: Drinker Biddle & Reath (dc)

20090273061 - Semiconductor substrate, semiconductor device, and method for manufacturing the semiconductor substrate: A double-structure silicon on insulator (SOI) substrate with a silicon layer, an insulation film (silicon oxide film), a silicon layer, and an insulation film in this order from the side of the surface. The upper-layer insulation film is formed so as to have a uniform distribution of depth while the... Agent: Sonnenschein Nath & Rosenthal LLP

20090273062 - Semiconductor package heat spreader: A semiconductor heat spreader from a unitary metallic plate is provided. The unitary metallic plate is formed into a panel, channel walls, at least two feet, and at least one external reversing bend. The channel walls depend from the panel to define a channel between the channel walls and the... Agent: Law Offices Of Mikio Ishimaru

20090273063 - Semiconductor device: One embodiment provides a semiconductor device including a carrier, a first chip attached to the carrier, a structured dielectric coupled to the chip and to the carrier, and a conducting element electrically connected with the chip and extending over a portion of the structured dielectric. The conducting element includes a... Agent: Dicke, Billig & Czaja

20090273064 - Semiconductor device and inspection method therefor: A semiconductor device includes a circuit block formed in a peripheral edge portion of a semiconductor chip, a circuit block pad formed on the circuit block providing an electrical connection for said circuit block, and a bonding pad laterally offset from the circuit block and the circuit block pad, the... Agent: Mcginn Intellectual Property Law Group, PLLC

20090273065 - Interconnection of lead frame to die utilizing flip chip process: Embodiments in accordance with the present invention relate to techniques which avoid the problems of deformation in the shape of a solder connection in a flip chip package, resulting from solder reflow. In one embodiment, a solder-repellent surface is created adjacent to the solder to constrain the reflow and thereby... Agent: Townsend And Townsend And Crew, LLP

20090273066 - Semiconductor device and method: An electronic device and fabrication of an electronic device. One embodiment provides applying a paste including electrically conductive particles to a surface of a semiconductor wafer. The semiconductor wafer is singulated with the electrically conductive particles for obtaining a plurality of semiconductor chips. At least one of the plurality of... Agent: Dicke, Billig & Czaja

20090273067 - Multi-chip discrete devices in semiconductor packages: Semiconductor packages that contain multiple dies containing discrete devices and methods for making such devices are described. The semiconductor package contains both a first die containing transistor and second die containing a diode. The interconnect lead of the semiconductor package is connected to the bond pad of the transistor. At... Agent: Kenneth E. Horton Kirton & Mcconkle

20090273068 - 3-d integrated circuit lateral heat dissipation: By filling an air gap between tiers of a stacked IC device with a thermally conductive material, heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the... Agent: Qualcomm Incorporated

20090273069 - Low profile chip scale stacking system and method: The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of... Agent: Fish & Richardson P.C.

20090273071 - Ic chip mounting package and process for manufacturing the same: In one embodiment of the present invention, an IC chip mounting package is arranged such that an IC chip and a film base member are connected via an interposer, and a section in which the IC chip, the film base member, and the interposer are connected is sealed with sealing... Agent: Harness, Dickey & Pierce, P.L.C

20090273070 - Liquid resin composition for electronic components and electronic component device: The invention relates to a liquid resin composition for electronic components which is used in sealing of electronic components, comprising a liquid epoxy resin, a curing agent containing a liquid aromatic amine, and an inorganic filler, and further comprising at least one member selected from a hardening accelerator, silicone polymer... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090273074 - Bond wire loop for high speed noise isolation: Semiconductor dies embodying electronic circuits are enclosed and protected within a package. To electrically access the die, the package includes external electrical leads which in turn connect to internal bond wires. The bond wires electrically connect the package to the die. As die density and circuit complexity increase, bond wire... Agent: Weide & Miller - Mindspeed

20090273073 - Connecting structure for flip-chip semiconductor package, build-up layer material, sealing resin composition, and circuit board: The invention provides a connecting structure for a flip-chip semiconductor package in which cracking and delamination are inhibited or reduced to improve reliability, and in which the potential range of designs is expanded for the inner circuitry of circuit boards and the inductance is reduced. The invention is a connecting... Agent: Smith, Gambrell & Russell

20090273072 - Semiconductor device and method for manufacturing the same: Disclosed is a semiconductor device eliminated of the effect of an adhesive used in assembling upon the semiconductor chip. According to the semiconductor device, the semiconductor device includes a board, a semiconductor chip provided on and contacting with the board, and a plurality of wires each having both ends firmly... Agent: Sughrue Mion, PLLC

20090273075 - Semiconductor device and manufacturing of the semiconductor device: A semiconductor device. In one embodiment the device includes a carrier. A first material is deposited on the carrier. The first material has an elastic modulus of less than 100 MPa. A semiconductor chip is placed over the first material. A second material is deposited on the semiconductor chip, the... Agent: Dicke, Billig & Czaja

20090273076 - Tape for heat dissipating member, chip on film type semiconductor package including heat dissipating member, and elctronic apparatus including the same: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface... Agent: Harness, Dickey & Pierce, P.L.C

20090273077 - Multi-lid semiconductor package: A multi-lid semiconductor package includes one or more die disposed on a substrate, an interconnect disposed on the substrate, one or more die lids, a die thermal interface between the one or more die and the corresponding die lid or lids, one or more substrate lids, and a substrate interface... Agent: Osha Liang L.L.P./sun

20090273080 - Display device and manufacturing method of the same: A display device includes a drive circuit chip, and a substrate on which the drive circuit chip is mounted. The drive circuit chip includes a semiconductor substrate, an insulation layer, a first conductive layer and a second conductive layer formed of metal between the semiconductor substrate and the insulation layer,... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090273078 - Electronic packages: Assemblies involving integrated circuit dies (e.g. packaged integrated circuits) and packaged dies electrically connected to circuit boards at times mechanically fail at conducting pads used for electrical interconnection. Such failure is mitigated by underlying appropriate pads with a compliant region having specific characteristics.... Agent: Mendelsohn, Drucker, & Associates, P.C.

20090273079 - Semiconductor package having passive component bumps: A semiconductor package includes contact bumps configured as passive circuit components. One or more contact bumps of the semiconductor package may be formed or configured as pull-up resistors, pull-down resistors, capacitors or inductors.... Agent: Warren A. Sklar (soer) Renner, Otto, Boisselle & Sklar, LLP

20090273081 - Pad cushion structure and method of fabrication for pb-free c4 integrated circuit chip joining: A controlled collapse chip connection (C4) method and integrated circuit structure for lead (Pb)-free solder balls with stress relief to the underlying insulating layers of the integrated circuit chip by deposing soft thick insulating cushions beneath the solder balls and connecting the metallization of the integrated circuit out-of-contact of the... Agent: Edward W. Brown

20090273082 - Methods and designs for localized wafer thinning: Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no... Agent: Kenneth E. Horton Kirton & Mcconkle

20090273083 - Electrically conductive fluid interconnects for integrated circuit devices: Disclosed are embodiments of an electrically conductive fluid interconnect for coupling an integrated circuit (IC) device to a substrate. The IC device may be coupled to the substrate in a socketless manner or using a socket. The electrically conductive fluid interconnect may include, for example, a metal, an electrically conductive... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090273085 - Cusin/sin diffusion barrier for copper in integrated-circuit devices: The present invention relates to an integrated-circuit device that has at least one Copper-containing feature in a dielectric layer, and a diffusion-barrier layer stack arranged between the feature and the dielectric layer. The integrated-circuit device of the invention has a diffusion-barrier layer stack, which comprises, in a direction from the... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090273084 - Optically transparent wires for secure circuits and methods of making same: A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive... Agent: Schmeiser, Olsen & Watts

20090273086 - Method of reducing erosion of a metal cap layer during via patterning in semiconductor devices: During the patterning of via openings in sophisticated metallization systems of semi-conductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may be established to redistribute material of the underlying metal region to exposed sidewall portions of the conductive cap layer, thereby establishing a... Agent: Williams, Morgan & Amerson

20090273087 - Closed-loop sputtering controlled to enhance electrical characteristics in deposited layer: This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with metal oxide deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of a desired electrical property as a function of cathode... Agent: Marc P. Schuyler

20090273089 - Method for manufacturing semiconductor device and semiconductor device: A semiconductor device in which a conductor of a bit line may be made as large in thickness as possible to reduce resistance of the bit line and to reduce capacitance across the neighboring bit lines. The device includes a first interlayer film having a first contact metal part accommodated... Agent: Mcginn Intellectual Property Law Group, PLLC

20090273091 - Semiconductor device and metal line fabrication method of the same: Embodiments relate to a method for forming a wiring in a semiconductor device, that may include laminating a conductive layer for wiring formation on a semiconductor substrate, forming a photoresist layer pattern on the conductive layer, performing primary dry etching for the conductive layer after employing the photoresist layer pattern... Agent: Sherr & Vaughn, PLLC

20090273088 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device includes forming a metal word line additionally over a vertical transistor to obtain a multi-layered structure, thereby preventing degradation of the operating speed of the semiconductor device by preventing an increase of resistance of a damascene word line that connects a surrounding gate... Agent: Marshall, Gerstein & Borun LLP

20090273090 - Semiconductor device and method for manufacturing the same: Embodiments relate to a semiconductor device and a method for manufacturing the same. Embodiments may include forming a lower porous oxide layer on a semiconductor substrate having a conductive layer, forming a pyrolytic polymer layer on the lower porous oxide layer, forming an upper porous oxide layer on the pyrolytic... Agent: Sherr & Vaughn, PLLC

20090273092 - Semiconductor module having an interconnection structure: In a method for manufacturing a semiconductor module, a metal layer is formed on a support substrate. Then, first conductive posts and a first insulating layer are formed on the metal layer. The first insulating layer surrounds the sides of the first conductive posts. Then, second conductive posts are formed... Agent: Young & Thompson

20090273093 - Planar packageless semiconductor structure with via and coplanar contacts: A semiconductor device includes a substrate having a first side and a second side and an epitaxial layer disposed over the second side. The device also includes a conductive via extending through the epitaxial layer to the second side and comprising a conductive contact; and a bond pad disposed over... Agent: Kathy Manke Avago Technologies Limited

20090273096 - High density memory device manufacturing using isolated step pads: An electronic device includes multiple IC dies stacked in an offset stacking arrangement on a substrate. Each IC die includes electrically isolated step pads that facilitates transmitting a dedicated signal between a (beginning) substrate bonding pad and a selected (terminal) contact pad of any die by way of short bonding... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way

20090273094 - Integrated circuit package on package system: An integrated circuit package on package system including: forming a first substrate assembly; forming a second substrate, having an auxiliary access port, supported by the first substrate assembly; exposing an integrated circuit die through the auxiliary access port; and coupling an external integrated circuit on the second substrate.... Agent: Law Offices Of Mikio Ishimaru

20090273095 - Rectangular-shaped controlled collapse chip connection: A rectangular-shaped controlled collapse chip connection (C4) is described. In one embodiment, there is a semiconductor chip package that comprises a semiconductor chip package substrate and a semiconductor chip having a plurality of rectangular-shaped C4 contacts attached thereto that connect the semiconductor chip to the semiconductor chip package substrate. The... Agent: Hoffman Warnick LLC

20090273098 - Enhanced architectural interconnect options enabled with flipped die on a multi-chip package: A particular chip is designed having a first variant (front side connected chip) of the chip and a second variant (back side connected chip). The first variant of the chip is attached to a carrier. The second variant of the chip is attached to the carrier inverted relative to the... Agent: Robert R. Williams IBM Corporation

20090273097 - Semiconductor component with contact pad: A structure and method of forming low cost bond pads is described. In one embodiment, the invention includes depositing an insulating layer over a last metal line of a substrate and forming an opening in the insulating layer. A colloid is printed over the insulating layer and fills the opening... Agent: Slater & Matsil, L.L.P.

20090273101 - Apparatus and method for preventing configurable system-on-a-chip integrated circuits from becoming i/o limited: An integrated circuit containing multiple modules coupled to a pad via a multiplexer. The modules are selectively coupled to the pad by the multiplexer to provide integrated circuit function flexibility with a limited number of pads. A multiplexer select signal determines which module or clock circuit is coupled by the... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090273100 - Integrated circuit having interleaved gridded features, mask set and method for printing: A method (300) for fabricating an integrated circuit includes the step of providing a substrate having a semiconductor surface (305). For at least one masking level (e.g. gate electrode, contact or via) of the integrated circuit, a mask pattern for the masking level is partitioned into a first mask and... Agent: Texas Instruments Incorporated

20090273099 - Semiconductor integrated circuit: On a semiconductor chip in a semiconductor integrated circuit, a plurality of circuit cells each of which has a pad are formed along a first chip side of the semiconductor chip. Among the plurality of circuit cells, one or more circuit cells at least in the vicinity of an end... Agent: Mcdermott Will & Emery LLP

20090273102 - Semiconductor substrate and method for manufacturing the same: A trench 11 is formed in an alignment region of an N+-type substrate 1. This trench 11 is used to leave voids 3 after the formation of an N−-type layer 2. Then, the voids 3 formed in the N+-type substrate 1 can be used as an alignment mark. Thus, such... Agent: Duane Morris LLP - Ny Patent Department