Active solid-state devices (e.g., transistors, solid-state diodes) inventions 10/09

20090242865 - Memory array with diode driver and method for fabricating the same: A method of fabricating a memory array. The method begins with a structure, generally composed of dielectric fill material and having conductive lines formed at its lower portion, and a sacrificial layer formed on its upper surface. Diodes are formed in the fill material, each diode having a lightly-doped first... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090242866 - Phase change memory device and method of fabricating the same: A semiconductor device includes an insulating layer on a substrate, a first electrode in the insulating layer having a first upper surface and a second upper surface, a second electrode in the insulating layer spaced apart from the first electrode by a first distance and having a third upper surface... Agent: Lee & Morse, P.C.

20090242867 - Phase change memory device having protective layer for protecting phase change material and method for manufacturing the same: A phase change memory device includes a semiconductor substrate, a plurality of bottom electrodes formed on the substrate, a plurality of phase change structures formed on the semiconductor substrate, each respectively contacting one of the bottom electrodes, and each having a phase change material layer and a top electrode stacked... Agent: Baker & Mckenzie LLP Patent Department

20090242868 - Semiconductor device and method of manufacturing the same: A solid electrolyte memory involves a problem that stable rewriting is difficult since the amount of ions in the solid electrolyte and the shape of the electrode are changed by repeating rewriting. In a semiconductor device in which information is stored or the circuit connection is changed by the change... Agent: Miles & Stockbridge PC

20090242870 - Light emitting device and method for manufacturing the same: Disclosed herein is a light emitting device. The light emitting device includes an n-type nitride semiconductor layer; an active layer on the n-type semiconductor layer, an AlN/GaN layer of a super lattice structure formed by alternately growing an AlN layer and a GaN layer on the active layer, and a... Agent: H.c. Park & Associates, PLC

20090242871 - Quantum dot inorganic electroluminescent device: An inorganic EL device is provided with a substrate, a first electrode, a first insulating layer, a light emitting layer, a second insulating layer and a second electrode. The inorganic EL light emitting device is characterized in that the light emitting layer contains a quantum dot and is arranged between... Agent: Oliff & Berridge, PLC

20090242869 - Super lattice/quantum well nanowires: Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such... Agent: Connolly Bove Lodge & Hutz LLP

20090242872 - Double quantum well structures for transistors: Double quantum well structures for transistors are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a first quantum well channel coupled with the first barrier... Agent: Cool Patent, P.C. C/o Cpa Global

20090242873 - Semiconductor heterostructures to reduce short channel effects: Semiconductor heterostructures to reduce short channel effects are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a back gate layer coupled to the first barrier... Agent: Cool Patent, P.C. C/o Cpa Global

20090242874 - Gan based semiconductor light-emitting device and method for producing same: A GaN based semiconductor light-emitting device is provided. The light-emitting device includes a first GaN based compound semiconductor layer of an n-conductivity type; an active layer; a second GaN based compound semiconductor layer; an underlying layer composed of a GaN based compound semiconductor, the underlying layer being disposed between the... Agent: K&l Gates LLP

20090242876 - Carbazole compounds: The present invention relates to carbazole compounds of formula (I) and a semiconducting material comprising such carbazole compounds. It also relates to a process for the preparation of such carbazole compounds, as well as to the use thereof as a semiconducting material, in particular as a host matrix for phosphorescent... Agent: Philips Intellectual Property & Standards

20090242875 - Forming electrodes to small electronic devices having self-assembled organic layers: In one embodiment of the invention, a method of fabricating a SAM device comprises the steps of: (a) providing a substrate having a top surface and a first metal electrode disposed on the top surface, (b) annealing the first metal electrode, (c) forming a SAM layer on a major surface... Agent: Michael J. Urbano

20090242877 - Oled device with hole-transport and electron-transport materials:

20090242878 - Optimization of new polymer semiconductors for better mobility and processibality:

20090242879 - Optoelectronic device and method of fabricating the same: A modified isolated polypeptide comprising an amino acid sequence encoding a photocatalytic unit of a photosynthetic organism being capable of covalent attachment to a solid surface and having a photocatalytic activity when attached thereto is disclosed.... Agent: Martin D. Moynihan D/b/a Prtsi, Inc.

20090242880 - Thermally stabilized electrode structure: Memory devices and methods for manufacturing are described herein. A memory device as described herein includes a first electrode layer, a second electrode layer, and a thermal isolation structure comprising a layer of thermal isolation material between the first and second electrode layers. The first and second electrode layers and... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090242881 - Thin film transistor substrate, display device having the same and method of manufacturing the display device: A thin film transistor substrate includes an insulating plate; a gate electrode disposed on the insulating plate; a semiconductor layer comprising a metal oxide, wherein the metal oxide has oxygen defects of less than or equal to 3%, and wherein the metal oxide comprises about 0.01 mole/cm3 to about 0.3... Agent: Cantor Colburn, LLP

20090242882 - Three-dimensional microstructures and methods for making same: Microstructures can be formed as patterned layers on a substrate and then erecting the microstructures out of the plane of the substrate. The microstructures may be formed over circuits in the substrate. In some embodiments the patterned layer provides resiliently-flexible members such as cantilevers or springs that can be buckled... Agent: Oyen, Wiggs, Green & Mutala LLP 480 - The Station

20090242888 - Display device and method for manufacturing the same: In a pixel portion, a scan signal line and an auxiliary capacitor line are formed using a second conductive film, and a data signal line is formed using a first conductive film. In a TFT portion, a gate electrode is formed using the first conductive film and electrically connected to... Agent: Cook Alex Ltd.

20090242887 - Display substrate having a transparent conductive layer made of zinc oxide and manufacturing method thereof: A display substrate is disclosed comprising: a supporting substrate; an organic resin layer formed on the supporting substrate; and a transparent electrode formed on the organic resin layer, wherein the transparent electrode includes: a first layer containing a zinc oxide and formed in close contact with the organic resin layer;... Agent: Masao Yoshimura, Chen Yoshimura LLP

20090242885 - Manufacturing process of liquid crystal display device, and liquid crystal display device: A manufacturing process of an LCD de vice of the invention includes forming a first substrate provided with a pixel part with thin film transistors and a seal portion arranged around the pixel part, forming a second substrate opposed to the first substrate, filling a liquid crystal layer between the... Agent: Young & Thompson

20090242884 - Method of producing display device, display device, method of producing thin-film transistor substrate, and thin-film transistor substrate: A method of producing a display device includes the steps of forming gate electrodes on a substrate so that an arrangement of a source and a drain, in a pixel row direction, of a thin-film transistor formed in each of pixels on the substrate is reversed every pixel row; forming... Agent: Rader Fishman & Grauer PLLC

20090242886 - Thin film transistor substrate: In forming a thin film transistor using multi-tone exposure, a wiring width of a foundational wiring is 40 μm or less, and a ratio of a wiring width of a foundational wiring in a dense case to a space between adjacent wirings is 1.7, preferably 1.0 or less.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242883 - Thin film transistor, active array substrate and method for manufacturing the same: A thin film transistor, an active array substrate having the same and methods for manufacturing the same are provided. The thin film transistor includes a base having a concave; a gate disposed in the concave; a gate insulator covering the gate and a portion of the gate insulator is in... Agent: Bacon & Thomas, PLLC

20090242889 - Thin film transistor, method for manufacturing the same, and display: Disclosed is a thin film transistor which is characterized by including a gate electrode 3, a gate insulating film 4, a channel layer 5 and source/drain layers 7, 8 stacked over a substrate 2 in this order or in reverse order, wherein the source/drain layers 7, 8 include n-type microcrystalline... Agent: Sonnenschein Nath & Rosenthal LLP

20090242892 - Semiconductor device and method for forming the same: In fabricating a thin film transistor, an active layer comprising a silicon semiconductor is formed on a substrate having an insulating surface. Hydrogen is introduced into The active layer. A thin film comprising SiOxNy is formed to cover the active layer and then a gate insulating film comprising a silicon... Agent: Eric Robinson

20090242890 - Semiconductor device, electrooptical apparatus, and electronic system: A semiconductor device on a flexible substrate includes a semiconductor layer constituting a plurality of bottom-gate thin-film transistors, first wiring lines, second wiring lines, a first insulating layer, and a gate insulating film. The first insulating layer and the gate insulating film are present below the semiconductor layer, the first... Agent: Harness, Dickey & Pierce, P.L.C

20090242891 - Thin-film semiconductor device and method for manufacturing the same: A thin-film semiconductor device including a transparent insulating substrate, an island semiconductor layer formed on the transparent insulating substrate and including a source region containing a first-conductivity-type impurity and a drain region containing a first-conductivity-type impurity and spaced apart from the source region, a gate insulating film and a gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242893 - Semiconductor device, production method thereof, and display device: The present invention provides a semiconductor device which can be produced by simple and cheap processes and effectively achieve improved performances and a reduced electric power consumption. Further, the present invention provides a production method thereof and a display device including the semiconductor device or a semiconductor device produced by... Agent: Nixon & Vanderhye, PC

20090242895 - Thin film transistor, method of fabricating the same, and organic lighting emitting diode display device including the same: A thin film transistor, a method of fabricating the same, and an organic light emitting diode display device including the same. The thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, including a channel region, source/drain regions, and a body contact region; a gate insulating layer... Agent: Stein Mcewen, LLP

20090242894 - Thin-film-transistor structure, pixel structure and manufacturing method thereof: A thin-film-transistor (TFT) structure, a pixel structure and a manufacturing method thereof are provided. The TFT structure is formed in the pixel structure of a liquid crystal display (LCD). The TFT structure comprises a gate, a first dielectric layer, a patterned semiconductor layer, a second dielectric layer and a third... Agent: James M. Wu Jw Law Group

20090242896 - Semiconductor device and method for manufacturing the same: A microstructure and a semiconductor element which are included in a micromachine have been generally formed in different steps. It is an object to provide a method for manufacturing a micromachine in which a microstructure and a semiconductor element are formed over one insulating substrate. A feature of the invention... Agent: Fish & Richardson P.C.

20090242897 - Indium gallium nitride-based ohmic contact layers for gallium nitride-based devices: Light emitting devices include a gallium nitride-based epitaxial structure that includes an active light emitting region and a gallium nitride-based outer layer, for example gallium nitride. A indium nitride-based layer, such as indium gallium nitride, is provided directly on the outer layer. A reflective metal layer or a transparent conductive... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090242898 - Method of controlling stress in gallium nitride films deposited on substrates: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial... Agent: Gates & Cooper LLP Howard Hughes Center

20090242899 - Epitaxial growth on low degree off-axis sic substrates and semiconductor devices made thereby: A method of epitaxially growing a SiC layer on a single crystal SiC substrate is described. The method includes heating a single-crystal SiC substrate to a first temperature of at least 1400° C. in a chamber, introducing a carrier gas, a silicon containing gas and carbon containing gas into the... Agent: Morris Manning Martin LLP

20090242900 - Memory device and method of manufacturing the same: The invention discloses a memory device and method thereof. The memory device comprises a substrate, an insulator layer, a first conducting layer, a CaCu3Ti4O12 resistor layer and a second conducting layer. The insulator layer is formed over the substrate. The first conducting layer is formed over the insulator layer. The... Agent: Morris Manning Martin LLP

20090242901 - Sic mosfets and self-aligned fabrication methods thereof: The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer.... Agent: General Electric Company Global Research

20090242902 - Light emitting devices with constant forward voltage: A light emitting device and method for producing the same is disclosed. The light emitting device includes a semiconductor material, an electrode positioned on the semiconductor material, a wire bonding area, and a resistor connected between the wire bonding area and the electrode.... Agent: Arent Fox LLP

20090242907 - Display device and manufacturing method thereof: To achieve enlargement and high definition of a display portion, a single crystal semiconductor film is used as a transistor in a pixel, and the following steps are included: bonding a plurality of single crystal semiconductor substrates to a base substrate; separating part of the plurality of single crystal semiconductor... Agent: Eric Robinson

20090242910 - Light emitting device: A light emitting device includes: a first semiconductor region; a second semiconductor region and third semiconductor region which are provided in the first semiconductor region; a first semiconductor light emitting element of which first electrode is electrically connected to a main surface of the second semiconductor region; a second semiconductor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242909 - Light-emitting device, linear light source, planar light unit and display apparatus: A light-emitting device used in a linear array of a plurality of them includes a semiconductor light-emitting element, a substrate on which the semiconductor light-emitting element is mounted, and a light-transmitting sealing resin formed on the front surface of the substrate to seal the semiconductor light-emitting element. Of each of... Agent: Brinks Hofer Gilson & Lione

20090242903 - Luminous body with led dies and production thereof: A luminous body comprises a transparent plastic moulding with indentations, and LED DIEs disposed within the indentations. One side of each LED DIE lies approximately flush with an upper side of the moulding, and each LED DIE is connected to an electricity supply via electrical conductors disposed on the moulding.... Agent: Connolly Bove Lodge & Hutz, LLP

20090242908 - Planar light source device: A planar light source device includes: a substrate having a thickness larger than 0.9 mm and including a metal layer; and a plurality of light-emitting diode chips disposed on the substrate in a matrix array. Each light-emitting diode chip has a chip size ranging from 0.0784 mm2 to 0.25 mm2.... Agent: Darby & Darby P.C.

20090242905 - Semiconductor device, optical print head and image forming apparatus: A semiconductor device and an optical print head, an image forming apparatus that has the semiconductor device are supplied capable of reduce occurrence probability of defect. The semiconductor device is formed by using semiconductor thin film bonded on the substrate, and includes a covering layer that covers at least one... Agent: Panitch Schwarze Belisario & Nadel LLP

20090242904 - Semiconductor light emitting apparatus and optical print head: A semiconductor light emitting apparatus is supplied capable of providing a high performance that can optimize simultaneously both an electrical characteristic and a light emitting characteristic. The semiconductor apparatus comprises an anode layer; a cathode layer that has a conductive type different from that of the anode layer; a gate... Agent: Panitch Schwarze Belisario & Nadel LLP

20090242906 - Semiconductor light emitting device and semiconductor light emitting unit: A semiconductor light emitting device includes: an outer surrounding body having a recessed portion formed in an upper surface of the outer surrounding body; a lead terminal led out from a side surface of the outer surrounding body; and a semiconductor light emitting element disposed in the recessed portion. The... Agent: Wilmerhale/dc

20090242912 - Multifunctional tape: A method comprises forming elongate structures (5) on a first substrate (3), such that the material composition of each elongate structure (7) varies along its length so as to define first and second physically different sections in the elongate structures. First and second physically different devices (1,2) are then defined... Agent: Mark D. Saralino ( Sharp ) Renner, Otto, Boisselle & Sklar, LLP

20090242911 - Organic light-emitting display device: An object of the present invention is to provide an organic light-emitting display device using a number of organic light-emitting elements that emit lights of different colors, wherein the life of the organic light-emitting elements that emits light of a color having a short life can be prolonged. According to... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090242918 - High efficiency group iii nitride led with lenticular surface: A light emitting diode is disclosed that includes a conductive substrate, a bonding metal on the conductive substrate and a barrier metal layer on the bonding metal. A mirror layer is encapsulated by the barrier metal layer and is isolated from the bonding metal by the barrier layer. A p-type... Agent: Summa, Additon & Ashe, P.A.

20090242914 - Led assembly with high heat dissipating capability: An LED assembly includes a substrate and a plurality of LEDs mounted on the substrate. Each LED comprises an LED die mounted on the substrate via an adhesive, a base spacedly surrounding the LED die, a pair of leads inserted in the base to be in electrical connection with the... Agent: PCe Industry, Inc. Att. Steven Reiss

20090242919 - Light emitting device: A light emitting device includes a leadframe, a light emitting unit, a transparent encapsulant, and a fluorescent colloid layer. The light emitting unit is disposed on the leadframe. The transparent encapsulant covers the light emitting unit, wherein the transparent encapsulant has a concave on which at least one reflective surface... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090242917 - Light-emitting device including light-emitting diode: A light-emitting device includes a light-emitting diode, a red light-emitting phosphor layer, a yellow light-emitting phosphor layer, and a blue light-emitting phosphor layer. These layers are stacked in the stacking sequence of the yellow, blue, and red phosphor layers in order of increasing distance from the LED. The stacking sequence... Agent: Mcginn Intellectual Property Law Group, PLLC

20090242921 - Method for coating phosphor, apparatus to perform the method, and light emitting diode comprising phosphor coating layer: A method of forming a phosphor coating layer on a light emitting diode (LED) chip using electrophoresis includes separating phosphor particles in a suspension according to a particle size, and coating the phosphor particles on a surface of the LED chip by sequentially depositing the separated phosphor particles on the... Agent: H.c. Park & Associates, PLC

20090242916 - Method for packaging a light emitting device: A method for packaging a light emitting element includes a step of providing a carrier formed with an anode electrode and a cathode electrode, a step of providing a light emitting object by utilizing a light emitting diode chip having a positive and negative electrodes, a step of directly contacting... Agent: Rosenberg, Klein & Lee

20090242915 - Semiconductor light-emitting device: A semiconductor light-emitting device includes: a hollow body including a bottom wall and a surrounding wall cooperating with the bottom wall to define an encapsulant-receiving recess, the bottom wall being formed with a through-hole, the surrounding wall having a diffuse surface that surrounds the encapsulant-receiving recess; a heat-dissipating body provided... Agent: Rosenberg, Klein & Lee

20090242920 - Side view led package and back light module comprising the same: Disclosed is a side view LED package that can be more accurately mounted onto a surface of a substrate such as a printed circuit board without distortion includes a first portion of a body allowing light to be emitted in front thereof, the first portion having a horizontal plane formed... Agent: H.c. Park & Associates, PLC

20090242913 - Silicon based light emitting diode: Provided is a highly efficient silicon-based light emitting diode (LED) including a Distributed Bragg Reflector (DBR), an n-type doping layer, and a p-type substrate structure. The silicon-based LED includes: a substrate having a p-type mesa substrate structure; an active layer that is formed on the substrate and has a first... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090242923 - Hermetically sealed device with transparent window and method of manufacturing same: The invention is a hermetically sealed semiconductor die package wherein a surface of the die can be positioned very close to the hermetic package and a method of fabricating such a package. The invention is particularly suited to hermetically sealed circuit components, such as dies with a light emitting surface... Agent: Christopher P. Maiorana, P.C.

20090242924 - Light emitting diodes with smooth surface for reflective electrode: A light emitting diode comprising an epitaxial layer structure, a first electrode, and a second electrode. The first and second electrodes are separately disposed on the epitaxial layer structure, and the epitaxial layer structure has a root-means-square (RMS) roughness less than about 3 at a surface whereon the first electrode... Agent: Arent Fox LLP

20090242922 - Light-emitting diode lamp: A light-emitting diode (LED) lamp includes a columnar body having a plurality of heat-radiating fins, an LED supporting end, and a mounting end; a first conducting plate disposed on the LED supporting end; an LED having a first electrode in electric contact with the first conducting plate; a second conducting... Agent: Wpat, PC Intellectual Property Attorneys

20090242926 - Package for optical semiconductor element: A package for an optical semiconductor element is provided. The package includes: a stem body having a sealing hole therein; and a lead pin having a glass sealing portion which is sealed with sealing glass in the sealing hole. Characteristic impedance of the glass sealing portion is adjusted to a... Agent: Drinker Biddle & Reath (dc)

20090242927 - Semiconductor light emitting module and method for manufacturing the same: A light emitting module includes a semiconductor light source, a first lead with a bonding pad to which the light source is attached, and a second lead spaced from the first lead in a first direction contained in the plane of the first die bonding pad. The second lead includes... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20090242925 - Semiconductor light-emitting element and process for production thereof: The present invention provides a semiconductor light-emitting element comprising an electrode part excellent in ohmic contact and capable of emitting light from the whole surface. An electrode layer placed on the light-extraction side comprises a metal part and plural openings. The metal part is so continuous that any pair of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090242928 - Resin sheet for encapsulating optical semiconductor element and optical semiconductor device: The present invention provides a resin sheet for encapsulating an optical semiconductor element, the resin sheet containing an encapsulation resin layer, an adhesive resin layer, a metal layer and a protective resin layer, in which the encapsulation resin layer and the metal layer adhered onto the adhesive resin layer are... Agent: Sughrue-265550

20090242929 - Light emitting diodes with patterned current blocking metal contact: A light emitting diode including an epitaxial layer structure, a first electrode formed on the epitaxial layer structure, and a second electrode formed on the epitaxial layer structure. The first electrode has a pattern and the second electrode has a portion aligned with the pattern of the first electrode. The... Agent: Arent Fox LLP

20090242930 - Semiconductor device: A lateral high-breakdown voltage semiconductor device is provided in which the breakdown voltages of elements as a whole are improved, while suppressing increases in cell area. A track-shape gate electrode surrounds a collector electrode extending in a straight line, a track-shape emitter electrode surrounds the gate electrode, and a track-shape... Agent: Rossi, Kimms & Mcdowell LLP.

20090242931 - Semiconductor device having igbt and diode: A semiconductor device includes: a substrate; an active element cell area including IGBT cell region and a diode cell region; a first semiconductor region on a first side of the substrate in the active element cell area; a second semiconductor region on a second side of the substrate in the... Agent: Posz Law Group, PLC

20090242932 - Large-area pin diode with reduced capacitance: The invention provides a design of PIN diode having a low capacitance and a large area of effective collection of photo-generated charge. The low capacitance is obtained by replacing a continuous collector layer in the diode by a sparse array of collector disks interconnected by narrow metallic runners at a... Agent: Silber & Fridman

20090242934 - Photodiode and method of fabrication: The present invention provides a highly reliable photodiode, as well as a simple method of fabricating such a photodiode. During fabrication of the photodiode, a grading layer is epitaxially grown on a top surface of an absorption layer, and a blocking layer, for inhibiting current flow, is epitaxially grown on... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20090242933 - Semiconductor photodiode and method of manufacture thereof: A method of manufacture of an avalanche photodiode involving a step of making a recess in a top window layer of an avalanche photodiode layer stack, such that a wall surrounding the recess runs smoothly and gradually from the level of the recess to the level of the window layer.... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20090242935 - Monolithically integrated photodetectors: Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant... Agent: Wolf Greenfield & Sacks, P.C.

20090242936 - Strained ultra-thin soi transistor formed by replacement gate: A semiconductor structure is described. The structure includes a transistor formed in a semiconductor substrate, the semiconductor substrate having a semiconductor-on-insulator (SOI) layer; a channel associated with the transistor and formed on a first portion of the SOI layer; and a source/drain region associated with the transistor and formed in... Agent: International Business Machines Corporation Dept. 18g

20090242937 - Semiconductor device and manufacturing method: A semiconductor device has source and drain electrodes formed on a substrate, a gate insulation film formed on the substrate between the source and drain electrodes, and a gate electrode formed on the gate insulation film. These elements are all covered by a dielectric sub-insulation film. An opening is formed... Agent: Rabin & Berdo, PC

20090242938 - Field effect transistor: A field effect transistor formed of a semiconductor of a III group nitride compound, includes an electron running layer formed on a substrate and formed of GaN; an electron supplying layer formed on the electron running layer and formed of AlxGal-xN (0.01≦x≦0.4), the electron supplying layer having a band gap... Agent: Kubotera & Associates, LLC

20090242939 - Wafer for backside illumination type solid imaging device, production method thereof and backside illumination solid imaging device: A wafer for backside illumination type solid imaging device has a plurality of pixels inclusive of a photoelectric conversion device and a charge transfer transistor at its front surface side and a light receiving surface at its back surface side, wherein said wafer is a SOI wafer obtained by forming... Agent: Sughrue Mion, PLLC

20090242940 - Sensor device and fabrication method for the same: The sensor device includes: a converter body made of silicon in the shape of a rhombus in plan, the converter body having an opening in the shape of a hexagon in plan; a substrate for holding the converter body; a movable film formed on the opening; a converter electrode formed... Agent: Mcdermott Will & Emery LLP

20090242942 - Asymmetric source and drain field effect structure and method: A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor structure using a semiconductor substrate that includes a horizontal plateau... Agent: Scully, Scott, Murphy & Presser, P.C.

20090242941 - Structure and method for manufacturing device with a v-shape channel nmosfet: A CMOS structure includes a v-shape surface in an nMOSFET region. The v-shape surface has an orientation in a (100) plane and extends into a Si layer in the nMOSFET region. The nMOSFET gate dielectric layer is a high-k material, such as Hf02. The nMOSFET has a metal gate layer,... Agent: International Business Machines Corporation Dept. 18g

20090242943 - Semiconductor device: A semiconductor device which can prevent peeling off of a gate electrode is provided. The semiconductor device has GaN buffer layer formed on substrate 11, undoped AlGaN layer 13 formed on this buffer layer 12, drain electrode 16 and source electrode 17 formed separately on undoped AlGaN layer 13, which... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242944 - Method of forming a semiconductor device using stress memorization: A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film... Agent: Freescale Semiconductor, Inc. Law Department

20090242946 - Semiconductor device and fabrication method for the semiconductor device: A semiconductor device which could strengthen the mechanical strength of the protective film and with which packaging of the wafer level with electric high reliability is performed and a fabrication method for the semiconductor device are provided. The semiconductor device includes a semiconductor substrate; a field effect transistor including a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242947 - Semiconductor device and fabrication method for the semiconductor device: A semiconductor device and a fabrication method for the semiconductor device which can remove the sacrifice layer deposited on the semiconductor device surface in a short time and whose manufacturing yield can be improved are provided. The semiconductor device and the fabrication method for the semiconductor device includes a field... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242945 - Semiconductor device and method of fabricating the same: In a method of fabricating a semiconductor device on a substrate having a pillar pattern, a gate electrode is formed on the pillar pattern without etching the latter. A conductive pattern is filled between adjacent pillar patterns, a spacer is formed above the conductive pattern and surrounding sidewalls of each... Agent: Lowe Hauptman Ham & Berner, LLP

20090242948 - Method of forming an inverted lens in a semiconductor structure: A flat-top convex-bottom lower lens is formed by first applying a positive tone photoresist over a silicon oxide layer and an optional metallic barrier layer thereupon in a back-end-of-line (BEOL) metallization structure. The positive tone photoresist is exposed under defocused illumination conditions and/or employing a half-tone mask so that a... Agent: Scully, Scott, Murphy & Presser, P.C.

20090242950 - Active pixel sensor having two wafers: A vertically-integrated image sensor includes a sensor wafer connected to a support circuit wafer. Each pixel region on the sensor wafer includes a photodetector, a charge-to-voltage conversion mechanism, a transfer mechanism for transferring charge from the photodetector to the charge-to-voltage conversion mechanism, and a reset mechanism for discharging the charge-to-voltage... Agent: F-p Patent Legal Staff

20090242949 - Cmos image sensor with reduced dark current: A carbon-containing semiconductor layer is formed on exposed surfaces of a p-doped semiconductor layer abutting sidewalls of a shallow trench. Following formation of a dielectric layer on the carbon-containing semiconductor layer, a surface pinning layer having a p-type doping is formed underneath the carbon-containing semiconductor layer. A shallow trench isolation... Agent: Scully, Scott, Murphy & Presser, P.C.

20090242951 - Solid-state image pickup device: A solid-state image pickup device has a photoelectric conversion element that converts light incident from a first surface of a substrate into a signal charge and accumulates the signal charge, a transistor that is formed on a second surface side opposite to the first surface of the substrate and reads... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242952 - Integrated circuit including a capacitor and method: An integrated circuit including a capacitor and a method of fabricating an integrated circuit. The capacitor has a first electrode. A plurality of conductive lines is separated from each other and is configured to be held at a potential being the same for all conductive lines. A second electrode encloses... Agent: Dicke, Billig & Czaja

20090242954 - Memory device and fabrication thereof: The invention is related to a memory device, including a substrate, a capacitor which is substantially C-shaped in a cross section parallel to the substrate surface and a word line coupling the capacitor. In an embodiment, the C-shaped capacitor is a deep trench capacitor, and in alternative embodiment, the C-shaped... Agent: Quintero Law Office, PC

20090242953 - Shallow trench capacitor compatible with high-k / metal gate: Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second... Agent: International Business Machines Corporation Dept. 18g

20090242955 - Integrated circuit, memory device and methods of manufacturing the same: An integrated circuit includes: a contact structure with a first stack of at least two conductive layers, and a gate electrode with a second stack of conductive layers, the second stack of layers having the same sequence of conductive layers as the first stack.... Agent: Edell, Shapiro & Finnan, LLC

20090242957 - Atomic layer deposition processes for non-volatile memory devices: Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090242956 - Tunnel dielectrics for semiconductor devices: Tunnel dielectrics for semiconductor devices are generally described. In one example, an apparatus includes a semiconductor substrate, a first tunnel dielectric having a first bandgap coupled to the semiconductor substrate, a second tunnel dielectric having a second bandgap coupled to the first tunnel dielectric, and a third tunnel dielectric having... Agent: Cool Patent, P.C. C/o Cpa Global

20090242959 - Flash memory cell: A flash memory cell is disclosed in the specification and drawing. The flash memory cell is described and shown with at least one floating gate heavily doped with P-type ions.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090242958 - Nand-type nonvolatile semiconductor memory device: a first control gate electrode, and a first source/drain region. The select transistor includes a third insulating film on the semiconductor substrate, a fourth insulating film made of an aluminum oxide containing at least one of a tetravalent cationic element, a pentavalent cationic element, and N (nitrogen), a second control... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242960 - Semiconductor memory device and manufacturing method thereof: A semiconductor memory device includes a semiconductor substrate, a memory cell provided on the semiconductor substrate and having a stacked gate structure formed by sequentially stacking a tunnel insulation film, a charge storage layer, a block insulation film, and a control gate electrode, a first transistor having a first gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242965 - Memory cell device having vertical channel and double gate structure: A memory cell device having a vertical channel and a double gate structure is provided. More specifically, a memory cell device having a vertical channel and a double gate structure is characterized by having a pillar active region with a predetermined height, which is including a first semiconductor layer forming... Agent: Casella & Hespos

20090242964 - Non-volatile memory device: A finFET-based non-volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a portion of the fin body and... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090242967 - Non-volatile semiconductor storage device and method of manufacturing the same: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge accumulation layer formed around the first columnar... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242968 - Nonvolatile semiconductor memory device and method for manufacturing same: In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242962 - Plasma oxidation of a memory layer to form a blocking layer in non-volatile charge trap memory devices: A blocking layer of a non-volatile charge trap memory device is formed by oxidizing a portion of a charge trapping layer of the memory device. In one embodiment, the blocking layer is grown by a radical oxidation process at temperature below 500° C. In accordance with one implementation, the radical... Agent: Cypress Semiconductor Corporation

20090242961 - Recessed channel select gate for a memory device: A memory device comprising one or more recessed channel select gates and at least one charge trapping layer.... Agent: Cool Patent, P.C. C/o Cpa Global

20090242963 - Semiconductor device and method for manufacturing a semiconductor device: In a semiconductor device, the side walls are made of SiO2, SiN or SiON, and the top insulating film or gate insulating film is made of an oxide including Al, Si, and metal element M so that the number ratio Si/M is set to no less than a number ratio... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242969 - Semiconductor storage device and method of manufacturing the same: A semiconductor storage device including a semiconductor substrate including an upper surface having a plurality of trenches formed into the upper surface; a plurality of element isolation insulating films filled in each of the trenches so as to protrude upward from the upper surface of the semiconductor substrate, the element... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242966 - Vertical-type semiconductor devices: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall... Agent: Mills & Onello LLP

20090242970 - Semiconductor device, capacitor, and field effect transistor: It is made possible to provide a semiconductor device that has the effective work function of the connected metal optimized at the interface between a semiconductor and the metal. A semiconductor device includes: a semiconductor film; an oxide film formed on the semiconductor film, the oxide film including at least... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242971 - Semiconductor device and method of fabricating the same: In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between... Agent: Lowe Hauptman Ham & Berner, LLP

20090242972 - Vertical channel transistor in semiconductor device and method of fabricating the same: A method of fabricating a vertical channel transistor for a semiconductor device includes forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof; forming a first insulation layer over the active pillars to fill a gap region between... Agent: Lowe Hauptman Ham & Berner, LLP

20090242976 - Semiconductor device: The semiconductor device of the present invention includes a first conductive type semiconductor layer; a second conductive type source region formed in a surface layer portion of the semiconductor layer; a groove formed by digging in the source region from a surface thereof; an insulating film laminated on the semiconductor... Agent: Rabin & Berdo, PC

20090242977 - Semiconductor device and dc-dc converter: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor region provided in the semiconductor substrate; a first trench formed in the semiconductor region; a second trench formed in the semiconductor substrate; a trench gate electrode provided in the first trench; and a trench source electrode... Agent: Patterson & Sheridan, L.L.P.

20090242974 - Semiconductor device and method for fabricating the same: A semiconductor device includes a plurality of trench patterns formed over a substrate; gate insulation layers formed over sidewalls of the trench patterns; gate electrodes formed over the trench patterns; line patterns coupling the gate electrodes; and source and drain regions formed in upper and lower portions of the substrate... Agent: Lowe Hauptman Ham & Berner, LLP

20090242973 - Source and body contact structure for trench-dmos devices using polysilicon: A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall... Agent: Joshua D. Isenberg Jdi Patent

20090242978 - Termination structure for power devices: A semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. The termination region includes a first silicon region of a first conductivity type extending to a first... Agent: Townsend And Townsend And Crew, LLP

20090242975 - Vertical pillar transistor: A vertical pillar transistor may include a plurality of lower pillars, a plurality of upper pillars, a first insulation part, a second insulation part and a word line. The plurality of lower pillars protrudes substantially perpendicular to a substrate and is defined by a plurality of trenches. The plurality of... Agent: Harness, Dickey & Pierce, P.L.C

20090242980 - Semiconductor device including capacitor element and method of manufacturing the same: In a semiconductor device, a memory region and a logic region are provided on one silicon substrate. A trench is provided in the silicon substrate in the memory region, a memory cell transistor is provided in the memory region and a logic transistor is provided in the logic region. The... Agent: Mcginn Intellectual Property Law Group, PLLC

20090242979 - Vertical transistor of semiconductor device and method of forming the same: A vertical transistor of a semiconductor device has a channel area formed in a vertical direction to a semiconductor substrate. After semiconductor poles corresponding to the length of semiconductor channels and gate electrodes surrounding sidewalls of the semiconductor poles are formed, subsequent processes of forming silicon patterns corresponding to junction... Agent: Marshall, Gerstein & Borun LLP

20090242981 - Semiconductor device: A semiconductor device includes: an epitaxial layer; a body layer, formed in the epitaxial layer, which includes a channel region; a source layer disposed in superposition on the body layer; a gate insulator, formed on the epitaxial layer, which is in a ring shape surrounding the source layer; a gate... Agent: Ditthavong Mori & Steiner, P.C.

20090242982 - Self-aligned complementary ldmos: The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown... Agent: Hiscock & Barclay, LLP

20090242983 - Semiconductor device having a field effect transistor using a high dielectric constant gate insulating film and manufacturing method of the same: In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating... Agent: Mcdermott Will & Emery LLP

20090242984 - Semiconductor device and method of manufacturing the same: Aimed at providing a semiconductor device capable preventing transistor characteristics from departing from design characteristics, the semiconductor device of the present invention has a gate insulating film and a gate electrode positioned over a channel forming region; two second-conductivity-type, high-concentration impurity diffused layers which function as the source and drain... Agent: Mcginn Intellectual Property Law Group, PLLC

20090242987 - Double-gate semiconductor devices having gates with different work functions and methods of manufacture thereof: A double-gate FinFET and methods for its manufacture are provided. The FinFET includes first and second gates (72, 74) adjacent respective sides of the fin (20), with at least a portion of the first gate facing the fin being formed of polycrystalline silicon, and at least a portion of the... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090242988 - High frequency semiconductor circuit device: A high frequency semiconductor circuit device in which a microwave circuit can be miniaturized is provided, which includes a GaAs substrate; a plurality of FETs formed on the GaAs substrate; and a microstrip line formed on the GaAs substrate and electrically connecting FETs each other, wherein a thickness of a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242985 - Method, structure and design structure for customizing history effects of soi circuits: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed between a gate electrode and an outer portion of an active region of a FET. Also provided is a structure having a high-leakage dielectric formed... Agent: Andrew M. Calderon Greenblum & Bernstein, P.L.C

20090242986 - Multi-gate field effect transistor and method for manufacturing the same: A multi-gate field effect transistor includes: a plurality of semiconductor layers arranged in parallel on a substrate; source and drain regions formed in each of the semiconductor layers; channel regions each provided between the source region and the drain region in each of the semiconductor layers; protection films each provided... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242989 - Complementary metal-oxide-semiconductor device with embedded stressor: In one embodiment, the invention is a complementary metal-oxide-semiconductor device with an embedded stressor. One embodiment of a field effect transistor includes a silicon on insulator channel, a gate electrode coupled to the silicon on insulator channel, and a stressor embedded in the silicon on insulator channel and spaced laterally... Agent: Wall & Tong, LLP IBM Corporation

20090242990 - Semiconductor device and manufacturing method of same: A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242991 - Semiconductor device: Aimed at reducing the area of a protective circuit in a semiconductor device provided therewith, a semiconductor device of the present invention has a first-conductivity-type well, a plurality of first diffusion layers formed in the well, a plurality of second diffusion layers formed in the well, and a diffusion resistance... Agent: Mcginn Intellectual Property Law Group, PLLC

20090242993 - Esd protection device and manufacturing method thereof: A junction forming region is formed between a drain region of a MOS structure and a device isolation region which surrounds the MOS structure and is in contact with the drain region, to form a PN junction together with the drain region. As a consequence, it is possible to adjust... Agent: Rabin & Berdo, PC

20090242992 - Inverter, logic circuit including an inverter and methods of fabricating the same: An inverter, a logic circuit including the inverter and method of fabricating the same are provided. The inverter includes a load transistor of a depletion mode, and a driving transistor of an enhancement mode, which is connected to the load transistor. The load transistor may have a first oxide layer... Agent: Harness, Dickey & Pierce, P.L.C

20090242994 - Hybrid transistor based power gating switch circuit and method: A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth.... Agent: Freescale Semiconductor, Inc. Law Department

20090242995 - Semiconductor device and method for fabricating the same: A semiconductor device includes an isolation region (11a) formed in a semiconductor substrate (10), an active region made of the semiconductor substrate (10) surrounded by the isolation region (11a) and having a trench portion, a MIS transistor of a first-conductivity type having a gate electrode (13) formed on the active... Agent: Mcdermott Will & Emery LLP

20090242996 - Soi transistor with floating body for information storage having asymmetric drain/source regions: By laterally asymmetrically defining the well dopant concentration in a floating body storage transistor, an increased well dopant concentration may be provided at the drain side, while a moderately low concentration may remain in the rest of the floating body region. Consequently, compared to conventional symmetric designs, a reduction in... Agent: Williams, Morgan & Amerson

20090242997 - Method for fabricating semiconductor structure and structure of static random access memory: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates... Agent: J C Patents, Inc.

20090242998 - Penetrating implant for forming a semiconductor device: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090242999 - Method for encapsulating a high-k gate stack by forming a liner at two different process temperatures: Encapsulation of a gate stack comprising a high-k dielectric material may be accomplished on the basis of a silicon nitride material that is deposited in a sequence of two deposition processes, in which the first process may be performed on the basis of a moderately low process temperature, thereby passivating... Agent: Williams, Morgan & Amerson

20090243000 - Method, structure and design structure for customizing history effects of soi circuits: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has... Agent: Andrew M. Calderon, Greenblum & Bernstein, P. L. C.

20090243001 - Sequential deposition and anneal of a dielectic layer in a charge trapping memory device: Deposition and anneal operations are iterated to break a deposition into a number of sequential deposition-anneal operations to reach a desired annealed dielectric layer thickness. In one particular embodiment, a two step anneal is performed including an NH3 or ND3 ambient followed by an N2O or NO ambient. In one... Agent: Cypress Semiconductor Corporation

20090243002 - Semiconductor device and method of fabricating the same: A semiconductor device according to one embodiment includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate via a gate insulating film; a first silicide layer formed on the gate electrode; a channel region formed in the semiconductor substrate below the gate electrode; source/drain regions formed in regions... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090243003 - Manufacturing method of a gas sensor integrated on a semiconductor substrate: A method manufactures a gas sensor integrated on a semiconductor substrate. The method includes: realizing a first plurality of openings in the semiconductor substrate; realizing a crystalline silicon membrane suspended on the semiconductor substrate, forming an insulating cavity buried in the substrate; realizing a second plurality of openings in the... Agent: Seed Intellectual Property Law Group PLLC

20090243006 - Electronic part with affixed mems: According to an aspect of the invention, an electronic part includes a substrate having a first planar surface, a first bump affixed to the first planar surface of the substrate, a second bump affixed to the first planar surface of the substrate a predetermined distance from the first bump, a... Agent: Arent Fox LLP

20090243004 - Integrated structure for mems device and semiconductor device and method of fabricating the same: The present invention relates to an integrated structure for a MEMS device and a semiconductor device and a method of fabricating the same, in which an etch stopping device is included on a substrate between the MEMS device and the semiconductor device for protecting the semiconductor device from lateral damage... Agent: North America Intellectual Property Corporation

20090243005 - Semiconductor physical quantity sensor and method for manufacturing the same: A method for manufacturing a semiconductor physical quantity sensor having a fixed portion, a movable portion and an output terminal includes: forming a metal layer on a semiconductor layer; forming a resist on the metal layer; forming an opening and a side etching hole in the resist; anisotropically etching the... Agent: Posz Law Group, PLC

20090243008 - Magnetoresistive element and magnetic memory: m

20090243007 - Spin-dependent tunnelling cell and method of formation thereof: A Spin-Dependent Tunnelling cell comprises a first barrier layer of a first material and a second barrier layer of a second material sandwiched between a first ferromagnetic layer and a second ferromagnetic layer. The first and second barrier layers are formed to a combined thicknesses so that a Tunnelling Magnetoresistance... Agent: Freescale Semiconductor, Inc. Law Department

20090243009 - Magnetic tunnel junction cell including multiple vertical magnetic domains: Magnetic tunnel junction cell including multiple vertical domains. In an embodiment, a magnetic tunnel junction (MTJ) structure is disclosed. The MTJ structure includes an MTJ cell. The MTJ cell includes multiple vertical side walls. Each of the multiple vertical side walls defines a unique vertical magnetic domain. Each of the... Agent: Qualcomm Incorporated

20090243010 - Thinfilm deposition method, thinfilm deposition apparatus, and thinfilm semiconductor device: A substrate holding unit, a plasma treatment chamber, and a nanoparticle supplying chamber are housed in a single chamber. The substrate holding unit holds a substrate. The plasma treatment chamber includes a gas passage for introducing a source gas to a vicinity of the substrate and a plasma generating unit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090243012 - Electromagnetic interference shield structures for semiconductor components: A microelectronic device assembly with an integrated conductive shield is disclosed herein. The microelectronic device assembly includes a semiconductor substrate, an integrated circuit carried by the semiconductor substrate, a dielectric encapsulant encasing at least a portion of the semiconductor substrate. The microelectronic device assembly also includes a conductive shield in... Agent: Perkins Coie LLP Patent-sea

20090243014 - Image sensor: Disclosed is an image sensor. The image sensor includes a substrate having photodiodes therein; a dielectric layer on the substrate; a passivation layer on the dielectric layer exposing the dielectric layer in a region corresponding to a first color filter; and a color filter layer on the exposed dielectric layer... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090243011 - Manufacturing optical mems with thin-film anti-reflective layers: In accordance with the teachings of one embodiment of the present disclosure, a method for manufacturing a semiconductor device includes forming a support structure outwardly from a substrate. The support structure has a first thickness and a first outer sidewall surface that is not parallel with the substrate. The first... Agent: Texas Instruments Incorporated

20090243013 - Semiconductor photoreceptor device: A semiconductor light detecting device includes an n-contact layer selectively disposed on an Fe—InP substrate. An optical waveguide layer is disposed on the n-contact layer and includes an n-cladding layer, a light absorption layer, and a p-cladding layer, laminated on one another over the n-contact layer, in that order. An... Agent: Leydig Voit & Mayer, Ltd

20090243015 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device, includes the steps of: forming a resin layer on an upper surface of a substrate including a photodiode such that the resin layer does not cover a light receiving region of the photodiode; forming at least one groove in the resin layer so... Agent: Sonnenschein Nath & Rosenthal LLP

20090243017 - Method of manufacturing solid state imaging device, solid state imaging device, and camera using solid state imaging device: A method of manufacturing a solid state imaging device having a photo-electric conversion portion array and a transfer electrode array, these arrays being provided in parallel to each other, upper surfaces and side wall surfaces of the transfer electrode array being covered with a light-shielding layer, and a transparent layer... Agent: Robert J. Depke Lewis T. Steadman

20090243016 - Semiconductor device: An apparatus is provided. The apparatus generally comprises a photoreceptive region and a circuit region formed in a substrate. A multilayer wiring region is then formed on the substrate over at least a portion of the circuit region. The multilayer wiring region includes a wiring layer and a light-blocking layer.... Agent: Texas Instruments Incorporated

20090243018 - Hybrid inorganic-organic polymer compositions for anti-reflective coatings: An organic-inorganic composition, which has a backbone containing —Si—O— units with chromophore groups attached directly to at least a part of the silicon atoms. The film forming composition and resulting coating properties can be tailored to suit the specific exposure wavelength and device fabrication and design requirements. By using two... Agent: Mccormick, Paulding & Huber LLP

20090243019 - Optical sensing device including visible and uv sensors: An optical sensing device includes a silicon-on-insulator (SOI) substrate a semiconductor support substrate, an insulating layer located on the semiconductor support substrate, and a semiconductor layer located on the insulating layer. The optical sensing device further includes a visible light sensor located in the semiconductor support substrate, and an ultraviolet... Agent: Volentine & Whitt PLLC

20090243020 - Producing layered structures with layers that transport charge carriers: Layered structures such as photosensing arrays include layers in which charge carriers can be transported. For example, a carrier-transporting substructure that includes a solution processing artifact can transport charge carriers that flow to or from it through charge-flow surface parts that are on electrically conductive regions of a circuitry substructure;... Agent: Leading Edge Law Group, PLC/xerox-parc

20090243021 - Isolation structures for preventing photons and carriers from reaching active areas and methods of formation: Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 μm into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching... Agent: Dickstein Shapiro LLP

20090243022 - Method of forming mask for lithography, method of forming mask data for lithography, method of manufacturing back-illuminated solid-state imaging device, back-illuminated solid-state imaging device and electronic device: A method of forming a mask for lithography includes the step of forming the mask by using reverse data in which positions of at least part of output terminals are reversed, when forming the mask for lithography used for manufacturing a back-illuminated solid-state imaging device which takes incident light from... Agent: Sonnenschein Nath & Rosenthal LLP

20090243023 - Dual seed semiconductor photodetectors: Dual seed semiconductor photodetectors and methods to fabricate thereof are described. A dual seed semiconductor photodetector is formed directly on an insulating layer on a substrate. The dual seed semiconductor photodetector includes an optical layer formed on a dual seed semiconductor layer. The dual seed semiconductor layer includes a seed... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090243024 - Wiring board and solid-state imaging device: Provided are a wiring board capable of mounting either a frontside incident type solid-state imaging element and a backside incident type solid-state imaging element and a solid-state imaging device. The wiring board 1 is a wiring board having a to-be-arranged region 1a at which the solid-state imaging element is arranged,... Agent: Drinker Biddle & Reath (dc)

20090243025 - Pixel structure with a photodetector having an extended depletion depth: An image sensor includes an imaging area that includes a plurality of pixels that are formed in a substrate layer of a first conductivity type. Each pixel includes a collection region that is formed in a portion of the substrate layer and doped with a dopant of a first conductivity... Agent: F-p, Patent Legal Staff Eastman Kodak Company

20090243026 - Schottky barrier diode and method for using the same: An intermediate metal film is formed between a Schottky electrode and a pad electrode. A Schottky barrier height between the intermediate metal film and a silicon carbide epitaxial film is equivalent to or higher than a Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film. By... Agent: The Webb Law Firm, P.C.

20090243027 - semiconductor integrated circuit device and a method of manufacturing the same: To achieve a further reduction in the size of a finished product by reducing the number of externally embedded parts, the embedding of a Schottky barrier diode which is relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. In such a case, it... Agent: Miles & Stockbridge PC

20090243028 - Capacitive isolation circuitry with improved common mode detector: An integrated circuit having voltage isolation capabilities comprising a first galvanically isolated area of the integrated circuit containing a first group of functional circuitry for processing a data stream. The first group of functional circuitry located in a substrate of the integrated circuit. Capacitive isolation circuitry located in conductive layers... Agent: Howison & Arnott, L.l.p

20090243030 - Method of forming shallow trench isolation structure: A method of fabricating an isolation structure and the structure thereof is provided. The method is compatible with the embedded memory process and provides the isolation structure with a poly cap thereon to protect the top corners of the isolation structure, without using an extra photomask.... Agent: J C Patents, Inc.

20090243029 - Method, structure and design structure for customizing history effects of soi circuits: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric formed in a divot on each side of a segmented FET comprised of active silicon islands and gate electrodes thereon, and a... Agent: Greenblum & Bernstein, P.L.C

20090243031 - Structure and method to control oxidation in high-k gate structures: In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region;... Agent: Scully, Scott, Murphy & Presser, P.C.

20090243032 - Electrical fuse structure: An e-fuse structure includes a cathode block; a plurality of cathode contact plugs on the cathode block; an anode block; a plurality of anode contact plugs on the cathode block; and a fuse link connecting the cathode block with the anode block, wherein a front row of the cathode contact... Agent: North America Intellectual Property Corporation

20090243033 - Fuse part in semiconductor device and method for forming the same: A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of... Agent: Lowe Hauptman Ham & Berner, LLP

20090243034 - Semiconductor device: A semiconductor device including a doped substrate of a first doping polarity and a doped semiconductor material of a second doping polarity. The semiconductor material is on, or in, the substrate, and the second doping polarity is opposite the first doping polarity such that the semiconductor material and the substrate... Agent: Thompson Hine L.L.P. Intellectual Property Group

20090243035 - Semiconductor device and method of manufacturing the same and semiconductor device mounting structure: In a semiconductor device that is formed by joining two semiconductor elements together to oppose device layers to each other, inductor patterns for transmitting and receiving a signal and feeding a power and bumps for connecting electrically the semiconductor elements and for supporting the inductor patterns and the semiconductor elements... Agent: Drinker Biddle & Reath (dc)

20090243038 - Method of manufacturing semiconductor device and semiconductor device: A method of manufacturing a semiconductor device has forming a capacitor having electrodes and a ferroelectric film provided therebetween above a substrate, forming a pad electrode electrically connected to one of the electrodes of the capacitor above the substrate, forming a protective film covering the pad electrode over the substrate,... Agent: Fujitsu Patent Center C/o Cpa Global

20090243039 - Mim capacitor and method for manufacturing the same: Disclosed are an MIM (Metal-Insulator-Metal) capacitor and a method of manufacturing the same. The MIM capacitor includes: a lower metal layer and a lower metal interconnection on a substrate; a barrier metal layer on the lower metal layer; an insulating layer on the barrier metal layer; an upper metal layer... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090243037 - Semiconductor device having capacitors fixed to support patterns and method for manufacturing the same: A semiconductor device containing a cylindrical shaped capacitor and a method for manufacturing the same is presented. The semiconductor device includes a plurality of storage nodes and a support pattern. The plurality of storage nodes is formed over a semiconductor substrate. The support pattern is fixed to adjacent storage nodes... Agent: Ladas & Parry LLP

20090243036 - Semiconductor devices and methods of manufacture thereof: Capacitor plates, capacitors, semiconductor devices, and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes at least one via and at least one conductive member coupled to the at least one via. The at least one conductive member comprises an enlarged region proximate the at least... Agent: Slater & Matsil LLP

20090243040 - Micro-heater arrays and pn-junction devices having micro-heater arrays, and methods for fabricating the same: Example embodiments include micro-heater arrays including first and second micro-heaters disposed perpendicular to or parallel with each other on a substrate and methods of fabricating pn junctions between first and second heating portions using the heat generated from the first and second heating portions, respectively, when applying a voltage to... Agent: Harness, Dickey & Pierce, P.L.C

20090243041 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion thereof. A trench is disposed in the workpiece extending at least through the buried layer. At least one sinker contact is disposed in... Agent: Slater & Matsil LLP

20090243042 - Lateral semiconductor device: A semiconductor device has a first main electrode and a second main electrode that are provided on a semiconductor layer. The semiconductor layer has: an n type first semiconductor region in contact with the first main electrode; a p type second semiconductor region in contact with the second main electrode;... Agent: Kenyon & Kenyon LLP

20090243043 - Growth method using nanostructure compliant layers and hvpe for producing high quality compound semiconductor materials: A method utilizes HVPE to grow high quality flat and thick compound semiconductors (15) onto foreign substrates (10) using nanostructure compliant layers. Nanostructures (12) of semiconductor materials car be grown on foreign substrates (10) by molecular beam epitaxy (MBE), chemical vapour deposition (CVD), metalorganic chemical vapour deposition (MOCVD) and hydride... Agent: Christie, Parker & Hale, LLP

20090243044 - Semiconductor wafer, semiconductor device, and method of manufacturing semiconductor device: Provided is a semiconductor wafer with a scribe line region and a plurality of element forming regions partitioned by the scribe line region, the semiconductor wafer including: conductive patterns formed in the scribe line region; and an island-shaped passivation film formed above at least a conductive pattern, which is or... Agent: Mcginn Intellectual Property Law Group, PLLC

20090243046 - Pulse-laser bonding method for through-silicon-via based stacking of electronic components: There is described a method of forming a through-silicon-via to form an interconnect between two stacked semiconductor components using pulsed laser energy. A hole is formed in each component, and each hole is filled with a plug formed of a first metal. One component is then stacked on another component... Agent: Wells St. John P.s.

20090243047 - Semiconductor device with an interconnect element and method for manufacture: A semiconductor device is provided configured to be electrically connected to another device by through silicon interconnect technology. The semiconductor device includes a semiconductor substrate with at least one through hole. A through silicon conductor extends inside the through hole from the upper side to the bottom side of the... Agent: Slater & Matsil, L.L.P.

20090243045 - Through hole vias at saw streets including protrusions or recesses for interconnection: A semiconductor package includes a semiconductor die having a contact pad formed over a top surface of the semiconductor die. The semiconductor die may include an optical device. In one embodiment, a second semiconductor die is deposited over the semiconductor die. The package includes an insulating material deposited around a... Agent: Robert D. Atkins

20090243048 - Metallic nanocrystal encapsulation: A method of forming a device includes forming protective shells about metallic nanocrystals supported by a substrate. The metallic nanocrystals having protective shells are encapsulated with a layer formed with process parameters that are not compatible with the integrity of unprotected metallic nanocrystals.... Agent: Schwegman, Lundberg & Woessner, P.A.

20090243049 - Double deposition of a stress-inducing layer in an interlayer dielectric with intermediate stress relaxation in a semiconductor device: Enhanced efficiency of a stress relaxation implantation process may be achieved by depositing a first layer of reduced thickness and relaxing the same at certain device regions, thereby obtaining an enhanced amount of substantially relaxed dielectric material in close proximity to the transistor under consideration, wherein a desired high amount... Agent: Williams, Morgan & Amerson

20090243050 - Isolation structure in memory device and method for fabricating the same: A method for fabricating an isolation structure in a memory device includes forming a first trench in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. The method also includes oxidating the surface of the first and second trenches to... Agent: Marshall, Gerstein & Borun LLP

20090243052 - Electronic device with shielding structure and method of manufacturing the same: An electronic device includes a substrate, an active circuit, and a shielding structure. The active circuit is formed on the substrate. The shielding structure is disposed surrounding the active circuit, and includes a first heavy ion-doped region, first metal stack, second heavy ion-doped region, second metal stack and top metal.... Agent: Bacon & Thomas, PLLC

20090243051 - Integrated conductive shield for microelectronic device assemblies and associated methods: Microelectronic device assemblies having integrated conductive shields are disclosed herein. The microelectronic device assemblies include a semiconductor substrate having a bond site and a solder ball electrically connected to the bond site, a dielectric sidewall at least partially encapsulating the semiconductor substrate, and a conductive shield in direct contact with... Agent: Perkins Coie LLP Patent-sea

20090243053 - Structure for reduction of soft error rates in integrated circuits: A structure for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level;... Agent: Schmeiser, Olsen & Watts

20090243054 - I/o connection scheme for qfn leadframe and package structures: Methods, systems, and apparatuses for integrated circuit packages and lead frames are provided. A quad flat no-lead (QFN) package includes a plurality of peripherally positioned pins, a die-attach paddle, an integrated circuit die, and an encapsulating material. The die-attach paddle is positioned within a periphery formed by the pins. The... Agent: Fiala & Weaver, P.l.l.c. C/o Cpa Global

20090243055 - Leadframe, semiconductor packaging structure and manufacturing method thereof: A semiconductor packaging structure includes a plurality of first inner leads, a plurality of second inner leads, a plurality of first outer leads, a plurality of stacked chips, an encapsulating body, and a plurality of wires. Wherein, a first protrusion portion is protruded from each of the first inner leads... Agent: Rosenberg, Klein & Lee

20090243056 - Chip package having asymmetric molding: A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave... Agent: J C Patents, Inc.

20090243058 - Lead frame and package of semiconductor device: A lead frame including a shield plate, a main frame, interconnection arms, support arms, and terminals is sealed with a resin mold including a base portion for embedding the shield plate and a peripheral wall for embedding the interconnection arms and support arms, thus forming a package base. The interconnection... Agent: Pillsbury Winthrop Shaw Pittman LLP

20090243057 - Semiconductor chip package assembly method and apparatus for countering leadfinger deformation: The invention provides semiconductor chip packages, tools, and methods for preventing and for correcting leadfinger deformation caused during wirebonding in semiconductor chip package manufacturing. Disclosed are improved heat blocks and methods for their use in ensuring adequate clearance between leadfingers and adjacent heat spreaders, as well as semiconductor chip package... Agent: Texas Instruments Incorporated

20090243059 - Semiconductor package structure: A semiconductor package structure includes a carrier having a plurality of leads, wherein each of the leads is composed of an inner lead and an outer lead; a chip arranged on the bottom surface of the inner leads; an electrical connecting structure and a molding component. The invention discloses that... Agent: Rosenberg, Klein & Lee

20090243061 - Complex semiconductor packages and methods of fabricating the same: Disclosed are complex semiconductor packages, each including a large power module package which includes a small semiconductor package, and methods of manufacturing the complex semiconductor packages. An exemplary complex semiconductor package includes a first package including: a first packaging substrate; a plurality of first semiconductor chips disposed on the first... Agent: Townsend And Townsend And Crew, LLP

20090243060 - Lead frame and package of semiconductor device: A lead frame including a stage and a plurality of terminals is embedded in a mold resin including a base portion for mounting a semiconductor chip (e.g. a microphone chip), a peripheral wall disposed in the periphery of the base portion, and an extension portion extended outside of the peripheral... Agent: Pillsbury Winthrop Shaw Pittman LLP

20090243062 - Ic tag and manufacturing method of the same: An IC tag comprises a substrate on which a wiring pattern is formed, an IC chip which is bonded and mounted to the substrate by bringing a bump into press-contact with the wiring pattern, a repulsive member that is arranged on the surface opposite to the surface of the substrate... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090243063 - Packaging method of micro electro mechanical system device and package thereof: Disclosed are a micro electro mechanical system (MEMS) device and a package thereof. The packaging method of a MEMS device comprises: sequentially forming a sacrificial layer, a support layer, and a block copolymer layer on a substrate on which the MEMS device is formed; self-assembling the block copolymer layer formed... Agent: The Belles Group, P.C.

20090243064 - Method and apparatus for a package having multiple stacked die: A method of manufacturing a semiconductor package involves providing a substrate having a window. The substrate may include a leadframe having half-etched leads. First and second semiconductor devices are mounted to a top surface of the substrate on either side of the window using an adhesive. A third semiconductor device... Agent: Robert D. Atkins

20090243076 - Electronic system modules and method of fabrication: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths of 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is used to fabricate the interconnection circuits. A polymer... Agent: Townsend And Townsend And Crew, LLP

20090243068 - Integrated circuit package system with non-symmetrical support structures: An integrated circuit package system including: providing a substrate with a wire-bonded die mounted thereover; mounting a first support structure and a second support structure of different size above the substrate; mounting a structure above the first support structure and the second support structure; and encapsulating the wire-bonded die, the... Agent: Law Offices Of Mikio Ishimaru

20090243069 - Integrated circuit package system with redistribution: An integrated circuit package system comprising: forming a base package having a molded top; providing a surface contact on the base package; and patterning a redistribution layer on the molded top for coupling the surface contact.... Agent: Law Offices Of Mikio Ishimaru

20090243071 - Integrated circuit package system with stacking module: An integrated circuit package system comprising: providing a module lead array; attaching a module integrated circuit adjacent the module lead array; attaching a module substrate over the module integrated circuit; and applying a module encapsulant over the module integrated circuit wherein the module lead array and the module substrate are... Agent: Law Offices Of Mikio Ishimaru

20090243070 - Integrated circuit package system with support structure under wire-in-film adhesive: An integrated circuit package in package system including: providing a substrate; mounting a wire bonded die with an active side over the substrate; connecting the active side to the substrate with bond wires; mounting a structure over the wire bonded die having a wire-in-film adhesive between the structure and the... Agent: Law Offices Of Mikio Ishimaru

20090243066 - Mountable integrated circuit package system with exposed external interconnects: The present invention provides a mountable integrated circuit package system comprising: providing an inner integrated circuit package including a first external interconnect having a shoulder; connecting an intraconnect between a second external interconnect and the shoulder; and forming an outer encapsulation over the inner integrated circuit package, the intraconnect, and... Agent: Law Offices Of Mikio Ishimaru

20090243067 - Mountable integrated circuit package system with substrate: A mountable integrated circuit package system includes: providing a substrate having an opening provided therein; providing an encapsulated integrated circuit package having an external leadfinger; mounting the encapsulated integrated circuit package by the external leadfinger proximate to the opening in the substrate; and connecting the external leadfinger and the substrate.... Agent: Law Offices Of Mikio Ishimaru

20090243075 - Mounting structure of semiconductor device and electronic apparatus using same: A mounting structure comprises: at least one semiconductor device having solder bumps as outer terminals and a flexible wiring board with wiring formed thereon. The semiconductor device is structured to be wrapped by the flexible wiring board, the mounting structure is provided with outer electrodes on both sides of the... Agent: Sughrue Mion, PLLC

20090243065 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device (100) comprises a first resin substrate (101) on which a first semiconductor chip (125) is mounted a surface thereof; a second resin substrate (111) on which a second semiconductor chip (131) is mounted on a surface thereof; and a resin base material (109), joined to a front... Agent: Smith, Gambrell & Russell

20090243074 - Semiconductor through silicon vias of variable size and method of formation: A through-silicon via structure is formed by providing a substrate having a first conductive catch pad and a second conductive catch pad formed thereon. The substrate is secured to a wafer carrier. A first etch of a first type is performed on the substrate underlying each of the first and... Agent: Freescale Semiconductor, Inc. Law Department

20090243072 - Stacked integrated circuit package system: A stacked integrated circuit package system includes: providing a base integrated circuit package, and mounting a top integrated circuit package having a top interposer and a top encapsulation with a cavity therein or the cavity as a space between top intra-stack interconnects and the top interposer, with the top interposer... Agent: Law Offices Of Mikio Ishimaru

20090243073 - Stacked integrated circuit package system: A stacked integrated circuit package system includes: providing a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity; mounting an intermediate integrated circuit package over the base interposer, and mounting a top integrated circuit package over the intermediate integrated... Agent: Law Offices Of Mikio Ishimaru

20090243077 - Integrated circuit package system with rigid locking lead: An integrated circuit package system includes: providing a protective layer having an opening; forming a conductive layer over the protective layer and filling the opening; patterning a rigid locking lead, having both a lead locking portion and a lead exposed portion, from the conductive layer; connecting an integrated circuit and... Agent: Law Offices Of Mikio Ishimaru

20090243078 - Power device packages having thermal electric modules using peltier effect and methods of fabricating the same: Provided are power device packages, which include thermal electric modules using the Peltier effect and thus can improve operational reliability by rapidly dissipating heat generated during operation to the outside, and methods of fabricating the same. An exemplary power device package includes: a thermal electric module having a first surface... Agent: Townsend And Townsend And Crew, LLP

20090243079 - Semiconductor device package: Provided is a semiconductor device package including a substrate formed of a silicon (Si)-based material. The semiconductor device package includes a first substrate which comprises first and second principal planes which are opposite each other, and a substrate body layer disposed between the first and second principal planes, the substrate... Agent: Townsend And Townsend And Crew, LLP

20090243080 - Flip chip interconnection structure with bump on partial pad and method thereof: A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed... Agent: Robert D. Atkins

20090243081 - System and method of forming a wafer scale package: A system and method for forming a wafer level package (WLP) (i.e., wafer level chip size package) is disclosed. The WLP includes a silicon integrated circuit (IC) substrate having a plurality of die pads formed on a top surface thereof and a plurality of polymer laminates positioned thereon. Each of... Agent: Ge Trading & Licensing

20090243082 - Integrated circuit package system with planar interconnect: An integrated circuit package system includes: mounting an integrated circuit die adjacent to a lead; forming a first encapsulation around and exposing the integrated circuit die and the lead; and forming a planar interconnect between the integrated circuit die and the lead with the planar interconnect on the first encapsulation.... Agent: Law Offices Of Mikio Ishimaru

20090243083 - Wafer integrated with permanent carrier and method therefor: A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first... Agent: Robert D. Atkins

20090243084 - Suspension microstructure and a fabrication method for the same: A suspension microstructure and its fabrication method, in which the method comprises the steps of: forming at least one insulation layer with inner micro-electro-mechanical structures on an upper surface of a silicon substrate, the micro-electro-mechanical structure includes at least one microstructure and a plurality of metal circuits that are independent... Agent: Dr. Banger Shia

20090243085 - Apparatus and method for attaching a heat dissipating device: A microelectronic package is provided. The microelectronic package includes a heat dissipating device having a top side and a bottom side and a thermal interface material disposed adjacent to the bottom side of the heat dissipating device. The microelectronic package also includes a patterned metal layer comprising at least two... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090243086 - Enhanced thermal dissipation ball grid array package: In a semiconductor chip, a thermal adhesive is used to bond an internal heat spreader to an active functional die. In an alternative embodiment a dummy die is place directly on top of the active functional die and a thermal adhesive is used to bond an internal heat spreader to... Agent: Conexant Systems, Inc

20090243087 - Semiconductor device and method for manufacturing same: In a DC-DC converter, a multilayer wiring layer is provided on a silicon substrate, and a control circuit configured to control an input circuit and an output circuit is formed in the silicon substrate and the multilayer wiring layer. Moreover, a sealing resin layer covering the multilayer wiring layer and... Agent: Patterson & Sheridan, L.L.P.

20090243089 - Module including a rough solder joint: A module includes a metallized substrate including a metal layer, a base plate, and a joint joining the metal layer to the base plate. The joint includes solder contacting the base plate and an inter-metallic zone contacting the metal layer and the solder. The inter-metallic zone has spikes up to... Agent: Dicke, Billig & Czaja

20090243088 - Multiple layer metal integrated circuits and method for fabricating same: A method of fabricating a plurality of layers of metal on a substrate depositing a first layer of metal on the substrate; depositing a first layer of planarization material over the substrate and first layer of metal to a depth above the top of the first layer of metal; polishing... Agent: Christopher P. Maiorana, P.C.

20090243093 - Contact structure and connecting structure: A contact structure disposed on a substrate is provided. The contact structure includes at least one pad, at least one polymer bump and at least one conductive layer. The pad is disposed on the substrate and the polymer bump is disposed on the substrate. The polymer bump has a curved... Agent: Jianq Chyun Intellectual Property Office

20090243090 - Mock bump system for flip chip integrated circuits: A mock bump system includes providing a flip chip integrated circuit having an edge and forming a mock bump near the edge.... Agent: Law Offices Of Mikio Ishimaru

20090243091 - Mock bump system for flip chip integrated circuits: A mock bump system includes: providing a first structure having an edge; and forming a mock bump near the edge.... Agent: Law Offices Of Mikio Ishimaru

20090243096 - Semiconductor device and fabrication method thereof: A semiconductor device and a method of manufacturing the same are disclosed. The method is carried out by forming solder pads on a substrate by wet etching, flipping a semiconductor chip having a plurality of connection bumps formed on an active surface of the semiconductor chip for the connection bumps... Agent: Edwards Angell Palmer & Dodge LLP

20090243092 - Semiconductor device and manufacturing method of semiconductor device: A semiconductor device includes a semiconductor element; a plate member disposed opposite to an electronic-circuit forming portion of the semiconductor element; and an elastic body arranged in a compressed state between the semiconductor element and the plate member, wherein the elastic body includes at least one first protruding portion at... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090243094 - Semiconductor device and manufacturing method thereof: The semiconductor device comprises a first area and a second area positioned adjacent to the outside of the first area, the semiconductor substrate having a main surface and side surfaces and disposed in such a manner that the main surface is positioned in the first area and each of the... Agent: Rabin & Berdo, PC

20090243097 - Semiconductor device having low dielectric constant film and manufacturing method thereof: A low dielectric constant film/wiring line stack structure made up of a stack of low dielectric constant films and wiring lines is provided in a region on the upper surface of the semiconductor substrate except for the peripheral part of this surface. The peripheral side surface of the low dielectric... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090243095 - Substrate, manufacturing method thereof, method for manufacturing semiconductor device: A substrate on which an IC element is fixed includes: a plurality of metal posts arranged in a plurality of columns in a lengthwise direction and in a plurality of rows in a crosswise direction when viewed in a plan view, the plurality of metal posts having first faces and... Agent: Oliff & Berridge, PLC

20090243100 - Methods to form a three-dimensionally curved pad in a substrate and integrated circuits incorporating such a substrate: Methods to form a three-dimensionally curved pad in a substrate and integrated circuits incorporating such a substrate are disclosed. An example method to form a three-dimensionally curved pad comprises isotropically etching a portion of a surface of a substrate to form a recess having a radial shape, forming a conductive... Agent: Texas Instruments Incorporated

20090243098 - Underbump metallurgy for enhanced electromigration resistance: A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer is formed on the metallic adhesion promotion layer,... Agent: Scully, Scott, Murphy & Presser, P.C.

20090243099 - Window type bga semiconductor package and its substrate: A window-type BGA semiconductor package is revealed, primarily comprising a substrate with a wire-bonding slot, a chip disposed on a top surface of the substrate, and a plurality of bonding wires passing through the wire-bonding slot. A plurality of plating line stubs are formed on a bottom surface of the... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090243101 - Method for forming interconnection levels of an integrated circuit: A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level comprising conductive tracks and vias separated by a porous dielectric material; (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings above portions of... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20090243102 - Method of aligning deposited nanotubes onto an etched feature using a spacer: A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched... Agent: Wilmerhale/boston

20090243103 - Synthesis of zeolite crystals and formation of carbon nanostructures in patterned structures: A method is provided for incorporating zeolite crystals in patterned structures, the zeolite crystals having pores (channels) with an orientation which is defined by the topology of the zeolite crystal type and the geometry of the patterned structure, resulting in pores parallel with the length axis of the patterned structures.... Agent: Knobbe Martens Olson & Bear LLP

20090243104 - Forming thick metal interconnect structures for integrated circuits: Embodiments of an apparatus and methods for forming thick metal interconnect structures for integrated structures are generally described herein. Other embodiments may be described and claimed.... Agent: Intel Corporation C/o Cpa Global

20090243106 - Structures and methods to enhance copper metallization: Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. The insulator includes a polymer or an insulating oxide compound. And, the inhibiting... Agent: Schwegman, Lundberg & Woessner/micron

20090243105 - Wire bonding on reactive metal surfaces of a metallization of a semiconductor device by providing a protective layer: In semiconductor devices having a copper-based metallization system, bond pads for wire bonding may be formed directly on copper surfaces, which may be covered by an appropriately designed protection layer to avoid unpredictable copper corrosion during the wire bond process. A thickness of the protection layer may be selected such... Agent: Williams, Morgan & Amerson

20090243107 - Novel approach to high temperature wafer processing: At temperatures near, and above, 385° C., gold can diffuse into silicon and into some contact materials. Gold, however, is an excellent material because it is corrosion resistant, electrically conductive, and highly reliable. Using an adhesion layer and removing gold from the contact area above and around a contact allows... Agent: Honeywell International Inc. Patent Services

20090243108 - Control of localized air gap formation in an interconnect stack: The present invention relates to a method for fabricating an interconnect stack of an integrated-circuit device. Air gaps are fabricated in the interconnect stack on one or more interconnect levels. The method comprises forming local etch vias (216, 218) between a lower etch-barrier layer (236) and an upper etch-barrier layer... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090243109 - Metal cap layer of increased electrode potential for copper-based metal regions in semiconductor devices: A conductive cap material for a copper region may be provided with enhanced etch resistivity by taking into consideration the standard electrode potential of one or more of the species contained therein. For example, instead of a conventionally used CoWP alloy, a modified alloy may be used, by substituting the... Agent: Williams, Morgan & Amerson

20090243110 - Voltage controlled oscillator: A semiconductor device includes a semiconductor substrate having an element region on a surface thereof, an active element being formed in the element region. An insulating layer is formed on the semiconductor substrate and covers the active element. An inductor is formed on the insulating layer and overlaps with the... Agent: Mcginn Intellectual Property Law Group, PLLC

20090243112 - Copper interconnection structure, semiconductor device, and method for forming copper interconnection structure: A copper interconnection structure includes an insulating layer, an interconnection and a barrier layer. The insulating layer includes silicon (element symbol: Si), carbon (element symbol: C), hydrogen (element symbol: H) and oxygen (element symbol: O). The interconnection is located on the insulating layer, and the interconnection includes copper (element symbol:... Agent: Masuvalley & Partners

20090243111 - Semiconductor substrate, electrode forming method, and solar cell fabricating method: The present invention is directed to a semiconductor substrate having an electrode formed thereon, the electrode including at least silver and glass frit, the electrode including: a multi-layered structure constituted of a first electrode layer joined directly to the semiconductor substrate, and an upper electrode layer formed of at least... Agent: Oliff & Berridge, PLC

20090243113 - Semiconductor structure: A fusible link between metallization layers of a semiconductor device comprises a tungsten plug deposited in a via interconnecting two aluminum metallization layers.... Agent: Knobbe Martens Olson & Bear LLP

20090243114 - densely packed metal segments patterned in a semiconductor die: A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the... Agent: Michael Farjami, Esq. Farjami & Farjami LLP

20090243117 - Contact structure, a semiconductor device employing the same, and methods of manufacturing the same: A contact structure that includes a first pattern formed on a substrate, wherein the first pattern has a recessed region in an upper surface thereof, a planarized buffer pattern formed on the first pattern, and a conductive pattern formed on the planarized buffer pattern.... Agent: F. Chau & Associates, LLC

20090243116 - Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics: By forming a protection layer prior to the application of the planarization layer during a dual damascene strategy for first patterning vias and then trenches, enhanced etch fidelity may be accomplished. In other aspects disclosed herein, via openings and trenches may be patterned in separate steps, which may be accomplished... Agent: Williams, Morgan & Amerson

20090243118 - Semiconductor device and manufacturing method of the same: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film... Agent: Miles & Stockbridge PC

20090243115 - Semiconductor device and method of manufacturing the same: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a memory array on a first substrate; and a peripheral circuit on a second substrate, wherein the first substrate and the second substrate may be attached to each other so that the memory array... Agent: Harness, Dickey & Pierce, P.L.C

20090243120 - Semiconductor element and semiconductor element fabrication method: A semiconductor element is provided that includes a semiconductor substrate, a circuit element disposed on the substrate, and a through-hole formed in the substrate having a stripe-like concavo-convex structure on its sidewall with stripes formed in the direction of the thickness of the semiconductor substrate.... Agent: Ratnerprestia

20090243119 - Semiconductor integrated circuit: Power wiring comprises a first-layer power wiring cluster in which VDD wiring trace and VSS wiring trace of different potentials at single trace width are arranged alternatingly; a second-layer power wiring cluster, disposed in a layer overlying the first-layer power wiring cluster, in which a VDD wiring trace and a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090243121 - Semiconductor integrated circuit and layout method for the same: A semi conductor integrated circuit includes a first via-contact configured to connect a first interconnection pattern provided for a first interconnection layer and a second interconnection pattern provided for a second interconnection layer, and a second via-contact configured to connect a third interconnection pattern provided for the first interconnection layer... Agent: Young & Thompson

20090243122 - Alignment mark for opaque layer: An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact... Agent: Texas Instruments Incorporated

20090243123 - Increasing exposure tool alignment signal strength for a ferroelectric capacitor layer: An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in... Agent: Texas Instruments Incorporated