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Active solid-state devices (e.g., transistors, solid-state diodes) October categorized by USPTO classification 10/09

20090256127 - Compounds for depositing tellurium-containing films: Disclosed herein are tellurium metal-organic precursors and methods for depositing tellurium-containing films on a substrate.... Agent: Air Liquide Intellectual Property

20090256128 - Nonvolatile data storage, semicoductor memory device including nonvolatile data storage and method of forming the same: A data storage and a semiconductor memory device including the same are provided, the data storage including a lower electrode, a first discharge prevention layer stacked on the lower electrode, a phase-transition layer on the first discharge prevention layer, a second discharge prevention layer stacked on the phase-transition layer, and... Agent: Harness, Dickey & Pierce, P.L.C

20090256131 - Memory cell that employs a selectively fabricated carbon nano-tube reversible resistance-switching element formed over a bottom conductor and methods of forming the same: In some aspects, a method of fabricating a memory cell is provided that includes: (1) fabricating a first conductor above a substrate; (2) selectively fabricating a carbon nano-tube (“CNT”) material above the first conductor by: (a) fabricating a CNT seeding layer on the first conductor, wherein the CNT seeding layer... Agent: Dugan & Dugan, PC

20090256130 - Memory cell that employs a selectively fabricated carbon nano-tube reversible resistance-switching element, and methods of forming the same: In some aspects, a method of fabricating a memory cell is provided that includes fabricating a steering element above a substrate, and fabricating a reversible-resistance switching element coupled to the steering element by fabricating a carbon nano-tube (“CNT”) seeding layer by depositing a silicon-germanium layer above the substrate, patterning and... Agent: Dugan & Dugan, PC

20090256132 - Memory cell that includes a carbon-based memory element and methods of forming the same: In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more... Agent: Dugan & Dugan, PC

20090256129 - Sidewall structured switchable resistor cell: A method of making a memory device includes forming a first conductive electrode, forming an insulating structure over the first conductive electrode, forming a resistivity switching element on a sidewall of the insulating structure, forming a second conductive electrode over the resistivity switching element, and forming a steering element in... Agent: Sandisk Corporation C/o Foley & Lardner LLP

20090256133 - Multiple layer resistive memory: A resistive memory cell may be composed of four stacked layers. Each layer may be sandwiched by electrodes. Connections may be formed from each of four directions around the stack, for example, aligned with each of four edges where the resistive layers are rectangular.... Agent: Trop, Pruner & Hu, P.C.

20090256134 - Process for fabricating nanowire arrays: A process is provided for etching a silicon-containing substrate to form nanowire arrays. In this process, one deposits nanoparticles and a metal film onto the substrate in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not... Agent: Mintz, Levin, Cohn, Ferris, Glovsky And Popeo, P.c

20090256135 - Thermal electron emitter and thermal electron emission device using the same: A thermal electron emitter includes at least one carbon nanotube twisted wire and a plurality of electron emission particles mixed with the twisted wire. The carbon nanotube twisted wire comprises a plurality of carbon nanotubes. A work function of the electron emission particles is lower than the work function of... Agent: PCe Industry, Inc. Att. Steven Reiss

20090256136 - Microresonator systems and methods of fabricating the same: Various embodiments of the present invention are related to microresonator systems that can be used as a laser, a modulator, and a photodetector and to methods for fabricating the microresonator systems. In one embodiment, a microdisk comprises: a top layer; a bottom layer; an intermediate layer having at least one... Agent: Hewlett-packard Company Intellectual Property Administration

20090256140 - Light-detecting device structure: A light-detecting device structure comprises a substrate, a vertical organic light-emitting transistor and a light-detecting unit, wherein the vertical organic light-emitting transistor is disposed at a first location on the substrate, and the light-detecting unit is disposed at a second location on the substrate, in which the first and the... Agent: Juan Carlos A. Marquez C/o Stites & Harbison PLLC

20090256144 - Method for manufacturing organic transistor and organic transistor: A method of producing an organic transistor which can form directly an organic semiconductor layer in pattern by simple processes and can produce an organic transistor excellent in transistor characteristics. The method includes: forming a hydrophobic/hydrophilic pattern substrate, in which a hydrophobic/hydrophilic pattern substrate is formed by using a hydrophobic... Agent: Ladas & Parry LLP

20090256137 - N-type semiconductor materials in thin film transistors and electronic devices: A thin film transistor comprises a layer of organic semiconductor that comprises an N,N′-1,4,5,8-naphthalenetetracarboxylic acid diimide having at least one cycloalkyl group having a fluorinated substituent at its 4-position that adopts an equatorial orientation in the trans configuration of the cycloalkyl group and an axial orientation in the cis configuration... Agent: Eastman Kodak Company Patent Legal Staff

20090256143 - Oligothiophene-arylene derivatives and organic thin film transistors using the same: An oligothiophene-arylene derivative wherein an arylene having n-type semiconductor characteristics is introduced into an oligothiophene having p-type semiconductor characteristics, thereby simultaneously exhibiting both p-type and n-type semiconductor characteristics. Further, an organic thin film transistor using the oligothiophene-arylene derivative.... Agent: Buchanan, Ingersoll & Rooney PC

20090256141 - Organic photosensitive optoelectronic devices containing tetra-azaporphyrins: Embodiments of the present invention provide an organic photosensitive optoelectronic device comprising at least one tetra-azaporphyrin compound of formula (I) are disclosed herein.... Agent: Mcdermott Will & Emery LLP

20090256138 - Organic thin film transistor: b

20090256142 - Organic thin film transistor and method for manufacturing same: Disclosed are an organic thin film transistor exhibiting a high switching current value even when a distance (channel length) between source and the drain electrodes is large, and a manufacturing method thereof. The organic thin film transistor of the invention comprises a substrate, a gate electrode, a gate insulating layer,... Agent: Lucas & Mercanti, LLP

20090256145 - Organic thin film transistor and organic thin film light-emitting transistor: An organic thin film transistor including a substrate having thereon at least three terminals of a gate electrode, a source electrode and a drain electrode, an insulator layer and an organic semiconductor layer, with a current between a source and a drain being controlled upon application of a voltage to... Agent: Millen, White, Zelano & Branigan, P.C.

20090256139 - Thin-film transistors: A thin film transistor having a semiconducting layer with improved flexibility and/or mobility is disclosed. The semiconducting layer comprises a semiconducting polymer and insulating polymer. Methods for forming and using such thin-film transistors are also disclosed.... Agent: Fay Sharpe / Xerox - Rochester

20090256146 - Semiconductor substrate with solid phase epitaxial regrowth with reduced depth of doping profile and method of producing same: Method of producing a semiconductor device, comprising: a) providing a semiconductor substrate, b) providing an insulating layer on a top surface of the semiconductor substrate, c) making an amorphous layer in a top layer of said semiconductor substrate by a suitable implant, d) implanting a dopant into said semiconductor substrate... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090256147 - Thin film transistor and method of manufacturing the same: A thin film transistor, including a transparent channel pattern, a transparent gate insulating layer in contact with the channel pattern, a passivation film pattern disposed on the channel pattern, a source/drain coupled to the channel pattern through a via hole in the passivation film pattern, and a gate facing the... Agent: Lee & Morse, P.C.

20090256148 - Zinc oxide light emitting diode: Provided is a zinc oxide light emitting diode having improved optical characteristics. The zinc oxide light emitting diode includes an n-type semiconductor layer, a zinc oxide active layer formed on the n-type semiconductor layer, a p-type semiconductor layer formed on the active layer, an anode in electrical contact with the... Agent: Occhiuti Rohlicek & Tsao, LLP

20090256149 - Structure for measuring body pinch resistance of high density trench mosfet array: o

20090256150 - Thin film transistor array panel and method for manufacturing the same: A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate; a first signal line and a second signal line disposed on the substrate; a switching thin film transistor connected to the first signal line and the second signal line, and comprising a... Agent: Cantor Colburn, LLP

20090256151 - Display substrate and method of manufacturing the same: A display substrate comprises a substrate; a source electrode arranged on the substrate; a drain electrode arranged on the substrate and spaced from the source electrode; a semiconductor layer arranged on the source electrode and the drain electrode; an insulating layer arranged on the semiconductor layer; and a gate electrode... Agent: Haynes And Boone, LLPIPSection

20090256152 - Pixel structure for transflective lcd panel: A pixel structure for a transflective LCD having a transparent region and a reflective region is provided. The pixel structure includes a transparent substrate, a TFT, at least one reflective structure, a passivation layer, a pixel electrode and a reflective layer. The TFT is disposed in a reflective region of... Agent: J C Patents

20090256153 - Thin film transistor matrix device and method for fabricating the same: A method for fabricating a thin film transistor matrix device which includes forming a transparent insulating substrate, arranging a plurality of thin film transistors on the substrate in a matrix, arranging a plurality of picture element electrodes on the substrate in a matrix and connecting the picture element electrodes to... Agent: Greer, Burns & Crain

20090256154 - Flexible substrate, method of fabricating the same, and thin film transistor using the same: Ef representing Young's modulus of the buffer layer, vf representing Poisson's ratio of the buffer layer, αf representing a coefficient of thermal expansion of the buffer layer, and αs representing the predetermined coefficient of thermal expansion of the metal substrate.... Agent: Lee & Morse, P.C.

20090256158 - Array substrate of liquid crystal display device and method of manufacturing the same: An array substrate comprising a base substrate, a common electrode, a gate line, a data line, a thin film transistor, a passivation layer and a pixel electrode of “” shape. The thin film transistor comprises a gate electrode, an active layer, a source electrode and a drain electrode; the gate... Agent: Ladas & Parry LLP

20090256157 - Display device and manufacturing method of display device: A display device includes a first substrate on which a semiconductor circuit is formed. A second substrate is disposed over the first substrate to include a first electrode formed on a first surface to perform image displaying, and a second electrode exposed to a second surface and bonded to the... Agent: Cooper & Dunham, LLP

20090256156 - Hybrid imaging sensor with approximately equal potential photodiodes: A hybrid MOS or CMOS image sensor. The sensor includes photon-sensing elements comprised of an array of photo-sensing regions deposited in the form of separate islands on or in a substrate. Pixel circuitry is created on and/or in the substrate at or near the edge of or beneath the photon-sensing... Agent: Trex Enterprises Corp.

20090256155 - Thin film transistor array panel and method for manufacturing the same: A thin film transistor panel includes a substrate, a gate line extending in a first direction on the substrate, a data line disposed on the substrate, the data line crossing the gate line with an insulation layer therebetween and extending in a second direction, a thin film transistor including a... Agent: H.c. Park & Associates, PLC

20090256159 - Gan semiconductor device: This invention discloses a GaN semiconductor device comprising a substrate; a metal-rich nitride compound thin film on the substrate; a buffer layer formed on the metal-rich nitride compound thin film, and a semiconductor stack layer on the buffer layer wherein the metal-dominated nitride compound thin film covers a partial upper... Agent: Bacon & Thomas, PLLC

20090256162 - Method for producing semi-insulating resistivity in high purity silicon carbide crystals: A method is disclosed for producing high quality semi-insulating silicon carbide crystals in the absence of relevant amounts of deep level trapping elements. The invention includes the steps of heating a silicon carbide crystal having a first concentration of point defects to a temperature that thermodynamically increases the number of... Agent: Summa, Additon & Ashe, P.A.

20090256161 - Power conversion apparatus: In the case where a chip is made of wide band gap semiconductor, a power conversion apparatus is obtained in which a component having a low heat resistant temperature is prevented from receiving thermal damage by heat generated at the chip. In a configuration including: a chip portion (20) including... Agent: Birch Stewart Kolasch & Birch

20090256160 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device is provided. A gate structure is formed on a substrate. A first dopant implantation and a first strain atom implantation are performed. Thereafter, spacers are formed on sidewalls of the gate structure. A second dopant implantation and a second strain atom implantation are... Agent: Portal Ipr Office Chun-ming Shih

20090256164 - Active device array substrate and method for fabricating the same: An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090256163 - Leds using single crystalline phosphor and methods of fabricating same: Methods for fabricating LED chips from a wafer and devices fabricated using the methods with one method comprising depositing LED epitaxial layers on an LED growth wafer to form a plurality of LEDs on the growth wafer. A single crystalline phosphor is bonded over at least some the plurality of... Agent: Koppel, Patrick, Heybl & Dawson

20090256165 - Method of growing an active region in a semiconductor device using molecular beam epitaxy: A method of making an (Al, Ga, In)N semiconductor device having a substrate and an active region is provided. The method includes growing the active region using a combination of (i) plasma-assisted molecular beam epitaxy; and (ii) molecular beam epitaxy with a gas including nitrogen-containing molecules in which the nitrogen-containing... Agent: Mark D. Saralino ( Sharp ) Renner, Otto, Boisselle & Sklar, LLP

20090256169 - Deposition substrate and method for manufacturing light-emitting device: The deposition substrate of the present invention includes a light-transmitting substrate having a first region and a second region. In the first region, a first heat-insulating layer transmitting light is provided over the light-transmitting substrate, a light absorption layer is provided over the first heat-insulating layer, and a first organic... Agent: Cook Alex Ltd

20090256168 - Display element, manufacturing method of the same and display device: A display element including: a first electrode; an auxiliary wiring formed on the periphery of the first electrode in such a manner as to be insulated from the first electrode; an insulating portion having first and second openings, the first opening adapted to expose the first electrode, and the second... Agent: Sonnenschein Nath & Rosenthal LLP

20090256167 - Light-emitting device: A light-emitting device (1) is disclosed, which comprises a radiation source (2), an inorganic layer (3) comprising a luminescent material (4); and a scattering layer (5) comprising scattering particles (6). The scattering layer (5) is located between the radiation source (2) and the inorganic layer (3), which is composed of... Agent: Philips Intellectual Property And Standards

20090256166 - Semiconductor light-emitting device: A semiconductor light-emitting device 10 has a semiconductor chip 12 for emitting light having a wavelength in blue to ultraviolet regions, and a sealing portion 16 formed in at least a partial region on a passage path on which the light is passed. The sealing portion 16 includes a sealing... Agent: Mcdermott Will & Emery LLP

20090256170 - Semiconductor light emitting element and method for manufacturing same: A semiconductor light emitter (A) includes an n-type semiconductor layer (2), a p-type semiconductor layer (4), and an active layer (3) between these two layers (2, 4). The light emitter (A) further includes an n-side electrode (5) on the n-type layer (2) and a p-side electrode (6) on the p-type... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20090256171 - Resin composition for sealing light-emitting device and lamp: A resin composition for sealing a light-emitting device of the present invention includes a silsesquioxane resin including two or more oxetanyl groups, a cationic polymerization initiator and a metal oxide fine particle. Furthermore, a lamp of the present invention includes a package equipped with a sealing member, an electrode exposed... Agent: Sughrue Mion, PLLC

20090256172 - Method of laser annealing semiconductor layer and semiconductor devices produced thereby: A laser annealing method includes forming a nitrogen-doped layer on a semiconductor layer, the nitrogen-doped layer having a nitrogen concentration of at least 3×1020 atoms/cc, irradiating a first area of the nitrogen-doped layer in a low oxygen environment with a laser beam and irradiating a second area of the nitrogen-doped... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090256173 - Complementary field effect transistors having embedded silicon source and drain regions: A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of... Agent: International Business Machines Corporation Dept. 18g

20090256174 - Device structures for a high voltage junction field effect transistor manufactured using a hybrid orientation technology wafer and design structures for a high voltage integrated circuit: Device structures for a high voltage junction field effect transistor and design structures for a high voltage integrated circuit. The device structure is manufactured using a hybrid orientation technology wafer with a first semiconductor layer with a first crystalline orientation, a second semiconductor layer with a second crystalline orientation, and... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090256175 - Method of doping transistor comprising carbon nanotube, method of controlling position of doping ion, and transistors using the same: Provided are a method of doping a carbon nanotube (CNT) of a field effect transistor and a method of controlling the position of doping ions. The method may include providing a source, a drain, the CNT as a channel between the source and the drain, and a gate, applying a... Agent: Harness, Dickey & Pierce, P.L.C

20090256176 - Solid-state imaging apparatus: A solid-state imaging apparatus, controlling a potential on a semiconductor substrate for an electronic shutter operation, includes: a first semiconductor region of the first conductivity type for forming a photoelectric conversion region; a second semiconductor region of the first conductivity type, formed separately from the photoelectric conversion region, for accumulating... Agent: Fitzpatrick Cella Harper & Scinto

20090256177 - Semiconductor device including an ohmic layer: In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to... Agent: Harness, Dickey & Pierce, P.L.C

20090256178 - Semiconductor device having misfets and manufacturing method thereof: A semiconductor device includes a dielectric film and gate electrode that are stacked on a substrate, sidewalls formed to cover the side surfaces of the electrode and dielectric film, and SiGe films formed to sandwich the sidewalls, electrode and dielectric film, filled in portions separated from the sidewalls, having upper... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090256179 - Image sensor: Embodiments relate to and image sensor. In embodiments, the image sensor may include a semiconductor substrate, a photodiode region, a gate electrode, a dummy gate, and an interlayer dielectric layer. The semiconductor substrate includes a field oxide layer. The photodiode region may be formed on the semiconductor substrate. The gate... Agent: Sherr & Vaughn, PLLC

20090256181 - Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines: A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as... Agent: Knobbe Martens Olson & Bear LLP

20090256182 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device includes a memory cell portion and a peripheral circuit portion. The memory cell portion includes a pillar capacitor with a lower electrode, a dielectric film, and an upper electrode sequentially formed on a side surface of a first insulating portion which is parallel to a predetermined... Agent: Young & Thompson

20090256180 - Standard cell having compensation capacitance: A standard cell includes a capacity element which is made up of a first well diffusion layer into which a first conductive impurity is diffused in a region from a surface of a substrate to a predetermined depth, an insulation film which is provided on the first well diffusion layer,... Agent: Mcginn Intellectual Property Law Group, PLLC

20090256183 - Single gate nonvolatile memory cell with transistor and capacitor: A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090256184 - Single gate nonvolatile memory cell with transistor and capacitor: A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090256185 - Metallized conductive strap spacer for soi deep trench capacitor: A conductive strap spacer is formed within a buried strap cavity above an inner electrode recessed below a top surface of a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A portion of the conductive strap spacer is metallized by reacting with a metal to form a strap metal semiconductor... Agent: Scully, Scott, Murphy & Presser, P.C.

20090256187 - Semiconductor device having vertical pillar transistors and method for manufacturing the same: A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a single surface of lower portions of the silicon pillars, and drain areas of the vertical pillar transistors are connected with one another.... Agent: Ladas & Parry LLP

20090256186 - Split gate non-volatile memory cell: A non-volatile memory (NVM) cell comprising a layer of discrete charge storing elements, a control gate, and a select gate is provided. The control gate has a first sidewall with a lower portion being at least a first angle 10 degrees away from 90 degrees with respect to substrate. Further,... Agent: Freescale Semiconductor, Inc. Law Department

20090256188 - Method for manufacturing semiconductor device and the semiconductor device: A method for manufacturing a semiconductor device which includes: alternately supplying a silicon source and an oxidant to deposit a silicon oxide film on a surface of a semiconductor substrate, wherein the silicon source is supplied under a supply condition where an adsorption amount of molecules of the silicon source... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090256190 - Semiconductor device and manufacturing method thereof: According to an aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate; active areas with island-like shapes formed on the semiconductor substrate; an element isolation area surrounding the active areas and including an element isolation groove formed on the semiconductor substrate and an element... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090256189 - Two bit u-shaped memory structure and method of making the same: A memory structure includes: a substrate; a control gate positioned on the substrate; floating gates positioned at two sides of the control gate, wherein the floating gates have a U-shaped bottom embedded in the substrate; a first dielectric layer positioned between the control gate and the substrate; a second dielectric... Agent: North America Intellectual Property Corporation

20090256191 - Split gate non-volatile memory cell with improved endurance and method therefor: A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlying a first portion of the channel region.... Agent: Freescale Semiconductor, Inc. Law Department

20090256192 - Nonvolatile semiconductor memory device and method of manufacturing the same: In a nonvolatile semiconductor memory device where a tunnel insulating film, a charge storage layer, a blocking insulating film, and a control gate are stacked one on top of another on a semiconductor substrate, with an element isolation insulating film buried between adjacent cells, a barrier layer composed of at... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090256193 - Semiconductor device and a method of manufacturing the same: In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is... Agent: Miles & Stockbridge PC

20090256195 - Semiconductor device and method of manufacturing the same: A semiconductor device in which current flows in a vertical direction includes a structure that decreases resistance between a source electrode and a drain electrode along with a current path at a position different from a position having highest electric field intensity between the source electrode and the drain electrode.... Agent: Young & Thompson

20090256194 - Semiconductor device with reduced resistance of bit lines and method for manufacturing the same: A semiconductor device comprises buried bit lines which are formed to be brought into contact with drain areas of vertical pillar transistors. The buried bit lines are arranged along a first direction in a silicon substrate. The buried bit lines are formed of epi-silicon to reduce the resistance of the... Agent: Ladas & Parry LLP

20090256197 - Semiconductor device and manufacturing method thereof: Provided is a technology, in a semiconductor device having a power MISFET and a Schottky barrier diode on one semiconductor substrate, capable of suppressing a drastic increase in the on-resistance of the power MISFET while making the avalanche breakdown voltage of the Schottky barrier diode greater than that of the... Agent: Mattingly & Malur, P.C.

20090256198 - Semiconductor devices having line type active regions and methods of fabricating the same: In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line... Agent: Mills & Onello LLP

20090256196 - Three-dimensional semiconductor device structures and methods: A three-dimensional semiconductor device structure includes a first semiconductor device and a second semiconductor device bonded together using a patterned conductive layer according to an embodiment of the invention. The first semiconductor device includes a first plurality of terminals on its front side, and the second semiconductor device includes a... Agent: Townsend And Townsend And Crew, LLP

20090256199 - lateral metal oxide semiconductor drain extension design: A semiconductor device comprising source and drain regions and insulating region and a plate structure. The source and drain regions are on or in a semiconductor substrate. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a... Agent: Texas Instruments Incorporated

20090256200 - Disconnected dpw structures for improving on-state performance of mos devices: A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second HVW region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first HVW region; a gate dielectric extending... Agent: Slater & Matsil, L.L.P.

20090256201 - Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods: A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20090256202 - Semiconductor-on-insulator device structures with a body-to-substrate connection for enhanced electrostatic discharge protection, and design structures for such semiconductor-on-insulator device structures: Semiconductor-on-insulator device structures with enhanced electrostatic discharge protection, and design structures for an integrated circuit with device structures exhibiting enhanced electrostatic discharge protection. A device is formed in a body region of a device layer of a semiconductor-on-insulator substrate, which is bounded by an inner peripheral sidewall of an annular... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090256203 - Top gate thin film transistor with independent field control for off-current suppression: A bottom-contacted top gate (TG) thin film transistor (TFT) with independent field control for off-current suppression is provided, along with an associated fabrication method. The method provides a substrate, and forms source and drain regions overlying the substrate, each having a channel interface top surface. A channel is interposed between... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20090256205 - 2-t sram cell structure and method: The present invention, in one embodiment, provides a memory device including a substrate including at least one device region; a first field effect transistor having a first threshold voltage and a second field effect transistor having a second threshold voltage, the second field effect transistor including a second active region... Agent: Scully, Scott, Murphy & Presser, P.C.

20090256204 - Soi transistor with merged lateral bipolar transistor: A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned between the source region and the drain region. The source-side lateral... Agent: Carey, Rodriguez, Greenberg & Paul, LLP

20090256206 - P-channel germanium on insulator (goi) one transistor memory cell: According to one exemplary embodiment, a p-channel germanium on insulator (GOI) one transistor memory cell comprises a buried oxide (BOX) layer formed over a bulk substrate, and a gate formed over a gate dielectric layer situated over a germanium layer formed over the buried oxide (BOX) layer. A source region... Agent: Farjami & Farjami LLP

20090256207 - Finfet devices from bulk semiconductor and methods for manufacturing the same: Disclosed herein is a transistor comprising a first fin having a first gate electrode disposed across the first fin; the gate electrode contacting opposing surfaces of the fin; and a planar oxide layer having a second gate electrode disposed across the planar oxide layer to form a planar metal oxide... Agent: Cantor Colburn LLP - IBM Fishkill

20090256208 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device according to one embodiment includes: forming a fin and a film on a semiconductor substrate, the film being located at least either on the fin or under the fin and on the semiconductor substrate; forming a gate electrode so as to sandwich both... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090256209 - Gate structure of semiconductor device: A gate structure of a semiconductor device comprising a silicon substrate having a field oxide film, a plurality of gates formed by sequentially stacking a first gate dielectric film, a first gate conductive film, and a gate silicide film on the silicon substrate. a thermal oxide film formed on a... Agent: Marshall, Gerstein & Borun LLP

20090256210 - Semiconductor device and fabrication method of the semiconductor device: It includes: a source electrode (21) formed on a semiconductor layer (12); a drain electrode (23) formed on the semiconductor layer (12); a gate electrode (22) formed between the source electrode (21) and the drain electrode (23); an insulating film (24) formed on the semiconductor layer (12) and the gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090256211 - Metal gate compatible flash memory gate stack: A first gate stack comprising two stacked gate electrodes in a first device region, a second gate stack comprising a metal gate electrode in a second device region, and a third gate stack comprising a semiconductor gate electrode in a third device region are formed by forming and removing portions... Agent: Scully, Scott, Murphy & Presser, P.C.

20090256212 - Lateral drain-extended mosfet having channel along sidewall of drain extension dielectric: An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the... Agent: Texas Instruments Incorporated

20090256213 - Structure and method for manufacturing device with a v-shape channel nmosfet: A CMOS structure includes a v-shape surface in an nMOSFET region. The v-shape surface has an orientation in a (100) plane and extends into a Si layer in the nMOSFET region. The nMOSFET gate dielectric layer is a high-k material, such as Hf02. The nMOSFET has a metal gate layer,... Agent: International Business Machines Corporation Dept. 18g

20090256214 - Semiconductor device and associated methods: A semiconductor device and process of fabricating the same, the semiconductor device including a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a gate electrode having sidewalls, on the gate insulating layer, first spacers on the sidewalls of the gate electrode, a source/drain region in the semiconductor substrate,... Agent: Lee & Morse, P.C.

20090256215 - Gated metal oxide sensor: An apparatus for sensing an analyte gas is provided. The apparatus may include a signal amplifier that may include a thin film transistor that may include a semiconducting film that may include a metal oxide capable of chemical interaction with the analyte gas, such as carbon monoxide. The apparatus may... Agent: Fish & Richardson P.C.

20090256216 - Wafer level csp sensor: An electronics package has a wafer level chip scale package (WLCSP) die substrate containing electronic circuits. Through-silicon vias through the die substrate electrically connect the electronic circuits to the bottom surface of the die substrate. A package sensor is coupled to the die substrate for sensing an environmental parameter. A... Agent: Sunstein Kann Murphy & Timbers LLP

20090256217 - Carbon nanotube memory cells having flat bottom electrode contact surface: The present invention is directed to structures and methods of fabricating nanotube electromechanical memory cells having a bottom electrode with a substantially planar contact surface. The bottom electrode is configured so that during the operation of the memory cell the nanotube crossbar of the cell can make contact with a... Agent: Wilmerhale/boston

20090256218 - Mems device having a layer movable at asymmetric rates: A microelectromechanical (MEMS) device includes a substrate and a movable layer mechanically coupled to the substrate. The movable layer moves from a first position to a second position at a first rate and from the second position to the first position at a second rate faster than the first rate.... Agent: Knobbe, Martens, Olson & Bear, LLP

20090256219 - Method for manufacturing a semiconductor component, as well as a semiconductor component, in a particular a diaphragm sensor: A method for producing a micromechanical diaphragm sensor includes providing a semiconductor substrate having a first region, a diaphragm, and a cavity that is located at least partially below the diaphragm. Above at least one part of the first region, a second region is generated in or on the surface... Agent: Kenyon & Kenyon LLP

20090256220 - Low switching current mtj element for ultra-high stt-ram and a method for making the same: A STT-RAM MTJ that minimizes spin-transfer magnetization switching current (Jc) while achieving a high dR/R is disclosed. The MTJ has a MgO tunnel barrier formed by natural oxidation to achieve a low RA, and a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel layer to minimize Jc0. There is... Agent: Saile Ackerman LLC

20090256221 - Method for making very small isolated dots on substrates: A method for forming very small isolated dots of a target material, e.g., a ferromagnetic material or phase change material, on a substrate includes providing a substrate having a layer of the target material disposed on a surface thereof, etching the layer of target material so as to form a... Agent: Haynes And Boone, LLPIPSection

20090256224 - Integrated circuit comprising mirrors buried at different depths: A semiconductor structure including a first active area under which is buried a first reflective layer and a least one second active area under which is buried a second reflective layer, wherein the upper surface of the second reflective layer is closer to the upper surface of the structure than... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20090256227 - Method of fabricating back-illuminated imaging sensors using a bump bonding technique: A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate, and resulting imaging device is disclosed. The method for manufacturing the imaging device includes the steps of providing a substrate comprising an insulator layer, and an epitaxial layer substantially overlying the insulator layer; fabricating at least one... Agent: Patent Docket Administrator Lowenstein Sandler P.C.

20090256228 - Micro-lenses for cmos imagers and method for manufacturing micro-lenses: A micro-lens and a method for forming the micro-lens is provided. A micro-lens includes a substrate and lens material located within the substrate, the substrate having a recessed area serving as a mold for the lens material. The recessed can be shaped such that the lens material corrects for optical... Agent: Dickstein Shapiro LLP

20090256222 - Packaging method of image sensing device: A packaging method for an image sensing device is disclosed. The packaging method includes the steps of a) providing an annular dam on a substrate; b) mounting an image sensing module, having a light-receiving region exposed, inside the annular dam on the substrate; c) connecting the image sensing module and... Agent: Bacon & Thomas, PLLC

20090256223 - Photodiode array: A photodiode array 1 has a plurality of photodetector channels 10 which are formed on an n-type substrate 2 having an n-type semiconductor layer 12, with a light to be detected being incident to the plurality of photodetector channels 10. The photodiode array 1 comprises: a p−-type semiconductor layer 13... Agent: Drinker Biddle & Reath (dc)

20090256225 - Solid-state image capturing device, manufacturing method of the solid-state image capturing device, and electronic information device: A solid-state image capturing device according to the present invention includes: a photoelectrical conversion section formed in a semiconductor substrate or in a substrate area provided on a substrate; a first transparent film provided on the photoelectrical conversion section; and a lens provided at a position above the first transparent... Agent: Edwards Angell Palmer & Dodge LLP

20090256226 - Solid-state imaging device, production method thereof, and electronic device: Disclosed is a solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel... Agent: Sonnenschein Nath & Rosenthal LLP

20090256229 - Semiconductor package, method for manufacturing the same, semiconductor module, and electronic device: In a camera module (1) of the present invention, a lens member (20) is attached to a semiconductor package (10). The semiconductor package (10) includes: an image sensor (11) mounted on a wiring board (13); and a wire 15 through which the wiring board (13) is electrically connected to the... Agent: Edwards Angell Palmer & Dodge LLP

20090256230 - Photoelectric conversion apparatus and imaging system using the photoelectric conversion apparatus: In a photoelectric conversion apparatus including a charge holding portion, a part of an element isolation region contacting with a semiconductor region constituting the charge holding portion extends from a reference surface including the light receiving surface of a photoelectric conversion element into a semiconductor substrate at a level equal... Agent: Fitzpatrick Cella Harper & Scinto

20090256231 - Unipolar semiconductor photodetector with suppressed dark current and method for producing the same: A photo-detector with a reduced G-R noise comprises two n-type narrow bandgap layers surrounding a middle barrier layer having an energy bandgap at least equal to the sum of the bandgaps of the two narrow bandgap layers. Under the flat band conditions the conduction band edge of each narrow bandgap... Agent: Venable LLP

20090256232 - Semiconductor device and fabrication method for the same: The semiconductor device includes: memory cells each having a first multilayer electrode including a first lower electrode made of a first conductive film and a first upper electrode made of a second conductive film formed one on the other with a first interface film therebetween; and a diode having a... Agent: Mcdermott Will & Emery LLP

20090256233 - Isolation structure in memory device and method for fabricating the isolation structure: An isolation structure in a memory device and a method for fabricating the isolation structure. In the method, a first trench is formed in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. A liner layer comprising a silicon nitride... Agent: Marshall, Gerstein & Borun LLP

20090256234 - Semiconductor device and method for producing the same: A semiconductor device is configured that a high-withstand voltage semiconductor device and logic circuits are integrated on a single chip and that a high-withstand voltage high-potential island including the high-potential-side logic circuit is separated using multiple partition walls enclosing therearound. The semiconductor device is provided with a multi-trench separation region... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090256235 - Semiconductor device: A semiconductor device (200) includes: an electrical fuse (100) including: a lower layer interconnect (120) formed on a substrate; a via (130) provided on the lower layer interconnect (120) so as to be connected to the lower layer interconnect (120); and an upper layer interconnect (110) provided on the via... Agent: Mcginn Intellectual Property Law Group, PLLC

20090256236 - Mems-topped integrated circuit with a stress relief layer and method of forming the circuit: The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer and... Agent: Law Office Of Mark C. Pickering

20090256238 - Capacitor of semiconductor device and method of fabricating the same: Disclosed are a capacitor of a semiconductor device and a method of fabricating the same. The capacitor includes a capacitor top electrode, a capacitor bottom electrode aligned with a bottom surface and three lateral sides of the capacitor top electrode, and a capacitor insulating layer between the capacitor top electrode... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090256237 - Semiconductor device, manufacturing method thereof, and data processing system: A miniaturized semiconductor device is provided by reducing the design thickness of a wiring line protecting film covering the surface of a wiring layer, and reducing the distance between the wiring layer and via plugs formed by a self-aligning process. Dummy mask layers extending in the same layout pattern as... Agent: Young & Thompson

20090256239 - Capacitor, chip comprising the capacitor, and method for producing the capacitor: A capacitor is described which includes a substrate with a doped area of the substrate forming a first electrode of a first capacitor. A plurality of trenches is arranged in the doped area of the substrate, the plurality of trenches forming a second electrode of the capacitor. An electrically insulating... Agent: Slater & Matsil LLP

20090256240 - Method for producing group iii-nitride wafers and group iii-nitride wafers: The present invention discloses a production method for group III nitride ingots or pieces such as wafers. To solve the coloration problem in the wafers grown by the ammonothermal method, the present invention composed of the following steps; growth of group III nitride ingots by the ammonothermal method, slicing of... Agent: Morrison & Foerster LLP

20090256241 - Thin silicon wafer and method of manufacturing the same: A method of manufacturing a thin silicon wafer by slicing a silicon single crystal includes: a thinning step S3 of polishing a rear surface of the silicon wafer to reduce the thickness of the silicon wafer after a device structure is formed on a front surface of the silicon wafer;... Agent: Greenblum & Bernstein, P.L.C

20090256242 - Method of forming an electronic device including forming a charge storage element in a trench of a workpiece: A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the... Agent: Larson Newman & Abel, LLP

20090256243 - Low k interconnect dielectric using surface transformation: Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement of at least one void formed within the solid structure... Agent: Schwegman, Lundberg & Woessner/micron

20090256244 - Semiconductor device packages with electromagnetic interference shielding: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the... Agent: Cooley Godward Kronish LLP Attn: Patent Group

20090256246 - Semiconductor packaging techniques: A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20090256245 - Stacked micro-module packages, systems using the same, and methods of making the same: Semiconductor die packages, methods of making said packages, and systems using said packages are disclosed. An exemplary package comprising at least one semiconductor die disposed on one surface of a leadframe and electrically coupled to at least one conductive region of the leadframe, and at least one passive electrical component... Agent: Townsend And Townsend And Crew, LLP

20090256247 - Semiconductor device and method including first and second carriers: A semiconductor device and method. One embodiment provides an integral array of first carriers and an integral array of second carries connected to the integral array of first carriers. First semiconductor chips are arranged on the integral array of first carriers. The integral array of second carriers is arranged over... Agent: Dicke, Billig & Czaja

20090256248 - Configuration terminal for integrated devices and method for configuring an integrated device: A configuration terminal for integrated devices includes a first and a second portion structurally independent and connected to respective first and second terminals and it has at least one contact terminal suitable to be selectively connected to such first and second terminals. Also a method configures an integrated device that... Agent: Seed Intellectual Property Law Group PLLC

20090256249 - Stacked, interconnected semiconductor package: An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.... Agent: Vierra Magen/sandisk Corporation

20090256250 - Semiconductor device and programming method: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090256251 - Electronic device packages and methods of formation: Provided are electronic device packages and their methods of formation. The electronic device packages include an electronic device mounted on a substrate, a conductive via and a locally thinned region in the substrate. The invention finds application, for example, in the electronics industry for hermetic packages containing an electronic device... Agent: Jonathan D. Baskin Rohm And Haas Electronic Materials LLC

20090256252 - Semiconductor die packages with multiple integrated substrates, systems using the same, and methods using the same: An exemplary semiconductor die package is disclosed having one or more semiconductor dice disposed on a first substrate, one or more packaged electrical components disposed on a second substrate that is electrical coupled to the first substrate, and an electrically insulating material disposed over portions of the substrates. The first... Agent: Townsend And Townsend And Crew, LLP

20090256253 - Continuously referencing signals over multiple layers in laminate packages: A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the voltage reference. A reference plane adjustment engine analyzes a... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090256254 - Wafer level interconnection and method: A semiconductor assembly includes a semiconductor wafer including backside contact pads coupled to respective contact regions of different signal types and insulation separating the backside contact regions by signal type. The semiconductor assembly further includes metallization situated over at least a portion of the insulation and interconnecting the backside contact... Agent: General Electric Company Global Research

20090256255 - Composite interconnect: A composite interconnect system includes a plurality of carbon nanotubes, a plurality of solder balls and standoff balls disposed on a first device to provide a connection to a second device. A die-attached substrate includes a substrate and one or more die disposed on the substrate by a die-attach composite... Agent: Osha Liang L.L.P./sun

20090256256 - Electronic device and method of manufacturing same: This application relates to a semiconductor device comprising an array of contact elements soldered to only one surface, wherein the array defines a predetermined pitch length, wherein the contact elements comprise a spherically shaped element and wherein the contact elements protrude from the only one surface by more than 60... Agent: Infineon Technologies Ag Patent Department

20090256257 - Final via structures for bond pad-solder ball interconnections: A structure and a method for forming the same. The structure includes a first dielectric layer, an electrically conductive bond pad on the first dielectric layer, and a second dielectric layer on top of the first dielectric layer and the electrically conductive bond pad. The electrically conductive bond pad is... Agent: Schmeiser, Olsen & Watts

20090256258 - Semiconductor chip with integrated via: An integrated circuit with a substrate with a lower and an upper surface is described. A via extends between the upper and the lower surface of the substrate. The via contains a conductive filling material that comprises carbon.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090256259 - Semiconductor device and method for manufacturing the same: A semiconductor device has a first interlayer insulating film formed on a semiconductor substrate, a first plug and a second plug embedded in holes formed to open the first interlayer insulating film, a capacitor formed on the first interlayer insulating film so as to connect to the first plug, a... Agent: Knobbe Martens Olson & Bear LLP

20090256260 - Semiconductor device: A semiconductor device including a semiconductor element and a functional member fixed thereto with an adhesive film is provided, where the performance or reliability degradation due to moisture entered by way of the adhesive film itself or the interfaces between the adhesive film and members adjacent thereto can be suppressed... Agent: Griffin & Szipl, PC

20090256261 - Semiconductor device and manufacturing method thereof: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties... Agent: Miles & Stockbridge PC

20090256262 - Semiconductor devices including porous insulators: Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed therethrough. The voids may be defined by shells of microcapsules. The voids impart the dielectric materials with reduced dielectric constants and, thus, increased electrical insulation properties.... Agent: Trask Britt, P.C./ Micron Technology

20090256263 - Structure and method for hybrid tungsten copper metal contact: The present invention in one embodiment provides a method of forming an interconnect comprising, providing a interlevel dielectric layer atop a substrate, the interlevel dielectric layer including at least one tungsten (W) stud extending from an upper surface of the interlevel dielectric to the substrate; recessing an upper surface of... Agent: Scully, Scott, Murphy & Presser, P.C.

20090256264 - Semiconductor structure and method of making the same: A semiconductor device is provided. An amorphous silicon layer that acts as a UV blocking layer replaces a conventional silicon-rich oxide (SRO) layer or the super silicon-rich oxide (SSRO) layer. By doing this, the process window is increased. In addition, silicon nitride sidewall spacer is formed inside the contact hole... Agent: North America Intellectual Property Corporation

20090256265 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes a plurality of contact layers located between two lines running in parallel in a first direction. Each of the contact layers has a structure in which an upper contact and a lower contact are coupled together. The plurality of contact layers are arranged zigzag... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090256266 - Apparatus and method for a chip assembly including a frequency extending device: A chip assembly includes a chip, a paddle, an interface layer, a frequency extending device, and lands. The chip has contacts. The interface layer is disposed between the chip and the paddle. The frequency extending device has at least a conductive layer and a dielectric layer. The conductive layer has... Agent: Mcdermott Will & Emery LLP

20090256267 - Integrated circuit package-on-package system with central bond wires: An integrated circuit package-on-package system includes: providing a base substrate having a central opening; attaching a bottom die below the base substrate partially covering the central opening, the bottom die connected through the central opening to a top surface of the base substrate; attaching a top die above the base... Agent: Law Offices Of Mikio Ishimaru

20090256268 - Partially underfilled solder grid arrays: An electronic device and a method of forming the device. The device including a module having opposite top surface and bottom surfaces; a first set of pads on the top surface of the module and a second set of pads on the bottom surface of the module substrate, wires within... Agent: Schmeiser, Olsen & Watts

20090250676 - Liquid crystalline organic semiconductor material, and semiconductor element or information recording medium using the same: P

20090250678 - Nonvolatile memory apparatus, nonvolatile memory element, and nonvolatile element array: A nonvolatile memory apparatus comprises a first electrode (111), a second electrode (112), a variable resistance layer (113) which is disposed between the electrodes, a resistance value of the variable resistance layer reversibly varying between a plurality of resistance states based on an electric signal applied between the electrodes, a... Agent: Mcdermott Will & Emery LLP

20090250679 - Phase-change memory device and method of fabricating the same: A phase-change memory device includes a lower electrode; and at least two phase-change memory cells sharing the lower electrode. Another phase-change memory device includes a heating layer having a smaller contact area with a phase-change material layer and a greater contact area with a PN diode structure.... Agent: Lowe Hauptman Ham & Berner, LLP

20090250677 - Reducing drift in chalcogenide devices: Chalcogenide materials conventionally used in chalcogenide memory devices and ovonic threshold switches may exhibit a tendency called drift, wherein threshold voltage or resistance changes with time. By providing a compensating material which exhibits an opposing tendency, the drift may be compensated. The compensating material may be mixed into a chalcogenide,... Agent: Trop, Pruner & Hu, P.C.

20090250680 - Semiconductor integrated circuit device: With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising... Agent: Mattingly & Malur, P.C.

20090250681 - Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Insulative material is deposited over the first electrode. An opening is formed into the insulative material over the first electrode. The opening includes sidewalls and... Agent: Wells St. John P.s.

20090250682 - Phase change memory device: Provided is a phase change memory device. The phase change memory device includes a first electrode and a second electrode. A phase change material pattern is interposed between the first and second electrodes. A phase change auxiliary pattern is in contact with at least one side of the phase change... Agent: Myers Bigel Sibley & Sajovec

20090250685 - Light emitting device: Disclosed are a light emitting device. The light emitting device includes a first conductive semiconductor layer, a light emitting layer, a protective layer, a nano-layer and a second conductive semiconductor layer. The light emitting layer is formed on the first conductive semiconductor layer. The protective layer is formed on the... Agent: Birch Stewart Kolasch & Birch

20090250684 - Light emitting semiconductor: A semiconductor element is disclosed having a layered body of a first conductivity type, a light emitting layer, a layered body of a second conductivity type, a constriction layer having a constriction hole, and a first electrode having a lighting hole, a second electrode positioned such that charge traveling between... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20090250686 - Method for fabrication of semipolar (al, in, ga, b)n based light emitting diodes: A yellow Light Emitting Diode (LED) with a peak emission wavelength in the range 560-580 nm is disclosed. The LED is grown on one or more III-nitride-based semipolar planes and an active layer of the LED is composed of indium (In) containing single or multi-quantum well structures. The LED quantum... Agent: Gates & Cooper LLP Howard Hughes Center

20090250683 - Nitride-based semiconductor light emitting element: The purpose of the present invention is to obtain a nitride-based semiconductor light emitting element capable of improving light emission efficiency by reducing sheet resistance and a forward voltage of a translucent electrode including indium cerium oxide. The nitride-based semiconductor light emitting element of the present invention is has a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090250687 - Semiconductor device and method to control the state of a semiconductor device and to manufacture the same: A semiconductor device includes a conduct structure to which are arranged contacts for a source and a drain, a resonance region including at least two barrier regions, at least one resonator between the barrier regions and a control electrode and which resonance region is arranged between the contacts. The conduct... Agent: Fildes & Outland, P.C.

20090250688 - Molecular quantum interference apparatus and applications of same: A molecular quantum interference device for use in molecular electronics. In one embodiment, the device includes a molecular quantum interference unit having a first terminal group and a second terminal group between which quantum interference affects electrical conduction, a molecular spacer having a first terminal group and a second terminal... Agent: Morris Manning Martin LLP

20090250689 - Nanowire: A method comprises applying a first electric field pulse to a nanowire comprising a channel and a charge trapping region configured to control conductivity of the channel, the first electric field pulse having a first polarity and a relatively large magnitude of integral of electric field during the pulse and,... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20090250690 - Organic thin film transistor substrate and method of manufacturing the same: In an organic thin film transistor (TFT) substrate, the organic TFT substrate includes gate lines, data lines, a gate electrode, a source electrode, a drain electrode, a gate insulating layer, an organic semiconductor layer, and an organic protective layer. The gate and data lines are insulated from each other and... Agent: H.c. Park & Associates, PLC

20090250691 - Phase change memory element and method for forming the same: A phase change memory and method for fabricating the same are provided. The phase change memory element includes: a substrate; rectangle-shaped dielectric patterns formed on the substrate and parallel with each other; electric conductive patterns partially covering a first sidewall and the top surface of the dielectric pattern and the... Agent: Quintero Law Office, PC

20090250692 - Radiation detector with asymmetric contacts: A room temperature radiation detector is made from a semi-insulating Cd1-xZnxTe crystal, where 0≦x≦1, having a first electrode made of Pt or Au on one surface of the crystal and a second electrode of Al, Ti or In on another surface of the crystal. In use of the crystal to... Agent: The Webb Law Firm, P.C.

20090250694 - Semiconductor device, manufacturing method of semiconductor device, and display device: A semiconductor device includes a substrate and a channel region which is formed above the substrate by printing, wherein a relationship L≧2a is satisfied where L is a channel length of the channel region and a is a minimum dimension among pattern dimensions and inter-pattern dimensions in the same layer... Agent: Sughrue-265550

20090250695 - Semiconductor device, manufacturing method of semiconductor device, display device, and manufacturing method of display device: A semiconductor device includes a substrate and a semiconductor layer having a channel region, the channel region is made from an oxide semiconductor which satisfies Vc/Va>4 where Vc is a volume ratio of a crystalline component and Va is a volume ratio of a non-crystalline component.... Agent: Sughrue-265550

20090250693 - Thin film transistor, display device, including the same, and associated methods: A thin film transistor (TFT), including a substrate, a gate electrode on the substrate, an oxide semiconductor layer including a channel region, a source region, and a drain region, a gate insulating layer between the gate electrode and the oxide semiconductor layer, and source and drain electrodes in contact with... Agent: Lee & Morse, P.C.

20090250696 - Near natural breakdown device: A semiconductor device includes a semiconductor region wherein the semiconductor region is a forced or non-forced Near Natural breakdown region, which is completely depleted when a predetermined voltage having a magnitude less than or equal to the breakdown voltage of a non-Natural breakdown (for example, Zener breakdown and Avalanche breakdown)... Agent: Haynes And Boone, LLPIPSection

20090250698 - Fabrication management system: With the evolution of technology, there is a continual demand for enhanced speed, capacity and efficiency. A modular, chip testing system associated with a single chip on a wafer is described. This system includes a performance structure for measuring chip performance during a testing period; a power structure for measuring... Agent: Texas Instruments Incorporated

20090250697 - Semiconductor device and manufacturing method therefor: Methods for detecting a void in an element portion of a semiconductor device having an element portion and a void detection structure are disclosed. As a part of the method, an insulating film is formed on a substrate, a plurality of holes is formed in the insulating film, and a... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090250699 - Electromagnetic wave detecting element: The present invention provides an electromagnetic wave detecting element that can suppress occurrence of cracking at a substrate peripheral portion, and occurrence of breakage of lead-out wires. An interlayer insulating film is formed so as to cover TFT switches on a substrate. An interlayer insulating film is formed so as... Agent: Moss & Burke, PLLC

20090250700 - Crystalline semiconductor stripe transistor: A transistor with crystalline semiconductor stripes and an associated fabrication process are provided. The method provides a substrate, and deposits a semiconductor layer overlying the substrate. The semiconductor layer is irradiated using a scanning step-and-repeat laser annealing process, which agglomerates portions of the semiconductor layer. In response to cooling agglomerated... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20090250701 - Circuit board, electronic device, and method for producing circuit board: The present invention provides a circuit board which can improve characteristics of a circuit element, an electronic device, and a method for producing a circuit board. The method for producing a circuit board of the present invention is a method for producing a circuit board including one or more polysilicon... Agent: Nixon & Vanderhye, PC

20090250704 - Semiconductor device and method of fabricating the same: An active matrix display device having a pixel structure in which pixel electrodes, gate wirings and source wirings are suitably arranged in the pixel portions to realize a high numerical aperture without increasing the number of masks or the number of steps. The device comprises a gate electrode and a... Agent: Fish & Richardson P.C.

20090250703 - Semiconductor device and method of manufacturing the same: It is provided a contacting method when a plurality of films to be peeled are laminating. Reduction of total layout area, miniaturization of a module, weight reduction, thinning, narrowing a frame of a display device, or the like can be realized by sequentially laminating a plurality of films to be... Agent: Eric Robinson

20090250702 - Static-tolerant display apparatus: A display apparatus includes a thin film transistor having a top-gate structure and a storage capacitor that are arranged on a first substrate. An upper electrode of the storage capacitor has a size larger than a size of a lower electrode, so as to cover an entire surface of the... Agent: Haynes And Boone, LLPIPSection

20090250705 - Silicon carbide semiconductor device comprising silicon carbide layer and method of manufacturing the same: A p base ohmic contact of a silicon carbide semiconductor device consists of a p++ layer formed by high-concentration ion implantation and a metal electrode. Since the high-concentration ion implantation performed at the room temperature significantly degrades the crystal of the p++ layer to cause a process failure, a method... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090250706 - Light activated silicon controlled switch: The present invention provides an optically triggered switch and a method of forming the optically triggered switch. The optically triggered switch includes a silicon layer having at least one trench formed therein and at least one silicon diode formed in the silicon layer. The switch also includes a first thyristor... Agent: Williams, Morgan & Amerson

20090250707 - Multi-chip assembly with optically coupled die: Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die... Agent: Intel Corporation C/o Cpa Global

20090250708 - Thin-film photodiode and display device: A thin-film photodiode has a substrate, a thin-film element formed on the substrate and a micro lens formed above the thin-film element. The thin-film element includes a first semiconductor layer of p-type semiconductor formed on the substrate, a second semiconductor layer formed in contact with the first semiconductor layer on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090250709 - Led package and light source device using same: An exemplary LED package includes a dielectric plate, a heat conductor, a first planar electrode and a second planar electrode, a LED chip, and metal wires. The dielectric plate comprises a receiving groove defined therein. The heat conductor is positioned in the dielectric plate opposite to the receiving groove, and... Agent: PCe Industry, Inc. Att. Steven Reiss

20090250710 - Semiconductor light emitting devices including multiple semiconductor light emitting elements in a substrate cavity: Semiconductor light emitting devices include a substrate having a cavity, multiple light emitting devices in the cavity and remote phosphor layers, scattering layers and/or lenses for the light emitting devices.... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090250712 - Light emitting device: A light emitting device is provided, which includes a light-emitting structure and a magnetic material. The light-emitting structure has an exciting binding energy of a bandgap. The magnetic material is coupled with the light-emitting structure to produce a magnetic field in the light-emitting structure. The exciting binding energy may be... Agent: Jianq Chyun Intellectual Property Office

20090250711 - Substrate for forming light-emitting layer, light emitter and light-emitting substance: 4 for forming light-emitting layer comprises a substrate single-crystal substrate 1, and an oriented fine crystal layer 3 being formed on the single-crystal substrate 4. One of the crystal axes of respective crystals, which constitute the oriented microcrystal layer 3, is oriented in a specific direction with respect to the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090250715 - Led transparent brick: An LED transparent brick comprises a transparent brick body, a photo catalyst layer, a connecting layer, a light reflection layer and one or more ultraviolet LEDs. The photo catalyst layer is placed at a first surface of the transparent brick body, and the connecting layer combines the transparent brick body... Agent: Wpat, PC Intellectual Property Attorneys

20090250717 - Light emitting device: A light emitting device includes a light emitting element having at least two electrodes disposed at the side of the light output surface thereof, and a base member having a recess and lead portions corresponding to the electrodes, the light emitting element being mounted on the base member and received... Agent: Jianq Chyun Intellectual Property Office

20090250716 - Light emitting devices having roughened/reflective contacts and methods of fabricating same: Light emitting devices include an active region of semiconductor material and a first contact on the active region. The first contact is configured such that photons emitted by the active region pass through the first contact. A photon absorbing wire bond pad is provided on the first contact. The wire... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090250713 - Reflective contact for a semiconductor light emitting device: A light emitting device includes a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region. A contact is formed on the semiconductor structure, the contact comprising a reflective metal in direct contact with the semiconductor structure and an additional metal or semi-metal disposed... Agent: Patent Law Group LLP

20090250714 - White light emitting diode and lighting apparatus using the same: Provided is a white LED including a substrate having a reflecting body provided thereon; an LED chip mounted on the substrate; a fluorescence reflecting layer formed on the LED chip; and a phosphor layer formed on the fluorescence reflecting layer and having a higher refractive index than the fluorescence reflecting... Agent: Mcdermott Will & Emery LLP

20090250718 - Light emitting diode and method for producing the same: A method for producing an LED includes steps of: providing a base (22), a chip body (21) and a die (40), wherein the base has a concave depression (23) defined therein and the die has a bottom wall (43) with an even surface having a surface roughness not smaller than... Agent: PCe Industry, Inc. Att. Steven Reiss

20090250719 - Nitride compound semiconductor device and semiconductor laser: A nitride semiconductor device includes a semiconductor substrate composed of gallium nitride, and a stack which is provided on the semiconductor substrate and includes at least one nitride semiconductor layer containing aluminum, wherein substrate thickness T of the semiconductor substrate and a sum S of products of proportions of aluminum... Agent: Rabin & Berdo, PC

20090250720 - Transient voltage suppressor and methods: Transient voltage suppressor and method for manufacturing the transient voltage suppressor having a dopant or carrier concentration in a portion of a gate region near a Zener region that is different from a dopant concentration in a portion of a gate region that is away from the Zener region.... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20090250721 - Electrical surge protective apparatus: Disclosed is an electrical surge protective apparatus comprising: a base region containing impurities of a first conductivity type; a first semiconductor region containing impurities of a second conductivity type; a second semiconductor region containing impurities of the same conductivity type as that of the second conductivity type; and a high... Agent: Young & Thompson

20090250722 - Method for forming a compound semi-conductor thin-film: A method is provided for fabricating a thin film semiconductor device. The method includes providing a plurality of raw semiconductor materials. The raw semiconductor materials undergo a pre-reacting process to form a homogeneous compound semiconductor target material. The compound semiconductor target material is deposited onto a substrate to form a... Agent: Mayer & Williams PC

20090250723 - Electronic device and heterojunction fet: In an electronic device of the present invention a gate Schottky electrode is formed on an active layer constructed of a GaN layer and an AlGaN layer, and a source ohmic electrode and a drain ohmic electrode are further formed on both sides of the gate Schottky electrode on the... Agent: Birch Stewart Kolasch & Birch

20090250724 - Bipolar transistor and method of making such a transistor: A bipolar transistor is formed on a heavily doped silicon substrate (1). An epitaxially grown collector (12) is formed on the substrate (1) and comprises silicon containing germanium at least at the top of the collector (12). An epitaxial base (13) is formed on the collector (12) to have the... Agent: Thompson Hine L.L.P. Intellectual Property Group

20090250725 - Ohmic metal contact protection using an encapsulation layer: A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality... Agent: Ladas & Parry

20090250726 - Low vt antifuse device: A one time programmable memory cell having an anti-fuse device with a low threshold voltage independent of core circuit process manufacturing technology is presented. A two transistor memory cell having a pass transistor and an anti-fuse device, or a single transistor memory cell having a dual thickness gate oxide, are... Agent: Borden Ladner Gervais LLP Anne Kinsman

20090250727 - Super junction semiconductor device: In the specification and drawing a super junction semiconductor device is disclosed. The super junction semiconductor device comprises a P-type layer, a N+ substrate, a N-type layer, a silicon dioxide layer and a P+ layer. The N+ substrate is disposed under the P-type layer. The N-type layer is disposed on... Agent: Chih Feng Yeh Brian M. Mcinnis

20090250728 - Solid state imaging device and method of manufacturing the same: A solid state imaging device has a plurality of photodetector parts 11 arranged in matrix, a plurality of vertical charge transfer electrodes 13 that read out signal charge from the photodetector parts and transfer the signal charge in the vertical direction, and a first light-shielding film 5 that shields the... Agent: Hamre, Schumann, Mueller & Larson P.C.

20090250729 - Capacitive micromachined ultrasonic transducer and manufacturing method: The integrated circuit/transducer device of the preferred embodiment includes a substrate, a complementary-metal-oxide-semiconductor (CMOS) circuit that is fabricated on the substrate, and a capacitive micromachined ultrasonic transducer (cMUT) element that is also fabricated on the substrate. The CMOS circuit and cMUT element are fabricated during the same foundry process and... Agent: Schox PLC

20090250730 - Microwave semiconductor device using compound semiconductor and method for manufacturing the same: An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090250731 - Field-effect transistor structure and fabrication method thereof: A field-effect transistor (FET) structure is provided. The FET structure includes a gate substrate, a dielectric layer, conductive electrodes, and a carbon nanotube (CNT). The gate substrate is made of a conductive material. The dielectric layer is disposed on the substrate. The conductive electrodes are disposed on the dielectric layer,... Agent: J.c. Patents

20090250732 - Semiconductor device and method of fabricating the same: In a method of fabricating a semiconductor device on a substrate having thereon a conductive layer, the conductive layer is patterned to form a plurality of opened regions. A gate insulation layer is formed on a sidewall of each of the opened regions. A pillar pattern is formed in each... Agent: Lowe Hauptman Ham & Berner, LLP

20090250733 - Pixel sensor with reduced image lag: A tensile-stress-generating structure is formed above a gate electrode in a CMOS image sensor to apply a normal tensile stress between a charge collection well of a photodiode, which is also a source region of a transfer transistor, and a floating drain in the direction connecting the source region and... Agent: Scully, Scott, Murphy & Presser, P.C.

20090250734 - Pixel with asymmetric transfer gate channel doping: A pixel including a substrate of a first conductivity type and having a surface, a photodetector of a second conductivity type that is opposite the first conductivity type, a floating diffusion region of the second conductivity type, a transfer region between the photodetector and the floating diffusion, a gate positioned... Agent: Ratnerprestia

20090250735 - Semiconductor memory: A semiconductor memory according to an embodiment of the present invention including first and second adjacent bit lines extending in a first direction and provided in the same interconnect layer, an active provided in a memory cell array, a first and second adjacent word lines extending in a second direction... Agent: Knobbe Martens Olson & Bear LLP

20090250737 - Secure memory device of the one-time programmable type: The integrated circuit includes a memory device of the irreversibly electrically programmable type. This device includes several memory cells, each memory cell having a dielectric zone positioned between a first electrode and a second electrode. Each memory cell is further associated with an access transistor. At least one first electrically... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20090250736 - Semiconductor device: In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from... Agent: Lee & Morse, P.C.

20090250738 - Simultaneous buried strap and buried contact via formation for soi deep trench capacitor: A node dielectric, an inner electrode, and a buried strap cavity are formed in the deep trench in an SOI substrate. A buried layer contact cavity is formed by lithographic methods. The buried strap cavity and the buried layer contact cavity are filled simultaneously by deposition of a conductive material,... Agent: Scully, Scott, Murphy & Presser, P.C.

20090250739 - Device structures with a hyper-abrupt p-n junction, methods of forming a hyper-abrupt p-n junction, and design structures for an integrated circuit: Device structures with hyper-abrupt p-n junctions, methods of forming hyper-abrupt p-n junctions, and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090250740 - Semiconductor device and method of manufacturing the same: A semiconductor device has a semiconductor substrate in which a plurality of device regions and a plurality of device isolation regions are alternately formed to extend in a first direction; and a plurality of contact plugs formed on the semiconductor substrate, connected to the device regions and arranged on the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090250741 - Semiconductor device and gate structure having a composite dielectric layer and methods of manufacturing the same: A semiconductor device and/or gate structure having a composite dielectric layer and methods of manufacturing the same is provided. In the semiconductor device, gate structure, and methods provided, a first conductive layer may be formed on a substrate. A native oxide layer formed on the first conductive layer may be... Agent: Harness, Dickey & Pierce, P.L.C

20090250742 - Neuron device: A neuron device includes: a semiconductor layer; source and drain regions formed in the semiconductor layer at a distance from each other; a protection film formed on an upper face of the semiconductor layer; a channel region formed in the semiconductor layer between the source region and the drain region;... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090250743 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device has side surfaces of neighboring bit lines that do not face each other to reduce a capacitance of a parasitic capacitor formed between adjacent bit lines. The semiconductor memory device includes contact plugs formed on a semiconductor substrate. Each contact plug is disposed between gate patterns.... Agent: Townsend And Townsend And Crew, LLP

20090250745 - Memory devices and methods of forming and operating the same: A memory device, including a first ground selection transistor, a first string selection transistor, and first memory cell transistors disposed in series between the first ground selection transistor and the first string selection transistor, wherein the first ground selection transistor and the first memory cell transistors have a same structure.... Agent: Lee & Morse, P.C.

20090250746 - Nor-type flash memory cell array and method for manufacturing the same: Disclosed is a non-volatile (e.g., NOR type flash) memory cell array and a method for manufacturing the same. The memory cell array includes a plurality of isolation layers on a semiconductor substrate, parallel to a bit line and defining an active device area, a plurality of common source areas in... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090250744 - Semiconductor memory device and manufacturing method therefor: A semiconductor memory device has a cover film (5), between a memory cell (gate electrode 4, and source and drain regions 2a and 2b) and an interlayer insulating film (6), the cover film covering the memory cell, wherein the cover film (5) has a hydrogen storage film (5a) that is... Agent: Mcginn Intellectual Property Law Group, PLLC

20090250747 - Non-volatile memory devices having a multi-layered charge storage layer: A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap... Agent: Myers Bigel Sibley & Sajovec

20090250748 - Semiconductor device and method of fabricating the same: A semiconductor device and method of fabricating the same includes preparing a substrate, forming a plurality of conductive layer patterns on the substrate, forming a gate insulation layer on sidewalls of the conductive layer patterns, forming a pillar neck pattern between the conductive layer patterns, forming a pillar head over... Agent: Lowe Hauptman Ham & Berner, LLP

20090250749 - Methods of forming asymmetric recesses and gate structures that fill such recesses and related methods of forming semiconductor devices that include such recesses and gate structures: In a method of forming an asymmetric recess, an asymmetric recessed gate structure filling the asymmetric recess, a method of forming the asymmetric recessed gate structure, a semiconductor device having the asymmetric recessed gate structure and a method of manufacturing the semiconductor device, a semiconductor substrate is etched to form... Agent: Myers Bigel Sibley & Sajovec

20090250750 - Trench gate power mosfet: A trench gate power MOSFET (1) of the present invention includes an n-type epitaxial layer (12), gates (18) and MOSFET cells. The gate (18) is disposed in a trench (14) formed in a surface of the n-type epitaxial layer (12). The MOSFET cell is formed on the surface of the... Agent: Lowe Hauptman Ham & Berner, LLP

20090250751 - Mos device with low on-resistance: Some of the embodiments of the present disclosure provide a metal oxide semiconductor (MOS) device comprising a drain region, a gate region surrounding the drain region and formed in a loop around the drain region, a plurality of source regions arranged around the gate region, wherein each source region is... Agent: Schwabe, Williamson & Wyatt, P.C.

20090250752 - Methods of fabricating semiconductor device having a metal gate pattern: A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to... Agent: Harness, Dickey & Pierce, P.L.C

20090250753 - Semiconductor device and method of fabricating the same: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed on the semiconductor substrate with a gate insulating layer intervening... Agent: Hiscock & Barclay, LLP

20090250756 - N-type schottky barrier tunnel transistor and manufacturing method thereof: An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090250754 - Partially depleted silicon-on-insulator metal oxide semiconductor device: A partially depleted silicon-on-insulator metal oxide semiconductor (PD-SOI MOS) device is provided. The PD-SOI MOS device includes a gate structure on a silicon-on-insulator substrate, source and drain regions in the silicon-on-insulator substrate beside the gate structure and a silicon dislocation leakage path in an interface of the source region and... Agent: J C Patents, Inc.

20090250755 - Semiconductor device: A transistor capable of adjusting a threshold value is obtained by adjusting an impurity concentration of a silicon substrate supporting an SOI layer and by controlling a thickness of a buried insulating layer formed on a surface of the silicon substrate in contact with the SOI layer.... Agent: Foley And Lardner LLP Suite 500

20090250757 - Semiconductor device and method for manufacturing same: There is provided a semiconductor device having excellent device characteristics and reliability in which Vth values of an nMOS transistor and a pMOS transistor are controlled to be values necessary for a low-power device. The semiconductor device includes a pMOS transistor and an nMOS transistor formed by using an SOI... Agent: Young & Thompson

20090250758 - Manufacturing method of semiconductor device, evaluation method of semiconductor device, and semiconductor device: A semiconductor element formed over the same substrate as a TFT, includes a semiconductor film having an impurity region; an insulating film formed over the semiconductor film; an electrode divided into a plurality of parts over the insulating film by spacing a distance a in a first direction (channel width... Agent: Fish & Richardson P.C.

20090250759 - Semiconductor device: A breakdown voltage of a clamp diode can be reduced while a leakage current is suppressed. A P− type diffusion layer is formed in a surface of an N− type semiconductor layer. An N+ type diffusion layer is formed in a surface of the P− type diffusion layer. A P+... Agent: Morrison & Foerster LLP

20090250760 - Methods of forming high-k/metal gates for nfets and pfets: Methods of forming high-k/metal gates for an NFET and PFET and a related structure are disclosed. One method includes recessing a PFET region; forming a first high-k dielectric layer and a first metal layer over the substrate; removing the first high-k dielectric layer and the first metal over the NFET... Agent: Hoffman Warnick LLC

20090250761 - Semiconductor device with transistors and its manufacturing method: A semiconductor device includes a semiconductor substrate, a first transistor including a first gate electrode, a first diffusion region, and a second diffusion region respectively formed above the semiconductor substrate, second transistor including a second gate electrode, the first diffusion region, and a third diffusion region respectively formed above the... Agent: Mcginn Intellectual Property Law Group, PLLC

20090250763 - Integrated circuit including a first channel and a second channel: An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first area and a second area. The first area is stress engineered to provide enhanced mobility in a first channel that has a first width. The second area is stress engineered to provide enhanced mobility in a... Agent: Spryip, LLC Ifx

20090250762 - Integrated circuit system employing sacrificial spacers: An integrated circuit system that includes: providing a substrate including a first device and a second device; configuring the first device and the second device to include a first spacer, a first liner made from a first dielectric layer, and a second spacer made from a sacrificial spacer material; forming... Agent: Law Offices Of Mikio Ishimaru

20090250764 - Stressed dielectric layer with stable stress: An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric layer is disposed over the substrate and the transistor. At least one of the isolation... Agent: HorizonIPPte Ltd

20090250765 - Low on resistance cmos \"wave\" transistor for integrated circuit applications: In one embodiment of the present invention an array of power transistors on a semiconductor chip has repeating patterns of two “wave” gates which have alternating longer and shorter horizontal sections which are offset mirror images of each other together with a third straight horizontal section. Alternating source and drain... Agent: Hiscock & Barclay, LLP

20090250767 - Ed inverter circuit and integrate circuit element including the same: A second semiconductor layer of a second nitride-based compound semiconductor with a wider bandgap formed on a first semiconductor layer of a first nitride-based compound semiconductor with a smaller bandgap includes an opening, on which a gate insulating layer is formed at a portion exposed through the opening. A first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090250768 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device according to the present invention includes: a first transistor formed on a semiconductor substrate 11, the first transistor including a first gate-insulating film 14a that is oxynitrided; and a second transistor including a second gate-insulating film 14b formed on the semiconductor substrate 11 and a barrier... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090250766 - Work function based voltage reference: A voltage reference is created from an operational amplifier circuit having two substantially identical P-channel metal oxide semiconductor (P-MOS) transistors with each one having a different gate dopant. The different gate dopants result in different threshold voltages for each of the two otherwise substantially identical P-MOS transistors. The difference between... Agent: King & Spalding LLP

20090250769 - Semiconductor device having multiple fin heights: A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist... Agent: Slater & Matsil, L.L.P.

20090250770 - Integration of a sense fet into a discrete power mosfet: A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common substrate. The main FET and each of the sense FETs include a source terminal,... Agent: Joshua D. Isenberg Jdi Patent

20090250771 - Mosfet and production method of semiconductor device: To provide a MOSFET which is increased in substrate bias effect γ without increasing parasitic capacitance and junction leak current, the MOSFET includes: a gate electrode (104) formed on a semiconductor substrate (101) and an insulating film (103); a sidewall insulating film (106) covering the side surface of the gate... Agent: Mcginn Intellectual Property Law Group, PLLC

20090250772 - Field effect transistor and method of manufacture: A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source... Agent: Greenblum & Bernstein, P.L.C

20090250774 - Gate structure: A gate structure includes a gate insulation layer pattern, a gate electrode, a first spacer and a protecting layer pattern. The gate insulation layer pattern is on a substrate. The gate electrode is on the gate insulation layer pattern, the gate electrode including a lower portion having a first width,... Agent: Mills & Onello LLP

20090250773 - Semiconductor device: A semiconductor device includes a first metal region, a plurality of vias, a plurality of second metal regions, a plurality of openings and a third metal region. The first metal region conducts source/drain current. The second metal regions are electrically connected to the first metal region through the vias for... Agent: Rabin & Berdo, PC

20090250775 - Magnetic device with integrated magneto-resistive stack: This magnetic device integrates a magneto-resistive stack, the stack comprising at least two layers made out of a ferromagnetic material, separated from each other by a layer of non-magnetic material; and means for causing an electron current to flow perpendicular to the plane of the layers, with at least one... Agent: Burr & Brown

20090250776 - Magnetic memory device: There is provided a magnetic memory device stable in write characteristics. The magnetic memory device has a recording layer. The planar shape of the recording layer has the maximum length in the direction of the easy-axis over a primary straight line along the easy-axis, and is situated over a length... Agent: Mcdermott Will & Emery LLP

20090250777 - Image sensor and image sensor manufacturing method: In an upper waveguide structure (14), a width (W1) of the upper portion is larger than a width (W2) of the lower portion. The upper waveguide structure (14) has a side face (14a) which obliquely extends from an edge portion (14b) of the upper face to an edge portion (14c)... Agent: Cowan Liebowitz & Latman P.C. John J Torrente

20090250778 - Photoelectric conversion device, imaging system, photoelectric conversion device designing method, and photoelectric conversion device manufacturing method: A photoelectric conversion device comprises a plurality of photoelectric conversion units, a first antireflection portion including a first insulation film which has a first refractive index and a second insulation film which has a second refractive index, and a second antireflection portion including an element isolation portion which includes an... Agent: Fitzpatrick Cella Harper & Scinto

20090250779 - Solid-state imaging device and manufacturing method thereof: A solid-state imaging device in the present invention includes plural photoelectric conversion elements, plural wiring layers, and plural optical waveguide regions each corresponding to and arranged over one of the plural photoelectric conversion elements. A top end of each of the plural optical waveguide regions is higher than a top... Agent: Greenblum & Bernstein, P.L.C

20090250780 - High fill-factor laser-treated semiconductor device on bulk material with single side contact scheme: The present disclosure provides systems and methods for configuring and constructing a single photo detector or array of photo detectors with all fabrications circuitry on a single side and an architecture that enables the laser step to be the final step or a late step in the fabrication process. Both... Agent: Pepper Hamilton LLP

20090250781 - Power semiconductor device: The present invention relates to a power semiconductor device comprising a switching power semiconductor element, and a free wheeling diode in anti-parallel connection to the switching power semiconductor element. The power semiconductor is characterized in that a reverse electrode of the switching power semiconductor element and a reverse electrode of... Agent: Mcdermott Will & Emery LLP

20090250782 - Subgroundrule space for improved metal high-k device: The present invention provides a semiconducting device including a substrate including at least one semiconducting region and isolation regions; a gate structure atop the substrate having a gate dielectric layer positioned on the semiconducting region and a metal layer atop the gate dielectric layer, the gate structure having a width... Agent: Scully, Scott, Murphy & Presser, P.C.

20090250783 - Semiconductor device having an annular guard ring: A semiconductor chip 100 includes a logic unit and an analog unit 153. Furthermore, the semiconductor chip 100 includes a silicon substrate 101; a first insulating film 123 to a sixth insulating film 143 formed on the silicon substrate 101; and an annular seal ring 105 consisting of a first... Agent: Young & Thompson

20090250784 - Structure and method for elimination of process-related defects in poly/metal plate capacitors: An integrated circuit includes silicon layer (2) supported by a bottom oxide layer (3), a shallow trench oxide (4) in the shallow trench (30), and a polycrystalline silicon layer (5) on the shallow trench oxide. A deep trench oxide (25) extending from the shallow trench oxide to the bottom oxide... Agent: Texas Instruments Incorporated

20090250785 - Methods of forming a shallow base region of a bipolar transistor: The disclosed subject matter provides a method of forming a bipolar transistor. The method includes depositing a first insulating layer over a first layer of material that is doped with a dopant of a first type. The first layer is formed over a substrate. The method also includes modifying a... Agent: Williams, Morgan & Amerson

20090250786 - Fuse part of semiconductor device and method of fabricating the same: A fuse part of a semiconductor device includes an insulation layer over a substrate, and a fuse over the insulation layer, wherein the fuse includes a plurality of blowing pads for irradiating a laser beam and the plurality of blowing pads have laser coordinates different from one another.... Agent: Lowe Hauptman Ham & Berner, LLP

20090250788 - Semiconductor device: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction, a plurality of second interconnections each adjacent to the first interconnection located at an edge of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090250787 - Semiconductor storage device and manufacturing method of the same: A semiconductor storage device includes: a first conductive adhesive layer selectively formed over a semiconductor substrate; an insulating film formed on the semiconductor substrate to cover the first conductive adhesive layer and having an opening exposing a central part of the first conductive adhesive layer; and a capacitive element including... Agent: Mcdermott Will & Emery LLP

20090250789 - Methods of counter-doping collector regions in bipolar transistors: The present invention provides a method of forming a bipolar transistor. The method includes doping a silicon layer with a first type of dopant and performing a first implant process to implant dopant of a second type opposite the first type in the silicon layer. The implanted dopant has a... Agent: Williams, Morgan & Amerson

20090250790 - Nitride semiconductor wafer and method of processing nitride semiconductor wafer: Circular nitride wafers having a diameter larger than 45 mm are made and polished. Gross-polishing polishes the nitride wafers in a pressureless state with pressure less than 60 g/cm2 by lifting up the upper turntable for remedying distortion. Distortion height H at a center is reduced to H≦12 μm. Minute-polishing... Agent: Mcdermott Will & Emery LLP

20090250791 - Crystalline semiconductor stripes: Crystalline semiconductor stripes and an associated fabrication process are provided. The method provides an insulator substrate, and deposits a semiconductor layer overlying the insulator substrate. The semiconductor layer is irradiated using a scanning step-and-repeat laser annealing process, which agglomerates portions of the semiconductor layer. In response to cooling agglomerated semiconductor... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20090250792 - Curing low-k dielectrics for improving mechanical strength: An integrated circuit structure including reflective metal pads is provided. The integrated circuit structure includes a semiconductor substrate; a first low-k dielectric layer overlying the semiconductor substrate, wherein the first low-k dielectric layer is a top low-k dielectric layer; a second low-k dielectric layer immediately underlying the first low-k dielectric... Agent: Slater & Matsil, L.L.P.

20090250793 - Bpsg film deposition with undoped capping: Semiconductor devices containing a CVD BPSG layer and an undoped CVD oxide cap layer are described. The cap layer can be any silicon oxide material with a thickness between about 50 Å and about 350 Å. The cap layer may be formed using a low temperature CVD process that is... Agent: Kenneth E. Horton Kirton & Mcconkle

20090250797 - multi-chip package: A lead frame assembly includes at least one die paddle. The die paddle includes a first landing area for receiving a first semiconductor chip and a second landing area for receiving a second semiconductor chip. One or more steps are provided between the first landing area and the second landing... Agent: Edell , Shapiro & Finnan , LLC

20090250798 - Integrated circuit package system with interconnect support: An integrated circuit package system with interconnect support is provided including providing an integrated circuit, forming an electrical interconnect on the integrated circuit, forming a contact pad having a chip support, and coupling the integrated circuit to the contact pad by the electrical interconnect, with the integrated circuit on the... Agent: Law Offices Of Mikio Ishimaru

20090250795 - Leadframe for packaged electronic device with enhanced mold locking capability: A packaged electronic device (20) includes a die pad (30), leads (32) arranged around the die pad (30), and a die (24) attached to an upper surface (34) of the die pad (30) and electrically connected to the leads (32). A packaging material (28) encapsulates the die pad (30), the... Agent: Meschkow & Gresham, P.L.C

20090250794 - Method of forming a semiconductor package and structure therefor: In one embodiment, a semiconductor package is formed to include a leadframe that includes a plurality of die attach areas for attaching a semiconductor die to the leadframe. The leadframe is positioned to overlie another leadframe that forms some of the external terminals or leads of the package.... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20090250796 - Semiconductor device package having features formed by stamping: Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations... Agent: Townsend And Townsend And Crew, LLP

20090250799 - Power semiconductor module comprising an explosion protection system: A power semiconductor module for energy distribution, includes at least one power semiconductor, connection terminals for connecting the power semiconductor module, and a housing, in which protection from explosion is ensured in the module even in the event of electric arcs. Therefore, each power semiconductor and each connection terminal is... Agent: Lerner Greenberg Stemer LLP

20090250801 - Semiconductor device: A semiconductor device in which a plurality of semiconductor elements are stacked, yet realizing high speed operation of the semiconductor elements. The semiconductor device is provided with semiconductor packages, and a spacer. The semiconductor packages are stacked, with the spacer interposed therebetween. The semiconductor packages have, respectively, package boards, and... Agent: Mcginn Intellectual Property Law Group, PLLC

20090250800 - Semiconductor device and manufacturing method therefor: A semiconductor device is provided that includes a semiconductor chip and a resin section that molds the semiconductor chip and has a first through-hole. A through electrode that is electrically coupled to the semiconductor chip, extends through the resin section, and extends between a top edge and a bottom edge... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090250802 - Multilayer wiring substrate, semiconductor package, and methods of manufacturing semiconductor package: A multilayer wiring substrate included in the semiconductor package includes: a first insulating layer and a second insulating layer, in which wiring layers are respectively provided on the upper and the lower surfaces; and; a core layer provided between the first insulating layer and the second insulating layer. The first... Agent: Mcginn Intellectual Property Law Group, PLLC

20090250803 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a chip, a laminated wiring structure formed integrally with the chip, a frame disposed to surround the chip and made of a material having stiffness, and a sealing resin formed to bury therein the frame and at least the periphery of the side surface of the... Agent: Kratz, Quintos & Hanson, LLP

20090250804 - Leadframe-based ic-package with supply-reference comb: An IC package includes a leadframe-diepad (112) and a supply-reference comb (114) for interconnecting a die (110) and the package I/O pins (124) in a manner that facilitates substantially ideal EMC performance. The leadframe-diepad includes a diepad-finger (118) and an elongated portion. The leadframe-diepad and the diepad-finger are connected to... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090250805 - Heat dissipation for integrated circuit: A packaged integrated circuit having a thermal pathway to exhaust heat from the integrated circuit. The integrated circuit is disposed on a package substrate, with an encapsulant disposed around the integrated circuit. A heat sink is disposed at least partially within the encapsulant, with at least a portion of one... Agent: Lng/lsi Joint Customer C/o Luedeka, Neely & Graham, P.C.

20090250807 - Electronic component and method for its production: An electronic component includes a number of leads and at least one cooling element. The bottom surface of the cooling element is exposed and the material of the cooling element is different from the material of the leads. At least one semiconductor chip is provided on the cooling element. An... Agent: Edell , Shapiro & Finnan , LLC

20090250806 - Semiconductor package using an active type heat-spreading element: A semiconductor package includes a carrier, a chip, a stiffener, a heat spreader and an active type heat-spreading element. The chip and the stiffener are disposed on the carrier. The heat spreader is disposed on the stiffener and includes a through opening. The active type heat-spreading element is disposed on... Agent: Lowe Hauptman Ham & Berner, LLP

20090250808 - Reliability improvement in a compound semiconductor mmic: A semiconductor package (M) includes a semiconductor substrate layer (100) having a first side or upper surface (120) and a second side or lower surface or backplane (104) opposite the first side (120). A heat producing active area (102) is formed associated with the first side (120) of the semiconductor... Agent: Marsteller & Associates, P. C.

20090250810 - Integrated circuit packaging system with warpage control system and method of manufacture thereof: A method of manufacture of an integrated circuit packaging system is provided including: providing a substrate; and placing a patterned layer over the substrate for substantially removing crying warpage from the substrate.... Agent: Law Offices Of Mikio Ishimaru

20090250809 - Semiconductor package having thermal stress canceller member: A semiconductor package includes a package-substrate, a first cavity formed on a first main surface of the package substrate, a first semiconductor chip mounted on the bottom surface of the first cavity, a first resin layer filled into the first cavity, and a thermal stress canceller member mounted on the... Agent: Mcginn Intellectual Property Law Group, PLLC

20090250812 - Flip-chip mounting substrate and flip-chip mounting method: A solder resist and a central pad to which a central Au bump provided on a semiconductor chip is flip-chip bonded are formed on a substrate main body. In a flip-chip mounting substrate where an underfill resin is provided after the semiconductor chip is mounted, a central opening portion for... Agent: Rankin, Hill & Clark LLP

20090250813 - Integrated circuit solder bumping system: An integrated circuit solder bumping system provides a substrate and forms a redistribution layer on the substrate. An insulation layer is formed on the redistribution layer. The insulation layer has a plurality of openings therethrough. A first UBM layer of titanium is deposited on the insulation layer and in the... Agent: Law Offices Of Mikio Ishimaru

20090250811 - Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask: A semiconductor device has a semiconductor die with an die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die over the substrate so that the bump material is disposed between... Agent: Robert D. Atkins

20090250814 - Flip chip interconnection structure having void-free fine pitch and method thereof: A semiconductor device is made by providing a semiconductor die having a contact pad, forming a circular solder bump on the contact pad, providing a substrate having a trace line, disposing a non-circular solder resist opening over the trace line, placing the solder bump in proximity to the trace line,... Agent: Robert D. Atkins

20090250815 - Surface treatment for selective metal cap applications: Interconnect structures in which a noble metal-containing cap layer is present directly on a non-recessed surface of a conductive material which is embedded within a low k dielectric material are provided. It has been determined that by forming a hydrophobic surface on a low k dielectric material prior to metal... Agent: Scully, Scott, Murphy & Presser, P.C.

20090250817 - Method of fabricating semiconductor device and semiconductor device: A method of fabricating a semiconductor device according to embodiments includes forming a resist film above an object to be etched, the resist film having a pattern with notches provided in the vicinity of corners having an angle of less than 180 degrees on an opening side, and dry etching... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090250816 - Ultra-thin diffusion-barrier layer for cu metallization: Diffusion barrier layer is required during copper metallization in IC processing to prevent Cu from diffusion into the contacting silicon material and reacting to form copper silicide, which consumes Cu and deteriorates electrical conduction. With decreasing feature sizes of IC devices, such as those smaller than 90 nano-meter (nm), the... Agent: Lowe Hauptman Ham & Berner, LLP

20090250818 - Via electromigration improvement by changing the via bottom geometric profile: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal... Agent: Law Offices Of Mikio Ishimaru

20090250820 - Configurable non-volatile logic structure for characterizing an integrated circuit device: An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes a number of MLR cells and includes a parity circuit having... Agent: William L. Paradice, Iii

20090250819 - Metal line of semiconductor device and method of forming the same: The invention relates to a metal line of a semiconductor device and a method of forming the same. According to a method of forming a metal line of a semiconductor device in accordance with an aspect of the invention, a semiconductor substrate in which contact plugs are formed within contact... Agent: Marshall, Gerstein & Borun LLP

20090250821 - Corrosion resistant via connections in semiconductor substrates and methods of making same: Devices and methods for protecting the metal within a via in a semiconductor substrate from corrosion are provided. Specifically, embodiments of the present invention relate to disposing a corrosion resistant metal layer within a recess formed in a semiconductor substrate such that the metal subsequently deposited within the via will... Agent: Fletcher Yoder (micron Technology, Inc.)

20090250822 - Multi-chip stack package: A multi-chip stack package comprising a first wiring substrate, a first chip, a second wiring substrate, and a second chip is provided. The first wiring substrate is with a front side and a rear side. The first chip is disposed on the front side of the first wiring substrate and... Agent: Jianq Chyun Intellectual Property Office

20090250823 - Electronic modules and methods for forming the same: Electronic modules are formed by encapsulating microelectronic dies within cavities in a substrate.... Agent: Goodwin Procter LLP Patent Administrator

20090250824 - Method and apparatus to reduce pin voids: A semiconductor package comprises a substrate that utilizes one or more pins to form external interconnects. The pins are bonded to bonding pads on the substrate by solder. The pins may each has a pin head that may have a bonding surface, wherein the bonding surface may comprises a center... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090250825 - Process for producing acid anhydride-based epoxy resin curing agent, acid anhydride-based epoxy resin composition, and cured product and optical semiconductor device using the same: The present invention relates to a process for producing an acid anhydride-based epoxy resin curing agent, an acid anhydride-based epoxy resin curing agent, an epoxy resin composition, and a cured product and optical semiconductor device using the same. The process for producing an acid anhydride-based epoxy resin curing agent according... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090250826 - Process for manufacturing semiconductor device and semiconductor device manufactured by such process: A process for manufacturing a semiconductor device that inhibits deterioration in the quality of the semiconductor device and a semiconductor device manufactured on such manufacturing process are presented. An operation of determining time-variation of water content in the resin substrate 11 (processing S1); an operation of coupling the semiconductor element... Agent: Mcginn Intellectual Property Law Group, PLLC

20090242865 - Memory array with diode driver and method for fabricating the same: A method of fabricating a memory array. The method begins with a structure, generally composed of dielectric fill material and having conductive lines formed at its lower portion, and a sacrificial layer formed on its upper surface. Diodes are formed in the fill material, each diode having a lightly-doped first... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090242866 - Phase change memory device and method of fabricating the same: A semiconductor device includes an insulating layer on a substrate, a first electrode in the insulating layer having a first upper surface and a second upper surface, a second electrode in the insulating layer spaced apart from the first electrode by a first distance and having a third upper surface... Agent: Lee & Morse, P.C.

20090242867 - Phase change memory device having protective layer for protecting phase change material and method for manufacturing the same: A phase change memory device includes a semiconductor substrate, a plurality of bottom electrodes formed on the substrate, a plurality of phase change structures formed on the semiconductor substrate, each respectively contacting one of the bottom electrodes, and each having a phase change material layer and a top electrode stacked... Agent: Baker & Mckenzie LLP Patent Department

20090242868 - Semiconductor device and method of manufacturing the same: A solid electrolyte memory involves a problem that stable rewriting is difficult since the amount of ions in the solid electrolyte and the shape of the electrode are changed by repeating rewriting. In a semiconductor device in which information is stored or the circuit connection is changed by the change... Agent: Miles & Stockbridge PC

20090242870 - Light emitting device and method for manufacturing the same: Disclosed herein is a light emitting device. The light emitting device includes an n-type nitride semiconductor layer; an active layer on the n-type semiconductor layer, an AlN/GaN layer of a super lattice structure formed by alternately growing an AlN layer and a GaN layer on the active layer, and a... Agent: H.c. Park & Associates, PLC

20090242871 - Quantum dot inorganic electroluminescent device: An inorganic EL device is provided with a substrate, a first electrode, a first insulating layer, a light emitting layer, a second insulating layer and a second electrode. The inorganic EL light emitting device is characterized in that the light emitting layer contains a quantum dot and is arranged between... Agent: Oliff & Berridge, PLC

20090242869 - Super lattice/quantum well nanowires: Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such... Agent: Connolly Bove Lodge & Hutz LLP

20090242872 - Double quantum well structures for transistors: Double quantum well structures for transistors are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a first quantum well channel coupled with the first barrier... Agent: Cool Patent, P.C. C/o Cpa Global

20090242873 - Semiconductor heterostructures to reduce short channel effects: Semiconductor heterostructures to reduce short channel effects are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a back gate layer coupled to the first barrier... Agent: Cool Patent, P.C. C/o Cpa Global

20090242874 - Gan based semiconductor light-emitting device and method for producing same: A GaN based semiconductor light-emitting device is provided. The light-emitting device includes a first GaN based compound semiconductor layer of an n-conductivity type; an active layer; a second GaN based compound semiconductor layer; an underlying layer composed of a GaN based compound semiconductor, the underlying layer being disposed between the... Agent: K&l Gates LLP

20090242876 - Carbazole compounds: The present invention relates to carbazole compounds of formula (I) and a semiconducting material comprising such carbazole compounds. It also relates to a process for the preparation of such carbazole compounds, as well as to the use thereof as a semiconducting material, in particular as a host matrix for phosphorescent... Agent: Philips Intellectual Property & Standards

20090242875 - Forming electrodes to small electronic devices having self-assembled organic layers: In one embodiment of the invention, a method of fabricating a SAM device comprises the steps of: (a) providing a substrate having a top surface and a first metal electrode disposed on the top surface, (b) annealing the first metal electrode, (c) forming a SAM layer on a major surface... Agent: Michael J. Urbano

20090242877 - Oled device with hole-transport and electron-transport materials:

20090242878 - Optimization of new polymer semiconductors for better mobility and processibality:

20090242879 - Optoelectronic device and method of fabricating the same: A modified isolated polypeptide comprising an amino acid sequence encoding a photocatalytic unit of a photosynthetic organism being capable of covalent attachment to a solid surface and having a photocatalytic activity when attached thereto is disclosed.... Agent: Martin D. Moynihan D/b/a Prtsi, Inc.

20090242880 - Thermally stabilized electrode structure: Memory devices and methods for manufacturing are described herein. A memory device as described herein includes a first electrode layer, a second electrode layer, and a thermal isolation structure comprising a layer of thermal isolation material between the first and second electrode layers. The first and second electrode layers and... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090242881 - Thin film transistor substrate, display device having the same and method of manufacturing the display device: A thin film transistor substrate includes an insulating plate; a gate electrode disposed on the insulating plate; a semiconductor layer comprising a metal oxide, wherein the metal oxide has oxygen defects of less than or equal to 3%, and wherein the metal oxide comprises about 0.01 mole/cm3 to about 0.3... Agent: Cantor Colburn, LLP

20090242882 - Three-dimensional microstructures and methods for making same: Microstructures can be formed as patterned layers on a substrate and then erecting the microstructures out of the plane of the substrate. The microstructures may be formed over circuits in the substrate. In some embodiments the patterned layer provides resiliently-flexible members such as cantilevers or springs that can be buckled... Agent: Oyen, Wiggs, Green & Mutala LLP 480 - The Station

20090242888 - Display device and method for manufacturing the same: In a pixel portion, a scan signal line and an auxiliary capacitor line are formed using a second conductive film, and a data signal line is formed using a first conductive film. In a TFT portion, a gate electrode is formed using the first conductive film and electrically connected to... Agent: Cook Alex Ltd.

20090242887 - Display substrate having a transparent conductive layer made of zinc oxide and manufacturing method thereof: A display substrate is disclosed comprising: a supporting substrate; an organic resin layer formed on the supporting substrate; and a transparent electrode formed on the organic resin layer, wherein the transparent electrode includes: a first layer containing a zinc oxide and formed in close contact with the organic resin layer;... Agent: Masao Yoshimura, Chen Yoshimura LLP

20090242885 - Manufacturing process of liquid crystal display device, and liquid crystal display device: A manufacturing process of an LCD de vice of the invention includes forming a first substrate provided with a pixel part with thin film transistors and a seal portion arranged around the pixel part, forming a second substrate opposed to the first substrate, filling a liquid crystal layer between the... Agent: Young & Thompson

20090242884 - Method of producing display device, display device, method of producing thin-film transistor substrate, and thin-film transistor substrate: A method of producing a display device includes the steps of forming gate electrodes on a substrate so that an arrangement of a source and a drain, in a pixel row direction, of a thin-film transistor formed in each of pixels on the substrate is reversed every pixel row; forming... Agent: Rader Fishman & Grauer PLLC

20090242886 - Thin film transistor substrate: In forming a thin film transistor using multi-tone exposure, a wiring width of a foundational wiring is 40 μm or less, and a ratio of a wiring width of a foundational wiring in a dense case to a space between adjacent wirings is 1.7, preferably 1.0 or less.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242883 - Thin film transistor, active array substrate and method for manufacturing the same: A thin film transistor, an active array substrate having the same and methods for manufacturing the same are provided. The thin film transistor includes a base having a concave; a gate disposed in the concave; a gate insulator covering the gate and a portion of the gate insulator is in... Agent: Bacon & Thomas, PLLC

20090242889 - Thin film transistor, method for manufacturing the same, and display: Disclosed is a thin film transistor which is characterized by including a gate electrode 3, a gate insulating film 4, a channel layer 5 and source/drain layers 7, 8 stacked over a substrate 2 in this order or in reverse order, wherein the source/drain layers 7, 8 include n-type microcrystalline... Agent: Sonnenschein Nath & Rosenthal LLP

20090242892 - Semiconductor device and method for forming the same: In fabricating a thin film transistor, an active layer comprising a silicon semiconductor is formed on a substrate having an insulating surface. Hydrogen is introduced into The active layer. A thin film comprising SiOxNy is formed to cover the active layer and then a gate insulating film comprising a silicon... Agent: Eric Robinson

20090242890 - Semiconductor device, electrooptical apparatus, and electronic system: A semiconductor device on a flexible substrate includes a semiconductor layer constituting a plurality of bottom-gate thin-film transistors, first wiring lines, second wiring lines, a first insulating layer, and a gate insulating film. The first insulating layer and the gate insulating film are present below the semiconductor layer, the first... Agent: Harness, Dickey & Pierce, P.L.C

20090242891 - Thin-film semiconductor device and method for manufacturing the same: A thin-film semiconductor device including a transparent insulating substrate, an island semiconductor layer formed on the transparent insulating substrate and including a source region containing a first-conductivity-type impurity and a drain region containing a first-conductivity-type impurity and spaced apart from the source region, a gate insulating film and a gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242893 - Semiconductor device, production method thereof, and display device: The present invention provides a semiconductor device which can be produced by simple and cheap processes and effectively achieve improved performances and a reduced electric power consumption. Further, the present invention provides a production method thereof and a display device including the semiconductor device or a semiconductor device produced by... Agent: Nixon & Vanderhye, PC

20090242895 - Thin film transistor, method of fabricating the same, and organic lighting emitting diode display device including the same: A thin film transistor, a method of fabricating the same, and an organic light emitting diode display device including the same. The thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, including a channel region, source/drain regions, and a body contact region; a gate insulating layer... Agent: Stein Mcewen, LLP

20090242894 - Thin-film-transistor structure, pixel structure and manufacturing method thereof: A thin-film-transistor (TFT) structure, a pixel structure and a manufacturing method thereof are provided. The TFT structure is formed in the pixel structure of a liquid crystal display (LCD). The TFT structure comprises a gate, a first dielectric layer, a patterned semiconductor layer, a second dielectric layer and a third... Agent: James M. Wu Jw Law Group

20090242896 - Semiconductor device and method for manufacturing the same: A microstructure and a semiconductor element which are included in a micromachine have been generally formed in different steps. It is an object to provide a method for manufacturing a micromachine in which a microstructure and a semiconductor element are formed over one insulating substrate. A feature of the invention... Agent: Fish & Richardson P.C.

20090242897 - Indium gallium nitride-based ohmic contact layers for gallium nitride-based devices: Light emitting devices include a gallium nitride-based epitaxial structure that includes an active light emitting region and a gallium nitride-based outer layer, for example gallium nitride. A indium nitride-based layer, such as indium gallium nitride, is provided directly on the outer layer. A reflective metal layer or a transparent conductive... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090242898 - Method of controlling stress in gallium nitride films deposited on substrates: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial... Agent: Gates & Cooper LLP Howard Hughes Center

20090242899 - Epitaxial growth on low degree off-axis sic substrates and semiconductor devices made thereby: A method of epitaxially growing a SiC layer on a single crystal SiC substrate is described. The method includes heating a single-crystal SiC substrate to a first temperature of at least 1400° C. in a chamber, introducing a carrier gas, a silicon containing gas and carbon containing gas into the... Agent: Morris Manning Martin LLP

20090242900 - Memory device and method of manufacturing the same: The invention discloses a memory device and method thereof. The memory device comprises a substrate, an insulator layer, a first conducting layer, a CaCu3Ti4O12 resistor layer and a second conducting layer. The insulator layer is formed over the substrate. The first conducting layer is formed over the insulator layer. The... Agent: Morris Manning Martin LLP

20090242901 - Sic mosfets and self-aligned fabrication methods thereof: The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer.... Agent: General Electric Company Global Research

20090242902 - Light emitting devices with constant forward voltage: A light emitting device and method for producing the same is disclosed. The light emitting device includes a semiconductor material, an electrode positioned on the semiconductor material, a wire bonding area, and a resistor connected between the wire bonding area and the electrode.... Agent: Arent Fox LLP

20090242907 - Display device and manufacturing method thereof: To achieve enlargement and high definition of a display portion, a single crystal semiconductor film is used as a transistor in a pixel, and the following steps are included: bonding a plurality of single crystal semiconductor substrates to a base substrate; separating part of the plurality of single crystal semiconductor... Agent: Eric Robinson

20090242910 - Light emitting device: A light emitting device includes: a first semiconductor region; a second semiconductor region and third semiconductor region which are provided in the first semiconductor region; a first semiconductor light emitting element of which first electrode is electrically connected to a main surface of the second semiconductor region; a second semiconductor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242909 - Light-emitting device, linear light source, planar light unit and display apparatus: A light-emitting device used in a linear array of a plurality of them includes a semiconductor light-emitting element, a substrate on which the semiconductor light-emitting element is mounted, and a light-transmitting sealing resin formed on the front surface of the substrate to seal the semiconductor light-emitting element. Of each of... Agent: Brinks Hofer Gilson & Lione

20090242903 - Luminous body with led dies and production thereof: A luminous body comprises a transparent plastic moulding with indentations, and LED DIEs disposed within the indentations. One side of each LED DIE lies approximately flush with an upper side of the moulding, and each LED DIE is connected to an electricity supply via electrical conductors disposed on the moulding.... Agent: Connolly Bove Lodge & Hutz, LLP

20090242908 - Planar light source device: A planar light source device includes: a substrate having a thickness larger than 0.9 mm and including a metal layer; and a plurality of light-emitting diode chips disposed on the substrate in a matrix array. Each light-emitting diode chip has a chip size ranging from 0.0784 mm2 to 0.25 mm2.... Agent: Darby & Darby P.C.

20090242905 - Semiconductor device, optical print head and image forming apparatus: A semiconductor device and an optical print head, an image forming apparatus that has the semiconductor device are supplied capable of reduce occurrence probability of defect. The semiconductor device is formed by using semiconductor thin film bonded on the substrate, and includes a covering layer that covers at least one... Agent: Panitch Schwarze Belisario & Nadel LLP

20090242904 - Semiconductor light emitting apparatus and optical print head: A semiconductor light emitting apparatus is supplied capable of providing a high performance that can optimize simultaneously both an electrical characteristic and a light emitting characteristic. The semiconductor apparatus comprises an anode layer; a cathode layer that has a conductive type different from that of the anode layer; a gate... Agent: Panitch Schwarze Belisario & Nadel LLP

20090242906 - Semiconductor light emitting device and semiconductor light emitting unit: A semiconductor light emitting device includes: an outer surrounding body having a recessed portion formed in an upper surface of the outer surrounding body; a lead terminal led out from a side surface of the outer surrounding body; and a semiconductor light emitting element disposed in the recessed portion. The... Agent: Wilmerhale/dc

20090242912 - Multifunctional tape: A method comprises forming elongate structures (5) on a first substrate (3), such that the material composition of each elongate structure (7) varies along its length so as to define first and second physically different sections in the elongate structures. First and second physically different devices (1,2) are then defined... Agent: Mark D. Saralino ( Sharp ) Renner, Otto, Boisselle & Sklar, LLP

20090242911 - Organic light-emitting display device: An object of the present invention is to provide an organic light-emitting display device using a number of organic light-emitting elements that emit lights of different colors, wherein the life of the organic light-emitting elements that emits light of a color having a short life can be prolonged. According to... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090242918 - High efficiency group iii nitride led with lenticular surface: A light emitting diode is disclosed that includes a conductive substrate, a bonding metal on the conductive substrate and a barrier metal layer on the bonding metal. A mirror layer is encapsulated by the barrier metal layer and is isolated from the bonding metal by the barrier layer. A p-type... Agent: Summa, Additon & Ashe, P.A.

20090242914 - Led assembly with high heat dissipating capability: An LED assembly includes a substrate and a plurality of LEDs mounted on the substrate. Each LED comprises an LED die mounted on the substrate via an adhesive, a base spacedly surrounding the LED die, a pair of leads inserted in the base to be in electrical connection with the... Agent: PCe Industry, Inc. Att. Steven Reiss

20090242919 - Light emitting device: A light emitting device includes a leadframe, a light emitting unit, a transparent encapsulant, and a fluorescent colloid layer. The light emitting unit is disposed on the leadframe. The transparent encapsulant covers the light emitting unit, wherein the transparent encapsulant has a concave on which at least one reflective surface... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090242917 - Light-emitting device including light-emitting diode: A light-emitting device includes a light-emitting diode, a red light-emitting phosphor layer, a yellow light-emitting phosphor layer, and a blue light-emitting phosphor layer. These layers are stacked in the stacking sequence of the yellow, blue, and red phosphor layers in order of increasing distance from the LED. The stacking sequence... Agent: Mcginn Intellectual Property Law Group, PLLC

20090242921 - Method for coating phosphor, apparatus to perform the method, and light emitting diode comprising phosphor coating layer: A method of forming a phosphor coating layer on a light emitting diode (LED) chip using electrophoresis includes separating phosphor particles in a suspension according to a particle size, and coating the phosphor particles on a surface of the LED chip by sequentially depositing the separated phosphor particles on the... Agent: H.c. Park & Associates, PLC

20090242916 - Method for packaging a light emitting device: A method for packaging a light emitting element includes a step of providing a carrier formed with an anode electrode and a cathode electrode, a step of providing a light emitting object by utilizing a light emitting diode chip having a positive and negative electrodes, a step of directly contacting... Agent: Rosenberg, Klein & Lee

20090242915 - Semiconductor light-emitting device: A semiconductor light-emitting device includes: a hollow body including a bottom wall and a surrounding wall cooperating with the bottom wall to define an encapsulant-receiving recess, the bottom wall being formed with a through-hole, the surrounding wall having a diffuse surface that surrounds the encapsulant-receiving recess; a heat-dissipating body provided... Agent: Rosenberg, Klein & Lee

20090242920 - Side view led package and back light module comprising the same: Disclosed is a side view LED package that can be more accurately mounted onto a surface of a substrate such as a printed circuit board without distortion includes a first portion of a body allowing light to be emitted in front thereof, the first portion having a horizontal plane formed... Agent: H.c. Park & Associates, PLC

20090242913 - Silicon based light emitting diode: Provided is a highly efficient silicon-based light emitting diode (LED) including a Distributed Bragg Reflector (DBR), an n-type doping layer, and a p-type substrate structure. The silicon-based LED includes: a substrate having a p-type mesa substrate structure; an active layer that is formed on the substrate and has a first... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090242923 - Hermetically sealed device with transparent window and method of manufacturing same: The invention is a hermetically sealed semiconductor die package wherein a surface of the die can be positioned very close to the hermetic package and a method of fabricating such a package. The invention is particularly suited to hermetically sealed circuit components, such as dies with a light emitting surface... Agent: Christopher P. Maiorana, P.C.

20090242924 - Light emitting diodes with smooth surface for reflective electrode: A light emitting diode comprising an epitaxial layer structure, a first electrode, and a second electrode. The first and second electrodes are separately disposed on the epitaxial layer structure, and the epitaxial layer structure has a root-means-square (RMS) roughness less than about 3 at a surface whereon the first electrode... Agent: Arent Fox LLP

20090242922 - Light-emitting diode lamp: A light-emitting diode (LED) lamp includes a columnar body having a plurality of heat-radiating fins, an LED supporting end, and a mounting end; a first conducting plate disposed on the LED supporting end; an LED having a first electrode in electric contact with the first conducting plate; a second conducting... Agent: Wpat, PC Intellectual Property Attorneys

20090242926 - Package for optical semiconductor element: A package for an optical semiconductor element is provided. The package includes: a stem body having a sealing hole therein; and a lead pin having a glass sealing portion which is sealed with sealing glass in the sealing hole. Characteristic impedance of the glass sealing portion is adjusted to a... Agent: Drinker Biddle & Reath (dc)

20090242927 - Semiconductor light emitting module and method for manufacturing the same: A light emitting module includes a semiconductor light source, a first lead with a bonding pad to which the light source is attached, and a second lead spaced from the first lead in a first direction contained in the plane of the first die bonding pad. The second lead includes... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20090242925 - Semiconductor light-emitting element and process for production thereof: The present invention provides a semiconductor light-emitting element comprising an electrode part excellent in ohmic contact and capable of emitting light from the whole surface. An electrode layer placed on the light-extraction side comprises a metal part and plural openings. The metal part is so continuous that any pair of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090242928 - Resin sheet for encapsulating optical semiconductor element and optical semiconductor device: The present invention provides a resin sheet for encapsulating an optical semiconductor element, the resin sheet containing an encapsulation resin layer, an adhesive resin layer, a metal layer and a protective resin layer, in which the encapsulation resin layer and the metal layer adhered onto the adhesive resin layer are... Agent: Sughrue-265550

20090242929 - Light emitting diodes with patterned current blocking metal contact: A light emitting diode including an epitaxial layer structure, a first electrode formed on the epitaxial layer structure, and a second electrode formed on the epitaxial layer structure. The first electrode has a pattern and the second electrode has a portion aligned with the pattern of the first electrode. The... Agent: Arent Fox LLP

20090242930 - Semiconductor device: A lateral high-breakdown voltage semiconductor device is provided in which the breakdown voltages of elements as a whole are improved, while suppressing increases in cell area. A track-shape gate electrode surrounds a collector electrode extending in a straight line, a track-shape emitter electrode surrounds the gate electrode, and a track-shape... Agent: Rossi, Kimms & Mcdowell LLP.

20090242931 - Semiconductor device having igbt and diode: A semiconductor device includes: a substrate; an active element cell area including IGBT cell region and a diode cell region; a first semiconductor region on a first side of the substrate in the active element cell area; a second semiconductor region on a second side of the substrate in the... Agent: Posz Law Group, PLC

20090242932 - Large-area pin diode with reduced capacitance: The invention provides a design of PIN diode having a low capacitance and a large area of effective collection of photo-generated charge. The low capacitance is obtained by replacing a continuous collector layer in the diode by a sparse array of collector disks interconnected by narrow metallic runners at a... Agent: Silber & Fridman

20090242934 - Photodiode and method of fabrication: The present invention provides a highly reliable photodiode, as well as a simple method of fabricating such a photodiode. During fabrication of the photodiode, a grading layer is epitaxially grown on a top surface of an absorption layer, and a blocking layer, for inhibiting current flow, is epitaxially grown on... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20090242933 - Semiconductor photodiode and method of manufacture thereof: A method of manufacture of an avalanche photodiode involving a step of making a recess in a top window layer of an avalanche photodiode layer stack, such that a wall surrounding the recess runs smoothly and gradually from the level of the recess to the level of the window layer.... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20090242935 - Monolithically integrated photodetectors: Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant... Agent: Wolf Greenfield & Sacks, P.C.

20090242936 - Strained ultra-thin soi transistor formed by replacement gate: A semiconductor structure is described. The structure includes a transistor formed in a semiconductor substrate, the semiconductor substrate having a semiconductor-on-insulator (SOI) layer; a channel associated with the transistor and formed on a first portion of the SOI layer; and a source/drain region associated with the transistor and formed in... Agent: International Business Machines Corporation Dept. 18g

20090242937 - Semiconductor device and manufacturing method: A semiconductor device has source and drain electrodes formed on a substrate, a gate insulation film formed on the substrate between the source and drain electrodes, and a gate electrode formed on the gate insulation film. These elements are all covered by a dielectric sub-insulation film. An opening is formed... Agent: Rabin & Berdo, PC

20090242938 - Field effect transistor: A field effect transistor formed of a semiconductor of a III group nitride compound, includes an electron running layer formed on a substrate and formed of GaN; an electron supplying layer formed on the electron running layer and formed of AlxGal-xN (0.01≦x≦0.4), the electron supplying layer having a band gap... Agent: Kubotera & Associates, LLC

20090242939 - Wafer for backside illumination type solid imaging device, production method thereof and backside illumination solid imaging device: A wafer for backside illumination type solid imaging device has a plurality of pixels inclusive of a photoelectric conversion device and a charge transfer transistor at its front surface side and a light receiving surface at its back surface side, wherein said wafer is a SOI wafer obtained by forming... Agent: Sughrue Mion, PLLC

20090242940 - Sensor device and fabrication method for the same: The sensor device includes: a converter body made of silicon in the shape of a rhombus in plan, the converter body having an opening in the shape of a hexagon in plan; a substrate for holding the converter body; a movable film formed on the opening; a converter electrode formed... Agent: Mcdermott Will & Emery LLP

20090242942 - Asymmetric source and drain field effect structure and method: A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor structure using a semiconductor substrate that includes a horizontal plateau... Agent: Scully, Scott, Murphy & Presser, P.C.

20090242941 - Structure and method for manufacturing device with a v-shape channel nmosfet: A CMOS structure includes a v-shape surface in an nMOSFET region. The v-shape surface has an orientation in a (100) plane and extends into a Si layer in the nMOSFET region. The nMOSFET gate dielectric layer is a high-k material, such as Hf02. The nMOSFET has a metal gate layer,... Agent: International Business Machines Corporation Dept. 18g

20090242943 - Semiconductor device: A semiconductor device which can prevent peeling off of a gate electrode is provided. The semiconductor device has GaN buffer layer formed on substrate 11, undoped AlGaN layer 13 formed on this buffer layer 12, drain electrode 16 and source electrode 17 formed separately on undoped AlGaN layer 13, which... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242944 - Method of forming a semiconductor device using stress memorization: A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film... Agent: Freescale Semiconductor, Inc. Law Department

20090242946 - Semiconductor device and fabrication method for the semiconductor device: A semiconductor device which could strengthen the mechanical strength of the protective film and with which packaging of the wafer level with electric high reliability is performed and a fabrication method for the semiconductor device are provided. The semiconductor device includes a semiconductor substrate; a field effect transistor including a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242947 - Semiconductor device and fabrication method for the semiconductor device: A semiconductor device and a fabrication method for the semiconductor device which can remove the sacrifice layer deposited on the semiconductor device surface in a short time and whose manufacturing yield can be improved are provided. The semiconductor device and the fabrication method for the semiconductor device includes a field... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242945 - Semiconductor device and method of fabricating the same: In a method of fabricating a semiconductor device on a substrate having a pillar pattern, a gate electrode is formed on the pillar pattern without etching the latter. A conductive pattern is filled between adjacent pillar patterns, a spacer is formed above the conductive pattern and surrounding sidewalls of each... Agent: Lowe Hauptman Ham & Berner, LLP

20090242948 - Method of forming an inverted lens in a semiconductor structure: A flat-top convex-bottom lower lens is formed by first applying a positive tone photoresist over a silicon oxide layer and an optional metallic barrier layer thereupon in a back-end-of-line (BEOL) metallization structure. The positive tone photoresist is exposed under defocused illumination conditions and/or employing a half-tone mask so that a... Agent: Scully, Scott, Murphy & Presser, P.C.

20090242950 - Active pixel sensor having two wafers: A vertically-integrated image sensor includes a sensor wafer connected to a support circuit wafer. Each pixel region on the sensor wafer includes a photodetector, a charge-to-voltage conversion mechanism, a transfer mechanism for transferring charge from the photodetector to the charge-to-voltage conversion mechanism, and a reset mechanism for discharging the charge-to-voltage... Agent: F-p Patent Legal Staff

20090242949 - Cmos image sensor with reduced dark current: A carbon-containing semiconductor layer is formed on exposed surfaces of a p-doped semiconductor layer abutting sidewalls of a shallow trench. Following formation of a dielectric layer on the carbon-containing semiconductor layer, a surface pinning layer having a p-type doping is formed underneath the carbon-containing semiconductor layer. A shallow trench isolation... Agent: Scully, Scott, Murphy & Presser, P.C.

20090242951 - Solid-state image pickup device: A solid-state image pickup device has a photoelectric conversion element that converts light incident from a first surface of a substrate into a signal charge and accumulates the signal charge, a transistor that is formed on a second surface side opposite to the first surface of the substrate and reads... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242952 - Integrated circuit including a capacitor and method: An integrated circuit including a capacitor and a method of fabricating an integrated circuit. The capacitor has a first electrode. A plurality of conductive lines is separated from each other and is configured to be held at a potential being the same for all conductive lines. A second electrode encloses... Agent: Dicke, Billig & Czaja

20090242954 - Memory device and fabrication thereof: The invention is related to a memory device, including a substrate, a capacitor which is substantially C-shaped in a cross section parallel to the substrate surface and a word line coupling the capacitor. In an embodiment, the C-shaped capacitor is a deep trench capacitor, and in alternative embodiment, the C-shaped... Agent: Quintero Law Office, PC

20090242953 - Shallow trench capacitor compatible with high-k / metal gate: Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second... Agent: International Business Machines Corporation Dept. 18g

20090242955 - Integrated circuit, memory device and methods of manufacturing the same: An integrated circuit includes: a contact structure with a first stack of at least two conductive layers, and a gate electrode with a second stack of conductive layers, the second stack of layers having the same sequence of conductive layers as the first stack.... Agent: Edell, Shapiro & Finnan, LLC

20090242957 - Atomic layer deposition processes for non-volatile memory devices: Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090242956 - Tunnel dielectrics for semiconductor devices: Tunnel dielectrics for semiconductor devices are generally described. In one example, an apparatus includes a semiconductor substrate, a first tunnel dielectric having a first bandgap coupled to the semiconductor substrate, a second tunnel dielectric having a second bandgap coupled to the first tunnel dielectric, and a third tunnel dielectric having... Agent: Cool Patent, P.C. C/o Cpa Global

20090242959 - Flash memory cell: A flash memory cell is disclosed in the specification and drawing. The flash memory cell is described and shown with at least one floating gate heavily doped with P-type ions.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090242958 - Nand-type nonvolatile semiconductor memory device: a first control gate electrode, and a first source/drain region. The select transistor includes a third insulating film on the semiconductor substrate, a fourth insulating film made of an aluminum oxide containing at least one of a tetravalent cationic element, a pentavalent cationic element, and N (nitrogen), a second control... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242960 - Semiconductor memory device and manufacturing method thereof: A semiconductor memory device includes a semiconductor substrate, a memory cell provided on the semiconductor substrate and having a stacked gate structure formed by sequentially stacking a tunnel insulation film, a charge storage layer, a block insulation film, and a control gate electrode, a first transistor having a first gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242965 - Memory cell device having vertical channel and double gate structure: A memory cell device having a vertical channel and a double gate structure is provided. More specifically, a memory cell device having a vertical channel and a double gate structure is characterized by having a pillar active region with a predetermined height, which is including a first semiconductor layer forming... Agent: Casella & Hespos

20090242964 - Non-volatile memory device: A finFET-based non-volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a portion of the fin body and... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090242967 - Non-volatile semiconductor storage device and method of manufacturing the same: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge accumulation layer formed around the first columnar... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242968 - Nonvolatile semiconductor memory device and method for manufacturing same: In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242962 - Plasma oxidation of a memory layer to form a blocking layer in non-volatile charge trap memory devices: A blocking layer of a non-volatile charge trap memory device is formed by oxidizing a portion of a charge trapping layer of the memory device. In one embodiment, the blocking layer is grown by a radical oxidation process at temperature below 500° C. In accordance with one implementation, the radical... Agent: Cypress Semiconductor Corporation

20090242961 - Recessed channel select gate for a memory device: A memory device comprising one or more recessed channel select gates and at least one charge trapping layer.... Agent: Cool Patent, P.C. C/o Cpa Global

20090242963 - Semiconductor device and method for manufacturing a semiconductor device: In a semiconductor device, the side walls are made of SiO2, SiN or SiON, and the top insulating film or gate insulating film is made of an oxide including Al, Si, and metal element M so that the number ratio Si/M is set to no less than a number ratio... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242969 - Semiconductor storage device and method of manufacturing the same: A semiconductor storage device including a semiconductor substrate including an upper surface having a plurality of trenches formed into the upper surface; a plurality of element isolation insulating films filled in each of the trenches so as to protrude upward from the upper surface of the semiconductor substrate, the element... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242966 - Vertical-type semiconductor devices: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall... Agent: Mills & Onello LLP

20090242970 - Semiconductor device, capacitor, and field effect transistor: It is made possible to provide a semiconductor device that has the effective work function of the connected metal optimized at the interface between a semiconductor and the metal. A semiconductor device includes: a semiconductor film; an oxide film formed on the semiconductor film, the oxide film including at least... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242971 - Semiconductor device and method of fabricating the same: In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between... Agent: Lowe Hauptman Ham & Berner, LLP

20090242972 - Vertical channel transistor in semiconductor device and method of fabricating the same: A method of fabricating a vertical channel transistor for a semiconductor device includes forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof; forming a first insulation layer over the active pillars to fill a gap region between... Agent: Lowe Hauptman Ham & Berner, LLP

20090242976 - Semiconductor device: The semiconductor device of the present invention includes a first conductive type semiconductor layer; a second conductive type source region formed in a surface layer portion of the semiconductor layer; a groove formed by digging in the source region from a surface thereof; an insulating film laminated on the semiconductor... Agent: Rabin & Berdo, PC

20090242977 - Semiconductor device and dc-dc converter: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor region provided in the semiconductor substrate; a first trench formed in the semiconductor region; a second trench formed in the semiconductor substrate; a trench gate electrode provided in the first trench; and a trench source electrode... Agent: Patterson & Sheridan, L.L.P.

20090242974 - Semiconductor device and method for fabricating the same: A semiconductor device includes a plurality of trench patterns formed over a substrate; gate insulation layers formed over sidewalls of the trench patterns; gate electrodes formed over the trench patterns; line patterns coupling the gate electrodes; and source and drain regions formed in upper and lower portions of the substrate... Agent: Lowe Hauptman Ham & Berner, LLP

20090242973 - Source and body contact structure for trench-dmos devices using polysilicon: A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall... Agent: Joshua D. Isenberg Jdi Patent

20090242978 - Termination structure for power devices: A semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. The termination region includes a first silicon region of a first conductivity type extending to a first... Agent: Townsend And Townsend And Crew, LLP

20090242975 - Vertical pillar transistor: A vertical pillar transistor may include a plurality of lower pillars, a plurality of upper pillars, a first insulation part, a second insulation part and a word line. The plurality of lower pillars protrudes substantially perpendicular to a substrate and is defined by a plurality of trenches. The plurality of... Agent: Harness, Dickey & Pierce, P.L.C

20090242980 - Semiconductor device including capacitor element and method of manufacturing the same: In a semiconductor device, a memory region and a logic region are provided on one silicon substrate. A trench is provided in the silicon substrate in the memory region, a memory cell transistor is provided in the memory region and a logic transistor is provided in the logic region. The... Agent: Mcginn Intellectual Property Law Group, PLLC

20090242979 - Vertical transistor of semiconductor device and method of forming the same: A vertical transistor of a semiconductor device has a channel area formed in a vertical direction to a semiconductor substrate. After semiconductor poles corresponding to the length of semiconductor channels and gate electrodes surrounding sidewalls of the semiconductor poles are formed, subsequent processes of forming silicon patterns corresponding to junction... Agent: Marshall, Gerstein & Borun LLP

20090242981 - Semiconductor device: A semiconductor device includes: an epitaxial layer; a body layer, formed in the epitaxial layer, which includes a channel region; a source layer disposed in superposition on the body layer; a gate insulator, formed on the epitaxial layer, which is in a ring shape surrounding the source layer; a gate... Agent: Ditthavong Mori & Steiner, P.C.

20090242982 - Self-aligned complementary ldmos: The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown... Agent: Hiscock & Barclay, LLP

20090242983 - Semiconductor device having a field effect transistor using a high dielectric constant gate insulating film and manufacturing method of the same: In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating... Agent: Mcdermott Will & Emery LLP

20090242984 - Semiconductor device and method of manufacturing the same: Aimed at providing a semiconductor device capable preventing transistor characteristics from departing from design characteristics, the semiconductor device of the present invention has a gate insulating film and a gate electrode positioned over a channel forming region; two second-conductivity-type, high-concentration impurity diffused layers which function as the source and drain... Agent: Mcginn Intellectual Property Law Group, PLLC

20090242987 - Double-gate semiconductor devices having gates with different work functions and methods of manufacture thereof: A double-gate FinFET and methods for its manufacture are provided. The FinFET includes first and second gates (72, 74) adjacent respective sides of the fin (20), with at least a portion of the first gate facing the fin being formed of polycrystalline silicon, and at least a portion of the... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090242988 - High frequency semiconductor circuit device: A high frequency semiconductor circuit device in which a microwave circuit can be miniaturized is provided, which includes a GaAs substrate; a plurality of FETs formed on the GaAs substrate; and a microstrip line formed on the GaAs substrate and electrically connecting FETs each other, wherein a thickness of a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242985 - Method, structure and design structure for customizing history effects of soi circuits: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed between a gate electrode and an outer portion of an active region of a FET. Also provided is a structure having a high-leakage dielectric formed... Agent: Andrew M. Calderon Greenblum & Bernstein, P.L.C

20090242986 - Multi-gate field effect transistor and method for manufacturing the same: A multi-gate field effect transistor includes: a plurality of semiconductor layers arranged in parallel on a substrate; source and drain regions formed in each of the semiconductor layers; channel regions each provided between the source region and the drain region in each of the semiconductor layers; protection films each provided... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242989 - Complementary metal-oxide-semiconductor device with embedded stressor: In one embodiment, the invention is a complementary metal-oxide-semiconductor device with an embedded stressor. One embodiment of a field effect transistor includes a silicon on insulator channel, a gate electrode coupled to the silicon on insulator channel, and a stressor embedded in the silicon on insulator channel and spaced laterally... Agent: Wall & Tong, LLP IBM Corporation

20090242990 - Semiconductor device and manufacturing method of same: A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090242991 - Semiconductor device: Aimed at reducing the area of a protective circuit in a semiconductor device provided therewith, a semiconductor device of the present invention has a first-conductivity-type well, a plurality of first diffusion layers formed in the well, a plurality of second diffusion layers formed in the well, and a diffusion resistance... Agent: Mcginn Intellectual Property Law Group, PLLC

20090242993 - Esd protection device and manufacturing method thereof: A junction forming region is formed between a drain region of a MOS structure and a device isolation region which surrounds the MOS structure and is in contact with the drain region, to form a PN junction together with the drain region. As a consequence, it is possible to adjust... Agent: Rabin & Berdo, PC

20090242992 - Inverter, logic circuit including an inverter and methods of fabricating the same: An inverter, a logic circuit including the inverter and method of fabricating the same are provided. The inverter includes a load transistor of a depletion mode, and a driving transistor of an enhancement mode, which is connected to the load transistor. The load transistor may have a first oxide layer... Agent: Harness, Dickey & Pierce, P.L.C

20090242994 - Hybrid transistor based power gating switch circuit and method: A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth.... Agent: Freescale Semiconductor, Inc. Law Department

20090242995 - Semiconductor device and method for fabricating the same: A semiconductor device includes an isolation region (11a) formed in a semiconductor substrate (10), an active region made of the semiconductor substrate (10) surrounded by the isolation region (11a) and having a trench portion, a MIS transistor of a first-conductivity type having a gate electrode (13) formed on the active... Agent: Mcdermott Will & Emery LLP

20090242996 - Soi transistor with floating body for information storage having asymmetric drain/source regions: By laterally asymmetrically defining the well dopant concentration in a floating body storage transistor, an increased well dopant concentration may be provided at the drain side, while a moderately low concentration may remain in the rest of the floating body region. Consequently, compared to conventional symmetric designs, a reduction in... Agent: Williams, Morgan & Amerson

20090242997 - Method for fabricating semiconductor structure and structure of static random access memory: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates... Agent: J C Patents, Inc.

20090242998 - Penetrating implant for forming a semiconductor device: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090242999 - Method for encapsulating a high-k gate stack by forming a liner at two different process temperatures: Encapsulation of a gate stack comprising a high-k dielectric material may be accomplished on the basis of a silicon nitride material that is deposited in a sequence of two deposition processes, in which the first process may be performed on the basis of a moderately low process temperature, thereby passivating... Agent: Williams, Morgan & Amerson

20090243000 - Method, structure and design structure for customizing history effects of soi circuits: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has... Agent: Andrew M. Calderon, Greenblum & Bernstein, P. L. C.

20090243001 - Sequential deposition and anneal of a dielectic layer in a charge trapping memory device: Deposition and anneal operations are iterated to break a deposition into a number of sequential deposition-anneal operations to reach a desired annealed dielectric layer thickness. In one particular embodiment, a two step anneal is performed including an NH3 or ND3 ambient followed by an N2O or NO ambient. In one... Agent: Cypress Semiconductor Corporation

20090243002 - Semiconductor device and method of fabricating the same: A semiconductor device according to one embodiment includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate via a gate insulating film; a first silicide layer formed on the gate electrode; a channel region formed in the semiconductor substrate below the gate electrode; source/drain regions formed in regions... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090243003 - Manufacturing method of a gas sensor integrated on a semiconductor substrate: A method manufactures a gas sensor integrated on a semiconductor substrate. The method includes: realizing a first plurality of openings in the semiconductor substrate; realizing a crystalline silicon membrane suspended on the semiconductor substrate, forming an insulating cavity buried in the substrate; realizing a second plurality of openings in the... Agent: Seed Intellectual Property Law Group PLLC

20090243006 - Electronic part with affixed mems: According to an aspect of the invention, an electronic part includes a substrate having a first planar surface, a first bump affixed to the first planar surface of the substrate, a second bump affixed to the first planar surface of the substrate a predetermined distance from the first bump, a... Agent: Arent Fox LLP

20090243004 - Integrated structure for mems device and semiconductor device and method of fabricating the same: The present invention relates to an integrated structure for a MEMS device and a semiconductor device and a method of fabricating the same, in which an etch stopping device is included on a substrate between the MEMS device and the semiconductor device for protecting the semiconductor device from lateral damage... Agent: North America Intellectual Property Corporation

20090243005 - Semiconductor physical quantity sensor and method for manufacturing the same: A method for manufacturing a semiconductor physical quantity sensor having a fixed portion, a movable portion and an output terminal includes: forming a metal layer on a semiconductor layer; forming a resist on the metal layer; forming an opening and a side etching hole in the resist; anisotropically etching the... Agent: Posz Law Group, PLC

20090243008 - Magnetoresistive element and magnetic memory: m

20090243007 - Spin-dependent tunnelling cell and method of formation thereof: A Spin-Dependent Tunnelling cell comprises a first barrier layer of a first material and a second barrier layer of a second material sandwiched between a first ferromagnetic layer and a second ferromagnetic layer. The first and second barrier layers are formed to a combined thicknesses so that a Tunnelling Magnetoresistance... Agent: Freescale Semiconductor, Inc. Law Department

20090243009 - Magnetic tunnel junction cell including multiple vertical magnetic domains: Magnetic tunnel junction cell including multiple vertical domains. In an embodiment, a magnetic tunnel junction (MTJ) structure is disclosed. The MTJ structure includes an MTJ cell. The MTJ cell includes multiple vertical side walls. Each of the multiple vertical side walls defines a unique vertical magnetic domain. Each of the... Agent: Qualcomm Incorporated

20090243010 - Thinfilm deposition method, thinfilm deposition apparatus, and thinfilm semiconductor device: A substrate holding unit, a plasma treatment chamber, and a nanoparticle supplying chamber are housed in a single chamber. The substrate holding unit holds a substrate. The plasma treatment chamber includes a gas passage for introducing a source gas to a vicinity of the substrate and a plasma generating unit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090243012 - Electromagnetic interference shield structures for semiconductor components: A microelectronic device assembly with an integrated conductive shield is disclosed herein. The microelectronic device assembly includes a semiconductor substrate, an integrated circuit carried by the semiconductor substrate, a dielectric encapsulant encasing at least a portion of the semiconductor substrate. The microelectronic device assembly also includes a conductive shield in... Agent: Perkins Coie LLP Patent-sea

20090243014 - Image sensor: Disclosed is an image sensor. The image sensor includes a substrate having photodiodes therein; a dielectric layer on the substrate; a passivation layer on the dielectric layer exposing the dielectric layer in a region corresponding to a first color filter; and a color filter layer on the exposed dielectric layer... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090243011 - Manufacturing optical mems with thin-film anti-reflective layers: In accordance with the teachings of one embodiment of the present disclosure, a method for manufacturing a semiconductor device includes forming a support structure outwardly from a substrate. The support structure has a first thickness and a first outer sidewall surface that is not parallel with the substrate. The first... Agent: Texas Instruments Incorporated

20090243013 - Semiconductor photoreceptor device: A semiconductor light detecting device includes an n-contact layer selectively disposed on an Fe—InP substrate. An optical waveguide layer is disposed on the n-contact layer and includes an n-cladding layer, a light absorption layer, and a p-cladding layer, laminated on one another over the n-contact layer, in that order. An... Agent: Leydig Voit & Mayer, Ltd

20090243015 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device, includes the steps of: forming a resin layer on an upper surface of a substrate including a photodiode such that the resin layer does not cover a light receiving region of the photodiode; forming at least one groove in the resin layer so... Agent: Sonnenschein Nath & Rosenthal LLP

20090243017 - Method of manufacturing solid state imaging device, solid state imaging device, and camera using solid state imaging device: A method of manufacturing a solid state imaging device having a photo-electric conversion portion array and a transfer electrode array, these arrays being provided in parallel to each other, upper surfaces and side wall surfaces of the transfer electrode array being covered with a light-shielding layer, and a transparent layer... Agent: Robert J. Depke Lewis T. Steadman

20090243016 - Semiconductor device: An apparatus is provided. The apparatus generally comprises a photoreceptive region and a circuit region formed in a substrate. A multilayer wiring region is then formed on the substrate over at least a portion of the circuit region. The multilayer wiring region includes a wiring layer and a light-blocking layer.... Agent: Texas Instruments Incorporated

20090243018 - Hybrid inorganic-organic polymer compositions for anti-reflective coatings: An organic-inorganic composition, which has a backbone containing —Si—O— units with chromophore groups attached directly to at least a part of the silicon atoms. The film forming composition and resulting coating properties can be tailored to suit the specific exposure wavelength and device fabrication and design requirements. By using two... Agent: Mccormick, Paulding & Huber LLP

20090243019 - Optical sensing device including visible and uv sensors: An optical sensing device includes a silicon-on-insulator (SOI) substrate a semiconductor support substrate, an insulating layer located on the semiconductor support substrate, and a semiconductor layer located on the insulating layer. The optical sensing device further includes a visible light sensor located in the semiconductor support substrate, and an ultraviolet... Agent: Volentine & Whitt PLLC

20090243020 - Producing layered structures with layers that transport charge carriers: Layered structures such as photosensing arrays include layers in which charge carriers can be transported. For example, a carrier-transporting substructure that includes a solution processing artifact can transport charge carriers that flow to or from it through charge-flow surface parts that are on electrically conductive regions of a circuitry substructure;... Agent: Leading Edge Law Group, PLC/xerox-parc

20090243021 - Isolation structures for preventing photons and carriers from reaching active areas and methods of formation: Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 μm into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching... Agent: Dickstein Shapiro LLP

20090243022 - Method of forming mask for lithography, method of forming mask data for lithography, method of manufacturing back-illuminated solid-state imaging device, back-illuminated solid-state imaging device and electronic device: A method of forming a mask for lithography includes the step of forming the mask by using reverse data in which positions of at least part of output terminals are reversed, when forming the mask for lithography used for manufacturing a back-illuminated solid-state imaging device which takes incident light from... Agent: Sonnenschein Nath & Rosenthal LLP

20090243023 - Dual seed semiconductor photodetectors: Dual seed semiconductor photodetectors and methods to fabricate thereof are described. A dual seed semiconductor photodetector is formed directly on an insulating layer on a substrate. The dual seed semiconductor photodetector includes an optical layer formed on a dual seed semiconductor layer. The dual seed semiconductor layer includes a seed... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090243024 - Wiring board and solid-state imaging device: Provided are a wiring board capable of mounting either a frontside incident type solid-state imaging element and a backside incident type solid-state imaging element and a solid-state imaging device. The wiring board 1 is a wiring board having a to-be-arranged region 1a at which the solid-state imaging element is arranged,... Agent: Drinker Biddle & Reath (dc)

20090243025 - Pixel structure with a photodetector having an extended depletion depth: An image sensor includes an imaging area that includes a plurality of pixels that are formed in a substrate layer of a first conductivity type. Each pixel includes a collection region that is formed in a portion of the substrate layer and doped with a dopant of a first conductivity... Agent: F-p, Patent Legal Staff Eastman Kodak Company

20090243026 - Schottky barrier diode and method for using the same: An intermediate metal film is formed between a Schottky electrode and a pad electrode. A Schottky barrier height between the intermediate metal film and a silicon carbide epitaxial film is equivalent to or higher than a Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film. By... Agent: The Webb Law Firm, P.C.

20090243027 - semiconductor integrated circuit device and a method of manufacturing the same: To achieve a further reduction in the size of a finished product by reducing the number of externally embedded parts, the embedding of a Schottky barrier diode which is relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. In such a case, it... Agent: Miles & Stockbridge PC

20090243028 - Capacitive isolation circuitry with improved common mode detector: An integrated circuit having voltage isolation capabilities comprising a first galvanically isolated area of the integrated circuit containing a first group of functional circuitry for processing a data stream. The first group of functional circuitry located in a substrate of the integrated circuit. Capacitive isolation circuitry located in conductive layers... Agent: Howison & Arnott, L.l.p

20090243030 - Method of forming shallow trench isolation structure: A method of fabricating an isolation structure and the structure thereof is provided. The method is compatible with the embedded memory process and provides the isolation structure with a poly cap thereon to protect the top corners of the isolation structure, without using an extra photomask.... Agent: J C Patents, Inc.

20090243029 - Method, structure and design structure for customizing history effects of soi circuits: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric formed in a divot on each side of a segmented FET comprised of active silicon islands and gate electrodes thereon, and a... Agent: Greenblum & Bernstein, P.L.C

20090243031 - Structure and method to control oxidation in high-k gate structures: In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region;... Agent: Scully, Scott, Murphy & Presser, P.C.

20090243032 - Electrical fuse structure: An e-fuse structure includes a cathode block; a plurality of cathode contact plugs on the cathode block; an anode block; a plurality of anode contact plugs on the cathode block; and a fuse link connecting the cathode block with the anode block, wherein a front row of the cathode contact... Agent: North America Intellectual Property Corporation

20090243033 - Fuse part in semiconductor device and method for forming the same: A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of... Agent: Lowe Hauptman Ham & Berner, LLP

20090243034 - Semiconductor device: A semiconductor device including a doped substrate of a first doping polarity and a doped semiconductor material of a second doping polarity. The semiconductor material is on, or in, the substrate, and the second doping polarity is opposite the first doping polarity such that the semiconductor material and the substrate... Agent: Thompson Hine L.L.P. Intellectual Property Group

20090243035 - Semiconductor device and method of manufacturing the same and semiconductor device mounting structure: In a semiconductor device that is formed by joining two semiconductor elements together to oppose device layers to each other, inductor patterns for transmitting and receiving a signal and feeding a power and bumps for connecting electrically the semiconductor elements and for supporting the inductor patterns and the semiconductor elements... Agent: Drinker Biddle & Reath (dc)

20090243038 - Method of manufacturing semiconductor device and semiconductor device: A method of manufacturing a semiconductor device has forming a capacitor having electrodes and a ferroelectric film provided therebetween above a substrate, forming a pad electrode electrically connected to one of the electrodes of the capacitor above the substrate, forming a protective film covering the pad electrode over the substrate,... Agent: Fujitsu Patent Center C/o Cpa Global

20090243039 - Mim capacitor and method for manufacturing the same: Disclosed are an MIM (Metal-Insulator-Metal) capacitor and a method of manufacturing the same. The MIM capacitor includes: a lower metal layer and a lower metal interconnection on a substrate; a barrier metal layer on the lower metal layer; an insulating layer on the barrier metal layer; an upper metal layer... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090243037 - Semiconductor device having capacitors fixed to support patterns and method for manufacturing the same: A semiconductor device containing a cylindrical shaped capacitor and a method for manufacturing the same is presented. The semiconductor device includes a plurality of storage nodes and a support pattern. The plurality of storage nodes is formed over a semiconductor substrate. The support pattern is fixed to adjacent storage nodes... Agent: Ladas & Parry LLP

20090243036 - Semiconductor devices and methods of manufacture thereof: Capacitor plates, capacitors, semiconductor devices, and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes at least one via and at least one conductive member coupled to the at least one via. The at least one conductive member comprises an enlarged region proximate the at least... Agent: Slater & Matsil LLP

20090243040 - Micro-heater arrays and pn-junction devices having micro-heater arrays, and methods for fabricating the same: Example embodiments include micro-heater arrays including first and second micro-heaters disposed perpendicular to or parallel with each other on a substrate and methods of fabricating pn junctions between first and second heating portions using the heat generated from the first and second heating portions, respectively, when applying a voltage to... Agent: Harness, Dickey & Pierce, P.L.C

20090243041 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion thereof. A trench is disposed in the workpiece extending at least through the buried layer. At least one sinker contact is disposed in... Agent: Slater & Matsil LLP

20090243042 - Lateral semiconductor device: A semiconductor device has a first main electrode and a second main electrode that are provided on a semiconductor layer. The semiconductor layer has: an n type first semiconductor region in contact with the first main electrode; a p type second semiconductor region in contact with the second main electrode;... Agent: Kenyon & Kenyon LLP

20090243043 - Growth method using nanostructure compliant layers and hvpe for producing high quality compound semiconductor materials: A method utilizes HVPE to grow high quality flat and thick compound semiconductors (15) onto foreign substrates (10) using nanostructure compliant layers. Nanostructures (12) of semiconductor materials car be grown on foreign substrates (10) by molecular beam epitaxy (MBE), chemical vapour deposition (CVD), metalorganic chemical vapour deposition (MOCVD) and hydride... Agent: Christie, Parker & Hale, LLP

20090243044 - Semiconductor wafer, semiconductor device, and method of manufacturing semiconductor device: Provided is a semiconductor wafer with a scribe line region and a plurality of element forming regions partitioned by the scribe line region, the semiconductor wafer including: conductive patterns formed in the scribe line region; and an island-shaped passivation film formed above at least a conductive pattern, which is or... Agent: Mcginn Intellectual Property Law Group, PLLC

20090243046 - Pulse-laser bonding method for through-silicon-via based stacking of electronic components: There is described a method of forming a through-silicon-via to form an interconnect between two stacked semiconductor components using pulsed laser energy. A hole is formed in each component, and each hole is filled with a plug formed of a first metal. One component is then stacked on another component... Agent: Wells St. John P.s.

20090243047 - Semiconductor device with an interconnect element and method for manufacture: A semiconductor device is provided configured to be electrically connected to another device by through silicon interconnect technology. The semiconductor device includes a semiconductor substrate with at least one through hole. A through silicon conductor extends inside the through hole from the upper side to the bottom side of the... Agent: Slater & Matsil, L.L.P.

20090243045 - Through hole vias at saw streets including protrusions or recesses for interconnection: A semiconductor package includes a semiconductor die having a contact pad formed over a top surface of the semiconductor die. The semiconductor die may include an optical device. In one embodiment, a second semiconductor die is deposited over the semiconductor die. The package includes an insulating material deposited around a... Agent: Robert D. Atkins

20090243048 - Metallic nanocrystal encapsulation: A method of forming a device includes forming protective shells about metallic nanocrystals supported by a substrate. The metallic nanocrystals having protective shells are encapsulated with a layer formed with process parameters that are not compatible with the integrity of unprotected metallic nanocrystals.... Agent: Schwegman, Lundberg & Woessner, P.A.

20090243049 - Double deposition of a stress-inducing layer in an interlayer dielectric with intermediate stress relaxation in a semiconductor device: Enhanced efficiency of a stress relaxation implantation process may be achieved by depositing a first layer of reduced thickness and relaxing the same at certain device regions, thereby obtaining an enhanced amount of substantially relaxed dielectric material in close proximity to the transistor under consideration, wherein a desired high amount... Agent: Williams, Morgan & Amerson

20090243050 - Isolation structure in memory device and method for fabricating the same: A method for fabricating an isolation structure in a memory device includes forming a first trench in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. The method also includes oxidating the surface of the first and second trenches to... Agent: Marshall, Gerstein & Borun LLP

20090243052 - Electronic device with shielding structure and method of manufacturing the same: An electronic device includes a substrate, an active circuit, and a shielding structure. The active circuit is formed on the substrate. The shielding structure is disposed surrounding the active circuit, and includes a first heavy ion-doped region, first metal stack, second heavy ion-doped region, second metal stack and top metal.... Agent: Bacon & Thomas, PLLC

20090243051 - Integrated conductive shield for microelectronic device assemblies and associated methods: Microelectronic device assemblies having integrated conductive shields are disclosed herein. The microelectronic device assemblies include a semiconductor substrate having a bond site and a solder ball electrically connected to the bond site, a dielectric sidewall at least partially encapsulating the semiconductor substrate, and a conductive shield in direct contact with... Agent: Perkins Coie LLP Patent-sea

20090243053 - Structure for reduction of soft error rates in integrated circuits: A structure for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level;... Agent: Schmeiser, Olsen & Watts

20090243054 - I/o connection scheme for qfn leadframe and package structures: Methods, systems, and apparatuses for integrated circuit packages and lead frames are provided. A quad flat no-lead (QFN) package includes a plurality of peripherally positioned pins, a die-attach paddle, an integrated circuit die, and an encapsulating material. The die-attach paddle is positioned within a periphery formed by the pins. The... Agent: Fiala & Weaver, P.l.l.c. C/o Cpa Global

20090243055 - Leadframe, semiconductor packaging structure and manufacturing method thereof: A semiconductor packaging structure includes a plurality of first inner leads, a plurality of second inner leads, a plurality of first outer leads, a plurality of stacked chips, an encapsulating body, and a plurality of wires. Wherein, a first protrusion portion is protruded from each of the first inner leads... Agent: Rosenberg, Klein & Lee

20090243056 - Chip package having asymmetric molding: A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave... Agent: J C Patents, Inc.

20090243058 - Lead frame and package of semiconductor device: A lead frame including a shield plate, a main frame, interconnection arms, support arms, and terminals is sealed with a resin mold including a base portion for embedding the shield plate and a peripheral wall for embedding the interconnection arms and support arms, thus forming a package base. The interconnection... Agent: Pillsbury Winthrop Shaw Pittman LLP

20090243057 - Semiconductor chip package assembly method and apparatus for countering leadfinger deformation: The invention provides semiconductor chip packages, tools, and methods for preventing and for correcting leadfinger deformation caused during wirebonding in semiconductor chip package manufacturing. Disclosed are improved heat blocks and methods for their use in ensuring adequate clearance between leadfingers and adjacent heat spreaders, as well as semiconductor chip package... Agent: Texas Instruments Incorporated

20090243059 - Semiconductor package structure: A semiconductor package structure includes a carrier having a plurality of leads, wherein each of the leads is composed of an inner lead and an outer lead; a chip arranged on the bottom surface of the inner leads; an electrical connecting structure and a molding component. The invention discloses that... Agent: Rosenberg, Klein & Lee

20090243061 - Complex semiconductor packages and methods of fabricating the same: Disclosed are complex semiconductor packages, each including a large power module package which includes a small semiconductor package, and methods of manufacturing the complex semiconductor packages. An exemplary complex semiconductor package includes a first package including: a first packaging substrate; a plurality of first semiconductor chips disposed on the first... Agent: Townsend And Townsend And Crew, LLP

20090243060 - Lead frame and package of semiconductor device: A lead frame including a stage and a plurality of terminals is embedded in a mold resin including a base portion for mounting a semiconductor chip (e.g. a microphone chip), a peripheral wall disposed in the periphery of the base portion, and an extension portion extended outside of the peripheral... Agent: Pillsbury Winthrop Shaw Pittman LLP

20090243062 - Ic tag and manufacturing method of the same: An IC tag comprises a substrate on which a wiring pattern is formed, an IC chip which is bonded and mounted to the substrate by bringing a bump into press-contact with the wiring pattern, a repulsive member that is arranged on the surface opposite to the surface of the substrate... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090243063 - Packaging method of micro electro mechanical system device and package thereof: Disclosed are a micro electro mechanical system (MEMS) device and a package thereof. The packaging method of a MEMS device comprises: sequentially forming a sacrificial layer, a support layer, and a block copolymer layer on a substrate on which the MEMS device is formed; self-assembling the block copolymer layer formed... Agent: The Belles Group, P.C.

20090243064 - Method and apparatus for a package having multiple stacked die: A method of manufacturing a semiconductor package involves providing a substrate having a window. The substrate may include a leadframe having half-etched leads. First and second semiconductor devices are mounted to a top surface of the substrate on either side of the window using an adhesive. A third semiconductor device... Agent: Robert D. Atkins

20090243076 - Electronic system modules and method of fabrication: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths of 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is used to fabricate the interconnection circuits. A polymer... Agent: Townsend And Townsend And Crew, LLP

20090243068 - Integrated circuit package system with non-symmetrical support structures: An integrated circuit package system including: providing a substrate with a wire-bonded die mounted thereover; mounting a first support structure and a second support structure of different size above the substrate; mounting a structure above the first support structure and the second support structure; and encapsulating the wire-bonded die, the... Agent: Law Offices Of Mikio Ishimaru

20090243069 - Integrated circuit package system with redistribution: An integrated circuit package system comprising: forming a base package having a molded top; providing a surface contact on the base package; and patterning a redistribution layer on the molded top for coupling the surface contact.... Agent: Law Offices Of Mikio Ishimaru

20090243071 - Integrated circuit package system with stacking module: An integrated circuit package system comprising: providing a module lead array; attaching a module integrated circuit adjacent the module lead array; attaching a module substrate over the module integrated circuit; and applying a module encapsulant over the module integrated circuit wherein the module lead array and the module substrate are... Agent: Law Offices Of Mikio Ishimaru

20090243070 - Integrated circuit package system with support structure under wire-in-film adhesive: An integrated circuit package in package system including: providing a substrate; mounting a wire bonded die with an active side over the substrate; connecting the active side to the substrate with bond wires; mounting a structure over the wire bonded die having a wire-in-film adhesive between the structure and the... Agent: Law Offices Of Mikio Ishimaru

20090243066 - Mountable integrated circuit package system with exposed external interconnects: The present invention provides a mountable integrated circuit package system comprising: providing an inner integrated circuit package including a first external interconnect having a shoulder; connecting an intraconnect between a second external interconnect and the shoulder; and forming an outer encapsulation over the inner integrated circuit package, the intraconnect, and... Agent: Law Offices Of Mikio Ishimaru

20090243067 - Mountable integrated circuit package system with substrate: A mountable integrated circuit package system includes: providing a substrate having an opening provided therein; providing an encapsulated integrated circuit package having an external leadfinger; mounting the encapsulated integrated circuit package by the external leadfinger proximate to the opening in the substrate; and connecting the external leadfinger and the substrate.... Agent: Law Offices Of Mikio Ishimaru

20090243075 - Mounting structure of semiconductor device and electronic apparatus using same: A mounting structure comprises: at least one semiconductor device having solder bumps as outer terminals and a flexible wiring board with wiring formed thereon. The semiconductor device is structured to be wrapped by the flexible wiring board, the mounting structure is provided with outer electrodes on both sides of the... Agent: Sughrue Mion, PLLC

20090243065 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device (100) comprises a first resin substrate (101) on which a first semiconductor chip (125) is mounted a surface thereof; a second resin substrate (111) on which a second semiconductor chip (131) is mounted on a surface thereof; and a resin base material (109), joined to a front... Agent: Smith, Gambrell & Russell

20090243074 - Semiconductor through silicon vias of variable size and method of formation: A through-silicon via structure is formed by providing a substrate having a first conductive catch pad and a second conductive catch pad formed thereon. The substrate is secured to a wafer carrier. A first etch of a first type is performed on the substrate underlying each of the first and... Agent: Freescale Semiconductor, Inc. Law Department

20090243072 - Stacked integrated circuit package system: A stacked integrated circuit package system includes: providing a base integrated circuit package, and mounting a top integrated circuit package having a top interposer and a top encapsulation with a cavity therein or the cavity as a space between top intra-stack interconnects and the top interposer, with the top interposer... Agent: Law Offices Of Mikio Ishimaru

20090243073 - Stacked integrated circuit package system: A stacked integrated circuit package system includes: providing a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity; mounting an intermediate integrated circuit package over the base interposer, and mounting a top integrated circuit package over the intermediate integrated... Agent: Law Offices Of Mikio Ishimaru

20090243077 - Integrated circuit package system with rigid locking lead: An integrated circuit package system includes: providing a protective layer having an opening; forming a conductive layer over the protective layer and filling the opening; patterning a rigid locking lead, having both a lead locking portion and a lead exposed portion, from the conductive layer; connecting an integrated circuit and... Agent: Law Offices Of Mikio Ishimaru

20090243078 - Power device packages having thermal electric modules using peltier effect and methods of fabricating the same: Provided are power device packages, which include thermal electric modules using the Peltier effect and thus can improve operational reliability by rapidly dissipating heat generated during operation to the outside, and methods of fabricating the same. An exemplary power device package includes: a thermal electric module having a first surface... Agent: Townsend And Townsend And Crew, LLP

20090243079 - Semiconductor device package: Provided is a semiconductor device package including a substrate formed of a silicon (Si)-based material. The semiconductor device package includes a first substrate which comprises first and second principal planes which are opposite each other, and a substrate body layer disposed between the first and second principal planes, the substrate... Agent: Townsend And Townsend And Crew, LLP

20090243080 - Flip chip interconnection structure with bump on partial pad and method thereof: A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed... Agent: Robert D. Atkins

20090243081 - System and method of forming a wafer scale package: A system and method for forming a wafer level package (WLP) (i.e., wafer level chip size package) is disclosed. The WLP includes a silicon integrated circuit (IC) substrate having a plurality of die pads formed on a top surface thereof and a plurality of polymer laminates positioned thereon. Each of... Agent: Ge Trading & Licensing

20090243082 - Integrated circuit package system with planar interconnect: An integrated circuit package system includes: mounting an integrated circuit die adjacent to a lead; forming a first encapsulation around and exposing the integrated circuit die and the lead; and forming a planar interconnect between the integrated circuit die and the lead with the planar interconnect on the first encapsulation.... Agent: Law Offices Of Mikio Ishimaru

20090243083 - Wafer integrated with permanent carrier and method therefor: A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first... Agent: Robert D. Atkins

20090243084 - Suspension microstructure and a fabrication method for the same: A suspension microstructure and its fabrication method, in which the method comprises the steps of: forming at least one insulation layer with inner micro-electro-mechanical structures on an upper surface of a silicon substrate, the micro-electro-mechanical structure includes at least one microstructure and a plurality of metal circuits that are independent... Agent: Dr. Banger Shia

20090243085 - Apparatus and method for attaching a heat dissipating device: A microelectronic package is provided. The microelectronic package includes a heat dissipating device having a top side and a bottom side and a thermal interface material disposed adjacent to the bottom side of the heat dissipating device. The microelectronic package also includes a patterned metal layer comprising at least two... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090243086 - Enhanced thermal dissipation ball grid array package: In a semiconductor chip, a thermal adhesive is used to bond an internal heat spreader to an active functional die. In an alternative embodiment a dummy die is place directly on top of the active functional die and a thermal adhesive is used to bond an internal heat spreader to... Agent: Conexant Systems, Inc

20090243087 - Semiconductor device and method for manufacturing same: In a DC-DC converter, a multilayer wiring layer is provided on a silicon substrate, and a control circuit configured to control an input circuit and an output circuit is formed in the silicon substrate and the multilayer wiring layer. Moreover, a sealing resin layer covering the multilayer wiring layer and... Agent: Patterson & Sheridan, L.L.P.

20090243089 - Module including a rough solder joint: A module includes a metallized substrate including a metal layer, a base plate, and a joint joining the metal layer to the base plate. The joint includes solder contacting the base plate and an inter-metallic zone contacting the metal layer and the solder. The inter-metallic zone has spikes up to... Agent: Dicke, Billig & Czaja

20090243088 - Multiple layer metal integrated circuits and method for fabricating same: A method of fabricating a plurality of layers of metal on a substrate depositing a first layer of metal on the substrate; depositing a first layer of planarization material over the substrate and first layer of metal to a depth above the top of the first layer of metal; polishing... Agent: Christopher P. Maiorana, P.C.

20090243093 - Contact structure and connecting structure: A contact structure disposed on a substrate is provided. The contact structure includes at least one pad, at least one polymer bump and at least one conductive layer. The pad is disposed on the substrate and the polymer bump is disposed on the substrate. The polymer bump has a curved... Agent: Jianq Chyun Intellectual Property Office

20090243090 - Mock bump system for flip chip integrated circuits: A mock bump system includes providing a flip chip integrated circuit having an edge and forming a mock bump near the edge.... Agent: Law Offices Of Mikio Ishimaru

20090243091 - Mock bump system for flip chip integrated circuits: A mock bump system includes: providing a first structure having an edge; and forming a mock bump near the edge.... Agent: Law Offices Of Mikio Ishimaru

20090243096 - Semiconductor device and fabrication method thereof: A semiconductor device and a method of manufacturing the same are disclosed. The method is carried out by forming solder pads on a substrate by wet etching, flipping a semiconductor chip having a plurality of connection bumps formed on an active surface of the semiconductor chip for the connection bumps... Agent: Edwards Angell Palmer & Dodge LLP

20090243092 - Semiconductor device and manufacturing method of semiconductor device: A semiconductor device includes a semiconductor element; a plate member disposed opposite to an electronic-circuit forming portion of the semiconductor element; and an elastic body arranged in a compressed state between the semiconductor element and the plate member, wherein the elastic body includes at least one first protruding portion at... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090243094 - Semiconductor device and manufacturing method thereof: The semiconductor device comprises a first area and a second area positioned adjacent to the outside of the first area, the semiconductor substrate having a main surface and side surfaces and disposed in such a manner that the main surface is positioned in the first area and each of the... Agent: Rabin & Berdo, PC

20090243097 - Semiconductor device having low dielectric constant film and manufacturing method thereof: A low dielectric constant film/wiring line stack structure made up of a stack of low dielectric constant films and wiring lines is provided in a region on the upper surface of the semiconductor substrate except for the peripheral part of this surface. The peripheral side surface of the low dielectric... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090243095 - Substrate, manufacturing method thereof, method for manufacturing semiconductor device: A substrate on which an IC element is fixed includes: a plurality of metal posts arranged in a plurality of columns in a lengthwise direction and in a plurality of rows in a crosswise direction when viewed in a plan view, the plurality of metal posts having first faces and... Agent: Oliff & Berridge, PLC

20090243100 - Methods to form a three-dimensionally curved pad in a substrate and integrated circuits incorporating such a substrate: Methods to form a three-dimensionally curved pad in a substrate and integrated circuits incorporating such a substrate are disclosed. An example method to form a three-dimensionally curved pad comprises isotropically etching a portion of a surface of a substrate to form a recess having a radial shape, forming a conductive... Agent: Texas Instruments Incorporated

20090243098 - Underbump metallurgy for enhanced electromigration resistance: A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer is formed on the metallic adhesion promotion layer,... Agent: Scully, Scott, Murphy & Presser, P.C.

20090243099 - Window type bga semiconductor package and its substrate: A window-type BGA semiconductor package is revealed, primarily comprising a substrate with a wire-bonding slot, a chip disposed on a top surface of the substrate, and a plurality of bonding wires passing through the wire-bonding slot. A plurality of plating line stubs are formed on a bottom surface of the... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090243101 - Method for forming interconnection levels of an integrated circuit: A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level comprising conductive tracks and vias separated by a porous dielectric material; (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings above portions of... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20090243102 - Method of aligning deposited nanotubes onto an etched feature using a spacer: A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched... Agent: Wilmerhale/boston

20090243103 - Synthesis of zeolite crystals and formation of carbon nanostructures in patterned structures: A method is provided for incorporating zeolite crystals in patterned structures, the zeolite crystals having pores (channels) with an orientation which is defined by the topology of the zeolite crystal type and the geometry of the patterned structure, resulting in pores parallel with the length axis of the patterned structures.... Agent: Knobbe Martens Olson & Bear LLP

20090243104 - Forming thick metal interconnect structures for integrated circuits: Embodiments of an apparatus and methods for forming thick metal interconnect structures for integrated structures are generally described herein. Other embodiments may be described and claimed.... Agent: Intel Corporation C/o Cpa Global

20090243106 - Structures and methods to enhance copper metallization: Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. The insulator includes a polymer or an insulating oxide compound. And, the inhibiting... Agent: Schwegman, Lundberg & Woessner/micron

20090243105 - Wire bonding on reactive metal surfaces of a metallization of a semiconductor device by providing a protective layer: In semiconductor devices having a copper-based metallization system, bond pads for wire bonding may be formed directly on copper surfaces, which may be covered by an appropriately designed protection layer to avoid unpredictable copper corrosion during the wire bond process. A thickness of the protection layer may be selected such... Agent: Williams, Morgan & Amerson

20090243107 - Novel approach to high temperature wafer processing: At temperatures near, and above, 385° C., gold can diffuse into silicon and into some contact materials. Gold, however, is an excellent material because it is corrosion resistant, electrically conductive, and highly reliable. Using an adhesion layer and removing gold from the contact area above and around a contact allows... Agent: Honeywell International Inc. Patent Services

20090243108 - Control of localized air gap formation in an interconnect stack: The present invention relates to a method for fabricating an interconnect stack of an integrated-circuit device. Air gaps are fabricated in the interconnect stack on one or more interconnect levels. The method comprises forming local etch vias (216, 218) between a lower etch-barrier layer (236) and an upper etch-barrier layer... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090243109 - Metal cap layer of increased electrode potential for copper-based metal regions in semiconductor devices: A conductive cap material for a copper region may be provided with enhanced etch resistivity by taking into consideration the standard electrode potential of one or more of the species contained therein. For example, instead of a conventionally used CoWP alloy, a modified alloy may be used, by substituting the... Agent: Williams, Morgan & Amerson

20090243110 - Voltage controlled oscillator: A semiconductor device includes a semiconductor substrate having an element region on a surface thereof, an active element being formed in the element region. An insulating layer is formed on the semiconductor substrate and covers the active element. An inductor is formed on the insulating layer and overlaps with the... Agent: Mcginn Intellectual Property Law Group, PLLC

20090243112 - Copper interconnection structure, semiconductor device, and method for forming copper interconnection structure: A copper interconnection structure includes an insulating layer, an interconnection and a barrier layer. The insulating layer includes silicon (element symbol: Si), carbon (element symbol: C), hydrogen (element symbol: H) and oxygen (element symbol: O). The interconnection is located on the insulating layer, and the interconnection includes copper (element symbol:... Agent: Masuvalley & Partners

20090243111 - Semiconductor substrate, electrode forming method, and solar cell fabricating method: The present invention is directed to a semiconductor substrate having an electrode formed thereon, the electrode including at least silver and glass frit, the electrode including: a multi-layered structure constituted of a first electrode layer joined directly to the semiconductor substrate, and an upper electrode layer formed of at least... Agent: Oliff & Berridge, PLC

20090243113 - Semiconductor structure: A fusible link between metallization layers of a semiconductor device comprises a tungsten plug deposited in a via interconnecting two aluminum metallization layers.... Agent: Knobbe Martens Olson & Bear LLP

20090243114 - densely packed metal segments patterned in a semiconductor die: A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the... Agent: Michael Farjami, Esq. Farjami & Farjami LLP

20090243117 - Contact structure, a semiconductor device employing the same, and methods of manufacturing the same: A contact structure that includes a first pattern formed on a substrate, wherein the first pattern has a recessed region in an upper surface thereof, a planarized buffer pattern formed on the first pattern, and a conductive pattern formed on the planarized buffer pattern.... Agent: F. Chau & Associates, LLC

20090243116 - Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics: By forming a protection layer prior to the application of the planarization layer during a dual damascene strategy for first patterning vias and then trenches, enhanced etch fidelity may be accomplished. In other aspects disclosed herein, via openings and trenches may be patterned in separate steps, which may be accomplished... Agent: Williams, Morgan & Amerson

20090243118 - Semiconductor device and manufacturing method of the same: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film... Agent: Miles & Stockbridge PC

20090243115 - Semiconductor device and method of manufacturing the same: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a memory array on a first substrate; and a peripheral circuit on a second substrate, wherein the first substrate and the second substrate may be attached to each other so that the memory array... Agent: Harness, Dickey & Pierce, P.L.C

20090243120 - Semiconductor element and semiconductor element fabrication method: A semiconductor element is provided that includes a semiconductor substrate, a circuit element disposed on the substrate, and a through-hole formed in the substrate having a stripe-like concavo-convex structure on its sidewall with stripes formed in the direction of the thickness of the semiconductor substrate.... Agent: Ratnerprestia

20090243119 - Semiconductor integrated circuit: Power wiring comprises a first-layer power wiring cluster in which VDD wiring trace and VSS wiring trace of different potentials at single trace width are arranged alternatingly; a second-layer power wiring cluster, disposed in a layer overlying the first-layer power wiring cluster, in which a VDD wiring trace and a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090243121 - Semiconductor integrated circuit and layout method for the same: A semi conductor integrated circuit includes a first via-contact configured to connect a first interconnection pattern provided for a first interconnection layer and a second interconnection pattern provided for a second interconnection layer, and a second via-contact configured to connect a third interconnection pattern provided for the first interconnection layer... Agent: Young & Thompson

20090243122 - Alignment mark for opaque layer: An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact... Agent: Texas Instruments Incorporated

20090243123 - Increasing exposure tool alignment signal strength for a ferroelectric capacitor layer: An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in... Agent: Texas Instruments Incorporated