Active solid-state devices (e.g., transistors, solid-state diodes) inventions 09/09

20090236581 - Resistance memory element, method of manufacturing resistance memory element and semiconductor memory device: A resistance memory element which memorizes a high resistance state and a low resistance state and is switched between the high resistance state and the low resistance state by an application of a voltage includes a first electrode layer of titanium nitride film, a resistance memory layer formed on the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090236582 - Phase-change ram and method for fabricating the same: A PRAM and a fabricating method thereof are provided. The PRAM includes a transistor and a data storage capability. The data storage capability is connected to the transistor. The data storage includes a top electrode, a bottom electrode, and a porous PCM layer. The porous PCM layer is interposed between... Agent: Buchanan, Ingersoll & Rooney PC

20090236583 - Method of fabricating a phase change memory and phase change memory: The present invention relates to a phase change memory and a method of fabricating a phase change memory. The phase change memory includes a heater structure disposed on a phase change material pattern, wherein the heater structure is in a tapered shape with a bottom portion contacting the phase change... Agent: North America Intellectual Property Corporation

20090236584 - Light-emitting device with enhanced luminous efficiency and method of producing the same: A light-emitting device comprises first and second dot members. The first dot member is formed so that it makes contact with the second dot member. The first dot member comprises a plurality of first quantum dot layers. Each of the plurality of first quantum dot layers comprises a plurality of... Agent: Foley & Lardner LLP

20090236585 - Nitride semiconductor light-emitting device, method of fabricating it, and semiconductor optical apparatus: A nitride semiconductor laser device has a nitride semiconductor substrate that includes a dislocation-concentrated region 102 and a wide low-dislocation region and that has the top surface thereof slanted at an angle in the range of 0.3° to 0.7° relative to the C plane and a nitride semiconductor layer laid... Agent: Morrison & Foerster LLP

20090236586 - Epitaxial material used for gan based led with low polarization effect and manufacturing method thereof: A method of manufacturing epitaxial material used for GaN based LED with low polarization effect, which includes steps of growing n-type InGaAlN layer composed of GaN buffer layer (2) and n-type GaN layer (3), low polarizing active layer composed of InGaAlN multi-quantum well structure polarized regulating and controlling layer (4)... Agent: Connolly Bove Lodge & Hutz, LLP

20090236587 - Semiconductor device including a plurality of different functional elements and method of manufacturing the same: At least first and second Si1-xGex (0≦x≦1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second Si1-xGex (0≦x≦1) layers. A lattice constant of the first Si1-xGex (0≦x≦1) layer is matched with a lattice constant of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090236588 - Nanowire-based device having isolated electrode pair: A nanowire-based device includes the pair of isolated electrodes and a nanowire bridging between respective surfaces of the isolated electrodes of the pair. Specifically, the nanowire-based device having isolated electrodes comprises: a substrate electrode having a crystal orientation; a ledge electrode that is an epitaxial semiconductor having the crystal orientation... Agent: Hewlett Packard Company

20090236590 - Light-emitting element, light-emitting device and electronic device: A light-emitting element with improved emission efficiency is provided. The light-emitting element includes a light-emitting layer in which a first light-emitting layer and a second light-emitting layer are stacked in contact with each other over an anode, and a first substance serving as an emission center substance in the second... Agent: Cook Alex Ltd.

20090236592 - Liquid crystal display device using small molecule organic semiconductor material: A liquid crystal display structure is provided. The liquid crystal display structure includes a pixel region and a thin film transistor on the substrate. The thin film transistor is adjacent to the pixel region and includes a gate electrode; a gate insulating layer having a top surface; a source electrode... Agent: Birch Stewart Kolasch & Birch

20090236591 - N,n'-bis(fluorophenylalkyl)-substituted perylene-3,4:9,10-tetracarboximides, and the preparation and use thereof: The present invention relates to N,N′-bis(fluorophenylalkyl)-substituted perylene-3,4:9,10-tetracarboximides, their preparation and their use as charge transport materials, exciton transport materials or emitter materials.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090236589 - Nitride semiconductor laminated structure and optical semiconductor device, and methods for producing the same: A nitride semiconductor laminated structure comprises: a substrate; a first p-type nitride semiconductor layer formed using an organometallic compound as a Group III element source material, a p-type impurity source material and ammonia as a Group V element source material, with the hydrogen concentration in the first p-type nitride semiconductor... Agent: Leydig Voit & Mayer, Ltd

20090236593 - Organic thin film transistor and process for manufacturing same: An organic thin film transistor includes a dielectric layer and an active layer overlapping the dielectric layer, a source contact and a drain contact arranged on a surface of the active layer opposite the dielectric layer and mutually separated by an intermediate region, the source contact and drain contact having... Agent: Hogan & Hartson LLP

20090236594 - Method for fabricating an inorganic nanocomposite: An inorganic nanocomposite is prepared by obtaining a solution of a soluble hydrazine-based metal chalcogenide precursor; dispersing a nanoentity in the precursor solution; applying a solution of the precursor containing the nanoentity onto a substrate to produce a film of the precursor containing the nanoentity; and annealing the film of... Agent: Connolly Bove Lodge & Hutz LLP

20090236597 - Process to make metal oxide thin film transistor array with etch stopping layer: The present invention generally relates to thin film transistors (TFTs) and methods of making TFTs. The active channel of the TFT may comprise one or more metals selected from the group consisting of zinc, gallium, tin, indium, and cadmium. The active channel may also comprise nitrogen and oxygen. To protect... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090236595 - Semiconductor structures with rare-earths: The present invention discloses structures to increase carrier mobility using engineered substrate technologies for a solid state device. Structures employing rare-earth compounds enable heteroepitaxy of different semiconductor materials of different orientations.... Agent: Fernandez & Associates LLP

20090236596 - Thin film field effect transistor and display: A TFT is provided which includes, on a substrate, at least a gate electrode, a gate insulating layer, an active layer containing an amorphous oxide semiconductor, a source electrode and a drain electrode, wherein a resistance layer containing an amorphous oxide and having a thickness of more than 3 nm... Agent: Moss & Burke, PLLC

20090236598 - Zno layer and semiconductor light emitting device: A ZnO layer is provided which can obtain emission at a wavelength longer than blue (e.g., 420 nm) and has a novel structure. A transition energy narrower by 0.6 eV or larger than a band gap of ZnO can be obtained by doping S into a ZnO layer.... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090236599 - Active device array substrate: An active device array substrate at least including a substrate, a plurality of pixel units, a plurality of first signal lines, a first connecting wire, a plurality of first switching devices, and a plurality of second signal lines is provided. The pixel units are disposed within an active area. One... Agent: Jianq Chyun Intellectual Property Office

20090236600 - Thin film transistor and display device: A thin film transistor is provided, which includes a gate insulating layer covering a gate electrode, a microcrystalline semiconductor layer provided over the gate insulating layer, an amorphous semiconductor layer overlapping the microcrystalline semiconductor layer and the gate insulating layer, and a pair of impurity semiconductor layers which are provided... Agent: Nixon Peabody, LLP

20090236601 - Thin film transistor: A thin film transistor includes a first insulating layer covering the gate electrode layer; source and drain regions which at least partly overlaps with the gate electrode layer; a pair of second insulating layers which is provided apart from each other in a channel length direction over the first insulating... Agent: Nixon Peabody, LLP

20090236602 - Integrated circuit, semiconductor device comprising the same, electronic device having the same, and driving method of the same: An integrated circuit mounting a DRAM which can realize high integration without complicated manufacturing steps. The integrated circuit according to the invention comprises a DRAM in which a plurality of memory cells each having a thin film transistor are disposed. The thin film transistor comprises an active layer including a... Agent: Fish & Richardson P.C.

20090236603 - Process for forming a wiring film, a transistor, and an electronic device: A wiring film having excellent adhesion and a low resistance is formed. A barrier film having copper as a main component and containing oxygen is formed on an object to form a film thereon by introducing an oxygen gas into a vacuum chamber in which the object to form a... Agent: Kratz, Quintos & Hanson, LLP

20090236606 - Dual gate layout for thin film transistor: A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090236607 - Electronic circuit: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layer is less than 1500 Å, e.g., between 100 and 750 Å. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second... Agent: Nixon Peabody, LLP

20090236605 - Tft-lcd pixel structure and manufacturing method thereof: A thin film transistor liquid crystal display (TFT-LCD) pixel structure comprising: a gate line and a gate electrode formed on a substrate; a first insulating layer, a semiconductor layer, and a doped semiconductor layer formed sequentially on the gate electrode and the gate line, wherein an isolating groove is formed... Agent: Ladas & Parry LLP

20090236604 - Thin film transistor substrates and method of manufacturing the same: A thin film transistor substrate includes a color filter layer and a gate line. The color filter layer has a reverse taper shape, which is used to pattern the gate line without a separate mask. Thus, the total number of masks used to manufacture the thin film transistor substrate can... Agent: Haynes And Boone, LLPIPSection

20090236609 - Method and apparatus for producing graphene oxide layers on an insulating substrate: In a method of making a functionalized graphitic structure, a portion of a multi-layered graphene surface extending from a silicon carbide substrate is exposed to an acidic environment so as to separate graphene layers in a portion of the multi-layered graphene surface. The portion of the multi-layered graphene surface is... Agent: Bryan W. Bockhop, Esq. Bockhop & Associates, LLC

20090236610 - Method for manufacturing a semiconductor structure, and a corresponding semiconductor structure: A method for manufacturing a semiconductor structure is provided which includes the following operations: supplying a crystalline semiconductor substrate, providing a porous region adjacent to a surface of the semiconductor substrate, introducing a dopant into the porous region from the surface, and thermally recrystallizing the porous region into a crystalline... Agent: Kenyon & Kenyon LLP

20090236608 - Method for producing graphitic patterns on silicon carbide: In a method of making a vertical graphitic path on a silicon carbide crystal having a horizontal surface, a portion of the silicon carbide crystal is removed from the horizontal surface so as to define a vertical surface that is transverse to the horizontal surface of the silicon carbide crystal.... Agent: Bryan W. Bockhop, Esq. Bockhop & Associates, LLC

20090236612 - Silicon carbide mos semiconductor device: A silicon carbide MOS semiconductor device is disclosed which suppresses degradation of efficiency percentage yield with respect to a breakdown voltage even when a surface region with a high impurity concentration is formed by ion implantation with such a high dose as required for attaining a good ohmic contact. The... Agent: Rossi, Kimms & Mcdowell LLP.

20090236611 - Silicon carbide semiconductor device and method of making the same: A silicon carbide semiconductor device provided as a semiconductor chip includes a substrate, a drift layer on the substrate, an insulation film on the drift layer, a semiconductor element formed in a cell region of the drift layer, a surface electrode formed on the drift layer and electrically coupled to... Agent: Posz Law Group, PLC

20090236613 - Semiconductor device and method of manufacturing the same: According to the present invention, a protective seal S1 for protecting a transparent member 11 is composed of an organic base 16, adhesive layers 17, and a second adhesive layer 18 having low adhesion. The adhesive layers 17 are provided only on edges corresponding, on the organic base 16, to... Agent: Steptoe & Johnson LLP

20090236614 - Tunable photonic crystal: An infrared emitter, which utilizes a photonic crystal (PC) structure to produce electromagnetic emissions with a narrow hand of wavelengths, includes a semiconductor material layer, a dielectric material layer overlaying the semiconductor material layer, and a metallic material layer having an inner side overlaying the dielectric material layer. The semiconductor... Agent: Foley & Lardner LLP

20090236617 - Led assembly incorporating a structure for preventing solder contamination when soldering electrode leads thereof together: An LED assembly includes a substrate and a plurality of LEDs mounted on the substrate. Each LED includes a base and a first and a second electrode leads inserted in the base. The first lead forms a groove in an end thereof, and the second lead forms a tab from... Agent: PCe Industry, Inc. Att. Steven Reiss

20090236616 - Led assembly with separated thermal and electrical structures thereof: An LED assembly includes a substrate and a plurality of LEDs mounted on the substrate. Each LED comprises an LED die, a base supporting the LED die thereon and thermally contacting the substrate to take heat generated by the LED die to the substrate, a pair of leads electrically connecting... Agent: PCe Industry, Inc. Att. Steven Reiss

20090236615 - Light emitting diode: A semiconductor device including a wafer-level LED includes a semiconductor structure coupled to first and second electrodes. The semiconductor includes a P-doped portion of a first layer to an N-doped portion of a second layer. The first layer includes a surface configured to emit light. The first electrode is electrically... Agent: Dicke, Billig & Czaja, PLLC

20090236618 - Light-emitting diode package and lead group structure for light-emitting diode package: A light-emitting diode package 1 of the present invention is a light-emitting diode package including: a diode group 2D made of a plurality of light-emitting diode chips 2 connected in series and a lead group 3 connected to the diode group 2D, in which the lead group 3 includes: a... Agent: Sughrue Mion, PLLC

20090236620 - Light emitting apparatus and display apparatus having the same: Disclosed are a light emitting apparatus and a display apparatus having the same. The light emitting apparatus comprises a first light emitting device which emits a light of a target color tinged with a first color, and a second light emitting device which emits a light of the target color... Agent: Birch Stewart Kolasch & Birch

20090236619 - Light emitting diodes with light filters: LED chips including an LED layer or layers capable of emitting light of a first wavelength, a light conversion layer on the LED capable of converting at least a portion of the light of a first wavelength to light of a second wavelength, and a filter layer therebetween that is... Agent: Julio Garceran Cree, Inc.

20090236621 - Low index spacer layer in led devices: A light emitting diode (LED) device having a low index of refraction spacer layer separating the LED chip and a functional layer. The LED chip has a textured light emission surface to increase light extraction from the chip. The spacer layer has an index of refraction that is lower than... Agent: Koppel, Patrick, Heybl & Dawson

20090236623 - Light emitting diode device: A light emitting diode device includes a substrate, a reflector cup, a light emitting diode chip, and a phosphor paste. The reflector cup is set on the substrate, and has a wall of a first length and a first height wherein the first length is defined by a corresponding inner... Agent: Troxell Law Office PLLC

20090236624 - Organic light emitting device and organic light emitting display apparatus comprising the same: An organic light emitting device includes an anode electrode having an improved characteristic. The organic light emitting device is constructed with a first electrode including indium tungsten oxide (IWO) so that the anode electrode can be readily patterned, an organic light emitting layer formed on the first electrode, and a... Agent: Robert E. Bushnell & Law Firm

20090236622 - White semiconductor light emitting device and method for manufacturing the same: An LED chip (2) emitting blue light is mounted on an insulating substrate (1) at both ends of which electrode films (11, 12) are formed, and a pair of electrodes of the LED chip (2) is electrically connected to the pair of electrode films (11, 12) respectively by connection means... Agent: Rabin & Berdo, PC

20090236625 - Led device with conductive wings and tabs: Apparatus for increased heat dissipation from a light-emitting diode (LED) die are provided. The apparatus may include a metal member thermally and electrically coupled to the LED die and having one or more wings for heat transfer away from the LED die and/or increased mechanical strength of the metal member.... Agent: Patterson & Sheridan, L.L.P.

20090236626 - Led lamp: An LED lamp includes a first heat sink, a second heat sink thermally contacting the first heat sink, and an LED module mounted on the first heat sink. The first heat sink comprises a plate and a plurality of first fins extending from the plate. The plate has a bare... Agent: PCe Industry, Inc. Att. Steven Reiss

20090236627 - Method of forming metal wiring: Provided is a method of forming metal wiring. The method includes forming a photosensitive film pattern on a substrate, hydrophobicizing at least part of the photosensitive film pattern, coating metal ink on the substrate having the photosensitive film pattern, forming a seed layer, and forming a metal layer. Alternatively, a... Agent: Haynes And Boone, LLPIPSection

20090236628 - Semiconductor light emitting device: A semiconductor light emitting device includes: a conductive substrate; a semiconductor light emitting layer which includes a first semiconductor layer formed on one surface of the conductive substrate and having a first conductivity type, and a second semiconductor layer formed on the first semiconductor layer and having a second conductivity... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090236630 - Nitride semiconductor light emitting device and method for fabricating the same: A nitride semiconductor light emitting device includes a nitride semiconductor multilayer film. The nitride semiconductor multilayer film is formed on a substrate and made of nitride semiconductor crystals, and includes a light emitting layer. In the nitride semiconductor multilayer film, facets of a cavity are formed, and a protective film... Agent: Mcdermott Will & Emery LLP

20090236629 - Sustrate and semiconductor light-emitting device: The present invention provides a substrate and a semiconductor light emitting device. Convexes having a curved surface are formed on the substrate. The semiconductor light emitting device comprises a substrate on which convexes having a curved surface are formed and a semiconductor layer on the substrate.... Agent: Fitch, Even, Tabin & Flannery

20090236631 - Bidirectional pnpn silicon-controlled rectifier: The present invention discloses a bidirectional PNPN silicon-controlled rectifier comprising: a p-type substrate; a N-type epitaxial layer; a P-type well and two N-type wells all formed inside the N-type epitaxial layer with the two N-type wells respectively arranged at two sides of the P-type well; a first semiconductor area, a... Agent: Rosenberg, Klein & Lee

20090236632 - Fet having high-k, vt modifying channel and gate extension devoid of high-k and/or vt modifying material, and design structure: A field effect transistor (FET) including a high dielectric constant (high-k), threshold voltage (Vt) modifying channel and a gate extension devoid of the high-k and/or Vt modifying material, and a related design structure, are disclosed. In one embodiment, a FET may include a gate having a channel region thereunder including... Agent: Hoffman Warnick LLC

20090236634 - Nitride semiconductor epitaxial wafer and nitride semiconductor device: A nitride semiconductor epitaxial wafer includes a growth substrate including a surface for growing a nitride semiconductor thereon, a first structure layer formed on the growth substrate, a dislocation propagation direction changing layer formed on the first structure layer for changing a propagation direction of a dislocation propagated in the... Agent: Mcginn Intellectual Property Law Group, PLLC

20090236633 - Sram devices utilizing strained-channel transistors and methods of manufacture: A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed... Agent: Slater & Matsil, L.L.P.

20090236635 - Wide bandgap hemts with source connected field plates: A HEMT comprising an active region comprising a plurality of active semiconductor layers formed on a substrate. Source electrode, drain electrode, and gate are formed in electrical contact with the active region. A spacer layer is formed on at least a portion of a surface of said active region and... Agent: Koppel, Patrick, Heybl & Dawson

20090236636 - Closed cell array structure capable of decreasing area of non-well junction regions: A closed cell array structure capable of decreasing area of non-well junction regions includes a plurality of closed cell units, arranged in a plane, each shaped as a polygon, and a plurality of gate windows, each formed in a corner of a closed cell unit in a gate layer without... Agent: North America Intellectual Property Corporation

20090236637 - Power and ground routing of integrated circuit devices with improved ir drop and chip performance: An integrated circuit chip with reduced IR drop and improved chip performance is disclosed. The integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of copper metal layers embedded in respective the plurality of IMD layers; a first passivation layer... Agent: North America Intellectual Property Corporation

20090236638 - Semiconductor constructions: The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The electrically conductive material can be incorporated into an electrically-grounded shield, and/or can be configured to create a magnetic field bias. Also, the conductive material... Agent: Wells St. John P.s.

20090236639 - Stacked bit line dual word line nonvolatile memory: An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090236640 - Method and structure for reducing induced mechanical stresses: Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable... Agent: Law Office Of Delio & Peterson, LLC.

20090236641 - Method of manufacturing semiconductor device for providing improved isolation between contact and cell gate electrode: A manufacture method is provided for forming a semiconductor device. The method includes: forming a plurality of gate electrodes through etching a conductive film deposited on a semiconductor substrate; forming a first nitride film to cover the gate electrodes; partially exposing the semiconductor substrate in a region between adjacent two... Agent: Mcginn Intellectual Property Law Group, PLLC

20090236642 - Transistor and cvd apparatus used to deposit gate insulating film thereof: In a transistor adapted to suppress characteristic degradation resulting from fluorine contained in a deposited film, the concentration of fluorine contained in a gate insulating film is reduced to 1.0×1020 atoms/cm3 or less. As a result, the transistor can provide excellent reliability even when it is continuously driven for a... Agent: Sharp Kabushiki Kaisha C/o Keating & Bennett, LLP

20090236645 - Cmos image sensor and method for manufacturing the same: A CIS and a method of manufacturing the same are provided. The CIS includes a device isolation layer formed on a device isolation region of a substrate of a first conductive type, the substrate including an active region and the device isolation region, the active region including a photodiode region... Agent: Jeff Lloyd Saliwanchik, Lloyd & Saliwanchik

20090236643 - Cmos image sensor and method of manufacturing: A method of manufacturing an image sensor is capable of preventing image lag and suppressing dark current by performing a substantially perfect reset process. Embodiments relate to a CMOS image sensor which includes a P−-type epi layer which is formed over a semiconductor substrate and defines a photodiode region FD,... Agent: Sherr & Vaughn, PLLC

20090236644 - High efficiency cmos image sensor pixel employing dynamic voltage supply: A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate... Agent: Scully, Scott, Murphy & Presser, P.C.

20090236646 - Field-effect transistor with spin-dependent transmission characteristics and non-volatile memory using the same: When a gate voltage VGS is applied, the Schottky barrier width due to the metallic spin band in the ferromagnetic source is decreased, and up-spin electrons from the metallic spin band are tunnel-injected into the channel region. However, down-spin electrons from the nonmagnetic contact (3b) are not injected because of... Agent: Oliff & Berridge, PLC

20090236648 - Semiconductor device: To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in... Agent: Miles & Stockbridge PC

20090236647 - Semiconductor device with capacitor: An embodiment of the invention is a semiconductor structure, comprising: a semiconductor chip at least partially embedded within a support; and a capacitor disposed outside the lateral boundary of the chip, the capacitor electrically coupled to the chip.... Agent: Infineon Technologies Ag Patent Department

20090236649 - Embedded memory device and a manufacturing method thereof: An embedded memory device solves the problem of the low reliability of the circuit due to the unstable power source. The embedded memory includes a metal-oxide semiconductor (MOS) capacitor and a metal-insulator-metal (MIM) capacitor to increase the stability of the power source ring to stabilize the voltage of the embedded... Agent: Rosenberg, Klein & Lee

20090236650 - Tantalum lanthanide oxynitride films: Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a tantalum... Agent: Schwegman, Lundberg & Woessner/micron

20090236651 - Semiconductor devices having a convex active region: Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of... Agent: Myers Bigel Sibley & Sajovec

20090236652 - Semiconductor memory device: A semiconductor memory device according to an embodiment of the present invention includes a resistance element which is constructed with a first conductor which extends in a first direction and is connected to a first contact; a second conductor which extends in said first direction and is connected to a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090236653 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and a control gate electrode. The tunnel insulating film is formed on a selected part of a surface of a semiconductor substrate. The floating gate electrode is formed on the tunnel insulating... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090236654 - Nonvolatile semiconductor storage device and method for manufacturing the same: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090236655 - Integrated circuit device gate structures: Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than... Agent: Myers Bigel Sibley & Sajovec

20090236656 - Semiconductor device having vertical channel transistor and method for fabricating the same: A semiconductor device having a substrate; a plurality of pillar structures, wherein each pillar structure includes an active pillar disposed over the substrate; a gate electrode surrounding an outer wall of the active pillar; an interlayer dielectric (ILD) layer insulating adjacent pillar structures; a gate contact penetrating the ILD layer... Agent: Lowe Hauptman Ham & Berner, LLP

20090236657 - Impact ionization devices and methods of making the same: Impact ionization devices including vertical and recessed impact ionization metal oxide semiconductor field effect transistor (MOSFET) devices and methods of forming such devices are disclosed. The devices require lower threshold voltage than conventional MOSET devices while maintaining a footprint equal to or less than conventional MOSFET devices.... Agent: Trask Britt, P.C./ Micron Technology

20090236658 - Array of vertical trigate transistors and method of production: An array of vertical trigate transistors and method of production are disclosed. One embodiment provides an array of selection transistors for selecting one of a plurality of memory cells. A selection transistor is a vertical trigate transistor.... Agent: Dicke, Billig & Czaja

20090236660 - Insulated-gate field-effect transistor and method of making the same: An IGFET that can be turned off when a reverse voltage is applied. Included is a semiconductor substrate having formed therein an n-type drain region, p-type first body region, p−-type second body region, n-type first source region, and n+-type second source region. Trenches etched in the substrate receive gate electrodes... Agent: Woodcock Washburn LLP

20090236659 - Isolation structure for semiconductor device with multiple terminals: A semiconductor device has a first region (10) and a second region (20), gate trenches (50) being formed in paid first and second regions including insulated gates to control conduction between source regions (42) and a common drain region (40) through a body region separated into first (34) and second... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090236661 - Dmos-transistor having improved dielectric strength of drain source voltages: A DMOS-transistor having enhanced dielectric strength includes a first well region. A highly doped source region is located in the first well region and is complementarily doped thereto. A highly doped bulk connection region is located in the first well region and has the same type of doping as the... Agent: Stevens & Showalter LLP

20090236662 - Guard ring structures for high voltage cmos/low voltage cmos technology using ldmos (lateral double-diffused metal oxide semiconductor) device fabrication: A semiconductor structure. The semiconductor structure includes a semiconductor substrate, a first transistor on the semiconductor substrate, and a guard ring on the semiconductor substrate. The semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface. The guard ring includes a semiconductor... Agent: Schmeiser, Olsen & Watts

20090236663 - Hybrid orientation substrate with stress layer: A hybrid orientation substrate includes a base substrate having a first orientation, a first surface layer having a first orientation disposed on the base substrate in a first region, and a second surface layer disposed on the base substrate in a second region. The second surface layer has an upper... Agent: HorizonIPPte Ltd

20090236664 - Integration scheme for constrained seg growth on poly during raised s/d processing: A method for constraining lateral growth of gate caps formed during an epitaxial silicon growth process to achieve raised source/drain regions on poly silicon is presented. The method is appropriate for integration into a manufacturing process for integrated circuit semiconductor devices. The method utilizes selective etch processes, dependant upon the... Agent: Larson Newman & Abel, LLP

20090236666 - Integrated circuitry: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The... Agent: Wells St. John P.s.

20090236665 - Semiconductor device and fabrication method thereof: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A... Agent: Quintero Law Office, PC

20090236667 - Semiconductor device comprising isolation trenches inducing different types of strain: By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately... Agent: Williams, Morgan & Amerson

20090236668 - Method to improve writer leakage in sige bipolar device: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein,... Agent: Hitt Gaines, PC Lsi Corporation

20090236669 - Metal gate transistor and polysilicon resistor and method for fabricating the same: A method for fabricating metal gate transistors and a polysilicon resistor is disclosed. First, a substrate having a transistor region and a resistor region is provided. A polysilicon layer is then formed on the substrate to cover the transistor region and the resistor region of the substrate. Next, a portion... Agent: North America Intellectual Property Corporation

20090236671 - High voltage-resistant semiconductor device and method of manufacturing high voltage-resistant semiconductor device: High voltage-resistant semiconductor devices adapted to control threshold voltage by utilizing threshold voltage variation caused by plasma damage resulting from the formation of multilayer wiring, and a manufacturing method thereof. Exemplary high voltage-resistant semiconductor devices include a plurality of MOS transistors having gate insulating films not less than about 350... Agent: Taft, Stettinius & Hollister LLP

20090236670 - Semiconductor device and a manufacturing process thereof: A semiconductor device has a plurality of drain metal blocks, a plurality of source metal blocks, a plurality of polysilicon strips, a first source metal strip, a first drain metal strip, and a plurality of first conductive wires. Each of the source metal blocks is disposed between two of the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090236673 - Method for suppressing layout sensitivity of threshold voltage in a transistor array: A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of interstitial atoms adjacent such surfaces, thus minimizing variations in threshold voltage of transistors within... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20090236672 - Semiconductor device: A semiconductor device includes a plurality of metal-insulator-semiconductor (MIS) transistors formed on a surface portion of a semiconductor substrate; and an isolation region isolating each of element regions of the MIS transistors, the isolation region including a first isolation region formed with a coating type insulating film embedded in a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090236674 - Mos transistor and manufacturing method thereof: Disclosed are a MOS transistor having a low resistance ohmic contact characteristic and a manufacturing method thereof capable of improving a drive current of the MOS transistor. A gate oxide layer, a gate electrode, and a spacer are formed on a silicon substrate, and a silicon carbide layer is deposited... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090236675 - Self-aligned field-effect transistor structure and manufacturing method thereof: A self-aligned field-effect transistor (FET) is provided. The self-aligned FET includes a substrate, a dielectric layer, conductive electrodes, and a carbon nanotube. A patterned back-gated conductive electrode is disposed in the substrate. The dielectric layer is disposed on the substrate. The conductive electrodes are disposed on the dielectric layer and... Agent: Jianq Chyun Intellectual Property Office

20090236676 - Structure and method to make high performance mosfet with fully silicided gate: The present invention in one embodiment provides a method of producing a device including providing a semiconducting device including a gate structure including a silicon containing gate conductor atop a substrate; forming a metal layer on at least the silicon containing gate conductor; and directing chemically inert ions to impact... Agent: Scully, Scott, Murphy & Presser, P.C.

20090236677 - Micro electro-mechanical sensor (mems) fabricated with ribbon wire bonds: A micro electro-mechanical sensor is provided. The micro electro-mechanical sensor includes a substrate, and a conducting plane disposed on the substrate. A conducting via is disposed on the substrate, such as adjacent to the conducting plane. A plurality of ribbon conductors are disposed over the conducting plane and electrically connected... Agent: Jackson Walker (conexant)

20090236678 - Sensor device and production method therefor: A sensor device having small variations in sensor characteristics and improved resistance to electrical noise is provided. This sensor device has a sensor unit, which is provided with a frame having an opening, a movable portion held in the opening to be movable relative to the frame, and a detecting... Agent: Cheng Law Group, PLLC

20090236679 - Schottky diode structures having deep wells for improving breakdown voltages: An integrated circuit structure includes a semiconductor substrate; a well region of a first conductivity type over the semiconductor substrate; a metal-containing layer on the well region, wherein the metal-containing layer and the well region form a Schottky barrier; an isolation region encircling the metal-containing layer; and a deep-well region... Agent: Slater & Matsil, L.L.P.

20090236680 - Semiconductor device with a semiconductor body and method for its production: A semiconductor device with a semiconductor body and method for its production is provided. The semiconductor body includes drift zones of epitaxially grown semiconductor material of a first conduction type. The semiconductor body further includes charge compensation zones of a second conduction type complementing the first conduction type, which are... Agent: Dicke, Billig & Czaja

20090236681 - Semiconductor device and fabrication method thereof: A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding... Agent: Quintero Law Office, PC

20090236682 - Layer stack including a tungsten layer: A method for producing a layer stack includes providing a tungsten layer, depositing an oxidation barrier layer that immunizes the tungsten layer against oxidation on top of the tungsten layer, and depositing a cap layer on top of the oxidation barrier layer. An integrated circuit is also described.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090236683 - Isolation structures for integrated circuits: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall... Agent: Patentability Associates

20090236684 - Method of fabricating a semiconductor device having first and second trenches using non-concurrently formed hard mask patterns: A semiconductor device comprising a trench device isolation layer and a method for fabricating the semiconductor device are disclosed. The method comprises forming a plurality of first trenches on a first region of a semiconductor substrate, filling the first trenches with a first insulation material to form first device isolation... Agent: Volentine & Whitt PLLC

20090236685 - Embedded interconnects, and methods for forming same: The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive interconnect structure that is embedded in the isolation region... Agent: Scully, Scott, Murphy & Presser, P.C.

20090236686 - Semiconductor device and method of forming ubm fixed relative to interconnect structure for alignment of semiconductor die: A semiconductor device is made by forming a first conductive layer over a temporary carrier. A UBM layer is formed over the temporary carrier and fixed in position relative to the first conductive layer. A conductive pillar is formed over the first conductive layer. A semiconductor die is mounted to... Agent: Robert D. Atkins

20090236687 - Fuse of semiconductor device and method for forming the same: A method for forming a fuse of a semiconductor device includes performing an ion-implanting process at sides of a fuse blowing region of a metal fuse, thereby increasing the concentration of impurity ions of a thermal transmission path region. In a subsequent laser blowing process, as a result of the... Agent: Marshall, Gerstein & Borun LLP

20090236688 - Semiconductor device having fuse pattern and methods of fabricating the same: A semiconductor device includes a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and... Agent: Marger Johnson & Mccollom, P.C.

20090236689 - Integrated passive device and method with low cost substrate: According to one aspect of the present invention, a method of forming a microelectronic assembly, such as an integrated passive device (72), is provided. An insulating initial dielectric layer (32) comprising charge trapping films of, for example, aluminum nitride or silicon nitride or silicon oxide or a combination thereof, is... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20090236690 - Wire bond and redistribution layer process: A semiconductor device comprises a copper redistribution line, a copper inductor and aluminum wire bond pads and the integration of the resulting device with an integrated circuit on a single chip, resulting in the decreased size of the chip.... Agent: Pillsbury Winthrop Shaw Pittman LLP

20090236691 - Deep trench (dt) metal-insulator-metal (mim) capacitor: A deep trench metal-insulator-metal (MIM) capacitor in an SOI-type substrate. In the deep trench, a layer of TiN, followed by a layer of high-k dielectric, followed by a second layer of TiN. The resulting capacitor is completely buried below the SOI layer, thereby allowing for subsequent structures to be placed... Agent: International Business Machines Corporation Dept. 18g

20090236692 - Rc filtering device having air gap construction for over voltage protection: The present invention relates to a RC filtering device, consists of: a lower substrate, a first intermediate substrate, a second intermediate substrate and an upper substrate. On top surface of the lower substrate is a cross form electrode layer. At both ends of the electrode layer in one direction forms... Agent: Lowe Hauptman Ham & Berner, LLP

20090236694 - Method of manufacturing iii-nitride crystal, and semiconductor device utilizing the crystal: The present III-nitride crystal manufacturing method, a method of manufacturing a III-nitride crystal (20) having a major surface (20m) of plane orientation other than {0001}, designated by choice, includes: a step of slicing III-nitride bulk crystal (1) into a plurality of III-nitride crystal substrates (10p), (10q) having major surfaces (10pm),... Agent: Judge Patent Associates

20090236693 - Planarization of gan by photoresist technique using an inductively coupled plasma: Films of III-nitride for semiconductor device growth are planarized using an etch-back method. The method includes coating a III-nitride surface having surface roughness features in the micron range with a sacrificial planarization material such as an appropriately chose photoresist. The sacrificial planarization material is then etched together with the III-nitride... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP

20090236695 - Semiconductor wafer with a heteroepitaxial layer and a method for producing the wafer: A multilayer semiconductor wafer has a substrate wafer having a first side and a second side; a fully or partially relaxed heteroepitaxial layer deposited on the first side of the substrate wafer; and a stress compensating layer deposited on the second side of the substrate wafer. The multilayer semiconductor wafer... Agent: Brooks Kushman P.C.

20090236696 - Semiconductor wafer with a heteroepitaxial layer and a method for producing the wafer: A multilayer semiconductor wafer has a substrate wafer having a first side and a second side; a fully or partially relaxed heteroepitaxial layer deposited on the first side of the substrate wafer; and a stress compensating layer deposited on the second side of the substrate wafer. The multilayer semiconductor wafer... Agent: Brooks Kushman P.C.

20090236697 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a super junction region that has a first-conductivity-type first semiconductor pillar region and a second-conductivity-type second semiconductor pillar region alternately provided on the semiconductor substrate. The first semiconductor pillar region and the second semiconductor pillar region in a termination region have a lamination form resulting from... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090236698 - Method of fabricating a semiconductor device: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate,... Agent: Fish & Richardson P.C.

20090236699 - Discreet placement of radiation sources on integrated circuit devices: An integrated circuit and methods of forming and using the integrated circuit. The circuit includes: a radiation-emitting layer over a selected region of a top surface of an integrated circuit chip, the radiation emitting layer comprising a first polymer or resin and a first radioactive material, the region smaller than... Agent: Schmeiser, Olsen & Watts

20090236700 - Semiconductor device and manufacturing method of the same: A semiconductor device includes a wiring board, a semiconductor element mounted on the wiring board, a sealing resin configured to cover the semiconductor element, a ground electrode having an end connected to a wiring layer of the wiring board and an exposing part exposed at a surface of the sealing... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090236701 - Chip arrangement and a method of determining an inductivity compensation structure for compensating a bond wire inductivity in a chip arrangement: A chip arrangement is disclosed. The chip arrangement includes a first chip, a first bond wire having an inductive element and coupled with the first chip at its one end and an inductivity compensation structure including a first conductive plate coupled with the first bond wire at the other end... Agent: Davidson Berquist Jackson & Gowdey LLP

20090236703 - Chip package structure and the method thereof: A chip package structure includes a chip-placed frame that having an adhesive layer thereon; a chip includes a plurality of pads on an active surface thereon, and is provided on the adhesive layer; a package structure is covered around the four sides of the chip-placed frame, and the height of... Agent: Sinorica, LLC

20090236702 - Sip substrate: Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect... Agent: Hiscock & Barclay, LLP

20090236704 - Integrated circuit package system with isolated leads: An integrated circuit package system comprising: forming a finger; forming a die pad adjacent the finger; applying a fill material around the finger and the die pad; forming a cavity in the finger and fill material; and attaching an integrated circuit die over the die pad adjacent the finger with... Agent: Law Offices Of Mikio Ishimaru

20090236705 - Apparatus and method for series connection of two die or chips in single electronics package: An apparatus and method for a two semiconductor device package where the semiconductor devices are connected in electrical series. The first device is mounted P-side down on an electrically conductive substrate. Non-active area on the P side is isolated from the electrically conductive substrate. The second device is mounted P-side... Agent: Mckee, Voorhees & Sease, P.L.C

20090236707 - Electronic devices with enhanced heat spreading: An electronic device with enhanced heat spread. A printed circuit board is disposed in a casing and includes a first metal ground layer, a second metal ground layer, and a metal connecting portion. The first metal ground layer is opposite the second metal ground layer. The metal connecting portion is... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090236706 - Semiconductor chip package: A semiconductor chip package comprises a lead frame having a chip carrier having a first surface and an opposite second surface. A first semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the first semiconductor chip has an area larger that that of... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090236708 - Semiconductor package having a bridged plate interconnection: A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, and a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metallized source contacts. A bridged source plate interconnection has a bridge portion, valley portions disposed on either side of... Agent: Schein & Cai LLP James Cai

20090236710 - Col semiconductor package: A Chip-On-Lead (COL) semiconductor package is revealed, primarily comprising a plurality of leadframe's leads each having a carrying bar, a finger and a connecting portion connecting the carrying bar to the finger. A chip has a back surface attached to the carrying bars and is electrically connected to the fingers... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090236712 - Ic package having reduced thickness: An IC package having reduced thickness includes a lead frame, a chip, and a plurality of bonding wires. The lead frame includes a front side, a rear side, a plurality of pins located on the front side, and a hollow portion formed on the lead frame. The chip is larger... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20090236711 - Method of making and designing lead frames for semiconductor packages: A lead frame with patterned conductive runs on the top surface to accept a wire bonded or flip-chip or COL configuration is disclosed. The top pattern is completed and the bottom is etched away creating cavities. The cavities are filled with a pre-mold material that lend structural support of the... Agent: Cesari And Mckenna, LLP

20090236714 - Robust leaded molded packages and methods for forming the same: A method for making a flip chip in a leaded molded package is disclosed. In some embodiments, the method includes using a leadframe structure including a die attach region and leads. The die attach region includes depressions proximate the inner portions of the leads, and an aperture in the die... Agent: Townsend And Townsend And Crew, LLP

20090236709 - Semiconductor chip package: A semiconductor chip package is disclosed. The semiconductor chip package comprises a lead frame having a chip carrier, wherein the chip carrier has a first surface and an opposite second surface. A semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the semiconductor... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090236713 - Semiconductor integrated circuit package and method of packaging semiconductor integrated circuit: In a method of packaging a semiconductor IC, a tape is attached to a back surface of a lead frame array, and the lead frame array is held between an upper mold chase and a lower mold chase of a mold, with the back surface of the lead frame array... Agent: Freescale Semiconductor, Inc. Law Department

20090236716 - Rectifying diode package structure: A rectifying diode package structure includes a base which has a holding deck to hold a diode chip and a protective portion on the perimeter of the base to form sealing space filled by a filling material to seal the diode chip in an integrated manner. The diode chip has... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090236715 - Semiconductor package structure with laminated interposing layer: The invention relates to microelectronic semiconductor chip assemblies having vertically stacked layers. In a disclosed example of a preferred embodiment, a vertically stacked semiconductor chip assembly includes a first semiconductor chip affixed to the surface of a substrate. A laminated interposing layer therebetween includes a first adhesive material and a... Agent: Texas Instruments Incorporated

20090236717 - Organic electronic component with dessicant-containing passivation material: The invention relates to an organic electronic component, such as e.g. an organic light diode or an organic solar cell with structures made of passivation material, the passivation material comprising at least one dessicant.... Agent: Gibson & Dernier L.L.P.

20090236720 - Integrated circuit package system with step mold recess: An integrated circuit package system includes: providing a stackable integrated circuit package system having a base encapsulation and a recess therein; stacking a top integrated circuit package system, having a top encapsulation with a protruding portion, with the stackable integrated circuit package system with the protruding portion aligned and matched... Agent: Law Offices Of Mikio Ishimaru

20090236723 - Integrated circuit packaging system with package-in-package and method of manufacture thereof: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate, having a component side and a system side; mounting a first integrated circuit die on the component side of the package substrate; mounting a second integrated circuit die on the component side of the package... Agent: Law Offices Of Mikio Ishimaru

20090236719 - Package in package system incorporating an internal stiffener component: The present invention is a package-in-package system, comprising: providing a bottom internal stacking module incorporating a semiconductor die and a package substrate, attaching an internal stiffening module with a die receptacle on the bottom internal stacking module, and attaching a top internal stacking module incorporating a semiconductor die and a... Agent: Law Offices Of Mikio Ishimaru

20090236718 - Package-on-package system with internal stacking module interposer: A package-on-package system includes: forming a first integrated circuit package including second top electrical contacts and first external electrical contacts on opposite sides thereof; forming an internal stacking module interposer including first top electrical contacts and base electrical connectors on opposite sides thereof; attaching the internal stacking module interposer to... Agent: Law Offices Of Mikio Ishimaru

20090236721 - Semiconductor device and manufacturing method thereof: A semiconductor device in accordance with one embodiment of the invention can include a substrate onto which a wiring pattern is formed. In addition, the semiconductor device can include a plurality of semiconductor packages. Each semiconductor package can include a lead frame that is coupled to an electrode of a... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090236722 - Semiconductor memory card and semiconductor memory device: A semiconductor memory card includes a wiring board having an outer shape where a cut-out portion is provided at a first long-edge. A second surface of the wiring board includes connection pads disposed along a portion except the cut-out portion of the first long-edge. A memory device is mounted on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090236724 - Ic package with wirebond and flipchip interconnects on the same die with through wafer via: Integrated circuit dies, integrated circuit packages, and methods for assembling the same are provided. An integrated circuit package includes a substrate, an integrated circuit die, a plurality of electrically conductive bump interconnects, an electrically conductive material, and one or more bond wires. The electrically conductive bump interconnects mount a first... Agent: Fiala & Weaver, P.l.l.c. C/o Cpa Global

20090236726 - Package-on-package semiconductor structure: A semiconductor package that includes a substrate having first and second major surfaces is presented. The package includes a plurality of landing pads and a semiconductor die disposed on the first major surface. A molded cap is disposed on the first surface to encapsulate the die and substrate. The landing... Agent: HorizonIPPte Ltd

20090236725 - Solder preform and electronic component: A solder preform according to the present invention has a variation in the size of high melting point metal particles which is at most 20 micrometers when the metal particle diameter is 50 micrometers, and an alloy layer of the high melting point metal particles and the main component of... Agent: Posz Law Group, PLC

20090236729 - Melting temperature adjustable metal thermal interface materials and packaged semiconductors including thereof: A melting temperature adjustable metal thermal interface material (TIM) and a packaged semiconductor including thereof are provided. The metal TIM includes about 20-98 wt % of In, about 0.03-4 wt % of Ga, and at least one element of Bi, Sn, Ag and Zn. The metal TIM has an initial... Agent: Jianq Chyun Intellectual Property Office

20090236728 - Semiconductor device: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface... Agent: Juan Carlos A. Marquez C/o Stites & Harbison PLLC

20090236727 - Wiring substrate and method of manufacturing the same, and semiconductor device and method of manufacturing the same: A wiring substrate is provided. The wiring substrate includes a multilayer wiring structure and a stiffener. The multilayer wiring structure includes: a plurality of insulating layers; a plurality of wiring patterns; and a plurality of chip mounting pads which are electrically connected to the wiring patterns and on which a... Agent: Drinker Biddle & Reath (dc)

20090236730 - Die substrate with reinforcement structure: Various semiconductor chip package substrates with reinforcement and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a package substrate that has a first side and a second side opposite to the first side. The first side has a central... Agent: Timothy M Honeycutt Attorney At Law

20090236731 - Stackable integrated circuit package system: A stackable integrated circuit package system including mounting an integrated circuit device over a package carrier, mounting a stiffener over the package carrier and mounting a mountable package carrier over the stiffener with a vertical gap between the integrated circuit device and the mountable package carrier.... Agent: Law Offices Of Mikio Ishimaru

20090236732 - Thermally-enhanced multi-hole semiconductor package: A thermal-enhanced multi-hole semiconductor package is revealed, primarily comprising a substrate with a plurality of alignment holes, a chip disposed on the substrate, an internal heat sink attached to the chip, and an encapsulant. The internal hear sink has a plurality of alignment bars and a heat dissipation surface. The... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090236733 - Ball grid array package system: A ball grid array package system comprising: forming a package base including: fabricating a heat spreader having an access port, attaching an integrated circuit die to the heat spreader, mounting a substrate around the integrated circuit die, and coupling an electrical interconnect between the integrated circuit die and the substrate;... Agent: Law Offices Of Mikio Ishimaru

20090236736 - Microelectronic devices and methods for manufacturing microelectronic devices: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such method includes forming a plurality of through holes in a substrate with the through holes arranged in arrays, and attaching a plurality of singulated microelectronic dies to the substrate with an active side of... Agent: Perkins Coie LLP Patent-sea

20090236734 - Semiconductor device with cross-talk isolation using m-cap and method thereof: A semiconductor device is made by forming an oxide layer over a substrate and forming a first conductive layer over the oxide layer. The first conductive layer is connected to ground. A second conductive layer is formed over the first conductive layer as a plurality of segments. A third conductive... Agent: Robert D. Atkins

20090236735 - Upgradeable and repairable semiconductor packages and methods: A semiconductor device package includes a carrier, one or more semiconductor devices on the carrier, and a redistribution element above the uppermost of the one or more semiconductor devices. The redistribution element includes an array of contact pads that communicate with each semiconductor device of the package. The package may... Agent: Trask Britt, P.C./ Micron Technology

20090236737 - Rf transistor output impedance technique for improved efficiency, output power, and bandwidth: An RF/microwave circuit is configured to eliminate the physical constraint that requires a sacrifice of one output series inductor wirebond for each shunt inductor wirebond. The circuit employs a multi-level metalized substrate as part of its output impedance matching network. The lower level of the multi-level substrate serves as an... Agent: Fountain Law Group, Inc.

20090236741 - Conductive structure of a chip and method for manufacturing the same: A conductive structure of a chip and a method for manufacturing the conductive structure are provided. An under bump metal (UBM) is formed on the redistribution layer (RDL) by performing an electroless plating process. Subsequently, the solder bump is formed on the under bump metal for electrical connection. Thus, the... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090236738 - Semiconductor device and method of forming oxide layer on signal traces for electrical isolation in fine pitch bonding: A semiconductor device has a semiconductor die with a solder bump formed on its surface. A contact pad is formed on a substrate. A signal trace is formed on the substrate. The pitch between the contact pad and signal trace is less than 150 micrometers. An electroless surface treatment is... Agent: Robert D. Atkins

20090236739 - Semiconductor package having substrate id code and its fabricating method: A semiconductor package with a substrate ID code and its manufacturing method are revealed. A circuit and a solder mask are formed on the bottom surface of a substrate where the solder mask covers most of the circuit and a circuit-free zone of the substrate. A chip is disposed on... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090236740 - Window ball grid array package: A WBGA (window ball grid array) semiconductor package includes a substrate having a slot as a window for a chip. The slot has four straight sections and four rounded corners respectively interconnecting adjacent two straight sides. Each rounded corner has a radius satisfying the minimum distance between the pads and... Agent: Birch Stewart Kolasch & Birch

20090236742 - Wire bonding over active circuits: A semiconductor device includes a semiconductor die mounted over a package substrate. The die has a bond pad located thereover. A stud bump consisting substantially of a first metal is located on the bond pad. A wire consisting substantially of a different second metal is bonded to the stud bump.... Agent: Lsi Corporation

20090236743 - Programmable resistive ram and manufacturing method: Programmable resistive RAM cells have a resistance that depends on the size of the contacts. Manufacturing methods and integrated circuits for lowered contact resistance are disclosed that have contacts of reduced size.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090236745 - Adhesion to copper and copper electromigration resistance: The present invention relates to the improved adhesion between a patterned conductive metal layer, usually a copper layer, and a patterned barrier dielectric layer. The structure with the improved adhesion comprises an adhesion layer between a patterned barrier dielectric layer and a patterned conductive metal layer. The adhesion layer improves... Agent: Air Products And Chemicals, Inc. Patent Department

20090236746 - Semiconductor device and method for fabricating semiconductor device: A semiconductor device includes a contact plug electrically connected to a semiconductor substrate; a first barrier metal film with a columnar crystal structure arranged in contact with the semiconductor substrate at least on a bottom surface side of the contact plug; an amorphous film made of a material of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090236744 - Semiconductor device and method of producing the same: A semiconductor device having a copper interconnection with high electromigration resistance is provided. A semiconductor device of the present invention includes an interconnection layer formed by forming a groove or a hole in an insulating film formed on a substrate, forming a barrier layer on the resulting substrate, forming a... Agent: Nixon & Vanderhye, PC

20090236747 - Semiconductor device and method for fabricating the same: A multilevel interconnect structure in a semiconductor device comprises a first insulating layer (2) formed on a semiconductor wafer (1), a Cu interconnect layer (4) formed on the first insulating layer (2), a second insulating layer (6) formed on the Cu interconnect layer (4), and a metal oxide layer (5)... Agent: Staas & Halsey LLP

20090236748 - Semiconductor device and method of manufacturing a semiconductor device: A semiconductor device may include the following. A diffusion barrier formed over a semiconductor substrate having a conductive layer. An etching stop layer formed over a diffusion barrier. Inter-metal dielectric (IMD) layers (e.g. having via holes formed over an etching stop layer and trenches wider than the via holes). Metal... Agent: Sherr & Vaughn, PLLC

20090236749 - Electronic device and manufacturing thereof: One aspect is a method including providing a carrier having a first conducting layer, a first insulating layer over the first conducting layer, and at least one through-connection from a first face of the first insulating layer to a second face of the first insulating layer; attaching at least two... Agent: Dicke, Billig & Czaja

20090236750 - Package structure in which coreless substrate has direct electrical connections to semiconductor chip and manufacturing method thereof: A package structure in which a coreless substrate has direct electrical connections to a semiconductor chip and a manufacturing method thereof are disclosed. The method includes the following steps: providing a metal carrier board having a cavity; placing a chip having a plurality of electrode pads on an active surface... Agent: Bacon & Thomas, PLLC

20090236755 - Chip package structure: A chip package structure is provided. The chip package structure comprises a first substrate, a second substrate and a plurality of chips. Therein, one of the chips is connected to the first substrate and electrically connected to the first substrate through a via hole of the first substrate. Thereby, the... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090236753 - Integrated circuit package system for stackable devices: An integrated circuit package system includes: providing a lower interposer substrate with lower exposed conductors; attaching a die over the lower interposer substrate; applying a stack encapsulant over the die and the lower interposer substrate having the lower exposed conductors partially exposed adjacent the stack encapsulant; and attaching an upper... Agent: Law Offices Of Mikio Ishimaru

20090236754 - Integrated circuit package system with stacking module: An integrated circuit package system includes: providing a module substrate having dimension predetermined for attachment adjacent a device; attaching a module die adjacent the module substrate; and applying a module molding material cantilevered from the module substrate and over the module die.... Agent: Law Offices Of Mikio Ishimaru

20090236751 - Integrated circuit package system with support structure for die overhang: An integrated circuit package system including: providing a substrate having a support mounted thereover; mounting an integrated circuit die above the substrate; mounting a wire-bonded die offset above the integrated circuit die creating an overhang supported by the support; connecting the wire-bonded die to the substrate with bond wires; and... Agent: Law Offices Of Mikio Ishimaru

20090236752 - Package-on-package system with via z-interconnections: A package-on-package system includes: providing an interposer substrate; mounting a base substrate under the interposer substrate and having a first integrated circuit die connected thereto; forming an encapsulant between the interposer substrate and the base substrate, the encapsulant encapsulating the first integrated circuit die; and forming a via z-interconnection extending... Agent: Law Offices Of Mikio Ishimaru

20090236756 - Flip chip interconnection system: A flip chip interconnection system includes: providing a conductive lead coated with a protective coating; forming a groove through the protective coating to the conductive lead for controlling solder position on a portion of the conductive lead; and attaching a flip chip having a solderable conductive interconnect to the portion... Agent: Law Offices Of Mikio Ishimaru

20090236757 - Semiconductor device and method for manufacturing: A semiconductor device and method for manufacturing. One embodiment includes a carrier, a structured layer arranged over the carrier and a semiconductor chip applied to the structured layer. The structured layer includes a first structure made of an elastic material and a second structure made of an adhesive material.... Agent: Dicke, Billig & Czaja

20090236758 - Semiconductor module: A semiconductor module has a plurality of semiconductor devices arranged on a substrate and mutually connected by signal bus wiring lines. Each pair of first semiconductor devices are connected to each other by the signal bus wiring lines, skipping a second semiconductor device located between the pair of first semiconductor... Agent: Young & Thompson

20090236759 - Curable silicone rubber composition and semiconductor device: A curable silicone rubber composition, comprising: (A) an organopolysiloxane containing two or more alkenyl groups within each molecule, (B) an organohydrogenpolysiloxane having two or more hydrogen atoms bonded to silicon atoms within each molecule, (C) a metal-based condensation reaction catalyst, (D) a platinum group metal-based addition reaction catalyst, and (E)... Agent: Birch Stewart Kolasch & Birch

20090236760 - Substrate for a display panel, and a display panel having the same: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is... Agent: Sharp Kabushiki Kaisha C/o Keating & Bennett, LLP

20090230377 - Phase change materials for applications that require fast switching and high endurance: A memory device utilizing a phase change material as the storage medium, the phase change material based on antimony as the solvent in a solid solution; wherein the memory device further includes a means for heating the phase change material.... Agent: Leander F. Aulisio

20090230375 - Phase change memory device: A semiconductor device is provided which includes a substrate having a dielectric layer formed thereon, a heating element formed in the dielectric layer, a phase change element formed on the heating element, and a conductive element formed on the phase change element. The phase change element includes a substantially amorphous... Agent: Haynes And Boone, LLPIPSection

20090230376 - Resistive memory devices: Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. In an embodiment, a bit line is formed of copper using a damascene technique, and when the copper bit line, a copper stud may be formed around the copper... Agent: Myers Bigel Sibley & Sajovec

20090230378 - Resistive memory devices: Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. An insulating layer enclosing a resistive memory element and an insulating layer enclosing a conductive line connected with the resistive memory element have different stresses, hardness, porosity degrees, dielectric... Agent: Myers Bigel Sibley & Sajovec

20090230379 - Integrated circuit, method of manufacturing an integrated circuit, and memory module: According to one embodiment of the present invention, an integrated circuit including a plurality of memory cells is provided. Each memory cell includes a resistivity changing memory element which includes a top electrode, a bottom electrode, and resistivity changing material being disposed between the top electrode and the bottom electrode.... Agent: Slater & Matsil, L.L.P.

20090230380 - Methods for formation of substrate elements: The present invention relates to methods of forming substrate elements, including semiconductor elements such as nanowires, transistors and other structures, as well as the elements formed by such methods.... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090230381 - Alingap led having reduced temperature dependence: To increase the lattice constant of AlInGaP LED layers to greater than the lattice constant of GaAs for reduced temperature sensitivity, an engineered growth layer is formed over a substrate, where the growth layer has a lattice constant equal to or approximately equal to that of the desired AlInGaP layers.... Agent: Philips Intellectual Property & Standards

20090230382 - Iii-v semiconductor core-heteroshell nanocrystals: The present invention provides a core/multishell semiconductor nanocrystal comprising a core and multiple shells, which exhibits a type-I band offset and high photoluminescence quantum yield providing bright tunable emission covering the visible range from about 400 nm to NIR over 1600 nm.... Agent: The Nath Law Group

20090230386 - Benzobisthiazole compound, benzobisthiazole polymer, organic film including the compound or polymer and transistor including the organic film: A benzobisthiazole compound having a specific formula, and a benzobisthiazole polymer having a specific benzothiazole structure. An organic film including the benzobisthiazole polymer, the benzobisthiazole compound and/or a polymer obtained from the benzobisthiazole compound. An organic thin-film transistor including an organic semiconductor layer including the organic film; a pair of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090230388 - Composition for producing organic insulator comprising an organic-inorganic metal hybrid material: A composition for producing an organic insulator is provided which comprises an organic-inorganic hybrid material (as defined). The hybrid material shows high solubility in organic solvents and monomers, and superior adhesion to substrates. In addition, the hybrid material displays a high dielectric constant and a high degree of crosslinking. Based... Agent: Harness, Dickey & Pierce, P.L.C

20090230387 - Organic semiconductor material, organic semiconductor thin film and organic semiconductor device: where each of R1 to R10 may be independently the same substituents or different substituents but all of R1, R4, R5, R6, R9 and R10 may never be hydrogen atoms at the same time, and where each of R1 to R10 is at least one kind of substituent selected from... Agent: K&l Gates LLP

20090230385 - Organic thin film transistor and method of manufacturing the same: Disclosed are an organic thin film transistor and a method of manufacturing the same. The organic thin film transistor includes a gate electrode, an insulating layer, an organic semiconductor layer, a protective layer, and source and drain electrodes. The insulating layer is on the gate electrode, and the organic semiconductor... Agent: H.c. Park & Associates, PLC

20090230383 - Passive matrix organic light emitting diode display device: A passive matrix organic light emitting diode display device comprises a plurality of vertical organic light emitting transistors, each having a first collector, a first grid/base, and a first emitter. Therein, the first collectors are electrically connected and arranged parallelly to form a plurality of first scan units, and the... Agent: Juan Carlos A. Marquez C/o Stites & Harbison PLLC

20090230384 - Vertical organic light emitting transistor assembly and horizontal organic light emitting transistor assembly: A vertical organic light emitting transistor assembly and-a horizontal organic light emitting transistor assembly are provided. The vertical organic light emitting transistor assembly comprises a first/second vertical transistor and a first/second organic light emitting diode perpendicularly integrated with the first/second vertical transistor, respectively. The horizontal organic light emitting transistor assembly... Agent: Juan Carlos A. Marquez C/o Stites & Harbison PLLC

20090230389 - Atomic layer deposition of gate dielectric layer with high dielectric constant for thin film transisitor: Embodiments of a thin film transistor with an atomic layer deposition gate dielectric layer having a high dielectric constant and a zinc indium oxide channel are disclosed.... Agent: Hewlett Packard Company

20090230392 - Organic electroluminescent display device and method of producing the same: An organic electroluminescent display device in which a plurality of light-emitting cells each having an organic electroluminescent portion are arranged on a substrate, wherein, for each of the light-emitting cells, a first transistor which controls energization on the organic electroluminescent portion, and a second transistor which switches a signal to... Agent: Sughrue-265550

20090230391 - Resistance storage element and method for manufacturing the same: A method for manufacturing a resistance storage element includes forming a lower electrode layer over a semiconductor substrate, forming a transition metal film over the lower electrode layer, forming an upper electrode layer over the transition metal film, and supplying oxygen contained in the lower electrode layer or the upper... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090230390 - Thin film transistor and display: A thin film transistor capable of reliably preventing the entry of light into an active layer, and a display including the thin film transistor are provided. A thin film transistor includes: a gate electrode; an active layer; and a gate insulating film arranged between the gate electrode and the active... Agent: Sonnenschein Nath & Rosenthal LLP

20090230393 - Diode: In a pn junction diode having a conductivity modulating element provided on a first principal surface of a semiconductor substrate, when an impurity concentration of a p type impurity region is lowered to shorten a reverse recovery time, hole injection is suppressed, thereby causing a problem that a forward voltage... Agent: Morrison & Foerster LLP

20090230399 - Active matrix substrate and its manufacturing method: An active matrix substrate with a high aperture ratio is provided, which is capable of preventing electrical short circuits between pixel electrodes and auxiliary capacitive electrodes. Gate lines and auxiliary capacitive electrodes are formed on an insulated substrate. The auxiliary capacitive electrodes have holes formed therethrough. To cover the gate... Agent: Buchanan, Ingersoll & Rooney PC

20090230397 - Display device and manufacturing method thereof: A display device includes a TFT substrate in which a plurality of first TFT elements each having an active layer of an amorphous semiconductor and a plurality of second TFT elements each having an active layer of a polycrystalline semiconductor are disposed on a surface of an insulating substrate, wherein... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090230394 - Image sensor array with conformal color filters: An image sensor pixel includes a photo-sensor region, a microlens, a first color filter layer, and a second color filter layer. The photo-sensor region is disposed within a semiconductor die. The microlens is disposed on the semiconductor die in optical alignment with the photo-sensor region. The first color filter layer... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090230395 - Thin film transistor substrate and method for manufacturing the same: A thin film transistor substrate and a method for manufacturing the same are provided. The thin film transistor substrate has a display area and a pad area defined in the vicinity of the display area, and includes a signal line formed in the display area and a signal pad formed... Agent: Haynes And Boone, LLPIPSection

20090230396 - Thin-film transistor substrate and display device having the same: Provided are a thin-film transistor (TFT) substrate and a display device having the same. In the TFT substrate and the display device having the same, first and second drain electrodes of first and second TFTs connected to first and second pixel electrodes, respectively, are vertically bent a plurality of times.... Agent: Haynes And Boone, LLPIPSection

20090230398 - Thin-film transistor substrate and method of repairing the same: A thin-film transistor substrate includes; gate lines which extend in a first direction, the gate lines including a first gate line and a second gate line, the first gate line disposed adjacent to and previous to the second gate line, data lines which are insulated from the gate lines and... Agent: Cantor Colburn, LLP

20090230400 - Thin film transistor and fabricating method thereof: A method for fabricating a thin film transistor is described. The method includes: providing a substrate; forming a sacrificial layer on the substrate; forming a polysilicon pattern layer on the substrate to surround the sacrificial layer; forming a gate insulation layer to cover at least the polysilicon pattern layer; forming... Agent: Jianq Chyun Intellectual Property Office

20090230402 - Display apparatus and method of manufacturing the same: A display apparatus including a first substrate including a pixel area; a gate line disposed on the first substrate; a data line disposed on the first substrate and insulated from the gate line; an insulating layer pattern interposed between the gate line and the data line in an area where... Agent: Cantor Colburn, LLP

20090230403 - Dual gate layout for thin film transistor: A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090230401 - Liquid crystal display device and method of manufacturing the same: A liquid crystal display device includes a gate line placed above a substrate, a gate insulating layer to cover the gate line, a source line placed above the gate insulating layer, an interlayer insulating layer to cover the source line, a comb-shaped or slit-shaped pixel electrode electrically connected a drain... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090230405 - Diode having schottky junction and pn junction and method for manufacturing the same: A manufacturing method of a diode includes: forming a P type semiconductor film on a N type semiconductor layer with a crystal growth method; forming a first metallic film on the P type semiconductor film so that the first metallic film contacts the P type semiconductor film with an ohmic... Agent: Posz Law Group, PLC

20090230406 - Homoepitaxial growth of sic on low off-axis sic wafers: A wafer including a SiC substrate having a surface that is inclined relative to a (0001) basal plane at an angle higher than 0.1 degree but less than 1 degree, a SiC homoepitaxial device layer, and a SiC homoepitaxial boundary layer having a thickness up to 1 μm arranged between... Agent: Venable LLP

20090230404 - Semiconductor device and manufacturing method therefor: MOSFET (30) is provided with SiC film (11). SiC film (11) has a facet on its surface, and the length of one period of the facet is 100 nm or more, and the facet is used as channel (16). Further, a manufacturing method of MOSFET (30) includes: a step of... Agent: Fish & Richardson P.C. Citigroup Center

20090230407 - Led device and method for fabricating the same: An LED device has a substrate, an N-type semiconductor layer formed on the substrate, a light-emitting layer on the N-type semiconductor layer, a P-type semiconductor layer on the light-emitting layer and a transparent electrode layer formed on the P-type semiconductor layer. A top surface of the transparent electrode layer is... Agent: Rabin & Berdo, PC

20090230408 - Optical device and method for manufacturing the same: An optical device includes a semiconductor substrate including a device region formed thereon, the device region including at least one of a light-receiving region and a light-emitting region; a light-transmissive flattening film covering the device region, and including a first concave portion located in a region on an outer side... Agent: Mcdermott Will & Emery LLP

20090230411 - Interdigitated multiple pixel arrays of light-emitting devices: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the... Agent: Gates & Cooper LLP Howard Hughes Center

20090230410 - Led package and method of manufacturing the same: The present invention relates to light emitting diode (LED) packages and methods of manufacturing the same, and more particularly, to an LED package and a method of manufacturing the same that can reduce a variation of color coordinates of mass-produced LED packages.... Agent: Mcdermott Will & Emery LLP

20090230409 - Underfill process for flip-chip leds: An underfill technique for LEDs uses compression molding to simultaneously encapsulate an array of flip-chip LED dies mounted on a submount wafer. The molding process causes liquid underfill material (or a softened underfill material) to fill the gap between the LED dies and the submount wafer. The underfill material is... Agent: Philips Intellectual Property & Standards

20090230412 - Electronic displays using optically pumped luminescent semiconductor nanocrystals: A multicolor electronic display is based on an array of luminescent semiconductor nanocrystals. Nanocrystals which emit light of different colors are grouped into pixels. The nanocrystals are optically pumped to produce a multicolor display. Different sized nanocrystals are used to produce the different colors. A variety of pixel addressing systems... Agent: Townsend And Townsend And Crew, LLP

20090230413 - Semiconductor light emitting device and method for manufacturing the same: A semiconductor light emitting device includes a semiconductor light source, a resin package surrounding the semiconductor light source, and a lead fixed to the resin package. The lead is provided with a die bonding pad for bonding the semiconductor light source, and with an exposed surface opposite to the die... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20090230416 - Al-ni-b alloy material for reflective film: With respect to a reflection-type display device, an Al-based alloy material for a reflective film, which has excellent reflective characteristics and can be directly bonded to a transparent electrode layer such as ITO and IZO is provided. The present invention is Al—Ni—B alloy material for a reflective film, comprising aluminum... Agent: Roberts & Roberts, LLP Attorneys At Law

20090230414 - Led light engine kernel and method of making the kernel: A light engine kernel for a light emitting diode (LED) includes a solid body of transparent material having an index of refraction of at least 1.5. The body has a domed, light-emitting top that is an inverted parabola of revolution, a reflective sidewall that is a compound parabolic concentrator (CPC),... Agent: Osram Sylvania Inc

20090230419 - Light emitting device: The present invention provides a light emitting device which comprises a blue light emitting diode, and at least an orthosilicate based phosphor for emitting light ranging from a green to yellow regions and a nitride or oxynitride based phosphor for emitting light in a red region over the light emitting... Agent: H.c. Park & Associates, PLC

20090230418 - Light emitting diode package and method of manufacturing the same: There is provided a light emitting diode package and a method of manufacturing the same in which a light emitting diode chip is separated from phosphors, and a phosphor area is variable in shape to improve thermal balance and luminous efficiency. A light emitting diode package according to an aspect... Agent: Mcdermott Will & Emery LLP

20090230417 - Light emitting diode package structure and method for fabricating the same: The present invention discloses a light emitting diode (LED) package structure, which includes a carrier, a first protrusion, a LED chip, and an adhesion layer. The first protrusion is disposed on the carrier and has a first opening to expose the carrier, wherein the first protrusion is formed by a... Agent: Jianq Chyun Intellectual Property Office

20090230415 - Organic light emitting element and method of manufacturing the same: The present invention relates to an organic light emitting element comprising: a first light emitting unit comprising a light emitting layer between a pair of electrodes; and a second light emitting unit comprising a light emitting layer between a pair of electrodes. In the organic light emitting element, one electrode... Agent: Greenblum & Bernstein, P.L.C

20090230420 - Housing body and method for production thereof: A package body (1) with an upper side (2), with an underside (22), opposite from the upper side (2), and with a side surface, which connects the upper side (2) and the underside (22) and is provided as a mounting surface (19), the package body (1) having a plurality of... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090230423 - Reinforced chip package structure: A reinforced chip package structure includes a light emitting element, a base, and a package member. The base has a base deck and a jutting bearing deck on the base deck to hold the light emitting element. The base deck and the bearing deck are interposed by an elevation difference... Agent: Ching-ling Huang

20090230424 - Semiconductor light emitting device and method for manufacturing the same: A light emitting device includes a semiconductor light emitting element, a first lead including an element mount portion on which the semiconductor light emitting element is mounted, and a second lead electrically connected to the semiconductor light emitting element. The light emitting device further includes a resin package covering the... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20090230422 - Semiconductor light-emitting element and method for producing the same: A semiconductor light-emitting element includes, a first semiconductor layer, a second semiconductor layer, a light-emitting layer provided between the first semiconductor layer and the second semiconductor layer, a first electrode connected to the first semiconductor layer, and a second electrode provided on the second semiconductor layer. A side of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090230421 - Semiconductor package structure, lead frame and conductive assembly for the same: A light emitting diode package structure, and a lead frame and a conductive assembly for the same are described. The light emitting diode package structure includes a conductive assembly, a semiconductor chip, and a package body. The conductive assembly includes a chip support and a bonding support. The chip support... Agent: Rosenberg, Klein & Lee

20090230425 - Water-barrier encapsulation method: The present invention generally relates to organic light emitting diode (OLED) structures and methods for their manufacture. To increase the lifetime of an OLED structure, an encapsulating layer may be deposited over the OLED structure. The encapsulating layer may fully enclose or “encapsulate” the OLED structure. The encapsulating layer may... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090230426 - Integrated esd protection device: An integrated electrostatic discharge (ESD) device includes a first ESD structure coupled to a pad terminal of the integrated ESD device and a second ESD structure coupled to a ground terminal of the integrated ESD device. The integrated ESD device also comprises a diffusion region that is shared by each... Agent: Texas Instruments Incorporated

20090230427 - Semiconductor devices having tensile and/or compressive stress and methods of manufacturing: Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. The structure includes a gate stack comprising an oxide layer, a polysilicon layer and sidewalls with adjacent spacers. The structure further includes an epitaxially grown straining material directly on the polysilicon layer and... Agent: Greenblum & Bernstein, P.L.C

20090230428 - Devices using abrupt metal-insulator transition layer and method of fabricating the device: The abrupt metal-insulator transition device includes: an abrupt metal insulator transition material layer including an energy gap of less than or equal to 2 eV and holes within a hole level; and two electrodes contacting the abrupt metal-insulator transition material layer. Here, each of the two electrodes is formed by... Agent: Ladas & Parry LLP

20090230429 - Field effect transistor: A field effect transistor (100) exhibiting good performance at high voltage operation and high frequency includes a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and... Agent: Young & Thompson

20090230430 - Field effect transistor: A field effect transistor includes a layer structure made of compound semiconductor (111) provided on a semiconductor substrate (110) made of GaAs or InP, as an operation layer, and employs a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a... Agent: Young & Thompson

20090230431 - Semiconductor device and manufacturing method thereof: The present invention has as an objective to provide: a semiconductor device to satisfy both of the trade-off characteristic advantages of the HBT; and the HFET and a manufacturing method thereof. The semiconductor device in the present invention is an HBT and HFET integrated circuit. The HBT includes a sub-collector... Agent: Greenblum & Bernstein, P.L.C

20090230432 - Hybrid substrates and method of manufacture: A hybrid substrate circuit on a common substrate is disclosed. A first circuit formed in a first semiconductor material is isolated via a buried oxide layer from a second circuit formed in a second semiconductor material. The first and second circuits may include CMOS, HEMTs, P-HEMTs, HBTs, radio frequency circuits,... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20090230433 - Nitride semiconductor device: A nitride semiconductor device includes an n-type layer made of a group III nitride semiconductor and a layer made of a group III nitride semiconductor containing a p-type impurity laminated and formed in contact with the n-type layer, and Al is contained in a portion of the n-type layer in... Agent: Rabin & Berdo, PC

20090230434 - Semiconductor memory device: A semiconductor memory device comprises a semiconductor substrate; a memory block formed on the semiconductor substrate and including plural stacked cell array layers of cell arrays each comprising a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090230435 - Semiconductor memory device: A semiconductor memory device comprises a semiconductor substrate; a plurality of memory cell arrays stacked on the semiconductor substrate, each memory cell array including a plurality of first lines paralleled with each other, a plurality of second lines paralleled with each other and formed crossing the first lines, and a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090230436 - Cmos image sensor with improved fill-factor and reduced dark current: A photosensor and an imaging array utilizing the same are disclosed. The photosensor includes a light conversion region that has separate charge storage regions. The light conversion region includes a plurality of separate charge storage regions within a doped region, each charge collection region being doped such that the mobile... Agent: The Law Offices Of Calvin B. Ward

20090230437 - Semiconductor range-finding element and solid-state imaging device: A part of a semiconductor layer directly under a light-receiving gate electrode functions as a charge generation region, and electrons generated in the charge generation region are injected into a part of a surface buried region directly above the charge generation region. The surface buried region directly under a first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090230441 - Device and method for switching electric signals and powers: A device for switching an electric signal having a first member having a p-doped area with a first terminal and an n-doped area with a second terminal and a second member coupled to the first member to cause a mechanical deformation of the first member in an area of a... Agent: Glenn Patent Group

20090230438 - Selective nitridation of trench isolation sidewall: A method is provided of forming a trench isolation region adjacent to a single-crystal semiconductor region for a transistor. Such method can include, for example, recessing a single-crystal semiconductor region to define a first wall of the semiconductor region, a second wall remote from the first wall and a plurality... Agent: International Business Machines Corporation Dept. 18g

20090230442 - Semiconductor apparatus and manufacturing method of the same: Provided is a semiconductor apparatus including a substrate region, an active region on the substrate region, a gate pattern on the active region, and first and second impurities-doped regions along both edges of the active region that do not overlap the gate pattern. The length of the first and second... Agent: Harness, Dickey & Pierce, P.L.C

20090230440 - Single event transient hardened majority carrier field effect transistor: Described herein is a majority carrier device. Specifically, an exemplary device may comprise source, channel, and drain regions in a thin semiconductor layer, and the source, channel, and drain region may all share a single doping type of varying concentrations. Further, the device may comprise an insulating layer above the... Agent: Honeywell International Inc. Patent Services

20090230439 - Strain bars in stressed layers of mos devices: A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further... Agent: Slater & Matsil, L.L.P.

20090230444 - Cmos image sensor configured to provide reduced leakage current: A complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) includes a semiconductor substrate including a photodiode therein as a light sensing unit. A floating diffusion region of a first conductivity type is provided in the semiconductor substrate, and is configured to receive charges generated in the photodiode. A power supply voltage region... Agent: Myers Bigel Sibley & Sajovec

20090230443 - Radiation imaging apparatus and radiation imaging system: A radiation imaging apparatus comprises a pixel region, on an insulating substrate 100, including a plurality of pixels arranged in a matrix, each pixel having a conversion element 101 that converts radiation into electric charges and a switching element 102 connected to the conversion element 101. The conversion element 101... Agent: Fitzpatrick Cella Harper & Scinto

20090230445 - Magnetic memory devices including conductive capping layers: A magnetic memory device includes a first magnetic layer having opposing sidewalls, a tunnel barrier layer on the first magnetic layer, the tunnel barrier layer having a top surface and having opposing sidewalls aligned with the opposing sidewalls of the first magnetic layer, and a second magnetic layer on the... Agent: Myers Bigel Sibley & Sajovec

20090230446 - Semiconductor device and bypass capacitor module: A semiconductor device includes an Si substrate having a first surface provided with semiconductor elements, such as a CMOS transistor and a diode, and a second surface opposite to the first surface. On one of the first and the second surfaces, a bypass capacitor is formed. The bypass capacitor includes... Agent: Collard & Roe, P.C.

20090230447 - Semiconductor device and method for manufacturing the same: A semiconductor device may include a capacitor and a transistor on a silicon-on-insulator (SOI) substrate and a method for manufacturing the semiconductor device may include forming such a structure. A semiconductor device, formed on a silicon-on-insulator structure including first and second silicon layers and a insulating layer buried between the... Agent: Marshall, Gerstein & Borun LLP

20090230448 - Semiconductor integrated circuit device and manufacture thereof: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may... Agent: Mattingly & Malur, P.C.

20090230449 - Semiconductor storage device: A non-volatile semiconductor storage device has: a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series; and a capacitor element area including capacitor elements. Each of the memory strings includes: a plurality of first conductive layers laminated on a substrate; and a plurality of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090230450 - Non-volatile semiconductor storage device: A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090230452 - Semiconductor device and method for manufacturing the same: A semiconductor device which has a semiconductor substrate, an isolation insulating film formed in the semiconductor substrate, a conductive pattern formed over the semiconductor substrate and the isolation insulating film, so that a side face of the conductive pattern is formed over the isolation insulating film, and an insulating film... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090230451 - Semiconductor device capable of suppressing short channel effect and method of fabricating the same: A semiconductor device includes a semiconductor substrate including at least one memory channel region and at least one memory source/drain region, the memory channel region and the memory source/drain region being arranged alternately, and at least one word line on the memory channel region, wherein the memory source/drain region has... Agent: Lee & Morse, P.C.

20090230453 - Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode,... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090230454 - Memory array with a pair of memory-cell strings to a single conductive pillar: Memory arrays and methods of forming memory arrays are disclosed. One such memory array has a first string of serially-coupled first memory cells and a second string of serially-coupled second memory cells sharing a single conductive pillar which forms a channel for both strings of serially-coupled memory cells. For example,... Agent: Leffery Jay & Polglaze, P.A. Attn: Tod A. Myrum

20090230456 - Semiconductor device: A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer.... Agent: Lee & Morse, P.C.

20090230455 - Structure and method for manufacturing memory: The present invention provides a memory device including at least two of a first dielectric on a semiconductor substrate; a floating gates corresponding to each of the at least two gate oxides; a second dielectric on the floating gates; a control gate conductor formed atop the second gate oxide; source... Agent: Scully, Scott, Murphy & Presser, P.C.

20090230459 - Non-volatile semiconductor memory device and method of manufacturing the same: A non-volatile semiconductor memory device includes a memory string which is electrically rewritable and includes a plurality of memory cells connected in series. The memory string includes a plurality of first conductive layers which are extended parallel to a substrate and laminated; a first semiconductor layer which is formed so... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090230458 - Non-volatile semiconductor storage device and method of manufacturing the same: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a columnar semiconductor layer extending in a direction perpendicular to a substrate; a plurality of conductive layers formed at a sidewall of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090230460 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory of an aspect of the present invention including a memory cell which has a first gate insulating film, a charge storage layer, a block insulating film, and a first gate electrode on the block insulating film, a first transistor which has a second gate insulating film... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090230457 - Semiconductor device and method of forming the same: A semiconductor device includes a plurality of transistors disposed on a semiconductor substrate, a device isolation layer disposed around the transistors, a guard ring disposed to surround the device isolation layer and the transistors, and a guard region disposed between adjacent transistors.... Agent: Mills & Onello LLP

20090230461 - Cell device and cell string for high density nand flash memory: The invention relates a cell device and a cell string for high density flash memory. The cell string includes a plurality of cell devices and switching devices connected to ends of the plurality of cell devices. The cell device includes a semiconductor substrate, an insulating film, a charge storage node... Agent: The Nath Law Group

20090230462 - Non-volatile semiconductor storage device and method of manufacturing the same: Each of the memory strings includes: a first columnar semiconductor layer extending in a vertical direction to a substrate; a plurality of first conductive layers formed to sandwich an insulation layer with a charge trap layer and expand in a two-dimensional manner; a second columnar semiconductor layer formed in contact... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090230463 - Integrated circuit long and short channel metal gate devices and method of manufacture: A method is provided for manufacturing an integrated circuit including a short channel (SC) device and a long channel (LC) device each overlaid by an interlayer dielectric. The SC device has an SC gate stack and the LC device initially has a dummy gate. In one embodiment, the method includes... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20090230464 - Semiconductor device including trench gate transistor and method of forming the same: A semiconductor device may include at least one active region that has at least one trench groove. A fin channel region is deposed in the active region and between the at least one trench groove and an isolation region of the semiconductor substrate. The gate insulating film is disposed on... Agent: Young & Thompson

20090230465 - Trench-gate field effect transistors and methods of forming the same: A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate... Agent: Townsend And Townsend And Crew, LLP

20090230466 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device includes forming a bulb-type trench separated from a surrounding gate and forming a buried bit line in the bulb-type trench, thereby preventing electric short of a word line and the buried bit line. A semiconductor device includes a vertical pillar formed over a... Agent: Marshall, Gerstein & Borun LLP

20090230467 - Semiconductor device and manufacturing method of the same: In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090230468 - Ldmos devices with improved architectures: An LDMOS device includes a substrate of a first conductivity type, an epitaxial layer on the substrate, a buried well of a second conductivity type opposite to the first conductivity type in a lower portion of the epitaxial layer, the epitaxial layer being of the first conductivity type below the... Agent: Hiscock & Barclay, LLP

20090230469 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device is provided which comprises: forming a first gate insulating film and a second gate insulating film in an active region of a semiconductor substrate; introducing an impurity of a first conductivity type into a first site where a first body region is to... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090230470 - Semiconductor device: Provided is a semiconductor device capable of easily setting a holding voltage with a low trigger voltage by locally forming a P-type diffusion layer between N-type source and drain diffusion layers of an NMOS transistor having a conventional drain structure used as an electrostatic protective element of the semiconductor device.... Agent: Bruce L. Adams, Esq Adams & Wilks

20090230472 - Semiconductor device having a floating body transistor and method for manufacturing the same: A method for manufacturing a semiconductor device that has a floating body transistor may include: etching a SOI substrate to expose a BOX region, epitaxially growing sidewalls of the substrate and contacting the grown silicon to a landing plug poly to form source/drain regions. The method reduces the occurrence of... Agent: Marshall, Gerstein & Borun LLP

20090230473 - Semiconuctor device and method for manufacturing the same: A semiconductor device includes a semiconductor layer formed on a substrate with an insulating film interposed therebetween, a gate insulating film formed on the semiconductor layer, a gate electrode which is formed on the gate insulating film, and includes a first region having a circular pattern in a plan view,... Agent: Harness, Dickey & Pierce, P.L.C

20090230471 - Trench memory with self-aligned strap formed by self-limiting process: A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the... Agent: International Business Machines Corporation Dept. 18g

20090230474 - Charge breakdown avoidance for mim elements in soi base technology and method: A semiconductor device including at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. A method of fabricating a semiconductor structure includes forming an SOI substrate, forming a BOX layer over... Agent: Andrew M. Calderon Greenblum & Bernstein, P.L.C

20090230475 - Field effect structure including carbon alloyed channel region and source/drain region not carbon alloyed: A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device structure. The field effect device structure includes a gate electrode located over a channel region within a semiconductor substrate that separates a plurality of source and drain regions within the semiconductor substrate. The channel... Agent: Scully, Scott, Murphy & Presser, P.C.

20090230476 - Optically triggered electro-static discharge protection circuit: The present invention provides a method and apparatus for providing electrostatic discharge (ESD) protection between a first and a second circuit node. One embodiment of the ESD protection circuit includes one or more steering diodes that generate electromagnetic radiation and couple the first circuit node to ground in response to... Agent: Williams, Morgan & Amerson

20090230477 - Resettable short-circuit protection configuration: A resettable short circuit protection configuration includes a power input terminal, a power output terminal, a first electrically controlled switch, which has a control end and two conducting ends, the two conducting ends being respectively electrically connected to the power input terminal and the power output terminal, a second electrically... Agent: Bacon & Thomas, PLLC

20090230478 - Apparatus and methods for improving multi-gate device performace: Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed.... Agent: Vyacheslav Spodik

20090230480 - Epitaxial silicon germanium for reduced contact resistance in field-effect transistors: A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090230479 - Hybrid process for forming metal gates of mos devices: A semiconductor structure includes a first MOS device including a first gate, and a second MOS device including a second gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second high-k dielectric over the first high-k dielectric; a first metal layer over the second high-k... Agent: Slater & Matsil, L.L.P.

20090230481 - Semiconductor device formed using single polysilicon process and method of fabricating the same: Provided are a semiconductor device including a source/drain and a gate formed using a doped polysilicon process, and a method of fabricating the semiconductor device. The method comprises: forming a gate insulating layer on a part of an active region on a first conductivity type epitaxial layer; forming a conductive... Agent: Hiscock & Barclay, LLP

20090230482 - Semiconductor device and manufacturing method thereof: A semiconductor device in which an E-FET and a D-FET are integrated on the same substrate, wherein an epitaxial layer includes, in the following order from the semiconductor substrate: a first threshold adjustment layer that adjusts a threshold voltage of a gate of the E-FET and a threshold voltage of... Agent: Greenblum & Bernstein, P.L.C

20090230483 - Semiconductor device: Disclosed herein is a semiconductor device including: first and second transistors, each of the first and second transistors being formed with a plurality of fin transistors, and the first and second transistors being connected in parallel to electrically share a source, wherein the plurality of fin transistors each include a... Agent: Sonnenschein Nath & Rosenthal LLP

20090230484 - Method of fabricating a semiconductor device: Embodiments relate to a method of fabricating a semiconductor device. In embodiments, a gate pattern may be formed on a semiconductor substrate, and sidewalls having a lower height than a height of the gate pattern may be formed at both sides of the gate pattern using a photoresist pattern. A... Agent: Sherr & Vaughn, PLLC

20090230485 - Element wafer and method for manufacturing the same: A recessed portion is provided in first and second insulating films, the first insulating film being stacked on a semiconductor wafer, the second insulating film being stacked on the first insulating film. The first and second insulating films are processed to form wiring in a formation region of the semiconductor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090230486 - Piezoelectric device and electronic apparatus: A piezoelectric device includes an integrated circuit (IC) chip and a piezoelectric resonator element, a part of the piezoelectric resonator element being disposed so as to overlap with a part of the IC chip when viewed in plan. The IC chip includes: an inner pad disposed on an active face... Agent: Oliff & Berridge, PLC

20090230487 - Semiconductor device, semiconductor device manufacturing method and lid frame: A semiconductor device includes: a substrate; a semiconductor chip that is fixed to a first surface of the substrate; a chip covering lid body that is provided on the first surface of the substrate so as to cover the semiconductor chip and that forms a hollow first space portion that... Agent: Dickstein Shapiro LLP

20090230488 - Low dark current image sensor: Imaging sensors (CMOS image sensor, CCD) with low dark current. The disclosed embodiments employ a stacked structure directly on the sensing area. The stack structure an SiO2 layer and with an HfO2 which is doped with Al, Ta, Be, Co, or Ge at the vicinity of the interface. The invention... Agent: Rader Fishman & Grauer PLLC

20090230489 - Low dark current image sensors by substrate engineering: Image sensors and the manufacture of image sensors having low dark current. A SiGe or Ge layer is selectively grown on the silicon substrate of the sensing area using an epitaxial chemical vapor deposition (CVD) method. After the SiGe or Ge growth, a silicon layer may be grown by the... Agent: Rader Fishman & Grauer PLLC

20090230491 - Photoelectric conversion device, imaging system, and photoelectric conversion device manufacturing method: A photoelectric conversion device comprises: a plurality of photoelectric conversion units each generating charges corresponding to light; an element isolation portion which electrically isolate the plurality of photoelectric conversion units; and an antireflection portion which are arranged to prevent reflection of light, which has entered the element isolation portion from... Agent: Fitzpatrick Cella Harper & Scinto

20090230492 - Solid-state image pickup device and method of manufacturing the same: A solid-state image pickup device which includes a substrate carrying a plurality of photoelectric conversion elements which are two-dimensionally arranged therein the substrate having a plurality of rectangular light-receiving faces each corresponding to the photoelectric conversion element, a flattening layer having a plurality of approximately rectangular concave faces each located... Agent: Staas & Halsey LLP

20090230490 - Solid-state imaging device and method for manufacturing the same: A solid-state imaging device includes: photoelectric transducers arranged in a matrix pattern on a substrate; and a plurality of color filter layers of different colors formed above the photoelectric transducers so as to correspond to the photoelectric transducers. One of the color filter layers of the color, which accounts for... Agent: Mcdermott Will & Emery LLP

20090230493 - Solid-state imaging device and method of fabricating solid-state imaging device: A solid-state imaging device includes: a solid-state imaging element having a light-receiving area; a transparent member disposed so as to oppose the light-receiving area; a supporting member configured to support the transparent member; a first mark disposed at either an upper surface of the transparent member or an upper surface... Agent: Fujitsu Patent Center C/o Cpa Global

20090230495 - Input display: An input display is provided in the present invention. The input display includes a thin film transistor (TFT) and a light blocking layer. The TFT includes a low-field electrode, a high-field electrode connected to the low-field electrode with a connecting section, and a field-effect area positioned on the connecting section... Agent: North America Intellectual Property Corporation

20090230494 - Solid-state imaging device, manufacturing method for the same, and imaging apparatus: A solid-state imaging device includes: a pixel section including, in a semiconductor substrate, plural photoelectric conversion sections that photoelectrically convert incident light to generate signal charges; metal wirings formed, on a first insulating film formed on the semiconductor substrate, above regions among the photoelectric conversion sections and above the periphery... Agent: Rader Fishman & Grauer PLLC

20090230496 - Solid-state imaging device: Disclosed herein is a solid-state imaging device including: a semiconductor substrate; a sensor of impurity diffusion layer formed on the surface layer of said semiconductor substrate; a negative charge accumulation layer formed on said sensor from an insulating material containing a first metallic substance; and an interfacial layer formed between... Agent: Sonnenschein Nath & Rosenthal LLP

20090230497 - Pin diode structure with zinc diffusion region: A PIN photodiode having a substrate, a first type electrode layer disposed on the substrate, a first layer of intrinsic material disposed over a portion of the first-type electrode layer, a first type window layer disposed over said intrinsic layer. An island shaped region of intrinsic material is disposed over... Agent: Emcore Corporation

20090230498 - Optical semiconductor device: An optical semiconductor device includes a semiconductor substrate; a light receiving element formed on the semiconductor substrate; a light absorbing element formed on the semiconductor substrate and located adjacent to the light receiving element; and a semiconductor element formed on the semiconductor substrate and used for signal processing. The light... Agent: Mcdermott Will & Emery LLP

20090230499 - Sensor device: A sensor device for sensing air flow speed at the exterior of an aircraft, comprising a substrate having an upper side on which is mounted a diaphragm over an aperture or recess in the substrate, the diaphragm being thermally and electrically insulative, and mounting on its upper surface a heating... Agent: Buchanan, Ingersoll & Rooney PC

20090230500 - Semiconductor device: A semiconductor device equipped with a primary semiconductor element and a temperature detecting element for detecting a temperature of the primary semiconductor element. The device includes a first semiconductor layer of a first conductivity type that forms the primary semiconductor element. A second semiconductor region of a second conductivity type... Agent: Rabin & Berdo, PC

20090230501 - Three dimensional structure memory: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit... Agent: Michael J. Ure

20090230504 - Hot process sti in sram device and method of manufacturing: A structure and method for forming SRAMs on HOT substrates with STI is described. Logic circuits may also be fabricated on the same chip with some devices on the SOI regions and other devices on the SOI regions.... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20090230503 - Method for manufacturing semiconductor substrate, and semiconductor device: Methods for manufacturing a semiconductor substrate and a semiconductor device by which a high-performance semiconductor element can be formed are provided. A single crystal semiconductor substrate including an embrittlement layer and a base substrate are bonded to each other with an insulating layer interposed therebetween, and the single crystal semiconductor... Agent: Eric Robinson

20090230502 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate; forming a second semiconductor layer on the first semiconductor layer; forming a first groove which penetrates the first and the second semiconductor layers by etching the first and the second semiconductor layers; forming... Agent: Harness, Dickey & Pierce, P.L.C

20090230505 - Self-aligned memory cells and method for forming: The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both... Agent: Ovonyx, Inc

20090230506 - Semiconductor device and method for fabricating the same: A semiconductor device includes a fuse pattern formed as conductive polymer layer having a low melting point. The fuse pattern is easily cut at low temperature to improve repair efficiency. The semiconductor device includes first and second fuse connecting patterns that are separated from each other by a distance, a... Agent: Townsend And Townsend And Crew, LLP

20090230509 - Finger capacitor structures: A capacitive structure formed in an Integrated Circuit (IC) includes a plurality of capacitor node conductor pairs, each including a first node conductor having a base portion and a plurality of finger portions and a second node conductor having a base portion and a plurality of finger portions that are... Agent: Garlick Harrison & Markison

20090230511 - Method for forming capacitor in a semiconductor device: A method for forming a capacitor of a semiconductor device ensures charging capacity and improves leakage current characteristic. In the capacitor forming method, a semiconductor substrate formed with a storage node contact is prepared first. Next, a storage electrode is formed such that the storage electrode is connected to the... Agent: Ladas & Parry LLP

20090230507 - Mim capacitors in semiconductor components: Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second... Agent: Slater & Matsil LLP

20090230510 - Semiconductor storage device and method of manufacturing the same: A rutile phase can be formed even in the case of a thin film by adding nickel or cobalt to titanium dioxide in the range of 0.5 to 10 atm %, and the use of this element-added titanium dioxide film in a capacitor dielectric film results in an increase in... Agent: Sughrue Mion, PLLC

20090230508 - Soi protection for buried plate implant and dt bottle etch: An SOI layer has an initial trench extending therethrough, prior to deep trench etch. An oxidation step, such as thermal oxidation is performed to form a band of oxide on an inner periphery of the SOI layer to protect it during a subsequent RIE step for forming a deep trench.... Agent: International Business Machines Corporation Dept. 18g

20090230512 - Nonvolatile memory devices that use resistance materials and internal electrodes, and related methods and processing systems: A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external... Agent: Myers Bigel Sibley & Sajovec

20090230513 - Compound semiconductor substrate and control for electrical property thereof: There is provided a compound semiconductor substrate prepared by forming a point defect in an inside structure thereof by implanting an electrically-neutral impurity with energy of 0.1 to 10MeV on a surface of the substrate. When the compound semiconductor is undoped, electrical resistance increases to increase insulating properties, and when... Agent: Lerner, David, Littenberg, Krumholz & Mentlik

20090230514 - Method of manufacturing nitride semiconductor device: A method of manufacturing a nitride semiconductor device includes the steps of: growing a group III nitride semiconductor layer on a substrate; forming a processed region in the substrate with a laser beam; and reducing the thickness of the substrate thereby spontaneously dividing the substrate from the processed region by... Agent: Rabin & Berdo, PC

20090230515 - Insulated gate semiconductor device and method for manufacturing the same: A well region in which an insulated gate semiconductor element is formed is a diffusion region, and an impurity concentration of the well region is lower toward its bottom portion. This leads to a problem of increased resistance. Therefore, particularly, an insulated gate semiconductor element having an up-drain structure has... Agent: Morrison & Foerster LLP

20090230516 - Pin diode with improved power limiting: A PIN diode comprising an N-type substrate comprising a cathode of the PIN diode and having an intrinsic layer disposed upon the N-type substrate and having a top surface a P-type material disposed upon the top surface of the intrinsic layer comprising an anode of the PIN diode and a... Agent: Tyco Technology Resources

20090230517 - Integrated circuit package system with integration port: An integrated circuit package system comprising: fabricating a package base including: forming a lead frame, coupling a first integrated circuit device under the lead frame, coupling a second integrated circuit device over the first integrated circuit device, and molding an enclosure on the lead frame, the first integrated circuit device,... Agent: Law Offices Of Mikio Ishimaru

20090230520 - Leadframe package with dual lead configurations: The invention provides a variety of leadframe packages in which signal connections and fixed voltage connections are configured differently to improve the relative performance of the connections relative to their assigned function. The signal connections incorporate one or more configurations of signal lead and corresponding signal bonding wires that tend... Agent: Harness, Dickey & Pierce, P.L.C

20090230519 - Semiconductor device: This application relates to a semiconductor device comprising: a carrier comprising a chip island and at least one first external contact element; only one semiconductor chip, wherein the semiconductor chip comprises a first electrode on a first surface and a second electrode on a second surface opposite to the first... Agent: Infineon Technologies Ag Patent Department

20090230518 - Semiconductor die package including ic driver and bridge: A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be... Agent: Townsend And Townsend And Crew, LLP

20090230521 - Stress mitigation in packaged microchips: A packaged microchip has a lead frame with a die directly contacting at least a single, contiguous portion of the lead frame. The portion of the lead frame has a top surface forming a concavity and contacting the die. The packaged microchip also has mold material substantially encapsulating part of... Agent: Bromberg & Sunstein LLP

20090230523 - Advanced quad flat no lead chip package having a cavity structure and manufacturing methods thereof: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a plurality of leads, a chip, and a package body. The die pad includes: (1) a peripheral edge region defining, a cavity with a cavity bottom including a central portion; (2) an upper... Agent: Cooley Godward Kronish LLP Attn: Patent Group

20090230526 - Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a... Agent: Cooley Godward Kronish LLP Attn: Patent Group

20090230525 - Advanced quad flat no lead chip package having marking and corner lead features and manufacturing methods thereof: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a first plurality of leads disposed in a lead placement area around the die pad, a second plurality of leads disposed in corner regions of the lead placement area, a semiconductor chip on... Agent: Cooley Godward Kronish LLP Attn: Patent Group

20090230529 - Integrated circuit packaging system with etched ring and die paddle and method of manufacture thereof: A method of manufacture of an integrated circuit packaging system is provided including: forming a D-ring includes half etching a paddle, etching a ring, and etching a tie bar. The tie bar is between the paddle and the ring. The system further includes mounting an integrated circuit die on a... Agent: Law Offices Of Mikio Ishimaru

20090230522 - Method for producing a semiconductor device and the semiconductor device: In a method of manufacturing a semiconductor device which has rear electrodes extended from a front surface to a rear surface of a substrate, the rear electrodes are formed from a side of the front surface by forming a groove on the front surface, by forming a metal film on... Agent: Collard & Roe, P.C.

20090230527 - Multi-chips package structure and the method thereof: A multi-chips package structure is provided, which includes a chip-placed frame having a plurality of chip-placed areas thereon, and two adjacent chip-placed areas is connected by a plurality of leads; a plurality of chips, each chip has a plurality of pads on an active surface thereon, and is provided on... Agent: Sinorica, LLC

20090230524 - Semiconductor chip package having ground and power regions and manufacturing methods thereof: A semiconductor package and related methods are described. In one embodiment the semiconductor package includes a die pad, a plurality of leads, a semiconductor chip, and a package body. The die pad includes a first part that includes a lower surface and a first peripheral edge region comprising a ground... Agent: Cooley Godward Kronish LLP Attn: Patent Group

20090230528 - Support mounted electrically interconnected die assembly: Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.... Agent: Haynes Beffel & Wolfeld LLP

20090230530 - Semiconductor device and method for producing semiconductor device: A back side of the silicon semiconductor substrate is roughly ground and is finishing-ground by using a whetstone having a copper content of less than 1 ppm, the back side being an opposite side of a side on which the semiconductor element is formed. The back side of the silicon... Agent: Sughrue Mion, PLLC

20090230531 - Semiconductor package with penetrable encapsulant joining semiconductor die and method thereof: A semiconductor device is made by mounting a first semiconductor die to a first substrate, forming a first encapsulant over the first semiconductor die, and forming a second encapsulant over the first encapsulant. The second encapsulant is penetrable, thermally conductive material. A second semiconductor die is mounted to the second... Agent: Robert D. Atkins

20090230533 - Manufacturing stacked semiconductor device: A method in accordance with an embodiment of the invention can include forming fan-out wirings on an insulating layer formed on a wafer. Additionally, electrodes of a plurality of semiconductor chips stacked on the fan-out wirings can be electrically coupled with the fan-out wirings. The wafer can be removed.... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090230534 - Semiconductor memory apparatus: The semiconductor memory apparatus related to an embodiment of the present invention includes a wiring substrate arranged with a device mounting part and connection pads aligned along one exterior side of the wiring substrate, a plurality of semiconductor memory devices including electrode pads which are arranged along one external side... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090230532 - System for solder ball inner stacking module connection: An integrated circuit package-in-package system including: providing a substrate; mounting a structure over the substrate; supporting an inner stacking module cantilevered over the substrate by an electrical interconnect connected to the substrate, the electrical interconnect forming a gap between the inner stacking module and the structure controlled by the size... Agent: Law Offices Of Mikio Ishimaru

20090230538 - Semiconductor chip package structure for achieving face-up electrical connection without using a wire-bonding process and method for making the same: A semiconductor chip package structure for achieving face-up electrical connection without using a wire-bonding process includes a package unit, a semiconductor chip, a substrate unit, a first insulative unit, a first conductive unit, a second conductive unit, and a second insulative unit. The package unit has a central receiving groove... Agent: Rosenberg, Klein & Lee

20090230539 - Semiconductor device: In recent years, as electronic equipment becomes thinner, an area for mounting a semiconductor device used in the electronic equipment is required to be smaller, and a thickness of an encapsulating resin for encapsulating a semiconductor substrate having a circuit formed thereon and the like also becomes smaller. The encapsulating... Agent: Young & Thompson

20090230537 - Semiconductor die package including embedded flip chip: A semiconductor die package. The semiconductor die package includes a leadframe structure, a first semiconductor die comprising a first surface attached to a first side of the leadframe structure, and a second semiconductor die attached to a second side of the leadframe structure. The second semiconductor die comprises an integrated... Agent: Townsend And Townsend And Crew, LLP

20090230536 - Semiconductor die package including multiple semiconductor dice: A semiconductor die package. The semiconductor die package includes a leadframe structure comprising a first die attach pad, and a second die attach pad laterally spaced from the first die attach pad, a first side and a second side opposite to the first side. The semiconductor die package further includes... Agent: Townsend And Townsend And Crew, LLP

20090230535 - Semiconductor module: A semiconductor module. In one embodiment, at least two semiconductor chips are placed on a carrier. The at least two semiconductor chips are then covered with a molding material. An exposed portion of the at least two semiconductor chips is provided. A first layer of conductive material is applied over... Agent: Dicke, Billig & Czaja

20090230540 - High performance multi-chip flip chip package: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of... Agent: Townsend And Townsend And Crew, LLP

20090230541 - Semiconductor device and manufacturing method of the same: A semiconductor device in which a chip is embedded in a wiring board and bump electrodes formed over the front surface of the semiconductor chip are flip-chip coupled to wiring formed in the wiring board and the entire back surface of the semiconductor chip functions well as a back electrode... Agent: Miles & Stockbridge PC

20090230542 - Semiconductor device with integrated passive circuit and method of making the same using sacrificial substrate: A semiconductor device is made by providing a sacrificial substrate, forming a first insulating layer over the sacrificial substrate, forming a first passivation layer over the first insulating layer, forming a second insulating layer over the first passivation layer, forming an integrated passive device over the second insulating layer, forming... Agent: Robert D. Atkins

20090230544 - Heat sink structure and semiconductor package as well as method for configuring heat sinks on a semiconductor package: A heat sink structure according to the present invention is provided. The heat sink has a through opening extending from the upper surface through to the lower surface. A solder is disposed in the through opening and on the upper and lower surfaces of the heat sink, wherein the portion... Agent: Lowe Hauptman Ham & Berner, LLP

20090230543 - Semiconductor package structure with heat sink: A semiconductor package structure with a heat sink is disclosed herein. The semiconductor package structure includes a substrate having a chip mounting area and a plurality of through holes surrounding the chip mounting area; a chip set on the chip mounting area and electrically connected to the substrate; a heat... Agent: Rosenberg, Klein & Lee

20090230545 - Electronic device contact structures: Electronic device contact structures are disclosed.... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.C.

20090230552 - Bump-on-lead flip chip interconnection: A flip chip interconnect is made by mating the interconnect bump directly onto a lead, rather than onto a capture pad. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having electrically conductive traces in a die... Agent: Robert D. Atkins

20090230547 - Design structure, semiconductor structure and method of manufacturing a semiconductor structure and packaging thereof: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher... Agent: Greenblum & Bernstein, P.L.C

20090230549 - Flip chip package: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to... Agent: Stanzione & Kim, LLP

20090230550 - Method and system for the modular design and layout of integrated circuits: An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width... Agent: Imperium Patent Works

20090230546 - Mounted body and method for manufacturing the same: A mounted body of the present invention includes: a multilayer semiconductor chip 20 including a plurality of semiconductor chips 10 (10a, 10b) that are stacked; and a mounting board 13 on which the multilayer semiconductor chip 20 is mounted. In this mounted body, each of the semiconductor chips 10 (10a,... Agent: Hamre, Schumann, Mueller & Larson P.C.

20090230551 - Semiconductor device: Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with... Agent: Mattingly & Malur, P.C.

20090230548 - Semiconductor package and multi-chip package using the same: A semiconductor package may have a semiconductor chip that includes a chip pad formed on a substrate including an integrated circuit, and a passivation layer exposing the chip pad, a first redistribution wiring layer that is connected to the chip pad and extends on the semiconductor chip and includes a... Agent: Stanzione & Kim, LLP

20090230553 - Semiconductor device including adhesive covered element: A semiconductor device includes a chip, at least one element electrically coupled to the chip, an adhesive at least partially covering the at least one element, and a mold material at least partially covering the chip and the adhesive.... Agent: Dicke, Billig & Czaja

20090230554 - Wafer-level redistribution packaging with die-containing openings: Methods, systems, and apparatuses for integrated circuit packages, and processes for forming the same, are provided. In one example, an integrated circuit (IC) package includes a thick film material that forms a opening, a die, an insulating material, a redistribution interconnect on the insulating material, and a ball interconnect. The... Agent: Fiala & Weaver, P.l.l.c. C/o Cpa Global

20090230555 - Tungsten liner for aluminum-based electromigration resistant interconnect structure: An underlying interconnect level containing underlying W vias embedded in a dielectric material layer are formed on a semiconductor substrate. A metallic layer stack comprising, from bottom to top, a low-oxygen-reactivity metal layer, a bottom transition metal layer, a bottom transition metal nitride layer, an aluminum-copper layer, an optional top... Agent: Scully, Scott, Murphy & Presser, P.C.

20090230556 - Nonvolatile semiconductor memory apparatus and manufacturing method thereof: A nonvolatile semiconductor memory apparatus 25 comprises a semiconductor substrate 11, a lower-layer wire 12 formed on the semiconductor substrate 11, an upper-layer wire 20 formed above the lower-layer wire 12 to cross the lower-layer wire 12, an interlayer insulating film 13 provided between the lower-layer wire 12 and the... Agent: Mcdermott Will & Emery LLP

20090230559 - Semiconductor device: A semiconductor device having macro circuit including a plurality of fine interconnections, an extension interconnection wider than the fine interconnections, having a first end connected to one or more of the fine interconnections and a second end located in an area of the semiconductor device external to the macro circuit,... Agent: Mcginn Intellectual Property Law Group, PLLC

20090230560 - Semiconductor device and manufacturing method thereof: A semiconductor device and manufacturing method thereof improving moisture resistance of a FeRAM. After a probe test using a pad, a metal film is formed to cover the pad in an opening of a protective film and a region from the pad to an opening outer periphery of the protective... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090230557 - Semiconductor device and method for making same: One or more embodiments are related to a semiconductor device, comprising: a metallic layer having a top surface and a sidewall surface; an intermediate layer disposed on a sidewall surface of the metallic layer; a dielectric layer disposed over the metallic layer, the dielectric layer having an opening formed therethrough;... Agent: Infineon Technologies Ag Patent Department

20090230558 - Semiconductor device and method for manufacturing the same: The present invention is a method for manufacturing a semiconductor device having a conductor and an insulating film on a substrate, the method including the steps of forming the conductor on the substrate, forming the insulating film on the conductor, removing the insulating film on the conductor, and blowing an... Agent: Masuvalley & Partners

20090230561 - Semiconductor device: A semiconductor device includes an active area having a source and a gate. A gate metal contact is deposited above and forms an electrical contact with the gate and a source metal contact is deposited above and forms an electrical contact with the source. The source metal contact includes a... Agent: Dicke, Billig & Czaja

20090230563 - Semiconductor device and method of manufacturing the same: A semiconductor device capable of preventing a crack from occurring in an electrode layer exposed through a through hole which is formed in a semiconductor substrate and a method of manufacturing the semiconductor device. In exemplary embodiments, a through via and an opening in a passivation film are disposed so... Agent: Taft, Stettinius & Hollister LLP

20090230562 - Semiconductor integrated circuit device: A semiconductor integrated circuit device including a dummy via is disclosed. In the semiconductor integrated circuit device, problems such as reduction in the designability and increase in fabrication cost which result from the existence of a dummy wire connected to the dummy via are suppressed. The semiconductor integrated circuit device... Agent: Mcdermott Will & Emery LLP

20090230564 - Chip structure and stacked chip package as well as method for manufacturing chip structures: A chip structure according to the present invention is provided. A plurality of pedestals extends from the back surface of the chip structure. Each of the pedestals is located at a position away from the edge of the back surface for a non-zero distance so that the pedestals of an... Agent: Lowe Hauptman Ham & Berner, LLP

20090230565 - Semiconductor package and method for manufacturing the same: A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces... Agent: Ladas & Parry LLP

20090230566 - Method of underfill air vent for flipchip bga: This invention relates to ejecting an underfill resin at multiple semiconductor die edges such that vacuum suction provided at a laminate through hole located beneath a stage enables spread of underfill resin from each edge simultaneously for quicker spread and reduction of voids. The excess underfill resin intentionally suctioned through... Agent: The Law Firm Of Andrea Hence Evans, LLC

20090230567 - Method of post-mold grinding a semiconductor package: A method of grinding a molded semiconductor package to a desired ultra thin thickness without damage to the package is disclosed. Prior to grinding a molded package to a desired package thickness, the package may be protected from excessive mechanical stress generated during grinding by applying a protective tape to... Agent: Intel Corporation C/o Cpa Global

20090230568 - Adhesive film for semiconductor and semiconductor device therewith: There is provided an adhesive film for a semiconductor, comprising a thermoplastic resin (A), an epoxy resin (B) and a curing agent (C), wherein a minimum melt viscosity of said adhesive film for a semiconductor is 0.1 Pa·s to 500 Pa·s both inclusive in a temperature range of 50° C.... Agent: Smith, Gambrell & Russell

20090230569 - Device comprising a semiconductor cmponent, and a manufacturing method: A device having at least one semiconductor component, which is covered by a protective material on its outer surface. The invention provides for the outer surface to be provided with a surface structure so as to enlarge the heat transfer area to the protective material. The invention furthermore relates to... Agent: Kenyon & Kenyon LLP

20090230570 - Resin composition and semiconductor device empolying the same: The present invention provides a resin composition for sealing a semiconductor device. The resin composition is in liquid state at room temperature, and can be supplied from a dispenser. The composition is advantageous in regard to molding time, viscosity, moldability and adhesion. This resin composition indispensably comprises a bisphenol type... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090230571 - Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure: A monolithic three dimensional semiconductor device structure includes a first layer including a first occurrence of a first reference mark at a first location, and a second layer including a second occurrence of the first reference mark at a second location, wherein the second location is substantially directly above the... Agent: Dugan & Dugan, PC

20090224223 - Functional molecular element: A functional molecular element is provided. The functional molecular element is adapted to change, by application of electric field, conformation of a disc shape like organic metallic complex molecule (1) which forms a columnar arrangement structure to exhibit function, wherein the structure of the organic metallic complex molecule is changed... Agent: K&l Gates LLP

20090224224 - Nonvolatile memory element, nonvolatile memory apparatus, nonvolatile semiconductor apparatus, and method of manufacturing nonvolatile memory element: A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (105), and a resistance variable layer (104) disposed between the first electrode (103) and the second electrode (104), a resistance value of the resistance variable layer varying reversibly according to an electric signal applied... Agent: Mcdermott Will & Emery LLP

20090224225 - Method of making an integrally gated carbon nanotube field ionizer device: A method of making an integrally gated carbon nanotube field ionization device comprising forming a first insulator layer on a first side of a substrate, depositing a conductive gate layer on the first insulator layer, forming a cavity in the substrate by etching a second side of the substrate to... Agent: Naval Research Laboratory Associate Counsel (patents)

20090224226 - Light emitting device of group iii nitride based semiconductor: A light emitting device of Group III nitride based semiconductor comprises a substrate, an N-type semiconductor layer formed on the substrate, an active layer formed on the N-type semiconductor layer, and a P-type semiconductor layer formed on the quantum well layer. The active layer comprises at least one quantum well... Agent: Wpat, PC Intellectual Property Attorneys

20090224227 - Type-ii inas/gasb superlattice photodiode and method of optimizing quantum efficiency: A type-II InAs/GaSb superlattice photodiode for optimizing quantum efficiency without reducing the differential resistance area product at zero bias. The photodiode features a GaSb: Be buffer, a In/GaSb: Be superlattice, a p-type doped π region, a InAs: Si/GaSb doped region, and a InAs: Si doped contact layer. The In/GaSb: Be... Agent: Husch Blackwell Sanders, LLP Husch Blackwell Sanders LLP Welsh & Katz

20090224228 - Inas/gasb infrared superlattice photodiodes doped with beryllium: An improved photodiode and method of producing an improved photodiode comprising doping an InAs layer of an InAs/GaSb region situated on top of an InAs/GaSb:Be superlattice and below an InAs:Si/GaSb regions such that the quantum efficiency of the photodiode increases and dominant dark current mechanisms change from diffusion to band-to-band... Agent: Husch Blackwell Sanders, LLP Husch Blackwell Sanders LLP Welsh & Katz

20090224229 - Polarity inversion of type-ii inas/gasb superlattice photodiodes: The subject invention comprises the realization of P-on-N type II InAs/GaSb superlattice photodiodes. A high-quality InAsSb layer lattice-mismatched to GaSb is used as a buffer to prepare the surface of the substrate prior to superlattice growth. The InAsSb layer also serves as an effective n-contact layer. The contact layer has... Agent: Husch Blackwell Sanders, LLP Husch Blackwell Sanders LLP Welsh & Katz

20090224230 - Carbon nanotube field effect transistor: A carbon nanotube field effect transistor includes a substrate, a source electrode, a drain electrode and a carbon nanotube. The carbon nanotube forms a channel between the source electrode and the drain electrode. The carbon nanotube field effect transistor also includes a gate dielectric and a gate electrode. The gate... Agent: Andrews Kurth LLP

20090224236 - Display employing organic material: A display is disclosed. The display includes a plurality of pixels configured to emit light. The display also includes a plurality of pixel control circuits that are each configured to regulate emission of light from a pixel. The pixel control circuits each include one or more two-terminal switching devices that... Agent: Weaver Austin Villeneuve & Sampson LLP

20090224231 - Electronic device, process for producing the same and electronic equipment making use thereof: An electronic device of the present invention includes at least one electrode (Au electrode 65) and an organic molecule layer (semiconductor layer 14) formed adjacent to the electrode, and in which charge transfers between the layer and the electrode. The organic molecule layer includes a plurality of first organic molecules... Agent: Hamre, Schumann, Mueller & Larson P.C.

20090224233 - Organic luminescence transistor device and manufacturing method thereof: a substrate; a first electrode layer provided on a side of an upper surface of the substrate; a layered structure provided locally on a side of an upper surface of the first electrode layer, the layered structure covering an area of a predetermined size in a plan view, the layered... Agent: Oliff & Berridge, PLC

20090224234 - Organic thin film transistors including metal oxide nanoparticles within a photocurable transparent polymer gate insulator layer and method for fabricating the same by using sol-gel and photocuring reactions: The present invention relates to an organic thin film transistor comprising a photocurable transparent inorganic/polymer composite layer as a gate insulator layer in which metal oxide nanoparticles are generated within a photocurable transparent polymer through sol-gel and photocuring reactions and whose permittivity is easily regulated; and a fabrication method thereof.... Agent: Jones Day

20090224237 - Semiconductor device, electronic device, and method of manufacturing semiconductor device: To provide a semiconductor device and a display device which can be manufactured through a simplified process and the manufacturing technique. Another object is to provide a technique by which a pattern of wirings or the like which is partially constitutes a semiconductor device or a display device can be... Agent: Cook Alex Ltd

20090224232 - Solid electrolytic capacitor and production method: The invention relates to a method for producing a solid electrolytic capacitor, in which a dielectric oxide film, a semiconductor layer and an electrode layer are sequentially formed on a rectangular parallelepiped sintered body of conductive powder having an anode lead implanted in one face and then the whole is... Agent: Sughrue Mion, PLLC

20090224235 - Transparent organic thin film transistor: e

20090224240 - Semiconductor light emitting element and method of manufacturing therefor: A semiconductor light emitting element of the present invention comprises: a zinc oxide (ZnO) single crystal substrate 12 with a substrate surface of a plane orientation insusceptible to a piezo electric field; a Lattice-matched layer 13 formed on the substrate surface to be lattice-matched with the ZnO single crystal substrate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090224239 - Thin film transistor, method of manufacturing the same, and electronic device using the same: A thin film transistor according to the present invention includes: a semiconductor layer (5); a source electrode (3s) and a drain electrode (3d) that each are connected to the semiconductor layer (5); an insulating layer (6) that is formed adjacent to the semiconductor layer (5); and a gate electrode (7)... Agent: Hamre, Schumann, Mueller & Larson P.C.

20090224238 - Transistor and method of manufacturing the same: A transistor according to example embodiments may include a channel layer, a source and a drain respectively contacting ends of the channel layer, a gate electrode separated from the channel layer, a gate insulating layer interposed between the channel layer and the gate electrode, and/or an insertion layer that is... Agent: Harness, Dickey & Pierce, P.L.C

20090224242 - Isolation circuit: An isolation circuit, comprising a first transistor having a gate, a first source/drain terminal, and a second source/drain terminal, a first pad coupled to the gate of the first transistor, the first pad operable to receive an enable signal, a second pad coupled to the first source/drain of the first... Agent: Schwegman, Lundberg & Woessner/micron

20090224241 - Semiconductor device: The present invention provides a semiconductor device which can realize the mounting of a plurality of chips at a high-speed, with high packaging density and at a low cost. In mounting a memory device chip 103 and an ASIC 104 on a wiring chip 102, connection pads 110, 116 are... Agent: Marshall, Gerstein & Borun LLP

20090224244 - Patterning of submicron pillars in a memory array: Methods in accordance with the invention involve patterning and etching very small dimension pillars, such as in formation of a memory array in accordance with the invention. When dimensions of pillars become very small, the photoresist pillars used to pattern them may not have sufficient mechanical strength to survive the... Agent: Dugan & Dugan, PC

20090224243 - Spontaneous growth of nanostructures on non-single crystalline surfaces: A method of forming nanostructures using catalyst-free epitaxial growth includes depositing a first layer of a non-single crystalline material on a support structure; heating the support structure and the first layer such that a combined layer is formed; and growing a nanostructure on the combined layer. A hetero-crystalline includes a... Agent: Hewlett Packard Company

20090224245 - Display device: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes... Agent: Fish & Richardson P.C.

20090224248 - Display device and manufacturing method thereof: The present invention provides a display device and a manufacturing method thereof. The display device includes a gate line, a data line that is insulated from and crosses the gate line, a thin film transistor including a semiconductor layer and connected to the gate line and the data line, a... Agent: H.c. Park & Associates, PLC

20090224247 - Liquid crystal display device: In a bottom-gate-type thin film transistor used in a liquid crystal display device in which a poly-Si layer and an a-Si layer are stacked, a quantity of an ON current which flows in the thin film transistor can be increased. A poly-Si layer and an a-Si layer are stacked on... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090224249 - Method for manufacturing el display device: A manufacture process of a thin film transistor mounted on an EL display device is simplified. A thin film transistor is manufactured by stacking a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film; forming a first resist mask over the... Agent: Fish & Richardson P.C.

20090224246 - Thin film transistor, display device using the same, and method of manufacturing the same: A thin film transistor (TFT) substrate, a display device having the same, and a method for manufacturing the same are disclosed. The TFT substrate includes: a substrate; a TFT formed on the substrate, the TFT including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode; and... Agent: Haynes And Boone, LLPIPSection

20090224253 - Crystallization method, thin film transistor manufacturing method, thin film transistor, display, and semiconductor device: According to a crystallization method, in the crystallization by irradiating a non-single semiconductor thin film of 40 to 100 nm provided on an insulation substrate with a laser light, a light intensity distribution having an inverse peak pattern is formed on the surface of the substrate, a light intensity gradient... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090224252 - Semiconductor device and manufacturing method thereof: The semiconductor device includes a thin film transistor; a first interlayer insulating film over the thin film transistor; a first electrode electrically connected to one of a source region and a drain region, over the first interlayer insulating film; a second electrode electrically connected to the other of the source... Agent: Eric Robinson

20090224251 - Thin film transistor device and method of manufacturing the same: A first insulating film is formed. Then, a gate electrode of a low voltage drive thin film transistor and a mask film for covering a region constituting a channel of a high voltage drive thin film transistor are formed with a molybdenum film on the first insulating film. An impurity... Agent: Greer, Burns & Crain

20090224250 - Top gate thin film transistor with enhanced off current suppression: A bottom-contacted top gate thin film transistor (TFT) with enhanced off current suppression is provided, along with an associated fabrication method. The method provided a substrate. Source and drain regions are formed overlying the substrate, each having a channel interface top surface. A channel is interposed between the source and... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20090224254 - Thin film transistor array panel and manufacturing method thereof: A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor... Agent: Haynes And Boone, LLPIPSection

20090224258 - Display device and manufacturing method thereof: In a display device which forms thin film transistors on a substrate, the thin film transistor includes an n-type thin film transistor and a p-type thin film transistor, a gate electrode of one thin film transistor out of the n-type thin film transistor and the p-type thin film transistor forms... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090224261 - Display device and manufacturing method thereof: A display device in which light leakage in a monitor element portion is prevented without increasing the number of steps and cost is provided. The display device includes a monitor element for suppressing influence on a light-emitting element due to temperature change and change over time and a TFT for... Agent: Cook Alex Ltd

20090224259 - Display substrate and method for manufacturing the same: A display substrate includes a gate wiring, a data wiring, a switching element, an organic layer, and a pixel electrode. The gate wiring contacts a first transparent conductive layer formed on the gate wiring. The data wiring crosses the gate wiring. The data wiring contacts a second transparent conductive layer... Agent: H.c. Park & Associates, PLC

20090224256 - Organic light emitting display: An organic light emitting display that prevents a material used to form a source electrode and a drain electrode from being diffused into an active layer and reduces contact resistance between the source and drain electrodes and a first electrode includes: a substrate; an active layer arranged on the substrate... Agent: Robert E. Bushnell & Law Firm

20090224255 - Semiconductor device and manufacturing method thereof: Channel doping is an effective method for controlling Vth, but if Vth shifts to the order of −4 to −3 V when forming circuits such as a CMOS circuit formed from both an n-channel TFT and a P-channel TFT on the same substrate, then it is difficult to control the... Agent: Cook Alex Ltd

20090224260 - Semiconductor device and method for manufacturing the same: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride... Agent: Cook Alex Ltd

20090224262 - Thin film transistor having a three-portion gate electrode and liquid crystal display using the same: A thin film transistor and a liquid crystal display, in which a gate electrode is formed to include at least one portion extending in a direction perpendicular to a gain growing direction in order to make electrical charge mobility of TFTs uniform without increasing the size of the driving circuit.... Agent: F. Chau & Associates, LLC

20090224257 - Thin film transistor panel and manufacturing method of the same: A thin film transistor array panel includes a gate line formed on a substrate and including a gate electrode, a semiconductor layer formed on a surface of the substrate having the gate line, a data line formed on the semiconductor layer, insulatedly intersecting the gate line, and including a source... Agent: Cantor Colburn, LLP

20090224263 - Generating stress in a field effect transistor: A structure for generating stress in a field effect transistor is described. Combinations of materials are described that when juxtaposed provide one of tensile or compressive stress to a channel region. In one or more aspects, tensile stress is provided to a channel region by materials having similar but different... Agent: Banner & Witcoff, Ltd.

20090224264 - Semiconductor component with regions electrically insulated from one another and method for making a semiconductor component: Semiconductor component comprising at least two semiconductor regions are disclosed. In one embodiment the semiconductor regions of the semiconductor component are electrically isolated from one another by an insulator, and a deposited, patterned, metallic layer extends over the semiconductor regions and over the insulator.... Agent: Infineon Technologies Ag Patent Department

20090224266 - Led chip package structure applied to a backlight module and method for making the same: An LED chip package structure applied to a backlight module includes a substrate unit, a light-emitting unit, a package body unit and an opaque unit. The light-emitting unit has a plurality of LED chips electrically arranged on the substrate unit. The package body unit has a plurality of package bodies... Agent: Rosenberg, Klein & Lee

20090224265 - Led chip package structure with a high-efficiency heat-dissipating substrate and method for making the same: An LED chip package structure with a high-efficiency heat-dissipating substrate includes a substrate unit, an adhesive body, a plurality of LED chips, package bodies and frame layers. The substrate unit has a positive substrate, a negative substrate, and a plurality of bridge substrates separated from each other and disposed between... Agent: Rosenberg, Klein & Lee

20090224268 - Light-emitting diode and lighting apparatus using the same: A light-emitting diode includes a substrate, a light-emitting diode element mounted on an upper surface of the substrate, and a sealing member that covers the light-emitting diode element. At least one pair of lower electrodes electrically connected to the light-emitting diode element and at least one pair of connecting electrodes... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20090224267 - Process for fabricating a thin film semiconductor device, thin film semiconductor device, and liquid crystal display: A process of fabricating a thin film semiconductor device is proposed, which is suitable for mass production and enables to lower the production cost. A first substrate is subject to anodization to form a porous layer thereon. Then, a thin film semiconductor layer is formed on the porous layer. Using... Agent: Rader Fishman & Grauer PLLC

20090224270 - Group iii nitride semiconductor thin film and group iii semiconductor light emitting device: A group III nitride semiconductor thin film and a group III nitride semiconductor light emitting device using the same. The group III nitride semiconductor thin film includes a substrate with a concave and convex portions formed thereon; a buffer layer formed on the substrate and made of a group III... Agent: Mcdermott Will & Emery LLP

20090224269 - Semiconductor light emitting device and method for manufacturing same, and epitaxial wafer: A semiconductor light emitting device includes: an upper growth layer including a light emitting layer; a transparent substrate through which a radiant light from the light emitting layer passes; and a foundation layer provided between the upper growth layer and the transparent substrate, the foundation layer having a surface-controlling layer... Agent: Turocy & Watson, LLP

20090224271 - Led package: To this end, an LED package according to the present invention comprises first and second lead frames disposed to be spaced apart from each other; an LED chip mounted on the first lead frame and connected to the second lead frame by a bonding wire; a supporting member formed to... Agent: H.c. Park & Associates, PLC

20090224273 - Light emitting device and light emitting module: [Means for Solving Problems] The device is characterized by including a container (20) which is formed of a transparent inorganic material and has a recessed opening, a light emitting chip (1) which is disposed in the recessed opening of the container (20) with a glass bonding member (4) interposed therebetween... Agent: Hogan & Hartson L.L.P.

20090224272 - Light emitting diode and manufacturing method thereof: A light-emitting diode and the manufacturing method thereof are disclosed. The manufacturing method comprises the steps of: sequentially forming a bonding layer, a geometric pattern layer, a reflection layer, an epitaxial structure and a first electrode on a permanent substrate, wherein the geometric pattern layer has a periodic structure; and... Agent: Bacon & Thomas, PLLC

20090224275 - Light emitting diode and method: A light emitting diode and methods of forming the same are provided. The light emitting diode includes an epitaxy chip having a first substrate, a first conductive semiconductor layer, a light emitting layer and a second conductive semiconductor layer on the first substrate; a second substrate holding the epitaxy chip;... Agent: Snell & Wilmer L.L.P. (main)

20090224276 - Semiconductor device, led head and image forming apparatus: Provided is a technique of effectively extracting the beams of light excited in an LED light emitter other than the light beams emitted from a light-emitting region in the direction of a light-extraction surface. A pit with a tapered sidewall is formed in a substrate. A thin-film semiconductor element is... Agent: Mots Law, PLLC

20090224277 - Semiconductor light emitting devices including a luminescent conversion element and methods for packaging the same: Methods of packaging a semiconductor light emitting device include dispensing a first quantity of encapsulant material into a cavity including the light emitting device. The first quantity of encapsulant material in the cavity is treated to form a hardened upper surface thereof having a selected shape. A luminescent conversion element... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090224274 - Tuning the emission color of single layer, patterned full color organic light emitting diodes: A process is provided for the effective tuning of the emitting light of OLEDs and thus, achieving single layer, patterned full color displays of optimal quality. The present invention describes a process for the tuning of the emitting color of OLEDs where in the emissive layer of single layer OLEDs... Agent: Mathews, Shepherd, Mckay, & Bruneau, P.A.

20090224280 - Light emitting diode package structure and manufacturing method therefor: A light emitting diode (LED) package and a manufacturing method therefore are disclosed. The LED package comprises: a transparent substrate, a transparent LED chip, a transparent adhesive for bonding the transparent LED chip, a lead frame, conductive wires, and an encapsulant. In the manufacturing method, a heating step is first... Agent: Pai Patent & Trademark Law Firm

20090224281 - Light-emitting devices having an active region with electrical contacts coupled to opposing surfaces thereof: A light-emitting device comprises a substrate that has a contact plug extending therethrough between first and second opposing surfaces. An active region is on the first surface, a first electrical contact is on the active region, and a second electrical contact is adjacent to the second surface of the substrate.... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090224279 - Optical semiconductor device and method of manufacturing optical semiconductor device: An optical semiconductor device includes: an optical semiconductor element including a light-emitting layer formed on a first principal surface, a first electrode formed on the light-emitting layer and having a smaller size than the first principal surface, and a second electrode formed on a second principal surface different from the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090224278 - Semiconductor light-emitting device, light-emitting module and lighting unit: A semiconductor light-emitting device (1) includes a semiconductor multilayer film (11), a base material (12) for supporting the semiconductor multilayer film (11), a first feed terminal (17a), and a second feed terminal (17b). A protruding portion (12c) is formed on the back surface (12b) of the base material (12) that... Agent: Hamre, Schumann, Mueller & Larson P.C.

20090224282 - Gallium nitride-based compound semiconductor light-emitting device: The inventive gallium nitride-based compound semiconductor light-emitting device comprises an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer which are formed in this order on a substrate, wherein each layer comprises a gallium nitride-based compound semiconductor, the light-emitting device has a negative electrode and a positive electrode... Agent: Sughrue Mion, PLLC

20090224283 - Method of fabricating photoelectric device of group iii nitride semiconductor and structure thereof: A method of fabricating a photoelectric device of Group III nitride semiconductor, where the method comprises the steps of: forming a first Group III nitride semiconductor layer on a surface of a temporary substrate; patterning the first Group III nitride semiconductor layer using photolithography and etching processes; forming a second... Agent: Wpat, PC Intellectual Property Attorneys

20090224284 - Semiconductor device and method of producing the same: A semiconductor substrate and a method of its manufacture has a semiconductor substrate having a carbon concentration in a range of 6.0×1015 to 2.0×1017 atoms/cm3, both inclusively. One principal surface of the substrate is irradiated with protons and then heat-treated to thereby form a broad buffer structure, namely a region... Agent: Rossi, Kimms & Mcdowell LLP.

20090224285 - Threading-dislocation-free nanoheteroepitaxy of ge on si using self-directed touch-down of ge through a thin sio2 layer: A method of forming a virtually defect free lattice mismatched nanoheteroepitaxial layer is disclosed. The method includes forming an interface layer on a portion of a substrate. A plurality of seed pads are then formed by self-directed touchdown by exposing the interface layer to a material comprising a semiconductor material.... Agent: Mh2 Technology Law Group, LLP

20090224286 - Mobility enhancement in sige heterojunction bipolar transistors: The present invention relates to a high performance heterojunction bipolar transistor (HBT) having a base region with a SiGe-containing layer therein. The SiGe-containing layer is not more than about 100 nm thick and has a predetermined critical germanium content. The SiGe-containing layer further has an average germanium content of not... Agent: Scully, Scott, Murphy & Presser, P.C.

20090224287 - Semiconductor device having a locally buried insulation layer: A semiconductor device having a locally buried insulation layer and a method of manufacturing a semiconductor device having the same are provided, in which a gate electrode is formed on a substrate, and oxygen ions are implanted into an active region to form a locally buried insulation layer. An impurity... Agent: F. Chau & Associates, LLC

20090224289 - Transistors including supported gate electrodes: A transistor includes a protective layer having an opening extending therethrough on a substrate, and a gate electrode in the opening. First portions of the gate electrode laterally extend on surface portions of the protective layer outside the opening on opposite sides thereof, and second portions of the gate electrode... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090224288 - Wide bandgap transistor devices with field plates: A transistor structure comprising an active semiconductor layer with metal source and drain contacts formed in electrical contact with the active layer. A gate contact is formed between the source and drain contacts for modulating electric fields within the active layer. A spacer layer is formed above the active layer... Agent: Koppel, Patrick, Heybl & Dawson

20090224290 - Two-way halo implant: A system and method for ion implantation during semiconductor fabrication. An integrated circuit may be designed with proximately located one-directional transistor gates. A two-way halo ion implantation is performed perpendicularly to the transistor gates in order to embed the dopant into the silicon body on the surface of the semiconductor... Agent: Banner & Witcoff, Ltd.

20090224291 - Method for self aligned sharp and shallow doping depth profiles: A method for fabricating a semiconductor device comprises forming a channel of a transistor, wherein the channel has a first conductivity type. The method further comprises depositing a layer of dielectric on at least a portion of the channel. The method further comprises etching a notch in the layer of... Agent: Baker Botts L.L.P.

20090224296 - Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps: A method (100) of forming semiconductor structures (202) including high-temperature processing steps (step 118), incorporates the use of a high-temperature nitride-oxide mask (220) over protected regions (214) of the device (202). The invention has application in many different embodiments, including but not limited to, the formation of recess, strained device... Agent: Texas Instruments Incorporated

20090224295 - Mos transistor manufacturing: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20090224293 - Semiconductor device and method for manufacturing same: A semiconductor device includes: a sidewall insulating film; a gate electrode; source and drain regions; a first stress film; and a second stress film.... Agent: Sonnenschein Nath & Rosenthal LLP

20090224294 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device includes the following processes. Multiple bit lines including a first silicide layer and/or a first polysilicon layer are formed. Then, multiple through holes are formed in the bit lines. Then, a first silicon layer is formed to fill the through holes. Then, a... Agent: Sughrue Mion, PLLC

20090224297 - Semiconductor device having a compressed device isolation structure: The semiconductor device includes a lower device isolation structure formed in a semiconductor substrate to define an active region. The lower device isolation structure has a first compressive stress. An upper device isolation structure is disposed over the lower device isolation structure. The upper device isolation structure has a second... Agent: Townsend And Townsend And Crew, LLP

20090224292 - Thin film transistor and method of producing thin film transistor: A method of producing a thin film transistor includes a gate electrode formation step that forms a gate electrode on a substrate, a gate insulating layer formation step that forms a gate insulating layer on the substrate in such a manner as to cover the gate electrode formed in the... Agent: Day Pitney LLP

20090224298 - Cmos image sensor and manufacturing method thereof: Disclosed are a CMOS image sensor and a manufacturing method thereof. The method includes the steps of: forming an isolation layer on a semiconductor substrate, defining an active region that includes a photo diode region and a transistor region; forming a gate in the transistor region, the gate including a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090224299 - Method and apparatus for providing an integrated circuit having p and n doped gates: A method and apparatus providing an integrated circuit having a plurality of gate stack structures having gate oxide layers with differing thicknesses and nitrogen concentrations and gate electrodes with differing conductivity types and active dopant concentrations.... Agent: Dickstein Shapiro LLP

20090224300 - Nonvolatile magnetic memory device: A nonvolatile magnetic memory device includes a magnetoresistance effect element that includes: a layered structure having a recording layer; a first wiring electrically connected to a lower part of the layered structure; a second wiring electrically connected to an upper part of the layered structure; and an interlayer insulation layer... Agent: Wolf Greenfield & Sacks, P.C.

20090224301 - Semiconductor memory device and method of manufacturing thereof: A semiconductor memory device comprises a field effect transistor including a source/drain region, an interlayer insulation film burying the field effect transistor, a ferroelectric capacitor including a lower electrode, a ferroelectric film and an upper electrode, the lower electrode with a concave-convex surface, and a plug electrically connecting between the... Agent: Knobbe Martens Olson & Bear LLP

20090224303 - High voltage capacitor and manufacture method thereof: A high voltage capacitor and a manufacture method thereof are provided. The high voltage capacitor comprises a double diffused drain layer, an oxide layer and a poly-crystal silicon layer. The double diffused drain layer is used as a bottom electrode plate of a high voltage capacitor. The oxide layer is... Agent: Rabin & Berdo, PC

20090224302 - Semiconductor device with inherent capacitances and method for its production: A semiconductor device with inherent capacitances and method for its production. The semiconductor device has an inherent feedback capacitance between a control electrode and a first electrode. In addition, the semiconductor device has an inherent drain-source capacitance between the first electrode and a second electrode. At least one monolithically integrated... Agent: Dicke, Billig & Czaja

20090224304 - Soft error protection structure employing a deep trench: A deep trench containing a doped semiconductor fill portion having a first conductivity type doping and surrounded by a buried plate layer having a second conductivity type doping at a lower portion is formed in a semiconductor layer having a doping of the first conductivity type. A doped well of... Agent: Scully, Scott, Murphy & Presser, P.C.

20090224305 - Nonvolatile semiconductor storage device with charge storage layer and its manufacturing method: A nonvolatile semiconductor storage device includes a semiconductor substrate, a charge storage layer formed above the semiconductor substrate, a control gate formed above the charge storage layer, a silicide layer formed above the control gate, a word gate formed above a side of the control gate. A top surface of... Agent: Mcginn Intellectual Property Law Group, PLLC

20090224306 - Nonvolatile semiconductor storage device with charge storage layer and its manufacturing method: A nonvolatile semiconductor storage device includes a semiconductor substrate, a charge storage layer formed above the semiconductor substrate, a control gate formed above the charge storage layer, a spacer layer formed above the control gate and a word gate formed above a side of the control gate and the spacer... Agent: Mcginn Intellectual Property Law Group, PLLC

20090224307 - Semiconductor device and method of fabricating the same: A semiconductor device and method of fabricating the same. In an aspect of the inventive method, a tunnel insulating layer, a first conductive layer, a dielectric layer, a second conductive layer, and a gate electrode layer are sequentially stacked over a semiconductor substrate. The gate electrode layer is patterned in... Agent: Marshall, Gerstein & Borun LLP

20090224308 - Vertical soi trench sonos cell: A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench... Agent: Scully, Scott, Murphy & Presser, P.C.

20090224309 - Nonvolatile semiconductor storage device and manufacturing method thereof: A method for manufacturing a nonvolatile semiconductor storage device, including: forming a first conductive layer so that it is sandwiched in an up-down direction by first insulating layers; forming a first hole so that it penetrates the first insulating layers and the first conductive layer; forming a first side wall... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090224310 - Power semiconductor device and method of manufacturing the same: A power semiconductor device capable of transmitting gate signals in all directions (e.g., up-/down-ward/right-/left-ward) on a plane and a method of manufacturing the same. The power semiconductor device includes first conductive regions, formed to a predetermined depth in a surface of a conductive low concentration epitaxial layer. The first conductive... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090224312 - Semiconductor device and manufacturing method therefor: A semiconductor device including a trench-gate MOS transistor on a semiconductor substrate is constituted of a trench formed in an active region, a fin channel region formed between a separation region and the trench in the active region, a first gate electrode embedded in the separation region in connection with... Agent: Young & Thompson

20090224311 - Semiconductor device and method of manufacturing the same: The semiconductor device includes a trench having a depth of a distance equal to or shorter than the L length of the transistor, and a buried layer is used in a bottom portion of the trench, whereby an effective channel length from each of a lower end of a high... Agent: Bruce L. Adams, Esq

20090224315 - Semiconductor device and method of manufacturing the same: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a... Agent: Miles & Stockbridge PC

20090224314 - Semiconductor device and the method of manufacturing the same: A power MOSFET exhibits a high breakdown voltage and low ON-state resistance. The device includes a trench formed in a semiconductor substrate, a gate electrode located along a side wall of the trench and a bottom wall of the trench near a side wall thereof, a pillar section, a first... Agent: Rossi, Kimms & Mcdowell LLP.

20090224313 - Semiconductor device having a gate contact on one surface electrically connected to a gate bus on an opposing surface: A power semiconductor device which includes a gate contact on one surface thereof connected to a gate bus on another opposing surface thereof using a conductive body extending through a via between the two surfaces of the device.... Agent: Farjami & Farjami LLP

20090224316 - Power mos device with conductive contact layer: A semiconductor device includes a drain, a body disposed over the drain, a source embedded in the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench extending through the source into the body,... Agent: Van Pelt, Yi & James LLP

20090224317 - Cross-coupled transistor layouts in restricted gate level layout architecture: A first P channel transistor and a first N channel transistor are defined by first and second gate electrodes, respectively. The second gate electrode is electrically connected to the first gate electrode. A second P channel transistor and a second N channel transistor are defined by third and fourth gate... Agent: Martine Penilla & Gencarella, LLP

20090224318 - Semiconductor device and manufacturing method of the same: The invention improves the performance of a semiconductor device. A metal silicide film is formed by a silicide process on a gate electrode and an n+-type source region of an LDMOSFET, and no such metal silicide film is formed on an n−-type offset drain region, an n-type offset drain region,... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090224319 - Highly conductive shallow junction formation: The invention relates to a method of forming a shallow junction. The method (100) comprises forming source/drain extension regions with a non-amorphizing tail implant (105) which is annealed conventionally (spike/RTP) and amorphizing implant which is re-grown epitaxially(SPER) (110). The non-amorphizing tail implant is generally annealed (106) before a doped amorphous... Agent: Texas Instruments Incorporated

20090224320 - Method and apparatus for fabricating an ultra thin silicon on insulator: In one embodiment, the invention is a method and apparatus for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature,... Agent: Wall & Tong, LLP IBM Corporation

20090224321 - Semiconductor device and method of manufacturing semiconductor device: Provided are a semiconductor device capable of improving the drive capacity of a MOS transistor even if the SOI layer is thinned; and a manufacturing method of the device. In a NMOS transistor formed in a NMOS formation region, a source/drain region is formed to penetrate through a buried oxide... Agent: Miles & Stockbridge PC

20090224322 - Thin film semiconductor device and method of manufacturing the same: A thin film semiconductor device has: a substrate; a low-voltage thin film transistor formed on the substrate and having a first gate insulating film; and a high-voltage thin film transistor formed on the substrate and having a second gate insulating film whose thickness is larger than that of the first... Agent: Dickstein Shapiro LLP

20090224325 - Antifuse elements: An antifuse element (102, 152, 252, 302, 352, 402, 602, 652, 702) includes a substrate material (101) having an active area (106) formed in an upper surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a gate oxide layer (110) disposed between... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20090224323 - Integrated circuit with mosfet fuse element: At least one MOS parameter of a MOS fuse is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse is programmed by applying a programming signal to the fuse terminals so that programming current flows through the fuse link. The fuse resistance is measured to... Agent: Xilinx, Inc Attn: Legal Department

20090224324 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a semiconductor substrate, and an electric fuse element, the electric fuse element including: first impurity-diffused layer regions formed in an active region of the semiconductor substrate; an insulating film formed on the semiconductor substrate between the first impurity-diffused layer regions; and a gate electrode formed on... Agent: Young & Thompson

20090224326 - Avoiding plasma charging in integrated circuits: A circuit having a circuit control terminal, a primary circuit and a protection circuit is provided. The primary circuit includes a primary control terminal and a primary gate oxide of a thickness T1. The primary control terminal is coupled to the circuit control terminal. The protection circuit having a protection... Agent: HorizonIPPte Ltd

20090224327 - Plane mos and the method for making the same: A plane MOS includes a substrate, an insulator layer whose surface is substantially parallel with the surface of the substrate disposed on the substrate, a gate, a source and a drain directly disposed on the insulator layer and a gate channel disposed between the source and the drain and contacting... Agent: North America Intellectual Property Corporation

20090224328 - Semiconductor device: A semiconductor device includes a substrate defining an active area thereon, a shallow trench isolation on the substrate and directly surrounding the active area, a gate, a source and a drain on the active area and a hard mask on the border of the shallow trench isolation and the active... Agent: North America Intellectual Property Corporation

20090224329 - Semiconductor device and manufacturing method of semiconductor device: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate; an element isolation region provided in the semiconductor substrate and having an oxide layer and an oxidant-diffusion prevention layer provided on the oxide layer; a gate dielectric film provided on the semiconductor substrate and the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090224330 - Semiconductor memory device and method for arranging and manufacturing the same: A semiconductor memory device and method of manufacturing the same are disclosed. The semiconductor memory device includes a semiconductor substrate having a cell region and a peripheral circuit region, first transistors provided on the semiconductor substrate, a first semiconductor layer provided on the first transistors, and bonded by a bonding... Agent: Myers Bigel Sibley & Sajovec

20090224331 - Semiconductor storage device using magnetoresistive effect element and method of manufacturing the same: A semiconductor storage device includes a semiconductor substrate, a source region, a source line, and a bit line. The source region is formed in an element region formed on the semiconductor substrate. The source line is formed to overlap with the source region in planar view. The bit line is... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090224333 - Power transistor with protected channel: A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to... Agent: Fish & Richardson P.C.

20090224332 - Semiconductor device: An n-type embedded layer is formed in an N-LV region of a SRAM cell region after an element isolation insulating film is formed on a p-type Si substrate. Thereafter, a p-well and an n-well are formed. In formation of a channel-doped layer, ion implantation is also performed into the N-LV... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090224334 - Merged field effect transistor cells for switching: Disclosed are embodiments of an improved integrated circuit switching device that incorporates multiple sets of series connected field effect transistors with each set further connected in parallel between two nodes. The sets are arranged in a linear fashion with each set positioned such that it is in contact with and... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090224335 - Field effect transistor with reduced shallow trench isolation induced leakage current: Edges of source and drain regions along the direction of a channel of a field effect transistor are formed within an active area offset from the boundary between the active area and a shallow trench isolation structure. Such a structure may be manufactured by forming a gate electrode structure that... Agent: Scully, Scott, Murphy & Presser, P.C.

20090224336 - Semiconductor device: A semiconductor device including a plurality of doped regions, a metal layer and a polysilicon layer is provided. The doped regions are disposed in a substrate. The metal layer includes a plurality of metal line patterns. The polysilicon layer disposed between the substrate and the metal layer includes a gate... Agent: J C Patents, Inc.

20090224337 - Mos devices with partial stressor channel: A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate and adjacent the gate electrode. The stressor has a tilted sidewall on... Agent: Slater & Matsil, L.L.P.

20090224338 - Semiconductor device and method of manufacturing the same: Disclosed herein is a semiconductor device, including: an insulating film provided on a semiconductor substrate so as to have a trench pattern; a gate insulating film provided so as to cover an inner wall of the trench pattern; and a gate electrode formed so as to be filled in the... Agent: Robert J. Depke Lewis T. Steadman

20090224339 - Silicon-germanium-carbon semiconductor structure: In accordance with one or more embodiments, a semiconductor structure includes a semiconductor substrate, a first semiconductor material over the semiconductor substrate, and a second semiconductor material over a portion the first semiconductor material, wherein the second semiconductor material comprises silicon-germanium-carbon (SiGeC) and wherein the first semiconductor material is a... Agent: Hvvi Semiconductors, Inc.

20090224340 - Antiferromagnetic half-metallic semiconductor and manufacturing method therefor: An antiferromagnetic half-metallic semiconductor of the present invention is manufactured by adding to a semiconductor two or more types of magnetic elements including a magnetic element with a d-electron number of less than five and a magnetic element with a d-electron number of more than five, and substituting a part... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090224342 - Magnetoresistive effect element and magnetic random access memory: A magnetoresistive effect element includes a reference layer, a recording layer, and a nonmagnetic layer. The reference layer is made of a magnetic material, has an invariable magnetization which is perpendicular to a film surface. The recording layer is made of a magnetic material, has a variable magnetization which is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090224341 - Method of forming a magnetic tunnel junction device: A method of manufacturing a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, depositing a conductive terminal within the trench, and depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a fixed magnetic orientation,... Agent: Qualcomm Incorporated

20090224346 - Image sensing apparatus and imaging system: An image sensing apparatus includes an image sensing region where a plurality of pixels are two-dimensionally arrayed. Each pixel includes a photoelectric conversion unit, and a semiconductor region arranged below an element isolation region having an insulation film to isolate the photoelectric conversion unit from an adjacent pixel. The semiconductor... Agent: Fitzpatrick Cella Harper & Scinto

20090224347 - Image sensor and method of manufacturing the same: An image sensor includes a first region of a substrate having photoelectric conversion elements formed therein, and includes a second region of the substrate outside of the first region. The image sensor includes a plurality of lenses, a plurality of embossing structures, and a protective layer. The lenses are formed... Agent: Law Office Of Monica H Choi

20090224349 - Image sensor including spatially different active and dark pixel interconnect patterns: An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical... Agent: Scully, Scott, Murphy & Presser, P.C.

20090224345 - Image sensor using back-illuminated photodiode and method of manufacturing the same: An image sensor using a back-illuminated photodiode and a manufacturing method thereof are provided. According to the present invention, since a surface of the back-illuminated photodiode can be stably treated, the back-illuminated photodiode can be formed to have a low dark current, a constant sensitivity of blue light for all... Agent: Cantor Colburn, LLP

20090224343 - Methods of forming imager devices, imager devices configured for back side illumination, and systems including the same: Imager devices configured for back side illumination include a structural support member surrounding a sensor array. A conductive element for communicating electrically with the sensor array may be provided on a front side of the sensor array. In some embodiments, a plurality of conductive elements may be provided on the... Agent: Treyz Law Group

20090224344 - Packaging method of image sensing device: A packaging method for an image sensing device is disclosed. The packaging method includes the steps of a) providing a wafer having at least an image sensing module with a light-receiving region exposed; b) forming a barrier around the light-receiving region on the image sensing module; c) dicing the wafer... Agent: Bacon & Thomas, PLLC

20090224348 - Solid-state imaging device and its manufacturing method: A solid-state imaging device includes a semiconductor substrate having a photoelectric conversion region, a first microlens provided above the semiconductor substrate, covering the photoelectric conversion region, and having a convex upper surface, for gathering external light into the photoelectric conversion region, and a second microlens provided above the first microlens... Agent: Mcdermott Will & Emery LLP

20090224350 - Semiconductor device, camera module, and semiconductor device manufacturing method: A semiconductor device is provided which has a semiconductor element having an element forming surface at which a sensor element is formed, a back surface on the opposite side of the element forming surface, and a light transmissive protective member laminated over the element forming surface via an adhering portion.... Agent: Volentine & Whitt PLLC

20090224351 - Cmos sensor with approximately equal potential photodiodes: A MOS or CMOS based active pixel sensor designed for operation with zero or close to zero potential across the pixel photodiodes to minimize or eliminate dark current. In this preferred embodiment, the voltage potential across the pixel photodiode structures is maintained constant and close to zero, preferably less than... Agent: Trex Enterprises Corp.

20090224352 - Method of manufacturing a photodiode array with through-wafer vias: A method for manufacturing a photodiode array includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has a first layer of a first conductivity proximate the first main surface and a second layer of a second conductivity proximate the second main... Agent: Panitch Schwarze Belisario & Nadel LLP

20090224353 - Diode: A diode includes the following: an n type semiconductor region; a p type semiconductor region provided in a part of a front face of the n type semiconductor region; an anode electrode (front face electrode) which adjoins a front face of the n type semiconductor region and a front face... Agent: Posz Law Group, PLC

20090224354 - Junction barrier schottky diode with submicron channels: A junction barrier Schottky diode is provided as having submicron channel width between implant regions by way of a process including the use of spacer technology. On-state resistance is lowered by providing the implant regions in a channel layer having increased dopant concentration.... Agent: Volentine & Whitt PLLC

20090224355 - Semiconductor device with buffer layer: A semiconductor device in one embodiment includes a depletion junction, a peripheral region adjacent the depletion junction, and a buffer layer. The buffer layer is adapted to reduce localization of avalanche breakdown proximate the interface between the depletion junction and the peripheral region.... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20090224356 - Method and apparatus for thermally aware design improvement: Thermally aware design improvement enables increasing performance, reliability, and other related metrics by performing a multi-dimensional thermal analysis of a design of an electronic component in an assumed operating environment. Results of the analysis are then used to drive optimizations and repairs to the design. The performance metrics include maximum... Agent: Walstein Bennett Smith Iii

20090224357 - Devices with cavity-defined gates and methods of making the same: Disclosed are methods, systems and devices, including a method that includes the acts of forming a semiconductor fin, forming a sacrificial material adjacent the semiconductor fin, covering the sacrificial material with a dielectric material, forming a cavity by removing the sacrificial material from under the dielectric material, and forming a... Agent: Fletcher Yoder (micron Technology, Inc.)

20090224358 - Method and resultant structure for floating body memory on bulk: A method for making floating body memory cells from a bulk substrate. A thin silicon germanium and overlying silicon layers are formed on the bulk substrate. Anchors and a bridge are formed to support the silicon layer when the silicon germanium layer is etched so that it can be replaced... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090224359 - Mom capacitors integrated with air-gaps: An integrated circuit structure combining air-gaps and metal-oxide-metal (MOM) capacitors is provided. The integrated circuit structure includes a semiconductor substrate; a first metallization layer over the semiconductor substrate; first metal features in the first metallization layer; a second metallization layer over the first metallization layer; second metal features in the... Agent: Slater & Matsil, L.L.P.

20090224360 - Semiconductor integrated circuit device and method of fabricating the same: A semiconductor integrated circuit device and a method of fabricating the same may be provided. The semiconductor integrated circuit device may include an align key pattern on a semiconductor substrate, a first passivation layer on the semiconductor substrate including the align key pattern and having a first opening exposing at... Agent: Harness, Dickey & Pierce, P.L.C

20090224361 - Semiconductor package with stacked semiconductor die each having ipd and method of reducing mutual inductive coupling by providing selectable vertical and lateral separation between ipd: A semiconductor package has first and second semiconductor die mounted to a substrate. The first semiconductor die includes a first inductor coil electrically coupled to the substrate. The second semiconductor die is mounted over the first semiconductor die. The second semiconductor die includes a second inductor coil electrically coupled to... Agent: Robert D. Atkins

20090224362 - Electrode structure of memory capacitor and manufacturing method thereof: After a fabrication process intended to miniaturize semiconductor devices, a surface area of a stack capacitor in a random access memory (RAM) is significantly reduced and capacity thereof is thus decreased, which in turn causes the capacitor not able to function properly. The present invention provides a composite lower electrode... Agent: Jianq Chyun Intellectual Property Office

20090224364 - Semiconductor circuit and method of fabricating the same: A bonded semiconductor structure includes a support substrate which carries a first electronic circuit, and an interconnect region carried by the support substrate. The interconnect region includes a capacitor and conductive line in communication with the first electronic circuit. The circuit includes a bonding layer carried by the interconnect region,... Agent: Schmeiser Olsen & Watts

20090224363 - Semiconductor device and manufacturing method thereof: In a manufacturing method of a semiconductor device, an insulating film is formed on a first conductive film. By using a mask film having an opening that exposes the insulating film, anisotropic etching is performed to form a recess is formed in an upper part of the insulating film exposed... Agent: Mcdermott Will & Emery LLP

20090224365 - Semiconductor device comprising passive components: A method of making a semiconductor device includes the steps of: providing a semiconductor substrate (110, 510, 1010, 1610) having a patterned interconnect layer (120, 520, 1020, 1620) formed thereon; depositing a first dielectric material (130, 530, 1030, 1630) over the interconnect layer; depositing a first electrode material (140, 540,... Agent: Bryan Cave LLP

20090224368 - Maskless selective boron-doped epitaxial growth: A semiconductor device, comprising a silicon layer, an n-type field-effect transistor (NFET) disposed in and on a silicon layer, and a p-type field-effect transistor (PFET) disposed in and on the silicon layer, wherein the PFET includes a boron-doped silicon-germanium layer disposed on the silicon layer. Also, a method for manufacturing... Agent: Banner & Witcoff, Ltd.

20090224366 - Semiconductor wafer of single crystalline silicon and process for its manufacture: Semiconductor wafer of monocrystalline silicon contain fluorine, the fluorine concentration being 1·1010 to 1·1016 atoms/cm3, and is free of agglomerated intrinsic point defects whose diameter is greater than or equal to a critical diameter. The semiconductor wafers are produced by providing a melt of silicon which is doped with fluorine,... Agent: Brooks Kushman P.C.

20090224367 - Silicon substrate and manufacturing method thereof: A silicon substrate is manufactured from a single crystal silicon that is doped with phosphorus (P) and is grown by a CZ method to have a predetermined carbon concentration and a predetermined initial oxygen concentration. An n+ epitaxial layer or an n+ implantation layer that is doped with phosphorus (P)... Agent: Greenblum & Bernstein, P.L.C

20090224369 - Ic substrate and method of manufacture of ic substrate: An integrated circuit (IC) substrate (32) comprising a germanium layer (26), an aluminium oxide layer (22), and an interfacial layer (28) provided on the germanium layer between the germanium layer and the aluminium oxide layer, which interfacial layer provides control of electrical properties at an interface between the germanium layer... Agent: Choate, Hall & Stewart LLP

20090224370 - Non-planar cvd diamond-coated cmp pad conditioner and method for manufacturing: The present invention relates to a composite material having non-planar geometries and edge-shaving surfaces comprising a CVD diamond coating applied to a composite substrate made from a ceramic material and a preferably unreacted carbide-forming material of various configurations and for a variety of applications.... Agent: John S. Pratt, Esq Kilpatrick Stockton, LLP

20090224371 - Protection for bonding pads and methods of formation: The formation of bonding pad protective layer over exposed bonding pad materials between stacked integrated circuit (IC) dies or wafers is described in preferred embodiments in which the bonding pad protective layer is formed in the integrated process of forming wafer bonding pads. The bonding pad protective layer prevents the... Agent: Slater & Matsil, L.L.P.

20090224372 - Wafer translator having a silicon core isolated from signal paths by a ground plane: Apparatus and methods are provided for wafer translators having a silicon core, an isolating conductive ground plane, and copper and subjacent resin layers disposed on the ground plane. A silicon substrate having at least one major surface coated with an electrically conductive layer is subjected to a number of printed... Agent: Raymond J. Werner

20090224373 - Integrated circuit and method for manufacturing same: When an integrated circuit having an interlayer insulation film built up on top of a wiring layer is subjected to a heat treatment, it is unlikely that a void formed in the interlayer insulation film will rupture in a portion wherein are connected a narrow gap between wirings and a... Agent: Oliff & Berridge, PLC

20090224374 - Advanced multilayer dielectric cap with improved mechanical and electrical properties: A dielectric cap, interconnect structure containing the same and related methods are disclosed. The inventive dielectric cap includes a multilayered dielectric material stack wherein at least one layer of the stack has good oxidation resistance, Cu diffusion and/or substantially higher mechanical stability during a post-deposition curing treatment, and including Si—N... Agent: Scully, Scott, Murphy & Presser, P.C.

20090224375 - Semiconductor device and semiconductor device manufacturing method: The present invention provides a semiconductor device for which thermal stress at mounting is reduced and a reduction in reliability with regard to moisture absorption is prevented. The semiconductor device includes a uppermost metal layer 12, a solder bump 17, metals 15 and 16 which connect an uppermost metal layer... Agent: Foley And Lardner LLP Suite 500

20090224376 - Circuit board having conductive shield member and semiconductor package using the same: A circuit board having a board body includes a via structure. The via structure includes a conductive connector passing through the board body and a conductive shield member surrounding at least a portion of the conductive connector. The shield member prevents distortion of a data signal applied to the conductive... Agent: Ladas & Parry LLP

20090224379 - Copper alloy sheet and qfn package: A QFN package is provided with a lead frame formed by processing a copper alloy sheet containing 0.01 to 0.50% by mass Fe, 0.01 to 0.20% by mass P, and Cu and inevitable impurities as other components, having a micro Vickers hardness of 150 or above, a uniform elongation of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090224378 - Package structure with embedded die and method of fabricating the same: A package structure with an embedded die includes a core layer, a first build-up wiring structure, and a second build-up wiring structure. The core layer has a first surface and a second surface opposite thereto. Besides, the core layer includes a first dielectric layer, a leadframe, a die, a first... Agent: J C Patents, Inc.

20090224377 - Semiconductor device with wire-bonding on multi-zigzag fingers: A semiconductor device having linear zigzag(s) for wire bonding is revealed, primarily comprising a chip, a plurality of leads made of a lead frame and a plurality of bonding wires electrically connecting the chip and the leads. At least one of the leads has a linear zigzag including a first... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090224380 - Leadframe and semiconductor package having downset baffle paddles: A lead frame with downset baffle paddles and a semiconductor package utilizing the same are revealed. The lead frame primarily comprises a plurality of leads formed oil a first plane, a baffle paddle formed on a second plane in parallel, and an internal tie bar formed between the first plane... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090224381 - Double-faced electrode package and its manufacturing method: A dual-face package has an LSI chip sealed with a mold resin, and electrodes for external connections on both of the front face and the back face. The LSI chip is bonded onto the die pad of a leadframe whose outer lead portions are exposed as back-face electrodes at least... Agent: Mcglew & Tuttle, PC

20090224384 - Chip package: A chip package including a die pad, a plurality of leads, a chip, an adhesive, and a molding compound is provided. The die pad has a top surface and a bottom surface opposite to the top surface, wherein the die pad has a blocking portion disposed on the top surface,... Agent: J C Patents, Inc.

20090224385 - Package structure of integrated circuit device and manufacturing method thereof: A package structure of an integrated circuit device comprises a copper foil substrate, an integrated circuit device, a plurality of metal wires and an encapsulation material. The copper foil substrate comprises an IC bonding area, a plurality of conductive areas and an insulating dielectric material. The integrated circuit device is... Agent: Wpat, PC Intellectual Property Attorneys

20090224383 - Semiconductor die package including exposed connections: A clip structure and semiconductor die package. The clip structure includes a first portion and a second portion, with a connecting structure located between the first and second portion. The clip structure is substantially planar. The semiconductor die package includes a semiconductor die located between a leadframe structure and a... Agent: Townsend And Townsend And Crew, LLP

20090224382 - Semiconductor package with mold lock vent: A semiconductor package including a leadframe having first and second major surfaces and a mold lock opening extending between the first and second major surfaces. The semiconductor package includes a semiconductor die coupled to the first major surface, and an encapsulating material formed about the semiconductor chip and a portion... Agent: Dicke, Billig & Czaja

20090224386 - Optical semiconductor device having pre-molded leadframe with window and method therefor: A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active... Agent: Robert D. Atkins

20090224387 - Semiconductor chip and method for manufacturing the same and semiconductor device: The semiconductor chip 1 has a semiconductor substrate 10. In the present embodiment, the semiconductor substrate 10, which is an SOI substrate, is constituted by comprising a support substrate 12, an insulating layer 14 formed on the support substrate 12 with a layered structure, and a silicon layer 16 formed... Agent: Sughrue Mion, PLLC

20090224389 - Integrated circuit package system with stacked devices: An integrated circuit package system comprising: providing an integrated circuit die having an active side; forming a first internal stacked module and a second internal stacked module over the active side of the integrated circuit die; and coupling an electrical interconnect between the first internal stacked module or the second... Agent: Law Offices Of Mikio Ishimaru

20090224390 - Integrated circuit with step molded inner stacking module package in package system: An integrated circuit package system including: providing a substrate; mounting an integrated circuit above the substrate; mounting an inner stacking module, having an inner stacking module encapsulation and a molded integral step molded in the inner stacking module encapsulation, above the integrated circuit; and encapsulating the inner stacking module, and... Agent: Law Offices Of Mikio Ishimaru

20090224388 - Semiconductor chip stacking for redundancy and yield improvement: A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of... Agent: Scully, Scott, Murphy & Presser, P.C.

20090224393 - Semiconductor device and fabricating method thereof: The present invention provides a semiconductor device capable of eliminating voltage (IR) drop of a semiconductor die inside the semiconductor device and a fabricating method of the semiconductor device. The semiconductor device comprises the semiconductor die, and the semiconductor die comprises a first surface area, a plurality of first pads... Agent: North America Intellectual Property Corporation

20090224392 - Semiconductor package having side walls and method for manufacturing the same: A semiconductor package includes a semiconductor chip having an upper surface, side surfaces connected with the upper surface, and bonding pads formed on the upper surface. A first insulation layer pattern is formed to cover the upper surface and the side surfaces of the semiconductor chip and expose the bonding... Agent: Ladas & Parry LLP

20090224394 - Solid-state image sensing apparatus and package of same: Warpage and twist of a solid-state image sensing apparatus is controlled, thereby preventing displacement occurring to the solid-state image sensing apparatus when it is mounted on a printed circuit board. The solid-state image sensing apparatus comprises a plurality of outer leads, and the outer leads each comprises a horizontal portion... Agent: Young & Thompson

20090224391 - Wafer level die integration and method therefor: A method of manufacturing a semiconductor device includes providing a wafer for supporting the semiconductor device. An insulation layer is disposed over a top surface of the wafer. The method includes forming a first interconnect structure over the top surface of the wafer with temperatures in excess of 200° C.,... Agent: Robert D. Atkins

20090224396 - Oversized contacts and vias in semiconductor chip defined by linearly constrained topology: A rectangular-shaped interlevel connection structure is defined to electrically connect a first structure in a first chip level with a second structure in a second chip level. The rectangular-shaped interlevel connection structure is defined by an as-drawn cross-section having at least one dimension larger than a corresponding dimension of either... Agent: Martine Penilla & Gencarella, LLP

20090224395 - Substrate strip for semiconductor packages: A substrate strip for semiconductor packages to slow the crack growth, primarily comprises a molding area and two side rails. The molding area includes a plurality of packaging units. The side rails are located outside the molding area and include two opposing longer sides of the substrate strip. A metal... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090224397 - Substrate and semiconductor package for lessening warpage: A substrate with reduced substrate warpage and a semiconductor package utilizing the substrate are revealed. The substrate primarily comprises a core where a wiring layer and a first solder mask are formed on one surface of the core, and a second solder mask and a die-attaching layer are formed on... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090224398 - Semiconductor module and method of manufacturing the same: A semiconductor module and a method of manufacturing the same are disclosed including a semiconductor element having an electrode, a heat radiation plate placed in thermal contact with a main surface of the semiconductor element and electrically connected to the electrode thereof, an insulation body directly formed on an outside... Agent: Nixon & Vanderhye, PC

20090224399 - Silicon nitride substrate, method of manufacturing the same, and silicon nitride circuit board and semiconductor module using the same: A silicon nitride substrate having appropriately adjusted warpage and surface roughness can be obtained by mixing magnesium oxide of 3 to 4 wt % and at least one kind of rare-earth element oxide of 2 to 5 wt % with silicon nitride source material powder to form a sheet-molded body,... Agent: Oliff & Berridge, PLC

20090224400 - Semiconductor assembly having reduced thermal spreading resistance and methods of making same: Semiconductor assemblies having reduced thermal spreading resistance and methods of making the same are described. In an example, a semiconductor device includes a primary integrated circuit (IC) die and at least one secondary IC die mounted on the primary IC die. A heat extraction element includes a base mounted to... Agent: Xilinx, Inc Attn: Legal Department

20090224401 - Semiconductor device and manufacturing method thereof: m

20090224404 - Method and system for fabricating semiconductor components with through interconnects: A method for fabricating a semiconductor component with through interconnects can include the steps of providing a semiconductor substrate with substrate contacts, and forming openings from a backside of the substrate aligned with the substrate contacts. The method can also include the steps of providing an interposer substrate (or alternately... Agent: Stephen A Gratton The Law Office Of Steve Gratton

20090224403 - Semiconductor device and method of manufacturing the same: A ball grid array semiconductor device has a wiring substrate (2), a semiconductor chip (6) disposed on one surface side of the wiring substrate, and a bump arrangement (5) as external terminals disposed on a surface side, opposite to the one surface side, of the wiring substrate. The semiconductor chip... Agent: Foley And Lardner LLP Suite 500

20090224402 - Semiconductor package having semiconductor die with internal vertical interconnect structure and method therefor: A semiconductor wafer is made by forming a first conductive layer over a sacrificial substrate, mounting a semiconductor die to the sacrificial substrate, depositing an insulating layer over the semiconductor die and first conductive layer, exposing the first conductive layer and contact pad on the semiconductor die, forming a second... Agent: Robert D. Atkins

20090224405 - Through via process: A through via process is performed on a semiconductor substrate with a contact plug formed in an interlayer dielectric (ILD), and then a via plug is formed in the ILD layer to extend through a portion of the semiconductor substrate, followed forming an interconnection structure electrically connected with the contact... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20090224406 - Dense seed layer and method of formation: Methods of forming dense seed layers and structures thereof are provided. Seed layers including a monolayer of molecules having a density of about 0.5 or greater may be manufactured over a metal layer, resulting in a well-defined interface region between the metal layer and a subsequently formed material layer. A... Agent: Slater & Matsil LLP

20090224408 - Methods for multi-wire routing and apparatus implementing same: A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual... Agent: Martine Penilla & Gencarella, LLP

20090224407 - Semiconductor device: A semiconductor device includes a plurality of first and second pads aligned along a first direction. The lengths of the first pads in parallel with the first direction are longer than those of the second pads in parallel with the first direction.... Agent: Sughrue Mion, PLLC

20090224409 - Semiconductor device: There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of... Agent: Rabin & Berdo, PC

20090224410 - Wafer translator having a silicon core fabricated with printed circuit board manufacturing techniques: Apparatus and methods are provided for wafer translators having a silicon core with copper and subjacent resin layers disposed thereon. A silicon substrate is subjected to a number of printed circuit board manufacturing operations including, but not limited to, application of resin-coated copper foils; mechanical grinding of copper layers; mechanical... Agent: Raymond J. Werner

20090224411 - Multi-chips module package structure and the method thereof: A chip package structure includes a carrier substrate having a circuit in both front side and the reverse side; each chips includes a plurality of pads is arranged near the central region on the active surface; and a polymer material is used to cover the chips and the carrier substrate,... Agent: Sinorica, LLC

20090224412 - Non-planar substrate strip and semiconductor packaging method utilizing the substrate strip: A non-planar substrate strip for semiconductor packages is revealed, primarily comprising a substrate core having an external surface, an external solder mask and a patterned thick solder mask. The external solder mask covers the external surfaces of a plurality of substrate units of the non-planar substrate strip. The patterned thick... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090224413 - Apparatus and methods for determining overlay of structures having rotational or mirror symmetry: Disclosed are overlay targets having flexible symmetry characteristics and metrology techniques for measuring the overlay error between two or more successive layers of such targets. In one embodiment, a target includes structures for measuring overlay error (or a shift) in both the x and y direction, wherein the x structures... Agent: Weaver Austin Villeneuve Sampson LLP - Kla Tencor Kla Tencor

20090218556 - Integrated circuit fabricated using an oxidized polysilicon mask: An integrated circuit includes a first electrode, a second electrode, and dielectric material including an opening. The opening is defined by etching the dielectric material based on an oxidized polysilicon mask formed using a keyhole process. The integrated circuit includes resistivity changing material deposited in the opening and coupled between... Agent: Dicke, Billig & Czaja

20090218557 - Phase change memory device and fabrication method thereof: A phase change memory device is provided in which the area of contact between phase change material and heater electrode is reduced to suppress current required for heating and a phase change region is formed directly on a contact to raise the degree of integration. The device comprises a heater... Agent: Foley And Lardner LLP Suite 500

20090218558 - Semiconductor device and method of forming the same: A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be... Agent: Harness, Dickey & Pierce, P.L.C

20090218559 - Integrated circuit, memory cell array, memory module, and method of manufacturing an integrated circuit: According to one embodiment of the present invention, an integrated circuit is provided including a plurality of magneto-resistive memory cells. Each memory cell includes a magnetic tunneling junction stack, wherein the top surfaces of the magnetic tunneling junctions stacks are electrically connected to a common continuous conductive plate.... Agent: Slater & Matsil, L.L.P.

20090218560 - Method for reversibly mounting a device wafer to a carrier substrate: New temporary bonding methods and articles formed from those methods are provided. The methods comprise bonding a device wafer to a carrier wafer or substrate only at their outer perimeters in order to assist in protecting the device wafer and its device sites during subsequent processing and handling. The edge... Agent: Hovey Williams LLP

20090218562 - High brightness light emitting diode with a bidrectionally angled substrate: A light emitting diode includes a substrate tilted toward first and second directions simultaneously, a first cladding layer formed with a semiconductor material of a first conductive type on the substrate, an active layer formed on the first cladding layer, and a second cladding layer formed with a semiconductor material... Agent: Chapman And Cutler

20090218561 - Organic electroluminescence element: An organic electroluminescence element including at least two light-emitting layers disposed between an anode and a cathode, wherein the at least two light-emitting layers include a light-emitting layer A that contains an electron transporting light-emitting material and a hole transporting host material, wherein a concentration of the electron transporting light-emitting... Agent: Moss & Burke, PLLC

20090218563 - Novel fabrication of semiconductor quantum well heterostructure devices: A device employing a quantum well structure having a pattern that is defined by a photolithographically patterned top gate electrode. By defining the active area of the quantum well structure by the patterning of the top gate electrode there is no need to pattern the quantum well structure itself, such... Agent: Zilka-kotab, PC- Hit

20090218564 - Alternating copolymers of phenylene vinylene and biarylene vinylene, preparation method thereof, and organic thin flim transister comprising the same: Disclosed herein are an alternating copolymer of phenylene vinylene and biarylene vinylene, a preparation method thereof, and an organic thin film transistor including the same. The organic thin film transistor maintains low off-state leakage current and realizes a high on/off current ratio and high charge mobility because the organic active... Agent: Harness, Dickey & Pierce, P.L.C

20090218565 - Resistance variable element: A resistance variable element is provided, which is capable of performing bipolar operation by a specified mechanism and usable as a memory. The resistance variable element has a laminated structure including an electrode, an electrode, an oxide layer between the electrodes, and an oxide layer in contact with the oxide... Agent: Greer, Burns & Crain

20090218566 - Localized compressive strained semiconductor: One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline semiconductor bridge is formed over a substrate. The bridge has a first portion bonded to the substrate, a second portion bonded to the substrate, and... Agent: Schwegman, Lundberg & Woessner/micron

20090218567 - Conductive bridge random access memory device and method of making the same: A method for making a semiconductor device (10) includes providing an interconnect layer (14) over an underlying layer (12), forming a first insulating layer (16) over the interconnect layer, and forming an opening (18) through the insulating layer to the interconnect layer. A first conductive layer (24) is formed over... Agent: Freescale Semiconductor, Inc. Law Department

20090218568 - Thin film transisotr and display device: To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating... Agent: Nixon Peabody, LLP

20090218571 - Active device array substrate and fabrication method thereof: A fabrication method of an active device array substrate is disclosed. A first metal material layer, a gate insulation material layer, a channel material layer, a second metal material layer, and a first photoresist layer are formed over a substrate sequentially. The first photoresist layer is patterned with a multi-tone... Agent: Jianq Chyun Intellectual Property Office

20090218569 - Display device: In a dummy pixel portion (122) of the present display device, the number of gate electrodes in a thin film transistor formed by a semiconductor layer (11) is reduced to two, so that distances from a contact hole (12) to another contact hole (13) and to a through-hole (14) can... Agent: Harness, Dickey & Pierce, P.L.C

20090218573 - Electric device: There is provided an electric device which can prevent a deterioration in a frequency characteristic due to a large electric power external switch connected to an opposite electrode and can prevent a decrease in the number of gradations. The electric device includes a plurality of source signal lines, a plurality... Agent: Cook Alex Ltd

20090218570 - Thin film transistor and flat panel display device including the same: A thin film transistor includes a channel layer including an amorphous 12CaO.7Al2O3 (C12A7) and a flat panel display device including the same. According to the present invention, the amorphous channel layer can be formed at a low temperature using C12A7. The thin film transistor including the amorphous channel layer has... Agent: Stein Mcewen, LLP

20090218572 - Thin-film transistor and display device: A thin-film transistor in which problems with ON-state current and OFF-state current are solved, and a thin-film transistor capable of high-speed operation. The thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions,... Agent: Nixon Peabody, LLP

20090218574 - Display device and manufacturing method therefor: A display device includes a thin film transistor above a substrate, in which the thin film transistor is configured to include a gate electrode, a gate insulating film formed to cover the gate electrode, a semiconductor layer formed to stride over the gate electrode on the gate insulating film, an... Agent: Juan Carlos A. Marquez C/o Stites & Harbison PLLC

20090218575 - Display device and manufacturing method thereof: Provided is a display device including a p-type thin film transistor formed on a substrate, in which the p-type thin film transistor includes: a gate electrode; a drain electrode; a source electrode; an insulating film; a semiconductor layer formed on a top surface of the gate electrode through the insulating... Agent: Juan Carlos A. Marquez C/o Stites & Harbison PLLC

20090218576 - Thin-film transistor and display device: A thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions so as to be overlapped at least partly with a gate electrode with a gate insulating layer interposed between the gate electrode... Agent: Nixon Peabody, LLP

20090218577 - High throughput crystallization of thin films: Under one aspect, a method of processing a film includes defining a plurality of spaced-apart regions to be crystallized within a film, the film being disposed on a substrate and capable of laser-induced melting; generating a sequence of laser pulses having a fluence that is sufficient to melt the film... Agent: Wilmerhale/columbia University

20090218578 - Semiconductor device: A semiconductor device comprises an AlN layer, a GaN layer, and an AlGaN layer sequentially formed on a semiconductor substrate. A first opening extends through said GaN layer and said AlGaN layer and exposes part of an upper surface of the AlN layer. A second opening extends through the semiconductor... Agent: Leydig Voit & Mayer, Ltd

20090218579 - Substrate heating apparatus, semiconductor device manufacturing method, and semiconductor device: In a substrate heating apparatus, thermoelectrons generated by a filament (132) in a vacuum heating vessel (103) are accelerated to collide against a conductive heater (131) which forms one surface of the vacuum heating vessel (103), thus generating heat. The conductive heater (131) is made of carbon. At least one... Agent: Fitzpatrick Cella Harper & Scinto

20090218580 - Structure of ac light-emitting diode dies: A structure of light-emitting diode (LED) dies having an AC loop (a structure of AC LED dies), which is formed with at least one unit of AC LED micro-dies disposed on a chip. The unit of AC LED micro-dies comprises two LED micro-dies arranged in mutually reverse orientations and connected... Agent: Rabin & Berdo, PC

20090218585 - aluminate phosphor containing bivalence metal elements, its preparation and the light emitting devices incorporating the same: A phosphor can be excited by UV, purple or blue light LED, its production and the light emitting devices. The general formula of the phosphor is LnaMb(O,F)12:(R3+, M′2+)x, wherein, Ln is at least one metal element selected from a group consisting of Sc, Y, La, Pr, Nd, Gd, Ho, Yb... Agent: Staas & Halsey LLP

20090218584 - Housing for an optoelectronic component, optoelectronic component, and method for producing a housing for an optoelectronic component: A housing for an optoelectronic component is disclosed, having a plastic base body that has a front side with an assembly region for at least one radiation emitting or radiation detecting body, wherein the plastic base body is formed from at least one first plastic component and at least one... Agent: Slater & Matsil, L.L.P.

20090218581 - Illumination system comprising a radiation source and a luminescent material: An illumination system, comprising a radiation source (1) and a luminescent material (3,4,5) comprising at least one phosphor capable of absorbing a part of light emitted by the radiation source and emitting light of wavelength different from that of the absorbed light; wherein said at least one phosphor is a... Agent: Philips Intellectual Property & Standards

20090218583 - Light-emitting device, electronic apparatus, and light-emitting device manufacturing method: Disclosed is a light-emitting device. The light-emitting device includes an EL layer and a heat dissipation layer. The EL layer includes a first semiconductor layer, a second semiconductor layer, and an active layer, the first semiconductor layer having a first conductivity type that is one of n type and p... Agent: Sonnenschein Nath & Rosenthal LLP

20090218582 - Optical device and method of fabricating the same: A method of fabricating an optical device is disclosed. The method comprises the step of forming an optical stack of laminated lenses and a phosphor film therebetween. The method further comprises the step of attaching the optical stack to an LED die. In addition, an optical device fabricated by the... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090218588 - Chip-scale packaged light-emitting devices: Light-emitting devices, and related components, systems, and methods associated therewith are provided. A light-emitting device can comprise a light-emitting die comprising a light-generating region capable of generating light and an emission surface through which generated light is capable of being emitted, and a package layer at least partially disposed over... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.C.

20090218586 - Led lamp: The present invention relates to a light emitting diode (LED) lamp, and an object of the present invention is to provide an LED lamp in which an LED can be easily exchanged and external vibration can be absorbed to prevent the play thereof. To this end, an LED lamp according... Agent: H.c. Park & Associates, PLC

20090218590 - Method of producing thin semiconductor structures: A method of making a thin gallium-nitride (GaN)-based semiconductor structure is provided. According to one embodiment of the invention, the method includes the steps of providing a substrate; sequentially forming one or more semiconductor layers on the substrate; etching a pattern in the one or more semiconductor layers; depositing a... Agent: Venable LLP

20090218587 - Radiation-emitting semiconductor body with carrier substrate and method for the production thereof: A radiation-emitting semiconductor body with a carrier substrate and a method for producing the same. In the method, a structured connection is produced between a semiconductor layer sequence (2) and a carrier substrate wafer (1). The semiconductor layer sequence is subdivided into a plurality of semiconductor layer stacks (200) by... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090218589 - Semiconductor die with reduced thermal boundary resistance: Thermal boundary resistances within nitride semiconductor LEDs are reduced or eliminated by forming a thick nitride epitaxial layer, which can be separated from a growth substrate, and by reducing the number of thermal boundary layers during laser lift-off. The thermal boundary resistances within nitride semiconductor LEDs can also be reduced... Agent: Goldeneye, Inc.

20090218591 - Method for connecting layers, corresponding component and organic light-emitting diode: A method for bonding several layers, which comprise at least one thermally bondable material, by means of a joint layer produced with the aid of thermocompression at least one of the layers comprising a semiconductor material, as well as to a correspondingly manufactured device. Also disclosed is a method for... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090218592 - Method of producing encapsulation resins: A process is provided for producing curable polyorganosiloxanes where noble metal oxides are used as hydrosilylation catalysts. The noble metals can be used in solid granular form or as part of a fixed bed, and do not form part of the final curable composition or cured product. The cured polyorganosiloxanes... Agent: Berliner & Associates

20090218593 - Nitride semiconductor light emitting device and method of frabicating nitride semiconductor laser device: There is provided a nitride semiconductor light emitting device having a light emitting portion coated with a coating film, the light emitting portion being formed of a nitride semiconductor, the coating film in contact with the light emitting portion being formed of an oxynitride. There is also provided a method... Agent: Harness, Dickey & Pierce, P.L.C

20090218594 - Semiconductor light receiving element: A semiconductor photosensitive element comprises: a semiconductor substrate of a first conductivity type; a first light absorption layer, a first semiconductor layer of a second conductivity type, a first semiconductor layer of the first conductivity type, a second light absorption layer, and a second semiconductor layer of a second conductivity... Agent: Leydig Voit & Mayer, Ltd

20090218595 - Semiconductor light receiving element: A semiconductor light detecting element comprises: a semiconductor substrate having a first major surface and a second major surface opposite each other; a first reflective layer, an absorptive layer, a phase adjusting layer, and a second reflective layer sequentially disposed, from the semiconductor substrate, on the first major surface of... Agent: Leydig Voit & Mayer, Ltd

20090218596 - Buffer layers for device isolation of devices grown on silicon: Various embodiments provide a buffer layer that is grown over a silicon substrate that provides desirable device isolation for devices formed relative to III-V material device layers, such as InSb-based devices, as well as bulk thin film grown on a silicon substrate. In addition, the buffer layer can mitigate parallel... Agent: Lee & Hayes, PLLC C/o Intellevate, LLC

20090218597 - Method for fabricating a semiconductor device having an epitaxial channel and transistor having same: A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening... Agent: Brinks Hofer Gilson & Lione

20090218598 - Warp-free semiconductor wafer, and devices using the same: A semiconductor wafer to be diced into individual SBDs, HEMTs or MESFETs has a substrate with a main semiconductor region and counter semiconductor region formed on its opposite surfaces. The main semiconductor region is configured to provide the desired semiconductor devices. In order to counterbalance the warping effect of the... Agent: Woodcock Washburn LLP

20090218599 - Polarization-induced barriers for n-face nitride-based electronics: A method for fabricating a potential barrier for a nitrogen-face (N-face) nitride-based electronic device, comprising using a thickness and polarization induced electric field of a III-nitride interlayer, positioned between a first III-nitride layer and a second III-nitride layer, to shift, e.g., raise or lower, the first III-nitride layer's energy band... Agent: Gates & Cooper LLP Howard Hughes Center

20090218600 - Memory cell layout: A method for manufacturing an integrated circuit and an integrated circuit are described. In one embodiment, the method for manufacturing the integrated circuit includes determining a layout for numerous memory elements based on memory-specific parameters, and determining a layout for a front-end-of-line (FEOL) component of the integrated circuit based on... Agent: Slater & Matsil, L.L.P.

20090218601 - Temperature monitoring in a semiconductor device by using an pn junction based on silicon/germanium material: By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence,... Agent: Williams, Morgan & Amerson

20090218602 - Photoelectric conversion device, its manufacturing method, and image pickup device: It is an object of the present invention to provide a manufacturing method of a photoelectric conversion device in which no plane channeling is produced even if ions are injected at a certain elevation angle into a semiconductor substrate surface made of silicon. A manufacturing method of a photoelectric conversion... Agent: Fitzpatrick Cella Harper & Scinto

20090218603 - Semiconductor device structures and methods of forming semiconductor structures: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090218605 - Methods of enhancing performance of field-effect transistors and field-effect transistors made thereby: Methods of enhancing the performance of a field-effect transistor (FET) by providing a percolating network of metallic islands to the inversion layer of the FET so as to effectively reduce the channel length of the FET. The metal islands can be provided in a number of ways, including Volmer-Weber metallic... Agent: Downs Rachlin Martin PLLC

20090218604 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a PMOS transistor of a peripheral circuit region. The PMOS transistor is formed over a silicon germanium layer to have a compressive strain structure, thereby increasing hole mobility of a channel region in operation of the device. The semiconductor device may include a second active region... Agent: Marshall, Gerstein & Borun LLP

20090218606 - Vertically integrated light sensor and arrays: Embodiments hereof include a photosensing device, comprising an isolation layer; a photodetector layer comprising a plurality of pixels, wherein the photodetector layer is in contact with a first side of the isolation layer, wherein the photodetector layer comprises a laser-processed semiconductor material; and a semiconductor layer disposed on a second... Agent: Pepper Hamilton LLP

20090218607 - Nonvolatile semiconductor memory and manufacturing method thereof: A nonvolatile semiconductor memory of an aspect of the invention includes memory cells in the memory cell forming area, and select gate transistors in the select gate forming area. Each memory cell has two first diffusion layers formed in a semiconductor substrate, a first gate insulating film formed on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090218608 - Semiconductor integrated circuit device and method of manufacturing the same: In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090218610 - Semiconductor memory devices including diagonal bit lines: A semiconductor memory device may include a semiconductor substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality... Agent: Myers Bigel Sibley & Sajovec

20090218609 - Semiconductor memory devices including offset bit lines: A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of... Agent: Myers Bigel Sibley & Sajovec

20090218611 - High density stepped, non-planar flash memory: A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same column. The second plurality of memory cells are coupled to the first plurality of memory cells through a... Agent: Leffert Jay & Polglaze, P.A.

20090218612 - Memory utilizing oxide-conductor nanolaminates: Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is separated from the channel region by a first gate oxide. The floating gate includes... Agent: Schwegman, Lundberg & Woessner, P.A.

20090218614 - Semiconductor storage device and method for manufacturing the same: A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090218613 - Semiconductor time switch suitable for embedding in nand flash memory device: A semiconductor time switch includes a cell portion and an electron booster. The cell portion contains parallel linear semiconductor layers provided on a substrate as active areas, first and second linear conductor layers alternately formed on the linear semiconductor layers through a gate insulating film as control gates and extending... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090218615 - Semiconductor device and method of manufacturing the same: A semiconductor device according to an embodiment of the present invention has a bit line and a word line. The device includes a substrate, a first gate insulation film formed on the substrate, a charge storage layer formed on the first gate insulation film, a second gate insulation film formed... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090218617 - Superjunction power semiconductor device: A superjunction power semiconductor device which includes spaced drift regions each extending from the bottom of a respective gate trench to the substrate of the device.... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20090218616 - Transistor having vertical channel and method for fabricating the same: A semiconductor device including vertical channel transistor and a method for forming the transistor, which can significantly decrease the resistance of a word line is provided. A vertical channel transistor includes a substrate including pillars each of which has a lower portion corresponding to a channel region. A gate insulation... Agent: Townsend And Townsend And Crew, LLP

20090218618 - Semiconductor device and method for forming same: A semiconductor device and method. One embodiments provides a semiconductor substrate having a trench with a sidewall isolation comprising a first isolating material, a field electrode formed in lower portion of the trench, a cover comprising a second material above the field electrode, the second material being selectively etchable to... Agent: Dicke, Billig & Czaja

20090218619 - Self-aligned slotted accumulation-mode field effect transistor (accufet) structure and method: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall... Agent: Bo-in Lin

20090218620 - High power and high temperature semiconductor power devices protected by non-uniform ballasted sources: This invention discloses a semiconductor power device disposed on a semiconductor substrate supporting an epitaxial layer as a drift region composed of an epitaxial layer. The semiconductor power device further includes a super-junction structure includes a plurality of doped sidewall columns disposed in a multiple of epitaxial layers. The epitaxial... Agent: Bo-in Lin

20090218621 - Semiconductor component with a drift region and a drift control region: A semiconductor component with a drift region and a drift control region. One embodiment includes a semiconductor body having a drift region of a first conduction type in the semiconductor body. A drift control region composed of a semiconductor material, which is arranged, at least in sections, is adjacent to... Agent: Dicke, Billig & Czaja

20090218622 - Ldmos transistor: The LDMOS transistor (1) of the invention comprises a source region (3), a channel region (4), a drain extension region (7) and a gate electrode (10). The LDMOS transistor (1) further comprises a first gate oxide layer (8) and a second gate oxide layer (9), which is thicker than the... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090218623 - Soi devices and methods for fabricating the same: Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated... Agent: Birch Stewart Kolasch & Birch

20090218624 - Soi device having an increasing charge storage capacity of transistor bodies and method for manufacturing the same: An SOI device includes an SOI substrate having a stacked structure including a buried oxide layer and a first silicon layer sequentially stacked on a silicon substrate. The SOI substrate possesses grooves having a depth that extends from an upper surface of the first silicon layer to a partial depth... Agent: Ladas & Parry LLP

20090218625 - Modified hybrid orientation technology: A semiconductor process and apparatus includes forming first and second metal gate electrodes (151, 161) over a hybrid substrate (17) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122)... Agent: Hamilton & Terrile, LLP - Freescale

20090218626 - Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device: In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090218629 - Etch stop layer of reduced thickness for patterning a dielectric material in a contact level of closely spaced transistors: In a dual stress liner approach, an intermediate etch stop material may be provided on the basis of a plasma-assisted oxidation process rather than by deposition so the corresponding thickness of the etch stop material may be reduced. Consequently, the resulting aspect ratio may be less pronounced compared to conventional... Agent: Williams, Morgan & Amerson

20090218627 - Field effect device structure including self-aligned spacer shaped contact: A semiconductor structure and a method for fabricating the semiconductor structure include or provide a field effect device that includes a spacer shaped contact via. The spacer shaped contact via preferably comprises a spacer shaped annular contact via that is located surrounding and separated from an annular spacer shaped gate... Agent: Scully, Scott, Murphy & Presser, P.C.

20090218628 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a NMOS transistor of a peripheral circuit region. The NMOS transistor is formed over a relaxed silicon germanium layer and a silicon layer to have a tensile strain structure, thereby increasing electron mobility of a channel region in operation of the device. The semiconductor device may... Agent: Marshall, Gerstein & Borun LLP

20090218630 - Semiconductor device including mos field effect transistor having offset spacers or gate sidewall films on either side of gate electrode and method of manufacturing the same: First and second impurity doped regions are formed in a semiconductor substrate. A first gate electrode is formed on the first impurity doped region with a first gate insulation film interposed therebetween. A second gate electrode is formed on the second impurity doped region with a second gate insulation film... Agent: Foley And Lardner LLP Suite 500

20090218633 - Cmos device comprising an nmos transistor with recessed drain and source areas and a pmos transistor having a silicon/germanium material in the drain and source areas: A recessed transistor configuration may be provided selectively for one type of transistor, such as N-channel transistors, thereby enhancing strain-inducing efficiency and series resistance, while a substantially planar configuration or raised drain and source configuration may be provided for other transistors, such as P-channel transistors, which may also include a... Agent: Williams, Morgan & Amerson

20090218632 - Cmos structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication: A semiconductor structure and a method for fabricating the semiconductor structure include a hybrid orientation substrate having a first active region having a first crystallographic orientation that is vertically separated from a second active region having a second crystallographic orientation different than the first crystallographic orientation. A first field effect... Agent: Scully, Scott, Murphy & Presser, P.C.

20090218634 - Semiconductor device and manufacturing method of the same: Provided is a highly reliable semiconductor device equipped with a plurality of semiconductor elements having desired properties, respectively; and a manufacturing method facilitating the manufacture of the semiconductor device. The semiconductor device is manufactured by forming a gate-electrode metal film having a thickness of from 3 to 30 nm over... Agent: Mcdermott Will & Emery LLP

20090218631 - Sram cell having asymmetric pass gates: Conductive stripes laterally abutting the dielectric lines are formed over a thin semiconductor layer on a gate dielectric. Angled halo ion implantation is performed to implant p-type dopants on the side of the drains of pull-down transistors and a first source/drain region of each pass gate transistor. The dielectric lines... Agent: Scully, Scott, Murphy & Presser, P.C.

20090218635 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device includes forming a transistor having a stacked structure in a peripheral circuit region to increase net die and forming a metal silicide layer over a source/drain region of a transistor formed over an upper layer to reduce a contact resistance. The semiconductor device... Agent: Marshall, Gerstein & Borun LLP

20090218636 - Integrated circuit system for suppressing short channel effects: An integrated circuit system that includes: providing a substrate including an active device with a gate and a gate dielectric; forming a first liner, a first spacer, a second liner, and a second spacer adjacent the gate; forming a material layer over the integrated circuit system; forming an opening between... Agent: Law Offices Of Mikio Ishimaru

20090218637 - Non-volatile semiconductor memory device and depletion-type mos transistor: A source-drain diffusion region of the first conductivity type is formed on the surface of the semiconductor layer to sandwich the gate electrode and has a second impurity concentration greater than the first impurity concentration. An overlapping region of the first conductivity type is formed on the surface of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090218638 - Nand flash peripheral circuitry field plate: A high voltage device for use in periphery circuitry of a NAND flash memory device comprising a field plate.... Agent: Cool Patent, P.C. C/o Cpa Global

20090218639 - Semiconductor device comprising a metal gate stack of reduced height and method of forming the same: By providing a CMP stop layer in a metal gate stack, the initial height thereof may be efficiently reduced after the definition of the deep drain and source areas, thereby providing enhanced process conditions for forming highly stressed dielectric materials. Consequently, the dielectric material may be positioned more closely to... Agent: Williams, Morgan & Amerson

20090218640 - Self aligned silicided contacts: Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over the liner. A first contact plug is... Agent: Slater & Matsil LLP

20090218641 - Piezoelectric substrate, fabrication and related methods: Improved methods, and related systems and devices, for fabricating selectively patterned piezoelectric substrates suitable for use in a wide variety of systems and devices. A method can include providing a piezoelectric substrate having a protrusion of substrate material, depositing an electrically conductive coating so as to cover a portion of... Agent: Townsend And Townsend And Crew, LLP

20090218642 - Microelectromechanical systems component and method of making same: A microelectromechanical systems (MEMS) component 20 includes a portion 32 of a MEMS structure 30 formed on a semiconductor substrate 34 and a portion 36 of the structure 30 formed in a non-semiconductor substrate 22. The non-semiconductor substrate 22 is in fixed communication with the semiconductor substrate 34 with the... Agent: Meschkow & Gresham, P.L.C

20090218643 - Semiconductor pressure sensor: Each of the aluminum electrodes that is likely to be corroded portions is prevented from being corroded by forming a titanium-tungsten layer and gold layer on the aluminum electrode. The connecting wires are prevented from being corroded by corrosive matters by using gold wires. The I/O terminals are also prevented... Agent: Crowell & Moring LLP Intellectual Property Group

20090218645 - multi-state spin-torque transfer magnetic random access memory: A multi-state spin-torque transfer magnetic random access memory (STTMRAM) is formed on a film and includes a first magnetic tunneling junctions (MTJ) having a first fixed layer, a first sub-magnetic tunnel junction (sub-MTJ) layer and a first free layer. The first fixed layer and first free layer each have a... Agent: Ipxlaw Group LLP

20090218644 - Integrated circuit, memory device, and method of manufacturing an integrated circuit: According to one embodiment of the present invention, an integrated circuit including a plurality of conductive lines is provided. The conductive lines are configured to guide electric currents or voltages. The conductive lines are at least partially surrounded by material which increases the electric field confinement of electric fields occurring... Agent: Slater & Matsil, L.L.P.

20090218646 - Electromagnetic wave detecting element: The present invention is to provide an electromagnetic wave detecting element that can suppress a decrease in utilization efficiency of electromagnetic waves at sensor portions. An upper electrode of each of plural sensor portions, that are provided in correspondence with intersection portions of plural scan lines and plural signal lines... Agent: Moss & Burke, PLLC

20090218647 - Semiconductor radiation detector with thin film platinum alloyed electrode: A compound semiconductor radiation detector includes a body of compound semiconducting material having an electrode on at least one surface thereof. The electrode includes a layer of a compound of a first element and a second element. The first element is platinum and the second element includes at least one... Agent: The Webb Law Firm, P.C.

20090218648 - Near-field optical probe based on soi substrate and fabrication method thereof: Provided is near-field optical probe including: a cantilever arm support portion that is formed of a lower silicon layer of a silicon-on-insulator (SOI) substrate, the cantilever arm support portion having a through hole formed therein at a side of the lower silicon layer; and a cantilever arm forming of a... Agent: Ladas & Parry LLP

20090218649 - Highly efficient silicon detector with wide spectral range: High efficiency silicon radiation detector from ultraviolet to near infrared region, including a structure with a wide spectral range that work at the ultraviolet region, said structure, comprises a silicon photodetector with an excess of silicon 3-10%, and annealing temperature at 1100° C., increasing the wave length range from 200... Agent: Carmen Pili Ekstrom

20090218650 - Image sensor device with submicron structure: An image sensor device is disclosed. The image sensor device comprises a substrate having a pixel region and at least one integrated circuit in the substrate of the pixel region. A photodiode is disposed on the substrate of the pixel region, comprising a lower electrode, a transparent upper electrode and... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090218651 - Composite substrates for thin film electro-optical devices: An electro-optic device includes at least one electro-optic module having first and second conductive layers and at least first and second semiconductor layers disposed between the conductive layers. At least one optically transparent, electrically insulating base substrate is disposed on the module. The base substrate has a plurality of grooves... Agent: Mayer & Williams PC

20090218652 - Device comprising electrode pad: A pad structure 100 includes an electrode pad (a first electrically conducting film 104 and a second electrically conducting film 110) and an insulating film provided over a peripheral region of the electrode pad so as to surround the electrode pad, and the insulating film has a structure including a... Agent: Young & Thompson

20090218653 - Exposure apparatus, method for cleaning member thereof, maintenance method for exposure apparatus, maintenance device, and method for producing device: A lithography apparatus includes a part having a photocatalytic coating. The lithography apparatus can be an extreme ultraviolet lithography apparatus or an immersion lithography apparatus.... Agent: Oliff & Berridge, PLC

20090218654 - Semiconductor memory devices including extended memory elements: A semiconductor memory device may include a semiconductor substrate having an active region thereof, and the active region may have a length and a width, with the length being greater than the width. A field isolation layer may be on the semiconductor substrate surrounding the active region. First and second... Agent: Myers Bigel Sibley & Sajovec

20090218655 - Integrated passive devices: The specification describes an integrated passive device (IPD) that is formed on a polysilicon substrate. A method for making the IPD is disclosed wherein the polysilicon substrate is produced starting with a single crystal handle wafer, depositing a thick substrate layer of polysilicon on one or both sides of the... Agent: Law Office Of Peter V.d.wilde

20090218656 - Methods of making semiconductor structures including vertical diode structures: Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the... Agent: Trask Britt, P.C./ Micron Technology

20090218657 - Inductively coupled integrated circuit with near field communication and methods for use therewith: A circuit includes a first integrated circuit or die having a first circuit and a first inductive interface. A second integrated circuit or die includes a second circuit and a second inductive interface, wherein the first inductive interface and the second inductive interface are aligned to magnetically communicate first signals... Agent: Garlick Harrison & Markison

20090218658 - Semiconductor device, electronic device, and manufacturing method of the same: The present invention provides a technology that makes it possible to enhance the gain and the efficiency of an RF bipolar transistor. Device isolation is given between a p+ type isolation region and an n+ type collector embedded region and between a p+ type isolation region and an n type... Agent: Miles & Stockbridge PC

20090218659 - Chamfered freestanding nitride semiconductor wafer and method of chamfering nitride semiconductor wafer: Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges... Agent: Mcdermott Will & Emery LLP

20090218660 - Semiconductor substrate, semiconductor device and method of manufacturing the same: A semiconductor substrate (1) includes a plurality of semiconductor elements (2) in which functional elements are constructed and which is formed in a grid pattern, wherein continuous linear grooves (3) are formed on longitudinal and lateral separating lines (4) that individually separate the plurality of semiconductor elements (2) with the... Agent: Steptoe & Johnson LLP

20090218661 - Silicon substrate and manufacturing method thereof: A silicon substrate is manufactured from single-crystal silicon which is grown to have a carbon concentration equal to or higher than 1.0×1016 atoms/cm3 and equal to or lower than 1.6×1017 atoms/cm3 and an initial oxygen concentration equal to or higher than 1.4×1018 atoms/cm3 and equal to or lower than 1.6×1018... Agent: Greenblum & Bernstein, P.L.C

20090218662 - Semiconductor device: A semiconductor device includes: a first semiconductor region of a first conductive type; a second semiconductor region of the first conductive type formed on an upper surface of the first semiconductor region and having a lower impurity concentration than that of the first semiconductor region; a third semiconductor region of... Agent: Wilmerhale/dc

20090218663 - Lead frame based semiconductor package and a method of manufacturing the same: A method of manufacturing a semiconductor package, where the package includes a surface for attachment of the package to a device by a joint formed of a connective material in a joint area of the surface. The method is characterised in that it comprises the step of patterning one or... Agent: Freescale Semiconductor, Inc. Law Department

20090218664 - Structure of a lead-frame matrix of photoelectron devices: A structure of a lead-frame matrix of photoelectron devices is provided. The lead-frame matrix is used to fabricate a first lead-frame array and a second lead-frame array. In the structure of the lead-frame matrix of the photoelectron devices, pins of the first lead-frame array and pins of the second lead-frame... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090218665 - Power device package and method of fabricating the same: Provided are a power device package, which can be made compact by mounting semiconductor chips in recesses formed in a substrate and improve operational reliability by rapidly dissipating heat generated during operation to the outside, and a method of fabricating the power device package. The power device package includes: a... Agent: Townsend And Townsend And Crew, LLP

20090218666 - Power device package and method of fabricating the same: Provided are a power device package, which can be made compact by vertically stacking substrates on which semiconductor chips are mounted, and a method of fabricating the power device package. The power device package includes: a first substrate comprising a first surface and a second surface opposite to each other,... Agent: Townsend And Townsend And Crew, LLP

20090218667 - Smart cards and methods for producing a smart card: The invention relates to smart cards. In one embodiment a smart card has a card body having at least a first, a second and a third layer. The first and the second layer are at least partly composed of polycarbonate. The third layer is arranged between the first and the... Agent: Infineon Technologies Ag Patent Department

20090218668 - Double-side mountable mems package: The MEMS package has a mounting substrate on which one or more transducer chips are mounted wherein the mounting substrate has an opening. A top cover is attached to and separated from the mounting substrate by a spacer forming a housing enclosed by the top cover, the spacer, and the... Agent: Saile Ackerman LLC

20090218669 - Multi-chip package structure and method of fabricating the same: A method of fabricating a multi-chip package structure is provided. In the method, a number of cavities are formed on a predetermined cutting line of a first wafer by partly removing the first wafer and a first metal layer. Conductive walls of a first circuit layer are electrically connected to... Agent: J C Patents, Inc.

20090218671 - Semiconductor device and method of fabricating the same: In a semiconductor device of the present invention, semiconductor chips are stacked in multi-layers. Each of the semiconductor chip includes: through vias extending through a top main surface thereof to a bottom surface opposite to the top main surface; a circuit element surface formed on the top main surface; pads... Agent: Mcdermott Will & Emery LLP

20090218670 - Storage medium and semiconductor package: A semiconductor package includes a semiconductor chip formed with a non-volatile semiconductor memory, a resin encapsulation that encapsulates the semiconductor chip, electrodes in a lattice (solder balls) formed and arrayed in a lattice on a bottom surface of the resin encapsulation. The solder balls include a signal electrode formed within... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090218675 - Multipackage module having stacked packages with asymmetrically arranged die and molding: Semiconductor chip packages have die asymmetrically arranged on the respective substrates. Two such packages having complementary arrangements can be stacked, one inverted with respect to the other, such that the two die are situated side-by-side in the space between the two substrates. Also, multipackage modules include stacked packages, each having... Agent: Law Offices Of Mikio Ishimaru

20090218674 - Semiconductor module: A semiconductor module including: a semiconductor chip, an integrated circuit being formed in the semiconductor chip; a plurality of electrodes electrically connected to the integrated circuit; an insulating film formed on the semiconductor chip and having a plurality of openings positioned corresponding to the plurality of electrodes; and a long... Agent: Harness, Dickey & Pierce, P.L.C

20090218673 - Semiconductor package having a bridge plate connection: A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area, a patterned source connection having a plurality of dimples formed thereon coupling... Agent: Schein & Cai LLP James Cai

20090218672 - Solder resist material, wiring board using the solder resist material, and semiconductor package: The present invention provides a solder resist material, which can suppress the warpage of a semiconductor package upon exposure to heat or impact even when used in a thin wiring board and meets a demand for size reduction in electronic devices and a higher level of integration, and a wiring... Agent: Ditthavong Mori & Steiner, P.C.

20090218676 - Semiconductor device: A small-sized surface mount package having a low on-resistance is achieved, in which a power MOSFET etc. is sealed. In one side a molding resin, two silicon chips are sealed. On one side of the molding resin, three source leads and one gate lead are arranged. The three source leads... Agent: Miles & Stockbridge PC

20090218677 - Board-on-chip type substrates with conductive traces in multiple planes, semiconductor device packages including such substrates, and associated methods: A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed... Agent: Trask Britt, P.C./ Micron Technology

20090218679 - Chip package and process thereof: A chip package is disclosed. The chip package comprises a chip, a plurality of bond pads, a plurality of connecting lines and a rigid cover. The chip has a plurality of recesses arranged along at least an edge of the chip and also has an active surface and a backside.... Agent: J C Patents, Inc.

20090218678 - Semiconductor ic-embedded substrate and method for manufacturing same: A semiconductor IC-embedded substrate suitable for embedding a semiconductor IC in which the electrode pitch is extremely narrow. The substrate comprises a semiconductor IC 120 in which stud bumps 121 are provided to the principal surface 120a, a first resin layer 111 for covering the principal surface 120a of the... Agent: Wolff Law Office, PLLC

20090218680 - Process of grounding heat spreader/stiffener to a flip chip package using solder and film adhesive: A method of grounding a heat spreader/stiffener to a flip chip package comprising the steps of attaching an adhesive film to a substrate and attaching a stiffener to the adhesive film. The adhesive film may have a number of first holes corresponding with a number of grounding pads on the... Agent: Christopher P Maiorana, PC Lsi Corporation

20090218681 - Carbon nanotube and metal thermal interface material, process of making same, packages containing same, and systems containing same: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can... Agent: Intel Corporation C/o Cpa Global

20090218682 - Semiconductor chip: An integrated circuit package comprising at least one semiconductor chip of a first material, wherein the semiconductor chip comprises an active part and a passive part that is connected to each other, the passive part comprises at least one cavity, the at least one cavity is filled with a filler... Agent: Warren A. Sklar (soer) Renner, Otto, Boisselle & Sklar, LLP

20090218683 - Semiconductor device: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the... Agent: Miles & Stockbridge PC

20090218684 - Autoclave capable chip-scale package: A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.... Agent: Ostrolenk Faber Gerb & Soffen

20090218687 - Semiconductor chip with passivation layer comprising metal interconnect and contact pads: The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and... Agent: Megica Corporation

20090218685 - Semiconductor module and method of producing the same: A semiconductor module including: a semiconductor chip in which an integrated circuit is formed; an electrode formed on the semiconductor chip and electrically connected to the integrated circuit; an insulating film formed on the semiconductor chip and having an opening positioned corresponding to the electrode; an elastic protrusion disposed on... Agent: Harness, Dickey & Pierce, P.L.C

20090218686 - Semiconductor, semiconductor module, method for manufacturing the semiconductor module, and mobile apparatus: A semiconductor module includes a device mounting board and a semiconductor device mounted on the device mounting board. The device mounting board includes an insulating resin layer, a wiring layer provided on one main surface of the insulating resin layer, and bump electrodes, electrically connected to the wiring layer, which... Agent: Mcdermott Will & Emery LLP

20090218689 - Flip chip semiconductor assembly with variable volume solder bumps: A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column... Agent: Smart & Biggar

20090218688 - Optimized passivation slope for solder connections: A semiconductor structure includes at least one bond pad. An insulator layer is on the surface of the semiconductor chip and on a portion of the bond pad. The polyimide layer comprises a bottom surface contacting and coplanar with the surface of the semiconductor chip, a top surface opposite and... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090218690 - Reduced-stress through-chip feature and method of making the same: A feature is inscribed in a major surface of a microelectronic workpiece having a material property expressed as a reference coefficient value. The feature includes a first material having a first coefficient value for the material property and a second material having a second coefficient value for the material property.... Agent: Slater & Matsil, L.L.P.

20090218692 - Barrier for copper integration in the feol: Copper integration in the FEOL stage is disclosed for a preliminary semiconductor device by forming a recess in a substrate of the device, the recess having a bottom surface and sidewall surfaces, depositing a barrier layer having about a 100% step coverage on the sidewall surfaces and the bottom surface,... Agent: Slater & Matsil LLP

20090218691 - Bilayer metal capping layer for interconnect applications: The invention provides semiconductor interconnect structures that have improved reliability and technology extendibility. In the present invention, a second metallic capping layer is located on a surface of a first metallic cap layer which is, in turn, located on a surface of the conductive feature embedded within a first dielectric... Agent: Scully, Scott, Murphy & Presser, P.C.

20090218693 - Low resistance high reliability contact via and metal line structure for semiconductor device: A semiconductor contact structure includes a copper plug formed within a dual damascene, single damascene or other opening formed in a dielectric material and includes a composite barrier layer between the copper plug and the sidewalls and bottom of the opening. The composite barrier layer preferably includes an ALD TaN... Agent: Duane Morris LLP (tsmc)IPDepartment

20090218694 - Semiconductor device, manufacturing method of semiconductor device, semiconductor manufacturing and inspecting apparatus, and inspecting apparatus: A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a... Agent: Mattingly & Malur, P.C.

20090218695 - Low contact resistance metal contact: A semiconductor structure and methods of making the same. The semiconductor structure includes a substrate having a silicide region disposed above a doped region, and a metal contact extending through the silicide region and being in direct contact with the doped region.... Agent: Greenblum & Bernstein, P.L.C

20090218696 - Semiconductor device including a padding unit: A semiconductor device includes bit lines formed over a substrate and a padding unit formed over the bit lines. The padding unit includes stacked padding layers. A lower padding layer is formed between the bit lines and an upper padding layer. The upper layer as a slit formed therein. The... Agent: Townsend And Townsend And Crew, LLP

20090218697 - Electronic device, method of manufacture of the same, and sputtering target: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090218698 - Wafer-level integrated circuit package with top and bottom side electrical connections: A wafer-level, batch processed, die-sized integrated circuit (IC) package with both top and bottom side electrical connections is disclosed. In one aspect, a number of bonding wires can be attached to bond pads on the top side (active circuit side) of an IC wafer. Trenches can be formed in the... Agent: Fish & Richardson P.C.

20090218699 - Metal interconnects in a dielectric material: A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The exposed portions of the dielectric layer which form the side walls of the trench are removed. A dielectric liner is then... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20090218700 - Three dimensional structure memory: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit... Agent: Michael J. Ure

20090218701 - Inductively coupled integrated circuit with magnetic communication path and methods for use therewith: An integrated circuit includes a first integrated circuit die having a first circuit and a first inductive interface and a second integrated circuit die having a second circuit and a second inductive interface. A substrate is coupled to support the first integrated circuit die and the second integrated circuit die,... Agent: Garlick Harrison & Markison

20090218702 - Methods for bonding and micro-electronic devices produced according to such methods: One inventive aspect is related to a method of bonding two elements and micro-electronic devices produced according to such methods. In one aspect, a micro-electronic device includes a first and a second element, bonded together by a joining structure. The joining structure has a first micropattern portion, a second micropattern... Agent: Knobbe Martens Olson & Bear LLP

20090218703 - Lamination tape for reducing chip warpage and semiconductor device containing such tape: A lamination tape is disclosed which includes a base film with an adhesive layer on one side wherein the coefficient of thermal expansion (CTE) of the adhesive layer is adapted so as to reduce warpage of a semiconductor die when the lamination tape is attached to the passive side of... Agent: Slater & Matsil, L.L.P.