Active solid-state devices (e.g., transistors, solid-state diodes) inventions 08/09

20090212272 - Self-converging bottom electrode ring: A method and memory cell including self-converged bottom electrode ring. The method includes forming a step spacer, a top insulating layer, an intermediate insulating layer, and a bottom insulating layer above a substrate. The method includes forming a step spacer within the top insulating layer and the intermediate insulating layer.... Agent: Law Office Of Ido Tuchman (yor)

20090212273 - Semiconductor devices having resistive memory elements: Provided is a semiconductor device including a resistive memory element. The semiconductor device includes a substrate and the resistive memory element disposed on the substrate. The resistive memory element has resistance states of a plurality of levels according to generation and dissipation of at least one platinum bridge therein.... Agent: Myers Bigel Sibley & Sajovec

20090212274 - Phase change memory random access device using single-element phase change material: A phase change memory cell with a single element phase change thin film layer; and a first electrode and a second electrode coupled to the single element phase change thin film layer. A current flows from the first electrode to the single element phase change thin film layer, and through... Agent: Law Office Of Ido Tuchman (yor)

20090212275 - Nano/micro-sized diode and method of preparing the same: A nano/micro-sized diode and a method of preparing the same, the diode including: a first electrode; a second electrode; and a diode layer that is disposed between the first electrode and the second electrode. The diode layer includes a first layer and a second layer. The first layer is disposed... Agent: Stein Mcewen, LLP

20090212278 - Current-injecting/tunneling light-emitting device and method: An apparatus and method for making it. Some embodiments include a light-emitting device having a light-emitting active region; a tunneling-barrier (TB) structure facing adjacent the active region; a TB grown-epitaxial-metal-mirror (TB-GEMM) structure facing adjacent the TB structure, wherein the TB-GEMM structure includes at least one metal is substantially lattice matched... Agent: Lemaire Patent Law Firm, P.l.l.c.

20090212277 - Group-iii nitride light-emitting device and method for manufacturing group-iii nitride based semiconductor light-emitting device: A group-III nitride light-emitting device is provided. An active layer having a quantum well structure is grown on a basal plane of a gallium nitride based semiconductor region. The quantum well structure is formed in such a way as to have an emission peak wavelength of 410 nm or more.... Agent: Venable LLP

20090212276 - Light-emitting diode device and a fabrication method thereof: The present invention provides a light-emitting diode (LED) device and a fabrication method thereof. The LED device has a double-layered contact layer structure with a surface of one contact layer being patterned to increase ohmic contact area of the double-layered contact layer structure to lower an operation voltage of the... Agent: Birch Stewart Kolasch & Birch

20090212279 - Nanostructure-based electronic device: The nanostructure-based electronic device comprises a solid support, an organic template layer, a nanostructure and electrodes. The organic template layer is on the surface of the solid support, and has a surface comprising a pair of spaced, electrically-charged regions arranged in tandem in an electrically-neutral background. The nanostructure is elongate,... Agent: Agilent Technologies Inc.

20090212281 - Organic semiconductor device, display using same, and imager: An organic semiconductor device in which recombination of holes and electrons and photoelectric conversion in an organic semiconductor layer are efficiently allowed to occur. The device comprises a bipolar organic semiconductor layer where electrons and holes move, a hole giving/receiving electrode which gives/receives holes to/from the organic semiconductor layer, an... Agent: Rabin & Berdo, Pc

20090212280 - Use of a metal complex as an n-dopant for an organic semiconducting matrix material, organic of semiconducting material and electronic component, and also a dopant and ligand and process for producing same: A method of using a metal complex as an n-dopant for doping an organic semiconducting matrix material in order to alter the latter's electrical characteristics is provided. In order to provide n-doped organic semiconductors with matrix materials having a low reduction potential, while achieving high conductivities, the n-dopant is a... Agent: Manu J Tejwani

20090212282 - Bright visible wavelength luminescent nanostructures and methods of making and devices for using the same: Luminescent nanostructures (e.g., nanowires) and devices are provided which are capable of emitting bright visible light. The luminescent nanowires are most preferably in the form of a doped ZnO having a spectrally integrated ratio of visible to UV light of at least about 1000 or greater. The dopant for the... Agent: Nixon & Vanderhye, Pc

20090212283 - Diode and resistive memory device structures: In an electronic device, a diode and a resistive memory device are connected in series. The diode may take a variety of forms, including oxide or silicon layers, and one of the layers of the diode may make up a layer of the resistive memory device which is in series... Agent: Paul J. Winters

20090212284 - Electronic device and manufacturing thereof: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled... Agent: Dicke, Billig & Czaja

20090212285 - Semiconductor device and method of manufacturing thereof: The manufacturing method of a semiconductor device according to the present invention comprises steps of forming a metal film, an insulating film, and an amorphous semiconductor film in sequence over a first substrate; crystallizing the metal film and the amorphous semiconductor film; forming a first semiconductor element by using the... Agent: Eric Robinson

20090212286 - Method for making amorphous polycrystalline silicon thin-film circuits: The invention relates to the fabrication of thin-film transistors made of amorphous silicon and of polycrystalline silicon on one and the same substrate. A polycrystalline silicon island (12) is formed, an insulating layer (14) and a first conducting layer (16) are deposited and these two layers are etched to the... Agent: Lowe Hauptman & Berner, LLP

20090212289 - Thin film transistor and method for fabricating same: A method for forming a thin film transistor on a substrate is disclosed. A gate electrode and a gate insulation layer are disposed on a surface of the substrate. A deposition process is performed by utilizing hydrogen diluted silane to form a silicon-contained thin film on the gate insulation layer... Agent: North America Intellectual Property Corporation

20090212287 - Thin film transistor and method for forming the same: A thin film transistor (TFT) and the method of forming the same is provided. The method of forming the TFT on a surface of a substrate, includes the steps of: forming a gate electrode; deposing a gate dielectric on the gate electrode; forming a nanocrystalline silicon (nc-Si) layer and an... Agent: Altera Law Group, Llc

20090212288 - Thin film transistor, display device including the same, and method of manufacturing the display device: A display device including the thin film transistor, and a method of manufacturing the display device are provided. The thin film transistor comprising a first gate electrode, a second gate electrode formed on the first gate electrode, a first semiconductor formed on the first gate electrode and including a polycrystalline... Agent: Haynes And Boone, LLP Ip Section

20090212290 - Display panel and method for manufacturing the same: A display panel includes; a lower gate line, a lower data line disposed substantially perpendicular to the lower gate line, a thin film transistor (“TFT”) connected to the lower gate line and the lower data line, an insulating layer disposed on the lower gate line, the lower data line, and... Agent: Cantor Colburn, LLP

20090212291 - Transparent thin film transistor and image display unit: An embodiment of the present invention is an transparent thin film transistor which has an substantially transparent substrate, a gate line made of a thin film of a substantially transparent conductive material, a substantially transparent gate insulating film, a substantially transparent semiconductor active layer, a source line made of a... Agent: Squire, Sanders & Dempsey L.l.p.

20090212292 - Layer-selective laser ablation patterning: A method of fabricating an organic electronic device is provided. The organic electronic device has a structure including an upper conductive layer and an underlying layer immediately beneath said upper conducting layer and having at least one solution process able semiconducting layer. The upper conducting layer preferably has a thickness... Agent: Knobbe Martens Olson & Bear LLP

20090212294 - Semiconductor device and manufacturing method thereof: An LDD region 207 provided in an n-channel TFT 302 forming a driving circuit enhances the tolerance for hot carrier injection. LDD regions 217-220 provided in an n-channel TFT (pixel TFT) 304 forming a pixel portion greatly contribute to the decrease in the OFF current value. Here, the LDD region... Agent: Eric Robinson

20090212293 - Semiconductor device and method for fabricating the same: A semiconductor device, comprising a substrate, a semiconductive layer and a gate electrode is provided. The semiconductive layer having a crystallization promoting material is formed over the substrate. The semiconductive layer has a channel region, a first doped region and a second doped region. The first doped region has a... Agent: Rabin & Berdo, Pc

20090212295 - Semiconductor device and method of fabricating the same: A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device includes a substrate, a thin film transistor formed on the substrate and having a semiconductor layer, a gate... Agent: H.c. Park & Associates, Plc

20090212297 - Laminating system: It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it... Agent: Nixon Peabody, LLP

20090212296 - Method for manufacturing display device: A first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, a second conductive film, and a first resist mask are formed; first etching is performed to expose at least a surface of the first conductive film; second etching accompanied by side etching is performed on... Agent: Fish & Richardson P.c.

20090212299 - Display element: A thin film transistor layer including a thin film transistor is formed at a liquid crystal layer side of a color filter layer on an array substrate. Since it becomes possible to form the color filter layer at a position on a relatively flat glass substrate, satisfactory characteristics of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090212300 - Liquid crystal display device and manufacturing method thereof, and electronic device: An objective is simplification of a manufacturing method of a liquid crystal display device or the like. In a manufacturing method of a thin film transistor, a stack in which a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are... Agent: Nixon Peabody, LLP

20090212298 - Thin film transistor substrate having nickel-silicide layer: Disclosed are a thin film transistor substrate of an LCD device and a method of manufacturing the same. The thin film transistor substrate includes a nickel-silicide layer formed on an insulating layer pattern including silicon and a metal layer formed on the nickel-silicide layer. Nickel is coated on the insulating... Agent: F. Chau & Associates, Llc

20090212301 - Double guard ring edge termination for silicon carbide devices and methods of fabricating silicon carbide devices incorporating same: Edge termination structures for semiconductor devices are provided including a plurality of spaced apart concentric floating guard rings in a semiconductor layer that at least partially surround a semiconductor junction. The spaced apart concentric floating guard rings have a highly doped portion and a lightly doped portion. Related methods of... Agent: Myers Bigel Sibley & Sajovec, P.a.

20090212302 - Substrate of liquid crystal device and method for manufacturing the same: A method for manufacturing a substrate of a liquid crystal display device is disclosed. The method includes forming a conductive line structure with low resistance to improve the difficulty of the resistance matching. The method can effectively reduce the resistance of the conductive line of the LCD panel to increase... Agent: Bacon & Thomas, Pllc

20090212304 - Led chip package structure with multifunctional integrated chips and a method for making the same: An LED chip package structure with multifunctional integrated chips includes a substrate unit, a light-emitting unit, a chip unit, and a package colloid unit. The light-emitting unit has a plurality of LED chips electrically arranged on the substrate unit. The chip unit is electrically arranged on the substrate unit, and... Agent: Rosenberg, Klein & Lee

20090212303 - Light-emitting diode matrix and method for producing a light-emitting diode matrix: A light-emitting diode matrix comprises a substrate, first and second electrodes electrically insulated from each other formed in or on the substrate, and a first organic layer on the first electrode and a second organic layer on the second electrode. The first organic layer is separated from the second organic... Agent: Dicke, Billig & Czaja

20090212305 - Semiconductor light emitting device: A semiconductor light emitting device can vary color temperatures of its emission light and have a simple and small configuration. The semiconductor light emitting device can include a substrate, electrode wiring formed on the substrate, a plurality of semiconductor light emitting elements mounted on the electrode wiring, and a wavelength... Agent: Cermak Kenealy Vaidya & Nakajima LLP

20090212306 - Device for an optoelectronic component and module with an optoelectronic component and a device: An apparatus having at least one fixing element is specified, the fixing dement being provided for fixing the apparatus to a housing body of an optoelectronic device and the apparatus being designed as a mount for a separate optical element.... Agent: Fish & Richardson Pc

20090212313 - Led module with application-specific color setting: An LED module with a blue LED chip, over which is arranged a conversion layer, which has a luminous material mixture mixing a further proportion of greater wavelength into the blue light, so that a reddish or greenish or yellowish white light is emitted from the LED module, the emitted... Agent: Marshall, Gerstein & Borun LLP

20090212309 - Light emitting diode package structure and a packaging method thereof: An LED package structure and an LED packaging method are disclosed. The LED package structure includes a substrate, an LED unit and a transparent holding wall. The LED unit is electrically connected and located on the surface of the substrate. The transparent holding wall that corresponds to the LED unit... Agent: Rosenberg, Klein & Lee

20090212307 - Light-emitting diode chip comprising a contact structure: In a luminescence diode chip having a radiation exit area (1) and a contact structure (2, 3, 4) which is arranged on the radiation exit area (1) and comprises a bonding pad (4) and a plurality of contact webs (2, 3) which are provided for current expansion and are electrically... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090212308 - Method for producing an led chip and led chip: A method is disclosed in which a base body is prepared that comprises a layer sequence intended for the LED chip and suitable for emitting electromagnetic radiation. A cap layer is applied to at least one main surface of the base body. A cavity is introduced into the cap layer... Agent: Fish & Richardson Pc

20090212315 - Semiconductor light emitting device and method for manufacturing the same: A semiconductor light emitting device is provided so that an optical axis thereof is properly set parallel with the mounting board when the device is mounted on the mounting board. The semiconductor light emitting device can have a structure in that light can be incident on the light guide plate... Agent: Cermak Kenealy Vaidya & Nakajima LLP

20090212311 - Semiconductor light-emitting device: The invention discloses a semiconductor light-emitting device, which includes a substrate, a first conductive type semiconductor material layer, a second conductive type semiconductor material layer, a light-emitting layer, a first electrode, a second electrode, and a plurality of bump structures. The first conductive type semiconductor material layer is formed on... Agent: Muncy, Geissler, Olds & Lowe, Pllc

20090212312 - Semiconductor light-emitting device: The invention discloses a semiconductor light-emitting device, which includes a substrate, a first conductive type semiconductor material layer, a second conductive type semiconductor material layer, a light-emitting layer, a first electrode, a second electrode, and a plurality of bump structures. The first conductive type semiconductor material layer is formed on... Agent: Muncy, Geissler, Olds & Lowe, Pllc

20090212310 - Soft lithographic molding of surface relief output couplers for organic light emitting diodes: The present invention provides a method and apparatus for surface relief output coupling in organic light emitting diodes is provided. The method includes forming a pattern in a surface of an elastomer (310) and laminating at least a portion of the pattern to a surface of an organic light emitting... Agent: Williams, Morgan & Amerson

20090212314 - Yellow emitting phosphors based on ce3+-doped aluminate and via solid solution for solid-state lighting applications: A Ce3+ based aluminate phosphor or Ce3+ based phosphor in a solid solution can be used for white light generation when combined with a blue or ultraviolet light emitting diode.... Agent: Gates & Cooper LLP Howard Hughes Center

20090212317 - Circuit board for direct flip chip attachment: A packaging method comprises: forming a circuit board by forming a substantially continuous conductive layer on an insulating board and removing selected portions of the continuous conductive layer to define an electrically conductive trace; laser cutting the electrically conductive trace to define sub-traces electrically isolated from each other by a... Agent: Fay Sharpe LLP

20090212318 - Nitride-based semiconductor light-emitting device and manufacturing method thereof: A nitride-based semiconductor light-emitting device and a manufacturing method thereof are provided. The nitride-based light-emitting device includes a first conductivity type nitride-based semiconductor layer, a light-emitting layer and a second conductivity type nitride-based semiconductor layer, that are successively layered above a translucent base. A first conductivity type electrode layer is... Agent: Morrison & Foerster LLP

20090212316 - Surface-mounted optoelectronic semiconductor component and method for the production thereof: A surface-mounted component, comprising an optoelectronic semiconductor chip, a molded body integrally molded onto the semiconductor chip, a mounting area formed at least in places by a surface of the molded body, at least one connection location and side areas of the component which are produced by means of singulation.... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090212319 - Gallium nitride-based compound semiconductor light emitting device: The present light emitting device comprises a substrate and a gallium nitride-based compound semiconductor layer formed on the substrate, wherein a planar shape is a rectangular shape with vertical and longitudinal sides each having a different length, and a side surface of the gallium nitride-based compound semiconductor layer is not... Agent: Sughrue Mion, Pllc

20090212320 - Semiconductor devices and semiconductor apparatuses including the same: Semiconductor devices and semiconductor apparatuses including the same are provided. The semiconductor devices include a body region disposed on a semiconductor substrate, gate patterns disposed on the semiconductor substrate and on opposing sides of the body region, and first and second impurity doped regions disposed on an upper surface of... Agent: Harness, Dickey & Pierce, P.L.C

20090212321 - Trench igbt with trench gates underneath contact areas of protection diodes: A trench PT IGBT (or NPT IGBT) having clamp diodes for ESD protection and prevention of shortage among gate, emitter and collector. The clamp diodes comprise multiple back-to-back Zener Diode composed of doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a... Agent: Bacon & Thomas, Pllc

20090212322 - Vertical semiconductor device: A vertical semiconductor device includes a semiconductor body, and first and second contacts on opposite sides of the semiconductor body. A plurality of regions are formed in the semiconductor body including, in a direction from the first contact to the second contact, a first region of a first conductivity type,... Agent: Maginot, Moor & Beck

20090212323 - Silicon-controlled rectifier (scr) device for high-voltage electrostatic discharge (esd) applications: A silicon-controlled rectifier (SCR) device having a high holding voltage includes a PNP transistor and an NPN transistor, each transistor having both p-type and n-type dopant regions in their respective emitter areas. The device is particularly suited to high voltage applications, as the high holding voltage provides a device which... Agent: Mh2 Technology Law Group, LLP

20090212325 - Hetero field effect transistor and manufacturing method thereof: A hetero field effect transistor includes: a main semiconductor region including a first semiconductor layer and a second semiconductor layer formed thereon to allow a generation of a two-dimensional carrier gas layer of a first conductive type on a heterojunction interface therebetween; a source electrode formed on the main semiconductor... Agent: Wilmerhale/dc

20090212326 - Hetero field effect transistor and manufacturing method thereof: A hetero field effect transistor includes: a first semiconductor layer; a second semiconductor layer formed on the first semiconductor layer to allow a generation of a two dimensional carrier gas layer of a first conductive type on a heterojunction interface between the first semiconductor layer and the second semiconductor layer;... Agent: Wilmerhale/dc

20090212324 - Heterojunction field effect transistor: An aspect of the invention provides a heterojunction field effect transistor that comprises: a base; a first GaN channel layer formed on the base; an AlN electron supply layer formed on the first GaN layer, and a second GaN cap layer formed on the AlN layer.... Agent: Mots Law, Pllc

20090212328 - Semiconductor device and manufacturing method thereof: A semiconductor device is provided. The semiconductor device includes a first gate line, a second gate line, a first contact electrode, first dummy gates, a second gate pad, and a second contact electrode. The first gate line is formed on a semiconductor substrate and the second gate line of a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090212327 - Standard cell libraries and integrated circuit including standard cells: A standard cell library includes a first power rail, a second power rail, a third power rail, a first standard cell, and second standard cells. The first power rail extends in a first direction. The second power rail extends in the first direction, and is spaced apart from the first... Agent: Myers Bigel Sibley & Sajovec

20090212329 - Super hybrid soi cmos devices: The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having... Agent: Scully, Scott, Murphy & Presser, P.c.

20090212330 - Method of fabricating a buried-gate semiconductor device and corresponding integrated circuit: A semiconductor device includes a semiconductive channel region and a gate region. The gate region has at least one buried part extending under the channel region. The buried part of the gate region is formed by forming a cavity under the channel region. That cavity is at least partial filled... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20090212331 - Semiconductor component with schottky zones in a drift zone: A description is given of a semiconductor component comprising a drift zone of a first conduction type and at least one Schottky metal zone arranged in the drift zone, and of a method for producing a semiconductor component.... Agent: Dicke, Billig & Czaja

20090212332 - Field effect transistor with reduced overlap capacitance: In a first structure, a metal gate portion may be laterally recessed from a substantially vertical surface of a gate conductor thereabove. A cavity is formed between the metal gate portion and a gate spacer. In a second structure, a disposable gate portion is removed after laterally recessing a metal... Agent: Scully, Scott, Murphy & Presser, P.c.

20090212333 - Method of manufacturing a buried-gate semiconductor device and corresponding integrated circuit: A semiconductor device includes a semiconductor channel region and a gate region, wherein the gate region includes at least one buried part extending under the channel region. The buried part of the gate region is formed from a cavity under the channel region. The cavity is filled with a first... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20090212334 - Semiconductor device and a method for manufacturing the same: Disclosed are embodiments relating to a semiconductor device and a method of manufacturing a semiconductor device that may prevent an increase of a dielectric effective constant of the IMD. In embodiments, a semiconductor device may include a substrate having a source/drain area, a gate electrode formed on the semiconductor substrate,... Agent: Sherr & Vaughn, Pllc

20090212335 - Complementary metal-oxide-semiconductor (cmos) image sensor and fabricating method thereof: A method of fabricating a complementary metal-oxide-semiconductor (CMOS) image sensor is provided. First, an isolation structure is formed in a substrate with a photo-sensitive region and a transistor device region in the substrate. The transistor device region includes at least a region for forming a transfer transistor. A dielectric layer... Agent: J C Patents, Inc.

20090212336 - Photoelectric conversion apparatus and imaging system using photoelectric conversion apparatus: A photoelectric conversion apparatus includes a photoelectric conversion unit with a semiconductor region of a first conduction type, an amplifying transistor, and a contact. The contact supplies, via a semiconductor region of a second conduction type arranged along a side surface and a bottom surface of an element isolation region,... Agent: Fitzpatrick Cella Harper & Scinto

20090212337 - Semiconductor device and method for manufacturing same: A hard mask material film is formed on a semiconductor substrate and a recess is formed immediately below an opening in an upper surface of the semiconductor substrate. Next, a p-type region is formed immediately below the recess by implanting impurities into an imaging region using the hard mask material... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090212338 - Semiconductor constructions, and methods of forming semiconductor constructions: Some embodiments include methods of forming semiconductor constructions. Oxide is formed over a substrate, and first material is formed over the oxide. Second material is formed over the first material. The second material may be one or both of polycrystalline and amorphous silicon. A third material is formed over the... Agent: Wells St. John P.s.

20090212339 - Flash memory device and method of fabricating the same: The present invention relates to flash memory devices and a method of fabricating the same. In an aspect of the present invention, the flash memory device includes trenches formed in a semiconductor substrate and having a step at their lower portion, a tunnel insulating layer formed in an active region... Agent: Marshall, Gerstein & Borun LLP

20090212340 - Flash memory devices: A gate electrode line which extends in a second direction crossing a first direction on a substrate including an active region which is defined by a device isolation layer and extends in the first direction and a charge trap layer disposed between the active region and the gate electrode line,... Agent: Myers Bigel Sibley & Sajovec

20090212342 - Asymmetric single poly nmos non-volatile memory cell: An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes an NMOS floating gate transistor and an optional select transistor. The floating gate transistor includes an... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way

20090212343 - Non-volatile two-transistor programmable logic cell and array layout: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within... Agent: Lewis And Roca LLP

20090212341 - Semitubular metal-oxide-semiconductor field effect transistor: An epitaxial semiconductor layer or a stack of a silicon germanium alloy layer and an epitaxial strained silicon layer is formed on outer sidewalls of a porous silicon portion on a substrate. The porous silicon portion and any silicon germanium alloy material are removed and a semitubular epitaxial semiconductor structure... Agent: Scully, Scott, Murphy & Presser, P.c.

20090212344 - Flash memory device: Disclosed herein is a flash memory device in which the distribution of threshold voltage is significantly reduced and the durability is improved even though a floating gate has a micro- or nano-size length. It comprises a tunneling insulation film formed on a semiconductor substrate; a multilayer floating gate structure comprising... Agent: Harness, Dickey & Pierce, P.L.C

20090212345 - Semiconductor device and method for manufacturing the same: Disclosed herein are a semiconductor device and a method for manufacturing the same. A method of manufacturing a semiconductor device includes forming a tunnel insulating layer, a first conductive layer, a dielectric layer, a second conductive layer and a gate electrode layer on a semiconductor substrate; patterning the gate electrode... Agent: Marshall, Gerstein & Borun LLP

20090212346 - Semiconductor memory element: A semiconductor memory element includes: a tunnel insulating film formed on a semiconductor substrate; a HfON charge storage film with Bevan clusters formed on the tunnel insulating film; a blocking film formed on the HfON charge storage film; and a gate electrode formed on the blocking film.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20090212351 - Electron blocking layers for electronic devices: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium... Agent: Brinks Hofer Gilson & Lione

20090212348 - Mirror bit memory device applying a gate voltage alternately to gate: A semiconductor device and a method for manufacturing thereof are provided. The semiconductor device includes: an ONO film including a charge storage layer on a semiconductor substrate; a plurality of bit lines each extending inside the semiconductor substrate; a plurality of interspaces each interposed between the adjacent bit lines; a... Agent: Spansion Llc C/o Murabito , Hao & Barnes LLP

20090212353 - Non-volatile memory: A non-volatile memory includes a substrate having two openings, a stacked gate structure disposed on the substrate between the two openings, a liner disposed on a bottom of each of the two openings and parts of a sidewall of each of the two openings, a second conductive layer disposed on... Agent: J C Patents, Inc.

20090212350 - Nonvolatile semiconductor storage device and method of manufacturing the same: A nonvolatile semiconductor storage device has a plurality of memory strings in which a plurality of electrically rewritable memory cells are connected in series. The memory string has a columnar semiconductor layer extending in a direction perpendicular to a substrate; a conductive layer formed so as to sandwich a charge... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20090212349 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a semiconductor substrate, and a nonvolatile memory cell provided on the semiconductor substrate, the nonvolatile memory cell including a tunnel insulating film provided on a surface of the semiconductor substrate, the tunnel insulating film including semiconductor grains, the semiconductor grains included in both end portions of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090212352 - Semiconductor memory device and method for manufacturing the same: A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090212347 - Sonos memory device with optimized shallow trench isolation: Method of manufacturing a non-volatile memory device on a semiconductor substrate in a memory area, said non-volatile memory device comprising a cell stack of a first semiconductor layer, a charge trapping layer and an electrically conductive layer, the charge trapping layer being the intermediate layer between the first semiconductor layer... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090212355 - Metal-oxide-semiconductor transistor device and method for making the same: A metal-oxide-semiconductor transistor device includes a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, an oxide layer formed on the epitaxial layer, a gate structure formed on the oxide layer, and a shallow junction well formed on the two lateral sides of the gate structure including a source... Agent: North America Intellectual Property Corporation

20090212356 - Semiconductor device: A semiconductor device includes: a double-diffused metal oxide semiconductor (DMOS) transistor having a gate electrode and a drain electrode region; and a protection element protecting the gate electrode with respect to overvoltage and coupled to the DMOS transistor on a structure of one semiconductor substrate. The DMOS transistor and the... Agent: Oliff & Berridge, Plc

20090212354 - Trench moseft with trench gates underneath contact areas of esd diode for prevention of gate and source shortate: A trench DMOS transistor having overvoltage protection and prevention for shortage between gate and source when contact trenches are applied includes a substrate of a first conductivity type and a body region of a second conductivity type formed over the substrate. Trench gates extend through the body region and the... Agent: Bayshore Patent Group, Llc

20090212357 - Semiconductor device and method of manufacturing the same: Provided is a semiconductor device. A well region (2) formed on a semiconductor substrate (1) includes a plurality of trench regions (12), and a source electrode (10) is connected to a source region (6) formed on a substrate surface between the trench regions (12). Adjacently to the source region (6),... Agent: Brinks Hofer Gilson & Lione/seiko Instruments Inc.

20090212358 - Semiconductor device and a method of manufacturing the same: A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as... Agent: Stanley P. Fisher Reed Smith LLP

20090212359 - Trenched mosfet with trenched source contact: A trenched MOSFET with trenched source contact, comprising: a semiconductor region, further comprising a silicon substrate, a epitaxial layer corresponding to the drain region of the trenched MOSFET, a base layer corresponding to the body region of the trenched MOSFET, and a source layer corresponding to the source region of... Agent: Bayshore Patent Group, Llc

20090212360 - High-voltage transistor and method for its manufacture: A high-voltage transistor is provided with a well of a first conductivity type, which is arranged in a substrate (10) of a second conductivity type, with a source (14), a drain (12), and a gate electrode (18) above a channel region (KN, KP) formed between the source and the drain,... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090212361 - Semiconductor device and method of manufacturing the same: A LOCOS offset type MOS transistor includes a MOS transistor including: a gate electrode formed on a gate oxide film, the gate oxide film being formed on a surface of a semiconductor substrate of a first conductivity type; a LOCOS oxide film and a first offset diffusion layer of a... Agent: Bruce L. Adams, Esq

20090212366 - Contact scheme for finfet structures with multiple fins: A FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or a local interconnect is provided. In accordance with the present invention, the inventive structure includes a plurality of semiconducting bodies (i.e., FINs) which extend above a surface of a substrate. A common patterned gate stack... Agent: Scully, Scott, Murphy & Presser, P.c.

20090212363 - Method for forming a one-transistor memory cell and related structure: According to one exemplary embodiment, a method for fabricating a one-transistor memory cell includes forming an opening by removing a portion of a gate stack of a silicon-on-insulator (SOI) device, where the SOI device is situated over a buried oxide layer. The method further includes forming a bottom gate of... Agent: Farjami & Farjami LLP

20090212365 - Semiconductor device and method of manufacturing the same: A semiconductor device includes: a monocrystalline substrate; an inter-layer film formed on the monocrystalline substrate; a contact hole penetrating the inter-layer film and partially exposing an upper surface of the monocrystalline substrate; a sidewall formed on an inner surface of the contact hole; a plurality of first monocrystalline layers which... Agent: Young & Thompson

20090212364 - Semiconductor substrates and manufacturing methods of the same: Semiconductor substrates and methods of manufacturing the same are provided. The semiconductor substrates include a substrate region, an insulation region and a floating body region. The insulation region is disposed on the substrate region. The floating body region is separated from the substrate region by the insulation region and is... Agent: Harness, Dickey & Pierce, P.L.C

20090212362 - Soi field effect transistor with a back gate for modulating a floating body: A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of... Agent: Scully, Scott, Murphy & Presser, P.c.

20090212367 - Arrangement of mosfet's for controlling same: An arrangement of a plurality of MOSFET's on a chip that includes a first terminal, a second terminal and a third terminal is provided, the arrangement having at least one first MOSFET used as a first control cell and at least one second MOSFET used as a second control cell,... Agent: Kenyon & Kenyon LLP

20090212369 - Gate effective-workfunction modification for cmos: CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of... Agent: Innovation Interface, Llc

20090212368 - Semiconductor device and method of fabricating the same: A semiconductor device including transistors and strain layers is provided. Each transistor includes a source region and a drain region on a substrate and a gate structure on a channel region between the source region and the drain region. Lengths of the channel regions of these transistors are the same,... Agent: J C Patents, Inc.

20090212370 - Semiconductor device having insulated gate field effect transistors and method of fabricating the same: A semiconductor device has a plurality of insulated gate field effect transistors on a semiconductor substrate. A SAC contact hole is formed between two gates of the insulated gate field effect transistors. A side portion of the SAC contact hole is separated from two gates of the insulated gate field... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20090212373 - Semiconductor device: A semiconductor device facilitates securing a high breakdown voltage and reducing a chip area thereof includes a low-potential gate driver circuit disposed on a semiconductor substrate, a high-breakdown-voltage junction edge-termination structure disposed in a peripheral portion of a high-potential gate driver circuit, disposed on the semiconductor substrate, for separating the... Agent: Rossi, Kimms & Mcdowell LLP.

20090212372 - Semiconductor device and method of fabricating the same: A semiconductor device according to one embodiment includes: a semiconductor substrate comprising an element isolation region; two gate electrodes formed in substantially parallel on the semiconductor substrate via respective gate insulating films; two channel regions each formed in regions of the semiconductor substrate under the two gate electrodes; a source/drain... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090212371 - Semiconductor device fabrication method: According to an aspect of the present invention, there is provided a method for fabricating a semiconductor device, the method including: forming a first region and a second region in a substrate; forming the high-permittivity insulating film on the substrate in the first region and in the second region; forming... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090212374 - Space efficient integratred circuit with passive devices: A multimodal integrated circuit (IC) is provided, comprising, first (74) and second (76) semiconductor (SC) devices, and first (78) and second (80) integrated passive devices (IPDs) coupled, respectively, to the first (74) and second (76) SC devices, wherein the first IPD (78) overlies the second SC device (76) and the... Agent: Ingrassia Fisher & Lorenz, P.c. (fs)

20090212375 - Semiconductor device and method of manufacturing the same: In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a... Agent: Brinks Hofer Gilson & Lione/seiko Instruments Inc.

20090212376 - Semiconductor transistors having high-k gate dielectric layers and metal gate electrodes: A semiconductor structure and a method for forming the same. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate... Agent: Schmeiser, Olsen & Watts

20090212377 - Semiconductor input control device: A force input control device suitable for high-volume applications such as cell phones, portable gaming devices and other handheld electronic devices along with other applications like medical equipment, robotics, security systems and wireless sensor networks is disclosed. The device can be one-axis or two-axis or three-axis sensitive broadening the range... Agent: Fitch Even Tabin & Flannery

20090212378 - Method for producing a micromechanical structural element and semiconductor arrangement: The method serves for producing a micromechanical structure element (13) on or in a crystal substrate (3), wherein the micromechanical structure element (13) is arranged in vibratable fashion in a recess (4) of the crystal substrate (3) and is connected to the crystal substrate (3) by means of a web... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090212380 - Method for manufacturing solid-state imaging device: The method includes the steps of forming a base layer 16 on a semiconductor substrate 11 with a plurality of photodiodes 12 arranged therein, forming a blue filter 17-1, a green filter 17-2 or a red filter 17-3 on the base layer 16 at a position above each of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20090212379 - Semiconductor apparatus, manufacturing method for the semiconductor apparatus, and electronic information device: A semiconductor apparatus according to the present invention includes one or a plurality of pairs of a standard pattern and an offset pattern formed therein with respect to the standard pattern as manufacturing information and other information at an information writing position, which is visible from the outside, of each... Agent: Edwards Angell Palmer & Dodge LLP

20090212381 - Wafer level packages for rear-face illuminated solid state image sensors: A solid state image sensor includes a microelectronic element having a front face and a rear face remote from the front face, the rear face having a recess extending towards the front surface. A plurality of light sensing elements may be disposed adjacent to the front face so as to... Agent: Tessera Lerner David Et Al.

20090212382 - Optical leadless leadframe package: Apparatuses and methods directed to a semiconductor chip package having an optical component are disclosed. Packages include a die having a light sensing region and a stress buffer on a first surface, a first opaque encapsulant having an opening therethrough disposed atop the first surface, and a second transparent or... Agent: Beyer Law Group LLP/ Nsc

20090212383 - Solid-state imaging device, camera module and electronic equipment module: A solid-state imaging device including: a photoelectric conversion element PD formed in a semiconductor substrate 22; a reading-out part which reads out signal charges from the photoelectric conversion element PD formed on one surface side of the semiconductor substrate 22; the other surface of the semiconductor substrate 22 made to... Agent: Sonnenschein Nath & Rosenthal LLP

20090212384 - Method of manufacturing solid-state image pickup element, and solid-state image pickup element: Disclosed herein is a method of manufacturing a solid-state image pickup element, the method including the steps of forming a plurality of photoelectric conversion elements within a semiconductor substrate; forming a wiring layer via an insulating film on a surface of the semiconductor substrate in which surface the plurality of... Agent: Robert J. Depke Lewis T. Steadman

20090212385 - Semiconductor device including vanadium oxide sensor element with restricted current density: In a semiconductor device including a semiconductor substrate and at least one sensor element made of vanadium oxide formed over the semiconductor substrate, the sensor element is designed so that a density of a current flowing through the sensor element is between 0 and 100 μA/μm2.... Agent: Young & Thompson

20090212386 - Mems device and method of making same: A MEMS device includes a P-N device formed on a silicon pin, which is connected to a silicon sub-assembly, and where the P-N device is formed on a silicon substrate that is used to make the silicon pin before it is embedded into a first glass wafer. In one embodiment,... Agent: Honeywell International Inc. Patent Services

20090212388 - High-z structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels: A structure for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target. The structure including a first trench in a semiconductor substrate, the first trench extending from a top surface of the substrate into the substrate a first... Agent: Schmeiser, Olsen & Watts

20090212387 - Manufacturing method for semiconductor device and semiconductor device: A trench is formed on a semiconductor substrate with a first insulation film patterned on the semiconductor substrate as a mask; a second insulation film is embedded in the trench and flattened; an upper portion of the first insulation film is selectively removed, and a part of a side face... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090212389 - Semiconductor device with capacitor and fuse, and method for manufacturing the same: A semiconductor device with a capacitor and a fuse, and a method for manufacturing the same are described. The semiconductor device comprises a semiconductor substrate having a capacitor region and a fuse region defined therein, a insulating layer over the semiconductor substrate, a storage node hole formed in the insulating... Agent: Marshall, Gerstein & Borun LLP

20090212390 - Inductively coupled integrated circuit and methods for use therewith: A circuit includes a first integrated circuit or die having a first circuit and a first inductive interface. A second integrated circuit or die has a second circuit and a second inductive interface. The first inductive interface and the second inductive interface are aligned to magnetically communicate signals between the... Agent: Garlick Harrison & Markison

20090212391 - Micromodules including integrated thin film inductors and methods of making the same: Micromodules and methods of making them are disclosed. An exemplary micromodule includes a substrate having a thin film inductor, and a bumped die mounted on the substrate and over the thin film inductor.... Agent: Townsend And Townsend And Crew, LLP

20090212392 - Capacitor pairs with improved mismatch performance: A semiconductor device includes a first capacitor comprising a plurality of first unit capacitors interconnected to each other, each having a first unit capacitance; and a second capacitor comprising a plurality of second unit capacitors interconnected to each other, each having a second unit capacitance, wherein the first unit capacitors... Agent: Steven H. Slater Slater & Matsil, L.l.p.

20090212393 - Method of manufacturing an electronic device including a pnp bipolar transistor: A method of manufacturing an electronic device including a PNP bipolar transistor comprises forming a collector in a substrate, depositing a base layer and an emitter layer on the substrate, and growing a nitride interface layer on the base layer as a base current modulation means, such that the nitride... Agent: Texas Instruments Incorporated

20090212394 - Bipolar transistor and method of fabricating the same: The invention provides a bipolar transistor with an improved performance because of a reduced collector series resistance and a reduced collector to substrate capacitance. The bipolar transistor includes a protrusion (5) which size may be reduced to a dimension that cannot be achieved with lithographic techniques. The protrusion (5) comprises... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090212395 - Identifying new semiconductor detector materials by d.c. ionization conductivity: Herein is described a method for identifying semiconductor radiation detector materials based on the mobility of internally generated electrons and holes. It was designed for the early stages of exploration, when samples are not available as single crystals, but as crystalline powders. Samples are confined under pressure in an electric... Agent: Lawrence Berkeley National Laboratory

20090212396 - Laser beam machining method and semiconductor chip: In a state where a protective tape 22 is attached to the front face 16a of a multilayer part 16, a substrate 4 is irradiated with laser light L while using its rear face 4b as a laser light entrance surface, so as to form a modified region 7 within... Agent: Drinker Biddle & Reath (dc)

20090212398 - Semiconductor device: A thin-film semiconductor element is formed on a plastic substrate in a semiconductor device. A thermal expansion buffer layer is interposed between the thin-film semiconductor element and the plastic substrate. Although the thin-film semiconductor element is made from a material with a thermal expansion coefficient differing from the thermal expansion... Agent: Rabin & Berdo, Pc

20090212397 - Ultrathin integrated circuit and method of manufacturing an ultrathin integrated circuit: A method of manufacturing an ultra thin integrated circuit comprises providing a substrate having a front side, a back side, and an edge extending from the front side to the back side; creating a defect layer in the substrate; forming semiconductor devices proximate the front side after creating the defect... Agent: Mark Tuttle

20090212399 - Electronic component and method of manufacturing the same: An electronic component includes a substrate, a functional element formed on the substrate, a plurality of terminals including a first terminal electrode connected to the functional element and a second terminal electrode layered on the first terminal electrode, and a feed line, one end of which is electrically connected to... Agent: Arent Fox LLP

20090212400 - Semiconductor device and manufacturing method and mounting method thereof: A semiconductor device includes: a semiconductor substrate having an active region on a surface thereof; at least one electrode pad provided in a peripheral portion of the surface of the semiconductor substrate; and a through electrode extending through the semiconductor substrate and connected to the electrode pad. A taper is... Agent: Mcdermott Will & Emery LLP

20090212401 - Package system for shielding semiconductor dies from electromagnetic interference: The present invention provides a package system including: providing a semiconductor die with a contact pad and a ground pad, mounting the semiconductor die on a package substrate using and adhesive layer, forming a vertical conductive structure on top of the ground pad in the semiconductor die, encapsulating at least... Agent: Law Offices Of Mikio Ishimaru

20090212402 - Semiconductor device: Disclosed is a semiconductor device which includes a semiconductor chip and a base substrate. The semiconductor chip includes a semiconductor substrate, an interconnect layer and a high-frequency interconnect. The interconnect layer is provided on the substrate. The high-frequency interconnect is formed within the interconnect layer. The semiconductor chip is mounted... Agent: Young & Thompson

20090212403 - Thermally enhanced molded leadless package: A molded leadless package (MLP) semiconductor device includes a heat spreader with a single connecting projection extending from an edge of a cap of the heat spreader to a leadframe. The heat spreader can include additional projections on its edges that act as heat collectors and help to secure the... Agent: Hiscock & Barclay, LLP

20090212404 - Leadframe having mold lock vent: A leadframe for supporting a semiconductor chip, the leadframe including a die pad having a first major surface and an opposing second major surface defining a thickness and having at least one perimeter edge, and an opening spaced from the at least one perimeter edge and extending through the thickness... Agent: Dicke, Billig & Czaja

20090212405 - Stacked die molded leadless package: A stacked die molded leadless package (MLP) stacks two dice and uses leads formed integrally with top and central clips and a leadframe to avoid wire bonding. The central clip leads are source and gate leads leading to source and gate portions of the central clip common to source and... Agent: Hiscock & Barclay, LLP

20090212406 - Semiconductor device and method of manufacturing the same: When manufacturing a semiconductor device by mounting a semiconductor chip 2 on a substrate 1 with a flip-chip method, projections 9 are formed between pads 4 arranged in multiple annular concentric layers on the semiconductor chip 2 other than pads 4 arranged along the innermost periphery thereof. On the substrate... Agent: Steptoe & Johnson LLP

20090212407 - Infinitely stackable interconnect device and method: An infinitely stackable interconnect device and method having the capability for electrical, thermal, optical, and fluidic interconnections to various layers. Through-substrate vias in the interconnect device are filled to enable electrical and thermal connection or optionally hermetically sealed relative to other surfaces to enable fluidic or optical connection. Optionally, optical... Agent: J. Charles Dougherty

20090212408 - Integrated circuit package system for stackable devices: An integrated circuit package system comprising: providing a package die; and connecting a connector lead having a first connector end with a protruded connection surface and a lowered structure over the package die.... Agent: Law Offices Of Mikio Ishimaru

20090212410 - Stack die packages: An integrated circuit package includes a substrate comprising a first contact. A first integrated circuit mechanically attached to the substrate. The first integrated circuit comprising a second contact. A first redistribution layer arranged on the first integrated circuit. The first redistribution layer includes a trace coupled to the second contact.... Agent: Harness, Dickey & Pierce P.L.C

20090212409 - Stackable semiconductor package and stack method thereof: A stackable semiconductor package is disclosed. In the stackable semiconductor package, land grid array (LGA) or ball grid array (BGA) semiconductor packages are stacked in the vertical direction. The stackable semiconductor package comprises: a first semiconductor package including a first substrate, at least one first semiconductor die mounted on the... Agent: Hyun Jong Park Tuchman & Park Llc

20090212411 - Semiconductor device and manufacturing method therefor: A semiconductor device includes a thermoplastic resin case, a semiconductor chip mounted within the thermoplastic resin case, a metal terminal having a wire bonding surface and an opposing contact surface, and a wire connected between the wire bonding surface and the semiconductor chip. The contact surface of the metal terminal... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20090212412 - Semiconductor package accomplishing fan-out structure through wire bonding: Provided is a semiconductor package accomplishing a fan-out structure through wire bonding in which a pad of a semiconductor chip is connected to a printed circuit board through wire bonding. A semiconductor package can be produced without a molding process and can be easily stacked on another semiconductor package while... Agent: Marger Johnson & Mccollom, P.c.

20090212413 - Ball grid array package layout supporting many voltage splits and flexible split locations: A die package generally including (A) ground paths routing a power ground from a ground power set of contact pads in a first conductive layer to a ground ring in a second conductive layer, (B) core paths routing a core voltage from a core power set of contact pads in... Agent: Christopher P Maiorana, Pc Lsi Corporation

20090212414 - Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same: Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically... Agent: Marger Johnson & Mccollom, P.c.

20090212415 - Integrated circuit package system with external interconnects within a die platform: The present invention provides an integrated circuit package system comprising: attaching a die platform to an integrated circuit die; mounting the integrated circuit die over an external interconnect with a bottom side of the external interconnect partially within the die platform; connecting the integrated circuit die and the external interconnect;... Agent: Law Offices Of Mikio Ishimaru

20090212416 - Integrated circuit package and method of manufacturing same: An integrated circuit package includes a substrate (110, 210) having a first surface (111, 211) and an opposing second surface (112, 212), and a die platform (130, 230) adjacent to the first surface of the substrate. The substrate has a recess (120, 220) therein. The integrated circuit package further includes... Agent: Intel Corporation C/o Cpa Global

20090212417 - Semiconductor device: A semiconductor device including: a heat sink, a die on the heat sink, resin encapsulating the die, and a mounting aperture in the resin having at least a segment between the heat sink and a first end of the resin, wherein the thickness of the heat sink is no greater... Agent: Slater & Matsil LLP

20090212418 - Thermal interface material design for enhanced thermal performance and improved package structural integrity: An electronic package comprising a semiconductor device, a heat spreader layer, and a thermal interface material layer located between the semiconductor device and the heat spreader layer. The thermal interface material layer includes a resin layer having heat conductive particles suspended therein. A portion of the particles are exposed on... Agent: Texas Instruments Incorporated

20090212419 - Integrated circuit package system with overhang film: An integrated circuit package system includes: connecting a first interconnect between a carrier and a bottom integrated circuit thereover; forming a film, having an overhang portion, over the bottom integrated circuit with the overhang portion over the first interconnect; mounting a top integrated circuit over the film; connecting a second... Agent: Law Offices Of Mikio Ishimaru

20090212420 - integrated circuit device and method for fabricating same: Fabricating an integrated circuit device includes providing a semiconductor substrate comprising a first surface and a sec-ond surface, forming a wiring layer on the first surface of the semiconductor substrate, providing a circuit chip, and arranging the circuit chip on the wiring layer of the semi-conductor substrate. The fabricating further... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090212422 - Joint reliability of solder joint between sn-yag solder and ni-p under bump metallic layer by cobalt addition: An improvement of joint reliability between Sn-yAg (0≦y≦4.0) solder and Ni—P under-bump metallic layers is achieved by cobalt (Co) addition. A solder joint with improved joint reliability is formed between a solder part of an electronic packaging and an under-bump metallic (UBM) layer, which has a specific structure comprising Sn-yAg-xCo... Agent: Bardmesser Law Group, P.c.

20090212421 - Polymer interlayer dielectric and passivation materials for a microelectronic device: Polymer interlayer dielectric and passivation materials for a microelectronic device are generally described. In one example, an apparatus includes one or more interconnect structures of a microelectronic device and one or more polymeric dielectric layers coupled with the one or more interconnect structures, the polymeric dielectric layers including copolymer backbones... Agent: Cool Patent, P.c. C/o Cpa Global

20090212424 - Routing structure of re-distribution layer and method for re-distributing routing structure in integrated circuit: A routing structure of an RDL of a chip is provided. The routing structure comprises a power route, a plurality of first stripes, a ground route, and a plurality of second stripes. The power route is arranged in a first direction and comprises a plurality of first bumps and a... Agent: J C Patents, Inc.

20090212425 - Semiconductor device and a method of manufacturing the same: A technique is provided which allows a chip mounted by wire bonding and a chip mounted by bump electrodes to share a manufacturing process. Both in a case where a chip is electrically coupled to an external circuit by bump electrodes and a case where the chip is electrically coupled... Agent: Miles & Stockbridge Pc

20090212426 - Semiconductor device and manufacturing method thereof: In a semiconductor device, a region under a pad electrode with a bump can be utilized efficiently and a large amount of force is prevented from applying locally to a semiconductor substrate under the bump when the semiconductor device is mounted. A first layer metal wiring is formed on the... Agent: Morrison & Foerster LLP

20090212427 - Solder structures including barrier layers with nickel and/or copper: An electronic device may include an electronic substrate, and an under bump seed metallurgy layer on the electronic substrate. A barrier layer may be provided on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the barrier layer and the electronic substrate, and... Agent: Myers Bigel Sibley & Sajovec

20090212423 - Stacked solder balls for integrated circuit device packaging and assembly: A semiconductor device is provided that includes a semiconductor chip, a plurality of solder bumps that electrically couple the semiconductor chip to the outside, and a metal bump being provided on the surface of each first solder bump which is at least a part of the plurality of solder bumps... Agent: Spansion Llc C/o Murabito , Hao & Barnes LLP

20090212428 - Re-distribution conductive line structure and the method of forming the same: A conductive line structure of a semiconductor device, the structure comprising a substrate having bonding pad; a first dielectric layer formed over the substrate; a solder pad formed over the first dielectric layer; a buffer scheme formed over the first dielectric layer and between the bonding pad and the solder... Agent: Kusner & Jaffe Highland Place Suite 310

20090212429 - Semiconductor device and method of supporting a wafer during backgrinding and reflow of solder bumps: A semiconductor device is made by providing a semiconductor wafer having an active surface, forming an under bump metallization layer on the active surface of the semiconductor wafer, forming a first photosensitive layer on the active surface of the semiconductor wafer, exposing a selected portion of the first photosensitive layer... Agent: Robert D. Atkins

20090212430 - Carbon nanotube-based conductive connections for integrated circuit devices: Electrical connection in an integrated circuit arrangement is facilitated with carbon nanotubes. According to various example embodiments, a carbon nanotube material (120, 135) is associated with another material (130, 125) such as a metal. The carbon nanotube material facilitates the electrical connection between different circuit components.... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090212431 - Thermally programmable anti-reverse engineering interconnects and methods of fabricating same: An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by... Agent: Schmeiser, Olsen & Watts

20090212434 - Methods of manufacturing semiconductor devices and a semiconductor structure: Processes for improving adhesion of films to semiconductor wafers and a semiconductor structure are provided. By implementing the processes of the invention, it is possible to significantly suppress defect creation, e.g., decrease particle generation, during wafer fabrication processes. More specifically, the processes described significantly reduce flaking of a TaN film... Agent: Greenblum & Bernstein, P.L.C

20090212432 - Semiconductor device, its manufacturing method, and sputtering target material for use in the method: A semiconductor device enables a barrier layer to fully acquire a barriering property against the diffusion of Cu from a wiring main body and the diffusion of Si from an insulating film, enhances the adhesiveness of the barrier layer and the insulating film and excels in reliability of operation over... Agent: Masuvalley & Partners

20090212433 - Structure and process for metallization in high aspect ratio features: A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material and is in direct contact with a metal semiconductor alloy located on an upper surface of a material stack... Agent: Scully, Scott, Murphy & Presser, P.c.

20090212435 - Power semiconductor device including a double metal contact: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.... Agent: Farjami & Farjami LLP

20090212437 - Semiconductor device: In a semiconductor device having a Low-k film as an interlayer insulator, peeling of the interlayer insulator in a thermal cycle test is prevented, thereby providing a highly reliable semiconductor device. In a semiconductor device having a structure in which interlayer insulators in which buried wires each having a main... Agent: Mattingly & Malur, P.c.

20090212436 - Semiconductor structure and method for forming the same: A semiconductor structure and method for forming the same are provided. The semiconductor structure comprises a semiconductor substrate, a plurality of top metallizations on the semiconductor substrate, a high density plasma layer filling gaps between the top metallizations and having a substantially planar upper surface overlying the top metallizations, and... Agent: Quintero Law Office, Pc

20090212439 - Fluorine depleted adhesion layer for metal interconnect structure: A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or... Agent: Scully, Scott, Murphy & Presser, P.c.

20090212438 - Integrated circuit device comprising conductive vias and method of making the same: A semiconductor substrate for an integrated circuit device comprises at least one insulating substrate region being formed of a cohesive insulating material. The insulating substrate region includes at least two conductive vias extending at least between a first surface and a second surface of the insulating substrate region.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090212440 - Semiconductor device: An object of the present invention is to solve the problem that the number of pads increases due to high packaging density and the size of semiconductor devices increases due to increase of the pad density. A semiconductor device according to the present invention uses a conductor trace on an... Agent: Mcginn Intellectual Property Law Group, Pllc

20090212441 - Semiconductor interconnect structure with stacked vias separated by signal line and method therefor: A semiconductor device is made by forming a first conductive layer over a substrate, forming a first passivation layer over the first conductive layer, forming a first via in the first passivation layer to expose the first conductive layer, forming a second conductive layer over the first passivation layer and... Agent: Robert D. Atkins

20090212442 - Integrated circuit package system with penetrable film adhesive: An integrated circuit package system including: providing a wire bonded die with an active side and a bond wire connected thereto; forming a penetrable film adhesive on the active side and partially encapsulating the bond wire; mounting an interposer, having a first functional side facing up away from the wire... Agent: Law Offices Of Mikio Ishimaru

20090212443 - Integrated circuit package substrate having configurable bond pads: Methods, systems, and apparatuses for integrated circuit package substrates, integrated circuit packages, and processes for assembling the same, are provided. A substrate for a flip chip integrated circuit package includes a substrate body having opposing first and second surfaces. A solder mask layer covers at least a portion of the... Agent: Fiala & Weaver, P.l.l.c. C/o Cpa Global

20090212444 - Semiconductor package and method of manufacturing the same: A semiconductor package including a substrate, a circuit pattern, a chip, at least one conductive material and an adhesive is provided. The substrate has a first surface, a second surface opposite thereto, and at least one through hole which penetrates the first surface and the second surface. The circuit pattern... Agent: Jianq Chyun Intellectual Property Office

20090212445 - Semiconductor integrated circuit: In a semiconductor integrated circuit, a second wiring layer includes a ground conductor having at least one opening formed therein. At least one opening is overlapped by at least one patch conductor included in a third wiring layer. At least one patch conductor and the ground conductor are electrically connected... Agent: Cantor Colburn, LLP

20090212446 - Semiconductor device: A semiconductor device including: a die pad, a die on the die pad, and resin encapsulating the die and forming an isolation thickness over the die pad, the resin including a mounting aperture and a major surface configured for mounting to an external device, the major surface having a non... Agent: Slater & Matsil LLP

20090212447 - Mark structure for coarse wafer alignment and method for manufacturing such a mark structure: A mark structure includes on a substrate, at least four lines. The lines extend parallel to each other in a first direction and are arranged with a pitch between each pair of lines that is directed in a second direction perpendicular to the first direction. The pitch between each pair... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090206315 - Integrated circuit including u-shaped access device: An integrated circuit includes a first contact, a second contact, and a U-shaped access device coupled to the first contact and the second contact. The integrated circuit includes self-aligned dielectric material isolating the first contact from the second contact.... Agent: Dicke, Billig & Czaja

20090206316 - Integrated circuit including u-shaped access device: An integrated circuit includes a U-shaped access device and a first line coupled to a first side of the access device. The integrated circuit includes a contact coupled to a second side of the access device and self-aligned dielectric material isolating the first line from the contact.... Agent: Dicke, Billig & Czaja

20090206318 - Nonvolatile memory device and method of manufacturing the same: A nonvolatile memory device, including a lower electrode on a semiconductor substrate, a phase change material pattern on the lower electrode, an adhesion pattern on the phase change material pattern and an upper electrode on the adhesion pattern, wherein the adhesion pattern includes a conductor including nitrogen.... Agent: Lee & Morse, P.C.

20090206317 - Phase change memory device and method for manufacturing the same: A method for manufacturing a phase change memory device includes steps of forming a first encapsulation layer on a semiconductor substrate having a bottom electrode contact and a phase change material layer stack structure contacting the bottom electrode contact, and forming a plurality of encapsulation spacers on sidewalls of the... Agent: Baker & Mckenzie LLP Patent Department

20090206319 - Semiconductor device for generating an oscillating voltage: A semiconductor device which displays an oscillating voltage due to the creation of charge domains which includes a plurality of semiconductor layers and at least two electrodes spaced from one another in the direction of the layers, an upper of which has a composition and/or dimensions predetermined so that a... Agent: Studebaker & Brackett PC

20090206322 - Broadband light emitting device lamps for providing white light output: A multi-chip light emitting device (LED) lamp for providing white light includes first and second broadband LED chips. The first LED chip includes a multi-quantum well active region having a first plurality of alternating active and barrier layers. The first plurality of active layers respectively include different relative concentrations of... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090206320 - Group iii nitride white light emitting diode: A white light-emitting diode is fabricated by metal organic chemical vapor deposition (MOCVD), which can produce a broad band emission covering all the visible range in the spectrum by capping the Indium nitride (InN) and Indium-rich Indium Gallium Nitride (InGaN) quantum dots (QDs) in single or multiple InxGa1-xN/InyGa1-yN quantum wells... Agent: Fulwider Patton LLP

20090206323 - Light-emitting element and method for manufacturing the same: A light-emitting element includes a n-type silicon oxide film and a p-type silicon nitride film. The n-type silicon oxide film and the p-type silicon nitride film formed on the n-type silicon oxide film form a p-n junction. The n-type silicon oxide film includes a plurality of quantum dots composed of... Agent: Foley & Lardner LLP

20090206321 - Thin film transistor comprising nanowires and fabrication method thereof: A thin film transistor includes nanowires. More specifically, the thin film transistor includes nanowires aligned between and extending to opposite facing lateral surfaces of source/drain electrodes on a substrate. The nanowires extend in a direction parallel to a major surface defining the substrate to form a semiconductor channel layer. Also... Agent: Cantor Colburn, LLP

20090206324 - Dislocation removal from a group iii-v film grown on a semiconductor substrate: Dislocation removal from a group III-V film grown on a semiconductor substrate is generally described. In one example, an apparatus includes a semiconductor substrate, a buffer film including a group III-V semiconductor material epitaxially coupled to the semiconductor substrate wherein the buffer film includes material melted by laser pulse irradiation... Agent: Cool Patent, P.C. C/o Cpa Global

20090206325 - Gan based semiconductor light-emitting device and method for producing same: A GaN based semiconductor light-emitting device is provided. The light-emitting device includes a first GaN based compound semiconductor layer of an n-conductivity type; an active layer; a second GaN based compound semiconductor layer; an underlying layer composed of a GaN based compound semiconductor, the underlying layer being disposed between the... Agent: K&l Gates LLP

20090206326 - Electroluminescent iridium compounds with fluorinated phenylpryidines, phenylpyrimidines, and phenylquinolines and devices made with such compounds: The present invention is generally directed to electroluminescent Ir(III) compounds, the substituted 2-phenylpyridines, phenylpyrimidines, and phenylquinolines that are used to make the Ir(III) compounds, and devices that are made with the Ir(III) compounds.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20090206331 - Light emitting device: A light emitting device and electronic equipment having a long life at a low electric power consumption are provided. A hole transporting region composed of a hole transporting material, an electron transporting region composed of an electron transporting material, and a mixture region in which both the hole transporting material... Agent: Fish & Richardson P.C.

20090206330 - Organic insulator composition, organic insulating layer including the composition, and organic thin film transistor including the same: An organic insulator composition according to example embodiments may include an organic insulating polymer and an epoxy-based crosslinking agent. The epoxy-based crosslinking agent may have an alkyl group or a fluorine-based side chain. The organic insulator composition may be used to form an organic insulating layer having increased chemical resistance.... Agent: Harness, Dickey & Pierce, P.L.C

20090206329 - Organic thin film transistor: To provide an organic thin film transistor including a pair of electrodes for allowing a current to flow through an organic semiconductor layer made of an organic semiconductor material, and a third electrode, wherein the organic semiconductor material is composed mainly of an arylamine polymer having a weight-average molecular weight... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090206327 - Organometallic complexes: Organometallic complexes are provided having at least one charge transporting ligand, and methods for making the same, as well as devices and sub-assemblies including the same.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20090206328 - Silicon-containing photosensitive composition, method for forming thin film pattern using same, protective film for electronic device, gate insulating film and thin film transistor: g

20090206332 - Oxide semiconductor transistor and method of manufacturing the same: An oxide semiconductor thin film transistor (TFT) and a method of manufacturing the oxide semiconductor TFT. The oxide semiconductor TFT includes a first gate insulating layer arranged between an oxide semiconductor channel layer and a first gate and a second gate insulating layer arranged between the channel layer and a... Agent: Robert E. Bushnell & Law Firm

20090206333 - Zno based semiconductor device and its manufacture method: A ZnO based semiconductor device includes: a lamination structure including a first semiconductor layer containing ZnO based semiconductor of a first conductivity type and a second semiconductor layer containing ZnO based semiconductor of a second conductivity type opposite to the first conductivity type, formed above the first semiconductor layer and... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090206334 - Display substrate, display panel having the same, and method of testing a display substrate: A display substrate includes a gate wire, a data wire which crosses the gate wire, a display part, a dummy pixel part and a test part. The display part includes a pixel element electrically connected to the gate wire and the data wire, and the pixel element includes a display... Agent: Cantor Colburn, LLP

20090206335 - Bipolar complementary semiconductor device: The invention relates to a BiCMOS device comprising a substrate having a first type of conductivity and a number of active regions that are provided therein and are delimited in a lateral direction by flat field-insulating regions. Vertical npn bipolar epitaxial base transistors are disposed in a first partial number... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20090206336 - Method to fabricate gate electrodes: A method for fabricating a semiconductor device comprises depositing a first layer of oxide on at least a portion of a channel of a transistor. The method further comprises depositing a layer of nitride on the first layer of oxide and etching at least a portion of the layer of... Agent: Baker Botts L.L.P.

20090206337 - Image sensor and method for manufacturing the same: An image sensor includes a lower metal interconnection, an interlayer dielectric, a first substrate, a photodiode, an upper electrode and an amorphous silicon layer. The lower metal interconnection and the interlayer dielectric are formed over the first substrate including a pixel region and a peripheral region. The photodiode is formed... Agent: Sherr & Vaughn, PLLC

20090206338 - Array substrate, liquid crystal display module including the array substrate and method of fabricating the array substrate: An array substrate for a liquid crystal display device includes a gate line and a gate electrode on a substrate, the gate electrode connected to the gate line; a gate insulating layer on the gate line and the gate electrode; an active layer of intrinsic amorphous silicon on the gate... Agent: Birch Stewart Kolasch & Birch

20090206339 - Flat display device and method for manufacturing the same: A flat display device is provided. The flat display device a substrate divided into an active region for displaying an image and a peripheral region that does not display the image, and includes: a gate line that crosses a data line to define a pixel region in the active region;... Agent: Mckenna Long & Aldridge LLP

20090206340 - Thin film transistor array panel: A thin film transistor array panel is provided according to one or more embodiments. In an embodiment, the thin film transistor array panel includes: a base substrate that has a display area and a peripheral area; a plurality of thin film transistors that are formed in the display area; a... Agent: Haynes And Boone, LLPIPSection

20090206341 - Solution-processed high mobility inorganic thin-film transistors: Fluid media comprising inorganic semiconductor components for fabrication of thin film transistor devices.... Agent: Reinhart Boerner Van Deuren S.c. Attn: Linda Kasulke, Docket Coordinator

20090206343 - Display apparatus and method of manufacturing the same: In a display apparatus and a method of manufacturing the display apparatus, a first insulating layer having a trench and a second insulating layer having a via hole corresponding to the trench are formed on an array substrate. After forming a seed layer in the trench, a conductive layer is... Agent: Cantor Colburn, LLP

20090206342 - Display device: An object is to reduce an occupied area of a protection circuit. Another object is to increase the reliability of a display device including the protection circuit. The protection circuit includes a first wiring over a substrate, an insulating film over the first wiring, and a second wiring over the... Agent: Eric Robinson

20090206345 - Semiconductor device: A semiconductor device having a display unit, which is small in size, suppresses the defect caused by the mounting of IC chips and the like on the substrate, and operates at a high speed. A semiconductor display unit and other circuit blocks are integrally formed on the substrate having an... Agent: Eric Robinson

20090206344 - System for displaying images: A system for displaying images is disclosed. The system includes a self-emitting display device including an array substrate having a pixel region. A light-emitting diode is disposed on the array substrate of the pixel region. First and second driving thin film transistors are electrically connected to a light-emitting diode. The... Agent: Liu & Liu

20090206346 - Tft lcd array substrate and manufacturing method thereof: The present invention discloses a method for manufacturing a TFT LCD array substrate by utilizing the gray tone mask technology and the photoresist lifting-off technology with only two masks in two photolithography processes, and to a TFT LCD array substrate manufactured by the same. In the resultant array substrate, the... Agent: Hasse & Nesbitt LLC

20090206347 - Semiconductor device: A unipolar semiconductor device having a drift layer (3) doped according to a first conductivity type forming a conducting path and regions (7, 8) doped according to a second conductivity type and arranged next to the drift layer, has the drift layer and the regions of a semiconductor material having... Agent: Dilworth & Barrese, LLP

20090206348 - Composite substrate, and method for the production of a composite substrate: A composite substrate (1) comprising a substrate body (2) and a utility layer (31) fixed on the substrate body (2). A planarization layer (4) is arranged between the utility layer (31) and the substrate body (2). A method for producing a composite substrate (1) applies a planarization layer (4) on... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090206349 - Semiconductor device and method of manufacturing the same: An object of the invention is to provide a smaller semiconductor device of which the manufacturing process is simplified and the manufacturing cost is reduced and a method of manufacturing the same. Furthermore, an object of the invention is to provide a semiconductor device having a cavity. A first supporting... Agent: Morrison & Foerster LLP

20090206350 - Led chip package structure with different led spacings and a method for making the same: An LED chip package structure with different LED spacing includes a substrate unit, a light-emitting unit, and a package colloid unit. The light-emitting unit has a plurality of LED chips electrically arranged on the substrate unit, and the LEDs are separated from each other by totally different spacing or partially... Agent: Rosenberg, Klein & Lee

20090206351 - Semiconductor light emitting device: Embodiments provide a semiconductor light emitting device which comprises a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, and a plurality of third semiconductor structures spaced apart on the second conductive semiconductor layer.... Agent: Birch Stewart Kolasch & Birch

20090206355 - Light emitting devices: Light-emitting devices, and related components, systems and methods are disclosed.... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.C.

20090206356 - Light-emitting diode: A through-hole extending from an element-mounting surface to a back surface of a substrate is formed along an edge area of a bottom surface of the substrate. This through-hole is filled with a conductive resin paste directly into a quarter through-hole made in the substrate. This makes the conductive resin... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20090206352 - Luminescence conversion led: A luminescence conversion LED having a radiation emitting chip that is connected to electrical connections and is surrounded by a housing that comprises at least a basic body and a cap, the chip being seated on the basic body, in particular in a cutout of the basic body, and the... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090206354 - Semiconductor light-emitting device: A semiconductor light-emitting device includes a support structure, and a light-emitting structure. The support structure includes a support substrate, and a support substrate side bonding layer disposed on one surface of the support substrate. The light-emitting structure includes a light-emitting structure side bonding layer bonded to the support substrate side... Agent: Mcginn Intellectual Property Law Group, PLLC

20090206353 - Thin-light emitting diode lamp, and method of manufacturing the same: A thin-type light emitting diode lamp includes a blue light emitting diode chip (6) disposed at a substantial center of an inner bottom surface of a groove-shaped recess (3) formed at an end surface and having a thin elongated rectangular opening, a red light conversion layer (7) covering the blue... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20090206358 - Package structure of compound semiconductor device and fabricating method thereof: A package structure of a compound semiconductor device comprises a thin film substrate, a die, at least one metal wire and a transparent encapsulation material. The thin film substrate comprises a first conductive film, a second conductive film, and an insulating dielectric material. The die is mounted on the surface... Agent: Wpat, PC Intellectual Property Attorneys

20090206357 - Semiconductor light emitting device: There is provided a nitride semiconductor light emitting device in which a semiconductor layer is not broken easily even when a reverse voltage is applied or even in long time operation, and excellent reliability is obtained, by preventing semiconductor layers from deterioration when manufacturing a device. On a surface of... Agent: Rabin & Berdo, PC

20090206361 - Group iii nitride semiconductor light emitting device, method for producing the same, and lamp thereof: A group III nitride semiconductor light emitting device with a double sided electrode structure which has a low driving voltage as well as excellent light emission efficiency is provided, and the group III nitride semiconductor light emitting device includes at least an impurity layer 30 composed of a high concentration... Agent: Sughrue Mion, PLLC

20090206362 - Light emitting diode by use of metal diffusion bonding technology and method of producing such light emitting diode: The main objective of present invention is to provide a manufacturing method of light emitting diode that utilizes metal diffusion bonding technology. AlInGaP light emitting diode epitaxial structure on a temporary substrate is bonded to a permanent substrate having a thermal expansion coefficient similar to that of the epitaxial structure,... Agent: Rosenberg, Klein & Lee

20090206359 - Light-emitting diode and method for fabrication thereof: A light-emitting diode (10) includes a transparent substrate and a compound semiconductor layer that contains a light-emitting part (12) containing a light-emitting layer (133) formed of (AlXGa1−X)YIn1−YP; in which 0≦X≦1 and 0<Y≦1), and that is joined to the transparent substrate (14). wherein the light-emitting diode (10) has on a main... Agent: Sughrue Mion, PLLC

20090206360 - Nitride semiconductor light emitting device and method of manufacturing the same: The present invention provides a nitride semiconductor light emitting device having an n-electrode that has an Au face excellent in ohmic contacts to an n-type nitride semiconductor and excellent in mounting properties, and a method of manufacturing the same. The nitride semiconductor light emitting device uses an n-electrode having a... Agent: Miles & Stockbridge PC

20090206363 - Solid-state switch capable of bidirectional operation: A monolithic switching device including a main semiconductor region configured to provide a current-carrying channel as in the form of two-dimensional electron gas. Disposed symmetrically on a surface of the main semiconductor region are two main electrodes to be coupled to an electric circuit for switching control, two gate electrodes... Agent: Woodcock Washburn LLP

20090206364 - Insulated gate bipolar transistor and method of fabricating the same: According to embodiments, an insulated gate bipolar transistor (IGBT) may include a first conductive type collector ion implantation area, formed within a substrate, second conductive type first buffer layers, formed over the collector ion implantation area and each including a first segment buffer layer and a second segment buffer layer,... Agent: Sherr & Vaughn, PLLC

20090206365 - Semiconductor device: A semiconductor device includes a semiconductor substrate; a first base region of a first conductivity type provided in the semiconductor substrate; a buffer region of the first conductivity type provided on a lower surface of the first base region and having an impurity concentration higher than an impurity concentration of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090206366 - Semiconductor device and method for fabricating the same: Disclosed is a semiconductor device including: an N-type RESURF region formed in a P-type semiconductor substrate; a P-type base region formed in an upper portion of the semiconductor substrate so as to be adjacent to the RESURF region; an N-type emitter/source region formed in the base region so as to... Agent: Mcdermott Will & Emery LLP

20090206367 - Design structure and method for a silicon controlled rectifier (scr) structure for soi technology: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.... Agent: Greenblum & Bernstein, P.L.C

20090206369 - High electron mobility transistor semiconductor device and fabrication method thereof: In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in... Agent: Posz Law Group, PLC

20090206368 - Rhombohedral cubic semiconductor materials on trigonal substrate with single crystal properties and devices based on such materials: Growth conditions are developed, based on a temperature-dependent alignment model, to enable formation of cubic group IV, group II-V and group II-VI crystals in the [111] orientation on the basal (0001) plane of trigonal crystal substrates, controlled such that the volume percentage of primary twin crystal is reduced from about... Agent: National Aeronautics And Space Administration Langley Research Center

20090206370 - Method and apparatus for fabricating a heterojunction bipolar transistor: In one embodiment, the invention is a method and apparatus for fabricating a heterojunction bipolar transistor. One embodiment of a heterojunction bipolar transistor includes a collector layer, a base region formed over the collector layer, a self-aligned emitter formed on top of the base region and collector layer, a poly-germanium... Agent: Wall & Tong, LLP IBM Corporation

20090206371 - Nitride semiconductor device and power conversion apparatus including the same: A nitride semiconductor device includes a first, a second, and a third nitride semiconductor layers that are laminated on a foundation semiconductor layer in stated order, the third nitride semiconductor layer having a wider band gap as compared with the second nitride semiconductor layer, a recess area that is dug... Agent: Birch Stewart Kolasch & Birch

20090206372 - Solid-state imaging device and method of driving the same: A solid-state imaging device includes an N-type semiconductor substrate, an N-type impurity region provided in the surficial portion of the N-type semiconductor substrate, a photo-electric conversion unit formed in the N-type impurity region, a charge accumulation unit formed in the N-type impurity region so as to contact with the photo-electric... Agent: Young & Thompson

20090206373 - Field effect transistor: A field effect transistor includes a GaN epitaxial substrate, a gate electrode formed on an electron channel layer of the substrate, and source and drain electrodes arranged spaced apart by a prescribed distance on opposite sides of the gate electrode. The source and drain electrodes are in ohmic contact with... Agent: Birch Stewart Kolasch & Birch

20090206374 - Multi-fin multi-gate field effect transistor with tailored drive current: Disclosed are embodiments of an improved multi-gated field effect transistor (MUGFET) structure and method of forming the MUGFET structure so that it exhibits a more tailored drive current. Specifically, the MUGFET incorporates multiple semiconductor fins in order to increase effective channel width of the device and, thereby, to increase the... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090206375 - Reduced leakage current field-effect transistor having asymmetric doping and fabrication method therefor: Reduced leakage current field-effect transistors and fabrication methods. Semiconductor device including substrate of first conductivity type, first well and second well of second conductivity type in substrate, channel of second conductivity type between first well and second well in substrate, and gate region of first conductivity type within channel, wherein... Agent: Perkins Coie LLP

20090206376 - Semiconductor device: A conventional semiconductor device has a problem that, when a vertical PNP transistor as a power semiconductor element is used in a saturation region, a leakage current into a substrate is generated. In a semiconductor device of the present invention, two P type diffusion layers as a collector region are... Agent: Fish & Richardson P.C.

20090206377 - Method and device for reducing crosstalk in back illuminated imagers: A method and resulting device for reducing crosstalk in a back-illuminated imager is disclosed, comprising providing a substrate comprising an insulator layer and a seed layer substantially overlying the insulator layer, an interface being formed where the seed layer comes in contact with the insulator layer; forming an epitaxial layer... Agent: Patent Docket Administrator Lowenstein Sandler P.C.

20090206378 - Photo sensor and flat panel display using the same: A photo sensor in a flat panel display includes a first transistor having first, second, and gate electrodes respectively coupled to first, second, and third nodes; a second transistor having first, second, and gate electrodes, respectively coupled to a fourth node, the first node, and a first control signal line;... Agent: Christie, Parker & Hale, LLP

20090206379 - Semiconductor device and manufacturing method thereof: A semiconductor device which can prevent the degradation of contact yield even when subjected to a high-temperature and long-time thermal process, and a manufacturing method thereof are provided. The semiconductor device includes: a first semiconductor circuit formed on a semiconductor substrate; a second semiconductor circuit formed above the first semiconductor... Agent: Knobbe Martens Olson & Bear LLP

20090206380 - Apparatus and method for using a well current source to effect a dynamic threshold voltage of a mos transistor: Deep submicron wells of MOS transistors, implemented over an ungrounded well, exhibit two modes of operation: a current sink mode and a current source mode. While operation as a current sink is well understood and successfully controlled, it is also necessary to control the current provided in the current source... Agent: Glenn Patent Group

20090206381 - Anti-fuse and method for forming the same, unit cell of nonvolatile memory device with the same: An anti-fuse includes a gate dielectric layer formed over a substrate, a gate electrode including a body portion and a plurality of protruding portions extending from the body portion, wherein the body portion and the protruding portions are formed to contact on the gate dielectric layer, and a junction region... Agent: Morgan Lewis & Bockius LLP

20090206382 - Flash memory device and programming and erasing methods therewith: A flash memory device and programming and erasing methods therewith is disclosed, to secure the programming and erasing characteristics by changing a structure of a floating gate, in which the flash memory device includes a first conductive type semiconductor substrate defined as a field area and an active area; a... Agent: Sherr & Vaughn, PLLC

20090206384 - Illuminating efficiency-increasable and light-erasable memory: An illuminating efficiency-increasable and light-erasable memory including a substrate, a memory device, many dielectric layers, and many cap layers is provided. The substrate includes a memory region. The memory device includes a select gate and a floating gate, and the select gate and the floating gate are disposed adjacently on... Agent: J C Patents, Inc.

20090206383 - Semiconductor devices having tunnel and gate insulating layers: A semiconductor device includes a semiconductor substrate having a surface, buried isolation regions protruding from the surface of the semiconductor substrate, and a first insulating layer on the surface of the semiconductor substrate between the isolation regions and including a fluorine, nitrogen, and/or heavy hydrogen impurity. A floating electrode is... Agent: Myers Bigel Sibley & Sajovec

20090206385 - Non-volatile memory device and method of operating the same: A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate... Agent: Volentine & Whitt PLLC

20090206386 - Decoding system capable of charging protection for flash memory devices: One embodiment of the present invention relates to a flash memory array. The flash memory array comprises at least two word lines of gate electrode material. At least one of the word lines is connected through a first metal level to a discharge circuit, while other word line(s) may connect... Agent: Eschweiler & Associates, LLC National City Bank Building

20090206392 - Memory device and fabrication method thereof: A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive... Agent: Harness, Dickey & Pierce, P.L.C

20090206387 - Non-volatile memory device, method of fabricating the same, and non-volatile semiconductor integrated circuit device, including the same: A non-volatile memory device has improved operating characteristics. The non-volatile memory device includes an active region; a wordline formed on the active region to cross the active region; and a charge trapping layer interposed between the active region and the wordline, wherein a cross region of the active region and... Agent: Mills & Onello LLP

20090206389 - Nonvolatile memory device and method of manufacturing the same: A nonvolatile memory device which contributes to improvement of electrical erase characteristics and a method of manufacturing the same are provided. The nonvolatile memory device includes a semiconductor substrate, a gate electrode formed on the semiconductor substrate, a diffusing layer electrode formed adjacent to the gate electrode on the semiconductor... Agent: Taft, Stettinius & Hollister LLP

20090206391 - Semiconductor memory device and method for manufacturing the same: A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed on the semiconductor substrate at predetermined intervals, a selecting transistor arranged on each of two sides of each of the plurality of word lines in which a spacing between the selecting transistor and an adjacent one... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090206390 - Semiconductor nonvolatile memory device with inter-gate insulating film formed on the side surface of a memory cell and method for manufacturing the same: A nonvolatile semiconductor device and method having a plurality of series-connected memory cells with floating and control gate electrodes, and a first insulating layer formed between the gate electrodes. One of the memory cells has the floating gate formed to contact the control gate electrode through an aperture in the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090206388 - Seperation methods for semiconductor charge accumulation layers and structures thereof: Devices and methods for isolating adjacent charge accumulation layers in a semiconductor device are disclosed. In one embodiment, a semiconductor device comprises a bit line formed in a semiconductor substrate, a charge accumulation layer formed on the semiconductor substrate, a word line formed on the charge accumulation layer across the... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090206393 - Nonvolatile memory element and method of manufacturing the same: A nonvolatile memory element includes a semiconductor region, a source region and a drain region provided in the semiconductor region, a tunnel insulating layer provided on the semiconductor region between the source region and the drain region, a charge storage layer provided on the tunnel insulating layer, a block insulating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090206394 - Strained channel pmos transistor and corresponding production method: The PMOS transistor (TR) has a channel width W of less than 1 micrometer, a channel length of less than or equal to 0.1 micrometer, and a distance of more than 0.5 micrometer between one edge of the channel and the corresponding edge of the active zone. The production of... Agent: Docket Clerk

20090206395 - Trench mosfet with double epitaxial structure: A trenched semiconductor power device includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The trenched semiconductor power device further includes a first epitaxial layer above heavily doped substrate and beyond the trench bottom and a second... Agent: Bo-in Lin

20090206396 - Vertical transistor of semiconductor device and method for forming the same: A vertical transistor of a semiconductor device and a method for forming the same are disclosed. The vertical transistor comprises a silicon fin disposed on a semiconductor substrate, a source region disposed in the semiconductor substrate below a lower portion of the silicon fin, a drain region disposed in an... Agent: Townsend And Townsend And Crew, LLP

20090206397 - Lateral trench mosfet with conformal depletion-assist layer: A lateral trench DMOS device formed in a substrate of a first conductivity type includes a vertical trench lined with a dielectric layer and containing a gate electrode. A source region of a second conductivity is adjacent the surface of the substrate and a sidewall of the trench. A drain... Agent: Advanced Analogic Technologies

20090206399 - Method of forming a recess channel trench pattern, and fabricating a recess channel transistor: A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern.... Agent: Marger Johnson & Mccollom, P.C.

20090206398 - Semiconductor device and manufacturing method of the semiconductor device: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal... Agent: Rossi, Kimms & Mcdowell LLP.

20090206400 - Systems and devices including fin transistors and methods of using, making, and operating the same: Disclosed are methods, systems and devices, including a system, having a memory device. In some embodiments, the memory device includes a plurality of fin field-effect transistors disposed in rows, a plurality of insulating fins each disposed between the rows, and a plurality of memory elements each coupled to a terminal... Agent: Fletcher Yoder (micron Technology, Inc.)

20090206401 - Trench transistor and method for fabricating a trench transistor: A trench transistor having a semiconductor body, in which a trench structure and an electrode structure embedded in the trench structure is disclosed. The electrode structure is electrically insulated from the semiconductor body by an insulation structure. The electrode structure has a gate electrode structure and a field electrode structure... Agent: Dicke, Billig & Czaja

20090206402 - Lateral trench mosfet with bi-directional voltage blocking: A lateral trench DMOS device formed in a substrate of a first conductivity type includes a trench extending downward from a surface of the substrate, the trench lined with a dielectric layer and containing a gate electrode. The device includes a source region of a second conductivity type adjacent the... Agent: Advanced Analogic Technologies

20090206403 - Method of trimming a hard mask layer, method for fabricating a gate in a mos transistor, and a stack for fabricating a gate in a mos transistor: A stack structure for forming a gate of a MOS transistor includes a substrate including a plurality of shallow trench isolations therein; a dielectric layer, a conductive layer and a hard mask layer formed on the substrate in sequence; and a tri-layer stack comprising a top photo resist layer, a... Agent: North America Intellectual Property Corporation

20090206405 - Fin field effect transistor structures having two dielectric thicknesses: Fin field-effect-transistor (finFET) structures having two dielectric thicknesses are generally described. In one example, an apparatus includes a semiconductor substrate, a semiconductor fin coupled with the semiconductor substrate, the semiconductor fin having at least a first surface, a second surface, and a third surface, the third surface being substantially parallel... Agent: Cool Patent, P.C. C/o Cpa Global

20090206406 - Multi-gate device having a t-shaped gate structure: A multi-gate device having a T-shaped gate structure is generally described. In one example, an apparatus includes a semiconductor substrate, at least one multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a gate region, a source region, and a drain region, the gate region being positioned between... Agent: Cool Patent, P.C. C/o Cpa Global

20090206404 - Reducing external resistance of a multi-gate device by silicidation: Reducing external resistance of a multi-gate device by silicidation is generally described. In one example, an apparatus includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a first surface, a second surface, and a third surface, the multi-gate fin also having a gate... Agent: Cool Patent, P.C. C/o Cpa Global

20090206407 - Semiconductor devices having tensile and/or compressive stress and methods of manufacturing: A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a... Agent: Greenblum & Bernstein, P.L.C

20090206412 - Hybrid orientation scheme for standard orthogonal circuits: Embodiments herein present device, method, etc. for a hybrid orientation scheme for standard orthogonal circuits. An integrated circuit of embodiments of the invention comprises a hybrid orientation substrate, comprising first areas having a first crystalline orientation and second areas having a second crystalline orientation. The first crystalline orientation of the... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090206408 - Nested and isolated transistors with reduced impedance difference: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions... Agent: HorizonIPPte Ltd

20090206411 - Semiconductor device and a method of manufacturing the same: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is... Agent: Miles & Stockbridge PC

20090206410 - Semiconductor device and method for manufacturing the same: Semiconductor devices required forming a stress control film to handle different stresses on each side when optimizing the stress on the respective P channel and N channel sections. A unique feature of the semiconductor device of this invention is that P and N channel stress are respectively optimized by making... Agent: Mcginn Intellectual Property Law Group, PLLC

20090206409 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device, includes forming a first insulating film containing silicon oxide as a main ingredient, on an underlying region, adhering water to the first insulating film, forming a polymer solution layer containing a silicon-containing polymer on the water-adhered first insulating film, and forming a second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090206413 - Cmos integration scheme employing a silicide electrode and a silicide-germanide alloy electrode: A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) are formed by patterning of a gate dielectric layer, a thin silicon layer, and a silicon-germanium alloy layer. After formation of the source/drain regions and gate spacers, silicon germanium alloy portions are removed from gate stacks. A... Agent: Scully, Scott, Murphy & Presser, P.C.

20090206414 - Contact configuration and method in dual-stress liner semiconductor device: A method for manufacturing a semiconductor device may comprise forming a conductive layer on a substrate, removing at least one portion of the conductive layer to form a plurality of separate conductive lines, forming a first stress-inducing layer of a first stress type on the conductive lines and the substrate,... Agent: Banner & Witcoff, Ltd.

20090206416 - Dual metal gate structures and methods: Two dummy gate structures containing disposable material portions and metal portions, source and drain regions, and metal semiconductor alloy regions are formed on a semiconductor substrate. A dielectric material layer is deposited and planarized so that top surfaces of the two remaining dummy gate structures are substantially coplanar. A disposable... Agent: Scully, Scott, Murphy & Presser, P.C.

20090206418 - Semiconductor constructions: The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes... Agent: Wells St. John P.s.

20090206417 - Semiconductor device and method for fabricating the same: A method for manufacturing a dual work function semiconductor device is disclosed. In one aspect, a method starts by forming a host dielectric layer over a first and second region of a substrate. A first dielectric capping layer is formed overlying the host dielectric layer on the first and second... Agent: Knobbe Martens Olson & Bear LLP

20090206415 - Semiconductor element structure and method for making the same: A semiconductor element structure includes a first MOS having a first high-K material and a first metal for use in a first gate, a second MOS having a second high-K material and a second metal for use in a second gate and a bridge channel disposed in a recess connecting... Agent: North America Intellectual Property Corporation

20090206419 - Monolithically integrated semiconductor assembly having a power component and method for producing a monolithically intergrated semiconductor assembly: A monolithically integrated semiconductor assembly having a power component, and a method for manufacturing a semiconductor assembly, are proposed, a monolithically integrated resistor element being provided between a first terminal and the second region, and a comparatively low-impedance electrical connection through the first region being provided between the resistor element... Agent: Kenyon & Kenyon LLP

20090206420 - Semiconductor device and method: A semiconductor device and method is disclosed. One embodiment provides an active region in a semiconductor substrate, including a first terminal region and a second terminal region. wherein the active region is interrupted by an inactive region, wherein an electrical power dissipation in the inactive region is zero or smaller... Agent: Dicke, Billig & Czaja

20090206421 - Organic light emitting display and manufacturing method thereof: Disclosed are an organic light emitting display and a manufacturing method thereof. The organic light emitting display includes an organic light emitting section that generates a light, a first thin film transistor that drives the organic light emitting section and includes a first polysilicon layer and a first gate electrode... Agent: Haynes And Boone, LLPIPSection

20090206423 - Method for manufacturing micromechanical components: The present invention relates to a method for manufacturing an acceleration sensor. In the method, thin SOI-wafer structures are used, in which grooves are etched, the walls of which are oxidized. A thick layer of electrode material, covering all other material, is grown on top of the structures, after which... Agent: Birch Stewart Kolasch & Birch

20090206422 - Micromechanical diaphragm sensor having a double diaphragm: A method for producing a micromechanical diaphragm sensor, and a micromechanical diaphragm sensor produced with the method. The micromechanical diaphragm sensor has at least one first diaphragm as well as a second diaphragm, which is disposed essentially on top of the first diaphragm. Furthermore, the micromechanical diaphragm sensor has a... Agent: Kenyon & Kenyon LLP

20090206424 - Hall-effect device with merged and/or non-merged complementary structure: A Hall-effect device with a merged and/or non-merged complementary structure in order to cancel stress induced offsets includes an n-type epitaxial Hall element and a p-type Hall element. The p-type Hall element can be implanted directly on top of the n-type epitaxial Hall element. The merged Hall elements can be... Agent: Honeywell International Inc. Patent Services

20090206427 - Magnetic memory device and method of fabricating the same: A magnetic memory device and a method of fabricating the same. The magnetic memory device includes a free layer, a write element, and a read element. The write element changes the magnetization direction of the free layer, and the read element senses the magnetization direction of the free layer. Herein,... Agent: Stanzione & Kim, LLP

20090206426 - Magnetoresistive effect element: A magnetoresistive element includes first, second, and third fixed layers, first, second, and third spacer layers, and a free layer. The first fixed layer is made of a ferromagnetic material and having an invariable magnetization direction. The first spacer layer is formed on the first fixed layer and made of... Agent: Knobbe Martens Olson & Bear LLP

20090206425 - Semiconductor device and method of manufacturing semiconductor device: Provided are a semiconductor device having an MTJ element capable of intentionally shifting the variation, at the time of manufacture, of a switching current of an MRAM memory element in one direction; and a manufacturing method of the device. The semiconductor device has a lower electrode having a horizontally-long rectangular... Agent: Mcdermott Will & Emery LLP

20090206428 - Direct electron detector: An electron detector (30) for detection of electrons comprises a semiconductor wafer (11) having a central portion (12) with a thickness of at most 150 μm, preferably at most 100 μm, formed by etching an area of a thicker wafer. On opposite sides of the central portion (12) there are... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090206429 - Angled implant for trench isolation: A trench isolation having a sidewall and bottom implanted region located within a substrate of a first conductivity type is disclosed. The sidewall and bottom implanted region is formed by an angled implant, a 90 degree implant, or a combination of an angled implant and a 90 degree implant, of... Agent: Dickstein Shapiro LLP

20090206433 - Image sensor and method for manufacturing the same: An image sensor and a method for manufacturing the same that includes a dielectric layer having a trench formed therein, a first micro-lens having a first structure formed in the trench, and a second micro-lens having a second structure formed over and contacting the first micro-lens such that the second... Agent: Sherr & Vaughn, PLLC

20090206432 - Image sensor and method of manufacturing the same: An image sensor and a method of manufacturing the same are provided. The image sensor includes a substrate having a sensor array area and a peripheral circuit area a first insulating film structure formed on the peripheral circuit area and including a plurality of first multi-layer wiring lines and a... Agent: F. Chau & Associates, LLC

20090206431 - Imager wafer level module and method of fabrication and use: Imager wafer level modules, methods of assembly for imager wafer level modules, and systems containing imager wafer level modules. An imager die and an optic lens stack are combined to form a module assembly. The module assembly is combined with a molded plastic, laminated plastic, or metallic interposer to form... Agent: Dickstein Shapiro LLP

20090206434 - Photoelectric conversion device and method of manufacturing the same: A photoelectric conversion device comprises a semiconductor substrate and a multilayer wiring structure, wherein the multilayer wiring structure includes a first wiring layer which serves as a top wiring layer in an effective region and contains aluminum as a principal component, a first insulation film arranged in the effective region... Agent: Fitzpatrick Cella Harper & Scinto

20090206435 - Solid state imaging device, manufacturing method of the same, and substrate for solid state imaging device: A method of manufacturing a solid state imaging device having photoelectric conversion devices, the method including: 1) forming a plurality of color filters differing in color from each other, 2) forming a transparent resin layer on the color filters, 3) forming an etching control layer on the transparent resin layer,... Agent: Staas & Halsey LLP

20090206430 - Solid-state imaging device and method for manufacturing the same: A pattern (6B) is formed by performing selective exposure and development on a photosensitive resist (6A), and then the pattern (6B) is decolorized by irradiating the pattern with ultraviolet or visible light. Then, a microlens (6) is formed by deforming the shape of the pattern (6B) into a microlens shape... Agent: Mcdermott Will & Emery LLP

20090206436 - Semiconductor apparatus: An improved semiconductor apparatus that comprises an elongated structure that extends into the substrate. The apparatus comprises a collection contact, a resistive path, a bias connection that creates along the length of the elongated structure, an electric field component that drives signal charge carriers in a direction perpendicular to the... Agent: Barnes & Thornburg LLP

20090206437 - Photo-detecting apparatus and photo-detecting method: A photo-detecting apparatus includes a photodiode that coverts light into electricity, a reverse-voltage switching unit that switches a reverse voltage to be applied to the photodiode, a current-difference detecting unit that detects a change in an output current of the photodiode occurring due to switching of the reverse voltage as... Agent: Staas & Halsey LLP

20090206438 - Semiconductor component: A semiconductor component and a method for manufacturing such a semiconductor component which has a resistance behavior which depends heavily on the temperature. This resistance behavior is obtained by a special multi-layer structure of the semiconductor component, one layer being designed in such a way that, for example, multiple p-doped... Agent: Kenyon & Kenyon LLP

20090206439 - Semiconductor device: In order to provide an ESD protection circuit having high immunity to ESD destruction without increasing a chip area of a semiconductor device, a diode-type ESD protection circuit formed of a junction between a first conductivity type diffusion layer and a second conductivity type diffusion layer is formed in an... Agent: Bruce L. Adams, Esq Adams & Wilks

20090206440 - Power semiconductor device: A semiconductor device has a heavily doped substrate and an upper layer with doped silicon of a first conductivity type disposed on the substrate, the upper layer having an upper surface and including an active region that comprises a well region of a second, opposite conductivity type. An edge termination... Agent: Coats & Bennett/infineon Technologies

20090206443 - Devices including fin transistors robust to gate shorts and methods of making the same: Disclosed are methods, systems and devices, including a method that includes the acts of etching an inter-row trench in a substrate, substantially or entirely filling the inter-row trench with a dielectric material, and forming a fin and a insulating projection at least in part by etching a gate trench in... Agent: Fletcher Yoder (micron Technology, Inc.)

20090206444 - Integrated semiconductor device: An integrated semiconductor device includes a plurality of semiconductor elements having different integrated element circuits or different sizes; an insulating material arranged between the semiconductor elements; an organic insulating film arranged entirely on the semiconductor elements and the insulating material; a fine thin-layer wiring that arranged on the organic insulating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090206442 - Method and structure for relieving transistor performance degradation due to shallow trench isolation induced stress: A method of forming shallow trench isolation (STI) regions for semiconductor devices, the method including defining STI trench openings within a semiconductor substrate; filling the STI trench openings with an initial trench fill material; defining a pattern of nano-scale openings over the substrate, at locations corresponding to the STI trench... Agent: Cantor Colburn LLP - IBM Fishkill

20090206441 - Method of forming coplanar active and isolation regions and structures thereof: Methods of forming coplanar active regions and isolation regions and structures thereof are disclosed. One embodiment includes shallow-trench-isolation (STI) formation in a semiconductor-on-insulator (SOI) layer on a substrate of a semiconductor structure; and bonding a handle wafer to the STI and SOI layer to form an intermediate structure. The intermediate... Agent: Hoffman Warnick LLC

20090206445 - Semiconductor device and method of forming the same: A semiconductor device may include, but is not limited to, first and second well regions, and a well isolation region isolating the first and second well regions. The first and second well regions each may include an active region, a device isolation groove that defines the active region, and a... Agent: Young & Thompson

20090206446 - Electrical device and fabrication method: An electrical device with a fin structure, a first section of the fin structure having a first width and a first height, a second section of the fin structure having a second width and a second height, wherein the first width is smaller than the second width and the first... Agent: Slater & Matsil LLP

20090206447 - Anti-fuse device structure and electroplating circuit structure and method: Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090206448 - Semiconductor device and method for manufacturing the same: A semiconductor device that prevents the leaning of storage node when forming a capacitor having high capacitance includes a plurality of cylinder-shaped storage nodes formed over a semiconductor substrate; and support patterns formed to fix the storage nodes in the form of an ‘L’ or a ‘+’ when viewed from... Agent: Ladas & Parry LLP

20090206449 - Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit: Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit. An electrical characteristic of semiconductor devices formed on a common substrate, such as the current gains of bipolar junction transistors, may be altered by modifying stresses in structures indirectly on or over, or... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090206452 - Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device: A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The... Agent: Schwegman, Lundberg & Woessner / Atmel

20090206450 - Method of manufacturing a semiconductor device, semiconductor device obtained herewith, and slurry suitable for use in such a method: The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (2) which is provided with at least one semiconductor element and the surface of which is provided with an aluminum layer (3) that is patterned by means of a chemical-mechanical... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090206451 - Semiconductor device: A semiconductor device is provided, in which a well contact diffusion layer pattern (13) and a sub-contact diffusion layer pattern (14) are arranged between a P-ch transistor diffusion layer pattern (11) and an N-ch transistor diffusion layer pattern (12), and a CMP dummy pattern (15) is arranged around a P-ch... Agent: Mcginn Intellectual Property Law Group, PLLC

20090206453 - Method for preparing modified porous silica films, modified porous silica films prepared according to this method and semiconductor devices fabricated using the modified porous silica films: A hydrophobic compound having at least one each of hydrophobic group (an alkyl group having 1 to 6 carbon atoms or a —C6H5 group) and polymerizable group (a hydrogen atom, a hydroxyl group or a halogen atom) is allowed to undergo a gas-phase polymerization reaction, under reduced pressure (of not... Agent: Arent Fox LLP

20090206454 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device includes the steps of: forming a first insulating film on a semiconductor substrate; removing part of the first insulating film; forming a second insulating film having a leakage current density higher than that of the first insulating film on a region where the... Agent: Mcdermott Will & Emery LLP

20090206455 - Integrated circuit stacked package precursors and stacked packaged devices and systems therefrom: A package-on-package (POP) package precursor and packaged devices and systems therefrom includes an electronic substrate including electrically conductive layers and a top surface. A first portion of the top surface has an IC die attached thereon. A second portion of the top surface has a plurality of first attach pads... Agent: Texas Instruments Incorporated

20090206456 - Module including a sintered joint bonding a semiconductor chip to a copper surface: A module includes a substrate including a first copper surface and a semiconductor chip. The module includes a first sintered joint bonding the semiconductor chip directly to the first copper surface.... Agent: Dicke, Billig & Czaja

20090206457 - Resin molding part and manufacturing method thereof: A primary molding product is formed by integrally forming a first lead frame and a second lead frame with a primary molding resin portion. In addition, in order to prevent separation of the first lead frame and the second lead frame from the primary molding resin portion, a hook-and-hold portion... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090206458 - Flat leadless packages and stacked leadless package assemblies: A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also,... Agent: Haynes Beffel & Wolfeld LLP

20090206459 - Quad flat non-leaded package structure: A quad flat non-leaded package structure including a die pad, a plurality of leads, a chip, and a molding compound is provided. The die pad has a top surface and an opposite bottom surface, and the leads are disposed around the die pad. A concave portion is disposed at the... Agent: J C Patents, Inc.

20090206461 - Integrated circuit and method: An integrated circuit and method of fabricating an integrated circuit. One embodiment includes a circuit chip, a contact pad, and a projecting top contact. A signal line couples the contact pad to the projecting top contact, the contact pad, the projecting top contact. The signal line is arranged on a... Agent: Dicke, Billig & Czaja

20090206460 - Intermediate bond pad for stacked semiconductor chip package: The invention provides apparatus and methods by which, in a stacked semiconductor chip package, a continuous electrical path may be provided among bond pads by way of one or more intermediate bond pad electrically isolated from its underlying surface.... Agent: Texas Instruments Incorporated

20090206464 - Method of forming semiconductor chips, the semiconductor chips so formed and chip-stack package having the same: Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of... Agent: Marger Johnson & Mccollom, P.C.

20090206462 - Semiconductor device and method for manufacturing thereof: A semiconductor device 100 includes: a first semiconductor package 10; a first interposer 12 having an upper surface on which the first semiconductor package 10 is mounted; a first molding resin 14 that is provided on the upper surface of the first interposer 12 and seals the first semiconductor package... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090206463 - Semiconductor device, method of manufacturing the same, and electronic equipment using the same: A semiconductor device includes a substrate 2, a semiconductor element 3, a molding resin portion 4, and a plurality of connection terminals 5 arranged on a surface of the substrate around the outer periphery of the molding resin portion 4. In a region B corresponding to a resin passage used... Agent: Steptoe & Johnson LLP

20090206468 - Board on chip package and manufacturing method thereof: A method of manufacturing a board on chip package including laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball... Agent: Staas & Halsey LLP

20090206467 - Integrated circuit package: Package (1) having a sensor assembly (2) with at least one sensitive surface (21) and an attachment surface (22), a carrier element (3) with a sensor attachment area (31), and a sensor attach material (4) for attaching the sensor assembly (2) to the sensor attachment area (31) of the carrier... Agent: Young & Thompson

20090206465 - Semiconductor chip package structure for achieving electrical connection without using a wire-bonding process and method for making the same: A semiconductor chip package structure for achieving electrical connection without using a wire-bonding process includes: a package unit, a semiconductor chip, a first insulative layer, first conductive layers, a second insulative layer, and second conductive layers. The package unit has a receiving groove. The semiconductor chip receives in the receiving... Agent: Rosenberg, Klein & Lee

20090206466 - Semiconductor device: A semiconductor device is provided that can further reduce the thickness of an electronic device and that can reduce its own mounting area and development period. This semiconductor device has a first semiconductor chip and a second semiconductor chip, and is formed in a WLCSP type package. On the upper... Agent: Fish & Richardson P.C. Citigroup Center

20090206469 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device has a plurality of wafers which are laminated to each other, wherein: each wafer includes an lamination surface to which another wafer is laminated and a substrate having an element formed thereon; the lamination surface is provided with an electric signal connecting portion that electrically connects to... Agent: Birch Stewart Kolasch & Birch

20090206471 - Electronic parts packaging structure and method of manufacturing the same: An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection... Agent: Kratz, Quintos & Hanson, LLP

20090206470 - Semiconductor device manufacturing method, semiconductor device, and wiring board: In a semiconductor device manufacturing method, a semiconductor chip is mounted on a support board so as to expose a side of the semiconductor chip on which a plurality of terminal electrodes are provided. An insulating layer is formed so as to cover the side of the semiconductor chip on... Agent: Drinker Biddle & Reath (dc)

20090206472 - Cof packaging structure, method of manufacturing the cof packaging structure, and method for assembling a driver ic and the cof packaging structure thereof: A COF packaging structure includes a substrate, a first conductive foil, and a second conductive foil. The substrate has a first surface and a second surface opposite to the first surface. The first conductive foil is disposed on the first surface of the substrate and has a first designated pattern... Agent: North America Intellectual Property Corporation

20090206474 - Electrical device and method of manufacturing electrical devices using film embossing techniques to embed integrated circuits into film: An electrical device and method of making same is provided wherein a chip or other electrical component is embedded in a substrate. The substrate may be a thermoplastic material capable of deforming around the chip and at least partially encasing the chip when heat and/or pressure is applied to the... Agent: Avery Dennison Corporation Amanda Wittine

20090206473 - System and method for integrated waveguide packaging: A millimeter wave system or package may include at least one printed wiring board (PWB), at least one integrated waveguide interface, and at least one monolithic microwave integrated circuit (MMIC). The package may be assembled in panel form incorporating parallel manufacturing techniques.... Agent: Snell & Wilmer L.L.P. (main)

20090206475 - Method of manufacturing semiconductor device, and semiconductor device: A method of manufacturing a semiconductor device which includes step of forming a lower resist film over an insulating interlayer; forming a first opening having a circular geometry in a plan view, and second to fifth openings arranged respectively on four sides of the first opening, in the lower resist... Agent: Mcginn Intellectual Property Law Group, PLLC

20090206476 - Conductive structure for a semiconductor integrated circuit: A conductive structure for a semiconductor integrated circuit is provided. The semiconductor integrated circuit comprises a pad, and a passivation layer partially overlapping the pad, which jointly define an opening portion. The conductive structure is adapted to be electrically connected to the pad through the opening portion. The conductive structure... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090206478 - Flip chip device and manufacturing method thereof: A flip chip device made using LCD-COG (liquid crystal display-chip on glass) technique. The flip chip device comprises a substrate, at least one chip having active area with a plurality of compliant bumps thereon. The compliant bumps are centrally disposed in the center of the chip for electrically connecting the... Agent: Rabin & Berdo, PC

20090206477 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device has a plurality of wafers which are laminated to each other, wherein: each wafer comprises an lamination surface to which another wafer is laminated; the lamination surface is provided with an electric signal connecting portion that electrically connects to said another surface so as to form a... Agent: Birch Stewart Kolasch & Birch

20090206480 - Fabricating low cost solder bumps on integrated circuit wafers: A low cost method of forming solder bumps on an integrated circuit (IC) wafer includes depositing solder directly onto stud bumps formed on bond pads of the IC wafer. In some implementations, stud bumps are formed on the IC wafer by performing wire ball-bonding onto metal bond pads of the... Agent: Fish & Richardson P.C.

20090206479 - Solder interconnect pads with current spreading layers: Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on... Agent: Schmeiser, Olsen & Watts

20090206481 - Stacking of transfer carriers with aperture arrays as interconnection joints: An interconnection mechanism between plated through holes is disclosed, a first embodiment includes a first substrate having a first plated through hole; a second substrate having a second plated through hole; a metal core is configured in between the two plated through holes; the metal ball has a diameter larger... Agent: Lowe Hauptman Ham & Berner, LLP

20090206482 - Tooling method for fabricating a semiconductor device and semiconductor devices fabricated thereof: A tooling method for fabricating semiconductor devices includes identifying two adjacent device lines having a device-to-device spacing width in an active region of a substrate, performing an operation to selectively define a first region as a region between the two adjacent device lines overlapping the active region, forming a first... Agent: North America Intellectual Property Corporation

20090206483 - Nanotube and metal composite interconnects: Nanotube and metal composite interconnects are generally described. In one example, an apparatus includes an interlayer dielectric (ILD) and one or more interconnect structures coupled to the ILD, the one or more interconnect structures including a composite of metal and one or more nanotubes.... Agent: Cool Patent, P.C. C/o Cpa Global

20090206484 - Microstructure modification in copper interconnect structure: Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured... Agent: Scully, Scott, Murphy & Presser, P.C.

20090206485 - Novel structure and method for metal integration: An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of forming the interconnect structure does not disrupt the coverage of the deposited diffusion barrier in the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090206486 - Wirebond over post passivation thick metal: A chip assembly includes a semiconductor chip and a wirebonded wire. The semiconductor chip includes a passivation layer over a silicon substrate and over a thin metal structure, a first thick metal layer over the passivation layer and on a contact point of the thin metal structure exposed by an... Agent: Megica Corporation

20090206487 - Wire bonding substrate and fabrication thereof: A method for forming a wire bonding substrate is disclosed. A substrate comprising a first surface and a second surface is provided. A through hole is formed in the substrate. A conductive layer is formed on the first surface and the second surface of the substrate and covers a sidewall... Agent: Quintero Law Office, PC

20090206490 - semiconductor device and a method of manufacturing the sae: A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second... Agent: Miles & Stockbridge PC

20090206489 - Dual damascene metal interconnect structure having a self-aligned via: A recessed region containing a line portion and a bulge portion is formed in a hard mask layer. Self-assembling block copolymers containing two or more different polymeric block components that are immiscible with one another are applied within the recessed region and annealed. A cylindrical polymeric block centered at the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090206491 - Semiconductor device: A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090206488 - Through substrate annular via including plug filler: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within... Agent: Scully, Scott, Murphy & Presser, P.C.

20090206492 - Semiconductor device: A semiconductor device includes a semiconductor chip, a first substrate, and a second substrate. The first substrate includes a plurality of wires and a plurality of first electrodes, each first electrode being connected with each wire. The second substrate includes the semiconductor chip that is mounted thereon, and a plurality... Agent: Mcginn Intellectual Property Law Group, PLLC

20090206493 - Flip chip interconnection pad layout: A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate... Agent: Robert D. Atkins

20090206494 - Wiring over substrate, semiconductor device, and methods for manufacturing thereof: A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also... Agent: Eric Robinson

20090206495 - Semiconductor device and method for manufacturing same: A semiconductor device wherein a force of peeling a chip from a substrate does not operate even the semiconductor device is exposed under a high temperature condition after bonding and a bonding state of the substrate and the chip can be maintained, and a method for manufacturing such semiconductor device... Agent: Nixon & Vanderhye, PC

20090200533 - Resistive memory element and method of fabrication: An integrated circuit including a memory cell and a method of manufacturing the integrated circuit are described. The memory cell includes a buried gate select transistor and a resistive memory element coupled to the buried gate select transistor. The resistive memory element stores information based on a resistivity of the... Agent: Ira S. Matsil Slater & Matsil, L.L.P.

20090200534 - Method for fabrication of polycrystalline diodes for resistive memories: The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing... Agent: Scully, Scott, Murphy & Presser, P.C.

20090200535 - Non-volatile memory element with improved temperature stability: An integrated circuit including a memory element is described. The memory element includes a solid electrolyte layer that includes a matrix material having a metal dissolved therein, and a dopant distributed in the matrix material, the dopant competing with the metal to bind with elements of the matrix material at... Agent: Slater & Matsil, L.L.P.

20090200536 - Method for manufacturing an electric device with a layer of conductive material contracted by nanowire: The electric device (100) according to the invention comprises a layer (107) of a memory material which has an electrical resistivity switchable between a first value and a second value. The memory material may be a phase change material. The electric device (100) further comprises a set of nanowires (NW)... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090200537 - Phase change memory device preventing contact loss and method for manufacturing the same: A phase change memory device includes a silicon substrate having a phase change cell region. A plurality of phase change cell are formed in the phase change region of the silicon substrate. A contact comprising a first contact and a second contact is formed on each of the phase change... Agent: Ladas & Parry LLP

20090200539 - Composite nanorod-based structures for generating electricity: Composite nanorod-based structures for generating electricity are disclosed. One embodiment is an article of manufacture that includes a first layer with an array of nanowires and a dielectric material. The nanowires include: a core semiconducting region with a first type of doping; a shell semiconducting region with a second type... Agent: Morgan, Lewis & Bockius, LLP. (pa)

20090200538 - Group lll-v compound semiconductor and a method for producing the same: A Group III-V compound semiconductor includes an n-type layer, a p-type layer, a p-type layer represented by a formula InaGabAlcN, having a thickness of not less than 300 nm, and a multiple quantum well structure which exists between the n-type layer and the p-type layer, has at least two quantum... Agent: Fitch, Even, Tabin & Flannery

20090200540 - Metal-oxide-semiconductor device including a multiple-layer energy filter: A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from... Agent: Ryan, Mason & Lewis, LLP

20090200541 - Making a structure: A structure includes a surface and a non-equilibrium two-dimensional semiconductor micro structure on the surface.... Agent: Hewlett Packard Company

20090200542 - Compounds and organic light emitting device using the same: Disclosed is an organic light emitting device. The organic light emitting device comprises a first electrode, organic material layer(s) comprising a light emitting layer, and a second electrode. The first electrode, the organic material layer(s), and the second electrode form layered structure and at least one layer of the organic... Agent: Mckenna Long & Aldridge LLP

20090200543 - Method of forming an electronic device on a substrate supported by a carrier and resultant device: A method for forming an electronic device on a flexible substrate conditions the surface of a carrier to form a holding area for retaining the flexible substrate. A contact surface of the flexible substrate is applied against the carrier with an intermediate binding material applied between at least the holding... Agent: Carestream Health, Inc.

20090200544 - Organic light emitting device and method of manufacturing the same: An organic light emitting device includes first, second, and third pixels each displaying a different color. Each pixel includes a first electrode, a second electrode facing the first electrode, and an emission layer between the first and second electrodes. The first electrodes of the first and second pixels respectively include... Agent: H.c. Park & Associates, PLC

20090200545 - Zno-based semiconductor device: Provided is a ZnO-based semiconductor device capable of growing a flat ZnO-based semiconductor layer on an MgZnO substrate having a main surface on the lamination side oriented in a c-axis direction. ZnO-based semiconductor layers 2 to 6 are epitaxially grown on an MgxZn1-xO (0≦x≦1) substrate 1 having a +C surface... Agent: Rabin & Berdo, PC

20090200548 - Guard ring extension to prevent realiability failures: An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090200549 - Semiconductor device: A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first seal ring. The first seal ring comprises a first monitor circuit isolated by a first dielectric layer embedded in... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090200546 - Test structures and methods: Test structures and methods for semiconductor devices, lithography systems, and lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a lithography mask, the lithography mask including a... Agent: Slater & Matsil LLP

20090200547 - Trench depth monitor for semiconductor manufacturing: A method of manufacturing a semiconductor wafer having at least one device trench extending to a first depth position includes providing a semiconductor substrate having first and second main surfaces and a semiconductor material layer having first and second main surfaces disposed on the first main surface of the semiconductor... Agent: Panitch Schwarze Belisario & Nadel LLP

20090200550 - Method for forming an electronic device on a flexible substrate supported by a detachable carrier: A method for forming an electronic device provides a carrier formed from a composite material comprising a plastic binder and an embedded material. A substrate material is attached to the carrier. The substrate is processed to form the electronic device thereon. The substrate is then detached from the carrier to... Agent: Carestream Health, Inc.

20090200553 - High temperature thin film transistor on soda lime glass: The present invention generally comprises a low cost TFT and a method of manufacturing a TFT. For TFTs, soda lime glass would be an attractive alternative to non-alkali glass, but a soda lime glass substrate will permit sodium to diffuse into the active layer and degrade the performance of the... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090200551 - Microcrystalline silicon thin film transistor: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a first gas mixture having a hydrogen containing gas to a silicon containing gas flow... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090200552 - Microcrystalline silicon thin film transistor: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a gas mixture having a hydrogen-based gas, a silicon-based gas and an argon gas into... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090200554 - Display device and method of manufacturing the same: The display device includes a substrate, a thin film transistor (TFT), which includes a gate electrode, a semiconductor layer, and source and drain electrodes, on the substrate member, a passivation layer on the TFT and having an opening to expose a portion of the drain electrode, and a pixel electrode... Agent: H.c. Park & Associates, PLC

20090200556 - Thin film transistor panel for multi-domain liquid crystal display: A thin film transistor array panel is provided, which includes: an insulating substrate; a plurality of first signal lines formed on the insulating substrate; a plurality of second signal lines formed on the insulating substrate and intersecting the first wire in an insulating manner; a pixel electrode formed in a... Agent: F. Chau & Associates, LLC

20090200555 - Thin film transistor substrate, defect repairing method therefor, and display device: A thin film transistor substrate includes: a substrate; a thin film transistor and a capacitor formed on the substrate; and a protective film for protecting an electrode on a back surface side of the capacitor when an electrode on a front surface side of the capacitor is cut by irradiation... Agent: Rader Fishman & Grauer PLLC

20090200557 - Semiconductor device: A semiconductor device includes a semiconductor layer including a channel region, and a first region and a second region to which an impurity element is introduced to make the first region and the second region a source and a drain, a third region, and a gate electrode provided to partly... Agent: Eric Robinson

20090200558 - Method and apparatus of fabricating liquid crystal display device: A method and an apparatus of fabricating a liquid crystal display device adapted to improve a lift-off efficiency are disclosed. The liquid crystal display device is also disclosed. The method includes forming a first thin film on a substrate; forming a photo-resist pattern on the first thin film; etching the... Agent: Mckenna Long & Aldridge LLP

20090200559 - Silicon carbide semiconductor device including deep layer: A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench penetrating the source region and the base region to the drift layer, a... Agent: Posz Law Group, PLC

20090200560 - Light emitting device and method of forming the same: An embodiment of present invention discloses a light-emitting device comprising a first multi-layer structure comprising a first lower layer; a first upper layer; and a first active layer able to emit light under a bias voltage and positioned between the first lower layer and the first upper layer; a second... Agent: Bacon & Thomas, PLLC

20090200561 - Composite phosphors based on coating porous substrates: A composite material is provided including a phosphor material of at least one of among hafnium oxide, niobium oxide, tantalum oxide or zirconium oxide as a conformal coating on a porous substrate, the composite characterized as exhibiting photoluminescence at room temperature. Also provided is a composite material including a phosphor... Agent: Los Alamos National Security, LLC

20090200562 - Integrated circuit die, integrated circuit package, and packaging method: An integrated circuit package includes an integrated circuit die 1 having a plurality of optical elements 5 sensitive to and/or capable of generating light, whereby data communication to circuitry of the integrated circuit die can be effected using a data channels implemented using the plurality of elements. The data channels... Agent: Freescale Semiconductor, Inc. Law Department

20090200563 - Group iii nitride semiconductor light-emitting device and production method therefor: Provided is a method for producing a Group III nitride semiconductor light-emitting device including a GaN substrate serving as a growth substrate, which method facilitates tapering of a bottom portion of the GaN substrate. In the production method, firstly, a Group III nitride semiconductor layer, an ITO electrode, a p-electrode,... Agent: Mcginn Intellectual Property Law Group, PLLC

20090200564 - Method and structure for fabricating smooth mirrors for liquid crystal on silicon devices: A method for fabricating a liquid crystal on silicon display device. The method includes providing a substrate, e.g., silicon wafer. The method includes forming a transistor layer overlying the substrate. Preferably, the transistor layer has a plurality of MOS devices therein. The method includes forming an interlayer dielectric layer (e.g.,... Agent: Townsend And Townsend And Crew, LLP

20090200565 - Gan-based semiconductor light emitting device: There is provided a GaN-based semiconductor light emitting device including: a substrate; and an n-type GaN-based semiconductor layer, an active layer and a p-type GaN-based semiconductor layer sequentially deposited on the substrate, wherein the active layer includes: a first barrier layer including AlxInyGa1−x−yN, where 0<x<1, 0<y<1, and 0<x+y<1; a second... Agent: Mcdermott Will & Emery LLP

20090200567 - Chip-type led package and light emitting apparatus having the same: Disclosed are a chip-type LED package and a light emitting apparatus having the same. The chip-type LED package includes a thermally conductive substrate with lead electrodes formed thereon. An LED chip is mounted on the thermally conductive substrate, and a lower molding portion covers the LED chip. In addition, an... Agent: H.c. Park & Associates, PLC

20090200569 - Optoelectronic substrate and methods of making same: A method of producing an optoelectronic substrate by detaching a thin layer from a semi-conducting nitride substrate and transferring it to an auxiliary substrate to provide at least one semi-conducting nitride layer thereon, metallizing at least a portion of the surface of the auxiliary substrate that includes the transferred nitride... Agent: Winston & Strawn LLP Patent Department

20090200568 - Semiconductor light-emitting device: An etching process includes forming a metal-fluoride layer at least as a part of an etching mask formed over a semiconductor layer at a temperature of 150° C. or higher; patterning the metal-fluoride layer; and etching the semiconductor layer using the patterned metal-fluoride layer as a mask. Using this etching... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090200566 - Side-view light emitting diode package having a reflector: Disclosed herein is a side-view light emitting diode package with a reflector. The side-view light emitting diode package of the present invention comprises first and second lead terminals spaced apart from each other. The package body supports the first and second lead terminals and has an elongated opening through which... Agent: H.c. Park & Associates, PLC

20090200570 - Light emitting device mounting substrate, light emitting device housing package, light emitting apparatus, and illuminating apparatus: A light-emitting apparatus with improved dissipation efficiency of heat transmitted to a specific electrode of a light-emitting device is provided. A light-emitting device mounting substrate used for the light emitting apparatus include a base body (1) which mounts thereon a light-emitting device (3); a first electrically conductive path (L1) formed... Agent: Hogan & Hartson L.L.P.

20090200571 - Semiconductor light emitting device of junction-down type and semiconductor light emitting element of junction-down type: In a semiconductor light emitting device of junction-down type, a semiconductor light emitting element having a stripe part is provided with a bonding part for die bonding in a part of a surface thereof where the stripe part is formed, the bonding part being at a position away from the... Agent: Rabin & Berdo, PC

20090200572 - Lighting device and production method of the same: Bonding between a light-emitting element and electrodes of a substrate is ensured to enhance reliability of a lighting device. In the lighting device of the present invention, a material made of metal alkoxide or polymetalloxane generated from metal alkoxide is used as a coating material covering the light-emitting element. This... Agent: Bruce L. Adams, Esq Adams & Wilks

20090200573 - Light emitting element and manufacturing method thereof: In a laser chip 1 using a nitride semiconductor having a hexagonal crystal structure, the −c plane is used as a first resonator facet A, which is the side of the laser chip 1 through which light is emitted. On the first resonator facet A, that is, on the −c... Agent: Harness, Dickey & Pierce, P.L.C

20090200574 - Power semiconductor device: A power semiconductor device includes a first layer of a first conductivity type, which has a first main side and a second main side opposite the first main side. A second layer of a second conductivity type is arranged in a central region of the first main side and a... Agent: Buchanan, Ingersoll & Rooney PC

20090200575 - Semiconductor device: A semiconductor device is provided with a semiconductor region, a gate electrode, a source electrode and a drain electrode. The semiconductor region is formed on a semiconductor substrate surface and includes a first semiconductor portion of a first conducting type, a second semiconductor portion of a second conducting type, a... Agent: GlobalIPCounselors, LLP

20090200576 - Semiconductor device: A semiconductor device includes: a first semiconductor layer including AlXGa1-XN (0≦X≦1); a second semiconductor layer provided on the first semiconductor layer, including AlYGa1-YN (0≦Y≦1, X<Y), and having a larger bandgap than the first semiconductor layer; a source electrode provided on the second semiconductor layer; a drain electrode provided on the... Agent: Patterson & Sheridan, L.L.P.

20090200577 - Semiconductor device and method of manufacturing such a device: The invention relates to a semiconductor device with a substrate (11) and a semiconductor body (11) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) comprising a first, a second and a third connection conductor, which emitter region (1) comprises a... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090200578 - Self-repairing field effect transisitor: A self repairing field effect transistor (FET) device, in accordance with one embodiment, includes a plurality of FET cells each having a fuse link. The fuse links are adapted to blow during a high current event in a corresponding cell.... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20090200579 - Semiconductor device and layout method thereof: A semiconductor device includes first lines extending in a first direction and formed in a first wiring layer in a predetermined arrangement order, second lines formed in a second wiring layer different from the first wring layer in the predetermined arrangement order, and contacts electrically connecting between the first lines... Agent: Mcginn Intellectual Property Law Group, PLLC

20090200580 - Image sensor and pixel including a deep photodetector: What is disclosed is an apparatus comprising a transfer gate formed on a substrate and a photodiode formed in the substrate next to the transfer gate. The photodiode comprises a shallow N-type collector formed in the substrate, a deep N-type collector formed in the substrate, wherein a lateral side of... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200581 - High breakdown voltage double-gate semiconductor device: A double-gate semiconductor device provides a high breakdown voltage allowing for a large excursion of the output voltage that is useful for power applications. The double-gate semiconductor device may be considered a double-gate device including a MOS gate and a junction gate, in which the bias of the junction gate... Agent: Peters Verny , L.L.P.

20090200582 - Semiconductor device with an improved operating property: The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region... Agent: Mcdermott Will & Emery LLP

20090200583 - Feature patterning methods: Methods of patterning features of semiconductor devices and methods of processing and fabricating semiconductor devices are disclosed. In one embodiment, a method of processing a semiconductor device includes forming first sidewall spacers on a first hard mask, removing the first hard mask, and forming a first material layer over the... Agent: Slater & Matsil LLP

20090200585 - Backside illuminated imaging sensor with backside p+ doped layer: A backside illuminated imaging sensor includes a semiconductor layer having a P-type region. A frontside and backside P+ doped layers are formed within the semiconductor layer. An imaging pixel having a photodiode is formed within the semiconductor layer, where the photodiode is an N- region formed within the P-type region... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200589 - Backside illuminated imaging sensor with improved infrared sensitivity: A backside illuminated imaging sensor includes a semiconductor layer and an infrared detecting layer. The semiconductor layer has a front surface and a back surface. An imaging pixel includes a photodiode region formed within the semiconductor layer. The infrared detecting layer is disposed above the front surface of the semiconductor... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200588 - Backside illuminated imaging sensor with light reflecting transfer gate: A backside illuminated imaging sensor includes a semiconductor having an imaging pixel that can include a photodiode region, an insulation layer, and a reflective layer. The photodiode is typically formed in the frontside of the semiconductor substrate. A surface shield layer can be formed on the frontside of the photodiode... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200586 - Backside illuminated imaging sensor with silicide light reflecting layer: A backside illuminated imaging sensor includes a semiconductor layer, a metal interconnect layer and a silicide light reflecting layer. The semiconductor layer has a front surface and a back surface. An imaging pixel that includes a photodiode region is formed within the semiconductor layer. The metal interconnect layer is electrically... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200584 - Full color cmos imager filter: A full color complementary metal oxide semiconductor (CMOS) imaging circuit is provided. The imaging circuit comprises an array of photodiodes including a plurality of pixel groups. Each pixel group supplies 3 electrical color signals, corresponding to 3 detectable colors. The circuit also includes a color filter array overlying the photodiode... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20090200591 - Image sensor with light receiving region having different potential energy according to wavelength of light and electronic product employing the same: There is provided a CMOS image sensor and an electronic product using the same. The CMOS image sensor includes a plurality of pixels for embodying colors having different wavelengths. Each of pixels includes a buried barrier layer disposed in a semiconductor substrate and having a barrier potential energy of a... Agent: Mills & Onello LLP

20090200590 - Image sensor with low electrical cross-talk: An array of pixels is formed using a substrate, where each pixel has a substrate having a backside and a frontside that includes metalization layers, a photodiode formed in the substrate, frontside P-wells formed using frontside processing that are adjacent to the photosensitive region, and an N-type region formed in... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200587 - Masked laser anneal during fabrication of backside illuminated image sensors: A technique for fabricating an array of imaging pixels includes fabricating front side components on a front side of the array. After fabricating the front side components, a dopant layer is implanted on a backside of the array. A mask is formed over the dopant layer to selectively expose portions... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200592 - Semiconductor device: A semiconductor device includes: a first source region and a first drain region formed at a distance from each other in a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate between the first source region and the first drain region; a first gate electrode formed on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090200593 - Semiconductor device having mos-transistor formed on semiconductor substrate and method for manufacturing thereof: A semiconductor device comprises MOS transistors sequentially arranged in the plane direction of a substrate, wherein a gate electrode and a wiring portion for connecting between the gate electrodes to each other are implanted into a layer that is lower than a surface of the substrate in which a diffusion... Agent: Young & Thompson

20090200596 - Fabrication method and structure for providing a recessed channel in a nonvolatile memory device: A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially... Agent: Volentine & Whitt PLLC

20090200594 - Nonvolatile semiconductor memory device and method of manufacturing the same: A nonvolatile semiconductor memory device has: a semiconductor substrate; a control gate and a floating gate that are formed side by side on a gate insulating film on a channel region in the semiconductor substrate; and an erase gate facing an upper surface of the floating gate. Side surfaces of... Agent: Foley And Lardner LLP Suite 500

20090200595 - Nonvolatile semiconductor memory device and method of manufacturing the same: A nonvolatile semiconductor memory device has: a semiconductor substrate; a control gate and a floating gate that are formed side by side on a gate insulating film on a channel region in the semiconductor substrate; an erase gate facing an upper surface of the floating gate; a first device isolation... Agent: Foley And Lardner LLP Suite 500

20090200597 - Split-gate nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a floating gate; an erasing gat; and a control gate. The floating gate is provided on a channel region of a semiconductor substrate through a first insulating layer. The erasing gate is provided on the floating gate through a second insulating layer. The control... Agent: Foley And Lardner LLP Suite 500

20090200598 - Flash memory structure with enhanced capacitive coupling coefficient ratio (cccr) and method for fabrication thereof: A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure... Agent: Scully, Scott, Murphy & Presser, P.C.

20090200600 - Nonvolatile semiconductor memory device and method of manufacturing the same: A nonvolatile semiconductor memory device has: a semiconductor substrate; a control gate and a floating gate that are formed side by side on a gate insulating film on a channel region in the semiconductor substrate; and an erase gate facing an upper surface of the floating gate and totally located... Agent: Foley And Lardner LLP Suite 500

20090200599 - U-shaped sonos memory having an elevated source and drain: A semiconductor device and a method for manufacturing thereof are provided. The semiconductor device includes two epitaxial semiconductor layers formed on a semiconductor substrate, bit lines formed on upper portions of the two epitaxial semiconductor layers, and a charge storage layer formed on the semiconductor substrate between the two epitaxial... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090200602 - Combined volatile and non-volatile memory device with graded composition insulator stack: A memory device is fabricated with a graded composition tunnel insulator layer. This layer is formed over a substrate with a drain and a source region. The tunnel insulator is comprised of a graded SiC—GeC—SiC composition. A charge blocking layer is formed over the tunnel insulator. A trapping layer of... Agent: Leffert Jay & Polglaze, P.A.

20090200601 - Embedded trap direct tunnel non-volatile memory: The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over the oxynitride layer. An injector layer is formed over the embedded trap layer. A high dielectric constant layer is formed over the... Agent: Leffert Jay & Polglaze, P.A.

20090200603 - High density vertical structure nitride flash memory: A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories. Array implementations for high-density... Agent: Saile Ackerman LLC

20090200604 - Vertical fin-fet mos devices: A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates... Agent: International Business Machines Corporation Dept. 18g

20090200605 - Metal-oxide-semiconductor device including an energy filter: A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from... Agent: Ryan, Mason & Lewis, LLP

20090200606 - Power device edge termination having a resistor with one end biased to source voltage: A field effect transistor (FET) includes a source electrode for receiving an externally-provided source voltage. The FET further includes an active region and a termination region surrounding the active region. A resistive element is coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an... Agent: Townsend And Townsend And Crew, LLP

20090200607 - Power mosfet: A power MOSFET of the invention includes a cell region in which a plurality of cells constituted of a transistor having a gate electrode formed in a trench is aligned, the plurality of cells being arranged to form a square grid and a gate interconnect lead formed so as to... Agent: Young & Thompson

20090200608 - Semiconductor device: To attain reduction in size of a semiconductor device having a power transistor and an SBD, a semiconductor device according to the present invention comprises a first region and a second region formed on a main surface of a semiconductor substrate; plural first conductors and plural second conductors formed in... Agent: Miles & Stockbridge PC

20090200611 - Semiconductor device and a method for manufacturing the same: A thin film transistor of the present invention has an active layer including at least source, drain and channel regions formed on an insulating surface. A high resistivity region is formed between the channel region and each of the source and drain regions. A film capable of trapping positive charges... Agent: Fish & Richardson P.C.

20090200610 - Semiconductor device and manufacturing method thereof: An N− layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N− layer, a trench isolation region is formed to surround the N− layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of... Agent: Mcdermott Will & Emery LLP

20090200609 - Semiconductor device, electro-optical device, electronic apparatus, method for manufacturing semiconductor device, method for manufacturing electro-optical device, and method for manufacturing electronic apparatus: The invention provides, as an aspect thereof, a semiconductor device that includes: a substrate; an underlying insulation film that is formed over the substrate; and a plurality of thin-film transistors that is formed over the underlying insulation film, each of the plurality of thin-film transistors having a semiconductor film, wherein... Agent: Harness, Dickey & Pierce, P.L.C

20090200612 - Integrated circuit having memory cells including gate material having high work function, and method of manufacturing same: An integrated circuit device (e.g., a logic or memory device) having a memory section including a plurality of memory cells, wherein each memory cell thereof includes at least one n-channel transistor having a gate, gate dielectric and first, second and body regions, wherein the gate of the at least one... Agent: Neil Steinberg

20090200613 - Semiconductor device: A transistor having a perpendicular channel direction and a transistor having a parallel channel direction are combined to cancel out stress-induced change in a characteristic value, providing a semiconductor device whose shift in characteristic value is small. Consequently, a channel that runs in a direction perpendicular to one side of... Agent: Brinks Hofer Gilson & Lione/seiko Instruments Inc.

20090200614 - Transistors, semiconductor devices, assemblies and constructions: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the... Agent: Wells St. John P.s.

20090200616 - Semiconductor device: According to one embodiment, it is possible to provide a semiconductor device provided with an MIS transistor which has an effective work function being, as much as possible, suitable for low threshold operation. A CMIS device provided with an electrode having an optimal effective work function and enabling low threshold... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090200615 - Semiconductor device and manufacturing method thereof: An element larger than silicon is ion-implanted to a contact liner in an N-channel region to break constituent atoms of the contact liner in the N-channel region. An element larger than silicon is ion-implanted to the contact liner in a P-channel region to break constituent atoms of the contact liner,... Agent: Mcdermott Will & Emery LLP

20090200617 - Semiconductor integrated circuit: Logic LSI includes first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4. The thick-film power switches are formed by thick-film power transistors manufactured in a process common to external input/output circuits I/O. The first power domains include second power domains... Agent: Miles & Stockbridge PC

20090200618 - Method of making transistor gates with controlled work function: Embodiments of the invention provide methods for making an integrated circuit comprising providing a substrate, forming a structured layer stack on the substrate comprising a dielectric layer located on the substrate and an oxide-free metallic layer located on the dielectric layer, wherein the metallic layer comprising a transition metal. The... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090200619 - Systems and methods for mems device fabrication: Systems and methods for MEMS device fabrication. A layer of photoresist is formed on a substrate. A first region of the substrate is exposed to a radiation source through a photomask. The first region of exposed photoresist is developed with a developer solution in order to etch the exposed regions... Agent: Honeywell International Inc. Patent Services

20090200620 - Mems transducer and manufacturing method therefor: An MEMS transducer is constituted of a diaphragm, a plate, a support structure for supporting the diaphragm and the plate with a gap layer surrounded by an interior wall, an electrode film (e.g. a pad conductive film) for covering a contact hole formed in the support structure, and a protective... Agent: Pillsbury Winthrop Shaw Pittman LLP

20090200621 - Photodiode chip having a high limit frequency: The invention relates to a photodiode chip which has a great limit frequency and a junction from the active photodiode area of a photodiode mesa to the output pad of the high-frequency output of the photodiode chip. The aim of the invention is to further increase the bandwidth factor of... Agent: Nutter Mcclennen & Fish LLP

20090200625 - Backside illuminated image sensor having deep light reflective trenches: An array of pixels is formed using a substrate having a frontside and a backside that is for receiving incident light. Each pixel typically includes metallization layers included in the frontside of the substrate, a photosensitive region formed in the backside of the substrate, and a trench formed around the... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200626 - Backside illuminated imaging sensor with vertical pixel sensor: A backside illuminated imaging sensor includes a vertical stacked sensor that reduces cross talk by using different silicon layers to form photodiodes at separate levels within a stack (or separate stacks) to detect different colors. Blue light-, green light-, and red light-detection silicon layers are formed, with the blue light... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200624 - Circuit and photo sensor overlap for backside illumination image sensor: A backside illuminated (“BSI”) imaging sensor pixel includes a photodiode region and pixel circuitry. The photodiode region is disposed within a semiconductor die for accumulating an image charge in response to light incident upon a backside of the BSI imaging sensor pixel. The pixel circuitry includes transistor pixel circuitry disposed... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200627 - Image sensor with high conversion efficiency: An image sensor includes a photoelectric converter, a reflector, and a charge carrier guiding region. The reflector is disposed under the photoelectric converter, and the charge carrier guiding region is disposed between the photoelectric converter and the reflector. The reflector reflects incident light passed by the photoelectric converter back through... Agent: Law Office Of Monica H Choi

20090200623 - Image sensor with micro-lenses of varying focal lengths: An image sensor having a plurality of micro-lenses disposed on a semiconductor substrate. A first micro-lens has a different focal length, height, shape, curvature, thickness, etc., than a second micro-lens. The image sensor may be back side illuminated or front side illuminated.... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200628 - Reduced imager crosstalk and pixel noise using extended buried contacts: Methods and structures to reduce the occurrence of crosstalk and pixel noise in solid state imager arrays. In an exemplary embodiment, a section of a layer patterned to form polysilicon buried-contacts in the pixel structure is also patterned to be disposed over the active, photosensor portion of the pixel. The... Agent: Dickstein Shapiro LLP

20090200622 - Self-aligned filter for an image sensor: An image sensor includes at least one photosensitive element disposed in a semiconductor substrate. Metal conductors may be disposed on the semiconductor substrate. A filter may be disposed between at least two individual metal conductors and a micro-lens may be disposed on the filter. There may be insulator material disposed... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200629 - Semiconductor device and manufacturing method therefor: A semiconductor device which includes a semiconductor chip formed with a light-reception area, a spacer, and a transparent substrate. The spacer is bonded to the semiconductor chip via a first adhesive and surrounding the light-reception area. The transparent substrate is bonded to the spacer via a second adhesive and disposed... Agent: Sonnenschein Nath & Rosenthal LLP

20090200630 - Solid-state image pickup device and method for manufacturing the same: A solid-state image pickup device which includes a solid-state image pickup chip, a transparent plate disposed to face a light-receiving surface of the solid-state image pickup chip, a frame-like spacer disposed on a peripheral portion of the light-receiving surface of the solid-state image pickup chip for maintaining a space between... Agent: Staas & Halsey LLP

20090200631 - Backside illuminated imaging sensor with light attenuating layer: A backside illuminated imaging sensor includes a semiconductor substrate, a metal interconnect layer and a light attenuating layer. The semiconductor substrate has a front surface, a back surface, and includes at least one imaging pixel formed on the front surface of the semiconductor substrate. The metal interconnect layer is electrically... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200632 - Image sensor having through via: One embodiment exemplarily described herein can be characterized as an image sensor including a substrate having a front surface and a rear surface; a photoelectric converting portion on the front surface of the substrate; a through via extending through the substrate, wherein the through via is electrically connected to the... Agent: Marger Johnson & Mccollom, P.C.

20090200633 - Semiconductor structures with dual isolation structures, methods for forming same and systems including same: A semiconductor structure with dual isolation structures is disclosed. The semiconductor structure may include a protruding isolation structure in a pixel array region of a substrate and an embedded isolation structure in a peripheral device region of the same substrate. A region of the protruding isolation structure extends from an... Agent: Trask Britt, P.C./ Micron Technology

20090200634 - Multi-angle rotation for ion implantation of trenches in superjunction devices: A method of manufacturing a semiconductor device includes providing a semiconductor wafer and forming at least one first trench in the wafer having first and second sidewalls and a first orientation on the wafer. The first sidewall of the at least one first trench is implanted with a dopant of... Agent: Panitch Schwarze Belisario & Nadel LLP

20090200635 - Integrated circuit having electrical isolation regions, mask technology and method of manufacturing same: An integrated circuit device (e.g., a logic or memory device) having a plurality of memory cells each including at least one transistor, wherein transistors of neighboring memory cells are separated by isolation regions. The isolation regions include a first liner layer, a barrier layer disposed on or over the first... Agent: Neil Steinberg

20090200636 - Sub-lithographic dimensioned air gap formation and related structure: Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at... Agent: Hoffman Warnick LLC

20090200637 - Methods and devices for a high-k stacked capacitor: An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend dielectric layer of an integrated circuit and depositing multiple layers of metal, each layer of metal electrically tied to an associated electrode. The method also includes alternately... Agent: Texas Instruments Incorporated

20090200638 - Mim capacitor integration: An integrated metal-insulator-metal capacitor is formed so that there is an extension portion of its top plate that does not face any portion of the bottom plate, and an extension portion of its bottom plate that does not face any portion of the top plate. Vias connecting the MIM capacitor... Agent: Freescale Semiconductor, Inc. Law Department

20090200639 - Package substrate with built-in capacitor and manufacturing method thereof: When a package substrate with a built-in capacitor includes a first thin-film small electrode 41aa and a second thin-film small electrode 42aa that are electrically short-circuited to each other via a pinhole P in a high-dielectric layer 43, a power supply post 61a and a via hole 61b are not... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090200640 - Variable resistive element, and its manufacturing method: A variable resistive element comprising a configuration that an area of an electrically contributing region of a variable resistor body is finer than that constrained by an upper electrode or a lower electrode and its manufacturing method are provided. A bump electrode material is formed on a lower electrode arranged... Agent: Nixon & Vanderhye, PC

20090200641 - Semiconductor device and method of manufacturing the same: The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090200642 - Highly tunable metal-on-semiconductor trench varactor: An array of deep trenches is formed in a doped portion of the semiconductor substrate, which forms a lower electrode. A dielectric layer is formed on the sidewalls of the array of deep trenches. The array of deep trenches is filled with a doped semiconductor material to form an upper... Agent: Scully, Scott, Murphy & Presser, P.C.

20090200643 - Semiconductor and method for producing the same: A method for producing a semiconductor by conducting superimposed doping of a plurality of dopants in a semiconductor substrate, which includes evaporating a (2×n) structure by a first dopant and forming its thin line structure on the substrate, then bringing the semiconductor substrate to a temperature capable of epitaxial growth,... Agent: Wenderoth, Lind & Ponack, L.L.P.

20090200644 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device includes a semiconductor layer, an electrode connected to the semiconductor layer, a sacrificial metal layer connected to the electrode and made of a metal having higher ionization tendency than the material of the semiconductor layer and the material of the electrode.... Agent: Leydig Voit & Mayer, Ltd

20090200645 - Semiconductor electronic device: A semiconductor electronic device comprises a substrate; a buffer layer formed on the substrate, the buffer layer including not less than two layers of composite layer in which a first semiconductor layer formed of a nitride-based compound semiconductor layer having a lattice constant smaller than a lattice constant of the... Agent: Turocy & Watson, LLP

20090200646 - One-dimensional arrays of block copolymer cylinders and applications thereof: Methods for fabricating sublithographic, nanoscale microstructures in one-dimensional arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.... Agent: Whyte Hirschboeck Dudek S.c. Intellectual Property Department

20090200648 - Embedded die system and method: A method and system is disclosed for facilitating miniaturization of an electronic device by efficiently utilizing available space. Specifically, in an exemplary embodiment, there is provided an electronic device comprising a substrate, a cavity formed in the substrate, and a bridge coupled to the substrate such that it spans the... Agent: Apple Inc. C/o Fletcher Yoder, PC

20090200647 - Shielded integrated circuit pad structure: An integrated circuit pad structure includes a ground strip (206) positioned below a pad (101). In one example a conductive element (102) is coupled to the pad (101), and at least two tiled layers, positioned below the first conductive element (102) and positioned above the ground strip (206) are included.... Agent: Vedder Price P.C. Joseph T. Cygan

20090200649 - Semiconductor device and manufacturing method of the same: A wire short-circuit defect during molding is prevented. A semiconductor device has a tab, a plurality of leads arranged around the tab, a semiconductor chip mounted over the tab, a plurality of wires electrically connecting the electrode pads of the semiconductor chip with the leads, and a molded body in... Agent: Mattingly & Malur, P.C.

20090200650 - Integrated circuit package and a method of making: An integrated circuit package includes a substrate and a first semiconductor chip. The first semiconductor chip is provided in a cavity on a first side of the substrate. The package further includes a second semiconductor chip provided on a second side of the substrate. The first semiconductor chip and the... Agent: Dicke, Billig & Czaja

20090200651 - Multi-chip package: A multi-chip package structure is provided with a first chip, a substrate adjacent to the first chip, a plurality of contacts connecting the first chip and the substrate, a second chip disposed between the first chip and the substrate and connecting to the first chip, and a underfill film, wherein... Agent: Jianq Chyun Intellectual Property Office

20090200653 - Memory modules and systems including the same: Provided is a memory module. The memory module may include a mounting substrate including a plurality of first substrate pads disposed on a top surface of the mounting substrate, a first semiconductor package disposed on a top surface of the mounting substrate, the first semiconductor package having a first frame... Agent: F. Chau & Associates, LLC

20090200652 - Method for stacking chips in a multi-chip package: A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090200654 - Method of electrically connecting a microelectronic component: A microelectronic assembly is provided which can include an element including a first dielectric layer and a second dielectric layer overlying the first dielectric layer, the second dielectric layer having an exposed surface defining an exposed major surface of the element. A plurality of substantially rigid metal posts can project... Agent: Tessera Lerner David Et Al.

20090200655 - Method of electrically connecting a microelectronic component: A microelectronic unit can include a support structure including a dielectric having oppositely-directed first and second surfaces. A plurality of substantially rigid posts can protrude parallel to one another in a direction beyond the first surface of the support structure. Each post may have a top surface remote from the... Agent: Tessera Lerner David Et Al.

20090200656 - Semiconductor device and manufacturing method thereof: There are constituted by a tab (1b) on which a semiconductor chip (2) is mounted, a sealing portion (3) formed by resin-sealing the semiconductor chip (2), a plurality of leads (1a) each having a mounted surface (1d) exposed to a peripheral portion of a rear surface (3a) of the sealing... Agent: Miles & Stockbridge PC

20090200657 - 3d smart power module: A 3D smart power module for power control, such as a three phase power control module, includes a two sided printed circuit (PC) board with power semiconductor devices attached to one side and control semiconductor devices attached to the other side. The power semiconductor devices are die bonded to a... Agent: Hiscock & Barclay, LLP

20090200658 - Circuit board structure embedded with semiconductor chips: A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric... Agent: Sawyer Law Group LLP

20090200659 - Chip package with channel stiffener frame: Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first... Agent: Timothy M Honeycutt Attorney At Law

20090200660 - Heatplates for heatsink attachment for semiconductor chips: An apparatus for heatsink attachment and a method for forming the apparatus. The apparatus includes a substrate, a semiconductor chip on top of and physically attached to the substrate, and a lid on top of the substrate. The lid includes a first thermally conductive material. The apparatus further includes a... Agent: Schmeiser, Olsen & Watts

20090200661 - Devices with faraday cages and internal flexibility sipes: A computer or microchip comprising an outer chamber and at least one inner chamber inside the outer chamber. The outer chamber and the inner chamber being separated at least in part by an internal sipe, and at least a portion of a surface of the outer chamber forming at least... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090200662 - Semiconductor package and method of making the same: The present invention relates to semiconductor devices comprising two or more dies stacked vertically on top of one another, and methods of making the semiconductor devices. The methods may comprise a combination of wafer-level through silicon interconnect fabrication and wafer-level assembly processes.... Agent: Sughrue Mion, PLLC

20090200664 - Manufacturing method of semiconductor apparatus and semiconductor apparatus: A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090200663 - Polymer and solder pillars for connecting chip and carrier: A method of connecting chips to chip carriers, ceramic packages, etc. (package substrates) forms smaller than usual first solder balls and polymer pillars on the surface of a semiconductor chip and applies adhesive to the distal ends of the polymer pillars. The method also forms second solder balls, which are... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090200665 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor construction assembly having a semiconductor substrate which has first and second surfaces, and has an integrated circuit element formed on the first surface, a plurality of connection pads which are connected to the integrated circuit element, a protective layer which covers the semiconductor substrate... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090200666 - Semiconductor integrated circuit device: A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner... Agent: Fitzpatrick Cella Harper & Scinto

20090200667 - Ohmic contact film in semiconductor device: The invention provides an ohmic contact film formed between a doped semiconductor material layer and a conductive material layer of a semiconductor device. The composition of the ohmic contact film according to a preferred embodiment of the invention is represented by the general formula MxQzNy, where M represents the II... Agent: Birch Stewart Kolasch & Birch

20090200669 - Enhanced interconnect structure: The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can be either partially embedded in the cap layer or completely embedded in the capping... Agent: International Business Machines Corporation Dept. 18g

20090200668 - Interconnect structure with high leakage resistance: An interconnect structure is provided in which the conductive feature (i.e., conductive material) is not coplanar with the upper surface of the dielectric material, but instead the conductive material is recessed below an upper surface of the dielectric material. In addition to being recessed below the upper surface of the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090200672 - Method for manufacturing semiconductor device: Disclosed is a method for manufacturing a semiconductor device. This method includes the step of forming a diffusion barrier film, which is interposed between a silicon film and a metal film and functions to prevent diffusion between the silicon and metal films. The diffusion barrier film is formed of a... Agent: Ladas & Parry LLP

20090200670 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090200671 - Sip semiconductor device and method for manufacturing the same: A System In Package (SIP) semiconductor device and a method for manufacturing a SIP device. A TiSiN film may be used as a diffusion barrier film for metal wiring in a SIP semiconductor device. A TiSiN film may provide relatively good step coverage in a relatively easy formation process, which... Agent: Sherr & Vaughn, PLLC

20090200673 - Via bottom contact and method of manufacturing same: A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via... Agent: Greenblum & Bernstein, P.L.C

20090200675 - Passivated copper chip pads: A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in... Agent: Slater & Matsil LLP

20090200676 - Semiconductor device: A semiconductor device which includes a first wiring with a via connected to the first wiring, a second wiring connected to the via and a dummy via disposed adjacent to the via at a distance of 100 nm or less and formed on the same layer as the via.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090200677 - Semiconductor device: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near... Agent: Mcdermott Will & Emery LLP

20090200674 - Structure and method of forming transitional contacts between wide and thin beol wirings: A structure and method of forming a conducting via for connecting two back end of the line (BEOL) metal wiring levels is described. The method includes forming a first interconnect structure having a first dimensional width in a first dielectric layer; depositing a second dielectric layer over said first dielectric... Agent: International Business Machines Corporation Dept. 18g

20090200678 - Device comprising multi-layered thin film having excellent adhesive strength and method for fabricating the same: A device comprises a multi-layered thin film having excellent adhesion due to the method of fabricating the same. More particularly, the device includes a multi-layered thin film consisting of a tantalum nitride layer, a tantalum layer formed on the tantalum nitride layer, and a gold thin film formed on the... Agent: Robert E. Bushnell & Law Firm

20090200681 - Forming compliant contact pads for semiconductor packages: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and... Agent: Trop, Pruner & Hu, P.C.

20090200679 - Semiconductor apparatus and method for manufacturing the same: A semiconductor apparatus including a semiconductor substrate, an insulating layer, a via hole, and a through-hole interconnection is provided. The insulating layer is formed on the semiconductor substrate. The via hole is formed through the semiconductor substrate and the insulating layer. The through-hole interconnection has a conductive layer formed on... Agent: Sonnenschein Nath & Rosenthal LLP

20090200680 - Semiconductor device: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board... Agent: Miles & Stockbridge PC

20090200683 - Interconnect structures with partially self aligned vias and methods to produce same: An interconnect structure having partially self aligned vias with an interlayer dielectric layer on a substrate, containing at least two conducting metal lines that traverse parallel to the substrate and at least two conducting metal vias that are orthogonal to the substrate. A method of producing the self aligned vias... Agent: Nugent & Smith, LLP

20090200682 - Via in via circuit board structure: Methods, systems, and apparatuses for electrical connections through circuit boards are described. A via-in-via structure in a circuit board provides two electrical signal paths. The circuit board includes a dielectric layer having opposing first and second planar surfaces. A first opening extends through the dielectric layer. An electrically conductive coating... Agent: Fiala & Weaver, P.l.l.c. C/o Cpa Global

20090200684 - Flip chip package with shelf and method of manufactguring there of: The semiconductor device according to the present invention has a planar semiconductor chip having projecting connection terminals provided on one surface thereof. A shelf is provided where a peripheral edge of a surface of the semiconductor chip opposite one surface thereof onto which connection terminals are provided is removed. This... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090200685 - Electronic packaging method and apparatus: The present invention utilizes a panel substrate as the packaging substrate carried by a working susceptor. Packaging devices are hung in the nearby of the working susceptor and moved by robot arms to the working susceptor, whereby the problems of substrate warpage and substrate transportation are overcome. Further, identical or... Agent: Eschweiler & Associates LLC National City Bank Building

20090200686 - Electrical connecting structure and bonding structure: A electrical connecting structure including a conductive pad, a polymer bump and a patterned conductive layer is provided. The conductive pad is on a substrate and the polymer bump is disposed over the substrate. The patterned conductive layer is disposed on the polymer bump and electrically connects to the conductive... Agent: Jianq Chyun Intellectual Property Office

20090200533 - Resistive memory element and method of fabrication: An integrated circuit including a memory cell and a method of manufacturing the integrated circuit are described. The memory cell includes a buried gate select transistor and a resistive memory element coupled to the buried gate select transistor. The resistive memory element stores information based on a resistivity of the... Agent: Ira S. Matsil Slater & Matsil, L.L.P.

20090200534 - Method for fabrication of polycrystalline diodes for resistive memories: The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing... Agent: Scully, Scott, Murphy & Presser, P.C.

20090200535 - Non-volatile memory element with improved temperature stability: An integrated circuit including a memory element is described. The memory element includes a solid electrolyte layer that includes a matrix material having a metal dissolved therein, and a dopant distributed in the matrix material, the dopant competing with the metal to bind with elements of the matrix material at... Agent: Slater & Matsil, L.L.P.

20090200536 - Method for manufacturing an electric device with a layer of conductive material contracted by nanowire: The electric device (100) according to the invention comprises a layer (107) of a memory material which has an electrical resistivity switchable between a first value and a second value. The memory material may be a phase change material. The electric device (100) further comprises a set of nanowires (NW)... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090200537 - Phase change memory device preventing contact loss and method for manufacturing the same: A phase change memory device includes a silicon substrate having a phase change cell region. A plurality of phase change cell are formed in the phase change region of the silicon substrate. A contact comprising a first contact and a second contact is formed on each of the phase change... Agent: Ladas & Parry LLP

20090200539 - Composite nanorod-based structures for generating electricity: Composite nanorod-based structures for generating electricity are disclosed. One embodiment is an article of manufacture that includes a first layer with an array of nanowires and a dielectric material. The nanowires include: a core semiconducting region with a first type of doping; a shell semiconducting region with a second type... Agent: Morgan, Lewis & Bockius, LLP. (pa)

20090200538 - Group lll-v compound semiconductor and a method for producing the same: A Group III-V compound semiconductor includes an n-type layer, a p-type layer, a p-type layer represented by a formula InaGabAlcN, having a thickness of not less than 300 nm, and a multiple quantum well structure which exists between the n-type layer and the p-type layer, has at least two quantum... Agent: Fitch, Even, Tabin & Flannery

20090200540 - Metal-oxide-semiconductor device including a multiple-layer energy filter: A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from... Agent: Ryan, Mason & Lewis, LLP

20090200541 - Making a structure: A structure includes a surface and a non-equilibrium two-dimensional semiconductor micro structure on the surface.... Agent: Hewlett Packard Company

20090200542 - Compounds and organic light emitting device using the same: Disclosed is an organic light emitting device. The organic light emitting device comprises a first electrode, organic material layer(s) comprising a light emitting layer, and a second electrode. The first electrode, the organic material layer(s), and the second electrode form layered structure and at least one layer of the organic... Agent: Mckenna Long & Aldridge LLP

20090200543 - Method of forming an electronic device on a substrate supported by a carrier and resultant device: A method for forming an electronic device on a flexible substrate conditions the surface of a carrier to form a holding area for retaining the flexible substrate. A contact surface of the flexible substrate is applied against the carrier with an intermediate binding material applied between at least the holding... Agent: Carestream Health, Inc.

20090200544 - Organic light emitting device and method of manufacturing the same: An organic light emitting device includes first, second, and third pixels each displaying a different color. Each pixel includes a first electrode, a second electrode facing the first electrode, and an emission layer between the first and second electrodes. The first electrodes of the first and second pixels respectively include... Agent: H.c. Park & Associates, PLC

20090200545 - Zno-based semiconductor device: Provided is a ZnO-based semiconductor device capable of growing a flat ZnO-based semiconductor layer on an MgZnO substrate having a main surface on the lamination side oriented in a c-axis direction. ZnO-based semiconductor layers 2 to 6 are epitaxially grown on an MgxZn1-xO (0≦x≦1) substrate 1 having a +C surface... Agent: Rabin & Berdo, PC

20090200548 - Guard ring extension to prevent realiability failures: An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090200549 - Semiconductor device: A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first seal ring. The first seal ring comprises a first monitor circuit isolated by a first dielectric layer embedded in... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090200546 - Test structures and methods: Test structures and methods for semiconductor devices, lithography systems, and lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a lithography mask, the lithography mask including a... Agent: Slater & Matsil LLP

20090200547 - Trench depth monitor for semiconductor manufacturing: A method of manufacturing a semiconductor wafer having at least one device trench extending to a first depth position includes providing a semiconductor substrate having first and second main surfaces and a semiconductor material layer having first and second main surfaces disposed on the first main surface of the semiconductor... Agent: Panitch Schwarze Belisario & Nadel LLP

20090200550 - Method for forming an electronic device on a flexible substrate supported by a detachable carrier: A method for forming an electronic device provides a carrier formed from a composite material comprising a plastic binder and an embedded material. A substrate material is attached to the carrier. The substrate is processed to form the electronic device thereon. The substrate is then detached from the carrier to... Agent: Carestream Health, Inc.

20090200553 - High temperature thin film transistor on soda lime glass: The present invention generally comprises a low cost TFT and a method of manufacturing a TFT. For TFTs, soda lime glass would be an attractive alternative to non-alkali glass, but a soda lime glass substrate will permit sodium to diffuse into the active layer and degrade the performance of the... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090200551 - Microcrystalline silicon thin film transistor: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a first gas mixture having a hydrogen containing gas to a silicon containing gas flow... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090200552 - Microcrystalline silicon thin film transistor: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a gas mixture having a hydrogen-based gas, a silicon-based gas and an argon gas into... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090200554 - Display device and method of manufacturing the same: The display device includes a substrate, a thin film transistor (TFT), which includes a gate electrode, a semiconductor layer, and source and drain electrodes, on the substrate member, a passivation layer on the TFT and having an opening to expose a portion of the drain electrode, and a pixel electrode... Agent: H.c. Park & Associates, PLC

20090200556 - Thin film transistor panel for multi-domain liquid crystal display: A thin film transistor array panel is provided, which includes: an insulating substrate; a plurality of first signal lines formed on the insulating substrate; a plurality of second signal lines formed on the insulating substrate and intersecting the first wire in an insulating manner; a pixel electrode formed in a... Agent: F. Chau & Associates, LLC

20090200555 - Thin film transistor substrate, defect repairing method therefor, and display device: A thin film transistor substrate includes: a substrate; a thin film transistor and a capacitor formed on the substrate; and a protective film for protecting an electrode on a back surface side of the capacitor when an electrode on a front surface side of the capacitor is cut by irradiation... Agent: Rader Fishman & Grauer PLLC

20090200557 - Semiconductor device: A semiconductor device includes a semiconductor layer including a channel region, and a first region and a second region to which an impurity element is introduced to make the first region and the second region a source and a drain, a third region, and a gate electrode provided to partly... Agent: Eric Robinson

20090200558 - Method and apparatus of fabricating liquid crystal display device: A method and an apparatus of fabricating a liquid crystal display device adapted to improve a lift-off efficiency are disclosed. The liquid crystal display device is also disclosed. The method includes forming a first thin film on a substrate; forming a photo-resist pattern on the first thin film; etching the... Agent: Mckenna Long & Aldridge LLP

20090200559 - Silicon carbide semiconductor device including deep layer: A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench penetrating the source region and the base region to the drift layer, a... Agent: Posz Law Group, PLC

20090200560 - Light emitting device and method of forming the same: An embodiment of present invention discloses a light-emitting device comprising a first multi-layer structure comprising a first lower layer; a first upper layer; and a first active layer able to emit light under a bias voltage and positioned between the first lower layer and the first upper layer; a second... Agent: Bacon & Thomas, PLLC

20090200561 - Composite phosphors based on coating porous substrates: A composite material is provided including a phosphor material of at least one of among hafnium oxide, niobium oxide, tantalum oxide or zirconium oxide as a conformal coating on a porous substrate, the composite characterized as exhibiting photoluminescence at room temperature. Also provided is a composite material including a phosphor... Agent: Los Alamos National Security, LLC

20090200562 - Integrated circuit die, integrated circuit package, and packaging method: An integrated circuit package includes an integrated circuit die 1 having a plurality of optical elements 5 sensitive to and/or capable of generating light, whereby data communication to circuitry of the integrated circuit die can be effected using a data channels implemented using the plurality of elements. The data channels... Agent: Freescale Semiconductor, Inc. Law Department

20090200563 - Group iii nitride semiconductor light-emitting device and production method therefor: Provided is a method for producing a Group III nitride semiconductor light-emitting device including a GaN substrate serving as a growth substrate, which method facilitates tapering of a bottom portion of the GaN substrate. In the production method, firstly, a Group III nitride semiconductor layer, an ITO electrode, a p-electrode,... Agent: Mcginn Intellectual Property Law Group, PLLC

20090200564 - Method and structure for fabricating smooth mirrors for liquid crystal on silicon devices: A method for fabricating a liquid crystal on silicon display device. The method includes providing a substrate, e.g., silicon wafer. The method includes forming a transistor layer overlying the substrate. Preferably, the transistor layer has a plurality of MOS devices therein. The method includes forming an interlayer dielectric layer (e.g.,... Agent: Townsend And Townsend And Crew, LLP

20090200565 - Gan-based semiconductor light emitting device: There is provided a GaN-based semiconductor light emitting device including: a substrate; and an n-type GaN-based semiconductor layer, an active layer and a p-type GaN-based semiconductor layer sequentially deposited on the substrate, wherein the active layer includes: a first barrier layer including AlxInyGa1−x−yN, where 0<x<1, 0<y<1, and 0<x+y<1; a second... Agent: Mcdermott Will & Emery LLP

20090200567 - Chip-type led package and light emitting apparatus having the same: Disclosed are a chip-type LED package and a light emitting apparatus having the same. The chip-type LED package includes a thermally conductive substrate with lead electrodes formed thereon. An LED chip is mounted on the thermally conductive substrate, and a lower molding portion covers the LED chip. In addition, an... Agent: H.c. Park & Associates, PLC

20090200569 - Optoelectronic substrate and methods of making same: A method of producing an optoelectronic substrate by detaching a thin layer from a semi-conducting nitride substrate and transferring it to an auxiliary substrate to provide at least one semi-conducting nitride layer thereon, metallizing at least a portion of the surface of the auxiliary substrate that includes the transferred nitride... Agent: Winston & Strawn LLP Patent Department

20090200568 - Semiconductor light-emitting device: An etching process includes forming a metal-fluoride layer at least as a part of an etching mask formed over a semiconductor layer at a temperature of 150° C. or higher; patterning the metal-fluoride layer; and etching the semiconductor layer using the patterned metal-fluoride layer as a mask. Using this etching... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090200566 - Side-view light emitting diode package having a reflector: Disclosed herein is a side-view light emitting diode package with a reflector. The side-view light emitting diode package of the present invention comprises first and second lead terminals spaced apart from each other. The package body supports the first and second lead terminals and has an elongated opening through which... Agent: H.c. Park & Associates, PLC

20090200570 - Light emitting device mounting substrate, light emitting device housing package, light emitting apparatus, and illuminating apparatus: A light-emitting apparatus with improved dissipation efficiency of heat transmitted to a specific electrode of a light-emitting device is provided. A light-emitting device mounting substrate used for the light emitting apparatus include a base body (1) which mounts thereon a light-emitting device (3); a first electrically conductive path (L1) formed... Agent: Hogan & Hartson L.L.P.

20090200571 - Semiconductor light emitting device of junction-down type and semiconductor light emitting element of junction-down type: In a semiconductor light emitting device of junction-down type, a semiconductor light emitting element having a stripe part is provided with a bonding part for die bonding in a part of a surface thereof where the stripe part is formed, the bonding part being at a position away from the... Agent: Rabin & Berdo, PC

20090200572 - Lighting device and production method of the same: Bonding between a light-emitting element and electrodes of a substrate is ensured to enhance reliability of a lighting device. In the lighting device of the present invention, a material made of metal alkoxide or polymetalloxane generated from metal alkoxide is used as a coating material covering the light-emitting element. This... Agent: Bruce L. Adams, Esq Adams & Wilks

20090200573 - Light emitting element and manufacturing method thereof: In a laser chip 1 using a nitride semiconductor having a hexagonal crystal structure, the −c plane is used as a first resonator facet A, which is the side of the laser chip 1 through which light is emitted. On the first resonator facet A, that is, on the −c... Agent: Harness, Dickey & Pierce, P.L.C

20090200574 - Power semiconductor device: A power semiconductor device includes a first layer of a first conductivity type, which has a first main side and a second main side opposite the first main side. A second layer of a second conductivity type is arranged in a central region of the first main side and a... Agent: Buchanan, Ingersoll & Rooney PC

20090200575 - Semiconductor device: A semiconductor device is provided with a semiconductor region, a gate electrode, a source electrode and a drain electrode. The semiconductor region is formed on a semiconductor substrate surface and includes a first semiconductor portion of a first conducting type, a second semiconductor portion of a second conducting type, a... Agent: GlobalIPCounselors, LLP

20090200576 - Semiconductor device: A semiconductor device includes: a first semiconductor layer including AlXGa1-XN (0≦X≦1); a second semiconductor layer provided on the first semiconductor layer, including AlYGa1-YN (0≦Y≦1, X<Y), and having a larger bandgap than the first semiconductor layer; a source electrode provided on the second semiconductor layer; a drain electrode provided on the... Agent: Patterson & Sheridan, L.L.P.

20090200577 - Semiconductor device and method of manufacturing such a device: The invention relates to a semiconductor device with a substrate (11) and a semiconductor body (11) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) comprising a first, a second and a third connection conductor, which emitter region (1) comprises a... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090200578 - Self-repairing field effect transisitor: A self repairing field effect transistor (FET) device, in accordance with one embodiment, includes a plurality of FET cells each having a fuse link. The fuse links are adapted to blow during a high current event in a corresponding cell.... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20090200579 - Semiconductor device and layout method thereof: A semiconductor device includes first lines extending in a first direction and formed in a first wiring layer in a predetermined arrangement order, second lines formed in a second wiring layer different from the first wring layer in the predetermined arrangement order, and contacts electrically connecting between the first lines... Agent: Mcginn Intellectual Property Law Group, PLLC

20090200580 - Image sensor and pixel including a deep photodetector: What is disclosed is an apparatus comprising a transfer gate formed on a substrate and a photodiode formed in the substrate next to the transfer gate. The photodiode comprises a shallow N-type collector formed in the substrate, a deep N-type collector formed in the substrate, wherein a lateral side of... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200581 - High breakdown voltage double-gate semiconductor device: A double-gate semiconductor device provides a high breakdown voltage allowing for a large excursion of the output voltage that is useful for power applications. The double-gate semiconductor device may be considered a double-gate device including a MOS gate and a junction gate, in which the bias of the junction gate... Agent: Peters Verny , L.L.P.

20090200582 - Semiconductor device with an improved operating property: The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region... Agent: Mcdermott Will & Emery LLP

20090200583 - Feature patterning methods: Methods of patterning features of semiconductor devices and methods of processing and fabricating semiconductor devices are disclosed. In one embodiment, a method of processing a semiconductor device includes forming first sidewall spacers on a first hard mask, removing the first hard mask, and forming a first material layer over the... Agent: Slater & Matsil LLP

20090200585 - Backside illuminated imaging sensor with backside p+ doped layer: A backside illuminated imaging sensor includes a semiconductor layer having a P-type region. A frontside and backside P+ doped layers are formed within the semiconductor layer. An imaging pixel having a photodiode is formed within the semiconductor layer, where the photodiode is an N- region formed within the P-type region... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200589 - Backside illuminated imaging sensor with improved infrared sensitivity: A backside illuminated imaging sensor includes a semiconductor layer and an infrared detecting layer. The semiconductor layer has a front surface and a back surface. An imaging pixel includes a photodiode region formed within the semiconductor layer. The infrared detecting layer is disposed above the front surface of the semiconductor... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200588 - Backside illuminated imaging sensor with light reflecting transfer gate: A backside illuminated imaging sensor includes a semiconductor having an imaging pixel that can include a photodiode region, an insulation layer, and a reflective layer. The photodiode is typically formed in the frontside of the semiconductor substrate. A surface shield layer can be formed on the frontside of the photodiode... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200586 - Backside illuminated imaging sensor with silicide light reflecting layer: A backside illuminated imaging sensor includes a semiconductor layer, a metal interconnect layer and a silicide light reflecting layer. The semiconductor layer has a front surface and a back surface. An imaging pixel that includes a photodiode region is formed within the semiconductor layer. The metal interconnect layer is electrically... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200584 - Full color cmos imager filter: A full color complementary metal oxide semiconductor (CMOS) imaging circuit is provided. The imaging circuit comprises an array of photodiodes including a plurality of pixel groups. Each pixel group supplies 3 electrical color signals, corresponding to 3 detectable colors. The circuit also includes a color filter array overlying the photodiode... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20090200591 - Image sensor with light receiving region having different potential energy according to wavelength of light and electronic product employing the same: There is provided a CMOS image sensor and an electronic product using the same. The CMOS image sensor includes a plurality of pixels for embodying colors having different wavelengths. Each of pixels includes a buried barrier layer disposed in a semiconductor substrate and having a barrier potential energy of a... Agent: Mills & Onello LLP

20090200590 - Image sensor with low electrical cross-talk: An array of pixels is formed using a substrate, where each pixel has a substrate having a backside and a frontside that includes metalization layers, a photodiode formed in the substrate, frontside P-wells formed using frontside processing that are adjacent to the photosensitive region, and an N-type region formed in... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200587 - Masked laser anneal during fabrication of backside illuminated image sensors: A technique for fabricating an array of imaging pixels includes fabricating front side components on a front side of the array. After fabricating the front side components, a dopant layer is implanted on a backside of the array. A mask is formed over the dopant layer to selectively expose portions... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200592 - Semiconductor device: A semiconductor device includes: a first source region and a first drain region formed at a distance from each other in a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate between the first source region and the first drain region; a first gate electrode formed on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090200593 - Semiconductor device having mos-transistor formed on semiconductor substrate and method for manufacturing thereof: A semiconductor device comprises MOS transistors sequentially arranged in the plane direction of a substrate, wherein a gate electrode and a wiring portion for connecting between the gate electrodes to each other are implanted into a layer that is lower than a surface of the substrate in which a diffusion... Agent: Young & Thompson

20090200596 - Fabrication method and structure for providing a recessed channel in a nonvolatile memory device: A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially... Agent: Volentine & Whitt PLLC

20090200594 - Nonvolatile semiconductor memory device and method of manufacturing the same: A nonvolatile semiconductor memory device has: a semiconductor substrate; a control gate and a floating gate that are formed side by side on a gate insulating film on a channel region in the semiconductor substrate; and an erase gate facing an upper surface of the floating gate. Side surfaces of... Agent: Foley And Lardner LLP Suite 500

20090200595 - Nonvolatile semiconductor memory device and method of manufacturing the same: A nonvolatile semiconductor memory device has: a semiconductor substrate; a control gate and a floating gate that are formed side by side on a gate insulating film on a channel region in the semiconductor substrate; an erase gate facing an upper surface of the floating gate; a first device isolation... Agent: Foley And Lardner LLP Suite 500

20090200597 - Split-gate nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a floating gate; an erasing gat; and a control gate. The floating gate is provided on a channel region of a semiconductor substrate through a first insulating layer. The erasing gate is provided on the floating gate through a second insulating layer. The control... Agent: Foley And Lardner LLP Suite 500

20090200598 - Flash memory structure with enhanced capacitive coupling coefficient ratio (cccr) and method for fabrication thereof: A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure... Agent: Scully, Scott, Murphy & Presser, P.C.

20090200600 - Nonvolatile semiconductor memory device and method of manufacturing the same: A nonvolatile semiconductor memory device has: a semiconductor substrate; a control gate and a floating gate that are formed side by side on a gate insulating film on a channel region in the semiconductor substrate; and an erase gate facing an upper surface of the floating gate and totally located... Agent: Foley And Lardner LLP Suite 500

20090200599 - U-shaped sonos memory having an elevated source and drain: A semiconductor device and a method for manufacturing thereof are provided. The semiconductor device includes two epitaxial semiconductor layers formed on a semiconductor substrate, bit lines formed on upper portions of the two epitaxial semiconductor layers, and a charge storage layer formed on the semiconductor substrate between the two epitaxial... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090200602 - Combined volatile and non-volatile memory device with graded composition insulator stack: A memory device is fabricated with a graded composition tunnel insulator layer. This layer is formed over a substrate with a drain and a source region. The tunnel insulator is comprised of a graded SiC—GeC—SiC composition. A charge blocking layer is formed over the tunnel insulator. A trapping layer of... Agent: Leffert Jay & Polglaze, P.A.

20090200601 - Embedded trap direct tunnel non-volatile memory: The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over the oxynitride layer. An injector layer is formed over the embedded trap layer. A high dielectric constant layer is formed over the... Agent: Leffert Jay & Polglaze, P.A.

20090200603 - High density vertical structure nitride flash memory: A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories. Array implementations for high-density... Agent: Saile Ackerman LLC

20090200604 - Vertical fin-fet mos devices: A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates... Agent: International Business Machines Corporation Dept. 18g

20090200605 - Metal-oxide-semiconductor device including an energy filter: A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from... Agent: Ryan, Mason & Lewis, LLP

20090200606 - Power device edge termination having a resistor with one end biased to source voltage: A field effect transistor (FET) includes a source electrode for receiving an externally-provided source voltage. The FET further includes an active region and a termination region surrounding the active region. A resistive element is coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an... Agent: Townsend And Townsend And Crew, LLP

20090200607 - Power mosfet: A power MOSFET of the invention includes a cell region in which a plurality of cells constituted of a transistor having a gate electrode formed in a trench is aligned, the plurality of cells being arranged to form a square grid and a gate interconnect lead formed so as to... Agent: Young & Thompson

20090200608 - Semiconductor device: To attain reduction in size of a semiconductor device having a power transistor and an SBD, a semiconductor device according to the present invention comprises a first region and a second region formed on a main surface of a semiconductor substrate; plural first conductors and plural second conductors formed in... Agent: Miles & Stockbridge PC

20090200611 - Semiconductor device and a method for manufacturing the same: A thin film transistor of the present invention has an active layer including at least source, drain and channel regions formed on an insulating surface. A high resistivity region is formed between the channel region and each of the source and drain regions. A film capable of trapping positive charges... Agent: Fish & Richardson P.C.

20090200610 - Semiconductor device and manufacturing method thereof: An N− layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N− layer, a trench isolation region is formed to surround the N− layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of... Agent: Mcdermott Will & Emery LLP

20090200609 - Semiconductor device, electro-optical device, electronic apparatus, method for manufacturing semiconductor device, method for manufacturing electro-optical device, and method for manufacturing electronic apparatus: The invention provides, as an aspect thereof, a semiconductor device that includes: a substrate; an underlying insulation film that is formed over the substrate; and a plurality of thin-film transistors that is formed over the underlying insulation film, each of the plurality of thin-film transistors having a semiconductor film, wherein... Agent: Harness, Dickey & Pierce, P.L.C

20090200612 - Integrated circuit having memory cells including gate material having high work function, and method of manufacturing same: An integrated circuit device (e.g., a logic or memory device) having a memory section including a plurality of memory cells, wherein each memory cell thereof includes at least one n-channel transistor having a gate, gate dielectric and first, second and body regions, wherein the gate of the at least one... Agent: Neil Steinberg

20090200613 - Semiconductor device: A transistor having a perpendicular channel direction and a transistor having a parallel channel direction are combined to cancel out stress-induced change in a characteristic value, providing a semiconductor device whose shift in characteristic value is small. Consequently, a channel that runs in a direction perpendicular to one side of... Agent: Brinks Hofer Gilson & Lione/seiko Instruments Inc.

20090200614 - Transistors, semiconductor devices, assemblies and constructions: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the... Agent: Wells St. John P.s.

20090200616 - Semiconductor device: According to one embodiment, it is possible to provide a semiconductor device provided with an MIS transistor which has an effective work function being, as much as possible, suitable for low threshold operation. A CMIS device provided with an electrode having an optimal effective work function and enabling low threshold... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090200615 - Semiconductor device and manufacturing method thereof: An element larger than silicon is ion-implanted to a contact liner in an N-channel region to break constituent atoms of the contact liner in the N-channel region. An element larger than silicon is ion-implanted to the contact liner in a P-channel region to break constituent atoms of the contact liner,... Agent: Mcdermott Will & Emery LLP

20090200617 - Semiconductor integrated circuit: Logic LSI includes first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4. The thick-film power switches are formed by thick-film power transistors manufactured in a process common to external input/output circuits I/O. The first power domains include second power domains... Agent: Miles & Stockbridge PC

20090200618 - Method of making transistor gates with controlled work function: Embodiments of the invention provide methods for making an integrated circuit comprising providing a substrate, forming a structured layer stack on the substrate comprising a dielectric layer located on the substrate and an oxide-free metallic layer located on the dielectric layer, wherein the metallic layer comprising a transition metal. The... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090200619 - Systems and methods for mems device fabrication: Systems and methods for MEMS device fabrication. A layer of photoresist is formed on a substrate. A first region of the substrate is exposed to a radiation source through a photomask. The first region of exposed photoresist is developed with a developer solution in order to etch the exposed regions... Agent: Honeywell International Inc. Patent Services

20090200620 - Mems transducer and manufacturing method therefor: An MEMS transducer is constituted of a diaphragm, a plate, a support structure for supporting the diaphragm and the plate with a gap layer surrounded by an interior wall, an electrode film (e.g. a pad conductive film) for covering a contact hole formed in the support structure, and a protective... Agent: Pillsbury Winthrop Shaw Pittman LLP

20090200621 - Photodiode chip having a high limit frequency: The invention relates to a photodiode chip which has a great limit frequency and a junction from the active photodiode area of a photodiode mesa to the output pad of the high-frequency output of the photodiode chip. The aim of the invention is to further increase the bandwidth factor of... Agent: Nutter Mcclennen & Fish LLP

20090200625 - Backside illuminated image sensor having deep light reflective trenches: An array of pixels is formed using a substrate having a frontside and a backside that is for receiving incident light. Each pixel typically includes metallization layers included in the frontside of the substrate, a photosensitive region formed in the backside of the substrate, and a trench formed around the... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200626 - Backside illuminated imaging sensor with vertical pixel sensor: A backside illuminated imaging sensor includes a vertical stacked sensor that reduces cross talk by using different silicon layers to form photodiodes at separate levels within a stack (or separate stacks) to detect different colors. Blue light-, green light-, and red light-detection silicon layers are formed, with the blue light... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200624 - Circuit and photo sensor overlap for backside illumination image sensor: A backside illuminated (“BSI”) imaging sensor pixel includes a photodiode region and pixel circuitry. The photodiode region is disposed within a semiconductor die for accumulating an image charge in response to light incident upon a backside of the BSI imaging sensor pixel. The pixel circuitry includes transistor pixel circuitry disposed... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200627 - Image sensor with high conversion efficiency: An image sensor includes a photoelectric converter, a reflector, and a charge carrier guiding region. The reflector is disposed under the photoelectric converter, and the charge carrier guiding region is disposed between the photoelectric converter and the reflector. The reflector reflects incident light passed by the photoelectric converter back through... Agent: Law Office Of Monica H Choi

20090200623 - Image sensor with micro-lenses of varying focal lengths: An image sensor having a plurality of micro-lenses disposed on a semiconductor substrate. A first micro-lens has a different focal length, height, shape, curvature, thickness, etc., than a second micro-lens. The image sensor may be back side illuminated or front side illuminated.... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200628 - Reduced imager crosstalk and pixel noise using extended buried contacts: Methods and structures to reduce the occurrence of crosstalk and pixel noise in solid state imager arrays. In an exemplary embodiment, a section of a layer patterned to form polysilicon buried-contacts in the pixel structure is also patterned to be disposed over the active, photosensor portion of the pixel. The... Agent: Dickstein Shapiro LLP

20090200622 - Self-aligned filter for an image sensor: An image sensor includes at least one photosensitive element disposed in a semiconductor substrate. Metal conductors may be disposed on the semiconductor substrate. A filter may be disposed between at least two individual metal conductors and a micro-lens may be disposed on the filter. There may be insulator material disposed... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200629 - Semiconductor device and manufacturing method therefor: A semiconductor device which includes a semiconductor chip formed with a light-reception area, a spacer, and a transparent substrate. The spacer is bonded to the semiconductor chip via a first adhesive and surrounding the light-reception area. The transparent substrate is bonded to the spacer via a second adhesive and disposed... Agent: Sonnenschein Nath & Rosenthal LLP

20090200630 - Solid-state image pickup device and method for manufacturing the same: A solid-state image pickup device which includes a solid-state image pickup chip, a transparent plate disposed to face a light-receiving surface of the solid-state image pickup chip, a frame-like spacer disposed on a peripheral portion of the light-receiving surface of the solid-state image pickup chip for maintaining a space between... Agent: Staas & Halsey LLP

20090200631 - Backside illuminated imaging sensor with light attenuating layer: A backside illuminated imaging sensor includes a semiconductor substrate, a metal interconnect layer and a light attenuating layer. The semiconductor substrate has a front surface, a back surface, and includes at least one imaging pixel formed on the front surface of the semiconductor substrate. The metal interconnect layer is electrically... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090200632 - Image sensor having through via: One embodiment exemplarily described herein can be characterized as an image sensor including a substrate having a front surface and a rear surface; a photoelectric converting portion on the front surface of the substrate; a through via extending through the substrate, wherein the through via is electrically connected to the... Agent: Marger Johnson & Mccollom, P.C.

20090200633 - Semiconductor structures with dual isolation structures, methods for forming same and systems including same: A semiconductor structure with dual isolation structures is disclosed. The semiconductor structure may include a protruding isolation structure in a pixel array region of a substrate and an embedded isolation structure in a peripheral device region of the same substrate. A region of the protruding isolation structure extends from an... Agent: Trask Britt, P.C./ Micron Technology

20090200634 - Multi-angle rotation for ion implantation of trenches in superjunction devices: A method of manufacturing a semiconductor device includes providing a semiconductor wafer and forming at least one first trench in the wafer having first and second sidewalls and a first orientation on the wafer. The first sidewall of the at least one first trench is implanted with a dopant of... Agent: Panitch Schwarze Belisario & Nadel LLP

20090200635 - Integrated circuit having electrical isolation regions, mask technology and method of manufacturing same: An integrated circuit device (e.g., a logic or memory device) having a plurality of memory cells each including at least one transistor, wherein transistors of neighboring memory cells are separated by isolation regions. The isolation regions include a first liner layer, a barrier layer disposed on or over the first... Agent: Neil Steinberg

20090200636 - Sub-lithographic dimensioned air gap formation and related structure: Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at... Agent: Hoffman Warnick LLC

20090200637 - Methods and devices for a high-k stacked capacitor: An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend dielectric layer of an integrated circuit and depositing multiple layers of metal, each layer of metal electrically tied to an associated electrode. The method also includes alternately... Agent: Texas Instruments Incorporated

20090200638 - Mim capacitor integration: An integrated metal-insulator-metal capacitor is formed so that there is an extension portion of its top plate that does not face any portion of the bottom plate, and an extension portion of its bottom plate that does not face any portion of the top plate. Vias connecting the MIM capacitor... Agent: Freescale Semiconductor, Inc. Law Department

20090200639 - Package substrate with built-in capacitor and manufacturing method thereof: When a package substrate with a built-in capacitor includes a first thin-film small electrode 41aa and a second thin-film small electrode 42aa that are electrically short-circuited to each other via a pinhole P in a high-dielectric layer 43, a power supply post 61a and a via hole 61b are not... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090200640 - Variable resistive element, and its manufacturing method: A variable resistive element comprising a configuration that an area of an electrically contributing region of a variable resistor body is finer than that constrained by an upper electrode or a lower electrode and its manufacturing method are provided. A bump electrode material is formed on a lower electrode arranged... Agent: Nixon & Vanderhye, PC

20090200641 - Semiconductor device and method of manufacturing the same: The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090200642 - Highly tunable metal-on-semiconductor trench varactor: An array of deep trenches is formed in a doped portion of the semiconductor substrate, which forms a lower electrode. A dielectric layer is formed on the sidewalls of the array of deep trenches. The array of deep trenches is filled with a doped semiconductor material to form an upper... Agent: Scully, Scott, Murphy & Presser, P.C.

20090200643 - Semiconductor and method for producing the same: A method for producing a semiconductor by conducting superimposed doping of a plurality of dopants in a semiconductor substrate, which includes evaporating a (2×n) structure by a first dopant and forming its thin line structure on the substrate, then bringing the semiconductor substrate to a temperature capable of epitaxial growth,... Agent: Wenderoth, Lind & Ponack, L.L.P.

20090200644 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device includes a semiconductor layer, an electrode connected to the semiconductor layer, a sacrificial metal layer connected to the electrode and made of a metal having higher ionization tendency than the material of the semiconductor layer and the material of the electrode.... Agent: Leydig Voit & Mayer, Ltd

20090200645 - Semiconductor electronic device: A semiconductor electronic device comprises a substrate; a buffer layer formed on the substrate, the buffer layer including not less than two layers of composite layer in which a first semiconductor layer formed of a nitride-based compound semiconductor layer having a lattice constant smaller than a lattice constant of the... Agent: Turocy & Watson, LLP

20090200646 - One-dimensional arrays of block copolymer cylinders and applications thereof: Methods for fabricating sublithographic, nanoscale microstructures in one-dimensional arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.... Agent: Whyte Hirschboeck Dudek S.c. Intellectual Property Department

20090200648 - Embedded die system and method: A method and system is disclosed for facilitating miniaturization of an electronic device by efficiently utilizing available space. Specifically, in an exemplary embodiment, there is provided an electronic device comprising a substrate, a cavity formed in the substrate, and a bridge coupled to the substrate such that it spans the... Agent: Apple Inc. C/o Fletcher Yoder, PC

20090200647 - Shielded integrated circuit pad structure: An integrated circuit pad structure includes a ground strip (206) positioned below a pad (101). In one example a conductive element (102) is coupled to the pad (101), and at least two tiled layers, positioned below the first conductive element (102) and positioned above the ground strip (206) are included.... Agent: Vedder Price P.C. Joseph T. Cygan

20090200649 - Semiconductor device and manufacturing method of the same: A wire short-circuit defect during molding is prevented. A semiconductor device has a tab, a plurality of leads arranged around the tab, a semiconductor chip mounted over the tab, a plurality of wires electrically connecting the electrode pads of the semiconductor chip with the leads, and a molded body in... Agent: Mattingly & Malur, P.C.

20090200650 - Integrated circuit package and a method of making: An integrated circuit package includes a substrate and a first semiconductor chip. The first semiconductor chip is provided in a cavity on a first side of the substrate. The package further includes a second semiconductor chip provided on a second side of the substrate. The first semiconductor chip and the... Agent: Dicke, Billig & Czaja

20090200651 - Multi-chip package: A multi-chip package structure is provided with a first chip, a substrate adjacent to the first chip, a plurality of contacts connecting the first chip and the substrate, a second chip disposed between the first chip and the substrate and connecting to the first chip, and a underfill film, wherein... Agent: Jianq Chyun Intellectual Property Office

20090200653 - Memory modules and systems including the same: Provided is a memory module. The memory module may include a mounting substrate including a plurality of first substrate pads disposed on a top surface of the mounting substrate, a first semiconductor package disposed on a top surface of the mounting substrate, the first semiconductor package having a first frame... Agent: F. Chau & Associates, LLC

20090200652 - Method for stacking chips in a multi-chip package: A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090200654 - Method of electrically connecting a microelectronic component: A microelectronic assembly is provided which can include an element including a first dielectric layer and a second dielectric layer overlying the first dielectric layer, the second dielectric layer having an exposed surface defining an exposed major surface of the element. A plurality of substantially rigid metal posts can project... Agent: Tessera Lerner David Et Al.

20090200655 - Method of electrically connecting a microelectronic component: A microelectronic unit can include a support structure including a dielectric having oppositely-directed first and second surfaces. A plurality of substantially rigid posts can protrude parallel to one another in a direction beyond the first surface of the support structure. Each post may have a top surface remote from the... Agent: Tessera Lerner David Et Al.

20090200656 - Semiconductor device and manufacturing method thereof: There are constituted by a tab (1b) on which a semiconductor chip (2) is mounted, a sealing portion (3) formed by resin-sealing the semiconductor chip (2), a plurality of leads (1a) each having a mounted surface (1d) exposed to a peripheral portion of a rear surface (3a) of the sealing... Agent: Miles & Stockbridge PC

20090200657 - 3d smart power module: A 3D smart power module for power control, such as a three phase power control module, includes a two sided printed circuit (PC) board with power semiconductor devices attached to one side and control semiconductor devices attached to the other side. The power semiconductor devices are die bonded to a... Agent: Hiscock & Barclay, LLP

20090200658 - Circuit board structure embedded with semiconductor chips: A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric... Agent: Sawyer Law Group LLP

20090200659 - Chip package with channel stiffener frame: Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first... Agent: Timothy M Honeycutt Attorney At Law

20090200660 - Heatplates for heatsink attachment for semiconductor chips: An apparatus for heatsink attachment and a method for forming the apparatus. The apparatus includes a substrate, a semiconductor chip on top of and physically attached to the substrate, and a lid on top of the substrate. The lid includes a first thermally conductive material. The apparatus further includes a... Agent: Schmeiser, Olsen & Watts

20090200661 - Devices with faraday cages and internal flexibility sipes: A computer or microchip comprising an outer chamber and at least one inner chamber inside the outer chamber. The outer chamber and the inner chamber being separated at least in part by an internal sipe, and at least a portion of a surface of the outer chamber forming at least... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090200662 - Semiconductor package and method of making the same: The present invention relates to semiconductor devices comprising two or more dies stacked vertically on top of one another, and methods of making the semiconductor devices. The methods may comprise a combination of wafer-level through silicon interconnect fabrication and wafer-level assembly processes.... Agent: Sughrue Mion, PLLC

20090200664 - Manufacturing method of semiconductor apparatus and semiconductor apparatus: A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090200663 - Polymer and solder pillars for connecting chip and carrier: A method of connecting chips to chip carriers, ceramic packages, etc. (package substrates) forms smaller than usual first solder balls and polymer pillars on the surface of a semiconductor chip and applies adhesive to the distal ends of the polymer pillars. The method also forms second solder balls, which are... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090200665 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor construction assembly having a semiconductor substrate which has first and second surfaces, and has an integrated circuit element formed on the first surface, a plurality of connection pads which are connected to the integrated circuit element, a protective layer which covers the semiconductor substrate... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090200666 - Semiconductor integrated circuit device: A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner... Agent: Fitzpatrick Cella Harper & Scinto

20090200667 - Ohmic contact film in semiconductor device: The invention provides an ohmic contact film formed between a doped semiconductor material layer and a conductive material layer of a semiconductor device. The composition of the ohmic contact film according to a preferred embodiment of the invention is represented by the general formula MxQzNy, where M represents the II... Agent: Birch Stewart Kolasch & Birch

20090200669 - Enhanced interconnect structure: The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can be either partially embedded in the cap layer or completely embedded in the capping... Agent: International Business Machines Corporation Dept. 18g

20090200668 - Interconnect structure with high leakage resistance: An interconnect structure is provided in which the conductive feature (i.e., conductive material) is not coplanar with the upper surface of the dielectric material, but instead the conductive material is recessed below an upper surface of the dielectric material. In addition to being recessed below the upper surface of the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090200672 - Method for manufacturing semiconductor device: Disclosed is a method for manufacturing a semiconductor device. This method includes the step of forming a diffusion barrier film, which is interposed between a silicon film and a metal film and functions to prevent diffusion between the silicon and metal films. The diffusion barrier film is formed of a... Agent: Ladas & Parry LLP

20090200670 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090200671 - Sip semiconductor device and method for manufacturing the same: A System In Package (SIP) semiconductor device and a method for manufacturing a SIP device. A TiSiN film may be used as a diffusion barrier film for metal wiring in a SIP semiconductor device. A TiSiN film may provide relatively good step coverage in a relatively easy formation process, which... Agent: Sherr & Vaughn, PLLC

20090200673 - Via bottom contact and method of manufacturing same: A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via... Agent: Greenblum & Bernstein, P.L.C

20090200675 - Passivated copper chip pads: A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in... Agent: Slater & Matsil LLP

20090200676 - Semiconductor device: A semiconductor device which includes a first wiring with a via connected to the first wiring, a second wiring connected to the via and a dummy via disposed adjacent to the via at a distance of 100 nm or less and formed on the same layer as the via.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090200677 - Semiconductor device: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near... Agent: Mcdermott Will & Emery LLP

20090200674 - Structure and method of forming transitional contacts between wide and thin beol wirings: A structure and method of forming a conducting via for connecting two back end of the line (BEOL) metal wiring levels is described. The method includes forming a first interconnect structure having a first dimensional width in a first dielectric layer; depositing a second dielectric layer over said first dielectric... Agent: International Business Machines Corporation Dept. 18g

20090200678 - Device comprising multi-layered thin film having excellent adhesive strength and method for fabricating the same: A device comprises a multi-layered thin film having excellent adhesion due to the method of fabricating the same. More particularly, the device includes a multi-layered thin film consisting of a tantalum nitride layer, a tantalum layer formed on the tantalum nitride layer, and a gold thin film formed on the... Agent: Robert E. Bushnell & Law Firm

20090200681 - Forming compliant contact pads for semiconductor packages: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and... Agent: Trop, Pruner & Hu, P.C.

20090200679 - Semiconductor apparatus and method for manufacturing the same: A semiconductor apparatus including a semiconductor substrate, an insulating layer, a via hole, and a through-hole interconnection is provided. The insulating layer is formed on the semiconductor substrate. The via hole is formed through the semiconductor substrate and the insulating layer. The through-hole interconnection has a conductive layer formed on... Agent: Sonnenschein Nath & Rosenthal LLP

20090200680 - Semiconductor device: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board... Agent: Miles & Stockbridge PC

20090200683 - Interconnect structures with partially self aligned vias and methods to produce same: An interconnect structure having partially self aligned vias with an interlayer dielectric layer on a substrate, containing at least two conducting metal lines that traverse parallel to the substrate and at least two conducting metal vias that are orthogonal to the substrate. A method of producing the self aligned vias... Agent: Nugent & Smith, LLP

20090200682 - Via in via circuit board structure: Methods, systems, and apparatuses for electrical connections through circuit boards are described. A via-in-via structure in a circuit board provides two electrical signal paths. The circuit board includes a dielectric layer having opposing first and second planar surfaces. A first opening extends through the dielectric layer. An electrically conductive coating... Agent: Fiala & Weaver, P.l.l.c. C/o Cpa Global

20090200684 - Flip chip package with shelf and method of manufactguring there of: The semiconductor device according to the present invention has a planar semiconductor chip having projecting connection terminals provided on one surface thereof. A shelf is provided where a peripheral edge of a surface of the semiconductor chip opposite one surface thereof onto which connection terminals are provided is removed. This... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090200685 - Electronic packaging method and apparatus: The present invention utilizes a panel substrate as the packaging substrate carried by a working susceptor. Packaging devices are hung in the nearby of the working susceptor and moved by robot arms to the working susceptor, whereby the problems of substrate warpage and substrate transportation are overcome. Further, identical or... Agent: Eschweiler & Associates LLC National City Bank Building

20090200686 - Electrical connecting structure and bonding structure: A electrical connecting structure including a conductive pad, a polymer bump and a patterned conductive layer is provided. The conductive pad is on a substrate and the polymer bump is disposed over the substrate. The patterned conductive layer is disposed on the polymer bump and electrically connects to the conductive... Agent: Jianq Chyun Intellectual Property Office

20090194755 - High density chalcogenide memory cells: A non-volatile memory cell is constructed from a chalcogenide alloy structure and an associated electrode side wall. The electrode is manufactured with a predetermined thickness and juxtaposed against a side wall of the chalcogenide alloy structure, wherein at least one of the side walls is substantially perpendicular to a planar... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090194757 - Phase change element extension embedded in an electrode: The present invention in one embodiment provides a method of forming a memory device that includes providing an interlevel dielectric layer including a conductive stud having a first width; forming an stack comprising a metal layer and a first insulating layer; forming a second insulating layer atop portions of the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090194756 - Self-aligned eletrode phase change memory: A phase change memory may be formed with an upper electrode self-aligned to a phase change memory element. In some embodiments, patterning techniques may be used to form the elements of the memory. The memory element may be formed as a sidewall spacer formed on both opposed sides of an... Agent: Trop, Pruner & Hu, P.C.

20090194758 - Heating center pcram structure and methods for making: Memory devices are described along with manufacturing methods. A memory device as described herein includes a bottom electrode and a first phase change layer comprising a first phase change material on the bottom electrode. A resistive heater comprising a heater material is on the first phase change material. A second... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090194760 - Memory element and display device: Disclosed herein is a memory element, including a parallel combination of a thin film transistor; and a resistance change element, the thin film transistor including a semiconductor thin film in which a channel region, and an input terminal and an output terminal located on both sides of the channel region,... Agent: Rader Fishman & Grauer PLLC

20090194759 - Phase change memory device: A phase change memory device is disclosed, including a substrate, a phase change layer over the substrate, a first electrode electrically connecting a first side of the phase change layer, a second electrode electrically connecting a second side of the phase change layer, wherein the phase change layer composes mainly... Agent: Quintero Law Office, PC

20090194761 - Enhancement of optical polarization of nitride light-emitting diodes by increased indium incorporation: An increase in the Indium (In) content in light-emitting layers of light-emitting diode (LED) structures prepared on nonpolar III-nitride substrates result in higher polarization ratios for light emission than LED structures containing lesser In content. Polarization ratios should be higher than 0.7 at wavelengths longer than 470 nm.... Agent: Gates & Cooper LLP Howard Hughes Center

20090194762 - Method of doping organic semiconductors: A method includes forming a contiguous semiconducting region that includes polyaromatic molecules. The region is heated to a temperature above room temperature in the presence of a dopant gas and the absence of light to form a doped organic semiconducting region.... Agent: Hitt Gaines, PC Alcatel-lucent

20090194763 - Semiconductor element, method for manufacturing the semiconductor element, electronic device and method for manufacturing the electronic device: A manufacturing method of a semiconductor element provided with a semiconductor layer containing a crystal of an organic semiconductor material of the invention includes the steps of (i) forming a frame (12) on a substrate (base) (11), and (ii) forming the semiconductor layer (crystal (13)) inside the frame (12). The... Agent: Hamre, Schumann, Mueller & Larson P.C.

20090194764 - Multi-layer storage node, resistive random access memory device including a multi-layer storage node and methods of manufacturing the same: A multi-layer storage node, resistive random access memory device and methods of manufacturing the same are provided. The resistive random access memory device includes a switching structure and a storage node connected to the switching structure. The storage node includes a lower electrode, a first layer, a second layer, and... Agent: Harness, Dickey & Pierce, P.L.C

20090194765 - Ceramic mesfet device and manufacturing method thereof: A method of manufacturing a MESFET using ceramic materials includes providing a substrate; providing a ceramic semiconductor material to apply onto the substrate to form a first ceramic semiconductor layer; providing a ceramic semiconductor material which is blended with ions, wherein the ceramic semiconductor material is applied onto a central... Agent: Rosenberg, Klein & Lee

20090194767 - Conductive oxide-deposited substrate and method for producing the same, and mis laminated structure and method for producing the same: A method for producing a conductive oxide-deposited substrate including depositing a conductive oxide thin film over a substrate, subjecting the conductive oxide thin film to heat treatment by irradiating with a condensed laser beam so as to be thermally changed in part, and subjecting the conductive oxide thin film to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090194766 - Thin film transistor, method of manufacturing the same, and flat panel display device having the same: A thin film transistor (TFT) using an oxide semiconductor layer as an active layer, a method of manufacturing the TFT, and a flat panel display (FPD) including the TFT are taught. The TFT includes a gate electrode formed on a substrate, an oxide semiconductor layer electrically insulated from the gate... Agent: Robert E. Bushnell & Law Firm

20090194768 - Vertical system integration: The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use... Agent: Michael J. Ure

20090194769 - Crystallizing method, thin-film transistor manufacturing method, thin-film transistor, and display device: A crystallizing method of causing a phase shifter to phase-modulate a laser beam whose wavelength is 248 nm or 300 nm or more from an excimer laser unit into a laser beam with a light intensity profile having a plurality of inverted triangular peak patterns in cross section and of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090194770 - Double-active-layer structure with a polysilicon layer and a microcrystalline silicon layer, method for manufacturing the same and its application: A first amorphous silicon layer is formed over a substrate and a second amorphous silicon layer is formed over the first amorphous silicon layer. When a laser annealing process is performed, the second amorphous silicon layer absorbs more laser light than the first amorphous silicon layer does. The first amorphous... Agent: Venable LLP

20090194771 - Semiconductor device and method for manufacturing the same: An object of the present invention is to provide a semiconductor device which has flexibility and resistance to a physical change such as bending and a method for manufacturing the semiconductor device. A semiconductor device of the present invention includes a plurality of transistors provided over a flexible substrate, each... Agent: Eric Robinson

20090194773 - Gallium nitride material devices including diamond regions and methods associated with the same: Gallium nitride material structures are provided, as well as devices and methods associated with such structures. The structures include a diamond region which may facilitate conduction and removal of heat generated within the gallium nitride material during device operation. The structures described herein may form the basis of a number... Agent: Wolf Greenfield & Sacks, P.C.

20090194772 - Method for fabricating silicon carbide vertical mosfet devices: A method of forming a vertical MOSFET device includes forming a first trench within a semiconductor layer of a first polarity, the first trench generally defining a well region of a second polarity opposite the first polarity; growing a first epitaxial well layer of the second polarity over the original... Agent: General Electric Company Global Research

20090194774 - Light source module with wavelength converting structure and the method of forming the same: A light source package module with a wavelength converting structure is provided. The light source package module comprises a frame having a substrate and sidewalls formed on the substrate. A plurality of LED dice is disposed on the substrate, and there is a space between each of the LED dice.... Agent: Bacon & Thomas, PLLC

20090194775 - Semiconductor light emitting devices with high color rendering: A packaged light emitting device (LED) includes a light emitting diode configured to emit primary light having a peak wavelength that is less than about 465 nm and having a shoulder emission component at a wavelength that is greater than the peak wavelength, and a wavelength conversion material configured to... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090194778 - Light emitting diode: A light emitting diode (10) includes an LED chip (14) and an encapsulant (16) enclosing the LED chip. The LED chip has a light emitting surface (141), and the encapsulant has a light output surface (161) over the light emitting surface. The light output surface defines a plurality of annular,... Agent: PCe Industry, Inc. Att. Steven Reiss

20090194779 - Light emitting diode and method for manufacturing the same: A light emitting diode includes a current leakage passage electrically connected in parallel to an active layer to better protect the light emitting diode from static electricity. The light emitting diode includes a substrate, an n-type nitride semiconductor layer on the substrate, an active layer on the n-type nitride semiconductor... Agent: H.c. Park & Associates, PLC

20090194783 - Light emitting element, production method thereof, backlight unit having the light emitting element, and production method thereof: A light emitting element includes: A light emitting element, includes: at least one LED chip provided on an installation surface of a substrate; a metallic reflecting plate, provided upright in a light projecting direction of the LED chip on the installation surface so as to surround an entire periphery of... Agent: Morrison & Foerster LLP

20090194776 - Light-emitting diode arragement comprising a color-converting material: With a light-emitting diode arrangement (1) having a light-emitting diode chip (2) arranged on a base (3), and colour conversion material (7) surrounding the light-emitting diode chip (2), which material is constituted to convert at least a part of the light emitted by the light-emitting diode chip (2) into light... Agent: Fish & Associates, PC Robert D. Fish

20090194777 - Optoelectronic device submount: A submount for an optoelectronic device includes a substrate, a first top pad on a top surface of the substrate, a first bottom pad on a bottom surface of the substrate and a first wrap-around contact in a sidewall recess of the substrate, in which the first wrap-around contact is... Agent: Fish & Richardson P.C.

20090194780 - Organic light emitting diode display device and method of fabricating the same: An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. When an organic layer having an emission layer (EML) is formed using a deposition mask, damage to a pixel defining layer due to inconsistencies or unevenness of the deposition mask is prevented or... Agent: Christie, Parker & Hale, LLP

20090194782 - Semiconductor light emitting device: A silver-plated metal member region on which a light emitting element is disposed, an extraction electrode having a copper plate pattern, and a convex resin portion separating the metal member region into a plurality of sections are provided on the bottom surface of a concave portion in a package of... Agent: Morrison & Foerster LLP

20090194781 - Wavelength conversion member, light-emitting device and phosphor: A wavelength conversion member provided with a composite phosphor obtained by coating surfaces of phosphor particles with coating material particles and has an average particle diameter of the coating material of not more than 1/10 of an average particle diameter of the phosphor particles, and a light emitting device using... Agent: Birch Stewart Kolasch & Birch

20090194784 - Group-iii nitride compound semiconductor device and production method thereof, group-iii nitride compound semiconductor light-emitting device and production method thereof, and lamp: A group-III nitride compound semiconductor device of the present invention comprises a substrate, an intermediate layer provided on the substrate, and a base layer provided on the intermediate layer in which a full width at half maximum in rocking curve of a (0002) plane is 100 arcsec or lower and... Agent: Sughrue Mion, PLLC

20090194785 - Semiconductor device and manufacturing method thereof: A p-type body region and an n-type buffer region are formed on an n− drift region. An n++ emitter region and a p++ contact region are formed on the p-type body region in contact with each other. A p++ collector region is formed on the n-type buffer region. An insulating... Agent: Rabin & Berdo, PC

20090194786 - Semiconductor device and method of manufacturing same: A semiconductor device includes deep first field limiting rings, shallow second field limiting rings, insulation films covering each surface portion of each of the first and the second field limiting rings, and conductive field plates each in contact with a surface of each of the first and the second field... Agent: Rossi, Kimms & Mcdowell LLP.

20090194787 - Vertical outgassing channels: InP epitaxial material is directly bonded onto a Silicon-On-Insulator (SOI) wafer having Vertical Outgassing Channels (VOCs) between the bonding surface and the insulator (buried oxide, or BOX) layer. H2O and other molecules near the bonding surface migrate to the closest VOC and are quenched in the buried oxide (BOX) layer... Agent: Gates & Cooper LLP Howard Hughes Center

20090194789 - Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region: By incorporating a carbon species below the channel region of a P-channel transistor prior to the formation of the gate electrode structure, an efficient strain-inducing mechanism may provided, thereby enhancing performance of P-channel transistors. The position and size of the strain-inducing region may be determined on the basis of an... Agent: Williams, Morgan & Amerson

20090194788 - Strained channel transistor structure and method: A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being... Agent: HorizonIPPte Ltd

20090194791 - Compound semiconductor device and manufacturing method thereof: A compound semiconductor device including an electron transport layer that is formed on a substrate and includes a III-V nitride compound semiconductor, a gate insulating film that is positioned above the compound semiconductor layer, and a gate electrode that is positioned on the gate insulating film. The gate insulating film... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090194790 - Field effect transister and process for producing the same: A field effect transistor has an MOS structure and is formed of a nitride based compound semiconductor. The field effect transistor includes a substrate; a semiconductor operating layer having a recess part and formed on the substrate; an insulating layer formed on the semiconductor operating layer including the recess part;... Agent: Kubotera & Associates, LLC

20090194792 - Semiconductor device and manufacturing method therefor: A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over... Agent: Mattingly & Malur, P.C.

20090194793 - Iii-nitride wafer and devices formed in a iii-nitride wafer: A III-nitride device having a support substrate that may include a first silicon body, a second silicon body, an insulation body interposed between the first and second silicon bodies, and a III-nitride body formed over the second silicon body.... Agent: Farjami & Farjami LLP

20090194794 - Solid-state image pickup device and manufacturing method thereof: A partial P type region 150 is provided at the predetermined position of a lower layer region of the vertical transfer register 124 and a channel stop region 126. This P type region 150 is used to adjust potential in the lower layer region of the vertical transfer register 124... Agent: Frommer Lawrence & Haug

20090194795 - Solid state imaging device and method for fabricating the same: A first oxide film (102) is formed on a semiconductor substrate (101). A first nitride film (103) is formed on first gate electrode formation regions of the first oxide film (102). A plurality of first gate electrodes (104) are provided on the first nitride film (103) so as to be... Agent: Mcdermott Will & Emery LLP

20090194796 - Vertical gallium nitride semiconductor device and epitaxial substrate: Affords epitaxial substrates for vertical gallium nitride semiconductor devices that have a structure in which a gallium nitride film of n-type having a desired low carrier concentration can be provided on a gallium nitride substrate of n type. A gallium nitride epitaxial film (65) is provided on a gallium nitride... Agent: Judge Patent Associates

20090194797 - Insulating film and semiconductor device including the same: It is made possible to provide an insulating film that can reduce the leakage current. An insulating film includes: an amorphous oxide dielectric film containing a metal, hydrogen, and nitrogen. The nitrogen amount [N] and the hydrogen amount [H] in the oxide dielectric film satisfy the following relationship: {[N]−[H]}/2≦1.0×1021 cm−3.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090194798 - Backside illuminated imaging sensor having a carrier substrate and a redistribution layer: A backside illuminated imaging sensor includes a semiconductor substrate having a front surface and a back surface. The semiconductor substrate has at least one imaging array formed on the front surface. The imaging sensor also includes a carrier substrate to provide structural support to the semiconductor substrate, where the carrier... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090194799 - Dual-pixel full color cmos imager: A dual-pixel full color complementary metal oxide semiconductor (CMOS) imager is provided, along with an associated fabrication process. Two stand-alone pixels are used for three-color detection. The first pixel is a single photodiode, and the second pixel has two photodiodes built in a stacked structure. The two photodiode stack includes... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20090194800 - Dual-pixel full color cmos imager with large capacity well: A dual-pixel full color CMOS imager is provided. The imager comprises a two-photodiode stack including an n doped substrate, a bottom photodiode, and a top photodiode. The bottom photodiode has a bottom p doped layer at a first depth overlying the substrate and a bottom n doped layer cathode overlying... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20090194801 - ferroelectric capacitor manufacturing process: A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a... Agent: Texas Instruments Incorporated

20090194802 - Semiconductor constructions, and dram arrays: The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. The invention also includes DRAM arrays having low rates of refresh. Additionally, the invention includes semiconductor constructions... Agent: Wells St. John P.s.

20090194803 - Semiconductor device and method for manufacturing the same: The present invention provides a semiconductor device capable of being mass-produced and a manufacturing method of the semiconductor device. The present invention also provides a semiconductor device using an extreme thin integrated circuit and a manufacturing method of the semiconductor device. Further, the present invention provides a low power consumption... Agent: Nixon Peabody, LLP

20090194804 - Non-volatile memory cell: Disclosed herein are non-volatile cells and methods of manufacturing the same. The nonvolatile memory cells include a high voltage device, a low voltage device, and a memory cell formed on a semiconductor substrate. The high voltage device, low voltage device, and memory cell are all self-aligned by using the gates... Agent: Fish & Richardson P.C.

20090194805 - Non-volatile memory device: A non-volatile memory device includes a substrate, an active region, an isolation layer, a tunnel insulation layer, a floating gate, a dielectric layer and a control gate. The active region includes an upper active region having a first width, and a lower active region beneath the upper active region and... Agent: Myers Bigel Sibley & Sajovec

20090194806 - Single poly type eeprom and method for manufacturing the eeprom: Embodiments relate to a single poly type EEPROM and a method for manufacturing an EEPROM. According to embodiments, a single poly type EEPROM may include unit cells. A unit cell may include a floating gate at a side of a control node formed on and/or over a semiconductor substrate having... Agent: Sherr & Vaughn, PLLC

20090194808 - Semiconductor device: A semiconductor device includes an element region having a channel region, and a unit gate structure inducing a channel in the channel region, the unit gate structure including a tunnel insulating film formed on the element region, a charge storage insulating film formed on the tunnel insulating film, a block... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090194809 - Semiconductor memory and method for manufacturing the same: A semiconductor memory in which a gate insulating film (tunnel insulating film) in a memory cell provides higher operational reliability. The semiconductor memory includes an insulating film 3 between a silicon substrate 1 and a gate electrode 4. The insulating film 3 is composed of a silicon oxide film 3f,... Agent: Young & Thompson

20090194807 - Semiconductor memory device and method for manufacturing the same: A semiconductor memory device includes: a semiconductor substrate; an element isolation trench formed on the semiconductor substrate so as to surround an element region in which a memory element is to be formed; a first gate insulating film formed on the element region of the semiconductor substrate; a charge storing... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090194810 - Semiconductor device using element isolation region of trench isolation structure and manufacturing method thereof: A stacked film including a gate dielectric film and electrode film of each memory cell of a flash memory is formed on a semiconductor substrate. The stacked film is patterned by reactive ion etching to form an isolation trench for formation of an element isolation region and the surface of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090194812 - structure for making a top-side contact to a substrate: A semiconductor structure includes a starting semiconductor substrate having a recessed portion. A semiconductor material is formed in the recessed portion and has a higher resistivity than the starting semiconductor substrate. A body region extends in the semiconductor material, and has a conductivity type opposite that of the semiconductor material.... Agent: Townsend And Townsend And Crew, LLP

20090194813 - Semiconductor device and method for manufacturing the same: The semiconductor device comprises a word line and a bit line. The word line comprises a gate electrode and a first metal interconnect. The first metal interconnect has contact with the gate electrode and extends into a region upper than a first impurity-diffused region in a first direction. The bit... Agent: Sughrue Mion, PLLC

20090194811 - Structure and method for forming field effect transistor with low resistance channel region: A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a first PN junction with the silicon region,... Agent: Townsend And Townsend And Crew, LLP

20090194814 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a channel region extending substantially perpendicular to a main surface of a semiconductor substrate; a first diffusion layer provided on a bottom of the channel region; a second diffusion layer provided on a top of the channel region; a first gate electrode that extends substantially perpendicular... Agent: Mcginn Intellectual Property Law Group, PLLC

20090194815 - High voltage transistor: A high voltage transistor that includes a substrate where an active region is defined, a first impurity region and a second impurity region in the active region and a third impurity region between the first and second impurity regions, and a first gate electrode on the active region between the... Agent: Stanzione & Kim, LLP

20090194817 - Cmos integrated circuit devices having stressed nmos and pmos channel regions therein: Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may... Agent: Myers Bigel Sibley & Sajovec

20090194819 - Cmos structures and methods using self-aligned dual stressed layers: A CMOS structure and methods for fabricating the CMOS structure provide that a first stressed layer located over a first transistor and a second stressed layer located over a second transistor abut but do not overlap. Such an abutment absent overlap provides for enhanced manufacturing flexibility when forming a contact... Agent: Scully, Scott, Murphy & Presser, P.C.

20090194816 - Semiconductor device and method of fabricating the same: A semiconductor device according to one embodiment includes: an n-type transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first spacer formed on a side face of the first gate electrode, a first channel region formed in the semiconductor substrate under... Agent: Turocy & Watson, LLP

20090194818 - Transistor gate forming methods and integrated circuits: A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited... Agent: Wells St. John P.s.

20090194820 - Cmos (complementary metal oxide semiconductor) devices having metal gate nfets and poly-silicon gate pfets: A semiconductor structure fabrication method. The method includes providing a structure which includes (a) first and second semiconductor regions, (b) first and second gate dielectric regions on the first and second semiconductor regions, respectively, (c) a high-K dielectric region on the first gate dielectric region, K being greater than 4,... Agent: Schmeiser, Olsen & Watts

20090194821 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device according to one embodiment includes: forming a SiGe crystal layer on a semiconductor substrate, the SiGe crystal layer having a first plane and a second plane inclined with respect to the first plane; forming an amorphous Si film on the SiGe crystal layer;... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090194822 - Continuous multigate transistors: An N doped area neighboring to a P doped area on a semiconductor material, function respectively as a first gate and a second gate for transistors. A dielectric layer is made under the gates. A source and a drain are made under and near two sides of the dielectric layer,... Agent: Lowe Hauptman Ham & Berner, LLP

20090194823 - Semiconductor device: A semiconductor device includes a first MISFET and a second MISFET which are formed over a semiconductor substrate and have the same conductive type. The first MISFET has a first gate insulating film arranged over the semiconductor substrate, a first gate electrode arranged over the first gate insulating film, and... Agent: Mattingly & Malur, P.C.

20090194824 - Body controlled double channel transistor and circuits comprising the same: By providing a body controlled double channel transistor, increased functionality in combination with enhanced stability may be accomplished. For instance, flip flop circuits usable for static RAM cells may be formed on the basis of the body controlled double channel transistor, thereby reducing the number of transistors required per cell,... Agent: Williams, Morgan & Amerson

20090194825 - Self-aligned contact structure in a semiconductor device: By forming an isolation structure that extends above the height level defined by the semiconductor material of an active region, respective recesses may be defined in combination with gate electrode structures of the completion of basic transistor structures. These recesses may be subsequently filled with an appropriate contact material, thereby... Agent: Williams, Morgan & Amerson

20090194826 - Field-effect microelectronic device, capable of forming one or several transistor channels: The invention relates to a field-effect microelectronic device, as well as the method of production thereof. The device includes a substrate as well as at least one improved structure capable of forming one or more transistor channels. This structure, formed by a plurality of bars stacked on the substrate, can... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090194829 - Mems packaging including integrated circuit dies: MEMS packaging schemes having a system-on-package (SOP) configuration and a system-on-board (SOB) configuration are provided. The MEMS package comprises one or more MEMS dies, a cap section having one or more integrated circuit (IC) dies, and a packaging substrate or a printed circuit board (PCB) arranged in a stacking manner.... Agent: Slater & Matsil, L.L.P.

20090194828 - Method for mems threshold sensor packaging: Apparatus, methods, and systems for bonding a cover wafer to a MEMS threshold sensors located on a silicon disc. The cover wafer is trenched to form a region when bonded to the silicon wafer that produces a gap over the contact bond pads of the MEMS threshold sensor. The method... Agent: Honeywell International Inc. Patent Services

20090194827 - Semiconductor device having element portion and method of producing the same: A semiconductor device includes a semiconductor substrate, an element portion provided in the semiconductor substrate, and a connecting portion connected to the semiconductor substrate electrically, in which the connecting portion is formed of a conductive material in order to perform an electrical connection to an outside. The connecting portion is... Agent: Posz Law Group, PLC

20090194830 - Semiconductor device transducer and method: A semiconductor device such as a resonant device has a capacitive, non-piezoelectric, actuator, the actuator comprising a depletion region. A capacitive actuator for a semiconductor device, a method for fabricating such an actuator, and a method for operating a semiconductor device are also provided. In the operating method, a drive... Agent: Nexsen Pruet, LLC

20090194831 - Integrated cavity in pcb pressure sensor: Described herein is an integrated pressure sensor assembly. The integrated pressure sensor assembly includes a printed circuit board assembly comprising a plurality of boards; a pressure die mounted on at least a portion of the printed circuit board assembly; and a housing engaged to the printed circuit board assembly. The... Agent: Jeffer, Mangels, Butler & Marmaro, LLP

20090194832 - Magnetic tunnel junction cell including multiple magnetic domains: In a particular embodiment, a magnetic tunnel junction (MTJ) structure is disclosed that includes an MTJ cell having multiple sidewalls that extend substantially normal to a surface of a substrate. Each of the multiple sidewalls includes a free layer to carry a unique magnetic domain. Each of the unique magnetic... Agent: Qualcomm Incorporated

20090194833 - Tmr device with hf based seed layer: A MTJ structure is disclosed in which the seed layer is made of a lower Ta layer, a middle Hf layer, and an upper NiFe or NiFeX layer where X is Co, Cr, or Cu. Optionally, Zr, Cr, HfZr, or HfCr may be employed as the middle layer and materials... Agent: Saile Ackerman LLC

20090194834 - Photoelectrochemical device and method using carbon nanotubes: A photoelectrochemical device and method using carbon nanotubes comprise highly electrically conductive carbon nanotubes formed at an interface between a transparent electrode and a metal oxide layer. According to the photoelectrochemical device and method, the interface resistance, which is caused due to an incomplete contact at the interface, is lowered... Agent: Cantor Colburn, LLP

20090194835 - Image sensor: An image sensor capable of reducing crosstalk between pixels is provided. The image sensor includes a photoelectric converter formed in a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a plurality of structures formed on the interlayer insulating layer, each of the plurality of structures including an... Agent: F. Chau & Associates, LLC

20090194836 - Image sensor and method for manufacturing the same: An image sensor includes a semiconductor substrate including circuitry, an interlayer dielectric including metal lines arranged on the semiconductor substrate, crystalline photodiode patterns arranged on the interlayer dielectric such that the photodiode patterns are connected to the metal lines, hard mask patterns arranged on the respective photodiode patterns, a device-isolation... Agent: Sherr & Vaughn, PLLC

20090194837 - Semiconductor light receiving element and method of manufacturing semiconductor light receiving element, and optical communication system: The present invention provides a semiconductor light receiving element capable of reducing capacity while minimizing increase in travel time of carriers. The semiconductor light receiving element includes a semiconductor stacked structure including a first conductivity type layer, a light absorbing layer, and a second conductivity type layer having a light... Agent: Sonnenschein Nath & Rosenthal LLP

20090194838 - Cosi2 schottky diode integration in bismos process: Cobalt silicide (CoSi2) Schottky diodes fabricated per the current art suffer from excess leakage currents in reverse bias. In this invention, an floating p-type region encircles each anode of a CoSi2 Schottky diode comprising of one or more CoSi2 anodes. The resulting p-n junction forms a depletion region under the... Agent: Texas Instruments Incorporated

20090194839 - Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same: A high-density memory array. A plurality of word lines and a plurality of bit lines are arranged to access a plurality of memory cells. Each memory cell includes a first conductive terminal and an article in physical and electrical contact with the first conductive terminal, the article comprising a plurality... Agent: Wilmerhale/boston

20090194840 - Method of double patterning, method of processing a plurality of semiconductor wafers and semiconductor device: A method of double patterning is disclosed. The method includes forming a first photosensitive layer; exposing the first photosensitive layer using a first reticle; developing the first photosensitive layer thereby forming a first image pattern including first elements; forming a second photosensitive layer; exposing the second photosensitive layer using the... Agent: Slater & Matsil, L.L.P.

20090194841 - Semiconductor device: A semiconductor device has a semiconductor substrate of a first conductivity type; first to third high-voltage insulated-gate field effect transistors formed on a principal surface of the semiconductor substrate; a first device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090194842 - Semiconductor device and method of manufacturing the same: A semiconductor device includes an SOI substrate, a first STI-type isolation region, a second STI-type isolation region, and an alignment mark region. The SOI substrate includes a support substrate, an insulating layer deposited on the support substrate, and a semiconductor layer which includes a thin film region and a thick... Agent: Sughrue Mion, PLLC

20090194843 - Integrated circuit arrangement including a protective structure: An integrated circuit arrangement. In one embodiment, the arrangement includes at least one first semiconductor zone of a first conduction type which is doped more highly than the basic doping of a first semiconductor layer and which is arranged at a distance from a first component zone adjoining the first... Agent: Dicke, Billig & Czaja

20090194845 - Semiconductor device comprising a capacitor in the metallization system and a method of forming the capacitor: By forming metal capacitors in the metallization structures of semiconductor devices, complex manufacturing sequences in the device level may be avoided. The process of manufacturing the metal capacitors may be performed on the basis of well-established patterning regimes of modern metallization systems by using appropriately selected etch stop materials, which... Agent: Williams, Morgan & Amerson

20090194844 - Substrate contact for advanced soi devices based on a deep trench capacitor configuration: By forming a first portion of a substrate contact in an SOI device on the basis of a trench capacitor process, the overall manufacturing process for patterning contact elements may be enhanced since the contacts may only have to extend down to the level of the semiconductor layer. Since the... Agent: Williams, Morgan & Amerson

20090194846 - Fully cu-metallized iii-v group compound semiconductor device with palladium/germanium/copper ohmic contact system: The present invention discloses a fully Cu-metallized III-V group compound semiconductor device, wherein the fully Cu-metallized of a III-V group compound semiconductor device is realized via using an N-type gallium arsenide ohmic contact metal layer formed of a palladium/germanium/copper composite metal layer, a P-type gallium arsenide ohmic contact metal layer... Agent: Sinorica, LLC

20090194847 - A1xga yin 1-x-yn crystal substrate, semiconductor device, and method of manufacturing the same: An AlxGayIn1-x-yN crystal substrate of the present invention has a main plane having an area of at least 10 cm2. The main plane has an outer region located within 5 mm from an outer periphery of the main plane, and an inner region corresponding to a region other than the... Agent: Drinker Biddle & Reath (dc)

20090194848 - Method for manufacturing gallium nitride crystal and gallium nitride wafer: There is provided a method for fabricating a gallium nitride crystal with low dislocation density, high crystallinity, and resistance to cracking during polishing of sliced pieces by growing the gallium nitride crystal using a gallium nitride substrate including dislocation-concentrated regions or inverted-polarity regions as a seed crystal substrate. Growing a... Agent: Drinker Biddle & Reath (dc)

20090194849 - Methods and apparatus for manufacturing semiconductor wafers: Methods and apparatus for fabricating a semiconductor sheet are provided. In one aspect, a method for fabricating a semiconductor wafer includes applying a layer of semiconductor material across a portion of a setter material, introducing the setter material and the semiconductor material to a predetermined thermal gradient to form a... Agent: John S. Beulick (17851) Armstrong Teasdale LLP

20090194850 - Crack stops for semiconductor devices: Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped... Agent: Slater & Matsil LLP

20090194851 - Semiconductor device packages with electromagnetic interference shielding: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element disposed adjacent to a periphery of the substrate unit; (2) a semiconductor device disposed adjacent to an upper surface of the substrate... Agent: Cooley Godward Kronish LLP Attn: Patent Group

20090194852 - Semiconductor device packages with electromagnetic interference shielding: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) a grounding element disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a... Agent: Cooley Godward Kronish LLP Attn: Patent Group

20090194853 - Shielded stacked integrated circuit packaging system and method of manufacture thereof: A method of manufacture of a shielded stacked integrated circuit packaging system includes forming a first integrated circuit structure having a first substrate and a first integrated circuit die; mounting a shield over the first substrate and the first integrated circuit die; mounting a second integrated circuit structure having a... Agent: Law Offices Of Mikio Ishimaru

20090194855 - Folded leadframe multiple die package: A multiple die package includes a folded leadframe for interconnecting at least two die attached to another leadframe. In a synchronous voltage regulator the folded leadframe, which is formed from a single piece of material, connects the high side switching device with the low side switching device to provide a... Agent: Hiscock & Barclay, LLP

20090194854 - Semiconductor device package and method of making a semiconductor device package: A method of manufacturing an electronic device is provided. The method comprises providing a carrier sheet, etching the lead frame material sheet to form a recess on a first surface of the lead frame material sheet, placing an electronic chip into the recess of the carrier sheet, and thereafter, selectively... Agent: Dicke, Billig & Czaja

20090194856 - Molded package assembly: A semiconductor die package is disclosed. The semiconductor die package is suitable for mounting on a circuit substrate such as a circuit board. The semiconductor die package comprises a leadframe structure and a semiconductor die coupled to the leadframe structure. A plurality of first conductive structures is attached to the... Agent: Townsend And Townsend And Crew, LLP

20090194858 - Hybrid carrier and a method for making the same: The present invention relates to a hybrid carrier and a method for making the same. The hybrid carrier has a plurality of interconnection leads, so that a wire bondable semiconductor device or a flip chip die apparatus can be placed on the hybrid carrier, and is electrically connected to die... Agent: Volentine & Whitt PLLC

20090194859 - Semiconductor package and methods of fabricating the same: Provided is a semiconductor package having a power device and methods of fabricating the same. The semiconductor package includes a lead frame, a polymer layer component on the lead frame, a metal layer component on the polymer layer component, and a semiconductor chip on the metal layer component. The polymer... Agent: Hiscock & Barclay, LLP

20090194857 - Thin compact semiconductor die packages suitable for smart-power modules, methods of making the same, and systems using the same: Disclosed are semiconductor die packages, methods of making them, and systems incorporating them. An exemplary package comprises a first substrate, a second substrate, a semiconductor die disposed between the first and second substrates, and an electrically conductive member disposed between the first and second substrates. The semiconductor die has a... Agent: Townsend And Townsend And Crew, LLP

20090194860 - Chip housing having reduced induced vibration: A premold housing for accommodating a chip structure includes a first part of the housing which is connected to the chip structure as well as connected in an elastically deflectable manner to an additional part of the housing which is fastened to the support structure bearing the entire housing. A... Agent: Kenyon & Kenyon LLP

20090194861 - Hermetically-packaged devices, and methods for hermetically packaging at least one device at the wafer level: A plurality of devices are hermetically packaged at the wafer level by 1) providing a substrate wafer having a plurality of at least partially-formed devices thereon; 2) forming separation walls on the substrate wafer, around different ones of the at least partially-formed devices; and 3) wafer bonding a cap wafer... Agent: Agilent Technologies Inc.

20090194862 - Semiconductor module and method of manufacturing the same: There is provided a semiconductor module having improved heat radiation efficiency. A semiconductor module includes a semiconductor element, a pair of Cu heat radiating plates sandwiching the semiconductor element, insulating and heat radiating plates sandwiching the Cu heat radiating plates, heat radiating fins sandwiching the insulating and heat radiating plates,... Agent: Sughrue Mion, PLLC

20090194863 - Semiconductor package and method for making the same: A semiconductor package includes: a semiconductor substrate; an inner insulator layer formed on the substrate; at least one internal wiring extending from a front side of the substrate along one of lateral sides of the substrate to a rear side of the substrate; a first outer insulator layer disposed at... Agent: Christie, Parker & Hale, LLP

20090194864 - Integrated module for data processing system: An apparatus for an integrated module. A silicon carrier with through-silicon vias has a plurality of die connected to a top side of the silicon carrier. In addition, a substrate is connected to a bottom side of the silicon carrier. The substrate is coupled to the plurality of die via... Agent: Duke W. Yee

20090194865 - Method for manufacturing a semiconductor device, method for detecting a semiconductor substrate and semiconductor chip package: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface... Agent: Gregory Turocy Amin, Turocy & Calvin, LLP

20090194866 - Semiconductor device having wiring line and manufacturing method thereof: An insulating film covering the upper surface of an external connection electrode of a semiconductor construct is formed. A mask metal layer in which there is formed an opening having a planar size smaller than that of the external connection electrode is formed on the insulating film. The mask metal... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090194867 - Integrated circuit package system with internal stacking module adhesive: An integrated circuit package system comprising: providing a substrate; forming a base assembled package over the substrate; forming a top package over the base assemble package; and applying a top package stacking material for stand-off or insulation to the base assembled package and the top package.... Agent: Law Offices Of Mikio Ishimaru

20090194869 - Heat sink package: The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip... Agent: Hiscock & Barclay, LLP

20090194868 - Panel level methods and systems for packaging integrated circuits with integrated heat sinks: Panel level methods and arrangements are described for attaching heat sinks in panel form with dice attached to a leadframe panel. Various methods produce integrated circuit packages each having an exposed heat sink on one outer surface of the package and an exposed die attach pad on a second opposite... Agent: Beyer Law Group LLP/ Nsc

20090194870 - Method and apparatus for solid state cooling system: The disclosure relates to a Point Cooler based on a combination of principles, including large area, low current density PN junction cooling, and electron emission from heavily doped shallowly-depleted P tips. Using Junction Cooling rather than thermoelectric cooling enables an all silicon device to be made that favorably competes with... Agent: Snell & Wilmer L.L.P. (grumman)

20090194871 - Semiconductor package and method of attaching semiconductor dies to substrates: A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to... Agent: Sughrue Mion, PLLC

20090194873 - integrated circuit device and a method of making the integrated circuit device: An integrated circuit device comprises a first semiconductor chip on a first substrate and a second semiconductor chip on a second substrate. A side surface of the first semiconductor chip is facing a side surface of the second semiconductor chip. At least one electric cable is provided to be connecting... Agent: Dicke, Billig & Czaja

20090194872 - Depopulating integrated circuit package ball locations to enable improved edge clearance in shipping tray: Methods, systems, and apparatuses for integrated circuit packages, transport containers, and for transporting integrated circuit packages are provided. A transport container for an integrated circuit package includes a body and a plurality of mounting features. The body has a surface that includes a package receiving region. The plurality of mounting... Agent: Fiala & Weaver, P.l.l.c. C/o Cpa Global

20090194874 - Semiconductor chip package and method for manufacturing thereof: A semiconductor chip package and a method for manufacturing thereof includes sequentially forming upper dielectric layer patterns and lower dielectric patterns over a substrate to expose an underlying metal line such that the lower dielectric layer patterns overlap the metal line, positioning a solder ball over and contacting the lower... Agent: Sherr & Vaughn, PLLC

20090194875 - High purity cu structure for interconnect applications: A structure and method of forming a high purity copper structure for interconnect applications is described. The structure includes a patterned dielectric material and at least one Cu-containing conductive material having an upper surface embedded within the dielectric material; and a diffusion barrier and a noble metal liner separating the... Agent: International Business Machines Corporation Dept. 18g

20090194876 - Interconnect structure and method for cu/ultra low k integration: A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper... Agent: Scully, Scott, Murphy & Presser, P.C.

20090194877 - Semiconductor device having soi structure: A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090194879 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a plurality of first interconnection layers which are provided in an insulating layer and formed in a pattern having a width and space smaller than a resolution limit of an exposure technique, and a second interconnection layer which is provided between the first interconnection layers in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090194878 - Semiconductor device and method for manufacturing the same: The present invention relates to a semiconductor device and a method of manufacture thereof, particularly, to the technology capable of preventing the overlap failure between the metal line and the bit line pad, since the size of the bit line pad can be increased and the height between the bit... Agent: Townsend And Townsend And Crew, LLP

20090194880 - Wafer level chip scale package and process of manufacture: Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.... Agent: Joshua D. Isenberg Jdi Patent

20090194883 - Data line structure in lead region and manufacturing method thereof: An embodiment of the invention provides a data line structure in a lead region of a thin film transistor liquid crystal display (TFT-LCD). The data line structure in the lead region comprises a substrate and a gate layer data line segment, a dielectric layer, a data line lead, and a... Agent: Ladas & Parry LLP

20090194882 - Electronic device: One embodiment provides a method of manufacturing semiconductor devices. For example, a sawn and expanded wafer is utilized having dielectrical material deposited between the diced and deposited chips. The method includes placing at least two chips on a metallic layer, depositing mold material on the metallic layer and between the... Agent: Dicke, Billig & Czaja

20090194881 - Method for manufacturing a wafer level package: A method for manufacturing a wafer level package of an integrated circuit element for direct attachment to a wiring board is disclosed. An integrated circuit element includes input/output pads located on an active side. A non-conductive support structure is formed on the active side of the integrated circuit element in... Agent: Slater & Matsil, L.L.P.

20090194884 - Power semiconductor module including a contact element: A power semiconductor module including a contact element. One embodiment provides an electrically conductive contact element extending in a longitudinal direction and having a first end and a second end lying opposite the first end. The contact element has a first flange at its first end. The first flange is... Agent: Dicke, Billig & Czaja

20090194885 - Semiconductor device having wiring line and manufacturing method thereof: On the lower surface of a semiconductor construct having an external connection electrode, there are formed an insulating film having a planar size greater than that of the semiconductor construct, and a metal layer and a mask metal layer having a connection pad portion in which a first opening corresponding... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090194886 - Pass through via technology for use during teh manufacture of a semiconductor device: Via structures are described which pass through a semiconductor substrate assembly such as a semiconductor die or wafer and allows for two different types of connections to be formed during a single formation process. One connection passes through the wafer without being electrically coupled to the wafer, while the other... Agent: Micron Technology, Inc.

20090194887 - Embedded die package on package (pop) with pre-molded leadframe: A multiple-chip package has top and bottom pre-molded leadframes formed prior to the flip-chip attachment of semiconductor die to the leadframes. After die attachment, underfill is used to encase all but one surface of the die, and the top and bottom leadframes are joined together by solder bump balls with... Agent: Hiscock & Barclay, LLP

20090194888 - Semiconductor device including wiring and manufacturing method thereof: A semiconductor construct is provided which has a semiconductor substrate, an external connection electrode, and an electrode enveloping layer for enveloping the external connection electrode. Also, a base plate is provided which includes a wiring having a first opening corresponding to the external connection electrode. Subsequently, the base plate is... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090194889 - Bond pad structure: A bonding pad structure is provided that includes two conductive layers and a connective layer interposing the two conductive layers. The connective layer includes a contiguous, conductive structure. In an embodiment, the contiguous conductive structure is a solid layer of conductive material. In other embodiments, the contiguous conductive structure is... Agent: Haynes And Boone, LLPIPSection

20090194890 - Integrated circuit and memory module: Embodiments of the invention relate generally to an integrated circuit and a memory module. In an embodiment of the invention, an integrated circuit is provided. The integrated circuit may include a semiconductor carrier including at least one electrically inactive region on an upper surface thereof, a passivation layer structure disposed... Agent: Slater & Matsil, L.L.P.