Active solid-state devices (e.g., transistors, solid-state diodes) inventions 07/09

20090189137 - Non-volatile memory device and method of manufacturing the same: In a phase change memory, electric property of a diode used as a selection device is extremely important. However, since crystal grain boundaries are present in the film of a diode using polysilicon, it involves a problem that the off leak property varies greatly making it difficult to prevent erroneous... Agent: Miles & Stockbridge PC

20090189136 - Semiconductor device and a manufacturing method of the semiconductor device: A reliability of a semiconductor device having a phase-change memory is improved. A phase-change memory device has a bottom-electrode plug buried in an interlayer insulator that is provided on a main surface of a semiconductor substrate, an electric conductive material layer provided on an upper portion of the bottom-electrode plug... Agent: Miles & Stockbridge PC

20090189138 - Fill-in etching free pore device: A memory cell includes a memory cell layer with a first dielectric layer over a bottom electrode layer, a second dielectric layer over the first dielectric layer, and a top electrode over the second dielectric layer. The dielectric layers define a via having a first part bounded by the first... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090189139 - Pore phase change material cell fabricated from recessed pillar: A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating... Agent: Scully, Scott, Murphy & Presser, P.C.

20090189141 - Phase change memory device and method of forming the same: A phase change memory device and a method of forming the same include a conductive pattern formed on a substrate. A lower electrode contact is disposed on the conductive pattern. The phase change pattern is disposed on the lower electrode contact. An upper electrode is disposed on the phase change... Agent: Mills & Onello LLP

20090189142 - Phase-change memory: A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on... Agent: Quintero Law Office, PC

20090189140 - Phase-change memory element: A phase-change memory element with side-wall contacts is disclosed. The phase-change memory element comprises a bottom electrode. A first dielectric layer is formed on the bottom electrode. A first electrical contact is formed on the first dielectric layer and electrically connects to the bottom electrode. A second dielectric layer is... Agent: Quintero Law Office, PC

20090189144 - Device for absorbing or emitting light and methods of making the same: A device disclosed herein includes a first layer, a second layer, and a first plurality of nanowires established between the first layer and the second layer. The first plurality of nanowires is formed of a first semiconductor material. The device further includes a third layer, and a second plurality of... Agent: Hewlett Packard Company

20090189143 - Nanotube array electronic and opto-electronic devices: Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The discussed electronic and photonic devices and circuits rely on the nanotube arrays grown on a variety of substrates, such as glass or Si wafer. The planar, multiple layer deposition technique and simple methods of change of the nanotube... Agent: Alexander Kastalsky

20090189145 - Photodetectors, photovoltaic devices and methods of making the same: A photodetector includes a first layer, a second layer and a plurality of nanowires established between the first and second layers. At least some of the plurality of nanowires have a bandgap that is different from a bandgap of at least some other of the plurality of nanowires.... Agent: Hewlett Packard Company

20090189146 - Multifinger carbon nanotube field-effect transistor: A multifinger carbon nanotube field-effect transistor (CNT FET) is provided in which a plurality of nonotube top gated FETs are combined in a finger geometry along the length of a single carbon nanotube, an aligned array of nanotubes, or a random array of nanotubes. Each of the individual FETs are... Agent: Greenberg Traurig LLP (la)

20090189149 - Composition for producing insulator and organic insulator using the same: Disclosed herein is a composition for producing an insulator. More specifically, the composition comprises a silane-based organic-inorganic hybrid material containing one or more multiple bonds, an acrylic organic crosslinking agent and a silane-based crosslinking agent having six or more alkoxy groups. Also disclosed herein is an organic insulator produced using... Agent: Harness, Dickey & Pierce, P.L.C

20090189152 - Ferroelectric memory device: Provided is a ferroelectric memory device. The ferroelectric memory device includes an inorganic channel pattern on a substrate, a source electrode and a drain electrode spaced apart from each other on the substrate and contacting the inorganic channel pattern, a gate electrode disposed adjacent to the inorganic channel pattern, and... Agent: F. Chau & Associates, LLC

20090189151 - Method for separating a non-emission region from a light emission region within an organic light emitting diode (oled): The present invention relates to a method for separating at least one non-emission region (16) from at least one emission region (15) within an organic light emitting diode (OLED) (1), which comprises a substrate material (10) as a carrier, whereas the substrate material (10) is coated and/or superimposed by at... Agent: Philips Intellectual Property And Standards

20090189150 - Organic semiconducting copolymer and organic electronic device including the same: An organic electronic device may include the above organic semiconducting copolymer. The organic semiconducting copolymer according to example embodiments may provide improved solubility, processability, and thin film properties. Consequently, the organic semiconducting copolymer may be used in a variety of electronic devices. A suitable electronic device may be an organic... Agent: Harness, Dickey & Pierce, P.L.C

20090189147 - Organic transistor comprising a self-aligning gate electrode, and method for the production thereof: An unpatterned semiconductor layer is applied to a substrate for the production of an organic transistor. An insulator is arranged on the semiconductor layer wherein at least the insulator layer is patterned, so that at least source and drain electrode layers can be formed subsequently. The source and drain electrode... Agent: Carella, Byrne, Bain, Gilfillan, Cecchi, Stewart & Olstein

20090189148 - Transistor element, display device and these manufacturing methods: A transistor element that a transistor using an organic semiconductor layer on a substrate, an insulating film between layers contacting the organic semiconductor layer and an upper electrode electrically contacting the transistor via a through hole provided in the insulating film between layers are layered, wherein the insulating film between... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090189153 - Field-effect transistor: Disclosed herein is a field-effect transistor comprising a channel comprised of an oxide semiconductor material including In and Zn. The atomic compositional ratio expressed by In/(In+Zn) is not less than 35 atomic % and not more than 55 atomic %. Ga is not included in the oxide semiconductor material or... Agent: Fitzpatrick Cella Harper & Scinto

20090189155 - Semiconductor device and manufacturing method thereof: To provide a semiconductor device in which a defect or fault is not generated and a manufacturing method thereof even if a ZnO semiconductor film is used and a ZnO film to which an n-type or p-type impurity is added is used for a source electrode and a drain electrode.... Agent: Nixon Peabody, LLP

20090189156 - Semiconductor device and manufacturing method thereof: To provide a semiconductor device in which a defect or fault is not generated and a manufacturing method thereof even if a ZnO semiconductor film is used and a ZnO film to which an n-type or p-type impurity is added is used for a source electrode and a drain electrode.... Agent: Nixon Peabody, LLP

20090189154 - Zno nanostructure-based light emitting device: A Light Emitting Diode (LED) formed on a substrate of a material selected from at least one of a semiconductor, an insulator and a metal; at least one semiconductor film layer of ZnO or GaN deposited on the substrate; a nanotips array of ZnO or its ternary compound, the array... Agent: Fox Rothschild LLP Princeton Pike Corporate Center

20090189157 - Device for measuring or inspecting substrates of the semiconductor industry: A device for measuring or inspecting substrates of the semiconductor industry, including a base frame and a module detachably mounted thereon via a module frame, wherein the module frame is detachably connected to the base frame via at least two self-aligning coupling elements and at least one alignment element, wherein... Agent: Simpson & Simpson, PLLC

20090189158 - Semiconductor device: A semiconductor device includes a wring board having a first surface with external connection terminals and a second surface with internal connection terminals. On the second surface of the wiring board, a semiconductor chip having electrode pads is mounted. The electrode pads of the semiconductor chip and the internal connection... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090189159 - Gettering layer on substrate: Disclosed herein are devices, methods and systems for implementing gettering layers. Devices including gettering layers can be implemented such that a gettering layer doped with carbon, boron, fluorine or any other appropriate impurity is formed on a semiconductor substrate, a device layer is formed on the gettering layer, and a... Agent: Fish & Richardson P.C.

20090189160 - Thin film transistor, method of fabricating the same, and organic light emitting diode display device having the tft: A thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device having the TFT, the TFT including a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate electrode, a semiconductor layer disposed on the... Agent: Stein Mcewen, LLP

20090189161 - Light emitting device: While suppressing the frequency of a signal line driver circuit, a blur of a moving image of a light-emitting device using a light-emitting transistor can be prevented, without reducing a frame frequency. A switching element is provided in a path of a current which flows between a source and a... Agent: Cook Alex Ltd.

20090189162 - Organic light emitting diode display device and method of fabricating the same: An organic light emitting diode display device to display a main image and a sub-image, such as background, illumination, or the like, without additional processes or a reduction in the resolution of the image, and a method of fabricating the same, the organic light emitting diode display device including: a... Agent: Stein Mcewen, LLP

20090189163 - Thin film transistor array substrate: A TFT array substrate includes a substrate, a patterned first metallic layer, a patterned stack layer, a patterned dielectric layer, a patterned transparent conductive layer, and a patterned third metallic layer. Elements of each TFT in the TFT array substrate are arranged vertically, so that the TFT array substrate has... Agent: Jianq Chyun Intellectual Property Office

20090189164 - Uniform large-grained and grain boundary location manipulated polycrystalline thin film semiconductors formed using sequential lateral solidification and devices formed thereon: Methods for processing an amorphous silicon thin film sample into a polycrystalline silicon thin film are disclosed. In one preferred arrangement, a method includes the steps of generating a sequence of excimer laser pulses, controllably modulating each excimer laser pulse in the sequence to a predetermined fluence, homoginizing each modulated... Agent: Baker Botts L.L.P.

20090189166 - Light emitting device having a plurality of light emitting cells and method of fabricating the same: Disclosed is a light emitting device having a plurality of light emitting cells. The light emitting device comprises a thermally conductive substrate, such as a SiC substrate, having a thermal conductivity higher than that of a sapphire substrate. The plurality of light emitting cells are connected in series on the... Agent: H.c. Park & Associates, PLC

20090189165 - Light-emitting diode light source: An LED light source comprises a lower substrate having an upper surface which is formed with a groove and covered with an insulating layer in an area outside the groove, wherein the insulating layer is partially covered with a metal layer; an upper substrate disposed on a top of the... Agent: Young & Thompson

20090189167 - Light emitting device with high light extraction efficiency: An exemplary solid-state light emitting device includes a substrate, a light emitting structure, a first electrode and a second electrode have opposite polarities with each other. The light emitting structure includes a first-type semiconductor layer, a second-type semiconductor layer and an active layer between the first-type semiconductor layer and the... Agent: PCe Industry, Inc. Att. Steven Reiss

20090189170 - Light emitting diode: A light emitting diode includes a casing, comprising a concave accommodation space; a lead frame, disposed in the casing, wherein the lead frame has at least two individual leads which extend into the accommodation space; a light emitting chip, disposed in the accommodation space and electrically connected to the leads;... Agent: Rosenberg, Klein & Lee

20090189169 - Light emitting diode lamp: A light emitting diode lamp includes a heat sink, a socket, a light emitting module, a holder and a lens. The socket and the holder are respectively positioned opposite sides of the heat sink. The light emitting module is combined with the heat sink and has a light emitting diode... Agent: Rosenberg, Klein & Lee

20090189171 - Light emitting diode package: An LED package includes a housing, a substrate, a pad frame and an LED chip. The housing includes a plastic material, and has a recess with an opening at a top of the housing. The substrate includes substantially the same material with the housing. The pad frame includes conductive material,... Agent: The Nath Law Group

20090189172 - Light emitting diode with higher illumination efficiency: A light emitting diode (LED) with higher illumination efficiency is revealed. The LED includes a LED chip and an optical layer arranged on the bottom of the LED chip. The optical layer is a light-guiding layer, a light reflective layer or an energy-conversion layer that increases light emitting efficiency of... Agent: Sinorica, LLC

20090189173 - Semiconductor device and method of manufacturing thereof: To provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the... Agent: Nixon Peabody, LLP

20090189168 - White light emitting device: A white light emitting device is provided, which includes a light emitting element that emits a first light having a wavelength between 300 nm and 410 nm; and a fluorescent layer positioned over the light emitting element. The fluorescent layer includes a fluorescent whitening agent capable of absorbing at least... Agent: Lin & Associates Intellectual Property, Inc.

20090189178 - Leadframe having a heat sink supporting part, fabricating method of a light emitting diode package using the same, and light emitting diode package fabricated by the method: Disclosed are a leadframe having heat sink supporting parts, a light emitting diode package in which the leadframe is employed, and a fabricating method of a light emitting diode package using the leadframe. The leadframe includes an outer frame surrounding a predetermined region. The heat sink supporting parts extend inward... Agent: H.c. Park & Associates, PLC

20090189174 - Light emitting diode package: A light-emitting diode (“LED”) package is disclosed. The LED package includes a substrate, a pad frame, an LED chip and a housing. The pad frame includes a conductive lead divided by insulation materials on the substrate. The LED chip is mounted on the conductive lead. The housing surrounds the LED... Agent: The Nath Law Group

20090189177 - Light emitting diode package and manufacturing method thereof: Disclosed are a light emitting diode package and a manufacturing method thereof. According to an embodiment of the present invention, the method includes: manufacturing a package main body having a plurality of cavities, the cavities being formed in a line on one surface, through molding by putting thermoplastic polymer into... Agent: Staas & Halsey LLP

20090189176 - Light-emitting diode package: Disclosed is a light-emitting diode package. The light-emitting diode package includes an electrode pad on which a chip is placed; a housing having a window through which the chip is exposed; a housing wall defining the window; and an electrode lead extended from the electrode pad in a direction of... Agent: The Nath Law Group

20090189175 - Side view type light emitting diode package: Disclosed is a side view light emitting diode (LED) package whose light emitting surface has been relatively expanded. The LED package includes a housing and a lead frame extended externally through the housing and bent in a direction of the recessed space. The housing includes a reflecting housing having a... Agent: The Nath Law Group

20090189179 - Method for manufacturing light emitting diode package: A method for manufacturing flip-chip light emitting diode (LED) package. A recess array is formed at the top surface of a silicon wafer. Two through-wafer via holes are formed in the recess. A plurality of LED chips are flip-chip mounted in each of the recesses, respectively. Two electrodes of each... Agent: Hdls Patent & Trademark Services

20090189180 - Silicone resin composition: A silicone resin composition is provided, which includes polysiloxane including (PSA1), (PSA2), (PSB) and (PSC), and a hydrosilylating catalyst, wherein a weight ratio between (PSA2) and (PSA1) (w2/w1) is 0.03-0.2:... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090189181 - Semiconductor device having insulated gate semiconductor element, and insulated gate bipolar transistor: A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a... Agent: Posz Law Group, PLC

20090189183 - Dual triggered silicon controlled rectifier: The present invention provides a dual triggered silicon controlled rectifier (DTSCR) including: a semiconductor substrate, an N-well, a P-well, a first N+ diffusion region and a first P+ diffusion region, a second N+ diffusion region and a second P+ diffusion region; a third P+ diffusion region, positioned in one side... Agent: North America Intellectual Property Corporation

20090189182 - Integrated rf esd protection for high frequency circuits: The invention relates to a high-frequency integrated circuit requiring ESD protection for a circuit node. One or more metallic layer is deposited within the integrated circuit and patterned to form a transmission line. The metallic layers are generally already present in the integrated circuit for signal routing. The transmission line... Agent: Slater & Matsil LLP

20090189185 - Epitaxial growth of relaxed silicon germanium layers: A relaxed silicon germanium structure comprises a silicon buffer layer produced using a chemical vapor deposition process with an operational pressure greater than approximately 1 torr. The relaxed silicon germanium structure further comprises a silicon germanium layer deposited over the silicon buffer layer. The silicon germanium layer has less than... Agent: Knobbe, Martens, Olson & Bear LLP

20090189184 - Semiconductor-on-diamond devices and associated methods: Semiconductor-on-diamond (SOD) substrates and methods for making such substrates are provided. In one aspect, a method of making an SOD substrate may include depositing a base layer onto a lattice-orienting silicon (Si) substrate such that the base layer lattice is substantially oriented by the Si substrate, depositing a semiconductor layer... Agent: Thorpe North & Western, LLP.

20090189187 - Active area shaping for ill-nitride device and process for its manufacture: A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same.... Agent: Farjami & Farjami LLP

20090189186 - Group iii nitride semiconductor device and epitaxial substrate: Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be reduced. In a high electron mobility transistor 11, a supporting substrate 13 is composed of AlN, AlGaN, or GaN, specifically. An AlYGa1−YN epitaxial layer 15 has a full-width-at-half maximum of (0002) plane XRD... Agent: Judge Patent Associates

20090189188 - Semiconductor device and fabrication method of the semiconductor device: A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a substrate; a nitride based compound semiconductor layer placed on the substrate and doped with a first transition metal atom; an aluminum gallium nitride layer (AlxGa1-xN) (where 0.1<=x<=1) placed on the nitride based compound semiconductor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090189189 - Semiconductor device and manufacturing method thereof: An exemplary embodiment provides a semiconductor device, in which a junction leakage current is reduced in MISFET including a source/drain impurity layer formed in a semiconductor region containing Ge, and a semiconductor device manufacturing method. The semiconductor device includes a channel region which is formed in a semiconductor substrate; a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090189190 - High electron mobility transistor, field-effect transistor, epitaxial substrate, method of manufacturing epitaxial substrate, and method of manufacturing group iii nitride transistor: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor 11 is provided with a supporting substrate 13 composed of gallium nitride, a buffer layer 15 composed of a first gallium nitride semiconductor, a channel layer 17 composed of a... Agent: Judge Patent Associates

20090189191 - Semiconductor device: A semiconductor device includes a field effect transistor formed of a GaN-based compound semiconductor and having a source electrode, a drain electrode, and a gate electrode, and a diode formed of a semiconductor material having a gandgap energy smaller than a bandgap energy of the GaN-based compound semiconductor. A cathode... Agent: Turocy & Watson, LLP

20090189192 - Deposition of group iii-nitrides on ge: The present invention provides a method for depositing or growing a group III-nitride layer, e.g. GaN layer (5), on a substrate (1), the substrate (1) comprising at least a Ge surface (3), preferably with hexagonal symmetry. The method comprises heating the substrate (1) to a nitridation temperature between 400° C.... Agent: Knobbe Martens Olson & Bear LLP

20090189193 - Selective spacer formation on transistors of different classes on the same device: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors,... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090189194 - Electrostatic discharge (esd) protection circuit placement in semiconductor devices: Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one electrostatic discharge (ESD) protection circuit or a portion thereof... Agent: Slater & Matsil LLP

20090189195 - Radio frequency (rf) circuit placement in semiconductor devices: Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one radio frequency (RF) circuit or a portion thereof is... Agent: Slater & Matsil LLP

20090189196 - Programmable nanotube interconnect: Programmable nanotube interconnect is disclosed. In one embodiment, a method includes forming a interconnect layer using a plurality of nanotube structures, and automatically altering a route of an integrated circuit based on an electrical current applied to at least one of the plurality of nanotube structures in the interconnect layer.... Agent: Lsi Corporation

20090189197 - Solid-state imaging device and imaging apparatus: A solid-state imaging device includes: an imaging region including a plurality of light-receiving parts; a first transfer section provided on the imaging region and transferring, in a first direction, signals generated by the light-receiving parts; a second transfer section provided at a first side of the imaging region and transferring,... Agent: Mcdermott Will & Emery LLP

20090189199 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a semiconductor substrate having, on a surface thereof, a (110) surface of Si1-xGex (0.25≦x≦0.90), and n-channel and p-channel MISFETs formed on the (110) surface, each MISFET having a source region, a channel region and a drain region. Each MISFET has a linear active region which is... Agent: Ohlandt, Greeley Ruggiero & Perle, L.L.P.

20090189198 - Structures of sram bit cells: An SRAM bit cell structure that can be produced in small sizes while maintaining performance is presented. In one configuration, an SRAM bit cell includes driver field effect transistors that are p-type field effect transistors, load field effect transistors that are n-type field effect transistors and transfer gates that are... Agent: Banner & Witcoff, Ltd.

20090189200 - Semiconductor device and fabrication method of the semiconductor device: A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate, and have a plurality of fingers; a gate terminal electrode, a source terminal electrode, and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090189202 - Electronic device including a gate electrode having portions with different conductivity types and a process of forming the same: An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer has a particular conductivity type. The process can also include selectively doping... Agent: Larson Newman Abel & Polansky, LLP

20090189201 - Inward dielectric spacers for replacement gate integration scheme: Inward dielectric spacers for a replacement gate integration scheme are described. A semiconductor device is fabricated by first providing a substrate having thereon a placeholder gate electrode disposed in a dielectric layer. The placeholder gate electrode is removed to from a trench in the dielectric layer. A pair of dielectric... Agent: Applied Materials/bstz Blakely Sokoloff Taylor & Zafman LLP

20090189205 - Semiconductor device and method for manufacturing the same: A semiconductor device having a source electrode and a drain electrode formed over a semiconductor substrate, a gate electrode formed over the semiconductor substrate and disposed between the source electrode and the drain electrode, a protection film made of an insulating material and formed between the source electrode and the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090189203 - Semiconductor device and method of manufacturing the same: A semiconductor device according to an embodiment of the present invention includes a substrate, a gate insulation film formed on the substrate, a gate electrode formed on the gate insulation film, sidewall insulation films provided on side surfaces of the gate electrode, and stress application layers embedded in source and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090189204 - Silicon thin film transistors, systems, and methods of making same: Systems and methods of fabricating silicon-based thin film transistors (TFTs) on flexible substrates. The systems and methods incorporate and combine deposition processes such as chemical vapor deposition and plasma-enhance vapor deposition, printing, coating, and other deposition processes, with laser annealing, etching techniques, and laser doping, all performed at low temperatures... Agent: Patterson, Thuente, Skaar & Christensen, P.A.

20090189206 - Cmos image sensor and method of fabricating the same: A CMOS image sensor and method for fabricating the same, wherein the CMOS image sensor has minimized dark current at the boundary area between a photodiode and an isolation layer. The present invention includes a first-conductivity-type doping area formed in the device isolation area of the substrate, the first-conductivity-type doping... Agent: Mckenna Long & Aldridge LLP

20090189207 - Multicolor photodiode array and method of manufacturing: Novel structures of the photodetector having broad spectral ranges detection capability are provided. The photodetector offers high quantum efficiency>95% over wide spectral ranges, high frequency response>10 GHz (@3 dB). The photodiode array of N×N (or M×N) elements is also provided. The array also offers wide spectral detection ranges ultraviolet to... Agent: Banpil Photonics, Inc.

20090189208 - Multicolor photodiode array and method of manufacturing: Novel structures of the photodetector having broad spectral ranges detection capability are provided. The photodetector offers high quantum efficiency>95% over wide spectral ranges, high frequency response>10 GHz (@3 dB). The photodiode array of N×N (or M×N) elements is also provided. The array also offers wide spectral detection ranges ultraviolet to... Agent: Banpil Photonics, Inc.

20090189209 - Semiconductor memory device: In a full CMOS SRAM having a lateral type cell (memory cell having three partitioned wells arranged side by side in a word line extending direction and longer in the word line direction than in the bit line direction) including first and second driver MOS transistors, first and second load... Agent: Mcdermott Will & Emery LLP

20090189210 - Semiconductor flash memory device and method of fabricating the same: A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20090189211 - Non-volatile memory arrays having dual control gate cell structures and a thick control gate dielectric and methods of forming: Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming are provided. A charge storage layer is etched into strips extending across a substrate surface in a row direction with a tunnel dielectric layer therebetween. The resulting strips may be continuous in the row direction or... Agent: Vierra Magen/sandisk Corporation

20090189212 - Electronic device having a doped region with a group 13 atom: An electronic device includes a memory cell. The memory cell includes a semiconductor region, a first current-carrying electrode adjacent to the semiconductor region, and a first dopant-containing region adjacent to a first current-carrying electrode. The semiconductor region includes a Group 14 atom and the first dopant-containing region includes a Group... Agent: Larson Newman Abel & Polansky, LLP

20090189213 - Nonvolatile semiconductor memory device and method of fabricating the same: A nonvolatile semiconductor memory device includes a semiconductor substrate having a plurality of active regions separately formed by a plurality of trenches formed in a surface of the substrate at predetermined intervals, a first gate insulating film formed on an upper surface of the substrate corresponding to each active region,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090189214 - Semiconductor device and fabrication method for the same: The semiconductor device includes: a plurality of bit lines formed in stripes in a semiconductor substrate of a first conductivity type, each of the bit lines being a diffusion layer of an impurity of a second conductivity type; a plurality of gate insulation films s formed on regions of the... Agent: Mcdermott Will & Emery LLP

20090189215 - Nonvolatile flash memory device and method for producing the same: A method of producing metallic nanocrystals (107) embedded in high-k dielectric material as well as a nonvolatile flash memory device (100) comprising a discrete charge carrier storage layer, the discrete charge carrier storage layer comprising metallic nanocrystals (107) embedded in high-k dielectric material. In the method described in this invention,... Agent: Foley And Lardner LLP Suite 500

20090189216 - Semiconductor component including a drift zone and a drift control zone: Semiconductor component including a drift region and a drift control region. One embodiment provides a drift zone and a drift control zone. A drift control zone dielectric is arranged between the first drift zone and the drift control zone and has at least two sections arranged at a distance from... Agent: Dicke, Billig & Czaja

20090189217 - Semiconductor memory devices including a vertical channel transistor: Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain... Agent: Myers Bigel Sibley & Sajovec

20090189218 - Structure and method for forming power devices with high aspect ratio contact openings: A field effect transistor (FET) includes body regions of a first conductivity type over a semiconductor region of a second conductivity type. Source regions of the second conductivity type extend over the body regions. Gate electrodes extend adjacent to but are insulated from the body regions by a gate dielectric... Agent: Townsend And Townsend And Crew, LLP

20090189219 - Semiconductor device and manufacturing method of the same: The present invention provides a technique capable of attaining an improvement in current detection accuracy in a trench gate type power MISFET equipped with a current detection circuit. Inactive cells are disposed so as to surround the periphery of a sense cell. That is, the inactive cell is provided between... Agent: Mattingly & Malur, P.C.

20090189220 - Power mos transistor device and layout: A power metal-oxide semiconductor (MOS) transistor device is provided. The power MOS transistor device includes a drain region disposed in a substrate, a gate structure layer disposed over the substrate, and enclosing a periphery of the drain region, and a source region formed in the substrate and distributed at an... Agent: Jianq Chyun Intellectual Property Office

20090189221 - Semiconductor device and method for manufacturing semiconductor device: Provided are a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes: a gate electrode formed of polysilicon on a substrate with a gate insulating layer interposed between the gate electrode and the substrate; a source region and a drain region formed on the substrate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090189222 - Semiconductor memory device: A memory includes a U-shape layer on a substrate; a first diffusion layer provided at an upper part of the U-shaped layer; a second diffusion layer provided at a lower part of the U-shaped layer; a body formed at an intermediate portion of the U-shaped layer between the first and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090189223 - Complementary metal gate dense interconnect and method of manufacturing: Complementary metal gate dense interconnects and methods of manufacturing the interconnects is provided. The method comprises forming a first metal gate on a wafer and second metal gate on the wafer. A conductive interconnect material is deposited in a space formed between the first metal gate and the second metal... Agent: Greenblum & Bernstein, P.L.C

20090189224 - Semiconductor device and fabrication process thereof: A semiconductor device includes: an insulated gate field effect transistor of a first conductivity type as a first transistor, the first transistor having a gate insulating film and a gate electrode; and an insulated gate field effect transistor of a second conductivity type opposite to the first conductivity type as... Agent: Robert J. Depke Lewis T. Steadman

20090189225 - Semiconductor device and its fabrication method: A semiconductor device includes a first MIS transistor, and a second MIS transistor having a threshold voltage higher than that of the first MIS transistor. The first MIS transistor includes a first gate insulating film made of a high-k insulating film formed on a first channel region, and a first... Agent: Mcdermott Will & Emery LLP

20090189226 - Electrical fuse circuit: An electrical fuse circuit includes, in addition to an independent power supply switch circuit, a plurality of fuse bit cells, each including a fuse element one end of which is connected to an output of the power supply switch circuit, and a first MOS transistor connected to the other end... Agent: Mcdermott Will & Emery LLP

20090189227 - Structures of sram bit cells: A SRAM bit cell and an associated method of producing the SRAM bit cell with improved performance and stability is provided. In one configuration, channel mobility of the transistors within the SRAM bit cell may be adjusted to provide improved stability. In order to adjust the channel mobility, a stress... Agent: Banner & Witcoff, Ltd.

20090189228 - Semiconductor transistor with p type re-grown channel layer: The invention is a device for controlling conduction across a semiconductor body with a P type channel layer between active semiconductor regions of the device and the controlling gate contact. The device, often a MOSFET or an IGBT, includes at least one source, well, and drift region. The P type... Agent: Summa, Additon & Ashe, P.A.

20090189229 - Semiconductor devices and methods of fabricating the same: Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin... Agent: Mills & Onello LLP

20090189230 - Method and system for packaging mems devices with incorporated getter: Methods and systems for packaging MEMS devices such as interferometric modulator arrays are disclosed. One embodiment of a MEMS device package structure includes a seal with a chemically reactant getter. Another embodiment of a MEMS device package comprises a primary seal with a getter, and a secondary seal proximate an... Agent: Knobbe, Martens, Olson & Bear, LLP

20090189231 - Electromagnectic wave detecting element: The present invention is to provide an electromagnetic wave detecting element that can prevent a decrease in light utilization efficiency at sensor portions. The sensor portions are provided so as to correspond to respective intersection portions of scan lines and signal lines, and have semiconductor layer that generate charges due... Agent: Moss & Burke, PLLC

20090189233 - Cmos image sensor and method for manufacturing same: An optical image sensor is fabricated by forming a pixel array and a peripheral region surrounding the pixel array on a semiconductor substrate, the peripheral region containing peripheral circuitry. An inter-level-dielectric layer is formed over the substrate and a plurality of interconnect wiring layers are formed over the inter-level-dielectric layer.... Agent: Duane Morris LLP (tsmc)IPDepartment

20090189232 - Methods and apparatuses providing color filter patterns arranged to reduce the effect of crosstalk in image signals: Methods and apparatuses providing color filter patterns arranged to reduce cross talk in image signals. The apparatuses include an array of pixels, each pixel having an associated color filter, arranged such that cross-talk is distributed among pixel signals of each color of the color filters.... Agent: Dickstein Shapiro LLP

20090189236 - Solid-state imaging device and method for manufacturing the same: A solid-state imaging device includes: a light-receiving pixel part configured to be formed on a semiconductor substrate; a black-level reference pixel part configured to be formed on the semiconductor substrate; and a multilayer interconnect part configured to be provided over the semiconductor substrate. The multilayer interconnect part includes an insulating... Agent: Robert J. Depke Lewis T. Steadman

20090189235 - Solid-state imaging device, manufacturing method for the same, and imaging apparatus: A solid-state imaging device having a light-receiving section that photoelectrically converts incident light includes an insulating film formed on a light-receiving surface of the light-receiving section and a film and having negative fixed charges formed on the insulating film. A hole accumulation layer is formed on a light-receiving surface side... Agent: Sonnenschein Nath & Rosenthal LLP

20090189234 - Solid-state imaging device, production method of the same, and imaging apparatus: In a solid-state imaging device, the pixel circuit formed on the first surface side of the semiconductor substrate is shared by a plurality of light reception regions. The second surface side of the semiconductor substrate is made the light incident side of the light reception regions. The second surface side... Agent: Sonnenschein Nath & Rosenthal LLP

20090189237 - Solid-state imaging element: The present invention provides a solid-state imaging element including: a silicon layer having a photodiode formed therein and a positive charge accumulation region formed on the surface thereof; and an optical waveguide formed above the photodiode to guide incident light into the photodiode, wherein an insulating layer is formed in... Agent: Sonnenschein Nath & Rosenthal LLP

20090189238 - Packaged microelectronic imagers and methods of packaging microelectronic imagers: Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried... Agent: Dickstein Shapiro LLP

20090189239 - Thermoelectric module: A thermoelectric module has a first substrate, a second substrate spaced from the first substrate, a plurality of P type thermoelectric elements and N type thermoelectric elements arranged in the space between the first and second substrates, and a plurality of electrodes which connect the P type and N type... Agent: Procopio, Cory, Hargreaves & Savitch LLP

20090189240 - Semiconductor device with at least one field plate: A semiconductor component with at least one field plate. One embodiment provides the field plate to make contact with the semiconductor body at a connection contact. The semiconductor body has in the region of the connection contact a doping concentration that is less than 5·1017 cm−3.... Agent: Dicke, Billig & Czaja

20090189241 - Using floating fill metal to reduce power use for proximity communication: One embodiment of the present invention provides a system that facilitates reducing the power needed for proximity communication. This system includes an integrated circuit with an array of transmission pads that transmit a signal using proximity communication. A layer of fill metal is located in proximity to this array of... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20090189242 - Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices: Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090189243 - Semiconductor device with trench isolation structure and method for fabricating the same: The present invention relates to a semiconductor device with a device isolation structure and a method for fabricating the same. The semiconductor device includes: a substrate provided with a trench formed in the substrate; and at least one device isolation structure including an oxide layer formed on the trench, a... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090189244 - Integrated circuit devices and methods and apparatuses for designing integrated circuit devices: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC... Agent: Synopsys, Inc./bstz Blakely Sokoloff Taylor & Zafman LLP

20090189245 - Semiconductor device with seal ring: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090189246 - Method of forming trench isolation structures and semiconductor device produced thereby: A method for forming a trench isolation structure and a semiconductor device are provided. The method comprises the following steps: forming a patterned mask on a semiconductor substrate; defining a trench with a predetermined depth D by using the patterned mask, wherein the trench has a bottom and a side... Agent: Holland & Knight LLP

20090189247 - Semiconductor device: An active barrier structure has a p-type region and an n-type region, each of which is in contact with a p-type impurity region and which are ohmic-connected to each other to attain a floating potential. A trench isolation structure is formed between an active barrier region and the other region... Agent: Mcdermott Will & Emery LLP

20090189248 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises an active region formed in a semiconductor substrate and a gate electrode formed on the active region via a gate insulating film formed on a surface of the active region. A peripheral portion of the gate electrode and a peripheral portion of the active region overlap... Agent: Young & Thompson

20090189250 - Semiconductor device and a method of manufacturing the same: A capacitor has an MIM (Metal Insulator Metal) structure comprising a lower electrode formed in the interior of an electrode trench which is formed in an interlayer insulating film, a dielectric film formed over the lower electrode, and an upper electrode formed over the dielectric film. The upper electrode and... Agent: Miles & Stockbridge PC

20090189249 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a first and second structures formed in a first insulating layer, a lower metal interconnection formed in the second structure, a metal-insulator-metal (MIM) capacitor formed in the first structure, and first, second and third electrodes formed in the first structure and electrically connected to the MIM... Agent: Sherr & Vaughn, PLLC

20090189251 - Capacitor formation for a pumping circuit: A capacitor structure for a pumping circuit includes a substrate, a U-shaped bottom electrode in the substrate, a T-shaped top electrode in the substrate and a dielectric layer disposed between the U-shaped bottom and T-shaped top electrode. The contact area of the capacitor structure between the U-shaped bottom and T-shaped... Agent: North America Intellectual Property Corporation

20090189252 - Iii-v mosfet fabrication and device: A semiconductor fabrication process includes forming a gate dielectric layer (120) overlying a substrate (101) that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure (121) that has a substantially vertical sidewall (127), e.g., a slope of approximately 45° to 90°. A... Agent: Fsi C/o Jackson Walker, LLP

20090189253 - Method of producing a nitride semiconductor device and nitride semiconductor device: AlxInyGa1-x-yN(0≦x≦1; 0≦x≦1; 0≦x+y≦1) layered device chips are produced by the steps of preparing a defect position controlled substrate of AlxInyGa1-x-yN(0≦x≦1; 0≦y≦1; 0≦x+y≦1) having a closed loop network defect accumulating region H of slow speed growth and low defect density regions ZY of high speed growth enclosed by the closed loop... Agent: Mcdermott Will & Emery LLP

20090189254 - Circuit connection structure, method for producing the same and semiconductor substrate for circuit connection structure: A circuit connection structure that exhibits excellent adhesiveness between a heat resistant resin film and a circuit adhesive member, even under high temperature and high humidity, is provided by introducing a chemically stable functional group into the heat resistant resin film by additional surface treatment to improve adhesiveness. In a... Agent: Griffin & Szipl, PC

20090189255 - Wafer having heat dissipation structure and method of fabricating the same: A wafer having a heat dissipation structure is provided. The wafer having the heat dissipation structure includes a wafer and a number of metallic heat dissipation parts. The wafer has a first surface and a second surface opposite thereto. Besides, a number of blind holes are formed on the second... Agent: J C Patents, Inc.

20090189256 - Manufacturing process of semiconductor device and semiconductor device: After forming a ring-shaped trench penetrating through a semiconductor substrate from a rear surface side thereof and forming an insulating film inside the trench and on the rear surface of the semiconductor substrate, a through hole is formed in the insulating film and semiconductor substrate on an inner side of... Agent: Mattingly & Malur, P.C.

20090189257 - Mesa type semiconductor device and manufacturing method thereof: A mesa type semiconductor device and its manufacturing method are offered to increase a withstand voltage as well as reducing a leakage current. An N−-type semiconductor layer is formed on a surface of a semiconductor substrate, and a P-type semiconductor layer is formed on the N−-type semiconductor layer. After that,... Agent: Morrison & Foerster LLP

20090189258 - Method of integrated circuit fabrication: A method for fabricating an integrated circuit including forming a first trench in a rear side of a semiconductor wafer, wherein the first trench has a depth extending partially through a thickness of the semiconductor wafer, coating the rear side with a layer of coating material, including filling the first... Agent: Dicke, Billig & Czaja

20090189259 - Electronic device and method of manufacturing: An electronic device and method of manufacturing. One embodiment includes attaching a first semiconductor chip to a first metallic clip. The first semiconductor chip is placed over a leadframe after the attachment of the first semiconductor chip to the first metallic clip.... Agent: Dicke, Billig & Czaja

20090189260 - Semiconductor device: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the... Agent: Mattingly & Malur, P.C.

20090189262 - Multiphase synchronous buck converter: Disclosed in this specification is a multiphase buck converter package and process for forming such package. The package includes at least four dies and at least nine parallel leads. The dies are electrically connected through a plurality of die attach pads, thus eliminating the need for wirebonding.... Agent: Hiscock & Barclay, LLP

20090189264 - Semiconductor device and manufacturing method of the same: The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over... Agent: Miles & Stockbridge PC

20090189261 - Ultra-thin semiconductor package: Semiconductor packages with a reduced-height die pad and associated methods for making and using these semiconductor packages are described. The semiconductor packages include a lead frame with die pad of reduced height so the die pad has a height that is less than that of the lead frame. The semiconductor... Agent: Kenneth E. Horton Kirton & Mcconkle

20090189263 - Wiring device for semiconductor device, composite wiring device for semiconductor device, and resin-sealed semiconductor device: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device electrically connects an electrode... Agent: Oliff & Berridge, PLC

20090189265 - Method and apparatus for making semiconductor devices including a foil: A method for manufacturing a semiconductor device including covering a portion of at least one semiconductor device with a foil, including covering at least one target region of the semiconductor device, and illuminating the foil with a laser to singulate from the foil a portion covering the at least one... Agent: Dicke, Billig & Czaja

20090189268 - Method of manufacturing semiconductor device: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package... Agent: Miles & Stockbridge PC

20090189267 - Semiconductor chip with chip selection structure and stacked semiconductor package having the same: A semiconductor chip with a chip selection structure suitable for a stacked semiconductor chip includes a semiconductor chip body and a chip selection structure. The chip selection structure includes a chip selection pad disposed over the semiconductor chip body, a main through electrode electrically connected to the chip selection pad,... Agent: Ladas & Parry LLP

20090189266 - Semiconductor package with stacked dice for a buck converter: Disclosed in this specification is a buck converter package with stacked dice and a process for forming a buck converter. The package includes a die attach pad with a low side die mounted on one surface and a high side die mounted on the opposing surface. The die attach pad... Agent: Hiscock & Barclay, LLP

20090189269 - Electronic circuit package: A electronic circuit package having a flexible substrate with metals layers on one or more of its surfaces forming a wiring pattern and/or surface mount bonding pads. Passive electronic components are integrated onto component packages that are mounted to the flexible substrate and electrically connected with the wiring pattern or... Agent: Wells St. John P.s.

20090189270 - Manufacturing process and structure for embedded semiconductor device: A manufacturing process for an embedded semiconductor device is provided. In the manufacturing process, at least one insulation layer and a substrate are stacked to each other, and a third metal layer is laminated on the insulation layer to embed a semiconductor device in the insulation layer. The substrate has... Agent: J C Patents, Inc.

20090189273 - Multiphase synchronous buck converter: Disclosed in this specification is a multiphase buck converter package and process for forming such package. The package includes at least four dice and several parallel leads. The dice are electrically connected through a plurality of die attach pads, thus eliminating the need for wirebonding.... Agent: Hiscock & Barclay, LLP

20090189271 - Printed circuit board, semiconductor package, card apparatus, and system: A printed circuit board providing high reliability using a packaging of high capacity semiconductor chip, a semiconductor package, and a card and a system using the semiconductor package. The semiconductor package includes a substrate having a first surface and a second surface, a semiconductor chip mounted on the first surface... Agent: Stanzione & Kim, LLP

20090189272 - Wafer level chip scale packages including redistribution substrates and methods of fabricating the same: Provided are wafer level chip scale packages, each having a redistribution substrate in which a pad pitch is improved, and methods of fabricating the same. An exemplary wafer level chip scale package includes a semiconductor chip and a redistribution substrate. The semiconductor chip includes a plurality of pads arranged with... Agent: Townsend And Townsend And Crew, LLP

20090189274 - Tape wiring substrate and tape package using the same: A tape wiring substrate may have dispersion wiring patterns. The dispersion wiring patterns may be provided between input/output wiring pattern groups to compensate for the intervals therebetween. Connecting wiring patterns may be configured to connect the dispersion wiring patterns to a first end of the adjacent input/output wiring pattern.... Agent: Volentine & Whitt PLLC

20090189275 - Integrated circuit package system with wafer scale heat slug: An integrated circuit package system includes: providing a singulated, layered structure equivalent in size to an integrated circuit die and having an adhesive layer, an electrical insulator layer, and a heat slug; attaching the integrated circuit die to a base; attaching bond wires to a top of the base for... Agent: Law Offices Of Mikio Ishimaru

20090189276 - Semiconductor chip and semiconductor device: A semiconductor chip, including: a substrate including an front surface; an integrated circuit formed on the front surface and including a plurality of semiconductor elements; and a heat-radiating plug formed in a region of the substrate corresponding to at least one of the semiconductor elements. The heat-radiating plug is made... Agent: Mcdermott Will & Emery LLP

20090189277 - Photosensitive compositions based on polycyclic polymers for low stress, high temperature films: s

20090189278 - Ultrasonic measuring method, electronic component manufacturing method, and semiconductor package: The waveform signals of ultrasonic waves reflected by a plurality of interfaces in a measurement object are received, the waveform signal of a reflected wave on a reference interface inside the measurement object is detected based on the amplitudes of the received waveform signals, and evaluation is made on the... Agent: Wenderoth, Lind & Ponack L.L.P.

20090189279 - Methods and systems for packaging integrated circuits: Methods of packaging integrated circuits are described. One method relates to attaching a singulated device wafer to a substrate. The singulated device wafer includes a multiplicity of integrated circuit dice arranged in a first configuration. The method also involves a substrate, which includes a sacrificial semiconductor wafer having device areas... Agent: Beyer Law Group LLP/ Nsc

20090189281 - semiconductor package and a method for manufacturing the same: A semiconductor package and a method for manufacturing the same capable of supplying power easily without an increase in the number of pads for power supply. The semiconductor package includes a semiconductor chip having a plurality of pads including pads for power supply disposed in a center portion and an... Agent: Ladas & Parry LLP

20090189280 - Method of forming a non volatile memory device: In one embodiment, a method of forming a semiconductor device is disclosed. A high-k dielectric is deposited of over a semiconductor body, and a portion of the high-k dielectric is wet etched an etchant selected from the group consisting of hot phos, piranha, and SC1.... Agent: Slater & Matsil LLP

20090189283 - Aluminum metal line of a semiconductor device and method of fabricating the same: A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer insulating layer. A photolithography process is performed to form a metal line pattern, and etching is... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090189282 - Semiconductor device: A semiconductor device according to the present invention includes: a low dielectric layer made of a low dielectric material; a high dielectric layer formed on the low dielectric layer and made of a high dielectric material having a higher dielectric constant than the low dielectric material; a protective layer formed... Agent: Rabin & Berdo, PC

20090189284 - Semiconductor device having a reductant layer and manufacturing method thereof: A semiconductor device includes an inter-metal dielectric (IMD) formed on a substrate and having at least one via hole, a via hole formed by filling the via hole with a first metal, a reductant layer formed on the via plug and the inter-metal dielectric to a predetermined thickness, and a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090189285 - On chip thermocouple and/or power supply and a design structure for same: A thermocouple and power supply structure. The structure is interleaved through a substrate. The structure includes a first through via extending through the substrate and connected to a first contact on a top surface and a second contact on a bottom surface of the substrate, through via extending through the... Agent: Schmeiser, Olsen & Watts

20090189286 - Fine pitch solder bump structure with built-in stress buffer: A fine pitch solder bump structure with a built-in stress buffer that is utilized in electronic packages, and a method of producing the fine pitch solder bump structure with built-in stress buffer. Employed is a very thick final passivation layer that is constituted of a polyimide as a so-called “cushion”... Agent: Scully, Scott, Murphy & Presser, P.C.

20090189287 - Noble metal cap for interconnect structures: An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to... Agent: Scully, Scott, Murphy & Presser, P.C.

20090189288 - Angled flying lead wire bonding process: A method is described having the steps of providing a surface having a plurality of wire bondable locations; wire bonding a wire to each of the wire bondable locations using a wire capillary tool; controlling the position of the capillary tool with respect to the substrate; after forming a wire... Agent: Daniel P. Morris IBM Corporation, Intellectual Property Law Dept.

20090189290 - Clustered stacked vias for reliable electronic substrates: A substrate via structure for stacked vias in a substrate/chip assembly includes: a center via stack and a plurality of stacked vias clustered around the center via stack. In this structure, the center via and the surrounding vias are made of copper. Some of the surrounding vias may be non-functional... Agent: Michael Buchenhorner, P.A.

20090189289 - Embedded constrainer discs for reliable stacked vias in electronic substrates: A substrate via structure for stacked vias includes: a plurality of stacked vias, wherein each via is disposed on a landing; and at least one constrainer disc surrounding at least one via, for constraining in-plane deformation of the substrate via structure. The constrainer disc is embedded such that the constrainer... Agent: Michael Buchenhorner, P.A.

20090189292 - Integrated circuit, semiconductor module and method for manufacturing a semiconductor module: Embodiments of the invention relate to a semiconductor, a semiconductor module and to a method for manufacturing a semiconductor module. In an embodiment of the invention, an integrated circuit includes a plurality of connection pads on at least one side of the integrated circuit, which connection pads can be coupled... Agent: Slater & Matsil, L.L.P.

20090189294 - Large area integration of quartz resonators with electronics: Methods for integrating quartz-based resonators with electronics on a large area wafer through direct pick-and-place and flip-chip bonding or wafer-to-wafer bonding using handle wafers are described. The resulting combination of quartz-based resonators and large area electronics wafer solves the problem of the quartz-electronics substrate diameter mismatch and enables the integration... Agent: Ladas & Parry

20090189291 - Multi-chip module: A multi-chip module and method is disclosed. One embodiment provides an electronic module having a first metal structure and a second metal structure. A first semiconductor chip is electrically connected with its back side to the first metal structure. A second semiconductor chip is arranged with its back side lying... Agent: Dicke, Billig & Czaja

20090189293 - Semiconductor device: A semiconductor device having a chip-on-chip structure is constituted of a first semiconductor chip and even-numbered pairs of second semiconductor chips, all of which are laminated together on the surface of an interposer. The first semiconductor chip controls each pair of the second semiconductor chips so as to activate one... Agent: Mcginn Intellectual Property Law Group, PLLC

20090189296 - Flip chip quad flat non-leaded package structure and manufacturing method thereof and chip package structure: A manufacturing method for a Flip Chip Quad Flat Non-leaded package structure is provided. A lead frame having a plurality of leads is provided at first in the manufacturing method. A dielectric layer is formed on the lead frame and exposes a top surface and a bottom surface of the... Agent: Jianq Chyun Intellectual Property Office

20090189297 - Semiconductor device: To provide a semiconductor device having high reliability by reducing the bending of a semiconductor device and mitigating stress exerted on external terminals. In a semiconductor device 1 having a semiconductor chip 9 mounted on a wiring substrate 2 comprising a base member 3 having a predetermined conductive pattern formed... Agent: Mcdermott Will & Emery LLP

20090189295 - Stack chip package structure and manufacturing method thereof: A stack chip package structure and a manufacturing method thereof are disclosed. The method comprises: providing a first substrate; disposing a first chip on the first substrate; disposing a second chip and at least one second substrate on the first chip, wherein the second substrate is electrically connected to the... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090189298 - Bonding pad structure and debug method thereof: The bonding pad structure includes a main bonding pad and a blank path. The blank path crosses through the main bonding pad for dividing the main bonding pad into a first sub-bonding pad and a second sub-bonding pad. The bonding pad structure may further include a solder covered on the... Agent: Chih Feng Yeh Brian M. Mcinnis

20090189299 - Method of forming a probe pad layout/design, and related device: A method of forming a probe pad layout/design, and related device. At least some of the illustrative embodiments are methods comprising testing a semiconductor device by electrically contacting a first portion of a semiconductor die by way of a first pad within a scribe street adjacent to the semiconductor die,... Agent: Texas Instruments Incorporated

20090189300 - Sealing film and a semiconductor device using the same: The present invention provides a sealing film excellent in filling properties and adhesiveness as a sealing film which comprises a resin layer containing the following (A), (B) and (C) and having a flow within the range of 150 to 1800 μm at 80° C.: (A) a resin component containing (a1)... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090184304 - Phase change memory device having plug-shaped phase change layers and method for manufacturing the same: A phase change memory device having plug-shaped phase change layers and a process of manufacturing the same is provided. The device and process includes forming first electrodes on a substrate. An insulation layer is then formed to cover the first electrodes. Plug-shaped phase change layers are then formed in the... Agent: Ladas & Parry LLP

20090184305 - Resistive memory devices and methods of manufacturing the same: A resistive memory device includes a first electrode and a first insulation layer arranged on the first electrode. A portion of the first electrode is exposed through a first hole in the first insulation layer. A first variable resistance layer contacts the exposed portion of the first electrode and extends... Agent: Harness, Dickey & Pierce, P.L.C

20090184308 - Forming an intermediate electrode between an ovonic threshold switch and a chalcogenide memory element: An intermediate electrode between an ovonic threshold switch and a memory element may be formed in the same pore with the memory element. This may have many advantages including, in some embodiments, reducing leakage.... Agent: Trop, Pruner & Hu, P.C.

20090184306 - Phase change memory cell with finfet and method therefor: A phase change memory (PCM) cell includes a transistor, a PCM structure, and a heater. The transistor has a first current electrode and a second current electrode in a structure, and a channel region having a first portion along a first sidewall of the structure and having a second portion... Agent: Freescale Semiconductor, Inc. Law Department

20090184307 - Phase change memory device and method of fabricating the same: A phase change memory device and a method of fabricating the same are provided. A phase change material layer of the phase change memory device is formed of germanium (Ge)-antimony (Sb)-Tellurium (Te)-based Ge2Sb2+xTe5 (0.12≦x≦0.32), so that the crystalline state is determined as a stable single phase, not a mixed phase... Agent: Rabin & Berdo, PC

20090184310 - Memory cell with memory element contacting an inverted t-shaped bottom electrode: Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a top surface and a width less than that of the base portion. A memory element... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090184309 - Phase change memory cell with heater and method therefor: A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structrure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at... Agent: Freescale Semiconductor, Inc. Law Department

20090184311 - Nanowire placement by electrodeposition: Electrodeposition is used to deposit nanowires in a controlled fashion with accurate placement and orientation. A substrate is provided with a mesa having electrically conductive sidewalls. The substrate is immersed in an electroplating solution having a dispersion of nanowires, and metal is electroplated onto the sidewalls of the mesa. During... Agent: Dan Steinberg

20090184312 - Benzofluorene compound and use thereof: (In the formulae, R1 to R4 each independently is a hydrogen atom, a halogen atom, a substituted or unsubstituted amino group, a linear, branched, or cyclic alkyl group, a linear, branched, or cyclic alkoxy group, a substituted or unsubstituted aryl group having 6-40 carbon atoms, or a substituted or unsubstituted... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090184313 - Materials for organic electroluminescent devices: The present invention relates to organic electroluminescent devices, in particular blue-emitting devices, in which compounds of the formulae (1) to (4) are used as host material or dopant in the emitting layer and/or as hole-transport material and/or as electron-transport material.... Agent: Connolly Bove Lodge & Hutz, LLP

20090184314 - Thin film transistor, matrix substrate, electrophoresis display device, and electronic apparatus: Provided is a thin film transistor including a substrate, a source electrode and a drain electrode disposed above the substrate so as to oppose each other, an organic semiconductor film disposed between the source electrode and the drain electrode to generate a channel region, and a gate electrode disposed opposite... Agent: Advantedge Law Group, LLC

20090184315 - Thin film transistor array substrate having improved electrical characteristics and method of manufacturing the same: A thin film transistor array substrate, which can have high mobility of charge and can achieve uniform electrical characteristics for wide display devices, and a method of manufacturing the thin film transistor array substrate, are provided. The thin film transistor array substrate includes an oxide semiconductor layer having a channel... Agent: Haynes And Boone, LLPIPSection

20090184316 - Method to extract gate to source/drain and overlap capacitances and test key structure therefor: A method to extract gate to source/drain and overlap capacitances is disclosed. A first capacitance of a first test key having a reference structure and a second capacitance of a second test key having a novel structure are measured. The second test key may comprise at least a gate formed... Agent: North America Intellectual Property Corporation

20090184317 - Array of mutually insulated geiger-mode avalanche photodiodes, and corresponding manufacturing process: An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type... Agent: Graybeal Jackson LLP

20090184319 - Display substrate and a method of manufacturing the display substrate: A method of manufacturing a display substrate is described. In the method, a gate line and a gate electrode are formed on a base substrate. A source metal layer is formed on the base substrate having the gate line and the gate electrode. A data line, a source electrode and... Agent: Haynes And Boone, LLPIPSection

20090184320 - Method of manufacturing an image tft array for an indirect x-ray sensor and structure thereof: In the image TFT array structure, at least one first line, a lower electrode, a pad electrode, a common electrode and a first electrode connected with the first line are defined simultaneously by etching a first conductive layer. At least one second line intersecting the first line, an upper electrode... Agent: North America Intellectual Property Corporation

20090184318 - Thin film transistor array panel, display device including the same, and method thereof: A thin film transistor (“TFT”) array panel according to an exemplary embodiment of the present invention includes a substrate, a first storage electrode formed on the substrate, a first TFT formed on the substrate and separated from the first storage electrode, a first insulating layer formed on the first storage... Agent: Cantor Colburn, LLP

20090184322 - Electroconductive film-forming method, a thin film transistor, a thin film transistor-provided panel and a thin film transistor-producing method: An electroconductive film having high adhesion and a low resistivity is formed. An electroconductive film composed mainly of copper and containing an addition metal such as Ti is formed by sputtering a target composed mainly of copper in a vacuum atmosphere into which a nitriding gas is introduced. Such an... Agent: Kratz, Quintos & Hanson, LLP

20090184321 - Microcrystalline silicon thin film transistor and method for manufacturing the same: This invention provides a top-gate microcrystalline thin film transistor and a method for manufacturing the same. An inversion layer channel is formed in a top interface of a microcrystalline active layer, and being separated from an incubation layer in a bottom interface of the microcrystalline active layer. The inversion layer... Agent: Birch Stewart Kolasch & Birch

20090184326 - Display substrate, method for manufacturing the display substrate and display apparatus having the display substrate: A display substrate includes a base substrate, a gate line, a gate insulation layer, a data line, a thin-film transistor (TFT) and a pixel electrode. The gate line is extended in a first direction on the base substrate. The gate insulation layer is formed on the base substrate to cover... Agent: Haynes And Boone, LLPIPSection

20090184325 - Method of planarizing substrate, array substrate and method of manufacturing array substrate using the same: A method of planarizing a substrate. An organic layer is formed on a base substrate to cover a metal line formed on the base substrate. A portion of the organic layer is removed to form a pre-planarization layer exposing the metal layer, so that a surface of the base substrate... Agent: Cantor Colburn, LLP

20090184323 - Thin film transistor array panel and method for manufacturing the same: The present invention relates to a thin film transistor array panel and a method for manufacturing the same. A thin film transistor array panel according to the present invention includes a substrate, a light blocking member formed on the substrate and including a first furrow and a receiving portion, a... Agent: Haynes And Boone, LLPIPSection

20090184324 - Thin film transistor array panel and method for manufacturing the same: The present invention relates to a thin film transistor array panel and a manufacturing method thereof. The thin film transistor array panel according to the present invention includes a substrate, a light blocking member formed on the substrate, a gate line disposed on the light blocking member. The gate line... Agent: Haynes And Boone, LLPIPSection

20090184328 - Electrical switching device and method of embedding catalytic material in a diamond substrate: An electrical switching device (30) is disclosed. The device comprises a diamond substrate (24), a cathode (34) in contact with the substrate and having electrically conductive emitters (32) extending into the substrate, and an upper electrode (36) in contact with the substrate and spaced from the cathode.... Agent: Zilka-kotab, PC

20090184327 - Method for producing silicon carbide single crystal: A method for the production of an SiC single crystal includes the steps of growing a first SiC single crystal in a first direction of growth on a first seed crystal formed of an SiC single crystal, disposing the first SiC single crystal grown on the first seed crystal in... Agent: Sughrue Mion, PLLC

20090184330 - Light-emitting module including substrate with space formed around rim: A light-emitting module includes a light-emitting element, a substrate on which are mounted the light-emitting element and heat dissipater. The substrate and heat dissipater are connected together by one mounting member and a space is formed around the rim of the substrate.... Agent: Young & Thompson

20090184329 - Positive electrode for semiconductor light-emitting device: l

20090184331 - Photodetection semiconductor device, photodetector, and image display device: Shields that transmit light to be detected and have conductivity are disposed on light receiving surfaces of photodiodes (1 and 2) to prevent electric charges from being induced to the photodiodes (1 and 2) by electromagnetic waves entered from an external. Two kinds of filters having light transmittance depending on... Agent: Brinks Hofer Gilson & Lione

20090184333 - Light emitting diode device: An LED device includes a substrate, a plurality of LEDs, a first light pervious layer, a reflective plate, and a plurality of phosphor particles contained in the first light pervious layer. The LEDs are electrically mounted on the substrate and configured for emitting light of a first wavelength. The reflective... Agent: PCe Industry, Inc. Att. Steven Reiss

20090184332 - Package structure module with high density electrical connections and method for packaging the same: A package structure module with high density electrical connections includes a drive IC structure, an LED array structure, and a plurality of conductive structures. The drive IC structure has a plurality of first open grooves formed on a lateral wall thereof. The LED array structure has a plurality of second... Agent: Rosenberg, Klein & Lee

20090184335 - Optical semiconductor device: An optical semiconductor device includes: a package having a bottom portion and a sidewall portion; a semiconductor chip having an optical element formed on one surface thereof and having an opposite surface to the one surface fixed to the bottom portion of the package; a transparent member fixed to the... Agent: Mcdermott Will & Emery LLP

20090184334 - Photonic crystal light emitting device and manufacturing method of the same: There is provided a photonic crystal light emitting device including: a light emitting structure including first and second conductivity type semiconductor layers and an active layer interposed therebetween; a transparent electrode layer formed on the second conductivity type semiconductor layer, the transparent electrode layer having a plurality of holes arranged... Agent: Mcdermott Will & Emery LLP

20090184337 - Light-emitting diode, package structure thereof and manufacturing method for the same: A light-emitting diode includes a sapphire substrate, an n-type semiconductor, a light-emitting layer, a p-type semiconductor layer, an anode and a conductive material. The n-type semiconductor layer is formed on the sapphire substrate and has a side surface, a center section and an edge around the center portion. The light-emitting... Agent: Kamrath & Associates P.A.

20090184336 - Semiconductor light emitting device and manufacturing method therefor: A semiconductor light emitting device includes: a semiconductor layer; an insulating film on the semiconductor layer and having an opening; a multilayer adhesive layer on the insulating film; and a Pd electrode in contact with the semiconductor layer through the opening and in contact with the multilayer adhesive layer. The... Agent: Leydig Voit & Mayer, Ltd

20090184338 - Semiconductor device: A semiconductor device having the present high withstand voltage power device IGBT has at a back surface a p collector layer with boron injected in an amount of approximately 3×1013/cm2 with an energy of approximately 50 KeV to a depth of approximately 0.5 μm, and an n+ buffer layer with... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090184339 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: an insulating film provided on a back surface of a semiconductor substrate; a plurality of isolation regions provided to reach the insulating film from a main surface of the semiconductor substrate; at least a first semiconductor layer and a second semiconductor layer which are electrically insulated... Agent: Turocy & Watson, LLP

20090184340 - Semiconductor device and method of producing the same: A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by a snap-back phenomenon. After an MOS gate structure is formed in a front surface of an FZ wafer, a rear surface of the FZ wafer... Agent: Rossi, Kimms & Mcdowell LLP.

20090184341 - Semiconductor device and method of producing the same: A method (and semiconductor device) of fabricating a semiconductor device eliminates shallow trench isolation (STI) recess in embedded SiGe p-type field effect transistor (pFET) structures. This increases device performance by improving isolation and decreasing leakage current caused by SiGe facet growth and silicide encroachment at the STI. A mask is... Agent: Docket Clerk

20090184342 - Method for enhancing growth of semi-polar (al,in,ga,b)n via metalorganic chemical vapor deposition: A method for growing a semi-polar nitride semiconductor thin film via metalorganic chemical vapor deposition (MOCVD) on a substrate, wherein a nitride nucleation or buffer layer is grown on the substrate prior to the growth of the semi-polar nitride semiconductor thin film.... Agent: Gates & Cooper LLP Howard Hughes Center

20090184343 - Isolation structure, non-volatile memory having the same, and method of fabricating the same: A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090184345 - Contacts for cmos imagers and method of formation: Low leakage contacts on leakage sensitive areas of a CMOS imager, such as a floating diffusion region or a photodiode, are disclosed. At least one low leakage polysilicon contact is provided over a leakage sensitive area of a CMOS imager. The polysilicon contact comprises a polysilicon region in direct contact... Agent: Dickstein Shapiro LLP

20090184344 - Solid-state image capturing element, method for manufacturing the solid-state image capturing element, and electronic information device: A solid-state image capturing element according to the present invention is provided, in which one or a plurality of light receiving sections for photoelectrically converting an incident light to generate a signal charge is provided on a surface of a semiconductor area or a surface of a semiconductor substrate and... Agent: Edwards Angell Palmer & Dodge LLP

20090184347 - Coating liquid for gate insulating film, gate insulating film and organic transistor: s

20090184346 - Nonvolatile memory and three-state fets using cladded quantum dot gate structure: The present invention discloses structures and method of fabricating cladded quantum dot gate nonvolatile memory and three-state field-effect transistor devices that can be scaled down to sub-22 nm dimensions and embedded along side with other functional circuits. Another innovation is the design of transport channel, which comprises an asymmetric coupled... Agent: The Law Offices Of Steven Mchugh, LLC

20090184348 - Slim spacer implementation to improve drive current: Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers... Agent: Texas Instruments Incorporated

20090184349 - 3d backside illuminated image sensor with multiplexed pixel structure: A three-dimensional pixel array, a method of manufacturing a pixel array and an imager including the three-dimensional pixel array. The three-dimensional array includes multiple groups of pixels, each group of pixels including a first layer and a second layer. The first layer includes multiple photosensitive elements, one per pixel in... Agent: Ratnerprestia

20090184355 - Integrated circuit arrangement with capacitor and fabrication method: An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20090184350 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel... Agent: Mcginn Intellectual Property Law Group, PLLC

20090184351 - Semiconductor device: A semiconductor device includes a semiconductor substrate, an active region formed in the semiconductor substrate and extending in a first direction, the active region including a transistor sub-region and a capacitor sub-region, a first trench extending around the transistor sub-region, an isolation layer disposed in the first trench, a second... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090184352 - Semiconductor device and method for manufacturing same: A semiconductor device includes: a semiconductor substrate; a lateral MOSFET formed in an upper portion of a first region of the semiconductor substrate; a vertical MOSFET formed in a second region of the semiconductor substrate; a backside electrode formed on a lower surface of the semiconductor substrate and connected to... Agent: Patterson & Sheridan, L.L.P.

20090184353 - Semiconductor device and method of manufacturing the same: To prevent two contacts that have different heights, share at least one interlayer insulating film and are disposed close to each other from being short-circuited to each other due to misalignment thereof, a semiconductor device according to the invention has a recess in an interlayer insulating film in which a... Agent: Sughrue Mion, PLLC

20090184354 - Semiconductor device comprising capacitor and method of fabricating the same: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in... Agent: Mcdermott Will & Emery LLP

20090184356 - Deep trench capacitor in a soi substrate having a laterally protruding buried strap: A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090184357 - Soi based integrated circuit and method for manufacturing: A SOI based integrated circuit and method for manufacturing a SOI based integrated circuit is disclosed. One embodiment provides an integrated circuit having a silicon-on-insulator carrier including a substrate, a buried insulating layer on the substrate and a semiconductor layer on the buried insulating layer. A trench extends at least... Agent: Dicke, Billig & Czaja

20090184358 - Method for fabricating a semiconductor device and the semiconductor device made thereof: A method for fabricating a semiconductor device and the device made thereof are disclosed. In one aspect, the method includes providing a substrate comprising a semiconductor material. The method further includes patterning at least one fin in the substrate, the fin comprising a top surface, at least one sidewall surface,... Agent: Knobbe Martens Olson & Bear LLP

20090184359 - Split-gate non-volatile memory devices having nitride tunneling layers: A memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a first trap-free-nitride layer formed on a channel region of a substrate, a second nitride layer formed on the first nitride layer, an oxide layer formed on the second... Agent: Haynes And Boone, LLPIPSection

20090184360 - Non-volatile memory device and method of fabricating the same: Provided are a non-volatile memory device that may expand to a stacked structure and may be more easily highly integrated and an economical method of fabricating the non-volatile memory device. The non-volatile memory device may include at least one semiconductor column. At least one first control gate electrode may be... Agent: Harness, Dickey & Pierce, P.L.C

20090184362 - Flash memory cell string: o

20090184361 - Lateral charge storage region formation for semiconductor wordline: Devices and methods for forming charge storage regions are disclosed. In one embodiment, a semiconductor device comprises a semiconductor layer having a trench, charge storage layers formed at both side surfaces of the trench, a wordline buried in the trench in contact with the charge storage layers, and source-drain regions... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090184363 - Silicon on insulator device and method for fabricating the same: An SOI device includes an SOI substrate having a structure in which a first buried oxide layer and a silicon layer are stacked in turn over a semiconductor substrate. A gate is formed over the silicon layer of the SOI substrate. A second buried oxide layer is formed at both... Agent: Ladas & Parry LLP

20090184364 - Non-volatile semiconductor storage device and method of manufacturing the same: A non-volatile semiconductor storage device includes device regions and device isolation regions that are formed on a semiconductor substrate, with a first direction defined as their longitudinal direction. The non-volatile semiconductor storage device also includes memory cells having a cell transistor formed on the device regions and a selection transistor... Agent: Gregory Turocy Amin, Turocy & Calvin, LLP

20090184366 - Semiconductor memory device and method for fabricating the same: A semiconductor memory device has a substrate having a semiconductor layer, an n-type semiconductor region formed beneath a main surface of the semiconductor layer, a plurality of cell gates being aligned at a space from each other and including a gate insulating film formed on the main surface of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090184365 - Semiconductor memory device using silicon nitride film as charge storage layer of storage transistor and manufacturing method thereof: A semiconductor memory device includes a tunnel insulating film, charge storage layer, block insulating film and control gate electrode stacked and formed on the surface of a semiconductor substrate. The charge storage layer is formed of an insulating film containing nitrogen. A dopant that reduces the trap density of charges... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090184367 - Semiconductor device manufacturing method, and semiconductor device: A method of manufacturing a semiconductor device in which the formation of buried wiring is facilitated includes: forming columnar patterns, which are arranged in a two-dimensional array, and bridge patterns, which connect the columnar patterns in a column direction, on a main surface of a silicon substrate; injecting an impurity... Agent: Young & Thompson

20090184368 - Ic chip: An IC chip, including a switch LDMOS device and an analog LDMOS device, is configured on a substrate having a first conductive type. Components of the two LDMOS devices respectively include two gate conductive layers configured on two first active regions of the substrate. A common source contact region having... Agent: J C Patents, Inc.

20090184369 - Finfet devices and methods for manufacturing the same: Disclosed herein is a tunneling fin field effect transistor comprising a fin disposed on a box layer disposed in a wafer; the wafer comprising a silicon substrate and a buried oxide layer. The fin comprises a silicide body that comprises a first silicide region and a second silicide region and... Agent: Cantor Colburn LLP - IBM Fishkill

20090184370 - Lateral soi semiconductor devices and manufacturing method thereof: A diode 10 comprises an SOI substrate in which are stacked a semiconductor substrate 20, an insulator film 30, and a semiconductor layer 40. A bottom semiconductor region 60, an intermediate semiconductor region 53, and a surface semiconductor region 54 are formed in the semiconductor layer 40. The bottom semiconductor... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090184371 - Semiconductor device with an soi structure: A first element includes a first diffused layer which is formed in the element forming film so as to reach an insulating film, a second diffused layer which is formed in the element forming film so as not to reach the insulating film, and a first body region formed between... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090184372 - Soi semiconductor components and methods for their fabrication: SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20090184373 - Semiconductor device and method for manufacturing a semiconductor device: A semiconductor device is provided which has a semiconductor substrate. An active cell area having at least one active cell is formed in the semiconductor substrate, wherein at least sections of the active cell area are surrounded by an edge termination region. An integrated gate runner structure is arranged at... Agent: Dickstein Shapiro LLP

20090184374 - Anisotropic stress generation by stress-generating liners having a sublithographic width: A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on... Agent: Scully, Scott, Murphy & Presser, P.C.

20090184375 - Method for forming strained channel pmos devices and integrated circuits therefrom: An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor... Agent: Texas Instruments Incorporated

20090184376 - Semiconductor device and method for fabricating the same: A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second... Agent: Knobbe Martens Olson & Bear LLP

20090184377 - Semiconductor devices and fabrication methods thereof: Semiconductor devices and methods of fabricating semiconductor devices are disclosed. A disclosed semiconductor device includes a silicon substrate, a source region and a drain region. A gate electrode is formed on the silicon substrate. Also, a metal silicide layer is formed on each of the gate electrode, the source region,... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090184378 - Structure and method to fabricate mosfet with short gate: A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor... Agent: Scully, Scott, Murphy & Presser, P.C.

20090184379 - Semiconductor device having dummy gate pattern: A semiconductor device includes a diffusion layer formed on a semiconductor substrate, a gate pattern arranged over the diffusion layer, and a dummy gate pattern arranged adjacently to the gate pattern with a constant gap over the diffusion layer. The gate pattern functions as a gate electrode of a MOS... Agent: Sughrue Mion, PLLC

20090184380 - Metal oxide semiconductor (mos) transistors with increased break down voltages and methods of making the same: A transistor comprises a substrate of a first conductivity type, a drain region and a source region of a second conductivity type, a gate, a gate oxide layer, an adjustment implant region of the first conductivity type and a planar junction. The drain region and the source region are disposed... Agent: Patent Prosecution O2mirco , Inc.

20090184381 - Semiconductor sensor and method for manufactruing the same: A semiconductor sensor includes: a semiconductor substrate; a plurality of piezoelectric thin films layered on the semiconductor substrate, the plurality of piezoelectric thin films including at least a pair of the piezoelectric thin films layered above and below; a pair of electrodes that are formed at an interface of at... Agent: Harness, Dickey & Pierce, P.L.C

20090184382 - Method to reduce dislocation density in silicon: A crystalline material structure is provided. The crystalline material structure includes a semiconductor structure being annealed at temperatures above the brittle-to-ductile transition temperature of the semiconductor structure, and cooled in an approximately linear time-temperature profile down to approximately its respective transition temperature T0.... Agent: Gauthier & Connors, LLP

20090184384 - Array of mutually isolated, geiger-mode, avalanche photodiodes and manufacturing method thereof: An embodiment of array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type and housing an anode region, of a second conductivity type, facing a top surface of the body, a cathode-contact region, having the first conductivity type and... Agent: Graybeal Jackson LLP

20090184385 - Optical semiconductor package with compressible adjustment means: An optical semiconductor package includes a support with a passage to receive a ring holding a lens situated facing an optical sensor. The support has, in the passage, at least one local release recess and the ring is equipped peripherally with a locally projecting, elastically deformable element. The local release... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20090184383 - Photodetector: A semiconductor photodetector is disclosed which can have a high responsivity, high saturation power, and high bandwidth. The photodetector comprises a waveguide structure comprising: an active waveguide comprising an absorber for converting photons conveying an optical signal into charge carriers conveying a corresponding electrical signal; a carrier collection layer for... Agent: Nixon & Vanderhye, PC

20090184386 - Solid-state image pickup device and fabrication method therefor: Disclosed herein is a solid-state image pickup device, including, a light receiving pixel section, a black level reference pixel section, a multi-layer wiring line section, a first light blocking film, a second light blocking film, a third light blocking film, and a fourth light blocking layer.... Agent: Robert J. Depke Lewis T. Steadman

20090184387 - Sensor, solid-state imaging device, and imaging apparatus and method of manufacturing the same: A sensor is provided. The sensor includes semiconductor layer; a photodiode, an impurity-doped polycrystalline silicon layer; and a gate electrode. The photodiode is formed in the semiconductor layer. The impurity-doped polycrystalline silicon layer is formed above the semiconductor layer. The gate electrode applies a gate voltage to the polycrystalline silicon... Agent: Sonnenschein Nath & Rosenthal LLP

20090184388 - Photodiode, ultraviolet sensor having the photodiode, and method of producing the photodiode: A photodiode includes a silicon semiconductor layer; a P-type high concentration diffusion layer with a P-type impurity diffused therein at a high concentration; an N-type high concentration diffusion layer with an N-type impurity diffused therein at a high concentration; and a low concentration diffusion layer with one of the P-type... Agent: Kubotera & Associates, LLC

20090184389 - Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same: A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material,... Agent: Wilmerhale/boston

20090184390 - Semiconductor device and method of manufacturing the same: A semiconductor device is disclosed, which includes a semiconductor substrate including a device region and an isolation region having an isolation trench, a gate electrode formed on the device region through a gate insulating film, a first isolation insulating film formed in the isolation trench, the first isolation insulating film... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090184391 - Semiconductor devices having fuses and methods of forming the same: Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be... Agent: Harness, Dickey & Pierce, P.L.C

20090184394 - High performance system-on-chip inductor using post passivation process: A system and method for forming post passivation passive components, such as resistors and capacitors, is described. High quality electrical components, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.... Agent: Megica Corporation

20090184393 - Memory capacitor and manufacturing method thereof: The structure strength of a memory capacitor is reduced as the height of the memory capacitor is increased, which results in collapse and a short circuit. This invention provides a capacitor with a special reinforced structure outside, wherein the reinforced structure extends upward from the bottom of the lower electrode... Agent: Jianq Chyun Intellectual Property Office

20090184392 - Method and structure for forming trench dram with asymmetric strap: A method of forming a trench device structure having a single-side buried strap is provided. The method includes forming a deep trench in a semiconductor substrate, said deep trench having a first side portion and a second side portion; depositing a node dielectric on said deep trench, wherein said node... Agent: International Business Machines Corporation Dept. 18g

20090184395 - Input/output (i/o) buffer: An I/O buffer including an I/O circuit, a pad and a pulling resistant device. The I/O circuit is for inputting or outputting a signal. The pulling resistant device has a plurality of resistant elements electrically connected between the I/O circuit and the pad, for forming a resistance value.... Agent: North America Intellectual Property Corporation

20090184397 - Nonvolatile memory device and processing method: A method of processing a nonvolatile memory device includes forming a first electrode, depositing a layer of sol-gel solution on the first electrode, hydrolyzing the layer of sol-gel solution to form a layer of variable electric resistance material, and forming a second electrode on the layer of variable electric resistance... Agent: Carlson, Gaskey & Olds, P.C.

20090184396 - Resistive random access memories and methods of manufacturing the same: Provided are resistive random access memories (RRAMs) and methods of manufacturing the same. A RRAM includes a storage node including a variable resistance layer, a switching device connected to the storage node, and a protective layer covering an exposed part of the variable resistance layer. The protective layer includes at... Agent: Harness, Dickey & Pierce, P.L.C

20090184398 - Group iii nitride compound semiconductor device: Disclosed is a group III nitride compound semiconductor device having a substrate, buffer layers on the substrate, and a group III nitride compound semiconductor layer on the top layer of the buffer layers. The buffer layers comprises a first buffer layer formed on the substrate and a second buffer layer... Agent: H.c. Park & Associates, PLC

20090184399 - System for and method of microwave annealing semiconductor material: A system for and method of processing, i.e., annealing semiconductor materials. By controlling the time, frequency, variance of frequency, microwave power density, wafer boundary conditions, ambient conditions, and temperatures (including ramp rates), it is possible to repair localized damage lattices of the crystalline structure of a semiconductor material that may... Agent: Spencer, Fane, Britt & Browne

20090184400 - Via gouging methods and related semiconductor structure: Methods for via gouging and a related semiconductor structure are disclosed. In one embodiment, the method includes forming a via opening in a dielectric material, the via opening aligned with a conductor; forming a protective coating over the dielectric material and in the via opening; performing via gouging; and removing... Agent: Hoffman Warnick LLC

20090184401 - Semiconductor device and method for manufacturing the same: It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090184402 - Method of fabricating a shallow trench isolation structure including forming a second liner covering the corner of the trench and first liner.: A method of fabricating a shallow trench isolation structure is provided. First, a pad oxide layer and a mask layer are formed sequentially on a substrate. Then, the mask layer and the pad oxide layer are patterned and the substrate is etched to form a trench. After that, a first... Agent: J C Patents, Inc.

20090184404 - Electromagnetic shilding structure and manufacture method for multi-chip package module: An electromagnetic shielding structure for a multi-chip package module includes a substrate having at least one conductive point, a plurality of chips, an encapsulating body and an electromagnetic shielding layer. Wherein the chips are arranged and encapsulated by the encapsulating body on the substrate. The electromagnetic shielding layer is arranged... Agent: Rosenberg, Klein & Lee

20090184403 - Method of forming a semiconductor package and structure thereof: An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed by forming a conductive layer (34, 46) over an encapsulant (32). The conductive layer includes a combination of a conductive glue (38, 48, 52) and a metal paint (36, 50). A wire loop (30) is coupled to the conductive layer... Agent: Freescale Semiconductor, Inc. Law Department

20090184405 - Package structure: A package structure is provided. The package structure includes a substrate, a semiconductor device, and a shielding cap. The substrate has at least an alignment recess located at a corner of the substrate. The semiconductor device is disposed on an upper surface of the substrate. The shielding cap having an... Agent: Bacon & Thomas, PLLC

20090184406 - Semiconductor package having insulated metal substrate and method of fabricating the same: Provided is a semiconductor package in which an adhesion force between an insulation metal substrate and a molding member is increased by removing a solder mask layer from the insulation metal substrate and a method of fabricating the semiconductor package. The semiconductor package includes an insulation metal substrate that includes... Agent: Hiscock & Barclay, LLP

20090184407 - Method to recover underfilled modules by selective removal of discrete components: Methods and reworked intermediate and resultant electronic modules made thereby, whereby a component in need of rework is located and removed from the module to reveal encapsulated solder connections residing within an underfill matrix. Heights of both the solder connections and underfill matrix are reduced, followed by etching the solder... Agent: Law Office Of Delio & Peterson, LLC.

20090184408 - Semiconductor device for fingerprint recognition: The semiconductor device includes the semiconductor chip having a sensor unit that performs fingerprint recognition, and a substrate having an opening formed in the position corresponding to the sensor unit. The semiconductor chip is flip chip bonded to the substrate such that the sensor unit corresponds to the opening, and... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090184409 - Semiconductor device including semiconductor chips with different thickness: In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted... Agent: Sughrue Mion, PLLC

20090184410 - Semiconductor package apparatus having redistribution layer: Provided is a semiconductor package apparatus having a redistribution layer. The apparatus includes at least one or more semiconductor chips, a packing part protecting the semiconductor chips, and a support part supporting the semiconductor chips. The apparatus also includes external terminals extending outside the packing part, redistribution layers installed between... Agent: Marger Johnson & Mccollom, P.C.

20090184411 - Semiconductor packages and methods of manufacturing the same: Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an... Agent: Stanzione & Kim, LLP

20090184412 - Resin-seal type semiconductor device: There is provided a resin-seal type semiconductor device (BGA type semiconductor device) whose heat dissipating characteristic is improved, so that it is prevented from deteriorating in reliability. This BGA type semiconductor device includes a wiring substrate on a predetermined area on which a semiconductor chip is mounted; a plurality of... Agent: Fish & Richardson P.C.

20090184413 - Insulative wiring board, semiconductor package using the same, and method for producing the insulative wiring board: The insulative wiring board of the present invention, with its both surfaces being covered with solder resist, includes at least one via hole in a semiconductor chip-mounting area penetrating the insulative wiring board, wherein conductor layers are electrically connected to each other via said at least one via hole. Further,... Agent: Nixon & Vanderhye, PC

20090184414 - Wafer level chip scale package having an enhanced heat exchange efficiency with an emf shield and a method for fabricating the same: A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The... Agent: Ladas & Parry LLP

20090184415 - Manufacturing method of a semiconductor device: A manufacturing method of a semiconductor device comprises: providing a first insulating film whose relative dielectric constant is at most a predetermined value above a substrate; providing a second insulating film whose relative dielectric constant is greater than the predetermined value on a surface of the first insulating film; forming... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090184416 - Mcm packages: An RF/IPD package with improved thermal management is described. The IPD substrate is attached to a system substrate with a thin RF chip mounted in the standoff between the IPD substrate and the system substrate. RF interconnections are made between the top of the RF chip and the bottom of... Agent: Law Office Of Peter V. D. Wilde

20090184417 - Polyol photosensitizers, carrier gas uv laser ablation sensitizers, and other additives and methods for making and using same: Disclosed are photosensitizers that include a polyol moiety covalently bonded to a fused aromatic moiety. Also disclosed is a method for improving UV laser ablation performance of a coating, such as a cationic UV curable coating, by incorporating an oxalyl-containing additive into the cationic UV curable or other coating. Oxalyl-containing... Agent: Peter Rogalskyj Rogalskyj & Weyand LLP

20090184419 - Flip chip interconnect solder mask: A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the remelt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection... Agent: Robert D. Atkins

20090184418 - Wiring substrate, tape package having the same, and display device having the same: A wiring substrate includes a base film, a plurality of first wirings and a plurality of second wirings. The base film has a chip-mounting region configured for mounting a semiconductor chip thereon. The first wirings extend in a first direction from inside the chip-mounting region to outside the chip-mounting region,... Agent: Stanzione & Kim, LLP

20090184420 - Post bump and method of forming the same: A post bump and a method of forming the post bump are disclosed. The method of forming the post bump can include: forming a resist layer, in which an aperture is formed in correspondence to a position of an electrode pad, over a substrate, on which the electrode pad is... Agent: Staas & Halsey LLP

20090184421 - Semiconductor device with high reliability and manufacturing method thereof: A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings includes a first metal wiring having a concentration profile... Agent: Young & Thompson

20090184423 - Low resistance and inductance backside through vias and methods of fabricating same: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench... Agent: Schmeiser, Olsen & Watts

20090184422 - Method for forming metal line of semiconductor device without production of sidewall oxide in metal line forming region: A method for forming a metal line of a semiconductor device includes forming an insulation layer having a contact hole over a semiconductor substrate. Any one of a TiN layer and a TaN layer is formed on the insulation layer, including a surface of the contact hole, and an anti-reflection... Agent: Ladas & Parry LLP

20090184424 - Semiconductor device and a method of manufacturing the same: The production of a crack in an insulating film under an external terminal of a semiconductor device due to external force applied to the external terminal is suppressed or prevented. Over the principal surface of a semiconductor substrate, there are formed multiple wiring layers. In the fifth wiring layer directly... Agent: Miles & Stockbridge PC

20090184425 - Conductive line structure and the method of forming the same: The conductive line structure of a semiconductor device including a base; at least one patterned conductive layer formed over the base; a conductive line formed over the at least one patterned conductive layer; a protection layer that encompasses the top surface and sidewall of the conductive line to prevent undercut... Agent: Kusner & Jaffe Highland Place Suite 310

20090184426 - Contact plugs of semiconductor device and method for forming the same: The contact plugs of a semiconductor device includes first contact plugs having an elliptical sectional shape, and second contact plugs formed on the first contact plugs and having a circular sectional shape. The second contact plugs being configured to come in contact with the first contact plugs, thereby preventing voids... Agent: Lowe Hauptman Ham & Berner, LLP

20090184427 - Flash memory device with word lines of uniform width and method for manufacturing thereof: A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090184429 - Integrated circuit comprising conductive lines and contact structures and method of manufacturing an integrated circuit: An integrated circuit comprises a first conductive lines and second lines as well as contact structures being in contact with the first and second conductive lines. The first conductive lines are arranged in a first metallization level, and second conductive lines are arranged in a second metallization level arranged above... Agent: Slater & Matsil, L.L.P.

20090184428 - Semiconductor device and method for manufacturing the same: A semiconductor substrate, an interwiring insulating film formed on the semiconductor substrate, a first protective film formed on the interwiring insulating film having an opening and a pad metal formed on the opening are provided. A groove is formed in a portion corresponding to a peripheral portion of the pad... Agent: Hamre, Schumann, Mueller & Larson P.C.

20090184430 - Semiconductor device and semiconductor module including semiconductor devices: Semiconductor device 1 includes: first wiring board 5 provided with a plurality of external terminals 9 on the under surface thereof; first semiconductor chip 3 with the under surface thereof mounted on the upper surface of first wiring board 5; and second semiconductor chip 10 with the under surface thereof... Agent: Young & Thompson

20090184431 - Liquid epoxy resin composition and flip chip semiconductor device: A liquid epoxy resin composition comprising (A) a liquid epoxy resin, (B) an aromatic amine curing agent comprising at least 5% by weight of a specific aromatic amine compound, and (C) an inorganic filler has a low viscosity for ease of working, cures into a cured product which has improved... Agent: Birch Stewart Kolasch & Birch

20090179185 - Phase change material layers and phase change memory devices including the same: A phase change material layer includes antimony (Sb) and at least one of indium (In) and gallium (Ga). A phase change memory device includes a storage node including a phase change material layer and a switching device connected to the storage node. The phase change material layer includes Sb and... Agent: Harness, Dickey & Pierce, P.L.C

20090179186 - Phase change memory cells delineated by regions of modified film resistivity: A Phase Change Memory (PCM) cell structure comprises both a lower electrode composed of a PCM layer and a conductive encapsulating upper electrode layer. The PCM layer is protected from damage by the conductive encapsulating layer. Electrical isolation between adjacent PCM cells is provided by high electrical resistance regions which... Agent: Graham S. Jones, Ii

20090179184 - Vertical spacer electrodes for variable-resistance material memories and vertical spacer variable-resistance material memory cells: Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted along the edge by electrodes. Processes include the formation of the bottom spacer electrodes as well as the variable-resistance material memory spacer cells. Devices include the variable-resistance memory cells.... Agent: Schwegman, Lundberg & Woessner/micron

20090179187 - 3-d and 3-d schottky diode for cross-point, variable-resistance material memories, processes of forming same, and methods of using same: A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a VRMM. A VRMM device may also include a conductive plug in a recess that is coupled to a VRMM. A VRMM array may also include a conductive plug in... Agent: Schwegman, Lundberg & Woessner/micron

20090179188 - Reproducible resistance variable insulating memory devices having a shaped bottom electrode: The present invention relates to the use of a shaped bottom electrode in a resistance variable memory device. The shaped bottom electrode ensures that the thickness of the insulating material at the tip of the bottom electrode is thinnest, creating the largest electric field at the tip of the bottom... Agent: Dickstein Shapiro LLP

20090179189 - Method for producing an electronic device with a layer structure and an electronic device: The invention relates to a method for producing a layer structure in an electronic device, especially in an organic light emitting device, the method comprising a step of producing the layer structure as a composite layer structure with free charge carriers generated by charge transfer between a first material and... Agent: Schmeiser, Olsen & Watts

20090179191 - Alingan light-emitting device: A semiconductor light-emitting device fabricated in the (Al,Ga,In)N materials system has an active region for light emission (3) comprising InGaN quantum dots or InGaN quantum wires. An AlGaN layer (6) is provided on a substrate side of the active region. This increases the optical output of the light-emitting device. This... Agent: Mark D. Saralino ( Sharp ) Renner, Otto, Boisselle & Sklar, LLP

20090179190 - Nitride semiconductor light emitting element: Provided is a nitride semiconductor light emitting element having an improved carrier injection efficiency from a p-type nitride semiconductor layer to an active layer by simple means from a viewpoint utterly different from the prior art. In the nitride semiconductor light emitting element, a buffer layer 2, an undoped GaN... Agent: Rabin & Berdo, PC

20090179192 - Nanowire-based semiconductor device and method employing removal of residual carriers: A nanowire-based device and method employ removal of residual carriers. The nanowire-based device includes a semiconductor nanowire having a semiconductor junction, and a residual carrier sink. The residual carrier sink is located at or adjacent to the semiconductor nanowire near the semiconductor junction and employs one or both of enhanced... Agent: Hewlett Packard Company

20090179193 - Carbon nanotube based integrated semiconductor circuit: Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090179197 - Device: A device is provided by use of a helical substituted polyacetylene. The device comprises a structure comprised of a helical substituted polyacetylene having a helical main chain, and a pair of electrodes for applying a voltage or electric current to the structure, wherein the molecule of the helical substituted polyacetylene... Agent: Fitzpatrick Cella Harper & Scinto

20090179195 - Organic luminescence transistor device and manufacturing method thereof: The invention is an organic luminescence transistor device including: a substrate; an assistance electrode layer provided on a side of an upper surface of the substrate; an insulation film provided on a side of an upper surface of the assistance electrode layer; a first electrode provided locally on a side... Agent: Oliff & Berridge, PLC

20090179194 - Organic thin film transistors: An organic thin film transistor has a gate dielectric layer which is formed from a block copolymer. The block copolymer comprises a polar block and a nonpolar block. The resulting dielectric layer has good adhesion to the gate electrode and good compatibility with the semiconducting layer.... Agent: Fay Sharpe / Xerox - Rochester

20090179196 - Pyrene-based organic compound, transistor material and light-emitting transistor device:

20090179198 - Thin film transistor comprising novel conductor and dielectric compositions: The invention relates to thin film transistors comprising novel dielectric layers and novel electrodes comprising metal compositions that can be provided by a dry thermal transfer process.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20090179199 - Field effect transistor with amorphous oxide layer containing microcrystals: A novel amorphous oxide applicable, for example, to an active layer of a TFT is provided. The amorphous oxide comprises microcrystals.... Agent: Fitzpatrick Cella Harper & Scinto

20090179200 - Semiconductor device: A self emission silicon emission display is provided at a low price, which contains silicon and oxygen which exist in abundance on the earth as the main component and which can be easily formed by conventional silicon process. A light emission element includes a first electrode for injecting electrons, a... Agent: Stanley P. Fisher Reed Smith LLP

20090179201 - Laser chalcogenide phase change device: A laser activated phase change device for use in an integrated circuit comprises a chalcogenide fuse configured to connect a first patterned metal line and a second patterned metal line and positioned between an inter layer dielectric and an over fuse dielectric. The fuse interconnects active semiconductor elements manufactured on... Agent: Young Basile Hanlon Macfarlane & Helmholdt, P.C.

20090179202 - Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to... Agent: Cantor Colburn, LLP

20090179204 - Crystal display: A display panel including first to third conductive films is provided, which includes: a first signal line including a first portion that includes the first conductive film, an intermediate portion that includes at least two of the first to the third conductive films (“intermediate portion films”), and a contact portion... Agent: F. Chau & Associates, LLC

20090179203 - Display substrate: A display substrate includes an insulating substrate, a thin-film transistor (TFT), a pixel electrode, a signal line and a pad part. The insulating substrate has a display region and a peripheral region surrounding the display region. The TFT is in the display region of the insulating substrate. The pixel electrode... Agent: Haynes And Boone, LLPIPSection

20090179205 - Semiconductor device and method of manufacturing same: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not... Agent: Fish & Richardson P.C.

20090179206 - Method and apparatus for generating giant spin-dependent chemcial potential difference in non-magnetic materials: A system, structure, and method of making the structure are disclosed for generating a large chemical potential difference between spin-up and spin-down electrons in non-magnetic materials. The device includes an inverse spin valve of a sandwiched layer structure with alternating non-magnetic and magnetic layers. In an embodiment of the invention,... Agent: Leydig Voit & Mayer, Ltd

20090179207 - Flip-chip phosphor coating method and devices fabricated utilizing method: Methods for fabricating light emitting diode (LED) chips one of which comprises flip-chip mounting a plurality of LEDs on a surface of a submount wafer and forming a coating over said LEDs. The coating comprising a conversion material at least partially covering the LEDs. The coating is planarized to the... Agent: Koppel, Patrick, Heybl & Dawson

20090179208 - Organic luminescence transistor device and manufacturing method thereof: The invention is an organic luminescence transistor device including: a substrate; an assistance electrode layer provided on an upper surface of the substrate; an insulation film provided on an upper surface of the assistance electrode layer; a first electrode provided locally on an upper surface of the insulation film, the... Agent: Oliff & Berridge, PLC

20090179209 - Light emitting device: A light emitting device is provided. In the present invention, a magnetic material is added to the light emitting device to change the current path and the distribution of the current density. As the main distribution of the current density is moved from the area between the electrodes to the... Agent: Jianq Chyun Intellectual Property Office

20090179212 - Led and phosphor for short-wave semiconductor: A phosphor for short-wave semiconductor LEDs to create white radiation that comes from the lumen of the phosphor and the blue radiation of the heterojunction absorbed by the phosphor. The phosphor is prepared from a YAG-based substrate and added with N−3 and F−1, having the chemical formula of (ΣLn)3Al5O12-δN−3δ/2F−1δ/2, in... Agent: The Weintraub Group, P.L.C

20090179214 - Light eitting device with magnetic field: A light emitting device with magnetic field includes a light-emitting structure and a first magnetic-source layer. The light-emitting structure includes a first doped structural layer, a second doped structural layer, an active layer between the two doped structural layers, a first electrode, and a second electrode. The first magnetic-source layer... Agent: Jianq Chyun Intellectual Property Office

20090179216 - Light eitting device with magnetic field: A light emitting device with magnetic field includes a light emitting device, a thermal conductive material layer and a magnetic layer. The thermal conductive material layer is coupled with the light emitting device to dissipate heat generated by the light emitting device. The magnetic layer is coupled with thermal conductive... Agent: Jianq Chyun Intellectual Property Office

20090179211 - Light emitting device: The present invention discloses a semiconductor light emitting device including an active layer for generating light by recombination of electron and hole between a first semiconductor layer having first conductivity and a second semiconductor layer having second conductivity different from the first conductivity, the second semiconductor layer being disposed on... Agent: Harness, Dickey, & Pierce, P.l.c

20090179210 - Patterning method for light-emitting devices: A method of patterning a substrate that includes locating a single mask film over the substrate and forming first opening portions in first locations in the mask film. First electrical materials are deposited over the substrate and mask film to form patterned areas in the first locations. Second opening portions... Agent: David Novais Patent Legal Staff

20090179213 - Phosphor coating systems and methods for light emitting structures and packaged light emitting diodes including phosphor coating: Methods are disclosed including applying a layer of binder material onto an LED structure. A luminescent solution including an optical material suspended in a solution is atomized using a flow of pressurized gas, and the atomized luminescent solution is sprayed onto the LED structure including the layer of binder material... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090179215 - Semiconductor light emitting device and fabrication method for the semiconductor light emitting device: A semiconductor light emitting device includes a first metal layer placed on the p-type semiconductor layer on the substrate, and includes a first pattern width W1; a second metal layer on the first metal layer; a transparent electrode layer on the second metal layer and the p type semiconductor layer,... Agent: Rabin & Berdo, PC

20090179218 - Light emitting device package: A light emitting device package including an light emitting device and at least one magnetic source is provided. The light emitting device includes a first doped type layer, a second doped type layer, and a light emitting layer. The light emitting layer is located between the first doped type layer... Agent: Jianq Chyun Intellectual Property Office

20090179217 - Light-emitting device with magnetic field: A light-emitting device with magnetic-source includes a light emitting stack structure. The light emitting stack structure has a first electrode and a second electrode distributed at a light output side of the light emitting stack structure. A magnetic-source layer is engaged with the light emitting stack structure to provide a... Agent: Jianq Chyun Intellectual Property Office

20090179219 - Side view type led package: In a side view type light emitting diode (LED) package, a lead frame portion and lead frame electrical contact portions are exposed outside a package body to serve as an additional heat dissipation path. The side view type LED package includes an LED chip, a package body having a side... Agent: H.c. Park & Associates, PLC

20090179221 - Semiconductor light emitting device: Provided is a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive type clad layer having a composition ratio of aluminum increased at a predetermined rate, an active layer on the first conductive type clad layer, and a second conductive type semiconductor layer on the active... Agent: Birch Stewart Kolasch & Birch

20090179220 - Semiconductor light-emitting device, method of manufacturing semiconductor light-emitting device, and lamp: o

20090179222 - Silicon controlled rectifier: A silicon controlled rectifier structure of polygonal layouts is provided. The polygonal first conductive type doped region is located in the middle of the polygonal second conductive type well. The first conductive type well shaped as a polygonal ring surrounds the second conductive type well and the second conductive type... Agent: J C Patents, Inc.

20090179223 - Bi-directional transistor with by-pass path and method therefor: In one embodiment, a transistor is formed to have a first current flow path to selectively conduct current in both directions through the transistor and to have a second current flow path to selectively conduct current in one direction.... Agent: Mr. Jerrry Chruma Semiconductor Components Industries, L.L.C.

20090179224 - Power semiconductor component with trench-type field ring structure: A power semiconductor component and a method for producing such a component. The component comprises a semiconductor base body having a first doping. A pn junction is formed in the base body by a contact region having a second doping with a first doping profile. A field ring structure has... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090179225 - Photo detector device: A photo detector device comprising a first layer comprising a first material, and a second layer arranged adjacent to the first layer, the second layer comprising strained silicon, wherein the second layer further comprises a light absorption region located substantially within the strained silicon, wherein the first or the second... Agent: Ibm Microelectronics Intellectual Property Law

20090179226 - Strain-direct-on-insulator (sdoi) substrate and method of forming: Methods (and semiconductor substrates produced therefrom) of fabricating (n−1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed... Agent: Docket Clerk

20090179227 - Nitride semiconductor device and method for producing nitride semiconductor device: This nitride semiconductor device comprises: an n-type first layer made of a group III nitride semiconductor; a p-type second layer made of a group III nitride semiconductor layer provided on the first layer; and an n-type third layer made of a group III nitride semiconductor with a p-type impurity content... Agent: Rabin & Berdo, PC

20090179228 - High performance collector-up bipolar transistor: Disclosed are embodiments of a hetero-junction bipolar transistor (HBT) structure and method of forming the structure that provides substantially lower collector-to-base parasitic capacitance and collector resistance, while also lowering or maintaining base-to-emitter capacitance, emitter resistance and base resistance in order to achieve frequency capabilities in the THz range. The HBT... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090179229 - Ohmic contact on p-type gan: An ohmic contact in accordance with the invention includes a layer of p-type GaN-based material. A first layer of a group II-VI compound semiconductor is located adjacent to the layer of p-type GaN-based material. The ohmic contact further includes a metal layer that provides metal contact. A second layer of... Agent: Kathy Manke Avago Technologies Limited

20090179231 - Integrated circuitry: This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen... Agent: Wells St. John P.s.

20090179230 - Wiring substrate, semiconductor device and manufacturing method thereof: The present invention provides a method for forming a wiring having a minute shape on a large substrate with a small number of steps, and further a wiring substrate formed by the method. Moreover, the present invention provides a semiconductor device in which cost reduction and throughput improvement are possible... Agent: Cook Alex Ltd

20090179232 - Low lag transfer gate device: A CMOS active pixel sensor (APS) cell structure includes at least one transfer gate device and method of operation. A first transfer gate device comprises a diodic or split transfer gate conductor structure having a first doped region of first conductivity type material and a second doped region of a... Agent: Scully, Scott, Murphy & Presser, P.C.

20090179233 - Micro-electro-mechanical systems (mems) device: The present invention provides a MEMS device, be implemented on many MEMS device, such as MEMS microphone, MEMS speaker, MEMS accelerometer, MEMS gyroscope. The MEMS device includes a substrate. A dielectric structural layer is disposed over the substrate, wherein the dielectric structural layer has an opening to expose the substrate.... Agent: Jianq Chyun Intellectual Property Office

20090179234 - Field effect transistor: A field effect transistor having a T-gate (10), the gate comprising a neck portion (16) and a T-bar portion (18) overhanging the neck portion, wherein the neck portion (16) comprises a plurality of spaced pillars (20). By forming the neck portion from a plurality of spaced pillars the area of... Agent: Scully Scott Murphy & Presser, PC

20090179235 - Semiconductor device, dc/dc converter and power supply: A semiconductor device in which the self-turn-on phenomenon is prevented that can significantly improve power conversion efficiency. The semiconductor device is a system-in-package for power supply applications in which a high-side switch, a low-side switch, and two drivers are included in a single package. The device includes an auxiliary switch... Agent: Dickstein Shapiro LLP

20090179236 - Recess etch for epitaxial sige: A PMOS transistor and a method for fabricating a PMOS transistor. The method may include providing a semiconductor wafer having a PMOS transistor gate stack, source/drain extension regions, and active regions. The method may also include forming epi sidewalls, performing a ex-situ recess etch, and performing an in-situ recess etch.... Agent: Texas Instruments Incorporated

20090179237 - Cmos image sensor and method for fabricating the same: CMOS image sensor and method for fabricating the same, the CMOS image sensor including a second conductive type semiconductor substrate having an active region and a device isolation region defined therein, wherein the active region has a photodiode region and a transistor region defined therein, a device isolating film in... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090179238 - Image pickup element performing image detection of high resolution and high image quality and image pickup apparatus including the same: In a pixel part, in a first active region, a photodiode and a transferring transistor are formed. In a second active region, a resetting transistor is formed. In a pixel part, in a first active region, a photodiode and a transferring transistor are formed. In a second active region, an... Agent: Buchanan, Ingersoll & Rooney PC

20090179239 - Cmos image sensors and methods of manufacturing the same: A complementary metal-oxide-semiconductor image sensor may include: a semiconductor substrate; a photodiode formed on a first portion of the semiconductor substrate; a transfer gate formed on the semiconductor substrate, near the photodiode, to transfer optical charges accumulated in the photodiode; a floating diffusion area formed on a second portion of... Agent: Harness, Dickey & Pierce, P.L.C

20090179240 - Device for detecting/storing electromagnetic beams, method for making same, and use thereof and imager incorporating same: The invention concerns a device for detecting and storing electromagnetic beams, an imager incorporating same, a method for making said device and use thereof. The inventive device comprises a field-effect phototransistor including: two source and drain contact electrodes, an electrical conduction unit which is connected to the two contact electrodes... Agent: Alston & Bird LLP

20090179242 - Image sensor and method for manufacturing the same: Embodiments relate to an image sensor. According to embodiments, an image sensor may include a metal interconnection and readout circuitry over a first substrate, a metal layer over the metal interconnection, and an image sensing device electrically connected to the metal layer. According to embodiments, an electric field may not... Agent: Sherr & Vaughn, PLLC

20090179243 - Photo detector array: A photo detector device includes a photosensitive transistor capable of detecting an optical signal including an image component and a background component and converting the optical signal into a current including an image current corresponding to the image component and a background current corresponding to the background component, a first... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090179241 - Photosensor and photo ic equipped with same: The present invention provides a photosensor formed in a semiconductor substrate having a silicon substrate, an insulating layer formed over the silicon substrate, and a silicon semiconductor layer formed over the insulating layer, comprising an ultraviolet photosensitive element formed in the silicon semiconductor layer, and at least one visible light... Agent: Rabin & Berdo, PC

20090179245 - Memory cell and memory device: A programmable magnetoresistive memory cell. The memory cell has a magnetic element that includes a first and a second ferromagnetic layer. The first and second ferromagnetic layers are separated by a non-ferromagnetic and preferably electrically insulating spacer layer. The data bit is read out by measuring the electrical resistance across... Agent: Ibm Corporation, T.j. Watson Research Center

20090179244 - Semiconductor component and semiconductor device: A semiconductor component includes an insulating region provided on the substrate, plural first conductivity type wire-form semiconductor layers aligned on the insulating region parallel to each other, second conductivity type source/drain regions provided to the respective semiconductor layers, a channel region provided between the source/drain regions, an insulating film provided... Agent: Charles N.j. Ruggiero, Esq. Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20090179246 - Semiconductor device and method for manufacturing the same: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower... Agent: Foley And Lardner LLP Suite 500

20090179247 - Semiconductor device: A technique which can improve manufacturing yield and product reliability is provided in a semiconductor device having a triple well structure. An inverter circuit which includes an n-channel type field effect transistor formed in a shallow p-type well and a p-channel type field effect transistor formed in a shallow n-type... Agent: Miles & Stockbridge PC

20090179248 - Nand flash memory device and method of fabricating the same: A NAND flash memory device includes a semiconductor substrate having a drain select transistor; a source select transistor, and memory cell transistors connected in series between the drain select transistor and the source select transistor, and an oxide film formed in the semiconductor substrate at each of a first side... Agent: Marshall, Gerstein & Borun LLP

20090179249 - Programmable nonvolatile memory and semiconductor integrated circuit device: Distance λm between a floating gate and a drain contact of a floating gate transistor forming a memory cell is set to be greater than a distance λ determined based on a minimum design dimension between a control gate and a contact of a peripheral transistor. Data retention characteristics of... Agent: Mcdermott Will & Emery LLP

20090179250 - Memory device: In an embodiment, a memory device, including: a semiconductor fin structure, each end portion of the fin structure including a source/drain region; a charge storage layer covering at least a portion of the fin structure; and a gate layer covering at least a portion of the charge storage layer.... Agent: Slater & Matsil LLP

20090179251 - Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures: Device and design structures for memory cells in a non-volatile random access memory (NVRAM) and methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes. The device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a floating gate electrode, a semiconductor body, and a control gate electrode... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090179252 - Flash memory device including multilayer tunnel insulator and method of fabricating the same: A flash memory device may include a lower tunnel insulation layer disposed on a substrate, an upper tunnel insulation layer disposed on the lower tunnel insulation layer, a floating gate disposed on the upper tunnel insulation layer, an intergate insulation layer disposed on the floating gate; and a control gate... Agent: Lee & Morse, P.C.

20090179254 - Memory device with improved performance and method of manufacturing such a memory device: Non-volatile memory device on a semiconductor substrate, comprising a semiconductor base layer, a charge storage layer stack, and a control gate; the base layer comprising source and drain regions and a current-carrying channel region being positioned in between the source and drain regions; the charge storage layer stack comprising a... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090179255 - Method for forming gate oxide of semiconductor device: The method for forming a triple gate oxide of a semiconductor device includes the steps of defining a first region, a second region and a third region, forming a first oxide film and forming a second oxide film on the first oxide film, blocking the first region and selectively removing... Agent: Morgan Lewis & Bockius LLP

20090179253 - Oxide-nitride-oxide stack having multiple oxynitride layers: A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the... Agent: Cypress Semiconductor Corporation

20090179256 - Memory having separated charge trap spacers and method of forming the same: A silicon-oxide-nitride-oxide-silicon (SONOS) memory and the corresponding forming method are disclosed. The memory includes a plurality of select gate structures arranged in an array, a plurality of charge trap spacers that do not contact each other, and a plurality of word lines. The word lines can directly contact the select... Agent: North America Intellectual Property Corporation

20090179257 - Non-volatile semiconductor memory device and method of manufacturing the same: A non-volatile semiconductor memory device includes a first columnar semiconductor layer and a plurality of first conductive layers formed such that a charge storage layer for storing charges is sandwiched between the first conductive layers and the first columnar semiconductor layer. Also, the non-volatile semiconductor memory device includes a second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090179258 - Nitride semiconductor device and method for producing nitride semiconductor device: A nitride semiconductor device includes: a nitride semiconductor structure portion including a first layer made of an n-type group III nitride semiconductor, a second layer made of a group III nitride semiconductor containing a p-type impurity provided on the first layer and an n-type region formed on a part of... Agent: Rabin & Berdo, PC

20090179260 - Method of manufacturing semiconductor device and semiconductor device: A method of manufacturing a semiconductor device, includes: forming a first and a second trench regions adjacent from each other in a first conductivity type semiconductor base; forming a second conductivity type semiconductor region in the semiconductor base between the first and second trench regions; forming a mask on the... Agent: Young & Thompson

20090179261 - Semiconductor device and a method of manufacturing the same: Provided is a manufacturing method of a semiconductor device wherein the generation of voids is prevented in aluminum-based electrodes or the like. The method is suitable for manufacturing a semiconductor device adapted for vehicles, which is required to have a high reliability. However, it is very difficult that power semiconductor... Agent: Miles & Stockbridge PC

20090179259 - Semiconductor device with (110)-oriented silicon: A method of forming a semiconductor device on a heavily doped P-type (110) semiconductor layer over a metal substrate includes providing a first support substrate and forming a P-type heavily doped (110) silicon layer overlying the first support substrate. At least a top layer of the first support substrate is... Agent: Townsend And Townsend And Crew, LLP

20090179262 - Floating body memory cell with a non-overlapping gate electrode: An integrated circuit includes a memory cell with a transistor. The transistor includes first and second doped portions, and a third portion disposed between the first and second doped portions. The first and the second doped portions and the third portion are disposed in a semiconductor substrate. The transistor further... Agent: Edell, Shapiro & Finnan, LLC

20090179263 - Process for manufacturing a power semiconductor device having charge-balance columnar structures on a non-planar surface, and corresponding power semiconductor device: An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the... Agent: Graybeal Jackson LLP

20090179264 - Ldmos integrated schottky diode: A semiconductor device includes a substrate having a first conductivity type and a semiconductor layer formed over the substrate and having lower and upper surfaces. A laterally diffused metal-oxide-semiconductor (LDMOS) transistor device is formed over the substrate and includes a source region of the first conductivity type and a drain... Agent: Duane Morris LLP - PhiladelphiaIPDepartment

20090179265 - Bi-directional, reverse blocking battery switch: Embodiments of the present invention relate to an improved die layout for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the... Agent: Townsend And Townsend And Crew, LLP

20090179268 - Design structures for high-voltage integrated circuits: Design structures for high-voltage integrated circuits. The design structure, which is formed using a semiconductor-on-insulator (SOI) substrate, may include device structure with a semiconductor body positioned between first and second gate electrodes. The first and second gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090179266 - Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures: Device structures for a metal-oxide-semiconductor field effect transistor (MOSFET) that is suitable for operation at relatively high voltages and methods of forming same. The MOSFET, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a channel in a semiconductor body that is self-aligned with a gate electrode. The gate electrode... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090179267 - Semiconductor-on-insulator high-voltage device structures, methods of fabricating such device structures, and design structures for high-voltage circuits: High-voltage device structures, methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes, and design structures for high-voltage circuits. The planar device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a semiconductor body positioned between two gate electrodes. The gate electrodes and the semiconductor body may be... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090179269 - Protection against charging damage in hybrid orientation transistors: A chip can include a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. An SOI device is disposed in a... Agent: International Business Machines Corporation Dept. 18g

20090179270 - Electrostatic discharge protection pattern for high voltage applications: Electrostatic discharge (ESD) protection in high voltage semiconductor devices is disclosed that provides enhanced current isolation between transistor drains or sources by creating an isolation island surrounding the drains or sources. This isolation island can be a higher-doped region within which the drain/source lies. The junction between the higher doping... Agent: Slater & Matsil, L.L.P.

20090179271 - Method and integrated circuits capable of saving layout areas: An integrated circuit includes a diffusion layer, a first poly-silicon layer, and a second poly-silicon layer. The first poly-silicon layer is located on the diffusion layer to form a transistor. The second poly-silicon includes a first section and a second section. The first section of the second poly-silicon layer is... Agent: North America Intellectual Property Corporation

20090179272 - Double gate depletion mode mosfet: A metal-oxide-semiconductor field effect transistor (MOSFET) has a body layer that follows the contour of exposed surfaces of a semiconductor substrate and contains a bottom surface of a shallow trench and adjoined sidewalls. A bottom electrode layer vertically abuts the body layer and provides an electrical bias to the body... Agent: Scully, Scott, Murphy & Presser, P.C.

20090179273 - Semiconductor device: A semiconductor device according to the present invention includes: a first region having a first conductive type; a plurality of second regions having a second conductive type that differs from the first conductive type, and formed to be arranged in the first region; a plurality of third regions having the... Agent: Sughrue Mion, PLLC

20090179274 - Semiconductor device and method for fabricating the same: A semiconductor device and a method for fabricating the same is disclosed, in which one line is formed from a main gate to a sidewall gate, so that it is possible to scale a transistor below nano degree, and the semiconductor device includes a semiconductor substrate; a device isolation layer... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090179275 - Semiconductor memory device junction and method of forming the same: The present invention relates to semiconductor memory device junction and a method of forming the same. The semiconductor memory device junction may include a semiconductor substrate having gate lines formed thereon, and a junction having first and second junction elements formed by implanting impurities of a different mass into the... Agent: Marshall, Gerstein & Borun LLP

20090179276 - Resistor ballasted transistors: A semiconductor chip comprises low voltage complementary metal oxide semiconductor (CMOS) sectors and high voltage lateral double diffused metal oxide semiconductor (LDMOS) sectors and at least one transistor within at least one of the low voltage CMOS sectors. The transistor has a semiconducting channel region within a substrate. A gate... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090179278 - Semiconductor device and manufacturing method of the same: In a p-type MOS transistor, a gate electrode is partially removed by a predetermined wet etching, so that an upper portion of the gate electrode is formed to be lower than an upper portion of a sidewall insulation film. As a result of such a constitution, in spite of formation... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090179277 - Semiconductor device and method for manufacturing the same: A semiconductor device according to the present invention includes: a semiconductor layer; an element separating portion, formed in a top layer portion of the semiconductor layer and separating, in the semiconductor layer, a first element forming region for forming a first conductive type MOSFET and a second element forming region... Agent: Rabin & Berdo, PC

20090179279 - Metal gate electrode stabilization by alloying: Stabilized metal gate electrode for complementary metal-oxide-semiconductor (“CMOS”) applications and methods of making the stabilized metal gate electrodes are disclosed. Specifically, the metal gate electrodes are stabilized by alloying wherein the alloy comprises a metal selected from the group consisting of Re, Ru, Pt, Rh, Ni, Al and combinations thereof... Agent: Connolly Bove Lodge & Hutz LLP

20090179280 - High threshold nmos source-drain formation with as, p and c to reduce damage: Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in NLDD and NSD regions is mainly due to phosphorus interstitial movement. Carbon implanatation is commonly used to reduce phosphorus diffusion in the NLDD, but contributes to gated... Agent: Texas Instruments Incorporated

20090179282 - Metal gate device with reduced oxidation of a high-k gate dielectric: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090179281 - Schottky barrier source/drain n-mosfet using ytterbium silicide: An N-type Schottky barrier Source/Drain Transistor (N-SSDT) that uses ytterbium silicide (YbSi2-x) for the source and drain is described. The structure includes a suitable capping layer stack.... Agent: Saile Ackerman LLC

20090179283 - Metal gate stack and semiconductor gate stack for cmos devices: A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed on the semiconductor substrate. Oxygen-impermeable dielectric spacers are formed... Agent: Scully, Scott, Murphy & Presser, P.C.

20090179284 - Semiconductor transistors having high-k gate dielectric layers, metal gate electrode regions, and low fringing capacitances: A semiconductor structure and a method for forming the same. The structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a gate dielectric region, and (iv) a gate electrode region, (v) a plurality of interconnect layers on... Agent: Schmeiser, Olsen & Watts

20090179285 - Metal gate electrodes for replacement gate integration scheme: Metal gate electrodes for a replacement gate integration scheme are described. A semiconductor device includes a substrate having a dielectric layer disposed thereon. A trench is disposed in the dielectric layer. A gate dielectric layer is disposed at the bottom of the trench and above the substrate. A gate electrode... Agent: Applied Materials/bstz Blakely Sokoloff Taylor & Zafman LLP

20090179287 - Functional device and manufacturing method thereof: A functional device includes: a substrate; a functional structure formed on the substrate; a cavity in which the functional structure is disposed; and a cover which covers the cavity, wherein the cover includes a bumpy structure including rib shaped portions, or groove shaped portions, which cross a covering range covering... Agent: Townsend And Townsend And Crew, LLP

20090179286 - Mems devices and methods of manufacture thereof: Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a first semiconductive material and at least one trench disposed in the first semiconductive material, the at least one trench having a sidewall. An insulating material layer is disposed over an upper... Agent: Slater & Matsil LLP

20090179288 - Semiconductor mechanical senseor: A semiconductor mechanical sensor having a new structure in which a S/N ratio is improved. In the central portion of a silicon substrate 1, a recess portion 2 is formed which includes a beam structure. A weight is formed at the tip of the beam, and in the bottom surface... Agent: Harness, Dickey & Pierce, P.L.C

20090179289 - Image sensor microlens structures and methods of forming the same: An image sensor includes a light receiving device in a substrate, a color filter over the light receiving device, a buffer film over the color filter, and a microlens on the buffer film. The microlens has a concave bottom face and a convex top face. The buffer film has a... Agent: Volentine & Whitt PLLC

20090179290 - Encapsulated imager packaging: A method and apparatus provide a leadless imager packaging structure having an integrated leadframe and a first encapsulant with an opening, which is covered by a transparent plate to form a cavity. The cavity contains an integrated circuit having a light sensitive area facing the transparent plate and which is... Agent: Dickstein Shapiro LLP

20090179291 - Compound semiconductor image sensor: A stack-type image sensor using a compound semiconductor. The stack-type image sensor includes a stack of photoelectric conversion units which are sequentially arranged in a light incident direction and which absorb light in ascending order of a wavelength from shortest to longest.... Agent: Cantor Colburn, LLP

20090179292 - Molybdenum-doped indium oxide structures and methods: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain indium and monolayers that contain molybdenum are deposited onto a substrate and subsequently processed to form molybdenum-doped indium oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure.... Agent: Schwegman, Lundberg & Woessner/micron

20090179293 - Image sensor and method for manufacturing the same: Embodiments relate to an image sensor. According to embodiments, an image sensor may include a circuitry, a first substrate, a photodiode, a metal interconnection, and an electrical junction region. The circuitry and the metal interconnection may be formed on and/or over the first substrate. The photodiode may contact the metal... Agent: Sherr & Vaughn, PLLC

20090179296 - Cmos imager pixel designs: A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are disclosed. The charge storage capacitor may be formed entirely over a field oxide region of the CMOS imager, entirely over an active area of a... Agent: Dickstein Shapiro LLP

20090179294 - Image sensor and method for manufacturing the same: An image sensor includes a readout circuitry, a first substrate, a first interlayer dielectric, a metal interconnection, a top metal, and an image sensing device. The readout circuitry is formed on and/or over the first substrate and the first interlayer dielectric is formed on and/or over the first substrate. The... Agent: Sherr & Vaughn, PLLC

20090179295 - Image sensor and method for manufacturing the same: Embodiments relate to an image sensor. According to embodiments, an image sensor may include a metal interconnection, readout circuitry, a first substrate, a metal layer, and an image sensing device. The metal interconnection and the readout circuitry may be formed on and/or over the first substrate. The image sensing device... Agent: Sherr & Vaughn, PLLC

20090179297 - Junction barrier schottky diode with highly-doped channel region and methods: A junction barrier Schottky device includes a semiconductor substrate with basal, drift, and channel regions doped to a first conductivity type. The channel region is more highly doped than the drift region, and a blocking region doped to a second conductivity type is disposed at least partly around the channel... Agent: Rothwell, Figg, Ernst & Manbeck, P.C.

20090179299 - Method of fabricating a release substrate: The invention relates to a method of fabricating a release substrate produced from semiconductor materials, the method comprising creating a reversible connection between two substrate release layers characterized in that the reversible connection is formed by a connecting layer produced using a first material as the basis, the connecting layer... Agent: Winston & Strawn LLP Patent Department

20090179298 - Superjunction device having a dielectric termination and methods for manufacturing the device: A superjunction semiconductor device is provided having at least one column of a first conductivity type and at least one column of a second conductivity type extending from a first main surface of a semiconductor substrate toward a second main surface of the semiconductor substrate opposed to the first main... Agent: Panitch Schwarze Belisario & Nadel LLP

20090179300 - Trench sidewall protection by a carbon-rich layer in a semiconductor device: When forming a trench in a porous low-K dielectric (such as an ILD) of a semiconductor device, a carbon-rich layer is formed in the sidewalls of the trench during trench etching. This carbon-rich layer may protect the trench from being excessively etched, which would otherwise form an undesirable hardmask undercut.... Agent: Banner & Witcoff, Ltd.

20090179301 - Fuse having cutting regions and fuse set structure having the same: A fuse includes a main fuse region and a plurality of cutting regions extend from the main fuse region.... Agent: Baker & Mckenzie LLP Patent Department

20090179302 - Programmable electronic fuse: A programmable device (eFuse), includes: a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having a first end (12a), a second end (12b), a fuse link (11) between the ends, and an upper surface S. The semiconductor material... Agent: Scully, Scott, Murphy & Presser, P.C.

20090179303 - Vertical bipolar transistor: A vertical heterobipolar transistor comprising a substrate of semiconductor material of a first conductivity type and an insulation region provided therein, a first semiconductor electrode arranged in an opening of the insulation region and comprising monocrystalline semiconductor material of a second conductivity type, which is either in the form of... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20090179304 - Semiconductor device and method of manufacturing the same: In the manufacture of semiconductor devices, cracking of a resin member caused during cutting and defects in the external appearance are prevented.... Agent: Steptoe & Johnson LLP

20090179305 - Substrate and manufacturing method of the same: According to the present invention, on a double-sided substrate 1, a plurality of through-holes 2 connected to one wire 6 for plating as well as wiring are collectively arranged within a narrow range close to the connection portion. After a plating process, a penetrating hole 12 is formed and the... Agent: Steptoe & Johnson LLP

20090179306 - Advanced low k cap film formation process for nano electronic devices: A carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. In some embodiments, the dielectric film may optionally include nitrogen. When nitrogen is present, the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090179307 - Integrated circuit system employing feed-forward control: An integrated circuit system that includes: providing a substrate and a material layer; measuring a parameter of the material layer; and correlating the thickness of an anti-reflective layer to the measured parameter of the material layer for critical dimension control.... Agent: Law Offices Of Mikio Ishimaru

20090179308 - Method of manufacturing a semiconductor device: According to one embodiment of the present invention, a method of manufacturing a semiconductor device is provided. The method includes: forming a semiconductor structure; forming a stress liner over the semiconductor structure; and changing the stress properties of at least a part of the stress liner.... Agent: Slater & Matsil LLP

20090179309 - Power semiconductor component with trench- type second contact region: A power semiconductor component and method for producing it. The component has a semiconductor base body with a first doping and a pn junction formed by a contact region having a second doping with a doping profile in the base body. The second contact region is arranged at a second... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090179310 - Pillar devices and methods of making thereof: A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity... Agent: Sandisk Corporation C/o Foley & Lardner LLP

20090179311 - Semiconductor component and method for producing the same: A semiconductor component of semiconductor chip size includes a semiconductor chip. The semiconductor chip has a metallic coating that completely covers the side edges, the rear side and the top side, on which surface-mountable external contacts are arranged. One embodiment includes power semiconductor components, wherein the metallic coating connects a... Agent: Dicke, Billig & Czaja

20090179312 - Integrated circuit package-on-package stacking system: An integrated circuit package-on-package stacking method includes forming a leadframe interposer including: forming a leadframe having a lead; forming a molded base only supporting the lead; and singulating the leadframe interposer from the leadframe.... Agent: Law Offices Of Mikio Ishimaru

20090179313 - Flex clip connector for semiconductor device: A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach... Agent: Townsend And Townsend And Crew, LLP

20090179314 - Integrated circuit package system with leadfinger support: An integrated circuit package system including forming a leadframe having a lead with a leadfinger support of a predetermined height, and attaching an integrated circuit die with an electrical interconnect at a predetermined collapse height determined by the predetermined height of the leadfinger support.... Agent: Law Offices Of Mikio Ishimaru

20090179316 - Flexible semiconductor device and fabrication method thereof: A flexible semiconductor device and a fabrication method thereof are disclosed. The method includes the steps of providing a CMOS (complementary metal-oxide semiconductor) chip having a silicon substrate, wherein an IC (integrated circuit) is formed on the silicon substrate; mounting the chip on a carrier board via the IC-laden side... Agent: Pearne & Gordon LLP

20090179315 - Semiconductor die packages having solder-free connections, systems using the same, and methods of making the same: Disclosed are spring structures that provide solderless electrical connections in semiconductor die packages. An exemplary spring structure comprises a first portion adapted to make an electrical connection to a conductive region of a semiconductor die, a second portion adapted to make an electrical connection to a conductive region of a... Agent: Townsend And Townsend And Crew, LLP

20090179317 - Semiconductor device and method for manufacturing the same: It is made possible to restrict warpage at the time of resin cure and achieve a smaller thickness. A semiconductor device includes: a first chip including a MEMS device and a first pad formed on an upper face of the MEMS device, the first pad being electrically connected to the... Agent: Turocy & Watson, LLP

20090179318 - Multi-channel stackable semiconductor device and method for fabricating the same, and stacking substrate applied to the semiconductor device: A multi-channel stackable semiconductor device and a method for fabricating the same, and a stacking substrate applied to the semiconductor device are provided. A plurality of stacking substrates and package members having known good dies are provided. Each stacking substrate includes a first surface, an opposite second surface, a plurality... Agent: Knobbe Martens Olson & Bear LLP

20090179319 - Stacked semiconductor package assembly having hollowed substrate: A stackable package substrate has an opening shaped and dimensioned to accommodate but not contact a mold cap of a package upon which the stackable package is to be mounted. On the die attach surface, the frame substrate accommodates a die attach margin adjacent at the edge of the opening;... Agent: Law Offices Of Mikio Ishimaru

20090179320 - Integrated circuit incorporating wire bond inductance: The invention relates to the field of electronics, more particularly to the wire bonds incorporated into an integrated circuit package such as a quad flat pack, a ball grid array or hybrid style module. The present invention takes the normally undesirable wire bond inductance and uses it in an operational... Agent: Stolowitz Ford Cowger LLP

20090179321 - Power semiconductor device: A power semiconductor device, having a first semiconductor region, and a second semiconductor region; mounted with a first electrode pad on a semiconductor substrate main surface at the inside surrounded by the third semiconductor region, mounted in the second semiconductor region, and a multilayer substrate having first and second wiring... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090179322 - Electronic package method and structure with cure-melt hierarchy: Disclosed herein are embodiments of electronic package incorporating a thermal interface material (e.g., a metal TIM) that is positioned between a lid and a chip on a substrate. The TIM has a predetermined (i.e., repeatable) minimum thickness and is further registered to the top surface of the chip (i.e., the... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090179323 - Local area semiconductor cooling system: A system and method in which a semiconductor chip has electrically inactive metal-filled vias adjacent to a semiconductor device or devices to be cooled and the semiconductor device or devices are preferably surrounded by thermally insulating vias. The metal-filled vias are contacted with a thermoelectric cooler to remove excess heat... Agent: International Business Machines Corporation Dept. 18g

20090179324 - Integrated circuit package and fabricating method thereof: The invention discloses an integrated circuit package. The integrated circuit package comprises a substrate having a first surface and a second surface opposite thereto and a first hole passing through the substrate from the first surface to the second surface. A plurality of conductive lines is disposed on a portion... Agent: Quintero Law Office, PC

20090179325 - Leadless package: Provided is a semiconductor package, and in particular a semiconductor package which is capable of electrically connecting to the outside without a lead. The leadless package includes a plurality of lower conducting layer patterns disposed separately from one another; an insulating layer pattern on the lower conducting layer patterns; a... Agent: Townsend And Townsend And Crew, LLP

20090179326 - Semiconductor device package: The invention provides a semiconductor device package. The package includes a chip disposed on a supported board and a conductive path formed between the chip and the supported board, on the backside of the supported board, or on the chip, so that the conductive path does not have to go... Agent: Quintero Law Office, PC

20090179327 - Packaging structure, method for manufacturing the same, and method for using the same: A packaging structure applied for a surface mounting process, comprising: a chip module having a packaging surface; and a pre-cured layer formed on the packaging surface of the chip module. As above-mentioned, the structure is employed for protecting the external surface of the wafer. The pre-cured layer is formed on... Agent: Rosenberg, Klein & Lee

20090179328 - Barrier sequence for use in copper interconnect metallization: A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090179330 - Interconnect structures with bond-pads and methods of forming bump sites on bond-pads: Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electrically coupled to the integrated circuitry. The workpiece further... Agent: Perkins Coie LLP Patent-sea

20090179329 - Semiconductor devices and method of fabricating the same: The present invention relates to semiconductor devices and a method of fabricating the same. According to a method of manufacturing semiconductor devices, there is first provided a semiconductor substrate in which a first pre-metal dielectric layer including trenches is formed. A diffusion barrier layer is formed on the entire surface... Agent: Marshall, Gerstein & Borun LLP

20090179331 - Integrated circuit insulators and related methods: A system and method for providing low dielectric constant insulators in integrated circuits is provided. One aspect of this disclosure relates to a method for forming an integrated circuit insulator. The method includes forming an insulating layer using a first structural material upon a substrate, the first structural material having... Agent: Schwegman, Lundberg & Woessner/micron

20090179332 - Semiconductor device and method of manufacturing the same: A semiconductor device including a semiconductor substrate; a first insulating film formed on the semiconductor substrate including a contact hole opened therethrough; a lower plug filled in the contact hole having a recess defined in an upper portion thereof; a second insulating film including a via hole opened therethrough; a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090179333 - Solder contacts and methods of forming same: An integrated circuit that comprises a substrate and a structured layer on the substrate. The structured layer comprises an opening to the substrate, a first field and a second field on the substrate, wherein the first field and the second field, at least in part, overlap with the opening. The... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090179334 - Apparatus for facilitating proximity communication between chips: One embodiment of the present invention provides a system for facilitating proximity communication between semiconductor chips. The system includes a base chip and a bridge chip, each of which includes an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20090179335 - Printed circuit board and semiconductor package including the same: A printed circuit board (PCB) and a semiconductor package that are configured to prevent delamination and voids. In one example embodiment, the semiconductor package includes a PCB having a base substrate on which conductive patterns are formed and which includes an interior region having a die paddle for receiving a... Agent: Marger Johnson & Mccollom, P.C.

20090179336 - Electronic module and a method of assembling such a module: The module is of the type comprising an electronic component provided with a conductive face that is electrically connected to a connection member of the component by means of a conductor that is corrugated at least in part so as to define an alternating sequence of oppositely-directed arcs, a first... Agent: Oliff & Berridge, PLC

20090173927 - Storage node, phase change memory device and methods of manufacturing and operating the same: Provided are a storage node, phase change memory device and methods of manufacturing and operating the same. The storage node may include an electrode, a phase change layer, and an anti-diffusion layer between the electrode and the phase change layer and including a silicide compound. The phase change memory device... Agent: Harness, Dickey & Pierce, P.L.C

20090173929 - Data memory, writable and readable by microtips, which has a well structure, and manufacturing method: The invention relates to data storage memories, that can be written and read by using at least one write or read microtip which comes near to a point zone to be written or to be read on the surface of a substrate, either in order to change the physical state... Agent: Lowe Hauptman & Berner, LLP

20090173928 - Polysilicon emitter bjt access device for pcram: A resistive non-volatile memory cell with a bipolar junction transistor (BJT) access device formed in conjunction with the entire memory cell. The memory cell includes a substrate acting as a collector, a semiconductor base layer acting as a base, and a semiconductor emitter layer acting as an emitter. Additionally, metal... Agent: Law Office Of Ido Tuchman (yor)

20090173930 - Memory element and memory device: A memory device of a resistance variation type, in which data retaining characteristic at the time of writing is improved, is provided. The memory device includes: a plurality of memory elements in which a memory layer is provided between a first electrode and a second electrode so that data is... Agent: Wolf Greenfield & Sacks, P.C.

20090173931 - Methods of making, positioning and orienting nanostructures, nanostructure arrays and nanostructure devices: Nanostructure manufacturing methods and methods for assembling nanostructures into functional elements such as junctions, arrays and devices are provided. Systems for practicing the methods are also provided. In one embodiment, a substrate is disclosed which comprises a first substrate region and a nanowire element attached to the first substrate region... Agent: Nanosys Inc.

20090173932 - Thermoelectric material, infrared sensor and image forming device: A thermoelectric conversion material includes a superlattice structure produced by laminating a barrier layer containing insulating SrTiO3, and a quantum well layer containing SrTiO3 which has been converted into a semiconductor by doping an n-type impurity therein. The quantum well layer has a thickness 4 times or less the unit... Agent: Edwards Angell Palmer & Dodge LLP

20090173933 - Thermal sensor with a silicon/germanium superlattice structure: A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20090173934 - Nonvolatile memory and three-state fets using cladded quantum dot gate structure: The present invention discloses use of quantum dot gate FETs as a nonvolatile memory element that can be used in flash memory architecture as well as in a nonvolatile random access memory (NVRAM) configuration that does not require refreshing of data as in dynamic random access memories. Another innovation is... Agent: The Law Offices Of Steven Mchugh, LLC

20090173935 - Preparation of thin film transistors (tft's) or radio frequency identification (rfid) tags or other printable electronics using ink-jet printer and carbon nanotube inks: The invented ink-jet printing method for the construction of thin film transistors using all SWNTs on flexible plastic films is a new process. This method is more practical than all of exiting printing methods in the construction TFT and RFID tags because SWNTs have superior properties of both electrical and... Agent: Winstead PC

20090173936 - Quantum processor: Multiple substrates that carry quantum devices are coupled to provide quantum mechanical communicators therebetween, for example, using superconducting interconnects, vias, solder and/or magnetic flux. Such may advantageously reduce a footprint of a device such as a quantum processor.... Agent: Seed Intellectual Property Law Group PLLC

20090173937 - Method for the production of a layer of organic material: The resulting layer of organic material shows an improvement of both the micro quality and the macro quality, leading to obtaining a fully continuous film with minor surface roughness and an accurate line resolution and edge definition.... Agent: Knobbe Martens Olson & Bear LLP

20090173938 - Metal oxide semiconductor, semiconductor element, thin film transistor and method of manufacturing thereof: A method of manufacturing a metal oxide semiconductor comprising the step of: conducting a transformation treatment on a semiconductor precursor layer containing a metal salt to form the metal oxide semiconductor, wherein the metal salt comprises one or more metal salts selected from the group consisting of a nitrate, a... Agent: Lucas & Mercanti, LLP

20090173939 - Hybrid wafers: A hybrid wafer comprises a single-crystal SixGe1-x layer (15), where 0≦x≦1, a high thermal conductivity layer (10), and between the single-crystal SixGe1-x layer (15) and the high thermal conductivity layer (10), an intermediate layer (21) having a thickness of between 1 nanometer and 1 micrometer and comprising at least one... Agent: Porter Wright Morris & Arthur, LLP Intellectual Property Group

20090173940 - Image sensor and method for manufacturing the same: An image sensor can include a first substrate, an amorphous layer, and a photodiode. A circuitry including a metal interconnection can be formed on the first substrate. The amorphous layer is disposed over the first substrate, and contacts the metal interconnection. The photodiode can be formed in a crystalline semiconductor... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090173941 - Method for fabricating a semiconductor structures and structures thereof: Methods of fabricating a semiconductor structure with a non-epitaxial thin film disposed on a surface of a substrate of the semiconductor structure; and semiconductor structures formed thereof are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the... Agent: Hoffman Warnick LLC

20090173943 - Active matrix array structure and manufacturing mehtod thereof: An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part... Agent: Jianq Chyun Intellectual Property Office

20090173942 - Pixel structure: A pixel structure formed on a substrate and electrically connected with a scan line and a data line, and including a semiconductor pattern and a pixel electrode is provided. The semiconductor pattern includes at least two channel areas, at least one doping area, a source area, and a drain area.... Agent: Jianq Chyun Intellectual Property Office

20090173945 - Method for forming conductive film, thin-film transistor, panel with thin-film transistor, and method for manufacturing thin-film transistor: A conductive film having high adhesion and low specific resistance is formed. A target containing copper as a main component is sputtered in vacuum ambience while an oxygen gas introduced, and then, a conductive film containing copper as a main component and additive metals, such as Ti or Zr, is... Agent: Kratz, Quintos & Hanson, LLP

20090173944 - Thin film transistor, active device array substrate and liquid crystal display panel: A thin film transistor (TFT) includes a substrate, a gate, a gate dielectric layer, a channel layer, a source and a drain. The gate and the gate dielectric layer are disposed on the substrate and the gate dielectric layer covers the gate. The channel layer is disposed on the gate... Agent: Jianq Chyun Intellectual Property Office

20090173947 - Display substrate and display panel having the same: A display substrate according to exemplary embodiments of the present invention includes a transistor layer, a color filter layer and a pixel electrode. The transistor layer includes a transistor connected to a gate line and a data line crossing each other, and a contact part extending from a drain electrode... Agent: Cantor Colburn, LLP

20090173946 - Pixel structure and active device array substrate: A pixel structure including an active device, a common line pattern, a protective layer, a pixel electrode, and a patterned semiconductor layer is provided. The active device is disposed on a substrate. In addition, the common line pattern is disposed on the substrate and covered with an insulation layer. The... Agent: Jianq Chyun Intellectual Property Office

20090173948 - Uniform large-grained and grain boundary location manipulated polycrystalline thin film semiconductors formed using sequential lateral solidification and devices formed thereon: Methods for processing an amorphous silicon thin film sample into a polycrystalline silicon thin film are disclosed. In one preferred arrangement, a method includes the steps of generating a sequence of excimer laser pulses, controllably modulating each excimer laser pulse in the sequence to a predetermined fluence, homoginizing each modulated... Agent: Baker Botts L.L.P.

20090173951 - Compound semiconductor device using sic substrate and its manufacture: A compound semiconductor device includes: a conductive SiC substrate; an AlN buffer layer formed on said conductive SiC substrate and containing Cl; a compound semiconductor buffer layer formed on said AlN layer which contains Cl, said compound semiconductor buffer layer not containing Cl; and a device constituent layer or layers... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090173950 - Controlling diamond film surfaces and layering: A method comprising: providing at least one first diamond film comprising polycrystalline diamond, e.g., nanocrystalline or ultrananocrystalline diamond, disposed on a substrate, wherein the first diamond film comprises a surface comprising diamond asperities and having a first diamond film thickness, removing asperities from the first diamond film to form a... Agent: Foley And Lardner LLP Suite 500

20090173949 - Silicon carbide mos field effect transistor with built-in schottky diode and method for manufacturing such transistor: This invention has a cell incorporating a built-in Schottky diode region disposed in at least part of an elementary cell that constitutes an SiC vertical MOSFET provided in a low-density p-type deposit film with a channel region and a base region inverted to an n-type by ion implantation. This built-in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090173952 - Semiconductor light-emitting device, illuminator and method of manufacturing semiconductor light-emitting device: A semiconductor light-emitting device having high reliability is obtained while suppressing separation between a support substrate and a semiconductor element layer. This semiconductor light-emitting device includes a support substrate (1), a first bonding layer (2a) formed on the support substrate (1), a second bonding layer (2b) formed on the first... Agent: Ditthavong Mori & Steiner, P.C.

20090173953 - Package with overlapping devices: A die package is disclosed. The die package includes a substrate, a first device attached to the substrate, and a leadframe structure attached to the substrate. The leadframe structure includes a portion disposed over the first device, and a second device is attached to the first portion of the leadframe... Agent: Townsend And Townsend And Crew, LLP

20090173954 - Semiconducting sheet: A substrate-free semiconducting sheet has an array of semiconducting elements dispersed in a matrix material. The matrix material is bonded to the edge surfaces of the semiconducting elements and the substrate-free semiconducting sheet is substantially the same thickness as the semiconducting elements.... Agent: Goldeneye, Inc.

20090173955 - White light emitting device: The invention relates to a monolithic white light emitting device using wafer bonding or metal bonding. In the invention, a conductive submount substrate is provided. A first light emitter is bonded onto the conductive submount substrate by a metal layer. In the first light emitter, a p-type nitride semiconductor layer,... Agent: Mcdermott Will & Emery LLP

20090173956 - Contact for a semiconductor light emitting device: An AlGaInP light emitting device is formed as a thin, flip chip device. The device includes a semiconductor structure comprising an AlGaInP light emitting layer disposed between an n-type region and a p-type region. N- and p-contacts electrically connected to the n- and p-type regions are both formed on the... Agent: Philips Intellectual Property & Standards

20090173958 - Light emitting devices with high efficiency phospor structures: A light emitting device includes a light emitting die configured to emit light having a first dominant wavelength, and an index matched wavelength conversion structure configured to receive light emitted by the light emitting die. The index matched wavelength conversion structure includes wavelength converting particles having a first index of... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090173959 - Panel-shaped semiconductor module: A solar battery module as a panel-shaped semiconductor module comprises multiple rod-shaped electric power generation semiconductor elements arranged in multiple rows and columns, a conductive connection mechanism connecting in series multiple semiconductor elements in each column and electrically connecting in parallel multiple semiconductor elements in each row, and a conductive... Agent: Jordan And Hamburg LLP

20090173960 - Semiconductor light emitting device with pre-fabricated wavelength converting element: A semiconductor light emitting device is provided with a separately fabricated wavelength converting element. The wavelength converting element, of e.g., phosphor and glass, is produced in a sheet that is separated into individual wavelength converting elements, which are bonded to light emitting devices. The wavelength converting elements may be grouped... Agent: Philips Intellectual Property & Standards

20090173957 - Wavelength-converting converter material, light-emitting optical component, and method for the production thereof: Disclosed is a wavelength-converting converter material comprising at least one wavelength-converting phosphor comprising phosphor particles, wherein a portion of said phosphor or all of said phosphor is present in the form of nanoparticles. Also disclosed is a light-emitting optical component comprising such a converter material and a method for producing... Agent: Fish & Richardson PC

20090173961 - Led semiconductor body and use of an led semiconductor body: An LED semiconductor body comprising a first radiation-generating active layer and a second radiation-generating active layer, the first active layer and the second active layer being arranged one above another in the vertical direction.... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090173963 - Light-emitting device: The present invention is related to a light-emitting device. The present invention illustrates a vertical light-emitting device in one embodiment, comprising the following elements: a conductive substrate includes a through-hole, a patterned semiconductor structure disposed on a first surface of the substrate, a first bonding pad and a second bonding... Agent: Bacon & Thomas, PLLC

20090173962 - Semiconductor light-emitting device, method of manufacturing the same, and lamp including the same: A semiconductor light-emitting device having a high light emission property and preventing an electrode from being peeled off during wire bonding. Also disclosed is a method of manufacturing a semiconductor light-emitting device 1 in which an n-type semiconductor layer (13), a light-emitting layer (14), and a p-type semiconductor layer (15)... Agent: Sughrue Mion, PLLC

20090173964 - Method of forming a carbon nanotube-based contact to semiconductor: Manufacturers encounter limitations in forming low resistance ohmic electrical contact to semiconductor material P-type Gallium Nitride (p-GaN), commonly used in photonic applications, such that the contact is highly transparent to the light emission of the device. Carbon nanotubes (CNTs) can address this problem due to their combined metallic and semiconducting... Agent: Wilmerhale/boston

20090173965 - Method of manufacturing nitride semiconductor light emitting device and nitride semiconductor light emitting device manufactured using the method: There are provided a method of manufacturing a nitride semiconductor light emitting device and a nitride semiconductor light emitting device manufactured using the same. A method of manufacturing a nitride semiconductor light emitting device according to an aspect of the invention includes: forming a mask layer on a substrate; removing... Agent: Mcdermott Will & Emery LLP

20090173966 - Integrated low leakage diode: An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to the gate and the comparable MOSFET... Agent: Hiscock & Barclay, LLP

20090173967 - Strained-channel fet comprising twist-bonded semiconductor layer: This invention provides a strained-channel field effect transistor (FET) in which the semiconductor of the channel of the FET is formed in a compliant substrate layer disposed over a twist-bonded semiconductor interface. This FET geometry increases the efficacy of local stress elements such as stress liners and embedded lattice-mismatched source/drain... Agent: Scully, Scott, Murphy & Presser, P.C.

20090173968 - Field effect transistor: A semiconductor device 100 contains an undoped GaN channel layer 105, an AlGaN electron donor layer 106 provided on the undoped GaN channel layer 105 as being brought into contact therewith, an undoped GaN layer 107 provided on the AlGaN electron donor layer 106, a source electrode 101 and a... Agent: Young & Thompson

20090173969 - Semiconductor device: As shown in FIG. 1, in a semiconductor device having an AlGaN—GaN heterojunction structure including an AlGaN layer 1 and a GaN layer 2, when the Al molar fraction of AlGaN (x %) and the thickness of the AlGaN layer (y nm) satisfy the relations: x+y<55, 25≦x≦40, and y≧10, y... Agent: Mcginn Intellectual Property Law Group, PLLC

20090173970 - Method of fabricating hetero-junction bipolar transistor (hbt) and structure thereof: A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation <110>. The hetero-junction bipolar structure may include an emitter, a base and a collector. The substrate may include a... Agent: Hoffman Warnick LLC

20090173971 - Memory cell layout structure with outer bitline: An integrated circuit (IC) includes a memory cell having source/drain regions for defining source/drains of a first pull-up or pull-down (PU/PD) transistor for a first storage node, a second PU/PD transistor for a second storage node, and driver, cell pass, and buffer pass transistors. The memory cell includes a first... Agent: Texas Instruments Incorporated

20090173972 - Semiconductor device: In a substrate power supply cell, a portion of a substrate power supply wiring is exposed by forming a power supply wiring in a U-shape, and a connection portion to an upper-layer wiring is provided at a boundary portion of the substrate power supply cell. Thereby, a leakage current is... Agent: Mcdermott Will & Emery LLP

20090173973 - Semiconductor device and method of manufacturing the same: A semiconductor device has a semiconductor (e.g., a silicon substrate), an electrically conductive region (e.g., a source region and a drain region) which is in contact with the semiconductor to form a Schottky junction, and an insulator. The insulator is in contact with the semiconductor and the electrically conductive region,... Agent: Birch Stewart Kolasch & Birch

20090173976 - Light-sensing device for multi-spectral imaging: A method of fabricating multi-spectral photo-sensors including photo-diodes incorporating stacked epitaxial superlattices monolithically integrated with CMOS devices on a common semiconductor substrate.... Agent: Sturm & Fix LLP

20090173974 - Two-by-two pixel structure in an imaging system-on-chip: The claimed subject matter provides systems and/or methods that facilitate mitigating an impact resulting from mismatch between signal chains in a CMOS imaging System-on-Chip (iSoC) sensor. Two-by-two pixel structures can be a basic building block upon which a pixel array is constructed. Further, each two-by-two pixel structure can be associated... Agent: Turocy & Watson, LLP

20090173975 - Well for cmos imager and method of formation: A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity... Agent: Dickstein Shapiro LLP

20090173977 - Method of mram fabrication with zero electrical shorting: An MTJ cell without footings and free from electrical short-circuits across a tunneling barrier layer is formed by using a Ta hard mask layer and a combination of etches. A first etch patterns the Ta hard mask, while a second etch uses O2 applied in a single high power process... Agent: Saile Ackerman LLC

20090173978 - Semiconductor memory cell and semiconductor memory array using the same: A memory element including a first FET, and a selection switch including a second FET are connected in series, and a semiconductor film and a dielectric film stacked over a substrate form a common channel and a common gate insulating film in the first and second FETs. A first gate... Agent: Mcdermott Will & Emery LLP

20090173979 - Ald of amorphous lanthanide doped tiox films: The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiOX) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and thulium, produces a reliable structure for use in a variety of electronic devices. The dielectric structure is formed by depositing titanium... Agent: Schwegman, Lundberg & Woessner/micron

20090173980 - Providing isolation for wordline passing over deep trench capacitor: A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of... Agent: International Business Machines Corporation Dept. 18g

20090173981 - Nonvolatile semiconductor storage device and method of manufacturing the same: A nonvolatile semiconductor storage device has a first laminated portion including first insulating layers and first conductive layers laminated alternately, and a second laminated portion provided on an upper surface of the first laminated portion and including a second conductive layer formed between second insulating layers. The first laminated portion... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090173982 - Method for forming memory cell and device: A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells and the plurality of access transistor selects which... Agent: Trask Britt, P.C./ Micron Technology

20090173983 - Semiconductor device and method of fabricating the same: A semiconductor device, comprising: a substrate; a floating body region formed in the substrate, a gate electrode formed above a first surface region of the floating body region via a gate insulating film, the gate electrode being connected to a word line; and source and drain regions, respectively, formed on... Agent: Foley And Lardner LLP Suite 500

20090173985 - Dense arrays and charge storage devices: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.... Agent: Foley And Lardner LLP Suite 500

20090173984 - Integrated circuit and method of manufacturing an integrated circuit: The present invention provides an integrated circuit with a floating body transistor comprising two source/drain regions and a floating body region arranged between the two source/drain regions comprising: a back gate electrode separated from the floating body by a first dielectric layer; a control gate electrode, separated from the floating... Agent: Coats & Bennett/qimonda

20090173986 - Semiconductor devices including gate structures and leakage barrier oxides: Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the... Agent: Myers Bigel Sibley & Sajovec

20090173987 - Flash memory device with isolation structure: A flash memory device includes trenches that are formed at regions on a semiconductor substrate spaced apart from one another at predetermined distances, buried floating gates buried into the trenches, a plurality of isolation structures formed between the buried floating gates, and a dielectric film and a control gate formed... Agent: Townsend And Townsend And Crew, LLP

20090173988 - Flash memory device and method of fabricating the same: A flash memory device includes control gates that are formed to completely surround the top and sides of floating gates. The control gates are located between the floating gates that are adjacent in the word line direction as well as the floating gates that are adjacent in the bit line... Agent: Townsend And Townsend And Crew, LLP

20090173989 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory of an aspect of the present invention includes a memory cell including, a charge storage layer on a gate insulating film, a multilayer insulator on the charge storage layer, and a control gate electrode on the multilayer insulator, the gate insulating film including a first tunnel... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090173991 - Methods for forming rhodium-based charge traps and apparatus including rhodium-based charge traps: Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge traps in electronic structures for use in a wide range of electronic devices and systems. In an embodiment, conductive nanoparticles are deposited on a dielectric layer by a plasma-assisted deposition process such that... Agent: Schwegman, Lundberg & Woessner/micron

20090173990 - Structures for and method of silicide formation on memory array and peripheral logic devices: A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage transistors. A second gate dielectric layer having... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090173992 - Semiconductor device with improved performance characteristics: The semiconductor device includes an active region, a recess, a Fin channel region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess is formed by etching the active region and its neighboring device isolation... Agent: Townsend And Townsend And Crew, LLP

20090173994 - Recess gate transistor: A recess gate of a semiconductor device is provided, comprising: a substrate having a recess formed therein; a metal layer formed at the bottom of the recess; a polysilicon layer formed over the metal layer; and a source region and a drain region formed adjacent to the polysilicon layer and... Agent: F. Chau & Associates, LLC

20090173996 - Recess gate type transistor: A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the... Agent: Marshall, Gerstein & Borun LLP

20090173993 - Structure and method of forming a topside contact to a backside terminal of a semiconductor device: A vertically conducting semiconductor device includes a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. An epitaxial layer extends over the topside surface of the semiconductor substrate but... Agent: Townsend And Townsend And Crew, LLP

20090173995 - Trench semiconductor device of improved voltage strength, and method of fabrication: A trench IGBT is disclosed which includes a semiconductor substrate having formed therein a set of cell trenches formed centrally and a set of annular guard trenches concentrically surrounding the cell trenches. The cell trenches receive cell trench conductors via cell trench insulators for providing IGBT cells. The guard trenches... Agent: Woodcock Washburn LLP

20090173997 - Mosfet and method for manufacturing mosfet: The present invention provides a MOSFET and so forth that offer high breakdown voltage and low on-state loss (high channel mobility and low gate threshold voltage) and that can easily achieve normally OFF. A drift layer 2 of a MOSFET made of silicon carbide according to the present invention has... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090173998 - Semiconductor device and manufacturing method thereof: In a MIS transistor of which gate length is 10 nm or less, a gate insulator comprising a silicon oxide film formed on a silicon substrate and a high-k film formed on the silicon oxide film has a nitrided region including more nitrogen at the lateral side than at the... Agent: Reed Smith LLP

20090173999 - Field effect transistor with gate having varying sheet resistance: A field effect transistor (FET) comprising a gate structure that includes at least one gate having a varying sheet resistance in a direction between a source contact and a drain contact. In an illustrative embodiment, the FET can be configured to operate as a radio frequency switch. In this case,... Agent: Hoffman Warnick LLC

20090174001 - Semiconductor device having fin transistor and planar transistor and associated methods of manufacture: Disclosed is a fin transistor and a planar transistor and a method of forming the same. The fin transistor and the planar transistor are formed to have gate electrodes with similar thicknesses by selectively recessing a semiconductor substrate in a planar region where the planar transistor is formed.... Agent: Volentine & Whitt PLLC

20090174000 - Semiconductor device including insulated-gate field-effect transistor: Fins of semiconductor are formed on the substrate. Each of the fins is located separately from one another. A gate insulating film is formed on side surfaces of the fins. A gate electrode is formed on the gate insulating film. The gate electrode extends to cross over the fins. A... Agent: Turocy & Watson, LLP

20090174003 - Dual work function device with stressor layer and method for manufacturing the same: A method for manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method relates to providing a substrate with a first and a second region. A gate dielectric is formed overlying the first and the second region. A metal gate layer is formed overlying the gate... Agent: Knobbe Martens Olson & Bear LLP

20090174002 - Mosfet having a high stress in the channel region: Source and drain extension regions are selectively removed by a dopant concentration dependent etch or a doping type dependent etch, and an embedded stress-generating material such as SiGe alloy or a Si:C alloy in the source and drain extension regions is grown on a semiconductor substrate. The embedded stress-generating material... Agent: Scully, Scott, Murphy & Presser, P.C.

20090174004 - Semiconductor device and fabricating method thereof: A semiconductor device including a semiconductor substrate having first and second device regions. A first trench is formed in the first region and a second trench is formed in the second region. The first trench and the second trench have different widths and different depths. The first trench and the... Agent: Lowe Hauptman Ham & Berner, LLP

20090174005 - Semiconductor device with gate-undercutting recessed region: A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.... Agent: Texas Instruments Incorporated

20090174007 - Semiconductor memory device: A semiconductor memory device comprising: a support substrate; an insulating film formed on the support substrate; a semiconductor film formed on the insulating film; a gate insulating film formed on the semiconductor film; a gate electrode film formed on the gate insulating film; and a source region and a drain... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090174006 - Structure and method of creating entirely self-aligned metallic contacts: The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper... Agent: Scully, Scott, Murphy & Presser, P.C.

20090174008 - Method and structure to protect fets from plasma damage during feol processing: Protecting a FET from plasma damage during FEOL processing by forming a FET-like structure in conjunction with and adjacent to an FET, in a same well as the FET, but having a body doped opposite to the well polarity. The FET-like structure is formed with thinner oxide than the gate... Agent: International Business Machines Corporation Dept. 18g

20090174009 - Semiconductor device and method for producing the same: The semiconductor device includes the concentration of the impurity of the first conductivity type in a doped channel layer of a first conductivity type in the pass transistor is set at a relatively low value, and pocket regions of the first conductivity type in a pass transistor are formed so... Agent: Fujitsu Patent Center C/o Cpa Global

20090174010 - Sram device structure including same band gap transistors having gate stacks with high-k dielectrics and same work function: An SRAM semiconductor device includes: at least a first and a second field effect transistor formed on a same substrate, each of the transistors including a gate stack, each gate stack including a semiconductor layer disposed on a metal layer, the metal layer being disposed on a high-k dielectric layer... Agent: International Business Machines Corporation Dept. 18g

20090174011 - Semiconductor device having guard ring: A semiconductor device includes an internal circuit region on a semiconductor substrate, at least one guard ring on the semiconductor substrate, the guard ring surrounding the internal circuit region, and at least one current blocking unit on the semiconductor substrate, the current blocking unit being configured to block an electric... Agent: Lee & Morse, P.C.

20090174012 - Field effect transistor: Provided is a field effect transistor, provided with a gate electrode 15, a source electrode 13, and a drain electrode 14 formed on a substrate, including a channel layer 11 formed of an oxide containing In, Zn, or Sn as the main component, and a gate insulating layer 12 provided... Agent: Fitzpatrick Cella Harper & Scinto

20090174013 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a silicon substrate, an SiO film, and a High-K film. The SiO film is first formed on the silicon substrate and then subjected to a nitridation process to obtain an SiON film from the SiO film. The nitridation process is performed such that nitrogen concentration in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090174014 - Micromechanical actuators comprising semiconductors on a group iii nitride basis: A semiconductor actuator includes a substrate base, a bending structure which is connected to the substrate base and can be deflected at least partially relative to the substrate base. The bending structure has semiconductor compounds on the basis of nitrides of main group III elements and at least two electrical... Agent: Fay Kaplun & Marcin, LLP

20090174016 - Magnetic memory device: A magnetic memory device is provided in which, even when a recording layer having an asymmetric shape and a local via are formed over a strap wiring with a sufficient distance allowed therebetween, increase in the size of the magnetic memory device can be suppressed. The magnetic memory device includes... Agent: Miles & Stockbridge PC

20090174015 - Memory cell and method of forming a magnetic tunnel junction (mtj) of a memory cell: A memory including a memory cell and method for producing the memory cell are disclosed. The memory includes a substrate in a first plane. A first metal connection extending in a second plane is provided. The second plane is substantially perpendicular to the first plane. A magnetic tunnel junction (MTJ)... Agent: Qualcomm Incorporated

20090174017 - Solid-state image sensor and method for manufacturing thereof as well as semiconductor device and method for manufacturing thereof: A solid-state image sensor and a method for manufacturing thereof and a semiconductor device and a method for manufacturing thereof are provided. A semiconductor substrate is made to be the thin film without using an SOI substrate and cost is reduced. An edge detection portion having hardness larger than that... Agent: K&l Gates LLP

20090174018 - Construction methods for backside illuminated image sensors: A method of constructing a backside illuminated image sensor is described. The method includes the steps of forming a semiconductor wafer, forming at least electrical contacts in the semiconductor wafer, forming, in a handle wafer separate from the semiconductor wafer, a plurality of via holes, attaching the semiconductor wafer to... Agent: Ratnerprestia

20090174019 - Image sensing device and manufacture method thereof: An image sensing device for receiving an incident light having an incident angle and photo signals formed thereby is provided. The image sensing device includes a micro prism and a micro lens for adjusting the incident angle and converging the incident light, respectively, a photo sensor for converting the photo... Agent: Haverstock & Owens LLP

20090174020 - Solid-state imaging device and method for manufacturing the same: A solid state imaging device includes a substrate having a plurality of pixels and a plurality of on-chip lenses arranged above the substrate, each on-chip lens having a lens surface formed by subjecting a transparent photosensitive film to exposure using a mask having a gradation pattern and development so that... Agent: Robert J. Depke Lewis T. Steadman

20090174021 - Photodiode for multiple wavelength operation: A photodiode includes a substrate having a first semiconductor type surface region on at least a portion thereof, and a second semiconductor type surface layer formed in a portion of the surface region. A multi-layer anti-reflective coating (ARC) is on the second semiconductor type surface layer, wherein the multi-layer ARC... Agent: Fliesler Meyer LLP

20090174022 - Hyperspectral imaging device: An hyperspectral imaging device comprising semiconductor nanocrystals is provided.... Agent: Martha Ann Finnegan Qd Vision, Inc.

20090174023 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor element is formed on a first surface of the substrate. A resin layer is formed over a second surface of the substrate which is opposite to the first surface of the substrate and on a part of the side surface of the substrate. A step is formed on... Agent: Eric Robinson

20090174024 - Image sensor and method for manufacturing the same: Embodiments relate to an image sensor and a method of manufacturing the same. According to embodiments, an image sensor may include a first substrate having circuitry formed thereon. It may further include a photodiode bonded to the first substrate and electrically connected to the circuitry, and a contact plug at... Agent: Sherr & Vaughn, PLLC

20090174025 - Image sensor and method for manufacturing the same: An image sensor can include a first substrate, an insulating layer, a photodiode, and a via plug. A circuitry including an interconnection can be formed on the first substrate. The insulating layer is formed over the first substrate so that the insulating layer covers the interconnection. The photodiode is formed... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090174026 - Silicon-based visible and near-infrared optoelectric devices: In one aspect, the present invention provides a silicon photodetector having a surface layer that is doped with sulfur inclusions with an average concentration in a range of about 0.5 atom percent to about 1.5 atom percent. The surface layer forms a diode junction with an underlying portion of the... Agent: Nutter Mcclennen & Fish LLP

20090174027 - Integrated circuit including isolation regions substantially through substrate: An integrated circuit including a substrate and trench isolation regions. The substrate supports a device. The trench isolation regions are configured to laterally isolate the device. The trench isolation regions extend substantially through the substrate.... Agent: Dicke, Billig & Czaja

20090174028 - Fuse in a semiconductor device and method for forming the same: A fuse of a semiconductor device, and a method for forming the same, wherein the fuse includes a zigzag-shaped fuse portion on a planar structure, thereby reducing energy when the fuse is cut. The laser irradiation time can be reduced, thereby preventing fuse cutting defects and damages on a neighboring... Agent: Marshall, Gerstein & Borun LLP

20090174029 - Semiconductor device and method of fabricating the same: A semiconductor device is provided including a first fuse link having a copper-containing metal film, a second fuse link having a polysilicon film, a semiconductor substrate, and a field insulating film formed on the semiconductor substrate. The second fuse link is formed on the field insulating film. An interlayer insulating... Agent: Mcginn Intellectual Property Law Group, PLLC

20090174031 - Dram having deep trench capacitors with lightly doped buried plates: By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm−3, a voltage difference between the... Agent: International Business Machines Corporation Dept. 18g

20090174030 - Linearity capacitor structure and method: Method (200) and apparatus (30, 50-53) are described for MOS capacitors (MOS CAPs). The apparatus (30, 50-53) comprises a substrate (31) having Ohmically coupled N and P semiconductor regions (32, 34; 54, 56; 92, 94) covered by a dielectric (35, 57, 95). A conductive electrode (36, 58, 96) overlies the... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20090174032 - Resistance change memory device: A resistance change memory device includes: a semiconductor substrate; a three dimensional cell array formed by a plurality of unit cell array blocks of two dimensional arrangement on the semiconductor substrate, the unit cell array block being formed by stacking a plurality of unit cell arrays including a first wiring,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090174033 - Adjustible resistor for use in a resistive divider circuit and method for manufacturing: A method of manufacturing a resistive divider circuit, comprising providing a silicon body (6) having a plurality of opposing pairs of intermediate taps extending therefrom. Each tap comprises a thin silicon stem (61) supporting a relatively wider silicon platform (62). A silicidation protection (SIPROT) layer (S) is deposited over the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090174034 - Semiconductor device and method of manufacturing such a device: The invention relates to a semiconductor device (10) with a substrate (12) and a semiconductor body (11) of silicon comprising a bipolar transistor with an emitter region, a base region and a collector region (1,2,3) first conductivity type, a second conductivity type opposite to said first conductivity type and the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090174035 - Semiconductor device: A semiconductor device includes a semiconductor substrate formed of at least two kinds of group III elements and nitrogen, an active layer formed on the semiconductor substrate, and a nitride semiconductor layer formed on a surface of the semiconductor substrate and formed between the semiconductor substrate and the active layer.... Agent: Ndq&m Watchstone LLP

20090174036 - Plasma curing of patterning materials for aggressively scaled features: A methodology is disclosed that enables the fabrication of semiconductor devices (i.e., STI structures, gates, and interconnects) with significantly reduced line edge roughness (LER) and line width roughness (LEW) post lithography patterning. The inventive methodology entails the use of an inert species containing plasma tuned to enhanced its' vacuum ultra... Agent: Scully, Scott, Murphy & Presser, P.C.

20090174038 - Production of single-crystal semiconductor material using a nanostructure template: A method of producing single-crystal semiconductor material comprises: providing a template material; creating a mask on top of the template material; using the mask to form a plurality of nanostructures in the template material; and growing the single-crystal semiconductor material onto the nanostructures.... Agent: Christie, Parker & Hale, LLP

20090174037 - Semiconductor substrate, method of fabricating the same, method of fabricating semiconductor device, and method of fabricating image sensor: In an example embodiment, an image sensor includes a semiconductor layer and isolation regions disposed in the semiconductor layer. The isolation regions define active regions of the semiconductor layer. The image sensor further includes photoelectric converters disposed in the semiconductor layer and at least one wiring layer disposed over a... Agent: Marger Johnson & Mccollom, P.C.

20090174039 - Semiconductor device and method of forming the same: A semiconductor device and a method of forming the same are provided. A semiconductor device may comprise a semiconductor substrate including a main surface configured to define a groove, a trench, and a cavity sequentially disposed downward from a given region of the main surface and open toward the main... Agent: Harness, Dickey & Pierce, P.L.C

20090174040 - Sacrificial pillar dielectric platform: Briefly, in accordance with one or more embodiments, a dielectric platform is at least partially formed in a semiconductor substrate and extending at least partially below a surface of a semiconductor substrate. The dielectric platform may include structural pillars formed by backfilling a first plurality of cavities etched in the... Agent: Hvvi Semiconductors, Inc.

20090174041 - Ultraviolet blocking structure and method for semiconductor device: Structures and methods for blocking ultraviolet rays during a film depositing process for semiconductor device are disclosed. In one embodiment, a semiconductor device includes an oxide-nitride-oxide (ONO) film formed on a semiconductor substrate, a gate electrode formed on the ONO film, a lower layer insulation film formed on the ONO... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090174042 - Radio frequency over-molded leadframe package: An over-molded leadframe (e.g., a Quad Flat No-lead (QFN)) package capable of operating at frequencies in the range of about five gigahertz (GHz) to about 300 GHz and a method of making the over-molded leadframe package are disclosed. The over-molded leadframe package includes a capacitance lead configured to substantially reduce... Agent: Snell & Wilmer L.L.P. (main)

20090174043 - Flexible contactless wire bonding structure and methodology for semiconductor device: A semiconductor device such as a field-effect transistor, improved to reduce device resistance, comprises a leadframe which includes a die paddle integral with a first set of leads and a second set of leads that is electrically isolated from the first set, a semiconductor die having its lower surface positioned... Agent: Mcdermott Will & Emery LLP

20090174044 - Multi-chip package: A semiconductor package is disclosed. Particularly, a multi-chip package is disclosed, which can stably maintain insulation between a plurality of semiconductor chips and effectively release heat to the outside. The semiconductor package includes an insulation layer including a diamond layer formed by a chemical vapor deposition method between a lead... Agent: Townsend And Townsend And Crew, LLP

20090174045 - Bump pad metallurgy employing an electrolytic cu / electorlytic ni / electrolytic cu stack: An electroless Cu layer is formed on each side of a packaging substrate containing a core, at least one front metal interconnect layer, and at least one backside metal interconnect layer. A photoresist is applied on both electroless Cu layers and lithographically patterned. First electrolytic Cu portions are formed on... Agent: Scully, Scott, Murphy & Presser, P.C.

20090174048 - Die package including substrate with molded device: A package is disclosed. The package includes a premolded substrate having a leadframe structure, a first device attached to the leadframe structure, and a molding material covering at least part of the leadframe structure and the first device. It also includes a second device attached to the premolded substrate.... Agent: Townsend And Townsend And Crew, LLP

20090174047 - Semiconductor die packages having overlapping dice, system using the same, and methods of making the same: Disclosed are semiconductor die packages having overlapping dice, systems that use such packages, and methods of making such packages. An exemplary die package comprises a leadframe, a first semiconductor die, and a second semiconductor die that has a recessed portion in one of its surfaces. The first die is disposed... Agent: Townsend And Townsend And Crew, LLP

20090174046 - Semiconductor package with an embedded printed circuit board and stacked die: A two tier power module has, in one form thereof, a PC board having upper and lower traces with an opening in the insulating material that contains a power device which has upward extending solder bump connections. An upper leadframe is mounted on the solder bumps and the upper tracks... Agent: Hiscock & Barclay, LLP

20090174049 - Ultra thin image sensor package structure and method for fabrication: An image sensor package having at least one chip supporting bar secured to a top surface of an image sensor chip. The thickness of the chip supporting bar is absorbed within a vertical dimension of wire loops that connect bonding pads to leads so that the chip supporting bar does... Agent: Kenton R. Mullins Stout, Uxa, Buyan & Mullins, LLP

20090174050 - In-plane silicon heat spreader and method therefor: A method of (and heat spreader for) dissipating heat from a heat source, includes providing a plurality of heat flux paths from the heat source, to remove the heat from the heat source.... Agent: Mcginn Intellectual Property Law Group, PLLC

20090174051 - Semiconductor package and semiconductor device: A substrate in which a plurality of terminals for a test and a plurality of terminals for external connection are arranged on the front surface, and a plurality of terminals for internal connection are arranged on the back surface, and a semiconductor chip in which a plurality of surface terminals... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090174058 - Chip scale package: A method for manufacturing a semiconductor package that includes forming a frame inside a conductive can, the frame being unwettable by liquid solder.... Agent: Ostrolenk Faber Gerb & Soffen

20090174052 - Electronic component, semiconductor package, and electronic device: In a conventional UBM made of, for example, Cu, Ni, or NiP, there has been a problem that when an electronic component is held in high-temperature conditions for an extended period, the barrier characteristic of the UBM is lost and the bonding strength decreases due to formation of a brittle... Agent: Sughrue Mion, PLLC

20090174055 - Leadless semiconductor packages: An encapsulation technique for leadless semiconductor packages entails: (a) attaching a plurality of dice (411) to die pads in cavities (41-45, 51-55) of a leadframe, the cavities arranged in a matrix of columns and rows; (b) electrically connecting the dice to a plurality of conducting portions (412-414) of the leadframe;... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20090174054 - Module with flat construction and method for placing components: A module for electrical components is proposed in which connection surfaces that can be bonded are provided on a multi-layer substrate with integrated wiring; a component chip is bonded on the top that has bond pads on its surface pointing upward and that contacts the substrate by means of bonding... Agent: Slater & Matsil, L.L.P.

20090174057 - Semiconductor device and programming method: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090174056 - Semiconductor module: A semiconductor module is disclosed. One embodiment provides a first semiconductor chip having a first contact pad on a first main surface and a second contact pad on a second main surface, a first electrically conductive layer applied to the first main surface, a second electrically conductive layer applied to... Agent: Dicke, Billig & Czaja

20090174053 - Substrate for semiconductor device, resin-sealed semiconductor device, method for manufacturing said substrate for semiconductor device and method for manufacturing said resin-sealed semiconductor device: A substrate 10 for a semiconductor device includes: a base plate 1, a plurality of external terminal portions 12p, 12q, respectively arranged in a plane on the base plate 1 and having external terminal faces 12pb, 12qb respectively facing the base plate 1; a plurality of internal terminal portions 11,... Agent: Oliff & Berridge, PLC

20090174059 - Method and manufacture of silicon based package and devices manufactured thereby: A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface... Agent: John A. Jordan, Esq.

20090174062 - Circuit board, semiconductor device, and manufacturing method of circuit board: A circuit board includes a semiconductor substrate which has a plurality of through holes passing from an upper surface to a lower surface thereof. A plurality of wiring lines are provided on the upper surface of the semiconductor substrate and have bottomed cylindrical portions located within regions corresponding to the... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090174060 - Hybrid integrated circuit device, and method for fabricating the same, and electronic device: A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate,... Agent: Mattingly & Malur, P.C.

20090174061 - Semiconductor device: To prevent peeling-off of a film in a solder connection pad of a semiconductor device, which peeling-off may occur due to thermal load and so on in the manufacture process, a pad structure is adopted in which a Cr film good in adhesiveness to either of a Ti film or... Agent: Townsend And Townsend And Crew, LLP

20090174063 - Semiconductor module: A semiconductor module 10 includes a ceramic substrate having a front surface on which a semiconductor element 12 is mounted and a rear surface on the opposite side of the front surface, a front metal plate 15 joined to the front surface, a rear metal plate 16 joined to the... Agent: Locke Lord Bissell & Liddell LLP Attn:IPDocketing

20090174064 - Integrated circuit package system with heat slug: An integrated circuit package system is provided including providing a substrate having a die attached and electrically bonded thereto. The system includes forming heat slug pillars on the substrate, positioning a heat slug on the heat slug pillars, and encapsulating the substrate, the die, the heat slug pillars, and the... Agent: Law Offices Of Mikio Ishimaru

20090174065 - Semiconductor device and method of manufacturing the same: As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining... Agent: Mcdermott Will & Emery LLP

20090174066 - Semiconductor device: In a multi-chip package semiconductor device, a drive chip having an analog circuit and a logic chip having a digital circuit are mounted within the same package. The driver chip includes a logic-chip power-supply circuit that makes up a logic-chip power supply for the logic chip and a group of... Agent: Osha Liang L.L.P.

20090174067 - Airgap-containing interconnect structure with patternable low-k material and method of fabricating: The present invention provides a method of fabricating an airgap-containing interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene airgap-containing low-k interconnect structures with at least... Agent: Scully, Scott, Murphy & Presser, P.C.

20090174068 - Semiconductor device, circuit board, and electronic instrument: A semiconductor device with a package size close to its chip size is, apart from a stress absorbing layer, such as to effectively absorb thermal stresses. A semiconductor device (150) has a semiconductor chip provided with electrodes (158), a resin layer (152) forming a stress relieving layer provided on the... Agent: Oliff & Berridge, PLC

20090174069 - I/o pad structure for enhancing solder joint reliability in integrated circuit devices: A semiconductor device is described. The device includes an integrated circuit die having an active surface that includes a plurality of input/output (I/O) pads. The device further includes a plurality of crack resistant structures. Each crack resistant structure is formed over an associated I/O pad and includes an associated raised... Agent: Beyer Law Group LLP

20090174071 - Semiconductor device including electrically conductive bump and method of manufacturing the same: A semiconductor device and method of manufacturing are provided that include forming an electrically conductive bump on a substrate and forming at least one passivation layer on the bump to reduce solder joint failures.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090174070 - Three-dimensional stacked substrate arrangements: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.... Agent: Intel Corporation C/o Cpa Global

20090174074 - Semiconductor device: The present invention provides a semiconductor device exhibiting an improved reliability of a bump coupling section. A semiconductor device is provided, which comprises: an interconnect layer; a stress-relaxing layer, covering the interconnect layer and provided with an opening exposing at least a portion of the interconnect layer; a post, covering... Agent: Young & Thompson

20090174072 - Semiconductor system having bga package with radially ball-depopulated substrate zones and board with radial via zones: A printed circuit board has contact lands (710) forms an array with depopulated elongated zones (820), which are radially oriented from the board center towards the board periphery. Conductive vias (803) are then clustered into these zones, the radial via channels. The radial orientation of via channels provides space needed... Agent: Texas Instruments Incorporated

20090174073 - Substrate for semiconductor package having coating film and method for manufacturing the same: A substrate for a semiconductor package includes a ball land disposed on one surface of an insulating layer. A solder resist is applied to the surface of insulating layer while leaving the ball land exposed. A coating film is applied on the exposed surface of the 1o ball land. The... Agent: Ladas & Parry LLP

20090174076 - Semiconductor device and the method of manufacturing the same: A semiconductor device includes a semiconductor substrate; a metal electrode wiring laminate on the semiconductor substrate, the metal electrode wiring laminate being patterned with a predetermined wiring pattern; the metal electrode wiring laminate including an undercoating barrier metal laminate and aluminum or aluminum alloy film on the undercoating barrier metal... Agent: Rossi, Kimms & Mcdowell LLP.

20090174075 - Simultaneous grain modulation for beol applications: The invention is directed to an improved semiconductor structure, such that within the same insulating layer, Cu interconnects embedded within the same insulating level layer have a different Cu grain size than other Cu interconnects embedded within the same insulating level layer.... Agent: International Business Machines Corporation Dept. 18g

20090174077 - Method for structuring a substrate: A method and intermediate product for structuring a substrate is disclosed. At least one seed layer including a first metal compound is positioned at least partially on the substrate. The seed layer is subjected to a solution comprising ions of a second metal compound. The ions are reduced in the... Agent: Slater & Matsil, L.L.P.

20090174078 - Semiconductor device and method of manufacturing the same: Provided is a semiconductor device and method of manufacturing the same. The semiconductor device may include a base material and a compound layer on the base material including a mixture of a non-adhesive organic material and a non-oxidizing metal material.... Agent: Harness, Dickey & Pierce, P.L.C

20090174079 - Plated pillar package formation: A device includes a first plurality of interconnects, a first fill material surrounding the first plurality of interconnects, a first plurality of traces, and a first chip. The first plurality of interconnects extend from a first side of the fill material to an opposite side of the fill material. Each... Agent: Foley & Lardner LLP

20090174080 - Semiconductor device: In order to improve the manufacturing yield of a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and attached to each other, the opening shape of each of conductive grooves (4A) formed in each chip (C2) obtained from a wafer (W2) is rectangular, and... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090174081 - Combination substrate: A combination substrate includes a first substrate having multiple wiring board mounting pads for installing a printed wiring board and multiple connection pads on the opposite side of the wiring board mounting pads, a second substrate having multiple package substrate mounting pads for loading one or more package substrates and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090174082 - Three dimensional structure memory: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit... Agent: Michael J. Ure

20090174083 - Wiring board and method of manufacturing the same, and electronic component device using the wiring board and method of manufacturing the same: A wiring board is provided with an external connection terminal to which an electrode terminal of an electronic component is to be connected. The external connection terminal is formed so that a portion thereof is electrically connected to a pad portion exposed from an outermost insulating layer on an electronic... Agent: Kratz, Quintos & Hanson, LLP

20090174085 - Semiconductor chip and semiconductor device, and method for manufacturing semiconductor device: A semiconductor chip is provided comprising a semiconductor substrate on which an integrated circuit is formed. The semiconductor chip, which is provided on the semiconductor substrate in an area array, further comprises a plurality of electrodes electrically coupled with the inside of the semiconductor substrate, wherein the electrodes are arranged... Agent: Harness, Dickey & Pierce, P.L.C

20090174084 - Via offsetting to reduce stress under the first level interconnect (fli) in microelectronics packaging: The invention is directed to an improved microelectronics device that reduces BEOL delamination by reducing the tensile stress imposed on the via which connects first level interconnects with the BEOL. Tensile stress imposed on the via is reduced by shifting the via towards the center of a silicon chip or... Agent: International Business Machines Corporation Dept. 18g

20090166600 - Integrated circuit devices having a stress buffer spacer and methods of fabricating the same: Integrated circuit devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in the contact hole and a stress buffer spacer is provided between the vertical diode and the insulating layer. Methods of forming... Agent: Myers Bigel Sibley & Sajovec

20090166601 - Non-volatile programmable variable resistance element: A phase-change memory element exhibits a non-uniform temperature profile in the phase-change material, resulting in a non-uniform temperature profile. The non-uniform temperature profile causes non-uniform growth of a programmed volume, resulting in a gradual R-I characteristic. The phase-change material may be a chalcogenide material.... Agent: Ovonyx, Inc

20090166603 - Method of forming a small contact in phase-change memory: A method of fabricating a phase-change memory cell is described. The cross-sectional area of a contact with a phase-change memory element within the cell is controlled by a width and an exposed length of a bottom electrode. The method allows the formation of very small phase-change memory cells.... Agent: Stout, Uxa, Buyan & Mullins LLP

20090166602 - Phase-change memory device capable of improving contact resistance and reset current and method of manufacturing the same: A phase-change memory device and a method of manufacturing the same, wherein the phase-change memory device includes a semiconductor substrate having a switching device, a phase-change layer formed on the semiconductor substrate having the switching device to change a phase thereof as the switching device is driven, and a bottom... Agent: Baker & Mckenzie LLP Patent Department

20090166604 - Resistance type memory device: A resistance type memory device is provided. The resistance type memory device includes a first and a second conductors and a metal oxide layer. The metal oxide layer is disposed between the first and the second conductors, and the resistance type memory device is defined in a first resistivity. The... Agent: J C Patents, Inc.

20090166605 - Phase change memory elements using self-aligned phase change material layers and methos of making and using same: A phase change memory element and method of forming the same. The memory element includes a substrate supporting a first electrode. An insulating material element is positioned over the first electrode, and a phase change material layer is formed over the first electrode and surrounding the insulating material element such... Agent: Dickstein Shapiro LLP

20090166608 - Light emitting semiconductor device and fabrication method for the light emitting semiconductor device: A semiconductor light emitting device and a fabrication method for the semiconductor light emitting device whose outward luminous efficiency improved are provided and the semiconductor light emitting device includes a substrate; a protective film placed on the substrate; an n-type semiconductor layer which is placed on the substrate pinched by... Agent: Rabin & Berdo, PC

20090166606 - Nitride semiconductor light emitting device and fabrication method thereof: Provided is a nitride semiconductor light emitting device including: a first nitride semiconductor layer; an active layer formed above the first nitride semiconductor layer; and a delta doped second nitride semiconductor layer formed above the active layer. According to the present invention, the optical power of the nitride semiconductor light... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090166607 - Nitride semiconductor light emitting element: Provided is a nitride semiconductor light emitting element having an improved carrier injection efficiency from a p-type nitride semiconductor layer to an active layer by simple means from a viewpoint utterly different from the prior art. A buffer layer 2, an undoped GaN layer 3, an n-type GaN contact layer... Agent: Rabin & Berdo, PC

20090166613 - Composition for forming gate insulating layer of organic thin-film transistor and organic thin film transistor using the same: The present invention relates to a composition for forming a gate insulating layer of an organic thin film transistor comprising polyarylate, and an organic thin film transistor comprising a gate insulating layer, which is formed using the composition, in contact with an organic semiconductor channel.... Agent: Mckenna Long & Aldridge LLP

20090166614 - Fluorinated rylenetetracarboxylic acid derivatives and use thereof: The present invention relates to fluorinated rylenetetracarboxylic acid derivatives, to a process for their preparation and to their use, especially as n-type semiconductors.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090166609 - Memory cell that employs a selectively fabricated carbon nano-tube reversible resistance-switching element formed over a bottom conductor and methods of forming the same: In some aspects, a method of fabricating a memory cell is provided that includes (1) fabricating a first conductor above a substrate; (2) selectively fabricating a carbon nano-tube (CNT) material above the first conductor; (3) fabricating a diode above the CNT material; and (4) fabricating a second conductor above the... Agent: Dugan & Dugan, PC

20090166610 - Memory cell with planarized carbon nanotube layer and methods of forming the same: In some aspects, a method of fabricating a memory cell is provided that includes (1) fabricating a first conductor above a substrate; (2) fabricating a carbon nano-tube (CNT) material above the first conductor; (3) depositing a dielectric material onto a top surface of the CNT material; (4) planarizing the dielectric... Agent: Dugan & Dugan, PC

20090166615 - Organic light-emitting element and display device: In Formula (1), R1 to R4 are each a hydrogen atom, a halogen atom, a substituted or unsubstituted alkyl group, a substituted or unsubstituted alkoxy group, a substituted or unsubstituted aralkyl group, a substituted or unsubstituted aromatic group, a nitro group, or a cyano group. In Formula (2), n represents... Agent: Canon U.s.a. Inc. Intellectual Property Division

20090166611 - Organic transistor and manufacturing method thereof: [Solving Means] An organic transistor including a substrate 1, a pair of a source electrode 4 and a drain electrode 5, an organic semiconductor layer 6 provided between the source electrode 4 and the drain electrode 5, and a gate electrode 2 provided in association with the organic semiconductor 6... Agent: Wenderoth, Lind & Ponack, L.L.P.

20090166612 - Techniques for device fabrication with self-aligned electrodes: This invention relates to the fabrication of electronic devices, such as thin-film transistors, in particular thin-film transistors in which patterning techniques are used for definition of electrode patterns that need to be accurately aligned with respect to underlying electrodes. The fabrication technique is applicable to various patterning techniques, such as... Agent: Schwegman, Lundberg & Woessner, P.A.

20090166616 - Oxide semiconductor device and surface treatment method of oxide semiconductor: Oxygen defects formed at the boundary between the zinc oxide type oxide semiconductor and the gate insulator are terminated by a surface treatment using sulfur or selenium as an oxygen group element or a compound thereof, the oxygen group element scarcely occurring physical property value change. Sulfur or selenium atoms... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090166617 - Integrated circuit and method for operating: An integrated circuit and a method for operating an integrated circuit is disclosed. One embodiment provides a semi-conductor component, an electronic system, and a method for operating an integrated circuit. A method for operating an integrated circuit provides applying a voltage to a line or a connection in accordance with... Agent: Dicke, Billig & Czaja

20090166621 - Resistance-based etch depth determination for sgt technology: A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test... Agent: Joshua D. Isenberg Jdi Patent

20090166620 - Semiconductor chip: In a semiconductor chip in which external connection pads are arranged in three or more rows in a staggered configuration at the peripheral portion thereof, a first pad which is arranged in the outermost row is used as a power supply pad or a ground pad for an internal core... Agent: Mcdermott Will & Emery LLP

20090166619 - Test pattern of semiconductor device and manufacturing method thereof: A method of manufacturing a test pattern for a semiconductor device includes the steps of forming, on a semiconductor substrate, a moat mask pattern including plural moat lines patterned in a comb-shape and etching a portion of the semiconductor substrate exposed by the moat mask pattern, to form a trench.... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090166618 - Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.... Agent: Williams, Morgan & Amerson

20090166624 - Crystallization apparatus, crystallization method, phase modulation element, device and display apparatus: A phase modulation element according to the present invention has a first area having a first phase value based on a phase modulation unit having a predetermined size and a second area having a second phase value based on the phase modulation unit having the predetermined size, and each phase... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090166622 - Plasma processing apparatus and semiconductor element manufactured by such apparatus: When a flow rate of a diluent gas is larger than a flow rate of a reaction gas, a reaction gas introducing tube (113) is connected to a part of a diluent gas introducing tube (111) which connects a plasma processing reaction chamber (101) to a diluent gas feeding unit... Agent: Nixon & Vanderhye, PC

20090166623 - Semiconductor device and method of manufacturing the semiconductor device: A first interconnection is formed along a groove of a substrate and on a bottom surface of the groove, and has a first thickness. A second interconnection is electrically connected to the first interconnection and has a second thickness larger than the first thickness. An acceleration sensing unit is electrically... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090166625 - Mos device structure: The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective... Agent: J C Patents, Inc.

20090166626 - Producing method for crystalline thin film: A method for producing a crystalline film by melting and resolidifying a film, characterized in preparing a film having a specific region and obtained either by (A) a step of forming a film in which a “specific region” and an “region continuous to a periphery of the specific region and... Agent: Fitzpatrick Cella Harper & Scinto

20090166627 - Image sensor and method for manufacturing the same: An image sensor may include a first substrate having circuitry including wires and a silicon layer formed on and/or over the first substrate to selectively contact the wires. The image sensor may include photodiodes bonded to the first substrate while contacting the silicon layer and electrically connected to the wires.... Agent: Sherr & Vaughn, PLLC

20090166628 - Image sensor and method for manufacturing the same: An image sensor includes a first substrate having a circuitry including a wire formed therein and a photodiode formed above the circuitry. An unevenness is formed at the top of the photodiode. The unevenness may, for example, be formed by selectively etching the top of the photodiode and may act... Agent: Sherr & Vaughn, PLLC

20090166630 - Array substrate of liquid crystal display and method for fabricating the same: A thin film transistor (TFT) for a liquid crystal display device includes a gate electrode, a source electrode, a drain electrode, an active region including a first semiconductor layer and a second semiconductor layer interposed within the first semiconductor layer, and an ohmic contact layer formed on the active region,... Agent: Morgan Lewis & Bockius LLP

20090166629 - Reducing gate cd bias in cmos processing: A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over and/or in a semiconductor body, and depositing a polysilicon layer over the semiconductor body in both the NMOS... Agent: Texas Instruments Incorporated

20090166631 - Thin film transistor and display device including the same: One object of the present invention is reduction of off current of a thin film transistor. Another object of the present invention is improvement of electric characteristics of the thin film transistor. Further, another object of the present invention is improvement of image quality of the display device including the... Agent: Fish & Richardson P.C.

20090166633 - Array substrate and method for manufacturing the same: In an array substrate capable of improving the quality of displayed images and a method for manufacturing the array substrate, the array substrate includes a base substrate, a first conductive pattern including a gate line and a first light-blocking pattern, a semiconductor layer overlapping the light-blocking pattern, a second conductive... Agent: Cantor Colburn, LLP

20090166635 - Array substrate and method of manufacturing the same: An array substrate includes a base substrate, a gate line, a gate insulation layer, a data line, a thin-film transistor (“TFT”) and a pixel electrode. The gate line includes a gate covering line formed in a first direction on the base substrate and a gate main line protruded from the... Agent: Cantor Colburn, LLP

20090166632 - Gate driver-on-array structure and display panel: A gate driver-on-array structure integrated in a display panel includes a bar-like conductive layer, a semiconductor layer, first conductive patterns, second conductive patterns, a first electrode line and a second electrode line. The bar-like conductive layer has a plurality of regions. The semiconductor layer is disposed within the regions of... Agent: Jianq Chyun Intellectual Property Office

20090166634 - Pixel structure and manufacturing method thereof: A pixel structure including a gate, a gate dielectric layer, a patterned semiconductor layer having a channel area disposed above the gate, a patterned dielectric layer having an etching-stop layer disposed above the gate and a number of bumps, a patterned metal layer having a reflective pixel electrode, a source... Agent: Jianq Chyun Intellectual Property Office

20090166636 - Thin film transistor, method of fabricating the same, and organic light emitting diode display device having the tft: A thin film transistor (TFT), a method of fabricating the same, and display device having the TFT of which the TFT includes a metal catalyst layer disposed on a substrate, a semiconductor layer disposed on the metal catalyst layer, a gate insulating layer disposed on the entire surface of the... Agent: Stein Mcewen, LLP

20090166637 - Display apparatus with storage electrodes having concavo-convex features: A display apparatus includes a substrate; a first insulating layer formed on the substrate and having an upper surface including a concavo-convex area including one or more concave features and one or more convex features; a first storage electrode overlaying the upper surface and a side surface of the first... Agent: Haynes And Boone, LLPIPSection

20090166638 - Display device and electronic device provided with the same: An object is to suppress decrease in luminance and appearance of flicker of a still image and to control a threshold voltage of a transistor for driving an EL element even in a state where the EL element continues to emit light for a certain period. An n-channel transistor and... Agent: Nixon Peabody, LLP

20090166639 - Active field emission substrate and active field emission display: An active field emission substrate including a thin film transistor (TFT) substrate and a field emission device substrate is provided. The TFT substrate has a plurality of TFTs, and each TFT at least includes a source, a drain, and a gate. The field emission device substrate is disposed on the... Agent: Jianq Chyun Intellectual Property Office

20090166640 - Copper wire, method for fabricating the same, and thin film transistor substrate with the same: The present invention relates to a copper wire in a semiconductor device in which a barrier layer is formed for improving adhesion of a copper wire without any additional fabricating step; a method for fabricating the same, and a flat panel display device with the same. The copper wire includes... Agent: Mckenna Long & Aldridge LLP

20090166641 - Thin film transistor, method of fabricating a thin film transistor and flat panel display device having the same: A thin film transistor (TFT) includes a substrate, a transparent semiconductor layer on the substrate, the transparent semiconductor layer including zinc oxide and exhibiting a charge concentration of about 1×1014 atom/cm3 to about 1×1017 atom/cm3, a gate electrode on the substrate, a gate insulating layer between the gate electrode and... Agent: Lee & Morse, P.C.

20090166642 - Compound semiconductor epitaxial substrate and method for producing the same: wherein A=(a concentration of all p-type carriers in an active state due to an acceptor impurity contained in the epitaxial layer on the back side of the channel layer)×(a total thickness of the epitaxial layer on the back side), and B=(a concentration of all p-type carriers in an active state... Agent: Fitch, Even, Tabin & Flannery

20090166643 - Light emitting and image sensing device and apparatus: There is provided a light emitting and image sensing device for a scene. The device is formed in a semiconductor substrate and comprises a photosensor component for sensing an image of the scene. The photosensor component is responsive to incident light from the scene and provides an electrical signal representative... Agent: Paul Steven Schranz

20090166644 - Monolithic light emitting device and driving method therefor: A monolithic light-emitting device and driving method therefore includes a plurality of light-emitting diodes, array-arranged monolithically on a single substrate. Thie light-emitting diodes include a pn junction-containing semiconductor material and a phosphor-containing layer passing light emitted from the semiconductor material, absorbing part, or whole of the light for conversion into... Agent: Fitch, Even, Tabin & Flannery

20090166645 - Light emitting diode having a thermal conductive substrate and method of fabricating the same: Disclosed are a light emitting diode having a thermal conductive substrate and a method of fabricating the same. The light emitting diode includes a thermal conductive insulating substrate. A plurality of metal patterns are spaced apart from one another on the insulating substrate, and light emitting cells are located in... Agent: H.c. Park & Associates, PLC

20090166646 - Light-emitting element having pnpn-structure and light-emitting element array: A light-emitting element including a light-emitting thyristor and a Schottky barrier diode is provided. A Schottky barrier diode is formed by contacting a metal terminal to a gate layer of a three-terminal light-emitting thyristor consisting of a PNPN-structure. A self-scanning light-emitting element array may be driven at 3.0V by using... Agent: Ratnerprestia

20090166647 - Multi-wavelength led array package module and method for packaging the same: A method for packaging a multi-wavelength LED array package module includes: forming at least one concave groove on a drive IC structure; arranging a multi-wavelength LED array set in the at least one concave groove; solidifying a plurality of liquid conductive materials to form a plurality of conductive elements that... Agent: Rosenberg, Klein & Lee

20090166648 - Multi-wavelength light-emitting module with high density electrical connections: A multi-wavelength light-emitting module with high density electrical connections includes a drive IC structure and a multi-wavelength LED array structure. The drive IC structure has a drive IC unit formed on a top surface thereof. The multi-wavelength LED array structure is disposed on the top surface of the drive IC... Agent: Rosenberg, Klein & Lee

20090166650 - Light-emitting device of group iii nitride-based semiconductor and manufacturing method thereof: A light-emitting device of Group III nitride-based semiconductor comprises a substrate, a first Group III nitride layer and a second Group III nitride layer. The substrate comprises a first surface and a plurality of convex portions protruding from the first surface. Each convex portion is surrounded by a part of... Agent: Wpat, PC Intellectual Property Attorneys

20090166649 - Nitride semiconductor light emitting device and fabrication method thereof: The present invention relates to a nitride semiconductor light emitting device including: a substrate having a predetermined pattern formed on a surface thereof by an etch; a protruded portion disposed on a non-etched region of the substrate, and having a first buffer layer and a first nitride semiconductor layer stacked... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090166659 - High efficiency group iii nitride led with lenticular surface: A light emitting diode is disclosed having a vertical orientation with an ohmic contact on portions of a top surface of the diode and a mirror layer adjacent the light emitting region of the diode. The diode includes an opening in the mirror layer beneath the geometric projection of the... Agent: Summa, Additon & Ashe, P.A.

20090166653 - Incorporating reflective layers into led systems and/or components: A light emitting apparatus includes a support having circuitry disposed thereon, at least one light emitting diode (LED) chip mounted on the support and in electrical communication with the circuitry and a reflective layer on the support adjacent the at least one chip.... Agent: Fay Sharpe LLP

20090166657 - Light emitting device: A light emitting device includes a substrate provided with a conductor wiring, a light emitting element mounted on the substrate and a light reflecting resin member configured and arranged to reflect light emitted from the light emitting element. The light emitting device also includes at least one of an electrically... Agent: GlobalIPCounselors, LLP

20090166656 - Light emitting diode: A light emitting diode (LED) (100) includes a base (200), a chip body (300) and an encapsulation portion (400) sealing the chip body (300) in the base (200). The base (200) has a concave depression (220) defined therein. The depression (220) has a bottom wall (222) and a sidewall (224)... Agent: PCe Industry, Inc. Att. Steven Reiss

20090166658 - Light emitting diodes including two reflector layers: A light emitting diode includes a diode region having a gallium nitride based n-type layer, an active region and a gallium nitride based p-type layer. A first reflector layer is provided on the gallium nitride based p-type layer, and a second reflector layer is provided on the gallium nitride based... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090166651 - Light-emitting device with inorganic housing: The present invention relates to a light-emitting device comprising at least one light-emitting diode, which emits light, and a housing arranged to receive at least a portion of said light. The housing comprises a translucent inorganic material and is provided with at least one recess, which comprises positioning and orientating... Agent: Philips Intellectual Property & Standards

20090166655 - Light-emitting diode structure: An LED structure includes a first conductive body, a first insulating body on the first conductive body, a second conductive body on the first insulating body, and an LED. The first conductive body has a conducting portion upward projected from the insulating body and the second conductive body, so that... Agent: Wpat, PC Intellectual Property Attorneys

20090166654 - Light-emitting diode with increased light efficiency: A novel light-emitting diode structure is proposed wherein the epitaxial layers are cleaved to micro-units to suppress transverse propagation of light generated in active layer and improve light extraction efficiency. Further enhancement in light output will be obtained by introducing a light extraction layer with microstructures or directly structuring the... Agent: Dicke, Billig & Czaja

20090166652 - White led, backlight using the same, and liquid crystal display device: n

20090166664 - High power light emitting diode package and manufacturing method thereof: There is provided a high power LED package and a method of manufacturing the same. The method includes: forming at least one chip mounting part and at least one through hole in a metal plate; forming an insulating layer of a predetermined thickness on an entire outer surface of the... Agent: Mcdermott Will & Emery LLP

20090166662 - Iii-nitride semiconductor light emitting device: The present disclosure relates to a III-nitride semiconductor light emitting device comprising: a plurality of III-nitride semiconductor layers with an active layer generating light by recombination of holes and electrons; and a branch electrode provided with an arm extended from the p-side bonding pad toward the n-side electrode and two... Agent: Harness, Dickey, & Pierce, P.l.c

20090166660 - Lead frame for led: A lead frame for LED is disclosed to include a body defining an accommodation chamber, a first bracket frame that has a first bottom base mounted in the accommodation chamber and a first connection leg and a second connection respectively extended from the first bottom base to the outside of... Agent: Troxell Law Office PLLC One Skyline Place

20090166661 - Light-emitting diode packaging structure and module and assembling method thereof: A light-emitting diode packaging structure, a packaging module and the assembling method thereof are disclosed. The assembling method comprises the steps of: providing a light-emitting diode, wherein the light-emitting diode has two electrode leads; providing two metal plates, wherein each of the metal plates has at least a clamping portion;... Agent: Troxell Law Office PLLC

20090166663 - Nitride semiconductor light-emitting device and method of manufacturing the same: A nitride semiconductor light-emitting device includes, a support substrate 170; a nitride semiconductor layer 100 which includes a p-type nitride semiconductor layer 140 formed on the support substrate 170, an MQW active layer 130 formed on the p-type nitride semiconductor layer 140, and an n-type nitride semiconductor layer 120 formed... Agent: Rabin & Berdo, PC

20090166665 - Encapsulated optoelectronic device: The invention provides an optoelectronic device (e.g. a LED device) and method thereof. The device includes an optoelectronic component at least partially surrounded by an encapsulant comprising a silicone such as an aliphatic silicone and an adhesion promoter. The optoelectronic device exhibits improved properties such as adhesion and structural integrity,... Agent: Fay Sharpe LLP

20090166666 - Semiconductor device: An exemplary semiconductor device is provided. The semiconductor device includes a semiconductor stacked layer and a conductive structure. The conductive structure is located on the semiconductor stacked layer. The conductive structure includes a bottom portion and a top portion on opposite sides thereof. The bottom portion is in contact with... Agent: Bacon & Thomas, PLLC

20090166670 - Anthracene-based compound and organic light emitting device employing the same: where R is a hydrogen atom, a halogen atom, a cyano group, a hydroxyl group, a substituted or unsubstituted C1-C20 alkyl group, a substituted or unsubstituted C3-C20 cycloalkyl group, a substituted or unsubstituted C5-C30 heterocycloalkyl group, a substituted or unsubstituted C1-C20 alkoxy group, a substituted or unsubstituted C6-C30 aryl group,... Agent: Robert E. Bushnell & Law Firm

20090166668 - Nitride semiconductor light emitting device: There is provided a nitride semiconductor light emitting device having high internal quantum efficiency by accelerating recombination radiation while employing a multiple quantum well structure in which each of well layers has a relatively large thickness. The nitride semiconductor light emitting device is provided with a nitride semiconductor lamination portion... Agent: Rabin & Berdo, PC

20090166669 - Nitride semiconductor light emitting device and method of manufacturing the same: A nitride semiconductor light emitting device and a method of manufacturing the same, which can prevent crystal defects such as dislocation while ensuring uniform current spreading into an active layer. The nitride semiconductor light emitting device includes a first n-nitride semiconductor layer formed on a substrate, a first intermediate pattern... Agent: Mcdermott Will & Emery LLP

20090166667 - Substrate for light-emitting diode, and light-emitting diode: The substrate for light-emitting diodes of the present invention is a substrate for light-emitting diodes, obtained by stacking a single crystal layer enabling to form a light-emitting diode element thereon and a ceramic composite layer for light conversion comprising a solidified body having formed therein at least two or more... Agent: Ip Group Of Dla Piper US LLP

20090166671 - Esd protection circuit: To this end an ESD protection circuit of the present invention comprises: a detection unit for detecting a rising time of a signal flowing into first and second power lines; a pre-driver for buffering and outputting an output signal of the detection unit; and a power clamp configured with an... Agent: Morgan Lewis & Bockius LLP

20090166672 - Sawtooth electric field drift region structure for power semiconductor devices: This invention discloses a semiconductor power device formed in a semiconductor substrate. The semiconductor power device further includes rows of multiple horizontal columns of thin layers of alternate conductivity types in a drift region of the semiconductor substrate where each of the thin layers having a thickness to enable a... Agent: Bo-in Lin

20090166673 - Lateral bipolar transistor with compensated well regions: Conduction between source and drain or emitter and collector regions is an important characteristic in transistor operation, particularly for lateral bipolar transistors. Accordingly, techniques that can facilitate control over this characteristic can mitigate yield loss by promoting the production of transistors that have an increased likelihood of exhibiting desired operational... Agent: Texas Instruments Incorporated

20090166674 - Ultraviolet light receiving element: In an ultraviolet light receiving element using a group III nitride semiconductor, the ultraviolet light receiving element having an enhanced light receiving sensitivity is provided. An electron is excited from a valence band to a conduction band 61 by means of a depleted layer generated by irradiating a light having... Agent: Oliff & Berridge, PLC

20090166675 - Strain engineering in semiconductor components: This disclosure relates to strain engineering to improve the performance of semiconductor components that include a strained region of the semiconductor substrate. The disclosure involves the amorphization of the target region and the recrystallization of the atomic lattice whilst imposing a strain on the region. The region so formed will... Agent: Texas Instruments Incorporated

20090166677 - Semiconductor device and manufacturing method thereof: A semiconductor device includes: a semiconductor substrate; a diode having a cathode formed on a first surface side of the semiconductor substrate and an anode formed on a second surface side of the semiconductor substrate; and a transistor formed over the semiconductor substrate. The transistor includes a semiconductor layer laminate... Agent: Mcdermott Will & Emery LLP

20090166676 - Sige device with sige-embedded dummy pattern for alleviating micro-loading effect: A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate... Agent: North America Intellectual Property Corporation

20090166678 - Semiconductor device and method of manufacturing the same: A semiconductor device 1 includes a substrate 2 having on a main surface thereof a central area and a peripheral area which surrounds the central area and is exposed, a semiconductor layer 4 which is formed on the main surface of the substrate 2, is made of a material harder... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090166679 - Integrated circuit and manufacturing process facilitating selective configuration for electromagnetic compatibility: An integrated circuit (IC) having a selectively-designated electromagnetic compatibility (EMC) performance characteristic. The IC includes an IC die having an input or output (I/O) node. A first I/O cell of a first type associated with the I/O node provides a first EMC performance characteristic, and a second I/O cell of... Agent: Patterson, Thuente, Skaar & Christensen, P.A.

20090166680 - Unity beta ratio tri-gate transistor static radom access memory (sram): In general, in one aspect, a method includes forming N-diffusion and P-diffusion fins in a semiconductor substrate. A P-diffusion gate layer is formed over the semiconductor substrate and removed from the N-diffusion fins. A pass-gate N-diffusion gate layer is formed over the semiconductor substrate and removed from the P-diffusion fins... Agent: RyderIPLaw C/o Cpa Global

20090166681 - Mos transistor and semiconductor device: According to one embodiment of the present invention, a MOS transistor includes a semiconductor layer including a source region, a drain region, and a channel region disposed between the source region and the drain region. A gate structure is arranged above the channel regions. A source wiring structure is arranged... Agent: Slater & Matsil LLP

20090166683 - Flexible layout for integrated mask-programmable logic devices and manufacturing process thereof: Integrated mask-programmable device, having a plurality of metal levels including a top metal level, a bottom metal level and a first intermediate metal level formed between the top and bottom metal levels, and a plurality of via levels arranged between the bottom and the first intermediate metal levels and between... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20090166682 - Methods and apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography: The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a damascene process. An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for... Agent: Dugan & Dugan, PC

20090166684 - Photogate cmos pixel for 3d cameras having reduced intra-pixel cross talk: A CMOS photodetector pixel formed of a substrate, an epitaxial layer above the substrate including a first region having the same polarity but a lower impurity concentration as that of the substrate, and a gate arrangement including a first gate that forms a charge accumulation region in the epitaxial layer... Agent: Dr. Allan C. Entis, Intellectual Property Ltd.

20090166686 - Edge-contacted vertical carbon nanotube transistor: A vertical device geometry for a carbon-nanotube-based field effect transistor has one or multiple carbon nanotubes formed in a trench.... Agent: Aka Chan LLP

20090166685 - Semiconductor device and method of fabricating the same: A semiconductor device according to one embodiment includes: a semiconductor substrate; a first impurity diffusion suppression layer formed on the semiconductor substrate for suppressing diffusion of a channel impurity; an impurity channel layer formed on the first impurity diffusion suppression layer and containing the channel impurity; a second impurity diffusion... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090166687 - Image sensor and method for manufacturing the same: An image sensor and a method for manufacturing the same may include a gate on a semiconductor substrate, a photodiode on the semiconductor substrate at a first side of the gate, a floating diffusion region on the semiconductor substrate at a second side of the gate, in which the second... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090166688 - Image sensor and method for manufacturing the same: An image sensor includes an interlayer dielectric including metal lines disposed on a semiconductor substrate; first conductive regions formed on a crystalline semiconductor substrate which is bonded to the semiconductor substrate, and connected with the metal lines; second conductive regions formed between the respective first conductive regions; first conductive-type high-density... Agent: Sherr & Vaughn, PLLC

20090166696 - Cmos image device with local impurity region: According to a CMOS image device and a method of manufacturing same, dark current is decreased by a local impurity region. The image device includes a semiconductor substrate, and a transfer gate formed on a predetermined portion of the semiconductor substrate and electrically insulated from the semiconductor substrate. A photodiode... Agent: Myers Bigel Sibley & Sajovec

20090166692 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor may include a dielectric layer formed on a semiconductor substrate, first and second passivation layers sequentially formed on the whole surface of the dielectric layer, a planarization layer, a color filter layer, and an overcoating layer and a microlens sequentially formed on the second passivation layer.... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090166693 - Image sensor and manufacturing method thereof: An image sensor and manufacturing method thereof are provided. The image sensor can include a gate on a semiconductor substrate, first and second p-type doping areas below the gate, a third p-type doping area adjacent to the first p-type doping area, and a fourth p-type doping area adjacent to the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090166689 - Image sensor and method for manufacturing the same: An image sensor includes a first substrate, readout circuitry, an electrical junction region, a metal interconnection and an image sensing device. The readout circuitry is formed on and/or over the first substrate and the electrical junction region is formed in the first substrate and electrically connected to the readout circuitry.... Agent: Sherr & Vaughn, PLLC

20090166694 - Image sensor and method for manufacturing the same: An image sensor and a method for manufacturing the same are provided. In the image sensor, a semiconductor substrate has a pixel region and a peripheral region defined by a first device isolation layer. First and second photodiode patterns are formed on the pixel region and are connected to lower... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090166695 - Image sensor and method for manufacturing the sensor: A method for manufacturing an image sensor having a peripheral circuit unit and a pixel unit includes forming a device isolation layer that defines an active area in the pixel area, on a semiconductor substrate, forming a gate pattern on the active area of the semiconductor substrate, forming a photodiode... Agent: Sherr & Vaughn, PLLC

20090166690 - Image sensor and method of manufacturing the same: An image sensor and manufacturing method thereof are provided. The image sensor can include a gate, a channel region, a first p-type doped region, a second p-type doped region, an n-type doped region, and a floating diffusion region. The gate can be disposed on a semiconductor substrate, and the channel... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090166691 - Image sensor and method of manufacturing the same: Image sensors and manufacturing methods thereof are provided. An image sensor according to an embodiment comprises a second conductive type diffusion layer formed on a first conductive type substrate; a device isolating layer formed in the second conductive type diffusion layer to isolate the second conductive type diffusion layer according... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090166698 - Capacitor and method of manufacturing the same: A capacitor with a mixed structure of a Metal Oxide Semiconductor (MOS) capacitor and a Poly-silicon Insulator Poly-silicon (PIP) capacitor includes a substrate and a diffusion junction region formed over the substrate. A high concentration diffusion junction region may be formed in a portion of the diffusion junction region. An... Agent: Sherr & Vaughn, PLLC

20090166699 - Semiconductor constructions: In some embodiments, an opening is formed through a first material, and sidewall topography of the opening is utilized to form a pair of separate anistropically etched spacers. The spacers are utilized to pattern lines in material underlying the spacers. Some embodiments include constructions having one or more openings which... Agent: Wells St. John P.s.

20090166697 - Semiconductor device and method of fabricating the same: Disclosed are a semiconductor device and method of fabricating the same. The semiconductor device includes a floating gate on a semiconductor layer; a first contact on the floating gate; a MIM capacitor including a lower electrode, an insulating layer, and an upper electrode on the first contact; a second contact... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090166700 - Single transistor memory cell with reduced recombination rates: A semiconductor fabrication method includes forming a semiconductor structure including source/drain regions disposed on either side of a channel body wherein the source/drain regions include a first semiconductor material and wherein the channel body includes a migration barrier of a second semiconductor material. A gate dielectric overlies the semiconductor structure... Agent: Freescale Semiconductor, Inc. Law Department

20090166701 - One transistor/one capacitor dynamic random access memory (1t/1c dram) cell: In general, in one aspect, a method includes forming a semiconductor fin. A first insulating layer is formed adjacent to the semiconductor fin. A second insulating layer is formed over the first insulating layer and the semiconductor fin. A first trench is formed in the second insulating layer and the... Agent: RyderIPLaw C/o Cpa Global

20090166703 - Memory device with a length-controllable channel: A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending... Agent: Quintero Law Office, PC

20090166702 - Trench-type semiconductor device structure: A trench-type semiconductor device structure is disclosed. The structure includes a semiconductor substrate, a gate dielectric layer and a substrate channel structure. The semiconductor substrate includes a trench having an upper portion and a lower portion. The upper portion includes a conductive layer formed therein. The lower portion includes a... Agent: Ingrassia Fisher & Lorenz, P.C.

20090166707 - Flash memory device and method for manufacturing the device: A flash memory device and a method for manufacturing the device includes forming a device isolation layer in a semiconductor substrate defining active regions, forming a control gate layer over the entire upper surface of the semiconductor substrate, forming a gate mask over the control gate layer, the gate mask... Agent: Sherr & Vaughn, PLLC

20090166704 - Non-volatile storage with substrate cut-out and process of fabricating: Shallow trench isolation regions are positioned between NAND strings (or other types of non-volatile storage). These isolation regions include sections that form concave cut-out shapes in the substrate for the NAND string (or other types of non-volatile storage). The floating gates (or other charge storage devices) of the NAND strings... Agent: Vierra Magen/sandisk Corporation

20090166705 - Nonvolatile semiconductor memory device and method of manufacturing thereof: In a nonvolatile semiconductor memory device, second conductivity type source and drain regions are formed separately from each other in a first conductivity type semiconductor region on a surface thereof. A second conductivity type semiconductor region is formed in the first conductivity type semiconductor region arranged between the source and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090166706 - Semiconductor device and method of manufacturing the same: A semiconductor device according to an embodiment of the present invention has a bit line and a word line. The device includes a substrate which is provided with first trenches extending in a bit-line direction and has side surfaces forming sidewalls of the first trenches, the substrate being provided with... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090166708 - Nonvolatile semiconductor memory with erase gate and its manufacturing method: A nonvolatile semiconductor memory device includes a semiconductor substrate, a select gate formed above the semiconductor substrate, a floating gate formed above the semiconductor substrate and an erase gate positioned lower than an upper surface of the floating gate, and opposite an edge of a lower surface of the floating... Agent: Mcginn Intellectual Property Law Group, PLLC

20090166709 - Flash memory device and method of fabricating the same: A flash memory device and method of fabricating thereof. In accordance with the method of the invention, a tunnel dielectric layer and an amorphous first conductive layer are formed over a semiconductor substrate. An annealing process to change the amorphous first conductive layer to a crystallized first conductive layer is... Agent: Marshall, Gerstein & Borun LLP

20090166712 - Nanocrystal non-volatile memory cell and method therefor: A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and... Agent: Freescale Semiconductor, Inc. Law Department

20090166710 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory device includes: a semiconductor substrate; and a memory cell. The memory cell includes: a source region and a drain region formed at a distance from each other on the semiconductor substrate; a tunnel insulating film formed on a channel region of the semiconductor substrate, the channel... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090166711 - Tunnel insulating layer of flash memory device and method of forming the same: The present invention discloses a tunnel insulating layer in a flash memory device and a method of forming the same, the method according to the present invention comprises the steps of forming a first oxide layer on a semiconductor substrate through a first oxidation process; forming a nitride layer on... Agent: Marshall, Gerstein & Borun LLP

20090166714 - Non-volatile memory device: A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the... Agent: Lee & Morse, P.C.

20090166717 - Nonvolatile memory device and method for manufacturing the same: Embodiments relate to a nonvolatile memory device and a method for manufacturing the same. According to embodiments, a nonvolatile memory device may include a tunnel ONO film having an oxide film, a nitride film, and an oxide film stacked on and/or over a semiconductor substrate. It may also include a... Agent: Sherr & Vaughn, PLLC

20090166715 - Scalable interpoly dielectric stacks with improved immunity to program saturation: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20090166716 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a first oxide-nitride-oxide (ONO) layer in which a block oxide, a tunnel oxide and a trap nitride are stacked sequentially on one side of a semiconductor substrate; a second oxide-nitride-oxide (ONO) layer in which the block oxide, the tunnel oxide and the trap nitride are stacked... Agent: Sherr & Vaughn, PLLC

20090166713 - Semiconductor device and method of fabricating the same: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device comprises a plurality of device isolation layers disposed in a semiconductor substrate, the device isolation layers extending in a word line direction and spaced apart from each other; a plurality of floating gate devices extending... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090166719 - Ldmos semiconductor device mask: Embodiments relate to an LDMOS semiconductor device mask that may reduce current leakage under a gate-off condition. According to embodiments, an LDMOS semiconductor device mask may include a moat mask to define a moat region, an NDT mask to define an N drift region, a PDT mask to define a... Agent: Sherr & Vaughn, PLLC

20090166718 - Method of predicting drain current in mos transistor: Embodiments relate to a method of predicting a drain current that may accurately predict drain current in a linear region, a saturation region, and a breakdown region by modeling a drain current in the breakdown region, in which inconsistency occurs when a drain current depending on a drain voltage is... Agent: Sherr & Vaughn, PLLC

20090166722 - High voltage structures and methods for vertical power devices with improved manufacturability: This invention discloses a semiconductor power device disposed on a semiconductor substrate supporting an epitaxial layer as a drift region composed of an epitaxial layer. The semiconductor power device further includes a super-junction structure includes a plurality of doped sidewall columns disposed in a multiple of epitaxial layers. The epitaxial... Agent: Bo-in Lin

20090166721 - Quasi-vertical gated npn-pnp esd protection device: Fashioning a quasi-vertical gated NPN-PNP (QVGNP) electrostatic discharge (ESD) protection device is disclosed. The QVGNP ESD protection device has a well having one conductivity type formed adjacent to a deep well having another conductivity type. The device has a desired holding voltage and a substantially homogenous current flow, and is... Agent: Texas Instruments Incorporated

20090166724 - Semiconductor device and method for manufacturing the same: Disclosed is a vertically arranged semiconductor device. The semiconductor device can include a semiconductor substrate comprising a first conductive type buried layer, a first conductive type drift region formed on the first conductive type buried layer, and a second conductive type well formed on the first conductive type drift region.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090166723 - Semiconductor device with vertical channel transistor and low sheet resistance and method for fabricating the same: A memory device includes a substrate, a plurality of wordlines arranged over the substrate, a plurality of pillars formed over the substrate between the wordlines, a gate electrode surrounding external walls of the pillars to be connected to the wordlines, and an insulation layer for insulating one sidewall of each... Agent: Townsend And Townsend And Crew, LLP

20090166720 - Semiconductor device, method for operating a semiconductor device and method for manufacturing a semiconductor device: A semiconductor device includes a semiconductor substrate having at least a pn-junction arranged in the semiconductor substrate. At least a field electrode is arranged at least next to a portion of the pn-junction, wherein the field electrode is insulated from the semiconductor substrate. A switching device is electrically connected to... Agent: Dickstein Shapiro LLP

20090166726 - Method of manufacturing semiconductor device and semiconductor device: There are provided a method of manufacturing a semiconductor device which is capable of narrowing only the width of a Fin channel while maintaining the widths of source and drain regions, and a semiconductor device. The method of manufacturing a semiconductor device is a method of manufacturing a Fin type... Agent: Young & Thompson

20090166727 - Power semiconductor having a lightly doped drift and buffer layer: A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension... Agent: Dicke, Billig & Czaja

20090166725 - Vertical transistor and method for forming the same: A vertical transistor includes a semiconductor substrate provided with a pillar type active pattern over the surface thereof. A first tensile layer is formed over the semiconductor substrate and around the lower end portion of the pillar type active pattern, and a second tensile layer is formed over the upper... Agent: Ladas & Parry LLP

20090166729 - Power semiconductor having a lightly doped drift and buffer layer: A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension... Agent: Dicke, Billig & Czaja

20090166733 - Semiconductor device and manufacturing method thereof: A method of manufacturing a semiconductor device including forming a first conductive-type buried layer in a substrate; forming a first conductive-type drift area on the first conductive-type buried layer; forming a gate insulating layer and gate electrodes by selectively removing the first conductive-type drift area; forming a first oxide layer... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090166732 - Semiconductor device and method of manufacturing the same: A semiconductor device according to an embodiment of the present invention has a transistor section which includes a trench gate type transistor, and a gate line section which includes a part provided between transistor sections. The device includes a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090166730 - Sic semiconductor device having bottom layer and method for manufacturing the same: A SiC semiconductor device includes: a substrate; a drift layer on the substrate; a trench on the drift layer; a base region in the drift layer sandwiching the trench; a channel between the base region and the trench; a source region in the base region sandwiching the trench via the... Agent: Posz Law Group, PLC

20090166728 - Structure and method for forming shielded gate trench fet with multiple channels: A field effect transistor (FET) includes a pair of trenches extending into a semiconductor region. Each trench includes a first shield electrode in a lower portion of the trench and a gate electrode in an upper portion of the trench over but insulated from the shield electrode. First and second... Agent: Townsend And Townsend And Crew, LLP

20090166731 - Vertical-type field-effect transistor and manufacturing method thereof: A vertical-type FET includes: a semiconductor layer having a plurality of trenches; a gate electrode partially embedded in the trenches; and a base region and a source region that are formed in the semiconductor layer between adjacent trenches. The gate electrode includes: a plurality of first gate structures respectively formed... Agent: Young & Thompson

20090166734 - Trench gate mosfet and method for fabricating the same: A trench gate MOSFET and a fabrication method thereof includes forming a first epitaxial layer over a semiconductor substrate, and then forming a second epitaxial layer formed over the first epitaxial layer, and then forming a body region over the second conductive type second epitaxial layer, and then forming a... Agent: Sherr & Vaughn, PLLC

20090166735 - Semiconductor device and method of manufacturing the same: The present invention relates to a method of manufacturing a semiconductor device having a shared contact for connection between a source/drain region and a gate electrode. After formation of a gate electrode via a gate insulating film on a semiconductor substrate, a top surface of the substrate is covered with... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090166736 - Lateral double difused metal oxide semiconductor transistor and method for manufacturing the same: A lateral double diffused metal oxide semiconductor a lateral double diffused metal oxide semiconductor (LDMOS) transistor which may include a first conductive type semiconductor substrate and a shallow trench isolation film defining an active region in the substrate. A second conductive type body region may be disposed over a portion... Agent: Sherr & Vaughn, PLLC

20090166737 - Method for manufacturing a transistor: A method for manufacturing a transistor is disclosed, which is capable of improving matching characteristics of regions within a transistor or among transistors on a wafer, from wafer-to-wafer, or from lot-to-lot. The method includes forming a photoresist pattern on a semiconductor substrate including an isolation layer, forming a drift region... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090166738 - Ram cell including a transistor with floating body for information storage having asymmetric drain/source extensions: In a floating body storage transistor, the dopant concentration at the emitter side of the parasitic bipolar transistor may be significantly increased on the basis of a tilted implantation process, while maintaining a desired graded dopant profile at the collector side. Consequently, voltages for reading and writing of the FB... Agent: Williams, Morgan & Amerson

20090166739 - Semiconductor device: In order to obtain substantially the same operating speed of a p-type MOS transistor and an n-type MOS transistor forming a CMOS circuit, the n-type MOS transistor has a three-dimensional structure having a channel region on both the (100) plane and the (110) plane and the p-type MOS transistor has... Agent: Foley And Lardner LLP Suite 500

20090166740 - Reduced mask configuration for power mosfets with electrostatic discharge (esd) circuit protection: A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body... Agent: Bo-in Lin

20090166743 - Independent gate electrodes to increase read stability in multi-gate transistors: Independent gate electrodes for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) gate stacks coupled with the semiconductor fin, the one or more PD gate stacks including a PD gate electrode, and one or more multi-gate pass... Agent: Cool Patent, P.C. C/o Cpa Global

20090166742 - Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin: Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region,... Agent: Cool Patent, P.C. C/o Cpa Global

20090166741 - Reducing external resistance of a multi-gate device using spacer processing techniques: Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate... Agent: Cool Patent, P.C. C/o Cpa Global

20090166744 - Semiconductor device with deep trench structure: Disclosed herein is a semiconductor device with a deep trench structure for effectively isolating heavily doped wells of neighboring elements from each other at a high operating voltage. The semiconductor device with a deep trench structure includes a semiconductor substrate in which a first conductivity type well and a second... Agent: Morgan Lewis & Bockius LLP

20090166746 - Semiconductor device: A semiconductor device has a first and a second active regions of a first conductivity type disposed on a semiconductor substrate, a third and a fourth active regions of a second conductivity type disposed on the semiconductor substrate, the second and the fourth active regions having sizes larger than those... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090166745 - Semiconductor device and photomask: Shared contact holes SC1 and SC2 reach both gate electrode layers GE1 and GE2 and a drain region PIR. In a planar view, a sidewall E2 of gate electrode layers GE1 and GE2 is shifted toward a side of a sidewall E4 from a virtual extended line E1a of the... Agent: Mcdermott Will & Emery LLP

20090166747 - Formation of metal gate electrode using rare earth alloy incorporated into mid gap metal: Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. A rare earth-rare earth alloy incorporated metal nitride layer is formed above a gate dielectric. This process provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting... Agent: Texas Instruments Incorporated

20090166751 - Image sensor and method for manufacturing the same: A method for manufacturing a CMOS transistor includes preparing a silicon substrate provided with a first buried layer, a second buried layer and a body, vertically forming device-isolation films inside the body, forming a first-type well inside the body arranged on the first buried layer, and vertically forming a first... Agent: Sherr & Vaughn, PLLC

20090166750 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a semiconductor wafer, a source region and a drain region formed within the semiconductor wafer, a gate electrode formed on the semiconductor wafer between the source region and the drain region, an interlayer film formed on the semiconductor wafer and the gate electrode, and a dummy... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090166749 - Semiconductor device and method for manufacturing the same: A semiconductor device includes n- and p-type semiconductor regions separately formed on a substrate, an interlayer insulator formed on the substrate and having first and second trenches formed to reach the n- and p-type regions. There are further included first and second gate insulators formed inside of the first and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090166748 - Semiconductor device and method of manufacturing the same: A semiconductor device including a silicon substrate and a field effect transistor including a gate insulating film on the silicon substrate, a gate electrode on the gate insulating film, and source/drain regions formed in the substrate on opposite sides of the gate electrode, wherein the gate electrode includes a silicide... Agent: Mcginn Intellectual Property Law Group, PLLC

20090166752 - Semiconductor devices and methods of manufacture thereof: A first gate dielectric of a first transistor is disposed over a workpiece in a first region, and a second gate dielectric of a second transistor is disposed over the workpiece in a second region. The second gate dielectric comprises a different material than the first gate dielectric. A first... Agent: Slater & Matsil LLP

20090166753 - Semiconductor device and method of manufacturing such a device: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (1) comprising a bipolar transistor with in that order a collector region (2), a base region (3), and an emitter region (4), wherein the semiconductor body comprises a projecting mesa (5) comprising at least... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090166754 - Circuit device and method of forming a circuit device having a reduced peak current density: In a particular embodiment, a method of forming a field effect transistor (FET) device having a reduced peak current density is disclosed. The method includes forming a field effect transistor (FET) device on a substrate. The FET device includes a drain terminal, a source terminal, a gate terminal, and a... Agent: Westman Champlin & Kelly, P.A.

20090166755 - Growth of unfaceted sige along a semiconductor device width: Semiconductor devices and fabrication methods are provided in which disposable gates are formed over isolation regions. Sidewall structures, including disposable sidewall structures, are formed on sidewalls of the disposable gates. An epitaxially grown silicon germanium is formed in recesses defined by the sidewalls. The process provides a compressive strained channel... Agent: Texas Instruments Incorporated

20090166756 - Mos transistor and semiconductor integrated circuit: A MOS transistor includes plural transistor cell blocks arranged adjacently in parallel to one another, wherein the plural transistor cell blocks are configured to have plural transistor cells, plural boundaries that are parallel to the plural transistor cells, and plural back gates arranged at the plural boundaries, each of the... Agent: Ipusa, P.l.l.c

20090166758 - Integrated circuit structure with electrical strap: A method of forming an IC is presented. The method includes providing a substrate having a plurality of transistors formed thereon. The transistors have gate stack, source and drain regions. An electrical strap is formed and in contact with at least a portion of at least one sidewall of the... Agent: HorizonIPPte Ltd

20090166757 - Stress engineering for sram stability: A design structure embodied in a machine readable medium is provided for use in the design, manufacturing, and/or testing of Ics that include at least one SRAM cell. In particular, the present invention provides a design structure of an IC embodied in a machine readable medium, the IC including at... Agent: Scully, Scott, Murphy & Presser, P.C.

20090166760 - Semiconductor device and method of manufacturing the same: Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a gate electrode in a first trench in a semiconductor substrate, a ground area in a second trench facing the gate electrode, and source and drain areas in third and fourth trenches at ends of the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090166759 - Transistor having raised source/drain self-aligned contacts and method of forming same: A transistor structure and a method of forming same. The transistor structure includes: a semiconductor substrate having a gate-side surface; a gate disposed on the gate-side surface, the gate extending above the gate-side surface by a first height; a semiconductor extension disposed on the gate-side surface and extending above the... Agent: Intel Corporation C/o Cpa Global

20090166761 - Field effect transistor structure with an insulating layer at the junction: A method of making a FET includes forming a gate structure (18), then etching cavities on either side. A SiGe layer (22) is then deposited on the substrate (10) in the cavities, followed by an Si layer (24). A selective etch is then carried out to etch away the SiGe... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090166762 - Monitoring pattern of semiconductor device and method for fabricating the same: A monitoring pattern of a semiconductor device and a method for fabricating the same, capable of increasing an area utilization rate. The monitoring pattern of a semiconductor device includes a gate electrode formed on a semiconductor substrate provided with an isolation film, a spacer formed on one sidewall of the... Agent: Sherr & Vaughn, PLLC

20090166763 - Semiconductor device and method for fabricating the same: Embodiments relate to a semiconductor device having a minimized on-resistance. According to embodiments, a semiconductor device may include at least one of the following: a first conductive type well formed on and/or over a semiconductor substrate, a second conductive type body region formed within the first conductive type well a... Agent: Sherr & Vaughn, PLLC

20090166764 - Transistor and fabricating method thereof: A transistor and fabricating method thereof includes sequentially forming a gate oxide layer and a poly gate over an active area of a semiconductor substrate, forming a drift region in the active area adjacent to the poly gate, and then forming a source/drain by simultaneously implanting impurity ions of various... Agent: Sherr & Vaughn, PLLC

20090166765 - Mos transistor and method for manufacturing the transistor: A MOS transistor and a method for manufacturing the transistor that may include forming a gate pattern on and/or over an active area of a semiconductor substrate defined as the active area and a field area, and silicide blocking films at each side of the gate pattern and partially over... Agent: Sherr & Vaughn, PLLC

20090166766 - Metal oxide semiconductor transistor with y shape metal gate: A metal oxide semiconductor (MOS) transistor with a Y structure metal gate is provided. The MOS transistor includes a substrate, a Y structure metal gate positioned on the substrate, two doping regions disposed in the substrate on two sides of the Y structure metal structure, a spacer, an insulating layer... Agent: North America Intellectual Property Corporation

20090166767 - Semiconductor device and method for manufacturing the same: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090166768 - Semiconductor device with metal silicides having different phases: A fully silicided gate with a selectable work function includes a gate dielectric over the substrate, a first metal silicide layer over the gate dielectric, and a second metal silicide layer wherein the first metal silicide has a different phase then the second metal silicide layer. The metal silicide layers... Agent: Duane Morris LLP (tsmc)IPDepartment

20090166770 - Method of fabricating gate electrode for gate of mosfet and structure thereof: A method of fabricating a gate electrode for a gate of a metal oxide semiconductor field effect transistor (MOSFET), where the transistor has a structure incorporating a gate disposed on a substrate. The substrate comprises a source-drain region. The gate includes a gate electrode disposed on a gate dielectric and... Agent: Hoffman Warnick LLC

20090166769 - Methods for fabricating pmos metal gate structures: Methods of forming a microelectronic structure are described. Those methods may include forming a gate dielectric layer on a substrate, forming a metal gate layer on the gate dielectric layer, and then forming a polysilicon layer on the metal gate layer in situ, wherein the metal gate layer is not... Agent: Intel Corporation C/o Cpa Global

20090166771 - Device comprising a sensor module: A device (1) comprising a sensor module (2) with a package (3) is produced at reduced costs by providing the package (3) with two or more substrates (4,5) each with a functional layer (14,15), at least one sensor (24,25) such as a magnetometer and/or an accelerometer being located in at... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090166772 - Micro-electro-mechanical systems (mems) device and process for fabricating the same: A micro-electro-mechanical systems (MEMS) device includes a back-plate substrate, having an intended region formed with a plurality of perforating holes. A first structural dielectric layer, disposed on the back-plate substrate, wherein the dielectric layer having an opening above the intended region. An etching stop layer, disposed over the first structural... Agent: Jianq Chyun Intellectual Property Office

20090166773 - Magnetic memory cell and magnetic random access memory: Provided is a reliable nonvolatile memory with a lower power consumption. A ferromagnetic interconnection which is magnetized antiparallel or parallel to a magnetization direction of a ferromagnetic pinned layer in a giant magnetoresistive device or a tunnel magnetoresistive device constituting the magnetic memory cell, is connected to a ferromagnetic free... Agent: Reed Smith LLP

20090166776 - Image sensor and fabricating method thereof: An image sensor includes an insulating interlayer including a metal line on a semiconductor substrate, a photodiode pattern provided on the insulating interlayer to be connected to the metal line, the photodiode pattern separated per unit pixel by a gap area, a device isolation insulating layer provided on the insulating... Agent: Sherr & Vaughn, PLLC

20090166777 - Image sensor and method for manufacturing the same: Embodiments relate to an image sensor and a method of manufacturing an image sensor. According to embodiments, an image sensor may include a gate over a semiconductor substrate, a first impurity region over the semiconductor substrate, a second impurity region over the semiconductor substrate, the second impurity region being shallower... Agent: Sherr & Vaughn, PLLC

20090166778 - Image sensor and method for manufacturing the same: Embodiments relate to an image sensor and a method for manufacturing the same. According to embodiments, a semiconductor substrate may include a pixel part and a peripheral part. A photo diode pattern may be formed over the pixel part having a height that is greater than a height of a... Agent: Sherr & Vaughn, PLLC

20090166779 - Image sensor and method for manufacturing the same: Embodiments relate to an image sensor and a method of manufacturing an image sensor. According to embodiments, an image sensor may include a first substrate, a photodiode, and an ion implantation isolation layer. According to embodiments, circuitry including a metal interconnection may be disposed over the first substrate. A photodiode... Agent: Sherr & Vaughn, PLLC

20090166775 - Method for manufacturing image sensor: Embodiments relate to an image sensor and a method for manufacturing an image sensor. According to embodiments, a method may include forming a semiconductor substrate including a pixel part and a peripheral part, forming an interlayer dielectric film including a metal wire on and/or over the semiconductor substrate, forming photo... Agent: Sherr & Vaughn, PLLC

20090166780 - Process for producing semiconductor substrate, semiconductor substrate for solar application and etching solution: Provided is: a process for producing safely at low cost a semiconductor substrate excellent in photoelectric transduction efficiency, in which a fine uneven structure suitable for a solar cell can be formed uniformly with desired size on the surface of the semiconductor substrate; a semiconductor substrate for solar application in... Agent: Marger Johnson & Mccollom, P.C.

20090166774 - Wire bonding method and semiconductor device: First and second semiconductor chips are arranged side by side on a package base. A plurality of electrode pads with exposed Al films are formed at regular intervals on the first and second semiconductor chips. An Au bump is formed on each electrode pad of the second semiconductor chip. Each... Agent: Sughrue Mion, PLLC

20090166781 - Emi shielding for imager devices: A module that provides EMI shielding for imager devices is disclosed which includes a die comprising an imager device and a plurality of contact pads, a stack positioned above the imager device, the stack comprising at least one lens, a conductive layer positioned above the stack, the conductive layer comprising... Agent: Perkins Coie LLP Patent-sea

20090166784 - Semiconductor device and method for fabricating semiconductor device: Gold bumps are located over electrode pads of a solid imaging device and an adhesive is formed over the gold bumps. A transparent plate is supported by the gold bumps and is made to adhere over the solid imaging device by the adhesive. The gold bumps and an electrode and... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090166783 - Solid-state imaging device, method of manufacturing the same, and camera and electronic apparatus using the same: A method of manufacturing a solid-state imaging device is provided. The method includes: forming an insulating layer extending over an effective pixel region where a plurality of pixels each having a photoelectric conversion element is arranged and a peripheral area adjacent to the effective pixel region; forming an opening in... Agent: Sonnenschein Nath & Rosenthal LLP

20090166782 - Wafer processing: Methods, devices, and systems for wafer processing are described herein. One method of wafer processing includes modifying a peripheral edge of a wafer to create a number of edge surfaces substantially perpendicular to a number of dicing paths and dicing the wafer along the number of dicing paths. In one... Agent: Brooks, Cameron & Huebsch , PLLC

20090166785 - Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device: A semiconductor package has a semiconductor die with an optically active region which converts light to an electrical signal. An expansion region is formed around the semiconductor die. A through hole via (THV) is formed in the expansion region. Conductive material is deposited in the THV. A passivation layer is... Agent: Quarles & Brady LLP

20090166786 - Image sensor and method for manufacturing the same: An image sensor includes a metal interconnection and readout circuitry over a first substrate, an image sensing device, and an ion implantation isolation layer. The image sensing device is over the metal interconnection, and an ion implantation isolation layer is in the image sensing device. The image sensing device includes... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090166787 - Image sensor and method for manufacturing the same: An image sensor includes a circuitry, a substrate, an electrical junction region, a high concentration first conduction type region, and a photodiode. The circuitry includes a transistor and is formed on and/or over the substrate. The electrical junction region is formed in one side of the transistor. The high concentration... Agent: Sherr & Vaughn, PLLC

20090166788 - Image sensor and method for manufacturing the same: Provided is an image sensor and a method for manufacturing the same. In the image sensor, a semiconductor substrate has a readout circuitry formed thereon. An interlayer insulating layer including a lower metal line is on the semiconductor substrate, the lower metal line being electrically connected with the readout circuitry.... Agent: Sherr & Vaughn, PLLC

20090166789 - Image sensor and method for manufacturing the same: An image sensor includes a first substrate and a photodiode. A circuitry including a metal interconnection is formed over the first substrate. The photodiode is formed over a first substrate, and contacts the metal interconnection. The circuitry of the first substrate includes a transistor over the first substrate, an electrical... Agent: Sherr & Vaughn, PLLC

20090166790 - Image sensor and method for manufacturing the same: An image sensor may comprise circuitry, a first lower electrode, a photodiode, an upper electrode, a second lower electrode, and an upper interconnection. The circuitry may comprise a first lower interconnection and a second lower interconnection over a dielectric of a substrate. The first lower electrode, the photodiode, and the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090166791 - Method for manufacturing image sensor: Embodiments relate to an image sensor and a method for manufacturing an image sensor. According to embodiments, an interlayer insulating layer including a metal line may be formed on and/or over a semiconductor substrate. A lower electrode layer connected with the metal line may be formed on and/or over the... Agent: Sherr & Vaughn, PLLC

20090166792 - Image sensor and method for manufacturing the same: Embodiments relate to an image sensor and a method of forming an image sensor. According to embodiments, an image sensor may include a first substrate and a photodiode. A circuitry including a metal interconnection may be formed on and/or over the first substrate. The photodiode may be formed over a... Agent: Sherr & Vaughn, PLLC

20090166793 - Image sensor and method for manufacturing the same: Embodiments relate to an image sensor. According to embodiments, an image sensor may include a metal interconnection, readout circuitry, a first substrate, an image sensing device, and a second conduction type interfacial layer. The metal interconnection and the readout circuitry may be formed on and/or over the first substrate. The... Agent: Sherr & Vaughn, PLLC

20090166794 - Temperature monitoring in a semiconductor device by thermocouples distributed in the contact structure: By forming thermocouples in a contact structure of a semiconductor device, respective extension lines of the thermocouples may be routed to any desired location within the die, without consuming valuable semiconductor area in the device layer. Thus, an appropriate network of measurement points of interest may be provided, while at... Agent: Williams, Morgan & Amerson

20090166795 - Schottky diode of semiconductor device and method for manufacturing the same: A method includes forming a first conductive type buried layer on a semiconductor substrate, forming a second conductive type epi-layer on the semiconductor substrate using an epitaxial growth method such that the epi-layer surrounds the buried layer, forming a first conductive type plug from the surface of the semiconductor substrate... Agent: Sherr & Vaughn, PLLC

20090166796 - Method for manufacturing integrated circuit and semiconductor structure of integrated circuit: A method for manufacturing an integrated circuit includes: performing ion implantation on a wafer to make a chip in the wafer have an original doping concentration; dividing the chip into a plurality of regions; and controlling at least one region of plurality of the regions to not have further ion... Agent: North America Intellectual Property Corporation

20090166797 - High-voltage integrated circuit device including high-voltage resistant diode: Provided is a high-voltage integrated circuit device including a high-voltage resistant diode. The device includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage... Agent: Hiscock & Barclay, LLP

20090166798 - Design methodology for guard ring design resistance optimization for latchup prevention: A design structure is disclosed for a circuit optimizing guard ring design by optimizing the path resistance value between the components of the parasitic lateral bipolar transistors in a CMOS circuit and the power supply or ground. By comparing the calculated path resistance value to a maximum resistance number derived... Agent: Scully, Scott, Murphy & Presser, P.C.

20090166800 - Interlayer dielectric material in a semiconductor device comprising a doublet structure of stressed materials: By forming a buffer material above differently stressed contact etch stop layers followed by the deposition of a further stress-inducing material, enhanced overall device performance may be accomplished, wherein an undesired influence of the additional stress-inducing layer may be reduced in device regions, for instance, by removing the additional material... Agent: Williams, Morgan & Amerson

20090166799 - Method of manufacturing a semiconductor device and such a semiconductor device: According to the invention the second sublayer (4B) is formed in such a way that the lower border thereof is in relation to the lower border of the first sublayer (4A) formed sunken in the semiconductor body (1). In this way the formation of so called FD (=Fully Depleted) SOI... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090166801 - Fuse of semiconductor device and method for manufacturing the same: A method for manufacturing a fuse of a semiconductor device comprises forming an island-type metal fuse in a region where a laser is irradiated, so that laser energy may not be dispersed in a fuse blowing process, thereby improving repair efficiency.... Agent: Marshall, Gerstein & Borun LLP

20090166802 - Semiconductor device with fuse and method for fabricating the same: A method for fabricating a semiconductor with a fuse includes providing a substrate, forming an insulation layer over the substrate, forming a polysilicon hard mask to form a metal contact over the insulation layer, forming a first mask pattern to form a fuse over the polysilicon hard mask, and removing... Agent: Lowe Hauptman Ham & Berner, LLP

20090166803 - Semiconductor device with fuse and method for fabricating the same: A method for fabricating a semiconductor with a fuse includes providing a substrate, forming an insulation layer over the substrate, forming a polysilicon hard mask to form a metal contact over the insulation layer, forming a first mask pattern to form a fuse over the polysilicon hard mask, and removing... Agent: Lowe Hauptman Ham & Berner, LLP

20090166804 - Forming inductor and transformer structures with magnetic materials using damascene processing for integrated circuits: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure... Agent: Intel Corporation C/o Cpa Global

20090166805 - Metal insulator metal capacitor and method of manufacturing the same: Disclosed are a metal insulator metal (MIM) capacitor and a method of manufacturing a MIM capacitor. The MIM capacitor includes a lower metal interconnection layer, a dielectric layer pattern formed on the lower metal interconnection layer, and a third metal layer pattern formed on the dielectric layer pattern. The dielectric... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090166806 - Epitaxial semiconductor layer and method: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods... Agent: Schwegman, Lundberg & Woessner/micron

20090166807 - Integrated semiconductor optical device: A semiconductor laser (a first semiconductor optical device) and an optical modulator (a second semiconductor optical device) are integrated on the same n-type InP substrate. The semiconductor laser butt-joined to the optical modulator. Each of the semiconductor laser and the optical modulator has a Be-doped p-type InGaAs contact layer. The... Agent: Leydig Voit & Mayer, Ltd

20090166808 - Laser processing method and semiconductor chip: This laser processing method irradiates a substrate 4 with laser light L while using a rear face 21 as a laser light entrance surface and locating a light-converging point P within the substrate 4, so as to form modified regions 71, 72, 73 within the substrate 4. Here, the HC... Agent: Drinker Biddle & Reath (dc)

20090166809 - Semiconductor device and its manufacture: A reliable semiconductor device is provided which comprises lower and upper IGBTs 1 and 2 preferably bonded to each other by solder, and a wire strongly connected to lower IGBT 1. The semiconductor device comprises a lower IGBT 1, a lower electrode layer 5 secured on lower IGBT 1, an... Agent: Bachman & Lapointe, P.C.

20090166810 - Semiconductor device crack-deflecting structure and method: The invention relates to microelectronic semiconductor devices, and to mass-production of the same on semiconductor wafers with novel crack-deflecting structures and methods. According to the invention, a semiconductor device includes an active circuit area surrounded by an inactive area and circumscribed with a bulwark having a crack-deflecting face oriented toward... Agent: Texas Instruments Incorporated

20090166811 - Semiconductor device and manufacturing method thereof: A semiconductor device has a semiconductor chip and through electrodes formed passing through the semiconductor chip. A ground layer connected to the through electrode and a patch antenna connected to the through electrode are provided through an inorganic insulating layer formed of SiO2 or SiN on a second face opposite... Agent: Drinker Biddle & Reath (dc)

20090166812 - Semiconductor and an arrangement and a method for producing a semiconductor: The present invention relates generally to semiconductors, material layers within semiconductors, a production method of semiconductors, and a manufacturing arrangement for producing semiconductors. A semiconductor according to the invention includes at least one layer with a surface, produced by laser ablation, wherein the uniform surface area to be produced includes... Agent: Young & Thompson

20090166813 - Method for manufacturing semiconductor device and semiconductor device: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer on the first semiconductor layer, etching the second semiconductor layer and the first semiconductor layer to form a first groove passing through the second semiconductor layer and the... Agent: Harness, Dickey & Pierce, P.L.C

20090166814 - Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material: A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further... Agent: Williams, Morgan & Amerson

20090166815 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device including a compound semiconductor laminated structure having a plurality of compound semiconductor layers formed over a semiconductor substrate, a first insulation film covering at least a part of a surface of the compound semiconductor laminated structure, and a second insulation film formed on the first insulation film,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090166816 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device may include: forming an oxide film pattern and a poly film pattern over a semiconductor substrate to expose a portion of the surface of the semiconductor substrate; and then forming a spacer composed of a first insulating material on sidewalls of the oxide... Agent: Sherr & Vaughn, PLLC

20090166817 - Extreme low-k dielectric film scheme for advanced interconnects: An extreme low-k (ELK) dielectric film scheme for advanced interconnects includes an upper ELK dielectric layer and a lower ELK dielectric with different refractive indexes. The refractive index of the upper ELK dielectric layer is greater than the refractive index of the lower ELK dielectric layer.... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20090166818 - Positive photosensitive resin composition, and semiconductor device and display therewith: Disclosed is a positive photosensitive resin composition containing (A) an alkali-soluble resin, (B) a diazoquinone compound, (d1) an activated silicon compound and (d2) an aluminum complex. Also disclosed is a positive photosensitive resin composition containing (A) an alkali-soluble resin, (B) a diazoquinone compound, (C) a compound having two or more... Agent: Smith, Gambrell & Russell

20090166819 - Chipset package structure: A chipset package structure includes a carrier, a plurality of pinouts, at least one semiconductor package preforms, at least one electromagnetic shielding layer and a protective layer. The pinouts are disposed on the carrier. The semiconductor package preforms is disposed on the second surface of the carrier and electrically connected... Agent: PCe Industry, Inc. Att. Steven Reiss

20090166820 - Tsop leadframe strip of multiply encapsulated packages: A method of fabricating a semiconductor leadframe package from a strip including multiply encapsulated leadframe packages, and a leadframe package formed thereby are disclosed. An entire row or column of leadframes gets encapsulated together. Encapsulating an entire row or column reduces the keep-out area between adjacent leadframe packages, which allows... Agent: Vierra Magen/sandisk Corporation

20090166821 - Leadframe design for qfn package with top terminal leads: A semiconductor package includes a leadframe. A first lead finger has a lower portion, a connecting portion extending vertically upward from the lower portion, and a substantially flat, top portion. The top portion forms a top terminal lead structure. A second lead finger is electrically connected to the first lead... Agent: Robert D. Atkins

20090166822 - Integrated circuit package system with shielding: An integrated circuit package system comprising: providing an elevated tiebar; forming a die paddle connected to the elevated tiebar; attaching an integrated circuit die over the die paddle adjacent the elevated tiebar; attaching a shield over the elevated tiebar and the integrated circuit die; and forming an encapsulant over a... Agent: Law Offices Of Mikio Ishimaru

20090166828 - Etched surface mount islands in a leadframe package: A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package includes a leadframe and one or more semiconductor die affixed to a die paddle of the leadframe. The leadframe is formed with a plurality of electrical terminals that get surface mounted... Agent: Vierra Magen/sandisk Corporation

20090166823 - Integrated circuit package system with lead locking structure: A mountable integrated circuit package system includes: providing a base; depositing a photoresist on the base; patterning the photoresist with an opening; filling the opening with a metal; depositing a further metal on the metal to form a lead pad; removing the photoresist; attaching a die over the base; bonding... Agent: Law Offices Of Mikio Ishimaru

20090166826 - Lead frame die attach paddles with sloped walls and backside grooves suitable for leadless packages: Disclosed are die paddle structures for leadframes and methods of attaching die to the die paddles. An exemplary die paddle comprises a sloped wall disposed around an attachment area for a die, where the sloped wall has an obtuse angle of inclination with respect to the attachment area. In one... Agent: Townsend And Townsend And Crew, LLP

20090166824 - Leadless package system having external contacts: A leadless package system includes: providing a chip carrier having indentations defining a pattern for a protrusion for external contact terminals; placing an external coating layer in the indentations in the chip carrier; layering a conductive layer on top of the external coating layer; depositing an internal coating layer on... Agent: Law Offices Of Mikio Ishimaru

20090166827 - Mechanical isolation for mems devices: A device according to the present invention includes a MEMS device supported on a first side of a die. A first side of an isolator is attached to the first side of the die. A package is attached to the first side of the isolator, with at least one electrically... Agent: Honeywell International Inc.

20090166829 - Semiconductor memory device: metallic wires for electrically connecting the electrode pads of the plurality of semiconductor elements included in the first and second element groups to the connection pads of the wiring board; and a sealing resin layer formed on the wiring board so as to seal the first and second element groups... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090166825 - System and apparatus for wafer level integration of components: In a semiconductor package, a substrate has an active surface containing a plurality of active circuits. An adhesive layer is formed over the active surface of the substrate, and a known good unit (KGU) is mounted to the adhesive layer. An interconnect structure electrically connects the KGU and active circuits... Agent: Robert D. Atkins

20090166830 - Metallic cover of miniaturization module: A metallic cover of a miniaturization module includes a substrate, a SMD chip unit and a metallic cover, the metallic cover embracing the SMD chip unit and having at least one sizing hole and a plurality of venting holes, the venting holes being disposed around the sizing hole, and the... Agent: Rosenberg, Klein & Lee

20090166831 - Sensor semiconductor package and method for fabricating the same: This invention provides a sensor semiconductor package and a method for fabricating the same. The method includes: mounting on a substrate a sensor chip having a sensor area; electrically connecting the sensor chip and the substrate by means of bonding wires; forming on a transparent member an adhesive layer with... Agent: Edwards Angell Palmer & Dodge LLP

20090166832 - Stacked flip-assembled semiconductor chips embedded in thin hybrid substrate: A semiconductor system having a substrate (101) including a rigid insulating interposer (110) with a high modulus and a top (140) and a bottom (150) low-modulus tape with flip-attached semiconductor chips (120, 130). The assembled chips, with the passive surfaces facing each other, are located in an opening (114) of... Agent: Texas Instruments Incorporated

20090166833 - Semiconductor unit which includes multiple chip packages integrated together: A semiconductor unit includes an interface plate, a supporting plate integrally formed with the interface plate, two chip packages positioned at opposite sides of the supporting plate, and leading traces running in the interface plate and the supporting plate, connected with the chip packages respectively.... Agent: PCe Industry, Inc. Att. Steven Reiss

20090166837 - Combination of chip package units: A combination includes a first chip package unit and a second chip package unit on which the first chip package unit is placed. Each of the first and second chip package units includes a substrate having a first surface, a second surface, a chip package electrically connected to the first... Agent: PCe Industry, Inc. Att. Steven Reiss

20090166835 - Integrated circuit package system with interposer: An integrated circuit package system including: providing a base substrate; coupling a base integrated circuit on the base substrate; forming a double side molded interposer unit over the base integrated circuit including: providing an interposer substrate having an interposer top and an interposer bottom, mounting a first integrated circuit to... Agent: Law Offices Of Mikio Ishimaru

20090166838 - Laminated mounting structure and memory card: To provide a stacked mounting structure in which the number of semiconductor chips that can be stacked is greater than conventionally, as well as a method for fabricating the same, each semiconductor chip has electrodes provided at least at one end in the stacked mounting structure, and a board holding... Agent: Mcdermott Will & Emery LLP

20090166834 - Mountable integrated circuit package system with stacking interposer: A mountable integrated circuit package system includes: forming a base integrated circuit package system includes: providing a first substrate, and forming a package encapsulation having a cavity over the first substrate with the first substrate partially exposed within the cavity; and mounting an interposer including a central aperture over the... Agent: Law Offices Of Mikio Ishimaru

20090166839 - Semiconductor stack device and mounting method: A semiconductor stack device having semiconductor chips stacked therein, wherein pads 4d of an uppermost semiconductor chip 2d are disposed on the side of a base substrate 1, and the pads 4d of the semiconductor chip 2d and electrodes 8d of the base substrate 1 are connected to each other... Agent: Steptoe & Johnson LLP

20090166836 - Stacked wafer level package having a reduced size: A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A... Agent: Ladas & Parry LLP

20090166840 - Wafer-level stack package: A wafer-level stack package includes semiconductor chips, first connection members, a second connection member, a substrate and an external connection terminal. The semiconductor chips have a power/ground pad and a signal pad. The first connection members are electrically connected to the power/ground pad and the signal pad of each of... Agent: Stanzione & Kim, LLP

20090166842 - Leadframe for semiconductor package: A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the... Agent: Stetina Brunda Garred & Brucker

20090166841 - Package substrate embedded with semiconductor component: A package substrate embedded with a semiconductor component includes a substrate, a semiconductor chip, a first dielectric layer, a first circuit layer and first conductive vias. The substrate is formed with an opening for allowing the semiconductor chip to be secured therein. The semiconductor chip has an active surface and... Agent: Knobbe Martens Olson & Bear LLP

20090166843 - Semiconductor device and method for manufacturing a semiconductor device: A semiconductor device includes a semiconductor chip including a first conducting element, and a second conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a first location. It further includes a third conducting element arranged outside the semiconductor chip and electrically connected to... Agent: Dickstein Shapiro LLP

20090166844 - Metal cover on flip-chip matrix-array (fcmx) substrate for low cost cpu assembly: In some embodiments, a metal cover on flip-chip matrix-array (FCMX) substrate for low cost CPU assembly is presented. In this regard, an apparatus is introduced comprising a plurality of integrated circuit dice coupled with a substrate, a thermal interface material on top surfaces of the dice, and a metal plate... Agent: Intel Corporation C/o Cpa Global

20090166845 - Integrated circuit package system with extended corner leads: An integrated circuit package system including: forming a die pad, wherein the die pad has a tiebar at a corner; forming a lead wherein the lead is connected to the tiebar; connecting an integrated circuit die to the die pad; and forming an encapsulation, having an edge, over the integrated... Agent: Law Offices Of Mikio Ishimaru

20090166846 - Pass-through 3d interconnect for microelectronic dies and associated systems and methods: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A... Agent: Perkins Coie LLP Patent-sea

20090166847 - Semiconductor chip package: A semiconductor chip package is provided. The semiconductor chip package comprises a package substrate having a first surface and a second surface opposite to the first surface. A through hole extends through the package substrate. A semiconductor chip is disposed on the first surface of the package substrate, wherein a... Agent: Quintero Law Office, PC

20090166848 - Method for enhancing the adhesion of a passivation layer on a semiconductor device: In a method for making a semiconductor component, an integrated circuit is provided with a chip pad on an active side. A conductive track is connected to the chip pad and a passivation layer covers the conductive track. Forming the conductive track includes structuring an uneven sidewall for form closure... Agent: Slater & Matsil, L.L.P.

20090166849 - Semiconductor chip: A semiconductor chip includes a die mounted on a packaging substrate. The die includes a semiconductor substrate; inter-metal dielectric layers on the semiconductor substrate; levels of metal interconnection, wherein at least two potential equivalent metal traces are formed in a level of the metal interconnection; a passivation layer disposed over... Agent: North America Intellectual Property Corporation

20090166850 - High-power semiconductor die packages with integrated heat-sink capability and methods of manufacturing the same: An exemplary semiconductor die package of the invention has a metal-oxide substrate disposed between a first surface of a semiconductor die and a heat-sinking component, with a conductive die clip or one or more electrical interconnect traces disposed between the metal-oxide substrate and the first surface of the semiconductor die.... Agent