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Active solid-state devices (e.g., transistors, solid-state diodes) June invention type 06/09

20090159866 - Integrated circuits with phase change devices: Embodiments include methods, apparatus, and systems with integrated circuits having phase change devices. One embodiment includes an integrated circuit die and a phase change die having a phase change material that changes phases when a temperature at the integrated circuit die exceeds a threshold for a predetermined amount of time.... Agent: Hewlett Packard Company

20090159867 - Phase change memory with layered insulator: A phase change memory may be formed with an insulator made up of two different layers having significantly different thermal conductivities. Pores may be formed within the stack of insulating layers and the pores may be filled with heaters, chalcogenide layers, and electrodes in some embodiments. The use of the... Agent: Trop, Pruner & Hu, P.C.

20090159868 - Phase change material layer and phase change memory device including the same: Provided are a phase change material layer and a phase change random access memory (PRAM) device including the same. By providing a phase change material layer formed of a III-V family material and a chalcogenide, a PRAM device with a set time shorter than that of a conventional PRAM device... Agent: Harness, Dickey & Pierce, P.L.C

20090159870 - Light emitting diode element and method for fabricating the same: The present invention discloses a light emitting diode (LED) element and a method for fabricating the same, which can promote light extraction efficiency of LED, wherein a substrate is etched to obtain basins with inclined natural crystal planes, and an LED epitaxial structure is selectively formed inside the basin. Thereby,... Agent: Joe Mckinney Muncy

20090159871 - Light emitting diode structure and method for fabricating the same: The present invention discloses a light emitting diode structure and a method for fabricating the same. In the present invention, a substrate is placed in a solution to form a chemical reaction layer. Next, the substrate is etched to form a plurality of concave zones and a plurality of convex... Agent: Joe Mckinney Muncy

20090159869 - Solid state light emitting device: A semiconductor structure (10, 10′, 70, 80) includes a light emitter (12, 72) carried by a support structure (11). The light emitter (12, 72) includes a base region (24, 76) with a sloped sidewall (12a, 12b) and a light emitting region (25, 77) positioned thereon. The light emitting (25, 77)... Agent: Greg L. Martinez

20090159872 - Reducing ambipolar conduction in carbon nanotube transistors: Ambipolar conduction can be reduced in carbon nanotube transistors by forming a gate electrode of a metal. Metal sidewall spacers having different workfunctions than the gate electrode may be formed to bracket the metal gate electrode.... Agent: Trop, Pruner & Hu, P.C.

20090159877 - Electroactive materials: b

20090159873 - Functional molecular device: A functional molecular device displaying its functions under the action of an electrical field is provided. A Louis base molecule, exhibiting positive dielectric constant anisotropy or exhibiting dipole moment along the long-axis direction of the Louis base molecule, is arrayed in the form of a pendant on an electrically conductive... Agent: K&l Gates LLP

20090159874 - Organic electroluminescent devices: f

20090159876 - Organic semiconductor material and organic field effect transistor: Disclosed is an adequately stable organic semiconductor material which can be used in a coating process while having high regularity and crystallinity. For obtaining such an organic semiconductor material, there is used a compound wherein 6-20 five-membered and/or six-membered aromatic rings are bound. This compound contains a partial structure represented... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090159878 - Organic thin film transistor: A thin film transistor comprising at least three terminals consisting of a gate electrode, a source electrode and a drain electrode; an insulator layer and an organic semiconductor layer on a substrate, which controls its electric current flowing between the source and the drain by applying a electric voltage across... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090159875 - Producing layered structures with semiconductive regions or subregions: In layered structures, channel regions and light-interactive regions can include the same semiconductive polymer material, such as with an organic polymer. A light-interactive region can be in charge-flow contact with a contacting electrode region, and a channel region can, when conductive, provide an electrical connection between the contacting electrode region... Agent: Leading Edge Law Group, PLC/xerox-parc

20090159880 - Electronic device and method of manufacturing the same: A method of manufacturing an electronic device comprising the subsequent steps of: providing a thermal conversion material or an area comprising the thermal conversion material and, in an adjoining area or in a vicinity of the thermal conversion material or the area comprising the thermal conversion material, a material having... Agent: Lucas & Mercanti, LLP

20090159879 - Thin film transistor, method of fabricating a thin film transistor and flat panel display device having the same: A TFT includes a substrate, a transparent semiconductor layer on the substrate, the transparent semiconductor layer including zinc oxide and exhibiting a surface roughness of about 1.3 nm or less, a gate electrode on the transparent semiconductor layer, a gate insulating layer between the gate electrode and the transparent semiconductor... Agent: Lee & Morse, P.C.

20090159881 - Semiconductor apparatus and method for manufacturing the same: The present invention is a method for manufacturing a semiconductor apparatus including a chip which is fabricated in large numbers on a wafer and has a plurality of information blocks. In the method, a unique information bit is written in a chip discrimination block of each chip 10 within a... Agent: Mattingly & Malur, P.C.

20090159883 - Test pattern for semiconductor device and method for forming the test pattern: A test pattern for a semiconductor device and a method for forming the test pattern that can determine the degree of over etching of contact holes and obviate the need to perform a physical analysis using SEM, FIB or the like after the wafer is destroyed.... Agent: Sherr & Vaughn, PLLC

20090159882 - Test pattern of semiconductor device and manufacturing method thereof: A test pattern of a semiconductor device and manufacturing method thereof are provided. The test pattern can include an isolation layer on a semiconductor substrate to define an active area, a gate electrode on the active area, and a source/drain area at a first area of the active area between... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090159885 - Diode and display device including diode: A thin film transistor which includes a microcrystalline semiconductor film over a gate electrode with a gate insulating film interposed therebetween to be in an inner region in which end portions of microcrystalline semiconductor film are in an inside of end portions of the gate electrode, an amorphous semiconductor film... Agent: Eric Robinson

20090159884 - Thin-film transistor, method of manufacturing the same, and display device: A method of manufacturing a thin-film transistor according to an embodiment of the present invention includes the step of forming a gate insulator on a gate electrode. The gate insulator includes at least a first region being in contact with a hydrogenated amorphous silicon film, and a second region positioned... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090159888 - Display panel and method for manufacturing the same: A display panel and a manufacturing method thereof which includes forming a color filter on an insulating substrate, forming a plurality of trenches in the color filter, forming a first metal layer in the trenches, forming a second metal layer on the first metal layer to form gate lines, forming... Agent: Cantor Colburn, LLP

20090159886 - Printed tft array: An electronic device and/or component is manufactured using additive processing steps, including additive printing steps. A first layer is printed using additive printing techniques wherein a single first material is used to print the first layer in a single processing step. A second layer is printed in more than a... Agent: Fay Sharpe / Xerox - Parc

20090159890 - Semiconductor display device: A semiconductor display device using a light-emitting element, which can suppress luminance unevenness among pixels due to the potential drop of a wiring, is provided. Power supply lines to which a power supply potential is supplied are electrically connected to each other in a display region where a plurality of... Agent: Cook Alex Ltd

20090159889 - Tft substrate, display panel including the tft substrate, display device including the tft substrate, and method for manufacturing the tft substrate: The present invention provides a method of manufacturing a TFT substrate, in which method a data signal line is separated into upper and lower regions at a separating point(Q) that is not around above a scan signal line but in a region where an i-layer and an n+ layer formed... Agent: Nixon & Vanderhye, PC

20090159887 - Thin film transistor and method of manufacturing the same: A thin film transistor and a method of manufacturing the thin film transistor is disclosed. The thin film transistor includes first and second ohmic contact layers, an activation layer, an insulating layer, a source electrode formed on the insulating layer and connected to the first ohmic contact layer through first... Agent: Haynes And Boone, LLPIPSection

20090159892 - Array substrate for liquid crystal display device and method of fabricating the same: An array substrate for an LCD device includes a first TFT including a first semiconductor layer, a first gate electrode, wherein the first gate electrode is directly over the first semiconductor layer; a first protrusion extending from the first gate electrode along an edge of the first semiconductor layer; a... Agent: Mckenna Long & Aldridge LLP

20090159893 - Light-receiving element and display device: A light-receiving element includes: a first-conductivity-type semiconductor region configured to be formed over an element formation surface; a second-conductivity-type semiconductor region configured to be formed over the element formation surface; an intermediate semiconductor region configured to be formed over the element formation surface between the first-conductivity-type semiconductor region and the... Agent: Sonnenschein Nath & Rosenthal LLP

20090159891 - Modifying a surface in a printed transistor process: A method of forming an electronic device includes depositing a dielectric, forming a first functional material layer having a first surface energy, depositing at least one first at least semiconductive feature of the device, forming a second functional material layer to provide a surface having a second surface energy, and... Agent: Marger Johnson & Mccollom/parc

20090159895 - Array substrate for liquid crystal display device and fabricating method of the same: A method of manufacturing an array substrate for a liquid crystal display device includes forming a gate line, a gate pad, a gate electrode, and a data pad on a substrate through a first mask process, forming a gate insulating layer on a substantial part of an entire surface of... Agent: Mckenna Long & Aldridge LLP

20090159894 - Semiconductor device and display device: To provide a semiconductor device and a display device which include a circuit element capable of improving performances and a circuit element capable of increasing a withstand voltage on the same substrate and which can improve the reliability. The semiconductor device of the present invention includes a first circuit element... Agent: Nixon & Vanderhye, PC

20090159897 - Method for treating semiconductor processing components and components formed thereby: A semiconductor processing component has an outer surface portion comprised of silicon carbide, the outer surface portion having a skin impurity level and a bulk impurity level. The skin impurity level is average impurity level from 0 nm to 100 nm of depth into the outer surface portion, the bulk... Agent: Larson Newman Abel & Polansky, LLP

20090159898 - Semiconductor device and method of manufacturing thereof: A semiconductor device is provided in which the contact resistance of the interface between an electrode and the semiconductor substrate is reduced. The semiconductor device includes a 4H polytype SiC substrate, and an electrode formed on a surface of the substrate. A 3C polytype layer, which extends obliquely relative to... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090159896 - Silicon carbide mosfet devices and methods of making: A method of making a silicon carbide MOSFET is disclosed. The method includes providing a semiconductor device structure, wherein the device structure comprises a silicon carbide semiconductor device layer, an ion implanted well region of a first conductivity type formed in the semiconductor device layer, an ion implanted source region... Agent: General Electric Company Global Research

20090159899 - Light- emitting device: A light-emitting device includes a substrate having an epitaxial-forming surface and a back surface opposite to the epitaxial-forming surface, the substrate being formed with a recess indented from the back surface, the back surface having a recessed portion that defines the recess, and a planar portion extending outwardly from the... Agent: Abelman, Frayne & Schwab

20090159900 - Infrared proximity sensor package with reduced crosstalk: Disclosed are various embodiments of an infrared proximity sensor package comprising an infrared transmitter die, an infrared receiver die, a housing comprising outer sidewalls, a first recess, a second recess and a partitioning divider disposed between the first and second recesses. The transmitter doe is positioned in the first recess,... Agent: Kathy Manke Avago Technologies Limited

20090159901 - Display: A display includes: a substrate having a pixel region and a sensor region in which photo-sensor parts are formed; an illuminating section operative to illuminate the substrate from one surface side of the substrate; a thin film photodiode disposed in the sensor region, having at least a P-type semiconductor region... Agent: Robert J. Depke Lewis T. Steadman

20090159902 - Flip-chip type semiconductor light-emitting device, method for manufacturing flip-chip type semiconductor light-emitting device, printed circuit board for flip-chip type semiconductor light-emitting device, mounting structure for flip-chip type semiconduc: A flip-chip type semiconductor light-emitting device having a positive electrode and a negative electrode similar in electrode area and capable of preventing the misalignment of the light-emitting device by utilizing the self alignment effect in manufacturing a light-emitting diode lamp and a printed circuit board for the flip-chip type semiconductor... Agent: Sughrue Mion, PLLC

20090159903 - Light chain: A light chain includes a plurality of light emitting diodes (LEDs) electrically connected to each other. Each LED includes an LED chip having a first pole and a second pole, and a packaging layer encapsulating the LED chip. A first electrode has an inner end connected to the first pole,... Agent: PCe Industry, Inc. Att. Steven Reiss

20090159905 - Light emitting assembly: A light emitting assembly includes: a heat sink having a base wall and at least one mesa protruding from the base wall; and at least one light emitting package unit having at least one light emitting package bonded to the mesa so as to transfer heat generated from the light... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC

20090159904 - Light source device, light source module, and method of making the light source device: A light source device includes a lead frame, a first solid-state lighting chip, a first transparent encapsulation, a second solid-state lighting chip, and a second transparent encapsulation. The first solid-state lighting chip and the second solid-state lighting chip are respectively located at two opposite sides of the lead frame and... Agent: PCe Industry, Inc. Att. Steven Reiss

20090159906 - Light-emitting device, method for manufacturing light-emitting device, and electronic apparatus: A light-emitting device includes an organic insulating layer lying above a face of a substrate, reflective layers arranged on a face of the organic insulating layer, an inorganic insulating layer extending over the reflective layers, pixel electrodes arranged on the inorganic insulating layer, and light-emitting sections arranged on the respective... Agent: Oliff & Berridge, PLC

20090159907 - Textured light emitting diodes: A high fill factor textured light emitting diode structure comprises: a first textured cladding and contact layer (2) comprising a doped III-V or II-VI group compound semiconductor or alloys of such semiconductors deposited by epitaxial lateral overgrowth (ELOG) onto a patterned substrate (1); a textured undoped or doped active layer... Agent: Christie, Parker & Hale, LLP

20090159908 - Semiconductor light emitting device with light extraction structures: Structures are incorporated into a semiconductor light emitting device which may increase the extraction of light emitted at glancing incidence angles. In some embodiments, the device includes a low index material that directs light away from the metal contacts by total internal reflection. In some embodiments, the device includes extraction... Agent: Philips Intellectual Property & Standards

20090159909 - Nitride semiconductor light-emitting device with electrode pattern: A nitride semiconductor light-emitting device with an electron pattern that applies current uniformly to an active layer to improve light emission efficiency is provided. The nitride semiconductor light-emitting device includes multiple layers of a substrate, an n-type nitride layer, an active layer of a multi-quantum-well structure, and a p-type nitride... Agent: Mcdermott Will & Emery LLP

20090159912 - Housing for a luminescence diode component: What is specified is a housing for a luminescence diode component comprising a housing cavity within which is arranged at least one chip mounting region for a luminescence diode chip and which has an output opening. In accordance with one embodiment, the housing has, at least at a vertical distance... Agent: Fish & Richardson PC

20090159915 - Led insert module and multi-layer lens: An LED insert module formed of a conducting carrier and a multi-layer lens is described. Layers of the lens are doped with phosphorescent material in order to control appearance of light produced by an LED die located in the insert module. Multiple modules may be embedded in a heat sink... Agent: Kenton R. Mullins Stout, Uxa, Buyan & Mullins, LLP

20090159910 - Light emitting diode structure and method for fabricating the same: The present invention discloses a light emitting diode structure and a method for fabricating the same. In the present invention, a substrate is placed in a solution to form a chemical reaction layer on carved regions; the carved region is selectively etched to form a plurality of concave zones and... Agent: Joe Mckinney Muncy

20090159916 - Light source with reflective pattern structure: A light source includes a substrate and a light-emitting unit. The substrate has a pattern structure, which includes a plurality of concave-convex structures. The light-emitting unit is formed on the pattern structure, and has a backlight surface connected to the pattern structure and a light outputting surface disposed opposite the... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090159913 - Light-emitting diode: An LED includes an LED chip having a first electrode and a second electrode, a first electrically conductive block and a second electrically conductive block insulated from the first electrically conductive block, a cavity defined in the first electrically conductive block configured for accommodating the LED chip, and a light... Agent: PCe Industry, Inc. Att. Steven Reiss

20090159911 - Light-emitting diode package and method for fabricating the same: An LED package (200) includes a housing (24), an LED array (22), a phosphor layer (262) and a transparent packaging layer (264). The LED array is received in the housing, the phosphor layer is uniformly and homogenously formed on the LED array; and the transparent packaging layer packages the LED... Agent: PCe Industry, Inc. Att. Steven Reiss

20090159917 - Semiconductor light emitting device: Provided are a semiconductor light emitting device and a method for fabricating the same. The semiconductor light emitting device comprises a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer comprising a dual roughness structure on the active layer.... Agent: Birch Stewart Kolasch & Birch

20090159918 - Semiconductor light emitting devices and submounts and methods for forming the same: A submount for a semiconductor light emitting device includes a semiconductor substrate having a cavity therein configured to receive the light emitting device. A first bond pad is positioned in the cavity to couple to a first node of a light emitting device received in the cavity. A second bond... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090159914 - White light emitting diode (wled) and packing method thereof: A white light emitting diode (LED) and the packing method thereof are described. The white LED includes a supporting frame, a LED chip, glue for mixing phosphor powder, and phosphor powder, wherein the glue for mixing phosphor powder comprises a first set of compositions and a second set of compositions,... Agent: Austin Rapp & Hardman

20090159919 - Led lighting apparatus with swivel connection: Disclosed is a LED lighting apparatus with one or more swivel connections. The LED lighting apparatus includes a housing with at least one end, at least one light emitting diode extending along the housing and at least one end cap. The end cap has an opening with a sidewall to... Agent: Young & Basile, P.C.

20090159920 - Nitride semiconductor light emitting device and manufacturing method of the same: There is provided a nitride semiconductor light emitting device including: a light emitting structure including n-type and p-type nitride semiconductor layers and an active layer disposed therebetween; n- and p-electrodes electrically connected to the n-type and p-type nitride semiconductor layers, respectively; and an n-type ohmic contact layer disposed between the... Agent: Mcdermott Will & Emery LLP

20090159922 - Nitride semiconductor light emitting device and method of manufacturing the same: e

20090159923 - Nitride semiconductor light emitting device, method of manufacturing nitride semiconductor light emitting device, and nitride semiconductor transistor device: Provided are a nitride semiconductor light emitting device including a coat film formed at a light emitting portion and including an aluminum nitride crystal or an aluminum oxynitride crystal, and a method of manufacturing the nitride semiconductor light emitting device. Also provided is a nitride semiconductor transistor device including a... Agent: Harness, Dickey & Pierce, P.L.C

20090159921 - Nitride semiconductor light emitting element, nitride semiconductor light emitting device and method for manufacturing such nitride semiconductor light emitting device: A nitride semiconductor device according to the present invention includes a n-GaN substrate 10 and a semiconductor multilayer structure arranged on the principal surface of the n-GaN substrate 10 and including a p-type region, an n-type region and an active layer between them. An SiO2 layer 30 with an opening... Agent: Mark D. Saralino (pan) Renner, Otto, Boisselle & Sklar, LLP

20090159924 - Semiconductor light emitting element and method for fabricating the same: The semiconductor laser of this invention includes an active layer formed in a c-axis direction, wherein the active layer is made of a hexagonal-system compound semiconductor, and anisotropic strain is generated in a c plane of the active layer.... Agent: Ratnerprestia

20090159925 - Bidirectional electronic switch: A main semiconductor region grown on a substrate has formed on its surface a pair of main electrodes spaced from each other, a gate electrode between the main electrodes, and a pair of diode-forming electrodes spaced farther away from the gate electrode than are the main electrodes. Making ohmic contact... Agent: Woodcock Washburn LLP

20090159926 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a thyristor in which a first-conductivity-type first region, a second-conductivity-type second region having a conductivity type reverse to the first conductivity type, a first-conductivity-type third region, and a second-conductivity-type fourth region are sequentially arranged to form junctions. The third region is formed on a semiconductor substrate... Agent: Robert J. Depke Lewis T. Steadman

20090159927 - Integrated circuit device and method for its production: An integrated circuit device includes a semiconductor body fitted with a first electrode and a second electrode on opposite surfaces. A control electrode on an insulating layer controls channel regions of body zones for a current flow between the two electrodes. A drift section adjoining the channel regions comprises drift... Agent: Dicke, Billig & Czaja

20090159928 - Power semiconductor devices: A power semiconductor device including source and drain regions located in a lateral arrangement in a first portion of the device, and at least one current providing cell located in a second portion of the device and spaced apart from the first portion at least by a substrate region of... Agent: Volentine & Whitt PLLC

20090159929 - Heterostructure device and associated method: A heterostructure device includes a semiconductor multi-layer structure that has a first region, a second region and a third region. The first region is coupled to a source electrode and the second region is coupled to a drain electrode. The third region is disposed between the first region and the... Agent: General Electric Company Global Research

20090159930 - High electron mobility transistor having self-aligned miniature field mitigating plate and protective dielectric layer and fabrication method thereof: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source... Agent: Posz Law Group, PLC

20090159931 - Semiconductor device: Provided are embodiments of a semiconductor device having bit lines and bit bar lines. The bit lines and the bit bar lines are arranged in alternate succession across a substrate. At least two of proximate bit lines, bit line bars, power lines, and ground lines of the semiconductor device are... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090159933 - Integration scheme for changing crystal orientation in hybrid orientation technology (hot) using direct silicon bonded (dsb) substrates: Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has... Agent: Texas Instruments Incorporated

20090159932 - Integration scheme for reducing border region morpphology in hybrid orientation technology (hot) using direct silicon bonded (dsb) substrates: Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells appropriate for the technology node. This invention provides a method... Agent: Texas Instruments Incorporated

20090159934 - Field effect device with reduced thickness gate: A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer... Agent: Scully, Scott, Murphy & Presser, P.C.

20090159935 - Cmos image sensor and method for manufacturing the same: Disclosed are a CMOS image sensor and a method for manufacturing the same, capable of improving the characteristics of the image sensor by increasing junction capacitance of a floating diffusion area. The CMOS image sensor generally includes a photodiode and a plurality of transistors (e.g., transfer, reset, drive, and select... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090159936 - Device with asymmetric spacers: An asymmetrical spacer adjacent a gate is formed. This asymmetry is used to form offset regions in a device.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090159938 - Method of manufacturing a semiconductor device and semiconductor device obtained with such a method: The invention relates to a method of manufacturing a semiconductor device (10) comprising a field effect transistor, in which method a semiconductor body of silicon (12) with a substrate (11) is provided at a surface thereof with a source region (1) and a drain region (2) of a first conductivity... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090159939 - Semiconductor device and manufacturing method for the same: A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region including second impurity atoms, provided shallower than the first diffusion region from a... Agent: Foley And Lardner LLP Suite 500

20090159937 - Simple scatterometry structure for si recess etch control: Dimensions of structures in integrated circuits are shrinking with each new fabrication technology generation. Maintaining control of profiles of structures in transistors and interconnects is becoming more important to sustaining profitable integrated circuit production facilities. Measuring profiles of structures with many elements in integrated circuits, such as MOS transistor gates... Agent: Texas Instruments Incorporated

20090159941 - Cmos image sensor and method for fabricating the same: A complementary metal oxide silicon (CMOS) image sensor and a method for fabricating the same. In one example embodiment, a CMOS image sensor includes a substrate, a first dielectric film, a plurality of metal patterns, a second dielectric film, a plurality of via holes, a plurality of metal wires, a... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090159945 - Image pickup apparatus and image pickup system: A well 302 is formed on a wafer 301, and semiconductor layers 101a, 101b are formed in the well to constitute photodiodes. A well contact 306 is formed between the semiconductor layers 101a, 101b. Element isolation regions 303b, 303a are provided between the well contact and the semiconductor layers, and... Agent: Fitzpatrick Cella Harper & Scinto

20090159942 - Image sensor and method for manufacturing the same: An image sensor can include a readout circuitry, a metal interconnection, a metal layer, and an image sensing device. The metal interconnection can be formed over the readout circuitry and the metal layer can be formed over the metal interconnection. The image sensing device can be formed over the metal... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090159943 - Image sensor and method for manufacturing the same: An image sensor may include a dielectric, a metal interconnection, an align key, a first substrate, a photodiode, and a transparent electrode. The first substrate may include a pixel region, a peripheral circuitry region and a scribe lane. The dielectric may include a metal interconnection and an align key over... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090159944 - Image sensor and method of manufacturing the same: An image sensor comprises a substrate including a photodiode, and an insulation pattern structure making contact with the photodiode on the substrate. An anti-reflection pattern is formed on the insulation pattern structure and the substrate. The anti-reflection pattern includes a first opening through which the insulation pattern structure is exposed... Agent: F. Chau & Associates, LLC

20090159940 - Structure and method for flexible sensor array: A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.... Agent: Marger Johnson & Mccollom, P.C. - Xerox

20090159946 - Logic non-volatile memory cell with improved data retention ability: A memory cell includes a semiconductor substrate; and a first, a second, and a third transistor. The first transistor includes a first dielectric over the semiconductor substrate; and a first floating gate over the first dielectric. The second transistor is electrically coupled to the first transistor and includes a second... Agent: Slater & Matsil, L.L.P.

20090159947 - Simplified vertical array device dram/edram integration: The present invention provides a semiconductor structure that includes an active wordline located above a semiconductor memory device and a passive wordline located adjacent to said active wordline and above an active area of a substrate. In accordance with the present invention, the passive wordline is separated from the active... Agent: Scully, Scott, Murphy & Presser, P.C.

20090159948 - Trench metal-insulator metal (mim) capacitors: The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET), and a design structure including the semiconductor device embodied in a machine readable medium. The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of... Agent: Scully, Scott, Murphy & Presser, P.C.

20090159949 - Semiconductor memory device which includes memory cell having charge accumulation layer and control gate: A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and a voltage generator. In the memory cell unit, memory cells having a charge accumulation layer and a control gate are connected in series. The word lines are connected to the control gates. The driver circuit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090159951 - Flash memory device: Embodiments relate to a flash memory device and a method of manufacturing a flash memory device, which may increase a coupling coefficient between a control gate and a floating gate by increasing a surface area of floating gate. In embodiments, a flash memory device may be formed by forming a... Agent: Sherr & Vaughn, PLLC

20090159952 - Method of fabricating non-volatile memory integrated circuit device and non-volatile memory integrated circuit device fabricated using the same: A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second... Agent: F. Chau & Associates, LLC

20090159950 - Semiconductor device and manufacturing method of semiconductor device: A conductor pattern including a gate electrode and an auxiliary pattern spaced apart by a narrow gap is formed on a substrate, an insulating film for a gate insulating film is formed so as to cover the same, a resist film is formed thereon, and the resist film is exposed... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090159953 - Method for manufacturing flash memory device: Embodiments relate to a flash memory device and a method for manufacturing a flash memory device. According to embodiments, a method may include forming a gate on and/or over a semiconductor substrate on and/or over which a device isolation film may be formed, forming a first spacer including a first... Agent: Sherr & Vaughn, PLLC

20090159954 - Non-volatile two-transistor programmable logic cell and array layout: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within... Agent: Lewis And Roca LLP

20090159955 - Nonvolatile memory device and method of fabricating the same: A nonvolatile memory device includes a semiconductor substrate, a tunneling insulation layer on the semiconductor substrate, a charge storage layer on the tunneling insulation layer, an inter-electrode insulation layer on the charge storage layer, and a control gate electrode on the inter-electrode insulation layer. The inter-electrode insulation layer includes a... Agent: Volentine & Whitt PLLC

20090159956 - Nor flash memory and method of manufacturing the same: A NOR flash memory has a plurality of memory cell transistors, wherein each memory cell transistor shares the source diffusion layer with another memory cell transistor adjacent thereto on one side thereof in the column direction and shares the drain diffusion layer with another memory cell transistor adjacent thereto on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090159958 - Electronic device including a silicon nitride layer and a process of forming the same: An electronic device can include a silicon nitride layer. In an embodiment, the silicon nitride layer can include boron, grains, or both. The silicon nitride layer may be used as part of a charge storage layer within a nonvolatile memory cell within the electronic device. In a particular embodiment, the... Agent: Larson Newman Abel & Polansky, LLP

20090159960 - Non-volatile memory device: A non-volatile memory device includes a memory cell region which is formed on a semiconductor substrate to store predetermined information, and a peripheral circuit region which is formed on the semiconductor substrate. The memory cell region includes a gate electrode; and a charge storage layer, the charge storage layer being... Agent: Rabin & Berdo, PC

20090159957 - Nonvolatile memories with laterally recessed charge-trapping dielectric: Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.... Agent: Haynes And Boone, LLPIPSection

20090159959 - Nonvolatile semiconductor memory device and method of fabricating the same: A charge trap flash (CTF) memory cell and manufacturing method include a semiconductor substrate and an isolation region and an active region being formed in the substrate. A tunneling layer, a charge trapping layer and a blocking layer are formed on the isolation region and the active region. A resistance... Agent: Mills & Onello LLP

20090159961 - Semiconductor memory device with stacked gate including charge storage layer and control gate and method of manufacturing the same: A semiconductor memory device includes a first active region, a second active region, a first element isolating region and a second element isolating region. The first active region is formed in a semiconductor substrate. The second active region is formed in the semiconductor substrate. The first element isolating region electrically... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090159962 - Non-volatile memory devices: Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and... Agent: Myers Bigel Sibley & Sajovec

20090159963 - Semiconductor device including a plurality of cells: A semiconductor device includes an insulated gate transistor and a resistor. The insulated gate transistor includes a plurality of first cells for supplying electric current to a load and a second cell for detecting an electric current that flows in the first cells. A gate terminal of the plurality of... Agent: Posz Law Group, PLC

20090159964 - Vertical channel transistor and method of fabricating the same: A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is deposited on the side wall of the active pillar pattern and serves as an ion diffusion barrier between the pillar patterns... Agent: Lowe Hauptman Ham & Berner, LLP

20090159965 - Semiconductor device and method for fabricating the same: A semiconductor device includes pillar patterns, a gate insulation layer surrounding the pillar patterns, and a conductive layer surrounding the gate insulation layer and connects neighboring gate insulation layers.... Agent: Lowe Hauptman Ham & Berner, LLP

20090159966 - High voltage semiconductor device, method of fabricating the same, and method of fabricating the same and a low voltage semiconductor device together on a substrate: A high voltage semiconductor device comprises a substrate, a well, a gate structure, and a source/drain structure in a grade region in a well in the substrate. The gate structure is disposed on the substrate with a portion vertically down into a trench in the well in the substrate and... Agent: North America Intellectual Property Corporation

20090159967 - Semiconductor device having various widths under gate: One embodiment of the invention relates to a semiconductor device formed over a semiconductor body. In this device, source and drain regions are formed in the body about lateral edges of a gate electrode and are separated from one another by a gate length. A channel region, which is configured... Agent: Texas Instruments Incorporated

20090159968 - Bvdii enhancement with a cascode dmos: Double diffused MOS (DMOS) transistors feature extended drain regions to provide depletion regions which drop high drain voltages to lower voltages at the gate edges. DMOS transistors exhibit lower drain breakdown potential in the on-state than in the off-state than in the off-state due to snapback by a parasitic bipolar... Agent: Texas Instruments Incorporated

20090159969 - Process for manufacturing a semiconductor power device comprising charge-balance column structures and respective device: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity... Agent: Graybeal Jackson LLP

20090159970 - Semiconductor device and its manufacturing method: Provided are a semiconductor device which can be manufactured at low cost and has a low on-resistance and a high withstand voltage, and its manufacturing method. The semiconductor device comprises an N-type well area formed on a P-type semiconductor substrate, a P-type body area formed within the well area, an... Agent: Nixon & Vanderhye, PC

20090159971 - Printed tft and tft array with self-aligned gate: A method is used to form a self-aligning thin film transistor. The thin film transistor includes a gate contact formed with a state-switchable material, and a dielectric layer to isolate the gate contact. A source-drain layer, which includes a source contact, and a drain contact are formed with a source-drain... Agent: Fay Sharpe / Xerox - Parc

20090159972 - Method of fabricating multi-gate semiconductor devices with improved carrier mobility: A method of fabricating a multi-gate device is disclosed. In one aspect, the method includes providing a substrate having a first semiconductor layer with a first carrier mobility enhancing parameter, an insulating layer, a second semiconductor layer with a second carrier mobility enhancing parameter different from the first carrier mobility... Agent: Knobbe Martens Olson & Bear LLP

20090159973 - Semiconductor device having non-silicide region in which no silicide is formed on diffusion layer: A semiconductor device includes first and second MOSFETs corresponding to at least first power source voltage and second power source voltage lower than the first power source voltage, and non-silicide regions formed in drain portions of the first and second MOSFETs and having no silicide formed therein. The first MOSFET... Agent: Turocy & Watson, LLP

20090159974 - Semiconductor device: A high-frequency power amplifier of the type to be mounted in an RF module for mobile phones having high-frequency power field effect transistors and gate protective diodes which are coupled between the gates and the sources of the high-frequency power field effect transistors. The gate protective diodes have an n... Agent: Mattingly & Malur, P.C.

20090159975 - Integration of planar and tri-gate devices on the same substrate: An apparatus including a first diffusion formed on a substrate, the first diffusion including a pair of channels, each of which separates a source from a drain; a second diffusion formed on the substrate, the second diffusion including a channel that separates a source from a drain; a first gate... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090159976 - Integrated circuit and method for making an integrated circuit: An integrated circuit comprises a dielectric layer located on a substrate and an electrode located on the dielectric layer. The electrode comprises a first metallic layer located on the dielectric layer and a second metallic layer. Moreover, a method of making an integrated circuit is described.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090159978 - Semiconductor device and process for manufacturing same: A semiconductor device 100 includes a first gate 210, which is formed using a gate last process. The first gate 210 includes a gate insulating film formed in a bottom surface in a first concave portion formed in the insulating film; a gate electrode formed over the gate insulating film... Agent: Young & Thompson

20090159977 - Semiconductor device having gate electrode including contact portion on element isolation region: A semiconductor device has gate electrodes disposed in plural columns, respectively, over a semiconductor substrate in such a way as to be lined up along the direction of a gate length, and a gate connection portion provided in the same layer where the respective gate electrodes in the plural columns... Agent: Mcginn Intellectual Property Law Group, PLLC

20090159979 - Semiconductor device with misfet: A semiconductor device includes a substrate, a semiconductor region provided in the substrate, a group of transistors including a plurality of MIS transistors and provided in the semiconductor region, the MIS transistors including a plurality of gate electrodes which extend in a first direction and are provided on the semiconductor... Agent: Foley And Lardner LLP Suite 500

20090159980 - Semiconductor device and method of fabricating the same: A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a conductive well formed by implanting a first conductive impurity into a semiconductor substrate, a device isolation film on one side of the conductive well, and an insulating region below the device isolation film... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090159981 - Strain modulation in active areas by controlled incorporation of nitrogen at si-sio2 interface: Adding nitrogen to the Si—SiO2 interface at STI sidewalls increases carrier mobility in MOS transistors, but control of the amount of nitrogen has been problematic due to loss of the nitrogen during liner oxide growth. This invention discloses a method of forming STI regions which have a controllable layer of... Agent: Texas Instruments Incorporated

20090159982 - Bi-cmos semiconductor device and method of manufacturing the same: A Bi-CMOS semiconductor device and method for manufacturing the same are provided. An n-well can be formed in a semiconductor substrate, and an NMOS transistor can be provided on the substrate separated from the n-well by a device isolation layer. An NPN bipolar transistor can be formed using the n-well.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090159983 - Non-destructive inline epi pattern shift monitor using selective epi: Integrated circuits using buried layers under epitaxial layers present a challenge in aligning patterns for surface components to the buried layers, because the epitaxial material over the buried layer diminishes the visibility of and shifts the apparent position of the buried layer. A method of measuring the lateral offset, known... Agent: Texas Instruments Incorporated

20090159984 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the same are provided. An n-well region can be formed on a semiconductor substrate, and a base contact region can be formed on the n-well region. An emitter contact region, a collector contact region, and a p-base region can also be formed... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090159985 - Integrated circuit system with contact integration: A method for forming an integrated circuit system includes providing an integrated circuit device; and forming an integrated contact over the integrated circuit device including: providing a via over the integrated circuit device; forming a selective metal in the via; forming at least one nanotube over the selective metal; and... Agent: Farjami & Farjami LLP

20090159986 - Semiconductor device: A semiconductor device is disclosed that can operate utilizing thermoelectric concepts. According to an embodiment, the semiconductor device can comprise: a source/drain conductor formed of a line of metal material on a substrate; a first gate conductor formed of a second line of metal material; and a second gate conductor... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090159987 - Semiconductor device for reducing interference between adjoining gates and method for manufacturing the same: A semiconductor device includes a semiconductor substrate having an active region having a plurality of recessed channel areas extending across the active region and a plurality of junction areas also extending across the active region. Gates are formed in and over the recessed channel areas of the active region. A... Agent: Ladas & Parry LLP

20090159988 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in... Agent: Ladas & Parry LLP

20090159989 - Semiconductor device and method of fabricating the same: Disclosed is a method of fabricating a semiconductor device. The method can include forming a gate material layer on an inner surface of a trench which extends into a part of a semiconductor substrate by passing through an insulating layer formed on the semiconductor substrate, etching the gate material layer... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090159990 - Semiconductor device and method of manufacturing the same: A semiconductor device and/or a method of manufacturing the same that may include: Forming a gate insulating film over a semiconductor substrate in a gate region. Forming a first gate pattern over the gate insulating film. Forming a second gate pattern over the first gate pattern, such that the second... Agent: Sherr & Vaughn, PLLC

20090159991 - Cmos devices with different metals in gate electrodes using spin on low-k material as hard mask: A semiconductor structure and a method of forming the same. The semiconductor structure includes a semiconductor substrate, a gate dielectric layer on top of the semiconductor substrate. The structure also includes a first metal containing region on top of the gate dielectric layer. The structure also includes a second metal... Agent: Schmeiser, Olsen & Watts

20090159993 - Semiconductor device and method for fabricating the same: A semiconductor device and/or a method for manufacturing a semiconductor device. A method may include at least one of the following: Forming a first oxide layer on a silicon substrate. Depositing a polysilicon layer on the first oxide layer. Forming a pattern on the polysilicon layer and the first oxide... Agent: Sherr & Vaughn, PLLC

20090159992 - Semiconductor device having a polysilicon electrode: A method of manufacturing a semiconductor device such as a MOS transistor. The device comprises a polysilicon gate (10) and doped regions (22,24) formed in a semiconductor substrate (12), separated by a channel region (26). The exposed surface of the semiconductor substrate is amorphized, by ion bombardment for example, so... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090159994 - Semiconductor device and method of manufacturing the same: Semiconductor devices and manufacturing methods thereof are provided. A semiconductor device can include a gate dielectric, a gate electrode, sidewall spacers, and source and drain regions. The gate electrode can include an electrode seed layer and an electrode metal layer. In another embodiment, the gate electrode can be formed of... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090159995 - Method to deposit particles on charge storage apparatus with charge patterns and forming method for charge patterns: The present invention discloses a method to deposit particles on a charge storage apparatus with charge patterns and a forming method for charge patterns. The forming method for charge patterns includes providing the charge storage apparatus having an electrically conducting substrate and a charge storage media layer. The charge storage... Agent: Rosenberg, Klein & Lee

20090159996 - Method of producing microsprings having nanowire tip structures: A stress-engineered microspring is formed generally in the plane of a substrate. A nanowire (or equivalently, a nanotube) is formed at the tip thereof, also in the plane of the substrate. Once formed, the length of the nanowire may be defined, for example photolithographically. A sacrificial layer underlying the microspring... Agent: JasIPConsulting

20090159997 - Wafer level package structure and production method therefor: A wafer level package structure, in which a plurality of compact sensor devices with small variations in sensor characteristics are formed, and a method of producing the same are provided. This package structure has a semiconductor wafer having plural sensor units, and a package wafer bonded to the semiconductor wafer.... Agent: Cheng Law Group, PLLC

20090159998 - Method for manufacturing semiconductor device: It is an object of the present invention to provide a method for manufacturing a semiconductor device, which is flexible and superiority in physical strength. As a method for manufacturing a semiconductor device, an element layer including a plurality of integrated circuits is formed over one surface of a substrate;... Agent: Eric Robinson

20090159999 - Quantum dot solar cell with electron rich anchor group: A solar cell may including a quantum dot, an electron conductor and a bridge molecule disposed between the quantum dot and the electron conductor. The bridge molecule may include a quantum dot anchor that bonds to the quantum dot and an electron conductor anchor that bonds to the electron conductor.... Agent: Honeywell International Inc.

20090160002 - Image sensor and method for fabricating the same: An image sensor may include an image sensor may include a photodiode formed over a semiconductor substrate. An interlayer dielectric, which may include a plurality of metal wires in a transistor region, may be formed over the semiconductor substrate, including a waveguide dielectric for guiding incident light in a photodiode... Agent: Sherr & Vaughn, PLLC

20090160003 - Image sensor and method for manufacturing the same: Embodiments relate to an image sensor and a method for manufacturing the same. According to embodiments, an image sensor may include a semiconductor substrate and a transistor. An interlayer insulating layer, including a metal line, may be formed on and/or over the semiconductor substrate. A lower electrode may be formed... Agent: Sherr & Vaughn, PLLC

20090160000 - Image sensor and method for manufacturing the sensor: An image sensor and a method for manufacturing the sensor are provided for reducing loss of light reflected from photodiodes, and thus, improving light efficiency. The method of manufacturing an image sensor can include providing a semiconductor substrate having a photodiode; and then forming a reflective film frame on the... Agent: Sherr & Vaughn, PLLC

20090160001 - Image sensor and method for manufacturing the sensor: An image sensor and a method for manufacturing the same are disclosed. The image sensor manufacturing method may include forming a hard mask pattern over a semiconductor substrate to cover a photodiode region; forming convex photodiodes by wet-etching the photodiode region in the semiconductor substrate using the hard mask pattern;... Agent: Sherr & Vaughn, PLLC

20090160004 - Semiconductor device and method for manufacturing the device: Embodiments relate to a semiconductor device and a method for manufacturing a semiconductor device. According to embodiments, a method may include forming a metal layer on and/or over a lower structure formed on and/or over a semiconductor substrate, forming neighboring metal lines by patterning the metal layer by a photolithography... Agent: Sherr & Vaughn, PLLC

20090160005 - Image sensor and method for manufacturing the same: An image sensor includes circuitry, a metal interconnection, a first substrate, a metal ion-implanted insulating layer, and a photodiode. The circuitry is formed on and/or over the first substrate, and the metal ion-implanted insulating layer is formed on and/or over the metal interconnection. The photodiode is formed in a crystalline... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090160006 - Systems and methods for biasing high fill-factor sensor arrays and the like: A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically... Agent: Oliff & Berridge, PLC.

20090160007 - Systems and methods for biasing high fill-factor sensor arrays and the like: A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically... Agent: Oliff & Berridge, PLC

20090160008 - Semiconductor device and method of manufacturing the same: A semiconductor device that includes an n-type semiconductor substrate and an upper electrode formed on an upper face of the semiconductor substrate and a method of manufacturing the semiconductor device are provided. A p-type semiconductor region is repeatedly formed in the semiconductor substrate in at least one direction parallel to... Agent: Kenyon & Kenyon LLP

20090160011 - Isolator and method of manufacturing the same: The present invention relates to an isolator and a method of manufacturing the same. An isolator according to the present invention includes a silicon wafer, protective devices formed in predetermined regions of the silicon wafer, and a transformer formed in a predetermined region on the silicon wafer, the transformer having... Agent: HorizonIPPte Ltd

20090160009 - Semiconductor array and method for manufacturing a semiconductor array: e

20090160010 - Semiconductor device and method for manufacturing the device: A semiconductor device and a method for manufacturing the device capable of preventing an LDD region and a lower portion of the gate electrode from overlapping each other to achieve desirable device performance are disclosed. Embodiments relate to a semiconductor device and a method for manufacturing the device that may... Agent: Sherr & Vaughn, PLLC

20090160012 - Semiconductor device and method for fabricating the same: Embodiments relate to a semiconductor device and a method for fabricating the same. According to embodiments, a semiconductor device may include a first device, a silicon epitaxial layer formed on and/or over the first device, a second device formed on and/or over the silicon epitaxial layer, and a connection via... Agent: Sherr & Vaughn, PLLC

20090160013 - Semiconductor device heat dissipation structure: A heat generating component of a semiconductor device is located between two heavily doped semiconductor regions in a semiconductor substrate. The heat generating component may be a middle portion of a diode having a light doping, a lightly doped p-n junction between a cathode and anode of a silicon controlled... Agent: Scully, Scott, Murphy & Presser, P.C.

20090160014 - Semiconductor device and method for manufacturing the same: A semiconductor device and/or a method for manufacturing a semiconductor device. A method may include at least one of the following: Forming a first semiconductor layer over a semiconductor substrate. Forming a second semiconductor layer over the first semiconductor layer. Forming a trench through the first and second semiconductor layers.... Agent: Sherr & Vaughn, PLLC

20090160015 - Semiconductor device and method of forming a semiconductor device: In a power semiconductor device and a method of forming a power semiconductor device, a thin layer of semiconductor substrate is left below the drift region of a semiconductor device. A power semiconductor device has an active region that includes the drift region and has top and bottom surfaces formed... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20090160016 - Semiconductor device: A semiconductor device having a bipolar transistor improved with heat dissipation. A semiconductor device having bipolar transistors formed in a plurality of device forming regions electrically isolated from each other by device isolation trenches traversing the semiconductor layer, in which a device isolation trench for each of unit bipolar transistors... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090160017 - Semiconductor device having capacitor, transistor and diffusion resistor and manufacturing method thereof: In manufacturing a semiconductor device including a substrate having a (111)-plane orientation and an off-set angle in a range between 3 degrees and 4 degrees, a capacitor, a transistor and a diffusion resistor are formed in the substrate, each of which are separated by a junction separation layer. A first... Agent: Posz Law Group, PLC

20090160018 - Inductor and manufacturing method threof: An inductor includes an inductor wiring made of a metal layer and having a spiral planar shape. In a cross-sectional shape in a width direction of the inductor wiring, the inductor wiring has a larger film thickness at least in its inner side end than in its middle part.... Agent: Mcdermott Will & Emery LLP

20090160021 - Corona prevention in high power mmics: The present invention is drawn to an MMIC capacitor comprising a dielectric material interposed between a metal top plate and a metal bottom plate; and a passivation layer having the composition of the dielectric material and applied to the capacitor components such that thickness of the layer eliminates a corona... Agent: HowardIPLaw Group

20090160022 - Method of fabricating mim structure capacitor: The present invention relates to a method of fabricating a MIM structure capacitor. The method includes sequentially depositing a nitride film, a Ti film, and a TiN film over a lower electrode metal layer, the nitride film being an insulating layer, and a combination of the Ti/TiN layers being a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090160020 - Moisture barrier capacitors in semiconductor components: Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.... Agent: Slater & Matsil LLP

20090160019 - Semiconductor capacitor: A capacitor structure is provided. The capacitor structure includes a plurality of first conductive lines paralleled disposed in a conductive layer on a substrate, wherein the first conductive lines are isolated to each other in the conductive layer and are grouped into a first electrode group and a second electrode... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090160023 - Semiconductor device and manufacturing method thereof: An insulation film (24) having a gradual inclination of a surface is formed by a high density plasma CVD method, an atmospheric pressure CVD method or the like, after a ferroelectric capacitor (23) is formed. Thereafter, an alumina film (25) is formed on the insulation film (24). According to the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090160024 - Vertical resistors and band-gap voltage reference circuits: A vertical resistor. A substrate includes a trench filled by an isolation layer. A first doped-type region and a second doped-type region are formed on both sides of the trench. The first doped-type region receives a control bias, the second doped-type region receives a reference bias, and a resistance between... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20090160025 - Lateral bipolar transistor: A P+ base drawing diffusion region is formed on a substrate having an SOI structure. N+ emitter diffusion regions are formed on both sides of the P+ base drawing diffusion region through isolation insulating films interposed therebetween. A P type SOI layer, which serves as a base diffusion region, is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090160026 - Nitride semiconductor free-standing substrate and method for making same: A nitride semiconductor free-standing substrate includes a nitride semiconductor crystal and an inversion domain with a density of not less than 10/cm2 and not more than 600/cm2 in a section parallel to a surface of the substrate and inside the substrate. A method for making the nitride semiconductor free-standing substrate... Agent: Mcginn Intellectual Property Law Group, PLLC

20090160028 - Method for forming gaps in micromechanical device and micromechanical device: An exemplary method for forming gaps in a micromechanical device includes providing a substrate. A first material layer is deposited over the substrate. A sacrificial layer is deposited over the first material layer. A second material layer is deposited over the sacrificial layer such that at least a portion of... Agent: PCe Industry, Inc. Att. Steven Reiss

20090160027 - Methods of manufacturing semiconductor devices and optical proximity correction: Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size... Agent: Slater & Matsil LLP

20090160029 - Scribe seal structure for improved noise isolation: Disclosed is a semiconductor wafer with an array of integrated circuit chips with scribe lane structures forming edge and intra-chip seals for use in protecting the IC circuitry. Substantially parallel scribe seal structures extend around the periphery of each chip; the two scribe seal structures have a separation gap. Preferred... Agent: Texas Instruments Incorporated

20090160030 - Methods for forming through wafer interconnects and structures resulting therefrom: The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the... Agent: Trask Britt, P.C./ Micron Technology

20090160032 - Printed electronic device and transistor device and manufacturing method thereof: An electronic device, e.g., a printed transistor device, comprises a substrate, a first conductive layer, a second conductive layer and a semiconductor layer. The substrate has a first platform and a second platform embossing on the surface thereof, and the first and second platforms are separated by a gap whose... Agent: Wpat, PC Intellectual Property Attorneys

20090160031 - Semiconductor device and method for fabricating the same: A semiconductor device capable of preventing damage to a thermal oxide layer in a trench, and a method for fabricating the same are disclosed. The device includes a trench in a field region of a semiconductor substrate; a pad oxide layer on the surface of the semiconductor substrate outside the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090160034 - Mesa semiconductor device and method of manufacturing the same: The invention provides a mesa semiconductor device and a method of manufacturing the same which minimize the manufacturing cost and prevents contamination and physical damage of the device. An N− type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is... Agent: Morrison & Foerster LLP

20090160035 - Mesa semiconductor device and method of manufacturing the same: The invention provides a mesa semiconductor device and a method of manufacturing the same which enhance the yield and productivity. An N− type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed... Agent: Morrison & Foerster LLP

20090160033 - Semiconductor optical element: A light receiving element 1 has a semiconductor substrate 101; a first mesa 11 provided over the semiconductor substrate 101, and having an active region and a first electrode (p-side electrode 111) provided over the active region; a second mesa 12 provided over the semiconductor substrate 101, and having a... Agent: Young & Thompson

20090160037 - Method of packaging integrated circuits: A method of packaging an integrated circuit die having a plurality of I/O pads is described. The method includes positioning the die within a die attach area of a first leadframe that includes a plurality of first leads. The method also includes positioning a second leadframe that includes a plurality... Agent: Beyer Law Group LLP/ Nsc

20090160036 - Package with multiple dies: A semiconductor die package is disclosed. It includes a leadframe structure comprising a first die attach pad and a second die attach pad. A plurality of leads extend from the first and second die attach pads. The plurality of leads includes at least a first control lead and a second... Agent: Townsend And Townsend And Crew, LLP

20090160038 - Semiconductor package with leads on a chip having multi-row of bonding pads: A LOC leadframe-based semiconductor package includes a chip with multiple rows of bonding pads. At least a bus bar is attached to the chip and is disposed between a first row of bonding pads and the fingers of the leads. A plurality of bonding wires electrically connect the first row... Agent: Joe Mckinney Muncy

20090160039 - Method and leadframe for packaging integrated circuits: A leadframe suitable for use in the packaging of at least two integrated circuit dice into a single integrated circuit package is described. The leadframe includes a plurality of leads. Each of a first set of the plurality of leads has a first side and a second side substantially opposite... Agent: Beyer Law Group LLP/ Nsc

20090160040 - Low temperature ceramic microelectromechanical structures: A method of providing microelectromechanical structures (MEMS) that are compatible with silicon CMOS electronics is provided. The method provides for processing and manufacturing is steps limiting a maximum exposure of an integrated circuit upon which the MEMS is manufactured during MEMS manufacturing to below a temperature wherein CMOS circuitry is... Agent: Freedman & Associates

20090160041 - Substrate package structure: A substrate package structure is disclosed herein. The substrate package structure includes a packaging substrate provided with a plurality of chip carriers set at one surface of the packaging substrate, wherein those chip carriers are formed by intersecting a plurality of cutting streets; a plurality of through holes set at... Agent: Rosenberg, Klein & Lee

20090160042 - Managed memory component: A system and method for combining a leaded package IC and a semiconductor die using a flex circuitry. The leaded packaged IC is disposed along an obverse side of a flex circuit. In a preferred embodiment, the lower surface of the body of the leaded packaged IC contacts the surface... Agent: Fish & Richardson P.C.

20090160043 - Dice rearrangement package structure using layout process to form a compliant configuration: A dice rearrangement package structure is provided, which a dice having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover the dices and the plurality of pads being exposed; one ends of plurality of... Agent: Sinorica, LLC

20090160044 - Semiconductor module mounting structure: The semiconductor module mounting structure includes a semiconductor module including therein a semiconductor device and electrodes exposed to both surfaces thereof, a wiring substrate having a mounting surface on which the semiconductor module is mounted, and a heat radiating body for dissipating heat from the semiconductor module. The wiring substrate... Agent: Nixon & Vanderhye, PC

20090160045 - Wafer level chip scale packaging: A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between... Agent: Joshua D. Isenberg Jdi Patent

20090160046 - Electronic device and method: An electronic device and method is disclosed. In one embodiment, a method includes providing an electrically insulating substrate. A first electrically conductive layer is applied over the electrically insulating substrate. A first semiconductor chip is placed over the first electrically conductive layer. An electrically insulating layer is applied over the... Agent: Dicke, Billig & Czaja

20090160047 - Downhole tool: A downhole tool having at least one semiconductor device, including: a die; a bonding pad which is attached to the surface of the die; a bonding wire which is attached to the bonding pad; a bonding point which is formed on the bonding pad for connecting the bonding wire to... Agent: Schlumberger K.k.

20090160048 - Semiconductor unit, and power conversion system and on-vehicle electrical system using the same: A semiconductor device includes a semiconductor chip and leads electrically connected to the electrodes of the semiconductor chip. A hollow radiator base houses the semiconductor device which is molded with high-thermal-conductivity resin having an electrical insulating property. The radiator base has a cooling-medium channel therein or radiating fins on the... Agent: Crowell & Moring LLP Intellectual Property Group

20090160051 - Semiconductor chip, method of fabricating the same and semiconductor chip stack package: Provided are a semiconductor chip, a method of fabricating a semiconductor chip, and a semiconductor chip stack package. The semiconductor chip includes a semiconductor substrate and a semiconductor device on the semiconductor substrate. A dielectric covers the semiconductor device. A top metal is on the dielectric and electrically connected to... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090160049 - Semiconductor device: A semiconductor device of the present invention includes a semiconductor chip; an internal pad for electrical connection formed on a surface of the semiconductor chip; a stress relaxation layer formed on the semiconductor chip and having an opening for exposing the internal pad; a connection pad made of a metal... Agent: Rabin & Berdo, PC

20090160050 - Semiconductor device manufacturing method, semiconductor device and wafer: A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer... Agent: Mccormick, Paulding & Huber LLP

20090160053 - Method of manufacturing a semiconducotor device: A method of manufacturing a semiconductor device is disclosed. One embodiment provides a carrier. Semiconductor chips are placed over the carrier. The semiconductor chips include contact elements. A polymer material is applied over the semiconductor chips and the carrier. The polymer material is removed until the contact elements are exposed.... Agent: Dicke, Billig & Czaja

20090160052 - Under bump metallurgy structure of semiconductor device package: The under bump metallization (UBM) structure of semiconductor device comprises a substrate having a bonding pad disposed on an active surface; a UBM adhered on the bonding pad, wherein the UBM includes lateral embedded portions and the size of the UBM is larger than the size of the bonding pad;... Agent: Kusner & Jaffe Highland Place Suite 310

20090160054 - Nitride semiconductor device and method of manufacturing the same: A nitride semiconductor device is provided which reduces the contact resistance at the interface between a P-type electrode and a nitride semiconductor layer. A nitride semiconductor device includes a P-type nitride semiconductor layer and a P-type electrode formed on the P-type nitride semiconductor layer. The P-type electrode is formed by... Agent: Leydig Voit & Mayer, Ltd

20090160055 - Ic solder reflow method and materials: Embodiments of IC manufacture resulting in improved electromigration and gap-fill performance of interconnect conductors are described in this application. Reflow agent materials such as Sn, Al, Mn, Mg, Ag, Au, Zn, Zr, and In may be deposited on an IC substrate, allowing PVD depositing of a Cu layer for gap-fill... Agent: Intel Corporation C/o Cpa Global

20090160056 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the same. The method can include forming a plurality of vias in a first interlayer insulation layer formed on a semiconductor substrate; and then forming a photoresist pattern over the first interlayer insulation layer to expose a portion of the first interlayer... Agent: Sherr & Vaughn, PLLC

20090160057 - Semiconductor device and method of manufacturing the same: A semiconductor device is provided in which penetration of a metal into a high impurity-doped active region from a side wall portion of a contact hole is prevented by reducing an aspect ratio to improve coverage of a titanium nitride film for the side wall portion of the contact hole,... Agent: Bruce L. Adams, Esq Adams & Wilks

20090160058 - Structure and process for the formation of tsvs: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a... Agent: Slater & Matsil, L.L.P.

20090160059 - Semiconductor device having improved adhesion and reduced blistering between etch stop layer and dielectric layer: One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first interlevel dielectric layer (165) over the transistors (120, 125), and forming metal interconnects (170, 175) within the first interlevel dielectric layer... Agent: Texas Instruments Incorporated

20090160060 - Method of manufacturing semiconductor device: Embodiments relate to a method of manufacturing a semiconductor device having a porous low-k dielectric layer. According to embodiments, a method may include forming an inter metal dielectric (IMD) layer on and/or over a semiconductor substrate, forming copper lines having a stepped structure in the IMD layer, forming a barrier... Agent: Sherr & Vaughn, PLLC

20090160061 - Introducing a metal layer between sin and tin to improve cbd contact resistance for p-tsv: The present disclosure provide an integrated circuit. The integrated circuit includes a through-silicon-via (TSV) trench configured in a semiconductor substrate; a conductive pad formed on the semiconductor substrate, the conductive pad being adjacent the TSV trench; a silicon nitride layer disposed over the conductive pad and in the TSV trench;... Agent: Haynes And Boone, LLPIPSection

20090160063 - Semiconductor device: A semiconductor device includes a semiconductor substrate; a sealing resin layer formed on a top face of the semiconductor substrate; a metal post formed on the top face of the semiconductor substrate such that a top face of the metal post is exposed through the sealing resin layer; a projecting... Agent: Fish & Richardson P.C.

20090160062 - Semiconductor devices and methods of manufacturing thereof: Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one... Agent: Slater & Matsil LLP

20090160064 - Semiconductor device and method for manufacturing the device: A semiconductor device and a method for manufacturing the device that minimizes a line width while maximizing integration density of the semiconductor device. The method includes forming an interlayer insulating film on a semiconductor substrate, and then forming a first via hole in the interlayer insulating film, and then forming... Agent: Sherr & Vaughn, PLLC

20090160065 - Reconstituted wafer level stacking: A stacked microelectronic assembly is fabricated from a structure which includes a plurality of first microelectronic elements having front faces bonded to a carrier. Each first microelectronic element may have a first edge and a plurality of first traces extending along the front face towards the first edge. After exposing... Agent: Tessera, Inc.

20090160066 - Semiconductor element, semiconductor device, and fabrication method thereof: Semiconductor elements and methods for fabricating semiconductor elements that allow semiconductor elements having the same function to utilize different packaging methods. An exemplary semiconductor element includes a first semiconductor element portion, including an internal circuit, electrodes electrically connected to the internal circuit, and a first insulating layer covering the internal... Agent: Taft, Stettinius & Hollister LLP

20090160068 - Flip-chip package and method of forming thereof: A flip-chip package is disclosed. The flip-chip package includes a substrate comprising at least one build-up layer. At least one longitudinal trench is formed in at least one build-up layer of the substrate. The at least one longitudinal trench filled with a conductive material. A conductive plane may be disposed... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Cpa Global

20090160067 - Integrated circuit package: An integrated circuit package is described that includes two dice. The active surface of each die includes a plurality of I/O pads. The active surface of the first die is positioned adjacent first surfaces of the leads of a leadframe such that I/O pads from the first die are arranged... Agent: Beyer Law Group LLP/ Nsc

20090160069 - Leadless alignment of a semiconductor chip: There is disclosed a mounting technique for mounting a semiconductor chip of the leadless or so-called flip chip type to a header. The header has an insert made of glass or other suitable non-conductive material within the header hollow. Mounted into the glass insert are a series of conductive metal... Agent: Arthur Plevy, Esquire The Plevy Law Firm

20090160070 - Metal line in a semiconductor device: A semiconductor having a metal line and a method of manufacturing a metal line in a semiconductor device is disclosed. In one example embodiment, a method of manufacturing a metal line in a semiconductor device includes various acts. A metal film for a metal line is formed on an interlayer... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090160071 - Die rearrangement package structure using layout process to form a compliant configuration: A die rearrangement package structure is provided, which includes a die that having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover a die and the active surface being exposed; a polymer material with... Agent: Sinorica, LLC

20090152526 - Method for manufacturing a memory element comprising a resistivity-switching nio layer and devices obtained thereof: The present disclosure is related to non-volatile memory devices comprising a reversible resistivity-switching layer used for storing data. The resistivity of this layer can be varied between at least two stable resistivity states such that at least one bit can be stored therein. In particular this resistivity-switching layer is a... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20090152527 - Method for producing catalyst-free single crystal silicon nanowires, nanowires produced by the method and nanodevice comprising the nanowires: Disclosed herein is a method for producing catalyst-free single crystal silicon nanowires. According to the method, nanowires can be produced in a simple and economical manner without the use of any metal catalyst. In addition, impurities contained in a metal catalyst can be prevented from being introduced into the nanowires,... Agent: Cantor Colburn, LLP

20090152528 - High-power, broad-band, superluminescent diode and method of fabricating the same: Provided are a superluminescent diode with a high optical power and a broad wavelength band, and a method of fabricating the same. The superluminescent diode includes: at least one high optical confinement factor (HOCF) region; and at least one low optical confinement factor (LOCF) region having a lower optical confinement... Agent: Ampacc Law Group

20090152529 - Light emitting devices with inhomogeneous quantum well active regions: A method of fabricating a light emitting device includes modulating a crystal growth parameter to grow a quantum well layer that is inhomogeneous and that has a non-random composition fluctuation across the quantum well layer.... Agent: Marger Johnson & Mccollom, P.C. - Xerox

20090152530 - Image sensor including photoelectric charge-trap structure: A pixel of an image sensor includes a first insulating structure, a photoelectric charge-trap structure, a second insulating structure, and a gate electrode. The first insulating structure is formed on a substrate, and the photoelectric charge-trap structure is formed on the first insulating structure. The second insulating structure is formed... Agent: Law Office Of Monica H Choi

20090152537 - Composition for organic polymer gate insulating layer and organic thin film transistor using the same: p

20090152536 - Dna-based electronic diodes and their applications: A semiconductor device provides a metal contact, a DNA layer, wherein the metal layer and the DNA layer are adapted to form a Schottky barrier junction there between, and a conductive contact with the DNA layer.... Agent: Burns & Levinson, LLP

20090152532 - Field effect transistor, method of manufacturing the same, and electronic device using the same: A field-effect transistor includes a semiconductor layer (14) having a portion functioning as a channel region. The semiconductor layer (14) includes, as its constituent components, a plurality of electrically conductive microparticles (52), organic semiconductor molecules (53) bonded to the microparticles (52) so as to link the microparticles to one another... Agent: Hamre, Schumann, Mueller & Larson P.C.

20090152533 - Increasing the external efficiency of light emitting diodes: The present disclosure relates to increasing the external efficiency of light emitting diodes, and specifically to increasing the outcoupling of light from an organic light emitting diode utilizing a diffraction grating.... Agent: Foley & Lardner LLP

20090152535 - Novel materials for improving the hole injection in organic electronic devices and use of the material: e

20090152531 - Polar semiconductor hole transporting material: A semiconductive hole transport material containing polar substituent groups, the polar substituent groups substantially not affecting the electronic properties of the hole transport material and the hole transport material being soluble in a polar solvent.... Agent: Marshall, Gerstein & Borun LLP

20090152534 - Producing layered structures with lamination: A layered structure can include laminated first and second substructures and an array with cell regions. The first substructure can include layered active circuitry, the second a top electrode layer. One or both substructure's surface that contacts the other can be on a polymer-containing layer, structured to generate free charge... Agent: Leading Edge Law Group, PLC/xerox-parc

20090152539 - Semiconductor apparatus and fabrication method of the same: It is an object of the present invention to provide a semiconductor device capable of preventing deterioration due to penetration of moisture or oxygen, for example, a light-emitting apparatus having an organic light-emitting device that is formed over a plastic substrate, and a liquid crystal display apparatus using a plastic... Agent: Fish & Richardson P.C.

20090152540 - Semiconductor device and process for producing same: A semiconductor device and process for producing same are provided. The process for producing a semiconductor device includes a first embossing step of pressing a stamp having a relief pattern onto a surface of a substrate to form a depression pattern on the surface of the substrate; a second step... Agent: K&l Gates LLP

20090152538 - Thiazole-based semiconductor compound and organic thin film transistor using the same: Provided are an organic semiconductor compound using thiazole, and an organic thin film transistor having an organic semiconductor layer formed of the organic semiconductor compound using thiazole. The novel organic semiconductor compound including thiazole has liquid crystallinity and excellent thermal stability, and thus is provided to form an organic semiconductor... Agent: Occhiuti Rohlicek & Tsao, LLP

20090152541 - Electronic device, semiconductor device and manufacturing method thereof: The present invention provides a manufacturing process using a droplet-discharging method that is suitable for manufacturing a large substrate in mass production. A photosensitive material solution of a conductive film is selectively discharged by a droplet-discharging method, selectively exposed to laser light, and developed or etched, thereby allowing only the... Agent: Nixon Peabody, LLP

20090152544 - Disguising test pads in a semiconductor package: A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical test of the completed package. The test pads are formed in shapes such as letters or objects so that they are... Agent: Vierra Magen/sandisk Corporation

20090152545 - Feature dimension measurement: A method of measuring dimensional characteristics includes providing a substrate and forming a reflective layer over the substrate. A dielectric layer is then formed over the reflective layer. The dielectric layer includes a grating pattern and a resistivity test line inset in a transparent region. Radiation is then directed onto... Agent: Haynes And Boone, LLPIPSection

20090152547 - Integrated circuit packaging system with leadframe interposer and method of manufacture thereof: A method of manufacture of an integrated circuit packaging system includes: forming a substrate; mounting a base integrated circuit on the substrate; forming a leadframe interposer, over the base integrated circuit, by: providing a metal sheet, mounting an integrated circuit die on the metal sheet, injecting a molded package body... Agent: Law Offices Of Mikio Ishimaru

20090152548 - Semiconductor component: A semiconductor component (has at least one semiconductor chip in which an electrical circuit is integrated. The semiconductor chip is surrounded by an electrically insulating encapsulating compound and has on its surface at least one termination surface for a test signal, which is covered by the encapsulating compound. The termination... Agent: The Webb Law Firm, P.C.

20090152543 - System, structure and method of providing dynamic optimization of integrated circuits using a non-contact method of selection, and a design structure: A system, structure and method is provided for providing dynamic optimization of integrated circuits using a non-contact method of selection, and a design structure on which a subject circuit resides. The method is provided for optimizing an electronic system having at least one integrated circuit. The method includes storing a... Agent: Andrew M. Calderon Greenblum & Bernstein, P.L.C

20090152542 - Testing the quality of lift-off processes in wafer fabrication: Test methods and components are disclosed for testing the quality of lift-off processes in wafer fabrication. A wafer is populated with one or more test components along with the functional components. These test components are fabricated with holes in an insulation layer that is deposited between conductive layers, where the... Agent: Duft Bornsen & Fishman, LLP

20090152546 - Wafer with scribe lanes comprising active circuits for die testing of complementary signal processing parts: A wafer (W) comprises at least one die (D1-D6) comprising first (P1) and second (P2) complementary signal processing parts, scribe lanes (SL) defined between and around each die, and coupling means (CM) defined in at least a part of the scribe lanes (SL) and connecting i) the first part output... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090152549 - Memory device: A memory device is provided, which includes a memory element including a first electrode, a second electrode, and a silicon layer disposed between the first electrode and the second electrode. The memory element is capable of being in a first state, a second state, and a third state. A first... Agent: Nixon Peabody, LLP

20090152550 - Semiconductor device and method for manufacturing semiconductor device: An object is to provide a semiconductor device including a microcrystalline semiconductor film with favorable quality and a method for manufacturing the semiconductor device. In a thin film transistor formed using a microcrystalline semiconductor film, yttria-stabilized zirconia having a fluorite structure is formed in the uppermost layer of a gate... Agent: Fish & Richardson P.C.

20090152557 - Electro-luminescence device including a thin film transistor and method of fabricating an electro-luminescence device: An electro-luminescence device including an electro-luminescence element and a thin film transistor electrically connected to the electro-luminescence element. The thin film transistor includes a gate electrode formed over a substrate, an insulating layer formed over the gate electrode, and a first semiconductor pattern formed over the insulating layer. An etch... Agent: F. Chau & Associates, LLC

20090152556 - Liquid crystal display panel and fabricating method thereof: A liquid crystal display panel includes: a thin film transistor array substrate having a gate line and a data line provided on the substrate; a gate insulating film between the gate line and the data line; a thin film transistor having a source electrode, a drain electrode and a gate... Agent: Mckenna Long & Aldridge LLP

20090152552 - Pixel structure and repairing method thereof: A pixel structure disposed on a substrate and including a common line, a reserved line, a dielectric layer, two repair lines, an active device, and a pixel electrode is provided. The reserved line and the common line are disposed on the substrate and are covered by the dielectric layer. The... Agent: Jianq Chyun Intellectual Property Office

20090152551 - Semiconductor device and manufacturing method thereof: A means of forming unevenness for preventing specular reflection of a pixel electrode, without increasing the number of process steps, is provided. In a method of manufacturing a reflecting type liquid crystal display device, the formation of unevenness (having a radius of curvature r in a convex portion) in the... Agent: Eric Robinson

20090152555 - Thin film transistor display substrate and method of the fabricating the same: A thin film transistor display substrate comprises a base substrate on which a pixel area including a first reflection area and a second reflection area is defined. A gate line formed on the base substrate and a data line formed on the base substrate. The data line is insulated from... Agent: Haynes And Boone, LLPIPSection

20090152554 - Thin film transistor, display device including the same and manufacturing method thereof: A thin film transistor, a display device, and a manufacturing method thereof. The thin film transistor includes a control electrode, a semiconductor overlapping the control electrode, and an input electrode and an output electrode disposed on or under the semiconductor and opposite to each other. The semiconductor includes a first... Agent: Cantor Colburn, LLP

20090152553 - Thin-film transistor, substrate and display device each having the thin-film transistor, and method of manufacturing the thin-film transistor: A thin-film transistor (TFT) includes a gate electrode, a semiconductor pattern, a source electrode, and a drain electrode. The semiconductor pattern includes an active layer being overlapped with the gate electrode and a low band gap portion having a lower energy band gap than the active layer. The source and... Agent: Haynes And Boone, LLPIPSection

20090152559 - Manufacturing method of thin film transistor and manufacturing method of display device: A manufacturing method of a thin film transistor and a display device using a small number of masks is provided. A first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked. Then, a resist mask having a recessed portion is... Agent: Fish & Richardson P.C.

20090152558 - Semiconductor device and method of manufacturing the same: Provided is a lateral semiconductor device with a trench structure for improving driving capability. A trench portion is formed in a well to give concave and convex portions in a gate width direction. A gate electrode is formed inside and above the trench portion with an insulating film therebetween. A... Agent: Bruce L. Adams, Esq Adams & Wilks

20090152562 - Liquid crystal display device and fabricating method thereof: A method of fabricating a liquid crystal display device includes forming first, second, and third active patterns on a substrate having a pixel region and a driving region, wherein the first and second active patterns are in the driving region and the third active pattern is in the pixel region,... Agent: Morgan Lewis & Bockius LLP

20090152560 - Method for fabricating thin film transistor array substrate and thin film transistor array substrate: After forming a gate electrode (4a) in a first step, a gate insulating film (5), a semiconductor film (8) and a conducting film (12) including a transparent conducting film (9) are stacked, and on the thus obtained multilayered body (18), a resist pattern (13a) including a first opening (14a) for... Agent: Nixon & Vanderhye, PC

20090152561 - Organic thin film transistor display substrate, method of fabricating the same, and display apparatus having the same: In an organic thin film transistor display substrate, a thin film transistor and a pixel electrode electrically connected to the thin film transistor are formed on an array substrate in which a plurality of pixel areas is defined. Also, color filters are formed in the pixel areas. Each color filter... Agent: Haynes And Boone, LLPIPSection

20090152563 - Photo-sensor and manufacturing method for photo-sensor: The present invention prevents disconnection of a source electrode and a drain electrode, taking account of adhesion with amorphous silicon. A photo-sensor according to the present invention is a photo-sensor having a TFT array substrate that has an element region in which thin film transistors are arranged in an array,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090152564 - Thin film transistor array substrate: A thin film transistor array substrate includes an insulating substrate, a plurality of scan lines, an insulating layer, a plurality of data lines, and a plurality of pixels arranged in an array of rows and columns. The pixels in each row are aligned in a row direction, the pixels in... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090152565 - Pendeo epitaxial structures and devices: A substrate comprising a trench lateral epitaxial overgrowth structure including a trench cavity, wherein the trench cavity includes a growth-blocking layer or patterned material supportive of a coalescent Pendeo layer thereon, on at least a portion of an inside surface of the trench. Such substrate is suitable for carrying out... Agent: Intellectual Property / Technology Law

20090152566 - Junction field-effect transistor: A junction field-effect transistor comprises an n-type semiconductor layer having a channel region, a buffer layer formed on the channel region and a p+ region formed on the buffer layer. The concentration of electrons in the buffer layer is lower than the concentration of electrons in the semiconductor layer. The... Agent: Fish & Richardson P.C.

20090152567 - Article including semiconductor nanocrystals: An article comprising an array of semiconductor nanocrystals arranged in a predetermined pattern, wherein the semiconductor nanocrystals are capable of generating light of one or more predetermined wavelengths in response to ambient light. In one embodiment the semiconductor nanocrystals emit light of different predetermined wavelengths.... Agent: Qd Vision, Inc.

20090152570 - Led chip package structure with high-efficiency light emission by rough surfaces and method of making the same: An LED chip package structure with high-efficiency light emission by rough surfaces includes a substrate unit, a light-emitting unit, and a package colloid unit. The substrate unit has a substrate body, and a positive electrode trace and a negative electrode trace respectively formed on the substrate body. The light-emitting unit... Agent: Rosenberg, Klein & Lee

20090152569 - Led module with reduced operating temperature: The present invention relates to a LED module with a reduced operating temperature. The LED module includes a substrate, a plurality of LED chips, a carrier and an encapsulant layer. These LED chips are disposed on the substrate and electrically connected to the substrate and are divided into a first... Agent: Kirton And Mcconkie

20090152568 - Method for packaging submount adhering light emitting diode and package structure thereof: A method for packaging submount adhering LED comprises providing a first substrate which has an upper surface, a lower surface forming a plurality of heat-dissipating cavities and a plurality of die-attaching regions defined on the upper surface. Each of the heat-dissipating cavities corresponds to the die-attaching region and has a... Agent: Troxell Law Office PLLC

20090152571 - Array type light-emitting device with high color rendering index: An array type light-emitting device with high color rendering index includes: a substrate, an array type light-emitting module, a plurality of wavelength-converting layers, and a plurality of transparent layers. The array type light-emitting module is composed of a plurality of light-emitting chip rows, and each light-emitting chip row has a... Agent: Rosenberg, Klein & Lee

20090152572 - Array type light-emitting device with high color rendering index: An array type light-emitting device includes a substrate, an array type light-emitting module, a wavelength-converting layer set, and a plurality of transparent layer sets. The array type light-emitting module is composed of a blue, a red, a green, a yellow and an amber light-emitting chip sets. The wavelength-converting layer set... Agent: Rosenberg, Klein & Lee

20090152574 - Multi-wavelength white light-emitting structure: A multi-wavelength white light-emitting structure uses a UV light emitting diode chip and a blue light emitting diode chip to excite a red phosphor and a green phosphor and generates a white light-emitting structure having good color rendering. The multi-wavelength white light-emitting structure uses a UV light emitting diode chip... Agent: Rosenberg, Klein & Lee

20090152573 - Textured encapsulant surface in led packages: A packaged LED device having a textured encapsulant that is conformal with a mount surface on which at least one LED chip is disposed. The textured encapsulant, which can be textured using an additive or subtractive process, is applied to the LED either prior to or during packaging. The encapsulant... Agent: Koppel, Patrick, Heybl & Dawson

20090152576 - Blue-green light-emitting semiconductor and phosphor for same: A blue-green light emitting semiconductor having an In—Ga—N heterostructure and covered with a light-converting layer formed of a thermosetting polymer layer and an inorganic phosphor having a long wave Stokes radiation displacement characteristic, characterized in that the In—Ga—N semiconductor heterostructure emits light in near ultraviolet region λ=375˜405 nm, the light-converting... Agent: The Weintraub Group, P.L.C

20090152577 - Light emitting diode and manufacturing method thereof: A light emitting diode comprises a substrate having a first surface and a second surface, a light emitting epitaxy structure placed on the first surface of the substrate, and a compound reflection layer placed on the second surface of the substrate. The second surface of the substrate further has a... Agent: Wpat, PC Intellectual Property Attorneys

20090152575 - Orange-yellow silicate phosphor and warm white semiconductor using same: A silicate phosphor prepared from Mg2Me+20.5Ln3Si2.5O12-2yN−3yF−1y, in which Me+2=Ca, Sr, Ba, Ln=Sc, Lu, Er, Ho, excited by one single ion or an ion pair of d, f-elements such as Ak+n=Cu+1, Ce+3, Eu+2, Ag+1, Mn+2. The phosphor has a cubic garnet architecture prepared by solid phase synthesis, and radiates at green,... Agent: The Weintraub Group, P.L.C

20090152578 - Iii-nitride semiconductor light emitting device: The present disclosure relates to a III-nitride semiconductor light emitting device which improves external quantum efficiency by using a p-type nitride semiconductor layer with a rough surface, the p-type nitride semiconductor layer including: a first nitride semiconductor layer with a first doping concentration, a second nitride semiconductor layer with a... Agent: Harness, Dickey, & Pierce, P.l.c

20090152580 - Light emitting device and method for manufacturing the same: A light-emitting chip includes a base, a transparent material layer and a light-emitting chip. The base has an upper surface including a conductive pattern. The transparent material layer is disposed on the upper surface of the base and has an opening part which is located on region at least part... Agent: Ditthavong Mori & Steiner, P.C.

20090152582 - Light emitting diode: A light emitting diode includes a reflective cup, an LED chip, and many electrodes, a first light scattering layer, and a phosphor layer. The reflective cup includes a bottom and a sidewall extending from the bottom. The LED chip is received in the reflective cup and mounted on the bottom... Agent: PCe Industry, Inc. Att. Steven Reiss

20090152581 - Light reflecting material, package for light emitting element accommodation, light emitting device and process for producing package for light emitting element accomodation: [Means for Solving Problems] There is provided a package for light emitting element accommodation comprising ceramic substrate (2) having conductor mounting region (8) for mounting of light emitting element (1) on its upper surface; frame (4) of a light reflecting material containing 74.6 mass % or more of alumina whose... Agent: Scully Scott Murphy & Presser, PC

20090152579 - Light-emitting diode and light-emitting diode lamp: The present invention provides a light-emitting diode (10) including a first conductive type silicon single crystal substrate (101), a light-emitting section (40) including a first pn junction structure composed of a III-group nitride semiconductor on the substrate, a first polarity ohmic electrode (107b) provided on the light-emitting section, and a... Agent: Sughrue Mion, PLLC

20090152583 - Light-emitting diode device and manufacturing method thereof: A light-emitting diode device includes an epitaxial layer, a current blocking layer and a current spreading layer. The current blocking layer is disposed on one side of the epitaxial layer and contacts with a portion of the epitaxial layer. The current spreading layer is disposed on one side of the... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090152584 - Light emitting device with bonded interface: In some embodiments of the invention, a transparent substrate AlInGaP device includes an etch stop layer that may be less absorbing than a conventional etch stop layer. In some embodiments of the invention, a transparent substrate AlInGaP device includes a bonded interface that may be configured to give a lower... Agent: Philips Intellectual Property & Standards

20090152585 - Gallium nitride-based compound semiconductor light-emitting device: It is an object of the present invention to provide a gallium nitride-based compound semiconductor light-emitting device that is excellent in light output efficiency and needs only a low driving voltage (Vf). The inventive gallium nitride-based compound semiconductor light-emitting device includes an n-type semiconductor layer, a light-emitting layer and a... Agent: Sughrue Mion, PLLC

20090152586 - Light emitting diode having active region of multi quantum well structure: Disclosed is a light emitting diode having an active region of a multi quantum well structure. The active region is positioned between GaN-based N-type and P-type compound semiconductor layers. At least one of barrier layers in the active region includes an undoped InGaN layer and a Si-doped GaN layer, and... Agent: H.c. Park & Associates, PLC

20090152587 - Deep guard regions for reducing latch-up in electronics devices: An embodiment of an integrated circuit includes a semiconductor layer, a well, first and second source/drain regions, and a guard region. The semiconductor layer has a first conductivity, and the well is disposed in the layer and has a second conductivity. The first source/drain region is formed in the well... Agent: Graybeal Jackson LLP

20090152588 - Esd protection device in high voltage and manufacturing method for the same: An ESD protection device comprises a substrate of a first conductive type; a transistor formed in the substrate having an input terminal of the first conductive type, a control terminal of a second conductive type, and a ground terminal of the first conductive type; and a diode formed in the... Agent: Birch Stewart Kolasch & Birch

20090152589 - Systems and methods to increase uniaxial compressive stress in tri-gate transistors: A transistor structure that increases uniaxial compressive stress on the channel region of a tri-gate transistor comprises at least two semiconductor bodies formed on a substrate, each semiconductor body having a pair of laterally opposite sidewalls and a top surface, a common source region formed on one end of the... Agent: Intel Corporation C/o Cpa Global

20090152590 - Method and structure for semiconductor devices with silicon-germanium deposits: A method of forming a semiconductor device including forming a second deposit of silicon-germanium on a first deposit of silicon-germanium, the first deposit formed in a conduction terminal region of a substrate of the semiconductor device and having a first percentage of germanium, and the second deposit having a second... Agent: Cantor Colburn LLP - IBM Fishkill

20090152591 - Design structure for an on-demand power supply current modification system for an integrated circuit: A design structure for a circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes and input/output element that selectively connects an input/output pin as a function of a power requirement or a signal bandwidth requirement of the integrated circuit. The input/output element... Agent: Downs Rachlin Martin PLLC

20090152592 - Structure for a latchup robust array i/o using through wafer via: A design structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD... Agent: Schmeiser, Olsen & Watts

20090152593 - Structure for a latchup robust gate array using through wafer via: A structure, method and a design structure for preventing latchup in a gate array. The design structure including: a NFET gate array and a PFET gate array in a substrate; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate... Agent: Schmeiser, Olsen & Watts

20090152594 - On-demand power supply current modification system and method for an integrated circuit: A circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes an input/output element that selectively connects an input/output pin as a function of a power requirement or a signal bandwidth requirement of the integrated circuit. The input/output element includes one or more... Agent: Downs Rachlin Martin PLLC

20090152595 - Semiconductor devices and method of testing same: There are provided a semiconductor device having a pattern which allows electric failures to be sensitively detected at high speeds, and a method of testing the same. In one embodiment, the semiconductor device comprises a pair of row wires including a plurality of first wires arranged in a first layer... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090152597 - Biosensor and method of manufacturing the same: Provided are a biosensor with a silicon nanowire and a method of manufacturing the same, and more particularly, a biosensor with a silicon nanowire including a defect region formed by irradiation of an electron beam, and a method of manufacturing the same. The biosensor includes: a silicon substrate; a source... Agent: Ampacc Law Group

20090152598 - Biosensor using silicon nanowire and method of manufacturing the same: Provided are a biosensor using a silicon nanowire and a method of manufacturing the same. The silicon nanowire can be formed to have a shape, in which identical patterns are continuously repeated, to enlarge an area in which probe molecules are fixed to the silicon nanowire, thereby increasing detection sensitivity.... Agent: Ampacc Law Group

20090152596 - Semiconductor fet sensor and method of fabricating the same: Provided are a semiconductor Field-Effect Transistor (FET) sensor and a method of fabricating the same. The method includes providing a semiconductor substrate, forming a sensor structure having a fin-shaped structure on the semiconductor substrate, injecting ions for electrical ohmic contact into the sensor structure, and depositing a metal electrode on... Agent: Ampacc Law Group

20090152600 - Process for removing ion-implanted photoresist: A method of manufacturing an IC that comprises fabricating a semiconductor device. Fabricating the device includes depositing a photoresist layer on a substrate surface and implanting one or more dopant species through openings in the photoresist layer into the substrate, and, into the photoresist layer, thereby forming an implanted photoresist... Agent: Texas Instruments Incorporated

20090152602 - Semiconductor device and method for manufacturing the same: m

20090152599 - Silicon germanium and polysilicon gate structure for strained silicon transistors: An integrated circuit semiconductor device, e.g., MOS, CMOS. The device has a semiconductor substrate. The device also has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. A dielectric layer forms sidewall spacers on edges of the gate structure. A recessed region is within... Agent: Townsend And Townsend And Crew, LLP

20090152601 - Strained nmos transistor featuring deep carbon doped regions and raised donor doped source and drain: Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.... Agent: Intel Corporation C/o Cpa Global

20090152603 - Image sensor and method for manufacturing the same: Embodiments relate to an image sensor that may include transistors, a first dielectric, a crystalline semiconductor layer on and/or over the first dielectric, a photodiode, a dummy region, via contacts, and a second dielectric. A photodiode may be formed by implanting impurity ions into a crystalline semiconductor layer to correspond... Agent: Sherr & Vaughn, PLLC

20090152605 - Image sensor and cmos image sensor: An image sensor includes a carrier generating portion having a photoelectric conversion function, a voltage conversion portion for converting signal charges to a voltage, a charge increasing portion for increasing carriers generated by the carrier generating portion and a light shielding film formed to cover at least one part of... Agent: Ditthavong Mori & Steiner, P.C.

20090152604 - System and method for sensing image on cmos: A system and method for sensing image on CMOS. According to an embodiment, the present invention provide a CMOS image sensing pixel. The pixel includes an n-type substrate, which includes a first width and a first thickness. The pixel also includes a p-type epitaxy layer overlying the n-type substrate. The... Agent: Townsend And Townsend And Crew, LLP

20090152607 - Ferroelectric stacked-layer structure, field effect transistor, and ferroelectric capacitor and fabrication methods thereof: A ferroelectric stacked-layer structure is fabricated by forming a first polycrystalline ferroelectric film on a polycrystalline or amorphous substrate, and after planarizing a surface of the first ferroelectric film, laminating on the first ferroelectric film a second thin ferroelectric film having the same crystalline structure as the first ferroelectric film.... Agent: Mcdermott Will & Emery LLP

20090152606 - Spin transistor using epitaxial ferromagnet-semiconductor junction: A spin transistor conducive to the miniaturization and large scale integration of devices, because a magnetization direction of a source and a drain is determined by a direction of the epitaxial growth of a ferromagnet. The spin transistor includes a semiconductor substrate having a channel layer formed thereinside; ferromagnetic source... Agent: Bradley Arant Boult Cummings LLP Intellectual Property Department

20090152608 - Dram cell transistor device and method: A method for forming a memory device. The method provides a protective layer overlying a surface region of a substrate before threshold voltage implant. The method then includes depositing a photo resist layer and patterning the photo resist by selectively removing a portion of the photo resist to expose the... Agent: Townsend And Townsend And Crew, LLP

20090152612 - High yield, high density on-chip capacitor design: A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native... Agent: Driggs, Hogg, Daugherty & Del Zoppo Co., L.p.a.

20090152611 - Semiconductor device and method for manufacturing the same: A semiconductor device comprises a first contact plug, a first structure and a second insulating layer, or comprises a first contact plug, a first structure, a protruding region and a second insulating layer. The first contact plug extends in a predetermined direction and including a step converting a cross section... Agent: Young & Thompson

20090152609 - Semiconductor integrated circuit device: A semiconductor integrated circuit device which is formed on an area comprises a first storage node which is formed on a first area having a first conductive type of the area, the first storage node having a first level, a second storage node which is formed on a second area... Agent: Foley And Lardner LLP Suite 500

20090152610 - Semiconductor memory device: This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090152613 - Semiconductor memory device having a floating body capacitor and method of manufacturing the same: A semiconductor memory device having a floating body capacitor. The semiconductor memory device can perform a memory operation using the floating body capacitor. The semiconductor memory device includes an SOI substrate having a staked structure in which a base substrate having a conducting surface, a buried insulating layer and a... Agent: Baker & Mckenzie LLP Patent Department

20090152614 - Nand flash memory device having a contact for controlling a well potential: A NAND flash memory device includes a plurality of active regions extending in a first direction on a substrate, the active regions including a first well of a first conductivity, a plurality of word lines extending on the first well in a second direction perpendicular to the first direction, first... Agent: Lee & Morse, P.C.

20090152615 - Semiconductor device and method for manufacturing the same: Embodiments relate to a semiconductor device that may include a floating gate, an inter poly dielectric formed on and/or over both sides of the floating gate in a bit line direction and on and/or over both side of the floating gate in a word line direction, and a control gate... Agent: Sherr & Vaughn, PLLC

20090152616 - Semiconductor device and method for manufacturing the same: Disclosed are a semiconductor device and a method for manufacturing the same. The method includes forming a gate layer on a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; forming a second oxide layer on the first oxide layer; exposing the first oxide layer by removing the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090152620 - Atomic layer deposition of gdsco3 films as gate dielectrics: The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of gadolinium oxide (Gd2O3) and scandium oxide (Sc2O3) acting as a single dielectric layer with a formula of GdScO3, and a method of fabricating such a dielectric layer, is described that produces a reliable structure with a high... Agent: Schwegman, Lundberg & Woessner/micron

20090152617 - Hetero-structure variable silicon richness nitride for mlc flash memory device: Charge storage stacks containing hetero-structure variable silicon richness nitride for memory cells and methods for making the charge storage stacks are provided. The charge storage stack can contain a first insulating layer on a semiconductor substrate; n charge storage layers comprising silicon-rich silicon nitride on the first insulating layer, wherein... Agent: Amin, Turocy & Calvin, LLP

20090152618 - Nonvolatile semiconductor memory device and method of fabricating the same: A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, a control electrode formed on the second insulation layer. The second insulation... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090152619 - Semiconductor device and manufacturing method of semiconductor device: Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power... Agent: Miles & Stockbridge PC

20090152621 - Nonvolatile charge trap memory device having a high dielectric constant blocking region: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source and drain regions. A gate stack is above the substrate over the channel region and between the pair of source and drain regions. The gate stack includes a... Agent: Cypress Semiconductor Corporation

20090152622 - Semiconductor device: A semiconductor device includes a first semiconductor region having a channel region, and containing silicon as a main component, second semiconductor regions sandwiching the first semiconductor region, formed of SiGe, and applying stress to the first semiconductor region, cap layers provided on the second semiconductor regions, and formed of silicon... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090152623 - Fin transistor: A fin transistor includes: a substrate; a plurality of semiconductor fins formed on the substrate; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress source for the semiconductor fins included in a region of the gate electrode and the region provided between... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090152624 - Integrated circuit device with a semiconductor body and method for the production of an integrated circuit device: An integrated circuit device with a semiconductor body and a method for the production of a semiconductor device a provided. The semiconductor body comprises a cell field with a drift zone of a first conduction type. In addition, the semiconductor device comprises an edge region surrounding the cell field. Field... Agent: Dicke, Billig & Czaja

20090152625 - Recessed channel transistor: A recessed channel transistor includes a single crystalline silicon substrate having a recessed portion, a bottom surface of the recessed portion including an elevated central portion, a channel doping region in the single crystalline silicon substrate, the channel doping region being under the bottom surface of the recessed portion, a... Agent: Lee & Morse, P.C.

20090152626 - Super halo formation using a reverse flow for halo implants: Shrinking dimensions of MOS transistors in integrated circuits requires tighter distributions of dopants in pocket regions from halo ion implant processes. In conventional fabrication process sequences, halo dopant distributions spread during source/drain anneals. The instant invention is a method of fabricating MOS transistors in an integrated circuit in which halo... Agent: Texas Instruments Incorporated

20090152627 - Semiconductor device: This invention is directed to offer a MOS transistor that has a high source-drain breakdown BVds, a low on resistance and a high electric current driving capacity. On resistance is lowered by forming an N well layer for lowering on resistance in the drift region. The N well layer is... Agent: Morrison & Foerster LLP

20090152628 - Semiconductor device and manufacturing method of the same: It is desirable to reduce chip area, lower on resistance and improve electric current driving capacity of a DMOS transistor in a semiconductor device with a DMOS transistor. On the surface of an N type epitaxial layer, a P+W layer of the opposite conductivity type (P type) is disposed and... Agent: Morrison & Foerster LLP

20090152629 - Methods of selectively oxidizing semiconductor structures, and structures resulting therefrom: Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ion beam including an oxidizing matter. Utilizing... Agent: Trask Britt, P.C./ Micron Technology

20090152631 - Semiconductor device and method for forming the same: A thin film transistor device reduced substantially in resistance between the source and the drain by incorporating a silicide film, which is fabricated by a process comprising forming a gate insulator film and a gate contact on a silicon substrate, anodically oxidizing the gate contact, covering an exposed surface of... Agent: Nixon Peabody, LLP

20090152630 - Semiconductor device using soi-substrate: According to a feature of the present invention, a semiconductor device includes a SOI substrate, including a semiconductor substrate; an insulating layer formed on the semiconductor substrate and a silicon layer formed on the insulating layer. A drain region and a source region are formed in the silicon layer so... Agent: Rabin & Berdo, PC

20090152632 - Latchup robust array i/o using through wafer via: A structure and a method for preventing latchup. The structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate... Agent: Schmeiser, Olsen & Watts

20090152633 - Semiconductor device: In a semiconductor device including, between an external connection terminal and an internal circuit region, an NMOS transistor for ESD protection having a gate potential fixed to a ground potential, the external connection terminal is formed above a drain region of the NMOS transistor for ESD protection, and the drain... Agent: Bruce L. Adams, Esq Adams & Wilks

20090152634 - Method of forming a semiconductor device and semiconductor device: A method of forming a semiconductor device comprises forming a control electrode over a portion of a semiconductor layer, forming recesses extending into the semiconductor layer on opposing sides of the control electrode, and forming doped regions in the semiconductor layer through the recesses. The doped regions form current electrode... Agent: Freescale Semiconductor, Inc. Law Department

20090152635 - Thin film transistor and method for manufacturing a display panel: Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer,... Agent: Haynes And Boone, LLPIPSection

20090152638 - Dual oxide stress liner: A transistor structure includes a first type of transistor (e.g., P-type) positioned in a first area of the substrate, and a second type of transistor (e.g., N-type) positioned in a second area of the substrate. A first type of stressing layer (compressive conformal nitride) is positioned above the first type... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090152636 - High-k/metal gate stack using capping layer methods, ic and related transistors: Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor... Agent: Hoffman Warnick LLC

20090152639 - Laminated stress overlayer using in-situ multiple plasma treatments for transistor improvement: Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than... Agent: Texas Instruments Incorporated

20090152637 - Pfet with tailored dielectric and related methods and integrated circuit: A PFET having tailored dielectric constituted in part by an NFET threshold voltage (Vt) work function tuning layer in a gate stack thereof, related methods and integrated circuit are disclosed. In one embodiment, the PFET includes an n-type doped silicon well (N-well), a gate stack including: a doped band engineered... Agent: Hoffman Warnick LLC

20090152642 - Selective implementation of barrier layers to achieve threshold voltage control in cmos device fabrication with high-k dielectrics: The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top... Agent: Scully, Scott, Murphy & Presser, P.C.

20090152640 - Semiconductor device and manufacturing process therefor: This invention provides a semiconductor device that can prevent a deviation of work function by adopting a gate electrode having a uniform composition and exhibits excellent operating characteristics by virtue of effective control of a Vth. The semiconductor device is characterized by comprising a PMOS transistor, an NMOS transistor, a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090152641 - Semiconductor memory device and method for manufacturing: A semiconductor memory device includes: a first n-type transistor; a first p-type transistor; a first wiring layer having a first interconnecting portion for connecting a drain of the first n-type transistor and a drain of the first p-type transistor; and a second wiring layer having a first conductive portion electrically... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090152643 - Semiconductor structures: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a first metal-oxide-semiconductor (MOS), a second MOS, a first semiconductor region, and a second semiconductor region. The first and the second MOSs are formed on the substrate. The first semiconductor region is formed between the substrate and the first... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090152644 - Semiconductor device and a method of manufacturing the same: A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide... Agent: Miles & Stockbridge PC

20090152645 - Methods for isolating portions of a loop of pitch-multiplied material and related structures: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a... Agent: Knobbe Martens Olson & Bear LLP

20090152647 - Field-effect transistor including localized halo ion regions, and semiconductor memory, memory card, and system including the same: A field-effect transistor including localized halo ion regions that can optimize HEIP characteristics and GIDL characteristics. The field-effect transistor includes a substrate, an active region, a gate structure, and halo ion regions. The active region includes source/drain regions and a channel region formed at a partial region in the substrate.... Agent: Marger Johnson & Mccollom, P.C.

20090152648 - Semiconductor device and method of fabricating the same: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a gate electrode that includes a body part disposed on the semiconductor substrate and a projecting part projecting downward from the body part; and source/drain regions at opposite sides of the gate electrode.... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090152646 - Structure and method for manufacturing device with planar halo profile: A semiconductor device and method for manufacturing the device with a planar halo profile is provided. The semiconductor device can be a MOSFET. The method of forming the structure includes forming an angled spacer adjacent a gate structure and implanting a halo implant at an angle to form a halo... Agent: Greenblum & Bernstein, P.L.C

20090152649 - Semiconductor device of multi-finger type: Provided is a semiconductor device of a multi-finger type. The semiconductor device comprises an active region, a guard ring, a source electrode, at least one gate electrode, and at least one drain electrode. The active region includes a source region, a drain region, and a channel region. The guard ring... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090152650 - High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods: A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an... Agent: Hoffman Warnick LLC

20090152651 - Gate stack structure with oxygen gettering layer: A transistor has a channel region in a substrate and source and drain regions in the substrate on opposite sides of the channel region. A gate stack is formed on the substrate above the channel region. This gate stack comprises an interface layer contacting the channel region of the substrate,... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090152652 - Method of manufacturing semiconductor device and the semiconductor device: Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090152654 - Micromechanical system: A micromechanical system includes a substrate, a first planar electrode, a second planar electrode, and a third planar electrode. The second planar electrode is movably positioned at a distance above the first planar electrode and the third planar electrode is positioned at a distance above the second electrode.... Agent: Kenyon & Kenyon LLP

20090152653 - Surface mount multi-axis electronics package for micro-electrical mechanical systems(mems) devices: A surface mount multi-axis cavity package for micro-electrical mechanical systems (MEMS) devices includes a substantially cubical housing having a plurality of sides and at least one internal cavity. A first plurality of solder pads are positioned on at least one side of the housing and a second plurality of solder... Agent: Delphi Technologies, Inc.

20090152655 - Mems device: A method of fabricating a micro-electrical-mechanical system (MEMS) apparatus on a substrate (10) comprises the steps of processing the substrate (10) so as to fabricate an electronic circuit (11); depositing a first electrode (15) that is operably coupled with the electronic circuit (11); depositing a membrane (16) so that it... Agent: Dickstein Shapiro LLP

20090152656 - Sensor device and production method therefor: A compact sensor device having stable sensor characteristics and the production method are provided. The sensor device is formed with a sensor substrate and a pair of package substrates bonded to both surface of the sensor substrate. The sensor substrate has a frame with an opening, a movable portion held... Agent: Cheng Law Group, PLLC

20090152657 - Magnetic field detector: Disclosed is a magnetic field detector having various structures that can be used as a high-density magnetic biosensor. An embodiment of the invention provides a magnetic field detector using a thin film for detecting magnetic beads. The magnetic field detector includes: a substrate; a magnetoresistive element that is formed on... Agent: Ladas & Parry LLP

20090152661 - Image sensor and method for manufacturing the same: A method for manufacturing the image sensor includes: forming a photoresist layer on a surface of an image sensor; exposing and developing the photoresist layer using a mask used for fabricating a plurality of micro-lenses, which has a number of first light shielding patterns aligned apart from one another and... Agent: Sherr & Vaughn, PLLC

20090152658 - Methods of packaging imager devices and optics modules, and resulting assemblies: A method of packaging imager devices and optics modules is disclosed which includes positioning an imager device and an optics module in each of a plurality of openings in a carrier body, introducing an encapsulant material into each of the openings in the carrier body and cutting the carrier body... Agent: Perkins Coie LLP Patent-sea

20090152660 - Photomask, image sensor, and method of manufacturing the image sensor: Provided are a photomask, an image sensor, and a method of manufacturing the image sensor. The image sensor can include photodiode structures, color filters, a planarization layer, and microlenses. The photodiode structures can be disposed on a semiconductor substrate according to unit pixel. The color filters can be disposed on... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090152659 - Reflowable camera module with improved reliability of solder connections: A reflowable camera module has a set of solder joints formed on a bottom surface of the camera module that provide electrical signal and power connections between the camera module and a printed circuit substrate. The solder joints are susceptible to failure caused by shear forces, particularly in corner regions.... Agent: Curtis A. Vock Lathrop & Gage LLP

20090152662 - Micro-sensor and manufacturing method thereof: The micro-sensor for a micro image pick-up device includes a flexible circuit board and a circuit substrate. The flexible circuit board has an opening exposing an end of a plurality of metal wires. An image sensing device that electrically connected to a plurality of printed wires disposed on the circuit... Agent: Stevens & Showalter LLP

20090152663 - Perforated silicon plate assembly for forming and transferring of silicon thin film solar cells: A perforated monocrystalline silicon plate assembly is provided for forming and transferring of monocrystalline silicon thin film solar cells. The assembly comprises a perforated monocrystalline silicon plate with a plurality of through holes and obstructive holes. The assembly is allowed to grow a first p-type epitaxial layer with an inverted... Agent: Bruce H. Johnsonbaugh Eckhoff & Hoppe

20090152664 - Materials, systems and methods for optoelectronic devices: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically... Agent: Courtney Staniford & Gregory LLP

20090152665 - Fabricating methods of photoelectric devices and package structures thereof: The invention discloses a method for fabricating a photoelectric device. A ceramic substrate is first provided, and then a first patterned electrode and a second patterned electrode are formed on and underneath the surface of the ceramic substrate. A plurality of photoelectric devices is sequentially connected to the first electrode... Agent: Wpat, PC Intellectual Property Attorneys

20090152666 - Thermoelectric semiconductor device: A thermoelectric semiconductor device includes a plurality of alternating P-type and N-type semiconductor elements disposed between first and second ceramic layers, first conductor elements attached to the first ceramic layer and interconnecting cold junctions of the P-type and N-type semiconductor elements, and second conductor elements attached to the second ceramic... Agent: Trop, Pruner & Hu, P.C.

20090152667 - Semiconductor with active component and method for manufacture: A semiconductor with active component and method for manufacture. One embodiment provides a semiconductor component arrangement having an active semiconductor component and a semiconductor body having a first semiconductor zone, a third semiconductor zone, and also a drift zone arranged between the first semiconductor zone and the third semiconductor zone.... Agent: Dicke, Billig & Czaja

20090152668 - Semiconductor apparatus: A semiconductor apparatus is disclosed. The semiconductor apparatus includes an SOI substrate including an active layer, a buried insulation film and a support substrate; a low potential reference circuit part located in the active layer and operable at a first reference potential; a high potential reference circuit part located in... Agent: Posz Law Group, PLC

20090152671 - Method for manufacturing simox wafer and simox wafer: This method for manufacturing a SIMOX wafer includes: heating a silicon wafer to 300° C. or more and implanting oxygen ions so as to form a high oxygen concentration layer within the silicon wafer; subjecting the silicon wafer to a cooling to less than 300° C. and an implanting of... Agent: Kolisch Hartwell, P.C.

20090152670 - Semiconductor device and method of fabricating the same: A semiconductor device and a method of fabricating the same includes a semiconductor substrate including a first trench; an epitaxial layer disposed on and/or over the semiconductor substrate and including a second trench connected to the first trench; a first insulator disposed in the first trench; and a second insulator... Agent: Sherr & Vaughn, PLLC

20090152672 - Semiconductor devices and methods of manufacture thereof: Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece having a plurality of trenches formed therein, forming a liner over the workpiece, and forming a layer of photosensitive material over the liner. The layer... Agent: Slater & Matsil LLP

20090152669 - Si trench between bitline hdp for bvdss improvement: Memory devices having improved BVdss characteristics and methods of making the memory devices are provided. The memory devices contain bitline dielectrics on bitlines of a semiconductor substrate; first spacers adjacent the side surfaces of the bitline dielectrics and on the upper surface of the semiconductor substrate; a trench in the... Agent: Amin, Turocy & Calvin, LLP

20090152673 - Semiconductor device and method for forming the same: Provided is a semiconductor and a method for forming the same. The method includes forming a buried insulating layer locally in a substrate. The substrate is etched to form an opening exposing the buried insulating layer, and a silicon pattern spaced in at least one direction from the substrate is... Agent: Ampacc Law Group

20090152676 - Electronic device including an inductor: An electronic device can include an inductor overlying a shock-absorbing layer. In one aspect, the electronic device can include a substrate, an interconnect level overlying the substrate, and the shock-absorbing layer overlying the interconnect level. The inductor can include conductive traces and looped wires. The conductive traces can be attached... Agent: Larson Newman Abel & Polansky, LLP

20090152675 - Inductor of semiconductor device and method for manufacturing the same: In a semiconductor device having a first region formed with the inductor and a second region formed with transistors, the inductor includes a deep well region formed in the silicon substrate beneath the first and second regions, a well region formed on the deep well region in the second region,... Agent: Sherr & Vaughn, PLLC

20090152674 - Semiconductor device: A semiconductor device contains a semiconductor substrate, an insulating film formed on the semiconductor substrate, an inductor formed over the semiconductor substrate while placing a portion of the insulating film in between, and a guard ring surrounding the inductor in a plan view, and isolating the inductor from other regions,... Agent: Mcginn Intellectual Property Law Group, PLLC

20090152678 - Capacitor of semiconductor device and method for manufacturing the same: A capacitor includes a first lower metal layer and an insulating layer on a lower interlayer dielectric layer of a semiconductor substrate; a first upper metal layer aligned on the insulating layer to partially expose it; a first capping layer and an upper interlayer dielectric layer on the insulating layer... Agent: Sherr & Vaughn, PLLC

20090152677 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device including: a conducting plug provided in an interlayer insulating film over a semiconductor substrate; and a capacitor including a lower electrode provided over the conducting plug, the lower electrode being connected to the conducting plug, a dielectric film provided on the lower electrode, and an upper electrode... Agent: Mcginn Intellectual Property Law Group, PLLC

20090152679 - Semiconductor device: A metal electrode is disposed on each of a plurality of resistor groups which are made of polycrystalline silicon resistors and constitute a resistor circuit. The metal electrode is connected to an end of the resistor via another interconnecting layer. Accordingly, the external influence which the metal electrode receives during... Agent: Brinks Hofer Gilson & Lione

20090152680 - Electrostatic discharge protection for bipolar semiconductor circuitry: Multiple emitter-base regions arc formed on a single contiguous collector. The multiple emitter-base regions are cascoded such that the base of one emitter-base region is directly wired to the emitter of an adjacent emitter-base region. An electrostatic discharge (ESD) protection unit, comprising a single collector and multiple emitter-base regions, provides... Agent: Scully, Scott, Murphy & Presser, P.C.

20090152681 - Nano-multiplication region avalanche photodiodes and arrays: An avalanche photodiode with a nano-scale reach-through structure comprising n-doped and p-doped regions, formed on a silicon island on an insulator, so that the avalanche photodiode may be electrically isolated from other circuitry on other silicon islands on the same silicon chip as the avalanche photodiode. For some embodiments, multiplied... Agent: Seth Z. Kalson C/o Cpa Global

20090152682 - Line element and method of manufacturing line element: An element capable of manufacturing various devices of any shape having plasticity or flexibility without being limited by shape and a method for manufacturing thereof are provided. An element characterized by that a circuit element is formed continuously or intermittently in the longitudinal direction. An element characterized by that a... Agent: Young & Thompson

20090152683 - Rounded die configuration for stress minimization and enhanced thermo-mechanical reliability: One aspect of the invention pertains to a semiconductor die with rounded sidewall junction edge corners. Such rounding reduces stress accumulations at those corners. In other embodiments of the invention, the sharpness of other corners and edges in the die are reduced. For example, reducing the sharpness of the bottom... Agent: Beyer Law Group LLP/ Nsc

20090152684 - Manufacture-friendly buffer layer for ferroelectric media: The present invention describes a method including: providing a substrate; forming a buffer layer epitaxially over the substrate with a manufacture-friendly process; forming a bottom electrode epitaxially over the buffer layer; and forming a ferroelectric layer epitaxially over the bottom electrode.... Agent: Intel Corporation C/o Cpa Global

20090152685 - Epitaxial wafer and method of producing the same: An epitaxial wafer comprises a silicon substrate, a gettering epitaxial film formed thereon and containing silicon and carbon, and a main silicon epitaxial film formed on the gettering epitaxial film, in which the gettering epitaxial film has a given carbon atom concentration and carbon atoms are existent between its silicon... Agent: Sughrue Mion, PLLC

20090152686 - Film forming method for dielectric film: The present invention is a film forming method for an SiOCH film, comprising a unit-film-forming step including: a deposition step of depositing an SiOCH film element by using an organic silicon compound as a raw material and by using a plasma CVD method; and a hydrogen plasma processing step of... Agent: Smith, Gambrell & Russell

20090152687 - Method of opening pad in semiconductor device: A method of opening a pad in a semiconductor device. A protective film on a pad may be etched with a pad opening pattern as a mask. Dielectric heating may be performed on the pad opened by etching the protective film. Organic material containing C and F groups on the... Agent: Sherr & Vaughn, PLLC

20090152688 - Integrated circuit package system for shielding electromagnetic interference: An integrated circuit package system comprising: providing a substrate; coupling an integrated circuit to the substrate; mounting a shielding element around the integrated circuit; applying a conductive shielding layer on the shielding element; and coupling a system interconnect to the shielding element.... Agent: Law Offices Of Mikio Ishimaru

20090152689 - Integrated circuit package for high-speed signals: An integrated circuit package having a multi-segment transmission line transformer for impedance matching a packaged integrated circuit, such as a driver or receiver, to a printed circuit board (PCB) transmission line to which the packaged chip is attached by, for example, solder balls. In one exemplary embodiment, a three-segment transmission... Agent: Ip Legal Services

20090152690 - Semiconductor chip substrate with multi-capacitor footprint: Various methods and apparatus for coupling capacitors to a chip substrate are disclosed. In one aspect, a method of manufacturing is provided that includes forming a mask on a semiconductor chip substrate that has plural conductor pads. The mask has plural openings that expose selected portions of the plural conductor... Agent: Timothy M Honeycutt Attorney At Law

20090152691 - Leadframe having die attach pad with delamination and crack-arresting features: One aspect of the invention pertains to a semiconductor package having a die and a die attach pad with a plurality of spaced apart pedestals supported by a web. A die is mounted on the die attach pad such that the die is supported by at least a plurality of... Agent: Beyer Law Group LLP/ Nsc

20090152692 - Integrated circuit package system with offset stacking: An integrated circuit package system includes: providing an interposer having a bond pad and a contact pad; mounting the interposer in an offset location over a carrier with an exposed side of the interposer coplanar with an edge of the carrier; connecting an electrical interconnect between bond pad and the... Agent: Law Offices Of Mikio Ishimaru

20090152693 - Semiconductor device: A semiconductor device includes a wiring board having: plural stacked insulating layers; test pads and external connection pads which are disposed on a face of the plural stacked insulating layers located on the side opposite to that where another wiring board is connected; first wiring patterns which electrically connect internal... Agent: Rankin, Hill & Clark LLP

20090152694 - Electronic device: Embodiments provide an electronic device. The electronic device includes a leadframe having a first face that defines an island and multiple leads configured to communicate with a chip attached to the island, a first structure element separate from and coupled to a first face of the leadframe, at least one... Agent: Dicke, Billig & Czaja

20090152695 - Semiconductor component and method of manufacture: A semiconductor component having a semiconductor chip mounted on a packaging substrate and a method for manufacturing the semiconductor component that uses batch processing steps for fabricating the packaging substrate. A heatsink is formed using an injection molding process. The heatsink has a front surface for mating with a semiconductor... Agent: Hvvi Semiconductors, Inc.

20090152696 - Semiconductor device: A semi-conductor device (100) comprises an exposed leadframe (10) with a die pad (11) and a plurality of leads (12). The die pad (11) has a substantially flat bottom surface (14) and a top surface (15). A semi-conductor die (2) is attached to a die attachment portion (31) of the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090152697 - Semiconductor device and manufacturing method of the same: The bonding time of a metallic ribbon is shortened in the semiconductor device which connects a lead frame with the bonding pad of a semiconductor chip with a metallic ribbon. The bottom of the wedge tool is divided into two by the V-groove at the first branch and the second... Agent: Miles & Stockbridge PC

20090152698 - Integrated matching networks and rf devices that include an integrated matching network: An integrated matching network includes a first die on a substrate, a second die on the substrate, and a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20090152699 - Packaging apparatus of terahertz device: There is provided a packaging apparatus of a terahertz device, the apparatus including: a terahertz device having an active region at which terahertz wave is radiated or detected; a device substrate mounting the terahertz device whose active region is positioned at an opening region formed at the center of the... Agent: Rabin & Berdo, PC

20090152702 - Coupling wire to semiconductor region: A first device has a surface and includes a micrometer-scale or smaller geometry doped semiconductor region extending along the surface. A second device has a surface opposite the surface of the first device and includes a micrometer-scale or smaller wire extending through the second device to a position in proximity... Agent: Hewlett Packard Company

20090152701 - Integrated circuit package system with package integration: An integrated circuit package system comprising: providing a package substrate; attaching a base package having a portion of the base package substantially exposed over the package substrate; forming a cavity through the package substrate to the base package; and attaching a device partially in the cavity and connected to the... Agent: Law Offices Of Mikio Ishimaru

20090152704 - Integrated circuit packaging system with interposer: An integrated circuit packaging system is provided including forming an interposer having a coupling slot, securing an upper die on the interposer, mounting the interposer over an integrated circuit, and coupling the integrated circuit to the upper die through the coupling slot.... Agent: Law Offices Of Mikio Ishimaru

20090152700 - Mountable integrated circuit package system with mountable integrated circuit die: A mountable integrated circuit package system includes: mounting an integrated circuit die over a package carrier; connecting a first internal interconnect between the integrated circuit die and the package carrier; and forming a package encapsulation over the package carrier and the first internal interconnect, with the integrated circuit die partially... Agent: Law Offices Of Mikio Ishimaru

20090152703 - Semiconductor components having through interconnects and backside redistribution conductors: A semiconductor component includes a semiconductor substrate having a circuit side with integrated circuits and substrate contacts and a back side, a plurality of through interconnects in the substrate, and redistribution conductors on the back side of the substrate. Each through interconnect includes a via aligned with a substrate contact,... Agent: Stephen A Gratton The Law Office Of Steve Gratton

20090152706 - Integrated circuit package system with interconnect lock: An integrated circuit package system includes: mounting a device structure over a package carrier; connecting an internal interconnect between the device structure and the package carrier; forming an interconnect lock over the internal interconnect over the device structure with interconnect lock exposing the device structure; and forming a package encapsulation... Agent: Law Offices Of Mikio Ishimaru

20090152707 - Methods and systems for packaging integrated circuits: Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto... Agent: Beyer Law Group LLP/ Nsc

20090152705 - Micromechanical component and method for fabricating a micromechanical component: A method for fabricating a microelectromechanical or microoptoelectromechanical component. The method includes producing first and second layer composites. The first has a first substrate and a first insulation layer, which covers at least one part of the surface of the first substrate, while the second has a second substrate and... Agent: Elliott N. Kramsky

20090152710 - Quad flat no-lead (qfn) packages: Quad Flat No-Lead (QFN) packages are provided. An embodiment of a QFN package includes a semiconductor chip including an active surface and an inactive surface, a plurality of leads, a plurality of wire bonds configured to couple the plurality of leads to the semiconductor chip, and a mold material including... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20090152709 - Semiconductor device: A semiconductor device with semiconductor chips stacked thereon is provided. The semiconductor device is reduced in size and thickness. In a first memory chip and a second memory chip, first pads of the first memory chip located at a lower stage and hidden by the second memory chip located at... Agent: Miles & Stockbridge PC

20090152708 - Substrate for high speed semiconductor package and semiconductor package having the same: The substrate for a semiconductor package includes a substrate body having a first surface and a second surface opposite to the first surface. Connection pads are formed near an edge of the first surface. Signal lines having conductive vias and first, second, and third line parts are formed. The first... Agent: Ladas & Parry LLP

20090152711 - Rectification chip terminal structure: The present invention includes a base, a rectification chip, a conductive element and a coupling collar. The base has an installation pedestal to hold the rectification chip surrounded by an insulation portion. The conductive element has a root portion to connect the rectification chip. The root portion is extended to... Agent: Joe Mckinney Muncy

20090152712 - Packaging apparatus for optical-electronic semiconductors and a packaging method therefor: A packaging apparatus for optical-semiconductors includes a mold base having a longitudinal receiving space, an encapsulating module attached to the mold base, and a fixing member attached to the encapsulating module. The bottom of the mold base has at least one air-vent and the mold base has a predetermined width.... Agent: Rosenberg, Klein & Lee

20090152713 - Integrated circuit assembly including thermal interface material comprised of oil or wax: Embodiments of a thermal interface material layer comprised of an oil or a wax are disclosed. The thermal interface material may be used to thermally couple an integrated circuit die to a thermal component, such as a heat spreader. Other embodiments are described and claimed.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090152714 - Semiconductor device and method for manufacturing the same: An electronic device includes: a substrate having first and second surfaces, wherein the first surface is opposite to the second surface; a first electronic element mounted on the first surface of the substrate; a second electronic element mounted on the second surface of the substrate; and a resin mold sealing... Agent: Posz Law Group, PLC

20090152715 - Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer: A semiconductor device is made by first forming a protective layer over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier... Agent: Quarles & Brady LLP

20090152716 - Wiring substrate and electronic component mounting structure: A wiring substrate on which an electronic component is flip-chip bonded, including a substrate main body, a solder resist which is formed on the substrate main body and having an opening, and a plurality of conductive pattern formed on the substrate main body, including exposure surfaces exposed from the opening... Agent: Rankin, Hill & Clark LLP

20090152717 - Method of forming stacked die package: A method of packaging semiconductor integrated circuits, including the steps of providing a transfer film and forming a patterned, conductive layer on a surface of the transfer film. A first semiconductor integrated circuit (IC) then is attached to the transfer film, where an active side of the first IC is... Agent: Freescale Semiconductor, Inc. Law Department

20090152719 - Methods of fluxless micro-piercing of solder balls, and resulting devices: A method is disclosed which includes forming a layer of conductive material above a substrate, forming a masking layer above the layer of conductive material, performing a first etching process on the layer of conductive material with the masking layer in place, removing the masking layer and, after removing the... Agent: Perkins Coie LLP Patent-sea

20090152720 - Multilayer chip scale package: A resin coated copper foil is used to fabricate a multilayer Chip Scale Package (CSP). A CSP package base has a first electrical routing layer. A resin coated copper foil is hot pressed onto the CSP package base and then patterned to form a second electrical routing layer. Conductive vias... Agent: Curtis A. Vock Lathrop & Gage LLP

20090152721 - Semiconductor package and method for making the same: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, a second metal layer and a third metal layer. The substrate has a surface having at least... Agent: Volentine & Whitt PLLC

20090152718 - Structure with die pad pattern: A structure includes a semiconductor die that has an arrangement of die pads on a surface of the semiconductor die. A first row of die pads consists of a first group of four die pads and run in a first direction. A second row of die pads are adjacent to... Agent: Freescale Semiconductor, Inc. Law Department

20090152722 - Synergy effect of alloying materials in interconnect structures: A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of... Agent: Slater & Matsil, L.L.P.

20090152724 - Ic interconnect for high current: IC interconnect for high current device, design structure thereof and method are disclosed. One embodiment of the IC interconnect includes a first via positioned in a dielectric and coupled to a high current device at one end; a buffer metal segment positioned in a dielectric and coupled to the first... Agent: Hoffman Warnick LLC

20090152723 - Interconnect structure and method of making same: An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap... Agent: Greenblum & Bernstein, P.L.C

20090152726 - Metal line of semiconductor device and method for fabricating the same: A metal line includes a lower metal line pattern having a first width formed over the dielectric pattern and an upper metal line pattern formed over and contacting the lower metal line pattern such that the upper metal line pattern has a second width less than the first width.... Agent: Sherr & Vaughn, PLLC

20090152725 - Thick metal interconnect with metal pad caps at selective sites and process for making the same: The present invention relates to a high power IC (Integrated Circuit) semiconductor device and process for making same. More particularly, the invention encompasses a high conductivity or low resistance metal stack to reduce the device R-on which is stable at high temperatures while in contact with a thick aluminum wire-bond... Agent: Ahsan & Associates

20090152727 - Bonding pad for anti-peeling property and method for fabricating the same: A bonding pad includes a conductive layer formed over an insulation layer, and a dummy pattern penetrating the insulation layer and stuck in the conductive layer, wherein a bonding process is performed.... Agent: Lowe Hauptman Ham & Berner, LLP

20090152728 - Semiconductor apparatus: A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each... Agent: Cantor Colburn, LLP

20090152729 - Semiconductor device: An improved reliability of a junction region between a bonding wire and an electrode pad in an operation at higher temperature is presented. A semiconductor device includes a semiconductor chip provided on a lead frame, which are encapsulated with an encapsulating resin. Lead frames are provided in both sides of... Agent: Foley And Lardner LLP Suite 500

20090152733 - Deep contacts of integrated electronic devices based on regions implanted through trenches: An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and has a surface. The contact region is contiguous... Agent: Graybeal Jackson LLP

20090152730 - Interconnected structure for tft-array substrate: An exemplary interconnected structure for transferring a voltage signal to a thin film transistor (TFT) array substrate includes a first metal layer (310), a second metal layer (320) isolated from the first metal layer and a conductive layer (340) isolated from the second metal layer. The first metal layer is... Agent: Wei Te Chung Foxconn International, Inc.

20090152732 - Semiconductor device and method of manufacturing the same: By covering inner surfaces of a wiring groove 26c and a via hole 27a with a fourth insulation film 25 containing porogen during a manufacturing process of a semiconductor device, an increase in the relative permittivity of the fourth insulation film 25 that is a low-permittivity film on the inner... Agent: Steptoe & Johnson LLP

20090152731 - Semiconductor package: In a semiconductor package, at least two of connection pads are formed into different-shape pads which are different in planar shape from other connection pads, and one different-shape pad and another different-shape pad are disposed in a manner that, when the position of the one different-shape pad is rotated about... Agent: Rankin, Hill & Clark LLP

20090152737 - Memory devices having contact features: Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In... Agent: Fletcher Yoder (micron Technology, Inc.)

20090152735 - Metal interconnection and method for manufacturing the same in a semiconductor device: Provided is a method for manufacturing a metal interconnection in a semiconductor device. The semiconductor device fabricated according to one embodiment comprises a copper interconnection having reduced sheet and contact resistance. In the method for manufacturing the copper interconnection, a dielectric comprising a via hole is formed on a semiconductor... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090152736 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device includes forming an insulating film above a semiconductor substrate, forming a concave portion in the insulating film, forming a precursor film including a predetermined metallic element on a surface of the insulating film, carrying out a heat treatment on the precursor film and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090152734 - Super-self-aligned contacts and method for making the same: A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each... Agent: Martine Penilla & Gencarella, LLP

20090152738 - Integrated circuit package having bottom-side stiffener: Embodiments of a bottom-side stiffening element are disclosed. The stiffening element may be disposed between an integrated circuit package and an underlying circuit board. In some embodiments, the stiffening element is attached to the underlying circuit board. Other embodiments are described and claimed.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090152741 - Chip structure and fabrication process thereof and flip chip package structure and fabrication process thereof: A chip structure including a chip, a first dielectric layer and at least one first conductive layer is provided. The chip has an active surface, a backside and at least one bonding pad disposed on the active surface. The first dielectric layer is disposed on the active surface and has... Agent: Jianq Chyun Intellectual Property Office

20090152740 - Integrated circuit package system with flip chip: An integrated circuit package system includes: mounting a flip chip over a carrier with a non-active side of the flip chip facing the carrier; mounting a substrate over the flip chip; connecting an internal interconnect between the flip chip and the carrier; and encapsulating the flip chip and the internal... Agent: Law Offices Of Mikio Ishimaru

20090152739 - Method and system for filters embedded in an integrated circuit package: Methods and systems for filters embedded in an integrated circuit package are disclosed and may include controlling filtering of signals within an integrated circuit via one or more filter components embedded within a multi-layer package bonded to the integrated circuit. The one or more filter components may be electrically coupled... Agent: Mcandrews Held & Malloy, Ltd

20090152742 - Method of manufacturing semiconductor package and semiconductor plastic package using the same: A method of manufacturing a semiconductor package may include: forming a first board; forming second boards, in each of which at least one cavity is formed; attaching the second boards to both sides of the first board, such that the second boards are electrically connected with the first board; and... Agent: Staas & Halsey LLP

20090152743 - Routing layer for a microelectronic device, microelectronic package containing same, and method of forming a multi-thickness conductor in same for a microelectronic device: A routing layer for a microelectronic device includes a first region (110, 510) containing a first trench (111, 511), a second region (120, 520) containing a second trench (121, 521), and an electrically conductive material (230, 530) in the first trench and in the second trench. The first trench has... Agent: Kenneth Nelson Intel Corporation

20090146126 - Probe-based memory: Apparatuses, a method, and a system for a non-volatile, probe-based memory device are disclosed herein. In various embodiments, probe-based memory may be one-time programmable or rewritable nonvolatile probe-based memory.... Agent: Schwabe, Williamson & Wyatt, P.C.

20090146125 - Resistive memory and method for manufacturing the same: A method for manufacturing resistive memory includes depositing a first conductive material layer on a substrate; etching the first conductive material layer to form a first signal line with a first surface; forming a memory material layer with a second surface coupled to the first signal line via the second... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090146127 - Phase change memory: Phase change memories comprising a top electrode, a phase change element, a plurality of via holes allocated between the top electrode and the phase change element, at least four heaters aiming at different regions of the phase change element, and a plurality of bottom electrodes and transistors corresponding to the... Agent: Quintero Law Office, PC

20090146128 - electrical device using phase change material, phase change memory device using solid state reaction and method for fabricating the same: Provided are a nonvolatile memory device and a method of fabricating the same, in which a phase-change layer is formed using a solid-state reaction to reduce a programmable volume, thereby lessening power consumption. The device includes a first reactant layer, a second reactant layer formed on the first reactant layer,... Agent: Ampacc Law Group

20090146129 - Multi-bit memory cell structure and method of manufacturing the same: A method of manufacturing a semiconductor memory cell including phase change material. A multi-bit memory cell may implement phase change material. Various kinds of information can be stored in one memory cell. A chip size may be minimized without sacrificing capacity and/or memory performance, as compared with a one-bit memory... Agent: Sherr & Vaughn, PLLC

20090146130 - Nitrogenated carbon electrode for chalcogenide device and method of making same: A nitrogenated carbon electrode suitable for use in a chalcogenide device and method of making the same are described. The electrode comprises nitrogenated carbon and is in electrical communication with a chalcogenide material. The nitrogenated carbon material may be produced by combining nitrogen and vaporized carbon in a physical vapor... Agent: Kevin L. Bray Ovonyx, Inc.

20090146131 - Integrated circuit, and method for manufacturing an integrated circuit: According to one embodiment of the present invention, a method of manufacturing an integrated circuit including a plurality of memory cells is provided, including: forming a first isolation layer including a plurality of contact elements, each contact element extending from the top surface of the first isolation layer to the... Agent: Slater & Matsil, L.L.P.

20090146132 - Nitride semiconductor device: There is provided a nitride semiconductor device including: an n-type nitride semiconductor layer; a p-type nitride semiconductor layer; and an active layer formed between the n-type and p-type nitride semiconductor layers, the active layer including a plurality of quantum well layers and at least one quantum barrier layer deposited alternately... Agent: Mcdermott Will & Emery LLP

20090146133 - Hybrid semiconductor structure: A method for the fabrication of a semiconductor structure that includes areas that have different crystalline orientation and semiconductor structure formed thereby. The disclosed method allows fabrication of a semiconductor structure that has areas of different semiconducting materials. The method employs templated crystal growth using a Vapor-Liquid-Solid (VLS) growth process.... Agent: Ibm Corporation, T.j. Watson Research Center

20090146135 - Detector and method of fabricating the same: Provided are a detector and a method of fabricating the same. The detector includes a base portion; first and second electrodes disposed on the base portion and spaced apart from each other; a reactant layer disposed between the first and second electrodes on the base portion to react with a... Agent: Rabin & Berdo, PC

20090146137 - Display substrate and method of manufacturing the same: In a manufacturing method of a display substrate according to one or more embodiments, a plurality of thin films are patterned by using a photoresist film pattern having different thicknesses in each area on a substrate as etch masks. The photoresist film pattern may be etch-backed at least twice during... Agent: Haynes And Boone, LLPIPSection

20090146139 - Materials for organic electroluminescent devices: The present invention relates to anthracene derivatives, to the use thereof in organic electroluminescent devices, and to organic electroluminescent devices comprising these compounds.... Agent: Connolly Bove Lodge & Hutz, LLP

20090146140 - Nonvolatile organic bistable memory device and method of manufacturing the same: A nonvolatile organic bistable memory device includes a substrate, a lower electrode disposed on the substrate, a lower charge injection layer disposed on the lower electrode, an insulating polymer layer including nanoparticles disposed on the lower charge injection layer, an upper charge injection layer disposed on the insulating polymer layer,... Agent: Volentine & Whitt PLLC

20090146136 - Organic memory device and method of fabricating the same: Provided are a highly integrated organic memory device and a method of fabricating the same. The device includes an insulating substrate, a lower electrode disposed on the insulating substrate, an electron channel layer disposed on the lower electrode, and an upper electrode disposed on the electron channel layer. A bulk... Agent: Ampacc Law Group

20090146134 - Semiconductive percolating networks: The present invention relates to a semi-conductive composition comprising carbon nanotubes in a matrix. These semiconductive compositions are useful in printing semiconducting portions of thin film transistors.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20090146138 - Thin-film transistor, electro-optical device, and electronic apparatus: e

20090146141 - Method for manufacturing n-type and p-type chalcogenide material, doped homojunction chalcogenide thin film transistor and method of fabricating the same: The present invention provides a doped homojunction chalcogenide thin film transistor and a method of fabricating the same, comprising forming an N-type chalcogenide layer constituting a channel layer on a substrate, forming and patterning a diffusion prevention layer on the upper part of the N-type chalcogenide layer, and forming a... Agent: Ladas & Parry LLP

20090146142 - Light-emitting device including nanorod and method of manufacturing the same: Provided are a light-emitting device including a plurality of nanorods each of which comprises an active layer formed between an n-type region and a p-type region, and a method of manufacturing the same. The light-emitting device comprises: a substrate; a first electrode layer formed on the substrate; a basal layer... Agent: Harness, Dickey & Pierce, P.L.C

20090146144 - Method and system supporting production of a semiconductor device using a plurality of fabrication processes: There is provided a tuning method for use by a semiconductor device capable of being fabricated using a plurality of fabrication processes comprising reading a fabrication identification included in the semiconductor device, associating the fabrication identification with one of the plurality of fabrication processes to determine an associated fabrication process... Agent: Farjami & Farjami LLP

20090146145 - Processing condition inspection and optimization method of damage recovery process, damage recovering system and storage medium: A processing condition inspection method of a damage recovery process for reforming a film having OH groups generated by damages from a predetermined process by using a processing gas includes preparing a substrate having an OH group containing resin film, measuring an initial film thickness of the OH group containing... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090146143 - Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing: A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line... Agent: Cantor Colburn LLP - IBM Fishkill

20090146146 - Semiconductor device formed in a recrystallized layer: A semiconductor device includes a substrate that includes a first layer and a recrystallized layer on the first layer. The first layer has a first intrinsic stress and the recrystallized layer has a second intrinsic stress. A transistor is formed in the recrystallized layer. The transistor includes a source region,... Agent: Slater & Matsil LLP

20090146148 - Backside illuminated image sensor: A backside illuminated image sensor includes a light receiving element disposed in a first substrate, an interlayer insulation layer disposed on the first substrate having the light receiving element, an align key spaced apart from the light receiving element and passing through the interlayer insulation layer and the first substrate,... Agent: Morgan Lewis & Bockius LLP

20090146147 - Digital x-ray detector and fabrication method thereof: A digital x-ray detector and its fabrication method are disclosed to strengthen an electrical connection between an upper electrode and a lower by employing a multi-contact hole structure and obtaining reliability of a contact hole by electrically connecting the side of the lower line and the upper electrode. A semiconductor... Agent: Mckenna Long & Aldridge LLP

20090146150 - Display device and method for manufacturing the same: A display device having the high aperture ratio and a storage capacitor with high capacitance is to be obtained. The present invention relates to a display device and a manufacturing method thereof. The display device includes a thin film transistor which includes a gate electrode, a gate insulating film, a... Agent: Cook Alex Ltd. Suite 2850

20090146149 - Semiconductor device, and manufacturing method thereof: In a display device such as a liquid crystal display device, a large-sized display screen is realized under low power consumption. A surface of a source wiring line of a pixel portion employed in an active matrix type liquid crystal display device is processed by way of a plating process... Agent: Fish & Richardson P.C.

20090146151 - Thin film transistor array substrate and method of manufacturing the same: A method for manufacturing a TFT-array substrate includes forming a first conductive pattern layer including a gate line, a gate electrode, and a lower gate pad electrode using a first mask, forming a channel and a second conductive pattern layer including a source electrode, a drain electrode, a data line,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090146153 - Pixel with strained silicon layer for improving carrier mobility and blue response in imagers: An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.... Agent: Dickstein Shapiro LLP

20090146152 - Thin film transistor array panel and method for manufacturing the same: A thin film transistor array panel and a method of its manufacture are presented. The thin film transistor array panel according to an embodiment includes a substrate, a gate line extending in a first direction on the substrate, a data line extending in a second direction on the substrate and... Agent: Haynes And Boone, LLPIPSection

20090146154 - Transistor with a-face conductive channel and trench protecting well region: A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region... Agent: Summa, Additon & Ashe, P.A.

20090146155 - Light-emitting diode: An LED includes a substrate having a substantially flat substrate surface, a plurality of electrodes extending through the substrate, an LED chip configured for emitting light, a first and a second coplanar reflective layers formed on the surface, and a light pervious encapsulation member mounted on the substrate surface. The... Agent: PCe Industry, Inc. Att. Steven Reiss

20090146156 - Led chip package structure with high-efficiency light-emitting effect and method for making the same: An LED chip package structure with high-efficiency light-emitting effect includes a substrate unit, a light-emitting unit, a package colloid unit, and a frame unit. The light-emitting unit has a plurality of LED chips electrically arranged on the substrate unit. The package colloid unit has a longitudinal package colloid covering the... Agent: Rosenberg, Klein & Lee

20090146157 - Light-emitting diode package: An LED package is provided. The LED package includes a leadframe having a pair of first electrodes and a pair of second electrodes, an LED chip disposed on the leadframe, and an encapsulant encapsulating a portion of the leadframe and the LED chip. The pair of first electrodes and the... Agent: Jianq Chyun Intellectual Property Office

20090146158 - Package for light emitting device and method for packaging the same: There are provided a light emitting device package and a method for manufacturing the same. The light emitting device includes: a plurality of barriers provided above a metal circuit board; a plurality of light emitting devices placed in a space between the barriers; and a lens unit provided at an... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090146159 - Light-emitting device, method of manufacturing the light-emitting device and liquid crystal display having the light-emitting device: A light-emitting device includes a substrate on which at least one light source region is defined, the light source region having one or more sub-light source regions that are separated from one another by a gap, a plurality of electrode patterns which are respectively formed in the sub-light source regions,... Agent: Cantor Colburn, LLP

20090146162 - Fabrication of nonpolar indium gallium nitride thin films, heterostructures and devices by metalorganic chemical vapor deposition: A method for the fabrication of nonpolar indium gallium nitride (InGaN) films as well as nonpolar InGaN-containing device structures using metalorganic chemical vapor deposition (MOVCD). The method is used to fabricate nonpolar InGaN/GaN violet and near-ultraviolet light emitting diodes and laser diodes.... Agent: Gates & Cooper LLP Howard Hughes Center

20090146160 - Gallium nitride semiconductor light emitting element: A gallium nitride semiconductor crystal 2 including a light emitting region is formed on the R plane of a sapphire substrate 1. In addition, in another constitution, a gallium nitride semiconductor crystal 2 is formed on the A plane of a GaN substrate 3 or on the M plane of... Agent: Rabin & Berdo, PC

20090146161 - Group iii nitride compound semiconductor stacked structure: The group III nitride compound semiconductor stacked structure of the present invention is a group III nitride compound semiconductor stacked structure comprising a substrate having provided thereon a first layer comprising a group III nitride compound semiconductor and a second layer being in contact with the first layer and comprising... Agent: Sughrue Mion, PLLC

20090146163 - High brightness light emitting diode structure: The present invention discloses a high brightness LED structure, wherein a highly-doped n-type AlInP island structure is formed on a portion of the surface of an AlGaInP semiconductor stack structure and functions as a current barrier structure. The island structure is covered by a p-type window layer and positioned below... Agent: Joe Mckinney Muncy

20090146164 - Blue-shifted triarylamine polymer: where Arl, Ar3, and Ar5 are the same or different and wherein each represents an optionally substituted aryl or heteroaryl group; Ar2 and Ar4 are the same or different and each represent a substituted aryl or heteroaryl group; and Ar2 and Ar4 sterically interact with one another so as to... Agent: Marshall, Gerstein & Borun LLP

20090146168 - High efficiency led with multi-layer reflector structure and method for fabricating the same: Provided are a high efficiency light emitting diode and a method for fabricating the same, in which a multi-layer reflector is laminated to a surface emission type light emitting diode to improve the efficiency of a light emitting diode. A high efficiency reflector is integrated on the light emitting diode... Agent: Gifford, Krass, Sprinkle,anderson & Citkowski, P.c

20090146170 - High light extraction efficiency nitride based light emitting diode by surface roughening: A III-nitride light emitting diode (LED) and method of fabricating the same, wherein at least one surface of a semipolar or nonpolar plane of a III-nitride layer of the LED is textured, thereby forming a textured surface in order to increase light extraction. The texturing may be performed by plasma... Agent: Gates & Cooper LLP Howard Hughes Center

20090146167 - Jacketed led assemblies removable from lamp husks and light strings containing same: A jacketed light emitting diode assembly is provided, which includes a light emitting diode, a lens body containing a semiconductor chip and a set of positive and negative contacts exiting said lens body from a base portion. An electrical wire set of first and second electrical wires are connected to... Agent: Berenato, White & Stavish, LLC

20090146165 - Led structure: A light emitting device, a wafer for making the same, and method for fabricating the same are disclosed. The device and wafer include a first layer of a first conductivity type, an active layer, and a layer of a second conductivity type. The active layer overlies the first layer, the... Agent: The Law Offices Of Calvin B. Ward

20090146169 - Method of fabricating light emitting diode package with surface treated resin encapsulant and the package fabricated by the method: Disclosed are a method of fabricating a light emitting diode package with a surface treated resin encapsulant and a package fabricated by the method. According to the method of fabricating a light emitting diode package, a resin encapsulant encapsulating a light emitting diode chip is surface treated using plasma. Thus,... Agent: H.c. Park & Associates, PLC

20090146171 - Semiconductor light-emitting device and method for manufacturing the same: A semiconductor light-emitting device and a method for manufacturing the same can include a soft silicon resin encapsulating an LED chip with a thin overcoat of microparticles located on the silicon resin to prevent dirt and dust from attaching to the silicon resin. The semiconductor light-emitting device can include a... Agent: Cermak Kenealy Vaidya & Nakajima LLP

20090146166 - Structure applying optical limit guide layer: A structure applying an optical wave guide layer includes an incident light source and at least one optical wave guide layer. The structure can be in any geometric shape such as a planar, hemispherical or conical shape. The geometric structure is designed for collecting and guiding the incident light source... Agent: Hdls Patent & Trademark Services

20090146172 - Component attach methods and related device structures: A method, and associated apparatus, for attaching a component (e.g., an electronic and/or optoelectronic component) is provided which can facilitate low-voiding of an attachment layer. The method includes disposing an attachment material layer over a surface, providing the component having a backside surface, disposing a portion of the backside surface... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.C.

20090146174 - Semiconductor device and manufacturing method thereof, and camera module including the same: A semiconductor device includes: an insulating base; a semiconductor element provided on the insulating base; a protector provided on the semiconductor element; and a frame provided on a periphery of the insulating base and surrounding the semiconductor element. A region inside the frame is filled with a sealing resin, and... Agent: Mcdermott Will & Emery LLP

20090146173 - Solid state illumination device: A solid state illumination device includes a solid state light emitting diode and a mounting base. The solid state light emitting diode includes encapsulation material, a wafer, and first and second electrodes. The first and second electrodes have first ends electrically connecting with the wafer, and opposite second ends exposed... Agent: PCe Industry, Inc. Att. Steven Reiss

20090146176 - Light emitting diode: The outer peripheral portion of a substrate is provided with a first peripheral edge and a second peripheral edge. The first peripheral edge is provided on the edge portion of a first upper surface of the substrate on which a light-emitting diode element is mounted. The second peripheral edge is... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20090146175 - Thermal stable transparent silicone resin compositions and methods for their preparation and use: A curable silicone composition includes (A) a polydiorganosiloxane having an average, per molecule, of at least two aliphatically unsaturated organic groups and at least one aromatic group; (B) a branched polyorganosiloxane having an average, per molecule, of at least one aliphatically unsaturated organic group and at least one aromatic group;... Agent: Dow Corning Corporation Co1232

20090146177 - Variable threshold trench igbt with offset emitter contacts: A trench type IGBT as disclosed herein includes a plurality of channel regions having one threshold voltage for the normal operation of the device and a plurality of channel regions having a threshold voltage higher than the threshold voltage for the normal operation of the device.... Agent: Ostrolenk Faber Gerb & Soffen

20090146178 - Photodiode: A photodiode in which increased sensitivity and speed are balanced. The photodiode includes: a semiconductor substrate; a plurality of active regions formed on the substrate by selective epitaxial growth; and a comb electrode provided for each of the plurality of active regions and in communication with each other to electrically... Agent: Sughrue Mion, PLLC

20090146179 - Planar arrays of photodiodes: An apparatus includes a light detector. The light detector includes a substrate with a planar surface and an array of photodiodes located along the planar surface. Each photodiode has a sequence of different semiconductor layers stacked vertically over the planar surface. The photodiodes are electrically connected in series.... Agent: Docket Administrator - Room 2f-192 Alcatel-lucent Usa Inc.

20090146181 - Integrated circuit system employing diffused source/drain extensions: An integrated circuit system that includes: providing a PFET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer.... Agent: Law Offices Of Mikio Ishimaru

20090146180 - Ldmos with channel stress: A method of forming a metal oxide semiconductor (MOS) device comprises defining an active area in an unstrained semiconductor layer structure, depositing a hard mask overlying the active area and a region outside of the active area, patterning the hard mask to expose the active area, selectively growing a strained... Agent: Freescale Semiconductor, Inc. Law Department

20090146182 - Nitride semiconductor device and method for fabricating the same: A nitride semiconductor device includes: first through third nitride semiconductor layers formed in sequence over a substrate. The second nitride semiconductor layer has a band gap energy larger than that of the first nitride semiconductor layer. The third nitride semiconductor layer has an opening. A p-type fourth nitride semiconductor layer... Agent: Mcdermott Will & Emery LLP

20090146183 - Method of forming a germanium silicide layer, semiconductor device including the germanium silicide layer, and method of manufacturing the semiconductor device: Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include forming a metal layer including vanadium (V)... Agent: Harness, Dickey & Pierce, P.L.C

20090146184 - Semiconductor device with t-gate electrode and method for fabricating the same: Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes... Agent: Rabin & Berdo, PC

20090146186 - Gate after diamond transistor: A gate after diamond transistor and method of making comprising the steps of depositing a first dielectric layer on a semiconductor substrate, depositing a diamond particle nucleation layer on the first dielectric layer, growing a diamond thin film layer on the first dielectric layer, defining an opening for the gate... Agent: Naval Research Laboratory Associate Counsel (patents)

20090146185 - Insulated gate e-mode transistors: Enhancement-mode III-nitride transistors are described that have a large source to drain barrier in the off state, low off state leakage, and low channel resistance in the access regions are described. The devices can include a charge depleting layer under the gate and/or a charge enhancing layer outside of the... Agent: Fish & Richardson P.C.

20090146187 - Nitride semiconductor element and process for producing the same: An undoped GaN layer, a silicon film, an n type GaN layer, an MQW active layer and a p type GaN layer are stacked sequentially in this order on an AlN buffer layer formed on a sapphire substrate. In this manner, the silicon film is formed in the mid-section of... Agent: Rabin & Berdo, PC

20090146188 - Semiconductor storage device and manufacturing method thereof: A semiconductor storage device includes a plurality of integrated memory cells. Each cell includes a first inverter having a first driver transistor and a first load transistor which are formed on a semiconductor substrate in order to form a first storage node, a second inverter having a second driver transistor... Agent: Sonnenschein Nath & Rosenthal LLP

20090146189 - Pads and pin-outs in three dimensional integrated circuits: A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a said circuit; and a memory array positioned above or below the substrate coupled to a said circuit to program the memory array.... Agent: Raminda U. Madurawe

20090146190 - Semiconductor memory device and method for fabricating semiconductor memory device: t

20090146191 - Low leakage schottky contact devices and method: Method and apparatus are described for semiconductor devices. The method (100) comprises, providing a partially completed semiconductor device (31-1) including a substrate (21), a semiconductor (22) on the substrate (21) and a passivation layer (25) on the semiconductor (22), and using a first mask (32), locally etching the passivation layer... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20090146193 - Conductive interconnects: A method of making a conductive interconnect structure includes the steps of: electrodepositing a metal on a conductive surface (4) of a carrier (2) to form a first elongate conductive interconnect (12); and electrodepositing a dielectric material (14) on said conductive interconnect (12) while the conductive interconnect (12) is in... Agent: Hewlett Packard Company

20090146192 - Mos transistor and method of forming the mos transistor with a sion etch stop layer that protects the transistor from pid and hot carrier degradation: A MOS transistor is formed with a dual-layer silicon oxynitride (SiON) etch stop film that protects the transistor from plasma induced damage (PID) and hot carrier degradation, thereby improving the reliability of the transistors. The first SiON layer is formed with SiH4 at a first flow rate, and the second... Agent: Law Office Of Mark C. Pickering

20090146194 - Semiconductor device and method of manufacturing a semiconductor device: The local bending of a silicon nanowire induces tensile strain in the wire due to the stretching of the silicon lattice. This in turn enhances the mobility of the free carriers (electrons) in the direction of transport along the wire. Thus, for example, when Gate-All-Around MOSFETs are fabricated along the... Agent: Nixon & Vanderhye, PC

20090146195 - Noise reduction in active pixel sensor arrays: A system for detecting high speed noise in active pixel sensors includes a photodiode for receiving low levels of light, a reset transistor, an amplifier transistor, a row select transistor, and a high-speed analog-to-digital converter. The reset transistor gate receives a reset signal, and the reset transistor drain receives a... Agent: CenturyIPGroup, Inc. [intel]

20090146196 - Image sensor: An image sensor, in particular a CMOS image sensor, for electronic cameras having a plurality of light-sensitive pixels which are arranged in rows and columns and whose signals are conducted via a plurality of column lines to column amplifiers, with a column amplifier being associated with each column line. At... Agent: Gifford, Krass, Sprinkle, Anderson & Citkowski, P.C.

20090146199 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and fabricating method can reduce leakage current of a photodiode reduced by configuring a triangular shape of a photodiode area to minimize an interface contacting the STI or performing deuterium annealing to remove dangling bonds from an interface contacting with oxide. The CMOS image sensor includes... Agent: Mckenna Long & Aldridge LLP

20090146197 - Photo-detector array device with roic monolithically integrated for laser-radar image signal and manufacturing method thereof: A photo-detector array device integrated with a read-out integrated circuit (ROIC) monolithically integrated for a laser-radar image signal and a manufacturing method thereof are provided. According to the photo-detector array device, a photodiode and control devices for selecting and outputting a laser-radar image signal are simultaneously formed on an InP... Agent: Rabin & Berdo, PC

20090146198 - Photodiodes, image sensing devices and image sensors: Provided are photodiodes, image sensing devices and image sensors. An image sensing device includes a p-n junction photodiode having a metal pattern layer on an upper surface thereof. An image sensor includes the image sensing device and a micro-lens formed above the metal pattern layer. The metal pattern layer filters... Agent: Harness, Dickey & Pierce, P.L.C

20090146200 - Magnesium-doped zinc oxide structures and methods: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently processed to form magnesium-doped zinc oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure.... Agent: Schwegman, Lundberg & Woessner/micron

20090146201 - Work function engineering for fn eras of a memory device with multiple charge storage elements in an undercut region: A memory device comprised of a plurality of memory cells that can each include multiple charge storage elements in undercut regions that are formed under a tunneling barrier and adjacent to a gate oxide layer of each memory cell. The tunneling barrier can be formed from a high work function... Agent: Amin, Turocy & Calvin, LLP

20090146202 - Organic memory device and method of manufacture: An organic memory device is disclosed that has an active layer, at least one charge storage layer of a film of an organic dielectric material, and nanostractures and/or nano-particles of a charge-storing material on or in the film of dielectric material. Each of the nanostructures and/or nano-particles is separated from... Agent: Dickstein Shapiro LLP

20090146205 - Floating gate of flash memory device and method of forming the same: Disclosed is a floating gate of a flash memory device, wherein a tunneling oxide layer is formed on a semiconductor substrate, and a floating gate is formed in the shape of a lens having a convex top surface.... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090146203 - Nonvolatile semiconductor memory device: In one aspect of the present invention, a nonvolatile semiconductor memory device may include a semiconductor substrate; a plurality of tunnel insulating films formed on the semiconductor substrate at predetermined intervals in a first direction; a plurality of floating gate electrodes each having a first portion and a second portion,... Agent: Amin, Turocy & Calvin, LLP

20090146204 - Semiconductor device and method of fabricating the same: A semiconductor device includes a first poly layer over a semiconductor substrate, an IPD layer over the first poly layer, a second poly layer over the IPD layer, an oxide layer over a sidewall of the second poly layer, a first insulating layer over a sidewall of the oxide layer,... Agent: Sherr & Vaughn, PLLC

20090146206 - Non-volatile semiconductor storage device and method of manufacturing the same: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate and having a first hollow extending downward from its... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090146208 - Independently controlled, double gate nanowire memory cell with self-aligned contacts: A double gate, dynamic storage device and method of fabrication are disclosed. A back (bias gate) surrounds three sides of a semiconductor body with a front gate disposed on the remaining surface. Two different gate insulators and gate materials may be used.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090146207 - Nonvolatile memory devices including common source: Provided is a nonvolatile memory device including a common source. The device includes a first active region crossing a second active region, a common source disposed in the second active region, and a source conductive line disposed on the common source in parallel to the common source. The source conductive... Agent: Myers Bigel Sibley & Sajovec

20090146209 - Semiconductor device: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of... Agent: Patterson & Sheridan, L.L.P.

20090146211 - Grounding front-end-of-line structures on a soi substrate: Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including... Agent: Hoffman Warnick LLC

20090146210 - Semiconductor on insulator (soi) structure and method for fabrication: A disclosed embodiment is a semiconductor on insulator (SOI) structure comprising a buried oxide layer over a bulk semiconductor layer, and a device layer over the buried oxide layer. At least one transistor is fabricated in the device layer, wherein a source/drain junction of the transistor does not contact the... Agent: Farjami & Farjami LLP

20090146212 - Negative differential resistance diode and sram utilizing such device: A negative differential resistance (NDR) diode and a memory cell incorporating that NDR diode are provided. The NDR diode comprises a p-type germanium region in contact with an n-type germanium region and forming a germanium pn junction diode. A first gate electrode overlies the p-type germanium region, is electrically coupled... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20090146214 - Method for manufacturing an eeprom cell: A method for manufacturing a cell of a non-volatile electrically erasable and programmable memory including a dual-gate MOS transistor. The method includes the steps of providing a semiconductor substrate covered with an insulating layer including a thinned down portion and having a first surface common with the substrate and a... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20090146213 - Semiconductor lsi circuit and a method for fabricating the semiconductor lsi circuit: Basic logic gates are formed in a small area, and a highly integrated and microscopic structure is provided. In an nMOSFET and a pMOSFET, gate electrodes are formed facing each other and sandwiching a semiconductor region via gate insulting layers. Respective drain regions of the nMOSFET and the pMOSFET are... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090146218 - Pmos depletable drain extension made from nmos dual depletable drain extensions: In accordance with an embodiment of the invention, there is an integrated circuit device having a complementary integrated circuit structure comprising a first MOS device. The first MOS device comprises a source doped to a first conductivity type, a drain extension doped to the first conductivity type separated from the... Agent: Mh2 Technology Law Group, LLP

20090146216 - Semiconductor device and manufacturing method of the same: After forming a pure silicon oxide film on respective surfaces of an n-type well and a p-type well, an oxygen deficiency adjustment layer made of an oxide of 2A group elements, an oxide of 3A group elements, an oxide of 3B group elements, an oxide of 4A group elements, an... Agent: Miles & Stockbridge PC

20090146215 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a first gate insulating film on a first region of a semiconductor substrate; a first gate electrode on the first gate insulating film; a second gate insulating film on a second region of the semiconductor substrate; and a second gate electrode on the second gate insulating... Agent: Mcdermott Will & Emery LLP

20090146217 - Semiconductor devices and methods of manufacture thereof: Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectric. A layer of semiconductive material is disposed over the thin layer of... Agent: Slater & Matsil LLP

20090146219 - Integrated circuit having memory cell array, and method of manufacturing same: An integrated circuit device (e.g., a logic device or a memory device) having (i) a memory cell array which includes a plurality of memory cells (for example, memory cells having electrically floating body transistors) arranged in a matrix of rows and columns, wherein each memory cell includes at least one... Agent: Neil Steinberg

20090146220 - Multi device and method of manufacturing the same: Embodiments relate to a multi device that may include a first MOS transistor having a first gate oxide film, and a second MOS transistor having a second gate oxide film thicker than the first gate oxide film. According to embodiments, a LDD structure of the first MOS transistor may be... Agent: Sherr & Vaughn, PLLC

20090146222 - Method for fabrication of single electron transistors: A method for fabricating a Single Electron Transistor (SET). The method comprises forming a FinFET structure, forming an SET structure from the FinFET structure such that an active area of the SET structure is formed from a channel of the FinFET structure, whereby the active area is self-aligned with a... Agent: Rothwell, Figg, Ernst & Manbeck, P.C.

20090146221 - Method of patterning semiconductor structure and structure thereof: Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protective layer; patterning the monocrystalline layer to form a hard mask; enhancing... Agent: Hoffman Warnick LLC

20090146223 - Process and method to lower contact resistance: A method removes the spacers from the sides of a transistor gate stack, and after the spacers are removed, the method implants an additional impurity into surface regions of the substrate not protected by the gate conductor (or alternatively just amorphizes these surface regions, without adding more impurity). The method... Agent: International Business Machines Corporation Dept. 18g

20090146224 - Composite passivation process for nitride fet: A nitride-based FET device that provides reduced electron trapping and gate current leakage. The device includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. The device includes semiconductor device layers deposited on... Agent: MillerIPGroup, PLC Northrop Grumman Corporation

20090146225 - Semiconductor device and method for fabricating the same: A method for manufacturing a semiconductor device includes a gate dielectric film formed over an active area of a semiconductor substrate, and a gate electrode formed over the gate dielectric film and formed of a silicidation film having a polysilicon area at the bottom of the gate electrode. Therefore, with... Agent: Sherr & Vaughn, PLLC

20090146227 - Capacitive sensor and manufacturing method therefor: A capacitive sensor according to the present invention includes a semiconductor substrate, a fixed electrode serving as a first electrode formed on a surface of or in the semiconductor substrate, a structure formed on the semiconductor substrate to have a vibratable second electrode that is formed to be spaced from... Agent: Volentine & Whitt PLLC

20090146226 - Mechanical memory tarnsistor: A mechanical memory transistor includes a substrate having formed thereon a source region and a drain region. An oxide is formed upon a portion of the source region and upon a portion of the drain region. A pull up electrode is positioned above the substrate such that a gap is... Agent: Gauthier & Connors, LLP

20090146228 - Microminiature moving device: A microminiature moving device has disposed on a single-crystal silicon substrate movable elements such as a movable rod and a movable comb electrode that are displaceable in parallel to the substrate surface and stationary parts that are fixedly secured to the single-crystal silicon substrate with an insulating layer sandwiched between.... Agent: Gallagher & Lathrop, A Professional Corporation

20090146229 - Semiconductor device and method for fabricating the same: Embodiments relate to a semiconductor device and a method for fabricating the same. According to embodiments, a semiconductor device may include a metal film spaced from a semiconductor substrate at a predetermined interval and in which a plurality of etching holes are formed. A bottom metal pattern disposed on and/or... Agent: Sherr & Vaughn, PLLC

20090146230 - Semiconductor pressure sensor, method for producing the same, semiconductor device, and electronic apparatus: A semiconductor pressure sensor includes: a first substrate; a buried insulating film laminated on the first substrate; a second substrate laminated on the buried insulating film; a plurality of electrodes including a lower electrode and at least two upper electrodes, the lower electrode being formed on the second substrate; and... Agent: Harness, Dickey & Pierce, P.L.C

20090146231 - Magnetic memory device having a c-shaped structure and method of manufacturing the same: A non-volatile magnetic memory device having one or more memory cells, each of the memory cells includes a magnetic switch including a C-shaped magnetic component and a write coil located proximate the magnetic component, the write coil coupled to receive a current sufficient to create a remnant magnetic polarity in... Agent: Morgan Lewis & Bockius LLP

20090146232 - Magnetoresistive device: A magnetoresistive device comprises a ferromagnetic region, a non-ferromagnetic region, an insulating region and a conductive region. The insulating region is arranged between the ferromagnetic region and the conductive region so as to provide a tunnel barrier. The non-ferromagnetic region separates the insulating region and the ferromagnetic region.... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090146233 - Non-magnetic semiconductor spin transistor: m

20090146237 - Image sensor and method for manufacturing thereof: An image sensor and a method for manufacturing thereof include a semiconductor substrate having a plurality of unit pixels formed therein, a dielectric film formed over the semiconductor substrate, a seed lens array including a plurality of seed lenses formed spaced apart by a gap of a predetermined width over... Agent: Sherr & Vaughn, PLLC

20090146234 - Microelectronic imaging units having an infrared-absorbing layer and associated systems and methods: Infrared (IR) absorbing layers and microelectronic imaging units that employ such layers are disclosed herein. In one embodiment, a method of manufacturing a microelectronic imaging unit includes attaching an IR-absorbing lamina having a filler material to a backside die surface of an imager workpiece. An individual imaging die is singulated... Agent: Perkins Coie LLP Patent-sea

20090146236 - Photosensitive resin composition for pad protective layer, and method for making image sensor using the same: The present invention provides a photosensitive resin composition for a pad protective layer that includes (A) an alkali soluble resin, (B) a reactive unsaturated compound, (C) a photoinitiator, and (D) a solvent. The (A) alkali soluble resin includes a copolymer including about 5 to about 50 wt % of a... Agent: Summa, Additon & Ashe, P.A.

20090146235 - Solid-state image capturing device, camera module and electronic information device: A solid-state image capturing device includes a plurality of electrode pads for inputting and outputting a signal or voltage from and to the outside, a plurality of photoelectric conversion elements, a planarization film for planarizing the difference in the level on the surface above the plurality of photoelectric conversion elements,... Agent: Edwards Angell Palmer & Dodge LLP

20090146238 - Cmos-based planar type silicon avalanche photo diode using silicon epitaxial layer and method of manufacturing the same: A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer... Agent: Ampacc Law Group

20090146239 - Photodiode: A photodiode balanced in increased sensitivity and speed. The photodiode includes a semiconductor substrate, an active region formed on the semiconductor substrate, and a comb electrode connected to the active region. The comb electrode includes a plurality of electrode fingers, and each of the electrode fingers includes a transparent electrode... Agent: Sughrue Mion, PLLC

20090146240 - Silicon-based visible and near-infrared optoelectric devices: In one aspect, the present invention provides a silicon photodetector having a surface layer that is doped with sulfur inclusions with an average concentration in a range of about 0.5 atom percent to about 1.5 atom percent. The surface layer forms a diode junction with an underlying portion of the... Agent: Nutter Mcclennen & Fish LLP

20090146241 - Semiconductor apparatus and manufacturing method thereof: The present invention provides a semiconductor apparatus for improving a switching speed and a withstand voltage, and a manufacturing method of the semiconductor apparatus. The semiconductor apparatus of the invention including a first conductive type semiconductor substrate, a first conductive type first semiconductor region with an impurity concentration lower than... Agent: Mcdermott Will & Emery LLP

20090146242 - Metal ion transistor and related methods: A metal ion transistor and related methods are disclosed. In one embodiment, the metal ion transistor includes a cell positioned in at least one isolation layer, the cell including a metal ion doped low dielectric constant (low-k) dielectric material sealed from each adjacent isolation layer; a first electrode contacting the... Agent: Hoffman Warnick LLC

20090146243 - Semiconductor device having recessed channel and method for manufacturing the same: A semiconductor device having a recessed channel and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate formed with an isolation layer defining an active region including a channel region and a junction region, a recessed trench including a top trench formed within the channel region... Agent: Marshall, Gerstein & Borun LLP

20090146244 - Semiconductor structure and method of manufacture: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material to form a first protrusion and a cavity having a boundary that is below a surface of the semiconductor material, wherein the first protrusion... Agent: Hvvi Semiconductors, Inc.

20090146245 - Semiconductor structure and method of manufacture: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material to form a cavity that extends at least about one micron or greater below the surface of the semiconductor material, filling the cavity with... Agent: Hvvi Semiconductors, Inc.

20090146246 - Semiconductor device and method of fabricating the same: The present invention relates to a semiconductor device and a method of manufacture thereof, being capable of improving the high integration by increasing a cell region while securing the reliability of device and the process margin through forming a cell region and a core region with the stacking structure.... Agent: Townsend And Townsend And Crew, LLP

20090146247 - Semiconductor ground shield: A ground shield is disclosed that includes a ‘cheesed’ metal positioned within a dielectric layer and a metal region positioned within a first metal level over the cheesed metal. The ground shield can have different forms depending on the metal used, and provisions are made to prevent diffusion of copper... Agent: Hoffman Warnick LLC

20090146248 - Semiconductor structure and method of manufacture: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a structure includes a dielectric material and a void below a surface of a substrate. The structure further includes a doped dielectric material over the dielectric material, over the first void, wherein at least... Agent: Hvvi Semiconductors, Inc.

20090146249 - Semiconductor structure and method of manufacture: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method to form a semiconductor structure includes removing a portion of a semiconductor material to form one or more suspended structures and a cavity, the cavity having a boundary that is below a... Agent: Hvvi Semiconductors, Inc.

20090146250 - Semiconductor device: A semiconductor device has an electrical fuse formed on a substrate, having a first interconnect, a second interconnect respectively formed in different layers, and a via provided in a layer between the first interconnect and the second interconnect, connected to one end of the second interconnect and connected also to... Agent: Mcginn Intellectual Property Law Group, PLLC

20090146251 - Semiconductor device: The semiconductor device of the present invention comprises a semiconductor substrate; and a conductive element formed on the semiconductor substrate and capable of being opened when a predetermined current flows, wherein the conductive element turns plurality of times.... Agent: Young & Thompson

20090146252 - Integrated inductor structure: This invention provides an integrated inductor structure including a substrate, a metal coil layer on the substrate and a dielectric layer between the substrate and the metal coil layer. A well shielding structure for reducing eddy current is disposed in the substrate under the metal coil layer. The well shielding... Agent: North America Intellectual Property Corporation

20090146253 - Semiconductor device and method of manufacturing the same: Manufacturing an inductor includes forming a spiral metal wire on a semiconductor substrate; forming a connection hole exposing a portion of the metal wire by selectively etching a first dielectric film formed to bury the metal wire, and forming a first metal film on the first dielectric film on which... Agent: Sherr & Vaughn, PLLC

20090146255 - Capacitor for semiconductor device and method for manufacturing the same: Disclosed is a capacitor of a semiconductor device, capable of varying a capacitance according to a design of the semiconductor device. The capacitor can include a first electrode area and a second electrode area with a dielectric therebetween. The first electrode area can have a metal electrode spanning the entire... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090146256 - Method of forming semiconductor device including capacitor and semiconductor device including capacitor: A method of forming a semiconductor device may include, but is not limited to, the following processes. A second insulating film may be formed over a first insulating film. At least one through-hole may be formed, which penetrates the first and second insulating films. At least one first electrode may... Agent: Young & Thompson

20090146254 - Semiconductor device and manufacturing method therefor: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore... Agent: Young & Thompson

20090146257 - Capacitor and semiconductor device including the same: A capacitor includes a first capacitor structure on a substrate, the first capacitor structure including a first electrode, a first dielectric layer pattern, and a second electrode, a second capacitor structure on the first capacitor structure, the second capacitor structure including a third electrode, a second dielectric layer pattern, and... Agent: Lee & Morse, P.C.

20090146258 - Self-aligned vertical pnp transistor for high performance sige cbicmos process: A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for... Agent: HorizonIPPte Ltd

20090146259 - Sub-resolution assist feature to improve symmetry for contact hole lithography: A method of making a mask design having optical proximity correction features is provided. The method can include obtaining a target pattern comprising a plurality of target pattern features corresponding to a plurality of features to be imaged on a substrate. The method can also comprise generating a mask design... Agent: Texas Instruments Incorporated

20090146260 - Semiconductor wafer including cracking stopper structure and method of forming the same: A semiconductor wafer may include, but is not limited to, the following elements. A semiconductor substrate has a device region and a dicing region. A stack of inter-layer insulators may extend over the device region and the dicing region. Multi-level interconnections may be disposed in the stack of inter-layer insulators.... Agent: Mcginn Intellectual Property Law Group, PLLC

20090146261 - Semiconductor device and fabrication method of the semiconductor device: A semiconductor device and its manufacturing method, the semiconductor device comprising: a semi-insulating substrate 11 in which an electrode (12) is formed on a surface (11a) of one side and in which an aperture (11c) passed through from the surface 11a of one side to a surface (11b) of another... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090146262 - Integrated circuit system employing selective epitaxial growth technology: An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to... Agent: Law Offices Of Mikio Ishimaru

20090146263 - Structure and method to increase effective mosfet width: An epitaxial layer of silicon (Si) or silicon-germanium (SiGe) extends over the edge of silicon trench isolation (STI), thereby increasing the effective width of an active silicon region (RX) bordered by the STI. The RX region may have a <100> crystal orientation. An effective width of an FET device formed... Agent: International Business Machines Corporation Dept. 18g

20090146264 - Thin film transistor on soda lime glass with barrier layer: The present invention generally comprises a low cost TFT and a method of manufacturing a TFT. For TFTs, soda lime glass would be an attractive alternative to non-alkali glass, but a soda lime glass substrate will permit sodium to diffuse into the active layer and degrade the performance of the... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090146265 - Ultra low k plasma enhanced chemical vapor deposition processes using a single bifunctional precursor containing both a sicoh matrix functionality and organic porogen functionality: A method for fabricating a SiCOH dielectric material comprising Si, C, O and H atoms from a single organosilicon precursor with a built-in organic porogen is provided. The single organosilicon precursor with a built-in organic porogen is selected from silane (SiH4) derivatives having the molecular formula SiRR1R2R3, disiloxane derivatives having... Agent: Scully, Scott, Murphy & Presser, P.C.

20090146266 - Memory device and method of fabricating the same: A method of fabricating memory devices is provided. First, a charge storage structure including a gate dielectric structure is formed on the substrate in sequence to form a charge trapping layer. Then, a gate conductive layer is formed above the charge storage structure. Afterwards, the gate conductive layer and at... Agent: J C Patents, Inc.

20090146270 - Embedded package security tamper mesh: Systems and methods for embedded tamper mesh protection are provided. The embedded tamper mesh includes a series of protection bond wires surrounding bond wires carrying sensitive signals. The protection bond wires are positioned to be vertically higher than the signal bond wires. The protection wires may be bonded to outer... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090146268 - Integrated circuit package system for electromagnetic isolation: An integrated circuit package system comprising: providing a lead frame; forming an integrated circuit package including the lead frame; providing a selectively exposed area on the lead frame; and coating a conductive shielding layer on the integrated circuit package for coupling the selectively exposed area.... Agent: Law Offices Of Mikio Ishimaru

20090146269 - Integrated circuit package system with shield: An integrated circuit package system includes: forming a first lead and a second lead; connecting an integrated circuit die with the first lead; forming an encapsulation over the integrated circuit die, the first lead, and the second lead with a portion of a top side of the second lead exposed;... Agent: Law Offices Of Mikio Ishimaru

20090146267 - Secure connector grid array package: Methods, systems, IC packages, and electrical devices for providing data security for ICs. A substrate-on-substrate connector grid array package with an electrical shield can protect sensitive information in a secure IC from being accessed by physical attacks. A current flow in the electrical shield can be monitored for disturbances which... Agent: Fish & Richardson P.C.

20090146272 - Electronic device: Embodiments provide an electronic device including a carrier defining a first major surface, a chip attached to the first major surface, an array of leads connected to the first major surface, and a thickness of encapsulation material disposed on the first major surface of the carrier. Each lead extends through... Agent: Dicke, Billig & Czaja

20090146271 - Integrated circuit package-in-package system: An integrated circuit package-in-package system is provided including mounting first integrated circuits stacked in a first offset configuration over a die-attach paddle having a first edge and a second edge, opposing the first edge; connecting the first integrated circuits and a second edge lead adjacent the second edge; mounting second... Agent: Law Offices Of Mikio Ishimaru

20090146274 - Integrated circuit packages includng sinuous lead frames: Integrated circuit packages include an integrated circuit mounting substrate having a hole that defines an inner wall of the integrated circuit mounting substrate. An integrated circuit is provided in the hole. A sinuous lead frame extends from the integrated circuit and is connected to the inner wall. The sinuous lead... Agent: Myers Bigel Sibley & Sajovec

20090146273 - Semiconductor device: In a semiconductor device wherein plural pads on a semiconductor element which are connected to function terminals on an external package are arranged in two lines along the periphery of the semiconductor element, an arrangement order of the plural pads on the semiconductor element is made different from an arrangement... Agent: Wenderoth, Lind & Ponack L.L.P.

20090146275 - Lead frame and semiconductor device provided with lead frame: A lead frame and a semiconductor device having a lead frame are disclosed. The lead frame is provided with a mount bed to mount a semiconductor chip, first and second lead terminals and first and second extension portions of band-shapes. The first and the second extension portions extend from sides... Agent: Amin, Turocy & Calvin, LLP

20090146276 - Flip-chip leadframe semiconductor package: A flip-chip leadframe semiconductor package designed to improve mold flow around the leadframe and semiconductor die. An embodiment of the semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulant covering the leadframe and semiconductor die, wherein a portion of the leadframe that is attached... Agent: Sughrue Mion, PLLC

20090146277 - Semiconductor device: A semiconductor device includes: a semiconductor module case; a metal terminal externally extending from within the case; a semiconductor element disposed within the case and electrically connected to the metal terminal; and a printed wiring board having a wiring pattern formed on a surface thereof, the printed wiring board being... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090146278 - Chip-stacked package structure with asymmetrical leadframe: The present invention provides a chip-stacked package structure, comprising: a lead-frame, composed of a plurality of inner leads and a plurality of outer leads, wherein the inner leads comprise a plurality of first inner leads in parallel and a plurality of second inner leads in parallel, and the ends of... Agent: Sinorica, LLC

20090146280 - Circuit member, manufacturing method of the circuit member, and semiconductor device including the circuit member: A circuit member 20 includes a lead frame material 1 having a die pad 3, a lead part 6 to be electrically connected with a semiconductor chip 30, and an outer frame 2 configured to support the die pad and the lead part. The lead frame material includes a resin... Agent: Burr & Brown

20090146279 - Method for attaching a semiconductor die to a leadframe, and a semiconductor device: A semiconductor device comprising a leadframe (4) with a carrier pad (3) bonded thereto, and a die (2) bonded to the carrier pad (3) to form a bonded assembly (5) which is encapsulated in a housing (7) with leads (8) of the leadframe (4) extending therefrom is formed by initially... Agent: Wolf Greenfield & Sacks, P.C.

20090146281 - System in package and fabrication method thereof: There is provided a system-in-package including: a substrate of a sawed base wafer on which a semiconductor circuit is formed; a conductive post formed on a top surface of the substrate; at least one semiconductor chip stacked on the top surface of the substrate; a buried layer formed on the... Agent: Hosoon Lee

20090146285 - Fabrication method of semiconductor package: The present invention provides a semiconductor package and a fabrication method thereof. The method includes the steps of: providing a chip carrier module having a plurality of chip carriers, disposing a plurality of electrical connecting points on the chip carriers, performing chip mounting and molding on the chip carrier module... Agent: Edwards Angell Palmer & Dodge LLP

20090146284 - Molded leadless packages and assemblies having stacked molded leadless packages: Molded leadless packages having improved stacked structures are disclosed. An exemplary molded leadless package includes a die attaching pad, a plurality of leads spaced apart from the die attaching pad at a periphery region of the die attaching pad, a semiconductor chip on the die attaching pad, a plurality of... Agent: Townsend And Townsend And Crew, LLP

20090146282 - Semiconductor package and method of forming similar structure for top and bottom bonding pads: A semiconductor package has a first semiconductor die mounted on a substrate. A conductive via is formed through the substrate. A first RDL is formed on a first surface of the substrate in electrical contact with the conductive via and the first semiconductor die. A second RDL is formed on... Agent: Quarles & Brady LLP

20090146283 - Stacked-type chip package structure and fabrication method thereof: A stacked-type chip package structure in which stacked chips and stacked flexible circuit boards are disposed on a substrate. A plurality of spacer layers is respectively sandwiched between two adjacent chips and stacked on top of each other. In addition, conductive bumps are disposed on the substrate and between the... Agent: Jianq Chyun Intellectual Property Office

20090146286 - Direct attach interconnect for connecting package and printed circuit board: A direct attach interconnect includes a housing and spring contacts. The housing has top and bottom sides lying in parallel planes defined by x and y axes. Passages extend along the z axis between the top and bottom housing sides. Each spring contact has a middle portion and top and... Agent: Brooks Kushman P.C. / Sun / Stk

20090146288 - Semiconductor device and method of manufacturing the same: A semiconductor element 22 is mounted on a stem 24 where a flat surface serving as the mounting part of the semiconductor element 22 is provided on a part of a cylindrical part, and the stem 24 is inserted and hermetically sealed into a cap 25 such that the cylindrical... Agent: Steptoe & Johnson LLP

20090146287 - Semiconductor device having a chip-size package: Disclosed are a semiconductor device, a method for manufacturing the same, and a method for mounting the same. The method for manufacturing a semiconductor device includes the steps of: preparing a package film having a planar configuration whose region is divided into a device-mounting film portion having a device hole... Agent: Venable LLP

20090146289 - Thermoset polyimides for microelectronic applications: Dendrimer/hyperbranched materials are combined with polyimide to form a low CTE material for use as a dielectric substrate layer or an underfill. In the alternative, ruthenium carbene complexes are used to catalyze ROMP cross-linking reactions in polyimides to produce a class of cross-linkable, thermal and mechanical stable material for use... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090146290 - Interconnect structure and method for semiconductor device: An interconnect method in a semiconductor device may include a step of examining various regions of an inter layer dielectric to identify regions having high densities or concentrations of trench features. A cap insulator layer may be added to the dielectric to assist in outgassing of absorbed impurities from the... Agent: Banner & Witcoff, Ltd.

20090146291 - Semiconductor packages: A semiconductor package includes a semiconductor chip including a semiconductor substrate and a plurality of cell transistors arranged on the semiconductor substrate. Channel regions of the cell transistors have channel lengths that extend in a first direction, and the package further includes a supporting substrate having an upper surface on... Agent: Myers Bigel Sibley & Sajovec

20090146292 - Semiconductor device thermal connection: A semiconductor device thermal connection used to remove heat from a semiconductor device, such as an integrated circuit, includes a metallic barrier layer on the semiconductor device, and a high thermal conductivity material on the metallic barrier layer that joins the semiconductor device to a thermal heat spreader. The metallic... Agent: Renner Otto Boisselle & Sklar, LLP

20090146293 - Flow distribution module and a stack of flow distribution modules: A flow distribution module (5) for distributing a flow of cooling fluid across a surface. Is adapted to be connected to another at least substantially identical module (5). Makes it possible to provide a cooling unit which may be customized to meet specific cooling needs without requiring special adaptation of... Agent: Mccormick, Paulding & Huber LLP

20090146294 - Gasket system for liquid-metal thermal interface: Embodiments of an apparatus are described. This apparatus includes a semiconductor-die layer mechanically coupled to a semiconductor die, and a heat-removal-device layer mechanically coupled to a heat-removal device. Moreover, a thermal-interface material is included between the semiconductor die and the heat-removal device, where the thermal-interface material is mechanically coupled to... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP

20090146295 - Ceramic substrate having thermal via: The present invention relates to a ceramic substrate having a thermal via passing through the substrate for purposes of radiating heat to the outside, wherein the ceramic substrate has a reinforcing structure that divides the opening of the thermal via into two or more parts, and the height of the... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20090146296 - Method of forming high-k dielectric stop layer for contact hole opening: A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The... Agent: HorizonIPPte Ltd

20090146297 - Semiconductor device and method of forming wafer level ground plane and power ring: A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Through hole vias (THV) are formed in the... Agent: Quarles & Brady LLP

20090146298 - Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles: A semiconductor device has a chip (101) with gold studs (212) assembled on a tape substrate (102), which has solder balls (103) for attachment to external parts. The tape substrate (about 30 to 70 μm thick) has on its first surface first copper contact pads (221) covered with a continuous... Agent: Texas Instruments Incorporated

20090146301 - Semiconductor device and method of manufacturing the same: A semiconductor device capable of realizing highly reliable three-dimensional mounting, and a method of manufacturing the same, are provided. A projected electrode 9 is formed in a region outside of an element mounting region of a substrate 5. The projected electrode 9 includes a protruding portion that protrudes from the... Agent: Steptoe & Johnson LLP

20090146299 - Semiconductor package and method thereof: A ball grid array (BGA) structure package includes: a circuit board including a top surface and a bottom surface, and the top surface includes a patterned metal point disposed thereon and the bottom surface includes a metal point corresponding to the patterned conductive point; a semiconductor die includes an active... Agent: Sinorica, LLC

20090146300 - Semiconductor packages and electronic products employing the same: Example embodiments of a semiconductor package are provided. In accordance with an example embodiment, a semiconductor package may include an external terminal connected to a concave surface of a bottom pad, wherein the bottom pad is recessed into a substrate. In accordance with another example embodiment, a semiconductor package may... Agent: Harness, Dickey & Pierce, P.L.C

20090146303 - Flip chip interconnection with double post: A packaged microelectronic assembly includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. Each of the first posts has a width in a direction of the front surface and a height extending from the front surface, wherein... Agent: Tessera Lerner David Et Al.

20090146302 - Method for manufacturing semiconductor device: Embodiments relate to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device capable of simplifying a silicide manufacturing process using a photo resist overhang structure. According to embodiments, a surface is subjected to a monochlorobenzene coating processing to cure the surface... Agent: Sherr & Vaughn, PLLC

20090146304 - Carbon nanotube integrated circuit devices and methods of fabrication therefor using protected catalyst layers: A method of fabricating an integrated circuit device is provided. The method includes sequentially forming a lower interconnection layer, a catalyst layer, and a buffer layer on a semiconductor substrate, forming an interlayer dielectric layer to cover the buffer layer, forming a contact hole through the interlayer dielectric layer so... Agent: Myers Bigel Sibley & Sajovec

20090146305 - Post passivation interconnection schemes on top of the ic chips: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a... Agent: Megica Corporation

20090146306 - Semiconductor device with epitaxial c49-titanium silicide (tisi2) layer and method for fabricating the same: The present invention relates to a semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. This titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090146307 - Top layers of metal for high performance ic's: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses... Agent: Mou-shiung Lin Room 301/302, No. 47

20090146308 - Nitride semiconductor device and method of manufacturing the same: A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, and on a p-type contact layer of... Agent: Leydig Voit & Mayer, Ltd

20090146309 - Semiconductor device and method of manufacturing the same: A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090146311 - Interconnect structure: An interconnect structure is disposed on a substrate with a conductive part thereon and includes a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a first... Agent: Jianq Chyun Intellectual Property Office

20090146310 - Semiconductor device and manufacturing method thereof: A semiconductor device subjected to an optical annealing process by radiation light whose principal wavelength is 1.5 μm or less includes a circuit pattern region formed on a semiconductor substrate, and a dummy pattern region formed separately from the circuit pattern region on the semiconductor substrate. The circuit pattern region... Agent: Charles N.j. Ruggiero, Esq. Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20090146312 - Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods: Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods are disclosed herein. One embodiment, for example, is directed to a method of processing a microelectronic workpiece including a semiconductor substrate having a plurality of microelectronic dies. The individual dies include integrated circuitry and a terminal... Agent: Perkins Coie LLP Patent-sea

20090146313 - Semiconductor device: In a semiconductor device according to an aspect of the invention, a direction in which a fourth metal interconnection layer located on a semiconductor layer is extended is orthogonal to a direction in which third interconnection layers ML30 and ML37 located on the fourth interconnection layer are extended. Thus, even... Agent: Mcdermott Will & Emery LLP

20090146315 - Integrated circuit package-on-package stacking system and method of manufacture thereof: An integrated circuit package-on-package stacking system includes: providing a first integrated circuit package, mounting a metalized interposer substrate over the first integrated circuit package, attaching a stiffener integrated with the metalized interposer substrate and having dimensions within package extents, and attaching a second integrated circuit package on the metalized interposer... Agent: Law Offices Of Mikio Ishimaru

20090146314 - Semiconductor device: A semiconductor device includes a first wiring board having a semiconductor element connection pad; a semiconductor element connected to the semiconductor element connection pad; and a second wiring board facing the semiconductor element and the first wiring board, the second wiring board being electrically connect to the first wiring board.... Agent: Ipusa, P.l.l.c

20090146316 - Flip-chip assembly with organic chip carrier having mushroom-plated solder resist opening: Disclosed are embodiments of a flip-chip assembly and method using lead-free solder. This assembly incorporates mushroom-plated metal layers that fill and overflow solder resist openings on an organic laminate substrate. The lower portion of metal layer provides structural support to its corresponding solder resist opening. The upper portion (i.e., cap)... Agent: International Business Machines Corporation Dept. 18g

20090146318 - Multilayer wiring board and semiconductor device: A multilayer wiring board includes: a substrate; connection pads arranged in a square grid fashion; and wiring patterns. Relationship between the connection pads and the wiring patterns satisfies: {(Ndl+1)P−d−s}/(w+s)>2Ndr+Ndl(a+1)+2a, wherein P is a pitch of the connection pads, d is a diameter of the connection pads, s is a minimum... Agent: Drinker Biddle & Reath (dc)

20090146317 - Package substrate having electrically connecting structure: A package substrate having an electrically connecting structure are provided. The package substrate include: a package substrate substance with at least a surface having a plurality of electrically connecting pads formed thereon, allowing an insulating protective layer to be formed on the surface of the package substrate substance and the... Agent: Pearne & Gordon LLP

20090146319 - Semiconductor device: A semiconductor device which can prevent damage to an ESD protection device by pressure when bonding is carried out, while having a pad configuration that can ensure bonding reliability, with the semiconductor device being made as small as possible. A bonding area that is an area for wire bonding with... Agent: Sughrue Mion, PLLC

20090146320 - Fabricated adhesive microstructures for making an electrical connection: An integrated circuit chip has one or more electrically conductive nano-fibers formed on one or more contact pads of the integrated circuit chip. The one or more electrically conductive nano-fibers are configured to provide an adhesive force by intermolecular forces and establish an electrical connection with one or more contact... Agent: Morrison & Foerster LLP

20090146321 - Wire bonding personalization and discrete component attachment on wirebond pads: Inner wire bond pads are formed within a peripheral region of a semiconductor chip and at least one bonding wire is attached to the inner wire bond pads. The semiconductor chip may be customized for a specific configuration of choice by wiring inner wire bond pads. Alternately, the bonding wires... Agent: Scully, Scott, Murphy & Presser, P.C.

20090146322 - Method of eliminating a lithography operation: Methods of semiconductor device fabrication are disclosed. An exemplary method includes processes of depositing a first pattern on a semiconductor substrate, wherein the first pattern defines wide and narrow spaces; depositing spacer material over the first pattern on the substrate; etching the spacer material such that the spacer material is... Agent: Sheppard Mullin Richter & Hampton LLP

20090146324 - Phenoxyphenyl polysiloxane composition and method for making and using same: A curable phenoxyphenyl polysiloxane composition is disclosed. A cured phenoxyphenyl polysiloxane composition is further disclosed, along with a method of making that cured phenoxyphenyl polysiloxane composition from the curable phenoxyphenyl silicon composition. An encapsulated semiconductor device, and a method of making that encapsulated semiconductor device by coating a semiconductor element... Agent: Jonathan D. Baskin Rohm And Haas Electronic Materials LLC

20090146323 - Resin for optical-semiconductor-element encapsulation containing polyaluminosiloxane and optical semiconductor device obtained with the same: The present invention relates to a resin for optical-semiconductor-element encapsulation which comprises a polyaluminosiloxane obtained by reacting a silicon compound with an aluminum compound, and an optical semiconductor device obtained with the resin. The resin has satisfactory light-transmitting properties and low hygroscopicity and suffers no discoloration when used at a... Agent: Sughrue-265550

20090146325 - Alignment for backside illumination sensor: An apparatus and manufacturing method thereof, wherein an integrated circuit is located in a first region of a substrate having first and second opposing major surfaces, and wherein an alignment mark is located in a second region of the substrate and extends through the substrate between the first and second... Agent: Haynes And Boone, LLPIPSection

20090146326 - Method and structures for indexing dice: A method of indexing a plurality of dice obtained from a material wafer comprising a plurality of stacked material layers, each die being obtained in a respective die position in the wafer, the method including providing a visible index on each die indicative of the respective die position, wherein providing... Agent: Graybeal Jackson LLP

20090140229 - Active material devices with containment layer: An active material electronic device is described with a containment layer. The device includes an active chalcogenide, pnictide, or phase-change material in electrical communication with an upper and lower electrode. The device includes a containment layer formed over the active material that prevents escape of volatilized matter from the active... Agent: Ovonyx, Inc

20090140230 - Memory cell device with circumferentially-extending memory element: A memory device comprises a contact and a pillar-shaped structure on the contact. The pillar-shaped structure includes a conductive inner element surrounded by a memory outer layer. A transition region is located at the memory outer layer above said contact. The conductive element may directly contact said contact.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090140233 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device having a large storage capacity and stabilized rewriting conditions in which a memory cell includes a nonvolatile recording material layer, a selector element and a semiconductor layer provided between the nonvolatile recording material layer and the selector element and having a thickness ranging from 5... Agent: Mattingly & Malur, P.C.

20090140232 - Resistive memory element: An integrated circuit including a resistive memory element is described. The resistive memory element includes a first solid electrolyte layer including a metal doped glass material, the glass material being at least partially amorphous, and a second solid electrolyte layer including the metal doped glass material. The resistive memory element... Agent: Slater & Matsil, L.L.P.

20090140231 - Semiconductor device and method of manufacturing the same: It is an object of the present invention to provide a technique in which a high-performance and highly reliable semiconductor device can be manufactured at low cost with high yield. A memory device according to the present invention has a first conductive layer including a plurality of insulators, an organic... Agent: Eric Robinson

20090140234 - Semiconductor device and method of manufacturing the same: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST... Agent: Mcdermott Will & Emery LLP

20090140239 - Compounds for organic semiconductor device having triazine group, organic semiconductor thin film and organic semiconductor device comprising the same, and methods of preparing them: y

20090140238 - Flat screen detector: A flat screen detector has a substrate with a transistor matrix thereon, a photodetector, and a passivation layer. The photodetector includes a structured first electrode including a number of sub-electrodes, a second electrode, and a photoactive layer between the first and second electrodes. The passivation layer is located between the... Agent: Schiff Hardin, LLP Patent Department

20090140241 - Organic semiconductor material, organic semiconductor thin film and organic semiconductor device: where each of R1 to R10 may be independently the same substituents or different substituents but all of R1, R4, R5, R6, R9 and R10 may never be hydrogen atoms at the same time, and where each of R1 to R10 is at least one kind of substituent selected from... Agent: K&l Gates LLP

20090140240 - Organic thin film transistor: A thin film transistor comprising at least three terminals consisting of a gate electrode, a source electrode and a drain electrode; an insulator layer and an organic semiconductor layer on a substrate, which controls its electric current flowing between the source and the drain by applying a electric voltage across... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090140235 - Semiconductor element and process for producing the same: The present invention provides a thin film transistor having excellent formability and processability, and particularly a thin film transistor using plastics as a substrate; an organic semiconductor as an active layer; and SiO2 thin films formed by coating as a sealing layer and a gate insulating layer, and a process... Agent: Oliff & Berridge, PLC

20090140236 - Thin film transistors: A thin film transistor has a semiconducting layer comprising a semiconductor and surface-modified carbon nanotubes. The semiconducting layer has improved charge carrier mobility.... Agent: Fay Sharpe / Xerox - Rochester

20090140237 - Thin film transistors: A thin film transistor has a semiconducting layer comprising a semiconductor and a mixture enriched in metallic carbon nanotubes. The semiconducting layer has improved charge carrier mobility.... Agent: Fay Sharpe / Xerox - Rochester

20090140243 - Oxide semiconductor thin film transistors and fabrication methods thereof: Oxide semiconductor thin film transistors (TFT) and methods of manufacturing the same are provided. The methods include forming a channel layer on a substrate, forming source and drain electrodes at opposing sides of the channel layer, and oxidizing a surface of the channel layer by placing an oxidizing material in... Agent: Harness, Dickey & Pierce, P.L.C

20090140242 - Semiconductor substrate with solid phase epitaxial regrowth with reduced junction leakage and method of producing same: Method of producing a semiconductor device, comprising: a) providing a semiconductor substrate, b) making a first amorphous layer in a top layer of the semiconductor substrate by a suitable implant, the first amorphous layer having a first depth, c) implanting a first dopant into the semiconductor substrate to provide the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090140246 - Method and test structure for monitoring cmp processes in metallization layers of semiconductor devices: By forming a large metal pad and removing any excess material thereof, a pronounced recessed surface topography may be obtained, which may also affect the further formation of a metallization layer of a semiconductor device, thereby increasing the probability of maintaining metal residues above the recessed surface topography. Consequently, by... Agent: Williams, Morgan & Amerson

20090140248 - On-chip test circuit for an embedded comparator: A semiconductor chip including an embedded comparator is provided with an on-chip test circuit for the comparator. The test circuit includes an analog input unit which, during a test mode of the chip, produces a range of analog voltage signals that are applied to a first input of the comparator... Agent: Slater & Matsil LLP

20090140247 - Semiconductor device and method of manufacturing semiconductor device: The semiconductor device of the present invention includes a first insulating film on a substrate having a first region and a second region, a light shielding film formed in the first region and an interconnect film formed in the second region in the first insulating film and a second insulating... Agent: Young & Thompson

20090140244 - Semiconductor device including a die region designed for aluminum-free solder bump connection and a test structure designed for aluminum-free wire bonding: In sophisticated semiconductor devices including copper-based metallization systems, a substantially aluminum-free bump structure in device regions and a substantially aluminum-free wire bond structure in test regions may be formed on the basis of a manufacturing process resulting in identical final dielectric layer stacks in these device areas. The number of... Agent: Williams, Morgan & Amerson

20090140245 - Structure for a method and structure for screening nfet-to-pfet device performance offsets within a cmos process: A design structure of a method of screening on-chip variation in NFET-to-PFET device performance for as-manufactured integrated circuits (ICs) made using a CMOS process. The method includes defining an acceptable frequency- or period-NFET-to-PFET device performance envelope by simulating a pair of ring oscillators, one of which contains only NFET transistors... Agent: Downs Rachlin Martin PLLC

20090140249 - Integrated circuit device and method for manufacturing integrated circuit device: An object of the present invention is to provide a structure of a thin film circuit portion and a method for manufacturing a thin film circuit portion by which an electrode for connecting to an external portion can be easily formed under a thin film circuit. A stacked body including... Agent: Eric Robinson

20090140250 - Semiconductor device: An object is to reduce off-current of a thin film transistor. Another object is to improve electric characteristics of a thin film transistor. Further, it is still another object to improve image quality of a display device using the thin film transistor. An aspect of the present invention is a... Agent: Eric Robinson

20090140251 - Thin film transistor, display device including thin film transistor, and method for manufacturing the same: A thin film transistor having excellent electric characteristics, a display device including the thin film transistor, and a manufacturing method thereof are provided. In a thin film transistor in which a microcrystalline germanium film, a gate insulating film in contact with one surface of the microcrystalline germanium film, and a... Agent: Fish & Richardson P.C.

20090140252 - Image sensor and method for manufacturing the sensor: An image sensor and a method of manufacturing the sensor. A method of manufacturing an image sensor may include at least one of: Forming a gate over a semiconductor substrate. Sequentially depositing a plurality of insulating films over the semiconductor substrate and the gate. Removing an upper-most insulating film of... Agent: Sherr & Vaughn, PLLC

20090140253 - Tft arrangement for display device: A new TFT arrangement is demonstrated, which enables prevention of TFT to be formed over a joint portion between the adjacent SOI layers prepared by the process including the separation of a thin single crystal semiconductor layer from a semiconductor wafer. The TFT arrangement is characterized by the structure where... Agent: Eric Robinson

20090140254 - Thin film transistor and flat panel display device including the same: A flat panel display device is disclosed. In one embodiment, the flat panel display device includes i) a semiconductor layer including a channel region and a groove, wherein the channel region electrically connects a source electrode and a drain electrode, and the groove is configured to separate the channel region... Agent: Knobbe Martens Olson & Bear LLP

20090140255 - Crystalline semicondutor film and method for manufacturing the same: An island of a crystalline semiconductor according to the present invention has an upper surface and a sloped side surface, which are joined together with a curved surface. Crystal grains in a body portion of the island, including the upper surface, and crystal grains in an edge portion of the... Agent: Nixon & Vanderhye, PC

20090140257 - Film formation method, thin-film transistor and solar battery: After a gate oxide film 10 has been formed on a silicon substrate G, a first step of forming a microcrystalline silicon film by high electron density plasma of an electron temperature of 2.0 eV or less and a second step of forming an ultra-microcrystalline silicon film by high electron... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090140256 - Thin film transistor and semiconductor device: An impurity element imparting one conductivity type is included in a layer close to a gate insulating film of layers with high crystallinity, so that a channel formation region is formed not in a layer with low crystallinity which is formed at the beginning of film formation but in a... Agent: Eric Robinson

20090140258 - Transistor and display and method of driving the same: A field-effect transistor including an electrically conductive substrate; a first insulating film coating the electrically conductive substrate; a gate electrode disposed on the electrically conductive substrate with the first insulating film interposed therebetween; a source electrode; a drain electrode opposing the source electrode with the channel therebetween; a second insulating... Agent: Fitzpatrick Cella Harper & Scinto

20090140259 - Thin film transistor, display device having thin film transistor, and method for manufacturing the same: A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device in a high yield are provided. In the thin film transistor, a gate electrode, a gate insulating film, crystal grains that... Agent: Fish & Richardson P.C.

20090140260 - Liquid crystal display device and fabricating method thereof: A method for fabricating a liquid crystal display (LCD) device comprises forming an active pattern and a data line on a substrate, the active pattern including a source, a drain, and a channel regions; a first insulation film on a portion of the substrate; forming a gate electrode in a... Agent: Mckenna Long & Aldridge LLP

20090140261 - Mos solid-state image device and method of manufacturing the same: A sidewall film 121 in a digital portion has a multilayer structure including at least an offset sidewall film 107b located inside. An extension diffusion layer 110 is formed adjacent to a source/drain diffusion region 111 through the offset sidewall film 107b and a gate electrode 102 as a mask.... Agent: Steptoe & Johnson LLP

20090140262 - Field-effect transistor: A field-effect transistor includes a carrier transport layer made of nitride semiconductor, a gate electrode having first and second sidewall surfaces on first and second sides, respectively, an insulating film formed directly on the gate electrode to cover at least one of the first and second sidewall surfaces, first and... Agent: Kratz, Quintos & Hanson, LLP

20090140263 - Method for diamond surface treatment and device using diamond thin film: A method for surface treatment of diamond comprising exposing the surface of diamond to UV light containing wavelengths of 172 nm to 184.9 nm and 253.7 nm at an integrated exposure of 10 to 5,000 J/cm2 in an environment of an atmosphere having an oxygen concentration of 20 to 100%... Agent: Ostrolenk Faber Gerb & Soffen

20090140264 - Semiconductor device: A hetero semiconductor corner region, which is a current-concentration relief region that keeps a reverse bias current from concentrating on the convex corner, is arranged in a hetero semiconductor region. Thereby, a current concentration on the convex corner can be prevented. As a result, an interrupting performance can be improved... Agent: Foley And Lardner LLP Suite 500

20090140265 - Light emitting device and electronic apparatus: A light emitting device includes a substrate having transparency, a light emitting element that emits light at least to the substrate side, and a light detecting element that is formed between the light emitting element and the substrate. The light detecting element is formed along an outer frame of the... Agent: Oliff & Berridge, PLC

20090140266 - Package including oriented devices: An package such as an optocoupler package is disclosed. The optocoupler package includes a leadframe structure comprising a first die attach pad comprising a first die attach pad surface and a second die attach pad with a second die attach pad surface. The optocoupler package further has an optical emitter... Agent: Townsend And Townsend And Crew, LLP

20090140267 - Semiconductor light emitting device and manufacturing method thereof: Disclosed are a semiconductor light emitting device comprising a single crystalline buffer layer and a manufacturing method thereof. The semiconductor light emitting device comprises a single crystalline buffer layer, and a compound semiconductor structure comprising III and V group elements on the single crystalline buffer layer.... Agent: Birch Stewart Kolasch & Birch

20090140269 - Display apparatus and method of manufacturing the same: In a display apparatus and a method of manufacturing the display apparatus, a gate line, a data line, and a plurality of layers are formed on an array substrate on which a pixel area, a pad area, and a peripheral area are defined. During the forming processes of the gate... Agent: Haynes And Boone, LLPIPSection

20090140270 - Display device and method for manufacturing thereof: An object is to provide a system-on-panel display device including a display portion and a peripheral circuit for controlling display on the display portion over one substrate, which can operate more accurately. The display device has a display portion provided with a pixel portion including a plurality of pixels and... Agent: Eric Robinson

20090140268 - Led array module and method of packaging the same: An LED array module includes a drive IC structure, at least one LED array, an adhesive element, and a first conductive structure. The drive IC structure has a concave groove formed on a top side thereof. The at least one LED array is received in the at least one concave... Agent: Rosenberg, Klein & Lee

20090140271 - Light emitting unit: A light emitting unit has a chamber. The light emitting unit includes at least one substrate, a plurality of light emitting diode (LED) dies and a gel or a fluid. The LED dies are disposed on the substrate and in the chamber. At least two LED dies are electrically connected... Agent: Birch Stewart Kolasch & Birch

20090140272 - Solid-state light source: A solid-state light source includes at least one stack of light emitting elements. The elements are an inorganic light emitting diode chip and at least one wavelength conversion chip or the elements are a plurality of light emitting diode chips and one or more optional wavelength conversion chips. The wavelength... Agent: Goldeneye, Inc.

20090140273 - Epitaxial wafer for semiconductor light emitting diode and semiconductor light emitting diode using same: An epitaxial wafer for a semiconductor light emitting device according to the present invention in which at least an n-type cladding layer formed with a mixed crystal made of an AlGaInP material, an active layer, a p-type Mg-doped cladding layer, and a p-type contact layer are stacked successively in that... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090140274 - Iii-nitride light emitting device including porous semiconductor layer: A semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown over a porous III-nitride region. A III-nitride layer comprising InN is disposed between the light emitting layer and the porous III-nitride region. Since the III-nitride layer comprising InN is grown... Agent: Patent Law Group LLP

20090140280 - Light-emitting device: A light-emitting device comprises a substrate, an epitaxial structure formed on the substrate including a first semiconductor layer, a second semiconductor layer, and a light-emitting layer formed between the first semiconductor layer and the second semiconductor layer. A trench is formed in the epitaxial structure to expose a part of... Agent: Bacon & Thomas, PLLC

20090140275 - Nanoparticle coupled to waveguide: A nanoparticle is able to emit single photons. A waveguide is coupled to the nanoparticle and able to receive the single photons. A backreflector is optically coupled to the waveguide and configured to reflect the single photons toward the waveguide.... Agent: Hewlett Packard Company

20090140276 - Optical functional film and method of manufacturing the same: A light emitting element includes a light emitting layer emitting light and a refractive index composite structure layer arranged in a light path of the light output from the light emitting layer. The refractive index composite structure layer includes a structure having characteristics (1) to (4) as follows: (1) an... Agent: Sharp Kabushiki Kaisha C/o Keating & Bennett, LLP

20090140281 - Semiconductor light emitting device and a method of manufacturing the same: Disclosed is a semiconductor light emitting device comprising a seed layer, a first conductive semiconductor layer into which the seed layer is partially inserted, a first electrode electrically connected to the first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, a second conductive semiconductor layer under... Agent: Birch Stewart Kolasch & Birch

20090140277 - Solide-state light source: A solid-state light source includes a substrate, a solid-state light-emitting chip, a plurality of micro-members and a light-permeable encapsulation. The substrate has a substantially flat surface. The solid-state light-emitting chip is arranged on the substantially flat surface of the substrate and electrically connected to the substrate. The micro-members are arranged... Agent: PCe Industry, Inc. Att. Steven Reiss

20090140279 - Substrate-free light emitting diode chip: A light emitting diode (LED) chip has a multilayer semiconductor structure that is at least 10 microns thick and does not require an attached growth substrate or transfer substrate for structural rigidity or support. The multilayer semiconductor structure includes a first doped layer, a second doped layer and an active... Agent: William Propp, Esq. Goldeneye, Inc.

20090140278 - Tunable led module: The objective of the invention is to provide with a tunable LED module capable of easily selecting a wavelength and reducing particular parts, comparing to that of prior art. The tunable LED module according to the present invention is applicable to a certain short range communication. The module comprises: an... Agent: Nixon & Vanderhye, PC

20090140282 - Led structure for flip-chip package and method thereof: LED structure can be packaged by using flip-chip package. An LED structure is covered by a conduction enhancing layer. A bumping area definition layer is then formed on the conduction enhancing layer to expose bumping area portions with p-pad and n-pad underneath, and a bumping pad is then formed over... Agent: Bacon & Thomas, PLLC

20090140283 - Light emitting device: An object of the present invention is to provide a light emitting device in which variations in an emission spectrum depending on a viewing angle with respect to a side from which luminescence is extracted are decreased. A light emitting device according to the invention has a transistor, an insulating... Agent: Nixon Peabody, LLP

20090140285 - Light emitting device having function of heat-dissipation and manufacturing process for such device: A light-emitting device of a light-emitting diode (LED) and a manufacture method thereof are provided. The light-emitting device includes a post-like metal material, a printed circuit board, conductors, insulators, light-emitting diodes, wires, and an encapsulating material. The light-emitting device has through holes, in which conductors are disposed and surrounded with... Agent: Jianq Chyun Intellectual Property Office

20090140284 - Transparent inorganic oxide dispersion and iorganic oxide particle-containing resin composition, composition for sealing light emitting element and light emitting element, hard coat film and optical functional film and optical component, and method for pr: The present invention provides a transparent inorganic oxide dispersion which makes it possible to improve the refractive index and mechanical characteristics and to maintain transparency by modifying the surface of inorganic oxide particles with a surface modifier having one or more reactive functional groups; and an inorganic oxide particle-containing resin... Agent: Merchant & Gould PC

20090140287 - Iii nitride crystal substrate, and light-emitting device and method of its manufacture: Toward making available III nitride crystal substrates advantageously employed in light-emitting devices, and light-emitting devices incorporating the substrates and methods of manufacturing the light-emitting devices, a III nitride crystal substrate has a major face whose surface area is not less than 10 cm2 and, in a major-face principal region excluding... Agent: Judge Patent Associates

20090140286 - Production method of group iii nitride semiconductor element: In the inventive production method, the Group III nitride semiconductor element has an n-type layer, an active layer and a p-type layer, which comprise a Group III nitride semiconductor, on a substrate in this order, wherein, during or/and after growth of the n-type layer and before growth of the active... Agent: Sughrue Mion, PLLC

20090140288 - High ion/ioff soi mosfet using body voltage control: A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In a particular case, the MOSFET may comprise another region... Agent: Water D. Fields Bebostad Fields, LLP

20090140289 - Semiconductor device: Each of first base regions of sequentially layered first IGBT and second IGBT has a peripheral section in the vicinity of the side face of the semiconductor substrate. Each of the IGBTs includes a P-type peripheral base region that is adjacent to the peripheral section of the first base region... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090140290 - Semiconductor component including a short-circuit structure: A semiconductor component including a short-circuit structure. One embodiment provides a semiconductor component having a semiconductor body composed of doped semiconductor material. The semiconductor body includes a first zone of a first conduction type and a second zone of a second conduction type, complementary to the first conduction type, the... Agent: Dicke, Billig & Czaja

20090140291 - Photo-detector for detecting image signal of infrared laser radar and method of manufacturing the same: A photo-detector, in which metal wiring for connecting electrodes is arranged on a planarized surface and thus the metal wiring arrangement is simplified, and a method of manufacturing the same are provided. The photo-detector includes a multi-layer compound semiconductor layer formed on a compound semiconductor substrate. A number of p-n... Agent: Ladas & Parry LLP

20090140292 - Integrated circuit and method of fabrication thereof: A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a... Agent: HorizonIPPte Ltd

20090140294 - hetero-structured, inverted-t field effect transistor: The present invention provides a method of forming a transistor. The method includes forming a first layer of a first semiconductor material above an insulation layer. The first semiconductor material is selected to provide high mobility to a first carrier type. The method also includes forming a second layer of... Agent: Williams, Morgan & Amerson

20090140295 - Gan-based semiconductor device and method of manufacturing the same: A GaN-based semiconductor device includes a silicon substrate; an active layer of a GaN-based semiconductor formed on the silicon substrate; a trench formed in the active layer and extending from a top surface of the active layer to the silicon substrate; a first electrode formed on an internal wall surface... Agent: Kubotera & Associates, LLC

20090140293 - Heterostructure device and associated method: A heterostructure device or article includes a carrier transport layer, a back channel layer and a barrier layer. The carrier transport layer has a first surface and a second surface opposing to the first surface. The back channel layer is secured to the first surface of the carrier transport layer... Agent: General Electric Company Global Research

20090140296 - Epitaxial growth of cubic crystalline semiconductor alloys on basal plane of trigonal or hexagonal crystal: Hetero-epitaxial semiconductor materials comprising cubic crystalline semiconductor alloys grown on the basal plane of trigonal and hexagonal substrates, in which misfit dislocations are reduced by approximate lattice matching of the cubic crystal structure to underlying trigonal or hexagonal substrate structure, enabling the development of alloyed semiconductor layers of greater thickness,... Agent: National Aeronautics And Space Administration Langley Research Center

20090140297 - Self-alignment scheme for a heterojunction bipolar transistor: Embodiments herein present a structure, method, etc. for a self-alignment scheme for a heterojunction bipolar transistor (HBT). An HBT is provided, comprising an extrinsic base, a first self-aligned silicide layer over the extrinsic base, and a nitride etch stop layer above the first self-aligned silicide layer. A continuous layer is... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090140298 - Semiconductor device and method for manufacturing the device: Embodiments relate to a layout structure of a dual port SRAM and a method for forming a SRAM. According to embodiments, a structure where a plurality lines and vias are electrically connected may include first lines that may be electrically connected to a cell region of a memory cell, and... Agent: Sherr & Vaughn, PLLC

20090140299 - Memory with high dielectric constant antifuses adapted for use at low voltage: A memory array having memory cells comprising a diode and an antifuse can be made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and by using a diode having a lower band... Agent: Dugan & Dugan, PC

20090140300 - Electronic tag chip: In order to extend the communication distance of an electronic tag chip, it is required to reduce power consumption of the electronic tag chip. After having formed capacitors and diodes on an SOI (Silicon on Insulator), remove a silicon substrate of the SOI. It becomes possible to reduce the capacitors... Agent: Mattingly & Malur, P.C.

20090140301 - Reducing contact resistance in p-type field effect transistors: Reducing contact resistance in p-type field effect transistors is generally described. In one example, an apparatus includes a first semiconductor substrate, a first noble metal film including palladium (Pd) coupled with the first semiconductor substrate, a second noble metal film including platinum (Pt) coupled with the first noble metal film,... Agent: Cool Patent, P.C. C/o Cpa Global

20090140303 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the same includes forming a via pattern having a matrix form in a dielectric layer. The via pattern includes a via slit provided at the center of the via pattern and a plurality of via holes provided at an outer periphery of... Agent: Sherr & Vaughn, PLLC

20090140302 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device according to one embodiment of the invention includes: forming a gate electrode on a semiconductor substrate through a gate insulating film; forming offset spacers on side surfaces of the gate electrode, respectively; etching the semiconductor substrate with a channel region below the offset... Agent: Foley And Lardner LLP Suite 500

20090140305 - Imaging device: A solid-state imaging device, a line sensor and an optical sensor for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio, and a method of operating a solid-state imaging device for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio... Agent: Foley And Lardner LLP Suite 500

20090140304 - Solid-state imaging device and camera: Disclosed is a solid-state imaging device which includes a plurality of pixels in an arrangement, each of the pixels including a photoelectric conversion element, pixel transistors including a transfer transistor, and a floating diffusion region, in which the channel width of transfer gate of the transfer transistor is formed to... Agent: Sonnenschein Nath & Rosenthal LLP

20090140306 - Semiconductor device and manufacturing method thereof: There is formed a gate electrode (word line) via a gate insulating film on a semiconductor substrate, the gate electrode extending in the direction inclining at an angle of approximately 45 degrees to the extending direction of an element region. The element region is divided into three portions by the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090140307 - Conductive line comprising a capping layer: An integrated circuit includes a conductive line, the conductive line having a conductive layer made of a metal or a first compound including a metal and a capping layer made of a second compound comprising the metal, the capping layer being in contact with the conductive layer, the first compound... Agent: Thomas G. Eschweiler, Esq. Eschweiler & Associates, LLC

20090140308 - Semiconductor device having capacitor formed on plug, and method of forming the same: A semiconductor device includes a silicon substrate, a capacitor element having a lower electrode, a capacitor dielectric film, a TiN film, and a W film, and an interlayer insulation film covering the end and a portion of the upper surface of the lower electrode and disposed with a concave portion... Agent: Mcginn Intellectual Property Law Group, PLLC

20090140309 - Semiconductor device with less power supply noise: A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is provided in a first well... Agent: Young & Thompson

20090140310 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the semiconductor device in which a micro controller unit (MCU) and a flash memory having the same structure as that of a logic circuit of the MCU are formed in the same chip.... Agent: Sherr & Vaughn, PLLC

20090140311 - Method of fabricating semiconductor device having storage capacitor and higher voltage resistance capacitor and semiconductor device fabricated using the same: Provided are a method of fabricating a semiconductor device having different kinds of capacitors, and a semiconductor device formed using the same. In a fabrication process, after preparing a substrate including a storage capacitor region and a higher voltage resistance capacitor region, a lower electrode layer may be formed on... Agent: Harness, Dickey & Pierce, P.L.C

20090140313 - Nonvolatile memory devices and methods of forming the same: A method of forming nonvolatile memory devices according to example embodiments of the present invention includes forming a device isolation layer defining active regions in a semiconductor substrate; forming a plurality of transistors on the active regions, the plurality of transistors comprising a pair of adjacent string selection transistors, a... Agent: Harness, Dickey & Pierce, P.L.C

20090140312 - Semiconductor storage device and manufacturing method thereof: A semiconductor storage device include a semiconductor substrate, an insulating layer provided on the semiconductor substrate and having an opening, a semiconductor layer provided on the insulating layer, the semiconductor layer having a recess at a center of a surface thereof above the opening, a memory cell unit provided on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090140314 - Flash memory device and method of manufacturing the same: Embodiments relate to a flash memory device and a method of manufacturing the same that may include a tunnel oxide layer on and/or over a semiconductor substrate having source and drain regions. The tunnel oxide layer may have a first width The flash memory device may include a first polysilicon... Agent: Sherr & Vaughn, PLLC

20090140317 - Multiple layer floating gate non-volatile memory device: The disclosed systems and methods relate to floating gate non-volatile memory cells, with a floating gate comprising at least two layers constructed in different conductive or semiconductive materials. At least two of the layers of the floating gate are separated by an intermediate dielectric layer having a predetermined thickness enabling... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20090140316 - Semiconductor memory device and method of fabricating the same: A semiconductor memory device includes an insulating film formed on a semiconductor substrate, a plurality of active areas formed on the insulating film from a semiconductor layer which is formed integrally with the substrate through openings of the insulating film, the active areas being formed by being divided into a... Agent: Amin, Turocy & Calvin, LLP

20090140315 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device comprises: a plurality of transistors having a stacked-gate structure, each transistor including a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090140318 - Nonvolatile memories with higher conduction-band edge adjacent to charge-trapping dielectric: In a nonvolatile memory, the tunnel dielectric (150) has a surface in physical contact with the charge trapping dielectric (160) and also has a surface in physical contact with a semiconductor region providing the active area (120, 130, 140). Under the vacuum level, the bottom edge of the conduction band... Agent: Haynes And Boone, LLPIPSection

20090140320 - Nonvolatile memory device and method of forming the nonvolatile memory device including giving an upper portion of an insulating layer an etching selectivity with respect to a lower portion: A nonvolatile memory device and a method of forming a nonvolatile memory device are provided. The nonvolatile memory device includes an active region of a semiconductor substrate defined by a device isolation layer, a tunnel insulating structure disposed on the active region, and a charge storage structure disposed on the... Agent: Volentine & Whitt PLLC

20090140319 - Semiconductor memory device and method of fabricating the same: A semiconductor memory devices and a method of fabricating the same includes sequentially stacking a tunnel insulating layer, a first nano-grain film, a conductive layer for a floating gate, and a second nano-grain film over a semiconductor substrate, forming a trench by etching the second nano-grain film, the conductive layer... Agent: Lowe Hauptman Ham & Berner, LLP

20090140325 - Forming metal-semiconductor films having different thicknesses within different regions of an electronic device: A method of forming an electronic device is provided that includes selectively implanting ions into a workpiece, wherein ions are implanted into a first region of the workpiece that includes a semiconductor material, while substantially none of the ions are implanted into a second region of the workpiece that also... Agent: Larson Newman Abel & Polansky, LLP

20090140323 - Integrated circuit having memory cell array including barriers, and method of manufacturing same: An integrated circuit device (e.g., a logic device or a memory device) having (i) a memory cell array which includes a plurality of memory cells (for example, memory cells having electrically floating body transistors) arranged in a matrix of rows and columns, wherein each memory cell includes at least one... Agent: Neil Steinberg

20090140324 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device and a flash memory device in which a tunnel oxide layer and a first polysilicon pattern are formed on and/or over a semiconductor substrate. A second polysilicon pattern and a third polysilicon pattern are formed on and/or over a sidewall of the... Agent: Sherr & Vaughn, PLLC

20090140321 - Semiconductor device and method of fabricating the same: A semiconductor device and a method of fabricating the same are provided. First, a first oxide layer and a nitride layer are formed on a base having a first region and a second region. Next, the nitride layer is oxidized. A part of nitride in the nitride layer moves to... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090140322 - Semiconductor memory device and method of manufacturing the same: A first insulation film (silicon dioxide film) and a second insulation film (aluminum oxide film) are laminated on a surface of a silicon substrate in this order to form a gate insulation film. At least one element (aluminum) of elements, which constitutes the second insulation film but is different from... Agent: Foley And Lardner LLP Suite 500

20090140327 - Semiconductor device and manufacturing method of the same: The vertical trench MOSFET comprises: an N type epitaxial region formed on an upper surface of an N+ type substrate having a drain electrode on a lower surface thereof; a gate trench extending from a front surface into the N type epitaxial region; a gate electrode positioned in the gate... Agent: Mattingly & Malur, P.C.

20090140326 - Short gate high power mosfet and method of manufacture: A short gate high power metal oxide semiconductor field effect transistor formed in a trench includes a short gate having gate length defined by spacers within the trench. The transistor further includes a buried region that extends beneath the trench and beyond a corner of the trench, that effectively shields... Agent: Volentine & Whitt PLLC

20090140328 - Bridged gate finfet: In a fin-type field effect transistor (FinFET) structure, a gate strap is positioned on the top of a gate conductor and runs along the gate conductor. The top of the gate strap is positioned a greater height above the top surface of the substrate than the top of the fin... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090140331 - Method of fabricating high voltage device: A method of fabricating a high voltage device by which an area due to isolation between a source and a drain can be reduced by planarizing a gate in forming a symmetric high voltage device having vertical-type drift regions. Accordingly, the gate is formed in a trench at a height... Agent: Sherr & Vaughn, PLLC

20090140329 - Semiconductor device: A semiconductor device (such as a MOSFET) can prevent a lowering in the reliability of a gate insulating film and can cope with a finer trench pattern. The MOSFET has a plurality of trenches penetrating a p−-type doped region and a gate electrode formed on the interior surface of each... Agent: Fish & Richardson P.c Citigroup Center

20090140332 - Semiconductor device and method of fabricating the same: A semiconductor device and a method of fabricating the same includes a groove formed in a semiconductor substrate, a gate electrode formed in the groove, source/drain regions disposed adjacent sidewalls of the gate electrode, and spacers interposed between the gate electrode and the source/drain regions such that the uppermost surface... Agent: Sherr & Vaughn, PLLC

20090140330 - Semiconductor device and method of manufacturing semiconductor device: The semiconductor device according to the present invention includes a semiconductor layer, a trench formed by digging the semiconductor layer from the surface thereof, a gate insulating film formed on the inner surface of the trench, and a gate electrode made of silicon embedded in the trench through the gate... Agent: Rabin & Berdo, PC

20090140333 - Method for preventing gate oxide damage of a trench mosfet during wafer processing while adding an esd protection module atop: e

20090140334 - Transistor, display driver integrated circuit including a transistor, and a method of fabricating a transistor: A transistor, a display driver integrated circuit having the transistor, and a method for fabricating a transistor are provided. A transistor, according to example embodiments, may include a substrate with a device active region defined by an isolation layer, wherein the device active region may include a source active region,... Agent: Harness, Dickey & Pierce, P.L.C

20090140335 - Drain-extended field effect transistor: A drain-extended field effect transistor includes a drain contact region and a drain extension region. The drain-extended field effect transistor further includes an electrostatic discharge protection region that is electrically connected between the drain contact region and the drain extension region to protect the drain-extended field effect transistor against electrostatic... Agent: Slater & Matsil LLP

20090140337 - Semiconductor device and manufacturing method thereof: A semiconductor device with increased freedom of wirings and a manufacturing method thereof are provided by enabling favorable connection between an upper wiring layer and a lower wiring layer through a semiconductor element. The semiconductor device includes: a first insulating layer over an insulating substrate; a first wiring layer and... Agent: Fish & Richardson P.C.

20090140336 - Silver nanoparticle compositions: s

20090140338 - Method of fabricating patterned soi devices and the resulting device structures: A method and resulting structure for fabricating a FET transistor for an integrated circuit on a silicon oxide (SOI) substrate comprising the steps of forming recesses in a substrate on both sides of a gate on the substrate, implanting oxygen ions into the recesses, and annealing the substrate to convert... Agent: Edward W. Brown

20090140339 - Esd protection device and method for manufacturing the same: Disclosed is an electro-static discharge protection device. The electro-static discharge protection device can include a second conductive type epitaxial layer on a substrate; a second conductive type well on a first region above the second conductive type epitaxial layer; a first conductive type deep well in the second conductive type... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090140340 - Esd protection device structure: An electrostatic discharge (ESD) protective device structure is disclosed. The ESD protection device includes: at least a first conductive type metal-oxide semiconductor (MOS), in which the drain and source of the first conductive type MOS are electrically connected to a first power terminal and a second power terminal separately; at... Agent: North America Intellectual Property Corporation

20090140341 - Independent n-tips for multi-gate transistors: Independent n-tips for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) devices coupled with the semiconductor fin, the one or more PD devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one... Agent: Cool Patent, P.C. C/o Cpa Global

20090140342 - Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical misfet and a vertical misfet, and a method of manufacturing a semiconductor device and a semiconductor device: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090140343 - Lateral diffusion field effect transistor with a trench field plate: A dielectric material layer is formed on a bottom surface and sidewalls of a trench in a semiconductor substrate. The silicon oxide layer forms a drift region dielectric on which a field plate is formed. Shallow trench isolation may be formed prior to formation of the drift region dielectric, or... Agent: Scully, Scott, Murphy & Presser, P.C.

20090140344 - Semiconductor device: A semiconductor device including a SRAM cell may include a data holding unit including a driver transistor and a load transistor, and receiving and holding data; and a data transferring unit including a transfer gate transistor whose source and drain are connected between the data holding unit and one of... Agent: Amin, Turocy & Calvin, LLP

20090140348 - method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approach: By providing a protection layer for suppressing stress relaxation in a tensile-stressed dielectric material during a dual stress liner approach, performance of N-channel transistors may be increased, while nevertheless maintaining a high degree of compatibility with conventional dual stress liner approaches.... Agent: Williams, Morgan & Amerson

20090140346 - Matched analog cmos transistors with extension wells: One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first... Agent: Texas Instruments Incorporated

20090140347 - Method and structure for forming multiple self-aligned gate stacks for logic devices: A method for forming multiple self-aligned gate stacks, the method comprising, forming a first group of gate stack layers on a first portion of a substrate, forming a second group of gate stack layers on a second portion of the substrate adjacent to the first portion of the substrate, etching... Agent: Cantor Colburn LLP - IBM Fishkill

20090140345 - Semiconductor structure including self-aligned deposited gate dielectric: A semiconductor structure, such as a field effect device structure, and more particularly a CMOS structure, includes a gate dielectric that is at least in-part aligned to an active region of a semiconductor substrate over which is located the gate dielectric. The gate dielectric comprises other than a thermal processing... Agent: Scully, Scott, Murphy & Presser, P.C.

20090140349 - Semiconductor integrated circuit device and process for manufacturing the same: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090140350 - Lithography for printing constant line width features: An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is deposited. Angled ion implantation of Ge, B,... Agent: Scully, Scott, Murphy & Presser, P.C.

20090140351 - Mos devices having elevated source/drain regions: A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming a slim spacer on sidewalls of the gate dielectric and the gate electrode; forming a silicon carbon (SiC) region adjacent the... Agent: Slater & Matsil, L.L.P.

20090140352 - Method of forming interlayer dielectric for semiconductor device: A method of forming an interlayer dielectric for a semiconductor device minimizing voids. During a process for forming a PMD oxide film being used as an interlayer dielectric, since TEOS impurities are added under a low-pressure controlled atmosphere, and gap filling characteristics are improved. Therefore, voids are minimized in the... Agent: Sherr & Vaughn, PLLC

20090140353 - Method of film deposition and film deposition system: The present invention is a method of film deposition that comprises a film-depositing step of supplying a high-melting-point organometallic material gas and a nitrogen-containing gas to a processing vessel that can be evacuated, so as to deposit a thin film of a metallic compound of a high-melting-point metal on a... Agent: Smith, Gambrell & Russell

20090140354 - Semiconductor device and method for manufacturing the same: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a gate structure which includes a silicon oxynitride (SiON) layer formed on a semiconductor substrate, a hafnium silicon oxynitride (HfSiON) layer formed on the silicon oxynitride (SiON) layer, a polysilicon layer formed on the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090140356 - Integrated sensor and circuitry and process therefor: A micromachined sensor having a capacitive sensing structure. The sensor includes a first substrate with first and second conductive layers separated by a buried insulator layer, and a member defined by the first and second conductive layers and the buried insulator layer. A first set of elements defined with the... Agent: Hartman & Hartman, P.C.

20090140355 - Semiconductor pressure sensor and its fabrication method: A semiconductor pressure sensor comprises a silicon support substrate (1), an insulating layer (2) formed on the silicon support substrate (1), and a silicon thin plate (3) formed on the insulating layer (2). A through-hole (1a) extending in the thickness direction of the silicon support substrate (1) is formed in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090140357 - High-temperature electrostatic transducers and fabrication method: A high temperature micromachined ultrasonic transducer (HTCMUT) is provided. The HTCMUT includes a silicon on insulator (SOI) substrate having a doped first silicon layer, a doped second silicon layer, and a first insulating layer disposed between the first and second silicon layers. A cavity is disposed in the first silicon... Agent: Lumen Patent Firm

20090140358 - Magnetoresistive element: A magnetoresistive element includes a first ferromagnetic layer having a first magnetization, the first magnetization having a first pattern when the magnetoresistive element is half-selected during a first data write, a second pattern when the magnetoresistive element is selected during a second data write, and a third pattern of residual... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090140359 - Semiconductor device, method of manufacturing the same, and signal transmitting/receiving method using the semiconductor device: A semiconductor device (100) including: a semiconductor substrate including a semiconductor chip formation region (102); a chip internal circuit (124); a signal transmitting/receiving inductor (114) which transmits/receives a signal to/from an outside in a non-contact manner by electromagnetic induction, and transmits/receives a signal to/from the chip internal circuit (124) through... Agent: Mcginn Intellectual Property Law Group, PLLC

20090140360 - Image sensor and fabricating method thereof: An image sensor and fabricating method thereof may include a semiconductor substrate, a plurality of photodiodes formed on and/or over the semiconductor substrate, a first insulating layer formed on and/or over the semiconductor substrate including the plurality of photodiodes, at least one metal line formed on and/or over the first... Agent: Sherr & Vaughn, PLLC

20090140361 - Image sensor and method of manufacturing the same: An image sensor and manufacturing method thereof are provided. The image sensor can includes a semiconductor substrate including a light receiving element, a metal interconnection layer having a trench, a guide pattern on a sidewall of the trench, and a color filter in the trench. Since the color filter can... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090140362 - Photo detector: A photo detector comprising a grating (PC). The grating (PC) is arranged on top of a surface of an active semiconductor layer. The grating (PC) is patterned in uninterrupted first strips (ST1), that are arranged in a first direction (x) in a first predetermined interval (a), and second strips (ST2),... Agent: Law Office Of Ido Tuchman (yor)

20090140363 - Optical semiconductor device having photosensitive diodes and process for fabricating such a device: An optical semiconductor device includes, in a zone (5), a structure of photosensitive diodes including a matrix (6) of lower electrodes (7), an intermediate layer (9) made of a photosensitive material formed on the matrix of lower electrodes and at least one upper electrode (10a) formed on the intermediate layer,... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.

20090140364 - Packaged semiconductor device and method of manufacturing the same: The present invention connects a first wiring portion located at one side of a substrate and a second wiring portion located at the other side. A side electrode connected to the first wiring portion is formed, and the second wiring portion is formed on an insulating layer formed on the... Agent: Mcglew & Tuttle, PC

20090140365 - Image sensor with back-side illuminated photoelectric converters: An image sensor includes a circuit substrate, a plurality of isolation regions, a plurality of photoelectric converters, and an insulation layer. The isolation regions are formed in a pixel region having the photoelectric converters formed therein with each photoelectric converter being electrically isolated by the isolation regions. The insulation layer... Agent: Law Office Of Monica H Choi

20090140366 - Photodiode with controlled current leakage: The present invention is directed towards radiation detectors and methods of detecting incident radiation. In particular the present invention is directed towards photodiodes with controlled current leakage detector structures and a method of manufacturing photodiodes with controlled current leakage detector structures. The photodiodes of the present invention are advantageous in... Agent: Patentmetrix

20090140367 - Optical semiconductor device and method for manufacturing the same: An optical semiconductor device is provided with a low concentration p-type silicon substrate (1); a low dopant concentration n-type epitaxial layer (second epitaxial layer) (26); a low dopant concentration p-type anode layer (27); a high concentration n-type cathode contact layer (9); a photodiode (2) made of the anode layer (27)... Agent: Mcdermott Will & Emery LLP

20090140368 - Method of producing photodiode and the photodiode: A photodiode includes a photosensitive element formed in a silicon semiconductor layer on an insulation layer. The photosensitive element includes a low concentration diffusion layer, a P-type high concentration diffusion layer, and an N-type high concentration diffusion layer. A method of producing the photodiode includes the steps of: forming an... Agent: Kubotera & Associates, LLC

20090140369 - Semiconductor power module package without temperature sensor mounted thereon and method of fabricating the same: Provided are a semiconductor power module package and a method of fabricating the same. The semiconductor power module package includes a substrate, semiconductor chips arranged on a top surface of the substrate, and a temperature sensor mounted on a top surface of at least one of the semiconductor chips. The... Agent: Townsend And Townsend And Crew, LLP

20090140370 - Semiconductor device: A semiconductor device is described. The semiconductor device comprises a protected device in a protected device area of a substrate. An electrostatic discharge power clamp device comprising an outer first guard ring and an inner second guard ring is in a guard ring area of the substrate, enclosing the protected... Agent: Quintero Law Office, PC

20090140371 - Semiconductor integrated device and manufacturing method for the same: A first exemplary aspect of an exemplary embodiment of the present invention is a semiconductor integrated device comprising a semiconductor substrate, a first impurity layer of a first conductivity type formed in the semiconductor substrate, a second impurity layer of a second conductivity type formed on the first impurity layer,... Agent: Mcginn Intellectual Property Law Group, PLLC

20090140373 - Method of manufacturing lcd driver ic: Disclosed is a method of manufacturing an LCD driver IC. The method includes forming a plurality of gate patterns on a semiconductor substrate by sequentially forming a plurality of gate insulating films and gate electrodes; sequentially depositing a plurality of spacer material layers covering the gate electrodes; forming spacers on... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090140372 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes an array having at least one first region and at least one second region. The at least one first region includes at least one first device oriented in a first direction. The at least... Agent: Slater & Matsil LLP

20090140377 - Dielectric isolation type semiconductor device and manufacturing method therefor: A dielectric isolation type semiconductor device includes a dielectric isolation type substrate in which a support substrate, an embedded dielectric layer, and a first conductive type semiconductor substrate of a low impurity concentration are laminated one over another. The semiconductor substrate includes a first semiconductor region of a first conductive... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090140375 - Method of forming isolation layer in semiconductor device: A semiconductor device can include a semiconductor substrate, a first trench formed in the semiconductor substrate, a second trench formed in the semiconductor substrate, a first device isolation layer formed in the first trench, a second device isolation layer formed in the second trench having a different structure than the... Agent: Sherr & Vaughn, PLLC

20090140376 - Semiconductor device and method for manufacturing the device: A method for forming a device isolation layer in a semiconductor substrate by destroying a lattice structure of the semiconductor substrate through a high-energy ion implantation process.... Agent: Sherr & Vaughn, PLLC

20090140374 - Semiconductor device with improved control ability of a gate and method for manufacturing the same: Disclosed is a semiconductor device capable of improving a control ability of a gate and enhancing operation characteristics of the gate. The semiconductor device comprises a semiconductor substrate having a recessed active region. An isolation structure is formed to define the recessed active region in the semiconductor substrate and the... Agent: Ladas & Parry LLP

20090140378 - Flash memory device and method of fabricating the same: In a method of fabricating a flash memory device, trenches are formed in an isolation area of a semiconductor substrate. A first insulating layer is formed on sidewalls and bottoms of the trenches. Conductive layer patterns are formed on the first insulating layers at the bottoms of the trenches. A... Agent: Townsend And Townsend And Crew, LLP

20090140379 - Semiconductor device and method for fabricating the same: A semiconductor device includes a device isolation region formed on a part of shallow trench isolation (STI) sidewalls to relieve stress applied to an active region, thereby improving current flowing toward a channel region.... Agent: Townsend And Townsend And Crew, LLP

20090140380 - Device with gaps for capacitance reduction: A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The... Agent: Beyer Law Group LLP

20090140381 - Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures: A semiconductor wafer contains a substrate having a plurality of active devices formed thereon. An analog circuit is formed on the substrate. The analog circuit can be an inductor, metal-insulator-metal capacitor, or resistor. The inductor is made with copper. A through substrate via (TSV) is formed in the substrate. A... Agent: Robert D. Atkins

20090140382 - Electric fuse device made of polysilicon silicide: A polysilicon silicide electric fuse device, comprising: a substrate; a semiconductor material layer disposed on said substrate, said semiconductor material layer includes lead-out areas of the same doping type at both ends, and an intermediate area of non-doping or having dopant concentration lower than those of said lead-out areas at... Agent: Sinorica, LLC

20090140383 - Method of creating spiral inductor having high q value: A method for fabricating an inductor structure having an increased quality factor (Q) is provided. In one embodiment, a substrate is provided over which a spirally patterned conductor layer is formed to produce a planar spiral inductor. A via hole is formed in the substrate within the spirally patterned conductor... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20090140384 - Process for obtaining a thin, insulating, soft magnetic film of high magnetization, corresponding film and corresponding integrated circuit: A thin soft magnetic film combines a high magnetization with an insulating character. The film is formed by nitriding Fe-rich ferromagnetic nanograins immersed in an amorphous substrate. A selective oxidation of the amorphous substrate is then performed. The result is a thin, insulating, soft magnetic film of high magnetization. Many... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20090140385 - Capacitor with nanotubes and method for fabricating the same: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090140386 - Semiconductor device having capacitor element: Provided is a semiconductor device which includes a capacitor element having a flat-plate-type lower electrode provided over a semiconductor substrate, a flat-plate-type TiN film provided over the lower electrode in parallel therewith, and a capacitor film provided between the lower electrode and the TiN film; and a first Cu plug... Agent: Young & Thompson

20090140387 - High-density 3-dimensional resistors: Interconnect, i.e., BEOL structures comprising at least one thin film resistor that is located at the same level as that of a neighboring conductive interconnect are provided. The present invention also provides a method of fabricating such interconnect structures utilizing processing steps that are compatible with current interconnect processing. Moreover,... Agent: Scully, Scott, Murphy & Presser, P.C.

20090140388 - Integrated circuit including an emitter structure and method for producing the same: A semiconductor emitter structure for emitting charge carriers of a first conductivity type in a base volume of a second conductivity type material neighbored to the emitter structure in a vertical direction, includes multiple emitter volumes of first conductivity tape material having a predetermined lateral dimension in a lateral direction... Agent: Dicke, Billig & Czaja

20090140389 - Nitride semiconductor device and method of manufacturing the same: A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, which is an antioxidant film for preventing... Agent: Leydig Voit & Mayer, Ltd

20090140390 - Gaas semiconductor substrate and method of manufacturing the same, and group iii-v compound semiconductor device and method of manufacturing the same: A GaAs semiconductor substrate includes a main surface (10m) having an inclined angle of 6° to 16° with respect to a (100) plane (10a), and a concentration of chlorine atoms on the main surface (10m) is not more than 1×1013 cm−2. Further, a method of manufacturing a GaAs semiconductor substrate... Agent: Drinker Biddle & Reath (dc)

20090140391 - Seal ring in semiconductor device: A semiconductor device includes a first circuit, a first seal ring and at least one first notch. The first seal ring surrounds the first circuit. The first notch cuts the first seal ring. Specifically, the first notch includes an inner opening, an outer opening and a connecting groove. The inner... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090140393 - Wafer scribe line structure for improving ic reliability: A semiconductor wafer having a multi-layer wiring structure is disclosed. The wafer comprises a plurality of chip die areas arranged on the wafer in an array and scribe line areas between the chip die areas. The scribe lines of a semiconductor wafer having USG top-level wiring layers above ELK wiring... Agent: Duane Morris LLP (tsmc)IPDepartment

20090140392 - Warpage resistant semiconductor package and method for manufacturing the same: A semiconductor package and a method for manufacturing the same is provided for minimizing or preventing warpage and twisting of semiconductor chip bodies as a result of thinning them during gringing. The semiconductor package includes a semiconductor chip body and a substrate. The semiconductor chip body has a first surface,... Agent: Ladas & Parry LLP

20090140395 - Edge seal for thru-silicon-via technology: One or more multilayer back side metallurgy (BSM) stack structures are formed on thru-silicon-vias (TSV). The multiple layers of metal may include an adhesion layer of chromium on the semiconductor wafer back side, a conductive layer of copper, diffusion barrier layer of nickel and a layer of nobel metal, such... Agent: John A. Jordan, Esq.

20090140394 - Semiconductor device and method of forming through hole vias in die extension region around periphery of die: A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of... Agent: Quarles & Brady LLP

20090140396 - Stressed interlayer dielectric with reduced probability for void generation in a semiconductor device by using an intermediate etch control layer of increased thickness: By forming an etch control material with increased thickness on a first stressed dielectric layer in a dual stress liner approach, the surface topography may be smoothed prior to the deposition of the second stressed dielectric material, thereby allowing the deposition of an increased amount of stressed material while not... Agent: Williams, Morgan & Amerson

20090140397 - Semiconductor device and manufacturing method therefor: A semiconductor device includes capacitors formed on the surface of an interlayer insulating film in connection with capacitive contact plug, wherein capacitors are constituted of base-side lower electrode films having hollow-pillar shapes, metal plugs embedded in hollows of base-side lower electrode films, and top-side lower electrode films having hollow-pillar shapes... Agent: Sughrue Mion, PLLC

20090140398 - Hard mask patterns of a semiconductor device and a method for forming the same: In a method for forming hard mask patterns of a semiconductor device first hard mask patterns are formed on a semiconductor substrate. Second hard mask patterns are formed and include first patterns which are substantially perpendicular to the first hard mask patterns and second patterns which are positioned between the... Agent: Townsend And Townsend And Crew, LLP

20090140399 - Semiconductor module with switching components and driver electronics: A semiconductor module comprises at least one semiconductor chip having at least one semiconductor switch. The at least one semiconductor chip is arranged on a carrier substrate. At least one driver component drives the at least one semiconductor switch. The at least one driver component is arranged on a circuit... Agent: Coats & Bennett/infineon Technologies

20090140400 - Method of mid-frequency decoupling: A printed wiring board semiconductor package or PWB power core comprising singulated capacitors embedded on multiple layers of the printed wiring board semiconductor package wherein at least a part of each embedded capacitor lies within the die shadow and wherein the embedded, singulated capacitors comprise at least a first electrode... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20090140401 - System and method for improving reliability of integrated circuit packages: An integrated circuit package includes a die, a bump, an underbump metallization layer formed between the bump and the die, a portion of the underbump metallization layer under the bump having a first radius, and a redistribution layer formed between the underbump metallization layer and the die. The redistribution layer... Agent: Texas Instruments Incorporated

20090140402 - Semiconductor device and method for manufacturing the same: A method includes: mounting a plurality of semiconductor elements on a substrate having wirings; connecting electrically electrodes of the semiconductor elements and the wirings; sealing the semiconductor elements with a resin, which is carried out by bringing a thermal conductor having a concavity and the substrate to be in contact... Agent: Hamre, Schumann, Mueller & Larson P.C.

20090140403 - Electronic device: Embodiments provide an electronic device including a leadframe, a chip attached to the leadframe, and encapsulation material disposed over a portion of the leadframe. The leadframe includes a first main face opposite a second main face and a plurality of edges extending between the first and second main faces. At... Agent: Dicke, Billig & Czaja

20090140404 - Hermetic seal and reliable bonding structures for 3d applications: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned... Agent: Scully, Scott, Murphy & Presser, P.C.

20090140405 - Semiconductor device and resin adhesive used to manufacture the same: A semiconductor device includes: a semiconductor element; a package body having the semiconductor element bonded inside thereof and electrically connected to the semiconductor element; a lid-like member covering the semiconductor element, and bonded to the package body to form a hollow structure; and a bonding member for bonding the package... Agent: Mcdermott Will & Emery LLP

20090140406 - Semiconductor mount: A mount for a semiconductor device has a first surface with at least one contact region and a second surface. The mount has a substrate to receive the second surface of the semiconductor device and a planar element. The planar element has an aperture sized to surround the semiconductor. A... Agent: The Mueller Law Office, P.C.

20090140407 - Integrated circuit package-on-package system with anti-mold flash feature: An integrated circuit package-on-package system includes: mounting an integrated circuit package system having a mountable substrate over a package substrate with the mountable substrate having a mold structure; forming a package encapsulation having a recess over the package substrate and the integrated circuit package system. The present invention also includes:... Agent: Law Offices Of Mikio Ishimaru

20090140408 - Integrated circuit package-on-package system with stacking via interconnect: An integrated circuit package-on-package system includes: providing a bottom integrated circuit package system having a bottom substrate; mounting a top integrated circuit package system having a top substrate over the bottom integrated circuit package system; forming a top stacking via through the top substrate; forming a bottom stacking via into... Agent: Law Offices Of Mikio Ishimaru

20090140409 - Semiconductor device: A semiconductor device includes a substrate having bumps on the backside thereof, a first semiconductor chip mounted on the surface of the substrate, a second semiconductor chip mounted on the first semiconductor chip above the surface of the substrate, a first bonding wire having a length L1 for connecting the... Agent: Mcdermott Will & Emery LLP

20090140410 - Electronic part and method of producing the same: It is an object of the invention to provide an electronic part capable of forming an accurate gap between opposing substrates while also capable of decreasing the area of the electronic part, and a method of producing the same. A second electrode portion (6), having a core pattern (7) and... Agent: Steptoe & Johnson LLP

20090140411 - Resin-sealed semiconductor device, manufacturing method thereof, base material for the semiconductor device, and layered and resin-sealed semiconductor device: The present invention provides a resin-sealed semiconductor device, which includes a semiconductor element; a plurality of terminal members, each surrounding the semiconductor element and including an external terminal portion, an internal terminal portion and a connecting portion; bonding wires, each connecting the semiconductor element with the internal terminal portion; and... Agent: Burr & Brown

20090140412 - Semiconductor device having improved solder joint and internal lead lifetimes: A semiconductor chip is mounted on a flexible wiring board through the interposition of an elastmer. The flexible wiring board is made up of a tape on which wiring is fixed. A part of the wiring is projected beyond the edge of the tape, extended in the direction of the... Agent: Sughrue Mion, PLLC

20090140414 - Semiconductor device: A semiconductor device includes a resin case, a plurality of external connection terminals fixedly provided on the resin case, and at least one semiconductor element provided in the resin case. At least one terminal block has at least one wiring terminal for electrically connecting the semiconductor element and the external... Agent: Kanesaka Berner And Partners LLP

20090140413 - Semiconductor package structure, applications thereof and manufacturing method of the same: A semiconductor package structure and the applications thereof and the manufacturing method are disclosed. The semiconductor package structure includes a carrier, a semiconductor device, a first package body, a lid and a second package body. The semiconductor device is electrically connected to the carrier via a first conductive element. The... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090140415 - Combination substrate: A combination substrate includes a first substrate having wiring board mounting pads for installing a printed wiring board and connection pads on an opposite side of the wiring board mounting pads, a second substrate having package substrate mounting pads for mounting one or more package substrates and having connection pads... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090140416 - Cap member and semiconductor device employing same: A cap member capable of alleviating degradation of reliability and improving fabrication yields is provided. The cap member has a cylindrical side wall portion, a top face portion closing one end of the side wall portion and having a light exit hole formed therein to allow extraction of laser light... Agent: Harness, Dickey & Pierce, P.L.C

20090140417 - Holistic thermal management system for a semiconductor chip: Various semiconductor chip thermal management systems and methods are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate and coupling a diamond heat spreader that has a thermoelectric cooler to the semiconductor chip. A vapor chamber is coupled to the... Agent: Timothy M Honeycutt Attorney At Law

20090140418 - Method for integrating porous low-k dielectric layers: Described herein are methods for integrating low-k dielectric layers with various interconnect structures. In one embodiment, a method for restoring a porous dielectric layer includes forming an opening in the porous low-k dielectric layer. The method further includes forming an opening in a barrier layer. The method further includes depositing... Agent: Applied Materials/bstz Blakely Sokoloff Taylor & Zafman LLP

20090140419 - Extended plating trace in flip chip solder mask window: A flip chip in accordance with an exemplary embodiment of the present invention has a ball grid array and a die disposed on the ball grid array, wherein the ball grid array includes conducting pads disposed under the die. Traces connecting conducting pads under the die are accessible to leads... Agent: Texas Instruments Incorporated

20090140421 - Semiconductor device and method of making integrated passive devices: A semiconductor device has integrated passive circuit elements. A first substrate is formed on a backside of the semiconductor device. The passive circuit element is formed over the insulating layer. The passive circuit element can be an inductor, capacitor, or resistor. A passivation layer is formed over the passive circuit... Agent: Quarles & Brady LLP

20090140420 - Soft error rate mitigation by interconnect structure: A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the... Agent: International Business Machines Corporation Dept. 18g

20090140422 - Substrate for semiconductor package with improved bumping of chip bumps and contact pads and semiconductor package having the same: The present invention relates to a substrate for a semiconductor package and a semiconductor package having the same. A substrate for a semiconductor package includes a substrate body; a contact pad group including a plurality of contact pads parallely arranged at a determined interval on a surface of the substrate... Agent: Ladas & Parry LLP

20090140425 - Chip package: The present provides the improved structure of a chip package, comprising an electrical contact surface of at least a chip configured with a under fill layer, the first solder mask layer, the first metal layer, dielectric material layer, the second metal layer, the second solder mask layer, and metal ball... Agent: Kan Kuan Chuan

20090140423 - Underbump metallurgy employing sputter-deposited nickel titanium alloy: A a metallic adhesion layer is formed on a last level metal plate exposed in an opening of a passivation layer. A Ni—Ti alloy in which the weight percentage of Ti is from about 6.5% to about 30% is deposited by sputtering onto the metallic adhesion layer to form an... Agent: Scully, Scott, Murphy & Presser, P.C.

20090140424 - Wafer level semiconductor package and method for manufacturing the same: A wafer level semiconductor package includes a semiconductor chip having a circuit part. A bonding pad group is disposed in the semiconductor chip and included in the bonding pad group is a power pad that is electrically connected to the circuit part. An internal circuit pattern is disposed at a... Agent: Ladas & Parry LLP

20090140426 - Flip chip package and method for manufacturing the same: A flip chip package includes a substrate and a semiconductor chip. The substrate includes a substrate body, a metal wiring having a terminal part some of which is disposed in the substrate body, a solder resist pattern formed on the substrate body with an opening for exposing the terminal part,... Agent: Ladas & Parry LLP

20090140427 - Metal foil interconnection of electrical devices: An electrical assembly (300, 400) includes a power IC such as a MOSFET (112, 412) attached to a substrate module (114, 214). The MOSFET includes a top surface comprising first and second conductive device surfaces (A, B), associated with first and second device ports, and a bottom surface comprising a... Agent: Pearson & Pearson, LLP

20090140428 - Air gap structure having protective metal silicide pads on a metal feature: A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask... Agent: Scully, Scott, Murphy & Presser, P.C.

20090140430 - Copper alloy sputtering target and semiconductor element wiring: A first copper alloy sputtering target comprising 0.5 to 4.0 wt % of Al and 0.5 wtppm or less of Si and a second copper alloy sputtering target comprising 0.5 to 4.0 wt % of Sn and 0.5 wtppm or less of Mn are disclosed. The first and/or the second... Agent: Howson & Howson LLP

20090140429 - Metal interconnection of a semiconductor device and method of manufacturing the same: A method of manufacturing a metal interconnection of a semiconductor device includes forming a base layer with at least one groove, the at least one groove having an open upper portion, forming a first metal layer in the at least one groove, forming a seed metal layer on the first... Agent: Lee & Morse, P.C.

20090140431 - Hybrid contact structure with low aspect ratio contacts in a semiconductor device: By forming the first metallization layer of a semiconductor device as a dual damascene structure, the contact elements may be formed on the basis of a significantly reduced aspect ratio, thereby enhancing process robustness and also improving electrical performance of the contact structure.... Agent: Williams, Morgan & Amerson

20090140434 - Flexible column die interconnects and structures including same: A flexible column interconnect for a microelectronic substrate includes a plurality of conductive columns extending from a bond pad or other conductive terminal in substantially mutually parallel arrangement, providing redundant current paths between the bond pad and a common cap in the form of a contact pad to which they... Agent: Trask Britt, P.C./ Micron Technology

20090140433 - Mems chip-to-chip interconnects: A chip-to-chip interconnect system suited for MEMS that do not require low-resistance connections is described. The interconnects may be fabricated simultaneously with MEMS ribbon structures such as are found in MEMS optical modulators.... Agent: Morrison Ulman Nupat, LLC

20090140432 - Pad structure to provide improved stress relief: A semiconductor interconnection comprises a semiconductor device, a substrate adjacent the semiconductor device, and a plurality of spring contacts on the semiconductor device or the substrate. A plurality of solder connections are on the opposite semiconductor device or substrate. Each spring contact comprises a contact surface and a conductive material... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090140436 - Method for forming a via in a substrate and substrate with a via: The present invention relates to a method for forming a via in a substrate and a substrate with a via. The method for forming a via in a substrate includes the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove that... Agent: Volentine & Whitt PLLC

20090140435 - Semiconductor integrated circuit device and a method of prototyping a semiconductor chip: In a semiconductor integrated circuit device comprising a semiconductor chip having a number of conductor layers and a number of via layers between the conductor layers, a routing matrix is provided in a small area of the chip to act as a revision number register. The routing matrix includes a... Agent: Faegre & Benson LLP Patent Docketing - Intellectual Property

20090140439 - Method of manufacturing a chip and a chip stack: Provided are a chip, a chip stack, and a method of manufacturing the Same. A plurality of chips which each include: at least one pad formed on a wafer; and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer and is formed in... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090140437 - Semiconductor device and fabrication method thereof: A semiconductor device including an intermediate insulating film formed over a plurality of first conductors over a semiconductor substrate. Contact holes are formed in the intermediate insulating film over the first conductors, and contact plugs are buried in the contact holes, respectively. A plurality of second conductors are formed over... Agent: Taft, Stettinius & Hollister LLP

20090140438 - Semiconductor device and manufacturing method thereof: Wirings each having a side face with a different angle, which is made accurately, in a desired portion over one mother glass substrate are provided without increasing the steps. With the use of a multi-tone mask, a photoresist layer is formed, which has a tapered shape in which the area... Agent: Eric Robinson

20090140440 - Multi-chip stack structure and method for fabricating the same: A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip... Agent: Edwards Angell Palmer & Dodge LLP

20090140441 - Wafer level die integration and method: In a wafer level chip scale package (WLSCP), a semiconductor die has active circuits and contact pads formed on its active surface. A second semiconductor die is disposed over the first semiconductor die. A first redistribution layer (RDL) electrically connects the first and second semiconductor die. A third semiconductor die... Agent: Quarles & Brady LLP

20090140442 - Wafer level package integration and method: In a wafer level chip scale package, a wafer level interconnect structure is formed on a dummy substrate with temperatures in excess of 200° C. First semiconductor die are mounted on the wafer level interconnect structure. The wafer level interconnect structure provides a complete electrical interconnect between the semiconductor die... Agent: Quarles & Brady LLP

20090140443 - Microstructure with enlarged mass and electrode area for kinetic to electrical energy conversion: A microstructure has a substrate, a fixed electrode having a plurality of fixed fingers fixed to the substrate, a movable electrode having a body (28) and a plurality of fingers (22) extending from the body, the movable electrode being movable relative to the fixed fingers to vary a capacitance of... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP