Active solid-state devices (e.g., transistors, solid-state diodes) inventions 04/09

20090108248 - Integrated circuit including doped semiconductor line having conductive cladding: An integrated circuit includes an array of memory cells and a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of memory cells. The integrated circuit includes conductive cladding contacting the doped semiconductor line.... Agent: Dicke, Billig & Czaja

20090108247 - Memory device: The memory layer is used which has a content of Zn or Cd of 20 at % or more and 50 at % or less, a content of Ge or Sb of 5 at % or more and 25 at % or less, and a content of Te of 40... Agent: Miles & Stockbridge PC

20090108249 - Phase change memory with diodes embedded in substrate: An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second... Agent: Slater & Matsil, L.L.P.

20090108250 - Light emitting diode: A light emitting diode (LED) has an n-type semiconductor layer, an active layer, a p-type semiconductor layer, and a transparent electrode layer. The LED includes a tunnel layer interposed between the p-type semiconductor layer and the transparent electrode layer, an opening arranged in the transparent electrode layer so that the... Agent: H.c. Park & Associates, PLC

20090108251 - Controlled growth of a nanostructure on a substrate: The present invention provides for nanostructures grown on a conducting substrate, and a method of making the same. The nanostructures grown according to the claimed method are suitable for manufacturing electronic devices such as an electron beam writer, and a field emission display.... Agent: Fish & Richardson P.C.

20090108252 - Lateral two-terminal nanotube devices and method for their formation: An apparatus, system, and method are provided for a lateral two-terminal nanotube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The lateral nanotube device can include a substrate, an anodic oxide material disposed on the substrate, and a... Agent: Squire, Sanders & Dempsey L.L.P.

20090108253 - Electronic component: The invention relates to an electronic component comprising a flexible substrate, on the surface of which is arranged a layer stack composed of thin layers, containing at least one electrical functional layer composed of an electrically conductive or semiconducting material, wherein the component comprises at least a first material, a... Agent: Carella, Byrne, Bain, Gilfillan, Cecchi, Stewart & Olstein

20090108254 - Fabrication method for organic electronic device and organic electronic device fabricated by the same method: The present invention provides a fabrication method for an organic electronic device comprising a step of stacking sequentially a first electrode made of a metal, one or more organic material layers, and a second electrode on a substrate, wherein the method comprises the steps of: 1) forming a layer on... Agent: Mckenna Long & Aldridge LLP

20090108255 - Processing additives for fabricating organic photovoltaic cells: Processing additives, as well as related compositions, photovoltaic cells, photovoltaic modules, and methods, are disclosed.... Agent: Fish & Richardson PC

20090108256 - Thin-film transistor substrate and method of manufacturing the same: A thin-film transistor (TFT) substrate includes a semiconductor pattern, a conductive pattern, a first wiring pattern, an insulation pattern and a second wiring pattern. The semiconductor pattern is formed on a substrate. The conductive pattern is formed as a layer identical to the semiconductor pattern on the substrate. The first... Agent: F. Chau & Associates, LLC

20090108257 - Critical dimension for trench and vias: Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.... Agent: HorizonIPPte Ltd

20090108258 - Semiconductor device and method for fabricating the same: A semiconductor device and a method for fabricating the same are disclosed, which are capable of improving the performance and the production yield of the device. The semiconductor device may include a semiconductor wafer having semiconductor chips thereon, a lower metal layer on the semiconductor wafer, a dielectric layer on... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090108261 - Array substrate and method of manufacturing the same: The present invention provides an array substrate and a method for manufacturing the same. The array substrate comprises a substrate and a plurality of gate lines parallel to each other and a plurality of data lines parallel to each other formed on the substrate, the gate lines intersecting the data... Agent: Ladas & Parry LLP

20090108262 - Display device: A display device includes an insulative array-substrate provided with display areas, composed of a plurality of pixels, formed thereon; an opposite substrate disposed opposite the array substrate; opposite electrodes, each individually corresponding to the pixels, formed on the surface opposite to the array substrate, of the opposite substrate; a black... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090108264 - Laminated conductive film, electro-optical display device and production method of same: The present invention provides a laminated conductive film, comprising a transparent conductive film and Al-based film, that is capable of realizing a high-quality film with superior electro-optical properties, without providing a buffer layer or protective layer. A laminated conductive film according to one aspect of the present invention is provided... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090108259 - Pixel structure and method for manufacturing the same: A pixel structure of a fringe field switching liquid crystal display (FFS-LCD) and a method for manufacturing the pixel structure are provided. Compared to the conventional method of using seven photolithography-etching processes for manufacturing a pixel structure, the method of the present invention uses only six photolithography-etching processes that save... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090108260 - Pixel structure and method for manufacturing the same: A method for manufacturing a pixel structure is provided. First, a first mask process is performed to form a patterned first metal layer on a substrate, wherein the patterned first metal layer includes a gate. Next, a second mask process is performed to form a patterned insulating layer and a... Agent: Bacon & Thomas, PLLC

20090108263 - Semiconductor device and manufacturing method thereof: The invention relates to a semiconductor device including a plurality of thin film transistors provided on a base member having a curved surface. The surface may be bent in either a convex shape or a concave shape. All channel length directions of the plurality of thin film transistors may also... Agent: Nixon Peabody, LLP

20090108265 - Thin film transistor, method of fabricating the same, and display apparatus having the same: A method of fabricating a thin film transistor includes forming a gate electrode on a substrate, forming a semiconductor layer on the gate electrode, forming a source electrode on the semiconductor layer, forming a drain electrode on the semiconductor layer spaced apart from the source electrode, forming a copper layer... Agent: Cantor Colburn, LLP

20090108266 - Friction control in apparatus having wide bandgap semiconductors: Apparatus comprising, in use, a wide bandgap semiconductor, a conductor which is moveable relative to the semiconductor and means for applying a potential across the junction between a conductor and semiconductor to control the friction generated by the relative movement between the semiconductor and the conductor. A method of controlling... Agent: Tarolli, Sundheim, Covell & Tummino L.L.P.

20090108267 - Composite light-emitting-diode packaging structure: A composite light-emitting-diode (LED) packaging structure includes an upper LED package structure and a lower LED package structure packaged integrally together. The upper LED package structure includes an upper substrate having a hollow structure and an upper LED transparent chip in the hollow structure and enclosed from top to bottom... Agent: Rabin & Berdo, PC

20090108268 - Composite light-emitting-diode packaging structure: A composite light-emitting-diode (LED) packaging structure having oppositely arranged chips comprises a first substrate with a first surface and a second surface, a second substrate with a first surface and a second surface, a first LED chip on the first surface of the first substrate, and a second LED chip... Agent: Rabin & Berdo, PC

20090108269 - Illumination device having one or more lumiphors, and methods of fabricating same: A light emitter comprising a monolithic die comprising at least one solid state light emitting device and at least a first lumiphor covering part of a light emission region of the die. In some embodiments, at least a second lumiphor is provided on the die. The first lumiphor can be... Agent: Burr & Brown

20090108272 - Light emitting device having light emitting elements: A light-emitting device operating on a high drive voltage and a small drive current. LEDs (1) are two-dimensionally formed on an insulating substrate (10) of e.g., sapphire monolithically and connected in series to form an LED array. Two such LED arrays are connected to electrodes (32) in inverse parallel. Air-bridge... Agent: H.c. Park & Associates, PLC

20090108273 - Light emitting device having light emitting elements: A light-emitting device operating on a high drive voltage and a small drive current. LEDs (1) are two-dimensionally formed on an insulating substrate (10) of e.g., sapphire monolithically and connected in series to form an LED array. Two such LED arrays are connected to electrodes (32) in inverse parallel. Air-bridge... Agent: H.c. Park & Associates, PLC

20090108274 - Light emitting device having light emitting elements: A light-emitting device operating on a high drive voltage and a small drive current. LEDs (1) are two-dimensionally formed on an insulating substrate (10) of e.g., sapphire monolithically and connected in series to form an LED array. Two such LED arrays are connected to electrodes (32) in inverse parallel. Air-bridge... Agent: H.c. Park & Associates, PLC

20090108275 - Light emitting device having light emitting elements: A light-emitting device operating on a high drive voltage and a small drive current. LEDs (1) are two-dimensionally formed on an insulating substrate (10) of e.g., sapphire monolithically and connected in series to form an LED array. Two such LED arrays are connected to electrodes (32) in inverse parallel. Air-bridge... Agent: H.c. Park & Associates, PLC

20090108271 - Light emitting diode package: A light emitting diode package includes a mount, a plurality of LED chips, and a first and a second sealants made of different materials. The mount has an accommodation space and at least one partition member to divide the accommodation space into a plurality of separate cavities. The LED chips... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090108270 - Master, pixel array substrate, electro-optical device and methods of manufacturing the same: A master having a substrate including displaying units and an ESD protection structure including an adjacent first region and a second region is provided. The displaying units have a predetermined-cutting region therebetween. Each displaying unit includes a peripheral circuit region and a display region having pixels. The ESD protection structure... Agent: Jianq Chyun Intellectual Property Office

20090108276 - High efficiency dilute nitride light emitting diodes: A light-emitting diode comprising AlnInmGa1-m-nNcAsvSbkP1-c-v-k where 0.001<c<0.1 and 0≦n, m, v, k≦1 adapted to emit light in a wavelength range of about 540 nm to about 700 nm.... Agent: Mintz, Levin, Cohn, Ferris, Glovsky And Popeo, P.c

20090108282 - Chip-type led and method for manufacturing the same: In a chip-type LED according to an embodiment of the present invention, a first recess hole for mounting an LED chip and a second recess hole for connecting a fine metal wire are formed in an insulating substrate, a metal sheet serving as a first wiring pattern is formed at... Agent: Morrison & Foerster LLP

20090108283 - Illumination device and method for manufacturing the same: An illumination device includes a circuit board (11), an LED element (12) mounted on the circuit board, a light-transmitting sealing resin (16) covering the LED element and containing a fluorescent material, a light reflector (14) covering the light-transmitting sealing resin and reflecting light emitted from the LED element, and a... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20090108279 - Light emitting device and method for manufacturing the same: A light emitting device having a light extraction structure, which is capable of achieving an enhancement in light extraction efficiency and reliability, and a method for manufacturing the same. The light emitting device includes a semiconductor layer having a multi-layered structure including a light emission layer; and a light extraction... Agent: Birch Stewart Kolasch & Birch

20090108281 - Light emitting diode package and method for fabricating same: An LED package comprising a submount having a top and bottom surface with a plurality of top electrically and thermally conductive elements on its top surface. An LED is included on one of the top elements such that an electrical signal applied to the top elements causes the LED to... Agent: Koppel, Patrick, Heybl & Dawson

20090108278 - Manufacturing method of an antistatic flip chip substrate connected to several chips: The present invention provides the manufacturing method and device of an antistatic flip chip substrate that can be connected to several chips; this device could protect LED semiconductors against electrostatic discharge damage, and also save cost and space for the assembly of LED semiconductors.... Agent: Alan D. Kamrath Kamrath & Associates

20090108277 - Periodically structured substrate and light emitting device including the same: A periodically structured substrate includes a slab and a periodic structure formed on the slab and including a plurality of spaced apart first surrounding elements and a plurality of spaced apart central elements. The first surrounding elements are periodically arranged in such a manner to form repeating polygonal patterns. Each... Agent: Foley And Lardner LLP Suite 500

20090108280 - Pixel structure and fabrication method thereof: A fabrication method of a pixel structure includes utilizing only a single photomask in two different lithographic processes for defining patterns of the source/drain and passivation layer respectively. Therefore, the total amount of photomasks of the fabrication process can be decreased.... Agent: North America Intellectual Property Corporation

20090108284 - Light emitting device: A light emitting device includes: a chip-mounting base; a light emitting chip mounted on the chip-mounting base; and a transparent encapsulant enclosing the light emitting chip and bonded to the chip-mounting base through a bonding material. The bonding material is an inorganic compound selected from one of a nitride compound... Agent: Rosenberg, Klein & Lee

20090108286 - Optoelectronic device: An optoelectronic device such as a light-emitting diode chip is disclosed. It includes a substrate, a multi-layer epitaxial structure, a first metal electrode layer, a second metal electrode layer, a first bonding pad and a second bonding pad. The multi-layer epitaxial structure on the transparent substrate comprises a semiconductor layer... Agent: Bacon & Thomas, PLLC

20090108285 - Rod-shaped semiconductor device: A rod-shaped semiconductor device having a light-receiving or light-emitting function is equipped with a rod-shaped substrate made of p-type or n-type semiconductor crystal, a separate conductive layer which is formed on a part of the surface of the substrate excluding a band-shaped part parallel to the axis of the substrate... Agent: Jordan And Hamburg LLP

20090108287 - One-transistor static random access memory with integrated vertical pnpn device: A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the... Agent: Hoffman Warnick LLC

20090108288 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate that includes a plurality of section having different thicknesses. The sections include a first section having a first thickness and a second section having a second thickness, the second section is the thinnest section among all the sections, and the first thickness is... Agent: Posz Law Group, PLC

20090108289 - Design structure for uniform triggering of multifinger semiconductor devices with tunable trigger voltage: A design structure for a circuit providing the same trigger voltage across the multiple fingers is provided, which comprises a data representing an external current injection source connected to individual fingers of a multi-finger semiconductor device. For example, the external injection current is supplied to the body of a MOSFET... Agent: Scully, Scott, Murphy & Presser, P.C.

20090108295 - Dopant profile tuning for mos devices by adapting a spacer width prior to implantation: By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or... Agent: Williams, Morgan & Amerson

20090108292 - Floating body field-effect transistors, and methods of forming floating body field-effect transistors: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is... Agent: Wells St. John P.s.

20090108293 - Method for suppressing lattice defects in a semiconductor substrate: A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20090108294 - Scalable high-k dielectric gate stack: A stack comprising a dielectric interface layer, a high-k gate dielectric layer, a group IIA/IIIB element layer is formed in that order on a semiconductor substrate. A metal aluminum nitride layer and, optionally, a semiconductor layer are formed on the stack. The stack is annealed at a raised temperature, e.g.,... Agent: Scully, Scott, Murphy & Presser, P.C.

20090108291 - Semiconductor device and method for fabricating the same: A semiconductor device including a gate structure, two doped regions, and two buffer layers is provided. The gate structure is disposed on a substrate. The two doped regions are made of boron doped silicon germanium (SiGeB) and are disposed in the substrate at both sides of the gate structure. The... Agent: J C Patents, Inc.

20090108290 - Source/drain strained layers: A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Further, the semiconductor device and method provide for an... Agent: Slater & Matsil, L.L.P.

20090108297 - Semi-insulating nitride semiconductor substrate and method of manufacturing the same, nitride semiconductor epitaxial substrate, and field-effect transistor: A method of manufacturing a semi-insulating nitride semiconductor substrate includes the steps of forming on an underlying substrate, a mask in which dotted or striped coating portions having a width or a diameter Ds from 10 μm to 100 μm are arranged at an interval Dw from 250 μm to... Agent: Drinker Biddle & Reath (dc)

20090108298 - Semiconductor device: A semiconductor device includes: substrate region; a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of the substrate regions; an active area between gate and source placed between the gate electrode and the source electrode; an active area between gate and drain... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090108296 - Semiconductor devices with different dielectric thicknesses: An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of... Agent: Freescale Semiconductor, Inc. Law Department

20090108299 - High electron mobility transistor semiconductor device having field mitigating plate and fabrication method thereof: A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the... Agent: Posz Law Group, PLC

20090108300 - Silicon germanium heterojunction bipolar transistor structure and method: Disclosed is a design structure for an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090108301 - Hybrid orientation semiconductor structure with reduced boundary defects and method of forming same: The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bonded to a base silicon substrate having a (001) surface crystal orientation to form a DSB wafer in which... Agent: Scully, Scott, Murphy & Presser, P.C.

20090108302 - Multiple crystallographic orientation semiconductor structures: A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a... Agent: Scully, Scott, Murphy & Presser, P.C.

20090108303 - Semiconductor component and method: A semiconductor component and method of making a semiconductor component. One embodiment provides a first metallization structure electrically coupled to charge compensation zones via an ohmic contact and to drift zones via a Schottky contact. A second metallization structure, which is arranged opposite the first metallization structure, is electrically coupled... Agent: Dicke, Billig & Czaja

20090108307 - Coaxial transistor structure: The present invention discloses a coaxial transistor formed on a substrate, particularly a coaxial metal-oxide-semiconductor field-effect transistor (CMOSFET). The chips or substrates of the CMOSFETs can be stacked up and connected via through-holes to form a coaxial complementary metal-oxide-semiconductor field-effect transistor (CCMOSFET), which is both full-symmetric and full-complementarily, has a... Agent: Frenkel & Associates

20090108304 - Protecting semiconducting oxides: In transistor structures such as thin film transistors (TFTs) in an array of cells, a layer of semiconducting oxide material that includes a channel is protected by a protective layer that includes low-temperature encapsulant material. The semiconducting oxide material can be a transition metal oxide material such as zinc oxide,... Agent: Leading Edge Law Group, PLC/xerox-parc

20090108305 - Semiconductor having a corner compensation feature and method: A semiconductor device includes an active semiconductor material. A transistor gate overlies a first portion of the active semiconductor material. A second portion intersects the first portion at a corner which is distorted during manufacture resulting in rounding of the corner. The active semiconductor material extends into the corner to... Agent: Freescale Semiconductor, Inc. Law Department

20090108308 - Transistor and method of fabricating the same: A transistor and a method of fabricating the same are provided. The transistor includes a SiGe epitaxial layer formed in a recess region of a substrate at both side of a gate electrode and a SiGe capping layer formed on the SiGe epitaxial layer. The transistor further includes a SiGe... Agent: Hosoon Lee

20090108306 - Uniform recess of a material in a trench independent of incoming topography: Columnar elements which extend to varying heights above a major surface of a substrate, e.g., polysilicon studs within trenches in the substrate, are recessed to a uniform depth below the major surface. The columnar elements are etched selectively with respect to a material exposed at the surface in an at... Agent: International Business Machines Corporation Dept. 18g

20090108310 - Cmos image sensor and fabricating method thereof: A CMOS image sensor and fabricating method thereof are disclosed, by which a light condensing effect is enhanced by providing an inner microlens to a semiconductor substrate. The present invention includes a plurality of photodiodes on a semiconductor substrate, a plurality of inner microlenses on a plurality of the photodiodes,... Agent: Mckenna Long & Aldridge LLP

20090108309 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor, which can monitor accurate overlay information even when a dual microlens is employed, and a method for manufacturing the same are disclosed. The CMOS image sensor includes a substrate having a photosensitive element formed therein; a light shield layer formed over the substrate and having a... Agent: Sherr & Vaughn, PLLC

20090108311 - Cmos detector with reduced sensitivity to x-rays: An imaging array and method for operating the same is disclosed. The imaging array includes a semiconductor substrate having an epitaxial layer of semiconductor material deposited on a first surface thereof. A plurality of photodiodes is formed in a top surface of the epitaxial layer. The imaging array also includes... Agent: The Law Offices Of Calvin B. Ward

20090108312 - Image sensor and method of stabilizing a black level in an image sensor: An image sensor includes a substrate, an anti-reflection board and a light shielding film. The substrate includes first pixels to receive a light, and second pixels to provide a black level compensation. The first pixels are formed in an active region and the second pixels are formed in a first... Agent: Stanzione & Kim, LLP

20090108313 - Reducing short channel effects in transistors: Microelectronic structures and associated methods for reducing short channel effects in transistors are generally described. In one example, an apparatus includes a semiconductor channel, one or more transistor gates coupled with the semiconductor channel, a spacer film coupled to the one or more transistor gates, and a semiconductor material epitaxially... Agent: Cool Patent, P.C. C/o Cpa Global

20090108314 - Embedded dram integrated circuits with extremely thin silicon-on-insulator pass transistors: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about... Agent: Michael J. Chang, LLC

20090108315 - Trench memory with monolithic conducting material and methods for forming same: A trench memory filled with a monolithic conducting material and methods for forming the same are disclosed. The trench memory includes a trench that has only a single, monolithic conducting material within the trench. The method includes forming a trench with a collar in the trench; forming a node dielectric... Agent: Hoffman Warnick LLC

20090108318 - Integrated circuit semiconductor device including stacked level transistors and fabrication method thereof: An integrated circuit semiconductor device includes a first transistor formed at a lower substrate and configured with at least one of a vertical transistor and a planar transistor. A bonding insulation layer is formed on the first transistor, and an upper substrate is bonded on the bonding insulation layer. A... Agent: Myers Bigel Sibley & Sajovec

20090108316 - Memory device with memory cell including mugfet and fin capacitor: One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate field effect transistor and associated with... Agent: Texas Instruments Incorporated

20090108317 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device includes forming a first interlayer insulating film including a storage node contact plug over a semiconductor substrate. A second interlayer insulating film is formed over the first interlayer insulating film and the storage node contact plug. A mask pattern is formed over the... Agent: Townsend And Townsend And Crew, LLP

20090108319 - Dram stack capacitor and fabrication method thereof: A DRAM stack capacitor and a fabrication method thereof has a first capacitor electrode formed of a conductive carbon layer overlying a semiconductor substrate, a capacitor dielectric layer and a second capacitor electrode. The first capacitor electrode is of crown shape geometry and possesses an inner surface and an outer... Agent: Quintero Law Office, PC

20090108320 - Tunable capacitor: Disclosed are embodiments of a design structure transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090108321 - Flash memory: A flash memory is provided. The flash memory includes a substrate, a first insulation layer formed on the substrate, a control gate disposed on the first insulation layer, and two floating gates coplanar with the substrate respectively disposed on both sides of the control gate.... Agent: Quintero Law Office, PC

20090108322 - Semiconductor memory having both volatile and non-volatile functionality and method of operating: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a fin structure extending from a substrate, the fin structure including a floating substrate region having a first conductivity type configured to store data as volatile memory; first and second regions interfacing with... Agent: Law Office Of Alan W. Cannon

20090108323 - Method of forming nonvolatile memory device having floating gate and related device: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the... Agent: Mills & Onello LLP

20090108326 - Semiconductor device and method of manufacturing the same: A semiconductor device has a semiconductor substrate, a plurality of first conductive patterns, a second conductive pattern having a top surface of which stepwisely or gradually decreases in height in a direction from a side facing the first conductive pattern toward an opposite side, a first insulation film formed over... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090108324 - Semiconductor fin based nonvolatile memory device and method for fabrication thereof: A semiconductor structure and a method for fabricating the semiconductor structure include a semiconductor fin having a first side and a second side opposite the first side. A first gate dielectric and a charge storage layer are successively layered upon the first side of the semiconductor fin. A second gate... Agent: Scully, Scott, Murphy & Presser, P.C.

20090108325 - Split gate device and method for forming: A method of making a semiconductor device on a semiconductor layer includes forming a select gate, a recess, a charge storage layer, and a control gate. The select gate is formed have a first sidewall over the semiconductor layer. The recess is formed in the semiconductor layer adjacent to the... Agent: Freescale Semiconductor, Inc. Law Department

20090108327 - Gate pattern having two control gates, flash memory including the gate pattern and methods of manufacturing and operating the same: Provided may be a gate pattern, flash memory and methods of manufacturing and operating the same. A gate pattern may include a floating gate on a tunneling dielectric layer, an inter-gate dielectric layer on the floating gate, a first control gate on the inter-gate dielectric layer, and a second control... Agent: Harness, Dickey & Pierce, P.L.C

20090108328 - Array of non-volatile memory cells: An array of nonvolatile memory cells comprises a substantially single crystalline semiconductor substrate of a first conductivity type, having a planar surface. A plurality of non-volatile memory cell units are arranged in a plurality of rows and columns in the substrate. Each cell unit comprises a first region of a... Agent: Dla Piper LLP (us )

20090108329 - Non-volatile semiconductor device and method of fabricating the same: A non-volatile semiconductor device includes a tunnel insulating film including a ridge and a valley, and a nano floating gate including a nano dot. The ridge and the valley are alternately arranged by a given interval. The nano dot is disposed over the valley of the tunnel insulating film.... Agent: Townsend And Townsend And Crew, LLP

20090108331 - Memory and manufacturing method thereof: A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second... Agent: Bacon & Thomas, PLLC

20090108332 - Non-volatile memory device with charge trapping layer and method for fabricating the same: Disclosed herein are a non-volatile memory device and a method of manufacturing the same. The non-volatile memory device includes a substrate, a tunneling layer disposed on the substrate, a charge trapping layer disposed on the tunneling layer, a blocking layer disposed on the charge trapping layer, and a control gate... Agent: Marshall, Gerstein & Borun LLP

20090108333 - Non-volatile semiconductor storage device and method of manufacturing the same: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090108330 - Split charge storage node outer spacer process: Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping... Agent: Amin, Turocy & Calvin, LLP

20090108334 - Charge trap device and method for fabricating the same: A charge trapping device includes a plurality of isolation layers, a plurality of charge trapping layers, a blocking layer, and a control gate electrode. The isolation layers define active regions, and the isolation layers and active regions extend as respective stripes along a first direction on a semiconductor substrate. The... Agent: Marshall, Gerstein & Borun LLP

20090108336 - Method for adjusting the height of a gate electrode in a semiconductor device: By providing an implantation blocking material on the gate electrode structures of advanced semiconductor devices during high energy implantation processes, the required shielding effect with respect to the channel regions of the transistors may be accomplished. In a later manufacturing stage, the implantation blocking portion may be removed to reduce... Agent: Williams, Morgan & Amerson

20090108335 - Stress transfer by sequentially providing a highly stressed etch stop material and an interlayer dielectric in a contact layer stack of a semiconductor device: By forming two or more individual dielectric layers of high intrinsic stress levels with intermediate interlayer dielectric material, the limitations of respective deposition techniques, such as plasma enhanced chemical vapor deposition, may be respected while nevertheless providing an increased amount of stressed material above a transistor element, even for highly... Agent: Williams, Morgan & Amerson

20090108337 - Method of and circuit for protecting a transistor formed on a die: A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling... Agent: Xilinx, Inc Attn: Legal Department

20090108338 - Trench mosfet with implanted drift region: A method to manufacture a trenched semiconductor power device including a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The method for manufacturing the trenched semiconductor power device includes a step of carrying out a tilt-angle implantation through... Agent: Bo-in Lin

20090108339 - High voltage tmos semiconductor device with low gate charge structure and method of making: A TMOS device (10) is formed using a semiconductor layer (16) of a first type. First and second regions (62,64) of the second type are formed in the semiconductor layer and are spaced apart. A third region (68) is formed in the semiconductor layer by implanting. The third region is... Agent: Freescale Semiconductor, Inc. Law Department

20090108340 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device includes forming a mask pattern over a semiconductor substrate to define a channel region. A portion of the semiconductor substrate is etched using the mask pattern as an etching mask to form a first pillar. A spacer is formed over a sidewall of... Agent: Townsend And Townsend And Crew, LLP

20090108341 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device includes forming a first vertical pillar over a semiconductor substrate. A spacer is formed over a sidewall of the first vertical pillar. A portion of the semiconductor substrate exposed between the first vertical pillars is etched to form a recess that exposes a... Agent: Townsend And Townsend And Crew, LLP

20090108344 - Semiconductor apparatus: The present invention provides a semiconductor apparatus having high reliability with respect to a withstand voltage, leakage characteristics, etc. by disposing a structure of preventing stress occurring by metal wiring from directly acting on a trench relating to the semiconductor apparatus having a trench gate. The semiconductor apparatus of the... Agent: Mcdermott Will & Emery LLP

20090108342 - Semiconductor component and method of manufacture: A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A semiconductor material includes an epitaxial layer disposed on a semiconductor substrate. A trench having an upper portion and a lower portion is formed in the epitaxial layer. A portion... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20090108343 - Semiconductor component and method of manufacture: A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A semiconductor material includes an epitaxial layer disposed on a semiconductor substrate. Field plate trenches extend into the semiconductor material and field plates are formed in the field plate trenches.... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20090108345 - Ldmos device and method of fabrication: An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090108346 - Hybrid-mode ldmos: An MOS-bipolar hybrid-mode LDMOS device has a main gate input and a control gate input wherein the device operates in an MOS mode when both gate inputs are enabled, and operates in a bipolar mode when the main gate input is enabled and the control gate input is disabled. The... Agent: Hiscock & Barclay, LLP

20090108347 - Lateral diffusion field effect transistor with asymmetric gate dielectric profile: A gate stack comprising a uniform thickness gate dielectric, a gate electrode, and an oxygen-diffusion-resistant gate cap is formed on a semiconductor substrate. Thermal oxidation is performed only on the drain side of the gate electrode, while the source side is protected from thermal oxidation. A thermal oxide on the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090108348 - Semiconductor device: A semiconductor device is provided. An isolation structure is formed in a substrate to define a first and a second active region, and a channel active region therebetween. A field implant region is formed below a portion of the isolation structure around the first, second, and channel active regions. A... Agent: J C Patents, Inc.

20090108351 - Finfet memory device with dual separate gates and method of operation: A FinFET device comprises a front gate (FG) and a separate back gate (BG) disposed on opposite sides of the fine. The fin structure may act as a floating body of a volatile memory cell. The front and back gates may be doped with the same or opposite polarity, and... Agent: International Business Machines Corporation Dept. 18g

20090108353 - Finfet structure and methods: A FinFET structure is fabricated by patterning a semiconductor substrate to form a nonplanar semiconductor structure including a first fin, a second fin substantially parallel to the first fin, and an inter-fin semiconductor strip coupled therebetween. The first fin, the second fin, and the inter-fin semiconductor strip each extend from... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20090108349 - High-performance fet device layout: A fast FET, a method and system for designing the fast FET and a design structure of the fast FET. The method includes: selecting a reference design for a field effect transistor, the field effect transistor including a source, a drain, a channel between the source and drain, a gate... Agent: Schmeiser, Olsen & Watts

20090108352 - Metal-gated mosfet devices having scaled gate stack thickness: Metal-oxide semiconductor field effect transistor (MOSFET) devices having metal gate stacks and techniques for improving performance thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate having a buried oxide layer at least a portion of which is configured to serve as a primary background... Agent: Michael J. Chang, LLC

20090108350 - Method for fabricating super-steep retrograde well mosfet on soi or bulk silicon substrate, and device fabricated in accordance with the method: A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde... Agent: Harrington & Smith, PC

20090108354 - Semiconductor device and method of manufacturing the same: A polysilicon film is formed all over a surface of a semiconductor substrate, then is subject to a CMP process through a mask pattern as a stopper. Then, a metal film is formed all over the resulting surface, and is allowed at least a part of the polysilicon film and... Agent: Young & Thompson

20090108355 - Soi cmos circuits with substrate bias: The present invention relates to methods and devices for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a silicon-on-insulator (SOI) substrate. Specifically, a substrate bias voltage is applied to the CMOS... Agent: Scully, Scott, Murphy & Presser, P.C.

20090108356 - Integration scheme for multiple metal gate work function structures: A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap... Agent: Scully, Scott, Murphy & Presser, P.C.

20090108357 - Semiconductor device: Electrode placement which applies easy heat dispersion of a semiconductor device with high power density and high exothermic density is provided for the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate 10, and have a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090108359 - A semiconductor device and method of manufacture therefor: The present invention provides a semiconductor device, and an integrated circuit including the semiconductor device. The semiconductor device, in one embodiment, includes: (1) a gate structure located over a substrate, the gate structuring including a gate dielectric and gate electrode; (2) source/drain regions located within the substrate proximate the gate... Agent: Hitt Gaines, PC Lsi Corporation

20090108360 - Methods, structures and designs for self-aligning local interconnects used in integrated circuits: Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates are designed to be active gates and some of the plurality of gates are designed to be formed over isolation regions. The method... Agent: Martine Penilla & Gencarella, LLP

20090108358 - Saddle type mos device: The present invention relates to a nano-scale MOS device having a saddle structure. Particularly, the invention relates to a high-density, high-performance MOS device having a novel structure capable of improving the scaling-down characteristic and performance of the MOS device, in which a channel and gate structure is formed in the... Agent: Greenblum & Bernstein, P.L.C

20090108362 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate, an isolation region including an insulator in a trench formed in the semiconductor substrate, an active region including a semiconductor region surrounded by the insulator in the trench and a single-crystal silicon layer formed on the semiconductor region, a gate insulating film formed... Agent: Young & Thompson

20090108363 - Strained semiconductor, devices and systems and methods of formation: In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The device region has a channel region, and the isolation regions have volumes. The volumes of the isolation regions are adjusted to provide the channel region with... Agent: Schwegman, Lundberg & Woessner/micron

20090108361 - Tensile strain source using silicon/germanium in globally strained silicon: By embedding a silicon/germanium mixture in a silicon layer of high tensile strain, a moderately high degree of tensile strain may be maintained in the silicon/germanium mixture, thereby enabling increased performance of N-channel transistors on the basis of silicon/germanium material.... Agent: Williams, Morgan & Amerson

20090108364 - Dual workfunction silicide diode: A CMOS diode and method of making it are disclosed. In one embodiment, the diode comprises a silicon substrate having an N doped region and a P doped region. A first silicide region is formed on the N doped region of the silicon substrate, and a second silicide region formed... Agent: International Business Machines Corporation Dept. 18g

20090108365 - High-k dielectric metal gate device structure and method for forming the same: A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is... Agent: Duane Morris LLP (tsmc)IPDepartment

20090108369 - Radio frequency device of semiconductor type: An RF device includes a semiconductor substrate; an insulating layer thereon; a first plate type ground layer having a slot, on a top of the insulating layer; a signal line in the insulating layer beneath the first ground layer; a plurality of second ground layers in the insulating layer around... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090108370 - Semiconductor device and manufacturing method thereof: There have been provided a semiconductor device capable of preventing defects associated with etching, such as an increase in leak current, deterioration in film-coating properties and deterioration in transistor properties, and a method for manufacturing the semiconductor device. A CMOS transistor includes, on the same semiconductor substrate, an NMOS transistor... Agent: Mcdermott Will & Emery LLP

20090108367 - Semiconductor device and method for manufacturing same: The present invention provides a semiconductor device includes: an element isolation region configured to be formed in a semiconductor substrate; a P-type field effect transistor configured to be formed in a first element formation region of the semiconductor substrate for which isolation by the element isolation region is carried out;... Agent: Robert J. Depke Lewis T. Steadman

20090108368 - Semiconductor device and method for manufacturing the same: A gate electrode of one of an nFET and a pFET includes a metal-containing layer in contact with a gate insulating film and a first silicon-containing layer formed on the metal-containing layer, and a gate electrode of the other FET includes a second silicon-containing layer in contact with a gate... Agent: Mcdermott Will & Emery LLP

20090108366 - Structure and method to fabricate metal gate high-k devices: Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active area, forming a gate structure over... Agent: Harrington & Smith, PC

20090108371 - Semiconductor device and manufacturing the same: A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090108374 - High density sram cell with hybrid devices: Hybrid SRAM circuit, hybrid SRAM structures and method of fabricating hybrid SRAMs. The SRAM structures include first and second cross-coupled inverters coupled to first and second pass gate devices. The pull-down devices of the inverters are FinFETs while the pull-up devices of the inverters and the pass gate devices are... Agent: Schmeiser, Olsen & Watts

20090108372 - Sram cell having a rectangular combined active area for planar pass gate and planar pull-down nfets: A planar pass gate NFET is designed with the same width as a planar pull-down NFET. To optimize a beta ratio between the planar pull-down NFET and an adjoined planar pass gate NFET, the threshold voltage of the planar pass gate NFET is increased by providing a different high-k metal... Agent: Scully, Scott, Murphy & Presser, P.C.

20090108373 - Techniques for enabling multiple vt devices using high-k metal gate stacks: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region;... Agent: Michael J. Chang, LLC

20090108375 - Semiconductor device: The present invention proposes a dummy metal fill structure which makes it possible to reduce variations in transistor characteristics as much as possible even if mask misalignment occurs, as well as to ensure the intended planarizing effect of the metal CMP process. The dummy metal fill formed above the gate... Agent: Mcdermott Will & Emery LLP

20090108376 - Semiconductor device having mos transistors which are serially connected via contacts and conduction layer: A semiconductor device includes a plurality of signal lines which are arranged at a predetermined pitch; first and second MOS transistors which are connected to the signal lines, and also serially connected to each other; and a connection device which functions as a connection node between the serially-connected first and... Agent: Young & Thompson

20090108377 - Method for fabricating gate dielectrics of metal-oxide-semiconductor transistors using rapid thermal processing: In a method for fabricating gate dielectrics of metal-oxide-semiconductor transistors, rapid thermal processing (RTP) of a gate dielectric material is performed at a temperature from 1000-1200° C. in a low-concentration oxidizing gas. The method regrows an oxide layer having a thickness of more than 0.05 nm between the gate dielectric... Agent: Stockwell & Smedley, Psc

20090108379 - Semiconductor device and fabrication method for the same: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to... Agent: Mcdermott Will & Emery LLP

20090108378 - Structure and method for fabricating self-aligned metal contacts: A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a stack comprising a bottom polysilicon (polySi) layer and a top metal semiconductor alloy (i.e., metal silicide) layer.... Agent: Scully, Scott, Murphy & Presser, P.C.

20090108380 - Fet-based gas sensor system: A sensor system for detection of gas with a modified ion selection FET. The FET may have a gate of low conductivity material for detection of a species in a fluid. A component such as a capacitor may be connected to an electrode of the FET, such as a source,... Agent: Honeywell International Inc.

20090108381 - Low temperature bi-cmos compatible process for mems rf resonators and filters: A method of formation of a microelectromechanical system (MEMS) resonator or filter which is compatible with integration with any analog, digital, or mixed-signal integrated circuit (IC) process, after or concurrently with the formation of the metal interconnect layers in those processes, by virtue of its materials of composition, processing steps,... Agent: F. Chau & Associates, LLC

20090108382 - Transducer for use in harsh environments: A pressure sensor for use in a harsh environment including a substrate and a sensor die directly coupled to the substrate by a bond frame positioned between the substrate and the sensor die. The sensor die includes a generally flexible diaphragm configured to flex when exposed to a sufficient differential... Agent: Thompson Hine L.L.P. Intellectual Property Group

20090108383 - High performance mtj element for conventional mram and for stt-ram and a method for making the same: A STT-RAM MTJ that minimizes spin-transfer magnetization switching current (Jc) is disclosed. The MTJ has a MgO tunnel barrier layer formed with a natural oxidation process to achieve a low RA (10 ohm-um2) and a Fe or Fe/CoFeB/Fe free layer which provides a lower intrinsic damping constant than a CoFeB... Agent: Saile Ackerman LLC

20090108386 - Image sensor and method for manufacturing the same: Provided is an image sensor and method for manufacturing the same. The image sensor includes a semiconductor substrate including a photodiode for each unit pixel, an interlayer insulating layer including metal lines on the semiconductor substrate, and an optical refractive part in a region of the interlayer insulating layer corresponding... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090108385 - Method and apparatus for improving crosstalk and sensitivity in an imager: A pixel sensor cell includes a substrate of a first conductivity type, and a photoconversion region. The photoconversion region includes a pinning layer of the first conductivity type for receiving incident light of multiple colors, and a diode implant layer of a second conductivity type, disposed below the pinning layer,... Agent: Ratnerprestia

20090108384 - Optoelectronic device with germanium photodetector: An optoelectronic device comprises a photodetector feature, an interfacial layer disposed above at least a portion of the photodetector feature, and a vertical contact disposed on at least a portion of the interfacial layer. The photodetector feature comprises germanium and is operative to convert a light signal into an electrical... Agent: Ryan, Mason & Lewis, LLP

20090108387 - Semiconductor device and method for strain controlled optical absorption: A semiconductor device which has controlled optical absorption includes a substrate, and a semiconductor layer supported by the substrate. The semiconductor has variable optical absorption at a predetermined optical frequency in relationship to a bandgap of the semiconductor layer. Also included is a strain application structure coupled to the semiconductor... Agent: Hewlett Packard Company

20090108388 - Semiconductor device and method of manufacturing the same: A semiconductor device has a semiconductor substrate including a light receiving element, a silicon oxide film formed on the semiconductor substrate, a plurality of wiring interlayer films formed on the silicon oxide film, and each including a wiring layer formed as the result of the fact that copper is buried,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090108389 - Imaging device comprising shielding unit which shields light incident from imaging area to optical black area and method of manufacturing the same: An imaging device according to an example of the invention comprises a first photoelectric conversion unit which is formed at an imaging area of a substrate, a second photoelectric conversion unit for black reference observation which is formed at an optical black area between the imaging area of the substrate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090108390 - Image sensor and method for manufacturing thereof: An image sensor may include a semiconductor substrate including a device isolating film and a light receiving device; an insulating film on the semiconductor substrate; a barrier; a metal wire layer on the insulating film; a trench between adjacent metal wires having a protective film pattern on sidewalls thereof; and... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090108391 - Solid-state imaging device and method for fabricating the same: A solid-state imaging device comprises an imaging region, a peripheral circuit region formed in an outer peripheral portion of the imaging region, a first conductivity type semiconductor substrate having the imaging region and the peripheral circuit region on a main surface thereof, a second conductivity type first semiconductor layer formed... Agent: Mcdermott Will & Emery LLP

20090108393 - Semiconductor device with a plurality of ground planes: A multi-chip module (MCM) with a plurality of ground planes/layers is provided. Each integrated circuit (IC) chip of the MCM has its own ground plane on a substrate in the MCM. This MCM structure may facilitate separate testing of each IC chip without affecting other chips and without being affected... Agent: Sidley Austin LLP

20090108392 - Semiconductor structure and method of manufacture: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a semiconductor device includes a plurality of rectilinear structures, wherein the plurality of rectilinear structures comprise silicon dioxide and extend from a surface of a semiconductor material to a distance of at least about... Agent: Hvvi Semiconductors, Inc.

20090108394 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device comprises forming a deposition structure including a first substrate, an insulating layer and a second substrate of a SOI substrate; etching the second substrate located in a boundary of cell and core regions and a peripheral region to form a line-type trench; filling... Agent: Townsend And Townsend And Crew, LLP

20090108395 - Semiconductor device having increased active region width and method for manufacturing the same: The disclosed semiconductor device includes a plurality of active patterns including first active patterns which protrude from a semiconductor substrate and have a first width and second active patterns which are connected to upper ends of the respective first active patterns and have a second width greater than the first... Agent: Ladas & Parry LLP

20090108399 - Apparatus and method for manufacturing semiconductor device incorporating fuse elements: An apparatus and a method for manufacturing semiconductor devices is disclosed for selectively disconnecting a fuse element out of plural fuse elements formed on a semiconductor wafer substrate which is provided with the plural fuse elements and a dielectric layer having at least one opening corresponding to the location for... Agent: Dickstein Shapiro LLP

20090108396 - Electrical fuse having a fully silicided fuselink and enhanced flux divergence: A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to... Agent: Scully, Scott, Murphy & Presser, P.C.

20090108398 - Fuse of semiconductor device and method for forming the same: A fuse in a semiconductor device includes: first and second fuse patterns, each being in the shape of a bar, separated from each other in a blowing region; first and second contact plugs respectively coupled to the first and the second fuse patterns; and a third fuse pattern coupled to... Agent: Marshall, Gerstein & Borun LLP

20090108397 - Thin film device with layer isolation structure: This invention provides a thin film device with layer isolation structures. Specifically, a plurality of patterned thin film device layers provide a first rail and a second rail. There is at least one overpass between the first rail and the second rail. The overpass is defined by an array of... Agent: Hewlett Packard Company

20090108400 - Anti-fuse structure including a sense pad contact region and methods for fabrication and programming thereof: An antifuse structure includes a sense pad contact region that is separate from an anode contact region and a cathode contact region. By including the sense pad contact region that is separate from the anode contact region and the cathode contact region, a programming current flow when programming the antifuse... Agent: Scully, Scott, Murphy & Presser, P.C.

20090108402 - Method for manufacturing capacitor of semiconductor device: A method for manufacturing a capacitor of a semiconductor device may include: forming an interlayer insulating film including a contact plug over a semiconductor substrate; forming a first stack film comprising a capacitor oxide film and a nitride film over the interlayer insulating film; etching the first stack film to... Agent: Marshall, Gerstein & Borun LLP

20090108401 - Semiconductor device: A semiconductor device is disclosed. One embodiment provides a semiconductor chip. The semiconductor chip includes a first electrode of a capacitor. An insulating layer is arranged on top of the first electrode. A second electrode of the capacitor is applied over the insulating layer, wherein the second electrode is made... Agent: Dicke, Billig & Czaja

20090108404 - Semiconductor device: The semiconductor device according to the present invention includes a plurality of capacitance elements. Each capacitance element has a structure obtained by holding a capacitance film made of an insulating material between first and second electrodes made of a metallic material. The first and second electrodes are so arranged as... Agent: Rabin & Berdo, PC

20090108405 - Semiconductor device and method of manufacturing the semiconductor device: A conductive film embedded in a predetermined region on an upper surface of an insulation film and metallic wirings embedded so as to penetrate through the conductive film and protrudes into the insulation film constitute a lower electrode of an MIM capacitor.... Agent: Mcdermott Will & Emery LLP

20090108403 - Semiconductor structure and method of manufacture: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a capacitor embedded in a dielectric material below the surface of a semiconductor substrate is disclosed. Other embodiments are described and claimed.... Agent: Hvvi Semiconductors, Inc.

20090108406 - Semiconductor device having two bipolar transistors constituting electrostatic protective element: A semiconductor device includes a pair of transistors formed in a first conductive type semiconductor substrate. Each of the transistors contains a collector region of a second conductive type, opposite to the first conductive type, formed in the semiconductor substrate, a base region of the first conductive type formed in... Agent: Mcginn Intellectual Property Law Group, PLLC

20090108407 - Oxygen-doped n-type gallium nitride freestanding single crystal substrate: Otherwise, oxygen can be doped into a gallium nitride crystal by preparing a C-plane gallium nitride seed crystal or a three-rotationally symmetric plane foreign material seed crystal, supplying material gases including gallium, nitrogen and oxygen to the C-plane gallium nitride seed crystal or the three-rotationally symmetric foreign seed crystal, growing... Agent: Smith, Gambrell, & Russell, LLP

20090108408 - Method for trapping implant damage in a semiconductor substrate: A method for minimizing the effects of defects produced in a implantated area of a crystal lattice during dopant implantation in the lattice. The method begins with the step of implanting a trap layer of trap atoms, the trap atoms having a size less than that of the lattice member... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20090108409 - Semiconductor device and manufacturing method thereof: A semiconductor device includes an element formed on a substrate, at least one insulating film formed on the substrate, and a seal ring formed in the insulating film so as to surround a region where the element is formed and to extend through the insulating film. The semiconductor device further... Agent: Mcdermott Will & Emery LLP

20090108410 - Semiconductor device: A semiconductor device includes a semiconductor substrate, a diffusion layer conductive film formed on the semiconductor substrate, an interlayer insulating film layered on the semiconductor substrate, an interconnect pattern and a via pattern formed in the interlayer insulating film, a plurality of circuit regions formed in the semiconductor substrate, and... Agent: Mcdermott Will & Emery LLP

20090108411 - Silicon substrate for package: In a silicon substrate for a package, a through electrode is provided with which a through hole passing through from a bottom surface of a cavity for accommodating a chip of an electronic device to a back surface of the substrate is filled. An end part of the through electrode... Agent: Rankin, Hill & Clark LLP

20090108412 - Semiconductor substrate and method for manufacturing a semiconductor substrate: A semiconductor substrate includes: a silicon support substrate with a first crystal orientation; a silicon functional substrate which is formed on the silicon support substrate and which has a first crystalline region with a crystal orientation different from the first crystal orientation of the silicon support substrate and a second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090108413 - Interlayer insulating film, interconnection structure, and methods of manufacturing the same: This invention provides an interlayer insulating film for a semiconductor device, which has low permittivity, is free from the evolution of gas such as CFx and SiF4 and is stable, and a wiring structure comprising the same. In an interlayer insulating film comprising an insulating film provided on a substrate... Agent: Foley And Lardner LLP Suite 500

20090108414 - Wafer: A wafer has a rare earth oxide layer disposed, typically sprayed, on a substrate. It is useful as a dummy wafer in a plasma etching or deposition system.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090108415 - Increasing etch selectivity during the patterning of a contact structure of a semiconductor device: By forming an intermediate etch stop material or by appropriately positioning an additional etch stop material in a spacer structure of a polysilicon line, the probability of exposing a shallow doped region of an active semiconductor region during a critical contact etch step for forming rectangular contacts may be significantly... Agent: Williams, Morgan & Amerson

20090108416 - Direct-connect signaling system: A direct-connect signaling system including a printed circuit board and first and second integrated circuit packages disposed on the printed circuit board. A plurality of electric signal conductors extend between the first and second integrated circuit packages suspended above the printed circuit board.... Agent: Tpl/interconnect Portfolio, LLC

20090108417 - Method and system for providing a continuous impedance along a signal trace in an ic package: A multi-layered integrated circuit chip package comprises a void layer that includes at least one void. The multi-layered integrated circuit chip package also includes an insulation layer that electrically insulates the void layer from a trace layer. At least one trace resides in the trace layer. The trace having a... Agent: Texas Instruments Incorporated

20090108419 - Leadframe for leadless package: A leadframe for a leadless package comprises a plurality of package areas, a plurality of slots, a plurality of connection portions, a plurality of openings, and a tape (film). Each package area comprises a plurality of package units, each of which comprises a die pad and a plurality of leads... Agent: Wpat, PC Intellectual Property Attorneys

20090108418 - Non-leaded semiconductor package structure: A non-leaded semiconductor package structure is proposed, in which the structure of a lead frame is improved to let the lower surface of a die paddle of the lead frame be used to carry a die and the upper surface thereof be exposed out of the package structure. Moreover, a... Agent: Rosenberg, Klein & Lee

20090108420 - Semiconductor device and its fabrication process: A technique capable of preventing whiskers which are generated in a plating film formed on the surface of each of leads of a semiconductor device is provided. Particularly, a technique capable of preventing generation of whiskers in a plating film containing tin as a primary material and not containing lead... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090108421 - Apparatus and method configured to lower thermal stresses: An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the... Agent: Dicke, Billig & Czaja

20090108422 - Semiconductor device: The present invention can supply power for each circuit section by separating and connecting bus-bar (21d) for each circuit section inside the semiconductor chip (22), and, in addition, can increase the number of pads (22a) for power supply or can use the lead (21a) conventionally used for power supply for... Agent: Miles & Stockbridge PC

20090108423 - Semiconductor package: A semiconductor package includes a leadframe defining a die pad, a chip electrically coupled to the die pad, encapsulation material covering the chip and the die pad, and a plurality of lead ends exposed relative to the encapsulation material and configured for electrical communication with the chip, and a nitrogen-containing... Agent: Dicke, Billig & Czaja

20090108424 - Leadframe for leadless package: A leadframe for a leadless package comprises a plurality of package areas, a plurality of first slots, a plurality of first side rails, a plurality of second side rails, and tape. Each of the package areas comprises a plurality of package units, each of which comprises a die pad and... Agent: Wpat, PC Intellectual Property Attorneys

20090108425 - Stacked package and method of manufacturing the same: In one embodiment, the stacked package includes a first chip disposed over a package substrate. The first chip has at least one first chip dummy pad, and the first chip dummy pad is not electrically connected to circuits of the first chip. A first dummy bonding wire is connected to... Agent: Harness, Dickey & Pierce, P.L.C

20090108426 - Optical device and method of manufacturing the same: An optical device includes a semiconductor substrate (11) on which a light receiving part (12) (or a light emitting part) and electrodes (13) are formed, and a translucent plate (2) bonded on the light receiving part (12) with a translucent adhesive (5), the semiconductor substrate (11) having a plurality of... Agent: Steptoe & Johnson LLP

20090108427 - Techniques for modular chip fabrication: Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the... Agent: Michael J. Chang, LLC

20090108429 - Flip chip packages with spacers separating heat sinks and substrates: A package structure includes a substrate; a die over and flip bonded on the substrate; a heat sink over the die; and one or more spacer separating the heat sink from the substrate.... Agent: Slater & Matsil, L.L.P.

20090108431 - Inverted package-on-package (pop) assemblies and packaging methods for integrated circuits: Integrated circuit package assemblies and packaging methods are provided. An integrated circuit package assembly includes a first circuit package including a first substrate having a top surface and a bottom surface, a first circuit die containing a programmable processor mounted to and electrically connected to the bottom surface of the... Agent: Fish & Richardson PC

20090108428 - Mountable integrated circuit package system with substrate having a conductor-free recess: A mountable integrated circuit package system includes: providing a carrier; mounting a first integrated circuit device over the carrier; mounting a substrate over the first integrated circuit device with the substrate having a conductor-free recess; connecting a first electrical interconnect under the conductor-free recess electrically connecting the carrier and the... Agent: Law Offices Of Mikio Ishimaru

20090108432 - Stack package made of chip scale packages: A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip... Agent: Marger Johnson & Mccollom, P.C.

20090108430 - Stacked semiconductor package in which semiconductor packages are connected using a connector: A stacked semiconductor package includes a semiconductor package module in which a plurality of semiconductor packages, which include a substrate and a semiconductor chip mounted over the substrate, are stacked. The stacked semiconductor package includes connectors for electrically connecting pairs of adjacent semiconductor packages so as to provide sequentially a... Agent: Ladas & Parry LLP

20090108433 - Multilayer semiconductor device package assembly and method: Methods for assembling multilayer semiconductor device packages are disclosed. A base substrate having device mounting sites is provided. A number of semiconductor devices are connected to the device mounting sites. Upper boards are attached to the base substrate and over each of the coupled devices. The method includes steps of... Agent: Texas Instruments Incorporated

20090108434 - Semiconductor integrated circuit device, pdp driver, and plasma display panel: In a semiconductor integrated circuit device of the present invention, temperature increase of a bonding wire can be suppressed even when conductive leads are short-circuited with each other, and reliability of the semiconductor integrated circuit device is improved. The conductive leads of a resin package for supplying a power supply... Agent: Steptoe & Johnson LLP

20090108435 - Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip... Agent: Mcginn Intellectual Property Law Group, PLLC

20090108436 - Semiconductor package: In a semiconductor package, a semiconductor chip is adhered with an adhesive member, with a circuit face of the semiconductor chip facing upward, onto a circuit board including a plurality of interconnections, a plurality of through holes, wire bonding pads and a solder resist for protecting the interconnections and the... Agent: Mcdermott Will & Emery LLP

20090108438 - Semiconductor device and method of manufacturing the same: Through heat discharge only by wiring connected to a conventional semiconductor chip, sufficient heat discharge performance may not be achieved in a recent semiconductor device. A semiconductor device according to an aspect of the present invention includes: a flexible substrate including a first main surface and a second main surface;... Agent: Mcginn Intellectual Property Law Group, PLLC

20090108437 - Wafer scale integrated thermal heat spreader: Various embodiments are directed to providing an electronic device with an integrated thermal heat spreader. In one embodiment, an electronic device may comprise an integrated circuit fabricated on a substrate and a heat spreader integrated with the electronic device after fabrication of the integrated circuit. The heat spreader may comprise... Agent: Tyco Electronics Corporation

20090108439 - Fluid cooled encapsulated microelectronic package: An encapsulated microelectronic package includes a fluid conducting cooling tube directly coupled to one or more semiconductor chips, with the encapsulant being molded over the semiconductor chips and portions of the cooling tube in proximity to the semiconductor chips. The encapsulant immobilizes the cooling tube with respect to the semiconductor... Agent: Delphi Technologies, Inc.

20090108440 - Semiconductor device: A semiconductor device is disclosed. One embodiment provides an arrangement of a plurality of semiconductor chips arranged side by side in a spaced apart relationship. A first material fills at least partly the spacings between adjacent semiconductor chips. A second material is arranged over the semiconductor chips and the first... Agent: Dicke, Billig & Czaja

20090108441 - Semiconductor clamp system: A system for clamping a plurality of semiconductors that includes: 1) a first endplate and a second endplate that are substantially parallel and oppose each other across a predetermine distance (the predetermined distance being fixed by one or more tension members that extend between the first endplate and the second... Agent: Ge Energy General Electric C/o Ernest G. Cusick

20090108444 - Chip package structure and its fabrication method: A chip package structure and its fabrication method are disclosed. Method of electrically connecting a chip with plural different metal layers is utilized to replace the conventional method of connecting identical metal layer merely. Besides, the method of a protective layer directly set on the metal layer to cover the... Agent: Rosenberg, Klein & Lee

20090108446 - Electrode structure for semiconductor chip: The bump electrode 100 of the present invention has a structure in which dummy metals 111 are provided in the uppermost layer portion of a silicon 101 between a pad-form wiring metal 102 and a wiring metal 103 such that an edge of each dummy metal and an edge of... Agent: Mcdermott Will & Emery LLP

20090108443 - Flip-chip interconnect structure: Various aspects can be implemented for providing flip-chip interconnect structures for connecting or mounting semiconductor chips to supporting substrates, such as cards, circuit boards, carriers, lead frames, and the like. In general, one aspect can be a method of providing a flip-chip interconnect structure that includes providing a semiconductor work... Agent: Fish & Richardson, PC

20090108442 - Self-assembled stress relief interface: A method of forming an interconnect assembly is provided in which contacts exposed at a face of a first element such as, for example, a microelectronic element are aligned and joined with corresponding contacts of an interconnect element confronting the face of the first element. At least one of the... Agent: International Business Machines Corporation Dept. 18g

20090108445 - Substrate structure and semiconductor package using the same: A substrate structure is provided. The substrate structure includes a substrate and a patterned wiring layer formed on the substrate. The patterned wiring layer includes a plurality of conductive traces. An isolation layer covers the patterned wiring layer and has an opening to expose a portion of at least one... Agent: Lowe Hauptman Ham & Berner, LLP

20090108448 - Metal pad of semiconductor device: A metal pad of a semiconductor device that prevents cracking during a ball bonding process in a metal pad applied to a wafer level package (WLP). The metal pad includes a main metal pad formed on and/or over a semiconductor substrate and electrically connected to a contact plug, and a... Agent: Sherr & Vaughn, PLLC

20090108447 - Semiconductor device having a fine pitch bondpad: A semiconductor device is provided, including a semiconductor chip having fine pitch bond pads, dummy bond pads, and ball bonds formed on the semiconductor chip, and electrically connected to circuits of the semiconductor chip, where the width of each fine pitch bond pad is less than the diameter of each... Agent: Marger Johnson & Mccollom, P.C.

20090108449 - Microelectronic device: A microelectronic device includes a non-polymeric substrate, an organic interlayer, and a indium tin oxide layer formed on the organic interlayer.... Agent: Hewlett Packard Company

20090108450 - Interconnect structure and method of making same: An interconnect structure and method of fabricating the same is provided. The interconnect structure is a highly reliable copper interconnect structure. The interconnect structure includes a planarized lower dielectric layer and a lower cap layer on the planarized lower dielectric layer. A copper material is formed in a trench of... Agent: Greenblum & Bernstein, P.L.C

20090108451 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a pattern layer formed on and/or over a semiconductor substrate, a fluorine-diffusion barrier layer containing a silicon-doped silicon oxide formed on and/or over the pattern layer, and an interlayer dielectric layer containing fluorine formed on and/or over the fluorine-diffusion barrier layer.... Agent: Sherr & Vaughn, PLLC

20090108452 - Semiconductor device and method for manufacturing the same: A method of manufacturing a semiconductor device including a sputtering process for forming a barrier film mainly having tantalum or tantalum nitride on an interlayer insulator formed by sputtering using a xenon gas. The sputtering process may include a step of forming one barrier film mainly composed of tantalum nitride... Agent: Masuvalley & Partners

20090108453 - Chip structure and method for fabricating the same: A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first... Agent: Mou-shiung Lin

20090108454 - Metal line in semiconductor device and fabricating method thereof: A metal line in a semiconductor device and fabricating method thereof includes a first contact plug on a substrate, a first insulating interlayer over the substrate including the first contact plug, a first etch stop layer formed over the first insulating interlayer; a trench in the first insulating interlayer and... Agent: Sherr & Vaughn, PLLC

20090108455 - Integrated circuit and process for fabricating thereof: A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Cpa Global

20090108456 - Solder-top enhanced semiconductor device and method for low parasitic impedance packaging: p

20090108457 - Apparatus for improved power distribution in a three dimensional vertical integrated circuit: A first through via is electrically insulated from surrounding wafer substrate material. A second through via is not electrically insulated from the surrounding wafer substrate material. This configuration is advantageous when the non-insulated via serves as the path for either Vdd or GND. By not insulating the through via, a... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20090108459 - Semiconductor device: A semiconductor device includes first underlying lines in an underlying wiring layer electrically connected to and shaped like a first semiconductor region, second underlying lines in the underlying wiring layer electrically connected to and shaped like a second semiconductor region, a first intermediate line in an intermediate wiring layer electrically... Agent: Young & Thompson

20090108458 - Semiconductor structure and method of manufacture: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, an electrical bus embedded in a dielectric material below a surface of a semiconductor substrate is disclosed. Other embodiments are described and claimed.... Agent: Hvvi Semiconductors, Inc.

20090108465 - Ceramic substrate grid structure for the creation of virtual coax arrangement: Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20090108460 - Device including a semiconductor chip having a plurality of electrodes: A device, including a semiconductor chip having a plurality of first electrodes is disclosed. A plurality of second electrodes is arranged on a first surface of the semiconductor chip. A first electrically conductive layer is applied over a first section of the first surface and electrically coupled to the first... Agent: Dicke, Billig & Czaja

20090108462 - Dual integration scheme for low resistance metal layers: By forming a metal line extending through the entire interlayer dielectric material in resistance sensitive metallization layers, enhanced uniformity of these metallization layers may be obtained. The patterning of respective via openings may be accomplished on the basis of a recess formed in a cap layer, which additionally acts as... Agent: Williams, Morgan & Amerson

20090108463 - Method of manufacturing semiconductor device and semiconductor device: According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a wiring layer over a substrate, forming a first film over the wiring layer, forming a second film over the first film, selectively etching the first and second films to form an first end... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090108464 - Semiconductor device and method for manufacturing the same: A first insulating layer including a first contact pad made of conductive polysilicon and a second insulating layer including a second contact pad are formed over a semiconductor silicon layer. After this, a via hole for a through-hole electrode is formed until the via hole penetrates through at least the... Agent: Young & Thompson

20090108461 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device includes providing a semiconductor substrate including a first landing plug and a second landing plug. A bit line is formed over the semiconductor substrate. The bit line is electrically coupled to the first landing plug. A stacked structure of an etch stop film... Agent: Townsend And Townsend And Crew, LLP

20090108466 - Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process: Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore,... Agent: Williams, Morgan & Amerson

20090108469 - Chip stack package: A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via... Agent: Marger Johnson & Mccollom, P.C.

20090108467 - Device with a plurality of semiconductor chips: A device with a plurality of semiconductor chips is disclosed. One embodiment provides a substrate. A first semiconductor chip is mounted over the substrate. A second semiconductor chip is mounted over the first semiconductor chip. A first electrically conducting element electrically couples the second semiconductor chip to the substrate and... Agent: Dicke, Billig & Czaja

20090108470 - Semiconductor device: A element group includes a plurality of semiconductor elements stacked in a step-like shape on a wiring board. The semiconductor elements are electrically connect to connection pads of the wiring board through metal wires. Among the plural semiconductor elements stacked in a step-like shape, the uppermost semiconductor element has a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090108468 - Stacked semiconductor package and method for manufacturing the same: A stacked semiconductor package includes a semiconductor chip module including at least two semiconductor chips, each semiconductor chip having a first face, a second face opposite to the first face, and a circuit part. A thorough portion passes through the first and second faces of the semiconductor chip. A recess... Agent: Ladas & Parry LLP

20090108471 - Wiring board of semiconductor device, semiconductor device, electronic apparatus, mother board, method of manufacturing wiring board of semiconductor device, method of manufacturing mother board and method of manufacturing electronic apparatus: In a wiring board of a semiconductor device according to the present invention, a land 9 provided with convex portions/concave portions arranged so as to comprise finite rotation symmetry is provided on a substrate 13 of a wiring board 1, a side surface and a part of a vicinity of... Agent: Mcginn Intellectual Property Law Group, PLLC

20090108472 - Wafer-level underfill process using over-bump-applied resin: A process of fabricating wafer-level underfilled microelectronic packages using over-bump application of a self-fluxing resin to a wafer, b-staging of the resin, dicing of the coated wafer, and joining the diced chips to substrates producing wafer-level underfilled microelectronic flip-chip packages. Moreover, provided are microelectronic packages, which are produced in accordance... Agent: Scully, Scott, Murphy & Presser, P.C.

20090108473 - Die-attach material overflow control for die protection in integrated circuit packages: Methods, systems, and apparatuses for integrated circuit packages are provided. An integrated circuit package includes a metal layer, an integrated circuit die, and an adhesive material. The metal layer has a first surface that has a die-attach region. The metal layer further has one or more recessed regions formed in... Agent: Fiala & Weaver, P.l.l.c. C/o Cpa Global

20090108474 - Junction structure and method of manufacturing the same: A junction structure and a method of manufacturing the same are provided which can achieve stable wire bonding between a Poly-Si film bonding pad and an Al wire. The junction structure is made up of a SiO2 film 5 formed on Si 4, a BPSG film 6 formed on the... Agent: Steptoe & Johnson LLP

20090101879 - Method for making self aligning pillar memory cell device: A method for making a memory cell assembly includes forming a memory cell access layer over a substrate to create an access device with a bottom electrode. A memory material layer is formed over the memory cell access layer in electrical contact with the bottom electrode. A first electrically conductive... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090101880 - Phase change memory devices and methods for fabricating the same: An exemplary memory device includes a first dielectric layer with a first conductive contact therein. A phase change material (PCM) is disposed on top of the first dielectric layer and provided with an insulating layer integrally on a top surface of the PCM. A first electrode is disposed over the... Agent: Quintero Law Office, PC

20090101881 - Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same: In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically... Agent: Marger Johnson & Mccollom, P.C.

20090101883 - Method for manufacturing a resistor random access memory with a self-aligned air gap insulator: A memory device including a programmable resistive memory material is described along with methods for manufacturing the memory device. A memory device disclosed herein includes top and bottom electrodes and a multilayer stack disposed between the top and bottom electrodes. The multilayer stack includes a memory element comprising programmable resistive... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090101884 - Phase change memory devices and methods for fabricating the same: Phase change memory devices and methods for fabricating the same are provided. A phase change memory device includes a first conductive electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer. A phase change material layer is disposed in the second dielectric... Agent: Quintero Law Office, PC

20090101882 - Programmable via devices: A device comprises a heater, a dielectric layer, a phase-change element, and a capping layer. The dielectric layer is disposed at least partially on the heater and defines an opening having a lower portion and an upper portion. The phase-change element occupies the lower portion of the opening and is... Agent: Ryan, Mason & Lewis, LLP

20090101885 - Method of producing phase change memory device: An area where a lower electrode is in contact with a variable resistance material needs to be reduced in order to lower the power consumption of a variable resistance memory device. The present invention provides a method of producing a variable resistance memory element whereby the lower electrode can be... Agent: Foley And Lardner LLP Suite 500

20090101886 - Semiconductor light-emitting device and method of fabricating the same: The invention discloses a semiconductor light-emitting device. The semiconductor light-emitting device includes a substrate, a first semiconductor material layer, a light-emitting layer, a second semiconductor material layer, a first transparent insulating layer, a metal layer and at least one electrode. The first semiconductor material layer, the light-emitting layer, and the... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090101888 - Method of manufacturing in (as) sb semiconductor on lattice-mismatched substrate and semiconductor device using the same: Disclosed is a method of manufacturing a semiconductor device whereby InAs(1-x)Sbx semiconductor layer is formed on an easily available and economical semiconductor substrate such as a GaAs substrate or a Si substrate. According to the method, a quantum dot layer is formed between a semiconductor substrate and a semiconductor layer... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20090101887 - Silicon germanium heterostructure barrier varactor: Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of... Agent: Law Office Of Delio & Peterson, LLC.

20090101889 - Optically interface electrically controlled devices: The present invention presents devices and methods for localized control and transport of excitons as well as separate processing of holes and electrons in a device with an optical input and an optical output. In an embodiment of the invention, an optoelectronic device includes a coupled or wide quantum well... Agent: Greer, Burns & Crain

20090101890 - Azaperylenes as organic semiconductors: A novel semiconductor device comprises an azaperylene organic semiconductor of the formula I (I) wherein each of R1, R2, R3 and R4 independently is selected from H, unsubstituted or substituted alkyl, unsubstituted or substituted alkenyl, unsubstituted or substituted alkynyl, unsubstituted or substituted aryl, halogen, Si(RH)3, XR6; or one or more... Agent: Joann Villamizar Ciba Corporation/patent Department

20090101894 - Method for fabricating metal-oxide semiconductor transistors: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing carbon, boron, and hydrogen into the semiconductor substrate... Agent: North America Intellectual Property Corporation

20090101891 - Multi-layered bipolar field-effect transistor and method of manufacturing the same: Disclosed herein is a multi-layered bipolar field-effect transistor, including a gate electrode, a gate insulating layer, an electron transport layer, a hole transport layer, a source electrode, and a drain electrode, in which an intermediate separating layer is formed between the electron transport layer and the hole transport layer, and... Agent: Harness, Dickey & Pierce, P.L.C

20090101893 - Organic thin film transistors: A method of forming an organic thin film transistor comprising source and drain electrodes with a channel region therebetween, a gate electrode, a dielectric layer disposed between the source and drain electrodes and the gate electrode, and an organic semiconductor disposed in at least the channel region between the source... Agent: Marshall, Gerstein & Borun LLP

20090101892 - Organic underlayers that improve the performance of organic semiconductors: A process for producing high performance organic thin film transistors in which the molecules in the organic thin film are highly ordered and oriented to maximize the mobility of current charge carriers. The uniform monolayer surface over various substrate materials so formed, result in a more reproducible and readily manufacturable... Agent: Thomas A. Beck Esq.

20090101895 - Display device: A display device includes a pixel including: a gate line; a gate insulating film; a substrate; a data line; a pixel electrode; a semiconductor layer formed on the gate line and the gate insulating film; a protective film formed on the data line, the pixel electrode, and the semiconductor layer;... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090101898 - Method and resulting structure for fabricating test key structures in dram structures: A method for fabricating test structures on a wafer for integrated circuits. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of integrated circuit chip structures on the semiconductor substrate and forming a plurality of MOS devices on a scribe line formed between... Agent: Townsend And Townsend And Crew, LLP

20090101897 - Package for a light emitting element: A high-brightness LED module includes a substrate with a recess in which a light emitting element is mounted. The recess is defined by a sidewalls and a relatively thin membrane. At least two micro-vias are provided in the membrane and include conductive material that passes through the membrane. A p-contact... Agent: Fish & Richardson P.C.

20090101896 - Semiconductor device: In a semiconductor device, a semiconductor chip is connected to a board through an interconnection layer. A plurality of first terminals, a plurality of second terminals and a plurality of third terminals are provided on the board, the interconnection layer and the semiconductor chip, respectively. The second terminals are connected... Agent: Mcdermott Will & Emery LLP

20090101899 - Stacked structure and method of patterning the same and organic thin film transistor and array having the same: A stacked structure including a soluble organic semiconductor material and a water soluble photosensitive material is provided. The water soluble photosensitive material is disposed on the surface of the soluble organic semiconductor material.... Agent: Jianq Chyun Intellectual Property Office

20090101904 - Display device: Disclosed herein is a display device including: a support substrate; a drive circuit provided on the support substrate; an interlayer insulating film which covers the drive circuit; organic field light-emitting elements arranged in a display region on the interlayer insulating film; and a lead-out wiring extended from the organic field... Agent: Sonnenschein Nath & Rosenthal LLP

20090101902 - Display device and method of manufacturing the same: A substrate comprising a thin-film-transistor (TFT) region, a pixel region, a gate-line region and a data-line region is provided. A transparent conductive layer and a first metal layer are orderly formed on the substrate. A conductive stack layer is formed within each of the TFT/pixel/gate-line regions and the end of... Agent: Bacon & Thomas, PLLC

20090101905 - Display unit and method of manufacturing the same: A display unit includes, on an insulating substrate, a plurality of wirings formed to extend in different directions, a thin-film transistor, and a display element. At least one of the plurality of wirings is a divided wiring having a crossing portion formed at an intersection with the other of the... Agent: Sonnenschein Nath & Rosenthal LLP

20090101907 - Image detector: An image detector which includes an active matrix substrate and a protection substrate bonded to the active matrix substrate by an insulating bonding member, in which the insulating bonding member is bonded to the active matrix substrate through an inorganic insulating film disposed in an area around the periphery of... Agent: Sughrue Mion, PLLC

20090101908 - Liquid crystal display device and method of fabricating the same: A method of fabricating an LCD device includes forming a gate line, a gate electrode, a gate pad electrode at an end of the gate line, and a common line on a substrate; forming a gate insulating layer on the gate electrode; forming an active layer on the gate insulating... Agent: Mckenna Long & Aldridge LLP

20090101900 - Optical sensor with photo tft: An optical sensor is disclosed. Each sensor pixel circuit of the optical sensor includes a first readout TFT for reading out voltage of a charge node, a second readout TFT for controllably resetting the charge node to a first reset voltage, and a photo TFT for discharging the voltage at... Agent: Squire, Sanders & Dempsey L.L.P.

20090101901 - Semiconductor device and manufacturing method thereof: By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase... Agent: Cook Alex Ltd

20090101906 - Semiconductor device and method for manufacturing semiconductor device: A first resist pattern is formed by exposure using a first multi-tone photomask, and a first conductive layer, a first insulating layer, a first semiconductor layer, and a second semiconductor layer are etched, so that an island-shaped single layer and an island-shaped stack are formed. Here, sidewalls are formed on... Agent: Fish & Richardson P.C.

20090101903 - Thin film transistor and method for manufaturing thereof: A thin-film transistor (TFT) includes a gate electrode, a gate dielectric layer, a semiconductor layer, source/drain electrodes, a passivation layer and a protection layer. The gate electrode is disposed on a substrate. The gate dielectric layer covers the gate electrode and the substrate. The semiconductor layer is disposed on the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090101909 - Semiconductor photodetectors: In one aspect, a method includes forming a pit in a top surface of a substrate by removing a portion of the substrate and growing a semiconductor material with a bottom surface on the pit, the semiconductor material different than the material of the substrate. The pit has a base... Agent: Occhiuti Rohlicek & Tsao, LLP

20090101911 - Thin film transistor, display device having the same, and associated methods: A thin film transistor (TFT), including a substrate, an active layer and a gate electrode on the substrate, and a first gate insulating layer and a second gate insulating layer between the active layer and the gate electrode. Each of the first gate insulating layer and the second gate insulating... Agent: Lee & Morse, P.C.

20090101910 - Thin-film transistor: A gate-insulated thin film transistor is disclosed. One improvement is that the thin film transistor is formed on a substrate through a blocking layer in between so that it is possible to prevent the transistor from being contaminated with impurities such as alkali ions which exist in the substrate. Also,... Agent: Nixon Peabody, LLP

20090101912 - Active device array for reducing delay of scan signal and flat panel display using the same: An active device array and flat panel display using the same are provided. The active device array includes a plurality of pixels, a plurality of scan-lines, a plurality of data-lines and a plurality of auxiliary scan-lines, wherein each pixel is electrically connected to a corresponding scan-line and a corresponding data-line.... Agent: Jianq Chyun Intellectual Property Office

20090101913 - Apparatus and method for reducing photo leakage current for tft lcd: A method of forming a thin film transistor (TFT) array panel, comprising the steps of: (i) forming a patterned first conductive layer, which includes a gate line and a shielding portion, on a substrate, (ii) forming a gate insulating layer on the patterned first conductive layer and the substrate, (iii)... Agent: Morris Manning Martin LLP

20090101916 - Microcrystalline semiconductor film, thin film transistor, and display device including thin film transistor: A thin film transistor with excellent electric characteristics and a display device having the thin film transistor are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode; a microcrystalline semiconductor film including an impurity element which serves as a donor, formed over the gate... Agent: Eric Robinson

20090101915 - Photo sensor and fabrication method thereof: A photo sensor includes a patterned shielding conductive layer disposed on a transparent substrate, and a buffer dielectric layer, a patterned semiconductor layer, and a dielectric layer disposed on the patterned shielding layer in order. The patterned semiconductor layer includes an intrinsic region, a first doped region, and a second... Agent: North America Intellectual Property Corporation

20090101914 - Semiconductor image sensing device: A signal charge corresponding to an incident light quantity is accumulated in a first node of each pixel circuit. An accumulated charge exhaust circuit includes each of first nodes of the plurality of pixel circuits belonging to the same pixel group, and a second node connected through discharge gates functioning... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090101917 - Thin film transistor substrate and display apparatus having the same: s

20090101918 - Semiconductor element and method for manufacturing same: A semiconductor device includes: a semiconductor layer 10; a semiconductor region 15s of a first conductivity type defined on the surface 10s of the semiconductor layer; a semiconductor region 14s of a second conductivity type defined on the surface 10s of the semiconductor layer to surround the semiconductor region 15s;... Agent: Mark D. Saralino (pan) Renner, Otto, Boisselle & Sklar, LLP

20090101919 - Photo-detector array, semiconductor image intensifier and methods of making and using the same: A sensor including an array of light sensitive pixels, each pixel including: at least one hetero-junction phototransistor having a floating base without contact, wherein each phototransistor is a mesa device having active layers exposed at side-walls of the mesa device; and at least one atomic layer deposited high-k dielectric material... Agent: Gibbons P.C.

20090101920 - White light emitting element and white light source: A white light source has an excitation light source and a white light emitting element provided at a position which allows the transmission of light from the excitation light source to generate white light through irradiation with the light from the excitation light source. The white light emitting element has... Agent: Greenblum & Bernstein, P.L.C

20090101921 - Led and thermal conductivity device combination assembly: AN LED and thermal conductivity device combination assembly includes a thermal conductivity device, two conducting members each having a metal conducting wire and an insulator surrounding the metal conducting wire and attached to the thermal conductivity device, LED chips each having a positive electrode and a negative electrode disposed at... Agent: Bacon & Thomas, PLLC

20090101922 - Led arrangement for producing pure monochomatic light: In an LED arrangement, two or more LEDs are particularly positioned for the color lights emitted therefrom to be fully mixed to produce a pure monochromatic light. The LEDs may include at least two identical LEDs, and each of the LEDs includes at least two light emitting chips that separately... Agent: Wpat, PC

20090101923 - Semiconductor light emitting device, method of manufacturing the same, and semiconductor light emitting device package using the same: There is provided a semiconductor light emitting device, a method of manufacturing the same, and a semiconductor light emitting device package using the same. A semiconductor light emitting device having a first conductivity type semiconductor layer, an active layer, a second conductivity type semiconductor layer, a second electrode layer, and... Agent: Mcdermott Will & Emery LLP

20090101924 - Gallium nitride semiconductor device on soi and process for making same: Methods and apparatus for producing a gallium nitride semiconductor on insulator structure include: bonding a single crystal silicon layer to a transparent substrate; and growing a single crystal gallium nitride layer on the single crystal silicon layer.... Agent: Corning Incorporated

20090101925 - Light emitting element and method for manufacturing the same: A light emitting element including: a growth substrate, which has, as a main plane, a plane on which cleavage directions are orthogonal to each other; a first nitride semiconductor layer formed on the main plane of the growth substrate; an active layer formed on the first nitride semiconductor layer; and... Agent: Rabin & Berdo, PC

20090101926 - Semiconductor light emitting device and method of manufacturing the same: Provided are a semiconductor light emitting device and a method of manufacturing the same. The semiconductor light emitting device comprises a first conductive type semiconductor layer, an active layer divided in plurality on the first conductive type semiconductor layer, and a second conductive type semiconductor layer divided in plurality on... Agent: Birch Stewart Kolasch & Birch

20090101927 - Method of manufacturing light emitting device: A method of manufacturing a semiconductor light emitting device employs a substrate formed by successively stacking an n-type semiconductor layered portion including an AlGaN layer, a light emitting layer containing In and a p-type semiconductor layered portion on a group III nitride semiconductor substrate having a larger lattice constant than... Agent: Rabin & Berdo, PC

20090101930 - Light emitting device with phosphor wavelength conversion: A light emitting device comprises an excitation source (20), one or more light emitting diode(s) operable to generate excitation light of a first wavelength range (λ1) and a light emitting surface (14) having a phosphor material (26) which absorbs at least a part of the excitation light and emits light... Agent: Fliesler Meyer LLP

20090101928 - Light emitting diode and method of fabricating the same: Provided are a light emitting diode and a method of fabricating the same. In an inorganic light emitting diode, at least one layer selected from a group consisting of an oxide layer, a nitride layer, and a metal layer is formed on an upper doping layer which is in contact... Agent: Ladas & Parry LLP

20090101931 - Light emitting diode structures: Light emitting diode (LED) structures are described that include a first layer and a light-generating layer, wherein light generated in the light-generating layer generally emerges from the LED structure through the upper surface of the first layer. The coupling out of light generated by spontaneous emission is enhanced by the... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20090101929 - Robust led structure for substrate lift-off: An etching step is performed on an LED/substrate wafer to etch through the LED epitaxial layers entirely around each LED on the substrate wafer to form a gap between each LED on the wafer. The substrate is not etched. When the LEDs/substrates are singulated, edges of each substrate extend beyond... Agent: Philips Intellectual Property & Standards

20090101933 - Semiconductor light emitting device and fabrication method of the semiconductor light emitting device: A semiconductor light emitting device which can control of current density and can optimize current density and in which a rise in luminosity is possible, and a fabrication method of the semiconductor light emitting device are provided. The semiconductor light emitting device including: a semiconductor substrate structure including a semiconductor... Agent: Rabin & Berdo, PC

20090101932 - Semiconductor light-emitting device and method of fabricating the same: The invention provides a semiconductor light-emitting device package structure. The semiconductor light-emitting device package structure includes a substrate, N sub-mounts, and N semiconductor light-emitting die modules, wherein N is a positive integer lager than or equal to 1. Each of the sub-mounts is embedded on the substrate and exposed partially.... Agent: Reed Smith LLP

20090101934 - Monolithic white light-emitting diode: The invention relates to a device comprising a matrix made of III-V nitride, said matrix comprising at least an active first portion through which an electrical current passes and at least a passive second portion through which no electrical current passes, said matrix comprising at least a first zone forming... Agent: Harness, Dickey & Pierce, P.L.C

20090101935 - Nitride semiconductor and method for manufacturing same: A nitride semiconductor includes: a substrate having a major surface including a first crystal polarity surface and a second crystal polarity surface different from the first crystal polarity surface; and a single polarity layer provided above the major surface and having a single crystal polarity.... Agent: Amin, Turocy & Calvin, LLP

20090101936 - Semiconductor light emitting element and wafer: There are provided a semiconductor light emitting element which allows an improvement in light extraction efficiency without increasing the number of fabrication steps, and a wafer. In a semiconductor light emitting element 1 formed by laminating a compound semiconductor layer 3 on a single crystal substrate, and dividing the single... Agent: Mcdermott Will & Emery LLP

20090101937 - Novel method for four direction low capacitance esd protection: The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20090101938 - Electrostatic discharge protection circuit: The present invention provides an electrostatic discharge (ESD) protection circuit with a silicon controlled rectifier (SCR) having a plurality of SCR fingers (SCRs) with the advantages to couple the different fingers or SCRs to decrease the multi-triggering problem and to increase the ESD-performance of the circuit. Additionally, a boost circuit... Agent: Patent Docket Administrator Lowenstein Sandler P.C.

20090101939 - Group iii nitride field effect transistors (fets) capable of withstanding high temperature reverse bias test conditions: Group III Nitride based field effect transistor (FETs) are provided having a power degradation of less than about 3.0 dB when operated at a drain-to-source voltage (VDS) of about from about 28 to about 70 volts, a gate to source voltage (Vgs) of from about −3.3 to about −14 volts... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090101940 - Dual gate fet structures for flexible gate array design methodologies: A gate array cell adapted for standard cell design methodology or programmable gate array that incorporates a dual gate FET device to offer a range of performance options within the same unit cell area. The conductivity and drive strength of the dual gate device may be selectively tuned through independent... Agent: Ibm Microelectronics Intellectual Property Law

20090101941 - Wrapped gate junction field effect transistor: A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conductivity type doping, which is the opposite of... Agent: Scully, Scott, Murphy & Presser, P.C.

20090101944 - Electronic device and method for manufacturing the same: It is made possible to form an interelectrode gap with high precision, without a decrease in the simplicity and convenience of the process to be carried out by an ink jet technique. A method for manufacturing an electronic device, includes: applying a water repellent agent onto a substrate by an... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090101942 - Planar field effect transistor structure and method: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090101943 - Reversely tapered contact structure compatible with dual stress liner process: A semiconductor device having a silicon layer, a transistor having an electrical connection region in the silicon layer; and a conductive plug formed on and in electrical contact with the electrical connection region, the plug having side walls that taper inward away from the silicon layer.... Agent: Banner & Witcoff, Ltd.

20090101945 - Semiconductor device: A semiconductor device includes: a semiconductor substrate; an N-type MOSFET formed in a surface of the semiconductor substrate; a tensile stress film provided on the semiconductor substrate at least around a directly overlying region of a channel region of the N-type MOSFET and having tensile stress therein; and a compressive... Agent: Foley And Lardner LLP Suite 500

20090101946 - Cmos image sensor and method for manufacturing the same: A CIS and a method for manufacturing the same are provided. The CIS includes an interlayer insulation layer formed on a substrate having a photodiode and a transistor formed thereon; a plurality of color filters formed on the interlayer insulation layer and spaced a predetermined interval apart from each other;... Agent: Jeff Lloyd, Saliwanchik, Lloyd & Saliwanchik A Professional Association

20090101951 - Cmos image sensor and fabricating method thereof: A CMOS image sensor and fabricating method thereof are disclosed. The method includes forming a plurality of photodiode regions on a semiconductor substrate, forming a plurality of color filters respectively corresponding to the photodiode regions, forming a planarization layer on the color filters, forming a protective layer on the planarization... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090101950 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same. In one example embodiment, a method for fabricating a CMOS image sensor includes various steps. First, an interlayer dielectric that includes a plurality of metal lines is formed on a semiconductor substrate that includes a photodiode. Next, a trench... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090101948 - Cmos image sensors having transparent transistors and methods of manufacturing the same: CMOS image sensors having transparent transistors and methods of manufacturing the same are provided. The CMOS image sensors include a photodiode and at least one transistor formed on the photodiode. The image sensor may include a plurality of transistors wherein at least one of the plurality of transistors is a... Agent: Harness, Dickey & Pierce, P.L.C

20090101952 - Image sensor and method for manufacturing the same: An image sensor and a method for manufacturing the same that includes photodiodes formed in a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, the first insulating layer including a seed pattern corresponding spatially to the positions of the photodiodes, lower microlenses composed of an organic material... Agent: Sherr & Vaughn, PLLC

20090101949 - Image sensor and method for manufacturing the same: An image sensor having maximized photosensitivity includes a photodiode and a transistor formed over the semiconductor substrate. A first passivation layer is formed over the semiconductor substrate including the transistor and the photodiode, a pre-metal dielectric layer formed over the first passivation layer and insulating layers having metal wirings formed... Agent: Sherr & Vaughn, PLLC

20090101947 - Image sensor device and fabrication method thereof: An image sensor device is disclosed. The image sensor device comprises a substrate having a pixel array therein. A first transparent layer with a curved surface is disposed on the substrate. A micro lens array is conformally disposed on the curved surface of the first transparent layer and corresponds to... Agent: Joe Mckinney Muncy

20090101953 - Photoelectric conversion element and solid-state imaging device: A photoelectric conversion element is provided and includes a photoelectric conversion portion which includes: a pair of electrodes including an electron-collecting electrode and a hole-collecting electrode; and a photoelectric conversion layer between the pair of electrodes. At least part of the photoelectric conversion layer includes a mixture layer of a... Agent: Sughrue-265550

20090101954 - Capacitor and semiconductor device having a ferroelectric material: A capacitor includes a pair of electrodes and a ferroelectric film sandwiched between the electrodes. The electrodes are provided perpendicular to the direction of the polarization axis of the ferroelectric film.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090101955 - Molecular electronic device and method of fabricating the same: A molecular electronic device, and a method of fabricating the same, includes a first electrode having a plurality of prominences and depressions on which a plurality of molecules are self-assembled. Capacitance of a molecular electronic device used as a capacitor is increased by forming prominences and depressions on the surface... Agent: Lowe Hauptman Ham & Berner, LLP

20090101956 - Embedded trench capacitor having a high-k node dielectric and a metallic inner electrode: A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device region after removal of... Agent: Scully, Scott, Murphy & Presser, P.C.

20090101957 - Simplified method of fabricating isolated and merged trench capacitors: Trench capacitors having small and large sizes can be formed simultaneously using a combined lithography process in which openings in a photomask have the same dimensions and spacings. Larger capacitors are formed when the openings in the photomask are aligned with one crystal plane of the semiconductor substrate causing the... Agent: International Business Machines Corporation Dept. 18g

20090101958 - Trench soi-dram cell and method for making the same: The present invention relates to a trench silicon-on-insulator (SOI) dynamic random access memory (DRAM) cell and a method for making the same. A source and a drain are utilized to each connect to one of two semiconductor conductive units on an external side of a main body having a plurality... Agent: Volentine & Whitt PLLC

20090101959 - Nonvolatile semiconductor memory device and method for manufacturing the same: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a semiconductor substrate; memory cell transistors that are series-connected; and a select transistor that includes: a first diffusion region that is formed in the semiconductor substrate at one end of the memory cell... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090101960 - Semiconductor memory device: According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: a contact region; a select gate region; and a memory cell region; a first element isolation region formed in the contact region and having a first depth; a second element... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090101961 - Memory devices with split gate and blocking layer: The present disclosure provides a memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, a tantalum-nitride layer, and a control gate layer. When a positive bias is... Agent: Macpherson Kwok Chen & Heid LLP

20090101962 - Semiconductor devices and methods of manufacturing and operating same: A semiconductor device and methods of manufacturing and operating the semiconductor device may be disclosed. The semiconductor device may comprise different nanostructures. The semiconductor device may have a first element formed of nanowires and a second element formed of nanoparticles. The nanowires may be ambipolar carbon nanotubes (CNTs). The first... Agent: Harness, Dickey & Pierce, P.L.C

20090101965 - Electron blocking layers for electronic devices: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium... Agent: Brinks Hofer Gilson & Lione

20090101964 - Method of forming nano dots, method of fabricating the memory device including the same, charge trap layer including the nano dots and memory device including the same: Provided are a method of forming nano dots, method of fabricating a memory device including the same, charge trap layer including the nano dots and memory device including the same. The method of forming the nano dots may include forming cores, coating surfaces of the cores with a polymer, and... Agent: Harness, Dickey & Pierce, P.L.C

20090101966 - Method of identifying logical information in a programming and erasing cell by on-side reading scheme: A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage... Agent: Rabin & Berdo, PC

20090101963 - Split charge storage node inner spacer process: Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first... Agent: Amin, Turocy & Calvin, LLP

20090101967 - Semiconductor device and method for manufacturing the same: A semiconductor device includes an insulating layer, a channel structure, an insulating structure and a gate. The channel structure includes a channel bridge for connecting two platforms. The bottom of the channel bridge is separated from the insulating layer by a distance, and the channel bridge has a plurality of... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090101968 - Structure of semiconductor device and manufacturing method of the same: A field effect transistor configured in a convex type Fin structure, in which diffusion layer 104 serving as source and drain regions is formed in a semiconductor layer that is sandwiched by STI regions 105 and projected upward of the isolation region, and which has a gate electrode overlapping a... Agent: Sughrue Mion, PLLC

20090101969 - Semiconductor device and method of manufacturing the same: A semiconductor device comprising: a semiconductor substrate; a first conductive layer provided on a surface of the substrate and serving as one of a source and a drain; a first insulating film provided on the first conductive layer; a gate electrode film provided on the first insulating film; a second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090101970 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device including a vertical cell transistor structure may include forming a vertical cell transistor structure over a semiconductor substrate of a cell region; forming an insulating film over the vertical cell transistor structure; planarizing the insulating film to expose a hard mask film disposed... Agent: Marshall, Gerstein & Borun LLP

20090101971 - Semiconductor device, manufacturing method thereof, and data processing system: A bottom of a gate trench has a first bottom relatively far from an STI and a second bottom relatively near from the STI A portion, in an active region, configuring the second bottom of the gate trench configures a side-wall channel region, and has a thin-film SOI structure sandwiched... Agent: Young & Thompson

20090101972 - Process for fabricating a field-effect transistor with doping segregation used in source and/or drain: Source and/or drain regions of a transistor are first doped with an appropriate dopant and a metal is subsequently deposited. After heating, a silicide will displace the dopant, creating an increased density of dopants at the border of the silicided region. The dopants that are adjacent to or in the... Agent: Sonnenschein Nath & Rosenthal LLP

20090101973 - Field effect transistor formed on an insulating substrate and integrated circuit thereof: A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type... Agent: Bruce L. Adams, Esq.

20090101974 - Semiconductor device: A semiconductor device includes an n+ type semiconductor substrate 1 and a super junction region that has, on the top of the substrate 1, an n and p type pillar regions 2 and 3 provided alternately. The device also includes, in the top surface of the super junction region, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090101976 - Body tie test structure for accurate body effect measurement: A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20090101975 - Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor: An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD1) in comparison with other transistors (T2) on the same integrated circuit arrangement (10). As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a... Agent: Slater & Matsil LLP

20090101977 - Semiconductor device and method for manufacturing the same: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor... Agent: Mcdermott Will & Emery LLP

20090101978 - Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure: Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090101980 - Method of fabricating a gate structure and the structure thereof: A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by... Agent: Hoffman Warnick LLC

20090101979 - Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon and devices formed thereby: Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial... Agent: Myers Bigel Sibley & Sajovec

20090101981 - One-transistor type dram: A one-transistor type DRAM simplifies a manufacturing process and reduces the height of a chip. In the one-transistor type DRAM, an active region is defined by a device isolating film. A first word line and a second word line extend across the active region and the device isolating film. A... Agent: Ladas & Parry LLP

20090101982 - Semiconductor device and manufacturing method thereof: A semiconductor device according to an embodiment of the present invention comprises: a semiconductor substrate; a first field-effect transistor formed on the semiconductor substrate, and including a fin constituted by a semiconductor layer having source and drain regions via a channel region in an extending direction, and a gate electrode... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090101983 - Method of achieving dense-pitch interconnect patterning in integrated circuits: Components in integrated circuits (ICs) are fabricated as small as possible to minimize sizes of the ICs and thus reduce manufacturing costs per IC. Metal interconnect lines are formed on minimum pitches possible using available photolithographic printers. Minimum pitches possible for contacts and vias are larger than minimum pitches possible... Agent: Texas Instruments Incorporated

20090101986 - Semiconductor device and electronic apparatus: A semiconductor device includes: a substrate having a first surface; an insulation layer; a semiconductor layer disposed to the first surface of the substrate with the insulation layer interposed between the semiconductor layer and the first surface; and a piezoelectric layer that is positioned between the first surface and the... Agent: Oliff & Berridge, PLC

20090101987 - Semiconductor device and method for manufacturing same: A semiconductor device includes: a semiconductor substrate; a p-channel field effect transistor formed in a first region of the semiconductor substrate; an n-channel field effect transistor formed in a second region of the semiconductor substrate; a compressive stress film with a compressive stress generated inside, the compressive stress film covering... Agent: Foley And Lardner LLP Suite 500

20090101984 - Semiconductor device having gate electrode including metal layer and method of manufacturing the same: A semiconductor device may include a gate dielectric film on a semiconductor substrate and/or a gate electrode. The gate electrode may include a first metal film, a first metal silicide film, and/or a conductive polysilicon film sequentially stacked on the gate dielectric film.... Agent: Harness, Dickey & Pierce, P.L.C

20090101985 - Trilayer resist scheme for gate etching applications: A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer... Agent: Scully, Scott, Murphy & Presser, P.C.

20090101988 - Bipolar transistors with resistors: Bipolar transistors in complimentary MOS (CMOS) integrated circuits (ICs) are often fabricated as parasitic components, in which emitters of bipolar transistors are implanted in the same processes as CMOS sources/drains, to avoid manufacturing costs associated with dedicated implants for bipolar emitters. Energies and doses of CMOS source/drain implants are typically... Agent: Texas Instruments Incorporated

20090101989 - Metal gate compatible electrical fuse: A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090101990 - Simiconductor integrated circuit device and method of manufacturing the same: A semiconductor integrated circuit device includes a first dopant region in a semiconductor substrate, an isolation region on the semiconductor substrate, the isolation region surrounding the first dopant region, a gate wire surrounding at least a portion of the isolation region, and a plurality of second dopant regions arranged along... Agent: Lee & Morse, P.C.

20090101991 - Semiconductor device and method of fabricating the same: A semiconductor device includes a device isolation structure having a grounded conductive layer to define an active region, and a gate formed over the active region and the device isolation structure.... Agent: Townsend And Townsend And Crew, LLP

20090101992 - Method of forming a transistor having gate protection and transistor formed according to the method: A microelectronic device and a method of forming same. The method comprises: a transistor gate; a first spacer and a second spacer respectively adjacent a first side and a second side of the gate; a diffusion layer supra-adjacent the gate; contact regions super-adjacent the diffusion layer and adjacent the first... Agent: Intel Corporation C/o Cpa Global

20090101993 - High-temperature stable gate structure with metallic electrode: The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has... Agent: Scully, Scott, Murphy & Presser, P.C.

20090101995 - Process for fabrication of finfets: A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090101994 - Semiconductor device and method for fabricating the same: A semiconductor device and a method for fabricating the same are disclosed. The semiconductor device includes a semiconductor substrate having an active region and a device isolation region defining the active region, and a resistor string formed over the active region.... Agent: Sherr & Vaughn, PLLC

20090101996 - Nanostructures with electrodeposited nanoparticles: A nanoelectronic device includes a nanostructure, such as a nanotube or network of nanotube, disposed on a substrate. Nanoparticles are disposed on or adjacent to the nanostructure so as to operatively effect the electrical properties of the nanostructure. The nanoparticles may be composed of metals, metal oxides or salts and... Agent: Weaver Austin Villeneuve & Sampson LLP

20090101997 - Micromechanical capacitive pressure transducer and production method: In a further method step, a diaphragm with a second electrode is produced at the surface of the semiconductor substrate. Furthermore, it is provided to apply a first layer, which preferably is made of dielectric material, on the diaphragm and the semiconductor substrate. With the aid of this first layer,... Agent: Kenyon & Kenyon LLP

20090101998 - Electro-acoustic sensing device: An electro-acoustic sensing device including a sensing chip, a carrier chip and a sealing element is provided. The sensing chip is for electro-acoustic transducing and thereby outputting an electrical signal. The carrier chip disposed below the sensing chip has at least one second connecting point, at least one electrical channel... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090101999 - Electronic device on substrate with cavity and mitigated parasitic leakage path: An electronic device. The electronic device includes a first electrode and a coating layer. The electronic device is fabricated on a substrate; the substrate has a cavity created in a top surface of the substrate; and the first electrode is electrically coupled to the substrate. The coating layer coats at... Agent: Kathy Manke Avago Technologies Limited

20090102000 - Cmos image sensor device and its formation method: A method for forming a CMOS image sensor (CIS) in accordance with embodiments includes sequentially forming a first photoresist and a blocking layer over a semiconductor substrate where a logic section including a photodiode may be formed. A micro lens array pattern may be formed by coating a second photoresist... Agent: Sherr & Vaughn, PLLC

20090102001 - Image sensor and a method for manufacturing thereof: An image sensor according to an embodiment includes a semiconductor substrate including a photodiode; a protective layer pattern having a lower trench that is disposed on the semiconductor substrate to expose the photodiode; an insulating layer pattern having the upper trench that is disposed on the lower trench of the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090102003 - Package comprising an electrical circuit: A package including an electrical circuit may be produced in a more efficient manner when on a substrate including a plurality of electrical circuits the circuits are tested for their functionality and when the functional circuits are connected, by means of a frame enclosing the circuit on the surface of... Agent: Schoppe, Zimmermann , Stockeler & Zinkler C/o Keating & Bennett, LLP

20090102002 - Packaged semiconductor assemblies and associated systems and methods: Semiconductor packages, packaged semiconductor devices, methods of manufacturing semiconductor packages, methods of packaging semiconductor devices, and associated systems are disclosed. A semiconductor package in accordance with a particular embodiment includes a die having a first side carrying a first bond site electrically connected to a sensor and/or a transmitter configured... Agent: Perkins Coie LLP Patent-sea

20090102004 - Sensor package: A sensor package includes an image sensing chip having a front surface, a plurality of bumps, a glass cover plate, and a connector. The plurality of bumps are formed on the front surface, and are electrically connected to the image sensing chip. The glass cover plate has a bottom surface... Agent: PCe Industry, Inc. Att. Steven Reiss

20090102005 - Wafer level package and mask for fabricating the same: An exemplary wafer level package comprises a semiconductor wafer with a plurality of semiconductor chips of perfect polygonal shapes thereon. A circuit-free area is defined over the semiconductor wafer to electrically isolate the semiconductor chips. A dam structure is substantially formed over the circuit-free area, wherein a portion of the... Agent: Joe Mckinney Muncy

20090102006 - Electrostatic micro actuator, electrostatic microactuator apparatus and driving method of electrostatic micro actuator: A semiconductor substrate; a cantilever which is formed on the semiconductor substrate so as to face the semiconductor substrate with an air layer therebetween, the cantilever being made from an electrically conductive material or a semiconductor material, and the cantilever being mechanically movable; a photodiode which is formed so as... Agent: Ostrolenk Faber Gerb & Soffen

20090102007 - Lateral power diode with self-biasing electrode: A semiconductor diode includes a drift region of a first conductivity type and an anode region of a second conductivity type in the drift region such that the anode region and the drift region form a pn junction therebetween. A first highly doped silicon region of the first conductivity type... Agent: Townsend And Townsend And Crew, LLP

20090102009 - Semiconductor device and method of forming the same: Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor device includes an active region of which an edge is curved. The semiconductor device includes a gate insulating layer, a floating gate, a gate interlayer dielectric layer and a control gate line on the active... Agent: Mills & Onello LLP

20090102010 - Semiconductor device with sti and method for manufacturing the semiconductor device: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090102008 - Semiconductor substrate and semiconductor device and manufacturing method of the same: A semiconductor substrate having an SOI layer is provided. Between an SOI layer and a glass substrate, a bonding layer is provided which is formed of one layer or a plurality of layers of phosphosilicate glass, borosilicate glass, and/or borophosphosilicate glass, using organosilane as one material by a thermal CVD... Agent: Fish & Richardson P.C.

20090102011 - Semiconductor device with a noise prevention structure: A semiconductor device including a substrate of a first semiconductor type with a pad region and a noise prevention structure in the substrate, on least one side of the pad region. The device further includes the substrate structure, a pad, and a dielectric layer therebetween.... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090102012 - Semiconductor devices having active elements with raised semiconductor patterns and related methods of fabricating the same: A semiconductor device may include a semiconductor region of a semiconductor substrate wherein a P-N junction is defined between the semiconductor region and a bulk of the semiconductor substrate. An insulating isolation structure in the semiconductor substrate may surround sidewalls of the semiconductor region. An interlayer insulating layer may be... Agent: Myers Bigel Sibley & Sajovec

20090102013 - Fuse box and method of forming the same: A fuse box includes a fuse pattern having a rugged profile and an interlayer insulating film including a fuse blowing window to fill the fuse pattern.... Agent: Townsend And Townsend And Crew, LLP

20090102014 - Anti-fuse cell and its manufacturing process: An anti-fuse cell includes a standard MOS transistor of an integrated circuit, with source and drain regions covered with a metal silicide layer and at least one track of a resistive layer at least partially surrounding the MOS transistor, and adapted to pass a heating current such that the metal... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20090102016 - Design structure incorporating vertical parallel plate capacitor structures: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a vertical parallel plate capacitor structure with a first plurality of conductive plates and a second plurality of conductive plates having an overlying relationship with the first plurality of conductive plates.... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090102015 - Integrated circuit, memory cell array, memory cell, memory module, method of operating an integrated circuit, and method of manufacturing an integrated circuit: According to one embodiment of the present invention, an integrated circuit includes a plurality of resistivity changing memory cells, each memory cell including a top electrode, a bottom electrode and resistivity changing material being disposed between the top electrode and the bottom electrode. The top electrodes together form a continuous... Agent: Slater & Matsil, L.L.P.

20090102018 - Localized masking for semiconductor structure development: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface... Agent: Schwegman, Lundberg & Woessner/micron

20090102017 - Semiconductor device and method of fabricating the semiconductor device: A semiconductor device and a method of fabricating a semiconductor device provide high quality cylindrical capacitors. The semiconductor device includes a substrate defining a cell region and a peripheral circuit region, a plurality of capacitors in the cell region, and supports for supporting lower electrodes of the capacitors. The lower... Agent: Volentine & Whitt PLLC

20090102019 - Controlled doping of semiconductor nanowires: A catalyst particle on a substrate is exposed to reactants containing a semiconductor material in a reactor. An intrinsic semiconductor nanowire having constant lateral dimensions is grown at a low enough temperature so that pyrolysis of the reactant is suppressed on the sidewalls of the intrinsic semiconductor nanowire. Once the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090102020 - Wafer and method for manufacturing same: A wafer with an orientation notch being cut in a portion of its circumference, the wafer includes: a reinforcing flange formed upright at periphery; and a thin section surrounded by the reinforcing flange and having a smaller thickness than the reinforcing flange. The reinforcing flange includes a circumferential portion formed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090102022 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device which minimizes the line width of a pattern and allows a low temperature oxide film and a thinly formed photoresist film to serve as ion blockers when performing an ion implantation process on the semiconductor substrate.... Agent: Sherr & Vaughn, PLLC

20090102021 - Through-silicon vias and methods for forming the same: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a substrate; a through-silicon via (TSV) extending into the substrate; a TSV pad spaced apart from the TSV; and a metal line over, and electrically connecting, the TSV and the TSV pad.... Agent: Slater & Matsil, L.L.P.

20090102023 - Method for manufacturing a structure, semiconductor device and structure on a substrate: One possible embodiment is a method for manufacturing a structure on a substrate which can be used in the manufacturing of a semiconductor device, including the steps of: forming a first structure on the substrate having at least one sidewall, forming at least one layer as a second structure selectively... Agent: Slater & Matsil, L.L.P.

20090102024 - Semiconductor device and method for fabricating same: A semiconductor device has an IC chip with a thickness of equal to or less than 100 μm and includes a semiconductor substrate. A device forming region is within the depth of approximately equal to or less than 5 μm from a surface of the semiconductor substrate, and a total... Agent: Nixon & Vanderhye, PC

20090102025 - Semiconductor device and method for manufacturing the same, dry-etching process, method for making electrical connections, and etching apparatus: A method for manufacturing a semiconductor device comprises dry-etching a thin film using a resist mask carrying patterns in which at least one of the width of each pattern and the space between neighboring two patterns ranges from 32 to 130 nm using a halogenated carbon-containing compound gas with the... Agent: Arent Fox LLP

20090102026 - Semiconductor-on-insulator substrate with a diffusion barrier: A diffusion barrier layer is incorporated between a top semiconductor layer and buried oxide layer. The diffusion barrier layer blocks diffusion of dopants into or out of buried oxide layer. The diffusion barrier layer may comprise a dielectric material such as silicon oxynitride or a high-k gate dielectric material. Alternately,... Agent: Scully, Scott, Murphy & Presser, P.C.

20090102027 - Method for manufacturing semiconductor device, semiconductor device, and electronic appliance: An object of the present invention is to provide a semiconductor device including an insulating layer with a high dielectric strength voltage, a low dielectric constant, and low hygroscopicity. Another object of the present invention is to provide an electronic appliance with high performance and high reliability, which uses the... Agent: Nixon Peabody, LLP

20090102028 - Method for manufacturing a semiconductor component and structure therefor: A method for manufacturing a semiconductor component that includes a leadframe having a non-metallic base structure and an intermediate leadframe structure. The non-metallic base structure may be, among other things, paper, cellulose, or plastic. A layer of electrically conductive material is formed over the non-metallic base structure. A circuit element... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20090102029 - Semiconductor device: A semiconductor device that can cope with larger numbers of pins and finer pitches while suppressing lowering of the manufacturing yield and reliability includes: a semiconductor chip having a plurality of electrodes provided on an upper surface thereof; a plurality of lead terminals including inner lead portions disposed toward the... Agent: Fish & Richardson P.C. Citigroup Center

20090102030 - Integrated circuit package with etched leadframe for package-on-package interconnects: Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery... Agent: Fiala & Weaver, P.l.l.c. C/o Cpa Global

20090102032 - Electronic device: An electronic device is disclosed. In one embodiment, the electronic device includes a substrate, a plurality of conducting lines formed on a first conducting material that is disposed on the substrate, and a layer of a second conducting material disposed on the plurality of conducting lines. The conducting lines include... Agent: Dicke, Billig & Czaja

20090102033 - Integrated circuit package: Package for an integrated circuit (IC), includes a housing (3) of a first material having two major surfaces (4, 5). The major surfaces are substantially parallel to each other. Furthermore, a lead frame (6) is present for carrying the IC (2), the lead frame (6) including contact terminals (7) for... Agent: Young & Thompson

20090102031 - Method for connecting a die attach pad to a lead frame and product thereof: Disclosed in this specification is a semiconductor package with a die attach pad and a lead frame which are electrically and mechanically connected to one another through a conductive wire ribbon. Such a configuration reduces the package footprint and also permits different styles of die attach pads and lead frames... Agent: Hiscock & Barclay, LLP

20090102034 - Packaged microchip with spacer for mitigating electrical leakage between components: A packaged microchip has a base, at least one spacer coupled to the base, and first and second microchips mounted to the at least one spacer. The at least one spacer is configured to substantially prevent leakage current between the first and second microchips.... Agent: Bromberg & Sunstein LLP

20090102038 - Chip scale stacked die package: A die prepared for stacking in a chip scale stacked die assembly, having interconnect sites in an area inward from a die edge and interconnect pads near at least one die edge. Second-level interconnection of the stacked die assembly can be made by way of connections between a first die... Agent: Haynes Beffel & Wolfeld LLP

20090102039 - Package on package structure: The present invention relates to a package on package (PoP) structure, which comprises: a first packaging substrate having a plurality of conductive elements on its surface; a second packaging substrate having a plurality of conductive elements on its surface; and a surface-ceramic aluminum plate sandwiched between the first packaging substrate... Agent: Bacon & Thomas, PLLC

20090102037 - Semiconductor package, module, system having solder ball coupled to chip pad and manufacturing method thereof: A semiconductor package structure having a solder ball coupled to a chip pad and a manufacturing method thereof, a semiconductor package module, and a system. A circuit board includes a through hole therein, and a conductor is formed on a sidewall of the through hole. A first semiconductor chip including... Agent: Stanzione & Kim, LLP

20090102035 - Semiconductor packaging device: Embodiments of the invention relate to a semiconductor module and to a method for manufacturing a semiconductor module. In an embodiment of the invention, a semiconductor module for mounting to a board may include at least an integrated circuit having connections on at least one side of the integrated circuit,... Agent: Slater & Matsil, L.L.P.

20090102036 - Stacked semiconductor package having interposing print circuit board: A stacked semiconductor package including a number of solder ball pads formed on a lower surface of an interposing print circuit board, which is smaller than that of solder ball pads formed on an upper surface thereof, a pitch of the solder ball pads formed on the lower surface of... Agent: Harness, Dickey & Pierce, P.L.C

20090102041 - Electrical connection device and assembly method thereof: An electrical connection device and assembly method thereof includes a substrate with a plurality of contacting portions arranged on a surface thereof; a chip module having a plurality of terminals inclining in one direction and compressed and contacted with the contacting portions correspondingly; at least one restricting structure which restricts... Agent: Rosenberg, Klein & Lee

20090102040 - Power semiconductor module: An apparatus includes a housing with a plurality of restraining elements and at least one supporting element. A cover is elastically deformed by the plurality of restraining elements and the at least one supporting means. At least one substrate carrying at least one semiconductor chip is provided within the housing.... Agent: Dicke, Billig & Czaja

20090102042 - Semiconductor device and method of fabricating semiconductor device: A semiconductor device including a semiconductor chip having external connecting terminals formed on one side is restrained to cause chipping in ridge line portion of semiconductor chip. A cover layer 103 is formed on the other side of the semiconductor chip 102. At least a part of an end portion... Agent: Mcginn Intellectual Property Law Group, PLLC

20090102043 - Semiconductor package and manufacturing method thereof: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the... Agent: Rabin & Berdo, PC

20090102044 - Device including a housing for a semiconductor chip: A device including a housing for a semiconductor chip is disclosed. One embodiment provides a plurality of leads. A first lead forms an external contact element at a first housing side and extends at the first housing side into the housing in the direction of an opposite second housing side.... Agent: Dicke, Billig & Czaja

20090102045 - Packaging substrate having capacitor embedded therein: A packaging substrate having capacitors embedded therein, comprising: two capacitor disposition layers, each respectively consisting of a high dielectric layer and two first circuit layers disposed on two opposite surfaces of the high dielectric layer, wherein each of the first circuit layers has a plurality of electrode plates and a... Agent: Bacon & Thomas, PLLC

20090102046 - On-chip temperature gradient minimization using carbon nanotube cooling structures with variable cooling capacity: An electronic device comprises a die with at least one defined hot-spot area; and at least one defined intermediate temperature area at a temperature lower than the temperature of the hot-spot area. The device also comprises a cooling structure comprising at least one bundle of first nanotubes for cooling the... Agent: The Law Offices Of Robert J. Eichelburg

20090102048 - Electronic device and manufacturing method thereof: Electronic device has substrate having at least one pad, electronic component having bump connected with pad of substrate electrically and mounting on substrate by flip chip bonding, conductive resin electrically connecting pad with bump, and insulation sheet disposed between substrate and electronic component. Substrate has recess on surface opposite to... Agent: Nec Corporation Of America

20090102047 - Flip chip package structure and carrier thereof: A flip chip package structure including a chip, a carrier, and a plurality of bumps is provided. The chip has a bonding surface and a plurality of bump pads thereon. The carrier is disposed corresponding to the chip and includes a substrate and a plurality of pre-solders. The substrate has... Agent: J C Patents, Inc.

20090102049 - Semiconductor device, layered type semiconductor device using the same, base substrate and semiconductor device manufacturing method: A semiconductor device has a plurality of external connection lands arranged on a base substrate for an external connection terminal used for electrical connection with an external member. The external connection lands at different arrangement positions have different heights in accordance with a warp of the base substrate which warp... Agent: Nixon & Vanderhye, PC

20090102050 - Solder ball disposing surface structure of package substrate: A solder ball disposing surface structure of a package substrate is disclosed, wherein a package substrate has a chip disposing surface with a first circuit layer, an opposed solder ball disposing surface with a second circuit layer, and a first insulative protection layer formed on the chip disposing surface and... Agent: Fulbright And Jaworski LLP

20090102053 - Metal line stacking structure in semiconductor device and formation method thereof: The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on a lower dielectric layer that is disposed over a semiconductor substrate, and performing a plasma treatment; forming a second... Agent: Fulbright And Jaworski LLP

20090102051 - Method to create super secondary grain growth in narrow trenches: The present invention relates to a method for obtaining enlarged Cu grains in small trenches. More specifically it related to a method for creating enlarged copper grains or inducing super secondary grain growth in electrochemically deposited copper in narrow trenches and/or vias to be used in semiconductor devices.... Agent: Knobbe Martens Olson & Bear LLP

20090102052 - Semiconductor device and fabricating method thereof: A semiconductor device and fabricating method thereof are disclosed. The method includes forming a first metal line over a substrate, forming a barrier layer over the substrate and the first metal line, forming an insulating layer on the barrier layer, forming a capping layer on the insulating layer, forming a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090102056 - Patterned leads for wlcsp and method for fabricating the same: The present invention provides patterned leads for a wafer level chip size package and methods for fabricating the same. The patterned leads include connection leads and solder pads. In designing, a compensation pattern is disposed on the connection lead or on the solder pad, so as to increase the distance... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20090102055 - Semiconductor device: It is an object of the invention to provide semiconductor devices which can protect privacy of consumers or holders of commercial products and control the communication range according to use, even when the semiconductor device which can exchange data without contact is mounted on the commercial products. A semiconductor device... Agent: Eric Robinson

20090102057 - Semiconductor device: The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 μm, and a broad portion integrally formed on... Agent: Rabin & Berdo, PC

20090102054 - Semiconductor package: A semiconductor package is disclosed. One embodiment provides a semiconductor package singulated from a wafer includes a chip defining an active surface, a back side opposite the active surface, and peripheral sides extending between the active surface and the back side; a contact pad disposed on the active surface; and... Agent: Dicke, Billig & Czaja

20090102058 - Method for forming a plug structure and related plug structure thereof: A method for forming a plug structure by utilizing a punching through process and the related plug structure are provided. An opening is defined in a substrate, and an unwanted oxide residue is disposed on a bottom of the opening. A glue layer is subsequently formed over the substrate. Portions... Agent: North America Intellectual Property Corporation

20090102059 - Semiconductor device: Increase in the chip size of a semiconductor device is suppressed. The semiconductor device includes: circuit vias provided in an interlayer insulating film between upper and lower wiring layers and coupling these wiring layers together; a planar ring-shaped protecting via that is provided in the interlayer insulating film under an... Agent: Miles & Stockbridge PC

20090102061 - Self-aligned wafer level integration system: c

20090102060 - Wafer level stacked die packaging: A method of manufacturing semiconductor devices by applying a pattern of adhesive pads on an active surface of a semiconductor wafer, the semiconductor wafer product so made and a stacked die package in which an adhesive wall leaves an air gap atop a bottom die. The wall may be in... Agent: Bromberg & Sunstein LLP

20090102064 - Connection structure and method of producing the same: A connection structure (package 10) has a first plate body 101 and a second plate body; in the first plate body 101, a wiring pattern having a plurality of connection terminals 102 is formed, and the second plate body has at least two connection terminals (electrode terminals 104) arranged facing... Agent: Hamre, Schumann, Mueller & Larson P.C.

20090102063 - Semiconductor package and method for fabricating the same: This invention provides a semiconductor package and a method for fabricating the same. The method includes: forming a first resist layer on a metal carrier; forming a plurality of openings penetrating the first resist layer; forming a conductive metal layer in the openings; removing the first resist layer; covering the... Agent: Edwards Angell Palmer & Dodge LLP

20090102062 - Wiring substrate and method of manufacturing the same, and semiconductor device: A wiring substrate of the present invention includes such a structure that a plurality of connection pads and leading wiring portions connected to the plurality of connection pads respectively are arranged to an insulating layer of a surface layer side, and the leading wiring portions are arranged to be bended... Agent: Kratz, Quintos & Hanson, LLP

20090102065 - Bonding pad for anti-peeling property and method for fabricating the same: A bonding pad includes an insulation layer with a trench, and a conductive pattern one portion of which is buried into the trench and the other portion of which is formed in a plate shape over the insulation layer.... Agent: Townsend And Townsend And Crew, LLP

20090102066 - Chip package structure and method of manufacturing the same: A chip package structure and a method of manufacturing the same are provided. The chip package structure includes a package portion and a plurality of external conductors. The package portion includes a distribution layer, a chip, a plurality internal conductors and a sealant. The distribution layer has a first surface... Agent: Bacon & Thomas, PLLC

20090102067 - Electrically enhanced wirebond package: Consistent with an example embodiment, there is an integrated circuit (IC) device in a packaging having electrically insulated connections. The IC device comprises a semiconductor device (100) mounted onto a die attachment area (10); the semiconductor device has a plurality of bonding pads (20a, 25a, 30a, 35a). A lead frame... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090102068 - System and method to manufacture an implantable electrode: The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center... Agent: Schox PLC

20090102070 - Alignment marks on the edge of wafers and methods for same: A semiconductor wafer having alignment marks a sufficient distance from the outer wafer edge that reference dicing channels and a method for same. A process for dicing WLUF coated wafers into singulated chips using said alignment marks on the outer edge of the wafer.... Agent: Nugent & Smith, LLP

20090102069 - Integrated circuit system with assist feature: An integrated circuit system comprising: providing a substrate; forming a main feature using a first non-cross-junction assist feature over the substrate; forming the main feature using a second non-cross-junction assist feature, adjacent a location of the first non-cross-junction feature, over the substrate; and forming an integrated circuit having the substrate... Agent: Law Offices Of Mikio Ishimaru

20090102071 - Semiconductor substrate and method for manufacturing semiconductor device: The present invention includes a first recognition mark which is arranged in a frame part of a perimeter of an implementation region having a plurality of semiconductor chips implemented therein so that the position of the semiconductor substrate can be macroscopically detected by using a recognition camera, and a second... Agent: Mcginn Intellectual Property Law Group, PLLC

20090095948 - Programmable resistive memory with diode structure: Programmable resistive memory cells are accessed by semiconductor diode structures. Manufacturing methods and integrated circuits for programmable resistive elements with such diode structures are also disclosed.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090095949 - Low area contact phase-change memory: A memory device includes a first electrode and a second electrode. A phase-change material is disposed between the first and second electrodes. The phase-change material is in electrical communication with the first and second electrodes at a first contact region and a second contact region respectively. The first and second... Agent: Honigman Miller Schwartz & Cohn LLP

20090095951 - Memory device with low reset current: An electronic device includes a first electrode and a second electrode. The device also includes a resistive material between the first and second electrodes. An active material is between the first electrode and the resistive material. The active material is in electrical communication with the first electrode and the active... Agent: Honigman Miller Schwartz & Cohn LLP

20090095950 - Nanoscale wire-based data storage: The present invention generally relates to nanotechnology and submicroelectronic devices that can be used in circuitry and, in some cases, to nanoscale wires and other nanostructures able to encode data. One aspect of the invention provides a nanoscale wire or other nanostructure having a region that is electrically-polarizable, for example,... Agent: Wolf Greenfield & Sacks, P.C.

20090095953 - Phase change materials and associated memory devices: A memory device utilizes a phase change material as the storage medium. The phase change material includes at least one of Ge, Sb, Te, Se, As, and S, as well as a nitride compound as a dopant. The memory device can be a solid-state memory cell with electrodes in electrical... Agent: Daniel E. Johnson IBM Corporation, Almaden Research Center

20090095952 - Storage node, phase change memory device and methods of operating and fabricating the same: A storage node, a phase change memory device, and methods of operating and fabricating the same are provided. The storage node may include a lower electrode, a phase change layer on the lower electrode and an upper electrode on the phase change layer, and the lower electrode and the upper... Agent: Harness, Dickey & Pierce, P.L.C

20090095954 - Field-effect transistor: A field-effect transistor is provided, which includes an organic thin film and which can realize a low threshold voltage while a stable, high field-effect mobility is ensured at the same time. In a field-effect transistor provided with a gate electrode, a source electrode, a drain electrode, a semiconductor film, a... Agent: Ostrolenk Faber Gerb & Soffen

20090095955 - Semiconductor integrated circuit and testing method thereof: A semiconductor integrated circuit including a detector and a secure checker. The detector generates a detection signal upon sensing an abnormal state in an operating environment of the semiconductor integrated circuit. The secure checker generates a check signal to find an operating condition of the detector and receives the detection... Agent: F. Chau & Associates, LLC

20090095956 - Single-crystal silicon substrate, soi substrate, semiconductor device, display device, and manufacturing method of semiconductor device: A semiconductor device of the present invention is arranged in such a manner that a MOS non-single-crystal silicon thin-film transistor including a non-single-crystal silicon thin film made of polycrystalline silicon, a MOS single-crystal silicon thin-film transistor including a single-crystal silicon thin film, and a metal wiring are provided on an... Agent: Birch Stewart Kolasch & Birch

20090095957 - Display device and method of manufacturing display device: To provide a display device, including a polysilicon thin film transistor, which achieves a reduction of an off current with a simple configuration and with only a slight increase in a number of processes. A display device includes: an insulating substrate, and a thin film transistor formed on the insulating... Agent: Stanley P. Fisher Reed Smith LLP

20090095958 - Thin film transistor array and displaying apparatus: A thin film transistor array is disclosed. The thin film transistor array includes plural gate electrodes formed on an insulation substrate, plural source electrodes formed above or under the gate electrodes via a gate insulation film so that the source electrodes cross the gate electrodes in a planar view, plural... Agent: Cooper & Dunham, LLP

20090095959 - Heat dissipation device for led chips: A heat dissipation device for removing heat from LED chips includes a heat sink and a plurality of substrates. The heat sink comprises a base plate. A plurality of fins extends upwardly from the base plate. The substrates each have a unidirectional heat transfer and are attached to a bottom... Agent: PCe Industry, Inc. Att. Steven Reiss

20090095960 - Heat dissipation member, semiconductor apparatus and semiconductor light emitting apparatus: A heat dissipation member includes a first plate-shaped member and a second plate-shaped member. The first plate-shaped member has a first surface thermally connectable with a heat generating element and a second surface. The second plate-shaped member is thermally connected with the second surface of the first plate-shaped member. The... Agent: Ditthavong Mori & Steiner, P.C.

20090095963 - Bare die semiconductor device configured for lamination: A bare die semiconductor device, e.g., a bare die LED, includes a substrate having a bottom face and a bottom die electrode. There is also a top face having a top face edge, a top face area, a top face periphery and a top die electrode. A semiconductor material provides... Agent: Michaud-duffy Group LLP

20090095961 - Combination of led and heat dissipation device: A combination of LED and heat dissipating device includes a heat dissipating device, an electrically insulative thermal conductivity layer covered on a part of the surface of the heat dissipating device, thermal and electric conducting layers disposed at the electrically insulative thermal conductivity layer and electrically isolated from one another,... Agent: Bacon & Thomas, PLLC

20090095962 - Method of manufacturing semiconductor device, method of manufacturing display apparatus, apparatus of manufacturing semiconductor device, and display apparatus: A method of manufacturing a semiconductor device includes the steps of: modifying a semiconductor film by applying a laser beam; and forming a semiconductor device on the modified semiconductor film. In the step of modifying the semiconductor film, the laser beam and the substrate are moved relative to each other... Agent: Sonnenschein Nath & Rosenthal LLP

20090095964 - Nitride semiconductor laser device and nitride semiconductor laser apparatus: In one embodiment of the present invention, a long-life nitride semiconductor laser element is disclosed wherein voltage characteristics do not deteriorate even when the element is driven at high current density. Specifically disclosed is a nitride semiconductor laser element which includes a p-type nitride semiconductor and a p-side electrode formed... Agent: Harness, Dickey & Pierce, P.L.C

20090095965 - Nitride semiconductor light emitting diode: A nitride semiconductor light emitting diode (LED) comprises an n-type nitride semiconductor layer; an electron emitting layer formed on the n-type nitride semiconductor layer, the electron emitting layer being composed of a nitride semiconductor layer including a transition element of group III; an active layer formed on the electron emitting... Agent: Lowe Hauptman Ham & Berner, LLP

20090095968 - Image sensor and method for manufacturing the same: Provided are an image sensor and a method for manufacturing the same. A trench can be formed through metal interconnection layers of the image sensor in a region corresponding to a light receiving device for each unit pixel. A passivation layer pattern can be provided at sidewalls of the trench... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090095967 - Light emitting device: The lighting device (1) includes an LED chip (10), a mounting substrate (20) mounting thereto the LED chip, an encapsulation member (50) made of an encapsulating resin material for encapsulation of the LED chip, and a lens (60) made of a transparent resin material. The lens (60) is provided in... Agent: Cheng Law Group, PLLC

20090095966 - Multiple conversion material light emitting diode package and method of fabricating same: An emitter package comprising a light emitting diode (LED) emitting light at a wavelength within a wavelength range and a plurality of phosphors. Each of the phosphors absorbs at least some light from the LED and re-emits a different wavelength of light. The package emits a combination of light from... Agent: Koppel, Patrick & Heybl

20090095969 - Substrate for mounting an optical semiconductor element, manufacturing method thereof, an optical semiconductor device, and manufacturing method thereof: A substrate for mounting optical semiconductor elements is provided, including a base substrate having an insulating layer and a plurality of wiring circuits formed on the upper face of the insulating layer, and having at least one external connection terminal formation opening portion which penetrates the insulating layer and reaches... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090095970 - White phosphors, methods of making white phosphors, white light emitting leds, methods of making white light emitting leds, and light bulb structures: Phosphor compositions, white phosphor compositions, methods of making white phosphor compositions, tinted white phosphor compositions, methods of making tinted white phosphor compositions, LEDs, methods of making LEDs, light bulb structures, paints including phosphor compositions, polymer compositions including phosphor compositions, ceramics including phosphor compositions, and the like are provided.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090095975 - Light emitting diode package: A light emitting diode package for preventing an electric short circuit among semiconductor layers and with excellent bonding strength. The light emitting diode package includes a package substrate, a light emitting diode chip bonded to an upper surface of the package substrate, and a bonding material for bonding the light... Agent: Mcdermott Will & Emery LLP

20090095972 - Light-emitting device: A light-emitting device is provided in a light-emitting element with a bonding wire that is a fine metallic wire formed mainly of gold or copper and coated at least partly with a substance capable of heightening a reflection coefficient of a wavelength of light emitted from the light-emitting element.... Agent: Sughrue Mion, PLLC

20090095973 - Semiconductor light emitting device: A semiconductor light emitting device has a device body made of a group III nitride semiconductor having a major surface defined by a nonpolar plane. In the device body, a contact portion with an n-type electrode includes a crystal plane different from the major surface. For example, the contact portion... Agent: Rabin & Berdo, PC

20090095974 - Semiconductor package and manufacturing method thereof: A semiconductor package including a base body having a recessed portion for installing an electronic component on one surface, the recessed portion including an inner bottom surface, inclined surface and a shoulder part and a wiring pattern having one end positioned in the inner bottom surface of the recessed portion... Agent: Rankin, Hill & Clark LLP

20090095971 - Wire bond led lighting unit: A wire bond LED lighting unit and method for maximizing heat transfer in an LED lighting unit are disclosed, wherein the LED lighting unit includes an LED package disposed on a first carrier plate and is in thermal communication therewith. A PWB is disposed on the first carrier plate spaced... Agent: Fraser Clemens Martin & Miller LLC

20090095976 - Nitride-based light-emitting device and method of manufacturing the same: Provided are a nitride-based light-emitting device including a transparent electrode made of a transparent conductive oxide having a higher work function than indium tin oxide and a method of manufacturing the same. The nitride-based light-emitting device has a sequentially stacked structure of a substrate, an n-type clad layer, an active... Agent: Buchanan, Ingersoll & Rooney PC

20090095977 - Vertical semiconductor device: In a vertical semiconductor device including a first base layer of a first conductivity type, second base layers of a second conductivity type, emitter layer of the first conductive type and gate electrodes which are formed at one main surface of the first base layer and including a buffer layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090095978 - Low capacitance over-voltage tage protection thyristor device: An over-voltage protection thyristor has reduced junction capacitance making it suitable for use in high bandwidth applications. The reduced capacitance is achieved through the introduction of a deep base region. The deep base region has a graded doping ,concentration which reduces with depth into the substrate. The thyristor is useful... Agent: Ralph A. Dowell Of Dowell & Dowell P.C.

20090095979 - Power module: A power module includes a substrate having first and second main substrate surfaces; a semiconductor device disposed on the first main substrate surface, and having a first main surface on which a first main electrode is formed, and a second main surface on which a second main electrode in contact... Agent: Fish & Richardson P.C.

20090095981 - Complementary metal oxide semiconductor device and method of manufacturing the same: Provided are a complementary metal oxide semiconductor (CMOS) device and a method of manufacturing the same. The CMOS device comprises an epi-layer that may be formed on a substrate; a first semiconductor layer and a second semiconductor layer that may be formed on different regions of the epi-layer, respectively; and... Agent: Harness, Dickey & Pierce, P.L.C

20090095980 - Reducing resistance in source and drain regions of finfets: A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections... Agent: Slater & Matsil, L.L.P.

20090095982 - Semiconductor device and method of manufacturing the same: A semiconductor device to which a stress technique is applied and in which a leakage current caused by silicidation can be suppressed. A gate electrode is formed over an element region defined by an isolation region formed in a semiconductor substrate with a gate insulating film between. Extension regions and... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090095984 - Dielectric interface for group iii-v semiconductor device: A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090095983 - Semiconductor device and method of making same: In one example embodiment, an integrated semiconductor circuit (400) is provided. The integrated circuit (400) comprises a substrate (430) comprising a first material and a first electronic device (455) comprising a first depressed region (415) within the substrate (430) and a set of first device contact locations (475) in a... Agent: Dillon & Yudell LLP

20090095985 - Multi-layer electrode, cross point memory array and method of manufacturing the same: Provided may be a multi-layer electrode, a cross point resistive memory array and method of manufacturing the same. The array may include a plurality of first electrode lines arranged parallel to each other; a plurality of second electrode lines crossing the first electrode lines and arranged parallel to each other;... Agent: Harness, Dickey & Pierce, P.L.C

20090095986 - Photo sensor with a low-noise photo element, sub-linear response and global shutter: A photo sensor exhibiting low noise, low smear, low dark current, high dynamic range and global shutter functionality consists either of a pinned (or buried) photodiode or a photo-sensitive charge-coupled device, each with associated transfer gate, a sub-linear element, a shutter transistor, a reset circuit and a read-out circuit. Using... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP

20090095987 - Transistor design and layout for performance improvement with strain: The present invention facilitates semiconductor device fabrication and performance by providing a semiconductor device that can improve channel mobility for both N type and P type transistor devices. The semiconductor device of the present invention is fabricated on a semiconductor substrate 802 that has a first and second crystallographic orientation... Agent: Texas Instruments Incorporated

20090095988 - Transistor design and layout for performance improvement with strain: The present invention facilitates semiconductor device fabrication and performance by providing a semiconductor device that can improve channel mobility for both N type and P type transistor devices. The semiconductor device of the present invention is fabricated on a semiconductor substrate 802 that has a first and second crystallographic orientation... Agent: Texas Instruments Incorporated

20090095989 - Multi-finger transistors including partially enclosing conductive lines: A multi-finger transistor includes gate fingers disposed on a substrate, at least one gate wiring connected to end portions of the gate fingers, source regions and drain regions disposed between the gate fingers, a conductive line partially enclosing the gate fingers and the gate wiring, and substrate plugs electrically connecting... Agent: Myers Bigel Sibley & Sajovec

20090095990 - Metal-oxide-semiconductor transistor and method of forming the same: A method of forming a metal-oxide-semiconductor (MOS) transistor device is provided. First, a semiconductor substrate is prepared. Subsequently, a gate structure is formed on the semiconductor substrate. The gate structure includes a first strip portion and a second strip portion that is not parallel to the first strip portion. The... Agent: North America Intellectual Property Corporation

20090095991 - Method of forming strained mosfet devices using phase transformable materials: A method of forming a strained metal oxide semiconductor field effect transistor (MOSFET) device includes forming a gate conductor and gate insulator layer over a semiconductor substrate; forming source and drain regions in the semiconductor substrate, thereby defining the MOSFET device; forming a phase transformable material layer over the MOSFET... Agent: Cantor Colburn LLP - IBM Fishkill

20090095992 - Semiconductor device including mos field effect transistor and method for manufacturing the semiconductor device: Element isolation regions are formed in a semiconductor substrate of a first conductivity type. A gate insulator is formed on the semiconductor substrate between the element isolation regions. A gate electrode is formed on the gate insulator. Sidewall insulating films are formed on side surfaces of the gate electrode. Trenches... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090095994 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises a substrate; an insulating layer formed over the substrate; a contact hole formed through the insulating layer; a plurality of first plug electrodes each formed inside the contact hole to the surface of the insulating layer; a capacitor layer formed on the first plug electrode in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090095993 - Semiconductor memory device and fabricating method for semiconductor memory device: According to an aspect of the present invention, there is provided a semiconductor memory device including a ferroelectric capacitor, including a semiconductor substrate, a transistor having diffusion layers being a source and a drain, the transistor being formed on a surface of the semiconductor substrate, a ferroelectric capacitor being formed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090095997 - Epitaxial silicon growth: Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric... Agent: Brooks, Cameron & Huebsch , PLLC

20090095996 - Semiconductor device: A semiconductor device includes a substrate including an active region, a first impurity region, second impurity regions, a word line and a bit line. The active region has end portions extending in a first direction and a central portion extending in a second direction inclined relative to the first direction.... Agent: Harness, Dickey & Pierce, P.L.C

20090095995 - Semiconductor device and a method of manufacturing the same: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode... Agent: Miles & Stockbridge PC

20090095998 - Deep trench capacitor and method: Disclosed herein are embodiments of a deep trench capacitor structure and a method of forming the structure that incorporates a buried capacitor plate contact that is simultaneously formed using an adjacent deep trench. This configuration eliminates the need for additional photolithographic processing, thereby, optimizing process windows. This configuration further eliminates... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090095999 - Semiconductor device and method of fabricating the same: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device includes a first conductive well region in a semiconductor substrate and a second conductive well region on or in the first conductive well region. A gate electrode is in a trench on a gate... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090096000 - Dram cells with vertical transistors: The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the... Agent: Knobbe Martens Olson & Bear LLP

20090096001 - Integrated circuit and method of manufacturing the same: A method of manufacturing an integrated circuit includes: forming a trench in a substrate, forming a high-k dielectric layer lining the trench, and removing a section of the high-k dielectric layer from the trench via an isotropic dry etch process.... Agent: Edell, Shapiro & Finnan, LLC

20090096002 - System and method for source/drain contact processing: System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric.... Agent: Slater & Matsil, L.L.P.

20090096003 - Semiconductor cell structure including buried capacitor and method for fabrication thereof: A semiconductor structure and a method for fabricating the semiconductor structure include at least one field effect transistor, and also a capacitor, located over a substrate. In particular, the capacitor is located interposed between the field effect transistor and the substrate. The field effect transistor may include a planar field... Agent: Scully, Scott, Murphy & Presser, P.C.

20090096004 - Semiconductor storage device and manufacturing method thereof: A semiconductor storage device includes: a substrate having a semiconductor layer at least on a surface thereof; and a plurality of quantum dot elements forming a charge storage layer formed above the semiconductor layer via a first insulating film that becomes a tunnel insulating film in such a manner that... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090096008 - Nonvolatile memory device and method of fabricating the same: A nonvolatile memory device having a blocking insulating layer with an excellent data retention property and a method of fabricating the same are provided. The nonvolatile memory device may include a semiconductor substrate having a channel region formed therein; and a gate stack including a tunneling insulating layer, a charge... Agent: Myers Bigel Sibley & Sajovec

20090096006 - Nonvolatile semiconductor storage apparatus and method for manufacturing the same: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage apparatus including: a semiconductor substrate on which element isolation trenches are formed to define element formation regions on the semiconductor substrate; gate insulating films that are formed on the element formation regions of the semiconductor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090096007 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090096005 - Semiconductor memory device including double spacers on sidewall of flating gate, electronic device including the same: A semiconductor memory device includes a device isolation layer formed in a semiconductor substrate to define a plurality of active regions. Floating gates are disposed on the active regions. A control gate line overlaps top surfaces of the floating gates and crosses over the active regions. The control gate line... Agent: Marger Johnson & Mccollom, P.C.

20090096012 - Flash memory device and method of fabricating the same: A flash memory secures a desired coupling ratio in a target thickness by lowering the leakage current through a high-dielectric (k) layer employing a combination of energy band gaps. The flash memory device includes a tunnel insulating layer formed on a semiconductor substrate, a first conductive layer formed on the... Agent: Townsend And Townsend And Crew, LLP

20090096011 - Non-volatile memory device having asymmetric source/drain junction and method for fabricating the same: Disclosed herein are non-volatile memory devices with asymmetric source/drain junctions and a method for fabricating the same. According to the method, a gate stack is formed on a semiconductor substrate, and impurity ions are implanted at a predetermined angle to form a source/drain junction in the semiconductor substrate. Thermal treatment... Agent: Marshall, Gerstein & Borun LLP

20090096009 - Nonvolatile memories which combine a dielectric, charge-trapping layer with a floating gate: A nonvolatile memory cell stores at least 50% of the charge in a dielectric, charge-trapping layer (160) and at least 20% of the charge in a floating gate (170). The floating gate is at most 20 nm thick.... Agent: Macpherson Kwok Chen & Heid LLP

20090096010 - Nonvolatile memory device and fabrication method thereof: A nonvolatile memory device and a fabrication method thereof are disclosed. The nonvolatile memory device comprises a tunnel insulating film formed on an active region of a semiconductor substrate, a first conductive layer for a floating gate formed on the tunnel insulating film, a dielectric layer formed on the first... Agent: Marshall, Gerstein & Borun LLP

20090096016 - Method of manufacturing a sonos device: A SONOS device and a method of manufacturing the same is provided. A tunnel dielectric layer, a charge trap layer, and a charge blocking layer are formed on a semiconductor substrate, and the charge blocking layer is formed on the charge trap layer such that the charge blocking layer is... Agent: Mckenna Long & Aldridge LLP

20090096013 - Non-volatile memory devices with charge storage regions: A memory device includes a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, and a control gate. Applying a positive bias to the control gate, the select gate and the... Agent: Macpherson Kwok Chen & Heid LLP

20090096014 - Nonvolatile memory devices that include an insulating film with nanocrystals embedded therein and methods of manufacturing the same: A nonvolatile memory device includes a semiconductor substrate, a charge-trap structure disposed on the semiconductor substrate, which includes an insulating film and a plurality of carbon nanocrystals embedded in the insulating film, and a gate disposed on the charge-trap structure. The nonvolatile memory device may exhibit memory hysteresis characteristics with... Agent: Myers Bigel Sibley & Sajovec

20090096015 - Nonvolatile semiconductor memory device and manufacturing method therefor: In a nonvolatile semiconductor memory device, a floating gate is formed on a semiconductor substrate through a gate insulating film, and has a first portion contacting the gate insulating film and a second portion extending upwardly from a part of a surface of the first portion. A first diffusion layer... Agent: Mcginn Intellectual Property Law Group, PLLC

20090096017 - Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same: A manufacturing method for stacked, non-volatile memory devices provides a plurality of bitline layers and wordline layers with charge trapping structures. The bitline layers have a plurality of bitlines formed on an insulating layer, such as silicon on insulator technologies. The wordline layers are patterned with respective pluralities of wordlines... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090096018 - Semiconductor device: A semiconductor device according to the present invention includes: a body region of a first conductive type; trenches formed by digging in from a top surface of the body region; gate electrodes embedded in the trenches; source regions of a second conductive type formed at sides of the trenches in... Agent: Rabin & Berdo, PC

20090096019 - Mosgated power semiconductor device with source field electrode: A power semiconductor device which includes a source field electrode, and at least one insulated gate electrode adjacent a respective side of the source field electrode, the source field electrode and the gate electrode being disposed in a common trench.... Agent: Ostrolenk Faber Gerb & Soffen

20090096020 - Semiconductror device and manufacturing method thereof: A semiconductor device includes field effect transistors, each having a semiconductor layer formed on a major surface of a semiconductor substrate, a base region formed in a surface layer portion of a semiconductor layer, a source region formed in a surface layer portion of the base region, a source electrode... Agent: Rabin & Berdo, PC

20090096021 - Semiconductor device having deep trench charge compensation regions and method: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.... Agent: Mr. Jerry Chruma Semiconductor Components Industries, L.L.C.

20090096022 - Lateral diffused metal oxide semiconductor device: An exemplary lateral diffused metal oxide semiconductor device includes a first-type substrate, a gate oxide film disposed on the first-type substrate, a poly gate disposed on the gate oxide film, a first second-type slightly doped region formed in the first-type substrate and acting as a well, a first first-type highly... Agent: PCe Industry, Inc. Att. Steven Reiss

20090096023 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device that eliminates the cause of increase in leakage current and therefore suppresses power increase in a highly integrated circuit by forming a shallow junction using a dopant-containing oxide film after etching a semiconductor substrate in source and drain regions.... Agent: Sherr & Vaughn, PLLC

20090096025 - Method for manufacturing a silicon-on-insulator (soi) wafer with an etch stop layer: Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these... Agent: Intel Corporation C/o Cpa Global

20090096024 - Semiconductor device and manufacturing method thereof: In a method for manufacturing a semiconductor device, a semiconductor film formed over an insulator is doped with an impurity element to a depth less than the thickness of the semiconductor film, thereby forming an impurity doped layer; a metal silicide layer is formed on the impurity doped layer; the... Agent: Nixon Peabody, LLP

20090096026 - Method of fabricating high voltage fully depleted soi transistor and structure thereof: A method of fabricating a high voltage fully depleted silicon-on-insulator (FD SOI) transistor, the FD SOI transistor having a structure including a region within a body on which a gate structure is disposed. The region includes a channel separating the source region and the drain region. Above the source region... Agent: Hoffman Warnick LLC

20090096027 - Power semiconductor device: A power semiconductor device comprising a first group of power transistor cells arranged in a first area of the power semiconductor device and a second group of power transistor cells arranged in a second area of the power semiconductor device. The first group of power transistor cells has an overall... Agent: Coats & Bennett/infineon Technologies

20090096028 - Transistor of the i-mos type comprising two independent gates and method of using such a transistor: The transistor comprises a source (1) and a drain (2) separated by a lightly doped intermediate zone (I). The intermediate zone (I) forms first (3) and second (4) junctions respectively with the source (1) and with the drain (2). The transistor comprises a first gate (5) to generate an electric... Agent: Oliff & Berridge, PLC

20090096030 - Semiconductor device: Provided is a semiconductor device in which an insulating region surrounding an element region is provided in an end portion of a semiconductor region with a super junction structure. Since a depletion layer in the element region ends in the insulating region, the end portion of the element region is... Agent: Barry E. Bretschneider Morrison & Foerster LLP

20090096029 - Semiconductor device and manufacturing method thereof: Disclosed is a semiconductor device wherein the switching speed of a transistor is increased. Specifically disclosed is a semiconductor device comprising a semiconductor layer formed on a part of an insulating layer, a first transistor formed on a lateral face of the semiconductor layer and having a first gate insulating... Agent: Wenderoth, Lind & Ponack, L.L.P.

20090096031 - Differential poly doping and circuits therefrom: A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and... Agent: Texas Instruments Incorporated

20090096032 - Semiconductor device and manufacturing method thereof: A semiconductor device includes first and second active regions on a semiconductor substrate, separated by an element isolation region; a line-shaped electrode disposed from over the first to over the second active region via the element isolation region; first and second FETs including a gate insulating film on the first... Agent: Young & Thompson

20090096033 - Isolation trench with rounded corners for bicmos process: A semiconductor device comprising a first transistor device on or in a semiconductor substrate and a second transistor device on or in the substrate. The device further comprises an insulating trench located between the first transistor device and the second transistor device. At least one upper corner of the insulating... Agent: Texas Instruments Incorporated

20090096034 - Partially and fully silicided gate stacks: Metal-oxide semiconductor (MOS) devices and techniques for the fabrication thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate; and at least one n-channel field effect transistor (NFET) having a gate stack over the substrate. The NFET gate stack comprises an NFET gate stack metal... Agent: Michael J. Chang, LLC

20090096035 - Semiconductor device, method for manufacturing semiconductor device, and method for manufacturing semiconductor memory device: A method for manufacturing a semiconductor device has forming a first insulating film on a semiconductor substrate, forming an electrode layer on said first insulating film, etching said electrode layer, said first insulating film and said semiconductor substrate of a first predetermined region to form a trench, burying an element-isolating... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090096036 - Semiconductor device and method of manufacturing the same: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090096037 - Semiconductor device having recessed field region and fabrication method thereof: A semiconductor device including an active region formed on a semiconductor substrate, and a field region adjacent to the active region, which is able to increase a width of the active region through use of a field recess portion at one surface side of the field region. The field recess... Agent: Marger Johnson & Mccollom, P.C.

20090096038 - Power mosfet array: A power metal-oxide-semiconductor field-effect transistor (MOSFET) array structure is provided. The power MOSFET array is disposed under a gate pad, and space under the gate pad can be well used to increase device integration. When the array and the conventional power MOSFET array disposed under the source pad are connected... Agent: Jianq Chyun Intellectual Property Office

20090096039 - High-voltage device and manufacturing method of top layer in high-voltage device: A high-voltage device including a first conductive type substrate, a gate, a second conductive type well, a second conductive type source region, a second conductive type drain region, conductive layers, and a first conductive type top layer. The gate is disposed on the substrate, and the well is disposed in... Agent: J C Patents, Inc.

20090096040 - Sensor geometry for improved package stress isolation: The sensor geometry for improved package stress isolation is disclosed. A counterbore on the backing plate improves stress isolation properties of the sensor. The counterbore thins the wall of the backing plate maintaining the contact area with the package. The depth and diameter of the counterbore can be adjusted to... Agent: Honeywell International Inc.

20090096041 - Semiconductor device: A semiconductor device is designed such that a semiconductor sensor chip having a diaphragm for detecting pressure variations based on the displacement thereof is fixed onto the upper surface of a substrate having a rectangular shape, which is covered with a cover member so as to form a hollow space... Agent: Dickstein Shapiro LLP

20090096042 - Magnetic element having reduced current density: A memory device includes a fixed magnetic layer, a tunnel barrier layer over the fixed magnetic layer, and a free magnetic structure formed over the tunnel barrier layer, wherein the free magnetic structure has layers or sub-layers that are weakly magnetically coupled. Thus, a low programming voltage can be used... Agent: Freescale Semiconductor, Inc. Law Department

20090096045 - Magnetoresistive device and nonvolatile magnetic memory equipped with the same: A fast and very low-power-consuming nonvolatile memory. A nonvolatile magnetic memory includes a high-output tunnel magnetoresistive device, in which spin-transfer torque is used for writing. A tunnel magnetoresistive device has a structure such that a ferromagnetic film of a body-centered cubic structure containing Co, Fe, and B, a MgO insulator... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090096043 - Mram with means of controlling magnetic anisotropy: We describe the manufacturing process for and structure of a CPP MTJ MRAM unit cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The strength of the switching field, Hs of the cell is controlled by the magnetic... Agent: Saile Ackerman LLC

20090096044 - Spin-wave architectures: Nano-scale and multi-scale computational architectures using spin waves as a physical mechanism for device interconnection are provided. Solid-state spin-wave computing devices using nano-scale and multi-scale computational architectures comprised of a plurality of inputs and a plurality of outputs are described where such devices are configured to simultaneously transmit data elements... Agent: Ballard Spahr Andrews & Ingersoll, LLP

20090096046 - Semiconductor device for radiation detection: The invention provides a semiconductor device (11) for radiation detection, which comprises a substrate region (1) of a substrate semiconductor material, such as silicon, and a detection region (3) at a surface of the semiconductor device (11), in which detection region (3) charge carriers of a first conductivity type, such... Agent: Philips Intellectual Property & Standards

20090096050 - Image sensor and method for manufacturing the same: Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a semiconductor substrate including a unit pixel, first to third color filters provided on the semiconductor substrate, a first micro-lens provided on each of the first and third color filters, and a second micro-lens... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090096047 - Imaging module package: An exemplary imaging module package includes a substrate, an imaging sensor chip set on the substrate, a housing positioned on the substrate, and a lens module. The housing includes a first chamber enclosing the imaging sensor chip therein, a second chamber coaxially extending from the first chamber for receiving the... Agent: PCe Industry, Inc. Att. Steven Reiss

20090096048 - Optical device and manufacturing method thereof and semiconductor device: An optical device includes a base and an optical element. The base has a through hole in a center and includes leads and a resin. Each lead has an L-shaped cross-section and is formed by an inner lead extending from the center toward a peripheral edge and an outer lead... Agent: Mcdermott Will & Emery LLP

20090096049 - Solid state imaging device, method of manufacturing the same, and imaging apparatus: A solid state imaging device having a light sensing section that performs photoelectric conversion of incident light includes: an insulating layer formed on a light receiving surface of the light sensing section; a layer having negative electric charges formed on the insulating layer; and a hole accumulation layer formed on... Agent: Sonnenschein Nath & Rosenthal LLP

20090096052 - Semiconductor device for radiation detection: The invention provides a semiconductor device (11) for radiation detection in a semiconductor substrate (1) comprising a detection region (3), which detects charge carriers that are generated upon incidence of radiation (X, L) on the semiconductor device (11). The semiconductor device further (11) comprises a further detection region (13), which... Agent: Philips Intellectual Property & Standards

20090096051 - Solid state imaging device and method for manufacturing same, and solid state imaging module: A solid state imaging device includes: an imaging device substrate with an imaging device section formed on a first major surface side thereof; a backside interconnect electrode provided on a second major surface side of the imaging device substrate and electrically connected to the imaging device section, the second major... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090096053 - Schottky barrier semiconductor device and method for manufacturing the same: A silicon carbide Schottky barrier semiconductor device provided with a Ta electrode as a Schottky electrode, in which the Schottky barrier height is controlled to a desired value in a range where power loss is minimized without increasing the n factor. The method for manufacturing the silicon carbide Schottky barrier... Agent: The Webb Law Firm, P.C.

20090096054 - Semiconductor device and method for manufacturing the same: A semiconductor device including a semiconductor substrate is provided. The semiconductor substrate includes a substrate having an insulating surface, and a plurality of stacks over the substrate having an insulating surface. Each of the plurality of stacks includes a bonding layer over the substrate having an insulating surface, an insulating... Agent: Eric Robinson

20090096055 - Method to form cmos circuits with sub 50nm sti structures using selective epitaxial silicon post sti etch: An STI field oxide element in an IC which includes a layer of epitaxial semiconductor on sidewalls of the STI trench to increase the width of the active area adjacent to the STI trench and decrease a width of dielectric material in the STI trench is disclosed. STI etch residue... Agent: Texas Instruments Incorporated

20090096056 - On-chip cooling systems for integrated circuits: Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. The cooling pipes system does not include any... Agent: Schmeiser, Olsen & Watts

20090096057 - Semiconductor device and method for fabricating the same: A semiconductor device includes a substrate where an isolation region and a plurality of active regions are defined, an anti-interference layer formed over the substrate in the isolation region, and a gate line simultaneously crossing the active region and the anti-interference layer.... Agent: Townsend And Townsend And Crew, LLP

20090096059 - Fuse structure including monocrystalline semiconductor material layer and gap: A fuse structure, a method for fabricating the fuse structure and a method for programming a fuse within the fuse structure each use a fuse material layer that is used as a fuse, and located upon a monocrystalline semiconductor material layer in turn located over a substrate. At least part... Agent: Scully, Scott, Murphy & Presser, P.C.

20090096058 - Pinched poly fuse: An electrical fuse has a region of a first conductivity type in a continuous type polysilicon of a second conductivity type that is opposite the first conductivity type. In one embodiment of the invention the PN junction between the region and the poly fuse is reverse biased.... Agent: Hiscock & Barclay, LLP

20090096060 - Antifuse structures, antifuse array structures, methods of manufacturing the same: Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of... Agent: Harness, Dickey & Pierce, P.L.C

20090096061 - Semiconductor device having high frequency wiring and dummy metal layer at multilayer wiring structure: A semiconductor device includes, a metal wiring, which functions as an inductor or transformer, formed on a first portion of a semiconductor substrate, a plurality of first dummy layers formed in a first density on the first portion of the semiconductor substrate, a plurality of second dummy layers formed in... Agent: Mcginn Intellectual Property Law Group, PLLC

20090096063 - Semiconductor apparatus with decoupling capacitor: A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair... Agent: Rabin & Berdo, PC

20090096062 - Stack capacitor in semiconductor device and method for fabricating the same: A stack capacitor in a semiconductor device includes a first capacitor formed on and/or over a semiconductor substrate and a second capacitor formed on and/or over the first capacitor. The first and second capacitors each have a multi-layer laminated structure which includes a lower electrode, a capacitor dielectric layer and... Agent: Sherr & Vaughn, PLLC

20090096064 - Method of forming poly pattern in r-string of lcd drive ic and structure of the same: A method of forming a poly pattern for minimizing a change in a storage value in the R-string pattern of the LCD panel drive IC (LDI) that includes depositing a poly silicon layer used as a resistor in a R-string structure over a semiconductor substrate; and then forming a poly... Agent: Sherr & Vaughn, PLLC

20090096065 - Electrical isolation of monolithic circuits using a conductive through-hole in the substrate: A monolithic electronic chip including: a substrate; a first circuit formed on a first circuit portion of the substrate; a second circuit formed on a second circuit portion of the substrate; and at least one conductive impedance tap formed a through-hole in the substrate. The substrate includes first and second... Agent: Ratnerprestia

20090096066 - Structure and method for device-specific fill for improved anneal uniformity: Disclosed is a design structure embodiment of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090096067 - Method of fabricating a metal oxynitride thin film that includes a first annealing of a metal oxide film in a nitrogen-containing atmosphere to form a metal oxynitride film and a second annealing of the metal oxynitride film in an oxidizing atmosphere: After the surface of the substrate is cleaned, an interface layer or an antidiffusion film is formed. A metal oxide film is built upon the antidiffusion film. Annealing is done in an NH3 atmosphere so as to diffuse nitrogen in the metal oxide film. Building of the metal oxide film... Agent: Cantor Colburn, LLP

20090096069 - Cof board: A COF board includes an insulating layer, and a terminal portion formed on the insulating layer. The terminal portion includes a first lead extending in a longitudinal direction, and a second lead extending in the longitudinal direction, and having a smaller length in the longitudinal direction than a length of... Agent: Akerman Senterfitt

20090096068 - System and method for stabilizing an amplifier: In one embodiment of the present invention, a semiconductor circuit including an amplifier disposed on a semiconductor substrate is disclosed. A first bond wire coupled to an input of the amplifier, a second bond wire coupled to an output of the amplifier, and a third bond wire coupled in series... Agent: Slater & Matsil LLP

20090096070 - Semiconductor package and substrate for the same: A semiconductor package is revealed with a special designed substrate. The substrate has a plurality of fingers, a dummy metal pattern, and at least a peripheral slot penetrating through the substrate. The dummy metal pattern is aligned to two opposing sides of the peripheral slot and is electrically isolated from... Agent: Joe Mckinney Muncy

20090096071 - Semiconductor package and electronic device having the same: A semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the... Agent: Stanzione & Kim, LLP

20090096072 - Package for a power semiconductor device: A package for a semiconductor die includes a die attach pad that provides an attachment surface area for the semiconductor die, and tie bars connected to the die attach pad. The die attach pad is disposed in a first general plane and the tie bars are disposed in a second... Agent: The Law Offices Of Bradley J. Bereznak

20090096074 - Semiconductor device: Disclosed herewith is a semiconductor device, which includes a semiconductor chip; a lead device that includes an island for mounting the semiconductor chip and having an area smaller than that of the semiconductor chip at its contact surface, as well as plural hanging leads for supporting the island and coming... Agent: Mcginn Intellectual Property Law Group, PLLC

20090096073 - Semiconductor device and lead frame used for the same: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090096075 - Stacked semiconductor package that prevents damage to semiconductor chip when wire-bonding and method for manufacturing the same: A stacked semiconductor package includes a substrate having first and second contact pads. A first stacked package group is disposed on the substrate, and the first stacked package group includes first semiconductor chips stacked in a stair form to expose first edge bonding pads. First conductive wires are used to... Agent: Ladas & Parry LLP

20090096076 - Stacked semiconductor package without reduction in stata storage capacity and method for manufacturing the same: A stacked semiconductor package includes a semiconductor chip module including at least two semiconductor chips with a semiconductor chip body having an upper surface, a lower surface, side surfaces coupling the upper surface and the lower surface, and a circuit part. The semiconductor chips include pads coupled to the circuit... Agent: Ladas & Parry LLP

20090096077 - Tenon-and-mortise packaging structure: A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least one tenon projection, and the lower surface forms a mortise slot corresponding to the tenon projection in... Agent: Bacon & Thomas, PLLC

20090096078 - Semiconductor device and method for manufacturing a semiconductor device: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die.... Agent: Mayer & Williams PC

20090096079 - Semiconductor package having a warpage resistant substrate: A semiconductor package is presented having a substrate, a semiconductor chip, an under-fill material, and a solder resist pattern. The substrate having a substrate body, wiring lines which are located on a first surface of the substrate body and which have connection pad parts, and ball lands which are located... Agent: Ladas & Parry LLP

20090096080 - Semiconductor package, electronic part and electronic device: Even when a substrate on which a semiconductor package has been mounted is made curved, stress upon electrical connections is mitigated, thereby eliminating faulty connections and improving connection reliability. A semiconductor chip has electrodes on a second face thereof. Support blocks, capable of bending and flexing, are placed at two... Agent: Young & Thompson

20090096081 - Semiconductor device: A semiconductor device includes a substrate, at least one semiconductor element mounted on the substrate, a resin housing for housing the semiconductor element, the resin housing having a cover thereon, at least one pin provided and standing in the resin housing, and at least one printed substrate disposed inside the... Agent: Kanesaka Berner And Partners LLP

20090096083 - Connecting structure for connecting at least one semiconductor component to a power semiconductor module: A connecting structure comprising a connecting device for electrically conductive connection to at least one semiconductor component and a filler. The connecting device is a film composite comprising at least two electrical films with an insulating film therebetween. The electrically conductive films are inherently structured and thus form conductor tracks.... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090096082 - High speed electrical interconnects and method of manufacturing thereof: A high speed electrical interconnection system is provided. The interconnection system comprises one or more electrical signal lines, or differential pairs of signal lines, and an inhomogeneous dielectric system. The dielectric system further comprises a homogeneous dielectric layer interposed between the electrical signal lines, and electrical conducting planes including a... Agent: Banpil Photonics, Inc.

20090096084 - Semiconductor chip packages having reduced stress: A structure and a method for forming the same. The structure includes (i) a carrier substrate which includes substrate pads, (ii) a chip physically attached to the carrier substrate, and (iii) a first frame physically attached to the carrier substrate. A CTE (coefficient of thermal expansion) of the first frame... Agent: Schmeiser, Olsen & Watts

20090096085 - Thermally enhanced wafer level package: A method of forming a package structure includes providing a plurality of dies; attaching the plurality of dies onto a heat-dissipating plate; and sawing the heat-dissipating plate into a plurality of packages, each including one of the plurality of dies and a piece of the heat-dissipating plate.... Agent: Slater & Matsil, L.L.P.

20090096086 - Cooling system for semiconductor devices: In one embodiment, the present invention includes a socket for a semiconductor package, where the socket has a frame with a segmented design, where socket streets are located between the segments. One or more of the streets may include a conduit to enable thermal transfer during operation of the semiconductor... Agent: Trop, Pruner & Hu, P.C.

20090096087 - Microelectronic assembly and method of preparing same: A microelectronic assembly includes a die (110, 210) having a surface (111, 211), a heat sink (120, 220) removably attached to the die, a thermally conductive layer (130, 230) between the die and the heat sink, and an anti-adhesion layer (140, 240) between the die and the heat sink. The... Agent: Intel Corporation C/o Cpa Global

20090096088 - Sealed wafer packaging of microelectromechanical systems: Multiple microelectromechanical systems (MEMS) on a substrate are capped with a cover using a layer that may function as a bonding agent, separation layer, and hermetic seal. A substrate has a first side with multiple MEMS devices. A cover is formed with through-holes for vias, and with standoff posts for... Agent: General Electric Company Global Research

20090096089 - Method for producing a thin semiconductor chip comprising an integrated circuit: In a method for producing a thin film chip including an integrated circuit, a semi-conductor wafer having a first surface is provided. At least one cavity is produced under a defined section of the first surface by means of porous silicon. A circuit structure is produced in the defined section.... Agent: Harness, Dickey & Pierce, P.L.C

20090096090 - Photolithography process and photomask structure implemented in a photolithography process: In a photolithography process, a photoresist layer is formed on a substrate. A photomask is aligned over the substrate to transfer pattern images defined in the photomask on the substrate. The photomask includes first and second patterns of different light transmission rates, and a dummy pattern surrounding the second pattern... Agent: David I. Roche Baker & Mckenzie LLP

20090096091 - Semiconductor device manufacturing apparatus, semiconductor device manufacturing method and semiconductor device: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090096092 - Bump i/o contact for semiconductor device: A bump contact electrically connects a conductor on a substrate and a contact pad on a semiconductor device mounted to the substrate. The first end of an electrically conductive pillar effects electrical contact and mechanical attachment of the pillar to the contact pad with the pillar projecting outwardly from the... Agent: North Weber & Baugh LLP

20090096093 - Inter-connecting structure for semiconductor package and method of the same: The interconnecting structure for a semiconductor die assembly comprises a build-up layers having RDL formed therein formed over a die having die pads formed thereon, wherein the RDL is coupled to the die pads; an isolation base having ball openings attached over the build-up layer to expose ball pads within... Agent: Kusner & Jaffe Highland Place Suite 310

20090096094 - Semiconductor device: In a wafer level CSP package, with respect to signal wiring 9b disposed in a signal wiring disposition forbidden region 16 in the vicinity of external output terminals disposed in a package outer peripheral portion, since a stress generated at signal wiring 9 can be dispersed by disposing dummy wiring... Agent: Steptoe & Johnson LLP

20090096096 - Semiconductor device and circuit device having the same mounted thereon: A semiconductor device has a semiconductor chip, terminals formed at a prescribed terminal pitch on the bottom side of the semiconductor chip, and columnar post electrodes formed on the terminals. The post electrodes are formed of two different metals, the side bonded with the terminals is constituted by first metallic... Agent: K.a. Patents

20090096097 - Semiconductor device and manufacturing method of the same: Semiconductor device 10 includes wiring substrate 11 including wiring 14 and wiring 15 in predetermined patterns, semiconductor chips 19 and 23 which are mounted on wiring substrate 11 with electrodes electrically connected to wiring 14 of wiring substrate 11 via wires 21 and 24, first sealing body 25 made of... Agent: Mcginn Intellectual Property Law Group, PLLC

20090096095 - Semiconductor device and method of manufacturing the same: Provided is a semiconductor device having a substrate, a semiconductor chip flip-chip mounted on the substrate, and a stacked film provided in a gap between the substrate and the semiconductor chip. The stacked film is composed of a protective film covering the surface of the substrate, and an underfill film... Agent: Mcginn Intellectual Property Law Group, PLLC

20090096098 - Inter-connecting structure for semiconductor package and method of the same: The interconnecting structure for a semiconductor die assembly comprises a build-up layers having RDL formed therein formed over a die having die pads formed thereon, wherein the RDL is coupled to the die pads; an isolation base having ball openings attached over the build-up layer to expose ball pads within... Agent: Kusner & Jaffe Highland Place Suite 310

20090096099 - Package substrate and method for fabricating the same: A package substrate and a method for fabricating the same are provided according to the present invention. The package substrate includes: a substrate body with a die attaching side and a ball implanting side lying opposite each other, having a plurality of wire bonding pads and a plurality of solder... Agent: Sawyer Law Group LLP

20090096101 - Bridge for semiconductor internal node: A method and apparatus for forming connections within a semiconductor device is disclosed. The semiconductor device incorporates a contact bridge between transistor contacts in close proximity. The contact bridge comprises a plurality of metal pillars each having a lower end in electrical contact with first and second transistor elements, respectively;... Agent: International Business Machines Corporation Dept. 18g

20090096100 - Semiconductor apparatus, manufacturing method of semiconductor apparatus, and joint material: A die bonding portion is metallically bonded by well-conductive Cu metal powders with a maximum particle diameter of about 15 μm to 200 μm and adhesive layers of Ag, and minute holes are evenly dispersed in a joint layer. With this structure, the reflow resistance of about 260° C. and... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090096102 - Conductor structure including manganese oxide capping layer: A microelectronic structure includes a dielectric layer located over a substrate. The dielectric layer is separated from a copper containing conductor layer by an oxidation barrier layer. The microelectronic structure also includes a manganese oxide layer located aligned upon a portion of the copper containing conductor layer not adjoining the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090096103 - Semiconductor device and method for forming barrier metal layer thereof: A method for forming a barrier metal layer includes forming a metal compound film composed of a first metal and a second metal on sidewalls of a contact hole, and then selectively etching the metal compound film and then simultaneously forming a barrier metal layer and a first metal seed... Agent: Sherr & Vaughn, PLLC

20090096105 - Contact structure of a wires and method manufacturing the same, and thin film transistor substrate including the contact structure and method manufacturing the same: In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes,... Agent: Macpherson Kwok Chen & Heid LLP

20090096104 - Semiconductor device having crack stop structure: Example embodiments relate to semiconductor devices having a single body crack stop structure configured to reduce or prevent crack propagation and/or moisture penetration. A semiconductor substrate according to example embodiments may include an active region and a crack stop region surrounding the active region. Interlayer insulating layers may be sequentially... Agent: Harness, Dickey & Pierce, P.L.C

20090096106 - Antireflective coatings: A method of forming a feature in a substrate comprising the steps of: forming a dielectric layer on a substrate; forming an antireflective coating over the dielectric layer; forming a photoresist pattern over the antireflective coating; etching the dielectric layer through the patterned photoresist; and removing the antireflective coating and... Agent: Air Products And Chemicals, Inc. Patent Department

20090096107 - Semiconductor integrated circuit device: In a semiconductor integrated circuit device, an element forming region and a metal wiring layer are covered with a passivation layer on a semiconductor substrate which is cut out in a rectangular shape. At four corners of the device, the passivation layer is provided with corner non-wiring regions formed directly... Agent: Fish & Richardson P.C. Citigroup Center

20090096108 - Structure and methods of forming contact structures: Methods and a structure. A method of forming contact structure includes depositing a silicide layer onto a substrate; depositing an electrically insulating layer over a first surface of the silicide layer; forming a via through the insulating layer extending to the first surface; depositing an electrically conductive layer covering a... Agent: Schmeiser, Olsen & Watts

20090096109 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a first insulation film formed over a semiconductor substrate; and a plurality of first interconnects selectively formed in the first insulation film. A plurality of gaps are formed in part of the first insulation film located between adjacent ones of the first interconnects so that each... Agent: Mcdermott Will & Emery LLP

20090096112 - Integrated circuit underfill package system: An integrated circuit underfill package system including providing a substrate having a dispense port, attaching a first integrated circuit die on the substrate, and supplying an underfill to the dispense port when the substrate and the first integrated circuit die are inverted.... Agent: Law Offices Of Mikio Ishimaru

20090096110 - Method for manufacturing a stacked semiconductor package, and stacked semiconductor package: A method for manufacturing a stacked semiconductor package where a plurality of semiconductor chips are stacked on a substrate, including: forming insulating layers at portions of a wafer corresponding to sides of the plurality of semiconductor chips when the plurality of semiconductor chips are in the wafer; processing the wafer... Agent: Amin, Turocy & Calvin, LLP

20090096111 - Semiconductor device and method of manufacturing the same: In a semiconductor device, a first semiconductor chip is stacked on a wiring substrate and has first electrode pads disposed at predetermined positions on an upper surface thereof. A second semiconductor chip is stacked on the first semiconductor chip through an insulating member in an offset manner so that the... Agent: Mcginn Intellectual Property Law Group, PLLC

20090096113 - Soi on package hypersensitive sensor: A hypersensitive semiconductor die structure is disclosed, in which flip-chip packaging is used in conjunction with a modified SOI die in which a thick silicon support substrate has been removed to increase sensitivity of the sensing device. Rather than being located beneath layers of interconnects and dielectric, the disclosed structure... Agent: Honeywell International Inc.

20090096114 - Epoxy resin composition and semiconductor device: wherein R1 and R2 are independently hydrogen or alkyl having 1 to 4 carbon atoms and two or more R1s or two or more R2s are the same or different; a is integer of 0 to 4; b is integer of 0 to 4; c is integer of 0 to... Agent: Smith, Gambrell & Russell

20090096115 - Semiconductor package and method for fabricating the same: A semiconductor package and a method for fabricating the same are disclosed. The present invention discloses mounting and electrically connecting a semiconductor chip to a chip carrier, forming an interfacial layer or a heat-dissipating member having the interfacial layer on the semiconductor chip, and forming an encapsulant for covering the... Agent: Edwards Angell Palmer & Dodge LLP

20090096116 - Alignment mark and mehtod for forming the same: The invention is directed to an alignment mark in a material layer in an alignment region of a wafer. The alignment mark comprises a plurality of sub-marks. Each of the sub-mark comprises a first element and a plurality of second elements. The second elements are embedded in the first element... Agent: J C Patents, Inc.

20090090899 - Phase change memory device and method of manufacturing the same: A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer... Agent: Lee & Morse, P.C.

20090090900 - Optoelectronic semiconductor chip: An optoelectronic semiconductor chip comprises the following sequence of regions in a growth direction (c) of the semiconductor chip (20): a p-doped barrier layer (1) for an active region (2), the active region (2), which is suitable for generating electromagnetic radiation, the active region being based on a hexagonal compound... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090090901 - Semiconductor light emitting device and method for manufacturing the same: Disclosed is a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive semiconductor layer, a lower super lattice layer under the first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, a second conductive super lattice layer on the active layer, and a... Agent: Birch Stewart Kolasch & Birch

20090090902 - Optical devices using a penternary iii-v material system: The invention relates to the design and processing of a semiconductor optical device. The device is formed of at least four layers of III-V compounds in which one consists of the penternary AlGalnAsSb material. The structure is wet etched in order to form optical ridge waveguides. One such device has... Agent: Dennison, Schultz & Macdonald

20090090903 - Cmos image sensor having thiophene derivatives: Provided is a CMOS image sensor that uses thiophene derivatives. The CMOS image sensor includes first through third photoelectric conversion units vertically and sequentially stacked on a semiconductor substrate. The first photoelectric conversion unit detects blue light and comprises a first electrode, a second electrode, and a p-type thiophene derivative... Agent: Cantor Colburn, LLP

20090090907 - Electrochemical device: An electrochemical device is provided, comprising a source contact connected to a first antenna pad, a drain contact connected to a second antenna pad, at least one gate electrode, an electrochemically active element arranged between, and in direct electrical contact with, the source and drain contacts, which electrochemically active element... Agent: Harness, Dickey & Pierce, P.L.C

20090090905 - Molecular device, single-molecular optical switching device, functional device, molecular wire, and electronic apparatus using functional device: A molecular device including: at least one molecule of zinc cytochrome c; in which an electron or a hole is transferred within the at least one molecule of zinc cytochrome c bar utilizing transition of an electron between molecular orbitals of the at least one molecule of zinc cytochrome c.... Agent: Bell, Boyd & Lloyd, LLP

20090090904 - Organic semiconductor device: Provided is an organic tunneling p-n junction diode. The organic tunneling p-n junction diode includes an n-doped organic semiconductor layer and a p-doped organic semiconductor layer which are doped with extrinsic impurities. When either a reverse-bias voltage or a forward-bias voltage is applied, the organic tunneling p-n junction diode is... Agent: Robert E. Bushnell & Law Firm

20090090906 - Organic thin film transistor device and manufacturing method therefor: An organic TFT device in which a plurality of organic TFTs can be formed in a narrow region and a manufacturing method therefor are proposed. The organic TFT device comprises a substrate, and a plurality of organic TFTs disposed in a transistor region on the substrate. The organic TFT device... Agent: Drinker Biddle & Reath (dc)

20090090908 - Providing a duplicate test signal of an output signal under test in an integrated circuit: Providing a duplicate test signal of an output signal under test in an integrated circuit including selecting through a multiplexer an output signal under test, the output signal under test selected from a plurality of output signals of the integrated circuit; providing through the multiplexer a duplicate signal of the... Agent: Ibm (rps-blf) C/o Biggers & Ohanian, LLP

20090090909 - Semiconductor device and manufacturing method thereof: To improve field effect mobility of an inverted-staggered TFT using amorphous silicon. In an inverted-staggered TFT, a thin amorphous semiconductor layer which is made to have n-type conductivity is formed between a gate insulating film and an amorphous semiconductor layer. By depositing an amorphous semiconductor layer after a substrate over... Agent: Eric Robinson

20090090911 - Manufacturing thin film transistor array panels for flat panel displays: A thin film transistor array panel for a flat panel display includes a substrate, a first signal line formed on the substrate, a second signal line intersecting and insulated from the first signal line, a switching element having a first terminal connected to the first signal line, a second terminal... Agent: Macpherson Kwok Chen & Heid LLP

20090090912 - Structure of thin film transistor array: A substrate having a gate electrode layer, a gate insulating layer, and a silicon layer thereon is provided. These layers are patterned into a gate area, a gate line and a gate line wiring area. A passivation layer is formed on the entire substrate and patterned to form two contact... Agent: Jianq Chyun Intellectual Property Office

20090090910 - Thin-film element, display device and memory cell using the thin-film element, and their fabrication methods: Pixel auxiliary capacitors (10) and pixel TFTs, which are thin-film elements, are formed on a substrate a lower electrode (Si) (3), insulating film, and an upper electrode (GE) (5) in this order. Each upper electrode (GE) (5) opposing to the corresponding lower electrode (Si) (3) is entirely enclosed within the... Agent: Nixon & Vanderhye, PC

20090090913 - Dual-gate memory device with channel crystallization for multiple levels per cell (mlc): A method and a dual-gate memory device having a memory transistor and an access transistor are provided to allow multiple bits to be stored in the dual-gate memory device. The memory transistor and the access transistor each have a channel region formed in a mobility enhanced material crystallized from an... Agent: Macpherson Kwok Chen & Heid LLP

20090090914 - Semiconductor thin film, method for producing the same, and thin film transistor: A transparent semiconductor thin film 40 having low carrier concentration and a large energy band gap is produced by forming a thin film which contains indium oxide and an oxide of a positive divalent element, and then oxidizing or crystallizing the thin film.... Agent: Millen, White, Zelano & Branigan, P.C.

20090090915 - Thin film transistor, display device having thin film transistor, and method for manufacturing the same: A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and methods for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over... Agent: Eric Robinson

20090090916 - Thin film transistor, display device having thin film transistor, and method for manufacturing the same: A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed... Agent: Eric Robinson

20090090917 - Gan single-crystal substrate and method for producing gan single crystal: A GaN single-crystal substrate has a substrate surface in which polarity inversion zones are included. The number density of the polarity inversion zones in the substrate surface is not more than 20 cm−2. A GaN single crystal production method includes introducing group III and V raw material gases on a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090090919 - Semiconductor device and method of producing the same: A semiconductor device includes a silicon carbide substrate having a channel region formed on a surface thereof; a silicon layer formed on the channel region; a gate insulation film formed on the silicon layer; and a gate electrode formed on the gate insulation film. A method of producing a semiconductor... Agent: Kubotera & Associates, LLC

20090090920 - Silicon carbide semiconductor device: A silicon carbide semiconductor device is disclosed. The silicon carbide semiconductor device includes a substrate; a drift layer having a first conductivity type and located on a first surface of the substrate; and a vertical type semiconductor element. The vertical type semiconductor element includes: an impurity layer having a second... Agent: Posz Law Group, PLC

20090090918 - Transparent nanocrystalline diamond contacts to wide bandgap semiconductor devices: A heterojunction between thin films of NCD and 4H—SiC was developed. Undoped and B-doped NCDs were deposited on both n− and p− SiC epilayers. I-V measurements on p+ NCD/n− SiC indicated Schottky rectifying behavior with a turn-on voltage of around 0.2 V. The current increased over eight orders of magnitude... Agent: Naval Research Laboratory Associate Counsel (patents)

20090090922 - Method of manufacturing gallium nitride-based compound semiconductor light-emitting device, gallium nitride-based compound semiconductor light-emitting device, and lamp: Provided are a method of manufacturing a gallium nitride-based compound semiconductor light-emitting device with a low driving voltage (Vf) and high light outcoupling efficiency, a gallium nitride-based compound semiconductor light-emitting device, and a lamp. In the method of manufacturing the gallium nitride-based compound semiconductor light-emitting device, a transparent conductive oxide... Agent: Sughrue Mion, PLLC

20090090921 - Nitride semiconductor light emitting diode: A nitride semiconductor light emitting diode (LED) comprises an n-type nitride semiconductor layer; an electron emitting layer formed on the n-type nitride semiconductor layer, the electron emitting layer being composed of a nitride semiconductor layer including a transition element of group III; an active layer formed on the electron emitting... Agent: Lowe Hauptman Ham & Berner, LLP

20090090923 - Method for manufacturing a semiconductor light-emitting device and semiconductor light-emitting device: A semiconductor light-emitting device and method for manufacturing the semiconductor light-emitting device includes a mask layer etching process on first and second mask layers provided on a Group-III nitride-based compound semiconductor substrate, the mask layer with a higher etching rate being closer to the p-type semiconductor layer; a semiconductor layer... Agent: Rohm Co., Ltd. C/o Keating & Bennett, LLP

20090090924 - Intermediate optical packages and systems comprising the same, and their uses: Methods and apparatuses for forming optical packages, and intermediate structures resulting from the same are disclosed, which provide an optical element over a device. The optical element is formed by applying a force to lateral portions of a liquid material layer formed below an elastomeric material layer such that the... Agent: Dickstein Shapiro LLP

20090090925 - Semiconductor device: There are a silicon laser device having a IV-group semiconductor such as silicon or germanium equivalent to the silicon as a basic constituent element on a substrate made of the silicon, and the like by a method capable of easily forming the silicon laser device by using a general silicon... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090090928 - Light emitting module and method for manufacturing the same: Provided are: a light emitting module capable of ensuring a high heat-dissipating property and mountable in any of sets in various shapes; and a method for manufacturing the light emitting module. The light emitting module mainly includes: a metal substrate; an insulating layer covering the upper surface of the metal... Agent: Morrison & Foerster LLP

20090090926 - Solid state light emitting device: A solid state light emitting device includes a laminated substrate structure (120), an LED chip (30), a transparent capsulation material (50) and an electric component (40). The laminated substrate structure includes a first substrate (10) and a second substrate (20) attached to each other by a sintering process. The first... Agent: PCe Industry, Inc. Att. Steven Reiss

20090090927 - Structure of light emitted diode package: A structure of light emitted diode package including a lead frame, a holder coupled on an end of the lead frame, a LED chip disposed on the holder, a lower sealing portion made by injection molding a first resin material to grab one end of lead frame with the LED... Agent: Joe Mckinney Muncy

20090090929 - Light-emitting diode chip and manufacturing method thereof: A light-emitting diode (LED) chip includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer and a groove. The first semiconductor layer, active layer and second semiconductor layer are formed on the substrate in sequence. The groove is formed in the first semiconductor layer, the active... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090090930 - Epitaxial substrate and manufacturing method thereof and manufacturing method of light emitting diode apparatus: A manufacturing method of an epitaxial substrate includes the steps of: forming a sacrificial layer, which has a first micro/nano structure, on a substrate; and forming a buffer layer on the sacrificial layer. The sacrificial layer comprises a plurality of micro/nano particles, and the first micro/nano structure is formed after... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090090932 - Nitride semiconductor ultraviolet leds with tunnel junctions and reflective contact: A structure and method for improving UV LED efficiency is described. The structure utilizes a tunnel junction to separate a P-doped layer of the LED from a n-doped contact layer. The n-doped contact layer allows the use of a highly reflective, low work function metal, such as aluminum, for the... Agent: Patent Documentation Center

20090090931 - Semiconductor light-emitting device and method of fabricating the same: The invention discloses a semiconductor light-emitting device and a method of fabricating the same. The semiconductor light-emitting device according to the invention includes a substrate, a buffer layer, a corrosion-resistant film, a multi-layer structure, and an ohmic electrode structure. The buffer layer is grown on an upper surface of the... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090090934 - Field effect transistor and method for manufacturing the same: A method for manufacturing a field effect transistor, includes: forming a mask of an insulating film on a semiconductor layer containing Si formed on a semiconductor substrate; forming the semiconductor layer into a mesa structure by performing etching with the use of the mask, the mesa structure extending in a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090090935 - High performance cmos device design: A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second... Agent: Slater & Matsil, L.L.P.

20090090933 - Method of producing strained si-soi substrate and strained si-soi substrate produced by the same: A strained Si-SOI substrate, and a method for producing the same are provided, wherein the method includes the steps of growing a SiGe mixed crystal layer 14 on an SOI substrate 10 having an Si layer 13 and a buried oxide film 12; forming protective films 15, 16 on the... Agent: Kolisch Hartwell, P.C.

20090090936 - Electric field read/write head, method of manufacturing the same, and information storage device comprising electric field read/write head: Provided is an electric field head including a resistance sensor to read information recorded on a recording medium. The resistance sensor includes a first semiconductor layer including a source and a drain, and a second semiconductor layer that is heterogeneously combined with the first semiconductor layer. Also, the electric field... Agent: Sughrue Mion, PLLC

20090090937 - Unit pixels, image sensor containing unit pixels, and method of fabricating unit pixels: Example embodiments provide a unit pixel, an image sensor containing unit pixels, and a method of fabricating unit pixels. The unit pixel may include a semiconductor substrate, photoelectric transducers formed within the semiconductor substrate, multi-layered wiring layers formed on a frontside of the semiconductor substrate, inner lenses formed on a... Agent: Harness, Dickey & Pierce, P.L.C

20090090938 - Channel stress engineering using localized ion implantation induced gate electrode volumetric change: A method for fabricating a semiconductor structure uses a volumetric change ion implanted into a volumetric change portion of a gate electrode that is located over a channel region within a semiconductor substrate to form a volume changed portion of the gate electrode located over the channel region within the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090090939 - Self-assembled sidewall spacer: A semiconductor structure is provided that includes a spacer directly abutting a topographic edge of at least one patterned material layer. The spacer is a non-removable polymeric block component of a self-assembled block copolymer. A method of forming such a semiconductor structure including the inventive spacer is also provided that... Agent: Scully, Scott, Murphy & Presser, P.C.

20090090940 - Semiconductor device: A semiconductor device is provided, which includes a first insulating layer over a first substrate, a transistor over the first insulating layer, a second insulating layer over the transistor, a first conductive layer connected to a source region or a drain region of the transistor through an opening provided in... Agent: Nixon Peabody, LLP

20090090941 - Semiconductor device and method of manufacturing the same: Aimed at providing a highly reliable semiconductor device appropriately increased in stress at the channel region so as to improve carrier injection rate, thereby dramatically improved in transistor characteristics, and made adaptable also to recent narrower channel width, and a method of manufacturing the same, and a method of manufacturing... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090090942 - Wiring structure, array substrate, display device having the same and method of manufacturing the same: A wiring structure includes a substrate, a copper oxide layer having 16˜39 at % oxygen on the substrate and a copper layer on the copper oxide layer. The copper oxide layer has a thickness of 10-1000 Å and the copper layer has a thickness of 300-8000 Å. The copper layer... Agent: Macpherson Kwok Chen & Heid LLP

20090090943 - Solid-state imaging device and manufacturing method of the same: A solid-state imaging device of the present invention includes: a semiconductor substrate including a first region of a first conductivity type; a signal accumulation region of a second conductivity type formed within the first region; a gate electrode formed above the first region; a drain region of a second conductivity... Agent: Greenblum & Bernstein, P.L.C

20090090944 - Image sensor and method of fabricating the same: Provided is an image sensor and a method of fabricating the image sensor. The image sensor can comprise: a semiconductor substrate comprising a photodiode; a metal wiring layer disposed on the semiconductor substrate and comprising a metal wiring and an interlayer dielectric; a trench formed in the interlayer dielectric to... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090090945 - Pixel with transfer gate with no isolation edge: A pixel and imager device, and method of forming the same, where the pixel has a transfer transistor gate associated with a photoconversion device and is isolated in a substrate by shallow trench isolation. The transfer transistor gate does not overlap the shallow trench isolation region.... Agent: Dickstein Shapiro LLP

20090090946 - Dram cell with magnetic capacitor: A DRAM cell includes a substrate, a transistor, and a magnetic capacitor. The substrate is composed of semiconductor material with a main surface, the transistor is formed at the main surface, and the magnetic capacitor is formed in a metal layer. The transistor includes a source region and a drain... Agent: Patterson & Sheridan, L.L.P.

20090090948 - Semiconductor device and a method of manufacturing the same: In a semiconductor device comprising a capacitive element, an area of the capacitive element is reduced without impairing performance, and further, without addition of an extra step in a manufacturing process. A first capacitor is formed between an active region of a semiconductor substrate provided through a first capacitive insulating... Agent: Miles & Stockbridge PC

20090090947 - Semiconductor device and method of manufacturing a semiconductor device: A semiconductor device includes a substrate having a first area and a second area, a first active structure disposed in the first area, a second active structure disposed in the second area, a first transistor disposed in the first area and a second transistor disposed in the second area. The... Agent: Myers Bigel Sibley & Sajovec

20090090949 - Semiconductor device and method of manufacturing the same: A semiconductor device includes: an active region insulated by an element-isolation insulating film embedded on a semiconductor substrate; multiple element forming sections that are provided in the active region; a semiconductor element that is formed in each of the element forming sections; and a channel stopper that is provided in... Agent: Young & Thompson

20090090950 - Semiconductor devices: Methods, devices, modules, and systems providing semiconductor devices in a stacked wafer system are described herein. One embodiment includes a first wafer for NMOS transistors in a CMOS architecture and a second wafer for PMOS transistors in the CMOS architecture, with the first wafer being bonded and electrically coupled to... Agent: Brooks, Cameron & Huebsch , PLLC

20090090951 - Capacitors integrated with metal gate formation: A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate; and a capacitor over the substrate. The capacitor includes a first layer including a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is formed... Agent: Slater & Matsil, L.L.P.

20090090953 - Flash memory device with straight word lines: Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090090952 - Plasma surface treatment for si and metal nanocrystal nucleation: A device, such as a nonvolatile memory device, and methods for forming the device in an integrated process tool are provided. The method includes depositing a tunnel oxide layer on a substrate, exposing the tunnel oxide layer to a plasma so that the plasma alters a morphology of a surface... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090090955 - Elevated channel flash device and manufacturing method thereof: A FLASH device including a substrate having a protrusive portion integrally formed thereon, two floating gates, a control gate and a dielectric layer is provided. The two floating gates are disposed on two sides of the protrusive portion and respectively covering a portion of the protrusive portion. The control gate... Agent: Jianq Chyun Intellectual Property Office

20090090956 - Flash memory device and method of manufacturing flash memory device: Provided is a flash memory device and a method of manufacturing the same. In the method, a tunnel oxide layer pattern and a first polysilicon pattern are formed on a semiconductor substrate. A first dielectric layer including a first oxide layer, a first nitride layer, a second oxide layer, a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090090957 - Multi-valued mask rom: A mask ROM is provided with a plurality of memory cells each including first and second nodes, and a transistor having a source and drain connected to the first and second nodes, respectively. A first memory cell out of the plurality of memory cells further includes a first resistive interconnection... Agent: Mcginn Intellectual Property Law Group, PLLC

20090090954 - Nonvolatile memory and manufacturing method thereof: Memory elements, switching elements, and peripheral circuits to constitute a nonvolatile memory are integrally formed on a substrate by using TFTs. Since semiconductor active layers of memory element TFTs are thinner than those of other TFTs, impact ionization easily occurs in channel regions of the memory element TFTs. This enables... Agent: Nixon Peabody, LLP

20090090958 - Semiconductor constructions: Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern... Agent: Wells St. John P.s.

20090090961 - Non-volatile semiconductor memory device: A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the... Agent: The Marbury Law Group, PLLC

20090090959 - Non-volatile semiconductor storage device and method of manufacturing the same: A first lamination part includes: a charge accumulation layer provided on the respective sidewalls of laminated first conductive layers and accumulating charges; and a first semiconductor layer provided in contact with the fourth insulation layer and formed to extend to the lamination direction. A second lamination part includes a second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090090960 - Non-volatile semiconductor storage device and method of manufacturing the same: A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090090962 - Nonvolatile semiconductor memory and method of manufacturing the same: A nonvolatile semiconductor memory device includes: a semiconductor substrate; a first gate electrode formed on the semiconductor substrate through a gate insulating film; a second gate electrode formed in a side direction of the first gate electrode and electrically insulated from the first gate electrode; and an insulating film formed... Agent: Mcginn Intellectual Property Law Group, PLLC

20090090965 - Non-volatile semiconductor storage device and method of manufacturing the same: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090090964 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a device isolation insulating film which is buried in a semiconductor substrate, a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a source region and a drain region which are provided in the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090090963 - Semiconductor memory device and method of manufacturing the same: A plurality of memory cells each constituted of a memory cell transistor having a gate electrode in a laminated structure composed of a charge storage layer and a control gate layer and a select transistor having source/drain diffusion layers while one of the source/drain diffusion layers is shared by the... Agent: Foley And Lardner LLP Suite 500

20090090966 - High density fet with integrated schottky: A semiconductor structure includes a monolithically integrated trench FET and Schottky diode. The semiconductor structure further includes a plurality of trenches extending into a semiconductor region. A stack of gate and shield electrodes are disposed in each trench. Body regions extend over the semiconductor region between adjacent trenches, with a... Agent: Townsend And Townsend And Crew, LLP

20090090967 - Mosfet active area and edge termination area charge balance: A method for fabricating a MOSFET having an active area and an edge termination area is disclosed. The method includes forming a first plurality of implants at the bottom of trenches located in the active area and in the edge termination area. A second plurality of implants is formed at... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20090090968 - Semiconductor apparatus: A semiconductor apparatus includes: a semiconductor layer of a first conductivity type; a first main electrode provided on a frontside of the semiconductor layer; a second main electrode provided on a backside of the semiconductor layer, the backside being opposite to the frontside; a plurality of semiconductor regions of a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090090969 - Electronic device and method of biasing: A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first... Agent: Larson Newman Abel & Polansky, LLP

20090090970 - Soi substrate contact with extended silicide area: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of... Agent: Schmeiser, Olsen & Watts

20090090971 - Mosfet devices and methods for making them: A semiconductor device is disclosed. The device comprises a first MOSFET transistor. The transistor comprises a substrate, a first high-k dielectric layer upon the substrate, a first dielectric capping layer upon the first high-k dielectric, and a first gate electrode made of a semiconductor material of a first doping level... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20090090972 - Tunable voltage isolation ground to ground esd clamp: A tunable voltage isolation ground to ground ESD clamp is provided. The clamp includes a dual-direction silicon controlled rectifier (SCR) and trigger elements. The SCR is coupled between first and second grounds. The trigger elements are also coupled between the first and second grounds. Moreover, the trigger elements are configured... Agent: Fogg & Powers LLC

20090090973 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a device isolation insulating film which is provided in a semiconductor substrate, and an insulated-gate field-effect transistor which is disposed adjacent to the device isolation insulating film in a gate length direction, the insulated-gate field-effect transistor including a gate insulation film which is provided on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090090974 - Dual stress liner structure having substantially planar interface between liners and related method: A dual stress liner structure having a substantially planar interface between liners and a related method are disclosed. In one embodiment, a dual stress liner structure may include a tensile stress liner over an NFET, the NFET including a PFET adjacent thereto; and a compressive stress liner over the PFET,... Agent: Hoffman Warnick LLC

20090090975 - Integrated circuit system employing fluorine doping: An integrated circuit system that includes: providing a substrate including a first integrated circuit region electrically connected to a second integrated circuit region; implanting a dielectric growth material underneath a gate for each of an NFET device and a PFET device within the first integrated circuit region and the second... Agent: Law Offices Of Mikio Ishimaru

20090090976 - Process for integrating planar and non-planar cmos transistors on a bulk substrate and article made thereby: A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090090977 - Resistor and fet formed from the metal portion of a mosfet metal gate stack: An integrated semiconductor device includes a resistor and an FET device formed from a stack of layers. The stack of layers includes a dielectric layer formed on a substrate; a metal conductor layer having lower electrical resistance formed on the dielectric layer; and a polysilicon layer formed on the metal... Agent: International Business Machines Corporation Dept. 18g

20090090978 - Semiconductor device and method for fabricating the same: A high-voltage transistor and a peripheral circuit including a second conductivity type MOSFET are provided together on a first conductivity type semiconductor substrate. The high-voltage transistor includes: a low concentration drain region of a second conductivity type formed in the semiconductor substrate; a low concentration source region of a second... Agent: Mcdermott Will & Emery LLP

20090090980 - Asymmetric-ldd mos device: The present invention proposes a new asymmetric-lightly-doped drain (LDD) metal oxide semiconductor (MOS) transistor that is fully embedded in a CMOS logic. The radio frequency (RF) power performance of both conventional and asymmetric MOS transistor is measured and compared. The output power can be improved by 38% at peak power-added... Agent: Anthony R. Barkume

20090090979 - High performance mosfet: A semiconductor structure which exhibits high device performance and improved short channel effects is provided. In particular, the present invention provides a metal oxide semiconductor field effect transistor (MOFET) that includes a low dopant concentration within an inversion layer of the structure; the inversion layer is an epitaxial semiconductor layer... Agent: Scully, Scott, Murphy & Presser, P.C.

20090090981 - Semiconductor device: A semiconductor device which has a high dielectric strength and allows its on resistance to be made sufficiently small is provided. This semiconductor device comprises a first electroconducive-type semiconductor layer, and a gate electrode which is disposed on a given region of an insulation film formed on the main surface... Agent: Birch Stewart Kolasch & Birch

20090090982 - Ultra-abrupt semiconductor junction profile: The present invention discloses a method including: providing a substrate; forming recessed regions adjacent to both sides of a gate on the substrate; performing an angled co-implant of a species in two steps with two different energies and two different doses into the recessed regions; forming Silicon-Germanium in the recessed... Agent: Intel Corporation C/o Intellevate, LLC

20090090983 - Dual work function high voltage devices: A transistor has a substrate having a channel region and source and drain regions within the substrate on opposite sides of the channel region. The structure includes a gate oxide above the channel region of the substrate and a gate conductor above the gate oxide. The polysilicon gate conductor comprises... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090090984 - Novel method to increase breakdown voltage of semiconductor devices: Methods of achieving high breakdown voltages in semiconductor devices by suppressing the surface flashover using high dielectric strength insulating encapsulation material are generally described. In one embodiment of the present invention, surface flashover in AlGaN/GaN heterostructure field-effect transistors (HFETs) is suppressed by using high dielectric strength insulating encapsulation material. Surface... Agent: Dority & Manning, P.A.

20090090985 - Semiconductor device and method for fabricating the same: A semiconductor device includes a substrate having an active region and an isolation region, a gate pattern crossing both the active region and the isolation region of the substrate, and a protrusion having a surface higher than that of the substrate over at least an edge of the active region... Agent: Townsend And Townsend And Crew, LLP

20090090986 - Fully and uniformly silicided gate structure and method for forming same: Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep... Agent: International Business Machines Corporation Dept. 18g

20090090987 - Mems element, mems device and mems element manufacturing method: An MEMS element (A1) includes a substrate (1), and a first electrode (2) formed on the substrate (1). The MEMS element (A1) further includes a second electrode (3) including a movable portion (31) spaced from the first electrode (2) and facing the first electrode. The movable portion (31) is formed... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20090090989 - Image sensor and method of manufacturing the same: An image sensor and a manufacturing method thereof are provided. The image sensor can comprise: a semiconductor substrate, a first dielectric, a second dielectric pattern, a planarization layer, and a color filter. The semiconductor substrate comprises a photodiode. The first dielectric is disposed on the semiconductor substrate. The second dielectric... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090090988 - Solid state imaging device, method of manufacturing the same, and imaging apparatus: A solid state imaging device includes: a plurality of sensor sections formed in a semiconductor substrate in order to convert incident light into an electric signal; a peripheral circuit section formed in the semiconductor substrate so as to be positioned beside the sensor sections; and a layer having negative fixed... Agent: Sonnenschein Nath & Rosenthal LLP

20090090990 - Formation of nitrogen containing dielectric layers having an improved nitrogen distribution: Provided is a method for manufacturing a gate dielectric. This method, without limitation, includes subjecting a silicon substrate to a first plasma nitridation process to incorporate a nitrogen region therein. This method further includes growing a dielectric material layer over the nitrogen region using a nitrogen containing oxidizer gas, and... Agent: Texas Instruments Incorporated

20090090991 - Method for manufacturing semiconductor device: A semiconductor device is provided. The semiconductor device according to the present invention includes a semiconductor substrate, a second insulation layer, a buffer insulation layer adjacent to the second insulation layer, a third insulation layer and transistors. A high voltage device region and a low voltage device region are defined... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090090992 - Isolation trench structure for high electric strength: The invention relates to an isolation trench structure and a corresponding layout wherein the insulating properties of isolation trenches (10, 10′) in critical areas (at intersections and junctions) are improved. Flattened and/or rounded off corner areas (10a, 10b) of the semiconductor regions to be insulated are produced, the etching and... Agent: Stevens & Showalter LLP

20090090994 - Electromigration fuse and method of fabricating same: Fuses and methods of forming fuses. The fuse includes: a dielectric layer on a semiconductor substrate; a cathode stack on the dielectric layer, a sidewall of the cathode stack extending from a top surface of the cathode stack to a top surface of the dielectric layer; a continuous polysilicon layer... Agent: Schmeiser, Olsen & Watts

20090090993 - Single crystal fuse on air in bulk silicon: An integrated eFUSE device is formed by forming a silicon “floating beam” on air, whereupon the fusible portion of the eFUSE device resides. This beam extends between two larger, supporting terminal structures. “Undercutting” techniques are employed whereby a structure is formed atop a buried layer, and that buried layer is... Agent: International Business Machines Corporation Dept. 18g

20090090995 - On-chip inductors with through-silicon-via fence for q improvement: A semiconductor structure for providing isolations for on-chip inductors comprises a semiconductor substrate, one or more on-chip inductors formed above the first semiconductor substrate, a plurality of through-silicon-vias formed through the first semiconductor substrate in a vicinity of the one or more on-chip inductors, and one or more conductors coupling... Agent: K & L Gates LLP

20090090999 - High permittivity low leakage capacitor and energy storing device and method for forming the same: A method is provided for making a high permittivity dielectric material for use in capacitors. Several high permittivity materials in an organic nonconductive media with enhanced properties and methods for making the same are disclosed. A general method for the formation of thin films of some particular dielectric material is... Agent: Greenberg Traurig LLP (la)

20090090998 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a first and second structures formed in a first insulating layer, a lower metal interconnection formed in the second structure, a metal-insulator-metal (MIM) capacitor formed in the first structure, and first, second and third electrodes formed in the first structure and electrically connected to the MIM... Agent: Sherr & Vaughn, PLLC

20090090996 - Semiconductor device with contact stabilization between contact plugs and bit lines and method for manufacturing the same: A semiconductor device includes a semiconductor substrate divided into a cell array region, a core region, and a peripheral region. Bit lines are formed in the respective regions. Storage node contact plugs are formed in the cell array region, and blocking patterns are simultaneously formed around the bit lines of... Agent: Ladas & Parry LLP

20090090997 - Solid electrolytic capacitor element and production method thereof: The present invention relates to a production method of solid electrolytic capacitor element, comprising a step of forming a semiconductor layer on a surface of a conductor having a dielectric oxide film thereon and having an anode lead connected thereto by conducting electrolytic oxidation-polymerization using pyrrole dimer at around room... Agent: Sughrue Mion, PLLC

20090091000 - Varactores including interconnect layers: In an embodiment of the present invention is provided a varactor comprising a substrate, a plurality of bottom electrodes positioned on a surface of the substrate separated to form a gap therein, a tunable dielectric material positioned on the surface of the substrate and within the gap, the tunable dielectric... Agent: James S. Finn

20090091001 - Crack resistant semiconductor package and method of fabricating the same: There are provided a semiconductor package comprising: a semiconductor substrate including an integrated circuit unit, and a crack-propagation preventing unit at least partially formed around a peripheral of the integrated circuit unit of the semiconductor substrate and filled with a heterogeneous material different from a material of the semiconductor substrate,... Agent: Hosoon Lee

20090091002 - Methods for producing improved epitaxial materials: This invention provides methods for fabricating substantially continuous layers of group III nitride semiconductor materials having low defect densities. The methods include epitaxial growth of nucleation layers on a base substrate, thermally treatment of said nucleation layer and epitaxial growth of a discontinuous masking layer. The methods outlined promote defect... Agent: Winston & Strawn LLP Patent Department

20090091003 - Insulator undergoing abrupt metal-insulator transition, method of manufacturing the insulator, and device using the insulator: Provided are an insulator that has an energy band gap of 2 eV or more and undergoes an abrupt MIT without undergoing a structural change, a method of manufacturing the insulator, and a device using the insulator. The insulator is abruptly transitioned from an insulator phase into a metal phase... Agent: Townsend And Townsend And Crew, LLP

20090091004 - Semiconductor device: A semiconductor device according to one aspect of the present invention includes a semiconductor substrate, an interlayer insulating film formed over the semiconductor substrate, a metal wiring formed over the interlayer insulating film, a protective insulating film formed on the metal wiring, and a resin film formed within a region... Agent: Sughrue Mion, PLLC

20090091005 - Shielding structure for semiconductors and manufacturing method therefor: A shielding structure for semiconductor includes a semiconductor substrate, at least one active region defined on the semiconductor substrate, a protecting layer, a shielding layer, and a covering layer. The protecting layer, produced by a semiconductor process, is disposed on the surface of the active region. The shielding layer produced... Agent: Rosenberg, Klein & Lee

20090091006 - Dual capillary ic wirebonding: The invention discloses apparatus and methods for the formation of bond wires in integrated circuit assemblies by attaching two separate wires using a dual capillary bond head. The separate wires are preferably non-identical, for example, being of different gauges and/or material composition. According to a preferred embodiment of the invention,... Agent: Texas Instruments Incorporated

20090091008 - Semiconductor device: A semiconductor device for programmable logic or operation processing includes a semiconductor chip; a first connecting terminal for electrically connecting the semiconductor device to a printed circuit board on which the semiconductor device is to be mounted; a second connecting terminal for electrically connecting the semiconductor device to another semiconductor... Agent: Kubotera & Associates. LLC

20090091007 - Semiconductor device having grooved leads to confine solder wicking: A packaged surface-mount semiconductor device has the outer, un-encapsulated lead segments structured in five adjoining portions: The first portion protrudes from the encapsulation about horizontally; the second portion forms a convex bend downwardly; the third portion is approximately straight downwardly; the fourth portion forms a concave bend upwardly; and the... Agent: Texas Instruments Incorporated

20090091009 - Stackable integrated circuit package: A packaged integrated circuit device is disclosed which includes a leadframe comprising a die paddle and a plurality of lead fingers, a plurality of integrated circuit die positioned above the paddle in a stacked arrangement, a plurality of conductive structures for coupling each of the plurality of die to the... Agent: Perkins Coie LLP Patent-sea

20090091011 - Semiconductor device having interconnected contact groups: The present invention is related to a method of producing a semiconductor device and the resulting device. The method is suitable in the first place for producing high power devices, such as High Electron Mobility Transistors (HEMT), in particular HEMT-devices with multiples source-gate-drain groups or multiple base bipolar transistors. According... Agent: Knobbe Martens Olson & Bear LLP

20090091010 - Wireless semiconductor package for efficient heat dissipation: Disclosed in this specification is a wireless semiconductor package with multiple dies, at least two of which are attached to a thermally and electrically conductive heat sink. The package provides an efficient means for dissipating heat.... Agent: Hiscock & Barclay, LLP

20090091013 - Lead frame, electronic component including the lead frame, and manufacturing method thereof: A lead frame of the present invention includes: a die pad on which a device is mounted; a first connection terminal which is provided around the die pad, and the lower surface of which serves as an external terminal; a second connection terminal which is provided around the die pad... Agent: Greenblum & Bernstein, P.L.C

20090091012 - Thermoplastic resin composition for semiconductor, adhesion film, lead frame, and semiconductor device using the same, and method of producing semiconductor device: The object of the present invention is to provide an adhesion film for semiconductor that is capable of bonding a semiconductor chip to a lead frame tightly at an adhesion temperature lower than that of the adhesion film of a traditional polyimide resin without generation of voids and that can... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090091014 - Semiconductor device having a flexible printed circuit: To provide a thin film device which becomes possible to be formed in the portion which has been considered impossible to be provided with such device by the conventional technique, and to provide a semiconductor device which occupies small space and which has high shock resistance and flexibility, a device... Agent: Fish & Richardson P.C.

20090091015 - Stacked-type chip package structure and method of fabricating the same: A stacked-type chip package structure including a first package structure, a second package structure, and a first molding compound is provided. The first package structure includes a first substrate, and a first chip stacked thereon and electrically connected thereto. The second package structure is stacked on the first package structure,... Agent: J C Patents, Inc.

20090091016 - I/o pad structures for integrated circuit devices: A semiconductor device, including methods and arrangements for making the same, are described. The device includes an integrated circuit die having a plurality of bond pads. At least one bond pad on the active surface of the die is an extended I/O pad. Each extended I/O pad extends to at... Agent: Beyer Law Group LLP/ Nsc

20090091017 - Partitioned integrated circuit package with central clock driver: Disclosed are IC partitioned packaging and interconnection constructions that provide for improved distribution of power, ground, cross chip interconnections and clocks.... Agent: Tpl/interconnect Portfolio, LLC

20090091018 - Electronic component sealing substrate, electronic component sealing substrate to be divided into a plurality of pieces, electronic apparatus including electronic component sealing substrate, and method for producing electronic apparatus: An electronic component sealing substrate capable of configuring an electronic apparatus in which the influence of electromagnetic coupling and radio frequency noises between an electrical connection path and a micro electronic mechanical system is suppressed is provided. An electronic component sealing substrate (4) for hermetically sealing a micro electronic mechanical... Agent: Hogan & Hartson L.L.P.

20090091019 - Memory packages having stair step interconnection layers: Disclosed are IC package structures having stair stepped layers and which have no plated vias. Such structures can be fabricated either as discrete packages or as strips such as might be beneficial in for use with memory devices wherein critical or high speed signals can be routed along the length... Agent: Shemwell Mahamedi LLP

20090091020 - Co-fired ceramic module: A co-fired ceramic module includes a ceramic substrate and at least one heat-emitting device. The ceramic substrate has at least one high thermal conductivity material. The heat-emitting device is disposed on the ceramic substrate. The substrate further includes a cavity and the heat-emitting device is disposed in the cavity.... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090091021 - Semiconductor device and method of manufacturing the same: An insulating resin 4 is packed between a semiconductor chip 5 and a tape carrier 1, with taper portions 4a formed on the side faces, and a resin layer 7 is formed in close contact with the rear face of the semiconductor chip 5, the tape carrier 1, and the... Agent: Steptoe & Johnson LLP

20090091022 - Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device: A method for fabricating a device, a semiconductor chip package, and a semiconductor chip assembly is disclosed. One embodiment includes applying at least one semiconductor chip on a first form element. At least one element is applied on a second form element. A material is applied on the at least... Agent: Dicke, Billig & Czaja

20090091023 - Semiconductor device package: A semiconductor device package incorporating a connector that reduces manufacturing operations and enables efficient manufacturing. The semiconductor device package includes a primary molded product and a secondary molded product. The primary molded product includes a semiconductor device, a lead connected to the semiconductor device, and a plug terminal formed by... Agent: Crompton, Seager & Tufte, LLC

20090091025 - Method for forming and releasing interconnects: A method for forming and releasing interconnects by using a dummy substrate. The method comprises applying metallization to the dummy substrate for creating a relatively strong bond between the metallization and the dummy substrate and a weak bond between a first end of each of the interconnects and the metallization;... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090091031 - Semiconductor device: A semiconductor device comprises: a package substrate having a plurality of bonding electrodes arranged in a peripheral region of a main surface thereof and wirings connected to the respective bonding electrodes and electrolessly plated; a semiconductor chip mounted on the package substrate; a plurality of wires connecting pads of the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090091028 - Semiconductor device and method of bump formation: A semiconductor device including a semiconductor substrate, a contact pad, a passivation layer, a bump, and a seeding layer is provided. The semiconductor substrate has an active surface. The contact pad is disposed on the active surface. The passivation layer is disposed on the active surface and exposes a central... Agent: J C Patents, Inc.

20090091030 - Semiconductor device, method for mounting semiconductor device, and mounting structure of semiconductor device: In order to realize a semiconductor device which is easily mounted on a circuit board and which has high mounting reliability, a semiconductor device 1 of the present invention includes: a semiconductor substrate 2; and an Au bump 3 provided on an electrode 21. The Au bump 3 is provided... Agent: Nixon & Vanderhye, PC

20090091029 - Semiconductor package having marking layer: The symbolization of a semiconductor device (100) is incorporated in a thin sheet (130) attached to the top of the device, facing outwardly with its bare surface. The material of the sheet (about 1 to 10 μm thick) includes regions of a first optical reflectivity and a first color, and... Agent: Texas Instruments Incorporated

20090091027 - Semiconductor package having restraining ring surfaces against soldering crack: A semiconductor package with crack-restraining ring surfaces is revealed, primarily comprising a chip carrier, a chip disposed on the chip carrier, and a plurality of belfry-like bumps. The belfry-like bumps are disposed on a plurality of corresponding conductive pads on the bottom surface of the chip carrier as external terminals.... Agent: Joe Mckinney Muncy

20090091024 - Stable gold bump solder connections: A metallic interconnect structure (200) for connecting a gold bump (205) and a copper pad (212), as used for example in semiconductor flip-chip assembly. A first region (207) of binary AuSn2 intermetallic is adjacent to the gold bump. A region (208) of binary AuSn4 intermetallic is adjacent to the first... Agent: Texas Instruments Incorporated

20090091026 - Stackable semiconductor package having plural pillars per pad: A stackable semiconductor package is revealed, primarily comprising a chip carrier, a chip, and a plurality of bottom bump sets. The chip carrier has a plurality of stacking pads disposed on the top surface and a plurality of bump pads on the bottom surface. The chip is disposed on and... Agent: Joe Mckinney Muncy

20090091032 - Bond pad design for fine pitch wire bonding: A bonding pad design is disclosed that includes one or more pad groups on a semiconductor device. Each pad group is made up of two or more bonding pads that have an alternating orientation, such that adjacent bonding pads have their bond ball on opposite sides in relation to the... Agent: Slater & Matsil, L.L.P.

20090091033 - Fabrication of metal oxide films: A process of fabricating a metal oxide film includes depositing a multiphase, metal-based precursor film comprising the metal and an oxide of the metal on a substrate. The process further includes thermally growing a metal oxide film from the precursor film in a humid atmosphere for a predetermined period of... Agent: Benesch, Friedlander, Coplan & Aronoff LLP Attn:IPDepartment Docket Clerk

20090091034 - Driving circuit of a liquid crystal display panel: A driving circuit of a liquid crystal display panel includes a substrate, a plurality of driver IC chips located on the substrate, a current supplier, and a first conductive wire set. The first conductive wire set has a plurality of conductive wire segments for connecting the driver IC chips in... Agent: North America Intellectual Property Corporation

20090091035 - Highly integrated and reliable dram and its manufacture: A semiconductor device and its manufacture method wherein the semiconductor substrate has first and second insulating films, the first insulating film being an insulating film other than a silicon nitride film formed at least on a side wall of a conductive pattern including at least one layer of metal or... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090091036 - Wafer structure with a buffer layer: A wafer structure with a buffer layer is provided. The wafer structure comprises a wafer which has at least one pad formed thereon, a passivation layer formed on the wafer for partially exposing the at least one pad, a buffer layer formed on the passivation layer and the pad, and... Agent: Bacon & Thomas, PLLC

20090091038 - Air gap for interconnect application: The present disclosure provides a method for fabricating an integrated circuit. The method includes forming an energy removable film (ERF) on a substrate; forming a first dielectric layer on the ERF; patterning the ERF and first dielectric layer to form a trench in the ERF and the first dielectric layer;... Agent: Haynes And Boone, LLPIPSection

20090091037 - Methods for fabricating contacts to pillar structures in integrated circuits: A pillar structure that is contacted by a vertical contact is formed in an integrated circuit. A hard mask is formed and utilized to pattern a least a portion of the pillar structure. The hard mask comprises carbon. Subsequently, the hard mask is removed. A conductive material is then deposited... Agent: Ryan, Mason & Lewis, LLP

20090091040 - Semiconductor device and semiconductor storage device: A semiconductor storage device includes a memory cell transistor and a selective transistor formed on a semiconductor substrate, a first interlayer insulating film which is formed on the semiconductor substrate, an insulating layer formed by use of a material higher in dielectric constant than the first interlayer insulating film, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090091039 - Semiconductor device, method of manufacturing the same, and semiconductor substrate: According to the present invention, for collective molding of semiconductor devices, a semiconductor substrate includes first electrodes formed on the front side, second electrodes formed on the back side and connected to external electrode terminals, and a plurality of semiconductor element mounting regions 203. Along partition lines 202 for partitioning... Agent: Steptoe & Johnson LLP

20090091043 - Die offset die to die bonding: A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge... Agent: Paul J. Winters

20090091042 - Integrated circuit package system including die having relieved active region: An integrated circuit package system includes: providing a substrate; attaching a base die to the substrate, the base die having a relief region with a shaped cross-section; and connecting a bond wire between an active base surface of the base die and the substrate, the bond wire extending through the... Agent: Law Offices Of Mikio Ishimaru

20090091041 - Stacked type chip package structure and method of fabricating the same: A stacked type chip package structure including a package structure, a corresponding substrate, and a number of second bumps is provided. The package structure includes a first chip, a second chip, a number of first bumps, and a first underfill. The first chip is disposed above the second chip. The... Agent: J C Patents, Inc.

20090091044 - Dicing die attachment film and method for packaging semiconductor using same: A dicing die attachment film includes a die attachment layer attached to one surface of a semiconductor wafer; a dicing film layer attached to a dicing die that is used for cutting the semi-conductor wafer into die units; and an intermediate layer laminated between the die attachment layer and the... Agent: Stroock & Stroock & Lavan LLP

20090091045 - Themosetting composition for optical semiconductor, die bond material for optical semiconductor device, underfill material for optical semiconductor device, sealing agent for optical semiconductor device, and optical semiconductor device: d

20090085023 - Phase change memory structures: A phase change memory cell has a first electrode, a heater, a phase change material, and a second electrode. The heater is over the first electrode, and the heater comprises a pillar. The phase change material is around the heater. The second electrode is electrically coupled to the phase change... Agent: Freescale Semiconductor, Inc. Law Department

20090085025 - Memory device including resistance-changing function body: A resistance-changing function body includes an object made of a first substance and interposed between a first electrode and a second electrode, and a plurality of particles made of a second substance and arranged within the object so that an electrical resistance between the first electrode and the second electrode... Agent: Birch Stewart Kolasch & Birch

20090085024 - Phase change memory structures: A phase change memory cell has a first electrode, a plurality of pillars, and a second electrode. The plurality of pillars are electrically coupled with the first electrode. Each of the pillars comprises a phase change material portion and a heater material portion. The second electrode is electrically coupled to... Agent: Freescale Semiconductor, Inc. Law Department

20090085026 - Structure and method for manipulating spin quantum state through dipole polarization switching: Disclosed herein is a structure and method for manipulating a spin state, regarded as important in the field of spintronics, by which the distribution of spin-up and spin-down states of carriers in a hybrid double quantum disk structure, composed of a diluted magnetic semiconductor and a ferroelectric compound semiconductor, is... Agent: Sughrue Mion, PLLC

20090085027 - Three dimensional strained quantum wells and three dimensional strained surface channels by ge confinement method: The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first graded SiGe fin on a Si substrate. The first graded SiGe... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Intellevate, LLC

20090085028 - Hybrid matrices for thin-layer transistors: e

20090085029 - Photoelectric conversion element and imaging device: In the formula (I), X represents O, S or N—R10; Rx and Ry each independently represents a hydrogen atom or a substituent, at least one of Rx and Ry is an electron-withdrawing group, and Rx and Ry may be connected to each other to form a ring, provided that Rx... Agent: Sughrue-265550

20090085030 - Increased reliability for a contact structure to connect an active region with a polysilicon line: By forming a direct contact structure connecting, for instance, a polysilicon line with an active region on the basis of an increased amount of metal silicide by removing the sidewall spacers prior to the silicidation process, a significantly increased etch selectivity may be achieved during the contact etch stop layer... Agent: Williams, Morgan & Amerson

20090085031 - Wafer-shaped measuring apparatus and method for manufacturing the same: The present invention provides a temperature measuring apparatus with favorable temperature measuring performance and a method of manufacturing the same. A temperature measuring apparatus (10) provided with a temperature sensor (11) arranged on a bottom surface of a depressed section (12c) of a semiconductor wafer (12). The semiconductor wafer (12)... Agent: Masuvalley & Partners

20090085032 - Pixel structure and fabricating method thereof: A method of fabricating a pixel structure is provided. First, a semiconductor material layer and a first conductive layer are sequentially formed on a substrate. Next, a first patterned photoresist layer with a fillister is formed on the first conductive layer by a first mask. A semiconductor layer, a drain,... Agent: Jianq Chyun Intellectual Property Office

20090085034 - Thin film transistor array substrate: The present invention relates to a thin film transistor array substrate comprising a gate line and a data line that are separated by an insulting layer and intersecting each other to define a pixel, wherein a data auxiliary line is disposed adjacent to an intersection portion between the data line... Agent: Ladas & Parry

20090085033 - Thin film transistor, pixel structure and fabrication methods thereof: A thin film transistor including a gate, a gate insulator layer, a doped semiconductor layer, a channel layer, a source, and a drain is provided. The gate is disposed on a substrate, and the gate insulator layer is disposed on the substrate and covers the gate. The doped semiconductor layer... Agent: Jianq Chyun Intellectual Property Office

20090085035 - Method of producing a semiconductor element in a substrate and a semiconductor element: A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities and carbide precipitates in the substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, annealing the substrate such that at least a part... Agent: Slater & Matsil LLP

20090085036 - Light sensor: A light sensor includes an intrinsic layer, a first ion doping area disposed one side of the intrinsic layer, a second ion doping area disposed at the other side of the intrinsic layer, an oxide insulating layer on the intrinsic layer, and a gate metal on the oxide insulating layer.... Agent: Kirton And Mcconkie

20090085037 - Array substrate for liquid crystal display and method for fabricating the same: A method for fabricating an array substrate for a liquid crystal display (LCD) is provided. A semiconductor layer and a transparent lower electrode formed on a substrate is provided and covered by a first dielectric layer serving as a gate dielectric layer and a capacitor dielectric layer. A gate electrode... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090085039 - Image display system and fabrication method thereof: The invention provides a method for fabricating a low-temperature polysilicon (LTPS) driving circuit and thin film transistor. The method includes: providing a substrate, forming an active layer, forming a gate insulating layer, forming a dielectric layer having an extending portion and forming a gate electrode. The extending portion of the... Agent: Liu & Liu

20090085040 - Liquid crystal display device and fabricating method thereof: A thin film transistor substrate and a fabricating method simplify a process and enlarge a capacitance value of a storage capacitor without any reduction of aperture ratio. A transparent first conductive layer and an opaque second conductive layer of a double-layer structured gate line are formed having a step coverage.... Agent: Mckenna Long & Aldridge LLP

20090085038 - Substrate for display device, manufacturing method for same and display device: The present invention provides the substrate for a display device, comprising a scan line, a signal line and a switching element on an insulating substrate, and further comprising an interlayer insulation film and a pixel electrode, the switching element is provided at an intersection of the scan line and the... Agent: Sharp Kabushiki Kaisha C/o Keating & Bennett, LLP

20090085041 - Thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a thin film transistor including a gate electrode, a drain electrode, a source electrode and a semiconductor on a substrate; forming a first passivation layer on the drain and the source electrodes; forming a transparent... Agent: Cantor Colburn, LLP

20090085042 - Display device having thin film semiconductor device and manufacturing method of thin film semiconductor device: A display device having a thin film semiconductor device including a semiconductor thin film having first and second semiconductor regions formed each into a predetermined shape above an insulative substrate, a conductor fabricated into a predetermined shape to the semiconductor thin film and a dielectric film put between the semiconductor... Agent: Stanley P. Fisher Reed Smith LLP

20090085043 - Semiconductor light emitting device and method of manufacturing the same: Disclosed are a semiconductor light emitting device, which can improve characteristics of the semiconductor light emitting device such as a forward voltage characteristic and a turn-on voltage characteristic, increase light emission efficiency by lowering an input voltage, and increase reliability of the semiconductor light emitting device by a low-voltage operation,... Agent: Mcdermott Will & Emery LLP

20090085044 - Silicon carbide semiconductor substrate and silicon carbide semiconductor device by using thereof: A manufacturing method is provided for a silicon carbide semiconductor substrate adapted for reduced basal plane dislocations in a silicon carbide epitaxial layer. Between a silicon carbide epitaxial layer for device fabrication (i.e., a drift layer) and a base substrate formed of a silicon carbide single-crystal wafer, a highly efficient... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090085045 - Method for producing a matrix of individual electronic components and matrix produced thereby: The invention relates to a method for producing a matrix of electronic components, comprising a step of producing an active layer on a substrate, and a step of individualizing the components by forming trenches in the active layer at least until the substrate emerges. The method comprises steps of depositing... Agent: Burr & Brown

20090085046 - Methods and systems relating to solid state light sources for use in industrial processes: Methods and systems relating to solid state light sources for use in industrial processes.... Agent: Marger Johnson & Mccollom, P.C.

20090085048 - Ac light emitting diode: Disclosed is a light emitting diode (LED) operated by being directly connected to an AC power source. An AC LED according to the present invention comprises a plurality of light emitting cells two-dimensionally arranged on a single substrate; and wires electrically connecting the light emitting cells; wherein the light emitting... Agent: H.c. Park & Associates, PLC

20090085047 - Integrated multi-colored led light source with heatsink and collimator: A LED light source is integrated with a heatsink and a collimator. Four isolated heatsinks form an optical taper in which a single color LED is mounted. The LEDs are arranged to form a reflective light recycling cavity. Up to four different colors can be combined inside the light recycling... Agent: William Propp. Esq. Goldeneye, Inc.

20090085052 - Gan type light emitting diode device and method of manufacturing the same: L

20090085050 - Island submount and a method thereof: An island submount used for carrying at least one light-emitting element having at least one electrical contact. The island submount includes a substrate, at least one island structure having a top surface and an inclined surface, and a conductive layer. The island structure is located on the substrate and corresponds... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090085051 - Light emitting diode device: A light emitting diode device includes a light emitting diode chip, a thermal conducting part, two electric conducting parts and two first conducting wires. The light emitting diode chip has a surface and two electrodes disposed on the surface. The thermal conducting part is electrically insulated to the electrodes. The... Agent: Rosenberg, Klein & Lee

20090085049 - Phosphor down converting element for an led package and fabrication method: There is provided a phosphor down converting element based on fluoropolymer resin and a method for fabricating the same. There is further provided a method for using said phosphor down converting element to generate white light from a radiation source. The method for fabricating phosphor down converting element includes preparing... Agent: Fay Sharpe LLP

20090085053 - Light emitting diode package with large viewing angle: A light emitting diode package with large viewing angle includes a substrate, a LED chip, transparent housing body, and phosphor matrix. The substrate has an upper surface with a first electrode and a second electrode and a lower surface opposite to the upper surface. The LED chip with a positive... Agent: Pro-techtor International Services

20090085054 - Iii-nitride semiconductor light emitting device: The present disclosure relates to a III-nitride semiconductor light emitting device, and more particularly, to a III-nitride semiconductor light emitting device which can facilitate current spreading and improve electrostatic discharge characteristic by providing an undoped GaN layer with a thickness over 300 Å in an n-side contact layer.... Agent: Harness, Dickey, & Pierce, P.l.c

20090085057 - Iii-nitride semiconductor light emitting device: The present disclosure relates to a III-nitride semiconductor light emitting device, and more particularly, to a III-nitride semiconductor light emitting device which can facilitate current spreading and improve electrostatic discharge characteristic by providing an undoped GaN layer with a thickness over 100 Å in an n-side contact layer.... Agent: Harness, Dickey, & Pierce, P.l.c

20090085055 - Method for growing an epitaxial layer: A method for growing an epitaxial layer and devices obtained by that method are disclosed. The method starts by providing a growth substrate having a top surface characterized by a first thermal expansion coefficient (TEC). A mask having a plurality of openings therein is formed on the top surface of... Agent: The Law Offices Of Calvin B. Ward

20090085056 - Optical semiconductor device and method for fabricating the same: According to an aspect of the present invention, there is provided an optical semiconductor device, comprising, a first AlN clad-layer, a first nitride semiconductor guide-layer formed on the first AlN clad-layer, refractive index of the first nitride semiconductor guide-layer being larger than refractive index of the first AlN clad-layer, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090085058 - Electronic device including a magneto-resistive memory device and a process for forming the electronic device: A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include... Agent: Larson Newman Abel & Polansky, LLP

20090085059 - Semiconductor device including electrostatic discharge protection circuit: A SGPMOS transistor includes a base, a P-type diffusion layer, a gate electrode, and a LOCOS oxide film. The base includes at least one of a N-type semiconductor substrate, a P-type semiconductor substrate, and a N-type well. The P-type diffusion layer includes a P-type source and a P-type drain. At... Agent: Dickstein Shapiro LLP

20090085060 - Semiconductor device: In a high-voltage semiconductor switching element, in addition to a first emitter region that is necessary for switching operations, a second emitter region, which is electrically connected with the first emitter region through a detection resistor in current detection means and is electrically connected with the current detection means, is... Agent: Mcdermott Will & Emery LLP

20090085061 - High-voltage semiconductor switching element: In a base region of a first conductivity type, at least one emitter region of a second conductivity type and at least one sense region of the second conductivity type, spaced away from the emitter region, are selectively formed. The emitter region and the sense region are located so as... Agent: Mcdermott Will & Emery LLP

20090085062 - Method to introduce uniaxial strain in multigate nanoscale transistors by self aligned si to sige conversion processes and structures formed thereby: Methods of forming a microelectronic structure are described. Embodiments of those methods may include providing a gate electrode comprising a top surface and first and second laterally opposite sidewalls, wherein a hard mask is disposed on the top surface, a source drain region disposed on opposite sides of the gate... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090085063 - Compound semiconductor device with t-shaped gate electrode and its manufacture: A method for manufacturing a compound semiconductor device forms an EB resist layer on first SiN film, performs EB exposure at high dose for recess forming opening and at low dose for eaves removing opening, develops the high dose EB resist pattern to etch the first SiN film, selectively etches... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090085064 - Heterojunction semiconductor device and method: A semiconductor device includes a first semiconductor substrate of a first band-gap material and a second semiconductor substrate of a second band-gap material. The second band-gap material has a lower band-gap than the first band-gap material. A heterojunction is formed between the first semiconductor substrate and the second semiconductor substrate... Agent: Dicke, Billig & Czaja

20090085065 - Method to fabricate iii-n semiconductor devices on the n-face of layers which are grown in the iii-face direction using wafer bonding and substrate removal: A method for fabricating III-N semiconductor devices on the N-face of layers comprising (a) growing a III-nitride semiconductor device structure in a Ga-polar direction on a substrate, (b) attaching a Ga face of the III-nitride semiconductor device structure to a host substrate, and (c) removing the substrate to expose the... Agent: Gates & Cooper LLP Howard Hughes Center

20090085066 - Method for integrating high voltage and high speed bipolar transistors on a substrate and related structure: According to an exemplary embodiment, a method for integrating a high speed bipolar transistor in a high speed transistor region of a substrate with a high voltage transistor in a high voltage transistor region of the substrate includes forming a buried subcollector in the high speed transistor region of the... Agent: Farjami & Farjami LLP

20090085067 - Semiconductor device and layout design method therefor: A layout design method for a semiconductor device includes a step of arranging transistors, a dummy gate forming step of forming dummy gates, which has a shape identical with a shape including gate electrodes or the gate electrodes and projected parts from active regions of the gate electrodes, in positions... Agent: Mcdermott Will & Emery LLP

20090085068 - Semiconductor integrated circuit having output buffer circuit: Provided is a semiconductor integrated circuit capable of preventing switching noise due to on/off switching of an output buffer transistor from being transmitted to circuits other then the output buffer transistor via power supply lines, wells, and a substrate. A semiconductor integrated circuit according to the present invention includes: a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090085069 - Nand-type flash array with reduced inter-cell coupling resistance: In a NAND-type nonvolatile reprogrammable memory array, inter-cell coupling resistance between adjoining memory cells is reducing by forming metal silicide insets embedded in the diffusion zone of the inter-cell coupling region. The diffusion zone includes a shallow implant region and a deep implant region. In one embodiment, the shallow implant... Agent: Macpherson Kwok Chen & Heid LLP

20090085070 - Solid-state image pickup device, method of manufacturing solid-state image pickup device, and image pickup device: Disclosed herein is a solid-state image pickup device including, a plurality of light receiving units, a transfer channel, a first transfer electrode, a second transfer electrode, first wiring, and second wiring.... Agent: Rader Fishman & Grauer PLLC

20090085072 - Biosensor using nanoscale material as transistor channel and method of fabricating the same: Example embodiments relate to a biosensor using a nanoscale material as a channel of a transistor and a method of fabricating the same. A biosensor according to example embodiments may include a plurality of insulating films. A first signal line and a second signal line may be interposed between the... Agent: Harness, Dickey & Pierce, P.L.C

20090085071 - Sensor device comprising elongated nanostructures: A sensor device is provided for determining the presence and/or amount of at least one component in a fluid. The sensor device comprises at least one sensor unit, the at least one sensor unit comprising at least one elongated nanostructure and a dielectric material surrounding the at least one elongated... Agent: Knobbe Martens Olson & Bear LLP

20090085075 - Method of fabricating mos transistor and mos transistor fabricated thereby: A method of fabricating a MOS transistor, and a MOS transistor fabricated by the method. The method can include forming a gate pattern on a semiconductor substrate. The gate pattern can be formed by sequentially stacking a gate electrode and a capping layer pattern. The capping layer pattern is formed... Agent: Stanzione & Kim, LLP

20090085073 - Mosfet structure and method of manufacture: A method of forming a portion (10) of a compound semiconductor MOSFET structure comprises forming a compound semiconductor layer structure (14) and an oxide layer (20) overlying the same. Forming the compound semiconductor structure (14) includes forming at least one channel material (16) and a group-III rich surface termination layer... Agent: Freescale Semiconductor, Inc. Law Department

20090085074 - Trench mosfet and method of manufacture utilizing four masks: In accordance with the invention, a trench MOSFET semiconductor device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first mask to define openings for the trench gate and termination; utilizing a second mask as a source mask with... Agent: Hayes Soloway P.C.

20090085079 - Image sensor and method for manufacturing the same: An image sensor and method of manufacturing the same are disclosed. A semiconductor substrate can be prepared comprising a photodiode region, a transistor region, and a floating diffusion region. A gate dielectric can be disposed under a surface of the semiconductor substrate in the transistor region. A first dielectric pattern... Agent: Bong Bin Park

20090085080 - Image sensor and method for manufacturing the same: Disclosed is an image sensor. The image sensor includes a semiconductor substrate including unit pixels, an interlayer dielectric layer including metal interconnections formed on the semiconductor substrate, a plurality of bottom electrodes formed on the interlayer dielectric layer in correspondence with the unit pixels, the plurality of bottom electrodes includes... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090085078 - Image sensor and method of manufacturing the same: An image sensor includes a pixel array including a photodiode, a peripheral region including a logic circuit, and an isolation region formed between the pixel array and the peripheral region and formed under the peripheral region to electrically isolate the pixel array from the peripheral region.... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090085076 - Photo sensor and a method for manufacturing thereof: According to a method of manufacturing photo sensor, a diode can be formed by one lithography step. In addition, the source/drain is arranged on a gate dielectric layer to avoid the conventional plug structure. Moreover, a diode stack is formed on one of the source/drain to simplify the structure of... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090085077 - Photo sensor and a method for manufacturing thereof: A photo sensor has an insulator layer for covering a diode stack, and the insulator layer is made of phtoresist to reduce a side leakage current.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090085081 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device with high response speed and high reliability. In the method for manufacturing a semiconductor device of the invention, a bonding layer is formed over a substrate, an insulating film and a storage capacitor portion lower electrode are formed over the bonding layer, a... Agent: Eric Robinson

20090085082 - Controlled intermixing of hfo2 and zro2 dielectrics enabling higher dielectric constant and reduced gate leakage: Controlled deposition of HfO2 and ZrO2 dielectrics is generally described. In one example, a microelectronic apparatus includes a substrate and a dielectric film coupled with the substrate, the dielectric film including ZrO2 and HfO2 wherein the ratio of Zr to Hf in the dielectric film is about 5 to 10... Agent: Cool Patent, P.C. C/o Cpa Global

20090085083 - Semiconductor memory device and method of forming the same: Provided may be a semiconductor memory device and a method of forming the semiconductor memory device. The memory device of example embodiments may include a bit line structure including a bit line on a semiconductor substrate, and a buried contact plug structure including a buried contact pad and a buried... Agent: Harness, Dickey & Pierce, P.L.C

20090085085 - Dram cell with capacitor in the metal layer: A DRAM cell includes a substrate, a transistor, and a capacitor. The substrate is composed of semiconductor material with a main surface, the transistor is formed at the main surface, and the capacitor is formed in a metal layer. The transistor includes a source region and a drain region formed... Agent: Patterson & Sheridan, L.L.P.

20090085084 - Integrated circuit and methods of manufacturing the same: A method of manufacturing an integrated circuit includes forming landing pads in an array region of a substrate, individual ones of the landing pads being electrically coupled to individual ones of portions of devices formed in the substrate in the array region. The method also includes forming wiring lines within... Agent: Edell, Shapiro & Finnan, LLC

20090085086 - Capacitive electrode having semiconductor layers with an interface of separated grain boundaries: The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090085087 - Liner for tungsten/silicon dioxide interface in memory: A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard mask, whereby a plurality of sacrificial columns... Agent: Foley And Lardner LLP Suite 500

20090085088 - Semiconductor device and method of forming the same as well as data processing system including the semiconductor device: A semiconductor device includes low voltage and high voltage transistors over a substrate. The low voltage transistor is configured by at least one unit transistor. The high voltage transistor is configured by a greater number of the unit transistors than the at least one unit transistor that configures the low... Agent: Sughrue Mion, PLLC

20090085090 - Non-volatile semiconductor memory device having an erasing gate: A non-volatile semiconductor memory device includes a semiconductor substrate; a floating gate formed above the semiconductor substrate; an erasing gate formed above the floating gate; a control gate formed above a channel region of a surface layer of the semiconductor substrate at a position corresponding to one lateral side of... Agent: Mcginn Intellectual Property Law Group, PLLC

20090085091 - Non-volatile semiconductor memory device having an erasing gate: A non-volatile semiconductor memory device includes a floating gate formed above a semiconductor substrate; an erasing gate formed above the floating gate; a control gate formed above a channel region of a surface layer of the semiconductor substrate at a position corresponding to one lateral side of the floating gate... Agent: Mcginn Intellectual Property Law Group, PLLC

20090085092 - Non-volatile semiconductor memory device having an erasing gate: A non-volatile semiconductor memory device includes: a floating gate formed above the semiconductor substrate; an erasing gate formed above the floating gate; a control gate formed above a channel region of a surface layer of the semiconductor substrate at a position corresponding to one lateral side of the floating gate... Agent: Mcginn Intellectual Property Law Group, PLLC

20090085093 - Semiconductor devices and method of fabricating the same: A semiconductor device and a fabricating method thereof are provided. The semiconductor device fabricating method includes forming a nitride layer pattern over a semiconductor substrate, forming a trench by etching the semiconductor substrate using the nitride layer pattern as a mask, forming a first insulation layer over an entire face... Agent: Sherr & Vaughn, PLLC

20090085089 - Two-bit flash memory: A flash memory includes a substrate with a protrusion, a control gate, two floating gates, and a dielectric layer. The protrusion extends from a top face of the substrate. The control gate is formed on the protrusion of the substrate and extendedly covers opposite sidewalls of the protrusion. The floating... Agent: Jianq Chyun Intellectual Property Office

20090085094 - Floating gate having multiple charge storing layers, method of fabricating the floating gate, non-volatile memory device using the same, and fabricating method thereof: Provided is a floating gate having multiple charge storing layers, a non-volatile memory device using the same, and a method of fabricating the floating gate and the non-volatile memory device, in which the multiple charge storing layers using metal nano-crystals of nano size is formed to thereby enhance a charge... Agent: Rosenberg, Klein & Lee

20090085095 - Profile engineered thin film devices and structures: The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090085096 - Nonvolatile memory devices and methods of forming the same: Provided are nonvolatile memory devices and methods of forming nonvolatile memory devices. Nonvolatile memory devices include a device isolation layer that defines an active region in a substrate. Nonvolatile memory devices further include a first insulating layer, a nonconductive charge storage pattern, a second insulating layer and a control gate... Agent: Myers Bigel Sibley & Sajovec

20090085097 - Methods of forming nitride stressing layer for replacement metal gate and structures formed thereby: Methods and associated structures of forming a microelectronic device are described. Those methods may include removing residual dielectric material from a metal gate structure, and then forming a stress relief layer on a top surface and on a sidewall region of the metal gate structure. A stress is introduced into... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090085098 - Semiconductor device including vertical mos transistors: A semiconductor device includes: a plurality of vertical MOS transistors sharing a gate electrode (2) of a first conductivity type; first semiconductor pillars (3, 4 and 5) with a gate insulating film (18) formed therearound, across the gate insulating film (18) the vertical MOS transistors facing the gate electrode; and... Agent: Sughrue Mion, PLLC

20090085101 - Lateral power mosfet with high breakdown voltage and low on-resistance: A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and... Agent: Slater & Matsil, L.L.P.

20090085100 - Semiconductor device: A super-junction semiconductor substrate is configured in such a manner that an n-type semiconductor layer of a parallel pn structure is opposed to a boundary region between an active area and a peripheral breakdown-resistant structure area. A high-concentration region is formed at the center between p-type semiconductor layers that are... Agent: Rossi, Kimms & Mcdowell LLP.

20090085099 - Trench mosfet and method of manufacture utilizing three masks: In accordance with the invention a vertical power trench MOSFET semiconductor device comprises P+ body and N+ source diffusions shorted together to prevent second breakdown caused by a parasitic bipolar transistor. The device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon... Agent: Hayes Soloway P.C.

20090085102 - Semiconductor device having vertical surrounding gate transistor structure, method for manufacturing the same, and data processing system: A semiconductor device is provided which includes: semiconductor pillars which include impurity diffused layers, each semiconductor pillar having a width which allows full depletion of a semiconductor forming each semiconductor pillar, the impurity diffused layers being electrically connected to each other; and a common gate section which covers side faces... Agent: Sughrue Mion, PLLC

20090085103 - Semiconductor device and method: A semiconductor device and production method is disclosed. In one embodiment, the semiconductor device includes a first electrode and a second electrode, located on surfaces of a semiconductor body, and an insulated gate electrode. The semiconductor body has a contact groove for the first electrode in an intermediate oxide layer.... Agent: Dicke, Billig & Czaja

20090085104 - Semiconductor device and method for manufacturing: A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a first surface and a second surface which is arranged opposite to the first surface. The semiconductor substrate includes a plurality of trench structures extending from the first surface into the semiconductor substrate. The thickness of the... Agent: Dicke, Billig & Czaja

20090085106 - Semiconductor device and semiconductor device manufacturing method: A semiconductor device having a low on resistance and high integration level with respect to the surface area of a substrate is provided. In the semiconductor device, a first trench, a second trench, and a third trench are provided in an element formation region provided on a semiconductor substrate. Metal... Agent: Rabin & Berdo, PC

20090085105 - Trench mosfet and method of manufacture utilizing two masks: A method for manufacturing a trench MOSFET semiconductor device comprises: providing a heavily doped N+ silicon substrate; forming an N type epitaxial layer; forming a thick SiO2 layer; creating P body and source area formations by ion implantation without any masks; utilizing a first mask to define openings for a... Agent: Hayes Soloway P.C.

20090085107 - Trench mosfet with thick bottom oxide tub: A semiconductor power device includes a plurality of trenched gates. The trenched gates include a thin dielectric layer padded sidewalls of the trenched gate and a tub-shaped thick dielectric layer below a bottom of the trenched gates having a width narrower than the trenched gate. In an exemplary embodiment, the... Agent: Bo-in Lin

20090085109 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type; a body region of a second conductivity type formed in a surface layer portion of the semiconductor layer; a trench dug from the surface of the semiconductor layer to penetrate the body region;... Agent: Rabin & Berdo, PC

20090085108 - Semiconductor device having cell transistor with recess channel structure: The present invention provides a semiconductor device comprising: a dual-gate peripheral transistor having a transistor structure of surface channel nMOSFET and a transistor structure of surface channel pMOSFET; and a cell transistor having an nMOSFET structure with a recess channel structure, a gate electrode of the cell transistor having an... Agent: Mcdermott Will & Emery LLP

20090085110 - Semiconductor device employing precipitates for increased channel stress: A method for fabricating a semiconductor device including implanting a selected material at a desired target depth below a surface of a silicon substrate, performing an annealing process to create a band of precipitates formed from the selected material and the silicon of the silicon substrate at the desired target... Agent: Dicke, Billig & Czaja

20090085111 - Semiconductor device and method of manufacturing the same: Provided is a semiconductor device and a method of manufacturing a semiconductor device. In the semiconductor device, high-concentration n type impurity regions are formed respectively below gate electrodes. By setting a gate length to be smaller than a depth of channel regions, pn junction interfaces formed of adjacent side faces... Agent: Morrison & Foerster LLP

20090085112 - Lateral diffusion metal-oxide-semiconductor structure: A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semiconductor substrate to form a recess. As... Agent: Wpat, PC Intellectual Property Attorneys

20090085113 - Semiconductor device: A semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type; an annular deep trench penetrating the semiconductor layer in the depth direction to surround an element forming region; a drain region of a second conductivity type formed in a surface layer portion of... Agent: Rabin & Berdo, PC

20090085114 - Semiconductor structure: A semiconductor structure includes a substrate, an undoped GaP insulating layer formed over the substrate, and a semiconductor layer formed over the GaP layer.... Agent: Infineon Technologies Ag Patent Department

20090085115 - Transistor and in-situ fabrication process: A method of fabricating semiconductor components in-situ and in a continuous integrated sequence includes the steps of providing a single crystal semiconductor substrate, epitaxially growing a first layer of rare earth insulator material on the semiconductor substrate, epitaxially growing a first layer of semiconductor material on the first layer of... Agent: Robert A. Parsons

20090085116 - Semiconductor device and method of manufacturing the same: A semiconductor device 1 includes a first semiconductor region 2B and a second semiconductor region 5 provided on a main surface of a substrate 2, being apart from each other and having first conductivity; a third semiconductor region 4 provided between the first semiconductor region 2B and the second semiconductor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090085117 - Level shift circuit and semiconductor device thereof: A level shift circuit and a semiconductor device are configured to prevent failure and malfunction even when an excessive negative voltage or ESD surge are applied to a high-voltage power supply terminal. The level shift circuit includes a level shift resistor, a current-limiting resistor connected in series to the level... Agent: Rossi, Kimms & Mcdowell LLP.

20090085119 - Double-gate transistor structure equipped with a multi-branch channel: a second gate electrode, separate from the first gate and situated on another side of the structure against the opposite sides of the rods, the semi-conductor rods and one or several insulating rods situated between the semi-conductor rods, separating the first gate electrode and the second gate electrode.... Agent: Pearne & Gordon LLP

20090085118 - Semiconductor memory device: A semiconductor memory device includes a first active region formed having a first portion extending laterally and second portion extendedly vertically upward from a central portion of the first portion; a second active region formed spaced from the first active region, the second active region having a third portion extending... Agent: Sherr & Vaughn, PLLC

20090085121 - Condensed memory cell structure using a finfet: An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element. The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET including a source, a drain,... Agent: Slater & Matsil, L.L.P.

20090085120 - Method for reduction of resist poisoning in via-first trench-last dual damascene process: Fabrication of interconnects in integrated circuits (ICs) use low-k dielectric materials, nitrogen containing dielectric materials, copper metal lines, dual damascene processing and amplified photoresists to build features smaller than 100 nm. Regions of an IC with low via density are subject to nitrogen diffusion from nitrogen containing dielectric materials into... Agent: Texas Instruments Incorporated

20090085125 - Mos transistor and cmos transistor having strained channel epi layer and methods of fabricating the transistors: Provided are a metal oxide semiconductor (MOS) transistor and a complementary MOS (CMOS) transistor each having a strained channel epi layer, and methods of fabricating the transistors. The MOS transistor may include at least one active region defined by an isolation structure formed in a substrate. At least one channel... Agent: Harness, Dickey & Pierce, P.L.C

20090085122 - Poly profile engineering to modulate spacer induced stress for device enhancement: The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due... Agent: Shimokaji & Associates, P.C.

20090085123 - Semiconductor device and method for fabricating the same: A semiconductor device comprises a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first sidewall formed on a side surface of a first gate electrode, and including a first inner sidewall having an L-shaped cross-section and a first outer sidewall. The second MIS transistor... Agent: Mcdermott Will & Emery LLP

20090085124 - Semiconductor storage device and manufacturing method of the same: A semiconductor storage device includes: a storage circuit, an access control circuit, a ground voltage supplying region, and a polysilicon portion. The storage circuit stores data. The access control circuit includes a first access transistor and a second access transistor and controls reading and writing of the data. The ground... Agent: Mcginn Intellectual Property Law Group, PLLC

20090085126 - Hybrid metal fully silicided (fusi) gate: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the... Agent: Slater & Matsil, L.L.P.

20090085127 - Non-volatile semiconductor memory based on enhanced gate oxide breakdown: A semiconductor memory structure based on gate oxide break down is constructed in a deep N-well. Thus, the electrical field over the programmable element during the transient procedure of gate oxide break down can be controlled to achieve the best memory programming results. The conductivity of the programmed memory cell... Agent: Perkins Coie LLP Patent-sea

20090085128 - Semiconductor device and method for manufacturing same: A semiconductor device includes a semiconductor substrate including a plurality of device regions and a device isolation region defining the device regions, and a semiconductor element located in a major surface of the semiconductor substrate and formed in at least one of the device regions. The device isolation region has... Agent: Amin, Turocy & Calvin, LLP

20090085129 - Defect-free source/drain extensions for mosfets having germanium based channel regions: A process for forming defect-free source and drain extensions for a MOSFET built on a germanium based channel region deposits a first silicon germanium layer on a semiconductor substrate, deposits a gate dielectric layer on the silicon germanium layer, and deposits a gate electrode layer on the gate dielectric layer.... Agent: Intel Corporation C/o Intellevate, LLC

20090085130 - Semiconductor device: The present invention relates to a semiconductor device comprising a semiconductor substrate (1), a gate insulator formed on this substrate, such as a gate oxide film (2), and a gate electrode (3) formed on the insulator. The gate electrode (3) has a metallic compound film (3a). This metallic compound film... Agent: Smith, Gambrell & Russell

20090085131 - Semiconductor device and manufacturing method thereof: The semiconductor device includes: a semiconductor substrate; a diffusion layer provided in the semiconductor substrate; a gate insulation film provided on the semiconductor substrate; a gate electrode provided on the gate insulation film; and a Ni silicide layer selectively provided on the diffusion layer, and a metal cap film having... Agent: Young & Thompson

20090085132 - Mram cell structure with a blocking layer for avoiding short circuits: A MRAM cell structure includes a bottom electrode; a magnetic tunnel junction unit disposed on the bottom electrode; a top electrode disposed on the magnetic tunnel junction unit; and a blocking layer disposed on the top electrode, wherein the blocking layer is wider than the magnetic tunnel junction unit for... Agent: K & L Gates LLP

20090085133 - On chip antenna and method of manufacturing the same: An antenna with air-filled trench is integrated with a radio frequency (RF) circuit. The trench locates directly under the metal lines that made up the antenna and is formed by etching from the back side of the semiconductor substrate until all the substrate material in the trench is removed. The... Agent: My The Doan

20090085135 - Image sensor and manufacturing method thereof: Provided are embodiments of an image sensor. The image sensor can comprise a first substrate including a transistor circuit, a lower interconnection layer, an upper interconnection layer, and a second substrate including a vertical stacked photodiode. The lower interconnection layer is disposed on the first substrate and comprises a lower... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090085136 - Image sensor and method for manufacturing the same: An image sensor and method of manufacturing the same are provided. The image sensor can comprise a photodiode region an interlayer dielectric, and a microlens. The interlayer dielectric can have a trench over the photodiode region, and the microlens can be disposed in the trench such that the microlens fills... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090085137 - Solid-state imaging device: In a solid-state imaging device of the present invention, light-sensitive elements 54, each of which includes a light receiving section capable of receiving light, are arranged in a matrix form at regular spacings in a photoreceiving region provided on a semiconductor substrate 51. A plurality of detecting electrodes 53 are... Agent: Mcdermott Will & Emery LLP

20090085134 - Wafer-level image sensor module, method of manufacturing the same, and camera module: Provided is a wafer-level image sensor module including a wafer; an image sensor mounted on the wafer; a transparent member installed above the top surface of the wafer so as to seal the image sensor; a plurality of vias formed in the wafer so as to be positioned outside the... Agent: Staas & Halsey LLP

20090085138 - Glass cap molding package, manufacturing method thereof and camera module: In order to achieve the object, the present invention provides a glass cap molding package including a substrate with an external connection terminal formed on a peripheral region of a top surface; an image sensor mounted on the top surface of the substrate; a transparent member installed on an upper... Agent: Lowe Hauptman Ham & Berner, LLP

20090085139 - Solid-state image sensing device and method for manufacturing the same: A solid-state image sensing element includes an effective pixel section in a central area of a light receiving surface thereof, and a ridge-shaped protruding portion is provided around the effective pixel section. A liquid transparent adhesive is applied on the effective pixel section, and a light transparent substrate is placed... Agent: Mcdermott Will & Emery LLP

20090085140 - Finger type photodiode and method of manufacturing the same: Provided are a finger type photodiode and a method of manufacturing the same, which can reduce noise by forming a shallow doping layer. The finger type photodiode includes a bottom substrate supporting layers to be formed thereon, an epitaxial layer formed on the bottom substrate, a finger doping layer formed... Agent: Lowe Hauptman Ham & Berner, LLP

20090085141 - Pixel matrix with compensation of ohmic drops on the power supplies: o

20090085142 - Solid-state imaging device and method for fabricating same: A solid-state imaging device includes a plurality of pixels two-dimensionally arrayed in a well region disposed on a semiconductor substrate, each pixel including a photoelectric conversion section having a charge accumulation region which accumulates signal charge; an element isolation layer which is disposed on the surface of the well region... Agent: Robert J. Depke Lewis T. Steadman

20090085143 -