Active solid-state devices (e.g., transistors, solid-state diodes) inventions 03/09

20090078924 - Phase change memory with various grain sizes: A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The... Agent: Slater & Matsil, L.L.P.

20090078926 - Phase change memory device and fabrication method thereof: A phase change memory device comprising an electrode, a phase change layer crossing and contacting the electrode at a cross region thereof, and a transistor comprising a source and a drain, wherein the drain of the transistor electrically connects the electrode or the phase change layer is disclosed.... Agent: Quintero Law Office, PC

20090078925 - Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of alternating tin chalcogenide and metal layers proximate thereto. The method of forming the device comprises sputtering the alternating tin chalcogenide and metal layers.... Agent: Dickstein Shapiro LLP

20090078927 - Composite hard mask for the etching of nanometer size magnetic multilayer based device: A composite hard mask is disclosed that enables sub-100 nm sized MTJ cells to be formed for advanced devices such as spin torque MRAMs. The hard mask has a lower non-magnetic metallic layer such as Ru to magnetically isolate an overlying middle metallic spacer such as MnPt from an underlying... Agent: Saile Ackerman LLC

20090078928 - Light-emitting element, light-emitting device, and information display device: A light-emitting device has a structure in which a semiconductor or a conductive substrate having a bottom electrode, a layer for generating hot electrons, quasi-ballistic electrons or ballistic electrons, a luminous layer, and a semitransparent surface electrode are deposited, or a structure in which a holes supply layer is provided... Agent: Wenderoth, Lind & Ponack, L.L.P.

20090078929 - Nanowire device and method of making a nanowire device: A method of making nanowires includes providing a silicon substrate having a silicon dioxide insulation on the surface thereof. The silicon dioxide is etched to form one or more pillars, each having a plurality of sidewalls. A thin film of gold is deposited on a sidewall and is subjected to... Agent: Nasa Goddard Space Flight Center

20090078930 - Quantum device, manufacturing method of the same and controlling method of the same: By bringing a tip of an AFM into contact with the surface of a GaAs substrate or an AlGaAs substrate, for example, applying a negative bias to the tip, and applying a positive bias to the GaAs substrate or the AlGaAs substrate, a donut-shaped oxide film is formed. Then, the... Agent: Kratz, Quintos & Hanson, LLP

20090078932 - Systems, devices, and methods for controllably coupling qubits: A coupling system may include first and second magnetic flux inductors communicatively coupled to a Josephson junction of an rf SQUID. The coupling system may allow transverse coupling between qubits. A superconducting processor may include at least one of the coupling systems and two or more qubits. A method may... Agent: Seed Intellectual Property Law Group PLLC

20090078931 - Systems, methods, and apparatus for qubit state readout: A superconducting readout system includes a computation qubit; a measurement device to measure a state of the computation qubit; and a latch qubit that mediates communicative coupling between the computation qubit and the measurement device. The latch qubit includes a qubit loop that includes at least two superconducting inductors coupled... Agent: Seed Intellectual Property Law Group PLLC

20090078933 - Organic light emitting device: An organic light emitting device includes a first electrode disposed on a substrate, a plurality of organic function layers disposed on the first electrode and comprising an emitting layer, and a second electrode disposed on the organic function layers. One of the organic layers includes an inorganic material. This layer... Agent: Ked & Associates, LLP

20090078934 - Zinc oxide based compound semiconductor light emitting device: There is provided a semiconductor light emitting device in which light emitting efficiency is totally improved in case of emitting a light having a short wavelength of 400 nm or less by raising internal quantum efficiency by enhancing crystallinity of semiconductor layers laminated and by raising external quantum efficiency by... Agent: Rabin & Berdo, PC

20090078935 - Semiconductor device: Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly... Agent: Mcdermott Will & Emery LLP

20090078936 - Semiconductor device: A PIN diode includes an anode electrode, a P layer, an I layer, an N layer and a cathode electrode. A polysilicon film is formed in a region near the pn junction or n+n junction where the density of carriers implanted in a forward bias state is relatively high, as... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090078939 - Display device and method for manufacturing the same: To provide a display device which can realize high performance of a field-effect transistor which forms a pixel of the display device and which can achieve improvement in an aperture ratio of a pixel, which has been reduced due to increase in the number of field-effect transistors, and reduction in... Agent: Eric Robinson

20090078938 - Electrophoretic display device and method for manufacturing thereof: It is an object to provide an electrophoretic display device having a thin film transistor which has highly reliable electric characteristics, lightweight, and flexibility. A gate insulating film is formed over a gate electrode, a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate... Agent: Eric Robinson

20090078937 - Production methods of pattern thin films, semiconductor element, and circuit substrate, and resist material, semiconductor element, and circuit substrate: The present invention provides production methods of a pattern thin film, a semiconductor element and a circuit substrate, capable of eliminating the number of photolithography processes needed for patterning; and a semiconductor element, a circuit substrate, and an electron device obtained by the production methods. The production method of the... Agent: Birch Stewart Kolasch & Birch

20090078940 - Location-controlled crystal seeding: A structure with location-controlled crystallization of an active semiconductor film using a crystal seed has been provided, along with an associated fabrication method. The method forms a first semiconductor film overlying a substrate having a crystallographic orientation. Typically, the structure is polycrystalline or single-crystal. The first semiconductor film is selectively... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20090078941 - Backplane structures for solution processed electronic devices: There is provided a backplane for an organic electronic device. The backplane has a TFT substrate; a multiplicity of electrode structures; and a bank structure defining a multiplicity of pixel openings on the electrode structures. The bank structure has a height adjacent to the pixel opening, hA, and a height... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20090078943 - Nitride semiconductor device and manufacturing method thereof: A nitride semiconductor device mainly made of a nitride semiconductor material having excellent heat dissipation characteristics and great crystallinity and a method for manufacturing thereof are provided. The method for manufacturing the nitride semiconductor includes vapor-depositing a diamond layer on a silicon substrate, bonding an SOI substrate on a surface... Agent: Greenblum & Bernstein, P.L.C

20090078942 - Semiconductor device and method of manufacturing the same: A semiconductor device includes an SiC substrate, a first SiC layer of first conductivity provided on the substrate, a second SiC layer of second conductivity provided on the first SiC layer, first and second SiC regions provided in the second SiC layer, facing each other and having the same depth,... Agent: Charles N.j. Ruggiero, Esq. Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20090078944 - Light emitting device and method of manufacturing the same: This semiconductor light emitting device includes an optical cavity made of a group III nitride semiconductor having a major growth surface defined by a nonpolar plane and including a pair of cavity end faces parallel to c-planes, and a reflecting portion made of a group III nitride semiconductor having a... Agent: Rabin & Berdo, PC

20090078945 - Light emitting device: A light emitting device is provided that includes a substrate having a thin film transistor, and an insulation film disposed over the substrate and having a via hole to expose the thin film transistor. The light emitting device further includes a first electrode over the insulation film and connecting with... Agent: Ked & Associates, LLP

20090078946 - Light emitting device: A light emitting device is disclosed. The light emitting device includes a substrate including a thin film transistor, an insulating film disposed over the thin film transistor, a first electrode disposed over the thin film transistor and connected to the thin film transistor, a function layer including at least one... Agent: Ked & Associates, LLP

20090078947 - Semiconductor light emitting device: An end face emission type semiconductor light emitting device which include: a substrate; a first conductive type clad layer stacked on the substrate; an active region layer including an active layer stacked on the first conductive type clad layer; a second conductive type clad layer stacked on the active region... Agent: Sughrue Mion, PLLC

20090078951 - Gallium nitride-based compound semiconductor light-emitting device: The inventive gallium nitride-based compound semiconductor light-emitting device has a gallium nitride-based compound semiconductor layer structure comprising an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer, on a substrate, wherein a positive electrode provided on the p-type semiconductor layer is a reflective positive electrode comprising a transparent... Agent: Sughrue Mion, PLLC

20090078948 - Illuminator and method for producing such illuminator: The present invention relates to an illuminator (10) comprising a substrate (12), a structured conductive layer (16) applied to one surface of the substrate, and at least one light source (18, 26) connected to the structured conductive layer. The illuminator is characterized in that it further comprises an unstructured reflective... Agent: Philips Intellectual Property & Standards

20090078957 - Light emitting device: A light emitting device includes a board, a semiconductor light emitting element formed on the board optionally via a submount, a cap sealing the semiconductor light emitting element and a reflector provided surrounding the cap. The cap has top and bottom surfaces that are parallel to the top surface of... Agent: Sughrue Mion, PLLC

20090078949 - Light emitting device with conversion structure: The invention relates to a light-emitting device comprising a conversion structure and one or several LEDs (40), which emit light into the conversion structure. The light is then converted and emitted with a high radiant flux.... Agent: Philips Intellectual Property & Standards

20090078953 - Light emitting diode package structure: The present invention provides a light emitting diode (LED) package, which includes a carrier substrate having a first surface and a second surface; a metal layer formed in the first surface of the carrier substrate, and a through hole formed in the central area of the metal layer to expose... Agent: Sinorica, LLC

20090078952 - Light-emitting chip device with high thermal conductivity: This invention provides a light-emitting chip device with high thermal conductivity, which includes an epitaxial chip, an electrode disposed on a top surface of the epitaxial chip and a U-shaped electrode base cooperating with the electrode to provide electric energy to the epitaxial chip for generating light by electric-optical effect.... Agent: Macpherson Kwok Chen & Heid LLP

20090078955 - Micro-emitter array based full-color micro-display: Disclosed is a semiconductor micro-emitter array for use in a full-color microdisplay. Each pixel includes three vertically-stacked red, green, and blue micro-emitters which minimizes pixel size. The microdisplay may be exclusively based on Group III-nitride semiconductors, with differing indium concentrations in three respective InGaN/GaN active regions for emitting the three... Agent: Lathrop & Gage Lc

20090078956 - Package structure of photoelectronic device and fabricating method thereof: A package structure for photoelectronic devices comprises a silicon substrate, a first insulating layer, a reflective layer, a second insulating layer, a first conductive layer, a second conductive layer and a die. The silicon substrate has a first surface and a second surface, wherein the first surface is opposed to... Agent: Wpat, PC Intellectual Property Attorneys

20090078950 - Package structure with replaceable element for light emitting diode: A package structure for an LED is disclosed. The structure includes a first substrate, an LED chip, a second substrate, a protection layer and a replaceable optical element. The LED chip is disposed on the first substrate. The second substrate is disposed on the first substrate, and surrounds the LED... Agent: Rosenberg, Klein & Lee

20090078954 - Semiconductor light emitting device and method for manufacturing the same: Disclosed is a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises a first conductive semiconductor layer comprising a first concave-convex pattern, a second concave-convex pattern on at least one pattern of the first concave-convex pattern, an active layer on the first... Agent: Birch Stewart Kolasch & Birch

20090078958 - Assembly of a heat dissipating base and a lead frame for a light emitting diode packaging device and method for making the same: A light emitting diode packaging device includes: a heat dissipating base; a light emitting dice mounted on the heat dissipating base; a lead frame coupled electrically to the light emitting dice and having a protruding wall defining a confining space for extension of a protruding part of the heat dissipating... Agent: Rosenberg, Klein & Lee

20090078959 - Solid-state optical device: A solid-state optical device includes a solid-state element, a power supplying/retrieving portion on which the solid-state element is mounted, the power supplying/retrieving portion supplying or retrieving electric power to/from the solid-state element, and a glass sealing material that seals the solid-state element. The glass sealing material has a thermal expansion... Agent: Mcginn Intellectual Property Law Group, PLLC

20090078960 - Light emitting diode with auxiliary electric component: An exemplary LED includes a substrate, an LED chip, a light pervious encapsulation, and an auxiliary electric component. The substrate includes a first surface, an opposite second surface, and an accommodating space defined therein between the first surface and the second surface. The LED chip is mounted on the first... Agent: PCe Industry, Inc. Att. Steven Reiss

20090078961 - Nitride-based light emitting device: The present invention relates to a nitride-based light emitting device having a buffer layer, an n-type nitride semiconductor layer, an active layer and a p-type semiconductor layer sequentially formed on a substrate, wherein an Al1-xSixN interlayer is formed inside of the n-type nitride semiconductor layer. Accordingly, threading dislocation generated from... Agent: H.c. Park & Associates, PLC

20090078962 - Adjustable field effect rectifier: An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference.... Agent: Law Offices Of James E. Eakin

20090078963 - Nano-optoelectronic chip structure and method: The present invention relates to integrated structures of III-V and Silicon materials for making optoelectronic devices on chip compatible with complimentary metal oxide semiconductor (CMOS). As a result, various light generation, detection, switching, modulation, filtering, multiplexing, signal manipulation and beam splitting devices could be fabricated in semiconductor material such as... Agent: Salah Khodja

20090078964 - Enhancement mode iii-nitride semiconductor device with reduced electric field between the gate and the drain: An enhancement mode III-nitride heterojunction device that includes a region between the gate and the drain electrode thereof that is at the same potential as the source electrode thereof when the device is operating.... Agent: Ostrolenk Faber Gerb & Soffen

20090078965 - Individually controlled multiple iii-nitride half bridges: A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die.... Agent: Ostrolenk Faber Gerb & Soffen

20090078966 - Field-effect transistor, semiconductor chip and semiconductor device: A FET exhibiting excellent uniformity and productivity and having a low noise figure and high associated gain as high-frequency performance, a semiconductor chip having this FET and a semiconductor device having the semiconductor chip. The FET includes a GaAs substrate on which are built up an i-type GaAs layer, an... Agent: Mcginn Intellectual Property Law Group, PLLC

20090078967 - Semiconductor chip and semiconductor device having a plurality of semiconductor chips: The present invention comprises a semiconductor chip, and a semiconductor device having a plurality of semiconductor chips, that enables ESD protection from another semiconductor chip without increasing the chip area in case the semiconductor chip is Multi-Chip-Packaged, without wasting chip area in case the semiconductor chip is not Multi-Chip-Packaged. The... Agent: Taft, Stettinius & Hollister LLP

20090078968 - Integrated circuit device and method for forming the same: In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connected to each of the element ground lines... Agent: Mcdermott Will & Emery LLP

20090078969 - Solid-state imaging device, imaging apparatus, and method of manufacturing solid-state imaging device: A solid-state imaging device includes: a semiconductor substrate; photoelectric conversion elements; vertical charge transfer paths that transfer charges generated in photoelectric conversion elements, in a vertical direction; a horizontal charge transfer path that transfers the charges transferred in vertical charge transfer paths, in a horizontal direction orthogonal to the vertical... Agent: Birch Stewart Kolasch & Birch

20090078970 - Semiconductor device: A semiconductor device is demonstrated in which a plurality of field-effect transistors is stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. Each of the plurality of filed-effect transistors has a semiconductor layer which is prepared by a process including separation of the semiconductor... Agent: Eric Robinson

20090078971 - Semiconductor device with structured current spread region and method: A semiconductor device with structured current spread region and method is disclosed. One embodiment provides a drift portion of a first conductivity type, a current spread portion of the first conductivity type and first portions of the first conductivity type. The current spread portion and the first portions are arranged... Agent: Dicke, Billig & Czaja

20090078972 - Sensor thin film transistor, thin film transistor substrate having the same, and method of manufacturing the same: A sensor thin film transistor includes a gate electrode, a gate insulation layer formed on the gate electrode, a semiconductor layer having a portion positioned above the gate electrode and on a side of the gate insulation layer opposite the gate electrode, and a source electrode and drain electrode having... Agent: Macpherson Kwok Chen & Heid LLP

20090078975 - Cmos image sensor: There is provided a CMOS image sensor including: a photodiode receiving light to generate photogenerated charges; a transmission gate unit transmitting the photogenerated charges generated by the photodiode to a first floating diffusion area, and increasing the capacitance of the first floating diffusion area; a transfer transistor transferring the photogenerated... Agent: Staas & Halsey LLP

20090078973 - Image sensor element for backside-illuminated sensor: Provides is a backside-illuminated sensor including a semiconductor substrate having a front surface and a back surface. A plurality of image sensor elements are formed on the front surface of the semiconductor substrate. At least one of the image sensor elements includes a transfer transistor and a photodetector. The gate... Agent: Haynes And Boone, LLPIPSection

20090078978 - Image sensor having a charge storage region provided within an implant region: A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface leakage and dark current and... Agent: Dickstein Shapiro LLP

20090078974 - Solid-state image capturing device; manufacturing method for the solid-state image capturing device; and electronic information device: A solid-state image capturing device is provided with a plurality of light receiving elements arranged on a surface section of a semiconductor substrate, a color filter of each color for each of the plurality of light receiving elements, and a plurality of microlenses each for condensing incident light into each... Agent: Edwards Angell Palmer & Dodge LLP

20090078976 - Solid-state imaging device and method for manufacturing thereof as well as driving method of solid-state imaging device: A solid-state imaging device with a structure such that an electrode for reading a signal charge is provided on one side of a light-receiving sensor portion constituting a pixel; a predetermined voltage signal V is applied to a light-shielding film formed to cover an image pickup area except the light-receiving... Agent: Sonnenschein Nath & Rosenthal LLP

20090078977 - Solid-state imaging device and method for manufacturing thereof as well as driving method of solid-state imaging device: A solid-state imaging device with a structure such that an electrode for reading a signal charge is provided on one side of a light-receiving sensor portion constituting a pixel; a predetermined voltage signal V is applied to a light-shielding film formed to cover an image pickup area except the light-receiving... Agent: Sonnenschein Nath & Rosenthal LLP

20090078979 - Semiconductor device and method of manufacturing the same: A semiconductor device includes: a semiconductor substrate and a transistor formed on the semiconductor substrate. The semiconductor device also includes: a first interlayer insulation film formed on the semiconductor substrate including the upper portion of the transistor, a first contact formed to be connected through the first interlayer insulation film... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090078980 - Method for producing an integrated circuit, integrated circuit, dram device and memory module: A method for producing an integrated circuit is disclosed. The integrated circuit includes an insulating material and a semiconducting material adjacent the insulating material. The semiconducting material is partially removed and the surface of the partially removed semiconducting material is treated. The insulating material is partially removed.... Agent: Slater & Matsil, L.L.P.

20090078981 - Semiconductor memory device and manufacturing method therefor: A semiconductor memory device in which a plurality of capacitors each including a columnar lower electrode, a capacitor insulation film and an upper electrode are stacked with interlayer films therebetween, a contact plug connects an upper face of each lower electrode of a lower layer with a bottom face of... Agent: Scully Scott Murphy & Presser, PC

20090078982 - Alpha hydroxy carboxylic acid etchants for silicon microstructures: α-Hydroxy carboxylic acid etchants for silicon microstructures are generally described. In one example, a method includes fabricating a protruding structure on a semiconductor substrate, the protruding structure comprising a first layer of silicon coupled with the semiconductor substrate, the first layer of silicon defining a bottom gate, a sacrificial layer... Agent: Cool Patent, P.C. C/o Cpa Global

20090078983 - Non-volatile semiconductor memory device and method of manufacturing the same: A MONOS type non-volatile semiconductor memory device which is capable of electrically writing, erasing, reading and retaining data, the memory device including source/drain regions, a first gate insulating layer, a first charge trapping layer formed on the first gate insulating layer, a second gate insulating layer formed on the first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090078984 - Semiconductor apparatus and method for manufacturing the same: According to an aspect of the present invention, there is provided a semiconductor apparatus including: a semiconductor substrate; a gate dielectric film that is formed on the semiconductor substrate; a floating gate electrode film that is formed on the gate dielectric film; an inter-gate dielectric film that includes: a metal... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090078985 - Semiconductor integrated circuit device and a method of manufacturing the same: The memory cell transistor includes, in a first well region, a pair of memory electrodes, one of which serves as source electrode and the other serves as drain electrode and a channel region interposed between the pair of memory electrodes. There is, on a channel region, a first gate electrode... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090078986 - Manufacturing method for an integrated circuit including different types of gate stacks, corresponding intermediate integrated circuit structure and corresponding integrated circuit: The present invention provides a manufacturing method for an integrated circuit and a corresponding integrated circuit. The integrated circuit comprises a plurality of first devices, each first device including a charge storage layer and a control electrode comprising a plurality of layers; and a plurality of second devices coupled to... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090078989 - Method of forming silicon nitride at low temperature, charge trap memory device including crystalline nano dots formed by using the same, and method of manufacturing the charge trap memory device: Provided are a method of forming silicon nitride at a low temperature, a charge trap memory device including crystalline nano dots formed by using the same, and a method of manufacturing the charge trap memory device. The method of forming silicon nitride includes loading a substrate into a chamber of... Agent: Harness, Dickey & Pierce, P.L.C

20090078987 - Programmable element and manufacturing method of semiconductor device: In one aspect of the present invention, a programmable element, may include a semiconductor substrate, source/drain layers formed apart from each other in the upper surface of the semiconductor substrate, a gate insulating film including a charge-trapping film containing Hf and formed on a portion between the source/drain layers of... Agent: Gregory Turocy Amin, Turocy & Calvin, LLP

20090078988 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a protection target element formed on a semiconductor substrate and includes a protection target element electrode, a substrate connecting part including a substrate connecting electrode electrically connected to the semiconductor substrate and a fuse structure provided between the protection target element electrode and the substrate connecting... Agent: Mcdermott Will & Emery LLP

20090078990 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090078991 - Stress enhanced semiconductor device and methods for fabricating same: A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20090078992 - Semiconductor device and a method of manufacturing the same: In the present invention, an npn junction is formed by circularly forming a p− type impurity region and n+ type impurity regions on a same single-crystalline substrate as a MOS transistor. Multiple npn junctions are formed apart from each other in concentric circular patterns. With this configuration, steep breakdown characteristics... Agent: Morrison & Foerster LLP

20090078993 - Semiconductor device with reduced gate-overlap capacitance and method of forming the same: A semiconductor device includes a vertically extending semiconductor portion above a semiconductor substrate, first and second diffusion regions being disposed near the bottom and top portions of the vertically extending semiconductor portion, respectively. A gate insulating film extends along the side surface of the vertically extending semiconductor portion which is... Agent: Young & Thompson

20090078994 - Semiconductor device and method for fabricating the same: Disclosed is a semiconductor device having an n-type drain region, a low concentration p-type body region formed on the n-type drain region, an n-type source region formed on the low concentration p-type body region, a high concentration p-type body region formed on the low concentration p-type body region, a gate... Agent: Mcdermott Will & Emery LLP

20090078995 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device includes a first conductivity type layer of a first conductivity type, a body layer of a second conductivity type formed on the first conductivity type layer, a gate trench passing through the body layer so that the deepest portion thereof reaches the first conductivity type layer, a... Agent: Rabin & Berdo, PC

20090078996 - Semiconductor device: A semiconductor device according to the present invention includes: an insulating layer; a semiconductor layer of a first conductive type laminated on the insulating layer; an annular deep trench having a thickness reaching the insulating layer from a top surface of the semiconductor layer; a body region of a second... Agent: Rabin & Berdo, PC

20090078997 - Dual metal gate finfets with single or dual high-k gate dielectric: A first high-k gate dielectric layer and a first metal gate layer are formed on first and second semiconductor fins. A first metal gate ring is formed on the first semiconductor fin. In one embodiment, the first high-k gate dielectric layer remains on the second semiconductor fin. A second metal... Agent: Scully, Scott, Murphy & Presser, P.C.

20090078998 - Semiconductor device having decreased contact resistance: Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20090078999 - Semiconductor device structures with floating body charge storage and methods for forming such semiconductor device structures.: Semiconductor device structures including a semiconductor body that is partially depleted to define a floating charge-neutral region supplying a floating body for charge storage and methods for forming such semiconductor device structures. The width of the semiconductor body is modulated so that different sections of the body have different widths.... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090079000 - Semiconductor device: An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel... Agent: Eric Robinson

20090079001 - Multi-channel esd device and method therefor: In one embodiment, an ESD device is configured to include a zener diode and a P-N diode.... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20090079002 - Superjunction structures for power devices and methods of manufacture: A power device includes an active region and a termination region surrounding the active region. A plurality of pillars of first and second conductivity type are alternately arranged in each of the active and termination regions. The pillars of first conductivity type in the active and termination regions have substantially... Agent: Townsend And Townsend And Crew, LLP

20090079003 - Method for protecting circuits from damage due to currents and voltages during manufacture: A protection circuit network includes one or more protection devices, used to protect one or more devices in an integrated circuit (IC) design. The protection devices are globally coupled together, for connection to an internal or external power supply. During manufacture of the IC, the protection circuit network protects the... Agent: Wallace W. Lin

20090079004 - Method for making a transistor with self-aligned double gates by reducing gate patterns: This invention relates to an improved microelectronic method for making a double gate structure for a transistor, and particularly gate patterns (108a,128a,208a,228a,308a,328a) with a critical dimension less than the critical dimension of the transistor channel zone (104b). This method particularly includes a step to reduce double gate patterns, using isotropic... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090079005 - Integrated circuits and methods of design and manufacture thereof: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are... Agent: Slater & Matsil LLP

20090079006 - Semiconductor apparatus: A semiconductor apparatus includes: a semiconductor device including a semiconductor layer, a first metal main electrode provided on the semiconductor layer and having a first region and a second region, and a metal gate interconnect provided on the semiconductor layer and insulated from and interposed between the first region and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090079007 - Semiconductor device and manufacturing method thereof: The present invention can prevent occurrence of an off-leak current in the NMISFETs formed over the Si (110) substrate and having a silicided source/drain region. The semiconductor device includes N channel MISFETs (Metal Insulator Semiconductor Field Effect Transistors) which are formed over a semiconductor substrate having a main surface with... Agent: Miles & Stockbridge PC

20090079008 - Cmos fabrication process: Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD... Agent: Texas Instruments Incorporated

20090079009 - Memory device, memory circuit and semiconductor integrated circuit having variable resistance: A first variable resistor (5) is connected between a first terminal (7) and a third terminal (9) and increases/reduces its resistance value in accordance with the polarity of a pulse voltage applied between the first terminal (7) and the third terminal (9). A second variable resistor (6) is connected between... Agent: Mcdermott Will & Emery LLP

20090079010 - Nickel silicide formation for semiconductor components: Semiconductor components are often fabricated that include a nickel silicide layer, e.g., as part of a gate electrode in a transistor component, which may be formed by forming a layer of nickel on a silicon-containing area of the semiconductor substrate, followed by thermally annealing the semiconductor substrate to produce a... Agent: Texas Instruments Incorporated

20090079011 - Method and structure for improving device performance variation in dual stress liner technology: A method and semiconductor structure that overcome the dual stress liner boundary problem, without significantly increasing the overall size of the integrated circuit, are provided. In accordance with the present invention, the dual stress liner boundary or gap therebetween is forced to land on a neighboring dummy gate region. By... Agent: Scully, Scott, Murphy & Presser, P.C.

20090079012 - Semiconductor device and method of fabricating the same: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a plurality of active regions which are defined in a semiconductor substrate, a plurality of gate lines which are formed as zigzag lines, extend across the active regions, are symmetrically arranged, and define a... Agent: F. Chau & Associates, LLC

20090079013 - Mos transistor and method for manufacturing the transistor: A MOS transistor and a method for manufacturing the transistor are disclosed. The method for manufacturing the MOS transistor may include successively stacking a pad oxide layer and a mask layer on a semiconductor substrate, patterning the pad oxide layer and the mask layer, to expose a trench forming region... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090079014 - Transistors with high-k dielectric spacer liner to mitigate lateral oxide encroachment: Embodiments of the invention generally relate to transistors with high-k dielectric spacer liner to mitigate lateral oxide encroachment. In this regard a semiconductor device is introduced having a substrate, a high-k gate dielectric layer on the substrate, a metal gate electrode on the high-k gate dielectric layer, and a high-k... Agent: Intel Corporation C/o Intellevate, LLC

20090079015 - Lanthanide dielectric with controlled interfaces: Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on... Agent: Brooks, Cameron & Huebsch , PLLC

20090079016 - Method for forming a dielectric stack: The present invention provides a method for fabricating a dielectric stack in an integrated circuit comprising the steps of (i) forming a high-k dielectric layer on a semiconductor substrate, (ii) subjecting the semiconductor substrate with the high-k dielectric layer to a nitrogen comprising vapor phase reactant and silicon comprising vapor... Agent: Knobbe Martens Olson & Bear LLP

20090079017 - Semiconductor device having multiple substrates: A semiconductor device includes a first substrate including first, second and third layers; and a second substrate including fourth, fifth and sixth layers. The first substrate provides an electric device. The second substrate provides a physical quantity sensor. The first layer of the first substrate and the fourth layer of... Agent: Posz Law Group, PLC

20090079018 - Magnetoresistive element and magnetic memory: A magnetoresistive element includes a first underlying layer having an NaCl structure and containing a nitride orienting in a (001) plane, a first magnetic layer provided on the first underlying layer, having magnetic anisotropy perpendicular to a film surface, having an L10 structure, and containing a ferromagnetic alloy orienting in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090079020 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate having a first surface in which a light-receiving portion and electrodes are provided. The semiconductor substrate has a penetrating wiring layer connecting the first surface and the second surface. A light-transmissive protective member is disposed on the semiconductor substrate so as to cover... Agent: Amin, Turocy & Calvin, LLP

20090079019 - Solid-state image capturing device, solid-state image capturing apparatus, and electronic information device: A solid-state image capturing device is provided. In the solid-state image capturing device, at least any of openings of electrode wiring layers, color filters and microlenses are provided on a light incident side above light receiving elements as a light receiving region in which the plurality of light receiving elements... Agent: Edwards Angell Palmer & Dodge LLP

20090079021 - Low ohmic through substrate interconnection for semiconductor carriers: It is described a low ohmic Through Wafer Interconnection (TWI) for electronic chips formed on a semiconductor substrate (600). The TWI comprises a first connection extending between a front surface and a back surface of the substrate (600). The first connection (610) comprises a through hole filled with a low... Agent: Philips Intellectual Property & Standards

20090079022 - Method of forming low capacitance esd device and structure therefor: In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20090079023 - Method of fabricating an integrated circuit with stress enhancement: A method of fabricating an integrated circuit including arranging a plurality of cells to form a desired floor plan of the integrated circuit, wherein each cell comprises at least one transistor, forming a plurality of circuit constituents from the plurality of cells of the floor plan, wherein each circuit constituent... Agent: Dicke, Billig & Czaja

20090079024 - Semiconductor device and method for manufacturing the same: To provide a method for manufacturing a large-area semiconductor device, to provide a method for manufacturing a semiconductor device with high efficiency, and to provide a highly-reliable semiconductor device in the case of using a large-area substrate including an impurity element. A plurality of single crystal semiconductor substrates are concurrently... Agent: Eric Robinson

20090079025 - Substrate provided with semiconductor films and manufacturing method thereof: A plurality of single crystal semiconductor substrates having a rectangular shape are disposed on a tray. Depression portions are provided in the tray so that the single crystal semiconductor substrates can fit in. The single crystal semiconductor substrates disposed on the tray are doped with hydrogen ions, so that damaged... Agent: Eric Robinson

20090079026 - Stress-generating structure for semiconductor-on-insulator devices: A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing... Agent: Scully, Scott, Murphy & Presser, P.C.

20090079027 - Shallow trench isolation structure compatible with soi embedded dram: A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that... Agent: Scully, Scott, Murphy & Presser, P.C.

20090079028 - Semiconductor device having fuse with protection capacitor: A semiconductor device has a fuse, an internal circuit and a protection capacitor. The fuse has a first terminal connected to be applied to a fixed voltage and a second terminal. The internal circuit includes a transistor. The transistor has a threshold voltage and a gate. The protection capacitor is... Agent: Rabin & Berdo, PC

20090079029 - Capacitor structure and fabricating method thereof: A capacitor structure including a substrate, a butting conductive layer, a second dielectric layer, a plurality of openings, a bottom electrode layer, a capacitor dielectric layer, a top electrode layer, and a second metal interconnect layer is provided. The substrate has a first dielectric layer and a first metal interconnect... Agent: J C Patents, Inc.

20090079030 - Forming soi trench memory with single-sided buried strap: A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask... Agent: Cantor Colburn LLP - IBM Fishkill

20090079031 - Method and device with improved base access resistance for npn bipolar transistor: A configuration composed of multiple short emitters still share common DTI regions and a single big piece of base poly. This allows for base current to flow in 4 directions (e.g., 2 dimensions) as opposed to only two. This significantly reduces the base resistance of the transistor that is crucial... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090079032 - Method of forming a high capacitance diode and structure therefor: In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20090079033 - Lateral junction varactor with large tuning range: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the... Agent: HorizonIPPte Ltd

20090079036 - Gallium nitride baseplate and epitaxial substrate: A method of forming an iron-doped gallium nitride for a semi-insulating GaN substrate is provided. A substrate (1), such as a (0001)-cut sapphire substrate, is placed on a susceptor of a metalorganic hydrogen chloride vapor phase apparatus (11). Next, gaseous iron compound GFe from a source (13) for an iron... Agent: Judge Patent Associates

20090079035 - Non-polar iii-v nitride material and production method: A method for growing flat, low defect density, and strain-free thick non-polar III-V nitride materials and devices on any suitable foreign substrates using a fabricated nano-pores and nano-network compliant layer with an HVPE, MOCVD, and integrated HVPE/MOCVD growth process in a manner that minimum growth will occur in the nano-pores... Agent: Kauth , Pomeroy , Peck & Bailey ,llp

20090079034 - Non-polar iii-v nitride semiconductor and growth method: A method for growing flat, low defect density, and strain-free thick non-polar III-V nitride materials and devices on any suitable foreign substrates using a fabricated nanocolumns compliant layer with an HVPE growth process is provided. The method uses a combination of dry and wet etching to create nanocolumns consisting of... Agent: Kauth , Pomeroy , Peck & Bailey ,llp

20090079037 - Micromechanical component and method for producing a micromechanical component: A micromechanical component, in particular a micromechanical sensor, having a first wafer and a second wafer is provided, the first wafer having at least one structural element, and the second wafer having at least one mating structural element, and, in addition, the structural element and the mating structural element are... Agent: Kenyon & Kenyon LLP

20090079038 - Method of making an integrated circuit including singulating a semiconductor wafer: A method of making an integrated circuit includes providing a semiconductor wafer having a first surface and a second surface opposite the first surface, at least one of the first surface and the second surface including a metallization layer deposited onto the surface. The method additionally includes forming a first... Agent: Dicke, Billig & Czaja

20090079039 - Semiconductor device, method for manufacturing semiconductor device, and method for designing manufacturing semiconductor device: A semiconductor device includes a semiconductor chip, a moisture resistant ring provided in the semiconductor chip and having a chamfered flat part in a position corresponding to a corner of the semiconductor chip, and a first monitor pattern formed inside the moisture resistant ring. At least a part of the... Agent: Staas & Halsey LLP

20090079040 - Semiconductor structure with coincident lattice interlayer: A semiconductor structure consistent with certain implementations has a crystalline substrate oriented with a {111} plane surface that is within 10 degrees of surface normal. An epitaxially grown electrically insulating interlayer overlays the crystalline substrate and establishes a coincident lattice that mates with the surface symmetry of the {111} plane... Agent: Miller Patent Services

20090079041 - Semiconductor package and method of reducing electromagnetic interference between devices: A wafer level semiconductor package has a substrate and an RF module and baseband module coupled to the substrate with solder bumps. An underfill material is disposed under the RF module and baseband module. A first shielding layer is applied to a first surface of the substrate. A seed layer... Agent: Quarles & Brady LLP

20090079042 - Center conductor to integrated circuit for high frequency applications: A microcircuit has a node thereon. A center conductor is electrically connected to the node and the center conductor has a length to minimum radius ratio of at least 50. A method of for providing electrical interconnections in a microcircuit, comprises the steps of depositing conductive bumps on the microcircuit;... Agent: Agilent Technologies Inc.

20090079045 - Package structure and manufacturing method thereof: A quad-flat non-leaded (QFN) multichip package and a multichip package are provided. The QFN multichip package includes a lead frame, a first chip, a second chip and a molding compound. The lead frame has a plurality of first leads and second leads alternately arranged with each other. Each first lead... Agent: Bacon & Thomas, PLLC

20090079043 - Semiconductor device and method of manufacturing the same: Provided is a semiconductor device including a semiconductor chip, a film (first film) which is provided so as to cover an active region with a peripheral portion of the semiconductor chip being uncovered, and is made of a dielectric material having a low dielectric constant, and a package molding resin... Agent: Young & Thompson

20090079044 - Semiconductor package and manufacturing method thereof: A semiconductor package includes a lead frame, at least one chip, and an encapsulation. The lead frame has a plurality of leads, and each of the leads includes at least one first conductive part, at least one second conductive part, and at least one third conductive part. The first conductive... Agent: J C Patents, Inc.

20090079046 - Semiconductor package and method for manufacturing the same: A semiconductor package includes a semiconductor device having a first main surface and a second main surface, a first electrode plate provided on the first main surface, a second electrode plate provided on the second main surface, and a wiring substrate provided between the semiconductor device and the first electrode... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090079047 - Cof package and tape substrate used in same: The present invention provides a COF package which comprises a tape substrate including a plurality of external input terminals and a plurality of external output terminals provided in a chip non-mounting area, a plurality of input wirings connected to the external input terminals respectively, a plurality of output wirings connected... Agent: Volentine & Whitt PLLC

20090079048 - Integrated circuit package system with under paddle leadfingers: An integrated circuit package system is provided including: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing the bottom... Agent: Law Offices Of Mikio Ishimaru

20090079050 - Air cavity package for flip-chip: According to an example embodiment, there is method (100) for manufacturing a semiconductor device in an air-cavity package. For a device die having an active surface, a lead frame is provided (5), the lead frame has a top-side surface and an under-side surface, the lead frame has predetermined pad landings... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090079049 - Integrated circuit package system with warp-free chip: An integrated circuit package system includes: providing an integrated circuit wafer having an active side and a backside; forming a stress-relieving layer on the backside; forming an adhesion layer on the stress-relieving layer; dicing the integrated circuit wafer into a semiconductor chip with the stress-relieving layer and the adhesion layer... Agent: Law Offices Of Mikio Ishimaru

20090079051 - Semiconductor device and manufacturing method of the same: The outflow of die bond material is prevented and the quality and the reliability of a semiconductor device are improved. A tab, a plurality of leads arranged around the tab, silver paste arranged on the chip supporting surface of the tab, and a semiconductor chip mounted via silver paste on... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090079052 - Semiconductor package, apparatus and method for manufacturing the semiconductor package, and electronic device equipped with the semiconductor package: Provided is a semiconductor package which includes a substrate that includes a chip region having an active surface and an inactive surface, and a dicing region having an active surface and an inactive surface; connection terminals disposed on the active surface that belongs to the chip region; a first molding... Agent: Mills & Onello LLP

20090079053 - Tape substrate and semiconductor module for smart card, method of fabricating the same, and smart card: Provided are a tape substrate for a smart card, a method of fabricating the same, and a semiconductor module and a smart card using the tape substrate. The tape substrate includes at least one tape unit. The at least one tape unit includes a chip mounting unit defining a region... Agent: Marger Johnson & Mccollom, P.C.

20090079054 - Semiconductor device, structure of mounting the same, and method of removing foreign matter from the same: A semiconductor device includes a package defining an enclosed inner space, a semiconductor chip having a movable portion on one side and housed in the closed inner space of the package, and a catching member located in the closed inner space of the package to catch and hold a foreign... Agent: Posz Law Group, PLC

20090079055 - Method and structure of expanding, upgrading, or fixing multi-chip package: Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090079056 - Large substrate structural vias: An electronic package and methods by which the package reduces thermal fatigue failure of conductors in the electronic package. The electronic package includes a carrier substrate having first and second surfaces and a plurality of anchor vias having a via material extending from the first surface toward the second surface.... Agent: Imperium Patent Works

20090079057 - Integrated circuit device: An integrated circuit device includes a carrier defining a surface with a semiconductor chip including an integrated circuit attached to the carrier. An insulation layer is disposed over the carrier, extending above the surface of the carrier a first distance at a first location and a second distance at a... Agent: Dicke, Billig & Czaja

20090079059 - Integrated semiconductor substrate structure using incompatible processes: A plurality of FPGA dice is disposed upon a semiconductor substrate. In order both to connect thousands of signal interconnect lines between the plurality of FPGA dice and to supply the immense power required, it is desired that the substrate construction include two different portions, each manufactured using incompatible processes.... Agent: Imperium Patent Works

20090079058 - Semiconductor substrate elastomeric stack: A reconfigurable high performance computer occupies less than 360 cubic inches and has an approximate compute power of 0.7 teraflops per second while consuming less than 1000 watts. The computer includes a novel stack of semiconductor substrate assemblies. Some semiconductor substrate assemblies involve field programmable gate array (FPGA) dice that... Agent: Imperium Patent Works

20090079060 - Method and structure for dispensing chip underfill through an opening in the chip: A method of making an integrated circuit package includes forming a through hole in an integrated circuit and assembling a die containing the integrated circuit on a carrier so that the die is mechanically and electrically connected to the carrier. Thereafter, an underfill material is dispensed between the die and... Agent: Ibm Corporation

20090079062 - Semiconductor package and electronic device: A semiconductor package is provided. The semiconductor package includes: a package substrate on which a semiconductor device is mounted; a heat spreader at least bonded to a surface of the semiconductor device and having a thermal expansion coefficient value equal to or less than a thermal expansion coefficient value of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090079061 - Thermally enhanced electronic flip-chip packaging with external-connector-side die and method: A method and apparatus for making a package having improved heat conduction characteristics and high frequency response. A relatively thick package substrate, such as copper, has a wiring layer bonded to one face, leaving the opposite face exposed, for example, to be a surface for connection to a heat sink.... Agent: Schwegman, Lundberg & Woessner/intel

20090079063 - Microelectronic package and method of cooling an interconnect feature in same: A microelectronic package comprises a substrate (110, 310), a die (320) supported by the substrate, an interconnect feature (130, 230, 330) connecting the die and the substrate to each other, and a thermoelectric cooler (140, 170, 240, 340) adjacent to the interconnect feature.... Agent: Intel Corporation C/o Intellevate, LLC

20090079064 - Methods of forming a thin tim coreless high density bump-less package and structures formed thereby: Methods of forming microelectronic device structures are described. Those methods may include placing a plurality of support rings onto a tacky layer of a support carrier, wherein the support rings are disposed within a cavity of the support carrier; placing a plurality of thin die onto a pedestal of the... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090079066 - Integrated circuit packaging system with passive components: An integrated circuit packaging system comprising: fabricating a system-in-package substrate; mounting a first integrated circuit die on the system-in-package substrate; mounting a second integrated circuit die on the system-in-package substrate; and coupling a passive component over and between the first integrated circuit die and the second integrated circuit die.... Agent: Law Offices Of Mikio Ishimaru

20090079065 - Semiconductor device including electronic component coupled to a backside of a chip: A semiconductor package includes a substrate, at least one chip including a first side and a backside opposite of the first side, the first side electrically coupled to the substrate, a conductive layer coupled to the backside of the at least one chip, and at least one electronic component coupled... Agent: Dicke, Billig & Czaja

20090079067 - Method for stacking semiconductor chips: In a semiconductor system (100) including a chip (101) and a workpiece (102), the chip has metal-filled vias (140) positioned between contact pads (120) and the respective edges (110). In addition, seals against microcracks (150) and thermo-mechanical stress (151) are located between the vias and the active components, and sometimes... Agent: Texas Instruments Incorporated

20090079068 - Methods for attaching a flip chip integrated circuit assembly to a substrate: A method for fabricating an integrated circuit assembly, comprises forming a conductive material pattern on a substrate using a process in which the conductive material in wet when formed, the conductive material pattern comprising contact points, before curing the conductive material, placing a integrated circuit comprising contact bumps on the... Agent: Baker & Mckenzie LLP Patent Department

20090079069 - Semiconductor device and method of forming interconnect structure in non-active area of wafer: A semiconductor wafer includes a plurality of semiconductor die. Contact pads are formed on an active area of the semiconductor die and non-active area of the semiconductor wafer between the semiconductor die. Solder bumps are formed on the contact pads in both the active area of the semiconductor die and... Agent: Quarles & Brady LLP

20090079074 - Semiconductor device having decoupling capacitor formed on substrate where semiconductor chip is mounted: A semiconductor device includes a substrate having a first surface and a second surface opposing to the first surface, a semiconductor chip mounted on the first surface of the substrate, a first pad formed on the first surface of the substrate to electrically connect to a first terminal of the... Agent: Mcginn Intellectual Property Law Group, PLLC

20090079072 - Semiconductor device having low dielectric insulating film and manufacturing method of the same: A semiconductor device includes a semiconductor substrate having an integrated circuit. A low dielectric film wiring line laminated structure portion is provided on the semiconductor substrate except a peripheral portion thereof, and is constituted by low dielectric films and wiring lines. The low dielectric film has a relative dielectric constant... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090079073 - Semiconductor device having low dielectric insulating film and manufacturing method of the same: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090079070 - Semiconductor package with passivation island for reducing stress on solder bumps: A flip chip style semiconductor package has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate. An under bump metallization (UBM) layer is in electrical contact with the contact pad. A passivation layer is formed over the substrate. In one case,... Agent: Quarles & Brady LLP

20090079071 - Stress relief structures for silicon interposers: An electronic device and method of making the device. The device includes: a carrier; a silicon interposer connected to a top surface of the carrier, the interposer having wires extending from a top surface of the interposer, through the interposer, to a bottom surface of the interposer, the wires at... Agent: Schmeiser, Olsen & Watts

20090079075 - Interconnect structures with patternable low-k dielectrics and method of fabricating same: The present invention provides an interconnect structure in which a patternable low-k material is employed as an interconnect dielectric material. Specifically, this invention relates to single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric. In general terms, the interconnect structure includes at least one patterned and... Agent: Scully, Scott, Murphy & Presser, P.C.

20090079076 - Patternable dielectric film structure with improved lithography and method of fabricating same: The present invention provides a method of fabricating an interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene low-k interconnect structures with at least one patternable... Agent: Scully, Scott, Murphy & Presser, P.C.

20090079077 - Interconnect structure with a via gouging feature absent profile damage to the interconnect dielectric and method of fabricating same: An interconnect structure including a gouging feature at the bottom of the via openings and a method of forming the same, which does not introduce either damages caused by Ar sputtering into the dielectric material that includes the via and line openings, nor plating voids into the structure are provided.... Agent: Scully, Scott, Murphy & Presser, P.C.

20090079078 - Minimization of interfacial resitance across thermoelectric devices by surface modification of the thermoelectric material: A coating architecture (106, 206, 306) minimizing interfacial resistance across an interface (100, 200, 300) of a metal (104, 204, 304) and a semiconductor including at least two layers (108, 110, 112, 208, 210, 212, 306) intermediate the metal (104, 204, 304) and the semiconductor.... Agent: Ohlandt, Greeley, Ruggiero & Perle, LLP

20090079079 - Semiconductor device with an air gap between lower interconnections and a connection portion to the lower interconnections not formed adjacent to the air gap: A method for fabricating a semiconductor device includes the steps of: forming a plurality of lower interconnections at intervals in a first insulating film; removing a portion of the first insulating film located between the lower interconnections, thereby forming an interconnection-to-interconnection gap; forming a second insulating film over the first... Agent: Mcdermott Will & Emery LLP

20090079080 - Semiconductor device with multi-layer metallization: One or more embodiments are related to a semiconductor device, comprising: a metallization layer comprising a plurality of portions, each of the portions having a different thickness. The metallization layer may be a final metal layer.... Agent: Infineon Technologies Ag Patent Department

20090079081 - Electronic device with wire bonds adhered between integrated circuits dies and printed circuit boards: An electronic device that has an integrated circuit die with a plurality of contacts pads, a printed circuit board with a plurality of conductors corresponding to each of the contact pads respectively, wire bonds electrically connecting each of the contact pads to the corresponding conductors and, an adhesive surface positioned... Agent: Silverbrook Research Pty Ltd

20090079082 - Bonding pad structure allowing wire bonding over an active area in a semiconductor die and method of manufacturing same: A wire bonding pad over an active area of a semiconductor die has grooves in two orthogonal sections thereof in the top surface of said wire bonding pad.... Agent: Hiscock & Barclay, LLP

20090079083 - Interconnect structure and fabricating method of the same: A fabricating method of an interconnect structure is provided. A first dielectric layer is formed on a substrate for covering an air gap region and a non-air gap region. Next, interconnects are formed in the first dielectric layer on the air gap region and in the first dielectric layer on... Agent: J C Patents, Inc.

20090079084 - Preventing breakage of long metal signal conductors on semiconductor substrates: An apparatus includes a volume of insulator disposed over a top surface of a semiconductor substrate, a tube of soft dielectric, and a metal conductor. The insulator has a hardness of more than approximately three gigapascals (gPa) and the soft dielectric has a hardness of less than three gPa. The... Agent: Imperium Patent Works

20090079085 - Semiconductor device: A semiconductor device including a semiconductor section including a semiconductor element and a recess formed in one of main surfaces and a metallic member at least a part of which is embedded in the recess. A void is formed in a region of the metallic member corresponding to the recess.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090079086 - Semiconductor device: A semiconductor device according to the present invention includes: a first interlayer dielectric film; a lower wire formed on the first interlayer dielectric film; a second interlayer dielectric film formed on the first interlayer dielectric film and the lower wire; and an upper wire formed on the second interlayer dielectric... Agent: Rabin & Berdo, PC

20090079087 - Semiconductor device and method for fabricating the same: A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a conductive section formed on the conductive land. The conductive section is electrically connected through the conductive land... Agent: Mcdermott Will & Emery LLP

20090079091 - Integrated circuit packaging system with interposer: An integrated circuit packaging system comprising: fabricating an interposer array having an access opening; fabricating a base package substrate sheet; attaching a first integrated circuit die over the base package substrate sheet; mounting the interposer array over the first integrated circuit die; and singulating a base package from the base... Agent: Law Offices Of Mikio Ishimaru

20090079088 - Semiconductor device with conductive die attach material: A semiconductor device includes a carrier such as a lead frame, a semiconductor die and an attachment member affixing the semiconductor die to the carrier. The attachment device includes an electrically conductive organic material.... Agent: Dicke, Billig & Czaja

20090079092 - Stacked dual-die packages, methods of making, and systems incorporating said packages: A semiconductor die package. It includes a substrate having a first surface and a second surface, a first semiconductor die having its front surface facing the first surface of the substrate, a conductive adhesive disposed between the first semiconductor die and the first surface of the substrate, and a second... Agent: Townsend And Townsend And Crew, LLP

20090079089 - Stacked semiconductor chips: Stacked semiconductor chips are disclosed. One embodiment provides a method including a first substrate having a first surface and an opposing second surface. The first substrate includes an array of first connection elements on the first surface of the first substrate. A second substrate has a first surface and an... Agent: Dicke, Billig & Czaja

20090079090 - Stacked semiconductor chips: Stacked semiconductor chips are disclosed. One embodiment provides an array of first semiconductor chips, covering the array of the first semiconductor chips with a mold material, and placing an array of second semiconductor chips over the array of the first semiconductor chips. The thicknesses of the second semiconductor chips is... Agent: Dicke, Billig & Czaja

20090079093 - Flip chip structure and method of manufacture: A flip chip structure includes glass stand-offs formed overlying a substrate surface. A conductive layer is formed overlying the glass stand-offs and configured for attaching to a next level of assembly. In one embodiment, photo glass processing is used to form the glass stand-offs.... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20090079094 - Solder bump with inner core pillar in semiconductor package: A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer.... Agent: Quarles & Brady LLP

20090079095 - Semiconductor wafer, semiconductor chip cut from the semiconductor wafer, and method of manufacturing semiconductor wafer: A disclosed semiconductor wafer includes plural semiconductor chip areas each having a color pattern capable of tracing the positional information of the semiconductor chip with respect to the semiconductor wafer. Each of the plural semiconductor chip areas arranged in a matrix manner on the semiconductor wafer includes an underlying insulation... Agent: Dickstein Shapiro LLP

20090079097 - Electronic component with wire bonds in low modulus fill encapsulant: An electronic component that has a support structure with a plurality of electrical conductors, a series of wire bonds, each of the wire bonds extending from one of the electrical conductors respectively, each of the wire bonds having an end section contacting the electrical conductor and an intermediate section contiguous... Agent: Silverbrook Research Pty Ltd

20090079096 - Integrated circuit package system with multiple device units: An integrated circuit package system comprising forming a first device unit, having a first external interconnect, and a second device unit, having a second external interconnect, in an array configuration; mounting an integrated circuit die over the first device unit; connecting the integrated circuit die and the first external interconnect;... Agent: Law Offices Of Mikio Ishimaru

20090072212 - Anti-fuse memory device: A One Time Programmable (OTP) memory cell (10) comprising a first, metallic layer (12) coated with a second, conductive stable transition compound (14) with an insulating layer (16) there-between. The first and second layers (12, 14) are selected according to the difference in Gibbs Free Energy between them, which dictates... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090072214 - Phase-change memory cell and method of fabricating the phase-change memory cell: A memory cell (and method of fabricating the memory cell) includes a stencil layer having a first opening, a phase-change material layer formed on a first electrode layer, and an electrically conductive layer formed on the first electrode layer, the electrically conductive layer having a pillar-shaped portion which is formed... Agent: Mcginn Intellectual Property Law Group, PLLC

20090072213 - Programmable via structure for three dimensional integration technology: A programmable link structure for use in three dimensional integration (3DI) semiconductor devices includes a via filled at least in part with a phase change material (PCM) and a heating device proximate the PCM. The heating device is configured to switch the conductivity of a transformable portion of the PCM... Agent: Cantor Colburn LLP-ibm Yorktown

20090072211 - Resistive random access memory and method for manufacturing the same: A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has... Agent: Bacon & Thomas, PLLC

20090072210 - Switching device: A switching device contains a thin film containing an organic material disposed between at least two electrodes, and the organic material is, for example, a triphenylamine compound represented by the general formula (I):... Agent: Rabin & Berdo, PC

20090072218 - Higher threshold voltage phase change memory: A phase change memory may be formed of a phase change material alloy that produces a higher threshold voltage and, in some cases, is operable at higher temperatures. For example, the formulation may include a poor metal, antimony, and at least one of tellurium or selenium.... Agent: Trop, Pruner & Hu, P.C.

20090072217 - Integrated circuits; methods for manufacturing an integrated circuit and memory module: Embodiments of the present invention relate generally to integrated circuits, to methods for manufacturing an integrated circuit and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a programmable arrangement. The programmable arrangement includes a substrate having a main processing surface, at least... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090072216 - Phase change memory cell array with self-converged bottom electrode and method for manufacturing: An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090072215 - Phase change memory cell in via array with self-aligned, self-converged bottom electrode and method for manufacturing: An array of “mushroom” style phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming an isolation layer on the separation layer and forming an array of memory element openings in the isolation layer using a lithographic process. Etch masks are formed within... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090072219 - Mos transistor on the basis of quantum interferance effect: A new type of Metal Oxide Semiconductor (MOS) transistor that works on the basis of the Quantum Interference Depression (QID) effect is disclosed. QID occurs inside an n-type semiconductor source-drain electrode of special geometry. Due to QID the Fermi level of said semiconductor increases locally inside the source drain electrode,... Agent: Borealis Technical Limited

20090072220 - Nitride semiconductor led and fabrication method thereof: A nitride semiconductor light emitting diode according to the present invention, includes: a substrate; a buffer layer formed on the substrate; an In-doped GaN layer formed on the buffer layer; a first electrode layer formed on the In-doped GaN layer; an InxGa1−xN layer formed on the first electrode layer; an... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090072221 - Nitride semiconductor device and method for fabricating the same: A nitride semiconductor device comprises: a well layer of nitride semiconductor containing In and Ga; barrier layers of nitride semiconductor sandwiching the well layer, containing Al and Ga, and having a larger band gap energy than the well layer; and a thin film layer provided between the well layer and... Agent: Mcdermott Will & Emery LLP

20090072223 - Field effect transistor using carbon nanotube, method of fabricating same, and sensor: A field effect transistor according to the present invention includes a carbon nanotube of two or more walls having an inner wall and an outer wall, source and drain electrodes formed on both sides of the carbon nanotube, and a gate electrode formed in a gate formation region of the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090072222 - Method for forming catalyst nanoparticles for growing elongated nanostructures: Preferred embodiments provide a method for forming at least one catalyst nanoparticle on at least one sidewall of a three-dimensional structure on a main surface of a substrate, the main surface lying in a plane and the sidewall of the three-dimensional structure lying in a plane substantially perpendicular to the... Agent: Knobbe Martens Olson & Bear LLP

20090072226 - Display device having organic thin film transistor: Provided is a display device having an organic TFT. The display device includes the organic TFT on a substrate, a passivation layer covering the organic TFT, and a bank layer on the passivation layer. At this point, at least one of the passivation layer and the bank layer is formed... Agent: Rabin & Berdo, PC

20090072224 - Field effect transistor: A field effect transistor including a gate isulation portion, an organic semiconductor portion, a source electrode and a drain electrode, wherein when a voltage is applied to the gate at 70° C. for 5.0±0.1 hours so that the field strength in the gate insulation portion would be 100±5 MV/m, the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090072225 - Flat panel display device having organic thin film transistor and manufacturing method thereof: Provided is a flat panel display device having an organic TFT and a manufacturing method thereof. The flat panel display device includes a first organic TFT having a first organic semiconductor active layer, and a second organic TFT having a second organic semiconductor active layer. At this point, the particle... Agent: Rabin & Berdo, PC

20090072230 - Gas-barrier film and organic device comprising same: A gas-barrier film comprising at least one silicon hydronitride layer and at least one silicon nitride layer on a surface of a flexible supporting substrate. The film has an excellent gas-barrier property.... Agent: Birch Stewart Kolasch & Birch

20090072227 - Organic compound crystal and field-effect transistor: A field-effect transistor includes a channel-forming region composed of an organic compound crystal including π-electron conjugated molecules each containing chalcogen atoms as a constituent, wherein the distance between chalcogen atoms of adjacent π-electron conjugated molecules is short, and the organic compound crystal has a periodic structure in which π-electron conjugated... Agent: Frommer Lawrence & Haug

20090072228 - Organic thin film transistor substrate and method of manufacture: An organic thin film transistor substrate includes a gate electrode formed on a substrate, a gate insulation layer formed on the gate electrode to have a source-connecting portion and a drain-seating groove, a source electrode formed in the source-connecting portion, a drain electrode formed in the drain-seating groove and an... Agent: Macpherson Kwok Chen & Heid LLP

20090072229 - Thin film transistor, method of fabricating the thin film transistor, organic light emitting diode display device, method of fabricating the organic light emitting diode display device, and donor substrate for laser induced thermal imaging: A thin film transistor (TFT), a method of fabricating the TFT, an organic light emitting diode (OLED) display device, a method of fabricating the OLED display device, and a donor substrate for laser induced thermal imaging (LITI) includes interconnections formed of a mixed layer of metal nanoparticles and carbon black... Agent: Stein, Mcewen & Bui, LLP

20090072231 - Formation of p-n homogeneous junctions: Methods, structures and devices are described, in which structures and devices have one or more p-n homo-junctions fabricated in solution. The junctions are formed by a sequential deposition of an oxide of copper from solution. Conduction type of the oxide of copper is controlled by pH of the solution.... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20090072233 - Light-emitting device using oxide semiconductor thin-film transistor and image display apparatus using the same: The present invention provides a light-emitting device, including: a pixel region provided on a substrate and including a blue pixel region, a green pixel region, and a red pixel region which correspond to lights of three primary colors of blue, green and red light, respectively, the pixel region including: a... Agent: Fitzpatrick Cella Harper & Scinto

20090072232 - Thin-film transistor and display device using oxide semiconductor: The thin-film transistor of the present invention has at least a semiconductor layer including: on a substrate, a source electrode, a drain electrode, and a channel region; a gate insulating film; and a gate electrode, wherein the semiconductor layer is an oxide semiconductor layer, and wherein the gate insulating film... Agent: Fitzpatrick Cella Harper & Scinto

20090072234 - Test stuctures for development of metal-insulator-metal (mim) devices: In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor... Agent: Paul J. Winters

20090072235 - Electronic device having liquid crystal display device: A display device of the present invention includes a first substrate and a second substrate opposed to each other, a liquid crystal interposed between the first substrate and the second substrate, an active matrix circuit and a driving circuit each comprising a thin film transistor formed over the first substrate,... Agent: Fish & Richardson P.C.

20090072236 - Pixel structure and manufacturing method thereof: A pixel structure and a manufacturing method thereof is provided, the pixel structure including a thin film transistor (TFT), a pixel electrode, a common line, a first dielectric layer and a second dielectric layer. Both of the TFT and the pixel electrode are disposed on the substrate and electrically coupled... Agent: Jianq Chyun Intellectual Property Office

20090072238 - Insulated gate field effect semiconductor devices and method of manufacturing the same: An LDD structure is manufactured to have a desired aspect ratio of the height to the width of a gate electrode. The gate electrode is first deposited on a semiconductor substrate followed by ion implantation with the gate electrode as a mask to form a pair of impurity regions. The... Agent: Nixon Peabody, LLP

20090072237 - Method for manufacturing thin film transistor and display device including the thin film transistor: To provide a method for manufacturing a thin film transistor with excellent electric characteristics and high reliability and a display device including the thin film transistor. A gate insulating film is formed over a gate electrode, crystal nuclei is formed over the gate insulating film using fluorosilane and silane, and... Agent: Eric Robinson

20090072239 - Gallium oxide single crystal composite, process for producing the same, and process for producing nitride semiconductor film utilizing gallium oxide single crystal composite: Provided are: a gallium oxide single crystal composite, which can provide, for example, upon a crystal growth of a nitride semiconductor, a high-quality cubic crystal in which mixing of a hexagonal crystal is reduced to thereby realize dominant growth of a cubic crystal over hexagonal crystal, and which can be... Agent: Edwards Angell Palmer & Dodge LLP

20090072240 - Iii-nitride devices with recessed gates: III-nitride devices are described with recessed gates. In some embodiments, the material around the gates is formed by epitaxially depositing different III-nitride layers on a substrate and etching through at least the top two layers in the gate region. Because adjacent layers in the top three layers of the structure... Agent: Fish & Richardson P.C.

20090072243 - Compound semiconductor device and method for fabricating compound semiconductor: In the present invention, a technology for causing arbitrary polarity, crystal face and crystal orientation to exist mixedly in a plane on the surface of a SiC substrate, and for forming a SiC layer or a group III-nitride or group II-oxide layer on the surface, is provided. A first SiC... Agent: Reed Smith LLP

20090072241 - Grid-umosfet with electric field shielding of gate oxide: A trench metal oxide semiconductor field effect transistor or UMOSFET, includes a buried region that extends beneath the trench and beyond a corner of the trench. The buried region is tied to a source potential of the UMOSFET, and splits the potential realized across the structure. This effectively shields the... Agent: Volentine & Whitt PLLC

20090072242 - Insulated gate bipolar conduction transistors (ibcts) and related methods of fabrication: Insulated gate bipolar conduction transistors (IBCTs) are provided. The IBCT includes a drift layer having a first conductivity type. An emitter well region is provided in the drift layer and has a second conductivity type opposite the first conductivity type. A well region is provided in the drift layer and... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090072244 - Method for manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device: The object is to provide a method for the fabrication of a semiconductor device having undergone an anneal treatment for the purpose of forming such ohmic contact as enables decrease of ohmic contact resistance and being provided on the (000-1) plane of silicon carbide with an insulating film and provide... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090072246 - Diode and memory device comprising the same: Provided are a diode and a memory device comprising the diode. The diode includes a p-type semiconductor layer and an n-type semiconductor layer, wherein at least one of the p-type semiconductor layer and the n-type semiconductor layer comprises a resistance changing material whose resistance is changed according to a voltage... Agent: Harness, Dickey & Pierce, P.L.C

20090072247 - Light emitting display device and method of fabricating the same: A light emitting display device includes a light emitting diode and a thin film transistor on a substrate, the light emitting diode and thin film transistor being electrically coupled to each other, and a photo diode on the substrate, the photo diode including an intrinsic region and a P-type doping... Agent: Lee & Morse, P.C.

20090072245 - Method of producing a light-emitting diode comprising a nanostructured pn junction and diode thus obtained: A nanostructured pn junction light-emitting diode is fabricated from a semi-conducting substrate doped by a first dopant and covered by a dielectric thin layer. An amorphous thin film formed by a semi-conducting material doped by a second dopant of opposite type to that of the first dopant is then deposited... Agent: Oliff & Berridge, PLC

20090072248 - Light emitting display device and method of fabricating the same: A light emitting display device includes a light emitting diode and a thin film transistor on a substrate, the light emitting diode and thin film transistor being electrically coupled to each other, and a photo diode on the substrate, the photo diode including an N-type doping region, a P-type doping... Agent: Lee & Morse, P.C.

20090072250 - Chip type semiconductor light emitting device: There is provided a reflective chip type semiconductor light emitting device, which has improved efficiency of taking out light and further improved luminance with the same input, and which emits high luminance light by emitting light uniformly from an area as large as possible and is suitable for lighting apparatuses.... Agent: Rabin & Berdo, PC

20090072249 - Nitride semiconductor light-emitting device: A nitride semiconductor light-emitting device including a first n-type nitride semiconductor layer, a light-emitting layer, a p-type nitride semiconductor layer, and a second n-type nitride semiconductor layer in this order, and further including an electrode formed of a transparent conductive film on the second n-type nitride semiconductor layer is provided.... Agent: Harness, Dickey & Pierce, P.L.C

20090072251 - Led surface-mount device and led display incorporating such device: In one embodiment, a surface-mount device comprises a casing having opposed, first and second main surfaces, side surfaces, and end surfaces. A lead frame partially encased by the casing comprises (1) an electrically conductive LED chip carrier part having a surface carrying a linear array of three LEDs adapted to... Agent: Koppel, Patrick & Heybl

20090072252 - Nitride semiconductor light emitting device and fabrication method therefor: Disclosed is a nitride semiconductor light emitting device including: one or more AllnN layers; an In-doped nitride semiconductor layer formed above the AllN layers; a first electrode contact layer formed above the In-doped nitride semiconductor layer; an active layer formed above the first electrode contact layer; and a p-type nitride... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090072253 - Semiconductor light emitting device, method for manufacturing same, and method for forming underlying layer: Disclosed herein is a semiconductor light emitting device including: (A) an underlying layer configured to be formed on a major surface of a substrate having a {100} plane as the major surface; (B) a light emitting part; and (C) a current block layer, wherein the underlying layer is composed of... Agent: Sonnenschein Nath & Rosenthal LLP

20090072254 - Polarization doping in nitride based diodes: A light emitting device comprising a three-dimensional polarization-graded (3DPG) structure that improves lateral current spreading within the device without introducing additional dopant impurities in the epitaxial structures. The 3DPG structure can include a repeatable stack unit that may be repeated several times within the 3DPG. The stack unit includes a... Agent: Koppel, Patrick & Heybl

20090072262 - (al,in,ga,b)n device structures on a patterned substrate: A nitride light emitting diode, on a patterned substrate, comprising a nitride interlayer having at least two periods of alternating layers of InxGa1-xN and InyGa1-yN where 0<x<1 and 0≦y<1, and a nitride based active region having at least one quantum well structure on the nitride interlayer.... Agent: Gates & Cooper LLP Howard Hughes Center

20090072263 - Color control by alteration of wavelength converting element: A light emitting device is produced by depositing a layer of wavelength converting material over the light emitting device, testing the device to determine the wavelength spectrum produced and correcting the wavelength converting member to produce the desired wavelength spectrum. The wavelength converting member may be corrected by reducing or... Agent: Patent Law Group LLP

20090072257 - Light emitting device: An upper electrode is formed on one surface of a semiconductor multilayer structure including a light emitting layer. An interface electrode is formed at a region of another surface of the semiconductor multilayer structure except a region right under the upper electrode. A center of the interface electrode coincides with... Agent: Mcginn Intellectual Property Law Group, PLLC

20090072261 - Light emitting diode device: A light emitting diode device includes a substrate, a light emitting diode chip, a plurality of wires, a plurality of lead frames, an insulating body, an encapsulant and a lens. The light emitting diode chip is electrically connected with a lead frame and the substrate. The substrate is electrically connected... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090072256 - Light emitting diode package and method of manufacturing the same: Provided is a light emitting diode (LED) package including a phosphor substrate; an LED chip mounted on the phosphor substrate; a circuit board mounted on the other region of the phosphor substrate excluding the region where the LED chip is mounted; an electrode connection portion for electrically connecting the LED... Agent: Mcdermott Will & Emery LLP

20090072259 - Light-emitting diode apparatus and manufacturing method thereof: A light-emitting diode (LED) apparatus includes a thermoconductive substrate, a thermoconductive adhesive layer, an epitaxial layer, a current spreading layer and a micro- or nano-roughing structure. The thermoconductive adhesive layer is disposed on the thermoconductive substrate. The epitaxial layer is disposed opposite to the thermoconductive adhesive layer and has a... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090072260 - Organic electroluminescence device and method for manufacturing the same: An organic electroluminescence device and a method for manufacturing the same are disclosed. The organic electroluminescence device includes a transparent substrate, a semiconductor layer including a source region, a channel region and a drain region, a gate insulating film having first contact holes on the source and drain regions and... Agent: Morgan Lewis & Bockius LLP

20090072258 - Organic light emitting display and method of manufacturing the same: An organic light emitting display includes an organic light emitting diode formed on a substrate, coupled to a transistor; a photodiode formed on the substrate and including a semiconductor layer including a high-concentration P doping region, an intrinsic region with defects and a high-concentration N doping region; and a controller... Agent: Stein, Mcewen & Bui, LLP

20090072255 - Phosphor and light-emitting device using same: The phosphor of the present invention has a high luminous efficiency and emits light of orange to red with high luminance. The use of the phosphor makes it possible to produce a light-emitting device, an illumination apparatus, and an image display, having a high efficiency and excellent color rendering properties.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090072264 - Method of fabricating vertical devices using a metal support film: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal techniques. Trenches that define the boundaries of the individual devices are formed through the semiconductor layers and into the insulating substrate, beneficially by inductive... Agent: Mckenna Long & Aldridge LLP

20090072265 - Process for producing light-emitting device and light-emitting device: After a LED mounted on a wiring board is prepared, a glass member having a shape approximated by a rectangular solid or a sphere is placed on the LED. In this step, the glass member is placed so that the central axis of the glass member placed on the LED... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090072266 - Semiconductor light emitting device: Disclosed herein is a semiconductor light emitting device including: a light emitting part formed of a multilayer structure arising from sequential stacking of a first compound semiconductor layer, an active layer, and a second compound semiconductor layer; a current block layer; and a burying layer, wherein a planar shape of... Agent: Sonnenschein Nath & Rosenthal LLP

20090072267 - Group iii nitride-based compound semiconductor light-emitting device: Provided is a GaN-based semiconductor light-emitting device which does not require an external constant-current circuit. The light-emitting device of the present invention includes a sapphire substrate; an AlN buffer layer formed on the substrate; and an HEMT structure formed on the buffer layer, the HEMT structure including a GaN layer... Agent: Mcginn Intellectual Property Law Group, PLLC

20090072268 - Semiconductor device: A semiconductor device includes a semiconductor substrate having a main surface and a semiconductor element having an insulated gate field effect portion formed in the semiconductor substrate. The semiconductor element includes an n− region, an n-type source region, a p-type base region, an n+ region, and a gate electrode. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090072269 - Gallium nitride diodes and integrated components: A diode device can include an enhancement mode gallium nitride transistor having a gate, a drain and a source, wherein the gate is connected to the drain to enable the device to perform as a diode. In some embodiments, an integrated switching-diode is described that includes a substrate, a gallium... Agent: Fish & Richardson P.C.

20090072271 - Epitaxial growth of thin smooth germanium (ge) on silicon (si) utilizing an interfacial silicon germanium (sige) pulse growth method: Disclosed is a method of growing thin and smooth germanium (Ge) on a strained or relaxed silicon (Si) layer comprising the steps of: (a) treating surface of the strained or relaxed Si layer to gaseous precursors of both Si (e.g., silane) and Ge (e.g., germane) for a predetermined short time... Agent: Attn: Matthew E. Connors Gauthier & Connors LLP

20090072270 - Low voltage transistors: The invention provides a transistor having a substrate, a structure supported by the substrate including a source, drain, gate, and channel, wherein the source and the channel are made of different materials, and a tunnel junction formed between the source and the channel, whereby the tunnel junction is configured for... Agent: Greer, Burns & Crain

20090072272 - Enhancement mode gallium nitride power devices: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.... Agent: Fish & Richardson P.C.

20090072273 - Iii-nitride semiconductor device with reduced electric field between gate and drain and process for its manufacture: A conductive field plate is formed between the drain electrode and gate of each cell of a III-Nitride semiconductor and is connected to the source electrode to reduce the electric field between the gate and the drain. The electrodes may be supported on N′ III-Nitride pad layers and the gate... Agent: Ostrolenk Faber Gerb & Soffen

20090072274 - Integrated circuit including a first gate stack and a second gate stack and a method of manufacturing: An integrated circuit including a first gate stack and a second gate stack and a method of manufacturing is disclosed. One embodiment provides non-volatile memory cells including a first gate stack and a gate dielectric on a first surface section of a main surface of a semiconductor substrate, and a... Agent: Dicke, Billig & Czaja

20090072275 - Solid-state imaging device and method for manufacturing thereof as well as driving method of solid-state imaging device: A solid-state imaging device with a structure such that an electrode for reading a signal charge is provided on one side of a light-receiving sensor portion constituting a pixel; a predetermined voltage signal V is applied to a light-shielding film formed to cover an image pickup area except the light-receiving... Agent: Sonnenschein Nath & Rosenthal LLP

20090072276 - Semiconductor wafer, semiconductor device and method of fabricating the same: A semiconductor substrate according to an embodiment includes: a first semiconductor wafer having a first crystal; and a second semiconductor wafer formed of a second crystal substantially same as the first crystal on the first semiconductor wafer, a crystal-axis direction of unit cell thereof being twisted at a predetermined angle... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090072278 - Method for applying a stress layer to a semiconductor device and device formed therefrom: A semiconductor device includes a substrate of semiconductor material. A source region, a drain region, and a conducting region of the semiconductor device are formed in the substrate and doped with a first type of impurities. The conducting region is operable to conduct current between the drain region and the... Agent: Baker Botts L.L.P.

20090072277 - System and method for enabling higher hole mobility in a jfet: A junction field effect transistor comprises a semiconductor wafer having a (110) and/or (100) surface orientation. A source region and a drain region are formed on the semiconductor wafer. A channel region of a p-conductivity type is formed between the source region and the drain region. The channel region is... Agent: Baker Botts L.L.P.

20090072279 - Capacitor-less memory and abrupt switch based on hysteresis characteristics in punch-through impact ionization mos transistor (pi-mos): The present invention exploits the impact ionization induced by drain voltage increase and the onset of a bipolar parasitic in an Ω-gate field effect metal oxide insulator transistor (called PI-MOS), in order to obtain a memory effect and abrupt current switching.... Agent: Nixon & Vanderhye, PC

20090072280 - Pmos transistor with increased effective channel length in the peripheral region and method of manufacturing the same: In manufacturing a PMOS transistor, a semiconductor substrate having an active region and a field region is formed with a hard mask layer, which covers a center portion of the active region on the substrate in a lengthwise direction of a channel. The hard mask layer exposes the center portion... Agent: Ladas & Parry LLP

20090072283 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and a method for manufacturing the same improves photosensitivity and prevent loss of light by forming a photo-sensing unit under a color filter. The CMOS image sensor may include a plurality of transistors formed on a semiconductor substrate, a metal line formed over the plurality of... Agent: Mckenna Long & Aldridge LLP

20090072281 - Cmos image sensor layout capable of removing difference between gr and gb sensitivities and method of laying out the cmos image sensor: Provided is a layout of a CMOS image sensor having an asymmetrical pixel structure in which a plurality of photodiodes may share a transistor block. The layout may include a first region in which a plurality of photodiodes are arranged asymmetrically on a semiconductor substrate, a second region including a... Agent: Harness, Dickey & Pierce, P.L.C

20090072282 - Image sensor and method for manufacturing the same: Provided is an image sensor. In the image sensor, a transistor region is on a substrate, and a photo diode region is at one side of the transistor region. A dielectric layer is formed on the transistor region and the photo diode region. A metal line is formed on the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090072284 - Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry: In accordance with the invention, an improved image sensor comprises an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques. The germanium elements are subsequently formed... Agent: Wolf Greenfield & Sacks, P.C.

20090072285 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same for preventing contamination and peeling of an array of micro lenses. The CMOS image sensor includes a plurality of photodiodes formed on and/or over a substrate, an insulating film formed on and/or over an entire surface of the substrate... Agent: Sherr & Vaughn, PLLC

20090072286 - Semiconductor device and its manufacturing method: A semiconductor device includes: a ferroelectric capacitor that is provided above a base substrate and includes a first electrode, a ferroelectric film provided on the first electrode and a second electrode provided on the ferroelectric film; a stopper film that covers a top surface of the second electrode of the... Agent: Harness, Dickey & Pierce, P.L.C

20090072287 - Semiconductor device and its manufacturing method: A semiconductor device includes: a ferroelectric capacitor including a first electrode provided above a substrate, a ferroelectric film provided on the first electrode and a second electrode provided on the ferroelectric film; a hydrogen barrier film that covers a top surface and a side surface of the ferroelectric capacitor; an... Agent: Harness, Dickey & Pierce, P.L.C

20090072288 - Terraced film stack: A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, which if not addressed can cause device failure.... Agent: Dinsmore & Shohl LLP

20090072289 - Semiconductor device having reduced thickness, electronic product employing the same, and methods of fabricating the same: A semiconductor device capable of reducing a thickness, an electronic product employing the same, and a method of fabricating the same are provided. The method of fabricating a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor in the first active region includes... Agent: Lee & Morse, P.C.

20090072290 - Soi cmos compatible multiplanar capacitor: An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon.... Agent: Scully, Scott, Murphy & Presser, P.C.

20090072291 - Semiconductor memory device: A semiconductor memory device includes: first word lines; second word lines, each of the second word lines being electrically connected to a corresponding one of the first word lines; bit lines; and memory cells, each of the memory cells including a transistor and a capacitor. The semiconductor memory device includes:... Agent: Scully Scott Murphy & Presser, PC

20090072293 - Flash memory and method for manufacturing the same: Provided are a flash memory and a method for manufacturing the same. The flash memory includes a semiconductor substrate having a device isolation region and an active region; a stacked gate on the semiconductor substrate; an insulation layer covering the semiconductor substrate and the stacked gate; a drain contact penetrating... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090072292 - Semiconductor device and method of making semiconductor device: One or more embodiments are related to a semiconductor device, comprising: a high-K dielectric material; and a nitrogen-doped silicon material disposed over said high-k dielectric material.... Agent: Infineon Technologies Ag Patent Department

20090072295 - Flash eeprom device and method for fabricating the same: In a flash EEPROM device, and method for fabricating the same, no bit line contact is made, thereby minimizing a design rule between a contact and a gate. Thus, cell size may be reduced. The flash EEPROM device includes a semiconductor substrate having an active area defined in a bit... Agent: Mckenna Long & Aldridge LLP

20090072294 - Method of manufacturing a non-volatile memory device: A method of manufacturing a non-volatile memory device employing a relatively thin polysilicon layer as a floating gate is disclosed, wherein a tunnel oxide layer is formed on a substrate and a polysilicon layer having a thickness of about 35 Å to about 200 Å is then formed on the... Agent: Mills & Onello LLP

20090072296 - Multibit electro-mechanical device and method of manufacturing the same: A multibit electro-mechanical memory device capable of increasing an integrated level of memory devices, and a method of manufacturing the same, are provided. The memory device includes a substrate, a bit line in a first direction on the substrate, a lower word line insulated from the bit line and in... Agent: Mills & Onello LLP

20090072297 - Multibit electro-mechanical memory device and method of manufacturing the same: A memory device comprises a cantilever electrode comprising a first portion that is supported by a pad electrode, and that extends from the pad electrode, and further comprising a second portion that arches over an upper part of the lower word line, wherein a lower void is between the second... Agent: Mills & Onello LLP

20090072298 - Semiconductor device and method of manufacturing the same: An embodiment of a semiconductor device includes a substrate including a cell region and a peripheral region; a cell gate pattern on the cell region; and a peripheral gate pattern on the peripheral region, wherein a first cell insulation layer, a second cell insulation layer, and a third cell insulation... Agent: Harness, Dickey & Pierce, P.L.C

20090072299 - Semiconductor device having high voltage mos transistor and fabrication method thereof: A semiconductor device having a high voltage MOS transistor. The device includes a gate oxide layer disposed between a gate electrode and a substrate on an active area and having relatively thick portions at edges thereof. A fabrication method includes forming on the substrate is a nitride layer having an... Agent: Lowe Hauptman Ham & Berner, LLP

20090072300 - Semiconductor device having trench gate structure: The present invention provides a vertical MOSFET which has striped trench gate structure which can secure avalanche resistance without increasing Ron. A vertical MOSFET 100 comprises a plurality of gate trenches 7 which is arranged in stripes, an array which is sandwiched with the plurality of gate trenches 7 and... Agent: Mcginn Intellectual Property Law Group, PLLC

20090072301 - Shielded gate trench (sgt) mosfet cells implemented with a schottky source contact: This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one active cell further includes a trenched source contact opened between the trenches wherein the trenched source contact opened through a source region into... Agent: Bo-in Lin

20090072302 - Gate metal routing for transistor with checkerboarded layout: In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in... Agent: The Law Offices Of Bradley J. Bereznak

20090072305 - Semiconductor device and method for manufacturing the same: A semiconductor device according to the present invention includes: a semiconductor layer made of silicon; a trench formed by digging in from a top surface of the semiconductor layer; a gate insulating film formed on an inner wall surface of the trench and made of silicon oxide; a gate electrode... Agent: Rabin & Berdo, PC

20090072304 - Trench misfet: In one embodiment of the present invention, trench sections cause regions where source diffusion sections and body diffusion sections are formed to be partitioned into line regions. The trench sections are formed not in a straight line shape but in a zigzag shape. Two adjacent trench sections are provided to... Agent: Harness, Dickey & Pierce, P.L.C

20090072303 - Nrom memory cell, memory array, related devices and methods: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store... Agent: Leffert Jay & Polglaze, P.A.

20090072306 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device according to the present invention includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer to be in contact with the first conductivity... Agent: Rabin & Berdo, PC

20090072307 - Semiconductor integrated circuit and method of manufacturing the same: A semiconductor integrated circuit includes a semiconductor substrate, a plurality of trenches formed to extend in one direction in the semiconductor substrate, at least one connecting trench connecting at least two of the plurality of trenches to each other, a plurality of trench transistors including a plurality of gate electrodes,... Agent: Lee & Morse, P.C.

20090072308 - Laterally diffused metal-oxide-semiconductor device and method of making the same: A laterally diffused metal-oxide-semiconductor (LDMOS) device as well as a method of making the same is disclosed. A gate is formed on a semiconductor substrate between a source region and a drain region with one side laterally extending onto a part of a field oxide layer and the opposite side... Agent: North America Intellectual Property Corporation

20090072309 - Semiconductor device: The semiconductor device according to the present invention includes an SJMOSFET having a plurality of base regions formed at an interval from each other and an SBD (Schottky Barrier Diode) having a Schottky junction between the plurality of base regions. The SBD is provided in parallel with a parasitic diode... Agent: Rabin & Berdo, PC

20090072310 - Semiconductor structure including high voltage device: A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first... Agent: HorizonIPPte Ltd

20090072311 - Mos transistor and manufacturing method thereof: There are provided a MOS transistor and a manufacturing method thereof. The MOS transistor includes a substrate on which an insulating layer is formed, a gate embedded in the insulating layer, wherein the top surface of the gate is exposed, a gate oxide layer formed on the insulating layer and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090072313 - Hardened transistors in soi devices: A series transistor device includes a series source, a series drain, a first constituent transistor, and a second constituent transistor. The first constituent transistor has a first source and a first drain, and the second constituent transistor has a second source and a second drain. All of the constituent transistors... Agent: Carey, Rodriguez, Greenberg & Paul, LLP

20090072312 - Metal high-k (mhk) dual gate stress engineering using hybrid orientation (hot) cmos: A hybrid orientation technology (HOT) CMOS structure is comprised of a tensile stressed NFET gate stack and a compressively stressed PFET gate stack, where each gate stack is comprised of a high dielectric constant oxide/metal, and where the source of the stress in the tensile stressed NFET gate stack and... Agent: Harrington & Smith, PC

20090072314 - Depletion mode field effect transistor for esd protection: The object of this invention is to present a field effect transistor by which the drain capacitance per unit gate width can be reduced. The gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14, drain region 18D (D) is formed inside the... Agent: Texas Instruments Incorporated

20090072315 - Semiconductor manufacturing process charge protection circuits: Embodiments of the invention relate to semiconductor manufacturing process charge protection circuits, integrated circuits and to methods for manufacturing a semiconductor manufacturing process charge protection circuit. In an embodiment of the invention, a charge protection circuit includes a first terminal coupled to a charge receiving region, a second terminal providing... Agent: Slater & Matsil LLP

20090072316 - Double layer stress for multiple gate transistors: Multiple gate transistors are provided with a dual stress layer for increased channel mobility and enhanced effective and saturated drive currents. Embodiments include transistors comprising a first stress layer under the bottom gate and a second stress layer overlying the top gate. Embodiments further include transistors with the bottom gate... Agent: Ditthavong Mori & Steiner, P.C.

20090072317 - Microelectronic structure by selective deposition: A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090072318 - Semiconductor device and method of fabricating the same: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device can include a gate insulating layer on a semiconductor substrate, a gate electrode on the gate insulating layer and source/drain regions in the semiconductor substrate at sides of the gate electrode. The gate electrode includes... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090072319 - Semiconductor device with relatively high breakdown voltage and manufacturing method: A semiconductor device includes at least one active component (18) having a p-n junction (26) on the semiconductor substrate in an active region (19) of the semiconductor substrate (4). A shallow trench isolation pattern is used to form a plurality of longitudinally extending shallow trenches (12) containing insulator (14). These... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090072320 - Asymmetrical layout for complementary metal-oxide-semiconductor integrated circuit to reduce power consumption: A Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit design layout incorporating an asymmetrical polysilicon gate and diffusion is disclosed. The resulting asymmetrical CMOS integrated circuit exhibits reduced current flow during operation to thereby decrease power consumption.... Agent: William C. Milks, Iii Russo & Hale LLP

20090072321 - Thin film transistor, semiconductor device, and method for manufacturing the same: A semiconductor element is operated without being affected even when the substrate is largely affected by heat shrink such as a large substrate. Furthermore, a thin film semiconductor circuit and a thin film semiconductor device each having the semiconductor element. Also, a semiconductor element is operated without being affected even... Agent: Eric Robinson

20090072322 - Semiconductor devices including line patterns separated by cutting regions: Semiconductor devices are provided. A semiconductor device can include a substrate and a plurality of dummy line patterns on the substrate that extend in a first direction parallel with one another. Each of the dummy line patterns can include a plurality of sub-line patterns aligned along the first direction and... Agent: Myers Bigel Sibley & Sajovec

20090072323 - Nonvolatile semiconductor memory device and manufacturing method thereof: In a nonvolatile semiconductor memory device which has a nonvolatile memory cell portion, a low-voltage operating circuit portion of a peripheral circuit region and a high-voltage operating circuit portion of the peripheral circuit region formed on a substrate and in which elements of the above portions are isolated from one... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090072324 - Semiconductor device having an elevated source/drain structure of varying cross-section: A semiconductor device with an elevated source/drain structure provided in each predetermined position defined by the oxide film and gate wiring on a semiconductor silicon substrate, where an orthographic projection image of a shape of an upper end portion of the elevated source/drain structure on the semiconductor silicon substrate along... Agent: Young & Thompson

20090072325 - Metal-oxide semiconductor transistor: A metal-oxide semiconductor (MOS) transistor includes a gate structure positioned in an active area defined in a substrate, a recessed source/drain, and an asymmetric shallow trench isolation (STI) for electrically isolating the active areas. A surface of the asymmetric STI and the substrate is coplanar.... Agent: North America Intellectual Property Corporation

20090072326 - Ultra high voltage mos transistor device: An ultra high voltage MOS transistor device includes a substrate; a source region formed in the substrate; a first doping region formed in the substrate and bordering upon the source region; a first ion well encompassing the source region and the first doping region; a gate oxide layer formed on... Agent: North America Intellectual Property Corporation

20090072328 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device includes forming a first gate insulating film over a cell region of a semiconductor substrate. A conductive layer is formed over the semiconductor substrate including the cell region and a peripheral region. An oxidizing process is performed on the conductive layer to form... Agent: Townsend And Townsend And Crew, LLP

20090072329 - Semiconductor device and method of manufacturing the same: The semiconductor device includes a field effect transistor comprising a gate insulating film having the film thickness of 1 nm or more, wherein at least an area of the gate insulating film which extending up to 1 nm from the side of the semiconductor layer in the thickness direction thereof... Agent: Scully Scott Murphy & Presser, PC

20090072327 - Semiconductor storage device and method for manufacturing the same: [Means for Solving Problems] a semiconductor device fabricating method according to a first aspect of the invention, a method for fabricating a semiconductor storage device that operates by transferring charges through a gate insulating film formed between a semiconductor substrate and a gate electrode, includes a step for introducing an... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090072330 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090072331 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090072332 - System-in-package platform for electronic-microfluidic devices: The present invention relates to an integrated electronic-micro fluidic device an integrated electronic-micro fluidic device, comprising a semiconductor substrate (106) on a first (122) support, an electronic circuit (102, 104) on a first semiconductor-substrate side of the semiconductor substrate, and a signal interface structure to an external device. The signal... Agent: Philips Intellectual Property & Standards

20090072334 - Semiconductor device, pre-mold package, and manufacturing method therefor: A pre-mold package of a semiconductor device is constituted of a lead frame, a mold resin having a box-like shape constituted of a side wall and a bottom for mounting at least one semiconductor chip, and a cover composed of a conductive material. The lead frame includes a shield plate... Agent: Pillsbury Winthrop Shaw Pittman LLP

20090072333 - Sensor array having a substrate and a housing, and method for manufacturing a sensor array: In a sensor array having a substrate and a housing, and in a method for manufacturing a sensor array are proposed, the housing substantially completely surrounds the substrate in a first substrate area, the housing is provided in a second substrate area at least partly open via an opening, and... Agent: Kenyon & Kenyon LLP

20090072335 - Image sensor package: An image sensor package is provided. The image sensor package may include a semiconductor substrate, an image sensor stacked over an upper surface of the semiconductor substrate, a pad formed on a lower surface of the semiconductor substrate and electrically connected with the image sensor, and a passive component formed... Agent: Staas & Halsey LLP

20090072336 - Solid-state imaging device and method for manufacturing thereof as well as driving method of solid-state imaging device: A solid-state imaging device having an electrode for reading a signal charge is provided on one side of a light-receiving sensor portion constituting a pixel; a predetermined voltage signal applied to a light-shielding film formed to cover an image pickup area except the light-receiving sensor portion; a second-conductivity-type semiconductor area... Agent: Sonnenschein Nath & Rosenthal LLP

20090072337 - Image sensors including photoelectric converting units having multiple impurity regions and methods of forming the same: An image sensor includes a semiconductor layer, and first and second photoelectric converting units including first and second impurity regions in the semiconductor layer that are spaced apart from each other and that are at about an equal depth in the semiconductor layer, each of the impurity regions including an... Agent: Myers Bigel Sibley & Sajovec

20090072338 - Semiconductor photodetector and manufacturing method therefor: A method for manufacturing a semiconductor photodetector includes: forming an insulating film on a semiconductor substrate; forming an electrode on and in contact with a predetermined area of a surface of the semiconductor substrate; forming a resist on the insulating film after forming the electrode; forming a power supply layer... Agent: Leydig Voit & Mayer, Ltd

20090072339 - Semiconductor device having diode and igbt: A semiconductor device includes: a semiconductor substrate including a first conductive type layer; a plurality of IGBT regions, each of which provides an IGBT element; and a plurality of diode regions, each of which provides a diode element. The plurality of IGBT regions and the plurality of diode regions are... Agent: Posz Law Group, PLC

20090072340 - Edge termination for high voltage semiconductor device: High voltage semiconductor devices with high-voltage termination structures are constructed on lightly doped substrates. Lightly doped p-type substrates are particularly prone to depletion and inversion from positive charges, degrading the ability of associated termination structures to block high voltages. To improve the efficiency and stability of termination structures, second termination... Agent: Marger Johnson & Mccollom, P.C.

20090072341 - Buried low-resistance metal word lines for cross-point variable-resistance material memories: Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and... Agent: Schwegman, Lundberg & Woessner/micron

20090072343 - Semiconductor device and electronic appliance: A high-performance semiconductor device using an SOI substrate in which a low-heat-resistance substrate is used as a base substrate. Further, a high-performance semiconductor device formed without using chemical polishing. Further, an electronic device using the semiconductor device. An insulating layer over an insulating substrate, a bonding layer over the insulating... Agent: John F. Hayden Fish & Richardson P.c

20090072342 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device includes forming an ion implanted region on a semiconductor substrate in a cell/core region. The semiconductor substrate is selectively etched to form a recess. The recess exposes a boundary of the ion implanted region. The ion implanted region exposed at the bottom of... Agent: Townsend And Townsend And Crew, LLP

20090072344 - Semiconductor device and method of fabricating the same: A method for fabricating a semiconductor device includes forming an insulating pattern over a semiconductor substrate. An epitaxial growth layer is formed over the semiconductor substrate exposed by the insulating pattern to fill the insulating pattern with the epitaxial growth layer. A recess gate having a recess channel is formed.... Agent: Townsend And Townsend And Crew, LLP

20090072347 - Semiconductor constructions, and electronic systems: The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H2, with the H2 being present to a concentration of from about 2% to about 40%, by volume. An... Agent: Wells St. John P.s.

20090072345 - Semiconductor device and method of producing the same: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from... Agent: Mcdermott Will & Emery LLP

20090072346 - Semiconductor device and method of producing the same: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from... Agent: Mcdermott Will & Emery LLP

20090072348 - Integrated circuits; methods for manufacturing an integrated circuit and memory module: Embodiments of the present invention relate generally to integrated circuits, to methods for manufacturing an integrated circuit and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a programmable arrangement. The programmable arrangement includes a substrate, at least one first electrode disposed in... Agent: Slater & Matsil, L.L.P.

20090072349 - Semiconductor device and method of manufacturing the same: Example embodiments provide a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may include a lower electrode including a first lower electrode and a second lower electrode, and the second lower electrode may be formed on at least a part of the... Agent: Harness, Dickey & Pierce, P.L.C

20090072350 - Semiconductor devices having a contact plug and fabrication methods thereof: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact... Agent: Myers Bigel Sibley & Sajovec

20090072352 - Gallium nitride bulk crystals and their growth method: A gallium nitride crystal with a polyhedron shape having exposed {10-10} m-planes and an exposed (000-1) N-polar c-plane, wherein a surface area of the exposed (000-1) N-polar c-plane is more than 10 mm2 and a total surface area of the exposed {10-10} m-planes is larger than half of the surface... Agent: Gates & Cooper LLP Howard Hughes Center

20090072353 - Method for increasing the area of non-polar and semi-polar nitride substrates: A method for fabricating a high quality freestanding nonpolar and semipolar nitride substrate with increased surface area, comprising stacking multiple films by growing the films one on top of each other with different and non-orthogonal growth directions.... Agent: Gates & Cooper LLP Howard Hughes Center

20090072351 - Method of manufacturing a semiconductor device and semiconductor device obtained by means of said method: The invention relates to a method of manufacturing a semiconductor device (10) comprising a substrate (11) and a semiconductor body (12) in which at least one semiconductor element (1) is formed, wherein on the substrate (11) a semiconductor layer (2) is formed comprising a mixed crystal of silicon and germanium,... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090072354 - Semiconductor device and method for fabricating the same: The semiconductor device includes an upper electrode line structure and a lower electrode line structure provided over a semiconductor substrate. The semiconductor device also includes a guard contact having a first portion and a second portion. The guard contact is disposed between the upper electrode line structure and the lower... Agent: Townsend And Townsend And Crew, LLP

20090072355 - Dual shallow trench isolation structure: A protective dielectric layer is formed on a first shallow trench having straight sidewalls, while exposing a second shallow trench. An oxidation barrier layer is formed on the semiconductor substrate. A resist is applied and recessed within the second shallow trench. The oxidation barrier layer is removed above the recessed... Agent: Scully, Scott, Murphy & Presser, P.C.

20090072356 - High-heat-resistant semiconductor device: In a wide gap semiconductor device of SiC or the like used at a temperature of 150 degrees centigrade or higher, the insulation characteristic of a wide gap semiconductor element is improved and a high-voltage resistance is achieved. For these purposes, a synthetic high-molecular compound, with which the outer surface... Agent: Crowell & Moring LLP Intellectual Property Group

20090072357 - Integrated shielding process for precision high density module packaging: An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a plurality of modules (30-33) to a process carrier (10) using a double side adhesive tape (12) before encapsulating the modules with a molding compound (16), and then forming shielding via ring... Agent: Hamilton & Terrile, LLP - Freescale

20090072358 - Semiconductor integrated circuit package, printed circuit board, semiconductor apparatus, and power supply wiring structure: A semiconductor integrated circuit package, a printed circuit board, a semiconductor apparatus, and a power supply wiring structure that allow attainment of stable power source and ground wiring without causing resonance even in a high-frequency bandwidth are provided. In an interior portion of the package, a power source wiring and... Agent: Hogan & Hartson L.L.P.

20090072359 - Stacked synchronous buck converter: A multichip module buck converter 10 has a high side power mosfet 12, a low side power mosfet 22 and a pre-molded leadframe 40 between the two mosfets for connecting the source of mosfet 12 to the drain of mosfet 22. Clips 14, 16, 18 and 26 carry the source,... Agent: Hiscock & Barclay, LLP

20090072360 - Molded semiconductor device including ic-chip covered with conductor member: A semiconductor device according to the present invention includes a conductor member, an IC-chip and leads, all molded together with a resin mold. The conductor member is composed of a base portion on which the IC-chip is mounted, a cover portion for covering a functioning surface of the IC-chip, and... Agent: Posz Law Group, PLC

20090072361 - Multi-chip stacked package structure: A multi-chip stacked package structure, comprising: a lead-frame having a top surface a back surface, the inner leads comprising a plurality of first inner leads and a plurality of second inner leads in parallel; a first chip fixedly connected to the back surface of the lead-frame, and the first chip... Agent: Sinorica, LLC

20090072362 - Thermal enhanced upper and dual heat sink exposed molded leadless package: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar... Agent: Hiscock & Barclay, LLP

20090072366 - Integrated circuit package system with dual connectivity: An integrated circuit package system includes: forming a die-attach paddle, a terminal pad, and an external interconnect with the external interconnect below the terminal pad; connecting an integrated circuit die with the terminal pad and the external interconnect; and forming an encapsulation, having a first side and a second side... Agent: Law Offices Of Mikio Ishimaru

20090072365 - Integrated circuit package system with external interconnects at high density: An integrated circuit package system includes: connecting an integrated circuit die and external interconnects; forming an encapsulation over the integrated circuit die and a portion of the external interconnects; and forming an isolation hole between the external interconnects and into a side of the encapsulation exposing the external interconnects.... Agent: Law Offices Of Mikio Ishimaru

20090072364 - Integrated circuit package system with leads separated from a die paddle: An integrated circuit package system is provided including forming a leadframe having a frame and a die paddle having leads thereon. The leads are held with respect to the die paddle. The leads are separated from the die paddle, and a die is attached to the die paddle. Bond wires... Agent: Law Offices Of Mikio Ishimaru

20090072363 - Integrated circuit package-in-package system with leads: An integrated circuit package-in-package system includes: forming an integrated circuit package system including: connecting a first integrated circuit die and a lead, and forming an inner encapsulation covering the first integrated circuit die and a portion of the lead; mounting a second integrated circuit die to the integrated circuit package... Agent: Law Offices Of Mikio Ishimaru

20090072367 - Leadframe: Particular embodiments of the present invention provide a leadframe suitable for use in packaging IC dice that enables stress reduction in and around the die, die attach material, die attach pad and mold interfaces. More particularly, various leadframes are described that include recesses in selected regions of the top surface... Agent: Beyer Law Group LLP/ Nsc

20090072370 - Multilayer wiring substrate, method of manufacturing the same, and semiconductor device: There is provided a multilayer wiring substrate on which at least one semiconductor element is mounted. The multilayer wiring substrate includes: a baseboard; a first wiring layer formed on the baseboard and having a plurality of first wiring portions; an insulating layer formed on the baseboard; a second wiring layer... Agent: Drinker Biddle & Reath (dc)

20090072368 - Package for monolithic compound semiconductor (csc) devices for dc to dc converters: A multichip module defining a dc to dc converter employs a monolithic chip containing at least two III-nitride switches (a monolithic CSC chip) mounted on a conductive lead frame. The CSC chip is copacked with an IC driver for the switches and with the necessary passives. The module defines a... Agent: Ostrolenk Faber Gerb & Soffen

20090072369 - Semiconductor device: Provided is a semiconductor device. In the semiconductor device, a rectangular header with two mounting regions is folded, and two semiconductor chips are then fixed respectively to the mounting regions facing each other. Thereby, a stacked structure of the semiconductor chips is achieved while a mounting area of a package... Agent: Morrison & Foerster LLP

20090072371 - Methods and articles incorporating local stress for performance improvement of strained semiconductor devices: A packaged semiconductor device (450) includes a semiconductor chip (400) having at least one selectively thinned substrate (cavity) region (410). A package (460) is provided for mounting, enclosing and electrically connecting the chip (400) to the outside world, and structure for applying external stress (470) to induce strain in the... Agent: Akerman Senterfitt

20090072372 - Planar array contact memory cards: A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having a plurality of connectors, a plurality of memory devices coupled to the card via a first portion of... Agent: Harrington & Smith, PC

20090072376 - Carrier structure stacking system and method: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC and the upper shoulder of leads of a lower IC while conductive transits that implement stacking-related intra-stack connections between the constituent... Agent: Fish & Richardson P.C.

20090072374 - Electric device, stack of electric devices, and method of manufacturing a stack of electric devices: According to one embodiment of the present invention, an electric device includes: a top surface and a bottom surface; a contact hole extending from the top surface through the device to the bottom surface; a conductive sealing element which seals the contact hole at or near the bottom surface; a... Agent: Slater & Matsil, L.L.P.

20090072375 - Integrated circuit package system with multi-chip module: An integrated circuit package system with multi-chip module is provided including: providing an upper substrate having an upper chip thereon; positioning a lower chip under the upper chip, the lower chip having bottom interconnects thereon; encapsulating the upper chip and the lower chip with a chip encapsulant on the upper... Agent: Law Offices Of Mikio Ishimaru

20090072373 - Packaged integrated circuits and methods to form a stacked integrated circuit package: Packaged integrated circuits and methods to form a thermal stacked integrated circuit package are disclosed. A disclosed method comprises attaching a first integrated circuit to at least one of a plurality of pads of a substrate, mounting a second integrated circuit above the first integrated circuit, placing a heat conductor... Agent: Texas Instruments Incorporated

20090072377 - Integrated circuit package system with delamination prevention structure: An integrated circuit package system includes: mounting an integrated circuit die over a carrier; attaching a delamination prevention structure over the integrated circuit die; and encapsulating the delamination prevention structure and the integrated circuit die.... Agent: Law Offices Of Mikio Ishimaru

20090072378 - Memory device system with stacked packages: An integrated circuit package system includes: providing a base package of an elongated rectangular-box shape containing first electrical circuitry and including: forming a rectangular contact strip on and adjacent to a first end of the base package; and forming a base contact pad on and adjacent to a second end... Agent: Law Offices Of Mikio Ishimaru

20090072380 - Microelectromechanical device packages with integral heaters: A microelectromechanical device package with integral a heater and a method for packaging the microelectromechanical device are disclosed in this invention. The microelectromechanical device package comprises a first package substrate and second substrate, between which a microelectromechanical device, such as a micromirror array device is located. In order to bonding... Agent: Texas Instruments Incorporated

20090072379 - Semiconductor device: A semiconductor device is disclosed. One embodiment includes a carrier, a semiconductor chip attached to the carrier, a first conducting line having a first thickness and being deposited over the semiconductor chip and the carrier and a second conducting line having a second thickness and being deposited over the semiconductor... Agent: Dicke, Billig & Czaja

20090072381 - Semiconductor device with double-sided electrode structure and its manufacturing method: According to the present invention, a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring, and an LSI chip is accommodated within the recess portion. Wiring traces are formed on the upper surface of a resin which seals the... Agent: Mcglew & Tuttle, PC

20090072382 - Microelectronic package and method of forming same: A microelectronic package includes a carrier (110, 210, 410, 1110) having a first surface (111, 211, 411, 1111) and an opposing second surface (112, 212, 412, 1112), an adhesive layer (120, 220, 221, 520, 1220, 1221) at the first surface of the carrier, a die (130, 230, 231, 530, 531,... Agent: Intel Corporation C/o Intellevate, LLC

20090072384 - Packaging substrate having heat-dissipating structure: Provided is a packaging substrate with a heat-dissipating structure, including a core layer with a first surface and an opposite second surface having a first metal layer and a second metal layer respectively. Portions of the first metal layer are exposed from a second cavity penetrating the core layer and... Agent: Edwards Angell Palmer & Dodge LLP

20090072383 - Semiconductor device, electronic component module, and method for manufacturing semiconductor device: A semiconductor element is provided with a heat dissipating path defined by a non-through hole in a first principal surface and that is filled with a conductive material. The semiconductor element is bonded to a heat sink with the conductive material disposed therebetween. Solder can be used as the conductive... Agent: Murata Manufacturing Company, Ltd. C/o Keating & Bennett, LLP

20090072385 - Electronic assemblies providing active side heat pumping and related methods and structures: An electronic assembly may include a packaging substrate, an integrated circuit (IC) semiconductor chip, a plurality of metal interconnection structures, and a thermoelectric heat pump. The integrated circuit (IC) semiconductor chip may have an active side including input/output pads thereon and a back side opposite the active side, and the... Agent: Myers Bigel Sibley & Sajovec

20090072386 - Semiconductor package and semiconductor package assembly: A semiconductor package includes a main body having a semiconductor device accommodating portion accommodating a basic circuit including a semiconductor device, external connection terminal members protruding outside the main body, and a cooling structure reducing heat generated by the device from the main body. The cooling structure includes a coolant... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090072387 - Curvilinear heat spreader/lid with improved heat dissipation: A heat spreader or lid for a microelectronic package, in which the heat spreader has an underside surface that includes at least one curvilinear contour, in which the curvilinear contour is selected from at least one positive or protruding curvilinear feature, at least one negative or recessed curvilinear feature, and... Agent: Connolly Bove Lodge & Hutz LLP

20090072388 - Semiconductor device with inductor: One or more embodiments are directed to a semiconductor structure, comprising: a support; a semiconductor chip at least partially embedded within the support; and an inductor electrically coupled to the chip, at least a portion of the inductor overlying the support outside the lateral boundary of the chip.... Agent: Infineon Technologies Ag Patent Department

20090072389 - Structure and method for forming a capacitively coupled chip-to-chip signaling interface: A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second semiconductor device spaced apart from the first device, a dielectric layer interposed between the first device and the second device, a... Agent: Karen Henckel Dorsey & Whitney LLP

20090072390 - Semiconductor apparatus and fabrication method thereof: A semiconductor apparatus (1) includes a semiconductor device (2), a first lead (3) having an electrode for connection with a source electrode (S) of the semiconductor device (2), a second lead (4) having an electrode for connection with a gate electrode (G) of the semiconductor device (2), a third lead... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090072396 - Method of forming low stress multi-layer metallurgical structures and high reliable lead free solder termination electrodes: Techniques for manufacturing a bond pad structure are provide. A method includes providing a substrate. A metal pad and passivation layer are formed over the substrate. The passivation layer includes an opening to expose a portion of the metal pad. A first film is deposited at least over the exposed... Agent: Townsend And Townsend And Crew, LLP

20090072395 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a semiconductor element, a lead, and a gold wire electrically connecting an electrode of the semiconductor element and the lead. In the semiconductor device, the gold wire is covered with a metal and is a continuous film formed by plating.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090072394 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor chip, a bump electrode, a molding portion, a redistribution layer and an outer connection electrode. The bump electrode is provided on an upper face of the semiconductor chip. The molding portion encapsulates an entire side face of the semiconductor chip and seals the bump... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090072391 - Structurally-enhanced integrated circuit package and method of manufacture: A chip scale integrated circuit package includes an integrated circuit chip which has a first face and a second face. A plurality of pillar bumps are formed on the first face of the integrated circuit chip. An encapsulant material encapsulates the sides and the first face of the integrated circuit... Agent: Sughrue Mion, PLLC

20090072393 - Structure and method for fabricating flip chip devices: A solder bump structure and an under bump metallurgical structure. An upper surface of a semiconductor substrate comprises a first conductive pad (200) disposed thereon. A passivation layer (202) overlies the upper surface. A second conductive pad (212) is disposed in an opening (204) in the passivation layer and in... Agent: Agere Lerner, David Et Al.

20090072392 - Techniques for forming solder bump interconnects: Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of... Agent: Ryan, Mason & Lewis, LLP

20090072397 - Redistribution layer for wafer-level chip scale package and method therefor: In an example embodiment, there is a method for packaging an integrated circuit device (IC) having a circuit pattern (305) in a wafer-level chip-scale (WLCS) package (300). The method includes depositing a metal layer (5, 10, 15) on a first dielectric layer (315) and filling (20) in bond pad openings... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090072399 - semiconductor mounting bonding wire: There is provided a bonding wire which does not cause a leaning failure or the like. A semiconductor mounting bonding wire has a breaking elongation of 7 to 20%, and stress at 1% elongation is greater than or equal to 90% of a tensile strength and is less than or... Agent: Darby & Darby P.C.

20090072398 - Integrated circuit, circuit system, and method of manufacturing: An integrated circuit, a circuit system and method of manufacturing such is disclosed. One embodiment provides a circuit chip including a first contact field on a chip surface; and an insulating layer on the chip surface. The insulating layer includes a flexible material. A contact pillar is coupled to the... Agent: Dicke, Billig & Czaja

20090072400 - Contact forming in two portions and contact so formed: Methods of forming a contact in two or more portions and a contact so formed are disclosed. One method includes providing a device including a silicide region; and forming a contact to the silicide region by: first forming a lower contact portion to the silicide region through a first dielectric... Agent: Hoffman Warnick LLC

20090072401 - Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer: Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The... Agent: Scully, Scott, Murphy & Presser, P.C.

20090072402 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device comprising forming a metal layer on a semiconductor substrate, patterning the metal layer to form a plurality of metal wires having side surfaces, forming spacers on both side surfaces of each of the metal wires, and forming an insulating layer between the spacers... Agent: Marshall, Gerstein & Borun LLP

20090072403 - Wiring structure, semiconductor device and manufacturing method thereof: A semiconductor device with a high-strength porous modified layer having a pore size of 1 nm or less, which is formed, in a multilayer wiring forming process, by forming a via hole and a wiring trench in a via interlayer insulating film and a wiring interlayer insulting film and then... Agent: Mcginn Intellectual Property Law Group, PLLC

20090072404 - Semiconductor device and method of manufacturing same: A highly reliable semiconductor device in which connection reliability is assured at very small vias comprises: a semiconductor substrate; a first wiring structure placed on the semiconductor substrate and having one or more first wiring layers, one or more insulating layers and a first via; a second wiring structure placed... Agent: Young & Thompson

20090072405 - Semiconductor device: The semiconductor device according to the present invention includes: a first wire made of a material mainly composed of Cu; a second wire made of a material mainly composed of Cu; an interlayer dielectric film formed between the first wire and the second wire; a via, made of a material... Agent: Rabin & Berdo, PC

20090072406 - Interconnect structure with improved electromigration resistance and method of fabricating same: An interconnect structure in which the electromigration resistance thereof is improved without introducing a gouging feature within the interconnect structure is provided. The interconnect structure includes a metallic interfacial layer that is at least horizontally present at the bottom of an opening located within a second dielectric material that is... Agent: Scully, Scott, Murphy & Presser, P.C.

20090072407 - Thermo-compression bonded electrical interconnect structure and method: An electrical structure and method for forming. The electrical structure includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect... Agent: Schmeiser, Olsen & Watts

20090072408 - Connecting and bonding adjacent layers with nanostructures: An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same.... Agent: Fish & Richardson P.C.

20090072409 - Interconnect structures incorporating air-gap spacers: A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures... Agent: Robert J. Eichelburg, Esq. Hodafel Building, Suite 200

20090072410 - Microelectronic circuit structure with layered low dielectric constant regions: The circuit structure includes at least two generally parallel conductor structures, and a plurality of substantially horizontal layers of layer dielectric material interspersed with substantially horizontally extending relatively low dielectric constant (low-k) volumes. The substantially horizontal layers and the substantially horizontally extending volumes are generally interposed between the at least... Agent: Ryan, Mason & Lewis, LLP

20090072411 - Semiconductor device with conductive interconnect: One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip; a conductive layer comprising at least a first conductive pathway and a second conductive pathway spacedly disposed from the first conductive pathway, the first conductive pathway electrically coupled to the chip, at least a portion of... Agent: Infineon Technologies Ag Patent Department

20090072414 - Bonding method of semiconductor and laminated structure fabricated thereby: A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090072412 - Integrated circuit package system with package encapsulation having recess: An integrated circuit package system includes: forming an external interconnect; connecting an integrated circuit die and the external interconnect; forming a package encapsulation, having a recess, covering the integrated circuit die with a portion of the external interconnect exposed by the recess; and connecting an integrated circuit device and the... Agent: Law Offices Of Mikio Ishimaru

20090072413 - Semiconductor device: A semiconductor device and method is disclosed. One embodiment provides a substrate and a first semiconductor chip applied over the substrate. A first electrically conductive layer is applied over the substrate and the first semiconductor chip. A first electrically insulating layer is applied over the first electrically conductive layer. A... Agent: Dicke, Billig & Czaja

20090072415 - Integrated circuit device having a gas-phase deposited insulation layer: An integrated circuit device includes a semiconductor device having an integrated circuit. A gas-phase deposited insulation layer is disposed on the semiconductor device, and a conducting line is disposed over the gas-phase deposited insulation layer.... Agent: Dicke, Billig & Czaja

20090072416 - Semiconductor device, and manufacturing method of semiconductor device: In a technique connecting between bonding pads of semiconductor chips, contact between wires is prevented. A semiconductor device of the present embodiment is provided with a semiconductor chip 1 in which a plurality of bonding pads 3 are arranged in line, a semiconductor chip 2 in which a plurality of... Agent: Mcginn Intellectual Property Law Group, PLLC

20090065757 - Nonvolatile memory element: A nonvolatile memory element in which Rb1-yMbyMnO3 having higher insulation properties than Ra1-xMaxMnO3 is inserted between the Ra1-xMaxMnO3 and a metal having a shallow work function or a low electronegativity in order to improve resistance change properties and switching properties and to control the resistance change properties. (In the formulas,... Agent: Nixon & Vanderhye, PC

20090065758 - Phase change memory array and fabrication thereof: A phase change memory array is disclosed, comprising a first cell having a patterned phase change layer, and a second cell having a patterned phase change layer, wherein the patterned phase change layer of the first cell and the patterned phase change layer of the second cell are disposed at... Agent: Quintero Law Office, PC

20090065760 - Resistive memory devices and methods of forming resistive memory devices: Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact... Agent: Myers Bigel Sibley & Sajovec

20090065759 - Semiconductor device and method for fabricating the same: A non-volatile memory semiconductor device and a method for fabricating the same are disclosed. The semiconductor device includes a PN junction diode formed over a semiconductor substrate. Insulating films may be formed over the PN junction diode and patterned to have via holes. A resistive random access memory including a... Agent: Sherr & Vaughn, PLLC

20090065761 - Programmable fuse/non-volatile memory structures in beol regions using externally heated phase change material: A programmable phase change material (PCM) structure includes a heater element formed at a BEOL level of a semiconductor device, the BEOL level including a low-K dielectric material therein; a first via in electrical contact with a first end of the heater element and a second via in electrical contact... Agent: Cantor Colburn LLP-ibm Yorktown

20090065762 - Light emitting diode with improved structure: A light emitting diode (LED) for minimizing crystal defects in an active region and enhancing recombination efficiency of electrons and holes in the active region includes non-polar GaN-based semiconductor layers grown on a non-polar substrate. The semiconductor layers include a non-polar N-type semiconductor layer, a non-polar P-type semiconductor layer, and... Agent: H.c. Park & Associates, PLC

20090065763 - Light-emitting semiconductor device: The present invention discloses a light-emitting semiconductor device, includes: a first electrode that is made of a high reflective metal; a second electrode; a tunnel junction layer coupling to the first electrode through a first ohmic contact and generating a tunnel current by applying a reverse bias voltage between the... Agent: Yokoi & Company U.s.a., Inc.

20090065764 - Methods and devices for forming nanostructure monolayers and devices including such monolayers: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).... Agent: Quine Intellectual Property Law Group, P.C.

20090065765 - Carbon nanotube grown on catalyst and manufacture method: A method for manufacturing carbon nanotubes includes the steps of: (a) depositing catalytic fine particles containing Al—Fe, Zr—Co or Hf—Co on a base body; and (b) growing carbon nanotubes on the catalytic fine particles deposited on the base body.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090065766 - Diketopyrrolopyrrole-based polymers: m

20090065770 - Fused ring compound and method for producing same, polymer, organic thin film containing those, and organic thin film device and organic thin film transistor comprising such organic thin film: wherein R11 and R12 each independently represent a hydrogen atom, an alkyl group having 1 to 20 carbon atoms, an alkoxy group, an alkylthio group, an alkylamino group, an alkoxycarbonyl group, an optionally substituted aryl group having 6 to 60 carbon atoms, an optionally substituted heterocyclic group having 4 to... Agent: Sughrue Mion, PLLC

20090065768 - Memory element and semiconductor device: To provide a memory element, a memory device, and a semiconductor device, which can be easily manufactured at low cost; are nonvolatile and data-rewritable; and have preferable switching properties and low operating voltage. A memory element of the invention includes a first conductive layer, a second conductive layer facing the... Agent: Eric Robinson

20090065767 - Multiple conductive layer tft: The present invention relates to a multiple layer pixel architecture for an active matrix display in which a common bus line is formed on a metal level which is separate from that on which the gate electrodes of the TFTs are formed. A multilayer electronic structure adapted to solution deposition,... Agent: Knobbe Martens Olson & Bear LLP

20090065769 - Semiconductor device amd method for manufacturing the same: It is an object of the present invention to provide a technique in which a high-performance and high reliable memory device and a semi-conductor device provided with the memory device are manufactured at low cost with high yield. The semiconductor device includes an organic compound layer including an insulator over... Agent: Eric Robinson

20090065771 - Field effect transistor using oxide film for channel and method of manufacturing the same: The present invention provides a field effect transistor including an oxide film as a semiconductor layer, wherein the oxide film includes one of a source part and a drain part to which one of hydrogen and deuterium is added.... Agent: Fitzpatrick Cella Harper & Scinto

20090065772 - Apparatus for detecting pattern alignment error: An apparatus for detecting pattern alignment error includes a first conductive pattern disposed over a first insulation member with a power source applied to the first conductive pattern; a second insulation member for covering the first conductive pattern; a second conductive pattern disposed on the second insulation member; a conductive... Agent: Ladas & Parry LLP

20090065774 - Multilayer semiconductor device: The present invention is applied to a multilayer semiconductor device including a plurality of layered semiconductor chips. At least one of the plurality of layered semiconductor chips comprises a pad that is not connected to any external circuit terminal of the multilayer semiconductor device. The multilayer semiconductor device further comprises... Agent: Sughrue Mion, PLLC

20090065773 - Semiconductor device: Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090065775 - Test-key for checking interconnect and corresponding checking method: A test key for checking an interconnect structure is described, including a contiguous metal line and multiple conductive plugs on the contiguous metal line, wherein one end of each plug contacts with the contiguous metal line. The other end of at least one plug is not connected to any conductor.... Agent: Jianq Chyun Intellectual Property Office

20090065776 - Print processing for patterned conductor, semiconductor and dielectric materials: Embodiments relate to printing features from an ink containing a material precursor. In some embodiments, the material includes an electrically active material, such as a semiconductor, a metal, or a combination thereof. In another embodiment, the material includes a dielectric. The embodiments provide improved printing process conditions that allow for... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090065778 - Active matrix substrate, display apparatus, and television receiver: An active matrix substrate of the present invention is arranged so that each pixel area has a transistor and a capacity electrode which is able to function as an electrode of a capacity. The active matrix substrate includes a conductor which is provided in a layer below the capacity electrode... Agent: Nixon & Vanderhye, PC

20090065777 - Display device and manufacturing method therefor: In a display device of the present invention which forms thin film transistors on a substrate, the thin film transistor comprises: a silicon nitride film which is formed on the substrate in a state that the silicon nitride film covers a gate electrode; a silicon oxide film which is selectively... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090065779 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a silicon substrate; a gate insulation film formed on the silicon substrate; and a gate electrode formed on the gate insulation film; wherein the gate electrode has a first doped polysilicon film formed on the gate insulation film, and a second doped polysilicon film formed on... Agent: Scully Scott Murphy & Presser, PC

20090065780 - Electro-optical device and electronic apparatus: An electro-optical device includes a contact hole with a channel-region adjacent portion next to the channel region of the semiconductor film and a first extending portion that extends from the channel-region adjacent portion along the first partial region of the semiconductor film when viewed in plan.... Agent: Advantedge Law Group, LLC

20090065781 - Touch substrate and electro-wetting display device having touch control function: A touch substrate includes a transparent substrate having a first surface and a second surface facing the first surface, a plurality of thin film transistor elements disposed on the second surface, and a capacitance touch structure. The capacitance touch structure includes a plurality of parallel first conductive electrodes disposed on... Agent: Wei Te Chung Foxconn International, Inc.

20090065784 - Display device and manufacturing method thereof: A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device in high yield are proposed. In a display device including a channel stop thin film transistor with an inverted-staggered structure, the channel stop thin film transistor with... Agent: Nixon Peabody, LLP

20090065783 - Electro-optical device and electronic apparatus: An electro-optical device includes a semiconductor layer, a first insulating film, a second insulating film, and a gate electrode. The first insulating film is formed in an island shape so as to cover a first junction region of the semiconductor layer. The second insulating film is formed in an island... Agent: Advantedge Law Group, LLC

20090065782 - Field shield dielectric as a mask during semiconductor ink jet printing: A display device and method for fabricating includes patterning a field shield dielectric layer to expose conductors and form a cavity over the conductors. InkJet printing a semiconductor material fills a portion of the cavity in contact with the conductors. An insulation material is deposited on the semiconductor material. A... Agent: Leydig Voit & Mayer, Ltd

20090065787 - Compound semiconductor structure: A method for manufacturing a compound semiconductor structure, includes (a) selecting a conductive SiC substrate in accordance with color and resistivity and (b) epitaxially growing a GaN series compound semiconductor layer on the selected conductive SiC substrate. The step (a) preferably selects a conductive SiC substrate whose main color is... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090065785 - Iii-nitride power semiconductor device: A power semiconductor device that includes common conduction regions, charge compensation regions, each adjacent a respective common conduction region, and a stand off region over the common conduction regions and charge compensation regions.... Agent: Ostrolenk Faber Gerb & Soffen

20090065786 - Process for producing thin nitride film on sapphire substrate and thin nitride film producing apparatus: A method for growing a nitride thin film on a sapphire substrate, in which using no resists, miniaturization can be accomplished while relieving vexatious complication of the process; and a relevant device using nitride thin film. There is provided a method for growing a nitride thin film on a sapphire... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090065788 - Semiconductor substrate with islands of diamond and resulting devices: Disclosed is a method of forming a substrate having islands of diamond (or other material, such as diamond-like carbon), as well as integrated circuit devices formed from such a substrate. A diamond island can form part of the thermal solution for an integrated circuit formed on the substrate, and the... Agent: Intel Corporation C/o Intellevate, LLC

20090065789 - Led chip package structure with high-efficiency light-emitting effect and method of packing the same: An LED chip package structure with high-efficiency light-emitting effect includes a substrate unit, a light-emitting unit, and a package colloid unit. The substrate unit has a substrate body, and a positive electrode trace and a negative electrode trace respectively formed on the substrate body. The light-emitting unit has a plurality... Agent: Rosenberg, Klein & Lee

20090065790 - Led chips having fluorescent substrates with microholes and methods for fabricating: Methods for fabricating semiconductor devices such as LED chips at the wafer level, and LED chips and LED chip wafers fabricated using the methods. An LED chip wafer according to the present invention comprises a plurality of LEDs on a wafer and a plurality of pedestals, each of which is... Agent: Koppel, Patrick & Heybl

20090065793 - Light emitting device: A light emitting device is disclosed herein. An embodiment of the light emitting device comprises a substrate and a reflector extending from the substrate. The reflector forms a cavity in conjunction with the substrate. A light emitter is located in the cavity. At least one first recessed portion is located... Agent: Kathy Manke Avago Technologies Limited

20090065794 - Light emitting diode device and manufacturing method therof: A light-emitting diode (LED) device and manufacturing methods thereof are provided, wherein the LED device comprises a substrate, a first type conductivity semiconductor layer, an active layer, a second type conductivity semiconductor layer, a transparent conductive oxide stack structure, a first electrode, and a second electrode. The first semiconductor layer... Agent: Bacon & Thomas, PLLC

20090065792 - Method of making an led device having a dome lens: A method of making a light emitting device is disclosed herein. The method includes providing an LED die and dispensing a photopolymerizable composition to form a photopolymerizable dome lens, wherein the photopolymerizable composition is optically coupled to the LED die. The photopolymerizable dome lens may be formed by the photopolymerizable... Agent: 3m Innovative Properties Company

20090065791 - White light led with multiple encapsulation layers: Light-emitting semiconductor devices with multiple encapsulation layers having more uniform white light when compared to conventional light-emitting devices and methods for producing the same are provided. The uniformity of the emitted white light may be quantified by comparing correlated color temperature (CCT) variations between devices, where embodiments of the present... Agent: Patterson & Sheridan, L.L.P.

20090065799 - Light emitting diode package: The present invention relates to a light emitting diode package, and provides a light emitting diode package employing a thermoelectric element therein. The light emitting diode package of the present invention is constructed such that the thermoelectric element is coupled to a housing or formed of a substrate itself so... Agent: H.c. Park & Associates, PLC

20090065797 - Light emitting unit and liquid crystal display device using the same: A light emitting unit capable of widely adjusting brightness or size, and a liquid crystal display device using the same are disclosed. The light emitting unit includes a circuit board including circuit lines having a plurality of connecting members, and a plurality of unit module connected to the connecting members... Agent: Mckenna Long & Aldridge LLP

20090065798 - Packaging technique for the fabrication of polarized light emitting diodes: A polarized light emitting diode (LED) includes a marker indicating a polarization direction. A package for the LED also includes a marker indicating the polarization direction. The markers on the LED and package are used for mutual alignment, wherein the LED is attached in a favorable orientation with respect to... Agent: Gates & Cooper LLP Howard Hughes Center

20090065796 - Surface mount light emitting apparatus: A surface mount LED apparatus is provided which can prevent separation of the surface of an LED chip from a sealing resin portion. Patterned circuits on a substrate are provided with a device mounting region and a wire bond region, and an increased-thickness portion having a thickness 1.6 times or... Agent: Cermak Kenealy & Vaidya, LLP

20090065795 - Transparent conductive film on p-type layer for gan-based led and method for fabricating the same: The present disclosure provides a transparent conductive film on P-type layer of GaN-based LED and a fabricating method thereof. The transparent conductive film is fabricated by Ni/ITO, Al/ITO or NiO/ITO. In one embodiment, the thickness of the Ni layer is 5 Å to 30 Å. The thickness of the Al... Agent: Rader, Fishman & Grauer PLLC

20090065800 - Optoelectronic component, device comprising a plurality of optoelectronic components, and method for the production of an optoelectronic component: Disclosed is an optoelectronic component (1) comprising a semiconductor function region (2) with an active zone (400) and a lateral main direction of extension, said semiconductor function region including at least one opening (9, 27, 29) through the active zone, and there being disposed in the region of the opening... Agent: Fish & Richardson P.C.

20090065801 - Surface plasmon polariton actuated transistors: A surface plasmon polaritron activated semiconductor device uses a surface plasmon wire that functions as an optical waveguide for fast communication of a signal and functions as a energy translator using a wire tip for translating the optical signal passing through the waveguide into plasmon-polaritron energy at a connection of... Agent: Carole A. Mulchinski, M1/040 The Aerospace Corporation,

20090065802 - Semiconductor device and manufacturing method of the same: Disclosed herein is a semiconductor device including: an element forming region of a semiconductor substrate isolated by an element isolating region formed in the semiconductor substrate; an insulating film formed on the semiconductor substrate; an opening portion formed in the insulating film to include a region to be selectively epitaxially... Agent: Sonnenschein Nath & Rosenthal LLP

20090065803 - Space-charge-free semiconductor and method: A semiconductor having a an n-type material and a p-type material, wherein the n-type material and p-type material are joined to form a space-charge-free p-n junction. The energy of the Fermi-level of the n-type material is equal to the energy of the Fermi-level of the p-type material. This allows for... Agent: Bond, Schoeneck & King, PLLC

20090065804 - Bipolar transistor with low resistance base contact and method of making the same: Embodiments of the present invention provide a bipolar transistor with low resistance base contact and method of manufacturing the same. The bipolar transistor includes an emitter, a collector, and an intrinsic base between the emitter and the collector. The intrinsic base extends laterally to an extrinsic base. The extrinsic base... Agent: Greenblum & Bernstein, P.L.C

20090065805 - Method and structure using a pure silicon dioxide hardmask for gate pattering for strained silicon mos transistors: A structure using pure silicon dioxide hard marsk for gate pattern. In an embodiment, the present invention provides a partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially... Agent: Townsend And Townsend And Crew, LLP

20090065806 - Mos transistor and fabrication method thereof: A MOS transistor and a fabrication method thereof are disclosed. The mobility of electrons or holes serving as charge carriers of the MOS transistor can be improved by forming a lattice stress-causing material in source/drain regions of a MOS transistor or by forming a gapping layer having a tensile stress... Agent: Sherr & Vaughn, PLLC

20090065807 - Semiconductor device and fabrication method for the same: The semiconductor device includes: a first MIS transistor formed on a first region of a first conductivity type in a semiconductor substrate; and a second MIS transistor formed on a second region of a second conductivity type in the semiconductor substrate. The first MIS transistor has a first gate insulating... Agent: Mcdermott Will & Emery LLP

20090065809 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device is provided in which a stress can be effectively applied from a semiconductor layer having a different lattice constant from a semiconductor substrate to a channel part, whereby carrier mobility can be improved and higher functionality can be achieved. In a semiconductor device 1 including a gate... Agent: Sonnenschein Nath & Rosenthal LLP

20090065808 - Semiconductor transistor having a stressed channel: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090065810 - Iii-nitride bidirectional switches: Bidirectional switches are described. The bidirectional switches include first and a second III-N based high electron mobility transistor. In some embodiments, the source of the first transistor is in electrical contact with a source of the second transistor. In some embodiments, the drain of the first transistor is in electrical... Agent: Fish & Richardson P.C.

20090065811 - Semiconductor device with ohmic contact and method of making the same: A semiconductor device with ohmic contact is provided with a method of making the same. In one embodiment, a method is provided for fabricating a semiconductor device. The method comprises providing a semiconductor structure with a N-type doped semiconductor contact layer, forming a platinum contact portion over the N-type doped... Agent: Tarolli, Sundheim, Covell & Tummino L.L.P.

20090065812 - Compound semiconductor substrate: Provides is a compound semiconductor substrate about which the thickness of its nitride semiconductor single crystal layer can be made large while the generation of cracks, crystal defects or the like is restrained in the nitride semiconductor single crystal layer. The substrate has a first intermediate layer 110 formed on... Agent: Foley And Lardner LLP Suite 500

20090065813 - Configuring structured asic fabric using two non-adjacent via layers: An application-specific integrated circuit (ASIC) is customized using two non-adjacent via layers. An array of logic cells, each including a plurality of logic devices, are arranged in a plurality of non-customized base layers. A first routing grid, which includes a first non-customized metal routing layer, a customized via layer, and... Agent: Tillman Wright, PLLC

20090065814 - Mos device with schottky barrier controlling layer: A semiconductor device is formed on a semiconductor substrate. The semiconductor device comprises a drain, an epitaxial layer overlaying the drain, and an active region. The active region comprises a body disposed in the epitaxial layer, having a body top surface, a source embedded in the body, extending from the... Agent: Van Pelt, Yi & James LLP

20090065815 - Solid-state imaging device and imaging apparatus: A solid-state imaging device includes a semiconductor substrate and a plurality of photoelectric conversion elements provided in the semiconductor substrate, wherein the plurality of photoelectric conversion elements include: effective photoelectric conversion elements which are photoelectric conversion elements for obtaining an imaging signal corresponding to light from a subject; and OB... Agent: Birch Stewart Kolasch & Birch

20090065816 - Modulating the stress of poly-crystaline silicon films and surrounding layers through the use of dopants and multi-layer silicon films with controlled crystal structure: In certain embodiments a method of forming a multi-layer silicon film is provided. A substrate is placed in a process chamber. An amorphous silicon film is formed on the substrate by flowing into the process chamber a first process gas comprising a silicon source gas. A polysilicon film is formed... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090065817 - Dielectric spacer removal: The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing... Agent: Scully, Scott, Murphy & Presser, P.C.

20090065819 - Apparatus and method of manufacture for an imager starting material: An imager apparatus and associated starting material are provided. Such starting material includes a first silicon layer and an oxide layer disposed adjacent to the first silicon layer. Further included is a first doped layer disposed adjacent to the oxide layer with a first doping, and a second doped layer... Agent: Zilka-kotab, PC

20090065818 - Structure for imagers having electrically active optical elements: A design structure embodied in a machine readable medium for use in a design process, the design structure representing a CMOS image sensor device comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting... Agent: Scully, Scott, Murphy & Presser, P.C.

20090065833 - Cmos image sensor: A CMOS image sensor is described, based on a substrate and including a transfer transistor, a reset transistor, a source follower transistor, a select transistor, a photodiode and a floating node structure. The substrate includes a floating node area between the transfer transistor and the reset transistor. The floating node... Agent: J C Patents, Inc.

20090065830 - Image sensor and a method for manufacturing the same: An image sensor and manufacturing method thereof are provided. A semiconductor substrate can include a center region and an edge region, each with a gate. A first impurity region and a second impurity region can be provided in the semiconductor substrate to a first side of each gate. A floating... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090065821 - Image sensor and fabricating method thereof: An image sensor and fabricating method thereof for preventing cross-talk between neighboring pixels by providing at least three light-shield walls combining to extend vertically above a lateral periphery of a photodiode for deflecting light from a microlens array towards the photodiode.... Agent: Sherr & Vaughn, PLLC

20090065824 - Image sensor and manufacturing method thereof: An image sensor can be formed of a first substrate having a readout circuitry, an interlayer dielectric, and lower lines, and a second substrate having a photodiode. The first substrate comprises a pixel portion and a peripheral portion. The readout circuitry is formed on the pixel portion. The interlayer dielectric... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090065825 - Image sensor and manufacturing method thereof: Provided is an image sensor. The image sensor comprises an interlayer dielectric, lines, and a crystalline semiconductor layer including photodiodes and a device isolation region. The interlayer dielectric can be formed on a first substrate comprising a readout circuitry. The lines pass through the interlayer dielectric to connect with the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090065827 - Image sensor and manufacturing method thereof: Provided is an image sensor. The image sensor can include a readout circuitry on a first substrate. An interlayer dielectric is formed on the first substrate, and comprises a lower line therein. A crystalline semiconductor layer is bonded to the interlayer dielectric. A photodiode can be formed in the crystalline... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090065828 - Image sensor and manufacturing method thereof: Provided is an image sensor. The image sensor can include a first substrate comprising a pixel portion in which a readout circuitry is provided and a peripheral portion in which a peripheral circuitry is provided. An interlayer dielectric including lines can be formed on the first substrate to connect with... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090065822 - Image sensor and method for manufacturing an image sensor: Provided are methods for manufacturing an image sensor. A method for manufacturing an image sensor can include: forming a readout circuitry on a substrate; forming an electrical junction region in the substrate; forming an interconnection connected to the electrical junction region; and forming an image sensing device on the interconnection.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090065823 - Image sensor and method for manufacturing an image sensor: Provided is an image sensor. The image sensor can include a readout circuitry on a first substrate, an electrical junction region in the first substrate electrically connected with the readout circuitry, and an interconnection on the first substrate. The interconnection can be formed for connection to the electrical junction region.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090065826 - Image sensor and method for manufacturing the same: Provided is an image sensor. The image sensor can include a first substrate, an image sensing device and a light shielding layer. The first substrate includes a readout circuitry and an interconnection. The image sensing device is formed on the interconnection. The light shielding layer is formed in portions of... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090065829 - Image sensor and method for manufacturing the same: Provided are image sensors and a method of manufacturing the same. The image sensor can include a semiconductor substrate having a metal line and a readout circuitry formed thereon; a photodiode on the semiconductor substrate, the photodiode including a first impurity region and a second impurity region horizontally arranged in... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090065831 - Image sensor and method for manufacturing the same: Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a semiconductor substrate including a CMOS circuit, a dielectric layer including a metal interconnection on the semiconductor substrate, a bottom electrode on the metal interconnection, in which the bottom electrode has at least one... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090065820 - Method and structure for simultaneously fabricating selective film and spacer: The present invention provides a method for simultaneously fabricating a selective film and a spacer. First, a semiconductor substrate is provided and a first device area and a second device area are defined on the semiconductor substrate. At least a gate is formed on the semiconductor substrate in the second... Agent: North America Intellectual Property Corporation

20090065832 - Solid-state imaging device: It is an object of the present invention to provide an image sensor having a high ratio of a surface area of a light receiving element to a surface area of one pixel. The above-described object is achieved by an inventive solid-state imaging device unit comprising solid-state imaging devices arranged... Agent: Brinks Hofer Gilson & Lione

20090065834 - Imagers having electrically active optical elements: A CMOS image sensor comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing... Agent: Scully, Scott, Murphy & Presser, P.C.

20090065835 - Capacitorless dram and methods of manufacturing and operating the same: Example embodiments provide a capacitorless dynamic random access memory (DRAM), and methods of manufacturing and operating the same. The capacitorless DRAM according to example embodiments may include a semiconductor layer separated from a top surface of a substrate and that contains a source region, a drain region, and a channel... Agent: Harness, Dickey & Pierce, P.L.C

20090065836 - Semiconductor device having mim capacitor and method of manufacturing the same: A semiconductor device having an MIM capacitor and a method of manufacturing the same. In one example embodiment, a semiconductor device having an MIM capacitor includes a lower electrode including a pair of metal patterns spaced apart from each other, a dielectric formed so as to cover the surfaces of... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090065837 - Semiconductor memory device having capacitor for peripheral circuit: Provided is a semiconductor memory device having peripheral circuit capacitors. In the semiconductor memory device, a first node is electrically connected to a plurality of lower electrodes of a plurality of capacitors in a peripheral circuit region to connect at least a portion of the capacitors in parallel. A second... Agent: Marger Johnson & Mccollom, P.C.

20090065838 - Semiconductor memory device and method of manufacturing the same: An improved semiconductor memory device having a silicon on insulator (SOI) structure. Exemplary devices provide improved charge injection into the device's floating gate electrode. Exemplary devices may include a semiconductor substrate including a transistor forming region and a capacitor forming region; a MOSFET; a MOS capacitor; a projection formed within... Agent: Taft, Stettinius & Hollister LLP

20090065839 - Driver for driving a load using a charge pump circuit: A charge pump circuit includes MOSFETs and MOS capacitors formed on the same substrate. Each of the MOS capacitors has a multiplicity of first electrodes formed in one region of the substrate, insulating layers formed on/above respective substrate regions between neighboring first electrodes, each layer covering at least the respective... Agent: Hogan & Hartson L.L.P.

20090065840 - Flash memory and manufacturing method of the same: A flash memory and a manufacturing method of the same includes a shallow trench isolation and an active region formed at a substrate, a plurality of stacked gates formed on and/or over the active region, a deep implant region formed at a lower portion of the shallow trench isolation and... Agent: Sherr & Vaughn, PLLC

20090065841 - Silicon oxy-nitride (sion) liner, such as optionally for non-volatile memory cells: An improved contact etch stop liner (CESL) is provided, to reduce stress effects in NVM cells using a nitride charge-trapping layer (such as NROM). SiON (silicon oxy-nitride) may be used in lieu of SiN (silicon nitride), for the CESL. Or, the CESL may be processed to be discontinuous, to reduce... Agent: Empk & Shiloh, LLP C/o Landon Ip, Inc.

20090065842 - Ta-lined tungsten plugs for transistor-local hydrogen gathering: The present electronic device includes a dielectric body having an opening therein. A tantalum layer is provided in the opening of the dielectric body, the layer having the characteristic of absorbing hydrogen with decrease in temperature, and releasing hydrogen with increase in temperature. A conductive tungsten plug is provided on... Agent: Paul J. Winters

20090065845 - Embedded semiconductor device and method of manufacturing an embedded semiconductor device: Provided are an embedded semiconductor device and a method of manufacturing an embedded semiconductor device. In a method of manufacturing the embedded semiconductor device, layers of at least one cell gate stack may be formed in a cell area of a substrate. A logic gate structure may be formed in... Agent: Harness, Dickey & Pierce, P.L.C

20090065844 - Nonvolatile semiconductor memory device and manufacturing method thereof: A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells each having a double-layered gate structure in which a floating gate and a control gate formed of a nickel silicide film are laminated, a first contact plug formed on a substrate contact portion of a surface of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090065843 - Semiconductor constructions, semiconductor processing methods, and methods of forming flash memory structures: Some embodiments include methods of reflecting ions off of vertical regions of photoresist mask sidewalls such that the ions impact foot regions along the bottom of the photoresist mask sidewalls and remove at least the majority of the foot regions. In some embodiments, trenches may be formed adjacent the photoresist... Agent: Wells St. John P.s.

20090065847 - Flash memory device and method for fabricating the same: An embedded flash memory device and a method for fabricating the same which reduces the size of a memory device using logic CMOS fabricating processes and enhancing a coupling ratio of the memory device. The flash memory device includes a coupling oxide layer on an active area of a semiconductor... Agent: Sherr & Vaughn, PLLC

20090065846 - Non-volatile memory and manufacturing method thereof: A manufacturing method of a non-volatile memory includes forming a first dielectric layer, a first conductive layer, and a first cap layer sequentially on a substrate to form first gate structures; conformally forming a second dielectric layer on the substrate; forming a first spacer having a larger wet etching rate... Agent: Jianq Chyun Intellectual Property Office

20090065850 - Non-volatile memory devices: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are... Agent: Mills & Onello LLP

20090065848 - Nonvolatile semiconductor storage device and manufacturing method thereof: A charge holding insulating film in a memory cell is constituted by a laminated film composed of a bottom insulating film, a charge storage film, and a top insulating film on a semiconductor substrate. Further, by performing a plasma nitriding treatment to the bottom insulating film, a nitride region whose... Agent: Miles & Stockbridge PC

20090065851 - Operating method of non-volatile memory device: A non-volatile memory device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the substrate and separated by a channel region. The stack layer includes an insulating layer disposed on the channel region, a charge storage layer disposed on... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090065849 - Semiconductor device and method for manufacturing the same: To improve a charge retention characteristic of a nonvolatile memory transistor. A first insulating film, a charge trapping film, and a second insulating film are formed between a semiconductor substrate and a conductive film. The charge trapping film is formed of a silicon nitride film including an upper region having... Agent: Eric Robinson

20090065852 - Nonvolatile memory device with nanowire channel and method for fabricating the same: A nonvolatile memory device with nanowire channel and a method for fabricating the same are proposed, in which side etching is used to shrink side walls of a side-gate to form a nanowire pattern, thereby fabricating a nanowire channel on the dielectric of the side walls of the side-gate. A... Agent: Sinorica, LLC

20090065853 - Fin field effect transistor: Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium (Si1-XGeX) body region for a fully depleted Fin field effect transistor (FinFET) having a body thickness of at least 10 nanometers (nm) for a process design rule of... Agent: Brooks, Cameron & Huebsch , PLLC

20090065854 - Semiconductor device and method of fabricating the same: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes second-conductive-type drift areas formed in a first-conductive-type well of a semiconductor substrate while being spaced apart from each other a vertical area protruding from the drift areas, and a second-conductive-type source/drain area formed on... Agent: Chang Young Ju

20090065855 - Mos device with integrated schottky diode in active region contact trench: A semiconductor device is formed on a semiconductor substrate. The device comprises a drain, an epitaxial layer overlaying the drain, and an active region. The active region comprises a body disposed in the epitaxial layer, having a body top surface and a body bottom surface, a source embedded in the... Agent: Van Pelt, Yi & James LLP

20090065857 - Raised vertical channel transistor device: A method for fabricating a vertical channel transistor device is provided. An opening is formed in a dielectric stack comprised of a pad nitride layer and a pad oxide layer. A plurality of epitaxial silicon growth and dry etching processes are carried out to form drain, vertical channel and source... Agent: North America Intellectual Property Corporation

20090065856 - Semiconductor device having vertical mos transistor and method for manufacturing the semiconductor device: In a vertical MOS transistor in which a semiconductor pillar is formed by etching a semiconductor substrate in a portion surrounded by an isolation film, the semiconductor pillar is covered with a gate insulating film and a gate electrode to be made a channel part, and diffusion layers to be... Agent: Mcginn Intellectual Property Law Group, PLLC

20090065858 - Dmos transistor and fabrication method thereof: In one example embodiment, a method of fabricating a DMOS transistor includes various steps. First, a P-type well or an N-type well is formed on a semiconductor substrate by an impurity injection. Next, a drift region is formed on the portion of the semiconductor substrate in which the well region... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090065860 - Semiconductor device and method for manufacturing the same: An exemplary object of the invention is to simultaneously achieve, in a semiconductor device which includes a trench gate structure formed by recessing a portion of a diffusion layer and an inter-diffusion-layer isolation insulating film which are formed on the a semiconductor substrate, good embeddability of the inter-diffusion-layer isolation insulating... Agent: Mcginn Intellectual Property Law Group, PLLC

20090065859 - Trench transistor and method for manufacturing the same: A trench transistor and a manufacturing method for the same are disclosed. The manufacturing method includes preparing a semiconductor substrate, forming a trench in the semiconductor substrate, forming a gate oxide layer over an inner wall of the trench, forming a gate having a first conductivity type by embedding polysilicon... Agent: Sherr & Vaughn, PLLC

20090065861 - Mos device with low injection diode: A semiconductor device is formed on a semiconductor substrate. The device includes a drain, an epitaxial layer overlaying the drain, and an active region. The active region includes a body disposed in the epitaxial layer, having a body top surface, a source embedded in the body, extending from the body... Agent: Van Pelt, Yi & James LLP

20090065862 - Semiconductor device and method of manufacturing the same: A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090065863 - Lateral double diffused metal oxide semiconductor device: In one example embodiment, an LDMOS device includes a first n-type well formed on a p-type substrate, a plurality of isolation layers formed in the first n-type well, a p-type ion implantation region formed on a surface of each of the isolation layers, and a gate selectively formed on the... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090065864 - Semiconductor device and method of fabricating the same: A semiconductor device and a method of fabricating the same are provided. The semiconductor device can include a buried conductive layer in a semiconductor substrate, an epitaxial layer on the buried conductive layer, and a plug passing through the epitaxial layer. The plug can be electrically connected to the buried... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090065865 - Semiconductor device and method of fabricating the same: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device can include a transistor structure including a gate electrode and a first channel region and source/drain regions on a substrate, and a second channel region and source/drain regions provided on the transistor structure. Accordingly, transistor... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090065866 - Non-planar silicon-on-insulator device that includes an \"area-efficient\" body tie: Non-planar SOI devices that include an “area-efficient” body tie are disclosed. The device includes a bulk substrate, an insulator layer formed on a surface of the bulk substrate, and a silicon body formed on a surface of the insulator layer. The silicon body preferably includes (i) a non-planar channel connecting... Agent: Honeywell International Inc.

20090065868 - Electronic circuit and method of manufacturing an electronic circuit: An electronic circuit includes at least one field effect transistor that is to be protected against electrostatic discharge events, and at least one protection field effect transistor. The protection field effect transistor has a crystal orientation that is different from a crystal orientation of the field effect transistor to be... Agent: Slater & Matsil LLP

20090065867 - Orientation-optimized pfets in cmos devices employing dual stress liners: A PFET is provided on a silicon layer having a (110) surface orientation and located in a substrate. A compressive stress liner disposed on the gate and source/drain regions of the PFET generates a primary longitudinal compressive strain along the direction of the PFET channel. A tensile stress liner disposed... Agent: Scully, Scott, Murphy & Presser, P.C.

20090065869 - Semiconductor device: A semiconductor device has a plurality of fins formed on a semiconductor substrate to be separated from each other, a first contact region which connects commonly one end side of the plurality of fins, a second contact region which connects commonly the other end side of the plurality of fins,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090065871 - Semiconductor chip and process for forming the same: A semiconductor chip comprises a first MOS device, a second MOS device, a first metallization structure connected to said first MOS device, a second metallization structure connected to said second MOS device, a passivation layer over said first and second MOS devices and over said first and second metallization structures,... Agent: Mou-shiung Lin Science-based Industrial Park

20090065870 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. One embodiment includes a semiconductor device including a workpiece, the workpiece including a first region and a second region proximate the first region. A first transistor is disposed in the first region of the... Agent: Slater & Matsil LLP

20090065872 - Full silicide gate for cmos: A method is provided for fabricating an n-type field effect transistor (“NFET”) and a p-type field effect transistor (“PFET”) in which the NFET and PFET are formed after which a protective hard mask layer, e.g., a dielectric stressor layer is formed to overlie edges of gates, source regions and drain... Agent: International Business Machines Corporation Dept. 18g

20090065873 - Semiconductor device and method of fabricating metal gate of the same: Provided is a semiconductor device that comprises a metal gate having a low sheet resistance characteristic and a high diffusion barrier characteristic and a method of fabricating the metal gate of the semiconductor device. The semiconductor device includes a metal gate formed on a gate insulating film, wherein the metal... Agent: Harness, Dickey & Pierce, P.L.C

20090065874 - Semiconductor memory device having layout area reduced: A metal supplying an N well voltage is provided in a first metal interconnection layer. The metal is electrically coupled to an active layer provided in an N well region by shared contacts so that the N well voltage is supplied to the N well region. A metal supplying a... Agent: Mcdermott Will & Emery LLP

20090065876 - Metal high-k transistor having silicon sidewall for reduced parasitic capacitance, and process to fabricate same: A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of... Agent: Harrington & Smith, PC

20090065875 - Metal-oxide-semiconductor device with a doped titanate body: A metal-oxide-semiconductor (MOS) device having a body of single-crystal strontium titanate or barium titanate (10) is provided in which the body comprises a doped semiconductor region (24) adjacent a dielectric region (26). The body may further comprise a doped conductive region separated from the semiconductor region by the dielectric region.... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090065877 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a first MOSFET including: first source and drain regions formed at a distance from each other in a first semiconductor region; a first insulating film formed on the first semiconductor region between the first source region and the first drain region; a first gate electrode formed... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090065878 - Diketopyrrolopyrrole-based derivatives for thin film transistors: s

20090065879 - High voltage device and method of fabricating the same: A high voltage device is provided. The high voltage device includes a gate on a substrate, two source/drain regions in the substrate beside the gate, and a composite gate dielectric layer that includes at least two stacked continuous layers, extending from one side to another side of the gate. Wherein,... Agent: J C Patents, Inc.

20090065880 - Semiconductor device made by using a laser anneal to incorporate stress into a channel region: In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming source/drains adjacent the gate electrodes, depositing a stress inducing layer over the gate electrodes. A laser anneal is conducted on at least the gate electrodes subsequent to depositing... Agent: Texas Instruments Incorporated

20090065881 - Electric field concentration minimization for mems: A method and resulting device for reducing an electrical field at an isolation gap in a capacitive actuator includes providing a bottom electrode layer and forming a pattern in the bottom electrode layer having an isolation gap between center and outer electrode components of the patterned electrode. A spacing material... Agent: Mh2 Technology Law Group, LLP (cust. No. W/xerox)

20090065882 - Semiconductor device, lead frame, and microphone package therefor: A semiconductor device is constituted of a mold sheet for mounting a sensor chip and a cover having a box-like shape, both of which are combined together so as to form a cavity therebetween. The mold sheet includes a stage having a rectangular shape in a plan view, a plurality... Agent: Pillsbury Winthrop Shaw Pittman LLP

20090065883 - Mram device with continuous mtj tunnel layers: A method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of memory cells includes: forming a fixed magnetic layer having magnetic moments fixed in a predetermined direction; forming a tunnel layer over the fixed magnetic layer; forming a free magnetic layer, having magnetic moments aligned in... Agent: K & L Gates LLP

20090065885 - Image sensor and method for manufacturing the same: Provided is an image sensor and method for manufacturing the same. In the image sensor, a first substrate has a lower metal line and a circuitry thereon. A crystalline semiconductor layer contacts the lower metal line and is bonded to the first substrate. A photodiode is provided in the crystalline... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090065884 - Solid-state imaging device: A solid-state imaging device is provided and includes: a semiconductor substrate; a plurality of photoelectric conversion elements arranged in a two-dimensional array in a surface portion of the semiconductor substrate; a conductive light shielding film above the surface portion, the conductive light shielding film having openings at a light-incident side... Agent: Birch Stewart Kolasch & Birch

20090065886 - Solid-state image pickup device and method for manufacturing the same: In a solid-state image pickup device, a thickness of an insulating film, a width and a thickness of wirings, a length of the wirings, or a diameter of bump portions formed on the wirings is formed so that a capacitance of a capacitor structure generated between a solid-state image sensor... Agent: Sughrue Mion, PLLC

20090065887 - Image sensor and method for manufacturing the same: Provided is an image sensor and a method for manufacturing the same. In the image sensor, a first substrate has a lower metal line and circuitry thereon. A crystalline semiconductor layer contacts the lower metal line and is bonded to the first substrate. A photodiode is provided in the crystalline... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090065888 - Semiconductor device and a method of manufacturing the same: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a main surface of a p-type semiconductor substrate, an n-type cathode region formed in... Agent: Miles & Stockbridge PC

20090065889 - Semiconductor integrated circuit device and method for designing the same: A semiconductor integrated circuit device has a basic cell structure which allows avoidance of wiring congestion of signal lines or the like. The semiconductor integrated circuit device comprises a plurality of basic cells having predetermined functions, respectively, which are configured by connecting semiconductor elements via wirings. Each of the basic... Agent: Mcdermott Will & Emery LLP

20090065890 - Semiconductor device and method for fabricating the same: Embodiments relate to the lowered reliability of a device due to deterioration caused by the concentration of an electric field in the top corner of an STI. To solve the reliability problem, the STI top corners have a local oxidation of silicon, the top corners of the STI are rounded,... Agent: Sherr & Vaughn, PLLC

20090065891 - Semiconductor substrate and process for producing it: d) splitting the donor wafer along the layer of cavities, resulting in a layer of semiconductor material on the carrier wafer. Semiconductor substrates prepared thusly may have a single-crystalline semiconductor layer having a thickness of 100 nm or less, a layer thickness uniformity of 5% or less, and an HF... Agent: Brooks Kushman P.C.

20090065892 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the same that reduces a process defect caused by pattern dependency in chemical mechanical polarization (CMP) or etching is excellent. The semiconductor device includes a device pattern formed on or in a substrate; and a plurality of dummy patterns having different longitudinal-sectional... Agent: Sherr & Vaughn, PLLC

20090065893 - Semiconductor devices and fabrication methods thereof: A semiconductor device and fabrication method thereof is disclosed. The method includes the steps of providing a substrate with a trench and a stacked layer thereon, performing an epitaxy process to form an epitaxial layer in the trench, conformably depositing an oxide layer on the epitaxial layer, and removing a... Agent: Quintero Law Office, PC

20090065894 - Electronic circuit device having silicon substrate: An electronic circuit device comprises a silicon substrate having front and rear surfaces, a semiconductor element formed on the front surface, and at least one through-hole penetrating through the front surface and the rear surface. At least one passive element is supported by the silicon substrate. At least one connecting... Agent: Bruce L. Adams, Esq. Adams & Wilks

20090065896 - Capacitor having ru electrode and tio2 dielectric layer for semiconductor device and method of fabricating the same: Provided are a capacitor of a semiconductor device using a TiO2 dielectric layer and a method of fabricating the capacitor. The capacitor includes a Ru bottom electrode formed on a semiconductor substrate, an rutile-structures RuO2 pretreated layer which is formed by oxidizing the Ru bottom electrode, a TiO2 dielectric layer... Agent: Occhiuti Rohlicek & Tsao, LLP

20090065895 - Mim capacitor high-k dielectric for increased capacitance density: According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a high-k dielectric layer comprising AlNX (aluminum nitride) on the first interconnect layer. The method further includes... Agent: Michael Farjami, Esq. Farjami & Farjami LLP

20090065897 - Semiconductor device and method of fabricating the same: A M-I-M capacitor semiconductor device capable of enhancing the reliability and capacitance of a capacitor and maximizing the integration density of the device, and a method of fabricating the same are disclosed. The semiconductor device includes a semiconductor substrate, a capacitor lower metal layer formed over the semiconductor substrate, a... Agent: Sherr & Vaughn, PLLC

20090065898 - Integrated beol thin film resistor: In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is... Agent: Anthony J. Canale Intellectual Property Law, IBM Corporation

20090065899 - Semiconductor device: The invention is directed to providing a technique for increasing a hold voltage of an electrostatic breakdown protection device having a bipolar transistor structure more than conventional and reducing the size of the device. A base region (a P impurity layer) is formed on a front surface of an epitaxial... Agent: Morrison & Foerster LLP

20090065900 - Group iii nitride-based compound semiconductor device: A characteristic feature of the invention is to form, in a Group III nitride-based compound semiconductor device, a negative electrode on a surface other than a Ga-polar C-plane. In a Group III nitride-based compound semiconductor light-emitting device, there are formed, on an R-plane sapphire substrate, an n-contact layer, a layer... Agent: Mcginn Intellectual Property Law Group, PLLC

20090065901 - Semiconductor element and manufacturing method thereof: A semiconductor element and a manufacturing method of the semiconductor element are provided. A ridge waveguide type semiconductor integrated element includes: an electrode of an EA portion and an electrode of an LD portion which are arranged so as to be away from each other; a contact layer of the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090065902 - Method of forming a semiconductor die having a sloped edge for receiving an electrical connector: A method of forming a low profile semiconductor package, and a semiconductor package formed thereby, is disclosed. The semiconductor die is formed with one or more sloped edges on which electrically conductive traces may be deposited to allow the semiconductor die to be coupled to another die and/or a substrate... Agent: Vierra Magen/sandisk Corporation

20090065903 - Semiconductor device and method for fabricating the same: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at... Agent: Mcdermott Will & Emery LLP

20090065905 - Conductive metal structure applied to a module ic and method of manufacturing the same: A conductive metal structure applied to a module IC includes a wafer, a first insulating unit, and a first conductive unit. The wafer has a main body and a through hole passing through the main body. The first insulating unit has a first inner insulating layer formed on an inner... Agent: Rosenberg, Klein & Lee

20090065906 - Semiconductor device and producing method of the same: A semiconductor device includes a semiconductor substrate having a through hole. An active layer is formed on a first surface of the semiconductor substrate. An inner wall surface of the through hole, a bottom surface of the through hole closed by the active layer and a second surface of the... Agent: Amin, Turocy & Calvin, LLP

20090065907 - Semiconductor packaging process using through silicon vias: A microelectronic unit 400 can include a semiconductor element 401 having a front surface, a microelectronic semiconductor device adjacent to the front surface, contacts 403 at the front surface and a rear surface remote from the front surface. The semiconductor element 401 can have through holes 410 extending from the... Agent: Tessera Lerner David Et Al.

20090065904 - Substrate having through-wafer vias and method of forming: An annular trench region is formed at a semiconductor substrate of an electronic device that defines a conductive plug of the through-wafer via, wherein the conductive plug includes an undisturbed portion of the semiconductor substrate.... Agent: Larson Newman Abel & Polansky, LLP

20090065908 - Methods of fabricating a micromechanical structure: Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second... Agent: Birch Stewart Kolasch & Birch

20090065909 - Segmented magnetic shielding elements: A second shield layer, under the master shielding layer, is added to a segmented MRAM array. This additional shielding is patterned so as to provide one shield per bit slice. The placement of longitudinal biasing tabs at the ends of these segmented shields ensures that each segmented shield is a... Agent: Saile Ackerman LLC

20090065910 - Semiconductor device and manufacturing method of the same: While a semiconductor device is provided with a plurality of element electrodes 5 formed on a semiconductor element 4 and a plurality of lead terminal electrodes 6 formed on a lead frame, the semiconductor device is equipped with a coupling conductor which electrically connects at least one electrode among the... Agent: Mcdermott Will & Emery LLP

20090065911 - Semiconductor package and manufacturing method thereof: A semiconductor package includes a carrier, at least one chip, an encapsulation, and a patterned conductive film. The carrier has a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface of the carrier and electrically connected to the carrier. The... Agent: J C Patents, Inc.

20090065912 - Semiconductor package and method of assembling a semiconductor package: A semiconductor package includes a semiconductor component including a circuit carrier with a plurality of inner contact pads, a semiconductor chip, and a plurality of electrical connections. An adhesion promotion layer is disposed on at least areas of the semiconductor component and a plastic encapsulation material encapsulates at least the... Agent: Edell , Shapiro & Finnan , LLC

20090065913 - Chip package with asymmetric molding: A chip package with asymmetric molding including a lead frame, a chip, an adhesive layer, bonding wires and an encapsulant, is provided. The lead frame includes a frame body and at least a turbulent plate. The frame body has inner lead portions and outer lead portions. The turbulent plate is... Agent: J C Patents, Inc.

20090065914 - Semiconductor device with leaderframe including a diffusion barrier: A semiconductor device includes a leadframe having a first face and an opposing second face, a portion of the first face defining a die pad, a diffusion barrier deposited on at least a portion of the die pad, and at least one chip coupled to the diffusion barrier.... Agent: Dicke, Billig & Czaja

20090065916 - Semiconductor die mount by conformal die coating: A conformal coating on a semiconductor die provides adhesion between the die and a support. No additional adhesive is necessary to affix the die on the support. The conformal coating protects the die during assembly, and serves to electrically insulate the die from electrically conductive parts that the die may... Agent: Haynes Beffel & Wolfeld LLP

20090065915 - Singulated semiconductor package: A semiconductor device includes a singulated semiconductor package having a leadframe, a chip electrically coupled to the leadframe, encapsulating material covering the chip and a portion of the leadframe, and a material layer disposed over opposing ends of the leadframe. The leadframe includes a first face and an opposing second... Agent: Dicke, Billig & Czaja

20090065917 - Multi-standards compliant card body: A card body comprises a module-receiving part (3) having a cavity for receiving an electronic module ML. The card body comprises a first side part (4) coupled to the module-receiving part (3), the first side part being separated from the module-receiving part by a first separation line (6), and a... Agent: Osha Liang L.L.P.

20090065921 - Electronic package device, module, and electronic apparatus: There is provided an electronic device package and the like in which it is not likely that damage occurs in a wiring pattern of an interposer substrate in a gap section formed, for example, between an electronic device and an insertion substrate. The semiconductor package in accordance with the present... Agent: Foley And Lardner LLP Suite 500

20090065918 - Interconnecting electrical devices: An intercoupling component includes first male contacts, each first male contact received within a corresponding aperture of a first array of apertures and extending beyond a second surface of a first insulative support member toward a second insulative support member, each first male contact having a first axis; second contacts,... Agent: Occhiuti Rohlicek & Tsao, LLP

20090065922 - Semiconductor device package structure: A semiconductor chip mounted interposer (60) is configured by executing wire bonding between a semiconductor chip (50) and an interposer (20), in which terminals (21) that connect to terminals (51) of the chip (50) and separate terminals (22) are formed, on the upper face of the interposer (20). A semiconductor... Agent: Mark D. Saralino (general) Renner, Otto, Boisselle & Sklar, LLP

20090065920 - Semiconductor package embedded in substrate, system including the same and associated methods: A device includes a base substrate, a package including an encapsulated die, the package at least partially embedded in the base substrate, and a wiring portion on the package and extending across at least a portion of the base substrate adjacent to the package.... Agent: Lee & Morse, P.C.

20090065919 - Semiconductor package having resin substrate with recess and method of fabricating the same: In one embodiment, a semiconductor package disclosed herein can be generally characterized as including a resin substrate having a first recess, a first interconnection disposed on a surface of the first recess, a first semiconductor chip disposed in the first recess, and an underfill resin layer substantially filling the first... Agent: Marger Johnson & Mccollom, P.C.

20090065923 - Semiconductor package with improved size, reliability, warpage prevention, and head dissipation and method for manufacturing the same: The semiconductor package includes a semiconductor package module with circuit patterns formed on an insulation substrate, at least two semiconductor chips electrically connected to each of the circuit patterns using bumps, and an insulation member filled in any open space in the semiconductor module. A cover plate is formed on... Agent: Ladas & Parry LLP

20090065925 - Dual-sided chip attached modules: An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads... Agent: Schmeiser, Olsen & Watts

20090065924 - Semiconductor package with reduced volume and signal transfer path: A semiconductor package includes a first semiconductor chip having a first semiconductor chip body including a first circuit region and peripheral regions arranged around the first circuit region. A first bonding pad group is arranged within the first circuit region and includes a plurality of bonding pads. A first redistribution... Agent: Ladas & Parry LLP

20090065926 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a base plate made of a material including at least a thermosetting resin, and having an opening, a vertical conductor filled and provided in the opening of the base plate, at least one semiconductor construct having a semiconductor substrate and a plurality of external connection electrodes... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090065927 - Semiconductor device and methods of manufacturing semiconductor devices: This application relates to a semiconductor device comprising a semiconductor chip, a molded body covering the semiconductor chip wherein the molded body comprises an array of recesses in a first surface of the molded body, first contact elements, and elastic elements in the recesses that connect the first contact elements... Agent: Infineon Technologies Ag Patent Department

20090065928 - Anti-stiction technique for electromechanical systems and electromechanical device employing same: A mechanical structure is disposed in a chamber, at least a portion of which is defined by the encapsulation structure. A first method provides a channel cap having at least one preform portion disposed over or in at least a portion of an anti-stiction channel to seal the anti-stiction channel,... Agent: Kenyon & Kenyon LLP

20090065929 - Multi-chip semiconductor device: A semiconductor device includes semiconductor chips differing in withstand voltage or in noise immunity, such as a multi-chip module. The semiconductor device includes first and second semiconductor chips mounted over a package substrate which has bonding pads arranged along the edges. The first semiconductor chip includes bonding pads for analog... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090065932 - Methods of forming nano-coatings for improved adhesion between first level interconnects and epoxy under-fills in microelectronic packages and structures formed thereby: Methods and associated structures of forming microelectronic devices are described. Those methods may include coating an interconnect structure disposed on a die with a layer of functionalized nanoparticles, wherein the functionalized nanoparticles are dispersed in a solvent, heating the layer of functionalized nanoparticles to drive off a portion of the... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090065930 - Package substrate including surface mount component mounted on a peripheral surface thereof and microelectronic package including same: A microelectronic combination and a method of making the combination. The combination includes a package substrate including a substrate body having a peripheral surface and contacts disposed at the peripheral surface; and a surface mount component electrically and mechanically bonded to the contacts.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090065931 - Packaged integrated circuit and method of forming thereof: Disclosed is a packaged integrated circuit and a method of forming thereof. The packaged integrated circuit includes a substrate, a plurality of solder bumps, a semiconductor die and a plurality of copper bumps. The plurality of solder bumps are configured on the substrate. Each of the plurality of solder bumps... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Intellevate, LLC

20090065933 - Semiconductor device and method of manufacturing the same: The present invention provides a semiconductor device that can suppresses poor connection caused by the variation of the heights of bumps during reflow heating, can be applied to a narrow array pitch, and can freely adjust the heights of the bumps.... Agent: Steptoe & Johnson LLP

20090065934 - Wiring substrate, tape package having the same, display device having the tape package, method of manufacturing the wiring substrate, method of manufacturing a tape package having the same and method of manufacturing a display device having the tape packa: A wiring substrate may include a base film, a plurality of wires, a first insulation member and a second insulation member. The base film may have a chip-mounting region where a semiconductor chip may be mounted thereon. The wires may extend from the chip-mounting region and the wires may include... Agent: Harness, Dickey & Pierce, P.L.C

20090065937 - Structure of high performance combo chip and processing method: A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the... Agent: Megica Corporation

20090065936 - Substrate, electronic component, electronic configuration and methods of producing the same: A substrate for an electronic component comprises a dielectric body having an upper surface including a plurality of inner contact pads and a lower surface including a plurality of outer contact pads. Each outer contact pad has an inner face and an outer face. An insulating layer covers the lower... Agent: Dicke, Billig & Czaja

20090065935 - Systems and methods for ball grid array (bga) escape routing: A ball grid array (BGA) package and its corresponding printed circuit board incorporate an improved escape routing scheme. The substrate includes a plurality of conductive pads having a periphery defined by a predetermined edge pattern forming routing channels therebetween. A plurality of signal lines connected to a subset of the... Agent: Ingrassia Fisher & Lorenz, P.C. (es)

20090065938 - Semiconductor element and method for manufacturing same: The semiconductor element of the present invention has an n-type Gallium nitride based compound semiconductor and an electrode that forms an ohmic contact with the semiconductor, wherein the electrode has a TiW alloy layer to be in contact with the semiconductor. According to a preferable embodiment, the above-mentioned electrode can... Agent: Wenderoth, Lind & Ponack, L.L.P.

20090065939 - Method for integrating selective ruthenium deposition into manufacturing of a semiconductior device: A method for integrating selective Ru metal deposition into manufacturing of semiconductor devices to improve electromigration and stress migration in bulk Cu. The method includes selectively depositing a Ru metal film on a metallization layer or on bulk Cu using a process gas containing Ru3(CO)12 precursor vapor and a CO... Agent: Tokyo Electron U.s. Holdings, Inc.

20090065940 - Metal wiring of a semiconductor device and method of forming the same: According to a method of forming a metal wiring of a semiconductor device, a contact plug is formed at height lower than the contact hole, which is formed on an interlayer insulation layer, and then a metal wiring is formed over the contact plug and interlayer insulation layer to completely... Agent: Marshall, Gerstein & Borun LLP

20090065941 - Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias: A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric... Agent: Schmeiser, Olsen & Watts

20090065942 - Semiconductor device, display device, and method of manufacturing semiconductor device: A semiconductor device includes a film containing silicon as the main ingredient, and an aluminum alloy film, such as a source electrode and a drain electrode, that is directly connected to the film containing silicon as the main ingredient, such as an ohmic low-resistance Si film, and contains at least... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090065943 - Microelectronic assembly having second level interconnects including solder joints reinforced with crack arrester elements and method of forming same: A microelectronic assembly and a method of forming the assembly. The microelectronic assembly includes a package having a package substrate having a die side and a carrier side, and substrate lands on the carrier side thereof; a microelectronic die mounted on the package substrate at the die side thereof; and... Agent: Laleh Jalali Intel Corporation

20090065946 - Method for fabricating semiconductor device and semiconductor device: A method of fabricating a semiconductor device having an air-gapped multilayer interconnect wiring structure is disclosed. After having formed a first thin film on or above a substrate, define a first opening in the first thin film. Then, deposit a conductive material in the first opening. Then form a second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090065944 - Reworked integrated circuit device and reworking method thereof: Reworking method for removing defects on integrated circuit device is disclosed. An integrated circuit is provided, which has a substrate, a conductive material layer formed in the substrate, a dielectric layer formed on the substrate, at least a contact plug embedded in the dielectric layer, and a conductive layer contacting... Agent: North America Intellectual Property Corporation

20090065945 - Semiconductor device for preventing inflow of high current from an input/output pad and a circuit for preventing inflow of high current thereof: A semiconductor device includes an input/output pad, an input line of an internal circuit, and a plurality of metal lines formed on a lower portion of the input/output pad to have a buffer area overlapping with a plane area of the input/output pad, wherein one of an entirety and a... Agent: Baker & Mckenzie LLP Patent Department

20090065947 - Semiconductor device having circularly connected plural pads via through holes and method of evaluating the same: A semiconductor device includes a plurality of wiring layers, a plurality of via layers, and a plurality of electrode pads. The electrode pads are circularly connected to each other through the wiring layers and the via layers.... Agent: Mcginn Intellectual Property Law Group, PLLC

20090065948 - Package structure for multiple die stack: A die module and method for assembling such a die module is provided. For example, present embodiments include providing a substrate and coupling a first sub-stack to the substrate, wherein the first sub-stack includes two or more die arranged in a first shingle stack configuration relative to one another such... Agent: Fletcher Yoder (micron Technology, Inc.)

20090065949 - Semiconductor package and semiconductor module having the same: A semiconductor package can include a semiconductor chip, an insulating substrate, first bond fingers, and pads. The insulating substrate can be attached to edge portions of the semiconductor chip. The first bond fingers can be arranged on edge portions of an upper surface of the insulating substrate. Further, the first... Agent: Mills & Onello LLP

20090065950 - Stack chip and stack chip package having the same: Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input/output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input/output buffers and internal circuits connected through circuit... Agent: Marger Johnson & Mccollom, P.C.

20090065952 - Semiconductor chip with crack stop: Various semiconductor chip crack stops and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor substrate that has a first corner defined by a first edge and a second edge. A crack stop is formed in the semiconductor... Agent: Timothy M Honeycutt Attorney At Law

20090065951 - Stacked die package: The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a... Agent: Konrad Raynes & Victor, LLP. Attn: Int77

20090065953 - Chip module and a fabrication method thereof: A chip module and a fabricating method thereof are provided. Firstly, a substrate is provided. Next, a chip is assembled on the substrate and electrically connected with the substrate. Afterward, a plurality of passive units is assembled on the substrate in the style of encircling the chip. Then, a first... Agent: Bacon & Thomas, PLLC

20090065955 - Method and structures for accelerated soft-error testing: An integrated circuit, method of forming the integrated circuit and a method of testing the integrated circuit for soft-error fails. The integrated circuit includes: a silicon substrate; a dielectric layer formed over the substrate; electrically conductive wires formed in the dielectric layer, the wires interconnecting semiconductor devices formed in the... Agent: Schmeiser, Olsen & Watts

20090065954 - Packaging method for wideband power using transmission lines: Embodiments of the invention relate to a package design incorporating an ultra-low characteristic impedance transmission line (T-line) bundle. The T-line bundle can extend from inside the package to outside the package in order to provide power delivery and power interconnect for a chip. In one embodiment, the T-line bundle can... Agent: Attma Sharma

20090065956 - Memory cell: Methods of forming line ends and a related memory cell including the line ends are disclosed. In one embodiment, the memory cell includes fa first device having a first conductive line extending over a first active region and having a first line end of the first conductive line positioned over... Agent: Hoffman Warnick LLC

20090057641 - Phase change memory cell with first and second transition temperature portions: A phase change memory cell includes first and second electrodes having generally coplanar surfaces spaced apart by a gap and a phase change bridge electrically coupling the first and second electrodes. The phase change bridge may extend over the generally coplanar surfaces and across the gap. The phase change bridge... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090057640 - Phase-change memory element: A phase-change memory element and fabrication method thereof is provided. The phase-change memory element comprises an electrode. A first dielectric layer is formed on the substrate. An opening passes through the first dielectric layer exposing the electrode. A heater with an extended part is formed in the opening, wherein the... Agent: Quintero Law Office, PC

20090057642 - Memory device: A memory or switching device includes a mesa and a first electrode conforming to said mesa. The device also includes a second electrode and a phase-change or switching material disposed between said first and second electrodes. The phase-change or switching material is in electrical communication with the first and second... Agent: Honigman Miller Schwartz & Cohn LLP

20090057645 - Memory element with improved contacts: A phase-change memory element comprising a phase-change memory material, a first electrical contact and a second electrical contact. At least one of the electrical contacts having a sidewall electrically coupled to the memory material.... Agent: Ovonyx, Inc

20090057643 - Phase change memory device and fabrication method thereof: A phase change memory device is disclosed. A second conductive spacer is under a first conductive spacer. A phase change layer comprises a first portion substantially parallel to the first and second conductive spacers and a second portion on top of the second conductive spacer, wherein the second conductive spacer... Agent: Quintero Law Office, PC

20090057644 - Phase-change memory units, methods of forming the phase-change memory units, phase-change memory devices having the phase-change memory units and methods of manufacturung the phase-change memory devices: A phase-change memory unit includes a lower electrode on a substrate, a phase-change material layer pattern including germanium-antimony-tellurium (GST) and carbon on the lower electrode, a transition metal layer pattern on the phase-change material layer pattern, and an upper electrode on the first transition metal layer pattern. The phase-change memory... Agent: Mills & Onello LLP

20090057646 - Optical semiconductor device and method for manufacturing the same: Because of a large lattice mismatch between a sapphire substrate and a group III-V compound semiconductor, a good crystal is difficult to grow. A high-quality AlN buffer growth structure A on a sapphire substrate includes a sapphire (0001) substrate 1, an AlN nucleation layer 3 formed on the sapphire substrate... Agent: Lowrie, Lando & Anastasi, LLP

20090057647 - Semiconductor light emitting device and method for manufacturing the same: Provided is a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises: a first conductive type semiconductor layer; an active layer on the first conductive type semiconductor layer; an undoped semiconductor layer on the active layer; a first delta-doped layer on the... Agent: Birch Stewart Kolasch & Birch

20090057648 - High hole mobility p-channel ge transistor structure on si substrate: The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Intellevate, LLC

20090057649 - Assembly of ordered carbon shells on semiconducting nanomaterials: In some embodiments of the invention, encapsulated semiconducting nanomaterials are described. In certain embodiments the nanostructures described are semiconducting nanomaterials encapsulated with ordered carbon shells. In some aspects a method for producing encapsulated semiconducting nanomaterials is disclosed. In some embodiments applications of encapsulated semiconducting nanomaterials are described.... Agent: Brookhaven Science Associates/ Brookhaven National Laboratory

20090057651 - Gated quantum resonant tunneling diode using cmos transistor with modified pocket and ldd implants: A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an inversion layer between two barrier regions, resulting in a quantum well less than 15 nanometers wide. Source and drain regions adjacent to the barrier... Agent: Texas Instruments Incorporated

20090057650 - Nanoscale wires and related devices: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length,... Agent: Wolf Greenfield & Sacks, P.C.

20090057652 - Multilayer structure with zirconium-oxide tunnel barriers and applications of same: A multilayer structure with zirconium-oxide tunnel barriers. In one embodiment, the multilayer structure includes a first niobium (Nb) layer, a second niobium (Nb) layer, and a plurality of zirconium-oxide tunnel barriers sandwiched between the first niobium (Nb) layer and the second niobium (Nb) layer, wherein the plurality of zirconium-oxide tunnel... Agent: Morris Manning Martin LLP

20090057653 - Methods for site-selective growth of horizontal nanowires, nanowires grown by the methods and nanodevices comprising the nanowires: Methods for the site-selective growth of horizontal nanowires are provided. According to the methods, horizontal nanowires having a predetermined length and diameter can be grown site-selectively at desired sites in a direction parallel to a substrate to fabricate a device with high degree of integration. Further provided are nanowires grown... Agent: Cantor Colburn, LLP

20090057654 - Spin fet and magnetoresistive element: A spin FET of an aspect of the present invention includes source/drain regions, a channel region between the source/drain regions, and a gate electrode above the channel region. Each of the source/drain regions includes a stack structure which is comprised of a low work function material and a ferromagnet. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090057657 - Method for forming pattern arrays and organic devices including the pattern arrays: The present invention includes forming a hydrophobic thin film on a substrate, removing a portion of the first hydrophobic thin film to form a first hydrophilic region, coating a first organic solution on the substrate and selectively wetting the first hydrophilic region, drying the first organic solution to form a... Agent: Macpherson Kwok Chen & Heid LLP

20090057660 - Method of fabricating substrateless thin film field-effect devices and an organic thin film transistor obtainable by the method: A method for the manufacture of a thin-film field-effect device comprising, on a mechanical support layer, source and drain electrodes (S, D), a layer of semiconductor material (SC) for the formation of a conduction channel, and a gate electrode (G) insulated from the channel region, is described. The method provides... Agent: Sughrue Mion, PLLC

20090057655 - Organic thin film transistor comprising gate electrode of nanocrystalline conductive carbon layer, fabrication method thereof, and organic semiconductor device comprising the same: Provided are an organic thin film transistor (OTFT) and a fabrication method thereof, an organic semiconductor device having the OTFT, and a flexible display device having the OTFT. The OTFT includes a substrate, a gate electrode, an insulating layer, an active layer, and a source/drain electrode. The gate electrode may... Agent: Rabin & Berdo, PC

20090057658 - Organic thin film transistor substrate and method of manufacturing the same: An organic thin film transistor substrate includes a substrate, a gate line on a surface of the substrate, a gate insulating layer insulating on the gate line, a data line on the gate insulating layer, an organic thin film transistor connected to the gate line and the data line, the... Agent: Macpherson Kwok Chen & Heid LLP

20090057659 - Photoelectric conversion element, solid-state image pickup device, and manufacturing method of the photoelectric conversion element: A photoelectric conversion element comprises: a pair of electrodes; and an organic photoelectric conversion layer between the pair of electrodes, wherein one of the electrodes is a first electrode that collects electrons generated in the organic photoelectric conversion layer; the other one of the electrodes is a second electrode that... Agent: Sughrue-265550

20090057656 - Thin film transistor and method for manufacturing the same: One embodiment of the present invention is a thin film transistor, including: an insulating substrate; a gate electrode and a gate insulator being formed on the insulating substrate, in this order; a source electrode and a drain electrode formed on the gate insulator, surface preparation of the source electrode and... Agent: Squire, Sanders & Dempsey L.L.P.

20090057661 - Method for chemical mechanical planarization of chalcogenide materials: A method and associated composition for chemical mechanical planarization of a chalcogenide-containing substrate (e.g., germanium/antimony/tellurium (GST)-containing substrate) are described. The composition and method afford low defect levels (e.g., scratches incurred during polishing) as well as low dishing and local erosion levels on the chalcogenide-containing substrate during CMP processing.... Agent: Air Products And Chemicals, Inc. Patent Department

20090057662 - Nanoparticle semiconductor device and method for fabricating: A low-temperature process for creating a semiconductive device by printing a liquid composition containing semiconducting nanoparticles. The semiconductive device is formed on a polymeric substrate by printing a composition that contains nanoparticles of inorganic semiconductor suspended in a carrier, using a graphic arts printing method. The printed deposit is then... Agent: Leveque Intellectual Property Law, P.C.

20090057663 - Oxide thin film transistor and method of manufacturing the same: An oxide thin film transistor and a method of manufacturing the oxide TFT are provided. The oxide thin film transistor (TFT) including: a gate; a channel formed to correspond to the gate, and a capping layer having a higher work function than the channel; a gate insulator disposed between the... Agent: Harness, Dickey & Pierce, P.L.C

20090057664 - E-beam inspection structure for leakage analysis: A testing structure, and method of using the testing structure, where the testing structure comprised of at least one of eight test structures that exhibits a discernable defect characteristic upon voltage contrast scanning when it has at least one predetermined structural defect. The eight test structures being: 1) having an... Agent: HorizonIPPte Ltd

20090057665 - Power managing semiconductor die with reduced power consumption: According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external... Agent: Farjami & Farjami LLP

20090057675 - Display device and electronic appliance including the display device: To provide a display device which has a narrower frame region and which includes a driver circuit not affected by variation in transistor characteristics. A base substrate having an insulating surface to which a single-crystal semiconductor layer is attached is divided into strips and is used for a driver circuit... Agent: Eric Robinson

20090057672 - Display device and manufacturing method of the same: A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a... Agent: Nixon Peabody, LLP

20090057667 - Display device and method for fabricating the same: Provided are a display device and a fabricating method thereof. The display device includes a substrate, a gate line, a common line, common electrodes, an insulating layer, a data line, a drain electrode, and pixel electrodes. The gate line is disposed in a first direction. The common line is disposed... Agent: Mckenna Long & Aldridge LLP

20090057668 - Display element and method of manufacturing the same: A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090057669 - Electro-optical device and electronic apparatus: An electro-optical device includes a switching element with a gate electrode provided opposite to the channel region. The gate electrode has a ring-shaped structure that surrounds a junction region between the channel region and a source/drain region.... Agent: Advantedge Law Group, LLC

20090057666 - Pixel structure and fabricating method thereof: A pixel structure and a fabrication method thereof are provided. A substrate with a light-shielding layer and a flat layer formed thereon is provided. A first photomask process is conducted to pattern a first metal layer and a semiconductor layer for forming a source, a drain, a channel layer, a... Agent: Jianq Chyun Intellectual Property Office

20090057673 - Pixel structure of solid-state image sensor: To eliminate uneven distribution of electrons caused by variation in threshold voltages of gates for distributing electrons and to have sensitivity in a long wavelength in a pixel structure of a solid-state image sensor of a charge sorting method, the structure has: a photodiode that generates electrons by photoelectric conversion;... Agent: Birch Stewart Kolasch & Birch

20090057670 - Semiconductor device and process for production thereof: Disclosed herein is a semiconductor device with high reliability which has TFT of adequate structure arranged according to the circuit performance required. The semiconductor has the driving circuit and the pixel portion on the same substrate. It is characterized in that the storage capacitance is formed between the first electrode... Agent: Cook Alex Ltd

20090057676 - Thin film semiconductor device: A thin film semiconductor device is provided which includes an insulating substrate, a Si thin film formed over the insulating substrate, and a transistor with the Si thin film as a channel thereof. The Si thin film includes a polycrystal where a plurality of narrow, rectangular crystal grains are arranged.... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090057674 - Thin film transistor, light-emitting display device having the same and associated methods: A thin film transistor (TFT) includes an N-type oxide semiconductor layer on a substrate, a gate electrode spaced apart from the N-type oxide semiconductor layer by a gate dielectric layer, a source electrode contacting a first portion of the N-type oxide semiconductor layer, and a drain electrode contacting a second... Agent: Lee & Morse, P.C.

20090057671 - Thin-film transistor substrate, method of manufacturing same and display apparatus having same: Contamination is blocked from material of a color filter layer provided on a thin-film transistors (TFT) supporting substrate by sealing over the color filter layer with an inorganic insulating layer. During mass production manufacture, a plasma surface cleaning step is employed after the color filter layer is deposited but before... Agent: Macpherson Kwok Chen & Heid LLP

20090057677 - Ferroelectric device and method for fabricating the same: A method for fabricating a ferroelectric device includes Step S1 of forming a polycrystalline electrode on or above a substrate in which a MOS transistor is formed, Step S2 of performing metal organic chemical vapor deposition to form an amorphous film of bismuth titanate on the polycrystalline electrode, and Step... Agent: Mcdermott Will & Emery LLP

20090057678 - Method of forming an integrated circuit and integrated circuit: A method of forming an integrated circuit, the method including forming at least one patterned gate stack on a substrate including a substrate surface; forming an amorphous substrate region in the substrate by implanting a first material in the substrate; and implanting a getter material to form a getter region... Agent: Slater & Matsil, L.L.P.

20090057680 - Semiconductor device and manufacturing method thereof: To provide a thin film integrated circuit at low cost and with thin thickness, which is applicable to mass production unlike the conventional glass substrate or the single crystalline silicon substrate, and a structure and a process of a thin film integrated circuit device or an IC chip having the... Agent: Eric Robinson

20090057679 - Thin film transistor and manufacturing method thereof: A manufacturing method of a TFT is provided. A polysilicon island, a gate insulating layer and a gate are sequentially formed on a substrate. LDD regions are formed in the polysilicon island below two sides of the gate, while the polysilicon island below the gate is a channel region. A... Agent: Jianq Chyun Intellectual Property Office

20090057681 - Thin-film device, method for manufacturing thin-film device, and display: A method for manufacturing a thin-film device includes forming a separation layer on a substrate, forming a base insulating layer on the separation layer, forming a thin-film device layer on the base insulating layer, bonding a transfer layer including the base insulating layer and the thin-film device layer to a... Agent: Harness, Dickey & Pierce, P.L.C

20090057682 - Active matrix substrate, display device, television receiver, manufacturing method of active matrix substrate, forming method of gate insulating film: In an active matrix substrate of the present invention, a gate insulating film for covering a gate electrode of each transistor has a thin portion, having a reduced film thickness, which is provided on a part overlapped on the gate electrode, and the thin portion is formed by using the... Agent: Nixon & Vanderhye, PC

20090057683 - Semiconductor device and method of manufacturing the semiconductor device: In a semiconductor device, a first interlayer insulating layer made of an inorganic material and formed on inverse stagger type TFTs, a second interlayer insulating layer made of an organic material and formed on the first interlayer insulating layer, and a pixel electrode formed in contact with the second interlayer... Agent: Cook Alex Ltd

20090057684 - Nitride semiconductor device and method for producing nitride semiconductor device: A nitride semiconductor device includes: a semiconductor base layer made of a conductive group III nitride semiconductor having a principal plane defined by a nonpolar plane or a semipolar plane; an insulating layer formed on the principal plane of the semiconductor base layer with an aperture partially exposing the principal... Agent: Rabin & Berdo, PC

20090057685 - Bipolar device and fabrication method thereof: In the invention, the emitter layer or the anode layer is formed of two high-doped and low-doped layers, a semiconductor region for suppressing recombination comprising an identical semiconductor having an impurity density identical with that of the low-doped layer is present being in contact with a base layer or a... Agent: Miles & Stockbridge PC

20090057686 - Semiconductor device and electric power converter, drive inverter, general-purpose inverter and super-power high-frequency communication equipment using the semiconductor device: In a semiconductor device that uses a silicon carbide semiconductor substrate having p type, n type impurity semiconductor regions formed by ion implantation, the electrical characteristics of the end semiconductor device can be improved by decreasing the roughness of the silicon carbide semiconductor substrate surface. The semiconductor device of this... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090057687 - Light emitting diode module:

20090057689 - Light-emitting device: A light-emitting device includes an active region, an n-type region, a p-type region, an n-electrode and a p-electrode. The active region is formed from a semiconductor material. The semiconductor material has a tetrahedral structure and includes an impurity. The impurity creates at least two energy levels connected with the allowed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090057688 - Optical semiconductor device and manufacturing method therefor: To provide an elemental technique for improving the emission intensity of deep ultraviolet light from a light emitting layer made of an AlGaInN-based material, in particular, an AlGaN-based material. First, an AlN layer is grown on a sapphire surface. The AlN layer is grown under a NH3-rich condition. The TMAl... Agent: Lowrie, Lando & Anastasi, LLP

20090057690 - Wafer level phosphor coating technique for warm light emitting diodes: Methods for wafer level fabricating of light emitting diode (LED) chips are disclosed with one embodiment of a method according to the present invention comprising providing a plurality of LEDs and then coating of the LEDs with a layer of first conversion material so that at least some light from... Agent: Koppel, Patrick & Heybl

20090057692 - Semiconductor light emitting device and method for manufacturing the same: Provided is a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises: a first semiconductor layer; a light emitting structure on one sided portion of the first semiconductor layer; a protection device structure on the other sided portion of the first semiconductor... Agent: Birch Stewart Kolasch & Birch

20090057691 - Semiconductor light emitting device and method of manufacturing the same: Provided are a semiconductor light emitting device and a method of manufacturing the same. The semiconductor light emitting layer comprises a first conductive type semiconductor layer, an active layer on the first conductive type semiconductor layer, and a second conductive type semiconductor layer on the active layer. The active layer... Agent: Birch Stewart Kolasch & Birch

20090057693 - Light-emitting element array and image forming apparatus: A light-emitting element array can be manufactured without the separation of a metal reflection layer. The light-emitting element array includes a plurality of light-emitting element portions provided on a substrate, at least one space of the spaces between adjacent light-emitting element portions being electrically separated from each other, wherein the... Agent: Fitzpatrick Cella Harper & Scinto

20090057694 - Light optoelectronic device and forming method thereof: The present invention provides an optoelectronic device with an epi-stacked structure, which includes a substrate, a buffer layer that is formed on the substrate, in which the buffer layer includes a first nitrogen-containing compound layer, an II/V group compound layer is provided on the first nitrogen-containing compound layer, a second... Agent: Sinorica, LLC

20090057695 - Nitride semiconductor device: A nitride semiconductor device according to the present invention sequentially includes at least an n-electrode, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The n-type semiconductor layer includes: an n-type GaN contact layer including n-type impurity-doped GaN having an electron concentration ranging from 5×1016 cm−3 to... Agent: Rabin & Berdo, PC

20090057696 - Light emitting diode device and manufacturing method therof: A light-emitting diode device (LED) device and manufacturing methods thereof are provided, wherein the LED device comprises a substrate, a first n-type semiconductor layer, an n-type three-dimensional electron cloud structure, a second n-type semiconductor layer, an active layer and a p-type semiconductor layer. The first n-type semiconductor layer, the n-type... Agent: Bacon & Thomas, PLLC

20090057697 - Led assembly with led-reflector interconnect: The present invention provides a high output LED assembly including a heat sink (18) and an LED (14) mounted at one end of the heat sink (18). The LED (14) is in electrical engagement with the heat sink (18). The assembly also includes a conductive reflector (12b) mounted to the... Agent: Hoffmann & Baron, LLP

20090057699 - Led with particles in encapsulant for increased light extraction and non-yellow off-state color: In one embodiment, sub-micron size granules of TiO2, ZrO2, or other white colored non-phosphor inert granules are mixed with a silicone encapsulant and applied over an LED. In one experiment, the granules increased the light output of a GaN LED more than 5% when the inert material was between about... Agent: Patent Law Group LLP

20090057698 - Light emission device: A light emitting apparatus 1 comprises: a semiconductor light emitting element 2; and a transparent ceramic phosphor 11 for converting a wavelength of a light emitted from the semiconductor light emitting element 2, wherein the semiconductor light emitting element 2 emits an ultraviolet light, and the ceramic phosphor 11 corresponding... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090057704 - Light emitting diode package having heat dissipating slugs: A light emitting diode package having heat dissipating slugs is provided. The light emitting diode package comprises first and second heat dissipating slugs formed of a conductive material and spaced apart from each other; a package main body coupled to the first and second heat dissipating slugs to support the... Agent: Marger Johnson & Mccollom, P.C.

20090057700 - Light emitting element and a manufacturing method thereof: A light emitting element and a method for manufacturing the same are disclosed. In accordance with the element and the method, the dielectric thin film including the embossed pattern partially covering the sapphire substrate prevents damage of a sapphire substrate that occurs during a texturing of the sapphire substrate and... Agent: The Nath Law Group

20090057701 - Phosphor coating method for fabricating light emmitting semiconductor device and applications thereof: A phosphor coating method for fabricating a light-emitting semiconductor is provided. The phosphor coating method comprises the steps as follows: First a light emitting semiconductor wafer having a plurality of die units formed thereon is provided, and a photoresist is then formed on the light emitting semiconductor wafer to cover... Agent: Joe Mckinney Muncy

20090057703 - Semiconductor light emitting device and method of fabricating thereof: A semiconductor light emitting device and a method of fabricating thereof are provided. The semiconductor light emitting device comprises: a first conductive semiconductor layer having an uneven pattern side; an active layer on the first conductive semiconductor layer; and a second conductive semiconductor layer on the active layer.... Agent: Birch Stewart Kolasch & Birch

20090057702 - Semiconductor light-emitting device: The invention discloses a semiconductor light-emitting device. The semiconductor light-emitting device according to the invention includes a substrate, a multi-layer structure, at least one electrode structure, and a light reflector. The substrate has an upper surface. The multi-layer structure is formed on the upper surface of the substrate. The multi-layer... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090057705 - Semiconductor element mounting substrate, semiconductor device using the same, and method for manufacturing semiconductor element mounting substrate: The invention provides a semiconductor element mounting substrate that, by virtue of an improvement in thermal conduction efficiency between the substrate and another member, can reliably prevent, for example, a light emitting element such as a semiconductor laser from causing a defective operation by heat generation of itself, by taking... Agent: Rabin & Berdo, PC

20090057707 - Semiconductor light emitting device and method for manufacturing same: A semiconductor light emitting device includes: a laminated body including a first semiconductor layer, a second semiconductor layer, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer; a first electrode provided on a first major surface of the laminated body and connected to... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090057706 - Set of ohmic contact electrodes on both p-type and n-type layers for gan-based led and method for fabricating the same: The present disclosure relates to set of a ohmic contact electrodes on both P-type and N-type layers of a GaN-based light emitting diode (LED) and a fabricating method thereof. The materials of ohmic contact electrodes on both P-type and N-type layers of a GaN-based LED are a metal combination of... Agent: Rader, Fishman & Grauer PLLC

20090057708 - Led light source having improved resistance to thermal cycling: A light source and method for making the same are disclosed. The light source includes a substrate, a die, and a cup. The substrate has a plurality of electrical traces thereon and the die includes an LED that is connected to two of the traces. The cup overlies the substrate... Agent: Kathy Manke Avago Technologies Limited

20090057709 - Nitride semiconductor light emitting diode: A nitride semiconductor light emitting diode (LED) comprises an n-type nitride semiconductor layer; an electron emitting layer formed on the n-type nitride semiconductor layer, the electron emitting layer being composed of a nitride semiconductor layer including a transition element of group III; an active layer formed on the electron emitting... Agent: Lowe Hauptman Ham & Berner, LLP

20090057710 - Insulated gate bipolar transistor and method for manufacturing the same: An insulated gate bipolar transistor according to an embodiment includes a first conductive type collector ion implantation area in a substrate; a second conductive type buffer layer, including a first segment buffer layer and a second segment buffer layer, on the first conductive collector ion implantation area; a first conductive... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090057712 - Semiconductor device: The relationship between a distance Ls between a base layer and an n type buffer layer formed on the surface of a drift layer and the thickness t of a semiconductor substrate in contact with the drift layer is set to Ls≦t≦2×Ls. A loss upon turn-off of a high breakdown... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090057711 - Semiconductor device with a u-shape drift region: A semiconductor device with a U-shape drift region comprises a semiconductor substrate of a first conductivity type, a trench filled with an insulator material formed in a portion of a first main surface of the substrate, a cell of the device including the trench and semiconductor region surrounding the trench.... Agent: Townsend And Townsend And Crew, LLP

20090057713 - Semiconductor device with a semiconductor body: A semiconductor body includes a drift zone of a first conduction type. A body zone of a second conduction type complementary to the first conduction type is located near the surface in the semiconductor body. The semiconductor body includes a near-surface field stop zone of the second complementary conduction type... Agent: Dicke, Billig & Czaja

20090057714 - Thyristor and methods for producing a thyristor: A thyristor having a semiconductor body in which a p-doped emitter, an n-doped base, a p-doped base and an n-doped main emitter are arranged successively in a vertical direction starting from a rear face toward a front face. For buffering of the transient heating, a metallization is applied to the... Agent: Dicke, Billig & Czaja

20090057716 - Epitaxial surge protection device: A surge protection device with small-area buried regions (38, 60) to minimize the device capacitance. The doped regions (38, 60) are formed either in a semiconductor substrate (34), or in an epitaxial layer (82), and then an epitaxial layer (40, 84) is formed thereover to bury the doped regions (38,... Agent: Handley Law Firm, PLLC Roger N. Chauza, PC

20090057717 - Low capacitance semiconductor device: A surge protection device with small-area buried regions (38, 60) to minimize the device capacitance. The doped regions (38, 60) are formed either in a semiconductor substrate (34), or in an epitaxial layer (82), and then an epitaxial layer (40, 84) is formed thereover to bury the doped regions (38,... Agent: Handley Law Firm, PLLC Roger N. Chauza, PC

20090057715 - Scr controlled by the power bias: A composite dual SCR circuit that acts to protect the Vcc node as well as an I/O node or pin. The dual SCR uses the Vcc to control or program the triggering point of the SCR connected to an I/O node. When Vcc is low, the SCR protecting an I/O... Agent: Cesari And Mckenna, LLP

20090057718 - High temperature ion implantation of nitride based hemts: A method is disclosed for forming a high electron mobility transistor. The method includes the steps of implanting a Group III nitride layer at a defined position with ions that when implanted produce an improved ohmic contact between the layer and contact metals, with the implantation being carried out at... Agent: Summa, Additon & Ashe, P.A.

20090057719 - Compound semiconductor device with mesa structure: A compound semiconductor device having mesa-shaped element region, and excellent characteristics are provided. The compound semiconductor device has: an InP substrate; an epitaxial lamination mesa formed above the InP substrate and including a channel layer, a carrier supply layer above the channel layer and a contact cap layer above the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090057720 - Field-effect semiconductor device, and method of fabrication: A HEMT-type field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main... Agent: Woodcock Washburn LLP

20090057721 - Semiconductor device, epitaxial wafer, and method of manufacturing the same: A manufacturing method and a semiconductor device produced by the method are provided, in which the semiconductor device can easily be manufactured while the hydrogen concentration is decreased. An N-containing InGaAs layer 3 is grown on an InP substrate by the MBE method, and thereafter a heat treatment is provided... Agent: Fish & Richardson P.C.

20090057722 - Semiconductor device: There is provided a semiconductor device formed of a highly integrated high-speed CMOS inverter coupling circuit using SGTs provided on at least two stages. A semiconductor device according to the present invention is formed of a CMOS inverter coupling circuit in which n (n is two or above) CMOS inverters... Agent: Brinks Hofer Gilson & Lione

20090057723 - Semiconductor device: A semiconductor device including a plurality of semiconductor elements, a substrate on which the plurality of semiconductor elements are mounted, the substrate also having a plurality of terminals for connecting to external equipment, a fuse mounted on the outside of a mounting area of the plurality of semiconductor elements and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090057725 - Image sensor and manufacturing method thereof: Disclosed is an image sensor. The image sensor includes a semiconductor substrate including a lower interconnection, a plurality of upper interconnection sections protruding upward from the semiconductor substrate, a first trench disposed between the upper interconnection sections such that the upper interconnection sections are spaced apart from each other, a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090057724 - Image sensor and sensor unit: An image sensor includes a charge storage portion for storing and transferring signal charges, a first electrode for forming an electric field storing the signal charges in the charge storage portion, a charge increasing portion for increasing the signal charges stored in the charge storage portion and a second electrode... Agent: Ditthavong Mori & Steiner, P.C.

20090057726 - Manufacturing method of semiconductor device, semiconductor device, and electronic device: An embrittlement layer is formed in a single crystal semiconductor substrate having a (110) plane as a main surface by irradiation of the main surface with ions, and an insulating layer is formed over the main surface of the single crystal semiconductor substrate. The insulating layer and a substrate having... Agent: Eric Robinson

20090057727 - Integrated circuit using complementary junction field effect transistor and mos transistor in silicon and silicon alloys: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The... Agent: Baker Botts L.L.P.

20090057728 - Dynamic random access memory having junction field effect transistor cell access device: A dynamic random access memory (DRAM) device can include a plurality of memory cells. Each memory cell can include a charge storing structure and an access device comprising an enhancement mode junction field effect transistor (JFET). The DRAM device can further include a plurality of sense amplifiers that each generates... Agent: Haverstock & Owens, LLP

20090057730 - Methods for forming self-aligned borderless contacts for strain engineered logic devices and structure thereof: A method for forming a borderless contact for a semiconductor FET (Field Effect Transistor) device, the method comprising, forming a gate conductor stack on a substrate, forming spacers on the substrate, such that the spacers and the gate conductor stack partially define a volume above the gate conductor stack, wherein... Agent: Cantor Colburn LLP - IBM Fishkill

20090057731 - Semiconductor device and method of manufacturing the same: In a MOS transistor, a structure of trenches or fins arranged in parallel to a gate length direction is formed in a stepwise manner along a gate width direction to thereby reduce a step height of each step. Even if the MOS transistor includes a deep trench or a high... Agent: Brinks Hofer Gilson & Lione

20090057729 - Semiconductor device and methods for fabricating same: A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20090057732 - Cmos image sensor and fabricating method thereof: A CMOS image sensor and a fabricating method for a semiconductor device are disclosed. Embodiments provide a CMOS image sensor having an improved structure using a light reflection system, with a fabricating method thereof to simplify the fabrication process and maximize a light receiving area. Embodiments may be applied to... Agent: Sherr & Vaughn, PLLC

20090057734 - Image sensor: An image sensor includes a photoelectric conversion portion generating signal charges, a first electrode for forming an electric field transferring the signal charges generated by the photoelectric conversion portion, formed to be adjacent to the photoelectric conversion portion; and a second electrode for forming an electric field transferring the signal... Agent: Ditthavong Mori & Steiner, P.C.

20090057733 - Image sensor and a method for manufacturing the same: An image sensor and manufacturing method thereof are provided. A semiconductor substrate can include a light blocking region and a light receiving region. A photodiode can be formed in the light blocking region and in the light receiving region. A gate can be disposed at a side of the photodiode... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090057735 - Image sensor having reduced dark current: An image sensor includes a light receiving device, a field effect transistor, a stress layer pattern, and a surface passivation material. The light receiving device is formed in a first region of a substrate. The field effect transistor is formed in a second region of the substrate. The stress layer... Agent: Law Office Of Monica H Choi

20090057737 - Integrated circuit with dielectric layer: A method of fabricating an integrated circuit with a dielectric layer on a substrate is disclosed. One embodiment provides forming the dielectric layer in an amorphous state on the substrate, the dielectric layer having a crystallization temperature; a doping the dielectric layer; a forming of a covering layer on the... Agent: Dicke, Billig & Czaja

20090057736 - Semiconductor device having reduced single bit fails and a method of manufacture thereof: One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The... Agent: Texas Instruments Incorporated

20090057738 - Capacitor for semiconductor device: A capacitor for a semiconductor device having a dielectric film between an upper electrode and a lower electrode is featured in that the dielectric film includes an alternately laminated film of hafnium oxide and titanium oxide at an atomic layer level.... Agent: Sughrue Mion, PLLC

20090057739 - Ge channel device and method for fabricating ge channel device: The Ge channel device comprises: a Ge channel layer (2); a Si-containing interface layer (4) formed on the Ge channel layer (2); a La2O3 layer (6) formed on the interface layer (4); and an electrically conductive layer (8) formed on the La2O3 layer (6). In this device, the Si-containing interface... Agent: Staas & Halsey LLP

20090057740 - Memory with surface strap: A memory with a surface strap. The memory comprises a trench capacitor, a self-aligned surface strap and a MOS transistor. The trench capacitor is formed in a semiconductor substrate. The self-aligned surface strap covers an opening of the trench capacitor and a active region in the periphery thereof. One of... Agent: Joe Mckinney Muncy

20090057741 - Dram cell with enhanced capacitor area and the method of manufacturing the same: A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor. The cell capacitor includes a first, second and third dielectric layer, and a first, second and third capacitor electrode. The first dielectric layer... Agent: Joe Mckinney Muncy

20090057742 - Cmos varactor: A varactor and method of fabricating the varactor. The varactor includes a silicon body in a silicon layer of an SOI substrate; a polysilicon electrode comprising a gate region and a plate region separated from the body by a gate dielectric layer, the gate and plate regions contiguous, the electrode... Agent: Schmeiser, Olsen & Watts

20090057743 - Integrated circuit including structures arranged at different densities and method of forming the same: A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the first structures, in a second portion. The first and second structures are defined by lithography processes using photomasks. At least... Agent: Edell, Shapiro & Finnan, LLC

20090057744 - Thickened sidewall dielectric for memory cell: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and... Agent: Knobbe Martens Olson & Bear LLP

20090057745 - Inverted nonvolatile memory device, stack module, and method of fabricating the same: Example embodiments provide a nonvolatile memory device that may be integrated through stacking, a stack module, and a method of fabricating the nonvolatile memory device. In the nonvolatile memory device according to example embodiments, at least one bottom gate electrode may be formed on a substrate. At least one charge... Agent: Harness, Dickey & Pierce, P.L.C

20090057747 - Nonvolatile memory device and method for fabricating the same: A nonvolatile memory device including a floating gate formed on a tunnel oxide layer that is formed on a semiconductor substrate. The device also includes a drain region formed in the substrate adjacent to one side of the floating gate, a source region formed in the substrate adjacent to another... Agent: Lowe Hauptman Ham & Berner, LLP

20090057746 - Semiconductor device: A semiconductor device having a passive element whose characteristic is adjustable even after manufacture by applying back bias voltage is provided. Formed on a main surface of a SOI substrate comprising a supporting substrate, a BOX layer, and an SOI layer is a MOS varactor comprising a gate dielectric formed... Agent: Miles & Stockbridge PC

20090057748 - Memory and manufacturing method thereof: A memory and a manufacturing method thereof are provided. The memory includes a dielectric layer, a polysilicon layer, a first buried diffusion, a second buried diffusion, a charge storage structure and a gate. The polysilicon layer is disposed on the dielectric layer and electrically connected to at least a voltage.... Agent: Bacon & Thomas, PLLC

20090057749 - Nonvolatile semiconductor memory device: A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090057751 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an example of the present invention includes a semiconductor region, source/drain areas arranged separately in the semiconductor region, a tunnel insulating film arranged on a channel region between the source/drain areas, a floating gate electrode arranged on the tunnel insulating film, an inter-electrode... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090057750 - Nonvolatile semiconductor memory element and manufacturing method thereof: A nonvolatile semiconductor memory element includes a semiconductor substrate, a source region and a drain region which are provided separately in the semiconductor substrate, a tunnel insulating layer which is provided between the source region and the drain region on the semiconductor substrate, a charge storage layer which is provided... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090057752 - Non-volatile memory and method for manufacturing the same: A non-volatile memory located on a substrate is provided. The non-volatile memory includes a tunnel layer, a charge trapping composite layer, a gate and a source/drain region. The tunnel layer is located on the substrate, the charge trapping composite layer is located on the tunnel layer and the gate is... Agent: J C Patents, Inc.

20090057753 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a source region and a drain region spaced from each other in a surface of a semiconductor layer, a tunnel insulating film provided on the semiconductor layer between the source region and the drain region, a charge storage film provided on the tunnel insulating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090057754 - Shielded gate trench fet with the shield and gate electrodes connected together in non-active region: A field effect transistor (FET) includes a plurality of trenches extending into a semiconductor region. Each trench includes a gate electrode and a shield electrode with an inter-electrode dielectric therebetween. A body region extends between each pair of adjacent trenches, and source regions extend in each body region adjacent to... Agent: Townsend And Townsend And Crew, LLP

20090057755 - Spacer undercut filler, method of manufacture thereof and articles comprising the same: Disclosed herein is a semiconducting device comprising a gate stack formed on a surface of a semiconductor substrate; a vertical nitride spacer element formed on each vertical sidewall of the gate stack; a portion of the vertical nitride spacer overlying the semiconductor substrate; a silicide contact formed on the semiconductor... Agent: Cantor Colburn LLP - IBM Fishkill

20090057757 - Trench gate semiconductor device and method of manufacturing the same: Disclosed is a trench gate semiconductor device including: a semiconductor layer having a first conductivity type; a first diffusion region having a second conductivity type having a planar structure on the semiconductor layer; a second diffusion region having the first conductivity type positioned selectively on the first diffusion region; a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090057756 - Trench mosfet with trench termination and manufacture thereof: A trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with a trench termination, including a substrate including a drain region which is strongly doped and a doping epi layer region, which is weekly doped the same type as the drain region, on the drain region; a plurality of source and body regions... Agent: Wpat, PC Intellectual Property Attorneys

20090057758 - Thin silicon-on-insulator high voltage transistor with body ground: A silicon (Si)-on-insulator (SOI) high voltage transistor with a body ground is provided with an associated fabrication process. The method provides a SOI substrate with a buried oxide (BOX) layer and a Si top layer having a first thickness and a second thickness, greater than the first thickness. A body... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20090057759 - Mos device and process having low resistance silicide interface using additional source/drain implant: An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a... Agent: Texas Instruments Incorporated

20090057761 - Fin field effect transistor and method of manufacturing the same: Provided are a FinFET and a method of manufacturing the same. A FinFET may include at least one active fin, at least one gate insulating layer pattern, a first electrode pattern, a second electrode pattern and at least one pair of source/drain expansion regions. The at least one active fin... Agent: Harness, Dickey & Pierce, P.L.C

20090057760 - Semiconductor device and fabricating method thereof: A semiconductor device and fabricating method thereof are disclosed, by which channel mobility is enhanced and by which effect of flicker noise can be minimized. Embodiments relate to a method of fabricating a semiconductor device which includes forming a first epi-layer over a substrate, forming a second epi-layer over the... Agent: Sherr & Vaughn, PLLC

20090057762 - Nanowire field-effect transistors: Field-effect transistors (FETs) having nanowire channels are provided. In one aspect, a FET is provided. The FET comprises a substrate having a silicon-on-insulator (SOI) layer which is divided into at least two sections electrically isolated from one another, one section included in a source region and the other section included... Agent: Michael J. Chang, LLC

20090057763 - Semiconductor memory device and manufacturing method thereof: This disclosure concerns a semiconductor memory device including an insulating film; a semiconductor layer provided on the insulating film; a source provided in the semiconductor layer; a drain provided in the semiconductor layer; a floating body provided between the source and the drain and being in an electrically floating state,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090057764 - Thin film transistor and display apparatus: A thin film transistor includes a crystal growth region in which a crystal is two-dimensionally grown on a plane, a source region and a drain region formed in the crystal growth region, and a gate electrode which is formed on a channel region between the source region and the drain... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090057765 - Finfet structure using differing gate dielectric materials and gate electrode materials: A semiconductor structure includes a first finFET and a second finFET. The first finFET and the second finFET may comprise an n-finFET and a p-finFET to provide a CMOS finFET structure. Within the semiconductor structure, at least one of: (1) a first gate dielectric within the first finFET and a... Agent: Scully, Scott, Murphy & Presser, P.C.

20090057766 - Integration of silicon boron nitride in high voltage and small pitch semiconductors: Integration of silicon boron nitride in high voltage semiconductors is generally described. In one example, a microelectronic apparatus includes a semiconductor substrate upon which transistors of an integrated circuit are formed, a plurality of transistor gates formed upon the semiconductor substrate, a gate spacer dielectric disposed between the gates, and... Agent: Cool Patent, P.C. C/o Intellevate

20090057767 - Semiconductor device, method for manufacturing the same, and method for driving the same: A semiconductor device includes a protected device formed on a semiconductor substrate, a first protection transistor formed in a second well of a second conductivity type, and a second protection transistor formed in a first well of a first conductivity type. A fourth source/drain diffusion layer of the second protection... Agent: Mcdermott Will & Emery LLP

20090057768 - Electrostatic discharge protection circuit: Disclosed is an ESD protection circuit, which includes: an ESD protection element, coupled to a pad; a transmitting gate circuit; an N MOSFET, for providing a first biasing voltage to the transmitting gate circuit according to the second voltage level; a first P MOSFET, for providing a second biasing voltage... Agent: North America Intellectual Property Corporation

20090057769 - Cmos device having gate insulation layers of different type and thickness and a method of forming the same: In the process sequence for replacing conventional gate electrode structures by high-k metal gate structures, the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps, thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques... Agent: Williams, Morgan & Amerson

20090057772 - Replacement gates to enhance transistor strain: Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090057770 - Semiconductor device and method of fabricating the same: A semiconductor device capable of preventing malfunction of a Schottky diode to reduce a failure ratio of the semiconductor device and a method for fabricating the same are disclosed. The semiconductor device includes first and second CMOS switching devices formed over a silicon substrate, a Schottky diode formed in a... Agent: Sherr & Vaughn, PLLC

20090057771 - Semiconductor device and method of manufacturing the same: Disclosed herein is a semiconductor device including a semiconductor substrate provided with an N-type FET and P-type FET, with a gate electrode of the N-type FET and a gate electrode of the P-type FET having undergone full-silicidation, wherein the gate electrode of the P-type FET has such a sectional shape... Agent: Sonnenschein Nath & Rosenthal LLP

20090057774 - Methods of forming bipolar transistors by silicide through contact and structures formed thereby: Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming an opening in a masking layer, implanting an amorphizing species into a silicon region disposed within the opening, wherein the silicon region comprises a portion of an emitter of a bipolar transistor; and forming... Agent: Intel Corporation C/o Intellevate, LLC

20090057773 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device including a complementary metal oxide semiconductor (CMOS) and a bipolar junction transistor (BJT), the method comprising the steps of: forming a gate oxide layer on a substrate having a p-type and an n-type well; removing the gate oxide layer on the p-type well;... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090057775 - Semiconductor device and method for manufacturing semiconductor device: A method for manufacturing a semiconductor device, including etching exposed areas of a substrate using patterned nitride and insulating layers as an etch mask to form a trench in the substrate; forming a buffer layer in the trench; forming a stress-inducing layer by implanting ions into a region of the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090057776 - Method of forming fully silicided nmos and pmos semiconductor devices having independent polysilicon gate thicknesses, and related device: A method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device. At least some of the illustrative embodiments are methods comprising forming an N-type gate over a semiconductor substrate (the N-type gate having a first thickness), forming a P-type gate over the... Agent: Texas Instruments Incorporated

20090057777 - Semiconductor device: A semiconductor device comprises a semiconductor substrate, a plurality of transistors provided in the semiconductor substrate, and an isolation region for isolating the plurality of transistors to one another, the isolation region being comprised of an isolating insulation film, wherein a crystal structure of at least a part of the... Agent: Foley And Lardner LLP Suite 500

20090057778 - Integrated circuit and method of manufacturing an integrated circuit: An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising... Agent: Thomas G. Eschweiler, Esq. Eschweiler & Associates, LLC

20090057779 - Semiconductor device and method of fabricating the same: A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a semiconductor substrate having a first area implanted with first conductive type impurities; an isolating film defining a first active area and a second active area in the first area; first LDD areas spaced... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090057780 - Finfet structure including multiple semiconductor fin channel heights: A semiconductor structure and a method for fabricating the semiconductor structure include a first semiconductor fin and a second semiconductor fin of the same overall height over a substrate. Due to the presence of a channel stop layer at the base of one of the first semiconductor fin and the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090057781 - Mugfet with optimized fill structures: A semiconductor structure includes active multi-gate fin-type field effect transistor (MUGFET) structures and inactive MUGFET fill structures between the active MUGFET structures. The active MUGFET structures comprise transistors that change conductivity depending upon voltages within gates of the active MUGFET structures. Conversely, the inactive MUGFET fill structures comprise passive devices... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090057782 - Semiconductor device: A semiconductor device is disclosed. Embodiments relate to a semiconductor device which includes an active region including a source region, a drain region, and a channel region. A gate electrode, source electrodes, and a drain electrode are formed around the active region. A plurality of gate fingers diverge from the... Agent: Sherr & Vaughn, PLLC

20090057783 - Semiconductor device and method of fabricating metal gate of the same: Provided is a semiconductor device and a method of fabricating a metal gate in the semiconductor device. The semiconductor device includes a metal gate formed on a gate insulating film, the metal gate is formed of a mixture of a metal nitride and a metal carbide, and a work function... Agent: Harness, Dickey & Pierce, P.L.C

20090057784 - Extension tailored device: The present invention discloses a semiconductor device with tailored extension structure comprising a semiconductor substrate. A gate dielectric is formed on the semiconductor substrate. A gate is formed on the gate dielectric. A first isolation layer is formed over the sidewall of the gate. Dielectric spacers are formed on the... Agent: Birch Stewart Kolasch & Birch

20090057785 - Method of fabricating extended drain mos transistor: A method of fabricating an extended drain MOS transistor which reduces a design rule and prevents the generation of leakage current. The method includes sequentially forming a diffusion film, a first conductive epitaxial layer, a gate oxide layer and a hard mask layer over a semiconductor substrate, forming a first... Agent: Sherr & Vaughn, PLLC

20090057786 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device includes a high dielectric constant gate insulator film provided on a Si substrate which is a semiconductor substrate, a gate electrode formed on the high dielectric constant gate insulator film, a protective film provided on side surfaces of the high dielectric constant gate insulator film and the... Agent: Sonnenschein Nath & Rosenthal LLP

20090057787 - Semiconductor device: There is provided a semiconductor device which can control a reaction caused between a gate electrode and a high-k gate dielectric film, and which has an element structure suitable for higher integration and speed-up. The semiconductor device has an insulated-gate field-effect transistor, wherein the insulated-gate field-effect transistor has: a gate... Agent: Young & Thompson

20090057788 - Angled implantation for removal of thin film layers: Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more angled ion implants, then... Agent: Intel Corporation C/o Intellevate, LLC

20090057791 - Microchip and soi substrate for manufacturing microchip: A plasma treatment or an ozone treatment is applied to the respective bonding surfaces of the single-crystal Si substrate in which the ion-implanted layer has been formed and the quartz substrate, and the substrates are bonded together. Then, a force of impact is applied to the bonded substrate to peel... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090057790 - Package for a micro-electro mechanical device: A package for a micro-electromechanical device (MEMS package) includes an inner enclosure having an inner cavity defined therein, and a fill port channel communicating with the inner cavity and of sufficient length to allow a quantity of adhesive to enter the fill port channel while preventing the adhesive from entering... Agent: Hewlett Packard Company

20090057789 - Package structure for micro-sensor: The invention discloses a package structure for a micro-sensor including a micro-cantilever for capturing a chemical substance. The package structure, according to the invention, includes a first substrate, a second substrate, and a casing. The first substrate thereon forms a processing circuit. The micro-sensor is bonded to a first upper... Agent: Morris Manning Martin LLP

20090057792 - Charge biased mem resonator: A resonator has a vibrating element (10) and at least a first (20) and a second (30) electrode, at least one of the electrodes storing an electric charge to make the device charge biased. A charge adjuster (C) can add to or reduce the stored charge. The charge adjuster can... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090057794 - Planar flux concentrator for mram devices: The present invention provides an MRAM that includes a conductive line for generating a magnetic field. The latter is enhanced by the addition of a flux concentrator made from a single plane of soft ferromagnetic material, magnetically stabilized by means of an antiferromagnetic layer. This structure, in addition to being... Agent: Saile Ackerman LLC

20090057793 - Spin transistor and method of manufacturing same: The spin transistor in accordance with the present invention comprises a magnetoresistive element having a fixed layer, a free layer, and a semiconductor layer provided between the fixed layer and free layer; a source electrode layer electrically connected to one end face in a laminating direction of the magnetoresistive element;... Agent: Oliff & Berridge, PLC

20090057795 - Sensor chip having conductivity film: A sensor chip is provided that includes a sensor element and a control circuit for controlling the sensor element disposed in semiconductor substrate. The control circuit includes a plurality of circuit elements, each of which is isolated by P-N junction separation. The sensor chip further includes a conductivity film disposed... Agent: Posz Law Group, PLC

20090057797 - Image sensor and a method for manufacturing the same: An image sensor and manufacturing method thereof are provided. An insulating layer having a wiring can be provided on a semiconductor substrate. A barrier wiring can be provided in the insulating layer between the wiring of a unit pixel and an adjacent wiring of an adjacent pixel. A device isolating... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090057798 - Method of producing semiconductor device, solid-state imaging device, method of producing electric apparatus, and electric apparatus: There is provided a method of producing a semiconductor device. The method includes the steps of: forming a first hard mask having an opening above a substrate; forming a sacrificial film above a side surface of the opening of the first hard mask; forming a second hard mask in the... Agent: Rader Fishman & Grauer PLLC

20090057796 - Photodiode being monolithically integrated onto a waveguide: A waveguide-integrated photodiode for high bandwidths with a semi-insulating monomode supply waveguide monolithically integrated on a substrate, together with an overlying photodiode mesa structure having an electroconducting n-contact layer, an absorption layer, a p+-contact layer and a metallic p-contact, the refraction index of the n-contact layer being greater than the... Agent: Indianapolis Office 27879 Brinks Hofer Gilson & Lione

20090057799 - Sensor semiconductor device and method for fabricating the same: A sensor semiconductor device and a method for fabricating the same are provided. At least one sensor chip is mounted and electrically connected to a lead frame. A first and a second encapsulation molding processes are sequentially performed to form a transparent encapsulant for encapsulating the sensor chip and a... Agent: Edwards Angell Palmer & Dodge LLP

20090057800 - Small-size module: According to one embodiment, a small-size module an IC chip having leads provided on at least two sides of the IC chip, a circuit substrate having a component mounting face, plural pairs of auxiliary substrates which are disposed between the component mounting face of the circuit substrate and the IC... Agent: Knobbe Martens Olson & Bear LLP

20090057801 - Back-illuminated, thin photodiode arrays with trench isolation: Back-illuminated, thin photodiode arrays with trench isolation. The trenches are formed on one or both sides of a substrate, and after doping the sides of the trenches, are filled to provide electrical isolation between adjacent photodiodes. Various embodiments of the photodiode arrays and methods of forming such arrays are disclosed.... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090057802 - Image sensor and method for manufacturing the same: Provided are an image sensor and a manufacturing method thereof. The image sensor can include a first epitaxial layer with a first ion implantation layer, a second epitaxial layer with a second ion implantation layer, and a third epitaxial layer with a third ion implantation layer on a substrate. The... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090057803 - Solid-state imaging device, camera and method of producing the solid-state image device: A solid-state imaging device in which a first conductive type epitaxial layer is formed on its first surface with an interconnection layer and light is received at a second surface of said epitaxial layer, the solid-state imaging device including: (a) a second conductive type region formed in said epitaxial layer... Agent: Sonnenschein Nath & Rosenthal LLP

20090057804 - Threshold voltage compensation for pixel design of cmos image sensors: The present disclosure is directed to a CMOS active pixel sensor that compensates for variations in a threshold voltage of a source follower contained therein. A structure in accordance with an embodiment includes: a replica source follower transistor; a system for creating a current in said replica source follower transistor... Agent: Hoffman Warnick LLC

20090057805 - Ultraviolet sensor: The ultraviolet sensor has a ZnO layer composed of an oxide semiconductor including ZnO; a (Ni,Zn)O layer which is provided in contact with the ZnO layer and which is composed of an oxide semiconductor including NiO and ZnO solid-solved therein; a first terminal electrode electrically connected to the ZnO layer,... Agent: Dickstein Shapiro LLP

20090057806 - Segmented photodiode: In one embodiment of the present invention, the segmented photodiode includes a p type substrate, a p type epitaxial layer formed on the p type substrate, an n type epitaxial layer formed on the p type epitaxial layer, and p type segmenting region provided in the n type epitaxial layer... Agent: Young & Thompson

20090057807 - Schottky barrier diode and manufacturing method thereof: The invention provides a Schottky barrier diode in which a forward voltage is low, a backward leakage current is small, and a withstanding voltage of an element is high, by improving both the forward voltage VF and the backward leakage current IR. A Schottky barrier diode of the invention includes... Agent: Mcdermott Will & Emery LLP

20090057808 - Semiconductor device, semiconductor element, and substrate: A semiconductor device, a semiconductor element, and a substrate are provided, which allow the semiconductor element to be provided with a reduced size when combined. The semiconductor device of the invention has a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal,... Agent: Volentine & Whitt PLLC

20090057809 - Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device: By forming a stressed dielectric layer on different transistors and subsequently relaxing a portion thereof, the overall process efficiency in an approach for creating strain in channel regions of transistors by stressed overlayers may be enhanced while nevertheless transistor performance gain may be obtained for each type of transistor, since... Agent: J. Mike Amerson, Williams, Morgan & Amerson, P.C.

20090057810 - Method of fabricating an integrated circuit: A method of fabricating an integrated circuit includes providing a semiconductor substrate having a doped area; generating a conductive structure towards the doped area, wherein the conductive structure includes an extending section that protrudes from the doped area; generating an electrically isolating layer at a sidewall of the extending section... Agent: Slater & Matsil, L.L.P.

20090057812 - Semiconductor device having multiple element formation regions and manufacturing method thereof: In a manufacturing of a semiconductor device, at least one of elements is formed in each of element formation regions of a substrate having a main side and a rear side, and the substrate is thinned by polished from a rear side of the substrate, and then, multiple trenches are... Agent: Posz Law Group, PLC

20090057811 - Simox wafer manufacturing method and simox wafer: A SIMOX wafer manufacturing method which is capable of providing etching conditions to prevent surface defects (divots) from being spread. The method includes an oxygen implantation process and a high temperature annealing step for forming a BOX layer, a front surface oxide film etching process to treat a front surface... Agent: Greenblum & Bernstein, P.L.C

20090057813 - Method for self-aligned removal of a high-k gate dielectric above an sti region: By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring... Agent: Williams, Morgan & Amerson

20090057814 - Semiconductor memory: A semiconductor memory according to an example of the invention includes active areas, and element isolation areas which isolate the active areas. The active areas and the element isolation areas are arranged alternately in a first direction. An n-th (n is odd number) active area from an endmost portion in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090057815 - Forming channel stop for deep trench isolation prior to deep trench etch: Methods of manufacturing a semiconductor structure are disclosed including a deep trench isolation in which a channel stop is formed in the form of an embedded impurity region in the substrate prior to the deep trench etch and formation of transistor devices (FEOL processing) on the substrate. In this fashion,... Agent: Hoffman Warnick LLC

20090057816 - Method to reduce residual sti corner defects generated during spe in the fabrication of nano-scale cmos transistors using dsb substrate and hot technology: A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the... Agent: Texas Instruments Incorporated

20090057817 - Microelectromechanical system and process of making the same: A micro electromechanical system and a fabrication method thereof, which has trenches formed on a substrate to prevent circuits from interfering each other, and to prevent over-etching of the substrate when releasing a microstructure.... Agent: Dr. Banger Shia

20090057819 - Electrical fuse device: The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one... Agent: Volentine & Whitt PLLC

20090057818 - Methods and systems involving electrically programmable fuses: An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse.... Agent: Cantor Colburn LLP - IBM Fishkill

20090057820 - Abrupt metal-insulator transition device with parallel conducting layers: An abrupt MIT (metal-insulator transition) device with parallel conducting layers is provided. The abrupt MIT device includes a first electrode disposed on a certain region of a substrate, a second electrode disposed so as to be spaced a predetermined distance apart from the first electrode, and at least one conducting... Agent: Rabin & Berdo, PC

20090057821 - Reprogrammable metal-to-metal antifuse employing carbon-containing antifuse material: A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group comprising at least one of amorphous carbon... Agent: Lewis And Roca LLP

20090057824 - Inductor of semiconductor device and method for manufacturing the same: An inductor of a semiconductor device and a method for manufacturing the same are disclosed. The inductor has a spiral structure, and includes a semiconductor substrate formed with a sub-structure. At least one metal line layer may be formed over the semiconductor substrate. At least one inductor line layer may... Agent: Sherr & Vaughn, PLLC

20090057822 - Semiconductor component and method of manufacture: A semiconductor component that includes a leadframe, a discrete passive circuit element, and an active circuit element. The discrete passive circuit element such as, for example, a discrete ferrite core inductor, is mounted either laterally or vertically adjacent to the leadframe. A semiconductor chip is attached to the discrete ferrite... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20090057825 - Semiconductor device and a method for fabricating the same: A semiconductor device including an inductor and a fabricating method thereof are provided. The semiconductor device can include a connection wiring provided on a semiconductor substrate; a metal wiring provided on an insulating layer in a spiral shape and electrically connected to the connection wiring; and holes provided in the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090057823 - Semiconductor structure with a discontinuous material density for reducing eddy currents: A semiconductor structure includes an inductor; and a semiconductor substrate underlying the inductor, having a discontinuous material density across a plane underneath and in parallel with the inductor, thereby reducing eddy currents induced by an electrical current flowing through the inductor.... Agent: K & L Gates LLP

20090057827 - Capacitor embedded in interposer, semiconductor device including the same, and method for manufacturing capacitor embedded in interposer: As for electrode pads for a semiconductor integrated circuit element, some of electrode pads for signal transmission are coupled to Ti films. Others of the electrode pads for signal transmission are coupled to electrode pads through wiring routed in multilayer wiring. Electrode pads for power supply are coupled to electrode... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090057828 - Metal-insulator-metal capacitor and method for manufacturing the same: A metal-insulator-metal (MIM) capacitor having fast frequency characteristics and a method for manufacturing the same are disclosed. The disclosed MIM capacitor may include a first intermetal insulating film, a lower metal layer formed over the first intermetal insulating film, a second intermetal insulating film formed around the lower metal layer,... Agent: Sherr & Vaughn, PLLC

20090057829 - Semiconductor device and method of designing the same: A semiconductor device includes a first wiring layer, a second wiring layer and an insulating layer provided between the first wiring layer and the second wiring layer. A capacitor has a first electrode formed on the first wiring layer and a second electrode formed on the second wiring layer in... Agent: Cantor Colburn, LLP

20090057826 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a capacitor plate includes a first propeller-shaped portion and a second propeller-shaped portion. A via portion is disposed between the first propeller-shaped portion and the second propeller-shaped portion.... Agent: Slater & Matsil LLP

20090057830 - Semidoncudtor device and method of manufacturing the same: On a surface of a semiconductor substrate, an epitaxial layer of a conductivity type opposite to a conductivity type of the semiconductor substrate is formed, trenches are formed in portions other than a portion serving as a resistor, and the trenches are filled with an insulating film to three-dimensionally form... Agent: Bruce L. Adams, Esq Adams & Wilks

20090057831 - Semiconductor device and method of forming a semiconductor device: A high voltage/power semiconductor device has a semiconductor layer having a high voltage terminal end and a low voltage terminal end. A drift region extends between the high and low voltage terminal ends. A dielectric layer is provided above the drift region. An electrical conductor extends across at least a... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20090057832 - Semiconductor device having diode-built-in igbt and semiconductor device having diode-built-in dmos: A semiconductor device includes: a semiconductor substrate; a diode-built-in insulated-gate bipolar transistor having an insulated-gate bipolar transistor and a diode, which are disposed in the substrate, wherein the insulated-gate bipolar transistor includes a gate, and is driven with a driving signal input into the gate; and a feedback unit for... Agent: Posz Law Group, PLC

20090057833 - Semiconductor device structure and integrated circuit therefor: A semiconductor device structure comprises a plurality of vertical layers and a plurality of conductive elements wherein the vertical layers and plurality of conductive elements co-operate to function as at least two active devices in parallel. The semiconductor device structure may also comprise a plurality of horizontal conductive elements wherein... Agent: Freescale Semiconductor, Inc. Law Department

20090057834 - Method for chemical mechanical planarization of chalcogenide materials: A method and associated composition for chemical mechanical planarization of a chalcogenide-containing substrate (e.g., germanium/antimony/tellurium (GST)-containing substrate) are described. The composition and method afford low defect levels as well as low dishing and local erosion levels on the chalcogenide-containing substrate during CMP processing.... Agent: Air Products And Chemicals, Inc. Patent Department

20090057835 - Group iii nitride semiconductor and a manufacturing method thereof: A manufacturing method of a group III nitride semiconductor includes the steps of: depositing a metal layer on an AlN template substrate or an AlN single crystal substrate formed by depositing an AlN single crystal layer with a thickness of not less than 0.1 μm nor more than 10 μm... Agent: Rader Fishman & Grauer PLLC

20090057836 - Semiconductor device having electrode film in which film thickness of periphery is thinner than film thickness of center: A semiconductor device includes a substrate having first main face having rectangular shape, a first electrode provided at the center on first main face of substrate, first electrode is made of conducting material harder than substrate, and a second electrode provided along at least a part of the periphery on... Agent: Rabin & Berdo, PC

20090057838 - Manufacturing method for semiconductor chips, and semiconductor chip: In a manufacturing method for performing plasma etching on a second surface of a semiconductor wafer that has a first surface where an insulating film is placed in dividing regions and the second surface which is opposite from the first surface and on which a mask for defining the dividing... Agent: Wenderoth, Lind & Ponack L.L.P.

20090057839 - Polymer-embedded semiconductor rod arrays: A structure consisting of well-ordered semiconductor structures embedded in a binder material which maintains the ordering and orientation of the semiconductor structures. Methods for forming such a structure include forming the semiconductor structures on a substrate, casting a binder material onto the substrate to embed the semiconductor structures in the... Agent: Steinfl & Bruno

20090057840 - Wafer manufacturing method, polishing apparatus, and wafer: The present invention provides a wafer manufacturing method and a wafer polishing apparatus which enable control of sags in a periphery of a wafer and improvement of nanotopology values thereof that is strongly required recently, and a wafer. In a polishing process for making a mirror surface of the wafer,... Agent: Rader Fishman & Grauer PLLC

20090057837 - Wafer with edge notches encoding wafer identification descriptor: An apparatus includes a semiconductor wafer having a surface terminating in an edge. A plurality of notches is defined along the edge. The plurality of notches encodes a wafer identification descriptor for the wafer. A system for identifying wafers includes a wafer sorter. The wafer sorter is adapted to scan... Agent: Williams, Morgan & Amerson

20090057841 - Wafer: A wafer having a device region, where a plurality of devices is formed, and an outer peripheral surplus region, which surrounds the device region, on the face of a circular wafer substrate is disclosed. A chamfered portion whose cross-sectional shape defines an arc-shaped surface in a range from the face... Agent: Greenblum & Bernstein, P.L.C

20090057842 - Selective removal of on-die redistribution interconnects from scribe-lines: Selective removal of on-die redistribution interconnect material from a scribe-line region is generally described. In one example, an apparatus includes a first semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, a second semiconductor die coupled with the first semiconductor die, the second... Agent: Cool Patent, P.C. C/o Intellevate

20090057843 - Semiconductor assemblies and methods of manufacturing such assemblies: Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of manufacturing a semiconductor device includes forming a plurality of first side trenches to an intermediate depth in a molded portion of a molded wafer having a plurality of dies... Agent: Perkins Coie LLP Patent-sea

20090057845 - Apparatus to saw wafer and having nozzle to remove burrs in scribe lanes, method of sawing wafer, and semiconductor package fabricated by the same: An apparatus to saw a wafer and having a nozzle to remove burrs in scribe lanes, a method of sawing a wafer, and a semiconductor package fabricated by the same. The apparatus includes a blade to cut scribe lanes of the wafer and a burr removing nozzle disposed spaced apart... Agent: Stanzione & Kim, LLP

20090057844 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device 1 comprises a semiconductor substrate 2 having a through hole 3. A first insulation layer 4 having an opening 4a equal in diameter to the through hole 3 covers a front surface of the semiconductor substrate 2, and a first wiring layer 5 is formed thereon to... Agent: Amin, Turocy & Calvin, LLP

20090057846 - Method to fabricate adjacent silicon fins of differing heights: A method to fabricate adjacent silicon fins of differing heights comprises providing a silicon substrate having an isolation layer deposited thereon, patterning the isolation layer to form first and second isolation structures, patterning the silicon substrate to form a first silicon fin beneath the first isolation structure and a second... Agent: Intel Corporation C/o Intellevate, LLC

20090057847 - Gallium nitride wafer: A gallium nitride wafer 11 has a substantially circular shape. The gallium nitride wafer 11 includes a plurality of stripe regions 13, a plurality of single crystal regions 15, and a visible mark 17. Each stripe region 13 represents the direction of <11-20> axis and extends in a direction of... Agent: Mcdermott Will & Emery LLP

20090057848 - Redistribution structures for microfeature workpieces: Microfeature dies with redistribution structures that reduce or eliminate line interference are disclosed. The microfeature dies can include a substrate having a bond site and integrated circuitry electrically connected to the bond site. The microfeature dies can also include and a redistribution structure coupled to the substrate. The redistribution structure... Agent: Perkins Coie LLP Patent-sea

20090057849 - Interconnect in a multi-element package: A packaged semiconductor device includes an interconnect layer over a first side of a polymer layer, a semiconductor device surrounded on at least three sides by the polymer layer and coupled to the interconnect layer, a first conductive element over a second side of the polymer layer, wherein the second... Agent: Freescale Semiconductor, Inc. Law Department

20090057851 - Method of manufacturing semiconductor device: Provided is a method of manufacturing a semiconductor device including: arranging multiple dies planarly between a first lead frame plate and a second lead frame plate, which face each other, to connect the multiple semiconductor chips to each of the first lead frame plate and the second lead frame plate;... Agent: Young & Thompson

20090057850 - Surface mountable semiconductor package with solder bonding features: A packaged circuit element such as an LED and a method for making the same are disclosed. The packaged circuit element includes a lead frame, a molded body, and a die containing the circuit element. The lead frame has first and second leads, each lead having first and second portions.... Agent: Kathy Manke Avago Technologies Limited

20090057852 - Thermally enhanced thin semiconductor package: A semiconductor die package is disclosed. The semiconductor die package includes a semiconductor die comprising an input at a first top semiconductor die surface and an output at a second bottom semiconductor die surface. A leadframe having a first leadframe surface and a second leadframe surface opposite the first leadframe... Agent: Townsend And Townsend And Crew, LLP

20090057853 - Semiconductor power module with flexible circuit leadframe: A semiconductor power module includes a semiconductor chip thermally interfaced to a ceramic substrate and a leadframe defined by a flexible circuit disposed intermediate the chip and the ceramic substrate. The flexible circuit includes a conductor layer that is selectively encased in an insulated jacket to ensure adequate electrical insulation... Agent: Delphi Technologies, Inc.

20090057856 - Bonding-patterned device and electronic component: A bonding-patterned device comprises: a bonding layer provided on a bonding surface to be bonded to a mounting member. The bonding-patterned device has a planar shape which is generally a parallelogram. The bonding-patterned device is separated and cut out from a plate material along a plurality of evenly spaced straight... Agent: Amin, Turocy & Calvin, LLP

20090057857 - Lead frame, semiconductor device, and method of manufacturing semiconductor device: A lead frame according to one aspect of the present invention is used for a resin-sealed-type semiconductor device and includes a first lead frame having a frame body part and a lead part, and a second lead frame having a frame body part and a lead part. The lead part... Agent: Young & Thompson

20090057854 - Self locking and aligning clip structure for semiconductor die package: A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip aligner structure, where the clip aligner structure is... Agent: Townsend And Townsend And Crew, LLP

20090057855 - Semiconductor die package including stand off structures: A semiconductor die package. It includes a semiconductor die including a first surface and a second surface opposite the first surface, an optional conductive structure, and a leadframe structure. The leadframe structure comprises a central portion suitable for supporting the semiconductor die, and a plurality of stand-off structures coupled to... Agent: Townsend And Townsend And Crew, LLP

20090057858 - Low cost lead frame package and method for forming same: According to one exemplary embodiment, a lead frame package includes a number of leads and a number of contacts, where each of the contacts is situated over one of the leads. The lead frame package further includes a semiconductor die including a number of bond pads. Each of the contacts... Agent: Farjami & Farjami LLP

20090057860 - Semiconductor memory package: Disclosed is a semiconductor memory package having a thin-film decoupling capacitor that reduces radio frequency noise. The semiconductor memory package in accordance with an embodiment of the present invention includes a substrate, a memory chip being mounted on one side of the substrate and a decoupling capacitor formed in the... Agent: Staas & Halsey LLP

20090057859 - Window-type ball grid array package structure and fabricating method thereof: A window-type ball grid array (WBGA) package structure includes a substrate, fingers, traces, a solder mask, a die, a window mold compound and solder balls. The substrate has a first surface and a second surface and a window passing there-through. The fingers are on the first surface near the window,... Agent: Jianq Chyun Intellectual Property Office

20090057861 - Integrated circuit package-in-package system with side-by-side and offset stacking: An integrated circuit package-in-package system includes: mounting a first integrated circuit device over a substrate; mounting an integrated circuit package system having an inner encapsulation over the first integrated circuit device with a first offset; mounting a second integrated circuit device over the first integrated circuit device and adjacent to... Agent: Law Offices Of Mikio Ishimaru

20090057864 - Integrated circuit package system employing an offset stacked configuration: A method for manufacturing an integrated circuit package system includes: providing a base package including a first integrated circuit coupled to a base substrate by an electrical interconnect formed on one side; and mounting an offset package over the base package, the offset package electrically coupled to the base substrate... Agent: Law Offices Of Mikio Ishimaru

20090057862 - Integrated circuit package-in-package system with carrier interposer: An integrated circuit package-in-package system includes: mounting an integrated circuit device over a package carrier; forming a subassembly including: providing an integrated circuit package system having a carrier interposer with an integrated circuit die thereover, and mounting a device under the carrier interposer; mounting the subassembly over the integrated circuit... Agent: Law Offices Of Mikio Ishimaru

20090057863 - Integrated circuit package-on-package system with anti-mold flash feature: An integrated circuit package-on-package system includes: mounting an integrated circuit package system having a mountable substrate over a package substrate; forming a package encapsulation having both a recess and an anti-mold flash feature over the package substrate and the integrated circuit package system including: forming the anti-mold flash feature having... Agent: Law Offices Of Mikio Ishimaru

20090057865 - Sandwiched organic lga structure: An LGA structure is provided having at least one semiconductor device over a substrate and a mechanical load apparatus over the semiconductor device. The structure includes a load-distributing material between the mechanical load apparatus and the substrate. Specifically, the load-distributing material is proximate a first side of the semiconductor device... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090057867 - Integrated circuit package with passive component: The present invention comprises a substrate, an integrated circuit mounted on the substrate, a passive component such as a capacitor mounted on the integrated circuit, and an encapsulation enclosing the integrated circuit and the passive component. The integrated circuit can be mounted in a flip-chip configuration with its active side... Agent: Morgan, Lewis & Bockius LLP

20090057866 - Microelectronic package having second level interconnects including stud bumps and method of forming same: A microelectronic package and a method of forming the package. The microelectronic package includes a first level package including: a package substrate having a die side and a carrier side a microelectronic die mounted on the package substrate at the die side thereof; and an array of first level interconnects... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090057868 - Wafer level chip size package for mems devices and method for fabricating the same: The present invention provides a wafer level chip size package having cavities within which micro-machined parts are free to move, allowing access to electrical contacts, and optimized for device performance. Also a method for fabricating a wafer level chip size package for MEMS devices is disclosed. This packaging method provides... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20090057869 - Co-packaged high-side and low-side nmosfets for efficient dc-dc power conversion: A circuit package assembly is disclosed. The assembly includes a conductive substrate; a high-side n-channel metal oxide semiconductor field effect transistor (NMOSFET) having a source on a side facing a surface of the conductive substrate and in electrical contact therewith and a low-side standard n-channel metal oxide semiconductor field effect... Agent: Joshua D. Isenberg Jdi Patent

20090057870 - Stacked semiconductor package with a reduced volume: The stacked semiconductor package includes a substrate having a plurality of connection pads; a first semiconductor chip disposed over the substrate, a plurality of first bonding pads disposed at an first of the first semiconductor chip, redistributions extending from the first bonding pads to the middle of the upper face;... Agent: Ladas & Parry LLP

20090057871 - Ball grid array package enhanced with a thermal and electrical connector: Ball grid array (BGA) packages are provided. A BGA package includes a substrate that has a surface and a stiffener that has a surface and a protruding portion. The surface of the substrate has an opening therein. The protruding portion is located on the surface of the stiffener. The surface... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090057872 - Through-chip via interconnects for stacked integrated circuit structures: A stacked IC structure has an integrated circuit (IC) having a front IC side, a back IC side, and a first conductive feature formed on the front IC side. A through-chip via connects to the first conductive feature on the front IC side. A substrate has an external circuit formed... Agent: Agilent Technologies Inc.

20090057873 - Packaging substrate structure with electronic component embedded therein and method for manufacture of the same: A packaging substrate structure with an electronic component embedded therein and a fabricating method thereof are disclosed. The packaging substrate structure comprises a core plate; a first built-up structure disposed on a surface of the core plate and comprising a first dielectric layer and a first circuit layer disposed on... Agent: Bacon & Thomas, PLLC

20090057874 - Semiconductor module including semiconductor chips in a plastic housing in separate regions: The invention relates to a semiconductor module (9) comprising semiconductor chips (1, 2) in a plastic housing (3) in separate regions (4, 5), and to a method for producing the same. In this case, the semiconductor module (9) has adjacent regions (4, 5) on a common wiring substrate (7) in... Agent: Dicke, Billig & Czaja

20090057875 - Semiconductor device: A highly reliable semiconductor device which is not damaged by local pressing force from the outside and in which unevenness of a portion where an antenna and an element overlap with each other is reduced. The semiconductor device includes a chip and an antenna. The chip includes a semiconductor element... Agent: Eric Robinson

20090057876 - Stacked package structure for reducing package volume of an acoustic micro-sensor: A stacked package structure utilizes flip-chip technology to stack an acoustic micro-sensor on an integrated circuit (IC) device having a recess as a back chamber and cover the acoustic micro-sensor using a glass substrate or a planar substrate with an aperture. With the use of the stacked package structure, the... Agent: Wpat, PC

20090057877 - Semiconductor device with gel-type thermal interface material: Various methods and apparatus for establishing a thermal pathway for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes forming a metal layer on a semiconductor chip and forming a gel-type thermal interface material layer on the metal layer. A solvent and a... Agent: Timothy M Honeycutt Attorney At Law

20090057878 - Semiconductor die package including heat sinks: A semiconductor die package including at least two heat sinks. The semiconductor die package includes a first heat sink, a second heat sink coupled to the first heat sink, and a semiconductor die between the first heat sink and the second heat sink. The semiconductor die is electrically coupled to... Agent: Townsend And Townsend And Crew, LLP

20090057880 - Semiconductor device, semiconductor package, stacked module, card, system and method of manufacturing the semiconductor device: A semiconductor device capable of improving the efficiency of dispersing heat via a dummy pad. The semiconductor device may be included in a semiconductor package, stack module, card, or system. Also disclosed is a method of manufacturing the semiconductor device. In the semiconductor device, a semiconductor substrate has a first... Agent: Marger Johnson & Mccollom, P.C.

20090057879 - Structure and process for electrical interconnect and thermal management: A structure and method for thermal management of integrated circuits. The structure for thermal management of integrated circuits includes first and second substrates bonded together, at least one of the first and second substrates including at least one circuit element, an entrance through-hole having a length extending through a thickness... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090057882 - Fluid cooled semiconductor power module having double-sided cooling: A semiconductor power module includes one or more power semiconductor power devices sandwiched between a fluid conducting base and a fluid conducting cover joined to the base. Fluid coolant entering the base diverges into a first flow path through the base and a second parallel flow path through the cover,... Agent: Delphi Technologies, Inc.

20090057881 - Microelectronic package and method of cooling same: A microelectronic package comprises a chip stack (110) that includes a substrate (111), a first die (112) over the substrate and a second die (113) over the first die, a first underfill layer (114) between the substrate and the first die, and a second underfill layer (115) between the first... Agent: Intel Corporation C/o Intellevate, LLC

20090057883 - Method and structure of minimizing mold bleeding on a substrate surface of a semiconductor package: A method and structure of minimizing mold bleeding on a substrate surface of a semiconductor package is disclosed. In one embodiment, a method includes forming a dam structure on an outer area of a substrate surface of a semiconductor package and blocking a flow of a mold material from a... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090057884 - Multi-chip package: Various semiconductor chip packages and package lids are disclosed. In one aspect, a method of manufacturing is provided that includes forming a semiconductor chip package lid with a peripheral wall that defines a first interior space. A first bridge structure is formed in the first interior space. The first bridge... Agent: Timothy M Honeycutt Attorney At Law

20090057885 - Semiconductor device: A semiconductor device is disclosed. One embodiment provides a semiconductor chip having a main surface, wherein a first molding compound accommodates the semiconductor chip. The first molding compound has a surface that is substantially coplanar to the main surface of the semiconductor chip. A second molding compound is arranged in... Agent: Dicke, Billig & Czaja

20090057886 - Semiconductor device and substrate: A semiconductor device of the invention include a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element comprises, a plurality... Agent: Volentine & Whitt PLLC

20090057892 - Electrode structure in semiconductor device and related technology: A first insulation film having a first opening is provided on an electrode pad of a semiconductor chip. A second insulation film having a second opening is provided on the first insulation film. A ground metallic layer which is to be in contact with the electrode pad via the first... Agent: Mcdermott Will & Emery LLP

20090057888 - Ic package having ic-to-pcb interconnects on the top and bottom of the package substrate: An integrated circuit package, according to one embodiment, includes a package substrate, an interface stratum and an integrated circuit die. Both the IC die and interface stratum are disposed on the package substrate. The integrated circuit die includes a microelectronic circuit having a plurality of inputs and outputs. A first... Agent: Nvidia C/o Murabito, Hao & Barnes LLP

20090057895 - Post passivation structure for a semiconductor device and packaging process for same: A post passivation rerouting support structure comprises a relatively thin support layer above the passivation layer to support the RDL, and a relatively thick support layer for fine pitch interconnects extending from the RDL and terminating as contact structures at the surface of the thick support layer, for a next... Agent: Mou-shiung Lin

20090057893 - Semiconductor apparatus: In order to solve a problem of occurrence of delamination of interlayer film due to occurrence of a crack in an LSI wiring layer in a UBM lower layer immediately under a solder bump in an outer periphery of an LSI chip, a semiconductor apparatus of the present invention includes... Agent: Mcginn Intellectual Property Law Group, PLLC

20090057890 - Semiconductor device: In this semiconductor device, connection parts between wafers are electrically insulated from each other, and a junction face shape of second electrical signal connection parts is larger than the shape of a positioning margin face that is formed by an outer shape when the periphery of a minimum junction face,... Agent: Birch Stewart Kolasch & Birch

20090057891 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a supporting base whereupon an electrode terminal is placed; an intermediate member mounted on said supporting base; a semiconductor element, a portion thereof being supported with said intermediate member, and placed on said supporting base; and a convex-shaped member which corresponds to the electrode terminal of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090057889 - Semiconductor device having wafer level chip scale packaging substrate decoupling: One aspect of the invention provides a semiconductor device that includes a microchip having an outermost surface. First and second bond pads are located on the microchip and near the outermost surface. A first UBM contact is located on the outermost surface and between the first and second bond pads.... Agent: Texas Instruments Incorporated

20090057894 - Structure of gold bumps and gold conductors on one ic die and methods of manufacturing the structures: A method for fabricating multiple metal layers includes the following steps. An electronic component is provided with multiple contact points. A first metal layer is deposited over said electronic component. A first mask layer is deposited over said first metal layer. A second metal layer is deposited over said first... Agent: Mou-shiung Lin

20090057887 - Wafer level packaging of semiconductor chips: A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a larger pads near... Agent: Advanced Micro Devices, Inc. C/o Vedder Price P.C.

20090057897 - High strength solder joint formation method for wafer level packages and flip applications: A Micro SMDxt package is provided that configured for mounting to a circuit board. The SMDxt package includes a silicon-based IC having an array of contact pads on one side of thereof, and a die electrically attached to the silicon-based IC. A plurality of solder balls is included, each of... Agent: Beyer Law Group LLP

20090057896 - Nail-shaped pillar for wafer-level chip-scale packaging: A wafer-level chip-scale packaging feature for a semiconductor device is disclosed which has a substrate, a plurality of nail-shaped conducting posts extending from a surface of the substrate, and a plurality of solder balls, where each of the solder balls is connected to one of the nail-shaped conducting posts. When... Agent: Slater & Matsil, L.L.P.

20090057898 - Semiconductor device and method of manufacturing the same: An insulating layer having an opening from which an electrode pad of a device is exposed is formed on the surface of a semiconductor substrate having the device fabricated therein, and an external terminal pad defined by a portion of a conductor layer formed on the insulating layer is connected... Agent: Kratz, Quintos & Hanson, LLP

20090057899 - Semiconductor integrated circuit device and method of fabricating the same: A semiconductor integrated circuit device includes a semiconductor substrate including a main chip region and a pad region, a multi-layer pad structure on the pad region of the semiconductor substrate, a redistribution pad through the semiconductor substrate and in contact with a bottom surface of the multi-layer pad structure, the... Agent: Lee & Morse, P.C.

20090057900 - Stacked chip package with redistribution lines: A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad,... Agent: Mou-shiung Lin

20090057901 - Structure of high performance combo chip and processing method: A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the... Agent: Megica Corporation

20090057902 - Method and structure for increased wire bond density in packages for semiconductor chips: A semiconductor package provides an IC chip on at least one package substrate and including signal bond pads, ground bond pads and power bond pads. The package substrate includes signal contact pads, ground contact pads and power contact pads which are respectively coupled to signal bond pads, ground bond pads... Agent: Duane Morris LLP (tsmc)IPDepartment

20090057903 - Semiconductor module, method for manufacturing semiconductor modules, semiconductor apparatus, method for manufacturing semiconductor apparatuses, and portable device: Cost is suppressed and a semiconductor module is made thinner. The semiconductor is of a structure where a semiconductor element is embedded in a recess formed in a wiring substrate. A substrate electrode provided around the recess and an element electrode are electrically connected through a wiring formed integrally with... Agent: Mcdermott Will & Emery LLP

20090057904 - Copper metal line in semicondcutor device and method of forming same: A Cu line in a semiconductor device and method of forming same are disclosed. The method may include forming an insulating interlayer on a semiconductor substrate, forming a contact hole and a trench in the insulating interlayer in sequence, forming a short-circuit preventing layer on the insulating interlayer including the... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090057905 - Semiconductor device and method of manufacturing the same: A metal interconnection layout for a semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device can maintain a minimum design rule and secure a distance between via holes to inhibit a metal bridge phenomenon from being generated. The semiconductor device comprises a substrate, an... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090057906 - Encapsulated silicidation for improved sic processing and device yield: A method for producing a silicide contact. The method comprises the steps of depositing a metal on a SiC substrate; forming an encapsulating layer on deposited metal; and annealing said deposited metal to form a suicide contact. The encapsulating layer prevents agglomeration and formation of stringers during the annealing process.... Agent: Andrews Kurth LLP

20090057907 - Interconnection structure: An interconnection structure includes an inter-layer dielectric; a topmost copper metal layer inlaid into the inter-layer dielectric; an insulating layer disposed on the inter-layer dielectric and the topmost copper metal layer; a via opening in the insulating layer for exposing a top surface of the topmost copper metal layer, wherein... Agent: North America Intellectual Property Corporation

20090057908 - Wire bond pads: A wire bond pad and method of fabricating the wire bond pad. The method including: providing a substrate; forming an electrically conductive layer on a top surface of the substrate; patterning the conductive layer into a plurality of wire bond pads spaced apart; and forming a protective dielectric layer on... Agent: Schmeiser, Olsen & Watts

20090057909 - Under bump metallization structure having a seed layer for electroless nickel deposition: Structures and methods for fabrication of an under bump metallization (UBM) str