SEARCH:      Monitor Keywords |  Custom RSS

Active solid-state devices (e.g., transistors, solid-state diodes) February patent applications/inventions, industry category 02/09

20090050867 - Feature formed beneath an existing material during fabrication of a semiconductor device and electronic systems comprising the semiconductor device: A method for forming a first feature within a dielectric, metal, or semiconductor material and, optionally, under an existing second feature, comprises the use of an anisotropic etch, the formation of a spacer used to prevent lateral etching, a subsequent isotropic etch to form a hollow opening, and the formation... Agent: Michael E. Romani Micron Technology, Inc.

20090050870 - Integrated circuit including memory element with spatially stable material: An integrated circuit includes a heater element serving as a first electrode, a second electrode, a memory element comprising resistance changing material coupled to the heater element and to the second electrode, and a diffusion compensation region coupled to the heater element and to the resistance changing material. The diffusion... Agent: Edell, Shapiro & Finnan, LLC

20090050868 - Nonvolatile memory element: Provided is a material composition which allows a nonvolatile memory element made of a perovskite-type transition metal oxide having the CER effect to be formed of three elements, which comprises an electric conductor having a shallow work function or a small electronegativity, such as Ti, as an electrode and a... Agent: Nixon & Vanderhye, PC

20090050869 - Phase-change random access memory and method of manufacturing the same: Provided is a phase-change random access memory (PRAM). The PRAM includes a bottom electrode, a bottom electrode contact layer, which is formed on one area of the bottom electrode, and an insulating layer, which is formed on a side of the bottom electrode contact layer, a phase-change layer, which is... Agent: Harness, Dickey & Pierce, P.L.C

20090050871 - Semiconductor device and process for producing the same: A semiconductor device having a phase-change memory cell comprises an interlayer dielectric film formed of, for example, SiOF formed on a select transistor formed on a main surface of a semiconductor substrate, a chalcogenide material layer formed of, for example, GeSbTe extending on the interlayer dielectric film, and a top... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090050872 - Process for manufacturing a copper compatible chalcogenide phase change memory element and corresponding phase change memory element: A copper-diffusion plug 21 is provided within a pore in dielectric layer over a copper signal line. By positioning the plug below a chalcogenide region, the plug is effective to block copper diffusion upwardly into the pore and into the chalcogenide region and thus to avoid adversely affecting the electrical... Agent: Seed Intellectual Property Law Group PLLC

20090050873 - System including memory with resistivity changing material and method of making the same: A method of manufacturing a memory cell includes: forming a first electrode, depositing a first insulator material over the first electrode, forming a via in the first insulator material, depositing a resistivity changing material in the via without completely filling the via, and forming a second electrode contacting the resistivity... Agent: Edell, Shapiro & Finnan, LLC

20090050874 - Nitride semiconductor light emitting device: A nitride semiconductor light emitting device includes n-type and p-type nitride semiconductor layers, an active layer disposed between the n-type and p-type nitride semiconductor layers and having a structure in which a plurality of quantum barrier layers and one or more quantum well layers are alternately stacked, and an electron... Agent: Staas & Halsey LLP

20090050875 - Nitride semiconductor light emitting device: A nitride semiconductor light emitting device includes n-type and p-type nitride semiconductor layers, and an active layer disposed between the n-type and p-type nitride semiconductor layers and having a stack structure in which a plurality of quantum barrier layers and one or more quantum well layers are alternately stacked. A... Agent: Staas & Halsey LLP

20090050876 - Transparent nanowire transistors and methods for fabricating same: Disclosed are fully transparent nanowire transistors having high field-effect mobilities. The fully transparent nanowire transistors disclosed herein include one or more nanowires, a gate dielectric prepared from a transparent inorganic or organic material, and transparent source, drain, and gate contacts fabricated on a transparent substrate. The fully transparent nanowire transistors... Agent: Reinhart Boerner Van Deuren S.c. Attn: Linda Kasulke, Docket Coordinator

20090050877 - Semiconductor memory device: A semiconductor memory device includes a semiconductor substrate, a semiconductor layer, a source/drain layer, first and second insulating films, and first and second gate electrodes. The semiconductor layer of one conductivity type is formed on a principal surface of the semiconductor substrate. The source/drain layer is formed on the principal... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090050880 - Method of fabricating thin-film transistor: The core metal of a protein such as ferritin is used as a nucleus for crystallizing a silicone thin film and then the thus crystallized film is employed in the channel part of a thin-film transistor. By aligning the protein on the surface of amorphous silicone and heating, the crystallinity... Agent: Posz Law Group, PLC

20090050883 - Method of manufacturing organic electroluminescent device and organic electroluminescent device: An organic electroluminescent device, which, on a substrate, has a plurality of first electrodes, and a second electrode opposing the plurality of first electrodes. The organic electroluminescent device also including a light-emitting functional layer between the second electrode and one of the first electrodes and a buffering layer that covers... Agent: Oliff & Berridge, PLC

20090050878 - Multifunction organic diode and matrix panel thereof: Disclosed is organic diode which is capable of light emitting display by an organic EL display, image sensing by a organic photodiode and power generation by an organic solar cell. Also disclosed is a matrix panel of such a multifunction organic diode. Specifically disclosed is a multifunction organic diode comprising... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090050882 - Organic thin film transistor: An organic thin film transistor including: a substrate; a gate electrode placed on the substrate; a gate insulating film placed on the gate electrode; a source electrode and a drain electrode which are placed on the gate insulating film; an organic semiconductor layer placed on the gate insulating film between... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20090050879 - Organic thin film transistor and active matrix display: An organic thin film transistor is disclosed. The organic thin film transistor includes a substrate, a gate electrode , a gate insulating film , a source electrode on the gate insulating film, a drain electrode on the gate insulating film at an interval with the source electrode, and an organic... Agent: Cooper & Dunham, LLP

20090050881 - Photoelectric conversion element, method for producing photoelectric conversion element, and solid-state imaging device: A photoelectric conversion element is provided and includes a photoelectric conversion portion. The photoelectric conversion portion includes: a pair of electrodes; and a photoelectric conversion layer between the pair of electrodes, and at least part of the photoelectric conversion layer includes a mixed layer of a p-type organic semiconductor and... Agent: Sughrue-265550

20090050884 - Thin film transistors using thin film semiconductor materials: The present invention generally comprises TFTs having semiconductor material comprising oxygen, nitrogen, and one or more element selected from the group consisting of zinc, tin, gallium, cadmium, and indium as the active channel. The semiconductor material may be used in bottom gate TFTs, top gate TFTs, and other types of... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090050887 - Chip on film (cof) package having test pad for testing electrical function of chip and method for manufacturing same: A chip on film (COF) package comprising a test pad for testing the electrical function of a semiconductor chip and a method for manufacturing same are provided. The COF package comprises a semiconductor chip mounted on a base film, a signal-input portion for receiving data and control signals and transmitting... Agent: F. Chau & Associates, LLC

20090050885 - Semiconductor wafers and methods of fabricating semiconductor devices: A semiconductor wafer includes a plurality of unitary semiconductor chips formed on a semiconductor substrate. Scribe lane region separate the unitary semiconductor chips from each other. Test element group (TEG) pads are configured to apply testing signals for testing respective test elements. A TEG pad is arranged such that an... Agent: Harness, Dickey & Pierce, P.L.C

20090050886 - Test device, sram test device, semiconductor integrated circuit device and methods of fabricating the same: A test device, SRAM test device, semiconductor integrated circuit, and methods of fabricating the same are provided. The test device may include a first test active region extending in one direction on a semiconductor substrate, a second test active, apart from the first test active region, extending in one direction... Agent: Harness, Dickey & Pierce, P.L.C

20090050888 - Semiconductor device and manufacturing method thereof: The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of... Agent: Eric Robinson

20090050890 - Contact structure: There is disclosed a contact structure for electrically connecting conducting lines formed on a first substrate of an electrooptical device such as a liquid crystal display with conducting lines formed on a second substrate via conducting spacers while assuring a uniform cell gap among different cells if the interlayer dielectric... Agent: Eric Robinson

20090050889 - Repairable capacitor for liquid crystal display: A thin film transistor array substrate, which can repair a current-leakage defect of a storage capacitor, is disclosed. The thin film transistor array substrate of the present invention comprises: a substrate, a plurality of data lines, and a plurality of scan lines, wherein the data lines and the scan lines... Agent: Bacon & Thomas, PLLC

20090050891 - Photodiode and display device: Disclosed is a photodiode having a silicon film (5) formed of a continuous grain silicon, where the silicon film (5) has a p-type semiconductor region (2), an intrinsic semiconductor region (3) and an n-type semiconductor region (4), which are arranged in this order along the surface of the silicon film... Agent: Nixon & Vanderhye, PC

20090050892 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and method for fabricating same are provided. The CMOS image sensor can include a gate electrode formed on an active area of a first conductive type semiconductor substrate, on which a photodiode area and a transistor area are defined; a low-density second conductive type diffusion region... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090050896 - Display device: The present invention provides a display device which forms a drive circuit using a bottom-gate-type TFT made of poly-Si which generates a small leak current in a periphery of a display region. A gate electrode is made of Mo having a high melting point, and a gate insulation film is... Agent: Stanley P. Fisher Reed Smith LLP

20090050895 - Semiconductor manufacturing method, semiconductor manufacturing apparatus, and display unit: In a semiconductor manufacturing method that manufactures a coplanar type thin film transistor, a microcrystalline film 10 that will become a channel region is formed on a glass substrate S, a sacrificial silicon oxide 20 film is formed on the microcrystalline film 10, and, in a state in which a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090050893 - Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same: A thin film transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate and crystallized using a metal catalyst, a gate insulating layer disposed on the semiconductor layer, a gate electrode disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate electrode, and source... Agent: Stein, Mcewen & Bui, LLP

20090050894 - Thin film transistor, method of fabricating the same, organic light emitting diode display device haing the tft, and method of fabricating the oled display device: A thin film transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate and including a channel region and source and drain regions, a gate electrode disposed in a position corresponding to the channel region of the semiconductor layer, a gate insulating layer interposed between the gate electrode... Agent: Stein, Mcewen & Bui, LLP

20090050900 - Field-effect transistor: At least two drain ohmic contacts are arranged to intersect with an active area. A source ohmic contact is arranged between the drain ohmic contacts. A drain coupling portion on an element separating area couples ends of the drain ohmic contacts on the same side thereof. A gate power supply... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090050901 - Glass-ceramic-based semiconductor-on-insulator structures and method for making the same: The present invention relates to a semiconductor-on-insulator structure including a semiconductor component comprised of substantially single-crystal semiconductor material layer and a single-crystal semiconductor material with an enhanced oxygen content layer; an oxide glass material layer; and a glass-ceramic layer.... Agent: Gibson & Dernier L.L.P.

20090050899 - High-output diamond semiconductor element: The present invention relates to a high-output diamond semiconductor element, including a Schottky electrode as a cathode, a diamond P− drift layer, a diamond p+ ohmic layer, an ohmic electrode as an anode, and an insulating film layer disposed to surround a circumference of the Schottky electrode. It also relates... Agent: Morgan Lewis & Bockius LLP

20090050902 - Semiconductor device having silicon carbide and conductive pathway interface: The present invention provides semiconductor device formed by an in situ plasma reducing process to reduce oxides or other contaminants, using a compound of nitrogen and hydrogen, typically ammonia, at relatively low temperatures prior to depositing a subsequent layer thereon. The adhesion characteristics of the layers are improved and oxygen... Agent: Patent Counsel, Ms/2061 Legal Affairs Dept.,

20090050898 - Silicon carbide semiconductor device and method for producing the same: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating... Agent: Mcdermott Will & Emery LLP

20090050897 - Substrate, method of polishing the same, and polishing apparatus: A polishing method and a polishing apparatus capable of polishing a surface of a substrate made of SiC or diamond extremely smoothly and efficiently without causing subsurface damage are provided. A polishing platen 1 can rotate around a rotating shaft 4, and is made of quartz having high transparency to... Agent: Oliff & Berridge, PLC

20090050904 - Light emitting diode circuit: A light emitting diode circuit includes a chip and a light emitting diode. The chip includes a current control unit that is used for controlling a driving current flowing through a path. The light emitting diode is positioned outside of the chip and is coupled to the path. The light... Agent: North America Intellectual Property Corporation

20090050903 - Selective wet etching of gold-tin based solder: The present invention is directed to post-deposition, wet etch processes for patterning AuSn solder material and devices fabricated using such processes. The processes can be applied to uniform AuSn layers to generate submicron patterning of thin AuSn layers having a wide variety of features. The use of multiple etching steps... Agent: Koppel, Patrick & Heybl

20090050905 - Highly efficient light-emitting diode: A high extraction efficiency light-emitting diode (LED) capable of producing a light beam of selected cross-section and selected spatial distribution of light in terms of intensity and angle is disclosed. The LED utilizes micro and/or nano optical elements in order to extract more light at one or more specified cone... Agent: Michael K. Lindsey Gavrilovich, Dodd & Lindsey, LLP

20090050906 - Photo detector and a display panel having the same: A photo detector has a sensing TFT (thin film transistor) and a photodiode. The sensing TFT has a gate and a base. The photodiode has an intrinsic semiconductor region electrically connected to the gate and the base of the sensing TFT. The sensing TFT and the photodiode both have a... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090050909 - Light-emitting diode apparatus and manufacturing method thereof: A light-emitting diode (LED) apparatus includes an epitaxial layer and an etching mask layer. The epitaxial layer has a first semiconductor layer, an active layer and a second semiconductor layer in sequence. The etching mask layer is disposed on the epitaxial layer and has a plurality of hollows. The second... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090050907 - Solid state lighting component: An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in... Agent: Koppel, Patrick & Heybl

20090050908 - Solid state lighting component: An LED component according to the present invention comprising an array of LED chips mounted on a submount with the LED chips capable of emitting light in response to an electrical signal. The array can comprise LED chips emitting at two colors of light wherein the LED component emits light... Agent: Koppel, Patrick & Heybl

20090050910 - Flat panel based light emitting diode package structure: The present invention discloses a flat panel based light emitting diode (LED) package structure. The package structure comprises a substrate, a plurality of first LED chips, a plurality of second LED chips and a protective layer. The first LED chips and the second LED chips are located on the substrate,... Agent: Rosenberg, Klein & Lee

20090050911 - Light emitting device packages using light scattering particles of different size: A radiation emitting device comprising light scattering particles of different sizes that at least partially surround an emitter, improving the spatial color mixing and color uniformity of the device. Multiple sizes of light scattering particles are dispersed in a medium to at least partially surround a single- or multiple-chip polychromatic... Agent: Koppel, Patrick & Heybl

20090050912 - Light emitting diode and outdoor illumination device having the same: A light emitting diode includes a first electrode, a second electrode, at least a first LED chip, at least a second LED chip, and an encapsulant. The second electrode has an opposite polarity with the first electrode and parallel with the first electrode. The first LED chip is electrically connected... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang

20090050915 - Group iii-v nitride semiconductor substrate and method for producing same: A group III-V nitride semiconductor substrate includes a first region of group III-V nitride semiconductor crystal grown on a facet on a heterosubstrate, and a second region of the group III-V nitride semiconductor crystal grown on a plane with a predetermined plane orientation on the heterosubstrate. The first region has... Agent: Mcginn Intellectual Property Law Group, PLLC

20090050914 - Semiconductor light-emitting device with selectively formed buffer layer on substrate: The invention discloses a semiconductor light-emitting device and a method of fabricating the same. The semiconductor light-emitting device according to the invention includes a substrate, a buffer layer, a multi-layer structure, and an ohmic electrode structure. The buffer layer is selectively formed on an upper surface of the substrate such... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090050919 - Light emitting diode module: The present invention relates to a light emitting diode (LED) module (10), comprising at least one LED chip (12) having a surface (13) for emitting light, and a ceramic conversion plate (14). The LED module is characterized in that the ceramic conversion plate includes a first segment (18) covering a... Agent: Philips Intellectual Property & Standards

20090050918 - Phosphor, its preparation method and light emitting devices using the same: A phosphor can be excited by UV, purple or blue light LED, its preparation method, and light emitting devices incorporating the same. The phosphor contains rare earth, silicon, alkaline-earth metal, halogen, and oxygen, as well as aluminum or gallium. Its General formula of is aLn2O3.MO.bM′2O3.fSiO2.cAXe: dR, wherein Ln is at... Agent: Staas & Halsey LLP

20090050917 - Semiconductor light emitting device: A semiconductor light emitting device includes a substrate, and a light emitting portion that is disposed on the substrate, and includes an active layer formed of a group III nitride semiconductor using a nonpolar plane or a semipolar plane as a growth principal surface, in which side end surfaces of... Agent: Rabin & Berdo, PC

20090050916 - Semiconductor light emitting device and semiconductor light emitting apparatus: A semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer, a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, a first electrode provided on the first semiconductor layer, a second electrode including a first metal film provided on the second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090050920 - Ceramic wiring board and process for producing the same, and semiconductor device using the same: A ceramic wiring board 10 includes a ceramic substrate 11 and a wiring layer 12 formed on the ceramic substrate 11. The wiring layer 12 includes a wiring part 13 and a connection part 14, the wiring part 13 having a base metal layer 15, a first diffusion preventive layer... Agent: Foley And Lardner LLP Suite 500

20090050924 - Droop-free high output light emitting devices and methods of fabricating and operating same: Light emitting devices include a semiconductor light emitting diode that is configured to operate at a substantially droop-free quantum efficiency while producing warm white light output of at least about 100 lumens/cool white light output of at least about 130 lumens. The semiconductor light emitting diode may include a single... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090050922 - Front and rear covering type led package structure and method for packaging the same: A front and rear covering type LED package structure includes an insulating body, a substrate unit, at least one light-emitting element, and a package colloid. The insulating body has a receiving space. The substrate unit has two electrode pins separated from each other. Each electrode pin has one side covered... Agent: Rosenberg, Klein & Lee

20090050921 - Light emitting diode array: A one-dimensional array of light emitting diodes (LEDs) is configured to place the LEDs in close proximity to each other, e.g., 150 μm or less and to place at least one side of the LEDs in close proximity to the edge of the substrate, e.g., 150 μm or less. With... Agent: Patent Law Group LLP

20090050923 - Light emitting diode package: Provided is an LED package including a printed circuit board (PCB); a conductive structure that is formed on the PCB and is composed of any one selected from a silicon structure and an aluminum structure; and an LED chip that is mounted on the PCB and is electrically connected to... Agent: Mcdermott Will & Emery LLP

20090050913 - Method for achieving low defect density algan single crystal boules: A method for growing bulk GaN and AlGaN single crystal boules, preferably using a modified HVPE process, is provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If desired, the bulk material can be doped during... Agent: Empk & Shiloh, LLP C/o Landon Ip, Inc.

20090050926 - Light emitting device: A light emitting device includes a light emitting element, an element mounting board including a wiring layer on an element mounting surface thereof, and a sealing portion that seals the light emitting element. The light emitting element includes a contact electrode including a transparent conductive film, a transparent dielectric layer... Agent: Mcginn Intellectual Property Law Group, PLLC

20090050925 - Resin molding, surface mounted light emitting apparatus and methods for manufacturing the same: The surface mounted light emitting apparatus comprises the light emitting device 10 based on GaN which emits blue light, the first resin molding 40 which integrally molds the first lead 20 whereon the light emitting device 10 is mounted and the second lead 30 which is electrically connected to the... Agent: Birch Stewart Kolasch & Birch

20090050930 - Light-emitting device and the manufacturing method thereof: This invention provides an optoelectronic semiconductor device having a rough surface and the manufacturing method thereof. The optoelectronic semiconductor device comprises a semiconductor stack having a rough surface and an electrode layer overlaying the semiconductor stack. The rough surface comprises a first region having a first topography and a second... Agent: Bacon & Thomas, PLLC

20090050927 - Method of fabrication ingaaln film and light-emitting device on a silicon substrate: There is provided a method of fabricating InGaAlN film on a silicon substrate, which comprises the following steps of forming a pattern structured having grooves and mesas on the silicon substrate, and depositing InGaAlN film on the surface of substrate, wherein the depth of the grooves is more than 6... Agent: Park, Vaughan & Fleming LLP

20090050929 - Semiconductor substrate with nitride-based buffer layer for epitaxy of semiconductor opto-electronic device and fabrication thereof: The invention discloses a semiconductor substrate for epitaxy of a semiconductor optoelectronic device and the fabrication thereof. The semiconductor substrate according to the invention includes a substrate, and a nitride-based buffer layer. The buffer layer is formed by an atomic layer deposition process and/or a plasma-enhanced (or a plasma-assisted) atomic... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090050928 - Zinc-blende nitride semiconductor free-standing substrate, method for fabricating same, and light-emitting device employing same: A zinc-blende nitride semiconductor free-standing substrate has a front surface and a back surface opposite the front surface. The distance between the front and back surfaces is not less than 200 μm. The area ratio of the zinc-blende nitride semiconductor to the front surface is not less than 95%.... Agent: Mcginn Intellectual Property Law Group, PLLC

20090050931 - Switching assembly for an aircraft ignition system: A switching assembly is disclosed for a high voltage aircraft ignition system. The switching assembly includes a ceramic substrate and switch die that includes an anode bonded to an electrical pad on the ceramic substrate. The switch die includes a semiconductor device having a plurality of interleaved gates and cathodes,... Agent: James D. Stevens Reising, Ethington, Barnes, Kisselle, P.C.

20090050932 - Semiconductor device and the method of manufacturing the same: To provide a semiconductor device that exhibits a high breakdown voltage, excellent thermal properties, a high latch-up withstanding capability and low on-resistance. The semiconductor device according to the invention, which includes a buried insulator region 5 disposed between an n−-type drift layer 3 and a first n-type region 7 above... Agent: Rossi, Kimms & Mcdowell LLP.

20090050934 - Microchannel avalanche photodiode (variants):

20090050933 - Semiconductor light-receiving device and method for manufacturing the same: Disclosed is a semiconductor light-receiving device having high reproducibility and reliability. Also disclosed is a method for manufacturing a semiconductor light-receiving device. Specifically disclosed is a semiconductor light-receiving device 100 with a mesa structure wherein a light-absorbing layer 6, an avalanche multiplication layer 4 and an electric-field relaxation layer 5... Agent: Sughrue Mion, PLLC

20090050935 - Silicon-germanium hydrides and methods for making and using same: The present invention provides silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the compounds. The compounds are defined by formula: SiHnI (GeHn2)y, wherein y is 2, 3, or 4 wherein n1 is 0 1, 2 or 3 to satisfy valency and wherein... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20090050936 - Nitride semiconductor device and power converter including the same: A nitride semiconductor device includes a RESURF layer containing p-type InxGa1−xN (0<x≦1); a channel layer, formed on this RESURF layer, containing InyGa1−yN (0≦y<x); a barrier layer including a nitride semiconductor layer, formed on this channel layer, having a wider energy gap than the channel layer; and a prescribed electrode.... Agent: Birch Stewart Kolasch & Birch

20090050937 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device of the present invention includes: a III-V nitride semiconductor layer including a channel region in which carriers travel; a concave portion provided in an upper portion of the channel region in the III-V nitride semiconductor layer; and a Schottky electrode consisting of a conductive material forming a... Agent: Mcdermott Will & Emery LLP

20090050938 - Mis gate structure type hemt device and method of fabricating mis gate structure type hemt device: A normally-off operation type HEMT device excellent in characteristics can be realized. A two-dimensional electron gas region is formed in a periphery of a hetero-junction interface of a base layer and a barrier layer, so that access resistance in an access portion, that is, between a drain and a gate... Agent: Burr & Brown

20090050939 - Iii-nitride device: A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body.... Agent: Ostrolenk Faber Gerb & Soffen

20090050940 - Semiconductor device: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad... Agent: Miles & Stockbridge PC

20090050941 - Semiconductor device: A semiconductor device including a plurality of field-effect transistors which are stacked with a planarization layer interposed therebetween over a substrate having an insulating surface, in which semiconductor layers in the plurality of field-effect transistors are separated from semiconductor substrates, and the semiconductor layers are bonded to an insulating layer... Agent: Eric Robinson

20090050942 - Self-aligned super stressed pfet: The embodiments of the invention comprise a self-aligned super stressed p-type field effect transistor (PFET). More specifically, a field effect transistor comprises a channel region comprising N-doped material and a gate above the channel region. The field effect transistor also includes a source region on a first side of the... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090050944 - Cmos image sensor and method of fabrication: A CMOS imaging device including a two pixel detection system for red, green, and blue light. One pixel detects red and blue light and another pixel detects green light. The detection of red and blue is based on wavelength and the device is structured such that in the red/blue pixel,... Agent: Dickstein Shapiro LLP

20090050943 - Imagers, apparatuses and systems utilizing pixels with improved optical resolution and methods of operating the same: A pixel array resolution is doubled by adding a plurality of second photodiodes, but only a single, common transfer control line. By controlling a combination of the single, common transfer control line and a transfer control line unique to controlling first transfer transistors in pixels in a row, first and... Agent: Dickstein Shapiro LLP

20090050945 - Solid-state image sensing device: A solid-state image sensing device has a pixel that includes a photodiode that generates an electrical charge according to an amount of incoming light, a floating diffusion portion, a charge transfer transistor that transfers the electrical charge to the floating diffusion portion from the photoelectric conversion portion, a reading circuit... Agent: Fitzpatrick Cella Harper & Scinto

20090050947 - Apparatus, system, and method providing backside illuminated imaging device: Method, apparatus, and/or system providing a backside illuminated imaging device. A non-planar metallic or otherwise reflective layer is provided in an image pixel cell at the frontside of the device substrate to capture radiation passing through the device substrate. The non-planar surface is formed to be capable of reflecting substantially... Agent: Thomas J. D'amico Dickstein Shapiro LLP

20090050946 - Camera module, array based thereon, and method for the production thereof: The invention relates to the development of economical camera modules having objectives contained therein with a minimal constructional length and excellent optical properties. It is made possible as a result that camera modules of this type can be used in mobile telephones or minicomputers, such as PDAs (personal digital assistant).... Agent: Barnes & Thornburg LLP

20090050949 - Semiconductor memory device and method of fabricating the same: The present invention is to provide a semiconductor memory device capable of providing excellent storage properties, scaling and high integration and a method of fabricating the same. A semiconductor memory device has a multiferroic film exhibiting ferroelectricity and ferromagnetism, a channel region on an interface of a semiconductor substrate below... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090050948 - Spin mos field effect transistor and tunneling magnetoresistive effect element using stack having heusler alloy: A spin MOS field effect transistor includes a source electrode and a drain electrode each having a structure obtained by stacking an impurity diffusion layer, a (001)-oriented MgO layer and a Heusler alloy. The impurity diffusion layer is formed in a surface region of a semiconductor layer. The (001)-oriented MgO... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090050950 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a first MOS type capacitor having a first insulating film and a first electrode that are formed on a semiconductor substrate, and a second MOS type capacitor having a second insulating film and a second electrode that are formed on the semiconductor substrate. The first electrode... Agent: Mcdermott Will & Emery LLP

20090050951 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes depositing first to third mask layers above a substrate, processing the third mask layer, processing the second mask layer, slimming the second mask layer in an L/S section and out of the L/S section,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090050952 - Flash memory device and fabrication method thereof: The present invention relates to a flash memory device and a fabrication method thereof. In an embodiment, a flash memory device includes a tunnel insulating film and a floating gate laminated over an active region of a semiconductor substrate, an isolation layer formed in a field region of the semiconductor... Agent: Lowe Hauptman Ham & Berner, LLP

20090050953 - Non-volatile memory device and method for manufacturing the same: A non-volatile memory device including a substrate, an insulating layer, a charge storage layer, a multi-layer tunneling dielectric structure and a gate is provided. The substrate has a channel region. The insulating layer is disposed on the channel region. The charge storage layer is disposed on the insulating layer. The... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090050954 - Non-volatile memory device including charge trap layer and method of manufacturing the same: Provided are a non-volatile memory device and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes a charge trap layer having a crystalline material. In the method, a tunneling insulating layer is formed on a substrate, and a crystalline charge trap layer is formed on the... Agent: Harness, Dickey & Pierce, P.L.C

20090050955 - Nonvolatile semiconductor device and method of manufacturing the same: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090050956 - Semiconductor memory device and method of manufacturing the same: In a memory cell including an nMIS for memory formed on the sides of an nMIS for select and an nMIS for select via dielectric films and a charge storage layer, the thickness of a gate dielectric under the gate longitudinal direction end of a select gate electrode is formed... Agent: Miles & Stockbridge PC

20090050957 - Semiconductor device and method of manufacturing the same: A semiconductor device 1 has a metallic base substrate 2 for heat-dissipating, a wiring board 3, a MOSFET 4 as a semiconductor element, externally leading terminals 5A, 5B, 5C, a casing 6 formed of a synthetic resin, a fixing resin 7, and a gel-like resin layer 8. On the metallic... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090050958 - Semiconductor device having a spacer layer doped with slower diffusing atoms than substrate: A semiconductor device includes a silicon substrate heavily-doped with phosphorous. A spacer layer is disposed over the substrate and is doped with dopant atoms having a diffusion coefficient in the spacer layer material that is less than the diffusion coefficient of phosphorous in silicon. An epitaxial layer is also disposed... Agent: Hiscock & Barclay, LLP

20090050959 - Method and structure for shielded gate trench fet: A shielded gate field effect transistor includes a trench extending into a semiconductor region. A shield electrode is in a lower portion of the trench, and is insulated from the semiconductor region by a shield dielectric. The shield dielectric comprises first and second dielectric layers, the first dielectric layer extending... Agent: Townsend And Townsend And Crew, LLP

20090050960 - Stacked trench metal-oxide-semiconductor field effect transistor device: Embodiments of the present invention are directed toward a trench metal-oxide-semiconductor field effect transistor (TMOSFET) device. The TMOSFET device includes a source-side-gate TMOSFET coupled to a drain-side-gate TMOSFET 1203. A switching node metal layer couples the drain of the source-side-gate TMOSFET to the source of the drain-side-gate TMOSFET so that... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20090050961 - Semiconductor device: A semiconductor device is disclosed which has a shorter turn-on time. The semiconductor device includes an epitaxial layer, two base regions embedded in a surface portion of the epitaxial layer, source regions respectively embedded in the base regions, a drain region including at least a portion of the epitaxial layer... Agent: Rabin & Berdo, PC

20090050962 - Mosfet with isolation structure for monolithic integration and fabrication method thereof: A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with... Agent: J C Patents, Inc.

20090050963 - Stressed mos device and methods for its fabrication: Stressed MOS devices and methods for their fabrication are provided. The stressed MOS device comprises a T-shaped gate electrode formed of a material having a first Young's modulus. The T-shaped gate electrode includes a first vertical portion and a second horizontal portion. The vertical portion overlies a channel region in... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20090050964 - Method for manufacturing thin film integrated circuit, and element substrate: Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. A... Agent: Eric Robinson

20090050965 - Semiconductor device and method of fabricating the same: A semiconductor device according to an embodiment includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate via a gate insulating film; a channel region formed in a region of the semiconductor substrate below the gate electrode; an epitaxial crystal layer containing a conductive impurity, which is formed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090050966 - Semiconductor device: In order to suppress an off leak current of an off transistor for ESD protection, in an NMOS for ESD protection whose isolation region has a shallow trench structure, a drain region is placed apart from the shallow trench isolation region so as not to be in direct contact with... Agent: Brinks Hofer Gilson & Lione

20090050967 - Semiconductor device: In a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection surrounded by a shallow trench for device isolation, in order to suppress the off-leak current in an off state, there is formed, in the vicinity of the drain region of the NMOS transistor for ESD... Agent: Brinks Hofer Gilson & Lione

20090050968 - Semiconductor device: Provided is a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection including drain regions connected with a first metal interconnect and source regions connected with another first metal interconnect alternately placed with each other, and gate electrodes each placed between each of the drain regions... Agent: Brinks Hofer Gilson & Lione

20090050969 - Semiconductor device: Provided is a semiconductor device including an electrostatic discharge (ESD) protection element provided between an external connection terminal and an internal circuit region. In the semiconductor device, interconnect extending from the external connection terminal to the ESD protection element includes a plurality of metal interconnect layers so that a resistance... Agent: Brinks Hofer Gilson & Lione

20090050970 - Diode-based esd concept for demos protection: The invention relates to an ESD protection circuit for an integrated circuit including a drain-extended MOS device and an output pad that requires protection. The ESD protection circuit includes a first diode coupled to the output pad and to a bias voltage rail, a second diode coupled to the output... Agent: Slater & Matsil LLP

20090050971 - High voltage durability transistor and method for fabricating same: According to one exemplary embodiment, a method for fabricating a high voltage durability transistor comprises forming a gate over a gate oxide layer formed over a substrate, aligning an exposure mask with the gate, and selectively blocking exposure of the gate during gate implant doping, by exposure shields formed in... Agent: Farjami & Farjami LLP

20090050973 - Integrated circuit including a first channel and a second channel: An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first area and a second area. The first area is stress engineered to provide enhanced mobility in a first channel that has a first width. The second area is stress engineered to provide enhanced mobility in a... Agent: Dicke, Billig & Czaja

20090050974 - Method, system and apparatus for gating configurations and improved contacts in nanowire-based electronic devices: Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and... Agent: Nanosys Inc.

20090050972 - Strained semiconductor device and method of making same: A method of making a semiconductor device is disclosed. A semiconductor body, a gate electrode and source/drain regions are provided. A liner is provided that covers the gate electrode and the source/drain regions. Silicide regions are formed on the semiconductor device by etching a contact hole through the liner.... Agent: Slater & Matsil LLP

20090050975 - Active silicon interconnect in merged finfet process: Dummy fins are positioned between source and drain regions of adjacent complementary multi-gate fin-type field effect transistors (MUGFETS) prior to selective silicon growth and silicidation. The dummy fins are parallel to, have the same thickness as, and have a smaller length than the fins within the MUGFETs. Further, the source... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090050976 - Process method to fully salicide (fusi) both n-poly and p-poly on a cmos flow: An improved method of forming a fully silicided (FUSI) gate in both NMOS and PMOS transistors of the same MOS device is disclosed. In one example, the method comprises forming a first silicide in at least a top portion of a gate electrode of the PMOS devices and not over... Agent: Texas Instruments Incorporated

20090050977 - Method to reduce boron penetration in a sige bipolar device: The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor... Agent: Hitt Gaines, PC Lsi Corporation

20090050978 - Semiconductor device: A disclosed semiconductor device includes a driver transistor including a source and a drain of a second conductive type provided with an interval therebetween in a semiconductor substrate of a first conductive type, a gate electrode extending in a predetermined direction and provided on the semiconductor substrate via a gate... Agent: Cooper & Dunham, LLP

20090050979 - Semiconductor device and manufacturing method thereof: A semiconductor device having a semiconductor substrate, a first impurity region including a first conductive impurity formed in the semiconductor substrate, a first transistor and a second transistor formed in the first impurity region, a first stress film and a second stress having a first stress over the first transistor... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090050980 - Method of forming a semiconductor device with source/drain nitrogen implant, and related device: A method of forming a semiconductor device with source/drain nitrogen implant, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate, implanting a dopant species into an active region adjacent to the gate stack, and reducing a diffusivity of the... Agent: Texas Instruments Incorporated

20090050981 - Semiconductor device: A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated... Agent: Mcdermott Will & Emery LLP

20090050982 - Method for modulating the effective work function: A new MOSFET device is described comprising a metal gate electrode, a gate dielectric and an interfacial layer. The interfacial layer comprises a lanthanum hafnium oxide material for modulating the effective work function of the metal gate. The gate dielectric material in contact with the interfacial layer is different that... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20090050983 - Semiconductor device and method of producing the same: There is provided a trap memory device suppresses electric charges from flowing from the outside into a charge accumulation region and accumulated electric charges from diffusing to the outside or flowing out due to a defect. A gate conductor 6 is formed through a laminate insulating film including a first... Agent: Sughrue Mion, PLLC

20090050984 - Mos structures that exhibit lower contact resistance and methods for fabricating the same: MOS structures that exhibit lower contact resistance and methods for fabricating such MOS structures are provided. In one method, a semiconductor substrate is provided and a gate stack is fabricated on the semiconductor substrate. An impurity-doped region within the semiconductor substrate aligned with the gate stack is formed. Adjacent contact... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20090050985 - Semiconductor device with increased channel length and method for fabricating the same: A semiconductor device with an increased channel length and a method for fabricating the same are provided. The semiconductor device includes: a substrate with an active region including a planar active region and a prominence active region formed on the planar active region; a gate insulation layer formed over the... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090050987 - Fabrication of piezoelectric single crystalline thin layer on silicon wafer: The present invention relates a method of fabricating a piezoelectric device through micromachining piezoelectric-on-silicon wafer. The wafers are constructed so that piezoelectric layer is a single wafer having a thin layer from 5 to 50 μm.... Agent: Jue Peng

20090050986 - Method for fabricating sensor chip, and sensor chip: A method for fabricating a sensor chip having a substrate, a cover layer, a spacer layer interposed between the substrate and the cover layer, and a hollow reaction section provided in the spacer layer, the method comprising the steps of: affixing two or more adhesive or bonding tapes onto a... Agent: Mcdermott Will & Emery LLP

20090050988 - Mems apparatus and method of manufacturing the same: A MEMS apparatus includes a MEMS unit formed on a semiconductor substrate and a cover provided with a pore and serving to seal the MEMS unit. The pore is sealed with a sealing material shaped in a sphere or a hemisphere.... Agent: Amin, Turocy & Calvin, LLP

20090050989 - Semiconductor device: A semiconductor device of the present invention includes a semiconductor substrate, a semiconductor element formed in the semiconductor substrate, a surface layer formed on the semiconductor substrate, and a capacitance type sensor formed on the surface layer. The surface layer has a planar portion whose surface is planar. The capacitance... Agent: Rabin & Berdo, PC

20090050990 - Semiconductor sensor device and method for manufacturing same: Provided is a semiconductor sensor device which is manufactured by an MEMS technology wherein machining technology and/or material technology is combined with semiconductor technology for detecting and measuring various physical quantities. In the semiconductor sensor device, cracks which generate in a cap chip and a molding resin are eliminated and... Agent: Sughrue Mion, PLLC

20090050991 - Magnetic element having low saturation magnetization: A magnetic device including a magnetic element is described. The magnetic element includes a fixed layer having a fixed layer magnetization, a spacer layer that is nonmagnetic, and a free layer having a free layer magnetization. The free layer is changeable due to spin transfer when a write current above... Agent: Fish & Richardson, PC

20090050992 - Amorphous soft magnetic shielding and keeper for mram devices: An amorphous soft magnetic thin film material for forming shielding and keeper applications in MRAM devices. The amorphous soft magnetic material may be deposited using Physical Vapor Deposition (PVD) in the presence of a magnetic field, in order to form shielding layers and keepers in a multi-layer metallization process. The... Agent: Dla Piper LLP (us )

20090050994 - Method of manufacturing semiconductor device with electrode for external connection and semiconductor device obtained by means of said method: A circuit element is disposed on an organic substrate and is connected to a wiring pattern provided on the organic substrate. Internal connection electrodes are formed on a support of a conductive material through electrofomiing such that the internal connection electrodes are integrally connected to the support. First ends of... Agent: Mcglew & Tuttle, PC

20090050993 - Photoelectric conversion device and multi-chip image sensor: A pixel space is narrowed without increasing PN junction capacitance. A photoelectric conversion device includes a plurality of pixels arranged therein, each including a first impurity region of a first conductivity type forming a photoelectric conversion region, a second impurity region of a second conductivity type forming a signal acquisition... Agent: Fitzpatrick Cella Harper & Scinto

20090050996 - Electronic device wafer level scale packages and fabrication methods thereof: Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing... Agent: Birch Stewart Kolasch & Birch

20090050995 - Electronic device wafer level scale packges and fabrication methods thereof: Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A trench is formed by etching the semiconductor exposing an... Agent: Birch Stewart Kolasch & Birch

20090050997 - Solid-state image capturing device, manufacturing method for the solid-state image capturing device, and electronic information device: A solid-state image capturing device having a plurality of light receiving sections for performing photoelectrical conversion on and capturing image light from a subject is provided. In the light receiving sections, a low concentration opposite conductivity layer is provided either on a single conductivity substrate or a single conductivity layer,... Agent: Edwards Angell Palmer & Dodge LLP

20090050998 - Semiconductor device: In one embodiment of the present invention, a semiconductor device has a photodiode over a P-type substrate, an NPN transistor formed over the P-type substrate, an N−-type buried region provided right under the NPN transistor as being buried in the P-type substrate, and a P+-type buried region formed in the... Agent: Sughrue Mion, PLLC

20090050999 - Apparatus for storing electrical energy: An apparatus to store electrical energy is provided. The apparatus includes a first magnetic section, a second magnetic section, and a semiconductor section configured between the first magnetic section and the second magnetic section, wherein the junction between the semiconductor section and the first and second magnetic section forms a... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090051000 - Semiconductor device structure: A semiconductor device structure is provided. By placing an insulating dielectric material in the drift region of a device to modulate the electric field distribution and current flow in the drift region, the breakdown voltage of the device is increased while the turn-on impedance of the device is reduced.... Agent: Holland & Knight LLP

20090051001 - Isolated vertical power device structure with both n-doped and p-doped trenches: A method for manufacturing an isolated vertical power device includes forming, in a back surface of a first conductivity type substrate, back isolation wall trenches that surround a conduction region of the device. In a front surface of the substrate, front isolation wall trenches are formed around the conduction region.... Agent: Stmicroelectronics, Inc.

20090051002 - Electrical fuse having a thin fuselink: A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuselink is converted to a thin metal semiconductor alloy fuselink as all of... Agent: Scully, Scott, Murphy & Presser, P.C.

20090051003 - Methods and structures involving electrically programmable fuses: A method for fabricating an eFuse, the method comprising disposing a crystalline silicon eFuse on a substrate having a fuse link portion, a first contact portion, and a second contact portion, wherein the fuse link is oriented parallel to the silicon crystal {110} plane direction, etching the eFuse using crystallographic... Agent: Cantor Colburn LLP - IBM Fishkill

20090051005 - Method of fabricating inductor in semiconductor device: A method of fabricating an inductor in a semiconductor device is disclosed. Embodiments include forming a first metal wire in a trench formed by etching a layer of a semiconductor substrate, forming an insulating layer over the substrate including the first metal wire, forming a via hole by etching the... Agent: Sherr & Vaughn, PLLC

20090051004 - Surface mount components joined between a package substrate and a printed circuit board: A microelectronic package and a method of forming the package. The package includes a first level package mounted to a carrier. The first level package includes a package substrate having a die side and a carrier side; and a microelectronic die mounted on the package substrate at the die side... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090051006 - N cell height decoupling circuit: A decoupling circuit disposed between a first rail and a second rail, where a third power rail is disposed between the first and second rails. A resistor having a first electrode and a second electrode is disposed between the first and second rails. Two capacitors are disposed between the first... Agent: Lsi Corporation

20090051007 - Semiconductor device and method for fabricating the same: A semiconductor device is composed of: an interconnect made of a first conductive film and a second conductive film that are stacked in sequence from the interconnect underside on an insulating film formed on a substrate; and a capacitor composed of a lower capacitor electrode made of the first conductive... Agent: Mcdermott Will & Emery LLP

20090051008 - Semiconductor device having a resistor and methods of forming the same: In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate... Agent: Mills & Onello LLP

20090051009 - Semiconductor device, method of manufacturing the same and resistor: Formed on an insulator are an N− type semiconductor layer having a partial isolator formed on its surface and a P− type semiconductor layer having a partial isolator formed on its surface. Source/drain being P+ type semiconductor layers are provided on the semiconductor layer to form a PMOS transistor. Source/drain... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090051010 - Ic package sacrificial structures for crack propagation confinement: Systems and methods for preventing damage to a unit with preventive structures are presented. In an embodiment, a unit of a collection of units includes a functional area and a preventive structure configured to prevent cracks from propagating into the functional area.... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090051011 - Semiconductor device having seal ring structure and method of forming the same: A semiconductor device of the present invention includes a seal ring structure. The seal ring structure includes a first metal layer including a though hole, the through hole having a bottom portion filled with an insulating material, and a second metal layer formed on the first metal layer. The second... Agent: Mcginn Intellectual Property Law Group, PLLC

20090051012 - Through-hole interconnection structure for semiconductor wafer: A through-hole interconnection structure for a semiconductor wafer, in which: the each wafer includes at least a first wafer and a second wafer electrically connected to the first wafer; an electrical signal connecting section of the second wafer is provided to protrude from a bonding surface of the second wafer,... Agent: Birch Stewart Kolasch & Birch

20090051013 - Semiconductor wafer for semiconductor components and production method: A semiconductor wafer for semiconductor components and to a method for its production is disclosed. In one embodiment, the semiconductor wafer includes a front side with an adjoining near-surface active zone as basic material for semiconductor component structures. The rear side of the semiconductor wafer is adjoined by a getter... Agent: Dicke, Billig & Czaja

20090051014 - Method of fabricating semiconductor device having silicide layer and semiconductor device fabricated thereby: A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region... Agent: Lee & Morse, P.C.

20090051015 - Semiconductor device and printed circuit board: For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this... Agent: Fitzpatrick Cella Harper & Scinto

20090051016 - Electronic component with buffer layer: An electronic component includes a metal substrate, a semiconductor chip configured to be attached to the metal substrate, and a buffer layer positioned between the metal substrate and the semiconductor chip configured to mechanically decouple the semiconductor chip and the metal substrate. The buffer layer extends across less than an... Agent: Dicke, Billig & Czaja

20090051017 - Lead frame with non-conductive connective bar: An electronic component includes a lead frame, a semiconductor chip and an encapsulating body. The lead frame includes a heat spreader area, a plurality of conductive lead fingers, at least one non-conductive tie bar, and a metal joint. The metal joint connects the at least one non-conductive tie bar to... Agent: Edell , Shapiro & Finnan , LLC

20090051018 - Semiconductor component and method of manufacture: In various embodiments, semiconductor components and methods to manufacture these components are disclosed. In one embodiment, a method to manufacture a semiconductor component is disclosed. The semiconductor includes a heat sink and a semiconductor die that has a first terminal on a top surface of the semiconductor die, a second... Agent: Hvvi Semiconductors, Inc.

20090051020 - Method of manufacturing semiconductor device, and semiconductor device: forming a half number of the plurality of lead lines and the remaining half number of the plurality of lead lines so as to have a shape of line symmetry with respect to the second axis; and mounting the semiconductor chip on a front surface side of a package.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090051019 - Multi-chip module package: A multi-chip module package is provided, which includes a first chip mounted on via a first conductive adhesive and electrically connected to a first chip carrier, a second chip mounted on via a second conductive adhesive and electrically connected to a second chip carrier which is spaced apart from the... Agent: Berliner & Associates

20090051021 - Semiconductor chip stack-type package and method of fabricating the same: Embodiments of the inventive concept provide a semiconductor chip stack-type package. The package comprises a lead frame including a die paddle part and a lead part, a first semiconductor chip group and a second semiconductor chip group stacked sequentially and mounted on one surface of the die paddle part, a... Agent: Marger Johnson & Mccollom, P.C.

20090051022 - Lead frame structure: A lead frame structure includes a lead frame, a partial plated portion, a semiconductor element, a Pb-free solder and a mold resin. The partial plated portion is formed on a part of a surface of the lead frame. The partial plated portion is made of a noble metal. The semiconductor... Agent: Nixon & Vanderhye, PC

20090051024 - Semiconductor package structure: A semiconductor package structure relates to a chip-embedded semiconductor package electrically connected to a second semiconductor component. The semiconductor package structure comprises a first packaging substrate having a first surface, a second surface and at least a first cavity penetrating through the first surface and the second surface. The semiconductor... Agent: Schmeiser Olsen & Watts

20090051023 - Stack package and method of fabricating the same: Provided is a stack package comprising: a substrate comprising a cavity; a first semiconductor chip disposed in the cavity; and a second semiconductor chip stacked on the substrate and electrically connected to the substrate by a plurality of conductive external terminals such as conductive bumps. Since both a horizontal packaging... Agent: Marger Johnson & Mccollom, P.C.

20090051025 - Fan out type wafer level package structure and method of the same: To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover,... Agent: Kusner & Jaffe Highland Place Suite 310

20090051026 - Process for forming metal film and release layer on polymer: A process for forming a releasable metal film includes depositing a metal onto a polymeric sheet such that the metal layer provides a low adhesive interface and exhibits relatively low stress. A barrier layer is then deposited onto the surface of the low adhesion interface. A thin film of a... Agent: Cantor Colburn LLP-ibm Yorktown

20090051027 - Method of manufacture and identification of semiconductor chip marked for identification with internal marking indicia and protection thereof by non-black layer and device produced thereby: An electronic integrated circuit has a planar front surface and a planar backsurface. Internal marking indicia identification are marked upon an marking surface on the exterior surface of the chip. The internal identification indicia on the chip surface are protected against remarking by a non-black, colored, optically transmissive layer, so... Agent: Mou-shiung Lin Science-based Industrial Park

20090051028 - Electronic device and electronic apparatus: An electronic device includes a semiconductor device and a wiring substrate having a wiring pattern. The semiconductor device includes: a semiconductor chip having an electrode; a convex-shaped resin protrusion provided on a surface of the semiconductor chip, the surface having the electrode; and wiring having a plurality of electrical coupling... Agent: Harness, Dickey & Pierce, P.L.C

20090051029 - Flip-chip type semiconductor device: A flip-chip type semiconductor device includes a semiconductor substrate. A plurality of electrode terminals are provided and arranged on a top surface of the semiconductor substrate, a sealing resin layer is formed on the top surface of the semiconductor substrate such that the electrode terminals are completely covered with the... Agent: Young & Thompson

20090051031 - Package structure and manufacturing method thereof: A package structure and a manufacturing method thereof are provided. The package structure comprises a carrier, a chip, at least one wire, a molding compound, at least one first solder ball and at least one second solder ball. The carrier has a chip chamber passing through the first surface and... Agent: Bacon & Thomas, PLLC

20090051030 - Semiconductor package with pad parts electrically connected to bonding pads through re-distribution layers: The semiconductor package includes: a semiconductor chip module having multiple adjacently arranged or integrally formed semiconductor chips each with a bonding pad group and a connection member electrically connecting each of the bonding pads included in the first bonding pad group to the corresponding bonding pad in the second bonding... Agent: Ladas & Parry LLP

20090051032 - Patterned nanoscopic articles and methods of making the same: Nanowire articles and methods of making the same are disclosed. A conductive article includes a plurality of inter-contacting nanowire segments that define a plurality of conductive pathways along the article. The nanowire segments may be semiconducting nanowires, metallic nanowires, nanotubes, single walled carbon nanotubes, multi-walled carbon nanotubes, or nanowires entangled... Agent: Wilmerhale/boston

20090051033 - Reliability improvement of metal-interconnect structure by capping spacers: The present invention relates to a metal-interconnect structure for electrically connecting integrated-circuit elements in an integrated-circuit device. It solves several problems of operational reliability in damascene interconnect structures, due to corner effects and structural defects present at top edges of interconnect lines fabricated according to prior-art processing technologies. In alternative... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090051034 - Semiconductor device and method for the same: A method for forming a semiconductor device is provided. The method includes the following steps. A substrate having a first contact is provided. A layered structure is formed on the substrate. A recess is formed into the layered structure to expose at least a portion of the first contact. A... Agent: Reed Smith LLP

20090051035 - Semiconductor integrated circuit: The semiconductor integrated circuit includes: a first wiring layer including a plurality of first interconnects formed to run in a first direction; a second wiring layer formed above the first wiring layer, the second wiring layer including a plurality of second interconnects formed to run in a second direction vertical... Agent: Mcdermott Will & Emery LLP

20090051036 - Semiconductor package having buss-less substrate: A ball grid array device with an insulating substrate (110) having metal traces (106, for example copper, about 18 μm thick) with sidewalls (108) at right angles to the trace top. The traces are grouped in a first (120) and a second set (121). The first set traces have the... Agent: Texas Instruments Incorporated

20090051037 - Semiconductor device and method of manufacture thereof: A semiconductor device relating to the present invention has multiple gate electrodes arranged on a semiconductor substrate at a narrow spacing and an interlayer insulating film covering the gate electrodes. The interlayer insulating film consists of a hygroscopic insulating film filling gate electrode spacing with a thinner thickness on the... Agent: Mcdermott Will & Emery LLP

20090051038 - Semiconductor device including semiconductor constituent and manufacturing method thereof: A semiconductor device includes a semiconductor constituent having a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. An under-layer insulating film is provided under and around the semiconductor constituent. A plurality of under-layer wires are provided under the under-layer insulating film and electrically... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090051041 - Multilayer wiring substrate and method for manufacturing the same, and substrate for use in ic inspection device and method for manufacturing the same: A multilayer wiring substrate includes one or more resin dielectric layers (81), conductor layers (84), via conductors (91), and projecting portions (85). The one or more resin dielectric layers (81) individually having via holes (90) formed therein and extending through a first surface (82) and a second surface (83). The... Agent: Sughrue Mion, PLLC

20090051040 - Power layout of integrated circuits and designing method thereof: The invention discloses a technique for designing the power layout of an integrated circuit. The power layout design forms a power mesh and a power ring with a plurality of metal trunks with uniform line width. In particular, the power ring includes a plurality of metal rings, which are formed... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090051039 - Through-substrate via for semiconductor device: A semiconductor device including a substrate having a front surface and a back surface is provided. A plurality of interconnect layers are formed on the front surface and have a first surface opposite the front surface of the substrate. A tapered profile via extends from the first surface of the... Agent: Haynes And Boone, LLPIPSection

20090051042 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a semiconductor substrate that has an integrated circuit; a plurality of electrodes that is formed on the semiconductor substrate, the plurality of the electrodes being electrically coupled to the integrated circuit; a passivation film that is formed on the semiconductor substrate, the passivation film having an... Agent: Harness, Dickey & Pierce, P.L.C

20090051043 - Die stacking in multi-die stacks using die support mechanisms: Systems, methods, and devices that facilitate stacking dies in a multi-die stack using die support mechanisms (DSMs) are presented. DSMs are employed to place a smaller die and attached wires underneath a larger die. DSMs can be placed on each side of the smaller die where the larger die overhangs... Agent: Amin, Turocy & Calvin, LLP

20090051046 - Semiconductor device and manufacturing method for the same: A semiconductor substrate provided with an integrated circuit is polished by CMP or the like, and the semiconductor substrate is made into a thin film by forming an embrittlement layer in the semiconductor substrate and separating a part of the semiconductor substrate; thus, semiconductor chips such as IC chips and... Agent: Eric Robinson

20090051045 - Semiconductor package apparatus: A semiconductor package apparatus comprises: at least one semiconductor chip; and a circuit board on which the semiconductor chip is installed, wherein at least one conductive plane for improving power and/or ground characteristics is positioned on a side of the semiconductor chip. In this manner, fabrication cost for the semiconductor... Agent: Mills & Onello LLP

20090051044 - Wafer-level packaged structure and method for making the same: A wafer-level packaging method is shown below: providing an un-cut wafer having a front side and a back side. A plurality of cutting lines is formed on the front side of the wafer so as to define the positions of each chip module such as a wireless module. The next... Agent: Rosenberg, Klein & Lee

20090051048 - Package structure and manufacturing method thereof: A package structure and a manufacturing method thereof are provided. The package structure includes a carrier, a chip-bonding structure and a chip. The chip-bonding structure is formed on a first surface of the carrier. The chip-bonding structure includes a cavity, a dam, several via holes and several solder bumps. The... Agent: Bacon & Thomas, PLLC

20090051047 - Semiconductor apparatus and method of manufacturing the same: There is provided a semiconductor apparatus which includes a substrate, a semiconductor chip mounted above the substrate, a first resin filled between the substrate and the semiconductor chip, and a second resin formed on the substrate and extending from a side surface of the semiconductor chip toward an outer edge... Agent: Mcginn Intellectual Property Law Group, PLLC

20090051049 - Semiconductor device, substrate and semiconductor device manufacturing method: The semiconductor device can prevent damages on a semiconductor chip even when a soldering material is used for bonding the back surface of the semiconductor chip to the junction plane of a chip junction portion such as an island or a die pad. This semiconductor device includes a semiconductor chip... Agent: Rabin & Berdo, PC

20090051050 - corner i/o pad density: An integrated circuit die has a plurality of I/O cells disposed about its periphery, each I/O cell having an I/O bonding pad. A first group of I/O cells is disposed at the periphery of the die at locations away from corners of the die, each of the first group of... Agent: Lewis And Roca LLP

20090051051 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a first insulator film having a first opening, a first wiring layer extending from the first opening onto the first insulator film, a first semiconductor chip mounted on the first insulator film so as to be electrically coupled with the first wiring layer, and a resin... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090051052 - Semiconductor device: A semiconductor device includes a molding resin layer and a semiconductor element encapsulated with the molding resin layer. The molding resin layer has an opening. A surface of the semiconductor element is partially exposed outside the molding resin layer through the opening. A groove is located in the surface of... Agent: Posz Law Group, PLC

20090051053 - Epoxy resin composition and semiconductor apparatus: The object of the present invention is to provide an epoxy resin composition which is excellent in flash characteristics and thermal conductivity, and gives an area mounting type semiconductor apparatus having little warpage and excellent temperature cycle properties. According to the present invention, there is provided an epoxy resin composition... Agent: Smith, Gambrell & Russell, LLP

20090045385 - Integrated circuit including memory element with high speed low current phase change material: An integrated circuit includes a first electrode, a second electrode, and a memory element coupled to the first electrode and to the second electrode, the memory element includes fast-operation resistance changing material doped with dielectric material.... Agent: Dicke, Billig & Czaja

20090045386 - Phase-change memory element: A phase-change memory element. The phase-change memory element comprises a first electrode and a second electrode. A first phase change layer is electrically coupled to the first electrode. A second phase change layer is electrically coupled to the second electrode. A conductive bridge is formed between and electrically coupled to... Agent: Birch Stewart Kolasch & Birch

20090045390 - Multi-resistive state memory device with conductive oxide electrodes: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one... Agent: Unity Semiconductor Corporation

20090045388 - Phase change material structure and related method: A structure including a phase change material and a related method are disclosed. The structure may include a first electrode; a second electrode; a third electrode; a phase change material electrically connecting the first, second and third electrodes for passing a first current through two of the first, second and... Agent: Hoffman Warnick LLC

20090045389 - Phase change memory device and method for manufacturing the same: A phase change memory device and a method for manufacturing the same. The method includes the steps of defining bottom electrode contact holes by removing portions of an insulation layer, to expose bottom electrodes, on a semiconductor substrate on which the bottom electrodes and the insulation layer are sequentially formed;... Agent: Baker & Mckenzie LLP Patent Department

20090045387 - Resistively switching semiconductor memory: One embodiment provides a non-volatile semiconductor memory with CBRAM memory cells at which there exists, between the Ag-doped GeSe layer and the Ag top electrode, a chemically inert barrier layer improving the switching properties of the CBRAM memory cell. The active matrix material layer of the memory cell includes a... Agent: Dicke, Billig & Czaja

20090045391 - Switch device and method of fabricating the same: Provided is a switch device that can be reliably turned on or off using a nanostructure that includes a nanotube and/or a nanowire. The switch device includes a lower conductive film formed on a substrate, a first insulating film formed on the lower conductive film and having a first hole... Agent: Myers Bigel Sibley & Sajovec

20090045392 - Nitride semiconductor device: There is provided a nitride semiconductor device including an active layer of a superlattice structure. The nitride semiconductor device including: a p-type nitride semiconductor layer; an n-type nitride semiconductor layer; and an active layer disposed between the p-type and n-type nitride layers, the active layer comprising a plurality of quantum... Agent: Mcdermott Will & Emery LLP

20090045393 - Nitride semiconductor device and method for manufacturing the same: There are provided a nitride semiconductor device having a structure capable of improving crystallinity of grown nitride semiconductor, carrying out easily removing a substrate, and dividing into chips very easily, by using zinc oxide based compound having excellent processability as a substrate, and a method for manufacturing the same. In... Agent: Rabin & Berdo, PC

20090045394 - Semiconductor device and a method of manufacture thereof: A method of manufacturing a semiconductor device comprises depositing a semiconductor layer over a semiconductor surface having at least one first region with a first (average surface lattice) parameter value and at least one second region having a second parameter value different from the first. The semiconductor layer is deposited... Agent: Mark D. Saralino ( Sharp ) Renner, Otto, Boisselle & Sklar, LLP

20090045395 - Strained-layer superlattice focal plane array having a planar structure: An infrared focal plane array (FPA) is disclosed which utilizes a strained-layer superlattice (SLS) formed of alternating layers of InAs and InxGa1−xSb with 0≦x≦0.5 epitaxially grown on a GaSb substrate. The FPA avoids the use of a mesa structure to isolate each photodetector element and instead uses impurity-doped regions formed... Agent: Sandia Corporation

20090045396 - Composition for forming passivation layer and organic thin film transistor comprising the passivation layer: Disclosed herein is a composition including a perfluoropolyether derivative, a photosensitive polymer or a copolymer thereof, and a photocuring agent, a passivation layer, organic thin film transistor, and electronic device including the same, a method of forming the passivation layer and methods of fabricating the organic thin film transistor and... Agent: Harness, Dickey & Pierce, P.L.C

20090045397 - Field effect transistor using amorphous oxide film as channel layer, manufacturing method of field effect transistor using amorphous oxide film as channel layer, and manufacturing method of amorphous oxide film: An amorphous oxide containing hydrogen (or deuterium) is applied to a channel layer of a transistor. Accordingly, a thin film transistor having superior TFT properties can be realized, the superior TFT properties including a small hysteresis, normally OFF operation, a high ON/OFF ratio, a high saturated current, and the like.... Agent: Fitzpatrick Cella Harper & Scinto

20090045399 - Field effect transistor with gate insulation layer formed by using amorphous oxide film: A field effect transistor includes a channel layer 11, a source electrode 13, a drain electrode 14, a gate insulation layer 12 and a gate electrode 15 formed on a substrate 10. The channel layer is made of an amorphous oxide and that the gate insulation layer is made of... Agent: Fitzpatrick Cella Harper & Scinto

20090045398 - Manufacture method for zno based compound semiconductor crystal and zno based compound semiconductor substrate: A manufacture method that can manufacture ZnO based compound semiconductor crystal of good quality. A ZnO substrate is prepared to have a principal surface made of a plurality of terraces of (0001) planes arranged stepwise along an m-axis direction, the envelop of the principal surface being inclined relative to the... Agent: Masao Yoshimura, Chen Yoshimura, LLP

20090045400 - Method for monitoring fuse integrity in a semiconductor die and related structure: According to one exemplary embodiment, a method for monitoring structural integrity of at least one fuse in semiconductor wafer, which includes at least one electrical monitoring structure, includes forming a monitoring window in a dielectric layer overlying the at least one electrical monitoring structure, where the monitoring window and a... Agent: Farjami & Farjami LLP

20090045401 - Semiconductor device and manufacturing method thereof: The present invention relates to a semiconductor device including a thin film transistor comprising a microcrystalline semiconductor which forms a channel formation region and includes an acceptor impurity element, and to a manufacturing method thereof. A gate electrode, a gate insulating film formed over the gate electrode, a first semiconductor... Agent: Eric Robinson

20090045403 - Contact structure and semiconductor device: To improve the reliability of contact with an anisotropic conductive film in a semiconductor device such as a liquid crystal display panel, a terminal portion (182) of a connecting wiring (183) on an active matrix substrate is electrically connected to an FPC (191) by an anisotropic conductive film (195). The... Agent: Eric Robinson

20090045404 - Semiconductor device and display device: A semiconductor device can easily reduce a leak current which flows when a reversely-staggered-type TFT element in which an active layer is made of polycrystalline semiconductor is turned off. The semiconductor device includes a reversely-staggered-type TFT element in which a semiconductor layer, a source electrode and a drain electrode are... Agent: Stanley P. Fisher Reed Smith LLP

20090045402 - Tft array substrate and manufacturing method the same: A method of manufacturing TFT array substrate uses only four photolithography processes without any special photo-mask. Pixel electrodes and gate electrodes are made on an upper surface of a substrate in a first photolithography. After that, gate insulating layers, active regions, source and drain doped regions, source and drain electrodes... Agent: Cooper & Dunham, LLP

20090045405 - Thin film transistor array: A thin film transistor array includes a substrate, scan lines, data lines, thin film transistors, upper electrodes and pixel electrodes. The scan lines and the data lines are disposed on the substrate to define pixel areas on the substrate. The thin film transistors are disposed inside corresponding pixel areas and... Agent: Jianq Chyun Intellectual Property Office

20090045406 - Semiconductor device and display device: A semiconductor device which can realize a diode function is provided with a manufacturing process of a polysilicon thin film transistor and without adding a dedicated process. A semiconductor device is provided having a semiconductor layer comprising a low-concentration p-type polysilicon region formed over a substrate, the semiconductor device comprising... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090045408 - Display device: A display device includes a display panel which forms a plurality of sub pixels on a substrate thereof, and a drive circuit which is configured to drive the plurality of sub pixels, wherein the drive circuit has a thin film transistor formed on the substrate, and the thin film transistor... Agent: Stanley P. Fisher Reed Smith LLP

20090045409 - Display device: A display device including both an n-channel thin film transistor and a p-channel thin film transistor each having excellent electric characteristics and high reliability is demonstrated, and a method for manufacturing thereof is also provided. The display device includes an inverted-staggered p-channel thin film transistor and an inverted-staggered n-channel thin... Agent: Eric Robinson

20090045407 - Solid-state imaging device: Realized is a solid-state imaging device capable of achieving both a finer pixel size and high light receiving efficiency with an excellent image characteristic. A high concentration p-well layer (5) is partially formed in the interior of a semiconductor substrate (1) centering on a region under a STI (6), and... Agent: Mcdermott Will & Emery LLP

20090045410 - Gan substrate and semiconductor device prepared by using method and apparatus of polishing gan substrate: In a polishing method of a GaN substrate according to this invention, first, while supplying a polishing solution 27 containing abrasives 23 and a lubricant 25, onto a platen 101, the GaN substrate is polished using the platen 101 and the polishing solution 27 (first polishing step). Then the GaN... Agent: Mcdermott Will & Emery LLP

20090045411 - Forming embedded dielectric layers adjacent to sidewalls of shallow trench isolation regions: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate; an insulating region extending from substantially a top surface of the semiconductor substrate into the semiconductor substrate; an embedded dielectric spacer adjacent the insulating region, wherein a bottom of the embedded dielectric spacer adjoins the semiconductor substrate; and... Agent: Slater & Matsil, L.L.P.

20090045412 - Method for production of silicon carbide layer, gallium nitride semiconductor device and silicon substrate: A method for producing a silicon carbide layer on a surface of a silicon substrate includes the step of irradiating the surface of the silicon substrate heated in a high vacuum at a temperature in a range of from 500° C. to 1050° C. with a hydrocarbon-based gas as well... Agent: Sughrue Mion, PLLC

20090045413 - Silicon carbide bipolar semiconductor device: In a SiC bipolar semiconductor device with a mesa structure having a SiC drift layer of a first conductive type and a SiC carrier injection layer of a second conductive type that are SiC epitaxial layers grown from a surface of a SiC single crystal substrate, the formation of stacking... Agent: The Webb Law Firm, P.C.

20090045414 - Silicon carbide semiconductor element, method of manufacturing the same, and silicon carbide device: A silicon carbide semiconductor element and a manufacturing method thereof are disclosed in which a low contact resistance is attained between an electrode film and a wiring conductor element, and the wiring conductor element is hardly detached from the electrode film. In the method, a nickel film and a nickel... Agent: Rossi, Kimms & Mcdowell LLP.

20090045415 - Backside-illuminated imaging device: A backside-illuminated imaging device is provided and includes: a plurality of charge accumulating areas in the semiconductor substrate which accumulate the electric charges; and a plurality of filters above a backside surface of the semiconductor substrate corresponding to the respective charge accumulating areas. The plurality of filters includes different color... Agent: Birch Stewart Kolasch & Birch

20090045416 - Optical element coupled to low profile side emitting led: A low profile, side-emitting LED with one or more optical elements, such as a reflector or lens, optically coupled to each light emitting sidewall is described. In one embodiment, a reflector is used to redirect the light emitted from each sidewall to a forward direction, e.g., in a flash configuration.... Agent: Patent Law Group LLP

20090045417 - Light emitting semiconductor device: A light emitting semiconductor device is provided, wherein the light emitting semiconductor device comprises a substrate, a plurality of flip chips, a heat conductive board and an insulating board. These flip chips are electrically connected on the substrate. The heat conductive board has a protruding portion used to support the... Agent: Pai Patent & Trademark Law Firm

20090045418 - Light emitting diode (led) with longitudinal package structure: The present invention provides erected LED package structure, which includes: a carrier substrate having a first surface, a second surface and a plurality of through holes passed through the first surface and the second surface of the carrier substrate, and the conductive material filled with each of the through holes;... Agent: Reed Smith LLP Suite 1400

20090045419 - Semiconductor light-emitting device with high light-extraction efficiency and method for fabricating the same: The invention discloses a semiconductor light-emitting device and a method of fabricating the same. The semiconductor light-emitting device according to the invention includes a substrate, a first semiconductor material layer, a multi-layer structure and an ohmic electrode structure. The substrate has a first upper surface and a plurality of recesses... Agent: Birch Stewart Kolasch & Birch

20090045420 - Backlight including side-emitting semiconductor light emitting devices: Individual side-emitting LEDs are separately positioned in a waveguide, or mounted together on a flexible mount then positioned together in a waveguide. As a result, the gap between each LED and the waveguide can be small, which may improve coupling of light from the LED into the waveguide. Since the... Agent: Patent Law Group LLP

20090045422 - Member for semiconductor light emitting device and method for manufacturing such member, and semiconductor light emitting device using such member: To provide novel semiconductor light-emitting device member superior in transparency, light resistance, and heat resistance and capable of sealing semiconductor light-emitting device and holding phosphor without generating cracks or peelings even after use for a long time, the member meets the following requirements: (1) comprising functional group forming hydrogen bond... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090045427 - Photonic crystal light emitting device: A photonic crystal structure is formed in an n-type region of a III-nitride semiconductor structure including an active region sandwiched between an n-type region and a p-type region. A reflector is formed on a surface of the p-type region opposite the active region. In some embodiments, the growth substrate on... Agent: Patent Law Group LLP

20090045426 - Semiconductor chip and method for producing a semiconductor chip: A semiconductor chip (1) comprises a semiconductor body (2) having a semiconductor layer sequence having an active region (23) provided for generating radiation. A contact (4) is arranged on the semiconductor body (2). An injection barrier (5) is formed between the contact (4) and the active region (23). A method... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090045425 - Semiconductor light emitting device and method for manufacturing same: A semiconductor light emitting device includes: a support substrate; a metal layer provided on the support substrate; a semiconductor layer provided on the metal layer and including a light emitting layer; a contact layer containing a semiconductor, selectively provided between the semiconductor layer and the metal layer, and being in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090045423 - Semiconductor light-emitting device: wherein r, 1s and 1c are distances from the drooping portion of the reflector, from the outer circumference of the sub-mount and from the outer circumference of the semiconductor light-emitting element to the center of the semiconductor light-emitting element, respectively, hs and d are heights of the sub-mount and of... Agent: Sughrue Mion, PLLC

20090045424 - Silicone based circuit board indicator led lens: The present invention relates generally to a light transmitting device. In one embodiment, the light transmitting device includes a light emitting diode (LED) chip, a surface mounting device and a lens comprising a silicone based material, wherein a portion of the lens achieves a total internal reflection of a light... Agent: Patterson & Sheridan L.L.P. Nj Office

20090045421 - Surface mount type light emitting diode package device: The invention discloses a surface mount type light emitting diode (LED) package device, which has a cup-shaped structure and comprises a specific lens bulged out over the cup opening. The lens is an aspheric lens having a specific curved surface not fully symmetric with respect to its central point, while... Agent: North America Intellectual Property Corporation

20090045432 - Circuit board for light emitting device package and light emitting unit using the same: A circuit board for a light emitting device and a light emitting unit using the same, which are capable of achieving an enhancement in light emission efficiency and an enhancement in reliability, are disclosed. The disclosed circuit board includes a substrate having a first surface and a second surface, at... Agent: Mckenna Long & Aldridge LLP

20090045429 - Diode structure and memory device including the same: Provided are a diode structure and a memory device including the same. The diode structure includes: a first electrode; a p-type Cu oxide layer formed on the first electrode; an n-type InZn oxide layer formed on the p-type Cu oxide layer; and a second electrode formed on the n-type InZn... Agent: Harness, Dickey & Pierce, P.L.C

20090045430 - Light emitting element: A heat radiation structure of a light emitting element has leads, each lead having a plurality of leg sections, and a light emitting chip mounted on any one of the leads. The present invention can provide a high-efficiency light emitting element, in which a thermal load is reduced by widening... Agent: H.c. Park & Associates, PLC

20090045431 - Light emitting element: A light-emitting device includes an element structure including at least two semiconductor layers having mutually different conductivity types. A transparent p-side electrode of ITO is formed on the element structure. A bonding pad is formed on a region of the p-side electrode. An n-side electrode made of Ti/Au is formed... Agent: Mcdermott Will & Emery LLP

20090045428 - Polarless surface mounting light emitting diode: A polarless surface mounting light emitting diode comprises a substrate having; an upper surface of the substrate being etched with four independent metal thin film block; an lower surface of the substrate being formed with two independent metal thin film block; two ends of the substrate being formed with electroplating... Agent: Peter P. W. Lin

20090045434 - Gallium nitride-based compound semiconductor light-emitting device: A gallium nitride-based compound semiconductor light-emitting device including a positive electrode having openings, which is excellent in light extraction efficiency. The gallium nitride-based compound semiconductor light-emitting device includes a substrate; an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer, the layers being formed of a gallium nitride-based... Agent: Sughrue Mion, PLLC

20090045433 - Nitride semiconductor light emitting device and production method thereof: The present invention provides a nitride semiconductor light emitting device, which comprises positive and negative electrodes with high adhesion, can output high power, and does not generate heat; specifically, the present invention provides a nitride semiconductor light emitting device comprising at least an ohmic contact layer, a p-type nitride semiconductor... Agent: Sughrue Mion, PLLC

20090045435 - Stamp having nanoscale structure and applications therefore in light-emitting device: A stamp having a nanoscale structure and a manufacturing method thereof are disclosed. The stamp includes a substrate, a buffer layer, and a nanoscale stamp layer. The method comprises forming a buffer layer on the substrate, and forming a stamp layer having a nanoscale structure on the buffer layer.... Agent: Bacon & Thomas, PLLC

20090045436 - Localized trigger esd protection device: The present invention provides an ESD device to reduce the total triggering current without increasing the overshoot voltage. This is achieved by localizing the triggering current, such that the local current density remains high enough to trigger the ESD device. This localized triggering provides a fast and efficient triggering of... Agent: Patent Docket Administrator Lowenstein Sandler P.C.

20090045437 - Method and apparatus for forming a semi-insulating transition interface: The disclosure relates to a method for forming an intermediate lattice transition buffer layer. The method includes: (a) depositing a first graded InAlAs layer on a substrate at a first constant temperature, the first graded InAlAs layer having an In/AI composition ratio which increases across the buffer layer from a... Agent: Snell & Wilmer L.L.P. (grumman)

20090045438 - Field effect transistor, and multilayered epitaxial film for use in preparation of field effect transistor: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a... Agent: Dickstein Shapiro LLP

20090045439 - Heterojunction field effect transistor and manufacturing method thereof: A heterojunction field effect transistor includes a laminated body. The laminated body includes a channel layer of GaN, an electron supply layer of AlN or AlxGa1-xN (0.6≦x<1) formed on the channel layer, and a cap layer of GaN formed on the electron supply layer.... Agent: Rabin & Berdo, PC

20090045440 - Method of forming an mos transistor and structure therefor: In one embodiment, an MOS transistor is formed with trench gates. The gate structure of the trench gates generally has a first insulator that has a first thickness in one region of the gate and a second thickness in a second region of the gate.... Agent: Mr. Jerry Chruma Semiconductor Components Industries, L.L.C.

20090045441 - Cmos image sensor package: A CMOS image sensor package is disclosed. The CMOS image sensor package includes: a substrate, on which a pre-designed circuit pattern is formed, and in which a cavity is formed; a pixel array sensor, which is electrically connected with the circuit pattern and stacked on one side of the substrate;... Agent: Staas & Halsey LLP

20090045442 - Solid state imaging device and method for fabricating the same: A first oxide film (102) and a first nitride film (103) are formed over a semiconductor substrate (101) so as to be stacked in this order. A plurality of first gate electrodes (104) are arranged on the first nitride film (103) so as to be spaced apart from one another... Agent: Mcdermott Will & Emery LLP

20090045443 - Split trunk pixel layout: A pixel array architecture having multiple pixel cells arranged in a split trunk pixel layout and sharing common pixel cell components. The array architecture increases the fill factor, and in turn, the quantum efficiency of the pixel cells. The common pixel cell components may be shared by a number of... Agent: Dickstein Shapiro LLP

20090045444 - Integrated device and circuit system: An integrated circuit, comprising a substrate stack, comprising a first substrate and a second substrate, the first substrate comprising a first contact field on a side face of the substrate stack and the second substrate comprising a second contact field on the side face; a side substrate, comprising a first... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090045445 - Capacitor structure used for flash memory: A method of forming a capacitor for use as a charge pump with flash memory, comprising: (a) concurrently forming polysilicon gates on a semiconductor body in a core region and a polysilicon middle capacitor plate in a peripheral region, (b) forming a first dielectric layer over the polysilicon gates and... Agent: Thomas G. Eschweiler, Esq. Eschweiler & Associates, LLC

20090045446 - Power semiconductor device: A power semiconductor device having a first active semiconductor component and a second active semiconductor component, the electrical connections of which are routed out of the semiconductor components in the form of connecting legs is disclosed. In one embodiment, the first semiconductor component is at least partially electrically connected to... Agent: Dicke, Billig & Czaja

20090045447 - Complex oxide nanodots: Methods and devices are disclosed, such as those involving forming a charge trap for, e.g., a memory device, which can include flash memory cells. A substrate is exposed to temporally-separated pulses of a titanium source material, a strontium source material, and an oxygen source material capable of forming an oxide... Agent: Knobbe Martens Olson & Bear LLP

20090045448 - Non-volatile memory device and methods of forming the same: Example embodiments provide a non-volatile memory device and methods of forming the same. The non-volatile memory device may define an active region in a semiconductor substrate, and may include a device isolation layer extending in a first direction, bit lines in the semiconductor substrate, the bit lines extending in a... Agent: Harness, Dickey & Pierce, P.L.C

20090045449 - Finned memory cells: For an embodiment, a memory array has a plurality fins protruding from a substrate. A tunnel dielectric layer overlies the fins. A plurality floating gates overlie the tunnel dielectric layer, and the floating gates correspond one-to-one with the fins protruding from the substrate. An intergate dielectric layer overlies the floating... Agent: Leffert Jay & Polglaze, P.A.

20090045450 - Non-volatile memory device and method of fabricating the same: Provided are a non-volatile memory device, which may have higher integration density, improved or optimal structure, and/or reduce or minimize interference between adjacent cells without using an SOI substrate, and a method of fabricating the non-volatile memory device. The non-volatile memory device may include: a semiconductor substrate comprising a body,... Agent: Harness, Dickey & Pierce, P.L.C

20090045451 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device that comprises the steps of: removing a second insulating film on a contact region of a first conductor; forming a second conductive film on the second insulating film; removing the second conductive film on the contact region of the first conductor to make... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090045452 - Structure and method of sub-gate nand memory with bandgap engineered sonos devices: A bandgap engineered SONOS device structure for design with various AND architectures. The BE-SONOS device structure comprises a spacer oxide disposed between a control gate overlaying an oxide-nitride-oxide-nitride-oxide stack and a sub-gate overlaying a gate oxide. In one example, a BE-SONOS sub-gate-AND array architecture has multiple strings of SONONOS devices... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090045455 - Nonvolatile memory device and method of fabricating the same: Example embodiments relate to nonvolatile semiconductor memory devices using an electric charge storing layer as a storage node and fabrication methods thereof. An electric charge trap type nonvolatile memory device may include a tunneling film, an electric charge storing layer, a blocking insulation film, and a gate electrode. The blocking... Agent: Harness, Dickey & Pierce, P.L.C

20090045453 - Nonvolatile memory devices including gate conductive layers having perovskite structure and methods of fabricating the same: A nonvolatile memory device includes a tunneling insulating layer on a semiconductor layer. A charge storage layer is on the tunneling insulating layer. A blocking insulating layer having a Perovskite structure is on the charge storage layer. A gate conductive layer having a Perovskite structure is on the blocking insulating... Agent: Myers Bigel Sibley & Sajovec

20090045454 - Semiconductor non-volatile memory cell, method of producing the same, semiconductor non-volatile memory having the semiconductor non-volatile memory cell, and method of producing the same: A semiconductor non-volatile memory cell includes an Si (silicon) layer containing substrate including an activation region having a ridge portion; an element separation region embedded in both sides of the activation region; a gate electrode with a gate insulation film inbetween formed over the ridge portion for covering a part... Agent: Kubotera & Associates, LLC

20090045456 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device is provided. The method includes forming a gate structure on a substrate. The gate structure includes a patterned gate dielectric layer, a patterned gate conductor layer, a cap layer and a spacer. Next, a first and a second recesses are formed in the... Agent: J C Patents, Inc.

20090045457 - Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (tvs): A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate... Agent: Bo-in Lin

20090045458 - Mos transistors for thin soi integration and methods for fabricating the same: MOS transistors for thin SOI integration and methods for fabricating such MOS transistors are provided. One exemplary method includes the steps of providing a silicon layer overlying a buried insulating layer and epitaxially growing a silicon-comprising material layer overlying the silicon layer. A trench is etched within the silicon-comprising material... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20090045459 - Semiconductor device and method of manufacturing semiconductor device: According to an aspect of an embodiment, a semiconductor device has a semiconductor substrate, a gate insulating film on the semiconductor substrate, a gate electrode formed on the gate insulating film, an impurity diffusion region formed in an area of the semiconductor substrate adjacent to the gate electrode to a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090045460 - mosfet for high voltage applications and a method of fabricating same: P-type source and drain regions are provided by diffusion in the n-type active layer. A p-type plug is provided at the source region, which extends through the active semiconductor layer to the insulating layer. The plug is provided so as to enable the source voltage applied to the device to... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090045461 - Active device on a cleaved silicon substrate: A hydrogen (H) exfoliation gettering method is provided for attaching fabricated circuits to receiver substrates. The method comprises: providing a Si substrate; forming a Si active layer overlying the substrate with circuit source/drain (S/D) regions; implanting a p-dopant into the S/D regions; forming gettering regions underling the S/D regions; implanting... Agent: Sharp Laboratories Of America, Inc

20090045462 - Ultrathin soi cmos devices employing differential sti liners: An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions... Agent: Scully, Scott, Murphy & Presser, P.C.

20090045463 - Active device array substrate: An active device array substrate including a substrate, a plurality of pixel units, a plurality of driving lines, a plurality of common lines, an electrostatic discharge (ESD) protection circuit, and a plurality of switch elements is provided. The substrate has a display region and a peripheral region adjacent to the... Agent: Jianq Chyun Intellectual Property Office

20090045464 - Esd protection for high voltage applications: An ESD device includes a low doped well connected to a first contact and a diffusion area connected to a second contact. A substrate between the low doped well and the diffusion area has a dopant polarity that is opposite a dopant polarity of the low doped well and the... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090045465 - Semiconductor device and method for fabricating the same: A semiconductor device can prevent exposure of an inner wall of a recess pattern caused by misalignment between masks. A gate electrode is formed inside the recess pattern so that only a gate hard mask layer is exposed above a substrate surface. Since the gate electrode is not exposed above... Agent: Townsend And Townsend And Crew, LLP

20090045466 - Semiconductor device: There are accomplished nMOSFET and pMOSFET both having high mobility, by optimizing stress and location of a film existing around a gate electrode such that high stress acts on a channel. In nMOSFET, a first film having compressive stress is formed on a gate electrode, and a second film having... Agent: Sughrue Mion, PLLC

20090045467 - Bipolar transistor finfet technology: This document discusses, among other things, apparatus having at least one CMOS transistor overlying a substrate; and at least one finned bipolar transistor overlying the substrate and methods for making the apparatus.... Agent: Schwegman, Lundberg & Woessner / Infineon

20090045468 - Trench isolation and method of fabricating trench isolation: Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material... Agent: Schmeiser, Olsen & Watts

20090045469 - Semiconductor device and manufacturing method thereof: A semiconductor device including a silicon substrate; a gate insulating film on the silicon substrate; a gate electrode on the gate insulating film; and source/drain regions formed in the substrate on both sides of the gate electrode, wherein the gate electrode includes a first silicide layered region formed of a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090045470 - Semiconductor device and manufacturing method of the same: Provided is a technology capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A p type strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The p type strained layer has a thickness adjusted... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090045471 - Semiconductor device fabricated by selective epitaxial growth method: A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090045472 - Methodology for reducing post burn-in vmin drift: A semiconductor device includes source/drain regions formed in a substrate and having a concentration of nitrogen of at least about 5E18 cm−3. A gate dielectric is located over the substrate and between the source/drain regions. Gate sidewall spacers are located over said source/drain regions. A nitrogen-doped electrode including polysilicon is... Agent: Texas Instruments Incorporated

20090045473 - Devices having horizontally-disposed nanofabric articles and methods of making the same: New devices having horizontally-disposed nanofabric articles and methods of making same are described. A discrete electro-mechanical device includes a structure having an electrically-conductive trace. A defined patch of nanotube fabric is disposed in spaced relation to the trace; and the defined patch of nanotube fabric is electromechanically deflectable between a... Agent: Wilmerhale/boston

20090045474 - Mems sensor and production method of mems sensor: The MEMS sensor includes a substrate, a lower thin film, opposed to a surface of the substrate at an interval, having a plurality of lower through-holes formed to pass through the lower thin film in the thickness direction thereof, an upper thin film, opposed to the lower thin film at... Agent: Rabin & Berdo, PC

20090045475 - Double sided integrated processing and sensing chip: A high density integrated processing and sensing chip includes an integrated signal processing circuit formed on one side of a substrate and a magnetic sensor element formed on an opposing side of the substrate. In one embodiment, the integrated signal processing circuit and the magnetic sensor are able to electrically... Agent: Honeywell International Inc. Patent Services Ab-2b

20090045476 - Image sensor package and method for forming the same: An image sensor package is provided including a substrate; a sensor chip; a plurality of bond wires for connecting the sensor chip to the substrate at predetermined locations; a sensor housing on the substrate for substantially encompassing the sensor chip, the sensor housing having a through-hole cavity defining an optical... Agent: Mcdermott Will & Emery LLP

20090045477 - Solid-state imager having anti-reflection film, display, and its manufacturing method: Solid-state image sensors are disclosed that include an optical unit which separates incident light into a plurality of color elements, an optical receiving unit which converts each of the color elements separated by the optical unit to an electrical signal and an anti-reflection film having a high-refractive-index layer with a... Agent: Klarquist Sparkman, LLP

20090045478 - Cmos image sensor package structure: The present invention provides a complementary metal oxide semiconductor (CMOS) sensor package structure that includes a carrier substrate having a top surface and a bottom surface; a metal layer placed on the top surface of the carrier substrate and exposed a portion of the top surface of the metal layer;... Agent: Reed Smith LLP

20090045479 - Image sensor with vertical drain structures: An image sensor includes an array of photo-detectors, a plurality of conductive line regions, and a conductive junction region. The array of photo-detectors is formed in a semiconductor substrate. Each conductive line region is formed under a respective line of photo-detectors along a first direction in the substrate. The conductive... Agent: Law Office Of Monica H Choi

20090045480 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a plurality of circuit cells on a semiconductor chip. The plurality of circuit cells are formed along a first chip side of the semiconductor chip. Each of the plurality of circuit cells has a pad. The semiconductor integrated circuit further includes a high voltage potential... Agent: Mcdermott Will & Emery LLP

20090045481 - Semiconductor device having breakdown voltage maintaining structure and its manufacturing method: A semiconductor device has an active portion having at least one well region in a semiconductor layer, and a breakdown voltage maintaining structure surrounding the active portion. The maintaining structure includes a conductor layer over each of a plurality of guard rings with an insulating film interposed in between and... Agent: Rossi, Kimms & Mcdowell LLP.

20090045482 - Shallow trench isolation with improved structure and method of forming: A shallow trench isolation (STI) structure has a top portion tapering in width from wide to narrow in a direction from a substrate surface, from a first width at a top of the first portion to a second width at a bottom of the first portion. The STI structure also... Agent: Slater & Matsil, L.L.P.

20090045483 - Semiconductor devices having trench isolation regions and methods of manufacturing semiconductor devices having trench isolation regions: A semiconductor device may include a semiconductor substrate, trench region, buffer pattern, gap fill layer, and transistor. The trench region may be provided in the semiconductor substrate to define an active region. The buffer pattern and gap fill layer may be provided in the trench region. The buffer pattern and... Agent: Harness, Dickey & Pierce, P.L.C

20090045484 - Methods and systems involving electrically reprogrammable fuses: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the... Agent: Cantor Colburn LLP - IBM Fishkill

20090045485 - Capacitor, method of manufacturing capacitor, capacitor manufacturing apparatus, and semiconductor memory device: The present invention provides a capacitor including: an under electrode; an upper electrode; and a dielectric film which is provided between the under electrode and the upper electrode, wherein at least a portion of the dielectric film is composed of an aluminum oxide film deposited by an atomic layer deposition... Agent: Young & Thompson

20090045486 - Method of manufacturing nitride semiconductor device: A method of manufacturing a nitride semiconductor device includes the steps of: forming a mask of a pattern selectively covering a cutting line on a first major surface of a substrate; forming group III nitride semiconductor layers exposing the mask provided on the cutting line by selectively growing a group... Agent: Rabin & Berdo, PC

20090045487 - Semiconductor chip, method of fabricating the same and stacked package having the same: A semiconductor chip, a method of fabricating the same and a stacked package having the same are disclosed. The semiconductor chip includes a wafer, a semiconductor device disposed on the wafer, an insulating layer covering the semiconductor device and disposed on the wafer, a deep via formed to penetrate the... Agent: Sherr & Vaughn, PLLC

20090045488 - Magnetic shielding package structure of a magnetic memory device: This invention provides a magnetic shielding package structure of a magnetic memory device, in which at least a magnetic memory device is embedded between a magnetic shielding substrate and a magnetic shielding layer. A plurality of through vias is formed in the magnetic shielding substrate or the magnetic shielding layer,... Agent: Birch Stewart Kolasch & Birch

20090045489 - Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning... Agent: Perkins Coie LLP Patent-sea

20090045490 - Power semiconductor module: Included are a semiconductor package, a first bus bar, a second bus bar and a soldering control unit. The semiconductor package includes a power semiconductor element, a first electrode plate and a second electrode plate. The first bus bar is a conductive member which is soldered onto the main surface... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090045491 - Semiconductor package structure and leadframe thereof: A semiconductor package structure including a chip and a leadframe unit is provided. The chip has an active surface and a plurality of recesses disposed thereon. The leadframe unit has at least one packaging area in which the chip is disposed. The packaging area has a plurality of leads on... Agent: J C Patents, Inc.

20090045492 - Lead frame, semiconductor device, method of manufacturing the lead frame, and method of manufacturing the semiconductor device: A lead frame is provided which can prevent a short circuit between wires and the ends of adjacent leads, the short circuit being caused by wire sweep during the injection of molding resin, in a configuration where the electrodes of a semiconductor chip and the leads disposed around the semiconductor... Agent: Steptoe & Johnson LLP

20090045493 - Semiconductor component and method of producing: A semiconductor component and method for producing. The semiconductor component includes a semiconductor device and a leadframe. A package layout is defined and the orientation of electrically conductive members with respect to the semiconductor device and inner contact areas of the leadframe is altered so as to maximize the interfacial... Agent: Dicke, Billig & Czaja

20090045494 - Method for manufacturing a microelectronic package: The invention relates to a method of packaging an electronic microsystem (200) and further to such a packaged device. With the method a packaged electronic microsystem (200) can be manufactured using a flexible foil (80) having conductive tracks (100) on at least on side of the flexible foil. The electronic... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090045495 - Semiconductor device with side terminals: Side terminals 3 at respective corners of a package are higher than side terminals 4 on each side of the package. Thus, even if the side terminals 4 on each side are lower than those according to the conventional art owing to miniaturization or the like, when a device is... Agent: Steptoe & Johnson LLP

20090045497 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a wiring board having connection pads thereon and a semiconductor chip mounted on the wiring board. The wiring board and the semiconductor chip are covered with a sealing portion. Conductive members are extended upward from the connection pads and are exposed from the sealing portion. Rewiring... Agent: Young & Thompson

20090045496 - Stacked microelectronic devices and methods for manufacturing stacked microelectronic devices: Stacked microelectronic devices and methods of manufacturing stacked microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a plurality of electrically isolated, multi-tiered metal spacers on a front side of a first microelectronic die, and attaching a back-side surface of a second... Agent: Perkins Coie LLP Patent-sea

20090045498 - Partitioning of electronic packages: Partitioning electronic sensor packages is provided. The electronic sensor package includes an electronic component, a sensor device, and electrical connections between the electronic component and the sensor device. A dam is written in the electronic sensor package to partition the package into two or more sections, where the sensor device... Agent: Lumen Patent Firm

20090045499 - Semiconductor package having a plurality input/output members: A semiconductor package has a first substrate having a plurality of electrically conductive patterns formed thereon. A first semiconductor die is coupled to the plurality of conductive patterns. A second semiconductor die is coupled to the first semiconductor die by a die attach material. A third semiconductor die is coupled... Agent: Weiss & Moy PC

20090045500 - Power semiconductor module with a connected substrate carrier and production method therefor: A power semiconductor module includes a housing, a substrate carrier with a circuit thereon and electrical connection elements extending therefrom. The carrier has a cutout between its inner surface (facing the interior of the module) and its outer surface. The cutout is smaller at the inner surface than at the... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090045502 - Chip scale package with through-vias that are selectively isolated or connected to the substrate: A semiconductor chip scale package formed with through-vias, which can be either isolated or electrically connected to a substrate, and a method of producing the semiconductor chip scale package with through-vias, which can be isolated or electrically connected to the substrate.... Agent: Scully, Scott, Murphy & Presser, P.C.

20090045503 - Multidirectional semiconductor device package thermal enhancement systems and methods: The invention provides thermally-enhanced semiconductor device package systems and associated methods for reducing thermal resistance for improved heat egress. In one disclosed embodiment of the invention, a semiconductor device package system includes a packaged semiconductor device having operable contacts for external electrical coupling. The packaged device has an exposed surface,... Agent: Texas Instruments Incorporated

20090045501 - Structure on chip package to substantially match stiffness of chip: Chip packages and a related method are disclosed that provide a structure on a side opposite a chip on a carrier of a chip package to substantially match a stiffness of the chip. In one embodiment, a chip package includes a chip coupled to a carrier; and a structure on... Agent: Hoffman Warnick LLC

20090045504 - Semiconductor package through-electrode suitable for a stacked semiconductor package and semiconductor package having the same: A semiconductor package including a through-electrode for stacked a semiconductor package and a semiconductor package having the same is disclosed. The semiconductor package through-electrode includes a first electrode having a recessed portion formed therein to pass through a semiconductor chip. A second electrode is disposed within the recess of the... Agent: Ladas & Parry LLP

20090045505 - Electronic device with package module: A package module is provided. The package module comprises a substrate having a surface comprising a die region. A die is disposed in the die region of the surface on the substrate. A flexible heat spreader conformally covers the surface of the substrate and the die. The invention also discloses... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090045506 - Cu-mo substrate and method for producing same: A Cu—Mo substrate 10 according to the present invention includes: a Cu base 1 containing Cu as a main component; an Mo base having opposing first and second principal faces 2a, 2b and containing Mo as a main component, the second principal face 2b of the Mo base 2 being... Agent: Nixon Peabody, LLP

20090045507 - Flip chip interconnection: Methods for forming flip chip interconnection, in which the bump interconnect is defined at least in part by an underfill. The underfill includes a material that is thermally cured; that is, raising the temperature of the underfill material can result in progressive curing of the underfill through stages including a... Agent: Quarles & Brady LLP

20090045509 - Electronic device: An electronic device including: a semiconductor chip on which an integrated circuit is formed; an electrode formed on the semiconductor chip and electrically connected to the integrated circuit; a resin protrusion disposed on the semiconductor chip; an interconnect formed on the electrode and extending over the resin protrusion; a wiring... Agent: Harness, Dickey & Pierce, P.L.C

20090045508 - Oblong peripheral solder ball pads on a printed circuit board for mounting a ball grid array package: Methods, systems, and apparatuses for ball grid array land patterns are provided. A ball grid array land pattern includes a plurality of land pads and electrically conductive traces. The plurality of land pads is arranged in an array of rows and columns. A perimeter edge of the array includes a... Agent: Fiala & Weaver, P.l.l.c. C/o Intellevate

20090045510 - Semiconductor device and method for mounting semiconductor chip: A semiconductor device includes a rigid substrate, a flexible solid-state image sensor and bumps. The bumps are aligned along a pair of opposing edges of the rigid substrate, and the diameter of the bumps gradually increases from the center to the ends of the edges. Owing to the difference in... Agent: Birch Stewart Kolasch & Birch

20090045512 - Carrier substrate and integrated circuit: A carrier substrate comprising a through contact connecting a first contact field on a top face of the carrier substrate to a second contact field on a bottom face of the carrier substrate and a substrate material being provided around the through contact.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090045511 - Integrated circuit including parylene material layer: An integrated circuit includes a substrate including a contact pad, a redistribution line coupled to the contact pad, and a dielectric material layer between the substrate and the redistribution line. The integrated circuit includes a solder ball coupled to the redistribution line and a parylene material layer sealing the dielectric... Agent: Dicke, Billig & Czaja

20090045513 - Semiconductor chip package, electronic device including the semiconductor chip package and methods of fabricating the electronic device: A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension... Agent: Marger Johnson & Mccollom, P.C.

20090045515 - Monitoring the magnetic properties of a metal layer during the manufacture of semiconductor devices: A method for manufacturing a semiconductor device that comprises forming an interconnect structure in an insulating layer located on a semiconductor substrate. The method also comprises depositing a metal cap layer on the interconnect structure and measuring a magnetic property of the metal cap layer. The magnetic property is compared... Agent: Texas Instruments Incorporated

20090045514 - Semiconductor device containing an aluminum tantalum carbonitride barrier film and method of forming: The method includes providing a substrate containing a dielectric layer having a recessed feature and forming a aluminum tantalum carbonitride barrier film over a surface of the recessed feature. The aluminum tantalum carbonitride barrier film is formed by depositing a plurality of tantalum carbonitride films, and depositing aluminum between each... Agent: Tokyo Electron U.s. Holdings, Inc.

20090045516 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20090045517 - Method for forming tungsten film, film-forming apparatus, storage medium and semiconductor device: The tungsten film is formed through a process in which a silicon-containing gas is delivered to a wafer M placed within a processing container 14 and a process executed after the silicon-containing gas supply process, in which a first tungsten film 70 is formed by alternately executing multiple times, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090045518 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device includes forming a plurality of conductive patterns over a substrate, forming a spin on dielectric (SOD) layer filling a portion of space between the conductive patterns, and forming an insulation pattern filling the remaining space over the SOD layer, wherein the stacked structure... Agent: Townsend And Townsend And Crew, LLP

20090045520 - Ic device having compact design: An IC device has a compact design. Capacitors, resistances and inductances are directly integrated in the IC device without packaging in advance. Thus, the IC device obtained has a slim size and an electric apparatus using the IC device has a big space for use.... Agent: Troxell Law Office PLLC

20090045519 - Semiconductor device and method of producing the same: In one embodiment of the present invention, a process is disclosed for producing a semiconductor device that can suppress the diffusion of an electrically conductive metal into an insulating film. The process for producing a semiconductor device is characterized by including the steps of (1) forming a groove in an... Agent: Harness, Dickey & Pierce, P.L.C

20090045521 - Semiconductor device: A semiconductor device includes: an interlayer insulation film; a lower interconnection layer; an upper interconnection layer; and a via hole extending through the interlayer insulation film to establish electric connection between the lower and upper interconnections; wherein a plurality of interconnection lines is provided in the lower interconnection layer, and... Agent: Mcdermott Will & Emery LLP

20090045522 - Semiconductor device having via connecting between interconnects: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect... Agent: Mcdermott Will & Emery LLP

20090045524 - Microelectronic package: A microelectronic package includes a lower unit having a lower unit substrate with conductive features and a top and bottom surface. The lower unit includes one or more lower unit chips overly/ing the top surface of the lower unit substrate that are electrically connected to the conductive features of the... Agent: Tessera Lerner David Et Al.

20090045527 - Multi-substrate region-based package and method for fabricating the same: A multi-substrate region-based package and a method for fabricating the same are provided. An active surface of a chip is divided into a plurality of functional regions, and each of the functional regions is electrically connected to a corresponding substrate via bonding wires. Each of the functional regions has a... Agent: Edwards Angell Palmer & Dodge LLP

20090045525 - Semiconductor element and semiconductor device: A semiconductor element is provided with electrode pads which are arranged on a front surface of an element main body, an insulating protection film which covers the front surface of the element main body excepting its outer peripheral area while exposing the electrode pads, and an insulating adhesive layer which... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090045523 - Semiconductor package-on-package (pop) device avoiding crack at solder joints of micro contacts during package stacking: A stacked semiconductor device primarily comprises semiconductor packages with a plurality of micro contacts and solder paste to soldering the micro contacts. Each semiconductor package comprises a substrate and a chip disposed on the substrate. The micro contacts of the bottom semiconductor package are a plurality of top bumps located... Agent: Joe Mckinney Muncy

20090045526 - Stacked memory without unbalanced temperature distributions: A stacked memory without unbalanced temperature distributions is disclosed. According to one aspect of the invention, a through electrode in each layer is connected one after the other such that regions to be activated in neighboring layers do not overlap in a vertical direction. According to another aspect of the... Agent: Mcginn Intellectual Property Law Group, PLLC

20090045528 - Semiconductor device: An electronic structural member or a semiconductor device having conductive bumps is provided. The conductive bump includes an organic buffer layer with an undercut structure, and the conductive bump is deformable during the bonding process so as to compensate the height difference between the conductive bumps. In addition, an adhesive... Agent: Morris Manning Martin LLP

20090045529 - Method of manufacturing semiconductor device: There is provided a method of manufacturing a semiconductor device. The method includes the successive steps of: (a) providing a semiconductor substrate; (b) forming a plurality of semiconductor chips having electrode pads on the semiconductor substrate; (c) forming internal connection terminals on the electrode pads; (d) forming an insulating layer... Agent: Rankin, Hill & Clark LLP

20090045530 - Microelectronic lithographic alignment using high contrast alignment mark: A microelectronic structure, and in particular a semiconductor structure, includes a substrate that includes an alignment mark comprising a substantially present element that has an atomic number at least 5 greater than a highest atomic number substantially present element within the substrate. Alignment to the alignment mark may be effected... Agent: Scully, Scott, Murphy & Presser, P.C.

20090039329 - Integrated circuit having a cell with a resistivity changing layer: In an embodiment of the invention, an integrated circuit having a cell is provided. The cell may include a field effect transistor structure which includes a gate stack and a resistivity changing material structure disposed above the gate stack, wherein the resistivity changing material structure includes a resistivity changing material... Agent: Slater & Matsil, L.L.P.

20090039330 - Two-terminal resistance switching element with silicon, and semiconductor device: A two-terminal resistance switching element, wherein two silicon films each doped with an impurity are arranged with a gap width in the order of nanometers.... Agent: Birch Stewart Kolasch & Birch

20090039337 - Memory element and memory device: A memory element having a storage layer containing an ion source layer between a first electrode and a second electrode is provided. The memory element stores information by changing an electrical characteristic of the storage layer, wherein at least Zr is added to the ion source layer as a metal... Agent: Bell, Boyd & Lloyd, LLP

20090039331 - Phase change material structures: Structures including a phase change material are disclosed. The structure may include a first electrode; a second electrode; a phase change material electrically connecting the first electrode and the second electrode for passing a current therethrough; and a tantalum nitride heater layer about the phase change material for converting the... Agent: Hoffman Warnick LLC

20090039333 - Phase change memory device and method for manufacturing the same: A phase change memory device includes a silicon substrate having a bar-type active region and an N-type impurity region formed in a surface of the active region. A first insulation layer is formed on the silicon substrate, and the first insulation layer includes a plurality of first contact holes and... Agent: Ladas & Parry LLP

20090039338 - Phase change memory devices and fabrication methods thereof: In a memory device, at least one conductive contact having a width of less than, or equal to, about 30 nm may be formed on a first electrode. A dielectric layer may be formed on the sides of the at least one conductive contact, and a phase change material film... Agent: Harness, Dickey & Pierce, P.L.C

20090039334 - Phase-change memory device and method for manufacturing the same: A phase-change memory device and a fabrication method thereof, capable of reducing driving current while minimizing a size of a contact hole used for forming a PN diode in the phase-change memory device that employs the PN diode. The method of fabricating the phase-change memory device includes the steps of... Agent: Baker & Mckenzie LLP Patent Department

20090039332 - Resistive non-volatile memory device: The present disclosure provides a memory cell. The memory cell includes a first electrode, a variable resistive material layer coupled to the first electrode, a metal oxide layer coupled the variable resistive material layer; and a second electrode coupled to the metal oxide layer. In an embodiment, the metal oxide... Agent: Haynes And Boone, LLPIPSection

20090039336 - Semiconductor device: The performance of a semiconductor device capable of storing information is improved. A memory layer of a memory element is formed by a first layer at a bottom electrode side and a second layer at a top electrode side. The first layer contains 20-70 atom % of at least one... Agent: Miles & Stockbridge PC

20090039335 - Semiconductor device and manufacturing method of the same: On an insulating film (31) in which a plug (35) is embedded, a second component releasing region (45) made of a first component and a second component, a solid electrolyte region (46) made of chalcogenide and an upper electrode region (47) are sequentially formed. The second component releasing region (45)... Agent: Miles & Stockbridge PC

20090039339 - Nonpolar iii-nitride light emitting diodes with long wavelength emission: A III-nitride film, grown on an m-plane substrate, includes multiple quantum wells (MQWs) with a barrier thickness of 27.5 nm or greater and a well thickness of 8 nm or greater. An emission wavelength can be controlled by selecting the barrier thickness of the MQWs. Device fabricated using the III-nitride... Agent: Gates & Cooper LLP Howard Hughes Center

20090039340 - Method and apparatus for acquiring physical information, method for manufacturing semiconductor device including array of a plurality of unit components for detecting physical quantity distribution, light-receiving device and manufacturing method therefor: Method and apparatus for acquiring physical information, method for manufacturing semiconductor device including array of a plurality of unit components for detecting physical quantity distribution, light-receiving device and manufacturing method therefor, and solid-state imaging device and manufacturing method therefore are provided. The method for acquiring physical information uses a device... Agent: Bell, Boyd & Lloyd, LLP

20090039341 - Method for the manufacturing of a non-volatile ferroelectric memory device and memory device thus obtained: The present invention relates to non-volatile ferroelectric memory devices (30) comprising a transistor (22) and a capacitor (23), and more particularly to non-volatile electrically erasable programmable ferroelectric memory elements, and a method for processing such non-volatile ferroelectric memory devices (30). The method according to the invention comprises a limited number... Agent: Philips Intellectual Property & Standards

20090039344 - Poly[bis(ethynyl)heteroacene]s and electronic devices generated therefrom: wherein R1 is hydrogen, halogen, a suitable hydrocarbon, or a heteroatom containing group; R2 is hydrogen, a suitable hydrocarbon, a heteroatom containing group, or a halogen; R3 and R4 are independently a suitable hydrocarbon, hydrogen, a heteroatom containing group, or a halogen; Ar is an aromatic component; x, y, a,... Agent: Fay Sharpe / Xerox - Rochester

20090039342 - Thin film field-effect transistor and process for producing the same: Such a thin film transistor and a process for producing the same are provided that is capable of preventing the FET characteristics from being deteriorated with a short channel length. Such a thin film field-effect transistor and a process for producing the same are provided that contains a substrate 10,... Agent: Kanesaka Berner And Partners LLP

20090039343 - Transistor: An electrolyte-gated field effect transistor is disclosed, the transistor comprising an electrolyte including a polymeric ionic liquid analogue. In a preferred embodiment, the transistor further comprises a source electrode, a drain electrode disposed so as to be separated from the source electrode, forming a gap between the source and drain... Agent: Oliff & Berridge, PLC

20090039346 - Mesoporous thin film and method of producing the same: A mesoporous thin film of the invention, in which a crosslinking structure having a metal phosphate (M—POx) skeleton is arranged so as to surround periodically arranged pores, is formed by use of a process that includes: a step of preparing a precursor solution containing phosphoric acid and a surfactant; a... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20090039345 - Tunnel junction barrier layer comprising a diluted semiconductor with spin sensitivity: The invention provides a magnetic tunnel junction having a tunneling barrier layer wherein said tunneling barrier layer comprises a diluted magnetic semiconductor with spin sensitivity. The magnetic tunnel junction may according to the invention comprise a bottom lead coupled to a bottom electrode which is coupled to a diluted magnetic... Agent: Ladas & Parry LLP

20090039348 - Multiple testing bars for testing liquid crystal display and method thereof: A plurality of gate lines are formed on an insulating substrate in the horizontal direction, a gate shorting bar connected to the data lines is formed in the vertical direction and a gate insulating film is formed thereon. A plurality of data lines intersecting the gate lines are formed on... Agent: Macpherson Kwok Chen & Heid LLP

20090039347 - Programming a microchip id register: A method is disclosed for programming an ID register of a microchip. The method comprises the step, prior to packaging, of attaching at least one additional ID pin to the die of the microchip. The at least one pin being so attached that, when the microchip is packaged, the at... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20090039352 - Display device and electronic device having the display device, and method for manufacturing thereof: To provide a display device including a thin film transistor in which high electric characteristics and reduction in off-current can be achieved. The display device having a thin film transistor includes a substrate, a gate electrode provided over the substrate, a gate insulating film provided over the gate electrode, a... Agent: Eric Robinson

20090039351 - Display device and manufacturing method thereof: To provide a display device having a thin film transistor with high electric characteristics and excellent reliability and a manufacturing method thereof. A gate electrode, a gate insulating film provided over the gate electrode, a first semiconductor layer provided over the gate insulating film and having a microcrystalline semiconductor, a... Agent: Eric Robinson

20090039350 - Display panel and method of manufacturing the same: In a display panel and a method of manufacturing the display panel, a gate line, a data line, and source and drain electrodes including a same material as the data line are formed on a substrate constituting the display panel, and the data line includes an aluminum based alloy containing... Agent: Macpherson Kwok Chen & Heid LLP

20090039349 - Manufacturing method of semiconductor device, manufacturing method of display device, semiconductor device, display device, and electronic device: A method for manufacturing a semiconductor device provided with a circuit capable of high speed operation while the manufacturing cost is reduced. A method for manufacturing a semiconductor device which includes forming an ion-doped layer at a predetermined depth from a surface of a single-crystal semiconductor substrate and forming a... Agent: Eric Robinson

20090039355 - Display device: A current pixel circuit of a display device includes a switching transistor which may be turned on in response to the current selection signal to transfer a data signal, a driving transistor for outputting a current corresponding to the data signal, and first and second transistors being turned on in... Agent: Christie, Parker & Hale, LLP

20090039353 - Organic light-emitting display device and method of manufacturing the same: An organic light-emitting display device includes a substrate; a gate electrode disposed on the substrate, the gate electrode including a first portion of a metal oxide layer and a metal layer; a pixel electrode disposed on the substrate so as to be insulated from the gate electrode, the pixel electrode... Agent: Stein, Mcewen & Bui, LLP

20090039354 - Tft array substrate and manufacturing method thereof: Provided are a thin film transistor (TFT) array substrate and the method manufacturing thereof. The TFT array substrate comprising: a substrate, and a gate line and a data line formed on the substrate, the gate line and the data line being separated by a gate insulating layer therebetween and intersecting... Agent: Ladas & Parry LLP

20090039356 - Planar nonpolar m-plane group iii-nitride films grown on miscut substrates: A nonpolar III-nitride film grown on a miscut angle of a substrate. The miscut angle towards the <000-1> direction is 0.75° or greater miscut and less than 27° miscut towards the <000-1> direction. Surface undulations are suppressed and may comprise faceted pyramids. A device fabricated using the film is also... Agent: Gates & Cooper LLP Howard Hughes Center

20090039358 - Sic crystal semiconductor device: A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers by high temperature annealing and a SiC semiconductor device fabricated by the method. The method for improving the quality of a SiC layer by eliminating or reducing some carrier trapping centers... Agent: The Webb Law Firm, P.C.

20090039357 - Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors: A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20090039359 - Light emitting diode with improved current spreading performance: Disclosed is a light emitting diode (LED) for enhancing the current spreading performance. The LED includes a plurality of contact holes exposing an N-type semiconductor layer through a P-type semiconductor layer and an active layer, and a connection pattern electrically connecting exposed portions of the N-type semiconductor layer through the... Agent: H.c. Park & Associates, PLC

20090039360 - Solid-state area illumination system: A solid-state area illumination system includes multiple LED devices, each LED device is formed on a separate substrate and each LED device emits differently colored light at different angles relative to the substrate. The peak frequencies of each color of light differ by at least the smallest of the full... Agent: David Novais Patent Legal Staff

20090039361 - Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication: A method of forming a semiconductor structure includes forming an opening in a dielectric layer, forming a recess in an exposed part of a substrate, and forming a lattice-mismatched crystalline semiconductor material in the recess and opening.... Agent: Goodwin Procter LLP Patent Administrator

20090039362 - Semiconductor light emitting device: A semiconductor light emitting device and a method of manufacturing the semiconductor light emitting device are provided. The semiconductor light emitting device comprises a substrate having a top surface that is curved to protrude, and a light emitting structure that is curved to protrude on the substrate and comprises an... Agent: Birch Stewart Kolasch & Birch

20090039363 - Semiconductor light emitting device and method of manufacturing the same: Provided are a semiconductor light emitting device and a method of manufacturing the same. The semiconductor light emitting device comprises a first conductive type semiconductor layer, an active layer, a first thin insulating layer, and a second conductive type semiconductor layer. The active layer is formed on the first conductive... Agent: Birch Stewart Kolasch & Birch

20090039364 - Semiconductor light emitting device and method of manufacturing the same: Provided are a semiconductor light emitting device and a method of manufacturing the same. The semiconductor light emitting device comprises a first conductive type semiconductor layer, an active layer, a first thin insulating layer, and a second conductive type semiconductor layer. The active layer is formed on the first conductive... Agent: Birch Stewart Kolasch & Birch

20090039374 - Flip chip type light-emitting element: In a flip chip type light-emitting element of the present invention, an n type contact electrode 14 is formed on an n layer 11 exposed in a comb-tooth shape, a light transmission electrode 15 made of an ITO is formed over the entire surface of an upper surface of a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090039373 - Group iii nitride-based compound semiconductor light emitting device: A group III nitride-based compound semiconductor light emitting device includes a polarity inversion layer including a surface with a convex portion, and a transparent electrode formed on the polarity inversion layer. The polarity inversion layer may have a magnesium concentration of not less than 1×1020 atoms/cm3, or not less than... Agent: Mcginn Intellectual Property Law Group, PLLC

20090039367 - Light emitting diodes with a p-type surface bonded to a transparent submount to increase light extraction efficiency: An (Al,Ga,In)N-based light emitting diode (LED), comprising a p-type surface of the LED bonded with a transparent submount material to increase light extraction at the p-type surface, wherein the LED is a substrateless membrane.... Agent: Gates & Cooper LLP Howard Hughes Center

20090039368 - Light-emitting device: A light-emitting device offering satisfactory light emission characteristics combined with improved reliability has a substrate on the principal surface of which a non-polar electrode layer is formed, an LED chip mounted in a predetermined region on the non-polar electrode layer, a plurality of cathode and anode electrode layers formed on... Agent: Mots Law, PLLC

20090039369 - Semiconductor light emitting apparatus: A semiconductor light emitting apparatus can include a housing filled with a wavelength conversion material-containing resin material which seals a semiconductor light emitting device inside the recess of the housing. A transparent resin material can be charged on the wavelength conversion material-containing resin material, and can be configured to prevent... Agent: Cermak Kenealy & Vaidya, LLP

20090039370 - Semiconductor light emitting device: A semiconductor light emitting device and a method of manufacturing the semiconductor light emitting device are provided. The semiconductor light emitting device comprises a substrate having a top surface that is curved to protrude, and a light emitting structure that is curved to protrude on the substrate and comprises an... Agent: Birch Stewart Kolasch & Birch

20090039372 - Semiconductor light emitting device: A semiconductor light emitting device includes a semiconductor light emitting element, a lead electrically connected to the semiconductor light emitting element, and a resin package covering the semiconductor light emitting element and part of the lead. The resin package includes a lens facing the front of the semiconductor light emitting... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20090039371 - Semiconductor light emitting device and light emitting apparatus having the same: A semiconductor light emitting device and a light emitting apparatus having the semiconductor light emitting device are provided. The semiconductor light emitting device comprises a substrate, a light emitting structure on the substrate, comprising a first conductive type semiconductor layer, an active layer, a second conductive type semiconductor layer, and... Agent: Birch Stewart Kolasch & Birch

20090039365 - Semiconductor light emitting devices with applied wavelength conversion materials and methods of forming the same: A semiconductor structure includes an active region configured to emit light upon the application of a voltage thereto, a window layer configured to receive the light emitted by the active region, and a plurality of discrete phosphor-containing regions on the window layer and configured to receive light emitted by the... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090039375 - Semiconductor light emitting devices with separated wavelength conversion materials and methods of forming the same: A semiconductor device includes a semiconductor light emitting device (LED) that emits light having a first peak wavelength upon the application of a voltage thereto, and first and second phosphor-containing regions on the LED that receive the light and convert at least a portion of the light to light having... Agent: Myers Bigel Sibley & Sajovec, P.A.

20090039366 - Semiconductor light-emitting device with high heat-dissipation efficiency and method for fabricating the same: The invention discloses a semiconductor light-emitting device and a method of fabricating the same. The semiconductor light-emitting device according to the invention includes a substrate, a multi-layer structure, a first electrode structure, and a second electrode structure. The substrate has an upper surface and a lower surface. The substrate therein... Agent: Birch Stewart Kolasch & Birch

20090039379 - Heat radiation package and semiconductor device: A heat radiation package of the present invention includes a substrate in an upper surface side of which recess portion is provided, embedded wiring portion which is filled in the recess portion of the substrate and on which semiconductor element which generates a heat is mounted, and a heat sink... Agent: Kratz, Quintos & Hanson, LLP

20090039381 - Light emitting diode package and method of manufacturing the same: An LED package is disclosed. The LED package includes a substrate having a plurality of sub patterns adhered by insulation adhesive, an LED chip mounted on the substrate and electrically connected to the substrate and a molding cap covering the LED chip. According to the LED package, as well as... Agent: The Farrell Law Firm, P.C.

20090039382 - Light emitting diode package structure: A light emitting diode (LED) package structure includes a substrate, an LED, a heat conducting layer, and a lead layer. The substrate is provided with a recess, in which the LED is disposed. The heat conducting layer is plated on outer surfaces of the substrate for transferring heat energy generated... Agent: Rosenberg, Klein & Lee

20090039376 - Light source, manufacturing method of light source, lighting apparatus, and display apparatus: Provided is a light source that has high reliability and hardly causes conductivity failure between a light emitting device and a conductive land. In an LED light source of the present invention, an LED bare chip is mounted to conductive lands of a substrate, using bumps (55a, 55b). The LED... Agent: Snell & Wilmer L.L.P. (panasonic)

20090039378 - Light-emitting film, light-emitting device and production method thereof: Provided is a light-emitting film having controllable resistivity, and a high-luminance light-emitting device, which can be driven at a low voltage, using such light-emitting film. The light-emitting film includes Cu as an addition element in a zinc sulfide compound which is a base material, wherein the zinc sulfide compound includes... Agent: Fitzpatrick Cella Harper & Scinto

20090039377 - Optical communication module and manufacturing method thereof: An infrared data communication module (A1) includes a substrate (1) consisting of a first layer (1A) and a second layer (1B), where the first layer is formed with a recess (11) open at its obverse surface, and includes the opening of the recess (11) and the second layer is fixed... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20090039380 - Package and semiconductor device: A package has a base substrate that is a metal plate electrically connected to one electrode of a UV-ray light emitting diode and a cover substrate that is a metal plate electrically connected to the other electrode and that is stacked on the base substrate. A plurality of packages are... Agent: Drinker Biddle & Reath (dc)

20090039383 - Vertical light emiting diode and method of making a vertical light emiting diode: A vertical gallium-nitrate-based LED and method of making a vertical gallium-nitrate-based LED using a stop layer is provided. Embodiments of the present invention use mechanical thinning and a plurality of superhard stop points to remove epitaxial layers with a high level of certainty. According one embodiment, the method of making... Agent: Venable LLP

20090039384 - Power rectifiers and method of making same: In one embodiment the present invention includes a semiconductor rectifier device comprising a first, second, and third semiconductor regions and a gate. The first semiconductor region is of a first conductivity type. The second semiconductor region is adjacent to the first semiconductor region which has a second conductivity type. The... Agent: Fountainhead Law Group, PC

20090039385 - Semiconductor devices: A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises... Agent: Greenblum & Bernstein, P.L.C

20090039386 - Semiconductor device: A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090039387 - Solid-state imaging element and method for manufacturing the same: A solid-state imaging element includes a layered substrate made of silicon and composed of, for example, an N-type substrate, a P-type layer, and an N-type layer. In the layered substrate, an imaging region in which a plurality of pixels are arranged and a peripheral circuit region are formed. A recess... Agent: Mcdermott Will & Emery LLP

20090039390 - Cmos transistor junction regions formed by a cvd etching and deposition sequence: This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090039388 - Integrated circuit system employing a condensation process: An integrated circuit system that includes: providing a PFET device including a PFET gate and a PFET gate dielectric; forming a source/drain extension from a first epitaxial layer aligned to a first PFET gate sidewall spacer; and forming a source/drain from a second epitaxial layer aligned to a second PFET... Agent: Law Offices Of Mikio Ishimaru

20090039389 - Method of fabricating metal oxide semiconductor transistor: The present invention provides a method for fabricating a metal oxide semiconductor transistor. First, a semiconductor substrate is provided and at least a gate is formed on the semiconductor substrate. A protective layer is then formed on the semiconductor substrate and the gate. Subsequently, at least a recess is formed... Agent: North America Intellectual Property Corporation

20090039391 - Semiconductor device and method for fabricating the same: On an insulation layer 12 formed on a silicon substrate 10, there are formed in an NMOS transistor region 16 an NMOS transistor 14 comprising a silicon layer 34, a lattice-relaxed silicon germanium layer 22 formed on the silicon layer 34, a tensile-strained silicon layer 24 formed on the silicon... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090039392 - Iii-nitride power semiconductor device: A III-nitride power semiconductor device that includes a two dimensional electron gas having a reduced charge region under the gate thereof.... Agent: Ostrolenk Faber Gerb & Soffen

20090039393 - Semiconductor device and method for manufacturing same: The semiconductor device, which provides reduced electric current leakage and parasitic resistance to achieve stable current gain, is provided. A first polycrystalline semiconductor layer is grown on a p-type polycrystalline silicon film exposed in a lower surface of a visor section composed of a multiple-layered film containing a p-type polycrystalline... Agent: Young & Thompson

20090039394 - Semiconductor device: The present invention enhances voltage conversion efficiency of a semiconductor device. In a non-isolated DC-DC converter that includes a high-side switch power MOSFET and a low-side switch power MOSFET, which are series-connected, the high-side switch power MOSFET and driver circuits for driving the high-side and low-side switch power MOSFETs are... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090039395 - Solid state image sensor: Forming an impurity region 6 and an impurity region 5 having a lower concentration than the impurity region 6 in a lower layer region of a gate electrode close to the boundary with a signal electron-voltage conversion section of a horizontal CCD outlet makes it possible to smooth a potential... Agent: Steptoe & Johnson LLP

20090039396 - Semiconductor substrate, semiconductor device, method of producing semiconductor substrate, and method of producing semiconductor device: A semiconductor substrate includes: a first semiconductor layer; an oxide layer that is formed on the first semiconductor layer; a second semiconductor layer that is formed on the oxide layer; a first recess that is formed in the second semiconductor layer with extending from an upper face of the second... Agent: Birch Stewart Kolasch & Birch

20090039397 - Image sensor structure: An avalanche photodiode is deposited and integrated directly on top of CMOS readout circuitry. The anode of the avalanche photodiode may be independently biased at high voltage so that the avalanche photodiode may be operated in an avalanche multiplication mode. The avalanche photodiode has a multi-layered structure which is not... Agent: Jianq Chyun Intellectual Property Office

20090039398 - Semiconductor device and manufacturing method of the same: An n type impurity region is continuously formed on the bottom portion of a channel region below a source region, a gate region and a drain region. The n type impurity region has an impurity concentration higher than the channel region and a back gate region, and is less influenced... Agent: Morrison & Foerster LLP

20090039399 - Semiconductor device and fabrication method of the same: A semiconductor device in which semiconductor epitaxial layers are embedded in the source/drain regions includes an element formation region formed in the major surface of a semiconductor substrate, a gate electrode formed on a part of the element formation region, the semiconductor epitaxial layers formed in the source/drain regions of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090039400 - Image sensor with inter-pixel isolation: An image sensor with a plurality of photodiodes that each have a first region constructed from a first type of material and a second region constructed from a second type of material. Located adjacent to the first region and between second regions of adjacent photodiodes is a barrier region. The... Agent: Irell & Manella LLP

20090039401 - Logic circuit and single-electron spin transistor: A logic circuit that can reconfigure its functions in a nonvolatile manner and a single-electron transistor to be used in the logic circuits are provided. The logic circuit has a single-electron spin transistor that includes: a source; a drain; an island that is provided between the source and the drain,... Agent: Oliff & Berridge, PLC

20090039402 - Semiconductor device with asymmetric transistor and method for fabricating the same: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090039403 - Semiconductor device including an improved capacitor and method for manufacturing the same: In a semiconductor device according to embodiments of the invention, a capacitor includes a storage electrode having a cylindrical storage conductive layer pattern and connecting members formed on the upper portion of the cylindrical storage conductive layer pattern. The connecting member connects to an adjacent connecting member of another storage... Agent: Marger Johnson & Mccollom, P.C.

20090039404 - Capacitor for a semiconductor device and method of forming the same: In a capacitor having a high dielectric constant, the capacitor includes a cylindrical lower electrode, a dielectric layer and an upper electrode. A metal oxide layer is formed on inner, top and outer surfaces of the lower electrode as the dielectric layer. A first sub-electrode is formed on a surface... Agent: Marger Johnson & Mccollom, P.C.

20090039405 - Oro and orpro with bit line trench to suppress transport program disturb: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and... Agent: Amin, Turocy & Calvin, LLP

20090039408 - Nonvolatile semiconductor memory and manufacturing method thereof: A nonvolatile semiconductor memory of an aspect of the present invention comprises a first element isolation insulating film containing an organic substance which surrounds a first region, a memory cell arranged in the first region, a second element isolation insulating film containing an organic substance which surrounds a second region,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090039406 - Semiconductor device manufacturing method, semiconductor device, plasma nitriding treatment method, control program and computer storage medium: A nitrided region is formed on a surface of a polysilicon layer by a nitriding treatment wherein plasma of a processing gas is generated by introducing microwaves into a processing chamber by a planar antenna having a plurality of slots. Then, a CVD oxide film or the like is formed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090039409 - Semiconductor memory device including multi-layer gate structure: A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent... Agent: Frommer Lawrence & Haug

20090039407 - Vertically integrated flash eprom for greater density and lower cost: A nonvolative memory in the form of a vertical flash EPROM with high density and low cost. A vertical MOS transistor is formed in well etched into a semiconductor substrate, the substrate having source, body and drain regions formed by ion implantation. A thin gate oxide or oxide-nitride-oxide (ONO) layer... Agent: Ronald Craig Fish, A Law Corporation

20090039410 - Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing: An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in... Agent: Dla Piper US LLP

20090039413 - Method to form uniform tunnel oxide for flash devices and the resulting structures: Thin oxide films are grown on silicon which has been previously treated with a gaseous or liquid source of chloride ions. The resulting oxide is of more uniform thickness than obtained on untreated silicon, thereby allowing a given charge to be stored on a floating gate formed over said oxide... Agent: Macpherson Kwok Chen & Heid LLP

20090039411 - Semiconductor device and method of manufacturing the same: According to an aspect of an embodiment, a semiconductor device has a substrate a first insulator formed in a first area of the substrate, and a second insulator formed in the second area of the substrate, a first transistor formed over a first device region surrounded by the first area,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090039412 - Semiconductor device including nonvolatile memory and method of fabricating the same: A semiconductor device including a nonvolatile memory and the fabrication method of the semiconductor device is described. There is provided a semiconductor device, including a semiconductor substrate, a nonvolatile memory cell including a first MOS transistor having a first gate formed on the semiconductor substrate, and source-drain regions formed in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090039414 - Charge trapping memory cell with high speed erase: A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a metal or metal compound gate, such as a platinum gate, by a blocking layer of material having a high dielectric constant, such as aluminum oxide, and separated from the semiconductor body including... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090039415 - Method of forming dielectric including dysprosium and scandium by atomic layer deposition and integrated circuit device including the dielectric layer: In one embodiment, the method of forming a dielectric layer includes supplying a first precursor at a temperature less than 400 degrees Celsius to a chamber including a substrate. The first precursor includes dysprosium. A first reaction gas is supplied to the chamber to react with the first precursor. A... Agent: Harness, Dickey & Pierce, P.L.C

20090039416 - Blocking dielectric engineered charge trapping memory cell with high speed erase: A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090039417 - Nonvolatile flash memory device and method for producing dielectric oxide nanodots on silicon dioxide: A method of producing dielectric oxide nanodots (104) embedded in silicon dioxide as well as a nonvolatile flash memory device comprising a trapping layer (224), the trapping layer (224) comprising dielectric oxide nanodots (104) embedded in silicon dioxide are presented. Firstly an ultra-thin metal film is deposited over a first... Agent: Davidson Berquist Jackson & Gowdey LLP

20090039418 - Multiple device types including an inverted-t channel transistor and method therefor: A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method... Agent: Freescale Semiconductor, Inc. Law Department

20090039419 - Semiconductor component with dynamic behavior: One embodiment provides a semiconductor component including a semiconductor body having a first side and a second side and a drift zone; a first semiconductor zone doped complementarily to the drift zone and adjacent to the drift zone in a direction of the first side; a second semiconductor zone of... Agent: Dicke, Billig & Czaja

20090039420 - Finfet memory cell having a floating gate and method therefor: A fin field effect transistor (FinFET) memory cell and method of formation has a substrate for providing mechanical support. A first dielectric layer overlies the substrate. A fin structure overlies the dielectric layer and has a first current electrode and a second current electrode separated by a channel. A floating... Agent: Freescale Semiconductor, Inc. Law Department

20090039421 - Nitride semiconductor device and method for producing nitride semiconductor device: f

20090039422 - Recess gate of semiconductor device and method for forming the same: A method for fabricating a semiconductor device, and more particularly, a method for forming a recess gate is disclosed. The method for forming a recess gate includes forming a first nitride layer over a semiconductor substrate, forming a first nitride layer pattern by selectively etching the first nitride layer to... Agent: Sherr & Vaughn, PLLC

20090039423 - Semiconductor device and method of manufacturing the same: A semiconductor device with first and second groups of transistors, the second group transistors each having a lower operating voltage than that of each of said transistors in said first group, the first group transistors have first gate electrodes formed from a silicon based material layer on a semiconductor substrate... Agent: Sonnenschein Nath & Rosenthal LLP

20090039424 - High-voltage mos transistor device: A high-voltage transistor device has a substrate, an isolation structure, a source, a gate, a drain, a plurality of doped regions, a plurality of ion wells, and a first dielectric layer disposed on the substrate. The high-voltage transistor device further has a first conductive layer and a plurality of first... Agent: North America Intellectual Property Corporation

20090039425 - High-voltage mos transistor device: A HV MOS transistor device having a substrate, a gate, a source, a drain, a first ion well of a first conductive type disposed in the substrate, and a plurality of field plates disposed on the substrate is disclosed. The HV MOS transistor device further has a first doped region... Agent: North America Intellectual Property Corporation

20090039426 - Extremely-thin silicon-on-insulator transistor with raised source/drain: An extremely-thin silicon-on-insulator transistor is provided that includes a buried oxide layer above a substrate, a silicon layer above the buried oxide layer, a gate stack on the silicon layer, a nitride liner on the silicon layer and adjacent to the gate stack, an oxide liner on and adjacent to... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.

20090039427 - Semiconductor device and a method of manufacturing the same: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090039428 - Fabricating method for silicon on insulator and structure thereof: A fabricating method for silicon on insulator is disclosed, and the fabricating method includes stripping the oxide and the nitride on the bottom surface of each of the trenches, forming a porous silicon on portions of the substrate by an anodizing process, spin coating a dielectric material to fill up... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090039429 - Soi mosfet device with reduced polysilicon loading on active area: Silicon-on-insulator (SOI) devices with reduced polysilicon loading on an active area uses at least one dielectric layer resistant to silicidation to separate at least one body contact region from source/drain regions, thus reducing gate capacitance and improving device performance. The SOI devices may be used in full depletion type transistors... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20090039430 - Semiconductor apparatus and method for manufacturing the same: The present invention is to carry out stable doping and to prevent the drastic pressure change in a treatment chamber by reducing degasification of resist during adding impurities. In the present invention, the stability of the impurity ion injection can be ensured by reducing degasification of resist by reducing the... Agent: Eric Robinson

20090039431 - Semiconductor device: Provided is a semiconductor device, including: an N-type MOS transistor for an internal element and a P-type MOS transistor for an internal element both provided in an internal circuit region; and an N-type MOS transistor for ESD protection provided between an external connection terminal and the internal circuit region, in... Agent: Brinks Hofer Gilson & Lione

20090039432 - Semiconductor device: A semiconductor device is provided with Zener diodes which are formed by using a polysilicon gate layer(s) so as to be connected to each other in parallel. Parallel-connected rectangular Zener diodes are formed outside an active region or parallel-connected striped Zener diodes are formed inside the active region. The Zener... Agent: Rossi, Kimms & Mcdowell LLP.

20090039433 - Semiconductor device with high-k/dual metal gate: An apparatus, and method of manufacture thereof, comprising a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first gate electrode having a first metal layer forming a first trench and a second metal layer filling the first trench, wherein the first and second metal... Agent: Haynes And Boone, LLPIPSection

20090039436 - High performance metal gate cmos with high-k gate dielectric: A CMOS structure is disclosed in which both type of FET devices have gate insulators containing high-k dielectrics, and gates containing metals. The threshold of the two type of devices are adjusted in separate manners. One type of device has its threshold set by exposing the high-k dielectric to oxygen.... Agent: Innovation Interface, LLC

20090039439 - Integration scheme for dual work function metal gates: A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate includes having a gate hardmask over the gate electrode layer during the formation of transistor source/drain regions. The method includes an independent work function adjustment process that implants Group IIIa series dopants into a gate polysilicon... Agent: Texas Instruments Incorporated

20090039435 - Low power circuit structure with metal gate and high-k dielectric: FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators, metal containing gates, and threshold adjusting cap layers. The NFET gate stack and the PFET gate stack each has a portion which is identical in the NFET device and in the PFET device. This... Agent: Innovation Interface, LLC

20090039438 - Negative differential resistance pull up element for dram: A memory cell includes a pull-up element that exhibits a refresh behavior that is dependent on the data value stored in the memory cell. The pull-up element is an NDR FET connected between a high voltage source and a storage node of the memory cell. The NDR FET receives a... Agent: Bever, Hoffman & Harms, LLP

20090039437 - Semiconductor device and method for fabricating the same: A semiconductor device includes a first gate electrode formed in a first region on a semiconductor substrate with a first gate insulating film sandwiched therebetween; and a second gate electrode formed in a second region on the semiconductor substrate with a second gate insulating film sandwiched therebetween. The first gate... Agent: Mcdermott Will & Emery LLP

20090039434 - Simple low power circuit structure with metal gate and high-k dielectric: FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators and metal containing gates. The metal layers of the gates in both the NFET and PFET devices have been fabricated from a single common metal layer. Due to the single common metal, device fabrication... Agent: Innovation Interface, LLC

20090039440 - Semiconductor device and method of fabricating the same: A semiconductor device comprising: a semiconductor substrate; an n-type MIS transistor which is formed on the semiconductor substrate and has a first metal gate electrode and a first polycrystalline silicon layer formed on the first metal gate electrode; a p-type MIS transistor which is formed on the semiconductor substrate and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090039441 - Mosfet with metal gate electrode: Devices comprising, and method for fabricating, a MOSFET with a metal gate electrode are disclosed. In one embodiment, the MOSFET includes a first doped region configured to receive current from a current source, a second doped region configured to drain current from the first doped region when an electric field... Agent: Fulbright & Jaworski L.L.P.

20090039442 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the... Agent: Slater & Matsil LLP

20090039443 - Gate structure: A gate structure includes a substrate, a gate dielectric layer, a first conductive layer, a second conductive layer, a cap layer and a first insulating spacer. The gate dielectric layer is disposed on the substrate. The first conductive layer is disposed on the gate dielectric layer and has an opening.... Agent: Jianq Chyun Intellectual Property Office

20090039444 - Semiconductor device and method of fabricating the same: A semiconductor device includes a semiconductor substrate including an upper surface having a first region including a pair of first impurity diffusion regions and a first channel region located between the impurity diffusion regions and a second region including a recess having a predetermined depth relative to the upper surface,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090039445 - Variable width offset spacers for mixed signal and system on chip devices: MOSFET gate structures comprising multiple width offset spacers are provided. A first and a second gate structure are formed on a semiconductor substrate. A pair of first offset spacers are formed adjacent either side of the first gate structure. Each of the first offset spacers comprises a first silicon oxide... Agent: Birch Stewart Kolasch & Birch

20090039446 - Semiconductor device with a high-k gate dielectric and a metal gate electrode: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed on a substrate that applies strain to the high-k gate dielectric layer, and a metal gate electrode that is formed on the high-k gate dielectric layer.... Agent: Intel Corporation C/o Intellevate, LLC

20090039447 - Fet device with stabilized threshold modifying material: A method for fabricating an FET device is disclosed. The FET device has a gate insulator with a high-k dielectric portion, and a threshold modifying material. The method introduces a stabilizing material into the gate insulator in order to hinder one or more metals from the threshold modifying material to... Agent: Innovation Interface, LLC

20090039448 - Thin film transistor, pixel structure and liquid crystal display panel: A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a semi-conductive layer, a gate insulator, a source and a drain. The gate insulator is located between the gate and the semi-conductive layer. A light shows a specific color after passing through the... Agent: Jianq Chyun Intellectual Property Office

20090039449 - Fingerprint sensing device having flexible printed circuit board serving as signal transmission structure and the method of manufacturing the same: A fingerprint sensing device includes a chip substrate, a plurality of first connecting pads and a flexible printed circuit board. The chip substrate has a plurality of fingerprint sensing cells. The first connecting pads are respectively disposed on the fingerprint sensing cells and exposed from a top surface of the... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090039451 - Method for manufacturing a magnetic memory device and magnetic memory device: A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so... Agent: Mcdermott Will & Emery LLP

20090039450 - Structure of magnetic memory cell and magnetic memory device: A structure of magnetic memory cell including a first anti-ferromagnetic layer is provided. A first pinned layer is formed over the first anti-ferromagnetic layer. A tunneling barrier layer is formed over the first pinned layer. A free layer is formed over the tunneling barrier layer. A metal layer is formed... Agent: Jianq Chyun Intellectual Property Office

20090039452 - Embedded bonding pad for image sensors: A semiconductor device includes a semiconductor substrate having a front surface and a back surface, elements formed on the substrate, interconnect metal layers formed over the front surface of the substrate, including a topmost interconnect metal layer, an inter-metal dielectric for insulating each of the plurality of interconnect metal layers,... Agent: Haynes And Boone, LLPIPSection

20090039453 - Semiconductor light receiving device: The present invention provides a semiconductor light receiving device that prevents local heat generation, has high-speed, high-sensitivity characteristics even at the time of an intensive light input, and exhibits high resistance to light inputs. The semiconductor light receiving device includes light absorption layers (3, 4) formed on an InP semiconductor... Agent: Young & Thompson

20090039454 - Solid-state image pickup device and fabrication method thereof: Provided is a solid-state image pickup device capable of suppressing deterioration of characteristic caused due to an antireflection film itself absorbing a light. In the solid-state image pickup device of the present invention, a plurality of color filters 8a, 8b, and 8c having spectral characteristics, respectively, different from each other... Agent: Mcdermott Will & Emery LLP

20090039455 - Image sensor package with trench insulator and fabrication method thereof: The invention provides an image sensor package and a method for fabricating thereof. The package comprises a substrate having an image sensor device electrically connected to a metal layer thereon and a covering plate disposed over the substrate. A plurality of trench insulators is formed in the substrate, whereby the... Agent: Birch Stewart Kolasch & Birch

20090039456 - Structures and methods for forming schottky diodes on a p-substrate or a bottom anode schottky diode: This invention discloses bottom-anode Schottky (BAS) device supported on a semiconductor substrate having a bottom surface functioning as an anode electrode with an epitaxial layer has a same doped conductivity as said anode electrode overlying the anode electrode. The BAS device further includes an Schottky contact metal disposed in a... Agent: Bo-in Lin

20090039457 - Low crosstalk substrate for mixed-signal integrated circuits: An integrated circuit laminate with a metal substrate for use with high performance mixed signal integrated circuit applications. The metal substrate provides substantially improved crosstalk isolation, enhanced heat sinking and an easy access to a true low impedance ground. In one embodiment, the metal layer has regions with insulation filled... Agent: John P. O'banion O'banion & Ritchey LLP

20090039458 - Integrated device: A method of fabricating an integrated device on a substrate with an exposed surface region is disclosed. One embodiment provides introducing a first component into the exposed surface region of the substrate. A material is provided on the exposed surface region. The material on the exposed surface region is cured... Agent: Dicke, Billig & Czaja

20090039459 - Isolation film in semiconductor device and method of forming the same: The present invention relates to an isolation film in a semiconductor device and method of forming the same. An isolation film is formed in a doped region of a peripheral region, in which the doped region is isolated from a deep well region of a cell region and the isolation... Agent: Lowe Hauptman Ham & Berner, LLP

20090039460 - Deep trench isolation structures in integrated semiconductor devices: A integrated semiconductor device has a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type over the first layer, a third semiconductor layer of a second conductivity type over the second layer, an isolation trench extending through the entire depth of the... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090039461 - Formation of improved soi substrates using bulk semiconductor wafers: The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical... Agent: Scully, Scott, Murphy & Presser, P.C.

20090039462 - Efuse devices and efuse arrays thereof and efuse blowing methods: An exemplary embodiment of an efuse device is provided and comprises a plurality of word lines, at least one bit line, a plurality of cells, a plurality of first selection devices, and at least one second selection device. The word lines are interlaced with the bit line. The cells are... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090039463 - Fuse box and method for fabricating the same and method for repairing the same in semiconductor device: A fuse box in a semiconductor device having a fuse line formed in a fuse line region to form a conductive pattern; wherein the conductive pattern has an empty space in the center thereof and a phase change material pattern in the empty space, and an insulation pattern formed over... Agent: Lowe Hauptman Ham & Berner, LLP

20090039464 - Semiconductor device: To protect an internal circuit against ESD breakdown which is caused by exposure of a cut-off portion of a fuse, a separate ESD protection circuit is not provided for each fuse as before, but the internal circuit is efficiently protected by a small number of ESD protection circuits by connecting... Agent: Sughrue Mion, PLLC

20090039465 - On-chip decoupling capacitor structures: The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with a passive capacitor formed in the back-end-of-line wiring to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor and a passive capacitor formed in at least two back-end-of-line... Agent: Ohlandt, Greeley, Ruggiero & Perle, LLP

20090039466 - Semiconductor device and method of manufacturing the same: Effective area of a capacitor is to be increased while suppressing increase in number of manufacturing steps. In a semiconductor device, a silicon substrate includes a plurality of first recessed portions having a first depth from the main surface thereof, a second recessed portion provided in a region other than... Agent: Sughrue Mion, PLLC

20090039467 - On-chip decoupling capacitor structures: The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with planar capacitors to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor, at least one planar capacitor, and a metal layer interconnecting said deep trench and planar capacitors.... Agent: Ohlandt, Greeley, Ruggiero & Perle, LLP

20090039468 - N well implants to separate blocks in a flash memory device: A semiconductor memory device that has an isolated area comprised of one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are comprised of the second conductivity and extend... Agent: Leffert Jay & Polglaze, P.A.

20090039469 - Low temperature impurity doping of silicon carbide: The method described herein enables the introduction of external impurities into Silicon Carbide (SiC) to be conducted at a temperature between 1150-1400° C. Advantages include: a) low temperature diffusion procedure with greater control of the doping process, b) prevent roughness of SiC surface, c) less surface defects and d) better... Agent: Haverstock & Owens LLP

20090039471 - Semiconductor device: A semiconductor device comprising: (a) a semiconductor substrate having a dicing region circumscribing a chip region, the chip region including a central region and a peripheral region around the central region; (b) an active electrical structure formed to extend from a first main surface to a second surface vertically spaced... Agent: Taft, Stettinius & Hollister LLP

20090039470 - Stress relief of a semiconductor device: A semiconductor device includes a die including an active region, a scribe region, and a perimeter, wherein the scribe region is closer to the perimeter than the active region. In one embodiment, the die further comprises a crack arrest structure formed in the scribe region, and wherein the crack arrest... Agent: Freescale Semiconductor, Inc. Law Department

20090039472 - Structure and method for creating reliable deep via connections in a silicon carrier: A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization... Agent: David Aker

20090039473 - Method of manufacturing semiconductor device and semiconductor device: A method of manufacturing a semiconductor device includes steps of forming a semiconductor device layer on an upper surface of a substrate including the upper surface, a lower surface and a dislocation concentrated region arranged so as to part a first side closer to the upper surface and a second... Agent: Ditthavong Mori & Steiner, P.C.

20090039475 - Apparatus and method for manufacturing semiconductor: m

20090039476 - Apparatus and method for selectively recessing spacers on multi-gate devices: Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed.... Agent: Intel Corporation C/o Intellevate, LLC

20090039474 - Formation method of porous insulating film, manufacturing apparatus of semiconductor device, manufacturing method of semiconductor device, and semiconductor device: In a formation method of a porous insulating film by supplying at least organosiloxane and an inert gas to a reaction chamber and forming an insulating film by a plasma vapor deposition method, a partial pressure of the organosiloxane in the reaction chamber is changed by varying a volume ratio... Agent: Mcginn Intellectual Property Law Group, PLLC

20090039478 - Method for utilizing heavily doped silicon feedstock to produce substrates for photovoltaic applications by dopant compensation during crystal growth: A method for using relatively low-cost silicon with low metal impurity concentration by adding a measured amount of dopant and or dopants before and/or during silicon crystal growth so as to nearly balance, or compensate, the p-type and n-type dopants in the crystal, thereby controlling the net doping concentration within... Agent: Holland & Knight LLP Attn: Stefan V. Stein/IPDept.

20090039477 - Silicon nitride substrate, a manufacturing method of the silicon nitride substrate, a silicon nitride wiring board using the silicon nitride substrate, and semiconductor module: In the silicon nitride substrate concerning an embodiment of the invention, degree of in-plane orientation fa of β type silicon nitride is 0.4-0.8. Here, degree of in-plane orientation fa can be determined by the rate of the diffracted X-ray intensity in each lattice plane orientation in β type silicon nitride.... Agent: Akerman Senterfitt

20090039479 - Module for integrating peripheral circuit and a manufacturing method thereof: A module for integrating peripheral circuit includes a silicon chip substrate, at least one peripheral circuit unit, and at least one main circuit unit. The peripheral circuit unit is integrated in the silicon chip substrate via a semiconductor manufacturing process. The main circuit unit is mounted on the surface of... Agent: Rosenberg, Klein & Lee

20090039480 - Semiconductor device and methods of forming the same: The semiconductor device includes a fuse structure disposed on a substrate. An interlayer dielectric disposed on the fuse structure. A first contact plug, a second contact plug, and a third contact plug penetrate the interlayer dielectric and wherein each of the first contact plug, the second contact plug and the... Agent: F. Chau & Associates, LLC

20090039481 - Semiconductor package with a reduced volume and thickness and capable of high speed operation and method for fabricating the same: A semiconductor package includes a semiconductor chip provided with a bonding pad disposed over a surface thereof; a through electrode passing from the surface to a second surface opposing the first surface and connected electrically with the bonding pad; and a redistribution disposed at the second surface and connected electrically... Agent: Ladas & Parry LLP

20090039483 - Heat slug and semiconductor package: A heat slug includes a heat spreading member and a supporting member. The supporting member extends outwardly from the edge of the heat spreading member. The tips of the supporting member are formed with a plurality of contact portions, wherein each said contact portion has a bottom face inclined to... Agent: Lowe Hauptman Ham & Berner, LLP

20090039482 - Package including a microprocessor & fourth level cache: A method, apparatus and system with a package including an integrated circuit disposed between die including a microprocessor and a die including a fourth level cache.... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090039486 - Circuit member, manufacturing method for circuit members, semiconductor device, and surface lamination structure for circuit member: A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as... Agent: Burr & Brown

20090039487 - Semiconductor device: A semiconductor device comprises a source frame having a die pad; a linear gate frame having a bonding pad; a semiconductor chip mounted on the die pad; wires which electrically connect a source terminal of the semiconductor chip to the die pad and electrically connect a gate terminal of the... Agent: Leydig Voit & Mayer, Ltd

20090039484 - Semiconductor device with semiconductor chip and method for producing it: A semiconductor chip has at least one first contact and one second contact on its top side and has connecting elements which are arranged jointly on a structure element and which connect the first contact and the second contact of the top side of the semiconductor chip to the external... Agent: Edell , Shapiro & Finnan , LLC

20090039488 - Semiconductor package and method for fabricating the same: A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier is... Agent: Edwards Angell Palmer & Dodge LLP

20090039485 - Thermally enhanced ball grid array package formed in strip with one-piece die-attached exposed heat spreader: Methods, systems, and apparatuses for integrated circuit packages, such as ball grid array packages, and processes for assembling the same, are provided. A first strip includes an array of package substrate sections. An IC die is mounted to each package substrate section of the first strip. A second strip includes... Agent: Fiala & Weaver, P.l.l.c. C/o Intellevate

20090039489 - method of producing optical mems: A method and apparatus for constructing MEMS devices is provided which employs a low cost molded housing that simultaneously provides precise and accurate alignment, mechanical protection, electrical connections and structural integrity for mounting optical and MEMS components. The package includes a MEMS die mounting surface, an optical component mounting surface... Agent: Seyfarth Shaw LLP

20090039490 - Mounting assembly of semiconductor packages prevent soldering defects caused by substrate warpage: A mounting assembly of semiconductor packages is revealed, primarily comprising at least a semiconductor package having a plurality of external terminals, a package carrier, and solder paste. The solder paste joints the external terminals to the package carrier. According to the distance to a central line on a substrate of... Agent: Joe Mckinney Muncy

20090039493 - Packaging substrate and application thereof: A packaging substrate is disclosed in the present invention, which includes a substrate body having a first surface and an opposite second surface. The first surface has a first cavity, and the second surface has a second cavity. The first cavity corresponds to and is interlinked to the second cavity.... Agent: Bacon & Thomas, PLLC

20090039491 - Semiconductor package having buried post in encapsulant and method of manufacturing the same: In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the... Agent: Marger Johnson & Mccollom, P.C.

20090039492 - Stacked memory device: A semiconductor memory device includes a stacked plurality of interposer chips, each interposer chip seating a smaller corresponding memory chip, wherein a lowermost interposer chip in the stacked plurality of interposer chips is mounted on a buffer chip. Each one of the stacked plurality of interposer chips includes a central... Agent: Volentine & Whitt PLLC

20090039494 - Power semiconductor module with sealing device for sealing to a substrate carrier and method for manufacturing it: A power semiconductor module comprising a housing of a first plastic, at least one substrate carrier with a circuit constructed thereon and electric terminating elements extending therefrom. The housing includes attachment means for its permanent connection with the substrate carrier. The housing has a permanently elastic sealing device of a... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090039495 - Wiring substrate and display device including the same: An active matrix substrate includes a first substrate and a driving integrated circuit chip mounted on the first substrate. A support member is provided between the active matrix substrate and the driving IC chip so as to be in contact with both the active matrix substrate and the driving IC... Agent: Sharp Kabushiki Kaisha C/o Keating & Bennett, LLP

20090039496 - Method for fabricating a semiconductor and semiconductor package: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of... Agent: Dicke, Billig & Czaja

20090039497 - Semiconductor device package having a back side protective scheme: The present invention provides a semiconductor device package, comprising a die having a back surface and an active surface formed thereon; an adhesive layer formed on the back surface of the die; a protection substrate formed on the adhesive layer; and a plurality of bumps formed on the active surface... Agent: Kusner & Jaffe Highland Place Suite 310

20090039498 - Power semiconductor module: A power semiconductor module is disclosed. One embodiment includes a multilayer substrate having a plurality of metal layers and a plurality of ceramic layers, where the ceramic layers are located between the metal layers.... Agent: Dicke, Billig & Czaja

20090039499 - Heat sink with thermally compliant beams: A heat dissipating structure includes: a heat spreader; and a plurality of compliant beams attached to the heat spreader. The beams are formed of a high-conductive material such that a maximum stress of each beam is less than a fatigue stress of the high-conductive material; said beams are placed at... Agent: Michael Buchenhorner, P.A.

20090039500 - Semiconductor package: A semiconductor package includes a base plate having first and second surfaces both facing in opposite directions, and a plurality of anisotropic heat conducting members disposed in the base plate and spaced away from each other. A semiconductor element having a heat generating unit is mounted on the first surface,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090039501 - Integrated circuit with galvanically bonded heat sink: An integrated circuit includes a semiconductor substrate, a first electrical contact formed on the semiconductor substrate, and a first heat sink element bonded to the first electrical contact via a galvanic bond.... Agent: Dicke, Billig & Czaja

20090039502 - Heatsink and semiconductor device with heatsink: A heatsink carries a UV-ray light emitting diode. Flow passages for causing circulation of a fluid that cools the UV-ray light emitting diode are opened in the heatsink. Supply ports and discharge ports are opened in a mount surface of a header where supply and discharge of the fluid for... Agent: Drinker Biddle & Reath (dc)

20090039503 - Semiconductor device: The invention provides a heat radiating structure which reduces a mechanical stress applied to an electronic part mounted on a printed circuit board including a semiconductor package. The heat radiating structure is constructed by a semiconductor package mounted on a printed circuit board, a thermal conduction sheet arranged on an... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090039504 - Semiconductor device: The semiconductor device includes a semiconductor module in which a semiconductor element is sealed with a resin, a reinforcing beam fixed to an upper surface of the semiconductor module via a plate-like spring, and a frame part to which both ends of the reinforcing beam are fixed, the frame part... Agent: Buchanan, Ingersoll & Rooney PC

20090039507 - Electronic element, electronic element device using the same, and manufacturing method thereof: An electronic element including an electronic element base and electrodes each of which has a first electrode having a surface composed of at least Al or an Al alloy and a second electrode composed of a metal nanoparticle sintered body and bonded to the first electrode. A bonding interface between... Agent: Dickstein Shapiro LLP

20090039506 - Semiconductor device including a semiconductor chip which is mounted spaning a plurality of wiring boards and manufacturing method thereof: The semiconductor device is made up of two wiring boards, a semiconductor chip, and a sealing part. The two wiring boards are spaced apart, and a semiconductor chip is mounted so as to span the two wiring boards. The semiconductor chip includes a predetermined circuit and a plurality of electrode... Agent: Young & Thompson

20090039505 - Thermally insulating bonding pad structure for solder reflow connection: A thermally insulating bonding pad for solder reflow is described. The bonding pad includes a structure. The structure forms the bonding pad. The bonding pad further includes an insulator formed on the structure. The insulator is configured to be interposed between the structure and a substrate of a component onto... Agent: Hitachi C/o Wagner Blecher LLP

20090039508 - Larger than die size wafer-level redistribution packaging process: Methods, systems, and apparatuses for integrated circuit packages, and processes for forming the same, are provided. In one example, an integrated circuit (IC) package includes an integrated circuit die, a layer of insulating material, a redistribution interconnect on the layer of insulating material, and a ball interconnect. The integrated circuit... Agent: Fiala & Weaver, P.l.l.c. C/o Intellevate

20090039510 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a semiconductor construct constructed by a semiconductor substrate and a plurality of external connection electrodes provided under the semiconductor substrate. A lower insulating film is provided under and outside the semiconductor construct. A sealing film is provided on the lower insulating film to cover a periphery... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090039509 - Semiconductor device and method of manufacturing the same: A semiconductor device is provided which can prevent contacts between thin metal wires for electrically connecting the electrodes of a substrate with the electrodes of a semiconductor element. The semiconductor device of the present invention includes metal protrusions formed on the electrodes of the semiconductor element, the metal protrusions having... Agent: Steptoe & Johnson LLP

20090039511 - Semiconductor device and method for fabricating the same: A semiconductor device and a method for fabricating the same that includes a drain contact that can prevent bridging between contact metals in metal contact line (M1C) processes. The method includes forming a contact hole extending through an interlayer dielectric film in a space between respective gate electrodes to expose... Agent: Sherr & Vaughn, PLLC

20090039513 - Contacting method for semiconductor material and semiconductor device: A contact-making method for a semiconductor material contains the method steps of forming a diffusion barrier which promotes electrical contact and adhesion on at least one portion of a surface of a semiconductor and forming a metallization on the diffusion barrier. The diffusion barrier being formed by applying a metalliforous... Agent: Lerner Greenberg Stemer LLP

20090039512 - Electromigration resistant interconnect structure: A line trench is formed in a dielectric layer that may contain an interlayer dielectric material. A metal liner is formed on the sidewalls and the bottom surface of the line trench. A conductive metal is deposited within a remaining portion of the line trench at least up to a... Agent: Scully, Scott, Murphy & Presser, P.C.

20090039514 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a semiconductor constituent provided with a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. A lower-layer insulating film is provided under and around the semiconductor constituent. A plurality of lower-layer wirings are electrically connected to the electrodes for external... Agent: Frishauf, Holtz, Goodman & Chick, PC

20090039515 - Ionizing radiation blocking in ic chip to reduce soft errors: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another... Agent: Hoffman Warnick LLC

20090039516 - Power semiconductor component with metal contact layer and production method therefor: A power semiconductor component having a basic body and at least one contact area. At least one first thin metallic layer of a first material is arranged on the contact area. A second metallic layer—thicker than the first—of a second material is arranged on the first material by a pressure... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090039517 - Chemical vapor deposition of titanium: A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second precursor with the seed... Agent: Schwegman, Lundberg & Woessner/micron

20090039518 - Method for forming a damascene structure: A method of forming a damascene structure comprises preparing a film stack on the substrate, wherein the film stack comprises a SiCOH-containing layer formed on the substrate, a silicon oxide (SiOx) layer formed on the SiCOH-containing layer, and a first mask layer formed on the silicon oxide layer. A trench... Agent: Tokyo Electron U.s. Holdings, Inc.

20090039520 - Semiconductor circuit device, wiring method for semiconductor circuit device and data processing system: Via multiplexing technology is provided which can contribute to high density wiring. For coupling wirings of different wiring layers, a multiple via cell section is used which has vias for electrically coupling wirings bent in an L-shape of different wiring layers on both sides with the L-shaped bent portion therebetween.... Agent: Miles & Stockbridge PC

20090039519 - Semiconductor device, photomask, semiconductor device production method, and pattern layout method: A semiconductor device according to an aspect of the invention includes plural line pattern and plural pad patterns. The line patterns are repeatedly disposed with a space pattern interposed therebetween. The pad pattern straddles plural columns of the line patterns. The pad pattern is connected to the line pattern located... Agent: Mcdermott Will & Emery LLP

20090039521 - Semiconductor structure and semiconductor manufacturing method: A semiconductor structure comprising a first signal layer, a second signal layer, a wiring layer and at least one via is provided. The wiring layer is formed between the first signal layer and the second signal layer. A conducting wire is disposed between a first terminal and a second terminal... Agent: Bacon & Thomas, PLLC

20090039522 - Bipolar and cmos integration with reduced contact height: Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating... Agent: International Business Machines Corporation Dept. 18g

20090039525 - Method of welding together at least two stacked members: In this soldering method, a laser is directed onto an end face of the stack in such a manner that the laser heats the stack. At least one parameter of the laser is adjusted to a value that is the image by means of a mathematical model of at least... Agent: Oliff & Berridge, PLC

20090039524 - Methods and apparatus to support an overhanging region of a stacked die: Methods and apparatus to support an overhanging region of stacked die are disclosed. A disclosed method comprises bonding a first die onto a substrate, placing a support element on the substrate; and bonding a second die onto the first die, wherein the second die overhangs at least one edge of... Agent: Texas Instruments Incorporated

20090039526 - Package and the method for making the same, and a stacked package: The present invention relates to a package and the method for making the same, and a stacked package. The method for making the package includes the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms;... Agent: Volentine & Whitt PLLC

20090039523 - Packaged integrated circuit devices with through-body conductive vias, and methods of making same: A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.... Agent: Perkins Coie LLP Patent-sea

20090039527 - Sensor-type package and method for fabricating the same: A sensor-type package and a method for fabricating the same are provided. A wafer having a plurality of semiconductor chips is provided, wherein a plurality of holes are formed on a first surface of each of the semiconductor chips, and a plurality of metallic pillars formed in the holes and... Agent: Edwards Angell Palmer & Dodge LLP

20090039528 - Wafer level stacked packages with individual chip selection: A method is provided for fabricating a stacked microelectronic assembly by steps including stacking and joining first and second like microelectronic substrates, each including a plurality of like microelectronic elements attached together at dicing lanes. Each microelectronic element has boundaries defined by edges including a first edge and a second... Agent: Tessera Lerner David Et Al.

20090039531 - Flip-chip package covered with tape: A manufacturing method of a semiconductor device includes arranging a melted resin on a substrate, arranging a semiconductor chip on the melted resin, pressing the semiconductor chip and flip-chip mounting the semiconductor chip on the substrate, and hardening the melted resin with the melted resin being subjected to a fluid... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090039529 - Integrated circuit having a plurality of connection pads and integrated circuit package: In accordance with an embodiment of the invention, an integrated circuit including a plurality of connection pads is provided, wherein a first connection pad is configured in accordance with a first contacting technology, and wherein a second connection pad is configured in accordance with a second contacting technology. The second... Agent: Slater & Matsil, L.L.P.

20090039530 - Near chip scale package integration process: Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first... Agent: Lowrie, Lando & Anastasi, LLP

20090039533 - Adhesion structure for a package apparatus: A packaging apparatus is disclosed having a substrate with an interior area and a peripheral area. The substrate is configured to have an integrated circuit chip bonded to an adhesion structure located substantially within the interior area of the substrate. The substrate is further configured to have the integrated circuit... Agent: Schneck & Schneck

20090039532 - Semiconductor device package having a back side protective scheme: The present invention provides a semiconductor device package, comprising a die having a back surface and an active surface formed thereon; an adhesive layer formed on the back surface of the die; a protection substrate formed on the adhesive layer; and a plurality of bumps formed on the active surface... Agent: Kusner & Jaffe Highland Place Suite 310

20090032794 - Phase change memory device and fabrication method thereof: A phase change memory device is disclosed. A first dielectric layer having a sidewall is provided. A bottom electrode is adjacent to the sidewall of the first dielectric layer, wherein the bottom electrode comprises a seed layer and a conductive layer. A second dielectric layer is adjacent to a side... Agent: Quintero Law Office, PC

20090032793 - Resistor random access memory structure having a defined small area of electrical contact: A memory cell device, of the type that includes a memory material switchable between electrical property states by application of energy, includes first and second electrodes, a plug of memory material (such as phase change material) which is in electrical contact with the second electrode, and an electrically conductive film... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090032795 - Schottky diode and memory device including the same: A Schottky diode and a memory device including the same are provided. The Schottky diode includes a first metal layer and an Nb-oxide layer formed on the first metal layer.... Agent: Harness, Dickey & Pierce, P.L.C

20090032796 - Phase change memory bridge cell: Memory devices are described along with manufacturing methods. An embodiment of a memory device as described herein includes a conductive bit line and a plurality of first electrodes. The memory device includes a plurality of insulating members, the insulating members having a thickness between a corresponding first electrode and a... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090032797 - Photocathode: When to-be-detected light is made incident from a support substrate 2 side of a photocathode E1, a light absorbing layer 3 absorbs this to-be-detected light and produces photoelectrons. However, depending on the thickness and the like of the light absorbing layer 3, the to-be-detected light can be transmitted through the... Agent: Drinker Biddle & Reath (dc)

20090032799 - Light emitting device: A light emitting device includes a substrate having a first surface and a second surface not parallel to the first surface, and a light emission layer disposed over the second surface to emit light. The light emission layer has a light emission surface which is not parallel to the first... Agent: Perkins Coie LLP

20090032798 - Light emitting diode (led): A light-emitting diode (LED) includes a p-type layer, an n-type layer, and an active layer arranged between the p-type layer and the n-type layer. The active layer includes at least one quantum well adjacent to at least one modulation-doped layer. Alternatively, or in addition thereto, at least one surface of... Agent: Hewlett Packard Company

20090032800 - Photonic crystal light emitting device: There is provided a photonic crystal light emitting device including: a substrate; a plurality of nano rod light emitting structures formed on the substrate to be spaced apart from one another, each of the nano rod light emitting structures including a first conductivity type semiconductor layer, an active layer and... Agent: Mcdermott Will & Emery LLP

20090032801 - Approach to contacting nanowire arrays using nanoparticles: An in situ approach toward connecting and electrically contacting vertically aligned nanowire arrays using conductive nanoparticles is provided. The utility of the approach is demonstrated by development of a gas sensing device employing the nanowire assembly. Well-aligned, single-crystalline zinc oxide nanowires were grown through a direct thermal evaporation process at... Agent: Carter, Deluca, Farrell & Schmidt, LLP

20090032802 - Mosfet device featuring a superlattice barrier layer and method: A method of forming a semiconductor structure comprises forming a channel layer; forming a superlattice barrier layer overlying the channel layer, and forming a gate dielectric overlying the superlattice barrier layer. The superlattice barrier layer includes a plurality of alternating first and second layers of barrier material. In addition, the... Agent: Freescale Semiconductor, Inc. Law Department

20090032803 - Method and apparatus for fabricating a carbon nanotube transistor: A method of fabricating a nanotube field-effect transistor having unipolar characteristics and a small inverse sub-threshold slope includes forming a local gate electrode beneath the nanotube between drain and source electrodes of the transistor and doping portions of the nanotube. In a further embodiment, the method includes forming at least... Agent: Moser, Patterson & Sheridan, LLP Suite 100

20090032804 - Self-aligned t-gate carbon nanotube field effect transistor devices and method for forming the same: A method is provided for forming a self-aligned carbon nanotube (CNT) field effect transistor (FET). According to one feature, a self-aligned source-gate-drain (S-G-D) structure is formed that allows for the shrinking of the gate length to arbitrarily small values, thereby enabling ultra-high performance CNT FETs. In accordance with another feature,... Agent: Medtronic, Inc.

20090032805 - Microresonator systems and methods of fabricating the same: Various embodiments of the present invention are related to microresonator systems that can be used as a laser, a modulator, and a photodetector and to methods for fabricating the microresonator systems. In one embodiment, a microresonator system comprises a substrate having a top surface layer, at least one waveguide embedded... Agent: Hewlett Packard Company

20090032808 - Enhancing performance characteristics of organic semiconducting films by improved solution processing: Improved processing methods for enhanced properties of conjugated polymer films are disclosed, as well as the enhanced conjugated polymer films produced thereby. Addition of low molecular weight alkyl-containing molecules to solutions used to form conjugated polymer films leads to improved photoconductivity and improvements in other electronic properties. The enhanced conjugated... Agent: Morrison & Foerster LLP

20090032811 - Functionalization of poly(arylene-vinylene) polymers for electronic devices: A method is provided for modifying a poly(arylene vinylene) or poly(heteroarylene vinylene) precursor polymer having dithiocarbamate moieties by reacting it with an acid and further optionally reacting the acid-modified polymer with a nucleophillic agent. Also provided are novel polymers and copolymers bearing nucleophillic side groups which are useful as components... Agent: Knobbe Martens Olson & Bear LLP

20090032807 - Method of manufacturing semiconductor element, semiconductor element, electronic device, and electronic equipment: The object of the present invention is to provide a method of manufacturing a semiconductor element which can produce a semiconductor element provided with a semiconductor layer having a high carrier transport ability, a semiconductor element manufactured by the semiconductor element manufacturing method, an electronic device provided with the semiconductor... Agent: Oliff & Berridge, PLC

20090032809 - Organic thin film transistor and method of manufacturing the same: Disclosed are an organic thin film transistor and a method of manufacturing the same, in which a crystalline organic binder layer is on the surface of an organic insulating layer and source/drain electrodes or on the surface of the source/drain electrodes. The organic thin film transistor may be improved in... Agent: Harness, Dickey & Pierce, P.L.C

20090032810 - Organic transistor and active-matrix substrate: An organic transistor includes a gate electrode having a predetermined length, source and drain electrodes overlapping the gate electrode in plan view, a channel region formed of the organic semiconductor between the source and drain electrodes, and a functional portion disposed on a first side of the gate electrode in... Agent: Harness, Dickey & Pierce, P.L.C

20090032806 - Polymer composite p-n junction and method for manufacturing same and polymer composite diode incorporating same: The present polymer composite p-n junction includes an n-type polymer composite layer and a p-type polymer composite layer. The n-type composite polymer layer includes a first polymer material and a number of electrically conductive particles imbedded therein. The p-type composite polymer layer includes a second polymer material and a number... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang

20090032812 - Microelectronic device: A microelectronic device includes a thin film transistor having an oxide semiconductor channel and an organic polymer passivation layer formed on the oxide semiconductor channel.... Agent: Hewlett Packard Company

20090032813 - Test wafer, manufacturing method thereof and method for measuring plasma damage: Embodiments of the present invention provide a test wafer capable of analyzing plasma damage, a manufacturing method thereof, and a method for measuring plasma damage using the same. A test wafer according to an embodiment includes a transistor device having at least one probe contact and a gate insulating film... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090032814 - Sige diac esd protection structure: A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of... Agent: Law Offices Of Mark C. Pickering

20090032817 - Back-to-back metal/semiconductor/metal (msm) schottky diode: A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20090032816 - Pixel well electrode: Various apparatus and methods relating to pixel wells and electrodes that are at least partially concurrently formed are disclosed.... Agent: Hewlett Packard Company

20090032815 - Pixel well electrodes: A multi-level mandrel is used to locate an electrode in a pixel well. A display includes an electrode recessed in a floor of a pixel well.... Agent: Hewlett Packard Company

20090032818 - Thin film transistor array panel and liquid crystal display including the panel: A gate wire including a gate line and a gate electrode is formed on an insulating substrate of a TFT array panel. A semiconductor pattern made of amorphous silicon is formed on the gate insulating layer covering the gate wire. A data wire including a data line, a source electrode,... Agent: F. Chau & Associates, LLC

20090032819 - Array substrate for liquid crystal display device and method of fabricating the same: An array substrate for a liquid crystal display device, including: a substrate; a gate line on the substrate; a data line crossing the gate line to define a pixel region; a thin film transistor connected to the gate line and the data line, the thin film transistor including a gate... Agent: Holland & Knight LLP

20090032820 - Reliable normally-off iii-nitride active device structures, and related methods and systems: A field-effect transistor includes a first gate, a second gate held at a substantially fixed potential in a cascode configuration, and a semiconductor channel. The semiconductor channel has an enhancement mode portion and a depletion mode portion. The enhancement mode portion is gated to be turned on and off by... Agent: Groover & Associates

20090032821 - Semiconductor device and electrical circuit device using thereof: A UMOSFET is capable of reducing a threshold voltage and producing a large saturation current. A typical UMOSFET according to the present invention includes: an N+ type SiC substrate constituting a drain layer; an N− type SiC layer that is in contact with the drain layer and constitutes a drift... Agent: Miles & Stockbridge PC

20090032822 - high power light emitting diode: A high power light emitting diode, The high power light emitting diode comprises a light emitting diode chip, a main module, two first electrode pins, two second electrode pins, and at least one heat dissipation board. The main module has a concave and the light emitting diode chip is positioned... Agent: Pai Patent & Trademark Law Firm

20090032823 - Photo sensor and light emitting display having the same: A photo sensor includes a light incidence unit including a plurality of light incidence layers, the light incidence unit having a varying light transmittance with respect to external light, and a photo sensing unit including a plurality of photo sensing elements, the photo sensing unit being configured to output electrical... Agent: Lee & Morse, P.C.

20090032824 - Image displaying device: An image displaying device having multiple photosensing devices have successfully suppressed a leakage current from each photosensing device and improved the S/N ratio. In the image displaying device, pixels and photosensing devices are disposed as pairs in a matrix pattern on a substrate. Each of the pixels and each of... Agent: Stanley P. Fisher Reed Smith LLP

20090032826 - Multi-chip light emitting diode package: A multi-chip light emitting diode (LED) package having a plurality of LED chips, a substrate, and a plurality of conductive paste layers is provided. The substrate has at least two hollow areas with conductive patterns formed on a bottom surface thereon. The conductive paste layers are pasted on the bottom... Agent: Birch Stewart Kolasch & Birch

20090032825 - Structure of led-based display module and method for manufacturing the same: The display module contains a circuit board, a heat-resistant and transparent protective layer, and a transparent and waterproofing enclosing member. The circuit board has a number of LED devices configured on the front surface and at least a terminal on the back surface. The LED devices are electrically and signally... Agent: Lin & Associates Intellectual Property, Inc.

20090032827 - Concave wide emitting lens for led useful for backlighting: Lenses for LEDs are described that efficiently create a substantially uniform light emission across a surface of a backlight box. The backlight may illuminate an LCD. A wide-emitting lens refracts light emitted by an LED die to cause a peak intensity to occur within 35-65 degrees off the die's center... Agent: Patent Law Group LLP

20090032828 - Iii-nitride device grown on edge-dislocation template: A semiconductor light emitting device includes a wurtzite III-nitride semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A template layer and a dislocation bending layer are grown before the light emitting layer. The template layer is grown such that at least 70%... Agent: Patent Law Group LLP

20090032829 - Led light source with increased thermal conductivity: A light source and method for making the same are disclosed. The light source includes a substrate, a plurality of dies and a transparent layer of encapsulant. The substrate includes an insulating layer having top and bottom surfaces, the top surface having a first metal patterned layer thereon, and the... Agent: Kathy Manke Avago Technologies Limited

20090032830 - Light emitting diode and manufacturing method thereof: A light-emitting diode and the manufacturing method thereof are disclosed. The manufacturing method comprises the steps of: sequentially forming a refraction dielectric layer, a bonding layer, an epitaxy structure and a first electrode on a permanent substrate, wherein the epitaxy structure comprises a first conductivity type semiconductor layer, an active... Agent: Pai Patent & Trademark Law Firm

20090032832 - Light emitting diode structure: A light emitting diode structure has a silicon substrate, a conductive layer, and a light emitting diode. The top surface of the silicon substrate has a cup-structure like paraboloid, and the bottom of the cup-structure has a plurality of through-holes penetrating the silicon substrate. The conductive layer fills up the... Agent: North America Intellectual Property Corporation

20090032831 - Optical waveguide apparatus and method for manufacturing the same: An optical waveguide apparatus having a very simple structure that can modulate a signal light guided through an optical waveguide is provided. A photoresist 13 is applied to an upper side of an SOI film 12, a photoresist mask 14 is formed, and the SOI film in a region that... Agent: Oliff & Berridge, PLC

20090032834 - Highly efficient led with microcolumn array emitting surface: A highly efficient light emitting diode with microcolumn array emitting surface, wherein the microcolumn array is prepared on the emitting surface of the light emitting diode, and can be formed with a two-dimensional periodic or non-periodic structure, the length and height of each microcolumn are in the same order of... Agent: Matthias Scholl

20090032835 - Iii-nitride semiconductor light emitting device: The present disclosure provides a III-nitride semiconductor light emitting device, including: a plurality of III-nitride semiconductor layers including an active layer for generating light by recombination of electrons and holes; and a substrate used to grow the plurality of III-nitride semiconductor layers, and including a protrusion with two opposite sides... Agent: Harness, Dickey, & Pierce, P.l.c

20090032833 - Light emitting diode having algan buffer layer and method of fabricating the same: The present invention relates to a light emitting diode having an AlxGa1-xN buffer layer and a method of fabricating the same, and more particularly, to a light emitting diode having an AlxGa1-xN buffer layer, wherein between a substrate and a GaN-based semiconductor layer, the Al x Ga 1-x N (O≦x≦1)... Agent: H.c. Park & Associates, PLC

20090032836 - Semiconductor light emitting diode that uses silicon nano dot and method of manufacturing the same: Provided is a semiconductor light emitting diode that uses a silicon nano dot and a method of manufacturing the same. The semiconductor light emitting diode includes a light emitting layer that emits light; a hole injection layer formed on the light emitting layer; an electron injection layer formed on the... Agent: Rabin & Berdo, PC

20090032837 - Asymmetric bidirectional silicon-controlled rectifier: The present invention discloses an asymmetric bidirectional silicon-controlled rectifier, which comprises: a second conduction type substrate; a first conduction type undoped epitaxial layer formed on the substrate; a first well and a second well both formed inside the undoped epitaxial layer and separated by a portion of the undoped epitaxial... Agent: Sinorica, LLC

20090032839 - Semiconductor device and its driving method: A semiconductor device having a thyristor SCR with reduced turn-off time. A third semiconductor region of the second conductivity type (anode AN) and a fourth semiconductor region of the first conductivity type (anode gate AG) are formed in the top layer of a first semiconductor region; fifth semiconductor region of... Agent: Texas Instruments Incorporated

20090032838 - Symmetric bidirectional silicon-controlled rectifier: The present invention discloses a symmetric bidirectional silicon-controlled rectifier, which comprises: a substrate; a buried layer formed on the substrate; a first well, a middle region and a second well, which are sequentially formed on the buried layer side-by-side; a first semiconductor area and a second semiconductor area both formed... Agent: Sinorica, LLC

20090032842 - Nanomembrane structures having mixed crystalline orientations and compositions: The present nanomembrane structures include a multilayer film comprising a single-crystalline layer of semiconductor material disposed between two other single-crystalline layers of semiconductor material. A plurality of holes extending through the nanomembrane are at least partially, and preferably entirely, filled with a filler material which is also a semiconductor, but... Agent: Wisconsin Alumni Research Foundation (warf)

20090032843 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a semiconductor substrate, and a MIS type FET provided on the semiconductor substrate, the MIS type FET includes a gate insulating film provide on the semiconductor substrate, a gate electrode provided on the gate insulating film, a channel region provided in the semiconductor substrate and being... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090032840 - Semiconductor device and method of manufacture: A semiconductor device and method of manufacture and, more particularly, a semiconductor device having strain films and a method of manufacture. The device includes an embedded SiGeC layer in source and drain regions of an NFET device and an embedded SiGe layer in source and drain regions of a PFET... Agent: Greenblum & Bernstein, P.L.C

20090032844 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device has forming a transistor including a source and a drain, forming a mixed crystal layer over the source and the drain, forming a silicide layer over the mixed crystal layer, forming a first insulating film and a second insulating film over the silicide... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090032841 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor... Agent: Slater & Matsil LLP

20090032845 - Soi field effect transistor having asymmetric junction leakage: A source trench and a drain trench are asymmetrically formed in a top semiconductor layer comprising a first semiconductor in a semiconductor substrate. A second semiconductor material having a narrower band gap than the first semiconductor material is deposited in the source trench and the drain trench to form a... Agent: Scully, Scott, Murphy & Presser, P.C.

20090032846 - Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device: A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Relatively long signal lines are... Agent: Synopsys, Inc./bstz Blakely Sokoloff Taylor & Zafman LLP

20090032847 - Semiconductor wafer and manufacturing method for semiconductor device: A semiconductor wafer and a manufacturing method for a semiconductor device are provided, which prevent peeling-off of films and pattern skipping in a wafer edge portion. A silicone substrate has formed thereon gate structures in active regions isolated by a trench isolation film; a contact interlayer film; and a multilayer... Agent: Mcdermott Will & Emery LLP

20090032848 - Semiconductor device and method for forming same: A method for manufacturing a semiconductor device. The method includes providing a semiconductor body of a conductivity type, wherein the semiconductor body comprises a first surface. At least one buried region of a second conductivity type is formed in the semiconductor body and at least a surface region of the... Agent: Dickstein Shapiro LLP

20090032849 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device includes a cylindrical main pillar that is formed on a substrate and of which a central axis is perpendicular to the surface of the substrate, source and drain diffused layers that are formed in a concentric shape centered on the central axis at upper and lower portions... Agent: Scully Scott Murphy & Presser, PC

20090032851 - Method for producing a semiconductor body having a recombination zone, semiconductor component having a recombination zone, and method for producing such a semiconductor component: In a method for producing a semiconductor body, impurities which act as recombination centers in the semiconductor body and form a recombination zone are introduced into the semiconductor body during the process of producing the semiconductor body. In a semiconductor component, comprising a semiconductor body having a front surface and... Agent: Infineon Technologies Ag Patent Department

20090032850 - N-channel mos transistor fabricated using a reduced cost cmos process: An NMOS transistor includes a semiconductor substrate of a first conductivity type, first and second well regions of a second conductivity type formed spaced apart in the substrate, a conductive gate formed over the region between the spaced apart first and second well regions where the region of the substrate... Agent: Patent Law Group LLP

20090032852 - Cmos image sensor: A CMOS (Complementary Metal-Oxide Semiconductor) image sensor is provided. A CMOS image sensor includes a first light-receiving unit converting light into charge, a first floating diffusion region, in which a first potential corresponding to the converted amount of charge is generated and a second floating diffusion region, to which the... Agent: Staas & Halsey LLP

20090032853 - Cmos image sensors and methods of fabricating the same: CMOS image sensors and methods of fabricating the same. The CMOS image sensors include a pixel array region having an active pixel portion and an optical block pixel portion which encloses the active pixel portion. The optical block pixel portion includes an optical block metal pattern for blocking light. The... Agent: Harness, Dickey & Pierce, P.L.C

20090032854 - Image sensor and sensor unit: This image sensor is so formed as to control at least either the potential of a portion of a transfer channel corresponding to a third electrode or the potential of another portion of the transfer channel corresponding to a fourth electrode to be lower than the potentials of portions of... Agent: Ditthavong Mori & Steiner, P.C.

20090032855 - Method for forming a deep trench in an soi device by reducing the shielding effect of the active layer during the deep trench etch process: By providing a conductive connection between the active semiconductor layer and the substrate material in an SOI device during the anisotropic etch process for forming a deep trench portion in the substrate material, the uniformity of the etch conditions may be increased, thereby enabling greater etch depth and enhanced controllability... Agent: Williams, Morgan & Amerson

20090032856 - Memory device and manufacturing method thereof: A manufacturing method of a volatile memory device is provided. The manufacturing method includes steps as follows. A sacrificial layer is formed in an area which is predetermined for forming a metal gate. Then, a thermal treatment process or other high temperature processes are performed in a peripheral circuit region.... Agent: Jianq Chyun Intellectual Property Office

20090032857 - Semiconductor device manufacturing method and semiconductor device: A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090032858 - Layout and structure of memory: A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the space between the gate conductor lines, which are for... Agent: North America Intellectual Property Corporation

20090032859 - Finfet flash memory device with an extended floating back gate: A floating gate is formed on one side of the semiconductor fin on a floating gate dielectric. A control gate dielectric is formed on the opposite side of the semiconductor fin and on the floating gate. A gate conductor is formed on the control gate dielectric across the semiconductor fin.... Agent: Scully, Scott, Murphy & Presser, P.C.

20090032860 - Programmable memory, programmable memory cell and the manufacturing method thereof: A programmable memory structure includes a substrate, an active area, a common-source and a common-drain respectively disposed on each side of the active area, a first and a second source contact electrically connected to the common-source, a first and a second drain contact electrically connected to the common-drain, and between... Agent: North America Intellectual Property Corporation

20090032863 - Nitridation oxidation of tunneling layer for improved sonos speed and retention: A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than... Agent: Cypress/blakely Blakely Sokoloff Taylor & Zafman LLP

20090032862 - Non-volatile memory cell and non-volatile memory device using said cell: A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two... Agent: Empk & Shiloh, LLP C/o Landon Ip, Inc.

20090032861 - Nonvolatile memories with charge trapping layers containing silicon nitride with germanium or phosphorus: A nonvolatile memory has a charge trapping layer which includes a layer (130) made of silicon nitride doped with germanium or phosphorus (210). The germanium or phosphorus contains a large percentage of scattered, non-crystallized atoms uniformly distributed in the silicon nitride layer to increase the charge trapping density.... Agent: Macpherson Kwok Chen & Heid LLP

20090032864 - Self-aligned charge storage region formation for semiconductor device: Devices and methods for forming self-aligned charge storage regions are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a layer of a nitride film stacked between two oxide films on a semiconductor substrate, and forming a gate electrode on the layer of the nitride film... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090032865 - Semiconductor component and method for producing it: A semiconductor component having differently structured cell regions, and a method for producing it. For this purpose, the semiconductor component includes a semiconductor body. A first electrode on the top side of the semiconductor body is electrically connected to a first zone near the surface of the semiconductor body. A... Agent: Dicke, Billig & Czaja

20090032866 - Methods of fabricating dual fin structures and semiconductor device structures with dual fin structures: Fin-FET devices and methods of fabrication are disclosed. The Fin-FET devices include dual fins that may be used to provide a trench region between a source region and a drain region. In some embodiments, the dual fins may be formed by forming a trench with fin structures on opposite sides... Agent: Trask Britt, P.C./ Micron Technology

20090032867 - Dmos type semiconductor device and method for manufacturing the same: A DMOS type semiconductor device and a method for manufacturing the same are provided. An isolation oxide layer with an ion implantation opening is formed on a semiconductor. A gate oxide film is formed on the semiconductor within the ion implantation opening. A gate is formed on the isolation oxide... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20090032868 - High performance power mos structure: A semiconductor device includes a source region and a drain region disposed in a substrate wherein the source and drain regions have a first type of dopant; a gate electrode formed on the substrate interposed laterally between the source and drain regions; a gate spacer disposed on the substrate and... Agent: Haynes And Boone, LLPIPSection

20090032869 - Semiconductor device and method of manufacturing the same: A semiconductor device is provided, which comprises a first transistor and a second transistor formed in a semiconductor layer. The first transistor includes a first source region and a first drain region sandwiching a first gate electrode with the first source region. The second transistor includes an LDD region and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090032870 - Semiconductor device and method for manufacturing same: A semiconductor device comprising a field effect transistor having higher breakdown voltage by reducing electric field concentration between the drain region and a gate electrode is provided. A semiconductor device includes, on a silicon substrate, an n-well source region and an n-well drain region, which are formed over a surface... Agent: Mcginn Intellectual Property Law Group, PLLC

20090032871 - Integrated circuit with interconnected frontside contact and backside contact: An integrated circuit includes a substrate including an active area, a first metal contact contacting a frontside of the active area, a second metal contact contacting a backside of the active area, and a wafer-level deposited metal structure positioned adjacent to an edge of the active area and interconnecting the... Agent: Dicke, Billig & Czaja

20090032872 - Multiple oxide thickness for a semiconductor device: Techniques associated with providing multiple gate insulator thickness for a semiconductor device are generally described. In one example, an apparatus includes a semiconductor fin having an impurity introduced to at least a first side of the fin, a first oxide having a first thickness coupled with the first side of... Agent: Cool Patent, P.C. C/o Intellevate

20090032873 - Ultra thin single crystalline semiconductor tft and process for making same: Methods and apparatus for producing a semiconductor on glass (SiOG) structure include: subjecting an implantation surface of a donor single crystal semiconductor wafer to an ion implantation process to create an exfoliation layer of the donor semiconductor wafer; bonding the implantation surface of the exfoliation layer to a glass substrate... Agent: Corning Incorporated

20090032874 - Method for integrating silicon-on-nothing devices with standard cmos devices: A method is provided for fabricating transistors of first and second types in a single substrate. First and second active zones of the substrate are delimited by lateral isolation trench regions, and a portion of the second active zone is removed so that the second active zone is below the... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.

20090032876 - Esd protection for bipolar-cmos-dmos integrated circuit devices: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells... Agent: Patentability Associates

20090032875 - Semiconductor device: There is provided a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the first conductivity type; a semiconductor region of the first conductivity type selectively provided on a front surface... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090032877 - Method of enhancing drive current in a transistor: A method of manufacturing a semiconductor device includes forming transistors including gate electrodes and source/drain regions over a substrate. A protective layer is placed over the source/drain regions and the gate electrodes. A portion of the protective layer is removed to expose a portion of the gate electrodes. The exposed... Agent: Texas Instruments Incorporated

20090032879 - Nitride-based semiconductor device: A nitride-based semiconductor device includes a diode provided on a semiconductor substrate. The diode contains a first nitride-based semiconductor layer made of non-doped AlXGa1−XN (0≦X<1); a second nitride-based semiconductor layer made of non-doped or n-type AlYGa1−YN (0<Y≦1, X<Y) having a lattice constant smaller than that of the first nitride-based semiconductor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090032878 - Semiconductor device and fabrication method thereof: A semiconductor device comprises a first gate electrode formed on a first region of a semiconductor substrate, a first impurity layer formed at least below both ends of the first gate electrode in the first region, a first side wall formed on both side surfaces of the first gate electrode,... Agent: Mcdermott Will & Emery LLP

20090032880 - Method and apparatus for tunable isotropic recess etching of silicon materials: Methods and apparatuses to etch recesses in a silicon substrate having an isotropic character to undercut a transistor in preparation for a source/drain regrowth. In one embodiment, a cap layer of a first thickness is deposited over a transistor gate stack and spacer structure. The cap layer is then selectively... Agent: Applied Materials/bstz Blakely Sokoloff Taylor & Zafman LLP

20090032883 - Semiconductor device: Disclosed is a semiconductor device which comprises one or more metal-insulator-semiconductor field effect transistors (MISFETs), each including: a gate insulating film composed of a silicon oxide film, a first hafnium-containing nitrided silicate film, and a second hafnium-containing nitrided silicate film which are sequentially deposited on a substrate; and a gate... Agent: Young & Thompson

20090032882 - Semiconductor device having insulated gate field effect transistors and method of manufacturing the same: N-type semiconductor region and P-type semiconductor region are provided in a surface region of a semiconductor substrate. Insulating film and silicon containing film are laminated on the semiconductor substrate. P-type impurities are introduced into a first portion of the silicon containing film above the N-type semiconductor region. The first portion... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090032884 - Semiconductor device, and method for manufacturing the same: According to an aspect of the invention, a semiconductor device comprises: a N-channel MIS transistor comprising; a p-type semiconductor layer; a first gate insulation layer formed on the p-type semiconductor layer; a first gate electrode formed on the first gate insulation layer; and a first source-drain region formed in the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090032881 - Semiconductor devices and methods of fabricating the same in which a mobility change of the major carrier is induced through stress applied to the channel: A semiconductor device includes a semiconductor substrate, a gate structure formed on the semiconductor substrate, wherein the gate structure includes a gate electrode formed on the semiconductor substrate and spacers formed on sidewalls of the gate electrode, source/drain regions formed in the semiconductor substrate on both sides of the gate... Agent: Myers Bigel Sibley & Sajovec

20090032885 - Buried isolation layer: The present disclosed integrated circuit includes a substrate having a top surface, a buried N type layer in the substrate, N type contact region extending from the surface to the buried N type region, a buried P type region abutting and above the buried N type region in the substrate,... Agent: Barnes & Thornburg LLP

20090032886 - Semiconductor transistors having reduced distances between gate electrode regions: A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) first and second semiconductor body regions.... Agent: Schmeiser, Olsen & Watts

20090032887 - Transistor having gate electrode with controlled work function and memory device having the same: A transistor includes a gate insulation layer over a substrate, a gate line comprising electrodes each having a different work function on the gate insulation layer, and a source junction and a drain junction formed inside portions of the substrate on first and second sides of the gate line.... Agent: Townsend And Townsend And Crew, LLP

20090032888 - Semiconductor device: A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is... Agent: Larson Newman Abel & Polansky, LLP

20090032889 - Field effect transistor having an asymmetric gate electrode: The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the channel. In one embodiment, the source side gate electrode comprises a silicon oxide based gate dielectric and... Agent: Scully, Scott, Murphy & Presser, P.C.

20090032890 - Multilayer dielectric: An apparatus and method relating to a first inorganic dielectric layer having a first concentration of defects and a second inorganic dielectric layer in contact with a first layer and having a second lesser concentration of defects are disclosed.... Agent: Hewlett Packard Company

20090032891 - Structure of magnetic random access memory and fabrication method thereof: A structure of magnetic random access memory includes a magnetic memory cell formed on a substrate. An insulating layer covers over the substrate and the magnetic memory cell. A write current line is in the insulating layer and above the magnetic memory cell. A magnetic cladding layer surrounds the periphery... Agent: Jianq Chyun Intellectual Property Office

20090032892 - Image tft array of a direct x-ray image sensor and method of fabricating the same: A method of fabricating an image TFT array of a direct X-ray image sensor includes forming a first transparent conductive layer on a substrate; forming a gate line including a gate electrode, a common line, and a common electrode jutting out from the common line; forming an insulation layer; forming... Agent: North America Intellectual Property Corporation

20090032894 - Flip-chip photodiode: A photodiode is provided according to various embodiments. In some embodiments, the photodiode includes a substrate and an active region. The active region is configured to receive light through the substrate. In such a configuration, the substrate not only participates in the photodiode operation acts as a light filter depending... Agent: Townsend And Townsend And Crew, LLP

20090032895 - Image sensor and method for manufacturing the same: An image sensor and a method for manufacturing the same are provided. The image sensor comprises at least one unit pixel, an interlayer dielectric, a color filter, a planarization layer, and a microlens. The microlens has a smooth surface after performing a plasma treatment process.... Agent: Kyung Min Park

20090032893 - Image sensor package and fabrication method thereof: An image sensor package and method for fabricating the same is provided. The image sensor package includes a first substrate comprising a via hole therein, a driving circuit and a first conductive pad thereon. A second substrate comprising a photosensitive device and a second conductive pad thereon is bonded to... Agent: Joe Mckinney Muncy

20090032896 - Optical semiconductor device: An optical semiconductor device includes a phototransistor for receiving incident light. The phototransistor includes a collector layer of a first conductivity type formed on a semiconductor substrate, a base layer of a second conductivity type formed on the collector layer, and an emitter layer of a first conductivity type formed... Agent: Mcdermott Will & Emery LLP

20090032897 - Semiconductor device and method for its manufacture: In semiconductor devices and methods for their manufacture, the semiconductor devices are arranged as a trench-Schottky-barrier-Schottky diode having a pn diode as a clamping element (TSBS-pn), and having additional properties compared to usual TSBS elements which make possible adaptation of the electrical properties. The TSBS-pn diodes are produced using special... Agent: Kenyon & Kenyon LLP

20090032899 - Integrated circuit design based on scan design technology: An integrated circuit is provided with a scan chain including a scan flip-flop and a dummy block. The dummy block has a clock terminal receiving a clock signal, a scan input terminal connected to a scan data line within the scan chain, and a scan output terminal connected to another... Agent: Mcginn Intellectual Property Law Group, PLLC

20090032898 - Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same: A method is disclosed for defining a dynamic array section to be manufactured on a semiconductor chip. The method includes defining a peripheral boundary of the dynamic array section. The method also includes defining a manufacturing assurance halo outside the boundary of the dynamic array section. The method further includes... Agent: Martine Penilla & Gencarella, LLP

20090032901 - Method of curing hydrogen silsesquioxane and densification in nano-scale trenches: Trenches in a semiconductor substrate are filled by (i) dispensing a film forming material on the semiconductor substrate and into the trenches; (ii) curing the dispensed film forming material in the presence of an oxidant at a first low temperature for a first predetermined period of time; (iii) curing the... Agent: Dow Corning Corporation Co1232

20090032900 - Method of protecting shallow trench isolation structure and composite structure resulting from the same: A method of protecting a shallow trench isolation structure is described, which is applied to a semiconductor device process that includes a first process causing a recess in the STI structure and a second process after the first process. The method includes forming a silicon nitride layer in the recess... Agent: J C Patents, Inc.

20090032903 - Multiple voltage integrated circuit and design method therefor: An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20090032902 - Semiconductor devices and methods for manufacturing the same: Semiconductor devices and methods for manufacturing the same are disclosed. An example method includes loading a first substrate to be provided with an oxynitride layer along with a second substrate having a nitride layer in a boat, and forming the oxynitride layer on the first substrate by placing the boat... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090032905 - Electronic devices including electrode walls with insulating layers thereon: An electronic device may include a substrate and a plurality of conductive electrodes on the substrate. Each of the conductive electrodes may have a respective electrode wall extending away from the substrate, and an electrode wall of at least one of the conductive electrodes may include a recessed portion. In... Agent: Myers Bigel Sibley & Sajovec

20090032904 - Orientation-independent multi-layer beol capacitor: A plurality of interdigitized conductive fingers are arranged to form a substantially square configuration in each of a plurality of layers separated by a high dielectric constant material, wherein each of the plurality of interdigitized conductive fingers includes at least one bend of substantially ninety degrees. The plurality of interdigitized... Agent: Cantor Colburn LLP - IBM Fishkill

20090032906 - Electro static discharge device and method for manufacturing an electro static discharge device: An electro static discharge device includes a semiconductor body. The semiconductor body includes a first surface, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type arranged on the first semiconductor region and a third semiconductor region of the first conductivity type.... Agent: Dickstein Shapiro LLP

20090032907 - Method for producing gaxin1-xn(0<x>) crystal gaxin1-xn(0<x<1) crystalline substrate, method for producing gan crystal, gan crystalline substrate, and product: Disclosed herein is a method for producing a GaxIn1-xN (0≦x≦1) crystal (12) by growing GaxIn1-xN (0≦x≦1) crystal (12) on the surface of a base substrate (7) by the reaction of a material gas, containing ammonia gas and at least one of a gallium halide gas and an indium halide gas,... Agent: Mcdermott Will & Emery LLP

20090032908 - Semiconductor device and method of manufacturing it: A method of manufacturing a semiconductor device capable of largely increasing the yield and a semiconductor device manufactured by using the method is provided. After a semiconductor layer is formed on a substrate, as one group, a plurality of functional portions with at least one parameter value different from each... Agent: Rader Fishman & Grauer PLLC

20090032910 - Dielectric stack containing lanthanum and hafnium: Dielectric layers containing a dielectric layer including lanthanum and hafnium and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a wide range of electronic devices.... Agent: Schwegman, Lundberg & Woessner/micron

20090032909 - Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners: Structures and a method for forming the same. The structure includes a semiconductor substrate, a transistor on the semiconductor substrate, and N interconnect layers on top of the semiconductor substrate, N being a positive integer. The transistor is electrically coupled to the N interconnect layers. The structure further includes a... Agent: Schmeiser, Olsen & Watts

20090032911 - Patterned thin soi: A process for treating a structure to prepare it for electronics or optoelectronics applications. The structure includes a bulk substrate, an oxide layer, and a semiconductor layer, and the process includes providing a masking to define on the semiconductor layer a desired pattern, and applying a thermal treatment for removing... Agent: Winston & Strawn LLP Patent Department

20090032912 - Semiconductor component with buffer layer: A semiconductor component having at least one pn junction and an associated production method. The semiconductor component has a layer sequence of a first zone having a first dopant. The first zone faces a first main area. Adjacent to the first zone are a second zone having a low concentration... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090032913 - Component and assemblies with ends offset downwardly: A stackable microelectronic component includes a dielectric layer having an attachment portion. The dielectric layer has a first side, a second side, and outer ends lying outwardly of the attachment portion. The outer ends are offset from the attachment portion. A semiconductor chip is assembled to the second side of... Agent: Tessera Lerner David Et Al.

20090032914 - Three-dimensional package module, method of fabricating the same, and method of fabricating passive device applied to the three-dimensional package module: Provided is a three-dimensional aluminum package module including: an aluminum substrate; an aluminum oxide layer formed on the aluminum substrate and having at least one first opening of which sidewalls are perpendicular to an upper surface of the aluminum substrate; a semiconductor device mounted in the first opening using an... Agent: Sheridan Ross PC

20090032916 - Semiconductor package apparatus: A semiconductor package apparatus and a method of fabricating the semiconductor package apparatus. The semiconductor package apparatus includes: semiconductor chips comprising active and inactive surfaces and protected by a packing portion; a substrate on which the semiconductor chips are installed; leads comprising front portions electrically coupled to the active surfaces... Agent: Marger Johnson & Mccollom, P.C.

20090032915 - Tfcc (tm) & swcc (tm) thermal flex contact carriers: Two groups of interconnection devices and methods are described. Both provide columns between electronic packages and boards or between chips and substrates or the like. In the first group, called Thermal Flex Contact Carrier (TFCC), the column elements are carved out of a flat laminated structure and then formed to... Agent: Gabe Cherian

20090032917 - Lead frame package apparatus and method: The present disclosure relates to a lead frame package comprising a die attach pad and two or more electrical interconnections, wherein at least one of the two or more interconnections is affixed to the die attach pad for electrically grounding the lead frame package. The present disclosure further relates to... Agent: Tyco Electronics Corporation

20090032918 - Integrated circuit package system with multiple devices: An integrated circuit package system includes: forming a die-attach paddle, an outer interconnect, and an inner interconnect toward the die-attach paddle beyond the outer interconnect; mounting an integrated circuit device over the die-attach paddle; connecting the integrated circuit device to the inner interconnect and the outer interconnect; encapsulating the integrated... Agent: Law Offices Of Mikio Ishimaru

20090032920 - Laser release process for very thin si-carrier build: A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.... Agent: Connolly Bove Lodge & Hutz LLP

20090032923 - Method and apparatus for stacking electrical components using via to provide interconnection: An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on... Agent: Kenton R. Mullins Stout, Uxa, Buyan & Mullins LLP

20090032921 - Printed wiring board structure and electronic apparatus: According to one embodiment, a printed wiring board structure includes first and second semiconductor packages each including a substrate, and a printed wiring board including first and second component mounting surfaces having a relationship given as front and back surfaces and an inter-chip connection part provided at one portion thereof,... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090032919 - Semiconductor device and lead frame: A semiconductor device which can surely prevent a wire bonded to an island from breaking due to, for instance, thermal shock and temperature cycle upon mounting. The semiconductor device includes a semiconductor chip; an island die bonded with the semiconductor chip on the surface; and a wire for electrically connecting... Agent: Rabin & Berdo, PC

20090032922 - Semiconductor package, printed wiring board structure and electronic apparatus: According to one embodiment, a semiconductor package comprises a substrate having one surface mounted with a semiconductor chip, and the other surface mounted with a plurality of arrayed external connection electrodes, a differential line pair provided on the surface of the substrate mounted with the semiconductor chip, and making a... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090032924 - Hermetically sealed package with window: A method for manufacturing a cover assembly including a transparent window portion and a frame of gas-impervious material that can be hermetically attached to a micro-device package base to form a hermetically sealed micro-device package. First a frame of gas-impervious material is provided the frame having a continuous sidewall defining... Agent: Howison & Arnott, L.l.p

20090032925 - Packaging with a connection structure: In a package including an image sensor die with an interconnect extending therethrough, a cover allowing light to pass is coupled to the die using at least one solder ball and a corresponding number of pads on each of the cover and die. Such pads are added to the cover... Agent: Charles B. Brantley Mail Stop 1-525

20090032926 - Integrated support structure for stacked semiconductors with overhang: The present disclosure relates to an integrated circuit packaging, a strip having a plurality of integrated circuit packages, and method of manufacture thereof, and more particularly, to a substrate having an integrated overhang support structure to support a ledge created by stacking a large circuit die on a small circuit... Agent: Advanced Micro Devices, Inc. C/o Vedder Price P.C.

20090032928 - Multi-chip stack structure having through silicon via and method for fabrication the same: The invention discloses a multi-chip stack structure having through silicon via and a method for fabricating the same. The method includes: providing a wafer having a plurality of first chips; forming a plurality of holes on a first surface of each of the first chips and forming metal posts and... Agent: Edwards Angell Palmer & Dodge LLP

20090032927 - Semiconductor substrates connected with a ball grid array: A stacked module has an upper semiconductor package that includes a substrate having opposed first and second surfaces. A cavity defined in the second surface receives at least a portion of a semiconductor mounted on the substrate of a lower semiconductor package. A plurality of solder bumps disposed between the... Agent: Marger Johnson & Mccollom, P.C.

20090032930 - Packaging substrate having chip embedded therein and manufacturing method thereof: A packaging substrate having a chip embedded therein, comprises a first aluminum substrate having a first cavity therein; a second aluminum substrate having a second cavity corresponding to the first cavity; a dielectric layer disposed between the first aluminum substrate and the second aluminum substrate; a chip embedded in the... Agent: Lowe Hauptman Ham & Berner, LLP

20090032929 - Semiconductor chips with reduced stress from underfill at edge of chip: Structures and methods for forming the same. A semiconductor chip includes a semiconductor substrate and a transistor on the semiconductor substrate. The chip further includes N interconnect layers on top of the semiconductor substrate and being electrically coupled to the transistor, N being a positive integer. The chip further includes... Agent: Schmeiser, Olsen & Watts

20090032931 - Power semiconductor module with connecting devices: A power semiconductor module having a housing with first connecting devices for arrangement on an external cooling component, at least one substrate carrier with power-electronics circuit arrangements constructed thereon and electrical terminal elements extending therefrom to second connecting devices for connection to external power lines, wherein the first and/or the... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090032932 - Integrated circuit packaging system for fine pitch substrates: An integrated circuit packaging system comprising: forming a substrate including; patterning a bonding pad on the substrate, patterning a first signal trace coupled to the bonding pad, patterning a second signal trace on the substrate, and connecting a pedestal on the second signal trace; mounting an integrated circuit on the... Agent: Law Offices Of Mikio Ishimaru

20090032933 - Redistributed chip packaging with thermal contact to device backside: Redistributed Chip Packaging with Thermal Contact to Device Backside An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the... Agent: Fsi C/o Jackson Walker, LLP

20090032934 - Potential-free housing leadthrough: The invention relates to a circuit arrangement with an electronic circuit on a printed circuit board and an electrically screening housing surrounding the circuit board, wherein there are on said circuit board a HF plug-and-socket connector connected to the electronic circuit with an outer conductor part and an inner conductor... Agent: Law Office Of Delio & Peterson, LLC.

20090032935 - Semiconductor device: Embodiments of a semiconductor device are disclosed.... Agent: Hewlett Packard Company

20090032937 - Cooling systems for power semiconductor devices: A cooling device is provided for liquid cooling a power semiconductor device. The device includes a coolant diverter for guiding liquid coolant to the power semiconductor device. The coolant diverter has a first plate for dividing the coolant diverter into a first cavity and a second cavity. The second cavity... Agent: Ingrassia Fisher & Lorenz, P.C. (gm)

20090032936 - Semiconductor device, method for the same, and heat radiator: A semiconductor device includes a semiconductor chip, and a multicomponent alloy layer formed on a face of the semiconductor chip, the multicomponent alloy layer being in a solid-liquid coexisting state in a specific temperature range, and including a surface having concavity and convexity caused by solidification segregation.... Agent: Harness, Dickey & Pierce, P.L.C

20090032938 - Electronic package with direct cooling of active electronic components: A cooling assembly includes a package with one or more dies cooled by direct cooling. The cooled package includes one or more dies with active electronic components. A coolant port allows a coolant to enter the package and directly cool the active electronic components of the dies.... Agent: N. Kenneth Burraston Kirton & Mcconkie

20090032940 - Conductor bump method and apparatus: Various semiconductor die conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a conductor pad of a semiconductor die. The conductor layer has a surface. A polymeric layer is formed on the surface... Agent: Timothy M Honeycutt Attorney At Law

20090032944 - Electronic device, method of producing the same, and semiconductor device: A semiconductor device includes n1 first interconnects (n is an integer larger than one) respectively formed on first electrodes and extending over a first resin protrusion, and n2 second interconnects (n2<n1) respectively formed on second electrodes and extending over a second resin protrusion. The first and second resin protrusions are... Agent: Harness, Dickey & Pierce, P.L.C

20090032939 - Method of forming a stud bump over passivation, and related device: A method of forming a stud bump over passivation, and related device. At least some of the illustrative embodiments are methods comprising depositing a first passivation layer over a semiconductor die, depositing a capping metal layer over the first passivation layer (the capping metal layer comprises a capping metal pad),... Agent: Texas Instruments Incorporated

20090032942 - Semiconductor chip with solder bump and method of fabricating the same: A semiconductor chip having a solder bump and a method of fabricating the same are provided. The semiconductor chip includes at least one under bump metal (UBM) layer formed on an electrode pad of the semiconductor chip, an adhesion enhance layer (AEL) formed on the UBM layer and having at... Agent: Marger Johnson & Mccollom, P.C.

20090032945 - Solder bump on a semiconductor substrate: A solder bump on a semiconductor substrate is provided. The solder bump has a semiconductor substrate with a top copper pad thereon, a protective layer on the semiconductor substrate and at least one inorganic passivation layer overlying the protective layer with a first opening exposing the top copper pad, wherein... Agent: Joe Mckinney Muncy

20090032943 - Substrate, substrate fabrication, semiconductor device, and semiconductor device fabrication: A substrate for fixing an integrated circuit (IC) element comprises: a substrate for fixing an integrated circuit element includes: a plurality of metal posts that are aligned in a longitudinal direction and a lateral direction in plan view, each of the plurality of metal posts having a first surface and... Agent: Oliff & Berridge, PLC

20090032941 - Under bump routing layer method and apparatus: Various semiconductor chip conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a semiconductor chip. The conductor structure has a first site electrically connected to a first redistribution layer structure and a second... Agent: Timothy M Honeycutt Attorney At Law

20090032946 - Integrated circuit: Integrated circuits and methods for making integrated circuits having a base layer, a side substrate, a circuit substrate and a connection. A bottom face of the base layer is disposed on the side substrate. The side substrate includes a first contact field, at least a second contact field, and a... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090032948 - Semiconductor chip package and method for designing the same: A semiconductor chip package is disclosed. The semiconductor chip package comprises a package substrate having a bottom surface. At least four adjacent ball pads are on the bottom surface, arranged in a first two-row array along a first direction and a second direction. At least four vias are drilled through... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090032947 - Semiconductor device and method of manufacturing: A semiconductor device has a semiconductor die having at least one bond pad formed on a first surface thereof. A substrate has at least one bond finger formed on a first surface thereof. A second surface of the semiconductor die is attached to the first surface of the substrate. A... Agent: Weiss & Moy PC

20090032949 - Method of depositing tungsten using plasma-treated tungsten nitride: Devices structures utilizing, and methods of forming, tungsten interconnects in semiconductor fabrication are disclosed. Tungsten deposition is accomplished by a three-step process that does not require a resistive nucleation material to be deposited prior to bulk tungsten deposition. By treating a tungsten nitride material with a hydrogen plasma, thereby reducing... Agent: Micron Technology, Inc.

20090032950 - Film forming method, semiconductor device manufacturing method, semiconductor device, program and recording medium: An adhesion between a Cu diffusion barrier film and a Cu wiring in a semiconductor device is improved and reliability of the semiconductor device is improved. A film forming method for forming a Cu film on a substrate to be processed is provided with a first process of forming an... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090032953 - Semiconductor device and method of manufacturing the same: A semiconductor device is described includes a wiring layer, an insulating layer stacked on the wiring layer, a trench formed by digging down the insulating layer from the surface thereof, a film-shaped lower electrode formed along the inner surface of the trench, a capacitor film formed along the surface of... Agent: Rabin & Berdo, PC

20090032951 - Small area, robust silicon via structure and process: A semiconductor structure includes: at least one silicon surface wherein the surface can be a substrate, wafer or other device. The structure further includes at least one electronic circuit formed on each side of the at least one surface; and at least one conductive high aspect ratio through silicon via... Agent: Michael Buchenhorner, P.A.

20090032952 - Tantalum amido-complexes with chelate ligands useful for cvd and ald of tan and ta205 thin films: Tantalum compounds of Formula I hereof are disclosed, having utility as precursors for forming tantalum-containing films such as barrier layers. The tantalum compounds of Formula I may be deposited by CVD or ALD for forming semiconductor device structures including a dielectric layer, a barrier layer on the dielectric layer, and... Agent: Intellectual Property / Technology Law

20090032954 - Semiconductor device and method of fabricating the same: A semiconductor device includes a first insulation film having a plurality of openings which exposes predetermined regions of a semiconductor substrate, a plurality of first conductive patterns partially filling the openings and a plurality of second conductive patterns disposed on the first conductive patterns within the openings and separated from... Agent: F. Chau & Associates, LLC

20090032956 - Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics: A semiconductor structure including a first rigid dielectric layer and a second rigid dielectric layer. A first non-rigid low-k dielectric layer is formed between the first and second rigid dielectric layer. A plurality of dummy fill shapes is formed in the first non-rigid layer which replace portions of the first... Agent: Greenblum & Bernstein, P.L.C

20090032955 - Semiconductor device, its manufacturing method and display apparatus: A semiconductor device including n, where notation n denotes a positive integer at least equal to three, conductive layers created as stacked layers on a substrate and connected to each other through a contact pattern, a manufacturing method thereof and a display apparatus thereof are provided.... Agent: Bell, Boyd & Lloyd, LLP

20090032957 - Semiconductor device and method of manufacturing the semiconductor device: A semiconductor device includes a lower structure, an insulation layer, metal contacts, a bridge and a metal pad. The lower structure has a metal wiring. An insulation layer is formed on the lower structure. The metal contacts penetrate the insulation layer to be connected to the metal wiring. The bridge... Agent: Marger Johnson & Mccollom, P.C.

20090032958 - Intermetallic conductors: Intermetallic conductive materials are used to form interconnects in an integrated circuit. In some cases, the intermetallic conductive material may be an intermetallic alloy of aluminum.... Agent: Mueting, Raasch & Gebhardt, P.A.

20090032962 - Centrifugal method for filing high aspect ratio blind micro vias with powdered materials for circuit formation: The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.... Agent: Connolly Bove Lodge & Hutz LLP

20090032959 - Electrical fuses and resistors having sublithographic dimensions: Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator... Agent: Scully, Scott, Murphy & Presser, P.C.

20090032961 - Semiconductor device having a locally enhanced electromigration resistance in an interconnect structure: By forming an alloy in a highly localized manner at a transition or contact area between a via and a metal line, the probability of forming an electromigration-induced shallow void may be significantly reduced, while not unduly affecting the overall electrical resistivity of the metal line. In one illustrative embodiment,... Agent: Williams, Morgan & Amerson

20090032960 - Semiconductor devices and methods of manufacturing semiconductor devices: Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end... Agent: Perkins Coie LLP Patent-sea

20090032966 - Method of fabricating a 3-d device and device made thereby: A method of fabricating a semiconductor device includes providing a semiconductor substrate having an active surface, thinning the substrate by removing material from a second surface of the substrate opposite the active surface, bonding a metal carrier to the second surface of the thinned substrate, forming a via opening in... Agent: Lee & Morse, P.C.

20090032963 - Semiconductor structures including tight pitch contacts and methods to form same: Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines... Agent: Trask Britt, P.C./ Micron Technology

20090032965 - Seminconductor device having p-n column portion: A semiconductor device includes: a first semiconductor layer; a p-n column portion over the first semiconductor layer and including second and third semiconductor layers, which are alternately arranged; and a peripheral portion adjacently to the p-n column portion and including a fourth semiconductor layer. An end second semiconductor layer has... Agent: Posz Law Group, PLC

20090032964 - System and method for providing semiconductor device features using a protective layer: Present embodiments relate to systems and methods for providing semiconductor device features using a protective layer during coating operations. One embodiment includes a method comprising providing a substrate with a hole formed partially therethrough, the hole comprising an opening in a first side of the substrate. Additionally, the method comprises... Agent: Fletcher Yoder (micron Technology, Inc.)

20090032967 - Semiconductor device with dynamic array section: A semiconductor chip is provided to include one or more distinct but functionally interfaced dynamic array sections. Each dynamic array section follows a dynamic array architecture that requires conductive features to be linearly defined along a virtual grate in each of a plurality of levels of the semiconductor chip. Each... Agent: Martine Penilla & Gencarella, LLP

20090032968 - Via configurable architecture for customization of analog circuitry in a semiconductor device: A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include... Agent: Womble Carlyle Sandridge & Rice, PLLC

20090032969 - Arrangement of integrated circuit dice and method for fabricating same: An arrangement of integrated circuit dice, includes first die including a first electrical coupling site and a second die comprising a second electrical coupling site, wherein the second die is stacked onto the first die such that the first electrical coupling site is at least partially exposed, wherein the first... Agent: Slater & Matsil, L.L.P.

20090032971 - Die stacking apparatus and method: Various stacked semiconductor devices and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor die that has a first bulk semiconductor side and a first opposite side. A second semiconductor die is provided that has a second... Agent: Timothy M Honeycutt Attorney At Law

20090032972 - Semiconductor device: A stacked-type semiconductor device includes a plurality of semiconductor elements stacked on a wiring board. Electrode pads of these semiconductor elements are electrically connected to connection pads of the wiring board via metal wires respectively. The long-looped metal wires connected to the upper semiconductor element are fixed by a wire... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090032973 - Semiconductor stack package having wiring extension part which has hole for wiring: A semiconductor stack package includes a first printed wiring board; a plurality of semiconductor chips stacked on the first printed wiring board, wherein among the semiconductor chips, the uppermost semiconductor chip has an electrode pad for providing power supply, a ground pad for providing grounding, and a signal pad for... Agent: Mcginn Intellectual Property Law Group, PLLC

20090032970 - Stacking of integrated circuits using glassy metal bonding: Techniques associated with stacking integrated circuits using glassy metal bonding are generally described. In one example, an apparatus includes a first integrated circuit having one or more bonding pads and a second integrated circuit having one or more bonding pads, the second integrated circuit being electrically and mechanically coupled with... Agent: Cool Patent, P.C. C/o Intellevate

20090032974 - Method and structure to reduce cracking in flip chip underfill: A method of assembling a microelectronic flip-chip arrangement includes attaching a chip having a defined length to a supporting substrate, wherein the chip forms a chip shadow line of the defined length on the supporting substrate, creating a first non-wettable zone on an outer portion of the bottom surface of... Agent: Cantor Colburn LLP - IBM Fishkill

20090032975 - Semiconductor device and method of providing common voltage bus and wire bondable redistribution: A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer... Agent: Quarles & Brady LLP

20090032977 - Semiconductor device: The present invention is disclosed a semiconductor device which enables to easily perform a visual inspection of the bonded state between a lead and a land of wiring board. This semiconductor device comprises a lead in which at least a part of the lower surface thereof is exposed form the... Agent: Rabin & Berdo, PC

20090032976 - Semiconductor device manufacturing method: Provided are a semiconductor device producing method making production steps therein simple while preventing a matter that wire bonding cannot be attained due to contamination of a bonding pad and preventing the generation of a warp in an adherend such as a substrate, a lead frame, or a semiconductor element,... Agent: Knobbe Martens Olson & Bear LLP

20090032978 - Microelectronic structure including dual damascene structure and high contrast alignment mark: A microelectronic structure, and in particular a semiconductor structure, includes a substrate and a dielectric layer located over the substrate. In addition at least one alignment mark is located interposed between the dielectric layer and the substrate. The at least one alignment mark comprises, or preferably consists essentially of, at... Agent: Scully, Scott, Murphy & Presser, P.C.

20090032979 - Semiconductor device having alignment mark and its manufacturing method: Many holes are formed in an interlayer insulating film and the surface of the interlayer insulating film is covered with a metal film, with its surface undulated by openings or recesses formed to scatter reflection light. The size of the recesses is about the size of contact holes of elements.... Agent: Rossi, Kimms & Mcdowell LLP.