Active solid-state devices (e.g., transistors, solid-state diodes) inventions 12/08

20080315170 - Quantum coherent switch utilizing commensurate nanoelectrode and charge density periodicities: A quantum coherent switch having a substrate formed from a density wave (DW) material capable of having a periodic electron density modulation or spin density modulation, a dielectric layer formed onto a surface of the substrate that is orthogonal to an intrinsic wave vector of the DW material; and structure... Agent: Los Alamos National Security, LLC

20080315173 - Integrated circuit having multilayer electrode: An integrated circuit includes a contact and a first electrode coupled to the contact. The first electrode includes at least two electrode material layers. The at least two electrode material layers include different materials. The integrated circuit includes a second electrode and a resistivity changing material between the first electrode... Agent: Dicke, Billig & Czaja

20080315171 - Integrated circuit including vertical diode: An integrated circuit includes a diode including a first polarity region and a second polarity region. The second polarity region contacts a bottom and sidewalls of the first polarity region. The integrated circuit includes a first electrode coupled to the diode, a second electrode, and resistivity changing material between the... Agent: Dicke, Billig & Czaja

20080315172 - Integrated circuit including vertical diode: An integrated circuit includes a vertical diode defined by crossed line lithography.... Agent: Dicke, Billig & Czaja

20080315174 - Variable resistance non-volatile memory cells and methods of fabricating same: Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming a cup-shaped electrode on sidewalls of an opening in an insulation layer and through the opening on an ohmic layer that is stacked on a conductive... Agent: Myers Bigel Sibley & Sajovec

20080315175 - Alignment, transportation and integration of nanowires using optical trapping: Individually trapping, transferring, and assembling high-aspect-ratio semiconductor nanowires into arbitrary structures in a fluid environment. Nanowires with diameters as small as 20 nm and aspect ratios of above 100 can be trapped and transported in three dimensions, enabling the construction of nanowire architectures which may function as active photonic devices.... Agent: John P. O'banion O'banion & Ritchey LLP

20080315177 - Light emission using quantum dot emitters in a photonic crystal: Devices and methods of manufacturing; for emitting substantially white light using a photonic crystal are described. The photonic crystal has a lattice of air holes and is made from a substrate containing quantum dots. The substrate is etched with three defects that are optically coupled together so that each emits... Agent: Wilmerhale/columbia University

20080315176 - Light-emitting diode and method for fabrication thereof: A light-emitting diode includes a substrate, a compound semiconductor layer including a p-n junction-type light-emitting part formed on the substrate, an electric conductor disposed on the compound semiconductor layer and formed of an electrically conductive material optically transparent to the light emitted from the light-emitting part and a high resistance... Agent: Sughrue Mion, PLLC

20080315178 - Semiconductor light emitting device: A semiconductor light emitting device is provided. The semiconductor light emitting device comprises: a first conductive semiconductor layer; an active layer on the first conductive semiconductor layer; a first quantum dot layer on the active layer; and a second conductive semiconductor layer on the first quantum dot layer.... Agent: Birch Stewart Kolasch & Birch

20080315179 - Semiconductor light emitting device: Provided is a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer. The active layer comprises a first active layer, a second active layer, an electron barrier layer on the first conductive type... Agent: Birch Stewart Kolasch & Birch

20080315180 - Semiconductor light emitting device: Provided is a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer. The active layer comprises a quantum barrier layer and a quantum well layer on the first conductive type semiconductor layer. An... Agent: Birch Stewart Kolasch & Birch

20080315181 - Nanotube schottky diodes for high-frequency applications: Described is a Schottky diode using semi-conducting single-walled nanotubes (s-SWNTs) with titanium Schottky and platinum Ohmic contacts for high-frequency applications. The diodes are fabricated using angled evaporation of dissimilar metal contacts over an s-SWNT. The devices demonstrate rectifying behavior with large reverse-bias breakdown voltages of greater than −15 V. In... Agent: Tope-mckay & Associates

20080315182 - Optical semiconductor device and method for manufacturing the same: There is provided an optical semiconductor device having a first optical semiconductor element including an InP substrate, a lower cladding layer formed on the InP substrate, a lower optical guide layer which is formed on the lower cladding layer and is composed of AlGaInAs, an active layer which is formed... Agent: Staas & Halsey LLP

20080315183 - Semiconductor device with carbon nanotube channel and manufacturing method thereof: A high-performance semiconductor device having a channel region structured from a carbon nanotube (CNT) for reducing or minimizing a drain leakage current is provided. This semiconductor device includes, in addition to the CNT-formed channel region, a gate electrode formed to overlie the channel region with a gate insulation film sandwiched... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080315184 - Switching element: A switching element comprising: an insulative substrate; a first electrode and a second electrode provided on one surface of the insulative substrate; and an interelectrode gap which is provided between the first electrode and the second electrode, and which has a gap on the order of nanometers in which switching... Agent: Crowell & Moring LLP Intellectual Property Group

20080315188 - Apparatus and method for depositing thin film: In a thin film depositing apparatus, a first reaction gas, a second reaction gas, and a non-volatile gas are supplied to a reaction chamber in order to form a protective layer, in which an organic layer and an inorganic layer are alternately stacked, on a process substrate. The first reaction... Agent: Macpherson Kwok Chen & Heid LLP

20080315187 - Enhancing performance characteristics of organic semiconducting films by improved solution processing: Improved processing methods for enhanced properties of conjugated polymer films are disclosed, as well as the enhanced conjugated polymer films produced thereby. Addition of low molecular weight alkyl-containing molecules to solutions used to form conjugated polymer films leads to improved photoconductivity and improvements in other electronic properties. The enhanced conjugated... Agent: Morrison & Foerster LLP

20080315192 - Integrated circuit comprising an organic semiconductor, and method for the production of an integrated circuit: An embodiment of the invention provides an integrated circuit having an organic field effect transistor (OFET) with a dielectric layer. The dielectric layer is prepared from a polymer formulation comprising: about 100 parts of at least one crosslinkable base polymer, from about 10 to about 20 parts of at least... Agent: Slater & Matsil LLP

20080315189 - Organic light emitting diode display device and method of fabricating the same: An organic light emitting diode (OLED) display device and a method of fabricating the same capable of minimizing the number of process operations and a decrease in aperture ratio. The OLED display device includes a compensation circuit to compensate for a threshold voltage of a driving transistor. A pixel circuit... Agent: Stein, Mcewen & Bui, LLP

20080315186 - Organic semiconductor device and organic semiconductor thin film: An organic semiconductor device includes a channel forming region including an organic semiconductor thin film which is composed of an organic semiconductor material having an oxidation or reduction mechanism in units of two-π-electrons and a two- or three-dimensional conduction path. It is thus possible to provide an organic semiconductor device... Agent: Bell, Boyd & Lloyd, LLP

20080315190 - Organic thin film transistor and method for surface modification of gate insulating layer of organic thin film transistor: This invention provides an organic thin film transistor, which can realize the modification of the surface of a gate insulating layer not only the case where the gate insulating layer is formed of an oxide, but also the case where the gate insulating layer is formed of a material other... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20080315191 - Organic thin film transistor array and method of manufacturing the same: An n-type TFT and a p-type TFT are realized by selectively changing only a cover coat without changing a TFT material using an equation for applying the magnitude of a difference in the Fermi energy between an interface of semiconductor and an electrode and between an interface of semiconductor and... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080315185 - Photodetector: A photodetector comprising: at least one electron transporting organic material; and at least one hole transporting material, wherein said at least one electron transporting organic material has an ionization potential of more than 5.5 eV.... Agent: Sughrue-265550

20080315194 - Oxide semiconductors and thin film transistors comprising the same: Oxide semiconductors and thin film transistors (TFTs) including the same are provided. An oxide semiconductor includes Zn atoms and at least one of Ta and Y atoms added thereto. A thin film transistor (TFT) includes a channel including an oxide semiconductor including Zn atoms and at least one of Ta... Agent: Harness, Dickey & Pierce, P.L.C

20080315193 - Oxide-based thin film transistor, method of fabricating the same, zinc oxide etchant, and a method of forming the same: Provided is a zinc (Zn) oxide-based thin film transistor that may include a gate, a gate insulating layer on the gate, a channel including zinc oxide and may be on a portion of the gate insulating layer, and a source and drain contacting respective sides of the channel. The zinc... Agent: Harness, Dickey & Pierce, P.L.C

20080315195 - Method and apparatus for monitoring via's in a semiconductor fab: A method for monitoring a semiconductor fabrication process creates a wafer of semiconductor chips. Each chip has a one or more diodes. Each diode is addressable as part of an array, corresponds to a physical location of the chip, and is connected in series to a stack. The stack is... Agent: Baker Botts L.L.P. Patent Department

20080315196 - Technique for evaluating a fabrication of a die and wafer: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known... Agent: Shemwell Mahamedi LLP

20080315197 - Semiconductor apparatus: A semiconductor apparatus includes: a substrate of single crystal silicon; a first device formed in a first region of a surface of the substrate; a first interlayer insulating film formed on the substrate; a polycrystalline silicon layer formed in a second region on the first interlayer insulating film; a second... Agent: Amin, Turocy & Calvin, LLP

20080315198 - Image sensor and method for manufacturing the same: An image sensor and a manufacturing method thereof are provided. The sensor includes a substrate, a bottom electrode, an intrinsic layer and a first conductive layer formed over the substrate, a diffusion barrier film formed over the first conductive layer, and an upper transparent electrode formed over the diffusion barrier... Agent: Sherr & Vaughn, PLLC

20080315200 - Oxide semiconductors and thin film transistors comprising the same: Oxide semiconductors and thin film transistors (TFTs) including the same are provided. An oxide semiconductor includes Zn atoms and at least one of Hf and Cr atoms added thereto. A thin film transistor (TFT) includes a channel including an oxide semiconductor including Zn atoms and at least one of Hf... Agent: Harness, Dickey & Pierce, P.L.C

20080315199 - Thin film transistor manufacturing method, thin film transistor and display device using the same: A thin film transistor manufacturing method includes the steps of: forming a gate electrode, gate insulating film and amorphous silicon film in succession on an insulating substrate; forming a channel protective film only in the region which will serve as a channel region of the amorphous silicon film; and forming... Agent: Sonnenschein Nath & Rosenthal LLP

20080315201 - Apparatus for producing electronic device such as display device, method of producing electronic device such as display device, and electronic device such as display device: An object of the present invention is to reduce an adverse effect of an atmosphere in a heat treatment device used in production of an electronic device, imparted on characteristics of the produced electronic device. To attain the object, an inner surface of the heat treatment device is covered with... Agent: Foley And Lardner LLP Suite 500

20080315202 - Display device: A resin material having a small relative dielectric constant is used as a layer insulation film 114. The resin material has a flat surface. A black matrix or masking film for thin film transistors is formed thereon using a metal material. Such a configuration prevents the problem of a capacity... Agent: Fish & Richardson P.C.

20080315205 - Display device and manufacturing method thereof: In the present invention, a wiring including Cu is provided as an electrode or a wiring used for the display device represented by the EL display device and the liquid crystal display device. Besides, sputtering is performed with a mask to form the wiring including Cu. With such structure, it... Agent: Eric Robinson

20080315203 - Thin film transistor substrate and display device: Disclosed herein is a TFT substrate which exhibits good characteristic properties despite the omission of the barrier metal layer to be normally interposed between the source-drain electrodes and the semiconductor layer in the TFT. The TFT substrate permits sure and direct connection with the semiconductor layer of the TFT. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080315204 - Thin film transistor, and active matrix substrate and display device provided with such thin film transistor: A thin film transistor according to the present invention includes a gate electrode; an insulating film covering the gate electrode; a semiconductor layer provided on the insulating film; and a source electrode and a drain electrode provided on the insulating film and the semiconductor layer. The insulating film is a... Agent: Nixon & Vanderhye, PC

20080315206 - Highly scalable thin film transistor: Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse... Agent: Sandisk Corporation C/o Foley & Lardner LLP

20080315207 - Method of fabricating polycrystalline silicon, tft fabricated using the same, method of fabricating the tft, and organic light emitting diode display device including the tft: A method of fabricating a polycrystalline silicon (poly-Si) layer includes providing a substrate, forming an amorphous silicon (a-Si) layer on the substrate, forming a thermal oxide layer to a thickness of about 10 to 50 Å on the a-Si layer, forming a metal catalyst layer on the thermal oxide layer,... Agent: Stein, Mcewen & Bui, LLP

20080315208 - Semiconductor device and manufacturing method thereof: [Solving Means] By performing the formation of the pixel electrode 127, the source region 123 and the drain region 124 by using three photomasks in three photolithography steps, a liquid crystal display device prepared with a pixel TFT portion, having a reverse stagger type n-channel TFT, and a storage capacitor... Agent: Eric Robinson

20080315209 - Group iii nitride semiconductor device and epitaxial substrate: Affords a Group III nitride semiconductor device having a structure that can improve the breakdown voltage. A Schottky diode (11) consists of a Group III nitride support substrate (13), a gallium nitride region (15), and a Schottky electrode (17). The Group III nitride support substrate (13) has electrical conductivity. The... Agent: Judge Patent Associates

20080315210 - High electron mobility transistor: A GaN-based semiconductor layer is stacked on a GaN-based single-crystal substrate. The GaN-based single-crystal substrate forms an electron transit layer, and the GaN-based semiconductor layer forms an electron supply layer. A principal growth plane of the GaN-based single-crystal substrate is an m-plane, and a principal growth plane of the GaN-based... Agent: Rabin & Berdo, PC

20080315211 - Sic semiconductor device with bpsg insulation film and method for manufacturing the same: A SiC device includes: a substrate; a drift layer; a base region; a source region; a channel layer connecting the drift layer and the source region; a gate oxide film on the channel layer and the source region; a gate electrode on the gate oxide film; an interlayer insulation film... Agent: Posz Law Group, PLC

20080315212 - Method for fabricating a p-type semiconductor structure: One embodiment of the present invention provides a method for fabricating a group III-V p-type nitride structure. The method comprises growing a first layer of p-type group III-V material with a first acceptor density in a first growing environment. The method further comprises growing a second layer of p-type group... Agent: Park, Vaughan & Fleming LLP

20080315213 - Process for producing an electroluminescent p-n junction made of a semiconductor material by molecular bonding: A method for making an electroluminescent PN junction includes molecular bonding a face in a crystalline semiconducting material doped with a first type of a first element with a face in a crystalline semiconducting material doped with a second type opposite to the first type, of a second element, at... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080315214 - Solderless integrated package connector and heat sink for led: Standard solderless connectors extend from a molded package body supporting at least one high power LED. The package includes a relatively large metal slug extending completely through the package. The LED is mounted over the top surface of the metal slug with an electrically insulating ceramic submount in-between the LED... Agent: Patent Law Group LLP

20080315215 - Semiconductor module: A semiconductor module (A1) comprises a semiconductor device (10) provided with a semiconductor chip, and a conductive cover (6) for electromagnetic shielding bonded to the semiconductor device (10) via an adhesive coat (8). The conductive cover (6) includes a surface facing the adhesive coat (8), and the surface is formed... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20080315216 - Terahertz electromagnetic wave radiation element and its manufacturing method: The present invention improves the efficiency of conversion from a non-radiation two-dimensional electron plasmon wave into a radiation electromagnetic wave, and realizes a wide-band characteristic. A terahertz electromagnetic wave radiation element of the present invention comprises a semiinsulating semiconductor bulk layer, a two-dimensional electron layer formed directly above the semiconductor... Agent: Mcglew & Tuttle, PC

20080315218 - Cubic illuminators: An exemplary illuminator includes a first electrode, a second electrode, and a light-emitting chip. The light-emitting chip includes light-emitting layers arranged three-dimensionally. The first and second electrodes are configured for providing different voltages to the light-emitting chip, and the light-emitting chip is capable of emitting light simultaneously along all dimensional... Agent: Wei Te Chung Foxconn International, Inc.

20080315217 - Semiconductor light source and method of producing light of a desired color point: This invention relates to a solid-state light source (100) comprising a first active region (110) for emitting an excitation light (102) and a second active region (120) for emitting a primary light (104), and a conversion element (130) for substantially converting the excitation light (102) into a secondary light (104).... Agent: Philips Intellectual Property & Standards

20080315219 - Light emitting diode light source device: A light emitting diode (LED) light source device includes a plurality of LED modules, a base and a clip. The base has a first base body, a second base body, and a third base body. The second base body and the third base body extend from two sides of the... Agent: Jianq Chyun Intellectual Property Office

20080315220 - High light efficiency solid-state light emitting structure and methods to manufacturing the same: In one embodiment of an epitaxial LED device, a buffer layer (e.g. dielectric layer) between the current spreading layer and the substitute substrate comprises a plurality of vias and has a refractive index that is below that of the current spreading layer. A reflective metal layer between the buffer layer... Agent: Davis Wright Tremaine LLP - San Francisco

20080315224 - Light emitting device and method of fabricating the same: Provided are a light emitting device and a method of fabricating the same, The light emitting device comprises: a first conductive semiconductor layer; an active layer comprising an InGaN well layer and a GaN barrier layer on the first conductive semiconductor layer; and a second conductive semiconductor layer on the... Agent: Birch Stewart Kolasch & Birch

20080315223 - Light emitting device and method of manufacturing the same: Provided is a light emitting device comprising a first conductive type semiconductor layer, an active layer, a semiconductor layer comprising Al, a high-concentration semiconductor layer, a low-mole InxGa1−xN layer, and a second conductive type semiconductor layer. The active layer is on the first conductive type semiconductor layer and emits light.... Agent: Birch Stewart Kolasch & Birch

20080315221 - Nitride-based semiconductor device and method of fabricating the same: A method of fabricating a nitride-based semiconductor device capable of reducing contact resistance between a nitrogen face of a nitride-based semiconductor substrate or the like and an electrode is provided. This method of fabricating a nitride-based semiconductor device comprises steps of etching the back surface of a first semiconductor layer... Agent: Mots Law, PLLC

20080315222 - Semiconductor light emitting device and method of manufacturing the same: A semiconductor light emitting device and a method of manufacturing the same are provided. The semiconductor light emitting device comprises a substrate, a mask seed layer formed on the substrate and comprising a TI group element, a nitride layer formed on the mask seed layer and comprising a III group... Agent: Birch Stewart Kolasch & Birch

20080315225 - Semiconductor light emitting device: Provided are a semiconductor light emitting device and a method of manufacturing the same. The semiconductor light emitting device comprises a p-type substrate, a p-type semiconductor layer, an active layer, and an n-type semiconductor layer. The p-type semiconductor layer is formed on the p-type substrate. The active layer is formed... Agent: Birch Stewart Kolasch & Birch

20080315226 - Light emitting diode, optoelectronic device and method of fabricating the same: A light emitting diode structure including a substrate, a strain-reducing seed layer, an epitaxial layer, a first electrode and a second electrode is provided. The strain-reducing seed layer having a plurality of clusters is disposed on the substrate, and the material of the clusters is selected from a group consisting... Agent: Jianq Chyun Intellectual Property Office

20080315230 - Electronic component package and method of manufacturing the same, and electronic component device: An electronic component package, includes a package substrate portion constructed by a silicon substrate in which a through hole is provided, an insulating layer formed on both surface sides of the silicon substrate and an inner surface of the through hole, and a through electrode filled in the through hole,... Agent: Kratz, Quintos & Hanson, LLP

20080315235 - Light emitting device: A light emitting device is provided that has a semiconductor light emitting element and a phosphor which converts a part of the luminescence spectrum emitted from the semiconductor light emitting element. The luminescence spectrum of the semiconductor light emitting element is located between a near ultraviolet region and a short-wavelength... Agent: Wenderoth, Lind & Ponack, L.L.P.

20080315231 - Light source, optical pickup, and electronic apparatus: A light source of the present invention includes: a semiconductor light emitting device which has a light emitting face and emits light from part of the light emitting face; a container which has a light transmitting window for transmitting the light and accommodates the semiconductor light emitting device; and a... Agent: Panitch Schwarze Belisario & Nadel LLP

20080315229 - Light-emitting device comprising conductive nanorods as transparent electrodes: Disclosed herein is an electrical light-emitting device including a transparent conductive nanorod type electrode, in which transparent conductive nanorods grown perpendicular to a light-emitting layer are used as the electrode. Hence, light is not absorbed by the electrode, and tunneling easily occurs due to nanocontact of the nanorods, thus increasing... Agent: Intellectual Property Law Group LLP

20080315227 - Light-emitting diode arrangement: A light-emitting diode arrangement is disclosed, comprising at least one light-emitting diode (LED) chip with a radiation decoupling surface through which a large portion of the electromagnetic radiation generated in the LED chip exits in a main direction of emission; a housing laterally surrounding the LED chip; and a reflective... Agent: Fish & Richardson PC

20080315232 - Light-emitting semiconductor device: A light-generating semiconductor region is grown on a substrate of electroconductive silicon or like light-absorptive material. An anode is placed atop the light-generating semiconductor region, and a cathode under the substrate. The light-generating semiconductor region and the substrate are encapsulated in an epoxy envelope. In order to prevent the substrate... Agent: Woodcock Washburn LLP

20080315228 - Low profile side emitting led with window layer and phosphor layer: Low profile, side-emitting LEDs are described that generate white light, where all light is emitted within a relatively narrow angle generally parallel to the surface of the light-generating active layer. The LEDs enable the creation of very thin backlights for backlighting an LCD. In one embodiment, the LED emits blue... Agent: Philips Intellectual Property & Standards

20080315234 - Optically active compositions and combinations of same with indium gallium nitride semiconductors: New combinations of semi-conductor devices in conjunction with optically active materials are set forth herein. In particular, light emitting semiconductors fashioned as diodes from indium gallium nitride construction are combined with high-performance optically active Langasite La3GasSi0i4 crystalline materials. When Langasite is properly doped, it will respond to the light output... Agent: The Webb Law Firm, P.C.

20080315236 - Optoelectronic semiconductor device and manufacturing method thereof: An embodiment of the invention discloses an optoelectronic semiconductor device comprising a semiconductor system capable of performing a conversion between light energy and electrical energy; an interfacial layer formed on at least two surfaces of the semiconductor system; an electrical conductor; and an electrical connector electrically connecting the semiconductor system... Agent: Bacon & Thomas, PLLC

20080315233 - Semiconductor light emitting device: Provided is a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive type semiconductor layer, an active layer, a second conductive type super lattice layer, and a second conductive type semiconductor layer. The active layer is formed on the first conductive type semiconductor layer. The second... Agent: Birch Stewart Kolasch & Birch

20080315237 - Gallium nitride-based compound semiconductor light emitting device: This gallium nitride-based compound semiconductor light emitting device includes an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer that are composed of gallium nitride-based compound semiconductors and are deposited in that order on a substrate, and further includes a negative electrode and a positive electrode that... Agent: Sughrue Mion, PLLC

20080315240 - Iii-nitride semiconductor light emitting device: The present disclosure relates to an III-nitride semiconductor light emitting device, particularly, an electrode structure thereof. The III-nitride semiconductor light emitting device includes a substrate, a plurality of III-nitride semiconductor layers grown on the substrate, and composed of a first III-nitride semiconductor layer with first conductivity, a second III-nitride semiconductor... Agent: Harness, Dickey, & Pierce, P.l.c

20080315238 - Porous circuitry material for led submounts: A submount comprising a ceramic substrate and a circuitry arranged thereon is provided. The circuitry comprises an electrically conducting porous material comprising at least one noble metal doped with at least one non-noble metal, the surface of at least portions of said electrically conducting porous material comprises oxides of said... Agent: Philips Intellectual Property & Standards

20080315241 - Surface mountable chip: A surface mountable device having a circuit device and a base section. The circuit device includes top and bottom layers having a top contact and a bottom contact, respectively. The base section includes a substrate having a top base surface and a bottom base surface. The top base surface includes... Agent: The Law Offices Of Calvin B. Ward

20080315239 - Thin double-sided package substrate and manufacture method thereof: The present invention discloses a manufacture method for a thin double-sided package substrate, which includes steps: providing a carrier; respectively forming a first conductive layer and a second conductive layer on the upper and lower surfaces of the carrier; forming a through-hole penetrating the first conductive layer and the carrier... Agent: Eschweiler & Associates, LLC National City Bank Building

20080315242 - System, apparatus and method of selective laser repair for metal bumps of semiconductor device stack: Exemplary embodiments of the selective laser repair apparatus and method may allow the repair of metal bumps in a semiconductor device stack by applying a laser beam to a damaged and/or defective bump. Metal bumps may be repaired and individual chips and/or packages forming a device stack need not be... Agent: Harness, Dickey & Pierce, P.L.C

20080315243 - Group iii nitride semiconductor light-emitting device: A group III nitride semiconductor light-emitting device comprises an n-type gallium nitride-based semiconductor layer, a first p-type AlXGa1-XN (0≦X<1) layer, an active layer including an InGaN layer, a second p-type AlYGa1-YN (0≦Y≦X<1) layer, a third p-type AlZGa1-XN layer (0≦Z≦Y≦X<1), and a p-electrode in contact with the third p-type AlZGa1-ZN layer.... Agent: Drinker Biddle & Reath (dc)

20080315244 - Light emitting diode and method for manufacturing the same: Provided are a light emitting diode (LED) and a method for manufacturing the same. The LED includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The active layer includes a well layer and a barrier layer that are alternately laminated at least twice. The barrier layer... Agent: H.c. Park & Associates, PLC

20080315245 - Nitride-based semiconductor substrate and semiconductor device: A nitride-based semiconductor substrate has a diameter of 25 mm or more, a thickness of 250 micrometers or more, a n-type carrier concentration of 1.2×1018 cm−3 or more and 3×1019 cm−3 or less, and a thermal conductivity of 1.2 W/cmK or more and 3.5 W/cmK or less. Alternatively, the substrate... Agent: Mcginn Intellectual Property Law Group, PLLC

20080315247 - Bonded-wafer superjunction semiconductor device: A bonded-wafer semiconductor device includes a semiconductor substrate, a buried oxide layer disposed on a first main surface of the semiconductor substrate and a multi-layer device stack. The multi-layer device stack includes a first device layer of a first conductivity disposed on the buried oxide layer, a second device layer... Agent: Panitch Schwarze Belisario & Nadel LLP

20080315246 - Transistor switch circuit and sample-and-hold circuit: A transistor switch circuit includes: a MOS transistor in which a channel is formed when a gate-source voltage is zero; and a voltage supply part which is connected to a gate of the MOS transistor to supply the gate with a voltage for turning off the MOS transistor.... Agent: Amin, Turocy & Calvin, LLP

20080315250 - Insulated gate semiconductor device and the method of manufacturing the same: A trench-type insulated-gate semiconductor device is disclosed that includes unit cells having a trench gate structure that are scattered uniformly throughout the active region of the device. The impurity concentration in the portion of a p-type base region, sandwiched between an n+-type emitter region and an n-type drift layer and... Agent: Rossi, Kimms & Mcdowell LLP.

20080315249 - Semiconductor device and manufacturing method thereof: A semiconductor substrate has a trench in a first main surface. An insulated gate field effect part includes a gate electrode formed in the first main surface. A potential fixing electrode fills the trench and has an expanding part expanding on the first main surface so that a width thereof... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080315248 - Semiconductor device having igbt cell and diode cell and method for designing the same: A semiconductor device includes: a semiconductor substrate; an IGBT cell; and a diode cell. The substrate includes a first layer on a first surface, second and third layers adjacently arranged on a second surface of the substrate and a fourth layer between the first layer and the second and third... Agent: Posz Law Group, PLC

20080315251 - Semiconductor device and method for fabricating thereof: A semiconductor device and/or a method for fabricating a semiconductor device (e.g. fabricating an LIGBT) that may minimize occurrences of latch-up due to increases of hole current. A semiconductor device and/or a method of fabricating a semiconductor device that may prevent and/or eliminate latch-up due to operation of a parasitic... Agent: Sherr & Vaughn, PLLC

20080315252 - Image sensor and method for manufacturing the same: An image sensor provides enhanced integration of transistor circuitry and photo diodes. The image sensor simultaneously improves resolution and sensitivity. An image sensor an a method for manufacturing prevents defects in a photo diode by adopting a vertical photo diode structure. An image sensor includes a substrate which may include... Agent: Sherr & Vaughn, PLLC

20080315253 - Front and backside processed thin film electronic devices: This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and... Agent: Wisconsin Alumni Research Foundation (warf)

20080315254 - Semiconductor device fabrication method, semiconductor device, and semiconductor layer formation method: A semiconductor device fabrication method and a semiconductor layer formation method for making a semiconductor layer having excellent morphology selectively epitaxial-grow over a semiconductor, and a semiconductor device. When a recessed source/drain pMOSFET is fabricated, a gate electrode is formed over a Si substrate in which STIs are formed with... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080315255 - Thermal expansion transition buffer layer for gallium nitride on silicon: A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate with a first thermal expansion coefficient (TEC), and forms a silicon-germanium (SiGe) film overlying the Si substrate. A buffer layer is deposited overlying the... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080315256 - Nitride semiconductor device: A nitride semiconductor device according to the present invention includes: a nitride semiconductor laminated structure comprising a first layer made of a Group III nitride semiconductor, a second layer laminated on the first layer and made of an Al-containing Group III nitride semiconductor with a composition that differs from that... Agent: Rabin & Berdo, PC

20080315257 - Semiconductor device and power conversion device using the same: In a semiconductor device in which a diode and a high electron mobility transistor are incorporated in the same semiconductor chip, a compound semiconductor layer of the high electron mobility transistor is formed on a main surface (first main surface) of a semiconductor substrate of the diode, and an anode... Agent: Miles & Stockbridge PC

20080315258 - Cell based integrated circuit and unit cell architecture therefor: A unit cell for an integrated circuit includes a first conductive type active region and a second conductive type active region which extend in a first direction. Each of the active regions has first and second ends. The first end of the second conductive type active region opposes the second... Agent: Volentine & Whitt PLLC

20080315259 - Semiconductor memory device: A semiconductor memory device is constructed to include a memory cell formed by a plurality of transistors, wherein each of gate wiring layers of all of the transistors forming the memory cell is arranged to extend in one direction.... Agent: Arent Fox LLP

20080315260 - Diode structure: An open-base semiconductor diode device has an emitter, base, and collector layers. The layers are configured and doped such that the device has an IV characteristic with: i. a punchthrough region beginning at a voltage Vpt with positive resistance, followed by, and ii. an avalanche region including a positive resistance... Agent: Patterson & Sheridan L.L.P. Nj Office

20080315261 - Dual conversion gain gate and capacitor combination: A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective storage capacitor. The dual conversion gain element having a control gate switches in the capacitance of the capacitor to change the conversion gain of the... Agent: Dickstein Shapiro LLP

20080315262 - Solid-state imaging device and method for manufacturing the same: It is an object of the present invention to provide a solid-state imaging device that can achieve a high sensitivity, finer pixels for increasing the number of pixels, a high-speed operation, and high image quality, and a method for manufacturing the same. There are provided a plurality of photoelectric conversion... Agent: Hamre, Schumann, Mueller & Larson P.C.

20080315263 - Imager pixel structure and circuit: An imager pixel and imaging device and system including an imager pixel for discharging a floating diffusion region are described. The imager pixel includes a photoconversion regions floating diffusion region, and a reset diode. A reset diode is coupled to the floating diffusion region and, when activated, discharges accumulated and... Agent: Trask Britt, P.C./ Micron Technology

20080315264 - Strain-compensated field effect transistor and associated method of forming the transistor: Disclosed are embodiments of a field effect transistor (FET) having decreased drive current temperature sensitivity. Specifically, any temperature-dependent carrier mobility change in the FET channel region is simultaneously counteracted by an opposite strain-dependent carrier mobility change to ensure that drive current remains approximately constant or at least within a predetermined... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080315265 - Semiconductor radiation detector optimized for detecting visible light: A semiconductor radiation detector comprises a bulk layer of semiconductor material, and on a first surface of the bulk layer in the following order: a modified internal gate layer of semiconductor of second conductivity type, a barrier layer of semiconductor of first conductivity type and pixel dopings of semiconductor of... Agent: Wood, Phillips, Katz, Clark & Mortimer

20080315266 - Junction field effect transistor with a hyperabrupt junction: A junction field effect transistor (JFET) has a hyperabrupt junction layer that functions as a channel of a JFET. The hyperabrupt junction layer is formed by two dopant profiles of opposite types such that one dopant concentration profile has a peak concentration depth at a tail end of the other... Agent: Scully, Scott, Murphy & Presser, P.C.

20080315267 - Device performance improvement using flowfill as material for isolation structures: A trench is formed in the surface of a provided semiconductor body. An oxide is deposited in the trench and a cap is deposited on the oxide, wherein the combination of the cap and the oxide impart a mechanical stress on the semiconductor body.... Agent: Slater & Matsil LLP

20080315268 - Methods and apparatus for semiconductor memory devices manufacturable using bulk cmos process manufacturing: The present invention discloses semiconductor devices that can be manufactured utilizing standard process of manufacturing and that can hold information. In accordance with a presently preferred embodiment of the present invention, one or more semiconductor devices can be formed in a well on a substrate where isolation trenches surround one... Agent: Venture Pacific Law, PC

20080315269 - Photodetector array using isolation diffusions as crosstalk inhibitors between adjacent photodiodes: A photodetector array includes a semiconductor substrate having opposing first and second main surfaces, a first layer of a first doping concentration proximate the first main surface, and a second layer of a second doping concentration proximate the second main surface. The photodetector includes at least one conductive via formed... Agent: Panitch Schwarze Belisario & Nadel LLP

20080315271 - Image sensor and method for fabricating the same: Disclosed are an image sensor and a method for fabricating the same. The method may include forming a gate, a photo diode, and a floating diffusion region on a pixel region of a semiconductor substrate; forming an oxide film on the pixel region and on an edge region of the... Agent: Workman Nydegger 1000 Eagle Gate Tower

20080315273 - Image sensor and method of manufacturing the same: An image sensor for minimizing a dark level defect is disclosed. The image sensor includes an isolation layer formed on a substrate. A field region and an active region are defined on the substrate by the isolation layer. A photodiode is formed in the image sensor in such a structure... Agent: F. Chau & Associates, LLC

20080315272 - Image sensor with gain control: An image sensor having a plurality of pixels; each pixel includes one or more photosensitive elements that collect charge in response to incident light; one or more transfer mechanisms that respectively transfer the charge from the one or more photosensitive elements; a charge-to-voltage conversion region having a capacitance, and the... Agent: Pedro P. Hernandez Patent Legal Staff

20080315270 - Multilayer antireflection coatings, structures and devices including the same and methods of making the same: Multi-layer antireflection coatings, devices including multi-layer antireflection coatings and methods of forming the same are disclosed. A block copolymer is applied to a substrate and self-assembled into parallel lamellae above a substrate. The block copolymer may optionally be allowed to self-assemble into a multitude of domains oriented either substantially parallel... Agent: Trask Britt, P.C./ Micron Technology

20080315274 - Deep trench capacitor and method of making same: A trench capacitor and method of forming a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner;... Agent: Schmeiser, Olsen & Watts

20080315275 - Capacitor pair structure for increasing the match thereof: A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20080315276 - Capacitor pair structure for increasing the match thereof: A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20080315277 - Semiconductor device: A semiconductor device 1 includes MOS transistors 10 and 70 and a MOS varactor 20. The transistors 10 and 70 and the varactor 20 are formed in the same semiconductor substrate 30. The gate insulating films 15 and 75 of the transistors 10 and 70 are the thinnest gate insulating... Agent: Young & Thompson

20080315278 - Insulated gate field effect transistors: The invention relates to FETs with stripe cells (6). Some of the cells have alternating low and high threshold regions (10, 8) along their length. In a linear operations regime, the low threshold regions conduct preferentially and increase the current density, thereby reducing the risk of thermal runaway. By distributing... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080315279 - Nanowire transistor with surrounding gate: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A. Attn: Marvin L. Beekman

20080315281 - Flash memory device and method of manufacturing the same: Disclosed are a flash memory device and a method of manufacturing the same. In the method of manufacturing the flash memory device, gate patterns of a cell area and a logic area are formed by sequentially depositing and patterning a first polysilicon layer, an ONO layer and a second polysilicon... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080315282 - Semiconductor devices including transistors having three dimensional channels: Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the semiconductor fin. A channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode is also provided.... Agent: Myers Bigel Sibley & Sajovec

20080315280 - Semiconductor memory device having memory cell unit and manufacturing method thereof: A semiconductor memory device includes a silicon substrate including a first region which has a buried insulating layer below a single-crystal silicon layer and a second region which does not have the buried insulating layer below the single-crystal silicon layer, at least one memory cell transistor which has a first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080315284 - Flash memory structure and method of making the same: A flash memory cell includes a substrate, a T-shaped control gate disposed above the substrate, a floating gate embedded in a lower recess of the T-shaped control gate, a dielectric layer between the T-shaped control gate and the floating gate; a cap layer above the T-shaped control gate, a control... Agent: North America Intellectual Property Corporation

20080315285 - Non-volatile memory devices and methods of fabricating the same: Non-volatile memory devices and methods of fabricating the same are provided. The non-volatile memory devices may include a semiconductor substrate having a pair of sidewall channel regions extending from the semiconductor substrate and opposite to each other, and a floating gate electrode between the pair of sidewall channel regions and... Agent: Harness, Dickey & Pierce, P.L.C

20080315286 - Semiconductor device: A decease in reliability of a memory element having a floating gate is suppressed. The invention relates to a semiconductor device having an island-like semiconductor film, which is formed over an insulating surface and includes a channel formation region and a high-concentration impurity region, a tunneling insulating film formed over... Agent: Nixon Peabody, LLP

20080315283 - Semiconductor device and method of fabricating the same: A semiconductor device includes a semiconductor substrate having a plurality of element regions and a plurality of element isolation regions in a first direction, a plurality of floating gate electrodes formed via a gate insulating film on the respective element regions, an intergate insulating film formed on the floating gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080315289 - Electrically erasable programmable read-only memory (eeprom) device and methods of fabricating the same: An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080315287 - Flash memory and method of fabricating the same: A flash memory comprising a substrate, a stacked structure over the substrate, a source, a drain and a source-side spacer is provided. The stacked structure includes a tunneling oxide layer, a floating gate on the tunneling oxide layer, an inter-gate dielectric layer on the floating gate and a control gate... Agent: J C Patents, Inc.

20080315288 - Memory cell of nonvolatile semiconductor memory: A memory cell of a nonvolatile semiconductor memory includes a semiconductor region, source/drain areas arranged separately from each other in the semiconductor region, a tunnel insulating film arranged on a channel region between the diffusion areas, a floating gate electrode arranged on the tunnel insulating film, an inter-electrode insulator arranged... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080315290 - Memory device and methods for its fabrication: A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an... Agent: Ingrassia Fisher & Lorenz, P.C.

20080315292 - Atomic layer deposition method and semiconductor device formed by the same: There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within a ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber;... Agent: Squire, Sanders & Dempsey L.L.P.

20080315293 - Atomic layer deposition method and semiconductor device formed by the same: There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within the ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber;... Agent: Squire, Sanders & Dempsey L.L.P.

20080315294 - Dual-gate device and method: A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor... Agent: Macpherson Kwok Chen & Heid LLP

20080315291 - Nonvolatile semiconductor memory device and method of manufacturing the same: A nonvolatile semiconductor memory device has a plurality of memory strings each including a plurality of electrically rewritable memory cells serially connected. The memory string includes a columnar semiconductor portion extending in the vertical direction from a substrate, a first charge storage layer formed adjacent to the columnar semiconductor portion... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080315295 - Atomic layer deposition method and semiconductor device formed by the same: Disclosed are atomic layer deposition method and a semiconductor device including the atomic layer, including the steps: placing a semiconductor substrate in an atomic layer deposition chamber; feeding a first precursor gas to the semiconductor substrate within the chamber to form a first discrete monolayer on the semiconductor substrate; feeding... Agent: Squire, Sanders & Dempsey L.L.P.

20080315296 - Non-volatile semiconductor storage device and method of manufacturing the same: A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080315298 - High-voltage metal-oxide-semiconductor transistor: A high-voltage metal-oxide-semiconductor (HV MOS) transistor is provided to form the decoder in a source driver of a display apparatus for substantially saving the layout area. The HV MOS transistor includes two doped regions with a first conductivity type disposed in a semiconductor substrate, and a gate region having a... Agent: Birch Stewart Kolasch & Birch

20080315297 - Semiconductor device: There is provided a semiconductor device having a drift layer with a pillar structure including first semiconductor layer portions of the first conduction type and second semiconductor layer portions of the second conduction type formed in pillars alternately and periodically on a semiconductor substrate. A device region includes a plurality... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080315299 - Semiconductor device: A semiconductor device includes a first first-conductivity-type semiconductor layer, a second first-conductivity-type semiconductor layer provided on a major surface of the first first-conductivity-type semiconductor layer; a third second-conductivity-type semiconductor layer being adjacent to the second first-conductivity-type semiconductor layer, provided on the major surface of the first first-conductivity-type semiconductor layer, and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080315300 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device includes: a semiconductor substrate having a substrate surface; a spiral body constituted by a linear semiconductor layer on which a body region including a channel region, a first source/drain region disposed on the body region, and a second source/drain region disposed under the body region or in... Agent: Mcginn Intellectual Property Law Group, PLLC

20080315301 - Trench gate power semiconductor device: A trench gate power MOSFET (1) includes: an n−-type epitaxial layer (12); a p-type body region (20) formed in the vicinity of an upper surface of the n−-type epitaxial layer (12); a plurality of trenches (14) formed so as to reach the n−-type epitaxial layer (12) from an upper surface... Agent: Lowe Hauptman Ham & Berner, LLP

20080315303 - Method of forming a semiconductor structure comprising insulating layers with different thicknesses: The method of forming a semiconductor structure in a substrate comprises, forming a first trench with a first width We and a second trench with a second width Wc, wherein the first width We is larger than the second width Wc, depositing a protection material, lining the first trench, covering... Agent: Dicke, Billig & Czaja

20080315302 - Method of forming nanotube vertical field effect transistor: A nanotube field effect transistor and a method of fabrication are disclosed. The method includes electrophoretic deposition of a nanotube to contact a region of a conductive layer defined by an aperture.... Agent: Patterson & Sheridan L.L.P. Nj Office

20080315305 - Semiconductor device and method of manufacturing the same: A LDD layer of the second conduction type locates in the surface of a semiconductor layer beneath a sidewall insulator film. A source layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the LDD layer. A resurf layer of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080315304 - Thin silicon-on-insulator high voltage auxiliary gated transistor: A silicon (Si)-on-insulator (SOI) high voltage transistor is provided with an associated fabrication process. The method provides a SOI substrate with a Si top layer. A control channel and an adjacent auxiliary channel are formed in the Si top layer. A control gate overlies the control channel and an auxiliary... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080315306 - Semiconductor device and method of fabricating the semiconductor device: A semiconductor device comprises a gate electrode on a semiconductor substrate, drift regions at opposite sides of the gate electrode, source and drain regions in the respective drift regions, and shallow trench isolation (STI) regions in the respective drift regions between the gate electrode and the source or drain region,... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080315307 - High voltage device: A high voltage device includes a semiconductor substrate and a gate. The semiconductor substrate includes a first doped region having a first conductive type, a second doped region having a second conductive type, a third doped region having the second conductive type, a fourth doped region surrounding the third doped... Agent: Egbert Law Offices

20080315308 - Low on-resistance lateral double-diffused mos device and method of fabricating the same: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the... Agent: J C Patents, Inc.

20080315309 - Fin field effect transistor devices with self-aligned source and drain regions: Improved fin field effect transistor (FinFET) devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a field effect transistor device comprises the following steps. A substrate is provided having a silicon layer thereon. A fin lithography hardmask is patterned on the silicon layer.... Agent: Michael J. Chang, LLC

20080315310 - High k dielectric materials integrated into multi-gate transistor structures: Embodiments of the present invention relate to the fabrication of three-dimensional multi-gate transistor devices with high aspect ratio semiconductor bodies through the use of a high K dielectric material layer which is selectively wet etched to from a high K gate dielectric. In one specific embodiment, the high K gate... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20080315311 - Semiconductor device: An object is to provide a semiconductor device in which an antenna is not bent and electric waves can be transmitted and received even if a substrate is bent and in which a thin and flexible substrate can be used. The present invention relates to a semiconductor device characterized in... Agent: Eric Robinson

20080315312 - Semiconductor devices having stacked structures: A method of forming a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate, and the interlayer insulating layer may have a contact hole therein exposing a portion of the semiconductor substrate. A single crystal semiconductor plug may be formed in the contact hole and on... Agent: Myers Bigel Sibley & Sajovec

20080315313 - Semiconductor device, method of manufacturing same and method of designing same: A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080315315 - Electronic device including a gated diode: An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to... Agent: Larson Newman Abel Polansky & White, LLP

20080315314 - Semiconductor device having a dual gate electrode and methods of making the same: Disclosed is a method for forming a dual gate electrode of a semiconductor device, which may improve manufacturing productivity by simplifying a process of forming gate electrodes in PMOS and NMOS regions, respectively, and may provide improvement in performance by making the two gate electrodes have a different thickness and... Agent: Workman Nydegger 1000 Eagle Gate Tower

20080315316 - Semiconductor device that is advantageous in operational environment at high temperatures: A semiconductor device comprises an N-type insulated-gate field-effect transistor including a first insulating layer that is provided along side walls of a gate electrode, has a negative thermal expansion coefficient, and applies a tensile stress to a channel region of the N-type insulated-gate field-effect transistor. The device also comprises a... Agent: Foley And Lardner LLP Suite 500

20080315318 - Semiconductor device and manufacturing method thereof: A semiconductor device includes an n-type MIS (Metal Insulator Semiconductor) transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate insulating film, a first fully silicided (FUSI) gate electrode formed on the first gate insulating film and made of a first metal silicide film, and a... Agent: Mcdermott Will & Emery LLP

20080315317 - Semiconductor system having complementary strained channels: A semiconductor system is provided including providing a semiconductor substrate; forming PMOS and NMOS transistors in and on the semiconductor substrate; forming a tensile strained layer on the semiconductor substrate; and relaxing the tensile strained layer around the PMOS transistor.... Agent: Law Offices Of Mikio Ishimaru

20080315319 - Semiconductor device and manufacturing method of the semiconductor device: A semiconductor device includes a dual gate CMOS logic circuit having gate electrodes with different conducting types and a trench capacitor type memory on a same substrate includes a trench of the substrate for the trench capacitor, a dielectric film formed in the trench, a first poly silicon film formed... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080315320 - Semiconductor device with both i/o and core components and method of fabricating same: A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an... Agent: Slater & Matsil, L.L.P.

20080315322 - Method for reliably removing excess metal during metal silicide formation: A method for manufacturing a semiconductor device. The method comprises forming a metal layer on a silicon-containing layer located on a semiconductor substrate. The method also comprises reacting a portion of the metal layer with the silicon-containing layer to form a metal silicide layer. The method further comprises removing an... Agent: Texas Instruments Incorporated

20080315321 - System and method for forming a semiconductor device source/drain contact: The present invention discloses a semiconductor source/drain contact structure, which comprises a substrate, a source/drain region disposed in the substrate, at least one non-silicided conductive layer including a barrier layer disposed over and in contact with the source/ drain region, and one or more contact hole filling metals disposed over... Agent: K & L Gates LLP

20080315323 - Method for forming line pattern array, photomask having the same and semiconductor device fabricated thereby: A method of forming a line pattern array comprises the steps of setting a layout which includes first continuous line patterns arranged to have a first line width and a second continuous line pattern arranged to have a second line width larger than the first line width and positioned outside... Agent: Marshall, Gerstein & Borun LLP

20080315324 - Method to obtain uniform nitrogen profile in gate dielectrics: The present invention, in one aspect, provides a method of manufacturing a microelectronics device 100 that includes depositing a first gate dielectric layer 160 over a substrate 115, subjecting the first gate dielectric layer 160 to a first nitridation process, forming a second gate dielectric layer 165 over the substrate... Agent: Texas Instruments Incorporated

20080315325 - Semiconductor device and method of manufacturing the same: A semiconductor device including a semiconductor substrate; an element isolation region formed in the substrate including trenches formed at a first depth and being filled with an element isolation insulating film; an element forming region formed on the substrate and being surrounded by the trenches; a gate electrode formed along... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080315326 - Method for forming an integrated circuit having an active semiconductor device and integrated circuit: An integrated circuit having an active semiconductor device is formed comprising a trench defined by conductor lines previously formed.... Agent: Fay Kaplun & Marcin, LLP

20080315327 - Tungsten plug drain extension: A power metal-oxide-semiconductor field effect transistor (MOSFET) cell includes a semiconductor substrate. A first electrode is disposed on the semiconductor substrate. A voltage sustaining layer is formed on the semiconductor substrate. A highly doped active zone of a first conductivity type is formed in the voltage sustaining layer opposite the... Agent: Panitch Schwarze Belisario & Nadel LLP

20080315328 - Dual poly deposition and through gate oxide implants: Dopants are implanted at relatively high energies into an unmasked first region of a semiconductor substrate through a thin layer of gate electrode material and a gate dielectric layer. Lower energy dopants are then implanted into the thin layer of gate electrode material. The first region is then masked off,... Agent: Texas Instruments Incorporated

20080315329 - Integrated circuit with a subsurface diode: An integrated circuit includes a first and second diode connected in parallel. The first diode has a first breakdown voltage and has first P type region and first N type region adjacent to each other at the surface of the substrate of a substrate to form a lateral diode. The... Agent: Barnes & Thornburg LLP

20080315330 - Sacrificial self-aligned interconnect structures: A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material adjacent to an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and the semiconductor device. A preexisting geometry of the active region is maintained... Agent: Trask Britt, P.C./ Micron Technology

20080315331 - Ultrasound system with through via interconnect structure: An ultrasound monitoring system. In one embodiment, an array of transducer cells is formed along a first plane and an integrated circuit structure, formed along a second plane parallel to the first plane, includes an array of circuit cells. A connector provides electrical connections between the array of transducer cells... Agent: General Electric Company Global Research

20080315332 - Micromechanical component and manufacturing method: A micromechanical component has a substrate, a first intermediate layer which is situated thereupon, and a first layer which is situated thereupon and is structured down to the first intermediate layer. A second intermediate layer is situated above the first layer. A second layer is situated on the former, at... Agent: Kenyon & Kenyon LLP

20080315334 - Packaged chip devices with atomic layer deposition protective films: A low-temperature inorganic dielectric ALD film (e.g., Al2O3 and TiO2) is deposited on a packaged or unpackaged chip device so as to coat the device including any exposed electrical contacts. Such a low-temperature ALD film generally can be deposited without damaging the packaged chip device. The ALD film is typically... Agent: Bromberg & Sunstein LLP

20080315333 - Substrate-level assembly for an integrated device, manufacturing process thereof and related integrated device: A substrate-level assembly having a device substrate of semiconductor material with a top face and housing a first integrated device, including a buried cavity formed within the device substrate, and with a membrane suspended over the buried cavity in the proximity of the top face. A capping substrate is coupled... Agent: Seed Intellectual Property Law Group PLLC

20080315335 - Magnetoresistive random access memory: A magnetoresistive random access memory includes first and second magnetoresistive effect element. A shape of the first magnetoresistive effect element has a first length in a first direction and a second length in a second direction. The second length is equal to or greater than the first length. A ratio... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080315336 - Method of assembly using array of programmable magnets: Systems and methods for assembling a structure onto a substrate include an array of programmable magnets disposed beneath a substrate, wherein a magnetic field is applied to the structure to levitate the structure above the substrate while the structure is moved relative to the substrate to align the structure with... Agent: Mccarter & English , LLP Stamford Office

20080315338 - Image sensor and method for manufacturing the same: Disclosed are an image sensor and a method for manufacturing the same. The image sensor can include a substrate with a photodiode formed thereon. A metal interconnection and interlayer dielectric layer can be formed on the substrate, the interlayer dielectric layer having a recess structure formed by selectively removing a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080315337 - Light receiving element: There is provided a structure for a light receiving element having a plurality of light receiving regions, whereby noise charges from a light receiving region can be prevented from becoming superimposed on the signal charges of another light receiving region so that the light receiving regions can generate accurate electric... Agent: Oliff & Berridge, PLC

20080315341 - Image sensor and method for manufacturing the same: An image sensor and a method for manufacturing the same are disclosed. The image sensor can include a passivation layer on a substrate having a pad area and a pixel area, a color filter layer on the passivation layer over the pixel area, a first low temperature oxide layer on... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080315339 - Solid-state imaging device: A solid-state imaging device includes a light-receiving portion, an optical filter layer, and quantum dots. The light receiving portion, where a photoelectric conversion is carried out, is formed in a semiconductor substrate. The optical filter layer is directly formed on or formed through another layer on the surface of the... Agent: Robert J. Depke Lewis T. Steadman

20080315340 - Solid-state imaging device and method of fabricating the same: A solid-state imaging device includes a layer including an on-chip lens above a sensor section, and the layer including the on-chip lens is composed of an inorganic film which transmits ultraviolet light. The layer including the on-chip lens may further include a planarizing film located below the on-chip lens. A... Agent: Sonnenschein Nath & Rosenthal LLP

20080315342 - Semiconductor device with a bulk single crystal on a substrate: Device and method of forming a device in which a substrate (10) is fabricated with at least part of an electronic circuit for processing signals. A bulk single crystal material (14) is formed on the substrate, either directly on the substrate (10) or with an intervening thin film layer or... Agent: Popovich, Wiles & O'connell, PA 650 Third Avenue South

20080315343 - Semiconductor device: A semiconductor device includes: a first insulating layer; a semiconductor layer provided on the first insulating layer; a first semiconductor region selectively provided in the semiconductor layer; a second semiconductor region selectively provided in the semiconductor layer and spaced from the first semiconductor region; a first main electrode provided in... Agent: Amin, Turocy & Calvin, LLP

20080315344 - Semiconductor integrated circuit: This invention is directed to improve the electrostatic discharge strength and the latch-up strength of the semiconductor integrated circuit. To achieve the certain level of stable quality of the semiconductor integrated circuit by eliminating the variety in the electrostatic discharge strength and the latch-up strength is also aimed. The first... Agent: Morrison & Foerster LLP

20080315345 - Technique for stable processing of thin/fragile substrates: A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second... Agent: Panitch Schwarze Belisario & Nadel LLP

20080315346 - Passivation of deep isolating separating trenches with sunk covering layers: Trenches are formed in an SOI wafer to isolate low-voltage and high-voltage elements in the wafer. The isolation trenches are formed with trench coverings that do not protrude above the trenches. Vertical in-trench and horizontal out-of-trench isolation layers are formed and the trenches are then filled to above the planar... Agent: Stevens & Showalter LLP

20080315349 - Method for manufacturing bonded wafer and bonded wafer: The present invention provides a method for manufacturing a bonded wafer prepared by bonding a base wafer and a bond wafer, comprising at least a step of etching an oxide film in a terrace region in an outer periphery of the bonded wafer wherein the oxide film in the terrace... Agent: Oliff & Berridge, PLC

20080315350 - Method for manufacturing semiconductor substrate, and semiconductor device: It is an object to form single-crystalline semiconductor layers with high mobility over approximately the entire surface of a glass substrate even when the glass substrate is increased in size. A first single-crystalline semiconductor substrate is bonded to a substrate having an insulating surface, the first single-crystalline semiconductor substrate is... Agent: Eric Robinson

20080315348 - Pitch by splitting bottom metallization layer: An integrated circuit structure includes a semiconductor substrate; a first bottom metallization (M1) layer over the semiconductor substrate; a second M1 layer over the first M1 layer, wherein metal lines in the first and the second M1 layer have widths of greater than about a minimum feature size; and vias... Agent: Slater & Matsil, L.L.P.

20080315347 - Providing gaps in capping layer to reduce tensile stress for beol fabrication of integrated circuits: Fabricating an integrated circuit using a cap layer that includes one or more gaps or voids. The gaps or voids are provided prior to performing deposition and cure for an inter-layer dielectric (ILD) layer adjoining the cap layer. The gaps or voids reduce and prevent tensile stress buildup by allowing... Agent: Cantor Colburn LLP - IBM Fishkill

20080315351 - Semiconductor substrate and maehtod for manufacturing the same: A semiconductor device and a method for manufacturing thereof are provided. The method includes a step of forming a first insulating film containing silicon and oxygen as its composition over a single-crystal semiconductor substrate, a step of forming a second insulating film containing silicon and nitrogen as its composition over... Agent: Eric Robinson

20080315352 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device begins when a first dielectric pattern is formed on and/or over a substrate, and a first etching process is performed to form a trench in the substrate. An edge portion of the first trench is exposed. An oxidation process is performed on and/or... Agent: Sherr & Vaughn, PLLC

20080315353 - Empty vias for electromigration during electronic-fuse re-programming: The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to an e-fuse device including an opening, a first via and a second via in an interlayer dielectric, wherein the opening, the first via and the second via are connected to an interconnect below the interlayer dielectric;... Agent: Hoffman Warnick LLC

20080315354 - Fuse for semiconductor device: Embodiments relate to a fuse for a semiconductor device. To maintain a stable blowing characteristic with a minimized applied current, the fuse includes a fuse line having a blowing characteristic dependent on applied current. A first contact pad has a plurality of contacts connected to one side of the fuse... Agent: Sherr & Vaughn, PLLC

20080315355 - Semiconductor device and method of manufacturing the same: A semiconductor device in accordance with the present invention includes a fuse formed on a substrate; a first insulator film provided so as to cover the fuse; cavity-forming pattern provided in the layer on the first insulator film; and second insulator film provided so as to cover the cavity-forming pattern,... Agent: Young & Thompson

20080315356 - Semiconductor die with backside passive device integration: According to an exemplary embodiment, a semiconductor die includes a backside surface opposite an active surface. The active surface includes at least one active device. The semiconductor die includes at least one passive device situated on the backside surface. The semiconductor die further includes an interconnect region situated over the... Agent: Farjami & Farjami LLP

20080315358 - Capacitive element, method of manufacture of the same, and semiconductor device: A capacitive element is characterized by including: a base (12); a lower barrier layer (13) formed on the base (12); capacitors (Q1 and Q2) made by forming a lower electrode (14a), capacitor dielectric layers (15a), and upper electrodes (16a) in this order on the lower barrier layer (13); and an... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080315357 - Integrated circuit and method including structuring a material: A method of making an integrated circuit including structuring a material. The method includes providing an arrangement of three-dimensional bodies. The material is arranged between the bodies and structured directed radiation. The projection pattern of the three-dimensional bodies is transferred into the material. The structured material connects at least two... Agent: Dicke, Billig & Czaja

20080315359 - Integrated circuit including vertical diode: An integrated circuit includes a vertical diode, a first electrode coupled to the vertical diode, and a resistivity changing material coupled to the first electrode. The integrated circuit includes a second electrode coupled to the resistivity changing material and a spacer having a first sidewall contacting a first sidewall of... Agent: Dicke, Billig & Czaja

20080315360 - Resistor of semiconductor device and method for fabricating the same: A resistor for a semiconductor device is provided. The resistor can include a first polysilicon layer formed on a semiconductor substrate; an insulating layer formed on regions of the first polysilicon layer; a second polysilicon layer formed on the insulating layer; and a contact electrically connected to the first polysilicon... Agent: Jeff Lloyd Saliwanchik, Lloyd & Saliwanchik

20080315361 - Semiconductor device and method of manufacturing the same: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) comprising a vertical bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080315362 - Micro-electro-mechanical system varactor: A micro-electro-mechanical system varactor. The varactor includes a substrate, a lower bias conductor partially overlaying the substrate, a first signal conductor partially overlaying the substrate, a dielectric layer at least partially overlaying the first signal conductor, a support structure coupled to the substrate, and a flexible structure coupled to the... Agent: Leveque Intellectual Property Law, P.C.

20080315363 - Method for producing a semiconductor component, and a semiconductor component: A method for producing a semiconductor component is proposed. The method includes providing a semiconductor body having a first surface; forming a mask on the first surface, wherein the mask has openings for defining respective positions of trenches; producing the trenches in the semiconductor body using the mask, wherein mesa... Agent: Dickstein Shapiro LLP

20080315364 - Semiconductor device and manufacturing method for same: After introducing oxygen into an N− type FZ wafer serving as an N− type first semiconductor layer, a P type second semiconductor layer and an anode are formed on a surface of the FZ wafer. The FZ wafer is irradiated with protons from the side of the anode, introducing crystal... Agent: Rossi, Kimms & Mcdowell LLP.

20080315365 - Method for designing dummy pattern, exposure mask, semiconductor device, method for manufacturing semiconductor device, and storage medium: A method for designing a dummy pattern that is formed in a vacant section of a chip region before a semiconductor substrate including the chip region that has a device graphics data section in which a circuit element pattern is formed and the vacant section in which the circuit element... Agent: Mcginn Intellectual Property Law Group, PLLC

20080315366 - Semiconductor device: The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an a interlayer insulating film. Dummy vias... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080315368 - Silicon wafer having through-wafer vias: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. A trench is formed in the semiconductor substrate at the first main surface. The trench extends to a first depth position in the semiconductor substrate. The trench is... Agent: Panitch Schwarze Belisario & Nadel LLP

20080315367 - Wiring substrate: There is provided a wiring substrate. The wiring substrate includes: a semiconductor substrate having a through hole; an insulating film provided to cover an upper surface, a lower surface and a first surface of the semiconductor substrate, the first surface corresponding to a side surface of the through hole; a... Agent: Drinker Biddle & Reath (dc)

20080315369 - Semiconductor device and semiconductor package having the same: A semiconductor device having no voids and a semiconductor package using the same is described. The semiconductor device includes a semiconductor chip having a circuit section which is formed in a first area and a peripheral section which is formed in a second area defined around the first area, and... Agent: Ladas & Parry LLP

20080315370 - Fabrication of optical-quality facets vertical to a (001) orientation substrate by selective epitaxial growth: Methods for forming {110} type facets on a (001) oriented substrate of Group III-V compounds and Group IV semiconductors using selective epitaxial growth is provided. The methods include forming a dielectric film on a (100) substrate. The dielectric film can then be patterned to expose a portion of the substrate... Agent: Mh2 Technology Law Group, LLP

20080315374 - Integrated circuit package-in-package system with magnetic film: An integrated circuit package-in-package system comprising: connecting a first integrated circuit device and a package substrate; applying a magnetic film over the first integrated circuit device; mounting a second integrated circuit device having an inner encapsulation over the magnetic film; and forming a package encapsulation over the first integrated circuit... Agent: Law Offices Of Mikio Ishimaru

20080315375 - Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and... Agent: Heslin Rothenberg Farley & Mesiti PC

20080315373 - Method of enabling alignment of wafer in exposure step of ic process after uv-blocking metal layer is formed over the whole wafer: A method of enabling alignment of a wafer in at least one exposure step of an integrated circuit process after a UV-blocking metal layer is formed over the whole wafer covering a patterned upmost metal layer of the integrated circuit is described, wherein the wafer has an edge portion where... Agent: J C Patents, Inc.

20080315371 - Methods and apparatus for emi shielding in multi-chip modules: Methods and structures provide a shielded multi-layer package for use with multi-chip modules and the like. A substrate (102) (e.g., chip carrier) has an adhesive layer (104), where electronic components (106, 108) are attached. An insulating layer (110) is formed over the plurality of electronic components, and a conductive encapsulant... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080315372 - Wafer level integration package: A semiconductor package includes a wafer having a first electrical contact pad integrated into a top surface of the wafer. A through-hole interconnection extends downward from a first surface of the first electrical contact pad. A die is electrically connected to a second surface of the first electrical contact pad.... Agent: Quarles & Brady LLP

20080315376 - Conformal emi shielding with enhanced reliability: An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a molded package panel to a process carrier (10) using a double side adhesive tape (12) before singulating the individual modules without separating them from the double side adhesive tape. By forming... Agent: Hamilton & Terrile, LLP - Freescale

20080315377 - Packaged electronic modules and fabrication methods thereof implementing a cell phone or other electronic system: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and... Agent: Heslin Rothenberg Farley & Mesiti PC

20080315378 - Semiconductor device with surface mounting terminals: A semiconductor device has a sealing body formed of an insulating resin and a semiconductor chip positioned within the sealing body. A gate electrode and a source electrode are on a first main surface of the semiconductor chip and a back electrode (drain electrode) is on a second main surface... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080315379 - Semiconductor packages including thermal stress buffers and methods of manufacturing the same: Provided is a semiconductor package and method of manufacturing the same. The semiconductor package may include a semiconductor chip, an encapsulant encapsulating the semiconductor chip, a lead unit, and a partially encapsulated by the encapsulating thermal stress buffer which absorbs thermal stress of the semiconductor chip or the encapsulant.... Agent: Harness, Dickey & Pierce, P.L.C

20080315380 - Integrated circuit package system having perimeter paddle: An integrated circuit package system comprising: forming a paddle having a hole and an external interconnect; mounting an integrated circuit device having an active side to the paddle with the active side facing the paddle and the hole; connecting a first internal interconnect between the active side and the external... Agent: Law Offices Of Mikio Ishimaru

20080315381 - Lead frame, semiconductor device using same and manufacturing method thereof: The present invention provides a semiconductor device which comprises a lead frame including a die pad having one or two or more openings, a substrate mounted over the die pad so as to expose a plurality of semiconductor chip connecting second electrode pads from the openings of the die pad,... Agent: Rabin & Berdo, PC

20080315382 - Multiple die integrated circuit package: A multiple die package and removable storage card is disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and electrically coupled to at least one lead... Agent: Vierra Magen/sandisk Corporation

20080315384 - Apparatuses and methods for forming electronic assemblies: Apparatuses and methods for forming displays are claimed. One embodiment of the invention includes a contact smart card wherein fluidic self assembly is used to build the microelectronic structures on the display such that a contact smart data is transmitted unidirectionally. A contact smart card is inserted directly into a... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080315383 - Chip frame for optical digital processor: A chip frame for an optical digital processor has a body with a concave seat integrally protruding downward from a bottom surface of the body. Multiple dents are defined on the bottom surface of the body to receive conductive elements such as springs. With the conductive elements, the chip frame... Agent: Pai Patent & Trademark Law Firm

20080315385 - Array molded package-on-package having redistribution lines: A semiconductor device with a sheet-like insulating substrate (101) integral with two or more patterned layers of conductive lines and vias, a chip attached to an assembly site, and contact pads (103) in pad locations has an encapsulated region on the top surface of the substrate, extending to the edge... Agent: Texas Instruments Incorporated

20080315386 - Semiconductor device: A semiconductor device includes a first semiconductor package, a second semiconductor package. The first semiconductor package includes a first semiconductor package base having a first cavity formed therein, a first mount component mounted in the first cavity, and a first magnet disposed on the first semiconductor package base. The second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080315387 - Semiconductor package-on-package system including integrated passive components: A semiconductor system (300) has one or more packaged active subsystems (310, 330); each subsystem has a substrate with electrical contact pads and one or more semiconductor chips stacked on top of each other, assembled on the substrate. The system further has a packaged passive subsystem (320) including a substrate... Agent: Texas Instruments Incorporated

20080315389 - Bumpless flip-chip assembly with a complaint interposer contractor: Consistent with an example embodiment, an integrated circuit device (IC) is assembled on a package substrate and encapsulated in a molding compound. There is a semiconductor die having a circuit pattern with contact pads. A package substrate having bump pad landings corresponding to the contact pads of the circuit pattern,... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080315390 - Chip scale package for a micro component: A package includes a sensor die with a micro component, such as a MEMS device, coupled to an integrated circuit which may include, for example, CMOS circuitry, and one or more electrically conductive bond pads near the periphery of the sensor die. A semiconductor cap structure is attached to the... Agent: Fish & Richardson P.C.

20080315391 - Integrated structures and methods of fabrication thereof with fan-out metallization on a chips-first chip layer: Electronic modules and methods of fabrication are provided implementing a first metallization level directly on a chips-first chip layer. The chips-first layer includes chips, each with a pad mask over an upper surface and openings to expose chip contact pads. Structural dielectric material surrounds and physically contacts the side surfaces... Agent: Heslin Rothenberg Farley & Mesiti PC

20080315388 - Vertical controlled side chip connection for 3d processor package: In some embodiments, vertical controlled side chip connection for 3D processor package is presented. In this regard, an apparatus is introduced having a substrate, a substantially horizontal, in relation to the substrate, integrated circuit device coupled to the substrate, and a substantially vertical, in relation of the substrate, integrated circuit... Agent: Intel Corporation C/o Intellevate, LLC

20080315392 - Rf power transistor packages with internal harmonic frequency reduction and methods of forming rf power transistor packages with internal harmonic frequency reduction: A packaged RE power device includes a transistor having a control terminal and an output terminal and configured to operate at a fundamental operating frequency, an RF signal input lead coupled to the control terminal, and an RF signal output lead coupled to the output terminal. A harmonic reducer is... Agent: Myers Bigel Sibley & Sajovec

20080315393 - Rf transistor packages with internal stability network and methods of forming rf transistor packages with internal stability networks: A packaged RF transistor device includes an RF transistor die including a plurality of RF transistor cells. Each of the plurality of RF transistor cells includes a control terminal and an output terminal. The RF transistor device further includes an RF input lead, and an input matching network coupled between... Agent: Myers Bigel Sibley & Sajovec

20080315394 - Semiconductor package and a method for manufacturing the same: A semiconductor package and a method for manufacturing the same capable of supplying power easily without an increase in the number of pads for power supply. The semiconductor package includes a semiconductor chip having a plurality of pads including pads for power supply disposed in a center portion and an... Agent: Ladas & Parry LLP

20080315395 - Stacked semiconductor package and method for manufacturing the same: Disclosed are a stacked semiconductor package and a method for manufacturing the same. The method for manufacturing a stacked semiconductor package includes preparing a substrate formed with a seed metal layer; laminating semiconductor chips having via holes aligned with one another on the seed metal layer to form a semiconductor... Agent: Ladas & Parry LLP

20080315396 - Mold compound circuit structure for enhanced electrical and thermal performance: According to an exemplary embodiment, an overmolded semiconductor package includes at least one semiconductor die situated over a package substrate. The overmolded semiconductor package further includes a mold compound overlying the at least one semiconductor die and the package substrate and having a top surface. The overmolded semiconductor package further... Agent: Farjami & Farjami LLP

20080315397 - Die mounting stress isolator: One method of the present invention includes preparing a die with traces and pads as desired for the intended use of the die. A MEMS device is mounted to the die. The die is then mounted to a substrate of the same material as the die. The substrate is then... Agent: Honeywell International Inc. Patent Services Ab-2b

20080315398 - Packaging substrate with embedded chip and buried heatsink: An embedded chip package includes a substrate having a dielectric interposer, a first metal foil on a first surface and a second metal foil on a second surface of the substrate, wherein the substrate has a cavity recessed into the first surface; a metal heatsink embedded within the cavity; a... Agent: North America Intellectual Property Corporation

20080315399 - Semiconductor device having through contacts through a plastic housing composition and method for the production thereof: The invention relates to a semiconductor device comprising through contacts through a plastic housing composition and a method for the production thereof. For this purpose, the wiring substrate has a solder deposit on which through contact elements are arranged vertically with respect to the wiring substrate and extend as far... Agent: Dicke, Billig & Czaja

20080315400 - Microelectromechanical systems design feature: A device for reducing the chance that a microelectromechanical systems (MEMS) device with moving parts will have those parts stick to a glass cover of the MEMS device, and a method for making the device. An example embodiment of the invention includes a MEMS device wafer, a substrate wafer, and... Agent: Honeywell International Inc. Patent Services Ab-2b

20080315401 - Power semiconductor module and method of manufacturing the power semiconductor module: A power semiconductor module has a silicon nitride insulated substrate, a metal circuit plate made of Cu or a Cu alloy, which is disposed on one surface of the silicon nitride insulated substrate, a semiconductor chip mounted on the metal circuit plate, and a heat dissipating plate made of Cu... Agent: Crowell & Moring LLP Intellectual Property Group

20080315402 - Printed circuit board, memory module having the same and fabrication method thereof: A printed circuit board, a memory module having the same, and a fabrication method thereof. The printed circuit board includes an interconnection substrate on which electronic components are mounted and in which a plurality of signal lines are arranged. The signal lines are electrically coupled to the electronic components. A... Agent: Marger Johnson & Mccollom, P.C.

20080315403 - Apparatus and methods for cooling semiconductor integrated circuit chip packages: Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for... Agent: F. Chau & Associates, LLC

20080315404 - Integrated thermal structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and... Agent: Heslin Rothenberg Farley & Mesiti PC

20080315405 - Heat spreader in a flip chip package: A microelectronic package with enhanced thermal management using an embedded heat spreader is disclosed. The microelectronic package comprises a die mounted on a substrate, a thermal interface material disposed in thermal conductive communication with the die and a heat spreader disposed in thermal conductive communication with the thermal interface material.... Agent: Intel Corporation C/o Intellevate, LLC

20080315406 - Integrated circuit package system with cavity substrate: An integrated circuit package system includes a base substrate having a base substrate cavity, attaching a junction integrated circuit package over the base substrate with a portion of the junction integrated circuit package in the base substrate cavity, and attaching a base integrated circuit over the junction integrated circuit package... Agent: Law Offices Of Mikio Ishimaru

20080315408 - Semiconductor package, semiconductor package module including the semiconductor package, and methods of fabricating the same: Provided are a semiconductor package and a semiconductor package module including the same. The semiconductor package may include a plurality of semiconductor chips, a plurality of leads connected to pads of the semiconductor chips and externally exposed, wherein the plurality of leads may be classified into a plurality of pin... Agent: Harness, Dickey & Pierce, P.L.C

20080315407 - Three-dimensional circuitry formed on integrated circuit device using two-dimensional fabrication: Stackable integrated circuit devices include an integrated circuit die having interconnect pads on an active (front) side, the die having a front side edge at the conjunction of the front side of the die and a sidewall of the die, and a back side edge at the conjunction of back... Agent: Haynes Beffel & Wolfeld LLP

20080315409 - Direct edge connection for multi-chip integrated circuits: The present invention allows for direct chip-to-chip connections using the shortest possible signal path.... Agent: Mark Wardas IBM Corporation

20080315413 - Electronic device manufacturing method and electronic device: There are provided the steps of forming a bump 104 on an electrode pad 103 provided on a semiconductor chip 101, forming a low-modulus insulating layer 120 on the semiconductor chip 101 and laminating, on the low-modulus insulating layer 120, a high-modulus insulating layer 121 having a higher elastic modulus... Agent: Drinker Biddle & Reath (dc)

20080315414 - Electronic device manufacturing method and electronic device: There are provided the steps of forming a bump 104 having a protruded portion 104B on an electrode pad 103 formed on a substrate 101A, forming an insulating layer 105 on the substrate 101A and exposing a part of the protruded portion 104B to an upper surface of the insulating... Agent: Drinker Biddle & Reath (dc)

20080315411 - Integrated circuit package system employing device stacking: An integrated circuit package system that includes: providing an electrical interconnect system including an inner lead-finger system and an outer lead-finger system; stacking a first device, a second device, and a third device between and over the electrical interconnect system; connecting the first device and the second device to the... Agent: Law Offices Of Mikio Ishimaru

20080315412 - Package structure with flat bumps for integrate circuit or discrete device and method of manufacture the same: The invention discloses a novel package structure of integrate circuit or discrete device and packaging method, and includes the lead pins adjacent to the island; another metal layer formed at the bottom of the island; another metal layer formed at the bottom of lead pins; chip mounted on the island;... Agent: Heslin Rothenberg Farley & Mesiti PC

20080315415 - Semiconductor device and manufacturing method thereof: The present invention provides a double-sided electrode package of a structure excellent in the reliability of connection and moisture resistance to another package, which is capable of being manufactured simply and at low cost. The present invention also provides a double-sided electrode package of a structure capable of forming inner... Agent: Rabin & Berdo, PC

20080315410 - Substrate including barrier solder bumps to control underfill transgression and microelectronic package including same: A microelectronic substrate and a microelectronic package including the substrate and a die bonded thereto. The substrate includes a substrate panel having a die-side surface including a die-attach region; a system of interconnects extending through the substrate panel and adapted to allow a connection of the substrate to external circuitry;... Agent: Laleh Jalali Intel Corporation

20080315416 - A semiconductor package with passive elements embedded within a semiconductor chip: A semiconductor package includes a semiconductor chip having bonding pads formed on a top surface and a first via hole and a second via hole formed on both-side edges; a passive element formed within the first via hole; a via wiring formed within the second via hole; a first wiring... Agent: Ladas & Parry LLP

20080315417 - Chip package: A chip package includes a patterned conductive layer, a first solder resist layer, a second solder resist layer, a chip, bonding wires and a molding compound. The patterned conductive layer has a first surface and a second surface opposite to each other. The first solder resist layer is disposed on... Agent: J C Patents, Inc.

20080315419 - Chromium/titanium/aluminum-based semiconductor device contact: A contact to a semiconductor including sequential layers of Cr, Ti, and Al is provided, which can result in a contact with one or more advantages over Ti/Al-based and Cr/Al-based contacts. For example, the contact can: reduce a contact resistance; provide an improved surface morphology; provide a better contact linearity;... Agent: Hoffman Warnick LLC

20080315418 - Methods of post-contact back end of line through-hole via integration: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes... Agent: Larry Williams

20080315421 - Die backside metallization and surface activated bonding for stacked die packages: Methods and apparatus to provide die backside metallization and/or surface activated bonding for stacked die packages are described. In one embodiment, an active metal layer of a first die may be coupled to an active metal layer of a second die through silicon vias and/or a die backside metallization layer... Agent: Caven & Aghevli C/o Intellevate, LLC

20080315420 - Metal pad formation method and metal pad structure using the same: A metal pad formation method and metal pad structure using the same are provided. A wider first pad metal is formed together with a first metal. A dielectric layer is then deposited thereon. A first opening and a second opening are formed in the dielectric layer to respectively expose the... Agent: Bacon & Thomas, PLLC

20080315422 - Methods and apparatuses for three dimensional integrated circuits: Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and... Agent: Larry Williams

20080315423 - Semiconductor device: A semiconductor device includes a carrier, a chip including a first face having a contact area, where the chip is attached to the carrier such that the contact area faces away from the carrier, a copper connector configured for attachment to the contact area, and a solder material configured to... Agent: Dicke, Billig & Czaja

20080315424 - Structure and manufactruing method of chip scale package: A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting... Agent: Mou-shiung Lin Science-based Industrial Park

20080315425 - Semiconductor devices and methods for fabricating the same: Semiconductor devices and methods of fabricating the same are disclosed. An illustrated semiconductor device fabricating method includes forming a titanium and titanium-nitride (Ti/TiN) metal layer on a lower oxide layer; forming an aluminum metal layer on the Ti/TiN metal layer; forming an indium tin oxide (ITO) layer on the aluminum... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080315426 - Metal cap with ultra-low k dielectric material for circuit interconnect applications: An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal... Agent: Scully, Scott, Murphy & Presser, P.C.

20080315427 - Substrate bonding method and semiconductor device: (a) A first Sn absorption layer (5) is formed on the principal surface of a first substrate (1), the first Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. (b) A second Sn absorption layer (17)... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080315429 - Method for improving the selectivity of a cvd process: A method of forming a noble metal cap on a conductive material embedded in a dielectric material in an interconnect structure. The method includes the step of contacting (i) a conductive material having a bare upper surface partially embedded in a dielectric material and (ii) vapor of a noble metal... Agent: Vazken A. Alexanian IBM Corporation

20080315428 - Thin film transistor and display device, and method for manufacturing thereof: The present invention discloses a display device and a manufacturing method thereof by which a manufacturing process can be simplified. Further, the present invention discloses technique for manufacturing a pattern such as a wiring into a desired shape with good controllability. A method for forming a pattern for constituting the... Agent: Nixon Peabody, LLP

20080315431 - Mounting substrate and manufacturing method thereof: A mounting substrate and a method of manufacturing the mounting substrate. The mounting substrate can include an insulation layer, a bonding pad buried in one side of the insulation layer in correspondence with a mounting position of a chip, and a circuit pattern electrically connected to the bonding pad. By... Agent: Staas & Halsey LLP

20080315430 - Nanowire vias: A method of fabricating an integrated circuit including arranging a nanowire with a first end portion thereof at a first contact surface of a first electrical contact and with a second end portion sticking up from the first contact surface, and embedding at least part of the nanowire in dielectric... Agent: Dickstein Shapiro, LLP

20080315432 - Electrical shielding in stacked dies by using conductive die dttach adhesive: In example embodiment, there is an integrated circuit (IC) device (5) assembled in a package (5) having a plurality of die including a first device (20) and at least one additional device (30). The IC comprises a substrate (10). A first device die (20), having bonding pads including ground connections,... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080315435 - Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice: An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area... Agent: Trask Britt, P.C./ Micron Technology

20080315433 - Self-aligned wafer or chip structure, self-aligned stacked structure and methods for fabircating the same: A self-aligned wafer or chip structure including a substrate, at least one first concave base, at least one second concave base, at least one connecting structure and at least one bump is provided. The substrate has a first surface and a second surface, and at least one pad is formed... Agent: Jianq Chyun Intellectual Property Office

20080315434 - Wafer level surface passivation of stackable integrated circuit chips: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of... Agent: Haynes Beffel & Wolfeld LLP

20080315436 - Semiconductor wafer that supports multiple packaging techniques: Methods, systems, and apparatuses for semiconductor wafers and integrated circuit chip packaging techniques are provided. A wafer is fabricated that supports multiple different packaging techniques. The wafer is formed to have a plurality of integrated circuit regions. A first plurality of terminals is formed on a surface of the wafer... Agent: Fiala & Weaver, P.l.l.c. C/o Intellevate

20080315437 - Tape wiring substrate and chip-on-film package using the same: A chip-on-film package may include a tape wiring substrate, a semiconductor chip mounted on the tape wiring substrate, and a molding compound provided between the semiconductor chip and the tape wiring substrate. The tape wiring substrate may include a film having upper and lower surfaces. Vias may penetrate the film.... Agent: Harness, Dickey & Pierce, P.L.C

20080315438 - Semiconductor device including a stress buffer: An integrated circuit includes a first surface configured for mounting to a carrier, an active area of the integrated circuit spaced from the first surface, a bond pad disposed over and in electrical communication with the active area, and a ceramic inorganic stress-buffering layer disposed between the active area and... Agent: Dicke, Billig & Czaja

20080315439 - Quad flat non-leaded chip package: A Quad Flat Non-leaded (QFN) chip package including a patterned conductive layer, a first solder resist layer, a chip, a plurality of bonding wires and a molding compound is provided. The patterned conductive layer has a first surface and a second surface opposite to each other. The first solder resist... Agent: J C Patents, Inc.

20080315440 - Method of manufacturing a plurality of semiconductor devices and carrier substrate: Individual devices (100) are locally attached to a carrier substrate (10), so that they can be removed therefrom individually. This is achieved through the use of a patterned release layer, particularly a layer that is removable through decomposition into gaseous or vaporized decomposition products. The mechanical connection between the carrier... Agent: Philips Intellectual Property & Standards

20080308783 - Memory devices and methods of manufacturing the same: Memory devices and methods of manufacturing the same are provided. In a memory device, a memory-switch structure is formed between a first and second electrode. The memory-switch structure includes a memory resistor and a switch structure. The switch structure controls current supplied to the memory resistor. A memory region of... Agent: Harness, Dickey & Pierce, P.L.C

20080308782 - Semiconductor memory structures: A semiconductor structure includes a transistor over a substrate, the transistor comprising a gate and a contact region, which is adjacent to the gate and within the substrate. A first dielectric layer is over the contact region. A contact structure is within the first dielectric layer and over the contact... Agent: Duane Morris LLP (tsmc)IPDepartment

20080308781 - Structure and process for a resistive memory cell with separately patterned electrodes: Methods of making MIM structures and the resultant MIM structures are provided. The method involves forming a top electrode layer over a bottom electrode and an insulator on a substrate and forming a top electrode by removing portions of the top electrode layer. The bottom electrode, insulator, or combination thereof... Agent: Amin, Turocy & Calvin, LLP

20080308785 - Phase change memory device and method of forming the same: Provided are a phase change memory device and a method for forming the phase change memory device. The method includes forming a phase change material layer by providing reactive radicals to a substrate. The reactive radicals may comprise precursors for a phase change material and nitrogen.... Agent: Myers Bigel Sibley & Sajovec

20080308784 - Variable resistance non-volatile memory cells and methods of fabricating same: Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming an ohmic layer on an upper surface of a conductive structure and extending away from the structure along at least a portion of a sidewall of... Agent: Myers Bigel Sibley & Sajovec

20080308786 - Manufacturing method for the integration of nanostructures into microchips: State-of-the-art synthesis of carbon nanostructures (25) by chemical vapor deposition involve heating a catalyst material to high temperatures up 700-1000° C. in a furnace and flowing hydrocarbon gases through the reactor over a period of time. In order to enable a self assembly of nanostructures (25) on microchips (10) without... Agent: Marshall, Gerstein & Borun LLP

20080308787 - Light emitting diode having active region of multi quantum well structure: Disclosed is a light emitting diode (LED) having an active region of a multiple quantum well structure in which well layers and barrier layers are alternately laminated between a GaN-based N-type compound semiconductor layer and a GaN-based P-type compound semiconductor layer. The LED includes a middle barrier layer having a... Agent: H.c. Park & Associates, PLC

20080308788 - Quantum dot semiconductor device: A quantum dot semiconductor device includes an active layer having a plurality of quantum dot layers each including a composite quantum dot formed by stacking a plurality of quantum dots and a side barrier layer formed in contact with a side face of the composite quantum dot. The stack number... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080308793 - Composition and organic insulator prepared using the same: Disclosed are a composition including a silane-based organic/inorganic hybrid material having a multiple bond and one or more organic metal compounds and/or one or more organic polymers, an organic insulator including the composition, an organic thin film transistor (OTFT) including the organic insulator and an electronic device including the OTFT.... Agent: Harness, Dickey & Pierce, P.L.C

20080308792 - Display device: A single-crystal semiconductor layer which is separated from a single-crystal semiconductor substrate, and bonded to and provided over a supporting substrate is used, whereby a transistor having uniform characteristics can be formed. A reference circuit having a bipolar transistor is provided, whereby temperature dependence of a driving transistor which is... Agent: Nixon Peabody, LLP

20080308789 - Field effect transistor and method of producing the same: An object of the present invention is to provide a field effect transistor showing high field-effect mobility and a high ON/OFF ratio, which can be produced simply by using a porphyrin compound with excellent crystallinity and orientation. The field effect transistor according to the present invention transistor contains at least... Agent: Fitzpatrick Cella Harper & Scinto

20080308794 - Light-emitting device, electronic device, and manufacturing method of light-emitting device: The present invention provides a light-emitting element and a light-emitting device which have high contrast, and specifically, provides a light-emitting device whose contrast is enhanced, not by using a polarizing plate but using a conventional electrode material. Reflection of external light is suppressed by provision of a light-absorbing layer included... Agent: Eric Robinson

20080308791 - Organic field effect transistor and making method: In an organic field effect transistor with an electrical conductor-insulator-semiconductor structure, the semiconductor layer is made of an organic compound, and the insulator layer is made of a polymer obtained through polymerization or copolymerization of 2-cyanoethyl acrylate and/or 2-cyanoethyl methacrylate.... Agent: Birch Stewart Kolasch & Birch

20080308790 - Organic siloxane film, semiconductor device using the same, flat panel display device, and raw material liquid: Disclosed is materials design for prolonging the duration of the low relative dielectric constant of an organic siloxane film having a low relative dielectric constant. Specifically, in an organic siloxane film having a relative dielectric constant of not more than 2.1, the elemental ratio of carbon to silicon in the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080308796 - Semiconductor device and manufacturing method thereof: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode... Agent: Cook Alex Ltd

20080308797 - Semiconductor device and manufacturing method thereof: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode... Agent: Cook Alex Ltd

20080308795 - Thin film transistor array panel and manufacturing method thereof: The disclosed thin film transistor array panel includes an insulating substrate, a channel layer including an oxide formed on the insulating substrate. A gate insulating is layer formed on the channel layer and a gate electrode is formed on the gate insulating layer. An interlayer insulating layer is formed on... Agent: Macpherson Kwok Chen & Heid LLP

20080308800 - Method of evaluating thermal stress resistance of semiconductor device, and semiconductor wafer having test element: A thermal stress resistance evaluating method of a semiconductor device includes: forming a test circuit on a corner of each of unit regions arranged on a wafer in an array arrangement; forming a TEG chip by dicing a TEG chip region which is determined by grouping at least two of... Agent: Young & Thompson

20080308798 - Semiconductor device: A semiconductor device in which size reduction is possible without functional devices below pads being damaged by stress. The semiconductor device has a plurality of pads above a semiconductor substrate as terminals for external connection. A plurality of dual use pads which are used in both a probing test and... Agent: Mcdermott Will & Emery LLP

20080308801 - Structure for stochastic integrated circuit personalization: A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features.... Agent: Cantor Colburn LLP-ibm Yorktown

20080308799 - Wiring structure and manufacturing method therefor: A wiring structure including a wiring pattern formed in an insulation film on a substrate, a pattern for measurement which is formed in the insulation film on the substrate in a region different from a region where the wiring pattern is formed and is irradiated with measuring light, and a... Agent: Nixon & Vanderhye, PC

20080308802 - Capacitor-less memory: It is an object of the present invention to provide a capacitor-less memory which can prevent a change of a threshold voltage due to flowing out of carriers and improve the memory retention property without a complicated structure. In the capacitor-less memory which uses a transistor, the transistor includes a... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080308807 - Display device and manufacturing method thereof: It is an object to provide a manufacturing method by which display devices can be manufactured in quantity without degrading the characteristics of thin film transistors. In a display device including a thin film transistor in which a microcrystalline semiconductor film, a gate insulating film in contact with the microcrystalline... Agent: Eric Robinson

20080308804 - Semiconductor device and manufacturing method thereof: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode... Agent: Cook Alex Ltd

20080308805 - Semiconductor device and manufacturing method thereof: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode... Agent: Cook Alex Ltd

20080308806 - Semiconductor device and manufacturing method thereof: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode... Agent: Cook Alex Ltd

20080308803 - Thin film transistor and display panel having the same: A thin film transistor includes a gate part which includes a gate electrode and a light blocking electrode extending from the gate electrode. The light blocking electrode prevents a light provided from beneath the gate electrode from being guided to a semiconductor layer. The light blocking electrode is overlapped by... Agent: Macpherson Kwok Chen & Heid LLP

20080308808 - Thin film transistor array substrate and method for fabricating same: An exemplary TFT array substrate includes an insulating substrate, a gate electrode provided on the insulating substrate, a gate insulating layer covering the gate electrode and the insulating layer, an amorphous silicon (a-Si) pattern formed on the gate insulating layer, a heavily doped a-Si pattern formed on the a-Si pattern,... Agent: Wei Te Chung Foxconn International, Inc.

20080308809 - Thin film transistor, method of fabricating the thin film transistor, and display device including the thin film transistor: A thin film transistor (TFT), a method of fabricating the TFT, and a display device including the TFT are provided. The TFT includes a semiconductor layer having a channel region and source and drain regions is crystallized using a crystallization-inducing metal. The crystallization-inducing metal is gettered by either a metal... Agent: Stein, Mcewen & Bui, LLP

20080308811 - Display device: The present invention provides a display device having thin film transistors which can reduce an OFF current in spite of the extremely simple constitution. In the display device having thin film transistors on a substrate, each thin film transistor includes a gate electrode which is connected with a gate signal... Agent: Stanley P. Fisher Reed Smith LLP

20080308810 - Semiconductor device and method for manufacturing the same: The invention relates to a semiconductor device and a method for manufacturing the semiconductor device, which includes: an insulating film over a substrate; a first pixel electrode embedded in the insulating film; an island-shaped single-crystal semiconductor layer over the insulating film; a gate insulating film and a gate electrode; an... Agent: Fish & Richardson P.C.

20080308812 - Ga-containing nitride semiconductor single crystal, production method thereof, and substrate and device using the crystal: A Ga-containing nitride semiconductor single crystal characterized in that (a) the maximum reflectance measured by irradiating the Ga-containing nitride semiconductor single crystal with light at a wavelength of 450 nm is 20% or less and the difference between the maximum reflectance and the minimum reflectance is within 10%, (b) the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080308814 - Gallium nitride substrate and gallium nitride layer formation method: There is disclosed a method for forming a gallium nitride layer of which resistivity is 1×106Ω·cm or more, including steps of: forming a gallium nitride layer containing iron on a substrate; and heating said gallium nitride layer formed on said substrate.... Agent: Drinker Biddle & Reath (dc)

20080308815 - Gan substrate, substrate with an epitaxial layer, semiconductor device, and gan substrate manufacturing method: Affords a GaN substrate from which enhanced-emission-efficiency light-emitting and like semiconductor devices can be produced, an epi-substrate in which an epitaxial layer has been formed on the GaN substrate principal surface, a semiconductor device, and a method of manufacturing the GaN substrate. The GaN substrate is a substrate having a... Agent: Judge Patent Associates

20080308813 - High breakdown enhancement mode gallium nitride based high electron mobility transistors with integrated slant field plate: High breakdown enhancement mode gallium nitride (GaN) based high electron mobility transistors (HEMTs) with integrated slant field plates. These HEMTs have an epilayer structure comprised of AlGaN/GaN buffer. Before the formation of the gate electrode, a passivation layer is deposited, and then the opening for the gate is patterned. The... Agent: Gates & Cooper LLP Howard Hughes Center

20080308816 - Transistors for replacing metal-oxide semiconductor field-effect transistors in nanoelectronics: Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET)... Agent: Dr. William T. Ralston

20080308817 - Galvanic isolator having improved high voltage common mode transient immunity: A galvanic isolator having a transmitter die, a receiver die, and a lead frame is disclosed. The transmitter die includes an LED having first and second contacts for powering the LED, and the receiver die includes a photodetector. The lead frame includes first and second transmitter leads, and first and... Agent: Kathy Manke Avago Technologies Limited

20080308818 - Light-emitting device: A light-emitting device includes an LED chip emitting a primary light, and a phosphor deposited on the LED chip for absorbing the primary light to excite a secondary light, wherein the wavelength of the primary light is shorter than 430 nm and the LED chip is driven by current density... Agent: Bacon & Thomas, PLLC

20080308821 - Dielectric layer and thin film transistor: A dielectric layer including a film with silicon compound contain oxygen and a film with silicon compound contain nitrogen is provided. A ratio of Si—N group absorption intensity to a thickness of the film with silicon compound contain nitrogen in an FTIR spectrum is substantially greater than or substantially equal... Agent: Jianq Chyun Intellectual Property Office

20080308819 - Light-emitting diode arrays and methods of manufacture: Light-emitting diode arrays, methods of manufacture and displays devices are provided. A representative display device includes: a single LED element type having a single type of semiconductor stack; wherein color layers are located on a light output side of the semiconductor stack, and each color layer is arranged to convert... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080308820 - Light-emitting diode arrays and methods of manufacture: A representative LED array includes: a base substrate (BS) and a plurality of light emitting diodes, each of the light emitting diodes comprising a stack of a first contact layer, a semiconductor stack and a second contact layer, the semiconductor stack being on top of the first contact layer, the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080308822 - Package structure of light emitting diode for backlight: A package structure of a light emitting diode for a backlight comprises a long-wavelength LED die and a short-wavelength LED die. The lights emitted from the two LED dies are mixed with the light emitted from excited fluorescent powders for serving as the backlight of a liquid crystal display. A... Agent: Wpat, PC Intellectual Property Attorneys

20080308823 - Overvoltage-protected light-emitting semiconductor device, and method of fabrication: A light-generating semiconductor region is grown by epitaxy on a silicon substrate. The light-generating semiconductor region is a lamination of layers of semiconducting nitrides containing a Group III element or elements. The silicon substrate has a p-type impurity-diffused layer formed therein by thermal diffusion of the Group III element or... Agent: Woodcock Washburn LLP

20080308825 - Encapsulant with scatterer to tailor spatial emission pattern and color uniformity in light emitting diodes: A light emitting device having an encapsulant with scattering features to tailor the spatial emission pattern and color temperature uniformity of the output profile. The encapsulant is formed with materials having light scattering properties. The concentration of these light scatterers is varied spatially within the encapsulant and/or on the surface... Agent: Koppel, Patrick & Heybl

20080308832 - Light-emitting device: A light-emitting device comprises a semiconductor light-emitting stack; and an optical field tuning layer formed on the semiconductor light-emitting stack to change beam angles of the light-emitting device.... Agent: Bacon & Thomas, PLLC

20080308828 - Phosphor-containing adhesive silicone composition, composition sheet formed of the composition, and method of producing light emitting device using the sheet: An addition curable adhesive silicone composition containing a phosphor dispersed uniformly therein is provided. The dispersive state of the phosphor remains stable over time. The composition, in an uncured state at room temperature, is either a solid or a semisolid, and is therefore easy to handle, and is suited to... Agent: Birch Stewart Kolasch & Birch

20080308827 - Process for preparing a bonding type semiconductor substrate: The process comprises a step of growing epitaxially mixed crystals of a compound semiconductor represented by the composition formula Inx(Ga1-yAly)1-xP on a GaAs substrate 12 to form an epi-wafer having an n-type cladding layer 14 (0.45≦x≦0.50, 0≦y≦1), an active layer 15, a p-type cladding layer 16 and a cover layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080308830 - Semiconductor device and manufacturing method therefor: An active layer of an NTFT includes a channel forming region, at least a first impurity region, at least a second impurity region and at least a third impurity region therein. Concentrations of an impurity in each of the first, second and third impurity regions increase as distances from the... Agent: Nixon Peabody, LLP

20080308831 - Semiconductor structure including mixed rare earth oxide formed on silicon: A method (and resultant structure) of forming a semiconductor structure, includes forming a mixed rare earth oxide on silicon. The mixed rare earth oxide is lattice-matched to silicon.... Agent: Mcginn Intellectual Property Law Group, PLLC

20080308824 - Thin flash or video recording light using low profile side emitting led: Very thin flash modules for cameras are described that do not appear as a point source of light to the illuminated subject. Therefore, the flash is less objectionable to the subject. In one embodiment, the light emitting surface area is about 5 mm×10 mm. Low profile, side-emitting LEDs optically coupled... Agent: Patent Law Group LLP

20080308826 - Thin-film transistor, array substrate having the thin-film transistor and method of manufacturing the array substrate: A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are... Agent: Cantor Colburn, LLP

20080308829 - Vertical led with current guiding structure: Techniques for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a metal... Agent: Patterson & Sheridan, L.L.P.

20080308833 - Group iii nitride-based compound semiconductor light-emitting device: The refractive index of a titanium oxide layer is modified by adding an impurity (e.g., niobium (Nb)) thereto within a range where good electrical conductivity is obtained. The Group III nitride-based compound semiconductor light-emitting device of the invention includes a sapphire substrate, an aluminum nitride (AlN) buffer layer, an n-contact... Agent: Mcginn Intellectual Property Law Group, PLLC

20080308834 - Light-emitting diode: A light-emitting diode (LED) is provided, wherein the LED comprises an epitaxial structure, a bonding layer and a composite substrate. The composite substrate comprises a patterned substrate having a pattern and a conductive material layer disposed around the patterned substrate. The bonding layer is formed on the composite substrate. The... Agent: The Webb Law Firm, P.C.

20080308836 - Nitride semiconductor device and method for growing nitride semiconductor crystal layer: There are provided a nitride semiconductor device such as a nitride semiconductor light emitting device, a transistor device or the like, obtained by forming a buffer layer of a single crystal of the nitride semiconductor, in which both a-axis and c-axis are aligned, directly on a substrate lattice-mismatched with the... Agent: Rabin & Berdo, PC

20080308835 - Silicon based solid state lighting: A semiconductor device includes a substrate comprising a first surface having a first orientation and a second surface having a second orientation and a plurality of III-V nitride layers on the substrate, wherein the plurality of III-V nitride layers are configured to emit light when an electric current is produced... Agent: Perkins Coie LLP

20080308837 - Vertical current controlled silicon on insulator (soi) device such as a silicon controlled rectifier and method of forming vertical soi current controlled devices: A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface... Agent: Law Office Of Charles W. Peterson, Jr. Burlington

20080308839 - Insulated gate bipolar transistor: The invention realizes IGBT having an NPT structure which has a smaller variation in switching characteristics and the like and lower on-resistance. In the IGBT of the invention, by setting a ratio of a width of a trench to an interval between the trenches within a range of 1 to... Agent: Morrison & Foerster LLP

20080308838 - Power switching transistors: In an embodiment, a integrated semiconductor device includes a first Vertical Junction Field Effect Transistor (VJFET) having a source, and a gate disposed on each side of the first VJFET source, and a second VJFET transistor having a source, and a gate disposed on each side of the second VJFET... Agent: Andrews Kurth LLP Intellectual Propery Department

20080308840 - Photo-field effect transistor and integrated photodetector using the same: A photo-FET based on a compound semiconductor including a channel layer formed on a substrate constituting a current path between source and drain electrodes, serving as part of a photodiode and a photosensitive region. A back-gate layer that serving as a substrate-side depletion layer formation layer is disposed between the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080308842 - Forming silicides with reduced tailing on silicon germanium and silicon: A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; an epitaxial region having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the epitaxial region comprises an impurity of a first conductivity type; a first portion of the semiconductor... Agent: Slater & Matsil, L.L.P.

20080308841 - Semiconductor substrate, semiconductor device and method of manufacturing a semiconductor substrate: A semiconductor substrate (1) of the present invention is made of nitrides of group III metals having wurtzite crystal structure and is grown in vapor phase either on a (0001) oriented foreign substrate (2), lattice mismatched to the semiconductor substrate materials, or on existing (0001) oriented highly dislocated layer (3)... Agent: Fay Sharpe LLP

20080308843 - Field effect transistor having a compositionally graded layer: A GaN heterojunction FET has an AlxGa1-xN first graded layer and an AlyGa1-yN second graded layer, which are formed sequentially on a channel layer. The Al mole fraction x of the first graded layer decreases linearly from, for example, 0.2 at an interface of the first graded layer with the... Agent: Birch Stewart Kolasch & Birch

20080308844 - Spin transistor using perpendicular magnetization: A spin transistor useful for device miniaturization and high-density integration is provided. The spin transistor includes: a semiconductor substrate including a channel layer; ferromagnetic source and drain disposed on the semiconductor substrate to be separated from each other and to be magnetized in a direction perpendicular to a surface of... Agent: Wells St. John P.s.

20080308845 - Heterogeneous group iv semiconductor substrates: Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual... Agent: Myers Bigel Sibley & Sajovec

20080308846 - Device and method for detecting biomolecules using adsorptive medium and field effect transistor: A device for detecting biomolecules includes: a semiconductor substrate; a source region and a drain region separately provided at the substrate; a chamber formed at the substrate including a region between the source region and the drain region, the chamber configured to contain a sample including the biomolecules; and an... Agent: Cantor Colburn, LLP

20080308847 - Method of making (100) nmos and (110) pmos sidewall surface on the same fin orientation for multiple gate mosfet with dsb substrate: A method of forming an integrated circuit device that includes a plurality of MuGFETs is disclosed. A PMOS fin of a MuGFET is formed on a substrate. The PMOS fin includes a channel of a first surface of a first crystal orientation. A NMOS fin of another MuGFET is formed... Agent: Texas Instruments Incorporated

20080308848 - Semiconductor device: A semiconductor device according to an aspect of the invention comprises an n-type FinFET which is provided on a semiconductor substrate and which includes a first fin, a first gate electrode crossing a channel region of the first fin via a gate insulating film in three dimensions, and contact regions... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080308849 - Semiconductor apparatus and complimentary mis logic circuit: A configuration is adopted comprising an NchMOS transistor 1 equipped with an insulating isolation layer 4 providing insulation and isolation using an SOI structure, and a capacitor formed using an insulating film, with a silicon substrate B being made thin and substrate capacitance being reduced. The NchMOS transistor 1 is... Agent: Greenblum & Bernstein, P.L.C

20080308850 - Transistor with reduced charge carrier mobility and associated methods: A device includes a first transistor including a fin and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. In a method, the fin of the first transistor is treated to have a lower... Agent: Schwegman, Lundberg & Woessner / Infineon

20080308851 - Photoelectric conversion element having a semiconductor and semiconductor device using the same: A semiconductor device, particularly, a photoelectric conversion element having a semiconductor layer is demonstrated. The photoelectric conversion element of the present invention comprises, over a substrate, a photoelectric conversion layer and first and second electrodes which are electrically connected to the photoelectric conversion layer. The photoelectric conversion element further comprises... Agent: Eric Robinson

20080308852 - Image sensor circuits including shared floating diffusion regions: An image sensor can include a plurality of photoelectric conversion elements arranged in a matrix. A plurality of floating diffusion regions can be shared by respective corresponding pairs of adjacent photoelectric conversion elements. A plurality of charge-transmission transistors can respectively correspond to the photoelectric conversion elements, where each of the... Agent: Myers Bigel Sibley & Sajovec

20080308853 - Tunnel transistor having spin-dependent transfer characteristics and non-volatile memory using the same: A MISFET the channel region of which is a ferromagnetic semi-conductor has a feature that the drain current can be controlled by the gate voltage and a feature that the transfer conductance can be controlled by the relative directions of magnetization in the ferromagnetic channel region and the ferromagnetic source... Agent: Oliff & Berridge, PLC

20080308854 - Semiconductor memory device and fabrication method thereof: A semiconductor memory device including a cylinder hole extended in a thickness direction of an insulating film; a capacitor configured from a lower electrode, which is formed on an inner surface of the cylinder hole, and an upper electrode, which is formed on a surface of the lower electrode via... Agent: Young & Thompson

20080308855 - Memory devices with isolation structures and methods of forming and programming the same: Memory devices and methods of programming and forming the same are disclosed. In one embodiment, a memory device has memory cells contained within dielectric isolation structures to isolate them from at least those memory cells in communication with other bit lines, such as to facilitate forward-bias write operations. The dielectric... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20080308856 - Integrated circuit having a fin structure: Embodiments of the invention relate generally to a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement, an integrated circuit, a cell arrangement, and a memory module. In an embodiment of the invention, a method for manufacturing an integrated circuit having a cell arrangement is provided,... Agent: Slater & Matsil, L.L.P.

20080308859 - Semiconductor device and method for manufacturing the same: A semiconductor device including a semiconductor substrate, and a memory cell and a peripheral circuit provided on the semiconductor substrate, the memory cell having a first insulating film, a first electrode layer, a second insulating film, and a second electrode layer provided on the semiconductor substrate in order, and the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080308858 - Semiconductor devices and electronic systems comprising floating gate transistors and methods of forming the same: Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In... Agent: Trask Britt, P.C./ Micron Technology

20080308857 - Systems and methods for self convergence during erase of a non-volatile memory device: A non-volatile memory device implements self-convergence during the normal erase cycle through control of physical aspects, such as thickness, width, area, etc., of the dielectric layers in the gate structure as well as of the overall gate structure. Self-convergence can also be aided during the normal erase cycle by ramping... Agent: Baker & Mckenzie LLP Patent Department

20080308860 - Method of forming a pattern for a semiconductor device, method of forming a charge storage pattern using the same method, non-volatile memory device and methods of manufacturing the same: A method of forming a semiconductor device pattern, a method of forming a charge storage pattern, a non-volatile memory device including a charge storage pattern and a method of manufacturing the same are provided. The method of forming the charge storage pattern including forming a trench on a substrate, and... Agent: Harness, Dickey & Pierce, P.L.C

20080308861 - Dual gate finfet: A circuit has a fin supported by a substrate. A source is formed at a first end of the fin and a drain is formed at a second end of the fin. A pair of independently accessible gates are laterally spaced along the fin between the source and the drain.... Agent: Schwegman, Lundberg & Woessner / Infineon

20080308862 - Mos transistor and method of manufacturing a mos transistor: The MOS transistor (1) of the invention comprises a gate electrode (10), a channel region (4), a drain contact region (6) and a drain extension region (7) mutually connecting the channel region (4) and the drain contact region (6). The MOS transistor (1) further comprises a shield layer (11) which... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080308863 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a buried isolation pattern between an active pattern on which transistors are formed and a substrate. The active pattern has adjacent sections each extending longitudinally in a first direction. A field isolation pattern is interposed between the adjacent sections of the active pattern. The buried isolation... Agent: Volentine & Whitt PLLC

20080308864 - Asymmetrical mos transistor and fabrication method thereof and devices using the same: An asymmetrical MOS transistor having characteristics of a variable resistor and a transistor is provided. The asymmetrical MOS transistor comprises a substrate, a gate structure, a pair of spacers, a pair of offset spacers, a source region, a drain region, and an extension region. Herein, the extension region is disposed... Agent: J C Patents, Inc.

20080308865 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a structure of a gate electrode/a high-k dielectric insulating film containing aluminum and having a dielectric constant greater than that of a silicon oxide film/the silicon oxide film/a silicon substrate, and is provided with a diffusion layer formed by diffusing an aluminum atom or an aluminum... Agent: Pearne & Gordon LLP

20080308866 - Semiconductor device and method for manufacturing the same: To provide a semiconductor device having lower junction capacitance, which can be manufactured with lower power consumption through a simpler process as compared with conventional, a semiconductor device includes a base substrate; a semiconductor film formed over the base substrate; a gate insulating film formed over the semiconductor film; and... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080308867 - Partially depleted soi field effect transistor having a metallized source side halo region: Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an... Agent: Scully, Scott, Murphy & Presser, P.C.

20080308868 - High voltage metal oxide semiconductor transistor and fabrication method thereof: A high voltage metal oxide semiconductor includes a doped substrate, two first isolation structures, a gate structure, a source region, a drain region, two second isolation structures, and two drift regions. The two first isolation structures are respectively disposed in the doped substrate. The gate structure is disposed between parts... Agent: J C Patents, Inc.

20080308869 - Semiconductor device which has mos structure and method of manufacturing the same: The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080308870 - Integrated circuit with a split function gate: An integrated circuit is disclosed. One embodiment provides a field-effect transistor including a gate electrode, a channel region and a first source/drain region. The gate electrode may include a main section determining a first flat band voltage between the gate electrode and the channel region and a first lateral section... Agent: Dicke, Billig & Czaja

20080308871 - Semiconductor device and method for producing the same: A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity... Agent: Mcdermott Will & Emery LLP

20080308872 - Cmos transistors with differential oxygen content high-k dielectrics: An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An... Agent: Scully, Scott, Murphy & Presser, P.C.

20080308874 - Complementary asymmetric high voltage devices and method of fabrication: An asymmetric semiconductor device (10) and method of forming the same in which 25V devices can be fabricated in processes with gate oxide thicknesses designed for 2.75 or 5.5V maximum operation. The device includes: a shallow trench isolation (STI) region (12) that forms a dielectric between a drain region (18)... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080308875 - Mask rom device, semiconductor device including the mask rom device, and methods of fabricating mask rom device and semiconductor device: A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off -cell junction... Agent: Marger Johnson & Mccollom, P.C.

20080308877 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device includes a semiconductor substrate; a first gate insulation film formed on the semiconductor substrate; a second gate insulation film formed on the semiconductor substrate; a first gate electrode formed on the first gate insulation film and fully silicided; and a second gate electrode formed on the second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080308876 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a first gate structure on a first region of a substrate, the first gate structure including sequentially formed a first insulating layer pattern, a first conductive layer pattern, and a first polysilicon layer pattern doped with first impurities of a first conductivity type, a first source/drain... Agent: Lee & Morse, P.C.

20080308873 - Semiconductor device with discontinuous cesl structure: A semiconductor device using a CESL (contact etch stop layer) to induce strain in, for example, a CMOS transistor channel, and a method for fabricating such a device. A stress-producing CESL, tensile in an n-channel device and compressive in a p-channel device, is formed over the device gate structure as... Agent: Slater & Matsil, L.L.P.

20080308878 - Semiconductor architecture having field-effect transistors especially suitable for analog applications: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that... Agent: Ronald J. Meetin, Attorney At Law

20080308879 - Mos structures with contact projections for lower contact resistance and methods for fabricating the same: MOS structures with contact projections for lower contact resistance and methods for fabricating such MOS structures have been provided. In an embodiment, a method comprises providing a semiconductor substrate, fabricating a gate stack on the substrate, and forming a contact projection on the substrate. Ions of a conductivity-determining type are... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080308880 - Semiconductor device: In one aspect of the present invention, a semiconductor device, may include a fin formed of a semiconductor layer protruding straight from a semiconductor substrate, the fin includes straight portion which extends in a direction in a plan view and a bent portion which extends in a direction different from... Agent: Amin, Turocy & Calvin, LLP

20080308882 - Application of gate edge liner to maintain gate length cd in a replacement gate transistor flow: A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove... Agent: Lsi Corporation

20080308881 - Method for controlled formation of a gate dielectric stack: The present disclosure relates to methods for forming a gate stack in a MOSFET device and to MOSFET devices obtainable through such methods. In exemplary methods described herein, a rare-earth-containing layer is deposited on a layer of a silicon-containing dielectric material. Before these layers are annealed, a gate electrode material... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080308883 - Monitoring pattern for silicide: Provided is a monitoring pattern for a silicide that may include a plurality of poly pads, a plurality of N-well regions and P-well regions, active regions, and a poly gate line. The plurality of poly pads are disposed on a semiconductor substrate. The plurality of N-well regions and P-well regions... Agent: Sherr & Vaughn, PLLC

20080308884 - Fabrication of inlet and outlet connections for microfluidic chips: A method of making a fluid communication channel between a micro mechanical structure provided on a front side of a device and the back side of said device is described. It includes making the required structural components by lithographic and etching processes on said front side. Holes are then drilled... Agent: Young & Thompson

20080308885 - Magnetic random access memory and fabricating method thereof: A magnetic random access memory including a substrate, a first conductor layer, a magnetic layer, an insulating layer, a dielectric layer, two contacts and a second conductor layer is provided. The first conductor layer is disposed on the substrate. The magnetic layer is disposed on the first conductor layer. The... Agent: J C Patents, Inc.

20080308887 - Semiconductor memory device: A semiconductor memory device includes first to third wiring layers formed above a semiconductor substrate, extending in a first direction, and sequentially arranged in a second direction perpendicular to the first direction, a plurality of active areas formed in the semiconductor substrate, and extending in a direction oblique to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080308886 - Semiconductor sensor: This application relates to a semiconductor sensor comprising a carrier that comprises a first surface and a second surface; a sensor chip attached to the first surface; attachment means on the second surface; and mould material applied over the sensor chip and the attachment means.... Agent: Infineon Technologies Ag Patent Department

20080308888 - Image sensor and method for manufacturing thereof: An image sensor includes a semiconductor substrate having a pixel region and a peripheral circuit region. An interlayer dielectric layer has metal wirings and a pad formed over the semiconductor substrate. A lower electrode is selectively formed over the metal wirings. A photo diode is formed over the interlayer dielectric... Agent: Sherr & Vaughn, PLLC

20080308889 - Image sensing module and method for packaging the same: An image sensing module and a method for packaging the same are disclosed. Meanwhile, the packaging method includes the steps of a) providing a substrate; b) forming plural passive devices on the substrate; c) adhering a chip on the substrate and bonding thereon; d) providing a ring frame, wherein the... Agent: Bacon & Thomas, PLLC

20080308890 - Back-illuminated type imaging device and fabrication method thereof: Light is illuminated from a back-surface side of a silicon substrate 4. A back-illuminated type imaging device 100 reads out, from a front-surface side of the silicon substrate 4, charges that are generated in the silicon substrate 4 in response to the illuminated light, so as to perform imaging. The... Agent: Birch Stewart Kolasch & Birch

20080308891 - Ultra low dark current pin photodetector: A photodetector and a method for fabricating a photodetector. The photodetector may include a substrate, a buffer layer formed on the substrate, and an absorption layer formed on the buffer layer for receiving incident photons and generating charged carriers. An N-doped interface layer may be formed on the absorption layer,... Agent: Duke W. Yee

20080308892 - Semiconductor component and method for producing a metal-semiconductor contact: A semiconductor component including a first layer (10) of a semiconductor material as a substrate, a second layer (12) running on said first layer (10), and at least two intermediate layers (14, 16) made of the materials of the first and second layers running between the first and second layer,... Agent: Dennison, Schultz & Macdonald

20080308894 - Electro-optical apparatus and a circuit bonding detection device and detection method thereof: This invention provides a circuit bonding detection device, a detection method thereof and an electro-optical apparatus incorporating the circuit bonding detection device. The circuit bonding detection device includes a substrate, a circuit module, a set of sensors, and a detection unit. A plurality of contact pads is disposed on the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080308893 - Imagers with contact plugs extending through the substrates thereof and imager fabrication methods: Methods for fabricating photoimagers, such as complementary metal-oxide-semiconductor (CMOS) imagers, include fabricating image sensing elements, transistors, and other low-elevation features on an active surface of a fabrication substrate, and fabricating contact plugs, conductive lines, external contacts, and other higher-elevation features on the back side of the fabrication substrate. Imagers with... Agent: Trask Britt, P.C./ Micron Technology

20080308895 - Semiconductor device: A semiconductor device and fabricating method thereof are provided. A dual gate oxide layer is formed by thermal oxidation after carrying out a prescribed pre-processing on an STI edge, which results in a high quality oxide layer by thermal oxidation and a uniformly maintained gate oxide layer thickness of a... Agent: Mckenna Long & Aldridge LLP

20080308896 - Integrated circuit device comprising a gate electrode structure and corresponding method of fabrication: The present invention provides an integrated circuit device comprising a semiconductor substrate and a gate electrode structure on the semiconductor substrate having at least one insulating layer of dielectric material on said semiconductor substrate and a metal layer on said at least one insulating layer, said metal layer containing niobium... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20080308897 - Substrate for manufacturing semiconductor device and manufacturing method thereof: A substrate with which a semiconductor device with excellent electric characteristics and high reliability can be manufactured is provided. An aspect of the invention is a method for manufacturing a substrate for manufacturing a semiconductor device: a first silicon oxide film, a silicon nitride film, and a second silicon oxide... Agent: Eric Robinson

20080308898 - Plasma excited chemical vapor deposition method silicon/oxygen/nitrogen-containing-material and layered assembly: A method for producing a layer arrangement is disclosed. A layer of oxygen material and nitrogen material is formed over a substrate that has a plurality of electrically conductive structures and/or over a part of a surface of the electrically conductive structures. The layer is formed using a plasma-enhanced chemical... Agent: Slater & Matsil LLP

20080308899 - Triangular space element for semiconductor device: Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first... Agent: Haynes And Boone, LLP

20080308900 - Electrical fuse with sublithographic dimension: A photolithography mask contains at least one sublithographic assist feature (SLAF) such that the image of the fuselink shape on a photoresist contains a constructive interference portion and two neck portions. The width of the constructive interference portion is substantially the same as a critical dimension of the lithography tool... Agent: Scully, Scott, Murphy & Presser, P.C.

20080308901 - Integrated circuit having a thin passivation layer that facilitates laser programming, and applications thereof: An integrated circuit having a thin passivation layer that facilitates laser programming, and applications thereof. In an embodiment, the integrated circuit includes a metal layer that has at least one fuse. A passivation layer is deposited over the metal layer. The passivation layer has a thickness that is less than... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080308902 - Semiconductor device: This disclosure concerns a semiconductor device comprising a switching transistor provided on a semiconductor substrate; an interlayer dielectric film formed on the switching transistor; a ferroelectric capacitor including an upper electrode, a ferroelectric film, and a lower electrode formed on the interlayer dielectric film; a contact plug provided in the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080308903 - Polycrystalline thin film bipolar transistors: A semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide is described. The emitter region and collector... Agent: Dugan & Dugan, PC

20080308904 - P-doped region with improved abruptness: A method of manufacturing a semiconductor device. The method comprises providing C atoms in a semiconductor substrate. The method also comprises implanting In atoms and p-type dopants into a predefined region of the substrate that is configured to have the carbon atoms. The method further comprises thermally annealing the semiconductor... Agent: Texas Instruments Incorporated

20080308905 - Semi-conductor device, and method of making the same: A semiconductor device and a method for manufacturing the device are disclosed. The device, and the method for making the device, includes the steps of forming a gate oxide film on a semiconductor substrate; forming a gate poly silicon layer on the gate oxide film; and implanting deuterium ions over... Agent: Workman Nydegger

20080308909 - Epitaxial wafers, method for manufacturing of epitaxial wafers, method of suppressing bowing of these epitaxial wafers and semiconductor multilayer structures using these epitaxial wafers: A technique for suppressing the bowing of an epitaxial wafer is provided. The epitaxial wafer is prepared by successively epitaxially growing a target group III-nitride layer, an interlayer and another group III-nitride layer on a substrate with a buffer layer. The interlayer is mainly composed of a mixed crystal of... Agent: Burr & Brown

20080308906 - Gan substrate, substrate with epitaxial layer, semiconductor device, and method of manufacturing gan substrate: A GaN substrate having a large diameter of two inches or more by which a semiconductor device such as a light emitting element with improved characteristics such as luminance efficiency, an operating life and the like can be obtained at low cost industrially, a substrate having an epitaxial layer formed... Agent: Drinker Biddle & Reath (dc)

20080308908 - Nitride semiconductor device and method for producing nitride semiconductor device: A nitride semiconductor device of the present invention includes: a nitride semiconductor laminated structure comprising an n type first layer, a second layer containing a p type dopant laminated on the first layer, and an n type third layer laminated on the second layer, each layer of the nitride semiconductor... Agent: Rabin & Berdo, PC

20080308907 - Planar nonpolar m-plane group iii nitride films grown on miscut substrates: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a... Agent: Gates & Cooper LLP Howard Hughes Center

20080308910 - Seminconductor device including through-wafer interconnect structure: Semiconductor devices including through-wafer interconnects are disclosed. According to an embodiment of the present invention, a semiconductor device may comprise a substrate having a first surface and a second, opposing surface, and a through-wafer interconnect extending into the first surface of the substrate. The through-wafer interconnect may include an electrically... Agent: Trask Britt, P.C./ Micron Technology

20080308911 - Semiconductor device and manufacturing method thereof: An object is to provide a semiconductor device with improved reliability in which a defect stemming from an end portion of a semiconductor layer provided in an island shape is prevented, and a manufacturing method thereof. Over a substrate having an insulating surface, an island-shaped semiconductor layer is formed, a... Agent: Nixon Peabody, LLP

20080308912 - Emi shielded semiconductor package: An EMI shielded semiconductor package is provided. The package includes a substrate and a chip disposed on the substrate. The chip is electrically connected to the substrate by a plurality of bonding wires. At least one shielding conductive block is formed on the substrate and electrically connected to the ground... Agent: Lowe Hauptman Ham & Berner, LLP

20080308913 - Stacked semiconductor package and method of manufacturing the same: A stacked semiconductor package includes a first semiconductor package, a second semiconductor package and a conductive connection member. The first semiconductor package includes a first semiconductor chip, a first lead frame having first outer leads that are electrically connected to the first semiconductor chip, and a first molding member formed... Agent: Marger Johnson & Mccollom, P.C.

20080308914 - Chip package: A chip package including a circuit substrate having an opening, a first chip, first bonding wires, a component, a first adhesive layer and a molding compound is provided. The first chip has a first active surface and a first rear surface opposite to the first active surface, the first chip... Agent: J C Patents, Inc.

20080308915 - Chip package: A chip package including a circuit substrate, a first chip, first bonding wires, a component, a first adhesive layer and a molding compound is provided. The first chip has a first active surface, a first rear surface and first bonding pads, the first rear surface is adhered on the circuit... Agent: J C Patents, Inc.

20080308916 - Chip package: A chip package including a carrier having an opening, a first chip, bumps, a second chip, bonding wires, a first adhesive layer and a molding compound is provided. The first chip and the second chip are disposed at two opposite side of the carrier. The bumps are disposed between the... Agent: J C Patents, Inc.

20080308917 - Embedded chip package: An electronic assembly is disclosed. One embodiment includes at least one semiconductor chip and a package structure embedding the semiconductor chip. The package structure includes at least one conducting line extending into an area of the package structure outside of the outline of the chip. The electronic assembly further includes... Agent: Dicke, Billig & Czaja

20080308919 - Hollow sealing structure and manufacturing method for hollow sealing structure: A manufacturing method for a hollow sealing structure, includes, a process for filling a recessed portion in a principal surface of a substrate with a first sacrificial layer, a process for forming a functional element portion on the principal surface of the substrate, a process for forming a second sacrificial... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080308918 - Semiconductor package with passive elements: The semiconductor package includes a plate having first via patterns formed on a center portion and second via patterns formed on edge portions; a connection wiring formed on a top surface of the plate to connect at least one first via patterns to at least one second via patterns; a... Agent: Ladas & Parry LLP

20080308920 - System and method of fabricating micro cavities: A system and method for manufacturing micro cavity packaging enclosure at the wafer level using MEMS (MicroElectroMechanical Systems) process, wherein micro cavities are formed from epoxy-bonded single-crystalline silicon wafer as its cap, epoxy and deposited metal or insulator as at least part of its sidewall, on substrate wafers.... Agent: Chang-feng Wan

20080308921 - Molded reconfigured wafer, stack package using the same, and method for manufacturing the stack package: A stack package includes at least two stacked package units. Each package unit comprises semiconductor chips having bonding pads on upper surfaces thereof; a molding part formed to surround side surfaces of the semiconductor chips; through-electrodes formed in the molding part; and re-distribution lines formed to connect the through-electrodes and... Agent: Ladas & Parry LLP

20080308922 - Method for packaging semiconductors at a wafer level: A method for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: lithographically forming in a material disposed on the surface portion of the semiconductor wafer device-exposing openings to exposed the devices and electrical contacts pads openings to expose electrical contact... Agent: Raytheon Company C/o Daly, Crowley, Mofford & Durkee, LLP

20080308923 - High performance chip carrier substrate: A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved closer to the edge of... Agent: John A. Jordan, Esq.

20080308924 - Circuit module having force resistant construction: Impact resistant circuit modules are disclosed for enclosing a die having a sensor area. Preferred modules include a flexible circuit and a die coupled thereto. The flexible circuit is preferably folded over compressible material to help absorb applied forces. A gap may be provided between sides of the die and... Agent: Fish & Richardson P.C.

20080308925 - Fabricating process and structure of thermal enhanced substrate: A fabricating process of a thermal enhanced substrate is provided for fabricating thermal conduction blocks to increase the heat dissipation area. First, a metallic substrate having a first surface and a second surface opposite to the first surface is provided. A first shallow trench with a first depth is then... Agent: J C Patents, Inc.

20080308926 - Heat dissipation package structure and method for fabricating the same: A heat dissipation package structure and method for fabricating the same are disclosed, which includes mounting and electrically connecting a semiconductor chip to a chip carrier through its active surface; mounting a heat dissipation member having a heat dissipation section and a supporting section on the chip carrier such that... Agent: Edwards Angell Palmer & Dodge LLP

20080308927 - Semiconductor device with heat sink plate: A semiconductor chip is mounted on an upper surface of the heat sink plate that is provided with a plurality of heat releasing terminals on a lower surface of the heat releasing. A plurality of electric signal terminals are regularly disposed in a lattice-like manner around the heat sink plate.... Agent: Hamre, Schumann, Mueller & Larson P.C.

20080308928 - Image sensor module with a three-dimensional die-stacking structure: This invention provides an image sensor module with a three-dimensional die-stacking structure. By filling a conductive material into through silicon vias within at least one image sensor die, and into via holes within an insulating layer, vertical electrical connections are formed between the image sensor die and an image processor... Agent: Birch Stewart Kolasch & Birch

20080308931 - Electronic structures including barrier layers defining lips: Forming an electronic structure may include forming a seed layer on a substrate, and forming a mask on the seed layer. The mask may include an aperture therein exposing a portion of the seed layer, and a barrier layer may be formed on the exposed portion of the seed layer.... Agent: Myers Bigel Sibley & Sajovec

20080308930 - Semiconductor device mounting structure, manufacturing method, and removal method of semiconductor device: A semiconductor device mounting structure includes a semiconductor device whose electrodes are aligned on its one main face; a circuit board having board electrodes electrically connected to the electrodes of the semiconductor device by solder bumps; and curable resin applied between at least the side face of the semiconductor device... Agent: Mcdermott Will & Emery LLP

20080308929 - Semiconductor device, chip package and method of fabricating the same: A semiconductor device has a chip, a first bump electrode, a conductive wire and a second bump electrode. The chip has at least one contact pad, and the first bump electrode is formed on the contact pad. The conductive wire is disposed on an active surface of the chip and... Agent: Lowe Hauptman Ham & Berner, LLP

20080308933 - Integrated circuit package system with different connection structures: An integrated circuit package system is provided including forming an external interconnect having a tip without a die-attach paddle; mounting a first integrated circuit device structure having a conductive ball over the tip; connecting a first wire between the first integrated circuit device structure and under the tip; and encapsulating... Agent: Law Offices Of Mikio Ishimaru

20080308935 - Semiconductor chip package, semiconductor package including semiconductor chip package, and method of fabricating semiconductor package: Provided are a semiconductor chip package, a semiconductor package, and a method of fabricating the same. In some embodiments, the semiconductor chip packages includes a semiconductor chip including an active surface, a rear surface, and side surfaces, bump solder balls provided on bonding pads formed on the active surface, and... Agent: Marger Johnson & Mccollom, P.C.

20080308932 - Semiconductor package structures: A semiconductor structure includes a plurality of solder structures between a first substrate and a second substrate. A first encapsulation material is substantially around a first one of the solder structures and a second encapsulation material is substantially around a second one of the solder structures. The first one and... Agent: Duane Morris LLP (tsmc)IPDepartment

20080308934 - Solder bump interconnect for improved mechanical and thermo-mechanical performance: An apparatus and method for a semiconductor package including a bump on input-output (IO) structure are disclosed involving a device pad, an under bump metal pad (UBM), a polymer, and a passivation layer. The shortest distance from the center of the device pad to its outer edge, and the shortest... Agent: Greenberg Traurig LLP (la)

20080308936 - Method and sturcture for self-aligned device contacts: Disclosed are embodiments of a semiconductor structure with a partially self-aligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080308937 - Copper-free semiconductor device interface and methods of fabrication and use thereof: Embodiments of copper-free semiconductor device interfaces and methods for forming and/or utilizing the same are provided herein. In some embodiments, a semiconductor structure may include a substrate having an exposed copper-containing feature; and a copper-free interface disposed over the substrate and providing a conductive interconnect between the copper-containing feature and... Agent: Raymond R. Moser Jr., Esq. MoserIPLaw Group

20080308938 - Under bump metallurgy structure and wafer structure using the same and method of manufacturing wafer structure: An under bump metallurgy structure and wafer structure using the same and method of manufacturing wafer structure are provided. The under bump metallurgy structure includes an adhesion layer, a barrier layer and a wetting layer. The adhesion layer is disposed on a bonding pad of a wafer. The barrier layer... Agent: Bacon & Thomas, PLLC

20080308940 - Lateral current carrying capability improvement in semiconductor devices: A semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device.... Agent: Schmeiser, Olsen & Watts

20080308939 - Semiconductor device and method for fabricating semiconductor device: A semiconductor device includes a plurality of first group wiring layers laminated on a substrate, and each of the first group wiring layers having a wire formed with a first minimum wire width and a main dielectric film portion; and a plurality of second group wiring layers laminated on a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080308941 - Hierarchical 2t-dram with self-timed sensing: An embodiment of the present invention is method of forming an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit... Agent: Cantor Colburn LLP-ibm Yorktown

20080308942 - Semiconductor wiring structures including dielectric cap within metal cap layer: Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring line, and a local dielectric cap positioned within a portion of the metal cap layer and in contact with the... Agent: Hoffman Warnick LLC

20080308943 - Wiring structure and semiconductor device, and their fabrication methods: A fabrication method for a wiring structure of the present invention includes: a process of forming a conductive wiring layer; a process of forming a wiring pattern on the wiring layer; a process of forming an insulative wiring interlayer film between wires of the wiring pattern; and a process of... Agent: Sughrue Mion, PLLC

20080308944 - Method for eliminating duo loading effect using a via plug: Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is characterized by a first thickness. The method also includes... Agent: Townsend And Townsend And Crew, LLP

20080308945 - Semiconductor integrated circuit: A semiconductor integrated circuit according to an example of the present invention includes a first interconnect extending in a first direction, a second interconnect arranged over the first interconnect and extending in a second direction intersecting the first direction, a first via for connecting a first contact part of the... Agent: SprinkleIPLaw Group

20080308947 - Die offset die to die bonding: A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge... Agent: Paul J. Winters

20080308946 - Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices: Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releaseably attached to a temporary carrier, a back side, and a plurality of first dies at the active... Agent: Perkins Coie LLP Patent-sea

20080308948 - Wafer-to-wafer alignments: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other... Agent: Schmeiser, Olsen & Watts

20080308949 - Flip chip package and method for manufacturing the same: A flip chip package realizes a fine pitch and improves the reliability of a bump joint and a method for manufacturing the same. The flip chip package includes a printed circuit board having a plurality of electrode terminals on one surface thereof; a semiconductor chip located on the printed circuit... Agent: Ladas & Parry LLP

20080308951 - Semiconductor package and fabrication method thereof: A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes providing a carrier board; forming a plurality of metal bumps on the carrier board; covering on the carrier board a resist layer having openings for exposure of the metal bumps, the openings being smaller than the... Agent: Edwards Angell Palmer & Dodge LLP

20080308950 - Semiconductor package and method for manufacturing thereof: A semiconductor package, which includes: a first substrate, on which a pre-designed pattern is formed; a first chip, mounted by a flip chip method on one side of the first substrate; a first molding, covering the first substrate and the first chip; a first via, which penetrates the first molding,... Agent: Staas & Halsey LLP

20080308952 - Method for reliably positioning solder on a die pad for attaching a semiconductor chip to the die pad and molding die for solder dispensing apparatus: The rotational orientation of a die pad about its longitudinal axis is determined. The desired rotational orientation of a semiconductor chip to be attached to the die pad is determined. A molding die is provided which comprises a body with a cavity disposed in a bottom surface. The rotational orientation... Agent: Dicke, Billig & Czaja, PLLC

20080308953 - Fabricated adhesive microstructures for making an electrical connection: An integrated circuit chip has one or more electrically conductive nano-fibers formed on one or more contact pads of the integrated circuit chip. The one or more electrically conductive nano-fibers are configured to provide an adhesive force by intermolecular forces and establish an electrical connection with one or more contact... Agent: Morrison & Foerster LLP

20080308954 - Semiconductor device and method of forming the same: A semiconductor device includes conductive lines on a substrate, sidewall spacers on sidewalls of the conductive lines, contacts between the conductive lines, the contacts separated from the conductive lines by the sidewall spacers and electrically connected to active regions of the substrate, contact pads on and electrically connected to corresponding... Agent: Lee & Morse, P.C.

20080303013 - Integrated circuit including spacer defined electrode: An integrated circuit includes a contact, a first spacer, and a first electrode including a first portion and a second portion. The second portion contacts the contact and is defined by the first spacer. The integrated circuit includes a second electrode and resistivity changing material between the second electrode and... Agent: Dicke, Billig & Czaja

20080303014 - Vertical phase change memory cell and methods for manufacturing thereof: The present invention discloses a vertical phase-change-memory (PCM) cell, comprising a stack of a bottom electrode (5) contacting a first layer of phase change material (14), a dielectric layer (12) having an opening (13), a second layer of phase change material (6) in contact with the first layer of phase... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080303015 - Memory having shared storage material: An integrated circuit includes a bit line and a plurality of access devices coupled to the bit line. The integrated circuit includes a plate of phase change material and a plurality of contacts. Each contact is coupled to an access device and contacting the plate of phase change material. A... Agent: Dicke, Billig & Czaja

20080303016 - Phase change memory devices employing cell diodes and methods of fabricating the same: Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the... Agent: F. Chau & Associates, LLC

20080303017 - Group iii nitride compound semiconductor light-emitting device: A group III nitride compound semiconductor light-emitting device according to the present invention includes: an active layer (105) comprised of a group III nitride compound semiconductor; a current blocking layer (108) which is formed on the active layer (105) and has a striped aperture (108a); a superlattice layer (p-type layer... Agent: Sughrue Mion, PLLC

20080303018 - Silicon-based light emitting diode for enhancing light extraction efficiency and method of fabricating the same: Due to the indirect transition characteristic of silicon semiconductors, the light extraction efficiency of a silicon-based light emitting diode is lower than that of a compound semiconductor-based light emitting diode. For this reason, there are difficulties in practically using and commercializing silicon-based light emitting diodes developed so far. Provided is... Agent: Rabin & Berdo, PC

20080303019 - Side chain-containing type organic silane compound, thin film transistor and method of producing thereof: A side chain-containing type organic silane compound represented by the formula (I) R—SiX1X2X3 wherein R represents a π-electron conjugate type organic residue composed of 3 to 10 units whose units are a group derived from a monocyclic aromatic hydrocarbon, a group derived from a monocyclic heterocyclic compound or the combination... Agent: Nixon & Vanderhye, PC

20080303020 - Thin film transistor, flat panel display device having the same, and associated methods: A thin film transistor includes a gate electrode, a first insulating layer on the gate electrode, a semiconductor layer on the gate electrode and separated from the gate electrode by the first insulating layer, the semiconductor layer including a channel region corresponding to the gate electrode, a source region, and... Agent: Lee & Morse, P.C.

20080303021 - Optimized thermally conductive plate and attachment method for enhanced thermal performance and reliability of flip chip organic packages: Disclosed are thermally conductive plates. Each plate is configured such that a uniform adhesive-filled gap may be achieved between the plate and a heat generating structure when the plate is bonded to the heat generating structure and subjected to a temperature within a predetermined temperature range that causes the heat... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080303022 - Optical sensor element, optical sensor device and image display device using optical sensor element: A highly sensitive optical sensor element, and a switch element such as a sensor driver circuit are formed on the same insulating substrate by using an LTPS planar process to provide a low cost area sensor (optical sensor device) incorporating the sensor driver circuit and the like or an image... Agent: Stanley P. Fisher Reed Smith LLP

20080303024 - Array substrate for fringe field switching mode liquid crystal display device and method of fabricating the same: An array substrate for a fringe field switching mode liquid crystal display device comprises a gate line on a substrate; a gate electrode connected to the gate line; a gate insulating layer on the gate line and the gate electrode; a semiconductor layer on the gate insulating layer and corresponding... Agent: Mckenna Long & Aldridge LLP

20080303023 - Organic light-emitting display apparatus: An organic light-emitting display apparatus includes a plurality of pixels arranged on a substrate, each pixel includes: a display region including at least one pixel thin film transistor and an organic light-emitting device electrically connected to the pixel thin film transistor; and a sensor region electrically connected to the display... Agent: Stein, Mcewen & Bui, LLP

20080303025 - Thin film transistor array panel: A thin film transistor array panel according to an embodiment of the present invention includes: a gate electrode; a semiconductor layer; a gate insulating layer disposed between the gate electrode and the semiconductor layer; a source electrode connected to the semiconductor layer; and a drain electrode connected to the semiconductor... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080303026 - Semiconductor device and method for manufacturing the device: A semiconductor device and a method for manufacturing the same that includes forming a gate insulating film on a semiconductor substrate; and then forming a doped polysilicon layer on the gate insulating film; and then forming a first metal layer on the doped polysilicon layer; and then forming a metal... Agent: Sherr & Vaughn, PLLC

20080303027 - Semiconductor device made by the method of producing hybrid orientnation (100) strained silicon with (110) silicon: There is provided a method of manufacturing a semiconductor device. In one aspect, the method includes providing a strained silicon layer having a crystal orientation located over a semiconductor substrate having a different crystal orientation. A mask is placed over a portion of the strained silicon layer to leave an... Agent: Texas Instruments Incorporated

20080303028 - Thin film transistor and method of manufacturing the same: A thin film transistor comprising a gate electrode, a gate insulating layer, an active layer, and source and drain electrodes is provided. The gate electrode overlaps with a channel region of the active layer, the gate insulating layer is provided between the gate electrode and the active layer, the source... Agent: Sheridan Ross PC

20080303030 - Display device and method of manufacturing the same: A semiconductor device includes an insulating substrate and a TFT element disposed on the substrate. The TFT element includes a gate electrode, a gate insulating film, a semiconductor layer, and a source electrode and a drain electrode arranged in that order on the insulating substrate. The semiconductor layer includes an... Agent: Stanley P. Fisher Reed Smith LLP

20080303029 - Structure, semiconductor device, tft driving circuit, panel, display and sensor for maintaining microstructure, methods for fabricating the structure, the semiconductor device, the tft driving circuit, the panel, the display and the sensor: A method for fabricating a structure according to the present invention includes the steps of: forming a groove in a substrate, dropping a solution in which microstructures such as nanowires are dispersed into the groove and the step of evaporating the solution to arrange the microstructures in the groove in... Agent: Mcdermott Will & Emery LLP

20080303031 - Vented die and package: A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.... Agent: HorizonIPPte Ltd

20080303032 - Bulk mono-crystalline gallium-containing nitride and its application: Bulk monocrystalline gallium-containing nitride, grown on the seed at least in the direction essentially perpendicular to the direction of the seed growth, essentially without propagation of crystalline defects as present in the seed, having the dislocation density not exceeding 104/cm2 and considerably lower compared to the dislocation density of the... Agent: Smith Patent Office

20080303035 - Compound semiconductor film, light emitting film, and manufacturing method thereof: Provided are a compound semiconductor film which is manufactured at a low temperature and exhibits excellent p-type conductivity, and a light emitting film in which the compound semiconductor film and a light emitting material are laminated and with which high-intensity light emission can be realized. The compound semiconductor film has... Agent: Fitzpatrick Cella Harper & Scinto

20080303033 - Formation of nitride-based optoelectronic and electronic device structures on lattice-matched substrates: A method of forming an AlInGaN alloy-based electronic or optoelectronic device structure on a nitride substrate and subsequent removal of the substrate. An AlInGaN alloy-based electronic or optoelectronic device structure formed on a nitride substrate is freed from the substrate on which it was grown.... Agent: Intellectual Property / Technology Law

20080303034 - Light-emitting gallium nitride-based iii-v group compound semiconductor device and manufacturing method thereof: A light-emitting gallium nitride-based III-V group compound semiconductor device and a manufacturing method thereof are disclosed. The light emitting device includes a substrate, a n-type semiconductor layer over the substrate, an active layer over the n-type semiconductor layer, a p-type semiconductor layer over the active layer, a conductive layer over... Agent: Rosenberg, Klein & Lee

20080303036 - Method of manufacturing semiconductor device and semiconductor device manufactured thereof: Methods of manufacturing a semiconductor device including a semiconductor substrate and a hetero semiconductor region including a semiconductor material having a band gap different from that of the semiconductor substrate and contacting a portion of a first surface of the semiconductor substrate are taught herein, as are the resulting devices.... Agent: Young & Basile, P.C.

20080303037 - Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby: A method of making a thin film transistor comprising a thin film semiconductor element comprised of a transparent zinc-oxide-based semiconductor material, wherein spaced apart first and second contacts in contact with said material are positioned on either side of a channel in the thin film semiconductor element such that the... Agent: Andrew J. Anderson Patent Legal Staff

20080303038 - Module comprising radiation-emitting semiconductor bodies: A module comprising a regular arrangement of individual radiation-emitting semiconductor bodies (1) which are applied on a mounting area (6) of a carrier (2), wherein a wire connection is fitted between two adjacent radiation-emitting semiconductor bodies (1) on a top side, opposite to the mounting area (6), of the two... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20080303040 - Backlight module and light emitting diode package structure therefor: A LED package structure including a carrier, LED chips, and a package body is provided. The carrier defines a cave with two opposite first side walls, two opposite second side walls and a rectangular bottom surface. An included angle between the first side wall and the bottom surface differs from... Agent: J C Patents, Inc.

20080303041 - Light emitting element, manufacturing method thereof and light emitting module using the same: A light emitting element, and a manufacturing method thereof, and a light emitting module using the same are provided. The light emitting element includes a first light emitting diode (LED), a second LED, a first electrode and a second electrode. The first LED is disposed on a substrate and has... Agent: Bacon & Thomas, PLLC

20080303039 - Mount for a semiconductor light emitting device: A mount for a semiconductor device includes a carrier, at least two metal leads disposed on a bottom surface of the carrier, and a cavity extending through a thickness of the carrier to expose a portion of the top surfaces of the metal leads. A semiconductor light emitting device is... Agent: Patent Law Group LLP

20080303047 - Light-emitting diode device and manufacturing method therof: A light-emitting diode (LED) device and manufacturing methods thereof are disclosed, wherein the LED device comprises a substrate, a plurality of micro-lens, a reflector, a first conductivity type semiconductor layer, an active layer, a second conductivity type semiconductor layer, a first electrode and a second electrode. The substrate has a... Agent: Bacon & Thomas, PLLC

20080303042 - Method for manufacturing substrate for semiconductor light emitting element and semiconductor light emitting element using the same: A light emitting element having a recess-protrusion structure on a substrate is provided. A semiconductor light emitting element 100 has a light emitting structure of a semiconductor 20 on a first main surface of a substrate 10. The first main surface of the substrate 10 has substrate protrusion portion 11,... Agent: Birch Stewart Kolasch & Birch

20080303049 - Methods for coupling diamond structures to photonic devices: Various embodiments of the present invention are directed to methods for coupling semiconductor-based photonic devices to diamond. In one embodiment of the present invention, a photonic device is optically coupled with a diamond structure. The photonic device comprises a semiconductor material and is optically coupled with the diamond structure with... Agent: Hewlett Packard Company

20080303043 - Semiconductor light emitting device: At least one recess and/or protruding portion is created on the surface portion of a substrate for scattering or diffracting light generated in a light emitting region. The recess and/or protruding portion has a shape that prevents crystal defects from occurring in semiconductor layers.... Agent: Morrison & Foerster LLP

20080303045 - Semiconductor light emitting device: A semiconductor light emitting device includes a semiconductor light emitting element, a lead electrically connected to the semiconductor light emitting element, and a resin package covering the semiconductor light emitting element and part of the lead. The resin package includes a lens facing the semiconductor light emitting element. The lead... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20080303046 - Semiconductor light emitting device: A semiconductor light emitting device includes a silicon substrate, a p-type semiconductor layer provided on the silicon substrate, a n-type semiconductor layer provided on the silicon substrate, the n-type semiconductor layer adjoining the p-type semiconductor layer, and a light emitting section formed at a p-n homojunction between the p-type semiconductor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080303048 - Semiconductor light emitting device: This invention discloses a light emitting semiconductor device including a light-emitting structure and an external optical element. The optical element couples to the light-emitting structure circumferentially. In addition, the refractive index of the external optical element is greater than or about the same as that of a transparent substrate of... Agent: Bacon & Thomas, PLLC

20080303044 - Semiconductor light-emitting device: A semiconductor light-emitting device includes a semiconductor light-emitting element which is capable of emitting light, a fluorescent substance which is capable of absorbing at least part of light emitted from the semiconductor light-emitting element and also capable of subsequently converting the wavelength of the absorbed light and emitting the light... Agent: Charles N.j. Ruggiero, Esq. Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20080303051 - Light emitting device and manufacturing method thereof: The present invention provides a light emitting device loaded with a light emitting semiconductor chip with a protective film formed on a light emitting portion, in which the protective film contains a first dielectric film formed of aluminum oxynitride, a second dielectric film formed of silicon nitride or silicon oxynitride,... Agent: Harness, Dickey & Pierce, P.L.C

20080303052 - Light emitting diode package having multiple molding resins: Disclosed is a light emitting diode (LED) package having multiple molding resins. The LED package includes a pair of lead terminals. At least portions of the pair of lead terminals are embedded in a package main body. The package main body has an opening through which the pair of lead... Agent: Marger Johnson & Mccollom, P.C.

20080303050 - Light emitting module: A light emitting module includes a heat dissipation base, a circuit board and a light emitting diode (LED) package. The supporting surface of the heat dissipation base has a positioning structure. The circuit board is disposed on the supporting surface of the heat dissipation base, and it has an opening... Agent: Jianq Chyun Intellectual Property Office

20080303054 - Apparatus for producing group-iii nitride semiconductor layer, method of producing group-iii nitride semiconductor layer, method of producing group-iii nitride semiconductor light-emitting device, group-iii nitride semiconductor light-emitting device ther: An apparatus for producing a group-III nitride semiconductor layer which forms a group-III nitride semiconductor layer on a substrate by a sputtering method, the apparatus including: a first plasma-generating region where a target containing a group-III element is disposed and the target is sputtered to generate material particles formed of... Agent: Sughrue Mion, PLLC

20080303053 - Gan based led having reduced thickness and method for making the same: A device having a carrier, a light-emitting structure, and first and second electrodes is disclosed. The light-emitting structure includes an active layer sandwiched between a p-type GaN layer and an n-type GaN layer, the active layer emitting light of a predetermined wavelength in the active layer when electrons and holes... Agent: The Law Offices Of Calvin B. Ward

20080303055 - Group-iii nitride-based light emitting device: Disclosed is a group-III nitride-based light emitting diode. The group-III nitride-based light emitting diode includes a substrate, an n-type nitride-based cladding layer formed on the substrate, a nitride-based active layer formed on the n-type nitride-based cladding layer, a p-type nitride-based cladding layer formed on the nitride-based active layer, and a... Agent: Macpherson Kwok Chen & Heid LLP

20080303056 - Semiconductor subassemblies with interconnects and methods for manufacturing the same: A semiconductor subassembly is provided for use in a switching module of an inverter circuit for a high power, alternating current motor application. The semiconductor subassembly includes a wafer having first and second opposed metallized faces; a semiconductor switching device electrically coupled to the first metallized face of the wafer... Agent: General Motors Corporation Legal Staff

20080303057 - Semiconductor device and method of manufacturing thereof: A semiconductor device and a method of forming the semiconductor device include a substrate and an n drift layer on the substrate with an insulator film placed between them. A trench is provided in a section between a p base region and an n buffer layer on the surface layer... Agent: Rossi, Kimms & Mcdowell LLP.

20080303058 - Solid state imaging device and method for fabricating the same: A solid state imaging device includes a pixel having a photoelectric conversion element formed on a semiconductor substrate. The photoelectric conversion element includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer and forming a... Agent: Mcdermott Will & Emery LLP

20080303059 - Optical semiconductor device: An n-type InGaAs light absorbing layer and an n-type InP layer (first conductivity type semiconductor layer), which is a window layer, and a multiplication layer are multilayered one atop another on an n-type InP substrate. By selectively diffusing impurities and implanting ions, a p-type InP region second conductivity type semiconductor... Agent: Leydig Voit & Mayer, Ltd

20080303062 - Semiconductor device with strain in channel region and its manufacture method: A first film made of SiGe is formed over a support substrate whose surface layer is made of Si. A gate electrode is formed over a partial area of the first film, and source and drain regions are formed in the surface layer of the support substrate on both sides... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080303060 - Semiconductor devices and methods of manufacturing thereof: Semiconductor devices and methods of manufacturing thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a first material on the semiconductor wafer, and affecting the semiconductor wafer with a manufacturing process. The manufacturing process inadvertently causes a portion of... Agent: Slater & Matsil LLP

20080303061 - Substrate production method and substrate: A process for the manufacture of a substrate having a top layer of a first material and an underlying layer of a second material whose lattice parameter is different from that of the first material. The process includes the steps of conducting an amorphization of the top layer to create... Agent: Winston & Strawn LLP Patent Department

20080303063 - Capacitorless dram and methods of manufacturing the same: Provided are a capacitorless DRAM and methods of manufacturing the same. The capacitorless DRAM may include a substrate including a source, a drain and a channel, a gate on the channel of the substrate, and a hole reserving unit below the channel.... Agent: Harness, Dickey & Pierce, P.L.C

20080303064 - Field-effect semiconductor device and method of fabrication: After creating an electron transit layer on a substrate, a baffle is formed on midpart of the surface of the electron transit layer, the surface having a pair of spaced-apart parts left on both sides of the baffle. A semiconducting material different from that of the electron transit layer is... Agent: Woodcock Washburn LLP

20080303065 - Semiconductor device and display device: It is an object of the invention to provide a thin, lightweight, high performance, and low in cost semiconductor device and a display device by reducing an arrangement area required for a power supply wiring and a ground wiring of a functional circuit and decreasing a drop in power supply... Agent: Nixon Peabody, LLP

20080303066 - Semiconductor device: A semiconductor device is provided which can suppress the deterioration of its reliability caused by liquid soaking into a gap. The semiconductor device includes plural gate electrode layers and an interlayer insulating film. The gate electrode layers are formed so as to extend in the same direction in a planar... Agent: Miles & Stockbridge PC

20080303068 - Field effect transistor using carbon based stress liner: A stress liner for use within a semiconductor structure that includes a field effect device has a dielectric constant less than about 7 and a compressive stress greater than about 5 GPa. The stress liner may be formed of a carbon based material, preferably a tetrahedral amorphous carbon (ta-C) material... Agent: Scully, Scott, Murphy & Presser, P.C.

20080303070 - Preventing cavitation in high aspect ratio dielectric regions of semiconductor device: Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing... Agent: Hoffman Warnick LLC

20080303067 - Split gate memory cell using sidewall spacers: A self-aligned split gate bitcell includes first and second regions of charge storage material separated by a gap devoid of charge storage material. Spacers are formed along sidewalls of sacrificial layer extending above and on opposite sides of the bitcell stack, wherein the spacers are separated from one another by... Agent: Freescale Semiconductor, Inc. Law Department

20080303069 - Two step photoresist stripping method sequentially using ion activated and non-ion activated nitrogen containing plasmas: A two-step nitrogen plasma method is used for stripping a photoresist layer from over a substrate. A first step within the two-step nitrogen plasma method uses a nitrogen plasma with ion activation to form from the photoresist layer over the substrate a treated photoresist layer over the substrate. A second... Agent: Scully, Scott, Murphy & Presser, P.C.

20080303072 - Cmos active pixel sensor: A CMOS active pixel sensor includes a silicon-on-insulator substrate having a silicon substrate with an insulator layer formed thereon and a top silicon layer formed on the insulator layer. A stacked pixel sensor cell includes a bottom photodiode fabricated on the silicon substrate, for sensing light of a longest wavelength;... Agent: Sharp Laboratories Of America, Inc

20080303073 - Cmos image sensor: Provided are a CMOS image sensor in which microlenses are formed in a remaining space in a patterned light shielding layer to improve image sensor characteristics and to protect the microlenses during packaging. The CMOS image sensor may include: a semiconductor substrate; at least one photodiode on or in the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080303071 - Image sensor and method for manufacturing the same: An image sensor and a fabricating method thereof are provided. A pixel area and a peripheral circuit area can have a step difference on a semiconductor substrate. A Complimentary Metal Oxide Semiconductor (CMOS) circuit can be provided on the pixel area, and an interlayer dielectric layer can be provided on... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080303074 - Semiconductor device and its manufacturing method: A semiconductor device is equipped with a plug conductive layer formed in an interlayer dielectric film on a substrate, and a conductive member provided on the plug conductive layer. The semiconductor device further includes a spacer dielectric film formed on the interlayer dielectric film and having a hole section connecting... Agent: Harness, Dickey & Pierce, P.L.C

20080303075 - Method for forming element isolation structure of semiconductor device, element isolation structure of semiconductor device, and semiconductor memory device: A method for forming an element isolation structure of a semiconductor device, includes: a trench forming step of forming a trench on a semiconductor substrate; and a laminating step of forming alternately multilayered film in the trench by sequentially and alternately laminating a plurality of first insulating films that apply... Agent: Young & Thompson

20080303076 - Shallow trench isolation in floating gate devices: The present invention provides a method for manufacturing a floating gate type semiconductor device on a substrate having a surface (2), and a device thus manufactured. The method comprises:—forming, on the substrate surface, a stack comprising an insulating film (4), a first layer of floating gate material (6) and a... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080303077 - Flash memory with 4-bit memory cell and method for fabricating the same: A memory device having at least one memory cell, and each memory cell is configured to store multiple bits. Each bit is stored in a charge storage layer of the memory cell. The memory device can include a double gate structure that can store 4-bits per cell that expands the... Agent: Akin Gump LLP - Silicon Valley

20080303078 - Nonvolatile semiconductor memory device and fabrication method for the same: The fabrication method for a nonvolatile semiconductor memory device having a memory cell area including memory cells and a peripheral circuit area adjacent to the memory cell area and including peripheral transistors, the method including the steps of: (1) forming a first active region in the memory cell area and... Agent: Mcdermott Will & Emery LLP

20080303079 - Non-volatile memory cells including fin structures: A method of forming a non-volatile memory device may include forming a fin protruding from a substrate, forming a tunnel insulating layer on portions of the fin, and forming a floating gate on the tunnel insulting layer so that the tunnel insulating layer is between the floating gate and the... Agent: Myers Bigel Sibley & Sajovec

20080303080 - Back-sided trapped non-volatile memory device: Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with asymmetric tunnel barriers. Embodiments of the present invention allow for direct tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth

20080303082 - Charge-balance power device comprising columnar structures and having reduced resistance: A charge-balance power device formed in an epitaxial layer having a first conductivity type and housing at least two columnar structures of a second conductivity type, which extend through the epitaxial layer. A first surface region of the second conductivity type extends along the surface of the epitaxial layer on... Agent: Graybeal, Jackson, Haley LLP

20080303081 - Device configuration and method to manufacture trench mosfet with solderable front metal: A vertical semiconductor power device includes a plurality of semiconductor power cells connected to a bottom electric terminal disposed on a bottom surface of a semiconductor substrate and at least a top electrical terminal disposed on a top surface of the substrate and connected to the semiconductor power cells. The... Agent: Bo-in Lin

20080303083 - Semiconductor apparatus and production method of the same: In order to provide a highly integrated semiconductor apparatus and a production method thereof which can avoid the floating of a channel portion that causes a problem when constituting a memory cell from three-dimensional transistors, a semiconductor apparatus includes: multiple three-dimensional transistors each of which includes: a first pillar; a... Agent: Sughrue Mion, PLLC

20080303084 - Vertical tunneling transistor: The disclosed embodiments relate to a vertical tunneling transistor that may include a channel disposed on a substrate. A quantum dot may be disposed so that an axis through the channel and the quantum dot is substantially perpendicular to the substrate. A gate may be disposed so that an axis... Agent: Fletcher Yoder (micron Technology, Inc.)

20080303086 - Semiconductor apparatus and method for fabricating the same: A semiconductor apparatus including a trench gate transistor having at least an active region surrounded by a device isolation insulating film; a trench provided by bringing both ends thereof into contact with the device isolation insulating film in the active region; a gate electrode formed in the trench via a... Agent: Mcginn Intellectual Property Law Group, PLLC

20080303085 - Semiconductor device including active pattern with channel recess, and method of fabricating the same: A semiconductor device including an active pattern having a channel recess portion, and a method of fabricating the same, are disclosed. In one embodiment, the semiconductor device includes an active pattern including first active regions and a second active region interposed between the first active regions. The active pattern protrudes... Agent: Marger Johnson & Mccollom, P.C.

20080303087 - Semiconductor device with integrated trench lateral power mosfets and planar devices: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the... Agent: Staas & Halsey LLP

20080303088 - Lateral dmos device structure and fabrication method therefor: A lateral DMOS device and a fabrication method therefor that may include forming a second conductive type well in a first conductive type semiconductor substrate and forming a Schottky contact in contact with the second conductive type well in a Schottky diode region, thereby preventing breakdown of the device due... Agent: Sherr & Vaughn, PLLC

20080303089 - Integrated circuit system with triode: An integrated circuit system includes an integrated circuit, forming a triode near the integrated circuit, and attaching a connector to the triode and the integrated circuit.... Agent: Farjami & Farjami LLP

20080303091 - Semiconductor device and a method of manufacturing the same: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080303090 - Super hybrid soi cmos devices: The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having... Agent: Scully, Scott, Murphy & Presser, P.C.

20080303092 - Asymetrical field-effect semiconductor device with sti region: A high voltage asymmetric semiconductor device (20) that includes a shallow trench isolation (STI) region (22) that forms a dielectric between a drain (34) and a gate (36) to allow for high voltage operation, wherein the STI region includes a lower corner (24) that is shaped, e.g. rounded, to reduce... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080303093 - Semiconductor apparatus: A semiconductor apparatus includes an internal circuit, a CMOS composed of a P-channel MOS transistor with a source connected to a high-potential power supply line and a gate connected to the internal circuit, and an N-channel MOS transistor with a source connected to a low-potential power supply line and a... Agent: Amin, Turocy & Calvin, LLP

20080303094 - Self-aligned split gate memory cell and method of forming: A method of forming a split gate memory device using a semiconductor layer includes patterning an insulating layer to leave a pillar thereof. A gate dielectric is formed over the semiconductor layer. A charge storage layer is formed over the gate dielectric and along first and second sides of the... Agent: Freescale Semiconductor, Inc. Law Department

20080303096 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes forming a transistor, the transistor including a fin having a first side and a second side opposite the first side. The transistor includes a first gate electrode disposed on... Agent: Slater & Matsil LLP

20080303095 - Varying mugfet width to adjust device characteristics: One embodiment of the present invention relates to an integrated circuit that includes a first multi-gate transistor that has a first fin width and a first threshold voltage. The integrated circuit also includes a second multi-gate transistor that has a second fin width that is greater than the first width... Agent: Texas Instruments Incorporated

20080303097 - Power fet with low on-resistance using merged metal layers: In one embodiment, relatively thin but wide metal bus strips overlying a high power FET are formed to conduct current to the source and drain narrow metal strips. A passivation layer is formed over the surface of the FET, and the passivation layer is etched to expose almost the entire... Agent: Patent Law Group LLP

20080303098 - Semiconductor device manufactured using a method to reduce cmp damage to low-k dielectric material: In one aspect, there is provided a method of manufacturing a semiconductor device. The method comprises depositing a barrier layer over a low-k dielectric layer located over a semiconductor substrate over which a metal layer is deposited. A chemical mechanical polish process is used to remove a portion of the... Agent: Texas Instruments Incorporated

20080303100 - Semiconductor device: On a semiconductor substrate, a gate electrode is disposed obliquely across the boundary between an N-type region and a P-type region, and thereby an effective gate width of a region, in which the boundary between the N-type region and the P-type region intersects with the gate electrode, is wider than... Agent: Rabin & Berdo, PC

20080303099 - Semiconductor device and fabrication method thereof: CMISFETs having a symmetrical flat band voltage, the same gate electrode material, and a high permittivity dielectric layer is provided for a semiconductor device including n-MISFETs and p-MISFETs, and a fabrication method thereof, the n-MISFETs including: a first metal oxide layer 20, placed on the 1st gate insulating film 16,... Agent: Fish & Richardson P.C.

20080303101 - Dual stress memorization technique for cmos application: A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a... Agent: Scully, Scott, Murphy & Presser, P.C.

20080303102 - Strained isolation regions: An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the... Agent: Slater & Matsil, L.L.P.

20080303103 - Semiconductor structure and method of forming the same: The present invention provides a semiconductor structure and a method of forming the same. The method includes the steps of providing a substrate, forming a mask layer with an opening on the substrate, locally oxidizing the substrate to form an oxide layer within the opening, removing the oxide layer, such... Agent: Ingrassia Fisher & Lorenz, P.C.

20080303104 - Method of fabricating semiconductor device isolation structure: A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one... Agent: Slater & Matsil, L.L.P.

20080303105 - Dual gate dielectric sram: An SRAM cell structure containing a PFET gate dielectric having a thicker effective oxide thickness (EOT) than an NFET gate dielectric and methods of manufacturing the same is provided. The PFET gate dielectric and the NFET gate dielectric may be silicon oxynitride layers, CVD oxide layers, or high-K dielectric layers... Agent: Scully, Scott, Murphy & Presser, P.C.

20080303106 - Image sensor package and packaging method for the same: An image sensor package includes a substrate, a sensor chip, a frame, a lens element and at least a pair of guide pins. The sensor chip is mounted on the substrate, and has two opposite sides and a sensing region, which has a sensing region central axis. The frame is... Agent: Lowe Hauptman Ham & Berner, LLP

20080303107 - Optical device and method for fabricating the same, camera module using optical device, and electronic equipment mounting camera module: An optical device includes a light receiving element chip having: an active region formed on a principal plane of a substrate and made by arranging a plurality of light receiving pixels; a circuit region disposed around an outer circumference of the active region; a penetrating conductor provided to penetrate the... Agent: Mcdermott Will & Emery LLP

20080303108 - Solid-state imaging device and manufacturing method for the same: Photoelectric converters are arranged two-dimensionally in a semiconductor substrate. A planarizing layer, a light shielding film, a further planarizing layer and condenser lenses are formed sequentially on the semiconductor substrate and the photoelectric converters. The light shielding film has apertures at positions corresponding to the photoelectric conversion devices. Multilayer interference... Agent: Mcdermott Will & Emery LLP

20080303109 - Optoelectronic device chip having a composite spacer structure and method making same: An optoelectronic device chip, and a method for making the chip, are disclosed. The chip comprises a device substrate, an optically transparent upper substrate, and a composite spacer layer which includes an adhesive material and a plurality of particles dispersed in said adhesive material. The distance between the device substrate... Agent: Randy W. Tung Tung & Associates

20080303110 - Integrated circuit package and method for operating and fabricating thereof: The invention provides an integrated circuit package and method for operating and fabricating thereof. The package comprises a transparent substrate having a first surface and a second surface opposite to each other and a semiconductor layer formed on the second surface of the transparent substrate. A photosensitive device is fabricated... Agent: Birch Stewart Kolasch & Birch

20080303111 - Sensor package and method for fabricating the same: The invention discloses a sensor package and a method for fabricating the same. The sensor package includes: a substrate with an opening; a sensor chip disposed in the opening and electrically connected to the substrate; an encapsulant filling spacing between the sensor chip and the opening so as to secure... Agent: Edwards Angell Palmer & Dodge LLP

20080303112 - Imaging device, method of driving imaging device, and method of manufacturing imaging device: An imaging device is provided and includes: a photoelectric conversion layer that has a silicon crystal structure and generates signal charges upon incidence of light; a multiplication and accumulation layer that multiplies the signal charges by a phenomenon of avalanche electron multiplication; and a wiring substrate that reads the signal... Agent: Birch Stewart Kolasch & Birch

20080303113 - Photodetecting device: A method of manufacturing a photodetecting device, by providing a first wafer that includes a photosensitive layer made of a semiconductor material and a second wafer that includes a circuit layer of electronic components, with one of the photosensitive layer or the circuit layer incorporating a field isolation layer; bonding... Agent: Winston & Strawn LLP Patent Department

20080303114 - Semiconductor device having p-n column layer and method for manufacturing the same: A semiconductor device is provided, which includes a substrate; a P-N column layer disposed on the substrate; a second conductivity type epitaxial layer disposed on the P-N column layer. The P-N column layer includes first conductivity type columns and second conductivity type columns, which are alternately arranged. Each column has... Agent: Posz Law Group, PLC

20080303115 - Semiconductor memory device and method of fabricating the same: A semiconductor memory device includes a semiconductor substrate having a dummy cell region adjacent to a memory cell region, a plurality of memory cell transistors, a selective gate transistor, a peripheral circuit transistor, a selective gate line, a contact plug, a dummy contact plug formed in an element forming region... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080303116 - Semiconductor on insulator apparatus: A method and apparatus for producing a relatively thin, relatively uniform semiconductor layer which has improved carrier mobility. In an embodiment, a lattice-matched insulator layer is formed on a semiconductor substrate, and a lattice-matched semiconductor layer is formed on the insulator layer to form a relatively thin, relatively uniform semiconductor... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20080303117 - Integrated circuit with multi-stage matching circuit: An integrated circuit with a multi-stage matching circuit with an inductive conductive structures with a first end and a second end in the integrated circuit and a capacitor structure in the integrated circuit connected to a tap between the ends of the inductive conductive structure between the inductive conductive structure... Agent: Eschweiler & Associates LLC

20080303118 - Process for fabricating a structure for epitaxy without an exclusion zone: A process for fabricating a composite structure for epitaxy, including at least one crystalline growth seed layer of semiconductor material on a support substrate, with the support substrate and the crystalline growth seed layer each having, on the periphery of their bonding face, a chamfer or an edge rounding zone.... Agent: Winston & Strawn LLP Patent Department

20080303119 - Method of manufacturing semiconductor device and semiconductor device: A method of manufacturing a semiconductor device includes forming a metal oxide on a semiconductor substrate, forming a gate electrode film on the metal oxide, and executing a thermal treatment on the semiconductor substrate provided with the metal oxide and the gate electrode film to crystallize the metal oxide.... Agent: Harness, Dickey & Pierce, P.L.C

20080303120 - Semiconductor chip package: A semiconductor chip package includes a main board; a ceramic substrate having a cavity within which at least one chip is electrically mounted, the cavity being placed at a lower portion of the ceramic substrate facing the main board; and a conductive shielding layer provided with a predetermined thickness on... Agent: Mcdermott Will & Emery LLP

20080303121 - Integrated electronic circuitry and heat sink: A multi-layer heatsink module for effecting temperature control in a three-dimensional integrated chip is provided. The module includes a high thermal conductivity substrate having first and second opposing sides, and a gallium nitride (GaN) layer disposed on the first side of the substrate. An integrated array of passive and active... Agent: Akerman Senterfitt

20080303122 - Integrated circuit package system with leaded package: An integrated circuit package system includes: providing a frame; attaching a leaded package having leads adjacent the frame wherein the leads extend towards a side opposite the frame; and applying a package encapsulant over the leaded package having the leads partially exposed opposite the frame.... Agent: Law Offices Of Mikio Ishimaru

20080303123 - Integrated circuit package system with leadfinger: An integrated circuit package system includes: providing a lead terminal; forming a dummy lead near the lead terminal; positioning a base integrated circuit adjacent the lead terminal and the dummy lead; connecting a die connector to the base integrated circuit and the dummy lead; mounting a stackable integrated circuit over... Agent: Law Offices Of Mikio Ishimaru

20080303124 - Lead frame-bga package with enhanced thermal performance and i/o counts: Methods and apparatus for integrated circuit (IC) packages with improved thermal performance and input/output capabilities are described. An integrated circuit (IC) package includes a leadframe, an IC die, a substrate having opposing first and second surfaces, a first wirebond, and a second wirebond. The leadframe includes a die attach pad... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080303127 - Cap-less package and manufacturing method thereof: A cap-less package comprises: a metallic die pad part; a submount mounted on the die pad part; an optical semiconductor element mounted on the submount; an insulating member fixed to the die pad part; a lead electrode inserted in the insulating member; and a wire connecting the lead electrode to... Agent: Leydig Voit & Mayer, Ltd

20080303128 - Leadframe with die pad and leads corresponding thereto: A leadframe includes a die pad and a plurality of leads corresponding to the die pad. The die pad for supporting a die is formed with a plurality of sides, each of the sides having at least one recess portion and at least one protrusion portion. The leads are substantially... Agent: Volentine & Whitt PLLC

20080303126 - Microelectromechanical system package and the method for manufacturing the same: A method for manufacturing a microelectromechanical system package is provided. A plurality of cavities is first formed on a surface of a silicon wafer. The surface of the silicon wafer is then bonded to the microelectromechanical system wafer in such a manner that the active areas of the chips on... Agent: Lowe Hauptman Ham & Berner, LLP

20080303125 - Three-dimensional package structure: A three-dimensional package structure includes an energy storage element, a semiconductor package body and a shielding layer. The semiconductor package body has a plurality of second conductive elements and at least one control device inside. The energy storage element is disposed on the semiconductor package body. The energy storage element... Agent: Thelen LLP

20080303129 - Patterned contact sheet to protect critical surfaces in manufacturing processes: The invention is directed a patterned contact sheet and to a method of bonding a cover wafer to an interposer wafer using the patterned contact sheet having a waffle-like pattern of a plurality of ridges and plurality of wells to form a cover/interposer combination or unit that can be bonded... Agent: Corning Incorporated

20080303131 - Electrically interconnected stacked die assemblies: In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating... Agent: Haynes Beffel & Wolfeld LLP

20080303130 - Package on package structure: A package on package structure includes a first chip package, a second chip package and a conductive film. The first chip package has a portion of first conductive lead which is exposed to the encapsulation body of the first chip package. The conductive film is arranged between the first chip... Agent: Rosenberg, Klein & Lee

20080303132 - Semiconductor chip packages having cavities: Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts.... Agent: Tessera Lerner David Et Al.

20080303133 - Integrated circuit package system with contoured die: An integrated circuit package system is provided including forming an external interconnect, providing a contoured integrated circuit die having both an extension and a base portion with the extension extending beyond the base portion, placing the contoured integrated circuit die with the base portion coplanar with the external interconnect and... Agent: Law Offices Of Mikio Ishimaru

20080303134 - Semiconductor package and method for fabricating the same: A semiconductor package and a method for fabricating the same are disclosed, which includes: providing a carrier board, forming a plurality of metal bumps on the carrier board, forming a metal layer on the carrier board to encapsulate the metal bumps, having at least one semiconductor chip electrically connected to... Agent: Edwards Angell Palmer & Dodge LLP

20080303135 - Pin grid array package substrate including pins having curved pin heads: An electrically conductive pin comprising a pin stern and a pin head attached to the pin stem. The pin head is adapted to be mounted onto a surface of a microelectronic substrate to support the pin stem. The pin head has an underside surface defining a continuous curve configured to... Agent: Laleh Jalali Intel Corporation C/o Intellevate, LLC

20080303136 - Semiconductor device and method for manufacturing same: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material... Agent: Young & Thompson

20080303138 - Insulated gate bipolar transistor: An insulated gate bipolar transistor includes bump pad connectors to provide thermal contact with a heat spreader for dissipating heat away form the insulated gate bipolar transistor.... Agent: Carlson, Gaskey & Olds, P.C.

20080303137 - Semiconductor devices with layers having extended perimeters for improved cooling and methods for cooling semiconductor devices: A semiconductor device is provided, and includes a wafer having first and second opposed metallized major faces and a transistor bonded to the first metallized face of the wafer. The transistor includes a first surface, and the first surface defines a first area. The device further includes a first metal... Agent: General Motors Corporation Legal Staff

20080303139 - Chip-in-slot interconnect for 3d chip stacks: A chip-in-slot interconnect for three-dimensional semiconductor chip stacks, and particularly having the ability of forming edge connections on semiconductor chips, wherein the semiconductor chips are mounted in one or more chip carriers which are capable of being equipped with embedded circuitry. Moreover, provision is made for unique methods for producing... Agent: Scully, Scott, Murphy & Presser, P.C.

20080303140 - Semiconductor device: To provide a semiconductor device which can increase reliability with respect to external force, especially pressing force, while the circuit size or the capacity of memory is maintained. A pair of structure bodies each having a stack of fibrous bodies of an organic compound or an inorganic compound, which includes... Agent: Eric Robinson

20080303141 - Method for etching a substrate and a device formed using the method: The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130... Agent: Texas Instruments Incorporated

20080303142 - Electronic system with vertical intermetallic compound: An electronic system is provided including forming a substrate having a contact, forming a conductive structure over the contact, mounting an electrical device having an external interconnect over the conductive structure, and forming a conductive protrusion from the conductive structure in the external interconnect.... Agent: Law Offices Of Mikio Ishimaru

20080303147 - High-frequency circuit device and radar: A semiconductor chip is provided with a high-frequency circuit. A multi-layer wiring section is comprised of organic material and formed on the semiconductor chip, an outermost layer of the multi-layer wiring section formed with a bump forming portion. A bump is formed on the bump forming portion. The multi-layer wiring... Agent: Oliff & Berridge, PLC

20080303143 - Microelectronic die including locking bump and method of making same: A microelectronic die and a method of providing same. The die includes a die substrate having an active surfaces and a locking bump on the active surface of the die substrate. The locking bump defines a recess adapted to receive therein a solder bump of a package substrate such that... Agent: Laleh Jalali Intel Corporation

20080303148 - Pad arrangement of driver ic chip for lcd and related circuit pattern structure of tab package: Output pads on an integrated circuit (IC) chip are arranged along a first longer side and are arranged along a second longer side with input pads. The output pads are connected to respective output patterns formed on top and bottom surfaces of a base film. All the output patterns may... Agent: Marger Johnson & Mccollom, P.C.

20080303145 - Printed circuit board, printed circuit board manufacturing method and electronic device: According to one embodiment, there is provided a printed circuit board which comprises a printed wiring board, a semiconductor package having a number of solder bonding members arranged on its back side and mounted on the printed wiring board by the solder bonding members being soldered to the wiring board,... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080303146 - Process for manufacturing substrate with bumps and substrate structure: A process for manufacturing a substrate with bumps is provided. First, a metallic substrate having a body and a plurality of conductive elements is provided. Next, a first dielectric layer is formed on the body, and the conductive elements are covered by the first dielectric layer. Then, a plurality of... Agent: J C Patents, Inc.

20080303144 - Structure, method and system for assessing bonding of electrodes in fcb packaging: Structures, methods, and systems for assessing bonding of electrodes in FCB packaging are disclosed. In one embodiment, a method comprises mounting a semiconductor chip with a plurality of first electrodes of a first shape to a mounted portion with a second electrode of a second shape, wherein the second shape... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20080303152 - Contact pad and method of forming a contact pad for an integrated circuit: A contact pad in an integrated circuit is disclosed. The contact pad comprises a flat portion comprising a base of the contact pad; a plurality of projections extending from and substantially perpendicular to the flat portion; and a solder ball attached to the projections and the flat portion. A method... Agent: Xilinx, Inc Attn: Legal Department

20080303149 - Electronic component: An electronic component including, on one surface of a substrate (1), a plurality of circuit elements and external terminals each consisting of a conductive protrusion (9) for the circuit elements is provided with a structure capable of resisting an external force after mounting. Each of the circuit elements includes, as... Agent: Harness, Dickey & Pierce, P.L.C

20080303150 - High-density fine line structure and method of manufacturing the same: A high-density fine line circuit structure mainly includes: a first semiconductor device, an insulated layer on the same surface, an outer circuit layer above the first semiconductor device, and a solder mask formed on the outer circuit layer. The surface which is not covered by the solder mask can be... Agent: Lin & Associates Intellectual Property, Inc.

20080303151 - Method of packaging a microchip: A method of packaging an integrated circuit singulates a wafer to form an integrated circuit, positions the integrated circuit on a carrier, and passivates the integrated circuit after the positioning the integrated circuit on the carrier. At this point, the integrated circuit is secured to the carrier. The method also... Agent: Bromberg & Sunstein LLP

20080303153 - Semiconductor device, manufacturing method thereof, and semiconductor device product: In a semiconductor device, a semiconductor element is built into a resin molded part molded in a flat plate shape. A wiring is electrically connected to the semiconductor element and is disposed on one surface of the resin molded part so that an inner surface side of the wiring is... Agent: Rankin, Hill & Clark LLP

20080303155 - Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures: The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the... Agent: Lsi Corporation

20080303154 - Through-silicon via interconnection formed with a cap layer: An integrated circuit structure and methods for forming the same are provided. The method includes providing a substrate; forming a through-silicon via (TSV) opening extending into the substrate; forming an under-bump metallurgy (UBM) in the TSV opening, wherein the UBM extends out of the TSV opening; filling the TSV opening... Agent: Slater & Matsil, L.L.P.

20080303156 - Semiconductor devices and methods of forming interconnection lines therein: An example disclosed semiconductor device includes a semiconductor substrate, a lower interlayer insulating layer formed on the substrate, a lower wire formed on the lower interlayer insulating layer, and an upper interlayer insulating layer which is formed on the lower interlayer insulating layer and has a via hole to expose... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080303157 - High thermal conductivity substrate for a semiconductor device: A method and apparatus for packaging semiconductor dies for increased thermal conductivity and simpler fabrication when compared to conventional semiconductor packaging techniques are provided. The packaging techniques described herein may be suitable for various semiconductor devices, such as light-emitting diodes (LEDs), central processing units (CPUs), graphics processing units (GPUs), microcontroller... Agent: Patterson & Sheridan, L.L.P.

20080303160 - Method for fabricating dual damascene structures using photo-imprint lithography, methods for fabricating imprint lithography molds for dual damascene structures, materials for imprintable dielectrics and equipment for photo-imprint lithography used in du: The process of producing a dual damascene structure used for the interconnect architecture of semiconductor chips. More specifically the use of imprint lithography to fabricate dual damascene structures in a dielectric and the fabrication of dual damascene structured molds.... Agent: Thomas A. Beck Esq.

20080303158 - Semiconductor integrated circuit device: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080303159 - Thin silicon based substrate: Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20080303161 - Semiconductor device and manufacturing method thereof: A method of manufacturing a semiconductor device includes: preparing a semiconductor element having a first metal layer made of first metal on a surface thereof, and a metal substrate made of second metal, the metal substrate having a fourth metal layer made of fourth metal on a surface thereof, and... Agent: Foley And Lardner LLP Suite 500

20080303162 - Semiconductor device: A semiconductor device includes a layered structure including a first nitride semiconductor layer and a second nitride semiconductor layer that are sequentially formed over a substrate in this order. The second nitride semiconductor layer has a wider bandgap than the first nitride semiconductor layer. A first electrode and a second... Agent: Mcdermott Will & Emery LLP

20080303163 - Through silicon via dies and packages: A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with... Agent: HorizonIPPte Ltd

20080303165 - Circuit arrangement and integrated circuit: A circuit arrangement includes a plurality of type-identical and identically operated active components, or separate sections of an active component, and includes a branched wiring structure for the interconnection of component connections. In each case the wiring end portions lie between a branching point and an input of different components... Agent: Eschweiler & Associates LLC

20080303167 - Device having high aspect-ratio via structure in low-dielectric material and method for manufacturing the same: A method for manufacturing a device having a via structure includes the following steps. A seed metallic layer is formed on a substrate. A patterned metallic-trace layer is formed on the seed metallic layer. A positive-type photoresist layer is formed on the patterned metallic-trace layer and seed metallic layer. The... Agent: Lowe Hauptman Ham & Berner, LLP

20080303164 - Structure and method of reducing electromigration cracking and extrusion effects in semiconductor devices: A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in... Agent: Cantor Colburn LLP - IBM Fishkill

20080303168 - Structure for preventing pad peeling: A structure for preventing pad peeling includes a semiconductor substrate, a dielectric layer, a pad, and a protective layer. The semiconductor substrate has an active circuit structure. The dielectric layer is disposed on the semiconductor substrate and has an opening located in the dielectric layer above an edge position of... Agent: Jianq Chyun Intellectual Property Office

20080303166 - Two-sided substrate lead connection for minimizing kerf width on a semiconductor substrate panel: A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.... Agent: Vierra Magen/sandisk Corporation

20080303169 - Integrated circuit arrangment including vias having two sections, and method for producing the same: An integrated circuit arrangement containing a via is disclosed. The via has an upper section having greatly inclined sidewalls. A lower section of the via has approximately vertical sidewalls. In one embodiment, a liner layer is used as a hard mask in the production of the via and defines the... Agent: Dicke, Billig & Czaja

20080303171 - Semiconductor device and a fabrication process thereof: A semiconductor device formed by the steps of forming a contact hole in an insulation film so as to extend therethrough and so as to expose a conductor body at a bottom part of the contact hole, forming a barrier metal film of tungsten nitride on the bottom part and... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080303170 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device 1 has a through hole 3 formed in a second substrate 2. On the front surface of the semiconductor substrate 2, a first insulating layer 4 is coated having an opening 4a of the same diameter as that of the through hole 3, and a first wiring... Agent: Amin, Turocy & Calvin, LLP

20080303174 - Chip package without core and stacked chip package structure: A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface,... Agent: J C Patents, Inc.

20080303175 - Electronic circuit package: An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080303172 - Method for stacking semiconductor chips and semiconductor chip stack produced by the method: Apparatus for packaging two chips includes, in some embodiments, a first chip having at least one elevation and at least one cutout on a bottom thereof. It also includes a second chip having at least one elevation and at least one cutout on a top thereof. In some embodiments disclosed,... Agent: Schwegman, Lundberg & Woessner / Infineon

20080303173 - Semiconductor device, a method of manufacturing a semiconductor device and a testing method of the same: A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SiP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined... Agent: Miles & Stockbridge PC

20080303176 - Patterned die attach and packaging method using the same: A semiconductor die is attached to a packaging substrate by a patterned layer of conductive metal that includes voids. The voids provide a space into which the metal may expand when heated in order to avoid placing mechanical stress on the bonds caused by mismatches in the thermal coefficients of... Agent: Tung & Associates / Randy W. Tung, Esq.

20080303177 - Bonding pad structure: A bonding pad structure including a bonding pad and a passivation layer is described. The bonding pad is disposed on a chip. The passivation layer covers the bonding pad. In addition, the passivation layer has a first opening exposing a bonding region of the bonding pad and a second opening... Agent: J C Patents, Inc.

20080296551 - Resistance memory element and method of manufacturing the same: A resistance memory element having a pair of electrodes and an insulating film sandwiched between a pair of electrodes includes a plurality of cylindrical electrodes of a cylindrical structure of carbon formed in a region of at least one of the pair of electrodes, which is in contact with the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080296550 - Resistive random access memory device and methods of manufacturing and operating the same: Provided may be a resistive random access memory (RRAM) device and methods of manufacturing and operating the same. The resistive random access memory device may include at least one first electrode, at least one second electrode spaced apart from the at least one first electrode, a first structure including a... Agent: Harness, Dickey & Pierce, P.L.C

20080296552 - Phase change memory cell structures and methods for manufacturing the same: Phase change memory cell structures and methods for fabricating the same are provided. An exemplary embodiment of a phase change memory cell structure includes a first electrode formed over a first dielectric layer. A second dielectric layer is formed over the first electrode. A conductive member is formed through the... Agent: Quintero Law Office, PC

20080296553 - Integrated circuit having contact including material between sidewalls: An integrated circuit includes a bottom electrode, a top electrode, resistivity changing material between the bottom electrode and the top electrode, and a contact contacting the top electrode. The contact includes a bottom and sidewalls. The integrated circuit includes first material between the sidewalls of the contact.... Agent: Dicke, Billig & Czaja

20080296554 - Phase change memory devices and fabrication methods thereof: Phase change memory devices and fabrication methods thereof. A phase change memory device includes an array of phase change memory cells. Each phase change memory cell includes a selecting transistor disposed on a substrate. An upright electrode structure is electrically connected to the selecting transistor. An upright phase change memory... Agent: Quintero Law Office, PC

20080296555 - Lamp with controllable spectrum: An area illumination inorganic electro-luminescent device including a substrate; and an array of one or more commonly addressed, light-emitting elements. Each commonly-addressed, light-emitting element includes a first electrode layer formed over the substrate, one or more light-emitting layers formed over the first electrode layer and a second electrode layer formed... Agent: David Novais Patent Legal Staff

20080296556 - Method for dopant calibration of delta doped multilayered structure: In a calibration method, the relation between dopant concentrations of δ-doping layers in a multilayered semiconductor structure and process parameters is determined S1 based on multiple bulk specimens of the material in which the δ-doping layers are located. A desired dopant concentration is selected S2, and the semiconductor structure with... Agent: Nixon & Vanderhye, PC

20080296559 - Method for fabricating a nanoelement field effect transistor with surrounded gate structure: A nanoelement field effect transistor includes a nanotube disposed on the substrate. A first source/drain region is coupled to a first end portion of the nanoelement and a second source/drain region is coupled to a second end portion of the nanoelement. A recess in a surface region of the substrate... Agent: Slater & Matsil LLP

20080296558 - Method of synthesizing y-junction single-walled carbon nanotubes and products formed thereby: A method has been developed of synthesizing Y-SWNTs with controlled density, position, and growth direction. The process includes patterning a substrate with a solvent solution of catalyst metal ions, dopant metal ions and metal oxide ions, having in a molar ratio of catalyst to dopant in the range of 0.1... Agent: Marshall, Gerstein & Borun LLP

20080296557 - Semiconductor power switch and method for producing a semiconductor power switch: A semiconductor power switch and method is disclosed. In one embodiment the semiconductor power switch has a source contact, a drain contact, a semiconductor structure which is provided between the source contact and the drain contact, and a gate which can be used to control a current flow through the... Agent: Dicke, Billig & Czaja

20080296563 - Carbon nanotube field effect transistor: A nanotube-based flexible field effect transistor and its method of manufacture is provided. The field effect transistor according to the invention comprises at least two contact electrodes, respectively drain and source electrodes, an electrical conduction zone connected to the contact electrodes, said zone comprising a plurality of single-wall carbon nanotubes... Agent: Davidson, Davidson & Kappel, LLC

20080296566 - Making organic thin film transistor substrates for display devices: An organic thin film transistor substrate for a display device includes a gate line, a data line insulated from the gate line, at least two organic thin film transistors, each of which is connected between the gate line and the data line, and both of which are commonly connected to... Agent: Macpherson Kwok Chen & Heid LLP

20080296561 - Memory device and semiconductor device: The present invention provides a memory device which has a memory element having a simple structure in which a composition layer is sandwiched between a pair of conductive layers. With this characteristic, a memory device which is involatile, easily manufactured, and additionally recordable can be provided. A memory device of... Agent: Eric Robinson

20080296560 - Method for manufacturing semiconductor device: The present invention provides a method for manufacturing a semiconductor device which can reduce characteristic deterioration due to impurity incorporation. The present invention also provides a semiconductor device and an electric appliance with reduced characteristic deterioration due to the impurity incorporation. The method for manufacturing a semiconductor device has a... Agent: Nixon Peabody, LLP

20080296565 - Method of fabricating polycrystalline silicon layer, tft fabricated using the same, method of fabricating tft, and organic light emitting diode display device having the same: A method of fabricating a polycrystalline silicon layer includes: forming an amorphous silicon layer on a substrate; crystallizing the amorphous silicon layer into a polycrystalline silicon layer using a crystallization-inducing metal; forming a metal layer pattern or metal silicide layer pattern in contact with an upper or lower region of... Agent: Stein, Mcewen & Bui, LLP

20080296562 - Methods and apparatus for fabricating carbon nanotubes and carbon nanotube devices: Methods and apparatus for fabricating carbon nanotubes (CNTs) and carbon nanotube devices. These include a method of fabricating self-aligned CNT field-effect transistors (FET), a method and apparatus of selectively etching metallic CNTs and a method and apparatus of fabricating an oxide in a carbon nanotube (CNT) device. These methods and... Agent: Andrews Kurth LLP Intellectual Property Department

20080296564 - Photoelectric conversion element and solar cell: in the formula, Ar11, Ar12, Ar13, Ar14 and Ar15 are each an arylene or heterocyclic group, or a composite group of an arylene group and a heterocyclic group, each of which may have a substituent, Ar11, Ar12, Ar13, Ar14 and Ar15 may form a ring by bonding with together, at... Agent: Lucas & Mercanti, LLP

20080296569 - Compound semiconductor material and method for forming an active layer of a thin film transistor device: A compound semiconductor material for forming an active layer of a thin film transistor device is disclosed, which has a group II-VI compound doped with a dopant ranging from 0.1 to 30 mol %, wherein the dopant is selected from a group consisting of alkaline-earth metals, group IIIA elements, group... Agent: Bacon & Thomas, PLLC

20080296567 - Method of making thin film transistors comprising zinc-oxide-based semiconductor materials: A method of making a thin film transistor comprising a zinc-oxide-containing semiconductor material and spaced apart first and second electrodes in contact with the material. The co-generation of high quality zinc oxide semiconductor films and contact electrodes is obtained, at low temperatures, using non-vacuum conditions, silver nanoparticles are deposited to... Agent: Andrew J. Anderson Patent Legal Staff

20080296568 - Thin film transistors and methods of manufacturing the same: A TFT includes a zinc oxide (ZnO)-based channel layer having a plurality of semiconductor layers. An uppermost of the plurality of semiconductor layers has a Zn concentration less than that of a lower semiconductor layer to suppress an oxygen vacancy due to plasma. The uppermost semiconductor layer of the channel... Agent: Harness, Dickey & Pierce, P.L.C

20080296571 - Multi-project wafer and method of making same: A semiconductor wafer is fabricated. The wafer has a plurality of dies. The plurality of dies include at least operable dies of a first type and operable dies of a second type different from the first type. The dies of the second type are rendered inoperable, while keeping the dies... Agent: Duane Morris LLP (tsmc)IPDepartment

20080296570 - Semiconductor device: A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first seal ring. The first seal ring comprises a first monitor circuit isolated by a first dielectric layer embedded in... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080296572 - Optical semiconductor device with sealing spacer: An optical semiconductor device may include a semiconductor component having an optical sensor on a front face thereof, and a transparent plate having electrical connection lines on a rear face thereof and lying outside a free region of the rear face. The front face of the semiconductor component may be... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080296573 - Solid-state element and solid-state element device: A solid-state element has: a semiconductor layer formed on a substrate, the semiconductor layer having a first layer that corresponds to an emission area of the solid-state element to and a second layer through which current is supplied to the first layer; a light discharge surface through which light emitted... Agent: Mcginn Intellectual Property Law Group, PLLC

20080296577 - Camera module package: There is provided a camera module package including: a substrate having an image sensor disposed on one surface thereof and a pad electrically connected to the image sensor; a protective cap adhered onto the substrate by an adhesive surrounding the image sensor to seal the image sensor, the protective cap... Agent: Staas & Halsey LLP

20080296576 - Display device: To provide a display device capable of reliably forming a resistive element formed on a substrate including pixels. A display device including at least a thin-film transistor and a resistive element on a substrate has a gate electrode, an insulating film, a semiconductor layer and a conductive layer which are... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080296574 - Pixel structure of lcd and fabrication method thereof: In this pixel structure, a metal layer/a dielectric layer/a heavily doped silicon layer constitutes a bottom electrode/a capacitor dielectric layer/a top electrode of a storage capacitor. At the same time, a metal shielding layer is formed under the thin film transistor to decrease photo-leakage-current.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080296575 - Thin film transistor, array substrate and method for manufacturing the same: A thin film transistor for a thin film transistor liquid crystal display (TFT-LCD), an array substrate and manufacturing method thereof are provided. The thin film transistor comprises a source, a drain, and a channel region between the source and drain. A source extension region is connected with the source, a... Agent: Hasse & Nesbitt LLC

20080296578 - Wiring material and a semiconductor device having a wiring using the material, and the manufacturing method thereof: An object of the present invention is to realize a semiconductor device having a high TFT characteristic. In manufacturing an active matrix display device, electric resistivity of the electrode material is kept low by preventing penetration of oxygen ion into the electrode in doping of an impurity ion. A display... Agent: Cook Alex Ltd

20080296579 - Nanosilicon semiconductor substrate manufacturing method and semiconductor circuit device using nanosilicon semiconductor substrate manufactured by the method: This invention provides a substrate structure capable of controlling the threshold voltage of a MOS transistor independently of the substrate concentration and easily suppressing a short channel effect caused by reducing the channel length. A first nanosilicon film formed from nanosilicon grains having the same grain size is formed on... Agent: Fitzpatrick Cella Harper & Scinto

20080296580 - Silicon oxide film, production method therefor and semiconductor device having gate insulation film using the same: The present invention provides a high-performance silicon oxide film as a gate insulation film and a semiconductor device having superior electric characteristics. The silicon oxide film according to the present invention includes CO2 in the film, wherein, when an integrated intensity of a peak is expressed by (peak width at... Agent: Young & Thompson

20080296581 - Pixel structure and method for forming the same: A pixel structure including at least one thin-film transistor, at least one storage capacitor, a patterned first metal layer, an interlayer dielectric layer, a passivation layer, and a patterned pixel electrode is provided. The storage capacitor is electrically connected to the thin-film transistor. The patterned first metal layer is covered... Agent: Bacon & Thomas, PLLC

20080296583 - Display device and manufacturing method of the same: A display device includes a capacitive element configured so that a portion of a semiconductor layer which is made conductive constitutes one electrode, an insulation film which covers the semiconductor layer constitutes a dielectric film, and a conductive layer which includes a portion which is formed over the insulation film... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080296582 - Tft-lcd array substrate: A thin film transistor liquid crystal display (TFT-LCD) array substrate with a repairable pixel structure is provided. The array substrate comprises a gate line and a data line, and the gate line and the data line intersect with each other to define a pixel unit. The pixel unit comprises a... Agent: Sheridan Ross PC

20080296585 - Growth method of gan crystal, and gan crystal substrate: A method of producing a GaN crystal is directed to growing a GaN crystal on a GaN seed crystal substrate. The method includes the steps of preparing a GaN seed crystal substrate including a first dopant such that the thermal expansion coefficient of the GaN seed crystal substrate becomes greater... Agent: Drinker Biddle & Reath (dc)

20080296584 - Iii-v nitride semiconductor layer-bonded substrate and semiconductor device: Affords III-V nitride semiconductor layer-bonded substrates from which semiconductor device of enhanced properties can be manufactured, and semiconductor devices incorporating the III-V nitride semiconductor layer-bonded substrates. The III-V nitride semiconductor layer-bonded substrate, in which a III-V nitride semiconductor layer and a base substrate are bonded together, is characterized in that... Agent: Judge Patent Associates

20080296586 - Composite wafers having bulk-quality semiconductor layers and method of manufacturing thereof: Method for producing composite wafers with thin high-quality semiconductor films atomically attached to synthetic diamond wafers is disclosed. Synthetic diamond substrates are created by depositing synthetic diamond onto a nucleating layer deposited on bulk semiconductor wafer which has been prepared to allow separation of the thin semiconductor film from the... Agent: Pillsbury Winthrop Shaw Pittman LLP

20080296587 - Silicon carbide semiconductor device having junction barrier schottky diode: A silicon carbide semiconductor device includes a substrate; a drift layer having a first conductivity type; an insulating layer; a Schottky electrode; an ohmic electrode; a resurf layer; and second conductivity type layers. The drift layer and the second conductivity type layers provide multiple PN diodes. Each second conductivity type... Agent: Posz Law Group, PLC

20080296588 - Semiconductor substrate with electromagnetic-wave-scribed nicks, semiconductor light-emitting device with such semiconductor substrate and manufacture thereof: The invention discloses a substrate and a fabricating method thereof for epitaxy of a semiconductor light-emitting device. An upper surface of the substrate according to the invention, where the epitaxy of the semiconductor light-emitting device is to be performed, has a plurality of electromagnetic-wave-scribed nicks.... Agent: Birch Stewart Kolasch & Birch

20080296589 - Solid-state lighting device package: The present invention provides a lighting device package, which can provide a means for efficient thermal access to the lighting device package in addition to a desired level of light extraction from the one or more light-emitting elements within the lighting device package. The lighting device package comprises a substrate... Agent: Philips Intellectual Property & Standards

20080296591 - Conductor structure, pixel structure, and methods of forming the same: A method for forming a conductor structure is provided. The method comprises: (1) providing a substrate; (2) forming a patterned dielectric layer with a first opening which exposes a portion of the substrate; forming a patterned organic material layer on the dielectric layer with a second opening which corresponds to... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080296590 - Led-based light source having improved thermal dissipation: A light source having a plurality of dies mounted on leads that are partially enclosed in a plastic body is disclosed. Each die is powered by first and second contacts. One contact is connected to the lead on which the die is mounted. Light from the LED exits the die... Agent: Kathy Manke Avago Technologies Limited

20080296592 - Semiconductor light-emitting device: A semiconductor light-emitting device includes: a light-emitting semiconductor element arranged on a lead frame; a transparent resin mold covering the light-emitting semiconductor element and the lead frame except a terminal portion of the lead frame; and a reflective surface formed on a bent portion of part of the lead frame.... Agent: Stevens Law Group

20080296593 - Silicon light emitting device: Provided is a highly-efficient silicon light emitting device including an improved structure by which more light of the light emitted toward the lateral side of the light emitting device is emitted toward the front side thereof than conventional light emitting devices so as to improve the brightness. The silicon light... Agent: Rabin & Berdo, PC

20080296594 - Nitride optoelectronic devices with backside deposition: Nitride optoelectronic devices that have asymmetric double-sided structures and methods fabricating such structures are disclosed. Two n-type III-N layers are formed simultaneously over opposite sides of a substrate with substantially the same composition. Thereafter, a p-type III-N active layer is formed over one of the n-type III-N layers but not... Agent: Townsend And Townsend And Crew LLP / Amat

20080296595 - Light emitting diode with high illumination: A light emitting diode (80) includes a first and a second semiconductor structures (30, 40), and an adhesive layer (34, 46) between the first and the second semiconductor structures. The first semiconductor structure includes a n-type AlGaInP cladding layer (13), a p-type AlGaInP cladding layer (17), an AlGaInP active layer... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang

20080296597 - Chip scale light emitting device: A light emitting device includes: a circuit board having a dielectric substrate and first and second electrodes provided on the dielectric substrate, the dielectric substrate being formed with a retaining hole; and a light emitting diode chip received in the retaining hole in the dielectric substrate and connected electrically to... Agent: Rosenberg, Klein & Lee

20080296598 - Current spreading layer with micro/nano structure, light-emitting diode apparatus and its manufacturing method: A light-emitting diode (LED) apparatus includes an epitaxial layer and a current spreading layer. The epitaxial layer has a first semiconductor layer, an active layer and a second semiconductor layer. The current spreading layer is disposed on the first semiconductor layer of the epitaxial layer and has a micro/nano roughing... Agent: Birch Stewart Kolasch & Birch

20080296599 - Led package with stepped aperture: A light emitting diode (LED) package for high temperature operation which includes a printed wire board and a heat sink. The LED package may include a formed heat sink layer, which may be thermally coupled to an external heat sink. The printed wire board may include apertures that correspond to... Agent: Darby & Darby P.C.

20080296601 - Light-emitting diode incorporating an array of light extracting spots: A light-emitting diode includes an optical layer formed in an array of substantially equidistant light extracting spots integrated to its multi-layered structure. The array of light extracting spots includes a distribution of juxtaposed hexagon patterns. The layer thickness of the light extracting spots is less than 800 Å.... Agent: David I. Roche Baker & Mckenzie LLP

20080296596 - Novel green emitting phosphors and blends thereof: Phosphor compositions, blends thereof and light emitting devices including white light emitting LED based devices, and backlights, based on such phosphor compositions. The devices include a light source and a phosphor material as described. Also disclosed are phosphor blends including such a phosphor and devices made therefrom.... Agent: Fay Sharpe LLP

20080296600 - Organic light emitting diode (oled) display and method of manufacturing the same: An organic light emitting display includes a substrate, an OLED including an anode electrode, a cathode electrode and an organic thin film formed between the anode electrode and the cathode electrode, a reflective layer on the OLED, the reflective layer comprising a laminated first material and second material, the first... Agent: Lee & Morse, P.C.

20080296605 - Light emitting device: A light emitting device includes a resin case including a concave portion with a reflector portion surrounding a light emitting element, a first lead and a second lead that are formed of a metal, exposed at a bottom of the concave portion of the case, and disposed away from each... Agent: Mcginn Intellectual Property Law Group, PLLC

20080296603 - Light emitting device with high light extraction efficiency: An exemplary solid-state light emitting device includes a substrate, a light emitting structure, a first electrode and a second electrode have opposite polarities with each other. The light emitting structure is formed on the substrate and includes a first-type semiconductor layer and a second-type semiconductor layer. The first electrode is... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang

20080296602 - Light emitting diode: A light emitting diode (LED) includes a substrate, a first type epitaxial layer, a light emitting layer, a second type epitaxial layer and a plurality of nano-particles. The first type epitaxial layer is disposed on the substrate. The light emitting layer is disposed on the first type epitaxial layer. The... Agent: Birch Stewart Kolasch & Birch

20080296604 - Light-emitting diode lead frame and manufacture method thereof: The invention discloses an LED lead frame and the manufacture method thereof. First, a press-formed strip including a guide strip, a first metal frame, and a second metal frame is provided. The first metal frame and the second metal frame are connected to the guide strip and are connected to... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20080296606 - Electronic module and chip card with indicator light: The invention generally relates to devices comprising semiconductor chips. More specifically, the invention relates to an electronic module (1) comprising at least one integrated circuit chip (10) which is connected to the conductor tracks of an insulating support and at least one light-emitting diode (16). According to one aspect of... Agent: Buchanan, Ingersoll & Rooney PC

20080296607 - Environmentally robust lighting devices and methods of manufacturing same: An illustrative lighting device comprises: a light emitting chip; a silicone encapsulant disposed over the light emitting chip; and a light transmissive vinyl or acrylic layer sealing an assembly including at least the silicone encapsulant and the light emitting chip. An illustrative method of fabricating a lighting device comprises: encapsulating... Agent: Fay Sharpe LLP

20080296608 - Light-emitting device: A light-emitting element 10 is fixed on a lead frame 20 with a die-bonding member 13. The light-emitting element 10 is sealed with a silicone resin 22 and further sealed with an epoxy resin 24 from above the silicone resin 22. The die-bonding member 13 is obtainable by dispersing titanium... Agent: Mcginn Intellectual Property Law Group, PLLC

20080296609 - Nitride semiconductor device comprising bonded substrate and fabrication method of the same: A substrate 1 for growing nitride semiconductor has a first and second face and has a thermal expansion coefficient that is larger than that of the nitride semiconductor. At least n-type nitride semiconductor layers 3 to 5, an active layer 6 and p-type nitride semiconductor layers 7 to 8 are... Agent: Morrison & Foerster LLP

20080296610 - Semiconductor light-emitting element and substrate used in formation of the same: For a semiconductor laser, a stacked member comprising an active layer is formed on the surface of a GaN single-crystal substrate, a defect aggregation portion is formed on the rear face of the GaN single-crystal substrate, and an electrode is formed so as to be electrically connected to the defect... Agent: Drinker Biddle & Reath (dc)

20080296611 - Semiconductor device and method for manufacturing same: A semiconductor device includes: a semiconductor layer having a first major surface, a second major surface provided on opposite side of the first major surface, and a channel formation region provided in a surface portion on the first major surface side; a first main electrode provided inside a dicing street... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080296612 - Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate and in a semiconductor device: Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing (100) platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing (102) platinum-... Agent: Slater & Matsil LLP

20080296613 - Esd protection devices: An ESD protection device is provided. The ESD protection device comprises an SCR and an ESD detection circuit. The SCR is coupled between a high voltage and a ground and has a special semiconductor structure which saves area. When the ESD detection circuit detects an ESD event, the ESD detection... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080296619 - Adhesive bonding with low temperature grown amorphous or polycrystalline compound semiconductors: Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300° C. to... Agent: Brinks Hofer Gilson & Lione

20080296620 - Electronic device including a semiconductor fin and a process for forming the electronic device: An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can... Agent: Larson Newman Abel Polansky & White, LLP

20080296615 - Fabrication of strained heterojunction structures: Growth of multilayer films is carried out in a manner which allows close control of the strain in the grown layers and complete release of the grown films to allow mounting of the released multilayer structures on selected substrates. A layer of material, such as silicon-germanium, is grown onto a... Agent: Wisconsin Alumni Research Foundation (warf)

20080296616 - Gallium nitride-on-silicon nanoscale patterned interface: A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate that is heated to a temperature in a range of about 300 to 800° C., and a first film is formed in compression overlying... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080296617 - Method using low temperature wafer bonding to fabricate transistors with heterojunctions of si(ge) to iii-n materials: A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor... Agent: Gates & Cooper LLP Howard Hughes Center

20080296614 - Mis-type field-effect transistor: A strained Si layer 2 is epitaxially grown on a base SiGe layer 1, and a gate insulating film 3a and a gate electrode 4a are formed. An impurity is then ion-implanted (FIG. 2A) into the base SiGe layer 1 and the strained Si layer 2 using the gate electrode... Agent: Foley And Lardner LLP Suite 500

20080296618 - P-gan/algan/aln/gan enhancement-mode field effect transistor: An enhancement mode High Electron Mobility Transistor (HEMT) comprising a p-type nitride layer between the gate and a channel of the HEMT, for reducing an electron population under the gate. The HEMT may also comprise an Aluminum Nitride (AlN) layer between an AlGaN layer and buffer layer of the HEMT... Agent: Gates & Cooper LLP Howard Hughes Center

20080296621 - Iii-nitride heterojunction device: A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof.... Agent: Ostrolenk Faber Gerb & Soffen

20080296622 - Buried channel mosfet using iii-v compound semiconductors and high k gate dielectrics: A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound... Agent: Scully, Scott, Murphy & Presser, P.C.

20080296623 - Bipolar transistor and method for making same: A heterojunction bipolar transistor: The transistor may a collector layer, a base layer and an emitter layer. The transistor may include a dielectric material being disposed over the base layer. The base layer may be a SiGe base layer.... Agent: Infineon Technologies Ag Patent Department

20080296624 - Semiconductor device and manufacturing method thereof: The object of the present invention is to provide a semiconductor device and the manufacturing method thereof which are capable of preventing decrease in the collector breakdown voltage and reducing the collector resistance. The semiconductor device according to the present invention includes: a HBT formed on a first region of... Agent: Greenblum & Bernstein, P.L.C

20080296625 - Gallium nitride-on-silicon multilayered interface: A multilayer thermal expansion interface between silicon (Si) and gallium nitride (GaN) films is provided, along with an associated fabrication method. The method provides a (111) Si substrate and forms a first layer of a first film overlying the substrate. The Si substrate is heated to a temperature in the... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080296627 - Nitride semiconductor device and method of manufacturing the same: In the nitride semiconductor device using the silicon substrate, the metal electrode formed on the silicon substrate has both ohmic contact property and adhesion, so that the nitride semiconductor device having excellent electric properties and reliability is obtained. The nitride semiconductor device includes a silicon substrate (2), a nitride semiconductor... Agent: Birch Stewart Kolasch & Birch

20080296626 - Nitride substrates, thin films, heterostructures and devices for enhanced performance, and methods of making the same: The present invention provides nitride semiconductors having a moderate density of basal plane stacking faults and a reduced density of threading dislocations, various products based on, incorporating or comprising the nitride semiconductors, including without limitation substrates, template films, templates, heterostructures with or without integrated substrates, and devices, and methods for... Agent: Black Lowe & Graham, PLLC

20080296628 - Semiconductor integrated circuit and method for manufacturing same: A semiconductor integrated circuit includes at least one first circuit portion and at least one second circuit portion. The first circuit portion includes a first interconnect or a diffusion layer formed by exposure using a high-precision mask. The second circuit portion includes a second interconnect or a diffusion layer formed... Agent: Amin, Turocy & Calvin, LLP

20080296629 - Solid-state imaging device, method of manufacturing the same, and imaging apparatus: A solid-state imaging device includes a semiconductor substrate; a first conductive region of the semiconductor substrate; a first conductive region on an upper surface side of the first conductive region of the semiconductor substrate; a second conductive region below the first conductive region on the upper surface side of the... Agent: Rader Fishman & Grauer PLLC

20080296630 - Cmos image sensor and pixel of the same: A pixel of an image sensor includes a gate insulation layer formed over a substrate doped with first-type impurities, a transfer gate formed over the gate insulation layer, a photodiode formed in the substrate at one side of the transfer gate, and a floating diffusion node formed in the substrate... Agent: Morgan Lewis & Bockius LLP

20080296631 - Metal-oxide-semiconductor transistor and method of forming the same: A method of forming a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate is prepared first, and the semiconductor substrate has a gate structure, a source region and a drain region. Subsequently, a stress buffer layer is formed on the semiconductor substrate, and covers the gate structure, the source... Agent: North America Intellectual Property Corporation

20080296633 - Electronic device including a transistor structure having an active region adjacent to a stressor layer: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or... Agent: Larson Newman Abel Polansky & White, LLP

20080296635 - Semiconductor device with strain: A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080296632 - Stress-enhanced performance of a finfet using surface/channel orientations and strained capping layers: Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel... Agent: Bever, Hoffman & Harms, LLP

20080296634 - Structure and method for manufacturing strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels: The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact... Agent: Scully, Scott, Murphy & Presser, P.C.

20080296636 - Devices and integrated circuits including lateral floating capacitively coupled structures: According to the present invention, semiconductor device breakdown voltage can be increased by embedding field shaping regions within a drift region of the semiconductor device. A controllable current path extends between two device terminals on the top surface of a planar substrate, and the controllable current path includes the drift... Agent: Lumen Patent Firm, Inc.

20080296637 - Semiconductor device and method of manufacturing the same: A semiconductor device includes first gate structures, second gate structures, a first capping layer pattern, a second capping layer pattern, first spacers, second spacers, third spacers, and a substrate having first impurity regions and second impurity regions. The first gate structures are arranged on the substrate at a first pitch.... Agent: Volentine & Whitt PLLC

20080296638 - Semiconductor device and method of manufacturing the same: A semiconductor device includes an active pattern on a substrate, the active pattern including a protrusion with a lower surface on the substrate and an upper surface opposite the lower surface, a width of the protrusion gradually decreasing from the lower surface to the upper surface, the upper surface of... Agent: Lee & Morse, P.C.

20080296639 - Semiconductor image sensor array device, apparatus comprising such a device and method for operating such a device: s

20080296640 - Solid-state image pickup device, method for making same, and image pickup apparatus: Disclosed herein is a solid-state image pickup device which includes: a light-receiving unit for photoelectric conversion of incident light; and a charge transfer unit of an n-channel insulating gate type configured to transfer a signal charge photoelectrically converted in the light-receiving unit; wherein the charge transfer unit has an insulating... Agent: Sonnenschein Nath & Rosenthal LLP

20080296644 - Cmos image sensors and methods of fabricating same: A CMOS image sensor includes an image transfer transistor therein. This image transfer transistor includes a semiconductor channel region of first conductivity type and an electrically conductive gate on the semiconductor channel region. A gate insulating region is also provided. The gate insulating region extends between the semiconductor channel region... Agent: Myers Bigel Sibley & Sajovec

20080296641 - Multi-well cmos image sensor and methods of fabricating the same: Provided is a multi-well CMOS image sensor and a method of fabricating the same. The multi-well CMOS image sensor may include a plurality of photodiodes vertically formed in a region of a substrate, an n+ wall that vertically connects an outer circumference of the photodiodes, and a floating diffusion region... Agent: Harness, Dickey & Pierce, P.L.C

20080296642 - Photodiode and photo ic using same: The present invention provides a photodiode comprising a first silicon semiconductor layer formed over an insulating layer, a second silicon semiconductor layer formed over the insulating layer, having a thickness ranging from greater than or equal to 3 nm to less than or equal to 36 nm, a low-concentration diffusion... Agent: Volentine & Whitt PLLC

20080296643 - Solid state image sensing device: A solid state image sensing device in which many pixels are disposed in a matrix on a two-dimensional plane comprises a plurality of light receiving devices disposed in such a way that a center interval may periodically change in a column direction and/or a row direction, and a plurality of... Agent: Arent Fox LLP

20080296645 - Solid-state imaging device and manufacturing method thereof: A solid-state imaging device includes a photoelectric conversion unit, a transistor, and an element separation region separating the photoelectric conversion unit and the transistor. The photoelectric conversion unit and the transistor constitute a pixel. The element separation region is formed of a semiconductor region of a conductivity type opposite to... Agent: Rader Fishman & Grauer PLLC

20080296646 - Semiconductor memory device and method for fabricating the same: According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate; a transistor that is formed on the semiconductor substrate; a ferroelectric capacitor including a bottom electrode that is formed above the semiconductor to be connected with the transistor, a ferroelectric film... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080296647 - Semiconductor memory device and manufacturing method thereof: The present invention provides a semiconductor memory device comprising a semiconductor substrate formed of a support substrate, an insulating film formed over the support substrate and a semiconductor layer formed over the insulating film; a MOSFET having a source layer and a drain layer both formed in the semiconductor layer... Agent: Rabin & Berdo, PC

20080296648 - Fin memory structure and method for fabrication thereof: A semiconductor fin memory structure and a method for fabricating the semiconductor fin memory structure include a semiconductor fin-channel within a finFET structure that is contiguous with and thinner than a conductor fin-capacitor node within a fin-capacitor structure that is integrated with the finFET structure. A single semiconductor layer may... Agent: Scully, Scott, Murphy & Presser, P.C.

20080296649 - Semiconductor device employing buried insulating layer and method of fabricating the same: A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain... Agent: Marger Johnson & Mccollom, P.C.

20080296650 - High-k dielectrics with gold nano-particles: A metal oxide semiconductor (MOS) structure having a high dielectric constant gate insulator layer containing gold (Au) nano-particles is presented with methods for forming the layer with high step coverage of underlying topography, high surface smoothness, and uniform thickness. The transistor may form part of a logic device, a memory... Agent: Schwegman, Lundberg & Woessner, P.A.

20080296651 - Semiconductor device: A disclosed semiconductor device comprises a non-volatile memory cell including a PMOS write transistor and an NMOS read transistor. The PMOS write transistor includes a write memory gate oxide film formed on a semiconductor substrate and a write floating gate of electrically-floating polysilicon formed on the write memory gate oxide... Agent: Dickstein Shapiro LLP

20080296652 - Split gate flash memory cell with ballistic injection: A split floating gate flash memory cell is comprised of source/drain regions in a substrate. The split floating gate is insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The sections of the floating gate are... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20080296654 - Non-volatile memory device and method for fabricating the same: A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a gate structure on a substrate, the gate structure including a first insulation layer, a first electrode layer for a floating gate and a second insulation layer; forming a third insulation layer on... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080296653 - Semiconductor memory: A semiconductor memory device of an aspect of the present invention comprises a plurality of memory cell transistors arranged in a memory cell array, a select transistor which is disposed in the memory cell array and which selects the memory cell transistor, and a peripheral circuit transistor provided in a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080296655 - Multi-time programmable memory and method of manufacturing the same: A multi-time programmable (MTP) memory includes a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer. The inter-gate dielectric layer is disposed on the floating gate,... Agent: Jianq Chyun Intellectual Property Office

20080296657 - Non-volatile memory devices and methods of manufacturing non-volatile memory devices: A non-volatile memory device includes a substrate and a tunnel insulation layer pattern, such that each portion of the tunnel insulation pattern extends along a first direction and adjacent portions of the tunnel insulation layer pattern may be separated in a second direction that is substantially perpendicular to the first... Agent: Myers Bigel Sibley & Sajovec

20080296658 - Process for manufacturing a memory device integrated on a semiconductor substrate and comprising nanocristal memory cells and cmos transistors: An embodiment of a process is disclosed herein for fabricating a memory device integrated on a semiconductor substrate and comprising at least a nanocrystal memory cell and CMOS transistors respectively formed in a memory area and in a circuitry area. According to an embodiment, a process includes forming a nitride... Agent: Graybeal, Jackson, Haley LLP

20080296656 - Semiconductor device: A semiconductor device includes a tunnel insulation film formed on a semiconductor substrate, a floating gate electrode formed on the tunnel insulation film, an inter-electrode insulation film formed on the floating gate electrode, a control gate electrode formed on the inter-electrode insulation film, a pair of oxide films which are... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080296661 - Integration of non-volatile charge trap memory devices and logic cmos devices: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels... Agent: Cypress/blakely Blakely Sokoloff Taylor & Zafman LLP

20080296660 - Low resistivity conductive structures, devices and systems including same, and methods forming same: A conductive structure and method for making same is disclosed and includes a first nucleation layer formed by performing a cyclic deposition process on a substrate, a second nucleation layer formed on the first nucleation layer by a CVD process, and a bulk metal layer formed on the second nucleation... Agent: Volentine & Whitt PLLC

20080296659 - Nand flash memory array having pillar structure and fabricating method of the same: The present invention relates to a NAND flash memory array having vertical channels and sidewall gate structure and a fabricating method of the same. A NAND flash memory array of the present invention has insulator strip structure and one or more semiconductor strips are next to the both sides of... Agent: Casella & Hespos

20080296662 - Discrete trap memory (dtm) mediated by fullerenes: A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical... Agent: Slater & Matsil LLP

20080296664 - Integration of non-volatile charge trap memory devices and logic cmos devices: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels... Agent: Cypress/blakely Blakely Sokoloff Taylor & Zafman LLP

20080296663 - Semiconductor device and method of manufacturing the same: A semiconductor device according to an embodiment of the present invention includes a first gate insulator, a first gate electrode, a second gate insulator, and a second gate electrode. Regarding the thickness of the second gate insulator, the thickness of the insulator, on a first edge of the first gate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080296665 - Mask for manufacturing tft, tft, and manufacturing thereof: A mask comprises a channel region half-exposure mask structure, a drain mask structure, and a source mask structure, wherein the channel region half-exposure mask structure comprises a channel region peripheral half-exposure mask structure, which extends from a portion that corresponds to a channel region of the TFT and is outside... Agent: Sheridan Ross PC

20080296667 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a fin active region with a tapered side surface, a gate electrode that has a side surface covering portion covering a part of the side surface of the fin active region and a top surface covering portion covering a part of a top surface of the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080296666 - Semiconductor device including an embedded contact plug: A semiconductor device includes an active area isolated by an isolation area on a semiconductor substrate. A transistor includes a gate electrode extending across the active area, source/drain regions formed in the active area on both sides of the gate electrode, and impurity-containing contact plugs connected to the source/drain regions.... Agent: Sughrue Mion, PLLC

20080296668 - Semiconductor device and method of manufacturing a semiconductor device: A semiconductor device has a substrate having a plurality of neighboring trenches, and a contact area, one mesa stripe each being formed between two neighboring trenches. The contact area contacts mesa stripes and surrounds an opening region in which the contact area is not formed and which is formed such... Agent: Dicke, Billig & Czaja

20080296669 - System and method for making a ldmos device with electrostatic discharge protection: A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity... Agent: Texas Instruments Incorporated

20080296670 - Semiconductor devices including transistors having a recessed channel region and methods of fabricating the same: Some embodiments of the present invention provide semiconductor devices including a gate trench in an active region of a semiconductor substrate and a gate electrode in the gate trench. A low-concentration impurity region is provided in the active region adjacent to a sidewall of the gate trench. A high-concentration impurity... Agent: Myers Bigel Sibley & Sajovec

20080296671 - Semiconductor memory device, manufacturing method thereof, and data processing system: A semiconductor memory device includes a silicon pillar, a gate electrode covering a side surface of the silicon pillar via a gate insulation film, diffusion layers (11, 12) provided in a lower part and an upper part, respectively of the silicon pillar, a bit line connected to the diffusion layer... Agent: Sughrue Mion, PLLC

20080296672 - Transistor device and method for manufacturing the same: A transistor device includes a recess in a surface of semiconductor substrate, a gate insulation layer formed over an inner side of the recess, a gate conductor filling the recess in which the gate insulation layer is formed, and source and drain regions located over the substrate adjacent the recess.... Agent: Sherr & Vaughn, PLLC

20080296673 - Double gate manufactured with locos techniques: This invention discloses a trenched semiconductor power device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments with a bottom... Agent: Bo-in Lin

20080296675 - Semiconductor device: The invention realizes low on-resistance and high current flow in a semiconductor device in which a current flows in a thickness direction of a semiconductor substrate. A first MOS transistor having first gate electrodes and first source layers is formed on a front surface of a semiconductor substrate, and a... Agent: Morrison & Foerster LLP

20080296674 - Transistor, integrated circuit and method of forming an integrated circuit: A transistor, an integrated circuit and a method of forming an integrated circuit is disclosed. One embodiment includes a gate electrode. The gate electrode is disposed in a gate groove formed in a semiconductor substrate and includes a conductive carbon material.... Agent: Dicke, Billig & Czaja

20080296676 - Soi fet with source-side body doping: An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side dopant concentration leads to elevated forward leakage current... Agent: Innovation Interface, LLC

20080296677 - Semiconductor device and method of manufacturing the same and data processing system: A semiconductor device is provided with a silicon pillar formed substantially perpendicularly to a main surface of a substrate, a gate electrode covering side surface of the silicon pillar via a gate insulation film, a conductive layer provided on an upper part of the silicon pillar, a cylindrical sidewall insulation... Agent: Sughrue Mion, PLLC

20080296678 - Method for fabricating high voltage drift in semiconductor device: A drift of a high voltage transistor formed using an STI (shallow trench isolation). The method for forming a high voltage drift of a semiconductor device can include forming a pad insulating film on a semiconductor substrate having a high voltage well; and then opening a region of the semiconductor... Agent: Sherr & Vaughn, PLLC

20080296679 - Lateral high-voltage transistor with vertically-extended voltage-equalized drift region: A lateral high-voltage device in which conductive trench plates are inserted across the voltage-withstand region, so that, in the on state, the current density vectors have less convergence. This can help reduce on-resistance.... Agent: Groover & Associates

20080296683 - Carbon nanotube having improved conductivity, process of preparing the same, and electrode comprising the carbon nanotube: Provided are a method of doping carbon nanotubes, p-doped carbon nanotubes prepared using the method, and an electrode, a display device or a solar cell including the carbon nanotubes. Particularly, a method of doping carbon nanotubes having improved conductivity by reforming the carbon nanotubes using an oxidizer, doped carbon nanotubes... Agent: Cantor Colburn, LLP

20080296681 - Contact structure for finfet device: In accordance with an embodiment, a FinFET device includes: one or more fins, a dummy fin, a gate line, a gate contact landing pad, and a gate contact element. Each of the fins extends in a first direction above a substrate. The dummy fin extends in parallel with the fins... Agent: Schwegman, Lundberg & Woessner / Infineon

20080296680 - Method of making an integrated circuit including doping a fin: A method of making an integrated circuit including doping a fin is disclosed. The method includes providing a substrate having at least one fin of a semiconductor material and carrying out a gas-phase doping of the at least one fin.... Agent: Dicke, Billig & Czaja

20080296682 - Mos structures with remote contacts and methods for fabricating the same: MOS structures with remote contacts and methods for fabricating such MOS structures are provided. In one embodiment, a method for fabricating an MOS structure comprises providing a semiconductor layer that is at least partially surrounded by an isolation region and that has an impurity-doped first portion. First and second MOS... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080296685 - Analog switch: An analog switch having a low capacitance is achieved. Potentials of input/output terminals of the analog switch and a well potential and a gate potential of an NMOS switching device are operated in synchronization via level shift buffers, thereby cancelling parasitic capacitances present between these elements.... Agent: Miles & Stockbridge PC

20080296684 - Semiconductor apparatus: A semiconductor apparatus includes a semiconductor substrate, an insulating film provided on the semiconductor substrate, and a semiconductor film provided on the insulating film. The semiconductor substrate includes a region of a first current path including at least one diode, the semiconductor film includes a region of a second current... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080296686 - Circuit board and display apparatus: A circuit board includes a transparent circuit substrate, at least one die and at least one electrostatic discharge (ESD) protection circuit. The transparent circuit substrate has a patterned conducting layer. The die is disposed on the transparent circuit substrate and has at least one input/output (I/O) electrical connecting pad. The... Agent: Birch Stewart Kolasch & Birch

20080296688 - Esd protection structure for i/o pad subject to both positive and negative voltages: An ESD protection circuit is disclosed for an n-channel MOS transistor formed in an inner p-well of a triple-well process and connected to an I/O pad that may experience both positive and negative voltages according to the present invention. A first switch connects the p-well containing the n-channel MOS transistor... Agent: Lewis And Roca LLP

20080296687 - Field-effect transistor (fet) with embedded diode: A Field-Effect Transistor (FET) is provided that includes a first portion and a second portion separated from the first portion by a gap. The FET further includes at least one diode embedded within the gap between the first and second portions.... Agent: Brian C. Oakes Tyco Technology Resources

20080296689 - Nanotube dual gate transistor and method of operating the same: A nanotube dual gate transistor and associated method of use are provided. The nanotube dual gate transistor includes a substrate, a nanotube material, a source conductor and a drain conductor, a top gate and a back gate. The nanotube material is formed over the substrate having a nanotube channel with... Agent: Greenberg Traurig LLP (la)

20080296693 - Enhanced transistor performance of n-channel transistors by using an additional layer above a dual stress liner in a semiconductor device: By forming an additional dielectric material, such as silicon nitride, after patterning dielectric liners of different intrinsic stress, a significant increase of performance of N-channel transistors may be obtained while substantially not contributing to a performance loss of the P-channel transistor.... Agent: Williams, Morgan & Amerson

20080296691 - Layout methods of integrated circuits having unit mos devices: A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction.... Agent: Slater & Matsil, L.L.P.

20080296690 - Metal interconnect system and method for direct die attachment: Provided herein is an exemplary embodiment of a semiconductor chip for directly connecting to a carrier. The chip includes a metal layer applied to a top surface of the chip; a passivation layer applied over the metal layer such that portions of the passivation layer is selectively removed to create... Agent: Goodwin Procter LLP Patent Administrator

20080296692 - Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel region: By incorporating a semiconductor species having the same valence and a different covalent radius compared to the base semiconductor material on the basis of an ion implantation process, a strain-inducing material may be positioned locally within a transistor at an appropriate manufacturing stage, thereby substantially not contributing to overall process... Agent: J. Mike Amerson, Williams, Morgan & Amerson, P.C.,

20080296694 - Semiconductor device with field plate and method: A method of making a semiconductor device includes forming shallow trench isolation structures (14) in a semiconductor device layer. The shallow trench isolation structures are U- or O-shaped enclosing field regions (28) formed of the semiconductor device layer which is doped and/or suicided to be conducting. The semiconductor device may... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080296695 - Semiconductor device and method of fabricating the same: A semiconductor is provided. The semiconductor device includes a transistor, a first strain layer and a second strain layer on a substrate. The first strain layer is configured at the periphery of the transistor. The second strain layer covers the transistor and a region exposed by the first strain layer.... Agent: J C Patents, Inc.

20080296696 - Semiconductor devices including doped metal silicide patterns and related methods of forming such devices: Provided are a semiconductor device and a method of forming the same. The method includes forming an interlayer dielectric on a semiconductor substrate, forming a contact hole in the interlayer dielectric to expose the semiconductor substrate, forming a metal pattern including a dopant on the exposed semiconductor substrate, and performing... Agent: Myers Bigel Sibley & Sajovec

20080296697 - Programmable semiconductor interposer for electronic package and method of forming: Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in said interposer. A user can program said interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices... Agent: Slater & Matsil, L.L.P.

20080296698 - Method for suppressing layout sensitivity of threshold voltage in a transistor array: A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of interstitial atoms adjacent such surfaces, thus minimizing variations in threshold voltage of transistors within... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20080296700 - Method of forming gate patterns for peripheral circuitry and semiconductor device manufactured through the same method: A method for forming gate patterns for a semiconductor device includes defining a cell array region and a peripheral region on a substrate. A layout is defined in a peripheral region. The layout comprises patterns having a plurality of fingers that extend along a first direction, wherein the fingers are... Agent: Townsend And Townsend And Crew, LLP

20080296699 - Semiconductor device in peripheral circuit region using a dummy gate: A semiconductor device in a peripheral circuit region includes a semiconductor substrate having a plurality of active areas which are disposed distantly from each other; a gate pattern including at least one gate disposed on the active area; a dummy gate disposed between the active areas and first and second... Agent: Ladas & Parry LLP

20080296701 - One-time programmable read-only memory: A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive... Agent: J C Patents, Inc.

20080296702 - Integrated circuit structures with multiple finfets: A semiconductor structure includes a semiconductor substrate; and a first Fin field-effect transistor (FinFET) and a second FinFET at a surface of the semiconductor substrate. The first FinFET includes a first fin; and a first gate electrode over a top surface and sidewalls of the first fin. The second FinFET... Agent: Slater & Matsil, L.L.P.

20080296703 - Method for producing a field-effect transistor, field-effect transistor and integrated circuit arrangement: A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods.... Agent: Slater & Matsil LLP

20080296704 - Semiconductor device and manufacturing method thereof: Top and bottom surfaces of a gate insulating film are terminated with fluorine atoms and the top surface of the gate insulating film is then etched. New dangling bonds are formed on the top surface of the gate insulating film. Such new dangling bonds are terminated with nitrogen atoms. A... Agent: Young & Thompson

20080296706 - Cobalt disilicide structure: A structure. The structure may include a layer of cobalt disilicide that is substantially free of cobalt monosilicide and there is substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may include a substrate that includes: an insulated-gate field effect transistor (FET) that... Agent: Schmeiser, Olsen & Watts

20080296705 - Gate and manufacturing method of gate material: A gate including a conductive buffer layer and a conductive layer is provided. The conductive buffer layer is disposed on a gate dielectric layer, and the average grain size of the conductive buffer layer is less than 100 nm. The conductive layer is disposed on the conductive buffer layer, and... Agent: J C Patents, Inc.

20080296707 - Semiconductor transistors with expanded top portions of gates: A semiconductor transistor with an expanded top portion of a gate and a method for forming the same. The semiconductor transistor with an expanded top portion of a gate includes (a) a semiconductor region which includes a channel region and first and second source/drain regions; the channel region is disposed... Agent: Schmeiser, Olsen & Watts

20080296708 - Integrated sensor arrays and method for making and using such arrays: The present invention relates to a method for making an integrated sensor comprising providing a sensor array fabricated on a top surface of a bulk silicon wafer having a top surface and a bottom surface, and comprising a plurality of sensors fabricated on the top surface of the bulk silicon... Agent: General Electric Company (pcpi) C/o Fletcher Yoder

20080296709 - Chip assembly: The present invention provides an integrated circuit chip assembly and a method of manufacturing the same. The assembly includes a package element having a top surface and an integrated circuit chip having a top surface, a bottom surface, edge surface between the top and bottom surfaces, and contacts exposed at... Agent: Tessera Lerner David Et Al.

20080296711 - Magnetoelectronic device having enhanced permeability dielectric and method of manufacture: A magnetoelectronic device structure 20 includes programming lines 26 and 28 and a magnetoelectronic device 24 between the programming lines 26 and 28. In one embodiment, layers 38, 40, and 42 of a colloidal dispersion of an electrically insulating material and magnetic particles are positioned between the magnetoelectronic device 24... Agent: Meschkow & Gresham, P.L.C

20080296710 - Photoconductive metamaterials with tunable index of refraction: Materials and structures whose index of refraction can be tuned over a broad range of negative and positive values by applying above band-gap photons to a structure with a strip line element, a split ring resonator element, and a substrate, at least one of which is a photoconductive semiconductor material.... Agent: Naval Research Laboratory Associate Counsel (patents)

20080296712 - Assembling two substrates by molecular adhesion: t

20080296713 - Image sensor with color filters and method of manufacturing the same: An image sensor with color filters capable of minimizing a distance through which incident light reaches photodiodes and flattening the color filters by minimizing step heights among color filters, and a method of manufacturing the same are provided. In the image sensor with the color filters, a metal is doped... Agent: Ipla P.A.

20080296715 - Semiconductor device and optical device module having the same: In a solid-state imaging device 1 in which a hollow section 9 is formed between a solid-state imaging element 2 and a covering section 4 and an air path 7 extending from the hollow section 9 to the outside is formed in an adhesive section 5, a shielding section 11... Agent: Edwards Angell Palmer & Dodge LLP

20080296714 - Wafer level package of image sensor and method for manufacturing the same: Provided is a wafer level package of an image sensor capable of simply and easily packaging an image sensor in a packaging process, and a method for manufacturing the same. The wafer level package of an image sensor includes a lower substrate including an image sensor, a conductive pattern coupled... Agent: Staas & Halsey LLP

20080296716 - Sensor semiconductor device and manufacturing method thereof: A sensor semiconductor device and a manufacturing method thereof are disclosed. The method includes: providing a light-permeable carrier board with a plurality of metallic circuits; electrically connecting the metallic circuits to a plurality of sensor chips through conductive bumps formed on the bond pads of the sensor chips, wherein the... Agent: Edwards Angell Palmer & Dodge LLP

20080296719 - Infrared detector and manufacturing method thereof: An infrared detector comprises: first and second container members bonded to each other along an annular bonding portion to define a vacuum-sealed inner space, where the second container member has an infrared-transmissive property; an infrared detecting element disposed in the inner space; a first annular metallization layer formed on the... Agent: Macpherson Kwok Chen & Heid LLP

20080296717 - Packages and assemblies including lidded chips: A lidded chip is provided which includes a chip having a major surface and a plurality of first chip contacts exposed at the major surface. A lid overlies the major surface. A chip carrier is disposed between the chip and the lid, the chip carrier having an inner surface confronting... Agent: Tessera Lerner David Et Al.

20080296718 - Semiconductor device and optical device module having the same: A solid-state imaging device 1 is arranged so that a hollow section 9 is formed between a solid-state imaging element 2 and a covering section 4 and an air path 7 is formed in an adhesive section 5 so as to extend from the hollow section 9 to the outside,... Agent: Edwards Angell Palmer & Dodge LLP

20080296720 - Backside-illuminated imaging device and manufacturing method of the same: A backside-illuminated imaging device, which performs imaging by illuminating light from a back side of a semiconductor substrate to generate electric charges in the semiconductor substrate based on the light and reading out the electric charges from a front side of the semiconductor substrate, is provided and includes: a back-side... Agent: Birch Stewart Kolasch & Birch

20080296722 - Junction barrier schottky diode: A junction barrier Schottky diode has an N-type well having surface and a first impurity concentration; a p-type anode region in the surface of the well, and having a second impurity concentration; and an N-type cathode region in the surface of the well and horizontally abutting the anode region, and... Agent: Barnes & Thornburg LLP

20080296721 - Junction barrier schottky diode with dual silicides and method of manufacture: An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a... Agent: Barnes & Thornburg LLP

20080296723 - Semiconductor device: Provided is a semiconductor device that is capable of suppressing occurrence of a crystal defect in an elongated circuit region formed in an SOI substrate. Low-voltage transistor regions are separated, by multiple inner isolation layers, into multiple sub-regions. For this reason, the length of the longitudinal direction of the sub-regions... Agent: Mcginn Intellectual Property Law Group, PLLC

20080296724 - Semiconductor substrate and manufacturing method of semiconductor device: To provide a semiconductor substrate including a crystalline semiconductor layer which is suitable for practical use, even if a material different from that of the semiconductor layer is used for a supporting substrate, and a semiconductor device using the semiconductor substrate. The semiconductor substrate includes a bonding layer which forms... Agent: Eric Robinson

20080296725 - Semiconductor component and method for fabricating the same: A semiconductor component includes a substrate, two isolation structures, a conductor pattern and a dielectric layer. The isolation structures are disposed in the substrate, and each of the isolation structures has protruding portions protruding from the surface of the substrate. A trench is formed between the protruding portions. The included... Agent: Jianq Chyun Intellectual Property Office

20080296726 - Fuse structure for maintaining passivation integrity: A fuse structure (106) includes a patterned conductor disposed over a passivation layer (302), which is disposed over a substrate (110), such as, for example, an inter-layer dielectric layer of an integrated circuit. A second passivation layer (112) is formed over the integrated circuit including over the fuse structure (106),... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080296727 - Programmable poly fuse: According to one exemplary embodiment, a programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled... Agent: Farjami & Farjami LLP

20080296728 - Semiconductor structure for fuse and anti-fuse applications: A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses... Agent: Scully, Scott, Murphy & Presser, P.C.

20080296731 - Enhanced on-chip decoupling capacitors and method of making same: An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20080296730 - Semiconductor device: A semiconductor device according to the present invention has a multilayer wiring structure laminating and disposing a plurality of with sandwiching an insulating film and includes: a copper wire having copper as a main component; an insulating film formed on the copper wire; an aluminum wire having aluminum as a... Agent: Rabin & Berdo, PC

20080296729 - Semiconductor device and method of manufacturing the same: A semiconductor device is manufactured by forming a hole as being extended through a first insulating film and an insulating interlayer stacked over a semiconductor substrate, allowing side-etching of the inner wall of the hole to proceed specifically in a portion of the insulating interlayer, to thereby form a structure... Agent: Young & Thompson

20080296732 - Methods of isolating array features during pitch doubling processes and semiconductor device structures having isolated array features: Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one embodiment, ends of the features are wider than middle regions of the features. During the pitch reduction process, spacer sidewalls formed between adjacent ends of the... Agent: Trask Britt, P.C./ Micron Technology

20080296734 - Microchip and method of manufacturing microchip: A microchip formed by joining a first substrate having at least one recess on its surface and a second substrate, wherein small projections of 0.5 to 30 μm in height are formed on at least a part of the surface having the recess of the first substrate, and a coating... Agent: Fish & Richardson P.C.

20080296733 - Semiconductor wafer assembly and method of processing semiconductor wafer: A semiconductor wafer assembly includes a disk-shaped semiconductor wafer including on a face side thereof a flat area having a plurality of semiconductor devices formed thereon and a beveled surface disposed around the flat surface, and a circular adhesive film bonded to a reverse side of the semiconductor wafer. The... Agent: Greer, Burns & Crain

20080296735 - Semiconductor device and method of manufacturing the same: In the present invention, a first circuit pattern 3 composing a semiconductor element is formed on the front side of a substrate 1, a first insulating layer 2 is formed on the first circuit pattern 3, solder electrodes 5 for external connection are formed on the first insulating layer 2,... Agent: Steptoe & Johnson LLP

20080296736 - Method for reducing microloading in etching high aspect ratio structures: A method for etching features of different aspect ratios in a conductive layer is provided. The method comprises: depositing over the conductive layer with an aspect ratio dependent deposition; etching features into the conductive layer with an aspect ratio dependent etching of the conductive layer; and repeating the depositing and... Agent: Beyer Law Group LLP

20080296737 - Methods for manufacturing a structure on or in a substrate, imaging layer for generating sublithographic structures, method for inverting a sublithographic pattern, device obtainable by manufacturing a structure: m

20080296738 - Gaas semiconductor substrate and fabrication method thereof: A GaAs semiconductor substrate includes a surface layer. When an atomic ratio is to be calculated using a 3d electron spectrum of Ga atoms and As atoms measured at the condition of 10° for the photoelectron take-off angle θ by X-ray photoelectron spectroscopy, the structural atomic ratio of all Ga... Agent: Mcdermott Will & Emery LLP

20080296739 - Method of forming a thin film structure and stack structure comprising the thin film: Provided is a method of forming a thin film structure and a stack structure comprising the thin film. The method may include forming a crystalline AlxOy film, forming a LaAlO film on the crystalline AlxOy film, and crystallizing the LaAlO film by annealing the LaAlO film.... Agent: Harness, Dickey & Pierce, P.L.C

20080296740 - Method of manufacturing semiconductor device, and semiconductor device: A method for manufacturing a semiconductor device is provided that can reduce warping of manufactured products after the formation of a final protective film. The method includes, in a semiconductor device having a semiconductor substrate provided with wiring and a final protective film formed on the wiring, forming a first... Agent: Rabin & Berdo, PC

20080296741 - Semiconductor device: Passivation films including first and second layers (first passivation film) are formed on a GaAs substrate (semiconductor substrate). A SiN film (second passivation film) is formed on the passivation films as a top layer passivation film by a catalytic chemical vapor deposition. The SiN film formed by catalytic chemical vapor... Agent: Leydig Voit & Mayer, Ltd

20080296743 - Semiconductor device and method for fabricating the same: The present invention relates to a semiconductor device, and a method for fabricating a semiconductor device, which involves an oxide-nitride-oxide stack in a silicon-oxide-nitride-oxide-silicon device. Barrier characteristics of an upper blocking dielectric layer and/or a lower tunneling dielectric layer on upper and lower sides of a charge trapping dielectric layer... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080296742 - Semiconductor device, and method for fabricating thereof: A semiconductor device having silicon-oxide-nitride-oxide-silicon (SONOS) structure that overcomes spatial limitations which trap charges by not utilizing a flat, planar structure of the ONO film including a charging trap layer, thereby making it possible to improve reliability for data preserving characteristic of a SONOS device.... Agent: Sherr & Vaughn, PLLC

20080296744 - Integrated circuit: According to one embodiment, an integrated circuit includes an internal circuit and a resin layer which covers the internal circuit. A radio wave absorbing material is mixed in the resin layer.... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080296745 - Semiconductor device having semiconductor chip and antenna: A semiconductor device comprises a lead frame, an antenna formed at a predetermined position on the lead frame, and a semiconductor chip. The semiconductor chip is mounted on an island of the lead frame through a spacer.... Agent: Young & Thompson

20080296746 - Lead frame and manufacturing method thereof, and semiconductor apparatus and manufacturing method thereof: The present invention includes a plurality of mounting portions on which a semiconductor element is mounted, a plurality of electrodes to which the semiconductor elements that are mounted on each of the mounting portions are electrically connected, a corner portion which connects the plurality of mounting portions and which has... Agent: Sughrue Mion, PLLC

20080296747 - Micromechanical component having thin-layer encapsulation and production method: A micromechanical component having a substrate and having a thin-layer, as well as having a cavity which is bounded by the substrate and the thin-layer, at least one gas having an internal pressure being enclosed in the cavity. The gas phase has a non-atmospheric composition. A method for producing a... Agent: Kenyon & Kenyon LLP

20080296749 - Package stacking through rotation: A packaged microelectronic element includes a package element that further includes a dielectric element having a bottom face and a top face, first and second bond windows extending between the top and bottom faces, a plurality of chip contacts disposed at the top face adjacent to the first and second... Agent: Tessera Lerner David Et Al.

20080296748 - Transmission line stacking: A microelectronic unit has a structure including a microelectronic element such as a semiconductor chip with a first contact disposed remote from the periphery of the structure. The unit further includes first and second redistribution conductive pads disposed near a periphery of the structure and a conductive path incorporating first... Agent: Tessera Lerner David Et Al.

20080296750 - Semiconductor device: A semiconductor device comprises a semiconductor chip having a photoelectric conversion function and conductor connecting with the semiconductor chip electrically. The semiconductor chip is sealed by resin. The resin comprises a first sealing resin, second sealing resin and third sealing resin. The second sealing resin has transparency for optical signal... Agent: Young & Thompson

20080296751 - Semiconductor pac