Active solid-state devices (e.g., transistors, solid-state diodes) inventions 11/08

20080290335 - Phase change memory device and method for fabricating the same: A phase change memory device comprising a substrate. A plurality of bottom electrodes isolated from each other is on the substrate. An insulating layer crosses a portion of the surfaces of any two of the adjacent bottom electrodes. A pair of phase change material spacers is on a pair of... Agent: Quintero Law Office, PC

20080290336 - Polarized light emitting diode: Disclosed is a polarized light emitting diode (LED) capable of emitting polarized light in the front direction thereof by forming a first grating layer on a quantum well layer and forming a second grating layer on a substrate. The polarized LED includes a nitride thin film formed on a substrate,... Agent: Morgan & Finnegan, L.L.P.

20080290338 - Hyperbranched polymer, organic light-emitting diode including organic layer including the hyperbranched polymer, and method of manufacturing the organic light-emitting diode: For a detailed description about Formula 1, the Detailed Description of the Invention may be referred to. The hyperbranched polymer is excellent in view of hole injection capability and/or electron blocking capability and adhesion with an electrode, and thus, the organic light-emitting diode including the organic layer including the hyperbranched... Agent: Robert E. Bushnell

20080290339 - Organic transistor, method of forming organic transistor and organic el display with organic transistor: The present invention is directed to manufacturing an organic transistor with an organic semiconductor film formed by a coating method, without involving a process of forming a rib for forming the organic semiconductor film. To be more specific, the organic transistor of the present invention includes: (1) a source electrode... Agent: Greenblum & Bernstein, P.L.C

20080290337 - Ultrathin dielectrics and the application thereof in organic field effect transistors: An organic field effect transistor, having a substrate, a source electrode, a drain electrode and a gate electrode and an organic semiconductor material is disclosed. Arranged between the gate electrode and the organic semiconductor material is a dielectric layer (gate dielectric) obtained from a self-assembled monolayer of an organic compound... Agent: Dicke, Billig & Czaja

20080290340 - Method for fabricating a semiconductor device having embedded interconnect structures to improve die corner robustness: In a method for fabricating a semiconductor device a redundant scribe seal structure is formed. The semiconductor device includes a die having a rectangular shape with sloped corners. A scribe seal is formed to surround the die, the scribe seal having sides to form sloped corners that match the sloped... Agent: Texas Instruments Incorporated

20080290342 - Methods and apparatus for a flexible circuit interposer: A substrate having a bending region and conductive paths formed therethrough is provided. In one embodiment, conductive paths are formed from a first region on the bottom surface of the substrate, through the bending region and to a second region on the top surface of the substrate. Methods of using... Agent: Fletcher Yoder (micron Technology, Inc.)

20080290341 - Stacked semiconductor device and method of testing the same: A stacked semiconductor device includes: an internal circuit; a through electrode provided to penetrate through a semiconductor substrate; a test wiring to which a predetermined potential different from a substrate potential is supplied at a time of a test; a first switch arranged between the through electrode and the internal... Agent: Young & Thompson

20080290343 - Organic light-emitting display device: An organic light-emitting display device. The organic light-emitting display device according to an embodiment of the present invention utilizes an N-type driving transistor, and therefore it has a drain electrode of a driving transistor electrically connected to a cathode electrode of an organic light-emitting diode, wherein the organic light-emitting display... Agent: Christie, Parker & Hale, LLP

20080290344 - Image display device and method for manufacturing the same: An image display device manufactured by using a polycrystalline semiconductor film. The polycrystalline semiconductor film is composed of crystal grains with a region free from crystal grain boundaries of at least 2 μm in width and at least 3 μm in length, small crystal grain boundary groups each composed of... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080290345 - Semiconductor device having display device: A semiconductor integrated circuit having a high withstand voltage TFT and a TFT which is capable of operating at high speed in a circuit of thin film transistors (TFT) and methods for fabricating such circuit will be provided. A gate insulating film of the TFT required to operate at high... Agent: Fish & Richardson P.C.

20080290347 - Gallium nitride semiconductor and method of manufacturing the same: The present invention provides to a gallium nitride (GaN) semiconductor and a method of manufacturing the same, capable of reducing crystal defects caused by a difference in lattice parameters, and minimizing internal residual stress. In particular, since a high-quality GaN thin film is formed on a silicon wafer, manufacturing costs... Agent: Christie, Parker & Hale, LLP

20080290346 - Light emitting device and manufacturing method thereof: Provided are a light emitting device and a manufacturing method thereof. The light emitting device comprises a first conductive semiconductor layer with a lower surface being uneven in height, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer.... Agent: Birch Stewart Kolasch & Birch

20080290348 - Semiconductor device: In the present invention, a vertical MOSFET is formed by growing epitaxial Si on a SiC substrate and forming a Si oxide layer on the Si. In particular, a semiconductor device according to the present invention includes a SiC substrate, and an epitaxial Si layer formed on a surface of... Agent: Rabin & Berdo, PC

20080290349 - Compound semiconductor wafer, light emitting diode and manufacturing method thereof: A light emitting diode includes a compound semiconductor crystal layer (2) including an emission layer (22) and a conductive substrate (6) bonded to the crystal layer (2) through a metallic layer (5). The metallic layer (2) includes a first metallic layer (51) formed on one principal surface of the compound... Agent: Mcginn Intellectual Property Law Group, PLLC

20080290350 - Led lamp with exposed heat-conductive fins: In one embodiment, a LED lamp includes a heat sink including rows of exposed fins on one surface and a conductive member opposite the fins and including two electrically connected side positive electrodes, one or more negative electrode spaced from and between the positive electrodes, and one or more conductive... Agent: Sam Chen

20080290351 - Semiconductor light emitting apparatus: A light emitting apparatus with a combination of a plurality of LED chips and a phosphor layer is provided and can be configured to significantly reduce variations in chromaticity and luminance. The plurality of semiconductor light emitting devices (LED chips) are disposed with a gap therebetween, and the phosphor layer... Agent: Cermak Kenealy & Vaidya, LLP

20080290353 - Microscale optoelectronic device packages: An optoelectronic device article comprises a substrate containing at least one electrically conductive microvia, at least one emitter diode and at least one ESD diode, optionally formed in situ, disposed in or on the substrate, and an electrically conductive path between the foregoing elements. A reflector cavity may be defined... Agent: Intellectual Property / Technology Law

20080290352 - Package for light emitting device: The present invention discloses a light emitting device package, comprising: a metal base; an electrical circuit layer provided at an upper side of the metal base for providing a conductive path; a light emitting device mounted in a second region having a smaller thickness than a first region on the... Agent: Birch Stewart Kolasch & Birch

20080290354 - Light emitting diode assembly: A light emitting diode (LED) assembly, comprising a metal substrate (1) which is partly covered on one side with a dielectric layer (2) on which an electric circuit (3) is present, and a multitude of LED units (5, 6, 7) each comprising a LED chip, wherein each LED unit is... Agent: Philips Intellectual Property & Standards

20080290355 - Warm white led and its phosphor that provides orange-yellow radiation: A phosphor providing orange-yellow radiation for use in warm white LEDs (light emitting diodes) is disclosed to include a substrate prepared from a rear-earth garnet and an activating agent prepared from cerium. The phosphor has a constant radiation maximum value under excitement of InGaN, and the total chemical stoichiometric equation... Agent: Troxell Law Office PLLC One Skyline Place

20080290359 - Light emitting device and manufacturing method of the same: There is provided a light emitting device including: a package body having first and second circumferential surfaces and a plurality of side surfaces formed therebetween, the package body defined into first and second level areas including the first and second circumferential surfaces, respectively; first and second external terminal blocks each... Agent: Mcdermott Will & Emery LLP

20080290361 - Light emitting device and method of manufacturing the same: A light emitting device comprises a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, a refractive layer on the active layer, and a second conductive semiconductor layer on the refractive layer.... Agent: Birch Stewart Kolasch & Birch

20080290357 - Light-emitting diode package: A light-emitting diode (LED) package including a carrier, a pair of conductive wire units, an LED chip, and a control circuit module is provided. The carrier has a carrying portion and a ring frame connected to the periphery of the carrying portion. The carrying portion has a dome-like upper surface... Agent: Jianq Chyun Intellectual Property Office

20080290356 - Reflective layered system comprising a plurality of layers that are to be applied to a iii/v compound semiconductor material: The invention describes a method for producing a reflective layer system and a reflective layer system for application to a III/V compound semiconductor material, wherein a first layer, containing phosphosilicate glass, is applied directly to the semiconductor substrate Disposed thereon is a second layer, containing silicon nitride. A metallic layer... Agent: Fish & Richardson PC

20080290358 - Semiconductor light-emitting device and a method to produce the same: A new structure of a semiconductor optical device and a method to produce the device are disclosed. One embodiment of the optical device of the invention provides a blocking region including, from the side close to the mesa, a p-type first layer and a p-type second layer. The first layer... Agent: Smith, Gambrell & Russell

20080290360 - Silicon-based light emitting diode using side reflecting mirror: A silicon light emitting diode capable of effectively utilizing light radiated toward the lateral side of a substrate by including a side reflecting mirror is provided. The silicon-based light emitting diode includes a p-type silicon substrate having a plurality of grooves, a light emitting diode layer formed on each of... Agent: Rabin & Berdo, PC

20080290362 - Illumination device with a wavelength converting element held by a support structure having an aperture: An illumination device includes a light source, such as one or more light emitting diodes and a wavelength converting element that is mounted on an opaque support structure. The support structure includes an aperture with which the wavelength converting element is aligned so that the converted light is emitted through... Agent: Patent Law Group LLP

20080290363 - Light emitting diode package: A light emitting diode (LED) package including a heat dissipation base, an electrical insulating layer, a circuit layer, and an LED chip is provided. The electrical insulating layer is disposed on the heat dissipation base. The circuit layer is disposed on the electrical insulating layer. The circuit layer has a... Agent: Jianq Chyun Intellectual Property Office

20080290364 - Semiconductor light-emitting element and a producing method thereof: A semiconductor light-emitting element 100 is formed including a buffer layer 102, a n-type GaN layer 103, a light-emitting layer 104 and a p-type layer 105 laminated in this order on a sapphire substrate and has a light transmitting electrode 106 made of a needle crystal of ITO.... Agent: Mcginn Intellectual Property Law Group, PLLC

20080290365 - Nitride semiconductor light emitting device: A nitride semiconductor light emitting device comprising an n-side nitride semiconductor layer and a p-side nitride semiconductor layer formed on a substrate, with a light transmitting electrode 10 formed on the p-side nitride semiconductor layer, and the p-side pad electrode 14 formed for the connection with an outside circuit, and... Agent: Birch Stewart Kolasch & Birch

20080290366 - Soi vertical bipolar power component: An SOI device comprises an isolation trench defining a vertical drift zone, a buried insulating layer to which the isolation trench extends, and an electrode region for emitting charge carriers that is formed adjacent to the insulating layer and that is in contact with the drift zone. The electrode region... Agent: Stevens & Showalter LLP

20080290367 - Layouts for multiple-stage esd protection circuits for integrating with semiconductor power device: A semiconductor power device supported on a semiconductor substrate includes a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a source metal connected to the source region, and... Agent: Bo-in Lin

20080290368 - Photovoltaic cell with shallow emitter: A photovoltaic semiconductor apparatus for use in forming a solar cell with shallow emitter is disclosed. The apparatus includes first and second adjacent oppositely doped volumes of semiconductor material forming a semiconductor heterojunction. The apparatus also includes a first passivation layer of material on the front side, the first passivation... Agent: Knobbe Martens Olson & Bear LLP

20080290369 - Semiconductor light-receiving device and manufacturing method thereof: A semiconductor light-receiving device and its manufacturing method are provided which are capable of suppressing dark current and deterioration. Semiconductor crystals were sequentially grown over an n-type InP substrate, including an n-type InP buffer layer, an undoped GaInAs light absorption layer, an undoped InP diffusion buffer layer, and a p-type... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080290370 - Semiconductor devices and methods of manufacturing thereof: Semiconductor devices and methods of manufacturing thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a recess in the workpiece. The recess has a depth having a first dimension. A first semiconductive material is formed in the recess to... Agent: Slater & Matsil LLP

20080290371 - Semiconductor devices including implanted regions and protective layers: A semiconductor structure includes a Group III-nitride semiconductor layer, a protective layer on the semiconductor layer, a distribution of implanted dopants within the semiconductor layer, and an ohmic contact extending through the protective layer to the semiconductor layer.... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080290372 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, and a protective insulating film composed of silicon nitride, which is formed over a surface of the compound semiconductor layer and whose film density in an intermediate portion is lower than that in a lower portion.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080290374 - Layout for high density conductive interconnects: In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other by an average spacing... Agent: Knobbe Martens Olson & Bear LLP

20080290373 - Semiconductor memory device: In a semiconductor memory device which includes a shared sense amplifier portion, a pair of memory cell portions disposed on opposite sides of the shared sense amplifier portion, a pair of transfer gates between the pair of memory cell portions and the shared sense amplifier portion, and bit lines constituting... Agent: Sughrue Mion, PLLC

20080290375 - Integrated circuit for various packaging modes: The present invention provides an integrated circuit suitable for various packaging modes. This integrated circuit includes: a core circuit, a plurality of pads, and a selection circuit. The selection circuit is coupled between the core circuit and the pads for determining the connection state between the core circuit and the... Agent: Apex Juris, PLLC

20080290376 - Semiconductor integrated circuit: [Means for solving] In the semiconductor integrated circuit consisting of at least a first block, a second block and a third block, the third block B5 is diagonally arranged between the first bock B1 and the second block B2 at a predetermined angle of approximately 45 degrees to the both... Agent: Mcdermott Will & Emery LLP

20080290377 - Thin film transistor array panel for a liquid crystal display: A plurality of gate lines formed on an insulating substrate, each gate line including a pad for connection to an external device; a plurality of data lines intersecting the gate lines and insulated from the gate lines, each data line including a pad for connection to an external device; and... Agent: F. Chau & Associates, LLC

20080290378 - Transistor package with wafer level dielectric isolation: A low cost transistor package is provided for high power applications. The package provides high thermal conductivity and dissipation for a silicon transistor die, high current carrying capability and isolation, and high power and thermal cycle life performance and reliability. A dielectric layer is fixed to a silicon transistor die,... Agent: Delphi Technologies, Inc.

20080290379 - Dual trench isolation for cmos with hybrid orientations: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a... Agent: Scully, Scott, Murphy & Presser, P.C.

20080290380 - Semiconductor device with raised spacers: A semiconductor device includes a substrate and a gate formed on the substrate. A gate spacer is formed next to the gate. The gate spacer has a height greater than the height of the gate. A method of forming a semiconductor device includes providing a substrate with a gate layer.... Agent: Haynes And Boone, LLP

20080290381 - Capacitance noise shielding plane for imager sensor devices: A conductive shield plane electrically isolating the photodiode regions from metal interconnect lines in an imager sensor device.... Agent: David J. Paul Micron Technology, Inc.

20080290382 - Solid-state imaging device and camera: A solid-state imaging device including: a substrate; a light-receiving part; a second-conductivity-type isolation layer; a detection transistor; and a reset transistor.... Agent: Sonnenschein Nath & Rosenthal LLP

20080290383 - Cmos imaging device comprising a microlens array exhibiting a high filling rate: A CMOS imager includes a photosite array and a microlens array. The microlens array comprises microlenses of a first type and microlenses of a second type, the microlenses of first type being manufactured according to a first circular template having a first radius, the microlenses of second type being manufactured... Agent: Seed Intellectual Property Law Group PLLC

20080290385 - Method for manufacturing ferroelectric capacitor, and ferroelectric capacitor: A method for manufacturing a ferroelectric capacitor includes the steps of: forming a base dielectric film on a substrate, and forming a first plug conductive section in the base dielectric film at a predetermined position; forming, on the base dielectric film, a charge storage section formed from a lower electrode,... Agent: Harness, Dickey & Pierce, P.L.C

20080290384 - Microelectronic device provided with transistors coated with a piezoelectric layer: An improved microelectronic device, and method for making such a microelectronic device. The device includes one or plural transistors and piezoelectric mechanisms, with an arrangement capable of applying a variable mechanical strain on transistor channels.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080290386 - Floating gate memory device with increased coupling coefficient: Methods and apparatus for increasing the coupling coefficient of a floating gate memory device includes an MOS capacitors with self-aligning gate structures that provide increased capacitance per unit area over conventional MOS capacitors.... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080290388 - Semiconductor contructions: The invention includes a method in which a semiconductor substrate is provided to have a memory array region, and a peripheral region outward of the memory array region. Paired transistors are formed within the memory array region, with such paired transistors sharing a source/drain region corresponding to a bitline contact... Agent: Wells St. John P.s.

20080290387 - Semiconductor device having reduced sub-threshold leakage: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080290389 - Dynamic random access memory and manufacturing method thereof: A dynamic random access memory (DRAM) is provided. The DRAM comprises a substrate, a vertical transistor, a deep trench capacitor and a buried strap. The substrate has a trench and a deep trench located on one side of the trench thereon. The vertical transistor is disposed in the trench, a... Agent: Jianq Chyun Intellectual Property Office

20080290390 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device suitable for preventing a threshold voltage of a recess gate from decreasing due to a voltage of an adjacent storage node comprises a semiconductor substrate having an active region which includes a gate area and... Agent: Townsend And Townsend And Crew, LLP

20080290391 - Memory cell and method for manufacturing the same: The invention provides a memory cell. The memory cell is disposed on a substrate and comprises a plurality of isolation structures defining at least a fin structure in the substrate. Further, the surface of the fin structure is higher than the surface of the isolation structure. The memory cell comprises... Agent: J C Patents, Inc.

20080290392 - Semiconductor device having n-channel type mos transistor with gate electrode layer featuring small average polycrystalline silicon grain size: In a semiconductor device including a semiconductor substrate, and an n-channel type MOS transistor produced in the semiconductor substrate, the n-channel type MOS transistor includes a gate insulating layer formed on the semiconductor substrate and having a thickness of at most 1.6 nm, and a gate electrode layer on the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080290394 - Gate electrode for a nonvolatile memory cell: A nonvolatile memory cell includes a substrate comprising a source, drain, and channel between the source and the drain. A tunnel dielectric layer overlies the channel, and a localized charge storage layer is disposed between the tunnel dielectric layer and a control dielectric layer. A gate electrode has a first... Agent: Brinks Hofer Gilson & Lione

20080290393 - Nonvolatile semiconductor memory device and manufacturing method thereof, semiconductor device and manufacturing method thereof, and manufacturing method of insulating film: An object is to provide a technique to manufacture an insulating film having excellent film characteristics. In particular, an object is to provide a technique to manufacture a dense insulating film with a high withstand voltage. Moreover, an object is to provide a technique to manufacture an insulating film with... Agent: Nixon Peabody, LLP

20080290395 - Semiconductor device and method of manufacturing the same: A method of realizing a flash floating poly gate using an MPS process can include forming a tunnel oxide layer on an active region of a semiconductor substrate; and then forming a first floating gate on and contacting the tunnel oxide layer; and then forming second and third floating gates... Agent: Sherr & Vaughn, PLLC

20080290396 - Semiconductor memory: A semiconductor memory according to an aspect of this invention comprises a semiconductor substrate which includes a memory cell array region and an interconnect line region adjoining the memory cell array region, memory cells which are provided in the memory cell array region, contact plugs which are provided in the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080290397 - Memory cell and method for manufacturing and operating the same: A memory cell is disposed on a substrate having plurality of isolation structures that define at least a fin structure in the substrate, wherein the surface of the fin structure is higher than that of the isolation structures. The memory cell includes a gate, a charge trapping structure, a protection... Agent: J C Patents, Inc.

20080290398 - Nonvolatile charge trap memory device having <100> crystal plane channel orientation: A nonvolatile charge trap memory device and a method to form the same are described. The device includes a channel region having a channel length with <100> crystal plane orientation. The channel region is between a pair of source and drain regions and a gate stack is disposed above the... Agent: Cypress/blakely

20080290399 - Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having... Agent: Cypress/blakely

20080290401 - Nonvolatile semiconductor memory devices with charge injection corner: An erase method where a corner portion on which an electric field concentrates locally is provided on the memory gate electrode, and charges in the memory gate electrode are injected into a charge trap film in a gate dielectric with Fowler-Nordheim tunneling operation is used. Since current consumption at the... Agent: Miles & Stockbridge PC

20080290400 - Sonos ono stack scaling: Scaling a nonvolatile trapped-charge memory device and the article made thereby. In an embodiment, scaling includes multiple oxidation and nitridation operations to provide a tunneling layer with a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a... Agent: Cypress/blakely

20080290402 - Semiconductor device and method for fabricating the same: A semiconductor device comprises an active region including a first active area to be a source/drain and a second active area to be a gate, and a device isolation region defining the active region. The first active area is obtained by growing a semiconductor substrate located between the gates as... Agent: Townsend And Townsend And Crew, LLP

20080290403 - Semiconductor apparatus: A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on the major surface and being adjacent to the second semiconductor layer, a termination semiconductor layer provided on the major surface of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080290406 - Method for producing a vertical field effect transistor: A method for producing a field effect transistor, in which a plurality of layers are in each case deposited, planarized and etched back, in particular a gate electrode layer, is disclosed. This method allows the manufacturing of transistors having outstanding electrical properties and having outstanding reproducibility.... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080290405 - Power mosfet diode: A power MOSFET diode includes a plurality of unit elements, each of which has a gate and a drain that are connected to each other by the structure and the process of UMOS, VMOS, VDMOS, and etc., so as to integrate the unit elements into a PMD without any body... Agent: Chao-cheng Lu 4-4, Alley 27, Lane 143

20080290404 - Semiconductor device and a method for manufacturing the same: A semiconductor device includes a semiconductor substrate provided with an active region including a gate forming area, a source forming area and a drain forming area. A recess is formed in the gate forming area. A gate is formed over the gate forming area that is formed with the recess... Agent: Townsend And Townsend And Crew, LLP

20080290407 - Semiconductor device: A semiconductor device has a semiconductor substrate, an insulating film, a semiconductor element and a resistance element. The semiconductor substrate has a first trench. The insulating film covers an inner surface of the first trench. The semiconductor element has an electrode. The resistance element is electrically connected to the electrode... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080290408 - Thin silicon-on-insulator double-diffused metal oxide semiconductor transistor: A method is provided for fabricating a silicon (Si)-on-insulator (SOI) double-diffused metal oxide semiconductor transistor (DMOST) with a stepped channel thickness. The method provides a SOI substrate with a Si top layer having a surface. A thinned area of the Si top layer is formed, and a source region is... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080290409 - Halo-first ultra-thin soi fet for superior short channel control: Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is... Agent: Scully, Scott, Murphy & Presser, P.C.

20080290410 - Mosfet with isolation structure and fabrication method thereof: A MOSFET with an isolation structure is provided. An N-type MOSFET includes a first N-type buried layer and a P-type epitaxial layer disposed in a P-type substrate. A P-type FET includes a second N-type buried layer and the P-type epitaxial layer disposed in the P-type substrate. The first, second N-type... Agent: J C Patents, Inc.

20080290411 - Semiconductor device and method for fabricating the same: A semiconductor device including at least one drift region formed near a channel region on a substrate, a first buried insulating layer formed in the drift region, and a first reduced surface field region interposed between the first buried insulating layer and the drift region. Accordingly, the semiconductor device provides... Agent: Sherr & Vaughn, PLLC

20080290412 - Suppressing short channel effects: An apparatus comprising a substrate of first dopant type and first dopant concentration; pocket regions in the substrate and having the first dopant type and a second dopant concentration greater than the first dopant concentration; a gate stack over the substrate and laterally between the pocket regions; first and second... Agent: Haynes And Boone, LLP

20080290413 - Soi mosfet with a metal semiconductor alloy gate-to-body bridge: A body contact region is formed in a portion of the active region. A gate dielectric and a gate conductor layer are formed on the active region and patterned to define a gate electrode. A portion of the gate electrode is removed to expose a top surface of the body... Agent: Scully, Scott, Murphy & Presser, P.C.

20080290414 - Integrating strain engineering to maximize system-on-a-chip performance: A semiconductor device comprising a first transistor device and second transistor device both on a semiconductor substrate. The first transistor device has a first n-channel and a first p-channel and the second transistor device has a second n-channel and a second p-channel. Each of the p-channels and the n-channels have... Agent: Texas Instruments Incorporated

20080290415 - Semiconductor device and method for fabricating the same: A semiconductor device includes: an isolation region formed in a semiconductor substrate; a first active region and a second active region surrounded by the isolation region; an n-type gate electrode and a p-type gate electrode formed on gate insulating films; an insulating film and a silicon region formed on the... Agent: Mcdermott Will & Emery LLP

20080290417 - Electronic component comprising a titanium carbonitride (ticn) barrier layer and process of making the same: An electronic component comprising several superimposed layers of materials including a TiCN barrier layer. A process for depositing a TiCN layer in order to obtain an electronic component, where a titanium precursor is chosen from among tetrakis (dimethylamido) titanium and/or tetrakis (diethylamido) titanium and is decomposed on a substrate by... Agent: Seed Intellectual Property Law Group PLLC

20080290416 - High-k metal gate devices and methods for making the same: A layer of P-metal material having a work function of about 4.3 or 4.4 eV or less is formed over a high-k dielectric layer. Portions of the N-metal layer are converted to P-metal materials by introducing additives such as O, C, N, Si or others to produce a P-metal material... Agent: Duane Morris LLP (tsmc)IPDepartment

20080290419 - Low on resistance cmos transistor for integrated circuit applications: An array of power transistors on a semiconductor chip has serpentine gates separated by alternating source and drain regions. The gates combine rounded ends and rectangular sections joining the rounded ends. This geometry allows the metallization, in which the upper and lower metal layers are substantially congruent with each other,... Agent: Hiscock & Barclay, LLP

20080290418 - Method for integrating nanotube devices with cmos for rf/analog soc applications: A method is provided of integrating the formation of nanotube devices on the same substrate or wafer as CMOS devices in a standard CMOS process. During a CMOS formation process, a region of the substrate containing CMOS devices is protected from certain nanotube fabrication processes while fabricating nanotube devices on... Agent: Greenberg Traurig LLP (la)

20080290420 - Sige or sic layer on sti sidewalls: A semiconductor structure includes a semiconductor substrate; an opening in the semiconductor substrate; a semiconductor layer in the opening and covering a bottom and sidewalls of the opening, wherein the semiconductor layer and the semiconductor substrate comprise different materials; and a dielectric material over the semiconductor layer and filling a... Agent: Slater & Matsil, L.L.P.

20080290422 - Asymmetric field effect transistors (fets): A semiconductor structure. The structure includes (a) a semiconductor channel region, (b) a semiconductor source block in direct physical contact with the semiconductor channel region; (c) a source contact region in direct physical contact with the semiconductor source block, wherein the source contact region comprises a first electrically conducting material,... Agent: Schmeiser, Olsen & Watts

20080290421 - Contact barrier structure and manufacturing methods: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric... Agent: Slater & Matsil, L.L.P.

20080290423 - Nanotube-based switching element: Nanotube-based switching elements and logic circuits. Under one aspect, a switching element includes an input node; an output node; a nanotube channel element comprising a ribbon of nanotube fabric; and a control electrode disposed in relation to the nanotube channel element to form an electrically conductive channel between the input... Agent: Wilmerhale/boston

20080290424 - Transistor design self-aligned to contact: The present invention provides a method of manufacturing a transistor device, a transistor device, and a method for manufacturing an integrated circuit. In one aspect, the method of manufacturing a transistor device includes providing a gate structure (140) over a substrate (110). An insulating layer (310) is formed over the... Agent: Texas Instruments Incorporated

20080290426 - Dmos device with sealed channel processing: A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then... Agent: Schwegman, Lundberg & Woessner / Atmel

20080290425 - Method for fabricating a semiconductor element, and semiconductor element: In a method for fabricating a semiconductor element in a substrate, first implantation ions are implanted into the substrate, whereby micro-cavities are produced in a first partial region of the substrate. Furthermore, pre-amorphization ions are implanted into the substrate, whereby a second partial region of the substrate is at least... Agent: Slater & Matsil LLP

20080290428 - Use of alloys to provide low defect gate full silicidation: The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming a layer of gate electrode material over a layer of gate dielectric material, wherein the layer of gate dielectric material is positioned over a substrate. This method... Agent: Texas Instruments Incorporated

20080290427 - Use of dopants to provide low defect gate full silicidation: The invention provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming an NMOS gate structure over a substrate, wherein the NMOS gate structure includes an NMOS gate dielectric and an NMOS gate electrode. The method further includes forming... Agent: Texas Instruments Incorporated

20080290429 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, a first conductive layer over the gate insulation layer, and a second conductive layer over the first conductive layer, etching the second conductive layer to form a second gate electrode using a first mask... Agent: Townsend And Townsend And Crew, LLP

20080290430 - Stress-isolated mems device and method therefor: A stress-isolated MEMS device (14) includes a platform (26) suspended over a substrate wafer (24). In one embodiment, the platform (26) is suspended by springs (38), but other suspension techniques may also be used. A transducer (28) is formed over the platform (26). The transducer (28) includes immovable portions (50)... Agent: Meschkow & Gresham, P.L.C

20080290431 - Nanorod sensor with single-plane electrodes: A nanorod sensor with a single plane of horizontally-aligned electrodes and an associated fabrication method are provided. The method provides a substrate and forms an intermediate electrode overlying a center region of the substrate. The intermediate electrode is a patterned bottom noble metal/Pt/Ti multilayered stack. TiO2 nanorods are formed over... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080290432 - System having improved surface planarity for bit material deposition: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the... Agent: Dickstein Shapiro LLP

20080290433 - Monolithic nuclear event detector and method of manufacture: A PIN diode-based monolithic Nuclear Event Detector and method of manufacturing same for use in detecting a desired level of gamma radiation, in which a PIN diode is integrated with signal processing circuitry, for example CMOS circuitry, in a single thin-film Silicon On Insulator (SOI) chip. The PIN diode is... Agent: Hayworth, Chaney & Thomas, P.A.

20080290434 - Color photodetector apparatus with multi-primary pixels: The invention discloses the color photodetector with multi-primary is introduced to detect the incident light with specific wavelength regimes. Combining the surface plasma resonance effect with photodetector can be utilized to enhance the photo-responsivity of the demanded light wavelength and also can substitute the conventionally color filter and infrared cutter.... Agent: Bacon & Thomas, PLLC

20080290437 - Image sensor and method for manufacturing the same: An image sensor that includes a contact plug formed in the substrate; a lower electrode formed on the contact plug; a photo diode formed on the lower electrode, the photo diode having a carbon nanotube provided therein; and an upper electrode formed on the photo diode. The photo diode can... Agent: Sherr & Vaughn, PLLC

20080290436 - Photon guiding structure and method of forming the same: A photon guiding structure for reducing optical crosstalk in an image sensor and method of forming the same. The method includes forming a trench within an interlayer dielectric region formed over a photo-conversion device. The trench is formed such that it is vertically aligned with and has a horizontal cross-sectional... Agent: Dickstein Shapiro LLP

20080290435 - Wafer level lens arrays for image sensor packages and the like, image sensor packages, and related methods: Image sensor packages, lenses therefore, and methods for fabrication are disclosed. A substrate having through-hole vias may be provided, and an array of lenses may be formed in the vias. The lenses may be formed by molding or by tenting material over the vias. An array of lenses may provide... Agent: Trask Britt, P.C./ Micron Technology

20080290438 - Image sensing devices and methods for fabricating the same: Image sensing devices and methods for fabricating the same are provided. An exemplary image sensing device comprises a first substrate having a first side and a second side opposing each other. A plurality of image sensing elements is formed in the first substrate at the first side. A conductive via... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080290439 - Optical device: An optical device includes a metal film that has a first plane and a second plane electrically connected to the first plane. For example, the second plane is integrally formed with the first plane. The second plane is arranged at an obtuse angle θ (90°<θ<180°) with respect to the first... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080290440 - Photodiode for image sensor and method of manufacturing the same: A photodiode for an image sensor capable of reducing reflection of light incident onto the photodiode and effectively absorbing transmitted light and a method of manufacturing the same are provided. In the photodiode for the image sensor, a silicon concavo-convex surface with a nano-thickness is formed by forming silicon oxide... Agent: Ipla P.A.

20080290441 - Photodetector for backside-illuminated sensor: A backside-illuminated sensor including a semiconductor substrate. The semiconductor substrate has a front surface and a back surface. A plurality of pixels are formed on the front surface of the semiconductor substrate. At least one pixel includes a photogate structure. The photogate structure has a gate that includes a reflective... Agent: Haynes And Boone, LLP

20080290442 - Process for high voltage superjunction termination: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is... Agent: Panitch Schwarze Belisario & Nadel LLP

20080290443 - Semiconductor device with a plurality of isolated conductive films: A semiconductor layer provided on a BOX (buried oxide) layer includes a first P-type region, an N+-type region, and an N−-type region which together form a diode. A plurality of second P-type regions are provided on a bottom part of the semiconductor layer. A plurality of insulating oxide films are... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080290444 - Capacitor structure in a semiconductor device: A semiconductor device comprises an integrated circuit formed on a substrate with a signal interface and at least one isolator capacitor. The integrated circuit comprises a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate, a thick passivation layer formed on the plurality of the interleaved... Agent: Koestner Bertani LLP

20080290445 - Method for manufacturing a semiconductor body with a trench and semiconductor body with a trench: A method for manufacturing a semiconductor body with a trench comprises the steps of etching the trench (11) in the semiconductor body (10) and forming a silicon oxide layer (12) on at least one side wall (14) of the trench (11) and on the bottom (15) of the trench (11)... Agent: Cohen Pontani Lieberman & Pavane LLP Suite 1210

20080290447 - Semiconductor device and methods of manufacturing the same: A method of making a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) device by a process of growing Meta-stable poly silicon (MPS) regions is provided. Meta-stable poly silicon (MPS) regions are formed in the active region of a semiconductor substrate, dielectric materials are formed on the MPS regions, and control gates are formed on parts... Agent: Workman Nydegger

20080290446 - Shallow trench isolation structures for semiconductor devices including wet etch barriers and methods of fabricating same: A semiconductor device includes a sidewall oxide layer covering an inner wall of a trench, a nitride liner on the sidewall oxide layer and a gap-fill insulating layer filling the trench on the nitride liner. A first impurity doped oxide layer is provided at edge regions of both end portions... Agent: Myers Bigel Sibley & Sajovec

20080290449 - Isolation structures for integrated circuits: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall... Agent: Patentability Associates

20080290450 - Isolation structures for integrated circuits: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall... Agent: Patentability Associates

20080290451 - Isolation structures for integrated circuits: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall... Agent: Patentability Associates

20080290448 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second... Agent: Slater & Matsil LLP

20080290452 - Trench-constrained isolation diffusion for integrated circuit die: A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density... Agent: Patentability Associates

20080290453 - Semiconductor device and method of fabrication thereof: A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step... Agent: Mcdermott Will & Emery LLP

20080290455 - Semiconductor device and method of blowing fuse thereof: A semiconductor device comprises an active region including a core circuit forming region and a buffer forming region, and a fuse element forming region arranged on a corner of the active region and to be able to be electrically fused. It is possible to arrange the fuse element without forming... Agent: Young & Thompson

20080290454 - Semiconductor integrated circuit device and method for manufacturing the same: A semiconductor integrated circuit device includes a plurality of metal wirings which are separated from one another with respective interlayer insulating films; at least one interlayer conductor for connecting adjacent ones of the metal wirings via the corresponding one of the interlayer insulating films; at least one functional element formed... Agent: Amin, Turocy & Calvin, LLP

20080290456 - Electrical fuse with metal silicide pipe under gate electrode: An electrical fuse (eFuse) has a gate prepared from a conductive or partially conductive material such as polysilicon, a semiconductor substrate having a pipe region in proximity to the gate, and first and second electrode regions adjacent the pipe region. A metal silicide layer is provided on the semiconductor substrate... Agent: Banner & Witcoff, Ltd.

20080290457 - Bonding pad structure disposed in semiconductor device and related method: The present invention discloses a bonding pad structure disposed in a semiconductor device and a method for forming the bonding pad structure. The semiconductor device includes a substrate. The bonding pad structure includes a connection structure and an induction structure. The connection structure allows for a direct connection with a... Agent: North America Intellectual Property Corporation

20080290458 - Post last wiring level inductor using patterned plate process: A semiconductor structure. The semiconductor structure includes: a substrate having at least one metal wiring level within the substrate; an insulative layer on a surface of the substrate; an inductor within the insulative layer; and a wire bond pad within the insulative layer. The inductor and the wire bond pad... Agent: Schmeiser, Olsen & Watts

20080290459 - Mim capacitors: A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned... Agent: Slater & Matsil LLP

20080290460 - Chip resistor, and its manufacturing method: A chip resistor includes: a pair of upper surface electrodes formed at opposing side portions of a rectangular substrate as opposed to each other with respect to a center line of the rectangular substrate extending in a direction connecting the side portions; a resistive element formed on the rectangular substrate... Agent: Wenderoth, Lind & Ponack L.L.P.

20080290461 - Deep trench isolation for power semiconductors: An integrated power semiconductor device has an isolation structure having two or more isolation trenches, and one or more regions in between the isolation trenches, and a bias arrangement coupled to the regions to divide a voltage across the isolation structure between the isolation trenches. By dividing the voltage, the... Agent: Workman Nydegger

20080290462 - Protective structure: A protective structure is produced by providing a semiconductor substrate with a doping of a first conductivity type. A semiconductor layer with a doping of a second conductivity type is applied at a surface of the semiconductor substrate. A buried layer with doping of a second conductivity type is formed... Agent: Dickstein Shapiro LLP

20080290463 - Lateral bipolar transistor and method of production: Emitter and collector regions of the bipolar transistor are formed by doped regions of the same type of conductivity, which are separated by doped semiconductor material of an opposite type of conductivity, the separate doped regions being arranged at a surface of a semiconductor body and being in electric contact... Agent: Dicke, Billig & Czaja

20080290464 - Npn device and method of manufacturing the same: A method of forming a semiconductor device is disclosed. The method includes providing a floor for a semiconductor device by utilizing a CMOS process. The method further includes providing a BiCMOS-like process on top of the floor to further fabricate the semiconductor device, wherein the BiCMOS-like process and the CMOS... Agent: Sawyer Law Group LLP

20080290465 - Varactor element and low distortion varactor circuit arrangement: A varactor element having a junction region, in which the depletion capacitance of the varactor element varies when a reverse bias voltage is applied to the varactor element. The varactor element has an exponential depletion capacitance-voltage relation, e.g. obtained by providing a predetermined doping profile in the junction region. The... Agent: The Webb Law Firm, P.C.

20080290466 - Semiconductor element: A semiconductor element includes a semiconductor layer having a first doping density, a metallization, and a contact area located between the semiconductor layer and the metallization. The contact area includes at least one first semiconductor area that has a second doping density higher than the first doping density, and at... Agent: Slater & Matsil LLP

20080290467 - Semiconductor memory structures: A semiconductor structure includes a first conductive layer coupled to a transistor. A first dielectric layer is over the first conductive layer. A second conductive layer is within the first dielectric layer, contacting a portion of a top surface of the first conductive layer. The second conductive layer includes a... Agent: Duane Morris LLP (tsmc)IPDepartment

20080290468 - Structure of flexible electronics and optoelectronics: A method for producing a flexible electronic device is provided. The method comprises steps of providing a flexible substrate, forming an inorganic film on the flexible substrate and etching the inorganic film to obtain an electronic element of the electronic device. In another aspect, a flexible electronic device is provided.... Agent: Volpe And Koenig, P.C.

20080290469 - Edge seal for a semiconductor device and method therefor: In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed... Agent: Mr. Jerry Chruma Semiconductor Components Industries, L.L.C.

20080290470 - Integrated circuit on corrugated substrate: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges... Agent: Bever, Hoffman & Harms, LLP

20080290471 - Method for making a thin-film structure and resulting thin-film structure: A method for making a thin-film structure includes a thin film stabilized on a substrate. The structure of the thin film is defined by a material which includes at least one first chemical species. The method includes a step of inputting particles of the first chemical species into the thin... Agent: Brinks Hofer Gilson & Lione

20080290473 - Method of manufacturing semiconductor device: A method for manufacturing a semiconductor device, in which a substrate is disposed in a chamber and a fluorine-containing silicon oxide film is formed on the substrate using a plasma CVD process. The fluorine-containing silicon oxide film is formed such that the release of fluorine from this silicon oxide layer... Agent: Volentine & Whitt PLLC

20080290472 - Semiconductor interlayer-insulating film forming composition, preparation method thereof, film forming method, and semiconductor device: wherein, R2(s) may be the same or different when there are plural R2s and each independently represents a linear or branched C1-8 alkyl group, R3(s) may be the same or different when there are plural R3s and each independently represents a linear or branched C1-4 alkyl group, and n is... Agent: Myers Bigel Sibley & Sajovec

20080290474 - Multi-layer circuit substrate and method having improved transmission line integrity and increased routing density: A multi-layer circuit substrate and method having improved transmission line integrity and increased routing density uses a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20080290475 - Semiconductor integrated circuit: A semiconductor integrated circuit which is connected to a substrate by solder bumps wherein, when at least one solder bump is connected to a signal line of the semiconductor integrated circuit and the semiconductor integrated circuit is mounted on the substrate, the semiconductor integrated circuit is bonded to the substrate... Agent: Staas & Halsey LLP

20080290478 - Lead-frame array package structure and method: The present invention provides a lead-frame array package structure. The package structure includes a lead-frame, which composed of a plurality of shorter leads and a plurality of longer leads. The first surface and a second surface are composed of the shorter leads and the longer leads. The chip is fixedly... Agent: Sinorica, LLC

20080290476 - Method for making semiconductor chips having coated portions: A method for making semiconductor chips having coated portions can include mounting the chips in lead frames, stacking the lead frames in an orientation in which a portion of one lead frame masks a portion of a chip mounted on another lead frame but leaves another portion of the chip... Agent: Kathy Manke Avago Technologies Limited

20080290480 - Microelectronic assembly and method for forming the same: A microelectronic assembly and a method for forming the same are provided. The method includes forming first and second lateral etch stop walls (44, 46) in a semiconductor substrate (20) having first and second opposing surfaces (22, 24). An inductor (56) is formed on the first surface (22) of the... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080290477 - Semiconductor device: A semiconductor device having a plurality of semiconductor chips mounted on a lead frame (10) and required portions covered with seal portions in which: the plurality of semiconductor chips are divided into a first group of semiconductor chips (Dx to Dz) and a second group of semiconductor chips (Du to... Agent: Pearne & Gordon LLP

20080290479 - Wafer level device package with sealing line having electroconductive pattern and method of packaging the same: Provided are wafer level package with a sealing line that seals a device and includes electroconductive patterns as an electrical connection structure for the device, and a method of packaging the same. In the wafer level package, a device substrate includes a device region, where a device is mounted, on... Agent: Staas & Halsey LLP

20080290482 - Method of packaging integrated circuits: A method of packaging integrated circuit dice into exposed die packages is described. The method includes depositing a metallic layer onto the back surface of an integrated circuit wafer such that it covers the back surface. The method additionally includes applying a protective layer over the metallic layer such that... Agent: Beyer Law Group LLP

20080290481 - Semiconductor device package leadframe: The invention provides semiconductor device packages, leadframes, and methods for their manufacture, with improved characteristics for the formation of metallurgical joints. In a disclosed preferred embodiment of a semiconductor device leadframe according to the invention, a generally rectangular sheet metal body has a semiconductor device mounting site for receiving a... Agent: Texas Instruments Incorporated

20080290483 - Semiconductor device, leadframe and structure for mounting semiconductor device: A structure of a semiconductor device is provided, where intervals can be narrowed between leads arranged around a semiconductor element to increase the number of leads, and electrical interference is prevented or reduced between the leads to cause no crosstalk between the leads. The semiconductor device of the present invention... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080290484 - Leadframe strip and mold apparatus for an electronic component and method of encapsulating an electronic component: A leadframe strip comprises a plurality of units arranged in a line. Each unit provides two component positions, each having a chip support substrate. The chip support substrates of the two component positions are mechanically linked by at least one support bar. The two component positions of a unit are... Agent: Dicke, Billig & Czaja

20080290485 - Integrated circuit package system with relief: An integrated circuit package system including: providing a die pad with a top, sides, and a bottom, the bottom having a relief with a flat surface and defining a wall and a center pad; mounting a barrier under the bottom of the die pad; mounting an integrated circuit die on... Agent: Law Offices Of Mikio Ishimaru

20080290486 - Leadframe package: A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of... Agent: North America Intellectual Property Corporation

20080290487 - Lead frame for semiconductor device: A lead frame for a semiconductor device includes at least one row of contact terminals and a die pad for receiving an integrated circuit die. An isolation material is located between the contact terminals and the die pad. The isolation material electrically isolates adjacent lead fingers from each other and... Agent: Freescale Semiconductor, Inc. Law Department

20080290488 - semiconductor device and a method of manufacturing the same: Detachably mountable memory card featuring a memory chip(s) and a control chip includes a substrate of an insulating material, conductive layers provided on a first main surface of the substrate, a plurality of external electrode terminals exposed to the opposing, second main surface of the substrate, and conductive portions electrically... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080290489 - Package structure and electronic device using the same: A package structure and an electronic device using the same are provided. The package structure includes a chip module and a cover. The chip module covered by the cover is used for receiving a first signal. The chip module includes a substrate, a heat sink and a first chip. The... Agent: Bacon & Thomas, PLLC

20080290490 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a first substrate made of semiconductor and having first regions, which are insulated from each other and disposed in the first substrate; and a second substrate having electric conductivity and having second regions and insulation trenches. Each insulation trench penetrates the second substrate so that the... Agent: Posz Law Group, PLC

20080290491 - Semiconductor package and stacked layer type semiconductor package: In a stacked layer type semiconductor package constructed by stacking a plurality of packages with each other, the plurality of packages include a semiconductor package including: a semiconductor chip; a substrate in which a concave portion has been formed, the semiconductor chip being mounted in the concave portion; and a... Agent: Drinker Biddle & Reath (dc)

20080290492 - Semiconductor packages with enhanced joint reliability and methods of fabricating the same: Provided is a semiconductor package with enhanced joint reliability and methods of fabricating the same. The method includes: forming package units including a semiconductor chip interposed between a bottom layer and a top layer; and sequentially stacking the package units on a substrate. The bottom layer and the top layer... Agent: Marger Johnson & Mccollom, P.C.

20080290493 - Stacked chip semiconductor device: A stacked chip semiconductor device whose size is substantially reduced by high density packaging of two or more semiconductor chips. In the semiconductor device, four semiconductor chips are stacked over a printed wiring board. The bottom semiconductor chip has an interface circuit which includes a buffer and an electrostatic discharge... Agent: Miles & Stockbridge PC

20080290494 - Backside release and/or encapsulation of microelectromechanical structures and method of manufacturing same: There are many inventions described and illustrated herein. In one aspect, the present inventions relate to devices, systems and/or methods of encapsulating and fabricating electromechanical structures or elements, for example, accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), filter or... Agent: Neil Steinberg

20080290495 - Low noise semiconductor device: As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band... Agent: Stanley P. Fisher Reed Smith LLP

20080290496 - Wafer level system in package and fabrication method thereof: There is provided a system-in-package (SiP), which includes a substrate obtained by cutting a wafer for each unit system; one or more first electronic devices mounted on the substrate by a heat radiation plate; a plurality of interlayer dielectrics sequentially formed on the substrate; and one or more second electronic... Agent: Marger Johnson & Mccollom, P.C.

20080290497 - Mounting board, mounted body, and electronic equipment using the same: The mounting board has a capacitor-forming sheet made from a valve metal, first and second board-forming structures, first and second electrodes, an extractor electrode, and a conductive polymer. The capacitor-forming sheet has an inner layer and a rough oxide film on at least one face of the inner layer. The... Agent: Wenderoth, Lind & Ponack L.L.P.

20080290498 - Semiconductor device: A semiconductor device is disclosed that includes a circuit board, a semiconductor element, a heat sink, and a stress relaxation member. The circuit board includes an insulated substrate, a metal circuit joined to one side of the insulated substrate, and a metal plate joined to the other side of the... Agent: Morgan & Finnegan, L.L.P.

20080290499 - Semiconductor device: A semiconductor device is disclosed that includes a ceramic substrate having first and second surfaces, a semiconductor element, a radiator, and an interposed portion located between the second surface and the radiator. The interposed portion has coupling regions that couple the second surface to the radiator, and non-coupling regions that... Agent: Morgan & Finnegan, L.L.P.

20080290500 - Semiconductor device: A semiconductor device has a ceramic substrate having a first surface and a second surface, a metal layer that is coupled to the second surface, a heat sink that is coupled to the metal layer and a stress relaxation member. The stress relaxation member is arranged between the metal layer... Agent: Morgan & Finnegan, L.L.P.

20080290501 - Semiconductor package: There is provided a semiconductor package including: a substrate having a plurality of electrode pads on a surface thereof; a semiconductor chip mounted on the substrate, the semiconductor chip electrically connecting with the plurality of electrode pads; and a stiffener arranged on the substrate so as to surround the semiconductor... Agent: Shimokaji & Associates, P.C.

20080290503 - Compliant thermal contactor: One embodiment of the present invention is a compliant thermal contactor that includes a resilient metal film having a plurality of first thermally conductive, compliant posts disposed in an array on a top side thereof and a plurality of second thermally conductive, compliant posts disposed in an array on a... Agent: Michael B. Einschlag, Esq.

20080290504 - Compliant thermal contactor: One embodiment of the present invention is a compliant thermal contactor that includes a resilient metal film having a plurality of first thermally conductive, compliant posts disposed in an array on a top side thereof and a plurality of second thermally conductive, compliant posts disposed in an array on a... Agent: Michael B. Einschlag, Esq.

20080290502 - Integrated circuit package with soldered lid for improved thermal performance: An integrated circuit die includes a circuit surface and a back surface opposite the circuit surface. An underbump metallurgy is formed on a back surface. A layer of solder is formed on the underbump metallurgy.... Agent: Lsi Logic Corporation Corporate Legal Department

20080290505 - Mold design and semiconductor package: A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed... Agent: HorizonIPPte Ltd

20080290506 - Semiconductor module and inverter device: A semiconductor module includes a base plate; a plurality of substrates placed on one surface of the base plate, with each substrate of the plurality of substrates including a switching element, a diode element, and a connection terminal area; and a parallel flow forming device that forms parallel coolant flow... Agent: Oliff & Berridge, PLC

20080290507 - Chip embedded printed circuit board and fabricating method thereof: The chip embedded printed circuit board and a fabricating method thereof are disclosed, wherein a circuit pattern is formed by depositing a metal layer on a support layer, a semiconductor chip is packaged on a support layer to wrap the semiconductor chip and the circuit pattern on the support layer... Agent: Lee, Hong, Degerman, Kang & Waimey

20080290508 - Semiconductor device, substrate, equipment board, method for producing semiconductor device, and semiconductor chip for communication: A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a plurality of first communication units for transmitting... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080290510 - Apparatus for crack prevention in integrated circuit packages: A microelectronic package having integrated circuits is provided. The microelectronic package includes multiple dielectric laminate layers, copper circuitry between the dielectric laminate layers where the copper circuitry includes circuit traces, and ball grid arrays/land grid arrays operatively connected to the copper circuitry such that conduction occurs. Further, proximate to the... Agent: Cantor Colburn LLP - IBM Fishkill

20080290511 - Chip assembly and method of manufacturing thereof: An assembly of a first chip (100) and a second chip (200), which first chip (100) is flexible and is provided with a first and a second resin layer (12, 52) on opposite sides (1, 2) of the chip (100), which allows to keep the first chip under compressive conditions,... Agent: Philips Intellectual Property & Standards

20080290509 - Chip scale package and method of assembling the same: A method of producing a chip scale package is disclosed. The method includes dicing a wafer into a plurality of chip arrays, each array including two or more integrated circuit chips. The method further includes mounting each array on a substrate and dicing each array, attached to the substrate, into... Agent: Sughrue Mion, PLLC

20080290512 - Semiconductor device and fabrication method thereof: For a suppressed breakage after a flip chip connection of a semiconductor device using a low-permittivity insulation film and a lead-free solder together, with an enhanced production yield, bump electrodes (2) are heated by a temperature profile having, after a heating up to a melting point of the bump electrodes... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080290514 - Semiconductor device package and method of fabricating the same: In a semiconductor device, a package including the semiconductor device and a method of forming the same, the semiconductor device package includes a semiconductor device, a wiring board, and an underfill material layer. The semiconductor device includes a semiconductor chip, a metal layer, and solder balls for bump contacts. The... Agent: Mills & Onello LLP

20080290513 - Semiconductor package having molded balls and method of manufacturing the same: Provided are a semiconductor package having molded balls on a bottom surface of a PCB and a method of manufacturing the semiconductor package. The semiconductor package includes: a semiconductor chip mounting member comprising circuit patterns on a first surface, an insulating layer defining openings exposing at least portions of the... Agent: Marger Johnson & Mccollom, P.C.

20080290518 - Dielectric interconnect structures and methods for forming the same: Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In... Agent: Hoffman Warnick LLC

20080290519 - Dual liner capping layer interconnect structure: A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer... Agent: International Business Machines Corporation Dept. 18g

20080290515 - Properties of metallic copper diffusion barriers through silicon surface treatments: In accordance with the invention, there are diffusion barriers, integrated circuits, and semiconductor devices and methods of fabricating them. The method of fabricating a diffusion barrier can include providing a dielectric layer, forming a first silicon enriched layer over the dielectric layer by exposing the dielectric layer to a silicon-containing... Agent: Texas Instruments Incorporated

20080290517 - Semiconductor device: A semiconductor device of the present invention includes an insulating film made of a low dielectric constant material having a smaller specific dielectric constant than SiO2, a wiring trench formed in the insulating film, a first barrier film made of SiO2 or SiCO formed at least on the side surface... Agent: Rabin & Berdo, PC

20080290516 - Semiconductor device with bonding pad support structure: A semiconductor device having bonding pads on a semiconductor substrate includes: an upper copper layer that is formed on the lower surface of the bonding pads with a barrier metal interposed and that has a copper area ratio that is greater than layers in which circuit interconnects are formed; and... Agent: Young & Thompson

20080290520 - Reliable metal bumps on top of i/o pads after removal of test probe marks: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.... Agent: Mou-shiung Lin

20080290522 - Carbon containing silicon oxide film having high ashing tolerance and adhesion: A semiconductor device includes an interlayer insulating film formed on or over a semiconductor substrate. An opening is formed in the interlayer insulating film and reaches a lower layer metal wiring conductor. A metal plug is formed by filling the opening with Cu containing metal via a barrier metal. The... Agent: Katten Muchin Rosenman LLP

20080290521 - Film-forming composition, insulating film with low dielectric constant, formation method thereof, and semiconductor device: In the invention, a silica sol prepared by hydrolyzing and condensing a silane compound represented by the following formula: Si(OR1)4 or R2nSi(OR3)4-n wherein R1s, R2(s) and R3(s) may be the same or different when a plurality of them are contained in the molecule and each independently represents a linear or... Agent: Myers Bigel Sibley & Sajovec

20080290523 - Semiconductor device including barrier metal and coating film and method for manufacturing same: A semiconductor device includes an interconnection layer provided on a substrate, a first insulating film provided on the substrate, and on the interconnection layer so as to coat the interconnection layer, the first insulating film includes a silicon oxide film, a second insulating film provided on the first insulating film,... Agent: Mcginn Intellectual Property Law Group, PLLC

20080290524 - Through via in ultra high resistivity wafer and related methods: A through via in an ultra high resistivity wafer and related methods are disclosed. A method for forming a through via comprises: providing a semiconductor wafer including a first silicon layer, a buried dielectric layer, and a substrate; forming a device on the first silicon; and forming a via from... Agent: Hoffman Warnick LLC

20080290527 - Methods for forming arrays of small, closely spaced features: Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed,... Agent: Knobbe Martens Olson & Bear LLP

20080290525 - Silicon-on-insulator structures for through via in silicon carriers: A silicon-on-insulator (SOI) structure is provided for forming through vias in a silicon wafer carrier structure without backside lithography. The SOI structure includes the silicon wafer carrier structure bonded to a silicon substrate structure with a layer of buried oxide and a layer of nitride lo separating these silicon structures.... Agent: John A. Jordan, Esq.

20080290526 - Test patterns for detecting misalignment of through-wafer vias: A semiconductor chip including a test pattern is provided. The semiconductor chip includes a semiconductor substrate; a through-wafer via in the semiconductor substrate; and a plurality of conductive patterns over the semiconductor substrate and adjacent to each other. The bottom surfaces of the plurality of conductive patterns and a top... Agent: Slater & Matsil, L.L.P.

20080290528 - Semiconductor package substrate having electrical connecting pads: A semiconductor package substrate having electrical connecting pads includes: a substrate body having a plurality of electrical connecting pads formed on surface thereof, and a plurality of protruding lumps or concave areas of any geometric shape respectively formed on surfaces of the electrical connecting pads for increasing contact surfaces of... Agent: Sawyer Law Group LLP

20080290529 - Semiconductor device and process for fabrication thereof: A semiconductor chip is attached to a lead frame with a filmy organic die-bonding material having a water absorption of 1.5% by volume or less; having a saturation moisture absorption of 1.0% by volume or less, having a residual volatile component in an amount not more than 3.0% by weight,... Agent: Griffin & Szipl, PC

20080290530 - Semiconductor device having photo aligning key and method for manufacturing the same: Embodiments consistent with the present invention provide a semiconductor device having a photo aligning key and a method for manufacturing the same. The semiconductor device includes a pattern photo aligning key formed on a scribe line of a semiconductor substrate, and a plurality of dummy pattern keys formed around the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080283812 - Phase-change memory element: A phase-change memory element. The phase-change memory comprises first and second electrodes. A phase-change material layer is formed between the first and second electrodes. And a carbon-doped oxide dielectric layer is formed to surround the phase-change material layer, wherein the first electrode electrically connects the second electrodes via the phase-change... Agent: Quintero Law Office, PC

20080283813 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device includes first conductive lines on a substrate, an interlayer insulating layer with a plurality of via holes on the substrate, second conductive lines on the interlayer insulating layer, and a resistive memory material in the via holes and electrically connected to the first and second conductive... Agent: Lee & Morse, P.C.

20080283814 - Phase-change memory element: A phase-change memory element for reducing heat loss is disclosed. The phase-change memory element comprises a composite layer, wherein the composite layer comprises a dielectric material and a low thermal conductivity material. A via hole is formed within the composite layer. A phase-change material occupies at least one portion of... Agent: Quintero Law Office, PC

20080283817 - Phase-change nonvolatile memory device using sb-zn alloy and manufacturing method thereof: Provided are a phase-change nonvolatile memory device and a manufacturing method thereof. The device includes: a substrate; and a stack structure disposed on the substrate and including a phase-change material layer. The phase-change material layer is formed of an alloy of antimony (Sb) and zinc (Zn), so that the phase-change... Agent: Cantor Colburn, LLP

20080283816 - Semiconductor memory device and method of manufacturing the same: A semiconductor device is provided with silicon pillars arranged in a matrix and formed substantially perpendicularly to a main surface of a substrate, bit lines provided above the silicon pillars, gate electrodes covering a side surface of each silicon pillars via gate insulation films, first and second diffusion layers provided... Agent: Sughrue Mion, PLLC

20080283815 - Variable resistance memory device having reduced bottom contact area and method of forming the same: A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical... Agent: Dickstein Shapiro LLP

20080283820 - Led packaged structure and applications of led as light source: LED packaged structures and applications thereof are disclosed, characterized in that: an active layer in the LED or the LED packaged structure is formed on a first semiconductor conductive layer with multi-quantum wells; and a second semiconductor conductive layer is formed on the active layer; wherein a plurality of particles... Agent: Reed Smith LLP

20080283821 - Method of growing gan crystal on silicon substrate, and light emitting device and method of manufacturing thereof: Example embodiments are directed to a method of growing GaN single crystals on a silicon substrate, a method of manufacturing a GaN-based light emitting device using the silicon substrate, and a GaN-based light emitting device. The method of growing the GaN single crystals may include forming a buffer layer including... Agent: Harness, Dickey & Pierce, P.L.C

20080283818 - Semiconductor heterostructure: A strained semiconductor heterostructure (10) comprises an injection region comprising a first emitter layer (11) having p-type conductivity and a second emitter layer (12) having n-type conductivity, and a light generation layer (13) positioned between the first emitter layer (11) and the second emitter layer (12). An electron capture region... Agent: Fay Sharpe LLP

20080283819 - Semiconductor light emitting device: A Si substrate 1, a metal adhesion layer 2, a reflective metal film 3 comprising a multilayer of metallic material having a light reflectivity, a SiO2 film 4, an ohmic contact portion 5 provided at a predetermined position of the SiO2 film 4, a GaP layer 6 including a Mg-doped... Agent: Scully Scott Murphy & Presser, PC

20080283822 - Semiconductor light emitting device: A semiconductor light emitting device includes a substrate and a quantum well active layer. The quantum well active layer has a plurality of barrier layers made of GaN-based semiconductor and a well layer made of GaN-based semiconductor sandwiched between the barrier layers and has polarized charge between the barrier layer... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080283823 - Gallium nitride-based semiconductor stacked structure: A gallium-nitride-based semiconductor stacked structure includes a sapphire substrate; a low temperature-deposited buffer layer which is composed of a Group III nitride material of AlxGayN (0.5<Y≦1, X+Y=1) containing gallium (Ga) in a predominant amount with respect to aluminum (Al), which has been grown at low temperature and which is provided... Agent: Sughrue Mion, PLLC

20080283824 - Method and structure for forming strained si for cmos devices: A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only... Agent: Greenblum & Bernstein, P.L.C

20080283826 - Aryl dicarboxylic acid diimidazole-based compounds as n-type semiconductor materials for thin film transistors: A thin film transistor comprises a layer of organic semiconductor material comprising an organic semiconductor material that comprises an aryl dicarboxylic acid diimidazole-based compound. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating... Agent: Eastman Kodak Company Patent Legal Staff

20080283825 - Dual-gate transistors: A field effect transistor device comprising: a source electrode; a drain electrode; a semiconductive region comprising an organic semiconductor material and defining a channel of the device between the source electrode and the drain electrode; a first gate structure comprising a first gate electrode and a first dielectric region located... Agent: Sughrue Mion, PLLC

20080283827 - Fused-fluorene-containing materials as semiconductor materials for thin film transistors: A thin film transistor comprises a layer of organic semiconductor material comprising an organic semiconductor material that comprises fused-fluorene-containing materials. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating a thin film transistor... Agent: Andrew J. Anderson Patent Legal Staff

20080283829 - Organic insulator composition including a hydroxyl group-containing polymer, dielectric film and organic thin film transistor using the same: An organic insulator composition including a crosslinking agent and a hydroxyl group-containing oligomer or hydroxyl group-containing polymer is provided. A dielectric film and an organic thin film transistor (OTFT) using an organic insulator composition are also provided. A dielectric film may include a compound having hydroxyl group-containing oligomers or hydroxyl... Agent: Harness, Dickey & Pierce, P.L.C

20080283828 - Organic semiconductor polymer having liquid crystal properties, organic active layer, organic thin film transistor, and electronic device including the same, and methods of fabricating the same: Example embodiments relate to an organic semiconductor polymer, in which fused thiophenes having liquid crystal properties and aromatic compounds having N-type semiconductor properties are alternately included in the main chain of the polymer, an organic active layer, an organic thin film transistor (OTFT), and an electronic device including the same,... Agent: Harness, Dickey & Pierce, P.L.C

20080283830 - Zinc-tin oxide thin-film transistors: Methods of forming transparent zinc-tin oxide structures are described. Devices that include transparent zinc-tin oxide structures as at least one of a channel layer in a transistor or a transparent film disposed over an electrical device that is at a substrate.... Agent: Schwegman, Lundberg & Woessner, P.A.

20080283831 - Zno-based thin film transistor and method of manufacturing the same: A ZnO-based thin film transistor (TFT) is provided herein, as is a method of manufacturing the TFT. The ZnO-based TFT has a channel layer that comprises ZnO and ZnCl, wherein the ZnCl has a higher bonding energy than ZnO with respect to plasma. The ZnCl is formed through the entire... Agent: Cantor Colburn, LLP

20080283832 - Integrated circuit comprising an amorphous region and method of manufacturing an integrated circuit: An integrated circuit comprises a doped semiconductor portion including an amorphous portion and a contact structure comprising a conductive material. The contact structure is in contact with the amorphous portion. According to another embodiment, an integrated circuit comprises a doped semiconductor portion including a region having a non-stoichiometric composition and... Agent: Fay Kaplun & Marcin, LLP

20080283836 - Light emitting display device and method for fabricating the same: Disclosed are a light emitting display and a method for fabricating the same. The light emitting display includes a substrate. A thin film transistor is formed on a first region of the substrate, and includes a semiconductor layer, a gate electrode, and source/drain electrodes. An organic light emitting diode is... Agent: Knobbe Martens Olson & Bear LLP

20080283837 - Semiconductor device: An object is to provide a structure for forming a circuit for which high-speed operation and low-voltage operation are required and a circuit for which sufficient reliability is required at the time of high voltage application in a circuit group provided over one substrate in a semiconductor device, and a... Agent: Fish & Richardson P.C.

20080283838 - Semiconductor device and manufacturing method thereof: A semiconductor device packaged in three dimensions comprises a first thin film device, a second thin film device, and a third thin film device, each of the first, second, and third thin film devices comprising a first insulating film, a first electrode formed over the first insulating film, a second... Agent: Fish & Richardson P.C.

20080283835 - Semiconductor device and method of manufacturing the same: To reduce variation among TFTs in manufacture of a semiconductor device including n-type thin film transistors and p-type thin film transistors. Further, another object of the present invention is to reduce the number of masks and manufacturing steps, and manufacturing time. A method of manufacturing a semiconductor device includes forming... Agent: Nixon Peabody, LLP

20080283833 - Thin film transistor array panel and manufacturing method thereof: The present invention provides a thin film transistor comprising: a substrate (110); a gate electrode (124) formed on the substrate; a gate insulating layer (140) covering the substrate and the gate electrode; a source electrode and a drain electrode (173, 175) formed on the gate insulating layer; a semiconductor layer... Agent: F. Chau & Associates, LLC

20080283839 - Non-volatile semiconductor storage device and manufacturing method thereof: A non-volatile semiconductor storage device includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed of polysilicon on the first insulating layer, a pair of conductor regions formed on the first insulating layer to pass through the semiconductor layer and to sandwich a part of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080283840 - Thin film transistor device and method of manufacturing the same, and liquid crystal display device: The present invention relates to a thin film transistor device formed on an insulating substrate of a liquid crystal display device and others, a method of manufacturing the same, and a liquid crystal display device. In structure, there are provided the steps of forming a negative photoresist film on a... Agent: Greer, Burns & Crain

20080283841 - Tft substrate and manufacturing method, and display device with the same: In forming a TFT and a storage capacitance element, whereas sharing with each other the conductive film and the insulation film, which are components of the TFT and the storage capacitance element, contributes to improving production efficiency, it is difficult to obtain a storage capacitance element that is optimized independently... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080283843 - Display device and electronic device using thin-film transistors formed on semiconductor thin films which are crystallized on insulating substrates: A method of receiving video data, a control signal, etc. via a non-contact transmission path is adopted, and a receiving circuit for receiving and amplifying a signal is formed on the same insulating substrate as a display device. Thus, there are provided a thin-film transistor which is formed in a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080283842 - Method for making semiconductor apparatus and semiconductor apparatus obtained by the method, method for making thin film transistor substrate and thin film transistor substrate obtained by the method, and method for making display apparatus and display a: A method for making a semiconductor apparatus including the steps of: forming a laminate structure of an insulating film made of a metal oxide and a semiconductor thin film on a substrate; forming a light absorption layer on top of the laminate structure; and irradiating an energy beam of a... Agent: Sonnenschein Nath & Rosenthal LLP

20080283844 - Method for manufacturing a field effect transistor having a field plate: An opening for forming a gate electrode is provided by a first photoresist pattern formed on an insulating film. Reactive ion etching by inductively coupled plasma is applied to the insulating film through the first photoresist pattern as a mask to thereby expose the surface of a GaN semiconductor layer,... Agent: Rabin & Berdo, PC

20080283845 - Silicon carbide semiconductor device having high channel mobility and method for manufacturing the same: A silicon carbide semiconductor device having a MOS structure includes: a substrate; a channel area in the substrate; a first impurity area; a second impurity area; a gate insulating film on the channel area; and a gate on the gate insulating film. The channel area provides an electric current path.... Agent: Posz Law Group, PLC

20080283846 - Method for growing semiconductor layer, method for producing semiconductor light-emitting element, semiconductor light-emitting element, and electronic device: Disclosed herein is a method for growing a semiconductor layer which includes the step of growing a semiconductor layer of hexagonal crystal structure having the (11-22) or (10-13) plane direction on the (1-100) plane of a substrate of hexagonal crystal structure.... Agent: Sonnenschein Nath & Rosenthal LLP

20080283847 - Integrated circuit package provided with cooperatively arranged illumination and sensing capabilities: An integrated circuit package includes an angled one-piece substrate having a light source fixed to one area and a sensor die fixed to a second area, such that the light source is directed to illuminate the field of view of the sensor die when a surface of interest is imaged.... Agent: Kathy Manke Avago Technologies Limited

20080283848 - Semiconductor device and method for manufacturing the same: A plurality of rectangle semiconductor substrates are attached to a single mother glass substrate. A pixel structure is determined so that even if a gap or a an overlapping portion is generated in a boundary between a plurality of semiconductor substrates, a single-crystal semiconductor layer does not overlap with the... Agent: Eric Robinson

20080283849 - Led device and method by which it is produced: A LED device formed of LED chips bonded to an exoergic member by the LED chips being bonded to an Au—Sn alloy layer formed on an upper surface of the exoergic member with columnar crystals being formed within the Au—Sn alloy layer extending in a direction perpendicular to the upper... Agent: Roberts Mlotkowski Safran & Cole, P.C. Intellectual Property Department

20080283851 - Gan substrate, and epitaxial substrate and semiconductor light-emitting device employing the substrate: GaN substrate (30) whose growth plane (30a) is oriented off-axis with respect to either the m-plane or the a-plane. That is, in the GaN substrate (30), the growth plane (30a) is either an m-plane or an a-plane that has been misoriented. Inasmuch as the m-plane and the a-plane are nonpolar,... Agent: Judge Patent Associates

20080283852 - Light-emitting device and a method for producing the same: A light-emitting device and a method to from the device are is described. The device described herein may realize the transversely single mode operation by the buried mesa configuration even when the active layer contains aluminum. The method provides a step to form the mesa on a semiconductor substrate with... Agent: Smith, Gambrell & Russell

20080283850 - Reflective positive electrode and gallium nitride-based compound semiconductor light-emitting device using the same: The inventive reflective positive electrode for a semiconductor light-emitting device comprises a contact metal layer adjoining a p-type semiconductor layer, and a reflective layer on the contact metal layer, wherein the contact metal layer is formed of a platinum group metal or an alloy containing a platinum group metal, and... Agent: Sughrue Mion, PLLC

20080283853 - Light-emitting diode, light-emitting diode substrate and production method of light-emitting diode: The light-emitting diode is a light-emitting diode including a light-converting material substrate and a semiconductor layer formed on the light-converting material substrate, wherein the light-converting material substrate includes a solidified body in which at least two or more oxide phases selected from a simple oxide and a complex oxide are... Agent: Ip Group Of Dla Piper US LLP

20080283854 - Light emitting diode device layer structure using an indium gallium nitride contact layer: A light emitting diode device layer structure including a p-type contact layer that contains at least some indium (In), wherein the p-type contact layer is a not-intentionally doped strained nitride contact layer.... Agent: Gates & Cooper LLP Howard Hughes Center

20080283860 - Light emitting device: A light emitting device includes an emission portion, an optical control portion for reflecting or refracting light emitted from the emission portion in a predetermined direction, a light guiding member including a light input surface to which the reflected or refracted light is inputted, a refection region formed on a... Agent: Mcginn Intellectual Property Law Group, PLLC

20080283858 - Light-emitting diode and method for manufacturing same: A light-emitting diode includes: a light-emitting structure, a transparent electrically conductive thick film, a first electrical contact and a second electrical contact. The light-emitting structure includes a first-type cladding layer, a second-type cladding layer, and an active layer sandwiched between the first-type cladding layer and the second-type cladding layer. The... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang

20080283859 - Light-emitting diode apparatus and manufacturing method thereof: A light-emitting diode (LED) apparatus includes an epitaxial multilayer, a micro/nano rugged layer and an anti-reflection layer. The epitaxial multilayer has a first semiconductor layer, an active layer and a second semiconductor layer in sequence. The micro/nano rugged layer is disposed on the first semiconductor layer of the epitaxial multilayer.... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20080283856 - Light-emitting diode module and the manufacturing thereof: A method for manufacturing a light-emitting diode (LED) module is provided. Plural LED package structures are formed on a substrate first. A space is located between two adjacent LED package structures. A Lens laminated plate is subsequently bonded to the LED package structures. The lens laminated plate includes plural lenses,... Agent: Raymond R. Moser Jr., Esq. MoserIPLaw Group

20080283857 - Novel phosphor for white light-emitting diodes and fabrication of the same: m

20080283855 - Optoelectronic thin-film chip: An optoelectronic thin-film chip is specified, comprising at least one radiation-emitting region (8) in an active zone (7) of a thin-film layer (2) and a lens (10, 12) disposed downstream of the radiation-emitting region (8). The lens is formed by at least one partial region of the thin-film layer (2),... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20080283861 - Power light emitting die package with reflecting lens and the method of making the same: A light emitting die package and a method of manufacturing the die package are disclosed. The die package includes a leadframe, at least one light emitting device (LED), a molded body, and a lens. The leadframe includes a plurality of leads and has a top side and a bottom side.... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20080283862 - Side-emission type semiconductor light-emitting device and manufacturing method thereof: A side-emission type semiconductor light-emitting device 10 includes a substrate 12, and the substrate 12 is provided with a case 14 formed of a resin having opacity and reflectivity. The substrate 12 is formed, on its surface, with electrodes 18a and 18b onto which an LED chip 20 is bonded.... Agent: Bodner & O'rourke, LLP

20080283863 - Transparent electrode: In order to emit a light from an electrode side, in semiconductor light emitting devices such as LED and the like, and liquid crystal, the electrode is formed of a transparent material so as to transmit a light through the transparent electrode and exit the light. A ZnO, which constitutes... Agent: Hogan & Hartson L.L.P.

20080283834 - Electrochromic display: An electrochromic display is disclosed which comprises an array-side substrate (10) wherein a TFT (14) and a pixel electrode (15) connected with the TFT (14) are formed, a color filter-side substrate (50) wherein a counter electrode (53) is formed, and an electrolyte layer (80) injected between the array-side substrate (10)... Agent: Foley & Lardner LLP

20080283864 - Single crystal phosphor light conversion structures for light emitting devices: Solid state light emitting devices include a solid state light emitting die and a light conversion structure. The light conversion structure may include a single crystal phosphor and may be on a light emitting surface of the solid state light emitting die. The light conversion structure may be attached to... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080283865 - Iii-nitride compound semiconductor light emitting device: The present invention relates a III-nitride compound semiconductor light emitting device in which a first layer composed of a carbon-containing compound layer, such as an n-type or p-type silicon carbide (SiC), silicon carbon nitride (SiCN) or carbon nitride layer (CN) layer, is formed on the p-type III-nitride semiconductor layer of... Agent: Darby & Darby P.C.

20080283866 - Nitride semiconductor light-emitting device and method for producing same: In a method for producing a nitride semiconductor light-emitting device according to the present invention, first, a nitride semiconductor substrate having groove portions formed is prepared. An underlying layer comprising nitride semiconductor is formed on the nitride semiconductor substrate including the side walls of the groove portions, in such a... Agent: Harness, Dickey & Pierce, P.L.C

20080283867 - Semiconductor device: A fourth semiconductor region of a first conduction type is provided in a partial region of a third semiconductor region of a second conduction type. This configuration enhances the blocking voltage at the time when the sheet carrier concentration of a fifth semiconductor region is enhanced.... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080283868 - Semiconductor device: A semiconductor device includes a first layer having a first conductivity type, a second layer having a second conductivity type, a third layer having the second conductivity type, one or more first zones having the first conductivity type and located within the second layer, wherein each one of the one... Agent: Coats & Bennett/infineon Technologies

20080283869 - Method for manufacturing semiconductor light emitting device: A method for manufacturing a semiconductor light emitting device, which is capable of providing high characteristic homogeneity and reproducibility, is disclosed. The disclosed method includes forming a buffer layer over a substrate, selectively growing a nitride crystal layer on the buffer layer, forming a nitride semiconductor layer having a multilayer... Agent: Ked & Associates, LLP

20080283870 - Field-effect semiconductor device: A HEMT-type field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on the main semiconductor region. Between these... Agent: Woodcock Washburn LLP

20080283871 - Semiconductor integrated circuit: A semiconductor integrated circuit having a substantially rectangular standard cell divided by first borderlines opposed to other standard cells longitudinally adjacent to the standard cell and second borderlines opposed to other standard cells laterally adjacent to the standard cell, the standard cell has: a p-type MOS transistor having first diffused... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080283872 - Variable path wiring cell, semiconductor integrated circuit designing method thereof, and forming method of variable path wiring cell: Provided are a first wiring layer where each of the first, second internally present wirings can be selectively connected to the first and the second externally extended wirings, and a second wiring layer that has substantially the same structure as that of the first wiring layer. There is further provided... Agent: Mcdermott Will & Emery LLP

20080283873 - Semiconductor device and method of manufacturing the same: A semiconductor device has a first semiconductor layer including a first circuit, a second semiconductor layer disposed on the first semiconductor layer and having a second circuit, and a via extending through portions of the first and second semiconductor layers and by which the first and second circuits are electrically... Agent: Volentine & Whitt PLLC

20080283874 - Field-effect transistors: The present invention provides a field-effect transistor and method for the fabrication of a field-effect transistor by deposition on a substrate (480), which method comprises a wet chemical deposition of materials that react to form a semi-conducting material. The materials deposited include cadmium, zinc, lead, tin, bismuth, antimony, indium, copper... Agent: Philips Intellectual Property & Standards

20080283875 - Field effect transistor, biosensor provided with it, and detecting method: A high-sensitivity field effect transistor using as a channel ultrafine fiber elements such as carbon nanotube, and a biosensor using it. The field effect transistor comprises a substrate, a source electrode and a drain electrode arranged on the substrate, a channel for electrically connecting the source electrode with the drain... Agent: Greenblum & Bernstein, P.L.C

20080283876 - Noise detection circuit: Noise occurring in a circuit is more accurately detected. A low-pass filter (11) is connected to a power supply line for a power supply terminal (VDD), and noise in the power supply line is removed to generate and output a referential voltage (V0). A high-pass filter (12) is connected to... Agent: Mcginn Intellectual Property Law Group, PLLC

20080283877 - Strained-channel transistor device: piezoelectric layer being arranged between two biasing electrodes, one of the two biasing electrodes being formed by a first layer based on at least one electrically conductive material such that the piezoelectric layer is arranged between this first conductive layer and the gate of the transistor.... Agent: Thelen LLP

20080283878 - Method and apparatus for monitoring endcap pullback: Various apparatus and methods of monitoring endcap pullback are disclosed. In one aspect, an apparatus is provided that includes a substrate that has a plurality of semiconductor regions. Each of the plurality of semiconductor regions has a border with an insulating structure. A transistor is positioned in each of the... Agent: Timothy M Honeycutt Attorney At Law

20080283879 - Transistor having gate dielectric layer of partial thickness difference and method of fabricating the same: A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick... Agent: Mills & Onello LLP

20080283884 - Cmos image device with polysilicon contact studs: A CMOS image device comprises a pixel array region including a photo diode region, a floating diffusion region, and at least one MOS transistor having a gate and a junction region, a CMOS logic region disposed around the pixel array region, the CMOS logic region including a plurality of nMOS... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080283887 - Cmos image sensor: A method of fabricating a CMOS image sensor is disclosed, by which image sensor characteristics are enhanced. In one aspect, the method includes forming a plurality of photodiodes in the photodiode region of a semiconductor substrate; stacking a first insulating layer over the semiconductor substrate including the photodiodes; forming a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080283880 - Cmos pixel sensor with depleted photocollectors and a depleted common node: An active pixel sensor in a p-type semiconductor body includes an n-type common node formed below a pinning region. A plurality of n-type blue detectors more lightly doped than the common node are disposed below pinning regions and are spaced apart from the common node forming channels below blue color-select... Agent: Lewis And Roca LLP

20080283881 - Image sensor and method for manufacturing the same: An image sensor according to one embodiment of the present invention includes a semiconductor substrate having a CMOS circuit formed therein; an interlayer dielectric layer formed on the semiconductor substrate and including a trench formed therein; a metal wiring and a first conductive layer formed within the trench of the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080283883 - Image sensor and method for manufacturing the same: An image sensor and a method for manufacturing the same are provided. The image sensor can include transistor circuitry on a substrate, and a photodiode arranged above the transistor circuitry. The photodiode can include carbon nanotubes and a conductive polymer layer on the carbon nanotubes. A transparent conducting electrode can... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080283882 - Semiconductor device: A semiconductor device includes: a compound semiconductor substrate; a buffer layer, a channel layer, and a Schottky junction forming layer sequentially formed on the compound semiconductor substrate, the buffer layer, the channel layer, and the Schottky junction forming layer each being a compound semiconductor; a source electrode and a drain... Agent: Leydig Voit & Mayer, Ltd

20080283885 - Small pixel for cmos image sensors with vertically integrated set and reset diodes: A pixel of an image sensor, the pixel includes a floating diffusion node to sense photo-generated charge, a reset diode to reset the floating diffusion node in response to a reset signal, and a set diode to set the floating diffusion node.... Agent: Morgan Lewis & Bockius LLP

20080283886 - Small pixel for image sensors with jfet and vertically integrated reset diode: A pixel and a pixel array of an image sensor device of the present invention have small pixel sizes by resetting sensed charge using a diode built vertically above a substrate. The pixel and the pixel array also have low noise performance by using a JFET as a source follower... Agent: Morgan Lewis & Bockius LLP

20080283888 - Spin transistor, programmable logic circuit, and magnetic memory: A spin transistor includes a non-magnetic semiconductor substrate having a channel region, a first area, and a second area. The channel region is between the first and the second areas. The spin transistor also includes a first conductive layer located above the first area and made of a ferromagnetic material... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080283889 - Semiconductor device: The present invention aims to enhance the reliability of a semiconductor device having first through fourth capacitive elements. The first through fourth capacitive elements are disposed over a semiconductor substrate. A series circuit of the first and second capacitive elements and a series circuit of the third and fourth capacitive... Agent: Miles & Stockbridge PC

20080283892 - Cylinder-type capacitor and storage device, and method(s) for fabricating the same: A one cylinder storage device and a method for fabricating a capacitor are disclosed, realizing simplified fabrication by overexposure with a mask having a plurality of holes, in which the method includes forming a contact hole in an insulating layer on a semiconductor substrate; forming a conductive layer on the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080283890 - Deep trench inter-well isolation structure: A deep trench is formed in a semiconductor substrate. The deep trench may comprise a pair of parallel substantially vertical sidewalls having a constant separation distance. A set of outer substantially vertical sidewalls may have a closed shape in a horizontal cross-section. At least one dielectric layer is formed in... Agent: Scully, Scott, Murphy & Presser, P.C.

20080283891 - Semiconductor structure and manufacturing method thereof: A semiconductor structure comprises a first wafer and a second wafer, between which a glue layer can be used for combination. The first wafer comprises a first semiconductor cell structure, and a surface of the first wafer comprises conductive pads electrically connected to the first semiconductor cell structure. The second... Agent: Wpat, PC Intellectual Property Attorneys

20080283894 - Forming floating body ram using bulk silicon substrate: A method for forming Z-RAM cells and the resulting semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate; a dielectric layer on the semiconductor substrate; an opening in the dielectric layer, wherein the semiconductor substrate is exposed through the opening; a semiconductor strip on the dielectric layer and... Agent: Slater & Matsil, L.L.P.

20080283893 - Illuminating efficiency-increasable and light-erasable embedded memory structure and fabricating method thereof: An illuminating efficiency-increasable and light-erasable embedded memory structure including a substrate, a memory device, many dielectric layers, many cap layers and at least three metal layers is described. The substrate includes a memory region and a core circuit region. The memory device includes a select gate and a floating gate,... Agent: J C Patents, Inc.

20080283895 - Memory structure and fabricating method thereof: A memory structure including a substrate, dielectric patterns, spacer patterns, a first dielectric layer, a conductor pattern, a second dielectric layer and doped regions is described. The dielectric patterns are disposed on the substrate. The spacer patterns are disposed on each sidewall of each of the dielectric patterns respectively. The... Agent: Jianq Chyun Intellectual Property Office

20080283896 - Nonvolatile semiconductor memory device with twin-well: A nonvolatile semiconductor memory device includes a first well of a first conductivity type, which is formed in a semiconductor substrate of the first conductivity type, a plurality of memory cell transistors that are formed in the first well, a second well of a second conductivity type, which includes a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080283899 - Conductive spacers extended floating gates: n

20080283897 - Flash memory device and fabrication method thereof: The invention provides a flash memory device and a method for fabricating thereof. The device comprises a gate stack layer of a gate dielectric layer and a gate polysilicon layer formed on a substrate, a stack layer comprising a floating polysilicon layer and gate spacer formed on the sidewall of... Agent: Quintero Law Office, PC

20080283898 - Non-volatile semiconductor memory device and method of manufacturing the same: A non-volatile semiconductor memory device comprises a plurality of memory cells, each including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a floating gate formed on the semiconductor substrate with the inclusion of the first insulating film, a second insulating film formed on the floating gate,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080283900 - Semiconductor device and method for manufacturing the same: Disclosed is a method of manufacturing a semiconductor device, which includes exposing a photoresist using an exposing mask provided with a light-shielding pattern having two or more narrow width portions, developing the photoresist to form a plurality of stripe-shaped resist patterns, selectively etching a first conductive film using the resist... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080283902 - Non-volatile memory device and method of manufacturing the same: A method of manufacturing a non-volatile memory device includes sequentially depositing a first insulation layer, a charge storage layer, and a second insulation layer on a substrate, forming a first opening through the resultant structure to expose the substrate, forming second and third openings through the second insulation layer to... Agent: Lee & Morse, P.C.

20080283901 - Nonvolatile memory with multiple bits per cell: A dual-gate memory cell includes a first memory device and a second memory device each having a gate electrode and a charge storage gate dielectric layer. The first and second memory devices share a channel region and source and drain regions. Such a memory cell is read by sensing the... Agent: Macpherson Kwok Chen & Heid LLP

20080283903 - Transistor with quantum dots in its tunnelling layer: According to an example embodiment there is a semiconductor component, which is arranged in a semiconductor body, with at least one source zone and with at least one drain zone which in each case is a first conductivity type, with at least one body zone of a second conductivity type... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080283905 - Nonvolatile memory devices and methods of fabricating the same: Provided are nonvolatile memory devices and methods of fabricating the same which may prevent or reduce deterioration of device characteristics and deterioration of a breakdown voltage. The nonvolatile memory device may include a semiconductor substrate, a charge-trap insulation layer on the semiconductor substrate and having a first region and second... Agent: Harness, Dickey & Pierce, P.L.C

20080283904 - Two-bit flash memory cell and method for manufacturing the same: A two-bit flash memory cell includes a substrate, a gate oxide layer disposed on the substrate, a gate stacked on the gate oxide layer. A charge storage spacer stack is disposed at either side of the gate. The charge storage spacer stack includes a bottom charge storage layer and an... Agent: North America Intellectual Property Corporation

20080283906 - Semiconductor device having tipless epitaxial source/drain regions: A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20080283908 - Lateral dmos device structure and manufacturing method thereof: A lateral DMOS device having a structure that prevents breakdown of a semiconductor device while enhancing the breakdown voltage property. The lateral DMOS device can include a body diode region having a second conduction type well region formed in a first conduction type semiconductor substrate, the second conduction type well... Agent: Sherr & Vaughn, PLLC

20080283907 - Semiconductor device and method of manufacturing the same: A semiconductor device is provided with first and second silicon pillars formed substantially perpendicularly to a main surface of a substrate, a gate electrode covering side surfaces of the first and second silicon pillars via a gate insulation film, first and second diffusion layers provided on a lower part and... Agent: Sughrue Mion, PLLC

20080283909 - Semiconductor device and method for manufacturing same: A semiconductor device includes a second-conductivity-type base region provided on a first-conductivity-type semiconductor layer, a first-conductivity-type source region provided on the second-conductivity-type base region, a gate insulating film covering an inner wall of a trench which passes through the second-conductivity-type base region and reaching the first-conductivity-type semiconductor layer, a gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080283910 - Integrated circuit and method of forming an integrated circuit: An integrated circuit and method of forming an integrated circuit is disclosed. One embodiment includes a FinFET of a first type having a first gate electrode and a FinFET of a second type having a second gate electrode. The first gate electrode is formed in a gate groove that is... Agent: Dicke, Billig & Czaja

20080283911 - High-voltage semiconductor device and method for manufacturing the same: A high-voltage semiconductor device and a method for manufacturing the same are disclosed. The disclosed high-voltage semiconductor device includes a semiconductor substrate, a first N type well in the semiconductor substrate, a first P type well in the first N type well, second N type wells in the first N... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080283913 - Semiconductor device: A semiconductor device includes a semiconductor substrate and a super junction structure on the substrate. The super junction structure is constructed with p-type and n-type column regions that are alternately arranged. A p-type channel layer is formed to a surface of the super junction structure. A trench gate structure is... Agent: Posz Law Group, PLC

20080283914 - Semiconductor device and method for manufacturing the same: An impurity buried layer constructed by two buried regions formed by impurities of identical type exist, a buried region formed by an impurity having a slow diffusion speed is provided on the entire surface of a transistor formation region, and a buried region formed by an impurity having a fast... Agent: Mcginn Intellectual Property Law Group, PLLC

20080283912 - Semiconductor device having super junction structure and method of manufacturing the same: A semiconductor device includes a silicon substrate having a (110)-oriented surface, a PN column layer disposed on the (110)-oriented surface, a channel-forming layer disposed on the PN column layer, a plurality of source regions disposed at a surface portion of the channel-forming layer, and gate electrodes penetrate through the channel-forming... Agent: Posz Law Group, PLC

20080283915 - High voltage semiconductor device and method of manufacturing the same: The present invention provides a high voltage semiconductor device and a method of manufacturing the same. The high voltage semiconductor device includes: a semiconductor substrate; a first high voltage N-type well formed on the semiconductor substrate; a first high voltage P-type well formed inside the first high voltage N-type well;... Agent: Sherr & Vaughn, PLLC

20080283920 - Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates: A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080283917 - Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby: Methods of fabricating a semiconductor structure in which a body of monocrystalline silicon is formed on a sidewall of a sacrificial mandrel and semiconductor structures made by the methods. After the body of monocrystalline silicon is formed, the sacrificial material of the mandrel is removed selective to the monocrystalline silicon... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080283916 - Semiconductor substrate, semiconductor device and manufacturing method thereof: It is an object to provide a method for manufacturing a semiconductor substrate in which contamination of a semiconductor layer due to an impurity is prevented and the bonding strength between a support substrate and the semiconductor layer can be increased. An oxide film containing first halogen is formed on... Agent: Eric Robinson

20080283919 - Single and double-gate pseudo-fet devices for semiconductor materials evaluation: Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior... Agent: Scully, Scott, Murphy & Presser, P.C.

20080283918 - Ultra thin channel (utc) mosfet structure formed on box regions having different depths and different thicknesses beneath the utc and sourcedrain regions and method of manufacture thereof: A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. A UT SOI channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than... Agent: Graham S. Jones, Ii

20080283921 - Dual-gate nmos devices with antimony source-drain regions and methods for manufacturing thereof: A dual-gate device includes an active layer between a first gate structure and a second gate structure. Each gate structure is isolated from the active layer by a dielectric layer and is located above a semiconductor or channel region in the active layer defined by spaced-apart diffusion regions formed by... Agent: Macpherson Kwok Chen & Heid LLP

20080283922 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a first conductivity type well formed on a semiconductor substrate, and a first transistor and a second transistor formed on the well. The first transistor has first pocket regions containing a first conductivity type impurity and first source/drain regions containing a second conductivity type impurity, and... Agent: Mcdermott Will & Emery LLP

20080283923 - Semiconductor device and manufacturing method thereof: A semiconductor device and a manufacturing method thereof are provided. The manufacturing method can form a structure of a thin film transistor (TFT) having a symmetric lightly doped region, and thus provide superior operation reliability and electrical performance. In addition, the manufacturing method forms gate patterns of different TFTs by... Agent: Jianq Chyun Intellectual Property Office

20080283925 - Multi-fin component arrangement and method for manufacturing a multi-fin component arrangement: In a first embodiment, a multi-fin component arrangement has a plurality of multi-fin component partial arrangements. Each of the multi-fin component partial arrangements has a plurality of electronic components, which electronic components have a multi-fin structure. At least one multi-fin component partial arrangement has at least one dummy structure, which... Agent: Slater & Matsil LLP

20080283924 - Semiconductor device and method for fabricating the same: The semiconductor device comprises a silicon wafer 10, a multilayer interconnection 12 buried in inter-layer insulation film formed on the upper surface of the silicon wafer 10, and a silicon nitride film 16b which is formed on the back surface of the silicon wafer 10 and is an insulation film... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080283926 - Method for integrating silicon germanium and carbon doped silicon within a strained cmos flow: The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes providing a substrate having a PMOS device region and NMOS device region. Thereafter, a first gate structure and a second gate structure are formed over the PMOS device... Agent: Texas Instruments Incorporated

20080283929 - Semiconductor device and manufacturing method of the same: In a p channel MOS transistor and an n channel MOS transistor each having a gate electrode made of metal on a gate insulating film made of oxide whose relative dielectric constant is higher than that of silicon oxide, threshold voltage thereof is reduced. A gate insulating film of a... Agent: Miles & Stockbridge PC

20080283928 - Semiconductor device and manufacturing method thereof: A semiconductor device comprises a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate insulating film formed on a first active region, and a first gate electrode formed on the first gate insulating film. The second MIS transistor includes a second gate insulating... Agent: Mcdermott Will & Emery LLP

20080283927 - Tunable stressed polycrystalline silicon on dielectrics in an integrated circuit: System and method for creating stressed polycrystalline silicon in an integrated circuit. A preferred embodiment comprises manufacturing an integrated circuit, comprising forming a trench in an integrated circuit substrate, forming a cavity within the integrated circuit substrate, wherein the cavity is linked to the trench, depositing a dielectric layer within... Agent: Slater & Matsil LLP

20080283930 - Extended depth inter-well isolation structure: By depositing and forming a spacer out of a semiconductor material layer or a dielectric material layer on the edges of an inter-well isolation area while forming a plug over an intra-well isolation area, a narrow intra-well isolation trench having a normal depth is formed in the intra-well isolation area,... Agent: Scully, Scott, Murphy & Presser, P.C.

20080283931 - Otp memory cell, otp memory, and method of manufacturing otp memory cell: An OTP memory cell according to the present invention includes: a semiconductor substrate including a lower electrode forming region having a lower electrode formed therein, a diffusion layer forming region having a source and a drain formed therein, a first trench-type insulating region, and a second trench-type insulating region; an... Agent: Mcginn Intellectual Property Law Group, PLLC

20080283933 - Oxygen-rich layers underlying bpsg: An integrated circuit structure and a method of forming the same are provided. The method includes providing a surface; performing an ionized oxygen treatment to the surface; forming an initial layer comprising silicon oxide using first process gases comprising a first oxygen-containing gas and tetraethoxysilane (TEOS); and forming a silicate... Agent: Slater & Matsil, L.L.P.

20080283932 - Semiconductor device manufactured using a gate silicidation involving a disposable chemical/mechanical polishing stop layer: In one aspect, there is provided a method of manufacturing a semiconductor device that comprises placing a blocking layer, a CMP stop layer and a bulk oxide layer over an oxide cap layer that is located over gate structures and source/drains located adjacent thereto. The bulk oxide layer and the... Agent: Texas Instruments Incorporated

20080283934 - Substantially l-shaped silicide for contact and related method: A structure, semiconductor device and method having a substantially L-shaped silicide element for a contact are disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the structure includes a substantially L-shaped silicide element including a base member... Agent: Hoffman Warnick LLC

20080283935 - Trench isolation structure and method of manufacture therefor: The disclosure provides a trench isolation structure, a semiconductor device, and a method for manufacturing a semiconductor device. The semiconductor device, in one embodiment, includes a substrate having a first device region and a second device region, wherein the first device region includes a first gate structure and first source/drain... Agent: Texas Instruments Incorporated

20080283936 - Silicon germanium flow with raised source/drain regions in the nmos: Provided is a method for manufacturing a semiconductor device that includes a substrate having a PMOS device region and NMOS device region. A first gate structure including a first hardmask and a second gate structure including a second hardmask are formed in the region and region, respectively. Epitaxial SiGe regions... Agent: Texas Instruments Incorporated

20080283937 - Semiconductor device and method for fabricating the same: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device can include a transistor structure, including a gate dielectric on a substrate, a gate electrode on the gate dielectric, a spacer at sidewalls of the gate electrode, and source/drain regions in the substrate; and an... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080283938 - Semiconductor device and method for manufacturing the same: Provided are a semiconductor device and a method for manufacturing the same. The semiconductor device may include a substrate having a plurality of isolation areas formed therein, the isolation areas defining an active region, a gate electrode formed on the active region, spacers formed on sides of the gate electrode,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080283939 - Dielectric-modulated field effect transistor and method of fabricating the same: The present invention relates to a Field-Effect Transistor (FET) and, more particularly, to a Dielectric-Modulated Field-Effect Transistor (DMFET) and a method of fabricating the same. A DMFET according to an embodiment of the present invention comprises a substrate in which a source and a drain are formed, wherein the source... Agent: Buchanan, Ingersoll & Rooney PC

20080283940 - Low-temperature grown high quality ultra-thin cotio3 gate dielectrics: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from alloys such as cobalt-titanium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a... Agent: Schwegman, Lundberg & Woessner/micron

20080283941 - Fabrication of transistors with a fully silicided gate electrode and channel strain: An integrated circuit includes one or more transistors on or in a semiconductor substrate. At least one of the transistors includes a gate electrode and source and drain structures. The gate electrode has a fully silicided gate electrode layer with a ratio of Ni:Si ranging from about 2:1 to about... Agent: Texas Instruments Incorporated

20080283943 - Electronic device comprising a mems element: The device (100) comprises a MEMS element (60) in a cavity (30) that is closed by a packaging portion (17) on a second side (2) of the substrate (10). Contact pads (25) are defined on a flexible resin layer (13) on an opposite first side (1) of the substrate. Electrical... Agent: Philips Intellectual Property & Standards

20080283942 - Package and packaging assembly of microelectromechanical sysyem microphone: A package of a MEMS microphone is suitable for being mounted on a printed circuit board. The package includes a substrate, at least one MEMS microphone, and a conductive sealing element. The MEMS microphone is arranged on the substrate, and electrically connected to a conductive layer on a bottom surface... Agent: Jianq Chyun Intellectual Property Office

20080283944 - Photostructurable glass microelectromechanical (mems) devices and methods of manufacture: A Film Bulk Acoustic (FBA) MEMS device in a wafer level package including a photostructurable glass material and methods of manufacture are described.... Agent: Kathy Manke Avago Technologies Limited

20080283945 - Semiconductor device: A lower electrode is formed over a semiconductor substrate via an insulator film, first and second insulator films are formed to cover the lower electrode, an upper electrode is formed over the second insulator film, third to fifth insulator films are formed to cover the upper electrode and a void... Agent: Miles & Stockbridge PC

20080283946 - Magnetoresistive random access memory and method of manufacturing the same: A magnetic random access memory includes a transistor having a gate electrode formed above a surface of a substrate, and first and second impurity diffusion regions which sandwich a channel region below the gate electrode, a first plug formed on the first impurity diffusion region, a recording element formed on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080283947 - Radiation image detector: A thermal deformation preventing layer is located between a recording photoconductive layer, which contains a-Se as a principal constituent, and a crystallization preventing layer, which is constituted of an a-Se layer containing at least one kind of element selected from the group consisting of As, Sb, and Bi. The thermal... Agent: Sughrue Mion, PLLC

20080283949 - Image sensor and method for manufacturing the same: An image sensor and a method for manufacturing the same are provided. The image sensor comprises a pixel region defined on a substrate, an interlayer dielectric on the substrate and comprising a trench above the pixel region, a color filter within the trench, and a microlens on the color filter.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080283950 - Image sensor and method of manufacturing the same: An image sensor and method for manufacturing the same are provided. The image sensor can include a semiconductor substrate, a metal interconnection layer, a light-receiving unit, a lens-type upper electrode, and a color filter. The semiconductor substrate can include a circuit region. The metal interconnection layer can include a metal... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080283948 - Semiconductor device having image sensor: A pixel area for generating an image signal corresponding to incident light is formed on a semiconductor substrate. A light-shielding layer is formed on the semiconductor substrate around the pixel area. The light-shielding layer has a slit near the pixel area and shields the incident light. A passivation film is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080283951 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a semiconductor substrate having a first electronic circuit and a second electronic circuit formed on an active surface, a pad electrode formed on the active surface by being connected to the first electronic circuit and/or the second electronic circuit, a first opening formed to some point... Agent: Rader Fishman & Grauer PLLC

20080283952 - Semiconductor package, method of fabricating the same and semiconductor package module for image sensor: Provided are a semiconductor package, a method of fabricating the same, and a semiconductor package module for an image sensor The semiconductor package includes a mounting portion on which a semiconductor chip is mounted; a semiconductor chip including a plurality of bonding pads disposed along an edge thereof, wherein the... Agent: Ipla P.A.

20080283953 - Negative feedback avalanche diode: A single-photon avalanche detector is disclosed that is operable at wavelengths greater than 1000 nm and at operating speeds greater than 10 MHz. The single-photon avalanche detector comprises a thin-film resistor and avalanche photodiode that are monolithically integrated such that little or no additional capacitance is associated with the addition... Agent: Demont & Breyer, LLC

20080283954 - Image sensor and method for manufacturing the same: Provided are an image sensor and a method for manufacturing the same. The image sensor includes a substrate, a first electrode, an intrinsic layer, a second conductive type conduction layer, and a second electrode. Circuitry including a lower interconnection is disposed on the substrate. The first electrode, the intrinsic layer,... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080283955 - Temperature sensing device: The present invention relates to an integrated device, comprising a semiconductor device formed on a semiconductor substrate, a temperature sensing element formed within a semi-conductive layer formed on the semiconductor substrate, an electrically insulating layer formed over the semi-conductive layer, a metal layer formed over the insulation layer and forming... Agent: Freescale Semiconductor, Inc. Law Department

20080283956 - Process for high voltage superjunction termination: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is... Agent: Panitch Schwarze Belisario & Nadel LLP

20080283957 - Method of fabricating semiconductor device having self-aligned contact plug and related device: Methods of fabricating a semiconductor device having a self-aligned contact plug are provided. Methods include forming a lower insulating layer on a semiconductor substrate, forming a plurality of interconnection patterns parallel to each other on the lower insulating layer; forming an upper insulating layer that is configured to fill between... Agent: Myers Bigel Sibley & Sajovec

20080283958 - Semiconductor device and method for manufacturing the same: It is an object to achieve high performance of a semiconductor integrated circuit depending on not only a microfabrication technique but also another way and to achieve low power consumption of a semiconductor integrated circuit. A semiconductor device is provided in which a crystal orientation or a crystal axis of... Agent: Eric Robinson

20080283960 - Production of a carrier wafer contact in trench insulated integrated soi circuits having high-voltage components: The invention relates to a method for producing structures which make it possible to form a trench insulation and to bring into contact SOI wafers provided with active thick layers and which are easily processable. For this purpose, a carrier wafer electric contact and the insulation trench are provided with... Agent: Hunton & Williams LLP Intellectual Property Department

20080283959 - Tapered through-silicon via structure: An integrated circuit structure includes a substrate; a through-silicon via (TSV) in the substrate, the TSV being tapered; a hard mask region extending from a top surface of the substrate into the substrate, wherein the hard mask encircles a top portion of the TSV; dielectric layers over the substrate; and... Agent: Slater & Matsil, L.L.P.

20080283961 - Semiconductor device and method of producing the same: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from... Agent: Mcdermott Will & Emery LLP

20080283962 - Self-aligned and extended inter-well isolation structure: A pedestal is formed out of the pad layer such that two edges of the pedestal coincide with a border of the wells as implanted. An extended pedestal is formed over the pedestal by depositing a conformal dielectric layer. The area of the extended pedestal is exposed the semiconductor surface... Agent: Scully, Scott, Murphy & Presser, P.C.

20080283963 - Electrical fuse circuit for security applications: A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage... Agent: K & L Gates LLP

20080283964 - Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application: An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original... Agent: Scully, Scott, Murphy & Presser, P.C.

20080283965 - Semiconductor device: A semiconductor device includes, in one semiconductor substrate: a plurality of switching elements connected between a terminal of an input voltage and an inductor; a driver circuit connected to a gate electrode of the switching element and driving the switching element; a reference voltage line connected to a source electrode... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080283966 - High density capacitor using topographic surface: Capacitor area is increased in the vertical direction by forming capacitors on topographic features on the chip. The features are formed during existing process steps. Adding vertical topography increases capacitance per unit area, reducing die size at no added development cost or mask steps.... Agent: Texas Instruments Incorporated

20080283967 - Semiconductor device: In a semiconductor device including a bipolar transistor, a base region has a two layer structure including a first base region, and a second base region which is provided around the first base region and has a lower impurity density than that of the first base region and has a... Agent: Mcginn Intellectual Property Law Group, PLLC

20080283968 - Group iii-nitride semiconductor crystal and manufacturing method thereof, and group iii-nitride semiconductor device: A method of manufacturing group III-nitride semiconductor crystal includes the steps of accommodating an alloy containing at least a group III-metal element and an alkali metal element in a reactor, introducing a nitrogen-containing substance in the reactor, dissolving the nitrogen-containing substance in an alloy melt in which the alloy has... Agent: Mcdermott Will & Emery LLP

20080283969 - Seal ring structure with improved cracking protection: An integrated circuit structure includes a semiconductor chip comprising a plurality of dielectric layers, wherein the plurality of dielectric layers includes a top dielectric layer; and a first seal ring adjacent edges of the semiconductor chip. The integrated circuit structure further includes a first passivation layer over a top dielectric... Agent: Slater & Matsil, L.L.P.

20080283971 - Semiconductor device and its fabrication method: A semiconductor device and a fabrication method thereof are disclosed. The method includes attaching a wafer with a plurality of chips on a carrier board having an insulating layer, a plurality of conductive circuits and a bottom board; forming a plurality of first grooves between solder pads of adjacent chips... Agent: Wpat, PC Intellectual Property Attorneys

20080283970 - Semiconductor integrated circuit device and process for manufacturing the same: A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080283973 - Integrated circuit including a dielectric layer and method: An integrated circuit including a dielectric layer and a method for producing an integrated circuit. In one embodiment, a dielectric layer is deposited in a process atmosphere. The process atmosphere includes a first starting component at a first point in time, a second starting component at a second point in... Agent: Dicke, Billig & Czaja

20080283974 - Semiconductor device and method of manufacturing semiconductor device: Disclosed herein is a semiconductor device including a gate insulating film formed over a semiconductor substrate, and a gate electrode formed over the gate insulating film, wherein the gate insulating film is so provided as to protrude from both sides of the gate electrode, and the gate electrode includes a... Agent: Sonnenschein Nath & Rosenthal LLP

20080283972 - Silicon compounds for producing sio2-containing insulating layers on chips: The present invention relates to a process for producing an SiO2-containing insulating layer on chips and the use of specific precursors for this purpose. The invention further relates to an insulating layer obtainable in this way and also to chips which have been provided with such an insulating layer.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080283975 - Formation of a silicon oxide interface layer during silicon carbide etch stop deposition to promote better dielectric stack adhesion: In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure including one or more copper interconnects and forming an etch... Agent: Texas Instruments Incorporated

20080283976 - Electromagnetic shielding device for an infrared receiver: An electromagnetic shielding device in an infrared receiver comprises of a wiring frame (4) of metal and an electromagnetic shielding cover (1) of metal. There is a window (2) in the electromagnetic shielding cover (1), in which there is provided a shielding net (3). The electromagnetic shielding cover (1) has... Agent: Hovey Williams LLP

20080283977 - Stacked packaged integrated circuit devices, and methods of making same: A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged integrated circuit device and a plurality of planar conductive members conductively coupling the first and second packaged integrated circuit devices to one another. A method is also... Agent: Perkins Coie LLP Patent-sea

20080283981 - Chip-on-lead and lead-on-chip stacked structure: A chip-stacked package structure comprises a lead frame, a first chip, and a second chip. The led frame is composed of a plurality of inner leads and a plurality of outer leads. The plurality of inner leads comprises a plurality of first inner leads in parallel and a plurality of... Agent: Sinorica, LLC

20080283980 - Lead frame for semiconductor package: A lead frame (10) for a quad flat non-leaded semiconductor package (606), includes a tie bar (12), a first group of leads (22) extending a first length from the tie bar (12) in a transverse direction (Y), and a second group of leads (24) extending a second length from the... Agent: Freescale Semiconductor, Inc. Law Department

20080283978 - Leadframe for a semiconductor device: A leadframe (40) for a semiconductor device has a radially extending leads (42) having inner lead portions (44) and outer lead portions (46), and a dam bar (48) that mechanically connects the leads (42) together near the outer lead portions (46). The inner lead portions (44) define an open area... Agent: Freescale Semiconductor, Inc. Law Department

20080283979 - Semiconductor package having reduced thickness: A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of the chip paddle. The leads are in... Agent: Stetina Brunda Garred & Brucker

20080283982 - Multi-chip semiconductor device having leads and method for fabricating the same: The present invention proposes a multi-chip semiconductor device having leads and a method for fabricating the same. The method includes the steps of: providing a substrate having a plurality of connection pads disposed on a surface thereof; mounting a plurality of semiconductor chips on the surface of the substrate, and... Agent: Edwards Angell Palmer & Dodge LLP

20080283984 - Package structure and manufacturing method thereof: A package structure and a manufacturing method thereof are provided. The package structure includes a leadframe, a die, a solder layer and several connecting components. The leadframe includes a heat dissipation pad and several leads. The heat dissipation pad is disposed in a substantial center of the leadframe. The leads... Agent: Bacon & Thomas, PLLC

20080283983 - Semiconductor device and manufacturing method thereof: A portion of a frame body is fixed on a surface of a heat-radiating plate, and on frame body, a semiconductor chip is die-bonded. Next, a prescribed electrode of semiconductor chip and corresponding lead terminal and the like are electrically connected by a prescribed wire. Next, the lead frame is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080283985 - Circuit substrate, molding semiconductor device, tray and inspection socket: Vias 7 penetrating a circuit substrate 2 or a seal ring 8 are provided on a part or the entire outer periphery of a molding semiconductor device 1 or in the cut region of the circuit substrate 2, so that adhesion between a substrate and a core 2C in the... Agent: Steptoe & Johnson LLP

20080283987 - Semiconductor device and method for manufacturing the same: An object is to realize a hermetically sealed package which ensures long-term airtightness inside the package by sealing using a substrate, or a sealing structure for reducing destruction caused by pressure from the outside. A frame of a semiconductor material is provided over a first substrate, which is bonded to... Agent: Fish & Richardson P.C.

20080283986 - System-in-package type semiconductor device: A system-in-package type semiconductor device includes a plurality of semiconductor chips, a first semiconductor chip 1110 to which electric power is supplied from first power supply wiring 1111, and first ground wiring 1112 to which the first circuit unit is coupled. Moreover, the system-in-package type semiconductor device includes a second... Agent: Muirhead And Saturnelli, LLC

20080283988 - Package and packaging assembly of microelectromechanical sysyem microphone: A package of microelectromechanical system (MEMS) microphone is suitable for being mounted on a printed circuit board. The package has a cover and at least one MEMS microphone. The cover has an inner surface and a conductive trace disposed thereon. The MEMS microphone is mounted on the inner surface of... Agent: Jianq Chyun Intellectual Property Office

20080283989 - Wafer level package and wafer level packaging method: Provided are a wafer level package and a wafer level packaging method, which are capable of performing an attaching process at a low temperature and preventing contamination of internal devices. In the wafer level package, a device substrate includes a device region, where a device is formed, and internal pads... Agent: Staas & Halsey LLP

20080283990 - Method of fabrication of ai/ge bonding in a wafer packaging environment and a product produced therefrom: A method of bonding of germanium to aluminum between two substrates to create a robust electrical and mechanical contact is disclosed. An aluminum-germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between... Agent: Sawyer Law Group LLP

20080283991 - Housed active microstructures with direct contacting to a substrate: A microstructured component with microsensors or other active mircrocomponent is provided. The microstructured component includes a substrate and at least one housing arranged on the substrate with one or more active microstructures situated on it.... Agent: Hunton & Williams LLP Intellectual Property Department

20080283993 - Die stacking system and method: Die stacking systems and methods are disclosed. In an embodiment, a die has a surface that includes a passivation area, at least one conductive bond pad area, and a conductive stacked die receiving area sized to receive at least a second die.... Agent: Qualcomm Incorporated

20080283992 - Multi layer low cost cavity substrate fabrication for pop packages: In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a base laminate substrate (BLS) (110) is formed to include a base center portion (112) and a peripheral portion (114) separated by a barrier element (120). The barrier element (120) forms a peripheral wall (118)... Agent: Texas Instruments Incorporated

20080283994 - Stacked package structure and fabrication method thereof: A stacked package structure and fabrication method thereof are disclosed, including providing a substrate having a plurality of stackable solder pads formed on surface thereof for allowing at least one semiconductor chip to be electrically connected to the substrate; forming an encapsulant for encapsulating the semiconductor chip and further exposing... Agent: Edwards Angell Palmer & Dodge LLP

20080283995 - Compact multi-port cam cell implemented in 3d vertical integration: A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect... Agent: Scully, Scott, Murphy & Presser, P.C.

20080283997 - Electronic device and pressure sensor: An electronic device requires an electronic component to be mounted for the purpose of static shielding. The mounting of such an electronic component raises a problem of avoiding thermal stresses and cracks generated due to the difference between the coefficients of linear expansion of component materials. A positioning recess, a... Agent: Crowell & Moring LLP Intellectual Property Group

20080283996 - Semiconductor package using chip-embedded interposer substrate: A semiconductor package using a chip-embedded interposer substrate is provided. The chip-embedded interposer substrate includes a chip including a plurality of chip pads; a substrate having the chip mounted thereon and including a plurality of redistribution pads for redistributing the chip pads; bonding wires for connecting the chip pads to... Agent: Marger Johnson & Mccollom, P.C.

20080283998 - Electronic system with expansion feature: An electronic system is provided including forming a substrate having a radiating patterned pad, mounting an electrical device having an external interconnect over the radiating patterned pad with the external interconnect offset from the radiating patterned pad, and aligning the external interconnect with the radiating patterned pad.... Agent: Law Offices Of Mikio Ishimaru

20080283999 - Chip package with pin stabilization layer: Various methods and apparatus for semiconductor packing are disclosed. In one aspect, a method of manufacturing is provided that includes coupling first ends of plural conductor pins to a first surface of a semiconductor chip package substrate. A layer is formed on the first surface that engages and resists lateral... Agent: Timothy M Honeycutt Attorney At Law

20080284000 - Integrated circuit packages, methods of forming integrated circuit packages, and methods of assembling integrated circuit packages: Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at... Agent: Wells St. John P.s.

20080284001 - Semiconductor device and fabrication method: A semiconductor device, in which a semiconductor element is mounted on one side of a circuit board that is made up from an insulating layer and a wiring layer, includes metal posts provided on the side of said circuit board on which said semiconductor element is mounted; and a sealing... Agent: Young & Thompson

20080284002 - Integrated circuit package system with thin profile: An integrated circuit package system is provided including attaching an external interconnect on a tape; attaching a backside element on the tape adjacent to the external interconnect; attaching an integrated circuit die with the backside element, the backside element is on a first passive side of the integrated circuit die;... Agent: Law Offices Of Mikio Ishimaru

20080284004 - Semiconductor device, substrate, equipment board, method for producing semiconductor device, and semiconductor chip for communication: A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a plurality of first communication units for transmitting... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080284003 - Semiconductor packages and method for fabricating semiconductor packages with discrete components: A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The package also includes a semiconductor die on the substrate in electrical communication with the contacts, and a die attach polymer attaching the die to the substrate. The die... Agent: Stephen A. Gratton

20080284005 - Fastener for heat sinks: This invention is related to an improvement in the structure of a fastener which includes a rod and a sleeve, wherein the rod has a flat top for depression and a rod body extending downwardly from the flat top to form three stepped portions. The upper end of the rod... Agent: Lowe, Hauptman, Gilman & Berner, LLP (itw)

20080284006 - Semiconductor devices including interlayer conductive contacts and methods of forming the same: In a semiconductor device and a method of forming the same, the semiconductor device comprises: a first insulating layer on an underlying contact region of the semiconductor device, the first insulating layer having an upper surface; a first conductive pattern in a first opening through the first insulating layer, an... Agent: Mills & Onello LLP

20080284007 - Semiconductor module and method for manufacturing semiconductor module: A semiconductor module includes a first metal foil; an insulating sheet mounted on a top surface of the first metal foil; at least one second metal foil mounted on a top surface of the insulating sheet; at least one semiconductor device mounted on the second metal foil; and a resin... Agent: Kanesaka Berner And Partners LLP

20080284008 - Semiconductor device: Provided is a semiconductor device which is small in size and in which the deformation of leads is prevented at the time of wire-bonding. The semiconductor device includes: an island; a semiconductor element mounted on the bottom surface of the island; leads provided close to the island; and a sealing... Agent: Fish & Richardson P.C.

20080284010 - Apparatus for connecting integrated circuit chip to power and ground circuits: In a method and system for transferring at least one of power and ground signal between a die and a package base of a semiconductor device, a connector is formed there between. The connector, which is disposed above the die attached to the package base, includes a center pad electrically... Agent: Texas Instruments Incorporated

20080284015 - Bump on via-packaging and methodologies: A semiconductor package with a semiconductor chip having under bump metallizations (UBMs) on a first surface and a substrate having open vias. The substrate is attached to the semiconductor chip with the UBMs in alignment with the open vias. An encapsulant surrounds the semiconductor chip and the substrate and a... Agent: Sughrue Mion, PLLC

20080284011 - Bump structure: A bump structure including at least one contact pad, at least one first polymer bump, at least one second polymer bump, and a conductive layer is provided. The contact pad is disposed on a substrate, and the first polymer bump is also disposed on the substrate. The second polymer bump... Agent: Jianq Chyun Intellectual Property Office

20080284014 - Chip assembly: A chip assembly includes a semiconductor chip, a bump and an external circuit. The semiconductor chip includes a semiconductor substrate, a transistor in and on the semiconductor substrate, multiple dielectric layers over the semiconductor substrate, a metallization structure over the semiconductor substrate, wherein the metallization structure is connected to the... Agent: Megica Corporation

20080284009 - Dimple free gold bump for drive ic: A conductive bump structure for an integrated circuit (IC) structure comprises a passivation layer, such as a silicon oxide/silicon nitride stack, that is formed on an upper surface of each of the conductive contact pads (e.g. Al pads) of the IC. A plurality of openings extend through the passivation layer... Agent: Stallman & Pollock LLP Attn: Michael J. Pollock

20080284013 - Method for manufacturing semiconductor device, and semiconductor device: A method for manufacturing a semiconductor device includes: when bonding a bump of an IC chip to a bonding position of a wiring pattern that is formed on an insulating film base member and has a surface covered by a plating layer, forming a plating layer around the bonding position... Agent: Oliff & Berridge, PLC

20080284016 - Reliable metal bumps on top of i/o pads after removal of test probe marks: In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during... Agent: Mou-shiung Lin

20080284012 - Semiconductor module manufacturing method, semiconductor module, and mobile device: A semiconductor substrate having on its surface an electrode of a semiconductor device and a pattern unit is prepared. A copper plate is formed provided with a first principle surface having a bump and a second principle surface, opposite to the first principle surface, having a trench. By adjusting the... Agent: Fish & Richardson P.C.

20080284018 - Integrated chip carrier with compliant interconnects: An electronic device includes: at least one electronic chip comprising a first coefficient of thermal expansion (CTE); and a carrier including a top surface connected to the bottom surface of the chip by solder bumps. The carrier further includes a second CTE that approximately matches the first CTE, and a... Agent: Michael Buchenhorner, P.A.

20080284017 - Methods of fabricating circuit board and semiconductor package, and circuit board and semiconductor package fabricated using the methods: Provided are methods of fabricating a circuit board and a semiconductor package, and a circuit board and a semiconductor package fabricated using the methods. The circuit board comprises: a lower wiring pattern disposed on an upper surface of a resin substrate comprising a filler; a resin layer disposed on the... Agent: Marger Johnson & Mccollom, P.C.

20080284019 - Conductor-dielectric structure and method for fabricating: A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the... Agent: Connolly Bove Lodge & Hutz LLP

20080284021 - Method for feol and beol wiring: A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall... Agent: Scully, Scott, Murphy & Presser, P.C.

20080284020 - Semiconductor contact structure containing an oxidation-resistant diffusion barrier and method of forming: The method includes providing a patterned structure in a process chamber, where the patterned structure contains a micro-feature formed in a dielectric material and a contact layer at the bottom of the micro-feature, and depositing a metal carbonitride or metal carbide film on the patterned structure, including in the micro-feature... Agent: Tokyo Electron U.s. Holdings, Inc.

20080284023 - Semiconductor device and method for manufacturing boac/coa: A BOAC/COA of a semiconductor device is manufactured by forming a conductive pad over a semiconductor device, forming a passivation oxide film over the semiconductor device including the conductive pad, forming an oxide film over the entire surface of the conductive pad and the passivation oxide film, forming an oxide... Agent: Sherr & Vaughn, PLLC

20080284022 - Semiconductor device and method for manufacturing the same: A semiconductor device (10) comprises a substrate (11), a semiconductor layer (12), an insulation film (13), a protective film (15), a source electrode (21), a drain electrode (22), a gate electrode (23). The semiconductor device (10) comprises a protective film (15) formed so as to cover at least an upper... Agent: Howard & Howard Attorneys, P.C.

20080284024 - Semiconductor device and method of manufacturing the same: A metal interconnection of semiconductor device and method for fabricating the same is provided. The semiconductor device can include a semiconductor substrate formed with device structures such as transistors. An interlayer dielectric layer can be formed on the semiconductor substrate with a metal interconnection formed therethrough. A spacer can be... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080284025 - Electrically conductive line: The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration in the fabrication of titanium silicide over polysilicon transistor gate lines. In one implementation, a method of forming an electrically conductive line includes providing a silicon-comprising layer over a substrate.... Agent: Qi Pan

20080284029 - Contact structures and semiconductor devices including the same and methods of forming the same: Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact... Agent: Myers Bigel Sibley & Sajovec

20080284030 - Enhanced mechanical strength via contacts: The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of... Agent: International Business Machines Corporation Dept. 18g

20080284028 - Integrated device fabricated using one or more embedded masks: A device fabricated using a multi-layered wafer that has an embedded etch mask adapted to map a desired device structure onto an adjacent (poly)silicon layer. Due to the presence of the embedded mask, it becomes possible to delay the etching that forms the mapped structure in the (poly)silicon layer until... Agent: Mendelsohn & Associates, P.C.

20080284031 - Method for improved process latitude by elongated via integration: Interconnect dual damascene structure are fabricated by depositing on a layer of at least one dielectric, a mask forming layer for providing the via-level mask layer of the dual damascene structures; creating an elongated via pattern in the via-level mask layer; depositing a layer of line-level dielectric and creating a... Agent: Connolly Bove Lodge & Hutz LLP

20080284027 - Method of manufacturing a semiconductor device and semiconductor device: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080284026 - Semiconductor device and method for fabricating the same: A semiconductor device comprises a first insulating film formed on a semiconductor substrate, a first metal pattern formed on the first insulating film, a second insulating film formed on the first metal pattern, a second metal pattern formed on the second insulating film, and a third metal pattern formed in... Agent: Mcdermott Will & Emery LLP

20080284032 - High performance system-on-chip using post passivation process: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting... Agent: Mou-shiung Lin

20080284033 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device includes a first metal foil, an insulating sheet mounted on an upper surface of the first metal foil main, at least one second metal foil mounted on the insulating sheet, at least one solder layer mounted on the at least one second metal foil, and at least... Agent: Kanesaka Berner And Partners LLP

20080284034 - Method of reducing the surface roughness of spin coated polymer films: According to one aspect of the invention, a method of constructing a memory array is provided. An insulating layer is formed on a semiconductor wafer. A first metal stack is then formed on the insulating layer and etched to form first metal lines. A polymeric layer is formed over the... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20080284035 - Semiconductor device: A semiconductor device and method is disclosed. In one embodiment, the method includes placing a first semiconductor over an electrically conductive carrier. The first semiconductor is covered with a molding compound. A through hole is formed in the molding compound. A first material is deposited in the through hole.... Agent: Dicke, Billig & Czaja

20080284036 - Structure for optimizing fill in semiconductor features deposited by electroplating: A structure and process are provided that are capable of reducing the occurrence of discontinuities within the metallization, such as voiding or seams, formed during electroplating at the edges of semiconductor metallization arrays. The structure includes a metallization bar located around the periphery of the array. The process employs the... Agent: Connolly Bove Lodge & Hutz LLP

20080284037 - Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers: Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.... Agent: F. Chau & Associates, LLC

20080284038 - Integrated circuit package system with perimeter paddle: An integrated circuit package system is provided including forming a perimeter paddle having a first external interconnect extending therefrom, mounting an integrated circuit die over the perimeter paddle, connecting a second external interconnect and the integrated circuit die, and encapsulating the integrated circuit die and the perimeter paddle with the... Agent: Law Offices Of Mikio Ishimaru

20080284039 - Interconnect structures with ternary patterned features generated from two lithographic processes: A method for fabricating an interconnect structure for interconnecting a semiconductor substrate to have three distinct patterned structures such that the interconnect structure provides both a low k and high structural integrity. The method includes depositing an interlayer dielectric onto the semiconductor substrate, forming a first pattern within the interlayer... Agent: Scully, Scott, Murphy & Presser, P.C.

20080284040 - Semiconductor device and method of manufacturing same: A semiconductor device in a packaged form including a semiconductor includes a semiconductor substrate with an active component disposed thereon and pads disposed on a surface thereof and connected to the active component, a first interconnection disposed on the semiconductor substrate and connected to the pads, a first insulating layer... Agent: Robert J. Depke Lewis T. Steadman

20080284041 - Semiconductor package with through silicon via and related method of fabrication: In a semiconductor package, an electrode has a first part extending through a semiconductor substrate and a second part extending from the first part through a compositional layer to reach a conductive pad.... Agent: Volentine & Whitt PLLC

20080284042 - Anisotropically conductive member and method of manufacture: An anisotropically conductive member has an insulating base material, and conductive paths composed of a conductive material which pass in a mutually insulated state through the insulating base material in a thickness direction thereof and which are provided in such a way that a first end of each conductive path... Agent: Sughrue Mion, PLLC

20080284043 - Base semiconductor component for a semiconductor component stack and method for the production thereof: A base semiconductor component for a semiconductor component stack is disclosed. In one embodiment, the base semiconductor component has a semiconductor chip arranged centrally on a stiff wiring substrate. The wiring substrate has, in its edge regions, contact pads which are electrically connected to external contacts and at the same... Agent: Dicke, Billig & Czaja

20080284044 - Capillary underfill of stacked wafers: A plurality of wafers are aligned and stacked on a thermally variable rotary table, the table and stack are rotated, and an underfill material is disposed and cured between wafers in the stack, bonding the wafers. Corresponding wafer portions of the plurality of wafers in the stack may be singulated... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20080284046 - Flip chip mounting method and bump forming method: A flip chip mounting method which is applicable to the flip chip mounting of a next-generation LSI and high in productivity and reliability as well as a bump forming method are provided. After a resin 14 containing a solder powder 16 and a gas bubble generating agent is supplied to... Agent: Mcdermott Will & Emery LLP

20080284045 - Method for fabricating array-molded package-on-package: A method and apparatus for fabricating a semiconductor device are disclosed. The method attaches semiconductor chips (130) on a sheet-like insulating substrate (101) integral with two or more patterned layers of conductive lines and vias and with contact pads (103) in pad locations. A mold is provided, which has a... Agent: Texas Instruments Incorporated

20080284047 - Chip package with stiffener ring: Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices in the first side. A polymeric stiffener ring is formed on the... Agent: Timothy M Honeycutt Attorney At Law

20080284048 - Alignment mark, semiconductor chip including the same, semiconductor package including the chip and methods of fabricating the same: Provided are an alignment mark with a higher rate of recognition, a semiconductor chip including the alignment mark, a semiconductor package including the semiconductor chip, and methods of fabricating the alignment mark, the semiconductor chip, and the semiconductor package. The alignment mark may include an align metal pad on a... Agent: Harness, Dickey & Pierce, P.L.C

20080277642 - Fabrication of phase-change resistor using a backend process: A phase change resistor device has a phase change material (PCM) for which the phase transition occurs inside the PCM and not at the interface with a contact electrode. For ease of manufacturing the PCM is an elongate line structure (210, 215) surrounded by the conductive electrode portions (200, 240)... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080277641 - Inverted variable resistance memory cell and method of making the same: An inverted variable resistance memory cell and a method of fabricating the same. The memory cell is fabricated by forming an opening in an insulating layer deposited over a semiconductor substrate, etching the top portion of the opening to have a substantially hemispherical-shape, forming a metal layer in the opening,... Agent: Dickstein Shapiro LLP

20080277643 - Phase change memory device using pnp-bjt for preventing change in phase change layer composition and widening bit line sensing margin: A phase change memory device includes a semiconductor substrate having bar-shaped active regions which extend in a first direction; base regions and emitter regions alternately formed in each active region; lower electrodes formed over the emitter regions to connect to the respective emitter regions; a phase change layer and an... Agent: Ladas & Parry LLP

20080277644 - Switch array circuit and system using programmable via structures with phase change materials: The present invention provides at least one programmable via structure that includes at least two phase change material vias that are both directly contacting a heating element, the programmable via structure further including a first terminal in contact with a first portion of the heating element, a second terminal in... Agent: Scully, Scott, Murphy & Presser, P.C.

20080277645 - Ferromagneic influence on quantum dots: A semiconductor magnetic body comprises a layer (11 15) intended to trap electrons, wherein said layer (11 15) is surrounded on both sides by a magnetic layer (16, 17). This leads to the creation of ferromagnetic character in spatially limited regions of electronic elements such as but not limited to... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080277646 - Vertical type nanotube semiconductor device: A vertical type nanotuhe semiconductor device including a nanotube bit line, disposed on a substrate and in parallel with the substrate and composed of a nanotube with a conductive property, and a nanotube pole connected to the bit line vertically to the substrate and provides a channel through which carriers... Agent: Myers Bigel Sibley & Sajovec

20080277647 - Materials and optical devices based on group iv quantum wells grown on si-ge-sn buffered silicon: A semiconductor structure including a single quantum well Ge1−x1−ySix1Sn/Ge1−x2Six2 heterostructure grown strain-free on Si(100) via a Sn1−xGex buffer layer is shown.... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080277652 - Carbon-containing semiconducting devices and methods of making thereof: Embodiments of the present invention relate to semiconducting carbon-containing devices and methods of making thereof. The semi-conducting carbon containing devices comprise an n-type semiconducting layer and a p-type semiconducting layer, both of which are positioned over a substrate. The n-type semiconducting layer can be formed by pyrolyzing a carbon- and... Agent: Knobbe Martens Olson & Bear LLP

20080277648 - Conductive thin film and thin film transistor: b

20080277649 - Field effect transistor and method of producing same: wherein R1 and R2 are independently selected from the group consisting of a hydrogen atom, a halogen atom, a hydroxyl group, and alkyl, alkenyl, oxyalkyl, thioalkyl, alkyl ester and aryl groups each having 1 to 12 carbon atoms with the proviso that adjacent R1 may be the same or different... Agent: Fitzpatrick Cella Harper & Scinto

20080277654 - Organic light emitting diode with fluorinion-doped anode and method for fabricating same: An exemplary organic light emitting diode (20) includes a substrate (21), a first electrode (22) with a plurality of fluorinions therein, an organic emission stack (29), and a second electrode (28) sequentially stacked in that order. A related method for fabricating the organic emitting diode is also provided.... Agent: Wei Te Chung Foxconn International, Inc.

20080277651 - Organic non-volatile memory material and memory device utilizing the same: Disclosed is an organic non-volatile memory (ONVM) material including nanoparticles evenly dispersed in a first polymer. The nanoparticles have a metal core covered by a second polymer to form a core/shell structure, and the first polymer has a higher polymerization degree and molecular weight than the second polymer. The ONVM... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080277650 - Organic photodetector and fabricating method of organic photodetector and organic thin film transistor: An organic photodetector including a substrate, a first electrode, an insulation layer, an organic layer, and a second electrode is provided. The first electrode is disposed on the substrate. The insulation layer is disposed on the first electrode. The organic layer is disposed on the substrate and the insulation layer... Agent: Jianq Chyun Intellectual Property Office

20080277655 - Organic semiconductor device: An organic semiconductor device with a vertical structure having both functions of an organic thin film transistor and light-emitting element, where the electrical characteristics as both the organic thin film transistor and light-emitting element can be controlled in the case of forming a gate electrode with an organic conductive film,... Agent: Fish & Richardson P.C.

20080277653 - Semiconductor element, and display pixel and display panel using the same: In a semiconductor element, and a display pixel and a display panel using the same, the semiconductor element includes a first electrode, a second electrode, an organic light-emitting layer and a third electrode. The second electrode and the first electrode are disposed separately. The organic light-emitting layer is electrically connected... Agent: Hdsl

20080277656 - Method of manufacturing zno semiconductor layer for electronic device and thin film transistor including the zno semiconductor layer: Provided are a method of manufacturing a ZnO semiconductor layer for an electronic device, which can control the size of crystals of the ZnO semiconductor layer and the number of carriers using a surface chemical reaction between precursors, and a thin film transistor (TFT) including the ZnO semiconductor layer. The... Agent: Ladas & Parry LLP

20080277657 - Thin film transistor and organic light emitting display using the same: Thin film transistors and organic light emitting displays using the same are provided. The thin film transistor may include a substrate, a semiconductor layer, a gate electrode, and source/drain electrodes on the substrate. The semiconductor layer is composed of a P-type semiconductor layer obtained by diffusing phosphorus into a zinc... Agent: Christie, Parker & Hale, LLP

20080277658 - Thin film transistor, method of manufacturing the same, organic light emitting display apparatus comprising the thin film transistor, and method of manufacturing the same: A thin film transistor includes a gate electrode; an active layer formed of an oxide and insulated from the gate electrode; and a source electrode and a drain electrode formed of an oxide on the active layer such that the source electrode and the drain electrode are insulated from the... Agent: Robert E. Bushnell

20080277661 - Semiconductor device and method of manufacturing the same: A technique of manufacturing a semiconductor device capable of performing a probe test by a common test apparatus as normal LSI chips even for large-area chips is provided. A chip comprising a device formed on a device area by a semiconductor process and including a plurality of test areas sectioned... Agent: Miles & Stockbridge PC

20080277660 - Semiconductor device, manufacturing method thereof, and measuring method thereof: To provide a semiconductor device capable of being easily subjected to a physical test without deteriorating characteristics. According to a measuring method of a semiconductor device in which an element layer provided with a test element including a terminal portion is sealed with first and second films having flexibility, the... Agent: Eric Robinson

20080277659 - Test structure for semiconductor chip: A test structure for use in a semiconductor chip. In a preferred embodiment, a number of die are formed in an array on a semiconductor wafer substrate. Each die includes an active area defined by a seal ring and is separated from those adjacent to it by a thin scribe... Agent: Slater & Matsil, L.L.P.

20080277662 - Semiconductor structures: A semiconductor structure is disclosed. The semiconductor structure includes a polycrystal substrate, a first single crystal layer formed thereon and a second single crystal layer formed on the first single crystal layer. A variation of coefficients of thermal expansion (CTE) between the first single crystal layer and the polycrystal substrate... Agent: Quintero Law Office, PC

20080277663 - Thin film transistor and method of manufacturing the same: Provided is a thin film transistor that includes a substrate on which an insulating layer is formed, a gate formed on a region of the insulating layer, a gate insulating layer formed on the insulating layer and the gate, a channel region formed on the gate insulating layer on a... Agent: Harness, Dickey & Pierce, P.L.C

20080277664 - Display apparatus and method thereof: A display apparatus includes pixel electrodes disposed on a first base substrate, a second base substrate which faces the first base substrate, color pixels disposed on the second base substrate, the color pixels correspond to the pixel electrodes in a one-to-one correspondence, each color pixel partially covers the corresponding pixel... Agent: Cantor Colburn, LLP

20080277665 - Semiconductor device, nonvolatile memory device and method for fabricating the same: A semiconductor device includes a conductive layer including a first and a second polysilicon layers having different grain boundaries, wherein a portion or an entire region of the first polysilicon layer is crystallized and wherein a grain boundary in a crystallized region is bigger than the grain boundary of the... Agent: Townsend And Townsend And Crew, LLP

20080277666 - Thin film transistor, organic light emitting display device including the same, and method of manufacturing the organic light emitting display device: A thin film transistor (TFT) may include a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, and a semiconductor layer on the gate insulating layer. The semiconductor layer may include a top surface, a channel area aligned in a vertical direction with the... Agent: Lee & Morse, P.C.

20080277667 - Method of producing iii-nitride substrate: An ingot 3 of a hexagonal III-nitride crystal is cut using a wire array 21 composed of a wire 22. On this occasion, the ingot 3 is cut in such a manner that the ingot 3 is sliced with supply of an abrasive fluid while feeding at least one of... Agent: Mcdermott Will & Emery LLP

20080277670 - Sic crystal and semiconductor device: The present invention discloses a SiC crystal, comprising: acceptor impurities that are in a concentration greater than 5×1017 cm−3; donor impurities that are in a concentration less than 1×1019 cm−3 and greater than the concentration of the acceptor impurities. The present invention discloses a semiconductor device, comprising: a SiC fluorescent... Agent: Yokoi & Co., U.s.a., Inc.

20080277669 - Sic semiconductor having junction barrier schottky device: A semiconductor device having a JBS diode includes: a SiC substrate; a drift layer on the substrate; an insulation film on the drift layer having an opening in a cell region; a Schottky barrier diode having a Schottky electrode contacting the drift layer through the opening and an ohmic electrode... Agent: Posz Law Group, PLC

20080277668 - Sis semiconductor having junction barrier schottky device: A semiconductor device having a junction barrier Schottky diode includes: a SiC substrate; a drift layer on the substrate; an insulation film on the drift layer having an opening in a cell region; a Schottky barrier diode having a Schottky electrode contacting the drift layer through the opening of the... Agent: Posz Law Group, PLC

20080277671 - Semiconductor device, method of manufacturing the same, electro-optic device and electronic apparatus: The invention provides a semiconductor device, a method of manufacturing the same, an electro-optic device and an electronic apparatus which are capable of addressing or solving a problem of mechanical mounting of a semiconductor element chip on a substrate. A semiconductor device includes a tile-shaped microelement bonded to a substrate,... Agent: Oliff & Berridge, PLC

20080277673 - Cavity exploration with an image sensor: A head of a cavity exploration device, with an integrated circuit support which has first and second surfaces and a plurality of through-holes associated with corresponding first and second conducting pads positioned on the respective first and second surfaces of the integrated circuit support, a respective conducting micro-cable is placed... Agent: Seed Intellectual Property Law Group PLLC

20080277672 - Lid structure for microdevice and method of manufacture: A system and a method are described for forming features at the bottom of a cavity in a substrate. Embodiments of the systems and methods provide an infrared transmitting, hermetic lid for a microdevice. The lid may be manufactured by first forming small, subwavelength features on a surface of an... Agent: Jaquelin K. Spong

20080277675 - Light-emitting diode assembly without solder: An electrical device in the form of a light emitting diode (LED) assembly. A plurality of LEDs are provided, wherein each has an anode and a cathode. A base holds this plurality of LEDs in a substantially fixed relationship. One or more anode conductors then each connect electrically to one... Agent: The Tpl Group

20080277674 - Semiconductor light emitting device, lighting module, lighting apparatus, and manufacturing method of semiconductor light emitting device: An LED bare chip which is one type of a semiconductor light emitting device (2) includes a multilayer epitaxial structure (6) composed of a p-GaN layer (12), an InGaN/GaN MQW light emitting layer (14) and an n-GaN layer (16). A p-electrode (18) is formed on the p-GaN layer (12), and... Agent: Snell & Wilmer L.L.P. (matsushita)

20080277676 - Light emitting diode using semiconductor nanowire and method of fabricating the same: Provided are a light emitting diode (LED) using a Si nanowire as an emission device and a method of fabricating the same. The LED includes: a semiconductor substrate; first and second semiconductor protrusions disposed on the semiconductor substrate to face each other; a semiconductor nanowire suspended between the first and... Agent: Harness, Dickey & Pierce, P.L.C

20080277677 - Light emitting diode assembly and light emitting diode display device: An exemplary light emitting diode (LED) assembly includes a cover, a substrate, a LED unit, a first electrode terminal, and a second electrode terminal. The substrate includes a first surface and a second surface on an opposite side of the substrate thereto. The substrate and the cover cooperatively define a... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang

20080277678 - Light emitting device and method for making the same: A method for making a light emitting device includes: forming a multi-layer structure on a substrate; forming a patterned mask material on one side of the multi-layer structure such that the patterned mask material covers an etch region of the multi-layer structure; forming a roughened layer on the multi-layer structure;... Agent: Townsend And Townsend And Crew, LLP

20080277679 - Light-emitting device: A light-emitting device, including a compound semiconductor layer disposed on a substrate, includes a light-emitting layer, and a dielectric constant change structure formed in a part of the compound semiconductor layer including a main surface as a light extraction surface of the compound semiconductor layer. The dielectric constant change structure... Agent: Mcginn Intellectual Property Law Group, PLLC

20080277682 - Dual surface-roughened n-face high-brightness led: A light emitting diode, comprising a substrate, a buffer layer on the substrate, an active layer on the buffer layer and between an n-type layer and a p-type layer, a tunnel junction adjacent the p-type layer, and n-type contacts to the tunnel junction and the n-type layer, wherein the buffer... Agent: Gates & Cooper LLP Howard Hughes Center

20080277680 - Led with improved light emittance profile: The present invention relates to a LED comprising a substrate layer with a first surface and a second surface opposing the first surface and having a refractive index of n1, a light emitting means provided on said first surface and an array of particles arranged on said second surface, characterized... Agent: Philips Intellectual Property & Standards

20080277681 - Light emitting diode: A light emitting diode includes a substrate, a reflecting layer, an active layer, a transparent electrode, a first photonic crystal structure, and a second photonic crystal structure. The reflecting layer is disposed on the substrate. The active layer is disposed on the reflecting layer. The transparent electrode is disposed on... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang

20080277683 - Soldering method for semiconductor optical device, and semiconductor optical device: A method for soldering a semiconductor optical device including a resin-made optical lens to an object by a reflow soldering process using a lead-free solder, and a semiconductor optical device for use in the method. A semiconductor optical device including a silicone resin-made optical lens as the resin-made optical lens... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080277685 - Light emitting diode package: Provided is a light emitting diode package in accordance with the present invention including a lead frame composed of at least a pair of lead terminals; a mold receiving a part of the lead frame therein and equipped with an irradiation window opened to radiate light, and further including one... Agent: Mcdermott Will & Emery LLP

20080277684 - Surface light emitting diode module with a surface light emitting diode connected to a conductive substrate tightly: A surface light emitting diode module includes a conductive substrate including a first electrode section. A first hole is formed on the first electrode section. The surface light emitting diode module further includes a surface light emitting diode installed on the conductive substrate. The surface light emitting diode includes a... Agent: North America Intellectual Property Corporation

20080277686 - Light emitting device and method for making the same: A light emitting diode includes: an epitaxial substrate having a roughened side and formed with alternately disposed ridges and valleys at the roughened side, each of the ridges having a roughened surface that is formed with a dense concentration of alternately disposed pits and protrusions; and an epitaxial layered structure... Agent: Townsend And Townsend And Crew, LLP

20080277687 - High power density switch module with improved thermal management and packaging: A semiconductor power device, e.g., an Insulated Gate Bi-polar Transistor (IGBT) or a Metal-Oxide Field Effect Transistor (MOSFET) may be constructed in a reusable and repairable cost-effective sealed shell. The switch may be provided with direct-pressure-contact caps which may perform as electrical conductors for a semiconductor die of the switch... Agent: Honeywell International Inc.

20080277688 - Semiconductor device and fabrication method thereof: A p-type collector layer is formed on a reverse side of an n-type high-resistivity first base layer, a p-type second base layer is formed on an obverse side of the first base layer, an emitter layer is formed on the second base layer, gate electrodes are formed inside trenches extending... Agent: Rabin & Berdo, PC

20080277689 - Electro-static discharge protection device: An electro-static discharge protection device includes a first conductive type well and a second conductive type well which are formed in a surface of the first conductive type layer or a first conductive type substrate. A first high concentration second conductive type region, a first high concentration first conductive type... Agent: Katten Muchin Rosenman LLP

20080277690 - Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer: A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting... Agent: Scully, Scott, Murphy & Presser, P.C.

20080277691 - Production of a transistor gate on a multibranch channel structure and means for isolating this gate from the source and drain regions: A method for fabricating a microelectronic device including a support, an etched stack of thin layers including at least one first block and at least one second block resting on the support, in which at least one drain region and at least one source region, respectively, are capable of being... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080277692 - Semiconductor device: A semiconductor device includes: a first semiconductor layer made of an AlxGa1−xN (0≦x<1); a second semiconductor layer provided on the first semiconductor layer and made of an undoped or first conductivity type AlyGa1−yN (0<y≦1, x<y); an anode electrode and a cathode electrode which are connected to the second semiconductor layer;... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080277693 - Imager element, device and system with recessed transfer gate: An imager element, device and imaging system image sensor pixel. The image sensor pixel includes a collection region, a floating diffusion region, and a transfer transistor having a recessed gate. The recessed gate is configured to couple the collection region to the floating diffusion region so that collected charge is... Agent: Trask Britt, P.C./ Micron Technology

20080277694 - Semiconductor component and method of manufacture: A semiconductor component that includes a Schottky device, an edge termination structure, a non-Schottky semiconductor device, combinations thereof and a method of manufacturing the semiconductor component. A semiconductor material includes a first epitaxial layer disposed on a semiconductor substrate and a second epitaxial layer disposed on the first epitaxial layer.... Agent: Mr. Jerry Chruma Semiconductor Components Industries, L.L.C.

20080277695 - Mosfet having a jfet embedded as a body diode: A field effect transistor, in accordance with one embodiment, includes a metal-oxide-semiconductor field effect transistor (MOSFET) having a junction field effect transistor (JFET) embedded as a body diode.... Agent: Morgan, Lewis & Bockius, LLP.

20080277696 - Lateral junction field effect transistor and method of manufacturing the same: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer... Agent: Fish & Richardson P.C.

20080277698 - Field effect transistor: a source electrode and a drain electrode alternately arranged on the channel region with a gate electrode interposed between the source electrode and the drain electrode, a bonding pad to be connected with an external circuit; and an air-bridge connected with the bonding pad, the air-bridge having an electrode contact... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080277697 - Semiconductor device for high frequency: A semiconductor device for high frequency includes a channel region fabricated on a compound semiconductor substrate, a gate electrode fabricated on the channel region, a source electrode and a drain electrode alternately fabricated on the channel region by sandwiching the gate electrode, a bonding pad to be connected to an... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080277699 - Recess etch for epitaxial sige: A PMOS transistor and a method for fabricating a PMOS transistor. The method may include providing a semiconductor wafer having a PMOS transistor gate stack, source/drain extension regions, and active regions. The method may also include forming epi sidewalls, performing a ex-situ recess etch, and performing an in-situ recess etch.... Agent: Texas Instruments Incorporated

20080277701 - High energy implant photodiode stack: An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, with a corresponding fabrication process. The color imager cell array is formed from a bulk silicon (Si) substrate without an overlying epitaxial Si layer. A plurality of color imager cells are formed in the bulk... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080277700 - Imaging device by buried photodiode structure: To achieve an image sensor with low noise, small dark current and the high sensitivity, an n-type region serving as a charge storage region (2) of a photodiode is buried in a substrate (1). The interface between silicon and a silicon oxide film (4) is covered with a p-layer (3)... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080277702 - Solid-state imaging device and camera having the same: Provided is a solid-state imaging device including unit pixels, wherein the unit pixels include two kinds of unit pixels including a first unit pixel and a second unit pixel that are formed on a common well on a semiconductor substrate. The first unit pixel includes: at least one photoelectric conversion... Agent: Greenblum & Bernstein, P.L.C

20080277706 - Ferroelectric memory device, ferroelectric memory manufacturing method, and semiconductor manufacturing method: A ferroelectric memory device manufacturing method includes the steps of forming an interlayer isolating film for covering a transistor formed on a semiconductor substrate; forming a conductive plug in the interlayer insulating film to contact a diffusion region of the transistor formed on the semiconductor substrate; forming a ferroelectric capacitor... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080277703 - Magnetoresistive random access memory and method of manufacturing the same: A magnetic random access memory includes a single tunnel junction element which includes a first fixed layer, a first recording layer, and a first nonmagnetic layer, a double tunnel junction element which includes a second fixed layer and a third fixed layer, a second recording layer, a second nonmagnetic layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080277704 - Semiconductor device and manufacturing method thereof: This disclosure concerns a semiconductor device comprising a switching transistor provided on a semiconductor substrate; an interlayer dielectric film formed on the switching transistor; a ferroelectric capacitor including an upper electrode, a ferroelectric film, and a lower electrode formed on the interlayer dielectric film; a contact plug provided within the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080277705 - Semiconductor device, semiconductor wafer structure and method for manufacturing the semiconductor wafer structure: There is provided a semiconductor device including, a semiconductor substrate having a circuit forming region and a peripheral region, a base insulating film formed over the semiconductor substrate, a capacitor formed of a lower electrode, a capacitor dielectric film made of a ferroelectric material, and an upper electrode in this... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080277707 - Semiconductor device and driving method thereof: It is an object of the invention to provide a digital circuit which can operate normally regardless of binary potentials of an input signal. A semiconductor device having a correcting unit and a logic unit wherein the correcting unit includes a capacitor, first and second switches, wherein the first electrode... Agent: Fish & Richardson P.C.

20080277708 - Semiconductor devices and methods of forming the same: A highly integrated semiconductor device has a device isolation layer demarcating a first active region in a first region of a substrate, and a second active region in a second region of the substrate. A first gate pattern and a second gate pattern are formed on the first active region... Agent: Volentine & Whitt PLLC

20080277709 - Dram structure: A DRAM structure includes a substrate, a MOS transistor, a deep trench capacitor, a surface strap positioned on the surface of the substrate and interconnecting a drain of the MOS transistor and an electrode of the deep trench capacitor, wherein the sidewall and the top surface of the surface strap... Agent: North America Intellectual Property Corporation

20080277710 - Semiconductor devices and methods of forming the same: Provided are semiconductor devices and methods of forming the same. In the semiconductor devices and methods of forming the same, different insulating patterns are disposed around a cell gate pattern and a peripheral gate pattern to impose different heat budgets around the cell gate pattern and the peripheral gate pattern.... Agent: Myers Bigel Sibley & Sajovec

20080277712 - Flash memory cell with a flair gate: An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that... Agent: Spansion LLC

20080277711 - Memory cell: A memory cell including a substrate with a protruding portion, the protruding portion having a side wall and a bottom, an upper doped region connected to a bit line, a lower region being closer to a bottom of the protruding portion than the upper region, a substrate contact, a control... Agent: Dickstein Shapiro LLP

20080277713 - Semiconductor memory device and method of fabricating the same: A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080277715 - Dielectric film and formation method thereof, semiconductor device, non-volatile semiconductor memory device, and fabrication method for a semiconductor device: In a film formation method of a semiconductor device including a plurality of silicon-based transistors or capacitors, there exist hydrogen at least in a part of the silicon surface in advance, and the film formation method removes the hydrogen by exposing the silicon surface to a first inert gas plasma.... Agent: Crowell & Moring LLP Intellectual Property Group

20080277714 - Nonvolatile memory device and method for fabricating the same: A nonvolatile memory device includes a control gate formed along a first direction over a substrate, an active region formed over the substrate, the active region being defined along a second direction crossing the control gate and including a fin type protruding portion having rounded top corners at a region... Agent: Townsend And Townsend And Crew, LLP

20080277716 - Semiconductor device: A semiconductor device includes a semiconductor substrate having a device formation region, a tunnel insulating film formed on the device formation region, a floating gate electrode formed on the tunnel insulating film, isolation insulating films which cover side surfaces of the device formation region, side surfaces of the tunnel insulating... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080277718 - 1t mems scalable memory cell: This invention relates to the use of a gate dielectric placed under the mobile gate electrode of MOS transistor, without the need of a conductive floating gate. The invention exploits the electromechanical hysteretic behavior of the mobile gate when down contacting (pull-in) and up separating (pull-out) from the gate dielectric,... Agent: Nixon & Vanderhye, PC

20080277717 - Minority carrier sink for a memory cell array comprising nonvolatile semiconductor memory cells: A memory cell array of nonvolatile semiconductor memory cells is specified in which a minority carrier sink is formed within a semiconductor body in the region of the memory cell array, the minority carrier sink being arranged outside a space charge zone structure that forms in the semiconductor body during... Agent: Dicke, Billig & Czaja

20080277719 - Non-volatile memory cell and method of manufacturing the same: The present invention relates to a non-volatile memory cell and a method of fabricating the same. The non-volatile memory cell according to the present invention comprises a substrate, a first oxide film formed over an active region of the substrate, a source and drain formed within the active region, a... Agent: Buchanan, Ingersoll & Rooney PC

20080277720 - Non-volatile memory device, method of fabricating the same, and semiconductor package including the same: A non-volatile memory device which can be highly-integrated without a decrease in reliability, and a method of fabricating the same, are provided. In the non-volatile memory device, a first doped layer of a first conductivity type is disposed on a substrate. A semiconductor pillar of a second conductivity type opposite... Agent: Marger Johnson & Mccollom, P.C.

20080277721 - Thin film transistor, pixel structure and fabricating method thereof: A fabricating method of a TFT includes first forming a source on a substrate. Then, a first insulation pattern layer is formed to cover parts of the source and the substrate. The first insulation pattern layer has an opening exposing a part of the source. Thereafter, a gate pattern layer... Agent: Jianq Chyun Intellectual Property Office

20080277722 - Semiconductor device and method of manufacturing the semiconductor device: A method of manufacturing a semiconductor. A first epitaxial layer is formed on a gate nitride layer, and a protection nitride layer is formed on the first epitaxial and gate nitride layers. A first gate insulation layer is formed on a drain silicide, a gate oxide layer is formed on... Agent: Lowe Hauptman Ham & Berner, LLP

20080277723 - Semiconductor device: In one embodiment of the present invention, a high withstand voltage transistor is disclosed having small sizes including an element isolating region. The semiconductor device is provided with the element isolating region formed on a semiconductor substrate; an active region demarcated by the element isolating region; a gate electrode formed... Agent: Harness, Dickey & Pierce, P.L.C

20080277724 - Electronic device having a dielectric layer: An electronic device, such as a thin film transistor, is disclosed having a dielectric layer formed from a composition comprising a compound having at least one phenol group and at least one group containing comprising silicon. The resulting dielectric layer has good electrical properties.... Agent: Fay Sharpe / Xerox - Rochester

20080277725 - Semiconductor memory device and manufacturing method thereof: This disclosure concerns a memory comprising a semiconductor layer extending in a first direction; a source; a drain; a body between the source and the drain; a bit-line extending in the first direction; a first gate-dielectric on a first side-surface of the body; a first gate-electrode on the first side-surface... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080277726 - Devices with metal gate, high-k dielectric, and butted electrodes: FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators and metal containing gates. The metal layers of the gates in both the NFET and PFET devices have been fabricated from a single common metal layer. As a consequence of using a single layer... Agent: Innovation Interface, LLC

20080277727 - Apparatus and method for electrostatic discharge protection with p-well integrated components: An electrostatic protection circuit has a transistor for pumping charge into the substrate and a transistor, including a parasitic transistor, for removing charge from the substrate and tabs. The circuit is enclosed by barrier that prevents the migration of charge from the region of the transistors. The added charge in... Agent: Texas Instruments Incorporated

20080277728 - Semiconductor structure for protecting an internal integrated circuit and method for manufacturing the same: A semiconductor structure for protecting an internal integrated circuit comprises a substrate; a plurality of first doping regions formed in the substrate and disposed substantially within an N-well; a plurality of second doping regions, formed in the substrate and disposed within an P-well; a N+ section, formed in the substrate... Agent: Bacon & Thomas, PLLC

20080277729 - Electrostatic discharge protection element: A gate controlled fin resistance element for use as an electrostatic discharge (ESD) protection element in an electrical circuit has a fin structure having a first connection region, a second connection region and a channel region formed between the first and second connection regions. Furthermore, the fin resistance element has... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080277730 - Semiconductor device manufactured using a laminated stress layer: There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and... Agent: Texas Instruments Incorporated

20080277731 - Body bias to facilitate transistor matching: One embodiment of the present invention relates to a method for transistor matching. In this method, a channel is formed within a first transistor by applying a gate-source bias having a first polarity to the first transistor. The magnitude of a potential barrier in a pocket implant region of the... Agent: Texas Instruments Incorporated

20080277732 - P-channel mos transistor and semiconductor integrated circuit device: A p-channel MOS transistor includes a gate electrode formed on a silicon substrate via a gate insulating film, a channel region formed below the gate electrode within the silicon substrate, and a p-type source region and a p-type drain region formed at opposite sides of the channel region within the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080277733 - Semiconductor device and process for manufacturing the same: A semiconductor device includes a semiconductor substrate; a gate electrode formed on the semiconductor substrate; source and drain extension regions formed in the semiconductor substrate on a first and a second side corresponding to a first sidewall surface and a second sidewall surface, respectively, of the gate electrode; a first... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080277734 - Implantation processes for straining transistor channels of semiconductor device structures and semiconductor devices with strained transistor channels: The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract... Agent: Trask Britt, P.C./ Micron Technology

20080277735 - Mos devices having elevated source/drain regions: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate... Agent: Slater & Matsil, L.L.P.

20080277736 - Semiconductor device and method of manufacturing the same: A semiconductor device has an n-channel MISFET having first diffusion layers formed in a first region of a surface portion of a semiconductor substrate so as to sandwich a first channel region therebetween, a first gate insulating film formed on the first channel region, and a first gate electrode including... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080277737 - Method of manufacturing a semiconductor device and semiconductor device obtained with such a method: The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) which is provided with at least one semiconductor element (E), wherein on the surface of the semiconductor body (12) a mesa-shaped semiconductor region (1) is formed, an insulating layer... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080277738 - Memory cells, memory banks, memory arrays, and electronic systems: Some embodiments include memory cells containing vertical floating bodies, and containing gates which entirely laterally surround the floating bodies. Some embodiments include memory banks which contain multiple memory cells extending from a conductively-doped diffusion region. Some embodiments include memory arrays in which electrically insulative partitions extend through a conductively-doped diffusion... Agent: Wells St. John P.s.

20080277739 - Finfet transistors: A fin FET array includes a number of fins 12 and a switch FET 52 between fins 12. The switch FET 52 acts to divide the transistor array into first 42 and second 44 FINFET regions having first 46 and second 48 gate electrodes controllably connected through the switch FET... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080277740 - Semiconductor device and semiconductor device manufacturing method: In the present invention, there is provided a semiconductor device including: element isolation regions formed in a state of being buried in a semiconductor substrate such that an element formation region of the semiconductor substrate is interposed between the element isolation regions; a gate electrode formed on the element formation... Agent: Sonnenschein Nath & Rosenthal LLP

20080277742 - Semiconductor device: In one aspect of the present invention, a semiconductor device may include a plurality of fins disposed substantially parallel to each other at predetermined intervals on a semiconductor substrate, a gate electrode formed to partially sandwich therein the both side surfaces, in the longitudinal direction, of each of the plurality... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080277741 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a semiconductor substrate; a source area, a channel area and a drain area vertically stacked on the semiconductor substrate; and a gate formed in both side walls of the stacked source area, channel area and drain area under interposition of a gate insulation layer.... Agent: Townsend And Townsend And Crew, LLP

20080277743 - Semiconductor device and method for fabricating the same: A semiconductor device includes a substrate having a recess in an area where a gate is to be formed, spacers formed over sidewalls of the recess, and a first gate electrode filling in the recess. The spacers include material having the first work function or insulation material. The first gate... Agent: Townsend And Townsend And Crew, LLP

20080277744 - High voltage device: The invention is directed to a method for manufacturing a high voltage device. The method includes steps of providing a substrate and then forming a first doped region having a first conductive type in the substrate. At least two second doped regions having a second conductive type are formed in... Agent: Jianq Chyun Intellectual Property Office

20080277745 - Fin filled effect transistor and method of forming the same: A fin field effect transistor and method of forming the same. The fin field effect transistor comprises a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further comprises shallow trench isolations formed in the bottom portions of... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080277746 - Nanowire sensor with self-aligned electrode support: A nanowire sensor with a self-aligned top electrode support insulator, and associated fabrication process are provided. The method begins with a doped silicon-containing substrate. A growth-promotion metal is deposited overlying the substrate. A silicon nitride electrode support is formed overlying the growth-promotion metal. Nanowires are grown from exposed regions of... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080277747 - Mems device support structure for sensor packaging: A sensor device and a method of forming comprises a die pad receives a MEMS device. The MEMS device has a first coefficient of thermal expansion (CTE). The die pad is made of a material having a second CTE compliant with the first CTE. The sensor device includes a support... Agent: Nazir Ahmad

20080277748 - Novel class of ferromagnetic semiconductors: Single crystal and polycrystal oxoruthenates having the generalized compositions (Baz,Sr1-z)FexCoyRu6−(x+y)O11 (1≦(x+y)≦5; 0≦z≦1) and (Ba,Sr)M2±xRu4∓xO11 (M=Fe,Co) belong to a novel class of ferromagnetic semiconductors with applications in spin-based field effect transistors, spin-based light emitting diodes, and magnetic random access memories.... Agent: Crowell & Moring LLP Intellectual Property Group

20080277750 - Layout method for mask, semiconductor device and method for manufacturing the same: A mask layout method, semiconductor device and method for fabricating the same using a mask created according to the subject mask layout method are provided. The semiconductor device can include a microlens main pattern on a substrate and a microlens dummy pattern at a side of the microlens main pattern.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080277749 - Light-sensitive component with increased blue sensitivity, method for the production thereof, and operating method: A light-sensitive component which has a semiconductor junction between a thin relatively highly doped epitaxial layer and a relatively lightly doped semiconductor substrate. Outside a light incidence window, an insulating layer is arranged between epitaxial layer and semiconductor substrate. In this case, the thickness of the epitaxial layer is less... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20080277751 - Method of fabricating cmos image sensor: A method of fabricating a CMOS image sensor is provided, in which a trapezoidal microlens pattern profile is formed to facilitate reflowing the microlens pattern and by which a curvature of the microlens may be enhanced to raise its light-condensing efficiency. The method includes forming a plurality of photodiodes on... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080277752 - Solid state imaging device, semiconductor wafer, optical device module, method of solid state imaging device fabrication, and method of optical device module fabrication: With the reduced size of a solid state imaging device, the invention provides: a solid state imaging device of a chip size and having good environmental durability; a semiconductor wafer used for fabricating a solid state imaging device; an optical device module incorporating a solid state imaging device; a method... Agent: Edwards Angell Palmer & Dodge LLP

20080277753 - Thin active layer fishbone photodiode and method of manufacturing the same: The present invention is directed toward a detector structure, detector arrays, and a method of detecting incident radiation. The present invention comprises a photodiode array and method of manufacturing a photodiode array that provides for reduced radiation damage susceptibility, decreased affects of crosstalk, reduced dark current (current leakage) and increased... Agent: Patentmetrix

20080277754 - Image sensor and fabrication method thereof: A method of fabricating an image sensor contains providing a semiconductor substrate with a plurality of pixels defined thereon, forming pixel electrodes on the pixels, and forming a barrier device filled between adjacent pixel electrodes, wherein the barrier device contains a high-k material. Then, a photoconductive layer and a transparent... Agent: North America Intellectual Property Corporation

20080277755 - Filling of insulation trenches using cmos-standard processes for creating dielectrically insulated areas on a soi disk: Insulating trenches isolate regions of a semiconductor layer and include hermetically sealed voids. After forming a trench, a first fill of SiO2 is formed by a CVD process with the oxide layers having increasing thickness toward the upper trench edges forming first bottlenecks. The first fill oxide layers are then... Agent: Stevens & Showalter LLP

20080277757 - Ballasted polycrystalline fuse: A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to form first and second terminal portions of a first width joined along a length of the fuse... Agent: Barnes & Thornburg LLP

20080277756 - Electronic device and method for operating a memory circuit: An electronic device is disclosed having a dielectric layer (12) formed at a semiconductor substrate (10). A polysilicon fuse structure (14) having a first length is formed overlying the dielectric layer (12). First and second portions (141, 142) of the polysilicon fuse structure are silicided, wherein a third portion (143)... Agent: Larson Newman Abel Polansky & White, LLP

20080277759 - Post last wiring level inductor using patterned plate process: A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above a top surface of the substrate; an insulative layer on and above a top surface of the capping layer; an inductor comprising a first portion in and... Agent: Schmeiser, Olsen & Watts

20080277758 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a semiconductor substrate that has an integrated circuit and an electrode, the electrode being electrically coupled to the integrated circuit; a resin layer that is formed on the semiconductor substrate, the resin layer having an upper surface and a lower surface, the upper surface and the... Agent: Harness, Dickey & Pierce, P.L.C

20080277760 - Integrated circuit device having openings in a layered structure: An integrated circuit device includes a substrate with a first layer situated on the substrate. The first layer defines a first opening with a cover layer deposited on the first layer and coating a sidewall portion of the first opening. A second layer is situated on the cover layer. The... Agent: Dicke, Billig & Czaja

20080277761 - On-chip isolation capacitors, circuits therefrom, and methods for forming the same: An integrated circuit includes a substrate having a semiconducting surface, and at least one isolation capacitor on the surface. The capacitor includes a bottom electrically conductive plate in or on the surface, a multi-layer dielectric comprising stack over the bottom plate, and a top electrically conductive plate formed over the... Agent: Texas Instruments Incorporated

20080277762 - Semiconductor device including capacitor including upper electrode covered with high density insulation film and production method thereof: A semiconductor device includes a lower electrode provided on a semiconductor substrate, an upper electrode provided on the lower electrode to overlap a part of the lower electrode, a first insulating film provided between the lower electrode and the upper electrode, and a second insulating film provided in contact with... Agent: Mcginn Intellectual Property Law Group, PLLC

20080277763 - Abrupt metal-insulator transition wafer, and heat treatment apparatus and method for the wafer: Provided are a wafer with the characteristics of abrupt metal-insulator transition (MIT), and a heat treatment apparatus and method that make it possible to mass-produce a large-diameter wafer without directly attaching the wafer to a heater or a substrate holder. The heat treatment apparatus includes a heater applying heat to... Agent: Cantor Colburn, LLP

20080277764 - Method of manufacturing a semiconductor device having a buried doped region: A method of providing a region of doped semiconductor (40) which is buried below the surface of a semiconductor substrate (10) without the requirement of epitaxially deposited layers is provided. The method includes the steps of forming first and second trench portions (26,28) in a semiconductor substrate and then introducing... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080277765 - Inhibiting damage from dicing and chip packaging interaction failures in back end of line structures: A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top... Agent: Graham S. Jones, Ii

20080277766 - Polymer membranes for microcalorimeter devices: An improved structure for supporting a microcalorimeter device is disclosed. The structure comprises a substrate with superconducting wiring elements disposed on a surface of the substrate. A membrane layer is suspended above the wiring elements and the substrate surface by a tab element, and a microcalorimeter is disposed on top... Agent: Duane Morris LLP - PhiladelphiaIPDepartment

20080277767 - Semiconductor device including a planarized surface and method thereof: A method of planarizing the surface of a semiconductor substrate to reduce the occurrence of a dishing phenomenon. A patterned etch stop layer defining a trench region is formed on a substrate. The substrate is etched to form a trench region, and a medium material layer and an oxide layer... Agent: Harness, Dickey & Pierce, P.L.C

20080277768 - Silicon member and method of manufacturing the same: There is provided a silicon member that can prevent the resistivity of a member itself from varying in a semiconductor manufacturing process, in particular, in a plasma processing process, thereby making wafer processing uniform and being not an impurity contamination source to a wafer to be processed, and a method... Agent: Foley And Lardner LLP Suite 500

20080277769 - Package integrated soft magnetic film for improvement in on-chip inductor performance: An integrated circuit package includes an integrated circuit with one or more on-chip inductors. A package cover covers the integrated circuit. A magnetic material is provided between the integrated circuit and the package cover. The magnetic material may be a soft magnetic thin film. The magnetic material may be affixed... Agent: F. Chau & Associates, LLC

20080277770 - Semiconductor device: A semiconductor device includes a lead frame having an element support and a lead portion. The lead frame has an area from the element support to inner leads of the lead portion, which is formed flat. First and second semiconductor elements are stacked in order on a lower surface of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080277771 - Electronic device package manufacturing method and electronic device package: By joining a lid member to a base member, internal electrodes put in contact with the lid member and an electronic device connected to the internal electrodes are placed in an internal space located in between the base member and the lid member. Then, by performing etching from a surface... Agent: Wenderoth, Lind & Ponack L.L.P.

20080277772 - Methods of packaging a semiconductor die and package formed by the methods: A method of packaging a semiconductor die (20). The method comprises mounting a semiconductor die (20) to a die attach pad (34) on a carrier (10) and electrically coupling an electrode (36) of the semiconductor die (20) and a contact pad (16) on the carrier (10) with a clip (54)... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080277773 - Circuit structures and methods with beol layer(s) configured to block electromagnetic interference: Back end of line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic interference. One such BEOL circuit structure includes one or more semiconductor substrates supporting one or more integrated circuits, and one or more BEOL layers disposed over the semiconductor substrate(s). At least one BEOL... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20080277774 - Power semiconductor device, electronic device, lead frame member, and method of making power semiconductor device: The power semiconductor device according to the present invention comprises a power element, a package encapsulating the power element with resin, a power element mounting portion used for mounting the power element, and a plurality of lead pins brought out of the package, including a power element lead pin brought... Agent: Birch Stewart Kolasch & Birch

20080277775 - Ultra-thin near-hermetic package based on rainier: A microelectronic package including a dielectric layer having top and bottom surfaces, the dielectric layer having terminals exposed at the bottom surface; a metallic wall bonded to the dielectric layer and projecting upwardly from the top surface of the dielectric layer and surrounding a region of the top surface; a... Agent: Tessera Lerner David Et Al.

20080277776 - Substrate and multilayer circuit board: A substrate includes a inorganic material base board has a recess and at least one penetration hole provided around the recess, and a semiconductor device accommodated in the recess and including at least one electrode pad provided on a surface of the semiconductor device. A resin filling is provided in... Agent: Ditthavong Mori & Steiner, P.C.

20080277777 - Heat dissipation semiconductor package: A heat dissipation semiconductor package includes a chip carrier, a semiconductor chip, a heat conductive adhesive, a heat dissipation member, and an encapsulant. The semiconductor chip is flip-chip mounted on the chip carrier and defined with a heat conductive adhesive mounting area. Periphery of the heat adhesive mounting area is... Agent: Edwards Angell Palmer & Dodge LLP

20080277778 - Layer transfer process and functionally enhanced integrated circuits products thereby: A structure for a semiconductor components is provided having a device layer sandwiched on both sides by other active, passive, and interconnecting components. A wafer-level layer transfer process is used to create this planar (2D) IC structure with added functional enhancements.... Agent: Ibm Corporation, T.j. Watson Research Center

20080277779 - Microelectronic package and method of manufacturing same: A microelectronic package comprises a substrate (110), a die (120) having a front side (121) and a back side (122) located over the substrate, a thermally conducting layer (130) on the back side of the die, a microchannel (140) above the thermally conducting layer, and a cap (150) on the... Agent: Intel Corporation C/o Intellevate, LLC

20080277780 - Electrical circuit device: An electrical circuit device includes an electrical circuit that includes a plurality of electrically connected components including a component that necessitates heat measures, a substrate that physically connects main components among the plural components of the electrical circuit, and a package that hermetically seals the substrate. The component that necessitates... Agent: Oliff & Berridge, PLC

20080277781 - Multi-die molded substrate integrated circuit device: One embodiment includes a substrate having a plurality of dies and a support frame made of molding material which is molded between adjacent dies so as to join together and support adjacent dies. The embodiment further has a plurality of interconnects formed on selected die terminals and the molding material... Agent: Konrad Raynes & Victor, LLP. Attn: Int77

20080277782 - Flash memory card: A Flash memory card is disclosed comprising a substrate, a Flash memory die on top of the substrate, a controller die on top of the Flash memory die, and an interposer coupled to with the controller die and on top of the Flash memory die wherein the interposer results in... Agent: Sawyer Law Group LLP

20080277785 - Package structure for integrated circuit device and method of the same: A package structure for packaging at least one of a plurality of integrated circuit devices of a wafer is provided. The package structure includes an extension metal pad, a first conductive bump and an insulator layer. The extension metal pad electrically contacts the at least one of the plurality of... Agent: Snell & Wilmer L.L.P. (main)

20080277783 - Printed circuit board and flip chip package using the same with improved bump joint reliability: A printed circuit board and a flip chip package using the same are designed to minimize thermal stress due to different thermal coefficients present in areas having metal lines and solder resist versus other areas on the printed circuit board. The printed circuit board includes an insulation layer; a first... Agent: Ladas & Parry LLP

20080277784 - Semiconductor chip and manufacturing method thereof: A semiconductor chip formed with a bump such that the bump corresponds to a pad electrode. The pad electrode is covered with a nickel layer. The bump has an indium layer and an intermediate metal compound layer disposed between the indium layer and the nickel layer, and the intermediate metal... Agent: Rader Fishman & Grauer PLLC

20080277786 - Semiconductor package substrate: A semiconductor package substrate includes a body having an upper surface and a lower surface opposite to one another, a plurality of circuit layers formed in the body, a plurality of solder pads formed on the upper surface of the body, and a plurality of solder ball pads formed on... Agent: Edwards Angell Palmer & Dodge LLP

20080277787 - Method and pad design for the removal of barrier material by electrochemical mechanical processing: A method and apparatus for processing barrier and metals disposed on a substrate in an electrochemical mechanical planarizing system are provided. In certain embodiments a method for electroprocessing a substrate is provided. The method comprises contacting the substrate with the non-conductive surface of a polishing pad assembly, establishing a first... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080277789 - Damascene structure and opening thereof: A method for fabricating a single-damascene opening is described. The method includes providing a substrate having a conductive line formed therein. A barrier layer, a dielectric layer, a metal hard mask layer, a silicon oxynitride layer, a bottom antireflection layer and a patterned photoresist layer are sequentially formed on the... Agent: Jianq Chyun Intellectual Property Office

20080277788 - Method for manufacturing a semiconductor device, and said semiconductor device: A method for manufacturing a semiconductor device has forming a first metal wire in a groove formed in an insulating film on a semiconductor substrate, forming an interlayer dielectric on the insulating film and the first metal wire, forming a via hole by etching the interlayer dielectric, forming a first... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080277790 - Semiconductor device: A semiconductor device having a semiconductor substrate, an interlayer insulating layer formed on the substrate and having a contact hole partially exposing the substrate, and a diffusion barrier formed on the interlayer insulating layer and in the contact hole. The diffusion barrier comprises a plurality of TaSiN thin films. The... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080277791 - Semiconductor devices and methods for manufacturing the same: Semiconductor devices having a copper line layer and methods for manufacturing the same are disclosed. An illustrated semiconductor device comprises a damascene insulating layer having a contact hole, a barrier metal layer including a first ruthenium layer, a ruthenium oxide layer and a second ruthenium layer, a seed copper layer... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080277792 - Semiconductor device and method for manufacturing the same: Overlapping dummy patterns for a semiconductor device are disclosed. According to an embodiment, a first dummy pattern is formed on a substrate; a second dummy pattern is formed to be overlapped with the first dummy pattern; and a third dummy pattern is formed to provide an electrical connection between the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080277794 - semiconductor device and a method of manufacturing the same: A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080277793 - Semiconductor device and manufacturing method thereof: A semiconductor device with improved moisture resistance and its manufacturing method as well as a manufacturing method of a semiconductor device which simplifies a manufacturing process and improves productivity are offered. This invention offers a CSP type semiconductor device and its manufacturing method that can prevent moisture and the like... Agent: Morrison & Foerster LLP

20080277795 - Semiconductor integrated circuit devices having upper pattern aligned with lower pattern molded by semiconductor substrate and methods of forming the same: Provided are semiconductor integrated circuit (IC) devices having an upper pattern aligned with a lower pattern molded by a semiconductor substrate and methods of forming the same. In the semiconductor IC devices, the lower pattern contacts the upper pattern using an active region and/or an isolation layer. The methods include... Agent: Marger Johnson & Mccollom, P.C.

20080277796 - Electronic structures utilizing etch resistant boron and phosphorus materials and methods to form same: A dense boron-based or phosphorus-based dielectric material is provided. Specifically, the present invention provides a dense boron-based dielectric material comprised of boron and at least one of carbon, nitrogen, and hydrogen or a dense phosphorus-based dielectric comprised of phosphorus and nitrogen. The present invention also provides electronic structures containing the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080277797 - Interconnect structures: A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at... Agent: Duane Morris LLP (tsmc)IPDepartment

20080277798 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the same. The semiconductor device includes a first main pattern formed on a substrate and a first dummy pattern formed in a parallel direction to a first main pattern on a layer on which the first main pattern is formed. Additional dummy... Agent: Sherr & Vaughn, PLLC

20080277799 - Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies: Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the active surface devices of a semiconductor substrate using through wafer interconnects (TWIs). The TWIs may be formed prior to forming the RDLs, after forming the RDLs, or substantially... Agent: Trask Britt, P.C./ Micron Technology

20080277801 - Semiconductor component and production method: A semiconductor device includes a first die, a substrate, and a first interconnect. The first die includes a first isolation region and a first contact at least partially overlapping the first isolation region. The substrate includes a second contact. The first interconnect couples the first contact to the second contact.... Agent: Dicke, Billig & Czaja

20080277800 - Semiconductor package and method of forming the same: Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in... Agent: Harness, Dickey & Pierce, P.L.C

20080277802 - Flip-chip semiconductor package and package substrate applicable thereto: A flip-chip semiconductor package structure and a package substrate applicable thereto are disclosed. The package substrate includes a body having at least a chip-attach area disposed thereon; a plurality of solder pads disposed in the chip-attach area and arranged at different intervals; and a fluid-disturbing portion disposed in the chip-attach... Agent: Edwards Angell Palmer & Dodge LLP

20080277803 - Semiconductor device: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within... Agent: Harness, Dickey & Pierce, P.L.C

20080277804 - Mask layout method, and semiconductor device and method for fabricating the same: Provided are a mask layout method and a semiconductor device and a method for fabricating the same. The semiconductor device can include a main pattern, a first dummy pattern, and a second dummy pattern. The main pattern can be disposed on a substrate. The first dummy pattern and the second... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080277805 - Semiconductor device: Disclosed is a semiconductor device having a wafer level package structure which is characterized by containing a resin layer composed of a resin composition which is curable at 250° C. or less. Such a semiconductor device having a wafer level package structure is excellent in low stress properties, solvent resistance,... Agent: Smith, Gambrell & Russell

20080277806 - Semiconductor wafer with assisting dicing structure and dicing method thereof: A semiconductor wafer with an assisting dicing structure. The wafer comprises a substrate having a front surface and a rear surface. The front surface of the substrate comprises at least two device regions separated by at least one dicing lane. The rear surface of the substrate comprises at least one... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080272356 - Fabrication of phase change memory element with phase-change electrodes using conformal deposition: A phase change memory element with phase change electrodes, and method of making the same. Exemplary embodiments include a phase change bridge, including a bottom contact layer, a first insulating layer disposed on the bottom contact layer, a first phase change region disposed on the bottom contact layer adjacent the... Agent: Cantor Colburn, LLP - IBM Arc Division

20080272354 - Phase change diode memory: An integrated circuit having a memory includes a semiconductor line and a phase change element contacting the semiconductor line. The phase change element provides a storage location. A diode junction is formed at the interface between the semiconductor line and the phase change element.... Agent: Dicke, Billig & Czaja

20080272355 - Phase change memory device and method for forming the same: A memory device using a phase change material and a method for forming the same are disclosed. One embodiment of a memory device includes a first insulating layer provided on a substrate and defining an opening; a first conductor including a first portion and a second portion, the first portion... Agent: Marger Johnson & Mccollom, P.C.

20080272357 - Phase changeable memory device structures: A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080272358 - Phase change memory devices and methods for fabricating the same: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and... Agent: Quintero Law Office, PC

20080272359 - Phase changeable memory cells: A phase changeable memory cell is disclosed. According to embodiments of the invention, a phase changeable memory cell is formed that has a reduced contact area with one of the electrodes, compared to previously known phase changeable memory cells. This contact area can be a sidewall of one of the... Agent: Marger Johnson & Mccollom, P.C.

20080272360 - Programmable metallization cell structures including an oxide electrolyte, devices including the structure and method of forming same: A microelectronic programmable structure suitable for storing information, a device including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an oxide ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the... Agent: Snell & Wilmer L.L.P. (main)

20080272361 - High density nanotube devices: Carbon-nanotube-based devices or nanowire-based devices are formed in multiple layers to obtain higher density of such devices. The layers may be all similar such as all carbon-nanotube-based transistors. Or they may be different, such as one layer with nanowire devices and another layer with nanotube devices. Or some layers such... Agent: Aka Chan LLP

20080272362 - Adapting short-wavelength led's for polychromatic, broadband, or white emission: An adapted LED is provided comprising a short-wavelength LED and a re-emitting semiconductor construction, wherein the re-emitting semiconductor construction comprises at least one potential well not located within a pn junction. The potential well(s) are typically quantum well(s). The adapted LED may be a white or near-white light LED. The... Agent: 3m Innovative Properties Company

20080272364 - Insulating film and electronic device: An insulating film comprising: a first barrier layer; a well layer provided; and a second barrier layer is proposed. The first barrier layer consists of a material having a first bandgap and a first relative permittivity. The well layer is provided on the first barrier layer, and consists of a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080272365 - Insulating film and electronic device: An insulating film comprising: a first barrier layer; a well layer provided; and a second barrier layer is proposed. The first barrier layer consists of a material having a first bandgap and a first relative permittivity. The well layer is provided on the first barrier layer, and consists of a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080272363 - Selectively conducting devices, diode constructions, constructions, and diode forming methods: Some embodiments include selectively conducting devices having a first electrode, a second electrode, and dielectric material between the first and second electrodes. The dielectric material may be configured to conduct current from the first electrode to the second electrode when a first voltage is applied across the first electrode and... Agent: Wells St. John P.s.

20080272366 - Field effect transistor having germanium nanorod and method of manufacturing the same: A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate oxide layer formed on a silicon substrate, at least one nanorod embedded in the gate oxide layer having both ends thereof... Agent: Harness, Dickey & Pierce, P.L.C

20080272368 - Extended redistribution layers bumped wafer: A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of... Agent: Quarles & Brady LLP

20080272367 - Light-emitting device having improved light output: A light-emitting LED device has one or more light-emitting LED elements, including first and second spaced-apart electrodes with one or more light-emitting layers formed there-between, wherein at least one of the electrodes is a transparent electrode. Also included are a first transparent encapsulating layer having a first optical index formed... Agent: David Novais Patent Legal Staff

20080272369 - Organic electronic device: An organic electronic device. The device includes a first electrode to inject or extract hole, the first electrode including a conductive layer and an n-type organic compound layer disposed on the conductive layer, a second electrode to inject or extract electron, a p-type organic compound layer disposed between the n-type... Agent: Mckenna Long & Aldridge LLP

20080272370 - Field-effect transistor and method for manufacturing the same: A method for manufacturing a field-effect transistor includes the steps of forming a source electrode and a drain electrode each containing hydrogen or deuterium; forming an oxide semiconductor layer in which the electrical resistance is decreased if hydrogen or deuterium is added; and, causing hydrogen or deuterium to diffuse from... Agent: Fitzpatrick Cella Harper & Scinto

20080272373 - Flash memory device having resistivity measurement pattern and method of forming the same: A flash memory device has a resistivity measurement pattern and method of forming the same. A trench is formed in an isolation film in a Self-Aligned Floating Gate (SAFG) scheme. The trench is buried to form a resistivity measurement floating gate. This allows the resistivity of the floating gate to... Agent: Marshall, Gerstein & Borun LLP

20080272371 - Resistance-based etch depth determination for sgt technology: A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test... Agent: Joshua D. Isenberg Jdi Patent

20080272372 - Test structures for stacking dies having through-silicon vias: A semiconductor die including a test structure is provided. The semiconductor die includes a loop-back formed on a surface of the semiconductor die. The loop-back structure includes a first bonding pad on a first surface; and a second bonding pad on the first surface, wherein the first and the second... Agent: Slater & Matsil, L.L.P.

20080272374 - Semiconductor display device: To provide a semiconductor display device capable of displaying an image having clarity and a desired color, even when the speed of deterioration of an EL layer is influenced by its environment. Display pixels and sensor pixels of an EL display each have an EL element, and the sensor pixels... Agent: Fish & Richardson P.C.

20080272376 - Semiconductor device and method of manufacturing the same: In a semiconductor device having a substrate which has a metal surface, an insulating film which is formed on the substrate having the metal surface, and a pixel unit which is formed on the insulating film; the pixel unit includes a TFT, and wiring lines connected with the TFT, and... Agent: Cook Alex Ltd

20080272375 - Thin film transistor array panel, display device including the panel, and method for manufacturing the display device: A thin film transistor array panel, a display device including the thin film transistor array panel, and a method for manufacturing the display device. The thin film transistor array panel includes a substrate having first and second surfaces, a first thin film form formed on the first surface and including... Agent: Cantor Colburn, LLP

20080272377 - Gallium nitride substrate and gallium nitride film deposition method: Affords high-carrier-concentration, low-cracking-incidence gallium nitride substrates and methods of forming gallium nitride films. A gallium nitride film 52 in which the carrier concentration is 1×1017 cm−3 or more is created. Initially, a gallium nitride layer 51 including an n-type dopant is formed onto a substrate 50. Then, the gallium nitride... Agent: Judge Patent Associates

20080272378 - Method for forming a nitride semiconductor layer and method for separating the nitride semiconductor layer from the substrate: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure.... Agent: Jianq Chyun Intellectual Property Office

20080272379 - Display apparatus, method and light source: In accordance with the invention, a display apparatus including a light source is provided, the light source having at least one superluminescent light emitting diode (SLED), the apparatus further having at least one light modulating device arranged in a beam path of a light beam emitted by the light source... Agent: Rankin, Hill & Clark LLP

20080272381 - Organic light emitting display with single crystalline silicon tft and method of fabricating the same: Provided is an organic light emitting display, in which a semiconductor circuit unit of 2T-1C structure including a switching transistor and a driving transistor formed of single crystalline silicon is formed on a plastic substrate. A method of fabricating the single crystalline silicon includes: growing a single crystalline silicon layer... Agent: Buchanan, Ingersoll & Rooney PC

20080272380 - Shield member in led apparatus: An LED apparatus for illumination toward a preferential side in a downward and outward direction including a shield member in the form of a layer positioned over LED packages and secondary lens members. The shield member has a shield portion and a substantially planar non-shield portion thereabout. In preferred embodiments,... Agent: Jansson Shupe & Munger Ltd.

20080272382 - Light emitting device and method of manufacturing the same: A light emitting device and a method of manufacturing the same are disclosed. The light emitting device includes a buffer layer formed on a substrate, a nitride semiconductor layer including a first semiconductor layer, an active layer, and a second semiconductor layer, which are sequentially stacked on the buffer layer,... Agent: Birch Stewart Kolasch & Birch

20080272387 - Adapting short-wavelength led's for polychromatic, broadband, or \"white\" emission: An adapted LED is provided comprising a short-wavelength LED and a re-emitting semiconductor construction, wherein the re-emitting semiconductor construction comprises at least one potential well not located within a pn junction. The potential well(s) are typically quantum well(s). The adapted LED may be a white or near-white light LED. The... Agent: 3m Innovative Properties Company

20080272386 - Light emitting devices for light conversion and methods and semiconductor chips for fabricating the same: Broad spectrum light emitting devices and methods and semiconductor chips for fabricating such devices include a light emitting element, such as a diode or laser, which emits light in a predefined range of frequencies. The light emitting element includes a shaped substrate suitable for light extraction through the substrate and... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080272384 - Light emitting diode: A light emitting diode (LED) having disposed on a top of a package an optical mechanism comprised of multiple grooves or dots to promote optical use efficiency of the packaging through light condensing effects produced by the optical mechanism to collect a light source inside the LED to emit in... Agent: Troxell Law Office PLLC

20080272385 - Light emitting diode: A light emitting diode includes a base, a light emitting chip, and a wavelength converting layer. The base is formed with a recessed portion that has a bottom wall surface, and a sidewall surface extending upwardly from the bottom wall surface and cooperating with the bottom wall surface to define... Agent: Rosenberg, Klein & Lee

20080272388 - Method for fabricating thin film pattern, device and fabricating method therefor, method for fabricating liquid crystal display, liquid crystal display, method for fabricating active matrix substrate, electro-optical apparatus, and electrical apparatus: A method for fabricating a thin film pattern on a substrate, includes the steps of: forming a concave part on the substrate that conforms to the thin film pattern; and applying a function liquid into the concave part.... Agent: Oliff & Berridge, PLC

20080272383 - Side mountable semiconductor light emitting device packages, panels and methods of forming the same: Side-mountable semiconductor light emitting device packages include an electrically insulating substrate having a front face and a back face and a side face extending therebetween. The side face is configured for mounting on an underlying surface. An electrically conductive contact is provided proximate an edge of the substrate on the... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080272389 - Infrared source: A sealed infrared radiation source includes an emitter membrane stimulated by an electrical current conducted through the membrane, which acts like an electrical conductor, wherein the membrane is mounted between first and second housing parts, at least one being transparent in the IR range, each housing part defining a cavity... Agent: Vern Maine & Associates

20080272390 - Led apparatus: An LED apparatus comprises a base, an LED device, an electrode member and an insulation layer. The base has a bevel side to be embedded with a corresponding receiving base for electrical conduction of an electrode (e.g., a negative electrode). The LED device is placed on an upper surface of... Agent: Connolly Bove Lodge & Hutz LLP

20080272392 - Nitride crystal, nitride crystal substrate, epilayer-containing nitride crystal substrate, semiconductor device and method of manufacturing the same: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal... Agent: Mcdermott Will & Emery LLP

20080272391 - Silicon compatible integrated light communicator: Various methods and devices are implemented using efficient silicon compatible integrated light communicators. According to one embodiment of the present invention, a semiconductor device is implemented for communicating light, such as by detecting, modulating or emitting light. The device has a silicon-seeding location, an insulator layer and a second layer... Agent: Crawford Maunu PLLC

20080272395 - Enhanced hole mobility p-type jfet and fabrication method therefor: Enhanced hole mobility p-type JFET and fabrication methods. A p-type junction field effect transistor including a substrate of n-type, a source region and a drain region formed in the substrate; wherein the source region and the drain region are p-type doped and at least one of the source region and... Agent: Perkins Coie LLP

20080272394 - Junction field effect transistors in germanium and silicon-germanium alloys and method for making and using: Junction field effect transistors (JFET) formed in substrates containing germanium. JFETs having polycrystalline semiconductor surface contacts with self-aligned silicide formed thereon and self-aligned source, drain and gate regions formed by thermal drive-in of impurities from surface contacts into the substrate, and implanted link regions. Others have a polycrystalline semiconductor gate... Agent: Perkins Coie LLP

20080272393 - Semiconductor device having strain-inducing substrate and fabrication methods thereof: A semiconductor device includes a semiconductor substrate that includes a substrate layer having a first composition of semiconductor material. A source region, drain region, and a channel region are formed in the substrate, with the drain region spaced apart from the source region and the gate region abutting the channel... Agent: Baker Botts L.L.P.

20080272396 - Simplified method of producing an epitaxially grown structure: Method to produce a structure consisting of depositing a material by columnar epitaxy on a crystalline face of a substrate (2), of continuing so that the columns (4) give a continuous layer (5). The surface is provided with a period array of bumps (3) on a nanometric scale, each bump... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080272397 - Semiconductor device with modulated field element: The current invention introduces a modulated field element incorporated into the semiconductor device outside the controlling electrode and active areas. This element changes its conductivity and/or dielectric properties depending on the electrical potentials of the interface or interfaces between the modulated field element and the semiconductor device and/or incident electromagnetic... Agent: Hoffman Warnick LLC

20080272398 - Conductive spacers for semiconductor devices and methods of forming: A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing... Agent: Joseph P. Abate Intellectual Property Law

20080272399 - Pixel sensor cell for collecting electrons and holes: The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel... Agent: Ibm Microelectronics Intellectual Property Law

20080272400 - Pixel sensor cell for collecting electrons and holes: The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel... Agent: Ibm Microelectronics Intellectual Property Law

20080272405 - Content addressable memory cell including a junction field effect transistor: A semiconductor device that includes a memory cell having a junction field effect transistor (JFET) used to form a content addressable memory (CAM) cell is disclosed. The JFET may include a data storage region disposed between a first and second insulating region. The data storage region provides a first threshold... Agent: Darryl G. Walker

20080272401 - Inverted junction field effect transistor and method of forming thereof: A junction field effect transistor includes a substrate and a well region on the substrate. A channel region lies in the well region. A source region lies in the channel region. A drain region lies in the channel region and apart from the source region. A gate region is isolated... Agent: Baker Botts L.L.P.

20080272402 - Jfet device with improved off-state leakage current and method of fabrication: A junction field effect transistor comprises a semiconductor substrate. A first impurity region of a first conductivity type is formed in the substrate. A second impurity region of the first conductivity type is formed in the substrate and spaced apart from the first impurity region. A channel region of the... Agent: Baker Botts L.L.P.

20080272403 - Jfet device with virtual source and drain link regions and method of fabrication: A junction field effect transistor comprises a semiconductor substrate. A source region of a first conductivity type is formed in the substrate. A drain region of the first conductivity type is formed in the substrate. A channel region of the first conductivity type is formed in the substrate. A gate... Agent: Baker Botts L.L.P.

20080272404 - Method for applying a stress layer to a semiconductor device and device formed therefrom: A semiconductor device includes a substrate of semiconductor material. A source region, a drain region, and a conducting region of the semiconductor device are formed in the substrate and doped with a first type of impurities. The conducting region is operable to conduct current between the drain region and the... Agent: Baker Botts L.L.P.

20080272406 - Double gate jfet with reduced area consumption and fabrication method therefor: Double gate JFET with reduced area consumption and fabrication method therefore. Double-gate semiconductor device including a substrate having a shallow trench isolator region comprising a first STI and a second STI, a channel region having a first and second channel edges, the channel region formed in the substrate and disposed... Agent: Perkins Coie LLP

20080272407 - Semiconductor device having a fin structure and fabrication method thereof: A semiconductor device includes a silicon on insulator (SOI) substrate, comprising an insulation layer formed on semiconductor material, and a fin structure. The fin structure is formed of semiconductor material and extends from the SOI substrate. Additionally, the fin structure includes a source region, a drain region, a channel region,... Agent: Baker Botts L.L.P.

20080272408 - Active area junction isolation structure and junction isolated transistors including igfet, jfet and mos transistors and method for making: Integrated active area isolation structure for transistor to replace larger and more expensive Shallow Trench Isolation or field oxide to isolate transistors. Multiple well implant is formed with PN junctions between wells and with surface contacts to substrate and wells so bias voltages applied to reverse bias PN junctions to... Agent: Perkins Coie LLP

20080272409 - Jfet having a step channel doping profile and method of fabrication: A junction field effect transistor comprises a semiconductor substrate, a source region formed in the substrate, a drain region formed in the substrate and spaced apart from the source region, and a gate region formed in the substrate. The transistor further comprises a first channel region formed in the substrate... Agent: Baker Botts L.L.P.

20080272412 - Method and structure to reduce contact resistance on thin silicon-on-insulator device: A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.... Agent: Mcginn Intellectual Property Law Group, PLLC

20080272410 - Self-aligned spacer contact: A metal-oxide-semiconductor field-effect transistor (MOSFET) having self-aligned spacer contacts is provided. In accordance with embodiments of the present invention, a transistor, having a gate electrode and source/drain regions formed on opposing sides of the gate electrode, is covered with a first dielectric layer. A first contact opening is formed in... Agent: Slater & Matsil, L.L.P.

20080272411 - Semiconductor device with multiple tensile stressor layers and method: A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a... Agent: Freescale Semiconductor, Inc. Law Department

20080272413 - Light-sensitive component: In order to detect light with in particular a high blue component, the inversion zone and the space charge zone of a CMOS-like structure are used. In conjunction with an at least partly transparent gate electrode, in particular a transparent conductive oxide or a patterned gate electrode, it becomes possible... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20080272414 - Image sensing cell, device, method of operation, and method of manufacture: An image sensing device can include one or more image sensing cells. Each image sensing cell can have a charge store element formed from a semiconductor material doped to a first conductivity type. The charge store element can be in contact with a channel region formed from a semiconductor material... Agent: Haverstock & Owens, LLP

20080272415 - Solid-state imaging device: A solid-state imaging device includes a photoelectric conversion section which is provided for each pixel and which converts light incident on a first surface of a substrate into signal charges, a circuit region which reads signal charges accumulated by the photoelectric conversion section, a multilayer film including an insulating film... Agent: Robert J. Depke Lewis T. Steadman

20080272420 - Cmos image sensor and manufacturing method thereof: A gate insulation layer with a high dielectric constant for a CMOS image sensor formed by a damascene process. A silicide layer on a gate electrode layer is formed in both a pixel region and a peripheral circuit region, and a silicide layer on a source/drain region is formed only... Agent: Mckenna Long & Aldridge LLP

20080272417 - Image sensor and method for manufacturing the same: An image sensor and method for manufacturing the same are provided. The image sensor can include an isolation area and active area on a substrate; a photodiode area and a transistor area provided on the active area; a gate insulating layer on the transistor area; and a gate electrode provided... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080272416 - Image sensor and method of manufacturing the same: Provided is an image sensor and method of manufacturing the same. The image sensor can include a semiconductor substrate, a metal interconnection layer, an inorganic layer, lens seed patterns, and microlenses. The semiconductor substrate can include unit pixels. The metal interconnection layer can be disposed on the semiconductor substrate to... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080272418 - Semiconductor component comprising a buried mirror: A method for forming a buried mirror in a semiconductor component includes the steps of forming a structure comprising a semiconductor layer laid on an insulating layer covering a substrate; forming one or several openings in the semiconductor layer emerging at the surface of the insulating layer; eliminating a portion... Agent: Graybeal, Jackson, Haley LLP

20080272419 - Solid-state imaging device: A solid-state imaging device includes a photoelectric conversion section which is provided for each pixel and which converts light incident on a first surface of a substrate into signal charges, a circuit region which reads signal charges accumulated by the photoelectric conversion section, a multilayer film including an insulating film... Agent: Robert J. Depke Lewis T. Steadman

20080272421 - Methods, constructions, and devices including tantalum oxide layers: Methods, constructions, and devices that include tantalum oxide layers adjacent to niobium nitride are disclosed herein. In certain embodiments, the niobium nitride is crystalline and has a hexagonal close-packed structure. Optionally, the niobium nitride can have a surface that includes niobium oxide adjacent to at least a portion thereof. In... Agent: Mueting, Raasch & Gebhardt, P.A.

20080272423 - Conductive structures, non-volatile memory device including conductive structures and methods of manufacturing the same: Conductive structures in an integrated circuit device including an integrated circuit substrate and first conductive layer patterns on the substrate. Second conductive layer patterns are on the substrate extending between respective ones of the first conductive layer patterns. Adjacent ones of the first and second conductive layer patterns are on... Agent: Myers Bigel Sibley & Sajovec

20080272422 - Transistor providing different threshold voltages and method of fabrication thereof: A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of the second portion allows... Agent: Baker Botts L.L.P.

20080272424 - Nonvolatile memory device having fast erase speed and improved retention characteristics and method for fabricating the same: Disclosed herein is a nonvolatile memory device that includes a substrate, a tunneling layer over the substrate, a charge trapping layer over the tunneling layer, an insulating layer for improving retention characteristics over the charge trapping layer, a blocking layer over the insulating layer, and a control gate electrode over... Agent: Marshall, Gerstein & Borun LLP

20080272426 - Nonvolatile memory transistors including active pillars and related methods and arrays: Nonvolatile memory transistors including active pillars having smooth side surfaces with an acute inward angle are provided. The transistor has an active pillar having smooth side surfaces with an acute inward angle and protrudes from semiconductor substrate. A gate electrode surrounds the side surfaces of the active pillar. A charge... Agent: Myers Bigel Sibley & Sajovec

20080272425 - Semiconductor storage element and manufacturing method thereof: A semiconductor storage element includes: a semiconductor layer constituted of a line pattern with a predetermined width formed on a substrate; a quantum dot forming an electric charge storage layer formed on the semiconductor layer through a first insulating film serving as a tunnel insulating film; an impurity diffusion layer... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080272427 - Sonos memory device with reduced short-channel effects: A non-volatile memory device on a semiconductor substrate having a semiconductor surface layer (2) comprises a source region (12,S), a drain region (12,D), a channel region (CO), a memory element (ME), and a gate (G). The channel region (CO) extends in a first direction (X) between the source region (12,S)... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080272431 - Method of manufacturing semiconductor device having recess gate structure with varying recess width for increased channel length: A varying-width recess gate structure having a varying-width recess formed in a semiconductor device can sufficiently increase the channel length of the transistor having a gate formed in the varying-width recess, thereby effectively reducing the current leakage and improving the refresh characteristics. In the method of manufacturing the recess gate... Agent: Ladas & Parry LLP

20080272430 - Semiconductor device and method of forming the same: A semiconductor device includes an active region defined in a substrate, the active region having a trench extending below a surface of the substrate; an impurity region provided along a bottom surface and a lower sidewall of the trench, wherein an upper portion of the impurity region is spaced apart... Agent: Marger Johnson & Mccollom, P.C.

20080272428 - Semiconductor device structure with a tapered field plate and cylindrical drift region geometry: A vertically oriented self terminating discrete trench MOS device (1) that includes a cylindrical drift region (18) that extend downward from a surface region to a substrate (11) and a dielectric region (20) that exponentially tapers outward from the cylindrical drift region as the drift region approaches the substrate.... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080272429 - Superjunction devices having narrow surface layout of terminal structures and methods of manufacturing the devices: Superjunction semiconductor devices having narrow surface layout of terminal structures and methods of manufacturing the devices are provided. The narrow surface layout of terminal structures is achieved, in part, by connecting a source electrode to a body contact region within a semiconductor substrate at a body contact interface comprising at... Agent: Panitch Schwarze Belisario & Nadel LLP

20080272432 - Accumulation mode mos devices and methods for fabricating the same: Accumulation mode MOS transistors and methods for fabricating such transistors are provided. A method comprises providing an SOI layer disposed overlying a substrate with an insulating layer interposed therebetween. The SOI layer is impurity doped with a first dopant of a first conductivity type and spacers and a gate stack... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080272433 - Dual metal gates for mugfet device: Exemplary embodiments provide methods and structures for controlling work function values of dual metal gate electrodes for transistor devices. Specifically, the work function value of one of the PMOS and NMOS metal gate electrodes can be controlled by a reaction between stacked layers deposited on a gate dielectric material. The... Agent: Texas Instruments Incorporated

20080272434 - Non-volatile memory device and method of manufacturing the same: A non-volatile memory device and a method of manufacturing the same are disclosed. In the non-volatile memory device, first gate structures and first impurity diffusion regions are formed on a substrate. A first insulating interlayer is formed on the substrate. A semiconductor layer including second gate structures and second impurity... Agent: Marger Johnson & Mccollom, P.C.

20080272435 - Semiconductor device and method of forming the same: A semiconductor device includes a first gate structure including a gate dielectric layer directly contacting the substrate, a bottom electrode on the gate dielectric layer and a top electrode on the bottom electrode, and a second gate structure including a gate dielectric layer directly contacting the substrate and a gate... Agent: North America Intellectual Property Corporation

20080272436 - Semiconductor device and method of fabricating the same: A semiconductor device includes a first stress film covering a first gate electrode and first source/drain areas of a first transistor area and at least a portion of a third gate electrode of an interface area, a second stress film covering a second gate electrode and second source/drain areas of... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080272438 - Cmos circuits with high-k gate dielectric: A CMOS structure is disclosed in which a first type FET contains a liner, which liner has oxide and nitride portions. The nitride portions are forming the edge segments of the liner. These nitride portions are capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first... Agent: Innovation Interface, LLC

20080272439 - Small geometry mos transistor with thin polycrystalline surface contacts and method for making: Process for fabrication of MOS semiconductor structures and transistors such as CMOS structures and transistors with thin gate oxide, polysilicon surface contacts having thickness on the order of 500 Angstroms or less and with photo-lithographically determined distances between the gate surface contact and the source and drain contacts. Semiconductor devices... Agent: Perkins Coie LLP

20080272437 - Threshold adjustment for high-k gate dielectric cmos: A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a thicker oxide... Agent: Innovation Interface, LLC

20080272440 - Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p+-type impurity region is formed between an NMOS and a PMOS and in contact with a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080272441 - Method and circuit for down-converting a signal: Methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal are described herein. Briefly stated, such methods, systems, and apparatuses operate by receiving an EM signal and an aliasing signal having an aliasing rate. The EM signal is aliased according to the aliasing signal to... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080272442 - N+ poly on high-k dielectric for semiconductor devices: The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped... Agent: Texas Instruments Incorporated

20080272443 - Field effect transistor having field plate electrodes: A field effect transistor includes an active layer formed on a semiconductor substrate, source and drain electrodes formed apart from each other on the active layer, a gate electrode formed between the source and drain electrodes, a first interlayer film formed on the active layer, a first field plate (FP)... Agent: Rabin & Berdo, PC

20080272444 - Method of manufacturing semiconductor device and semiconductor device: A method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device that is provided with a step of successively forming a gate insulating film and a gate electrode on a semiconductor substrate and a step of forming a silicon nitride film that... Agent: Sughrue Mion, PLLC

20080272445 - Low-k displacer for overlap capacitance reduction: Source/drain extensions and source and drain regions are formed in a semiconductor substrate utilizing an optional temporary first gate spacer and a temporary second gate spacer. After forming a gate silicide and a source and drain silicide in a silicidation process, the optional temporary first gate spacer and a temporary... Agent: Scully, Scott, Murphy & Presser, P.C.

20080272447 - Method for manufacturing a micro-electro-mechanical device, in particular an optical microswitch, and micro-electro-mechanical device thus obtained: A method for manufacturing a micro-electro-mechanical device, which has supporting parts and operative parts, includes providing a first semiconductor wafer, having a first layer of semiconductor material and a second layer of semiconductor material arranged on top of the first layer, forming first supporting parts and first operative parts of... Agent: Seed Intellectual Property Law Group PLLC

20080272446 - Packaged mems device assembly: A packaged micro-electromechanical systems (MEMS) device assembly includes a MEMS device, a substrate within which the MEMS device is disposed, and a lid disposed over the substrate. The assembly may include one or more first cavities within the lid having a predetermined volume satisfying packaging specifications for the packaged MEMS... Agent: Hewlett Packard Company

20080272448 - Integrated circuit having a magnetic tunnel junction device: An integrated circuit having a magnetic tunnel junction device is disclosed. In one embodiment, the device includes: a spin transfer torque magnetization reversal structure including a first ferromagnetic structure, a second ferromagnetic structure, and a tunnel barrier structure between the first ferromagnetic structure and the second ferromagnetic structure.... Agent: Steven E. Dicke Dicke, Billig & Czaja, PLLC

20080272452 - Image sensor and method for manufacturing the same: An image sensor that includes a hard mask layer formed in the upper surface region of the planarization layer and under a microlens to protect an underlying planarization layer from chemicals used during performing a cleaning process after formation of the microlens. The microlens is composed of inorganic materials to... Agent: Sherr & Vaughn, PLLC

20080272451 - Image sensor and method of manufacturing the same: An image sensor and method of manufacturing the same are provided. The image sensor can include a semiconductor substrate having unit pixels; an interlayer dielectric layer formed on the semiconductor substrate and including metal interconnections; a first protective layer comprising an oxide layer formed on the interlayer dielectric layer; a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080272453 - Optical device cooling apparatus and method: An optical device cooling apparatus includes an image sensor array and a MEMS fan. The MEMS fan is formed integrally with the image sensor array, and cools the image sensor array.... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080272450 - Portable optical detection chip and manufacturing method thereof: A portable optical detection chip comprises a substrate, a plurality of avalanche-type photosensitive device modules and a plurality of plane mirrors. The plurality of avalanche-type photosensitive device modules are formed on the substrate, and each of them comprises a plurality of avalanche-type photosensitive devices and a plurality of lenses. Each... Agent: Wpat, PC Intellectual Property Attorneys

20080272449 - Solid-state image pickup device, solid-state image pickup device manufacturing method and camera: A solid-state image pickup device 1 has a construction in which a P-type semiconductor layer 102, an insulating layer 104, a color filter 106, a light transmitting layer 107, and a light focusing layer 108 are sequentially laminated on an N-type semiconductor layer 101. A plurality of photodiodes 103 are... Agent: Mcdermott Will & Emery LLP

20080272454 - Light-collecting device, solid-state imaging apparatus and method of manufacturing thereof: Each pixel (2.8 mm square in size) includes a distributed refractive index lens (1), a color filter (2) for green, Al wirings (3), a signal transmitting unit (4), a planarized layer (5), a light-receiving element (Si photodiode) (6), and an Si substrate (7). The concentric circle structure of the distributed... Agent: Wenderoth, Lind & Ponack L.L.P.

20080272455 - Solid-state imaging device: An n/p semiconductor substrate is formed in such a manner that an n type semiconductor layer is deposited on a p+ semiconductor substrate. An imaging area including a plurality of n type semiconductor regions making photoelectric conversion and a plurality of p type semiconductor region for isolation formed around the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080272456 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises a buffer layer 16 of an i-InAlAs layer formed over an SI-InP substrate 14, insulating films 24, 36 of BCB formed over the buffer layer 16, and a coplanar interconnection including a signal line 52 and ground lines 54 formed over the insulating film 36, a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080272457 - Formation of dummy features and inductors in semiconductor fabrication: A structure and a method for forming the same. The structure includes (a) a substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface, (b) N semiconductor regions on the substrate, and (c) P semiconductor regions on the substrate, N and P... Agent: Schmeiser, Olsen & Watts

20080272458 - Post last wiring level inductor using patterned plate process: A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above the substrate; an insulative layer on and above the capping layer; a first layer of photo-imagable material on and above the insulative layer; a layer of oxide... Agent: Schmeiser, Olsen & Watts

20080272459 - Semiconductor device and manufacturing method of semiconductor device: A semiconductor device and method of manufacturing the same are provided. According to certain embodiments, a device layer structure can be formed above a metal wiring line by using a stepped portion of the wiring line as an alignment key. The stepped portion can be provided by a height difference... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080272461 - Capture of residual refractory metal within semiconductor device: There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and... Agent: Buchanan, Ingersoll & Rooney PC

20080272460 - Thin film resistors integrated at two different metal interconnect levels of single die: An integrated circuit includes a first thin film resistor on a first dielectric layer. A first layer of interconnect conductors on the first dielectric layer includes a first and second interconnect conductors electrically contacting the first thin film resistor. A second dielectric layer is formed on the first dielectric layer.... Agent: Texas Instruments Incorporated

20080272463 - Method and apparatus for growing a group (iii) metal nitride film and a group (iii) metal nitride film: A process and apparatus for growing a group (III) metal nitride film by remote plasma enhanced chemical vapour deposition are described. The process comprises heating an object selected from the group consisting of a substrate and a substrate comprising a buffer layer in a growth chamber to a temperature in... Agent: Heller Ehrman LLP

20080272462 - Nitride-based semiconductor device and method for fabricating the same: A nitride-based semiconductor device according to the present invention includes a semiconductor multilayer structure supported on a substrate structure 101 with electrical conductivity. The principal surface of the substrate structure 101 has at least one vertical growth region, which functions as a seed crystal for growing a nitride-based semiconductor vertically,... Agent: Mark D. Saralino (mei) Renner, Otto, Boisselle & Sklar, LLP

20080272465 - Semiconductor die with through-hole via on saw streets and through-hole via in active area of die: A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle... Agent: Quarles & Brady LLP

20080272464 - Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer: A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle... Agent: Quarles & Brady LLP

20080272466 - Semiconductor substrates including vias of nonuniform cross section and associated structures: Methods for forming a via and a conductive path are disclosed. The methods include forming a via within a wafer with cyclic etch/polymer phases, followed by an augmented etch phase. The resulting via may include a first portion having a substantially uniform cross section and a second portion in the... Agent: Trask Britt, P.C./ Micron Technology

20080272467 - Method for forming fine pattern of semiconductor device: A method for forming a fine pattern of a semiconductor device includes forming a deposition film over a substrate having an underlying layer. The deposition film includes first, second, and third mask films. The method also includes forming a photoresist pattern over the third mask film, patterning the third mask... Agent: Marshall, Gerstein & Borun LLP

20080272468 - Grounded shield for blocking electromagnetic interference in an integrated circuit package: An integrated circuit package for blocking electromagnetic interference includes a top layer formed in a package substrate. A first plurality of via groups is formed in the top layer surrounding an area on the top layer for an integrated circuit die. At least one lower layer is formed in the... Agent: Lsi Logic Corporation Corporate Legal Department

20080272469 - Semiconductor die package and integrated circuit package and fabricating method thereof: A semiconductor die package includes a substrate, a semiconductor die mounted on the substrates a molding covering the semiconductor die and which is formed on the substrate and a conductive layer laminated on the molding.... Agent: Cha & Reiter, LLC

20080272470 - Same size through-hole via die stacked package: A semiconductor package includes a substrate or leadframe structure. A plurality of interconnected dies, each incorporating a plurality of through-hole vias (THVs) disposed along peripheral surfaces of the plurality of dies, are disposed over the substrate or leadframe structure. The plurality of THVs are coupled to a plurality of bond... Agent: Quarles & Brady LLP

20080272471 - Electro-optical device and electronic apparatus: An electro-optical device includes an electro-optical panel having a substrate; a plurality of input terminals that are arranged in a first direction on the substrate; and a semiconductor device provided with a plurality of input bumps electrically connected to the input terminals through conductive organic members. The input terminals connected... Agent: Harness, Dickey & Pierce, P.L.C

20080272472 - Semiconductor packaging device comprising a semiconductor chip including a mosfet: A thin semiconductor device difficult to cause breakage of a semiconductor chip is disclosed. The semiconductor device comprises a sealing member, a semiconductor chip positioned within the sealing member, the semiconductor chip having a source electrode and a gate electrode on a first main surface thereof and a drain electrode... Agent: Stanley P. Fisher Reed Smith LLP

20080272474 - Apparatus for integrated circuit cooling during testing and image based analysis: An apparatus for implementing integrated circuit cooling during testing and image-based analysis thereof includes a lid configured to define a cavity surrounding an integrated circuit die, the die mounted to a module substrate. One or more fluid passages are defined within the lid, wherein the passages facilitate the flow of... Agent: Cantor Colburn LLP - IBM Fishkill

20080272473 - Optical device and method of manufacturing the same: The present invention provides an optical device (2) including: a substrate (1) having a resin base (11) provided with an opening, a plurality of conductors (13) embedded in the resin base (11) such that at least parts of the plurality of conductors (13) are exposed on a lower face of... Agent: Steptoe & Johnson LLP

20080272475 - Air cavity package for a semiconductor die and methods of forming the air cavity package: A die package (72) for a semiconductor die (20). A plurality of the die packages (72) are formed on a single carrier (10) by applying a body (55) of molding compound across a carrier (10) with an air cavity (70) defined in the molding compound about each of a plurality... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080272478 - Circuit and method for interconnecting stacked integrated circuit dies: Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080272477 - Package-on-package using through-hole via die on saw streets: A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically... Agent: Quarles & Brady LLP

20080272476 - Through-hole via on saw streets: A semiconductor device is manufactured by, first, providing a wafer designated with a saw street guide. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies.... Agent: Quarles & Brady LLP

20080272479 - Integrated circuit package system with device cavity: An integrated circuit package system is provided including connecting an integrated circuit die with an external interconnect, forming a first encapsulation having a device cavity with the integrated circuit die therein, mounting a device in the device cavity over the integrated circuit die, and forming a cover over the device... Agent: Law Offices Of Mikio Ishimaru

20080272480 - Land grid array semiconductor package: An LGA (Land Grid Array) semiconductor package mainly comprises a substrate, a chip, a soldering layer and a foot stand. The chip is disposed on a top surface of the substrate and is electrically connected to a plurality of metal pads formed on a bottom surface of the substrate. The... Agent: Troxell Law Office PLLC

20080272481 - Pin grid array package substrate including slotted pins: An electrically conductive pin comprising a pin stem and a pin head attached to the pin stem. The pin head is adapted to be mounted onto a surface of a microelectronic substrate to support the pin stem. The pin head defines at least one slot therein, the at least one... Agent: Intel Corporation C/o Intellevate, LLC

20080272482 - Integrated circuit package with top-side conduction cooling: An IC package that employs top-side conduction cooling. The IC package has a low thermal resistance between a substrate housed within the package and the lid of the package. Thermal resistance is decreased by increasing the conduction cross-sections laterally through the package and lid and vertically from the package into... Agent: Honeywell International Inc.

20080272483 - High power package with dual-sided heat sinking: An assembly includes a semiconductor die disposed between an upper substrate and a lower substrate. A circuit board that defines a through hole is spaced axially below the upper substrate to define a gap between the upper substrate and the circuit board. An upper heat sink is thermally connected to... Agent: Delphi Technologies, Inc.

20080272484 - Liquid cooled power electronic circuit comprising a stacked array of directly cooled semiconductor chips: A stacked array of channeled semiconductor chips defining a power electronic circuit is mounted in a sealed container provided with inlet and outlet passages for liquid coolant. Leadframe terminals supported by the container engage selected terminals of the semiconductor chips and form leads for mounting the container on a circuit... Agent: Delphi Technologies, Inc.

20080272485 - Liquid cooled power electronic circuit comprising stacked direct die cooled packages: A plurality of direct die cooled semiconductor power device packages are vertically stacked with both coolant and electrical interfacing to form a liquid cooled power electronic circuit. The packages are individually identical, and selectively oriented prior to stacking in order to form the desired circuit connections and laterally stagger the... Agent: Delphi Technologies, Inc.

20080272486 - Chip package structure: A chip package structure includes a carrier, an interposer, a plurality of electrically conductive elements, a first sealant, a chip, and a second sealant. The interposer is disposed on the carrier. The electrically conductive elements electrically connect the interposer and the carrier. The first sealant seals the electrically conductive elements.... Agent: J C Patents, Inc.

20080272487 - System for implementing hard-metal wire bonds: A wire bond system including providing an integrated circuit die with a bond pad thereon, forming a soft bump on the bond pad, and wire bonding a hard-metal wire on the soft bump.... Agent: Law Offices Of Mikio Ishimaru

20080272489 - Package substrate and its solder pad: A semiconductor chip substrate with solder pad includes: a core layer and at least one conductive structure formed on the surface of the core layer; an insulation layer with at least one patterned opening covering the conductive structure, wherein the patterned opening has a center portion and a plurality of... Agent: Abelman, Frayne & Schwab

20080272488 - Semiconductor device: A semiconductor device according to the present invention includes a semiconductor chip having a functional surface formed with a functional element, an electrode pad provided directly on the functional element on the functional surface of the semiconductor chip, a protective resin layer laminated on the functional surface of the semiconductor... Agent: Rabin & Berdo, PC

20080272491 - Manufacturing of a semiconductor device and the manufacturing method: A technology that improves the reliability of a semiconductor device and realizes a high performance by a laminated structure that has enough barrier properties against copper, reduces the wire delay time by lowering the capacitance between wirings and improves the adhesion between wirings is provided. There is a semiconductor device... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080272490 - Semiconductor device including ruthenium electrode and method for fabricating the same: A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a first plug filled in a portion of the contact hole,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080272492 - Method of blocking a void during contact formation process and device having the same: An electronic device can include conductive regions. A void can extend between different portions of an insulating layer. Different openings can intersect the void. A liner layer can substantially block the void, substantially preventing subsequently forming an electrical leakage path along the void. In one aspect, a stressor layer can... Agent: Larson Newman Abel Polansky & White, LLP

20080272493 - Semiconductor device: A semiconductor device is disclosed. The device includes a substrate, a first porous SiCOH dielectric layer, a second porous SiCOH dielectric layer, and an oxide layer. The first porous SiCOH dielectric layer overlies the substrate. The second porous SiCOH dielectric layer overlies the first porous SiCOH dielectric layer. The oxide... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080272494 - Semiconductor device: A semiconductor device is provided, including: a first barrier metal film provided by a PVD process in a recess formed in at least one insulating film, and containing at least one metal element belonging to any of the groups 4-A, 5-A, and 6-A; a second barrier metal film continuously provided... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080272495 - Semiconductor device having high-frequency interconnect: Provided is a semiconductor device including high-frequency interconnect and dummy conductor patterns (second dummy conductor patterns). The dummy conductor patterns are disposed in a interconnect layer different from a interconnect layer in which the high-frequency interconnect is disposed. The dummy conductor patterns are disposed so as to keep away from... Agent: Young & Thompson

20080272498 - Method of fabricating a semiconductor device: A method for fabricating a semiconductor device. A preferred embodiment comprises forming a via in a semiconductor substrate, filling the via with a disposable material such as amorphous carbon, forming a dielectric layer on the substrate covering the via, performing a back side etch to expose the disposable material in... Agent: Slater & Matsil, L.L.P.

20080272497 - Methods of forming conductive vias through substrates, and structures and assemblies resulting therefrom: Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a... Agent: Trask Britt, P.C./ Micron Technology

20080272496 - Planar interconnect structure for hybrid circuits: Described herein is an electronic device in which one or more planar interconnect structure are interposed between two substrates each incorporating a hybrid circuit. The planar interconnect structure has a plurality of conductive traces formed on one of its faces for electrically connecting sets of interconnection points of each of... Agent: Schwegman, Lundberg & Woessner, P.A.

20080272499 - Through-wafer vias: A through-wafer via interconnect region is in a circuit portion of a wafer, the circuit portion including at least one electrically conducting metal layer and configured for use, after dicing of the wafer, as one of a plurality of layers stacked vertically to form a three dimensional integrated circuit. Within... Agent: Koppel, Patrick & Heybl

20080272500 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device according to the present invention has a semiconductor chip provided with an insulating layer formed so as to be thinner in a first secondary-wire-free area than in a first secondary-wire-containing area. Further, the semiconductor chip has an edge extending further outward than a side wall, which severs... Agent: Nixon & Vanderhye, PC

20080272501 - Semiconductor package substrate structure and manufacturing method thereof: A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating... Agent: Schmeiser Olsen & Watts

20080272502 - Packaging board and manufacturing method therefor, semiconductor module and manufacturing method therefor, and portable device: A method for manufacturing a semiconductor module includes: a first process of forming a conductor on one face of an insulating layer; a second process of exposing the conductor from the other face of the insulating layer; a third process of providing a first wiring layer on an exposed area... Agent: Mcdermott Will & Emery LLP

20080272503 - Semiconductor device and method for making same: A transfer mold process for encapsulation of a matrix array package of dice on a substrate is proposed wherein the flow of the mold compound between dice is at least partly obstructed. In other words, the flow velocity of the mold compound between dice is constrained with the goal of... Agent: Slater & Matsil, L.L.P.

20080272504 - Package-in-package using through-hole via die on saw streets: A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects... Agent: Quarles & Brady LLP