Active solid-state devices (e.g., transistors, solid-state diodes) inventions 10/08

20080258125 - Resistive memory cell fabrication methods and devices: A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current... Agent: Dickstein Shapiro LLP

20080258126 - Memory cell sidewall contacting side electrode: A memory cell includes a memory cell layer over a memory cell access layer. The memory cell access layer comprises a bottom electrode. The memory cell layer comprises a dielectric layer and a side electrode at least partially defining a void with a memory element therein. The memory element comprises... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080258128 - Phase-changeable memory devices: A phase-changeable memory device includes a substrate having a contact region on an upper surface thereof. An insulating interlayer on the substrate has an opening therein, and a lower electrode is formed in the opening. The lower electrode has a nitrided surface portion and is in electrical contact with the... Agent: Myers Bigel Sibley & Sajovec

20080258127 - Precursor, thin layer prepared including the precursor, method of preparing the thin layer and phase-change memory device: A Te precursor containing Te, a 15-group compound (for example, N) and/or a 14-group compound (for example, Si), a method of preparing the Te precursor, a Te-containing chalcogenide thin layer including the Te precursor, a method of preparing the thin layer; and a phase-change memory device. The Te precursor may... Agent: Harness, Dickey & Pierce, P.L.C

20080258129 - Phase-change memory device: A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258130 - Beveled led chip with transparent substrate: A light emitting diode is disclosed that includes a transparent (and potentially low conductivity) silicon carbide substrate, an active structure formed from the Group III nitride material system on the silicon carbide substrate, and respective ohmic contacts on the top side of the diode. The silicon carbide substrate is beveled... Agent: Summa, Allan & Additon, P.A.

20080258131 - Light emitting diode: The present invention relates to a light emitting diode. More specifically, the present invention relates to a light emitting diode comprising an N-type semiconductor layer formed on a substrate, an active layer formed on the N-type semiconductor layer and a P-type semiconductor layer formed on the active layer, wherein the... Agent: Marger Johnson & Mccollom, P.C.

20080258132 - Quantum dot optoelectronic device having an sb-containing overgrown layer: A quantum dot optoelectronic device has an overgrown layer containing antimony (Sb). The optical characteristics and thermal stability of the optoelectronic device are thus greatly enhanced due to the improved crystal quality and carrier confinement of the quantum dot structure.... Agent: Troxell Law Office PLLC

20080258133 - Semiconductor device and method of fabricating the same: Disclosed is a semiconductor device. The semiconductor device includes a first type nitride-based cladding layer formed on a growth substrate having an insulating property, a multi quantum well nitride-based active layer formed on the first type nitride-based cladding layer and a second type nitride-based cladding layer, which is different from... Agent: Cantor Colburn, LLP

20080258134 - Method for making a semiconductor device including shallow trench isolation (sti) regions with maskless superlattice deposition following sti formation and related structures: A semiconductor device may include a semiconductor substrate having a surface, a shallow trench isolation (STI) region in the semiconductor substrate and extending above the surface thereof, and a superlattice layer adjacent the surface of the semiconductor substrate and comprising a plurality of stacked groups of layers. More particularly, each... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080258135 - Semiconductor structure having plural back-barrier layers for improved carrier confinement: A semiconductor structure having: a channel layer having a conductive channel therein; a pair of polarization generating layers; a spacer layer disposed between the pair of polarization generating layers. The polarization generating layers create polarization fields along a common, predetermined direction. Each one of the pair of polarizations layers may... Agent: Raytheon Company C/o Daly, Crowley, Mofford & Durkee, LLP

20080258136 - Logic circuit: The invention includes a two terminal switching device having two stable resistivity values for each applied voltage, which when a voltage of not more than a first threshold voltage (Vth1) is applied, becomes in a first state having a higher resistivity, whereas when a larger second threshold voltage (Vth2) or... Agent: Rabin & Berdo, PC

20080258137 - Thin film field effect transistors having schottky gate-channel junctions: An active electronic device has drain and source electrodes that make ohmic conduct with a layer of a semiconductor. The semiconductor layer may be a thin layer of an organic or amorphous semiconductor. The drain and source electrodes are on a first face of the layer of semiconductor at locations... Agent: Oyen, Wiggs, Green & Mutala LLP 480 - The Station

20080258138 - Thin film transistor array panel and fabricating method thereof, and flat panel display with the same: An organic thin film transistor array panel, for an embodiment, includes a plurality of pixel electrodes formed on a top layer to cover organic thin film transistors, with display areas defined by the areas of the pixel electrodes. Accordingly, the aperture ratio of the display device may be increased. A... Agent: Macpherson Kwok Chen & Heid LLP

20080258142 - Semiconductor device, its manufacture method and template substrate: The semiconductor device has: a ZnO-containing substrate containing Li; a zinc silicate layer formed above the ZnO-containing substrate; and a semiconductor layer epitaxially grown relative to the ZnO-containing substrate via the zinc silicate layer.... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080258139 - Structure with transistor: A structure with a transistor is disclosed comprising a substrate, a gas barrier layer on the substrate, and a transistor on the gas barrier layer. The transistor can include an oxide semiconductor layer. The oxide semiconductor layers can comprise In—Ga—Zn—O. A display, such as a liquid crystal display, can have... Agent: Squire, Sanders & Dempsey L.L.P.

20080258140 - Thin film transistor including selectively crystallized channel layer and method of manufacturing the thin film transistor: Provided are a thin film transistor (TFT) including a selectively crystallized channel layer, and a method of manufacturing the TFT. The TFT includes a gate, the channel layer, a source, and a drain. The channel layer is formed of an oxide semiconductor, and at least a portion of the channel... Agent: Harness, Dickey & Pierce, P.L.C

20080258141 - Thin film transistor, method of manufacturing the same, and flat panel display having the same: A thin film transistor (TFT), a method of manufacturing the TFT, and a flat panel display comprising the TFT are provided. The TFT includes a gate, a gate insulating layer that contacts the gate, a channel layer that contacts the gate insulating layer and faces the gate with the gate... Agent: Harness, Dickey & Pierce, P.L.C

20080258143 - Thin film transitor substrate and method of manufacturing the same: A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a first conductive pattern group including a gate electrode on a substrate, forming a gate insulating layer on the first conductive pattern group, forming a semiconductor layer and an ohmic contact layer on the gate insulating layer by... Agent: Cantor Colburn, LLP

20080258144 - Semiconductor wafer, semiconductor chip and method of manufacturing semiconductor chip: A semiconductor wafer of the present invention is provided with a substrate having a semiconductor element formation layer, a lowermost metal layer formed on the semiconductor element formation layer and an uppermost layer formed on the lowermost metal layer, and the semiconductor wafer also has plural chip regions and an... Agent: Volentine & Whitt PLLC

20080258145 - Semiconductor devices including an amorphous region in an interface between a device isolation layer and a source/drain diffusion layer: Semiconductor devices and methods for fabricating the same are disclosed in which an amorphous layer is formed in an interface between a device isolation layer and a source or drain region to stably thin a silicide layer formed in the interface. A leakage current of the silicide layer formed in... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080258146 - Thin-film transistor and fabrication method thereof: A fabrication method of a TFT includes successively forming four thin films containing a first conductive layer, an insulation layer, a semiconductor layer, and a second conductive layer on a substrate, performing a first PEP process to pattern the four thin films for forming a semiconductor island and a gate... Agent: North America Intellectual Property Corporation

20080258147 - Semiconductor device forming method: In thin film transistors (TFTs) having an active layer of crystalline silicon adapted for mass production, a catalytic element is introduced into doped regions of an amorphous silicon film by ion implantation or other means. This film is crystallized at a temperature below the strain point of the glass substrate.... Agent: Nixon Peabody, LLP

20080258149 - Liquid crystal display and panel therefor: A thin film transistor array panel according to an embodiment of the present invention includes: a gate line; a data line intersecting the gate line; a thin film transistor connected to the gate line and the data line; a pixel electrode connected to the thin film transistor; and a shielding... Agent: F. Chau & Associates, LLC

20080258148 - Thin film transistor and organic electroluminescence display using the same: In a thin film transistor, a semiconductor layer containing Si and Ge is applied, a Ge concentration of this semiconductor layer is high at the side of the insulating substrate, and crystalline orientation of the semiconductor layer indicates a random orientation in a region of 20 nm from the side... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080258151 - Light emitting device and method for manufacturing the same: Disclosed are a light emitting device and a method for manufacturing the same. A light emitting diode comprises a plurality of Un-GaN layers and a plurality of N-type semiconductor layers, an active layer on the N-type semiconductor layer, and a P-type semiconductor layer on the active layer, wherein at least... Agent: Birch Stewart Kolasch & Birch

20080258150 - Method to fabricate iii-n field effect transistors using ion implantation with reduced dopant activation and damage recovery temperature: Structures to reduce dopant activation temperatures for ion implantation in III-N transistors, using low aluminum content layers in proximity to the conducting channel, are disclosed. A method to increase the temperature at which structures can be annealed by annealing in an active nitrogen ambient, for example, in NH3 in a... Agent: Gates & Cooper LLP Howard Hughes Center

20080258152 - Sic semiconductor device having outer periphery structure: A SiC semiconductor device includes: a SiC substrate; a SiC drift layer on the substrate having an impurity concentration lower than the substrate; a semiconductor element in a cell region of the drift layer; an outer periphery structure including a RESURF layer in a surface portion of the drift layer... Agent: Posz Law Group, PLC

20080258153 - Silcon carbide semiconductor device having schottky barrier diode and method for manufacturing the same: An SiC semiconductor device is provided, which comprises: a substrate made of silicon carbide and having a principal surface; a drift layer made of silicon carbide and disposed on the principal surface; an insulating layer disposed on the drift layer and including an opening; a Schottky electrode contacting with the... Agent: Posz Law Group, PLC

20080258154 - Semiconductor device manufacturing method and display device: Disclosed herein is a semiconductor device manufacturing method for performing an annealing process of irradiating a semiconductor film on which element forming areas including thin film transistor forming areas are arranged in a two-dimensional pattern with energy beams using a plurality of irradiating optical systems, wherein in the annealing process,... Agent: Sonnenschein Nath & Rosenthal LLP

20080258155 - Semiconductor device, optical measuring and detecting device, and method of manufacturing the same: Disclosed is a semiconductor device which is capable of preventing operation of the signal processing part from being unstable due to light not blocked by the light blocking layer by being obliquely incident on the signal processing part and preventing the operation of the signal processing part from being unstable... Agent: Taft, Stettinius & Hollister LLP

20080258158 - Light emission device: A light emission device includes a plurality of semiconductor light emitting elements and a supporting substrate on which the plurality of semiconductor light emitting elements are flip-chip mounted. Each of the plurality of semiconductor light emitting elements has a substantially rectangular shape which has a first side and a second... Agent: Ditthavong Mori & Steiner, P.C.

20080258156 - Light-emitting diode apparatus: In a light-emitting diode apparatus, light emitted from a principal plane of an emission layer has a plurality of unequal luminous intensities depending on the in-plane azimuth angle of the principal plane of the emission layer, and at least one of a light-emitting diode chip and a package has a... Agent: Ditthavong Mori & Steiner, P.C.

20080258157 - Packaging method of led of high heat-conducting efficiency and structure thereof: A packaging method of LED of high heat-conducting efficiency and a structure thereof firstly is to provide a copper substrate having a plurality of indentations. An insulating layer is formed on the surface of the substrate and the bottom of the indentations. Meanwhile, a set of metallic circuits is formed... Agent: Hdsl

20080258159 - Method for preparing metal phosphide nanocrystal from phosphite compound and method for passivating nanocrystal core with the same: Disclosed herein is a method for the preparation of metal phosphide nanocrystals using a phosphite compound as a phosphorous precursor. More specifically, disclosed herein is a method for preparing metal phosphide nanocrystals by reacting a metal precursor with a phosphite compound in a solvent. A method is also provided for... Agent: Cantor Colburn, LLP

20080258160 - Led device comprising thin-film phosphor having two dimensional nano periodic structures: Disclosed herein is an LED device which comprises a light-emitting diode (LED) and a laminate formed on the LED, the laminate consisting of a substrate and a phosphor thin film laminated on the substrate, wherein the phosphor thin film has a two-dimensional nanoperiodic structure formed in a forward direction of... Agent: Christie, Parker & Hale, LLP

20080258164 - Light emitting device: Light emitting device 1 includes an LED chip 10, a mounting substrate 20 carrying the LED chip, a dome-shaped color conversion member 70, and encapsulation member 50. Color conversion member 70 is molded from a transparent resin material and a fluorescent material which is excited by a light emitted from... Agent: Cheng Law Group, PLLC

20080258165 - Light emitting diode chip: A substrate-free LED chip has a multilayer semiconductor structure at least 10 microns thick provided on a growth substrate. One or more arrays of parallel streets are etched into the multilayer semiconductor structure using a first pulsed laser beam. By scanning a second pulsed laser beam through the growth substrate... Agent: Goldeneye, Inc.

20080258162 - Package for a high-power light emitting diode: A package for a high-power light emitting diode (LED) has a packaging substrate, at least one LED chip, at least one pair of conductive wires and an encapsulant. The packaging substrate has a reflective base with a recess, a dissipating board and at least one pair of electrodes. The electrodes... Agent: Hershkovitz & Associates, LLC

20080258163 - Semiconductor light-emitting device with high light-extraction efficiency: The invention discloses a semiconductor light-emitting device and a fabricating method thereof. The semiconductor light-emitting device according to the invention includes a substrate, a multi-layer structure, a top-most layer, and at least one electrode. The multi-layer structure is formed on the substrate and includes a light-emitting region. The top-most layer... Agent: Birch Stewart Kolasch & Birch

20080258161 - Transparent ohmic contacts on light emitting diodes with carrier substrates: A light emitting diode is disclosed that includes an active structure formed of at least p-type and n-type epitaxial layers of Group III nitride on a conductive carrier substrate. A conductive bonding system joins the active structure to the conductive carrier substrate. A first transparent ohmic contact is on the... Agent: Summa, Allan & Additon, P.A.

20080258170 - Light emitting diode structure: The light emitting diode structure includes a substrate, a first electricity semiconductor layer formed on the substrate, a light-emitting layer formed on the first electricity semiconductor layer, a second electricity semiconductor layer formed on the light-emitting layer, a barrier layer formed on the second electricity semiconductor layer, and a contact... Agent: Raymond R. Moser Jr., Esq. MoserIPLaw Group

20080258167 - Package structure for light-emitting elements: The present invention discloses a package structure for light-emitting elements, wherein a horizontally-extending thermal conductive plate contacts a thermal conductive substrate having a larger heat-dissipating area. Via such a horizontal heat-dissipation mechanism, the heat generated by light-emitting elements is dissipated at a higher rate; thereby, the light-emitting elements have a... Agent: Sinorica, LLC

20080258166 - Semiconductor light emitting device and method for manufacturing the same: There is provided a semiconductor light emitting semiconductor device including an n-side electrode which has a structure capable of stably suppressing the contact resistance between the n-side electrode and a nitride semiconductor layer. Further, there is provided a light emitting device and a manufacturing method wherein an ohmic contact between... Agent: Rabin & Berdo, PC

20080258168 - Semiconductor light emitting device packages and methods: A submount for a light emitting device package includes a rectangular substrate. A first bond pad and a second bond pad are on a first surface of the substrate. The first bond pad includes a die attach region offset toward a first end of the substrate and configured to receive... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080258169 - Substrate for mounting light emitting element, light emitting module and lighting apparatus: A substrate for mounting light emitting elements having two or more conductive layers and an insulating layer provided between each conductive layer, which are formed on the outside of an enameled substrate, the enameled substrate being an enamel layer covering the surface of a core metal. The conductive layer provided... Agent: Sughrue Mion, PLLC

20080258171 - Semiconductor light emitting device excellent in heat radiation: A semiconductor light emitting device is provided which comprises: a semiconductor light emitting chip 2 mounted on a top surface 12 of a support plate 1, wiring conductors 3 disposed adjacent to side surfaces 11 of support plate 1, and a plastic encapsulant 6 for sealing side surfaces 11 of... Agent: Bachman & Lapointe, P.C.

20080258172 - Insulated gate bipolar transistor with built-in freewheeling diode: An insulated gate bipolar transistor includes a first main electrode on a first main surface and in contact with a base region of an insulated gate transistor at the first main surface, a first semiconductor layer of a first conductivity type on a second main surface, a second semiconductor layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258173 - Vertical p-n junction device and method of forming same: A P-N junction device and method of forming the same are disclosed. The P-N junction device may include a P-N diode, a PiN diode or a thyristor. The P-N junction device may have a monocrystalline or polycrystalline raised anode. In one embodiment, the P-N junction device results in a raised... Agent: Hoffman Warnick LLC

20080258174 - Optical device and method of fabricating the same: Disclosed is an optical device including an optical member and a contact layer stacked on at least one of top and bottom surfaces of the optical member. The contact layer has at least one transparent conducting oxynitride (TCON) layer. The TCON consists of at least one of indium (In), tin... Agent: Macpherson Kwok Chen & Heid LLP

20080258175 - Stressed mos device: A stressed MOS device is provided that includes a silicon substrate, a gate electrode and an epitaxial layer of stress inducing monocrystalline semiconductor material. The silicon substrate is characterized by a monocrystalline silicon lattice constant. The gate electrode overlies a silicon channel region at the surface of the silicon substrate.... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080258176 - Antimonide-based compound semiconductor with titanium tungsten stack: An apparatus in one example comprises an antimonide-based compound semiconductor (ABCS) stack, an upper barrier layer formed on the ABCS stack, and a gate stack formed on the upper barrier layer. The upper barrier layer comprises indium, aluminum, and arsenic. The gate stack comprises a base layer of titanium and... Agent: Patti, Hewitt & Arezina LLC

20080258177 - method of manufacturing a semiconductor device and a semiconductor device: Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080258178 - Method of forming a mos transistor: A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region,... Agent: North America Intellectual Property Corporation

20080258179 - Hybrid molecular electronic device for switching, memory, and sensor applications, and method of fabricating same: A hybrid molecular electronic device having switching, memory, and sensor application is disclosed. In one embodiment, the device resembles a conventional field-effect transistor (FET) formed on a silicon-on-insulator (SOI) substrate. Source and drain doped regions are formed in an upper surface of the SOI substrate, and a metallization layer which... Agent: Winstead PC

20080258180 - Cross-section hourglass shaped channel region for charge carrier mobility modification: A semiconductor structure and a method for fabricating the semiconductor structure include a semiconductor substrate having a cross-section hourglass shaped channel region. A stress imparting layer is located adjacent the channel region. The hourglass shape may provide for enhanced vertical tensile stress within the channel region when it is longitudinally... Agent: Scully Scott Murphy & Presser, PC

20080258181 - Hybrid substrates and methods for forming such hybrid substrates: Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one of the different crystal orientations into mutually aligned device and... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080258182 - Bicmos compatible jfet device and method of manufacturing same: A BiCMOS-compatible JFET device comprising source and drain regions (17, 18) which are formed in the same process as that used to form the emitter out-diffusion or a vertical bipolar device, wherein the semiconductor layer which forms the emitter cap in the bipolar device forms the channel (16) of the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080258183 - Method of manufacturing a device by locally heating one or more metallization layers and by means of selective etching: A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that... Agent: Maginot, Moore & Beck Chase Tower

20080258184 - Normally-off integrated jfet power switches in wide bandgap semiconductors and methods of making: Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single- or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant... Agent: Morris Manning Martin LLP

20080258185 - Semiconductor structure with dielectric-sealed doped region: Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are... Agent: Slater & Matsil, L.L.P.

20080258186 - Source and drain formation in silicon on insulator device: A silicon on insulator device has a silicon layer (10) over a buried insulating layer (12). A nickel layer is deposited over a gate (16), on sidewall spacers (22) on the sides of the gate (16), and in a cavity on both sides of the gate (16) in the silicon... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080258189 - Image sensor and method of manufacturing the same: An image sensor and a method of manufacturing the same are provided. The image sensor includes a semiconductor substrate, a metal line layer, a first conduction type conducting layer, a first pixel isolation layer, an intrinsic layer, and second conduction type conducting layer. The semiconductor substrate includes a circuit region.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080258188 - Metal oxide semiconductor device and method of fabricating the same: A method of fabricating an MOS device is provided. First, gates and source/drain regions of transistors are formed on a substrate. A photodiode doped region and a floating node doped region are formed in the substrate. Thereafter, a spacer stacked layer including a bottom layer, an inter-layer and a top... Agent: J C Patents, Inc.

20080258187 - Methods, systems and apparatuses for the design and use of imager sensors: An imager sensor cell design having readout circuitry contained within the photodiode region.... Agent: David J. Paul Mail Stop 1-525

20080258190 - Solid-state image sensing device and camera system using the same: A solid-state image sensing device includes a plurality of pixels. Each pixel has a photodiode, a first transistor, and a second transistor. The photodiode is constituted by a first-conductivity-type semiconductor region and a second-conductivity-type semiconductor region. The first and second conductivity types are opposite to each other. The first transistor... Agent: Fitzpatrick Cella Harper & Scinto

20080258191 - Capacitor device providing sufficient reliability: A capacitor device includes a dielectric layer configured to have a composition represented as (Ba1-x, Srx)Ti1-zScyO3+δ (0<x<1, 0.01<z<0.3, 0.005<y<0.02, −0.5<δ<0.5) and an in-plane deformation ∈ of crystal that satisfies −0.4<<0.4, an upper electrode and a lower electrode that are placed on respective sides of the dielectric layer, and a substrate... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080258193 - Ferroelectric memory and method of manufacturing the same: A ferroelectric memory that stores information by using a hysteresis characteristic of a ferroelectric, has a semiconductor substrate; a lower electrode formed above said semiconductor substrate; a ferroelectric film formed on said lower electrode; and an upper electrode formed on said ferroelectric film, wherein said upper electrode includes an AOx-type... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080258194 - Flip feram cell and method to form same: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric... Agent: Scully, Scott, Murphy & Presser, P.C.

20080258192 - Semiconductor device and manufacturing method thereof: This disclosure concerns a semiconductor device comprising an insulating film provided on a semiconductor substrate; a lower contact formed in the insulating film; a ferroelectric capacitor including a first lower electrode provided on the lower contact and connected to the lower contact, a second lower electrode provided on the first... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080258195 - Semiconductor device and method of manufacturing the same: A ferroelectric capacitor is formed above a semiconductor substrate (1), and thereafter, wirings (24a) are formed. A barrier film (25) covering the wirings (24a) is formed. A silicon oxide film (26) embedding gaps between the adjacent wirings (24a) is formed. The silicon oxide film (26) is polished until a surface... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080258196 - Semiconductor structure of a display device and method for fabricating the same: A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080258197 - Semiconductor-insulator-silicide capacitor: A semiconductor-insulator-silicide (SIS) capacitor is formed by depositing a thin silicon containing layer on a salicide mask dielectric layer, followed by lithographic patterning of the stack and metallization of the thin silicon containing layer and other exposed semiconductor portions of a semiconductor substrate. The thin silicon containing layer is fully... Agent: Scully, Scott, Murphy & Presser, P.C.

20080258198 - Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for cmos: s

20080258199 - Flash memory device and fabricating method thereof: A new device structure according to the present invention is compatible with existing fabrication process and is based on a recessed channel, which is capable of easily implementing highly-integrated/high-performance and 2-bit/cell. The proposed device has a structure suppressing the short channel effect while largely reducing the cell area and enabling... Agent: Greenblum & Bernstein, P.L.C

20080258200 - Memory cell having a shared programming gate: A semiconductor memory device includes a substrate, and a trench formed in the substrate. First and second floating gates, each associated with corresponding first and second memory cells, extend into the trench. Since the trench can be made relatively deep, the floating gates may be made relatively large while the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080258202 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a semiconductor substrate having a first trench, an element isolation insulating film, a floating gate electrode, a second gate insulating film and a control gate electrode. The element isolation insulating film includes a sidewall having such a height as to be in contact with... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258201 - Semiconductor memory device and method of manufacturing the same: A manufacturing method of a semiconductor memory device for manufacturing a first semiconductor device and a second semiconductor device wherein a cell array ratio is smaller than that of the first semiconductor device, said manufacturing method has forming the height of first element-isolating insulating films of first memory cell array... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258204 - Memory structure and operating method thereof: A memory structure including a substrate, a charge trapping layer, a block layer, a conducting layer and two doped regions is provided in the present invention. The charge trapping layer is disposed on the substrate. The block layer is disposed on the charge trapping layer. The conducting layer is disposed... Agent: J C Patents, Inc.

20080258205 - Non-volatile semiconductor memory device: An erase current of a non-volatile semiconductor memory device is decreased. A memory cell of the non-volatile semiconductor memory device comprises a source region and a drain region formed in a semiconductor substrate. Over a portion of the semiconductor substrate between the source region and the drain region, a select... Agent: Miles & Stockbridge PC

20080258203 - Stacked sonos memory: An integrated circuit includes a first SONOS memory cell and a second SONOS memory cell. The second memory cell is stacked on the first memory cell.... Agent: Dicke, Billig & Czaja

20080258207 - Block contact architectures for nanoscale channel transistors: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080258206 - Self-aligned gate structure, memory cell array, and methods of making the same: A self-aligned gate structure includes a first gate region and a second gate region. The first gate region extends in semiconductor substrate portions to a lesser depth than in isolation trenches that are adjacent to the semiconductor substrate portions. The first gate region comprises a first conductive material. The second... Agent: Edell, Shapiro & Finnan, LLC

20080258208 - Semiconductor component including compensation zones and discharge structures for the compensation zones: A semiconductor component including compensation zones and discharge structures for the compensation zones. One embodiment provides a drift zone of a first conduction type, at least one compensation zone of a second conduction type, complementary to the first conduction type, the at least one compensation zone being arranged in the... Agent: Dicke, Billig & Czaja

20080258209 - Semiconductor device and manufaturing method thereof: A semiconductor device comprises a plurality of semiconductor pillars laid out in matrix in a first and a second directions parallel with a main surface of a semiconductor substrate, and extending to a direction substantially perpendicular to the main surface; gate insulating films covering each surface of the plurality of... Agent: Sughrue Mion, PLLC

20080258210 - Semiconductor component and method of manufacture: A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in... Agent: Mr. Jerry Chruma Semiconductor Components Industries, L.L.C.

20080258211 - Semiconductor device and method for manufacturing the same: In a MIS-type semiconductor device having a trench gate structure, a withstand voltage is ensured without changing the thickness of a drift layer and on-resistance can be reduced without applying a high gate drive voltage. The lower half of a trench extending through a p-base region into an n-drift region... Agent: Rossi, Kimms & Mcdowell LLP.

20080258213 - Shielded gate field effect transistor: A FET includes a trench in a semiconductor region. The trench has a lower portion with a shield electrode therein, and an upper portion with a gate electrode therein, where the upper portion is wider than the lower portion. The semiconductor region includes a substrate of a first conductivity type... Agent: Townsend And Townsend And Crew, LLP

20080258212 - Trench metal oxide semiconductor with recessed trench material and remote contacts: Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20080258214 - Semiconductor device and method of fabricating the same: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can provide a trench MOS transistor having an up-drain structure. The semiconductor device can include a first conductive type well in a semiconductor substrate, a second conductive type well on the first conductive type... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080258215 - Ldmos device: An LDMOS transistor comprises source, channel and extended drain regions. The extended drain region comprises a plurality of islands that have a conductivity type that is opposite to the extended drain region. The islands have a depth less than a depth of the extended drain region.... Agent: Coats & Bennett/infineon Technologies

20080258216 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a field effect transistor including a semiconductor substrate having a channel-forming region, an insulating film formed on the semiconductor substrate, a gate electrode trench formed in the insulating film, a gate insulating film formed at the bottom of the gate electrode trench, a gate electrode formed... Agent: Sonnenschein Nath & Rosenthal LLP

20080258218 - Semiconductor device and method of manufacturing the same: A MIS transistor having an inclined stacked source/drain structure increased in speed is provided. The MIS transistor comprises: a gate electrode formed on a substrate; a first sidewall insulating film formed on the substrate and along a sidewall of the gate electrode; source/drain semiconductor regions formed on a main surface... Agent: Miles & Stockbridge PC

20080258217 - Semiconductor device structure for anti-fuse: The present invention discloses a semiconductor device, the device comprising a semiconductor layer on a substrate. A gate oxide and a gate electrode are formed on the semiconductor substrate. A gate conductive layer is formed on the gate electrode. A first doped region is formed in the semiconductor layer. A... Agent: Birch Stewart Kolasch & Birch

20080258220 - Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors: This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for... Agent: Scully, Scott, Murphy & Presser, P.C.

20080258219 - Method to selectively modulate gate work function through selective ge condensation and high-k dielectric layer: A semiconductor device is provided which comprises a semiconductor layer (109), a dielectric layer (111), first and second gate electrodes (129, 131) having first and second respective work functions associated therewith, and a layer of hafnium oxide (113) disposed between said dielectric layer and said first and second gate electrodes.... Agent: Fortkort & Houston P.C.

20080258221 - Substrate solution for back gate controlled sram with coexisting logic devices: A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level... Agent: Scully, Scott, Murphy & Presser, P.C.

20080258222 - Design structure incorporating a hybrid substrate: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes devices formed in a hybrid substrate characterized by semiconductor islands of different crystal orientations. An insulating layer divides the islands of at least one of the different crystal orientations... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080258223 - Esd protection device: An ESD protection device is provided. The ESD protection device of the present invention includes a semiconductor substrate/well, a first doped region, a second doped region and a third doped region. The first doped region doped with a first dopant is disposed in the semiconductor substrate/well. The second doped region... Agent: J C Patents, Inc.

20080258224 - Trenched mosfets with improved gate-drain (gd) clamp diodes: A MOSFET device that includes a first Zener diode connected between a gate metal and a drain metal of said semiconductor power device for functioning as a gate-drain (GD) clamp diode. The GD clamp diode includes multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a... Agent: Bo-in Lin

20080258225 - Mos transistors having high-k offset spacers that reduce external resistance and methods for fabricating the same: MOS transistors having high-k spacers and methods for fabricating such transistors are provided. One exemplary method comprises forming a gate stack overlying a semiconductor substrate and forming an offset spacer about sidewalls of the gate stack. The offset spacer is formed of a high-k dielectric material that results in a... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080258226 - Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material: Methods for manufacturing trench type semiconductor devices containing thermally unstable refill materials are provided. A disposable material is used to fill the trenches and is subsequently replaced by a thermally sensitive refill material after the high temperature processes are performed. Trench type semiconductor devices manufactured according to method embodiments are... Agent: Panitch Schwarze Belisario & Nadel LLP

20080258228 - Contact scheme for mosfets: A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a contact extending from a top surface of the first ILD into the first ILD; a second ILD over the first ILD; a... Agent: Slater & Matsil, L.L.P.

20080258229 - Semiconductor device and method for fabricating the same: A semiconductor device includes an N-type MOS transistor and a P-type MOS transistor. The N-type MOS transistor has a first gate insulating film and a first gate electrode. The P-type MOS transistor has a second gate insulating film and a second gate electrode. The first gate insulating film and the... Agent: Mcdermott Will & Emery LLP

20080258230 - Semiconductor device and method for manufacturing the same: There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258227 - Strained spacer design for protecting high-k gate dielectric: A semiconductor device pair is provided. The semiconductor device pair comprises a semiconductor substrate comprising a first gate structure with a first type polarity and a second gate structure with a second type polarity, the first and the second gate structures comprise a high-K gate dielectric. A plurality of oxygen-free... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080258231 - Semiconductor device: A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter... Agent: Ditthavong Mori & Steiner, P.C.

20080258232 - Semiconductor device and method for producing the same: A semiconductor device includes a substrate, an insulating film disposed on the substrate, a resistor groove disposed in the insulating film, and a resistor disposed in the resistor groove. The resistor is separated from all side surfaces of the resistor groove by a predetermined distance.... Agent: Sonnenschein Nath & Rosenthal LLP

20080258233 - Semiconductor device with localized stressor: A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped... Agent: Slater & Matsil, L.L.P.

20080258235 - Manufacturing method of semiconductor device and semiconductor device: A gate insulating film and a gate electrode of an nMOS transistor are laminated and formed in this order on a semiconductor substrate. A source/drain region of the nMOS transistor is formed in the upper surface of the semiconductor substrate. The source/drain region is silicided after siliciding all the regions... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258234 - Semiconductor structure for low parasitic gate capacitance: A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride... Agent: Scully, Scott, Murphy & Presser, P.C.

20080258236 - Method of manufacturing a semiconductor device: With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080258237 - Semiconductor device having multi-channel and method of fabricating the same: An embodiment of the present invention relates to a semiconductor device having a multi-channel and a method of fabricating the same. In an aspect, the semiconductor device includes a semiconductor substrate in which isolation layers are formed, a plurality of trenches formed within an active region of the semiconductor substrate,... Agent: Lowe Hauptman Ham & Berner, LLP

20080258239 - Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material: Methods for manufacturing trench type semiconductor devices involve refilling the trenches after high temperature processing steps are performed. The methods allow thermally unstable materials to be used as refill materials for the trenches of the device. Trench type semiconductor devices containing thermally unstable refill materials are also provided. In particular,... Agent: Panitch Schwarze Belisario & Nadel LLP

20080258238 - Semiconductor device manufactured using an oxygenated passivation process during high density plasma deposition: In one aspect, the method comprises forming trenches in a semiconductor substrate and filling the trenches with a dielectric material. The process of filling the trenches includes depositing the dielectric material with a plasma gas mixture, etching the dielectric material with a chemical etch including nitrogen fluoride and using a... Agent: Texas Instruments Incorporated

20080258240 - Integrated circuits and interconnect structure for integrated circuits: An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with respective ones of the N plane-like metal layers, where M is an integer greater than one, wherein the first plane-like metal layer and the N plane-like metal layers are located... Agent: Harness, Dickey & Pierce P.L.C

20080258241 - Integrated circuits and interconnect structure for integrated circuits: An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively. The first source region is arranged between first sides of the first and second drain regions and the second and third source regions are... Agent: Harness, Dickey & Pierce P.L.C

20080258243 - Field effect transistor: A field effect transistor includes: a first nitride semiconductor layer having a plane perpendicular to a (0001) plane or a plane tilted with respect to the (0001) plane as a main surface; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider bandgap than... Agent: Mcdermott Will & Emery LLP

20080258242 - Low contact resistance ohmic contact for a high electron mobility transistor and fabrication method thereof: A semiconductor device (100) is formed on a semi-insulating semiconductor substrate (101) including a channel layer (104), a spacer layer (105), an electron supply layer (106), and a barrier layer (108). A composite layer (110) is formed over the barrier layer (108). A metal (116) is deposited over the composite... Agent: Posz Law Group, PLC

20080258245 - Semiconductor constructions and transistor gates: One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined... Agent: Wells St. John P.s.

20080258244 - Semiconductor device: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate, a gate dielectric layer provided on the semiconductor substrate, a source region provided in the semiconductor substrate, a drain region provided in the semiconductor substrate, and a gate electrode provided on the gate dielectric layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258246 - Passive electrically testable acceleration and voltage measurement devices: Acceleration and voltage measurement devices and methods of fabricating acceleration and voltage measurement devices. The acceleration and voltage measurement devices including an electrically conductive plate on a top surface of a first insulating layer; a second insulating layer on a top surface of the conductive plate, the top surface of... Agent: Schmeiser, Olsen & Watts

20080258247 - Spin-transfer mram structure and methods: A spin-transfer MRAM bit includes a free magnet layer positioned between a pair of spin polarizers, wherein at least one of the spin polarizers comprises an unpinned synthetic antiferromagnet (SAF). The SAF may include two antiparallel fixed magnet layers separated by a coupling layer. To improve manufacturability, the layers of... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080258249 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same improve photosensitivity by imparting a color filter layer with the function of a microlens layer. The CMOS image sensor includes a semiconductor substrate; a plurality of photo-sensing elements formed in the semiconductor substrate; and a color filter layer comprised... Agent: Mckenna Long & Aldridge LLP

20080258248 - Image sensor and method for manufacturing the same: An image sensor and a method for manufacturing the same are provided. A photodiode region and transistor region are vertically-integrated to improve the fill factor and resolution of the image sensor. Unit pixels can be isolated by a metal isolation layer arranged between adjacent photodiode areas.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080258250 - Solid-state image capturing device, method of manufacturing the same, and electronic information device: A solid-state image capturing device is provided, in which a multilayered wiring section having a plurality of wiring layers laminated via respective interlayer insulation films is provided on a semiconductor substrate or a semiconductor region formed on the substrate where a plurality of light receiving sections for photoelectrically converting a... Agent: Edwards Angell Palmer & Dodge LLP

20080258251 - Image sensor: An image sensor including a second line formed at an upper part of a photodiode region as a transparent electrode for passing light. The second line is composed of a polymeric material having transparency and conductivity.... Agent: Sherr & Vaughn, PLLC

20080258252 - Circuit arrangement having a free-wheel diode: An object of the present invention is to reduce the conducting loss of an existing conversion circuit while suppressing its noise. The present invention is typically a circuit arrangement includes at least one switching device and a free-wheel diode connected in parallel with the switching device. The free-wheel diode is... Agent: Miles & Stockbridge PC

20080258253 - Integrated microprocessor system for safety-critical regulations: Disclosed is an integrated circuit arrangement for safety-critical applications, such as for regulating and controlling tasks in an electronic brake system for motor vehicles. The arrangement includes several electronic, cooperating functional groups (25, 25′), with electric lines (30) provided to interconnect the functional groups (25, 25′). The functional groups consist... Agent: Craig Hallacher Continental Teves, Inc.

20080258254 - Process for realizing an integrated electronic circuit with two active layer portions having different crystal orientations: A process for realizing an integrated electronic circuit makes it possible to obtain transistors with p-type conduction and transistors with n-type conduction, in respective active zones having crystal orientations adapted to each conduction type. In addition, each active zone is electrically insulated from a primary substrate of the circuit, so... Agent: Seed Intellectual Property Law Group PLLC

20080258255 - Electromigration aggravated electrical fuse structure: A fuse structure with aggravated electromigration effect is disclosed, which comprises an anode area overlaying a first plurality of contacts that are coupled to a positively high voltage during a programming of the fuse structure, a cathode area overlaying a second plurality of contacts that are coupled to a complementary... Agent: K & L Gates LLP

20080258256 - Semiconductor electrically programmable fuse element with amorphous silicon layer after programming and method of programming the same: A fuse link is formed between first and second terminals. The first and second terminals and fuse link have a polysilicon layer and a layer formed on the polysilicon layer and containing a metal element. At least a portion of the fuse link is an amorphous silicon layer.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258257 - Electronic device and use thereof: The integrated capacitor structure comprises a first branch with a first capacitor (60) and a second branch with a second capacitor (70). The second capacitor (70) has a higher capacitance density and a lower breakdown voltage than the first capacitor (60). The first branch has a shorter RC time constant... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080258259 - Semiconductor chip and semiconductor device: A semiconductor chip and a semiconductor device mounting the semiconductor chip capable of increasing a capacitance of a capacitor without reducing the number of signal bumps or power bumps of a package and the number of C4 solder balls of the semiconductor chip, and achieving a stable power supply with... Agent: Miles & Stockbridge PC

20080258258 - Semiconductor device: The invention provides a semiconductor device which has a capacitor element therein to achieve size reduction of the device, the capacitor element having larger capacitance than conventional. A semiconductor integrated circuit and pad electrodes are formed on the front surface of a semiconductor substrate. A second insulation film is formed... Agent: Morrison & Foerster LLP

20080258260 - Semiconductor device and method for manufacturing the same: A semiconductor device including a capacitor formed over a semiconductor substrate and including a lower electrode, a dielectric film formed over the lower electrode and an upper electrode formed over the dielectric film, an insulation film formed over the semiconductor substrate and the capacitor, and an electrode pad formed over... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080258261 - Split chip: This Invention is a design method and a system for a miniaturized silicon circuit whereby the circuit is split into two pieces. This process is known to the Inventor as a bifurcated circuit or disintegrated circuit and is titled the “Split Chip” by the Inventor. The Split Chip contemplates an... Agent: James Neil Rodgers

20080258262 - Semiconductor device with improved pads: A semiconductor device has: a circuit portion having semiconductor elements formed on a semiconductor substrate; insulating lamination formed above the semiconductor substrate and covering the circuit portion; a multilevel wiring structure formed in the insulating lamination and including wiring patterns and via conductors; and a pad electrode structure formed above... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080258263 - High current steering esd protection zener diode and method: A method of fabricating a N+/P+ zener diode where the reverse breakdown occurs in a controlled, and uniform manner leading to improved speed of operation and increase in current handling capability.... Agent: Pillsbury Winthrop Shaw Pittman LLP

20080258264 - Semiconductor device and method for manufacturing the same: Disclosed is a semiconductor device comprising a Ge semiconductor area, and an insulating film area, formed in direct contact with the Ge semiconductor area, containing metal, germanium, and oxygen.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258265 - Methods for forming an assembly for transfer of a useful layer: Methods for transferring of a useful layer from a support are described. In an embodiment, the method includes for facilitating transfer of a useful layer from a support by providing an interface in a first support to define a useful layer; and forming a peripheral recess on the first support... Agent: Winston & Strawn LLP Patent Department

20080258266 - Semiconductor device and manufacturing method thereof: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and... Agent: Mcdermott Will & Emery LLP

20080258267 - Method of producing semiconductor device and semiconductor device: A method of producing a semiconductor device which can reliably perform conductor filling to form a through hole electrode by a simple method is provided. A method of producing a semiconductor device of the present invention includes the steps of thinning a substrate from its back side in a state... Agent: Nixon & Vanderhye, PC

20080258268 - Trench structure and method of forming the trench structure: Disclosed are embodiments of an improved deep trench capacitor structure and memory device that incorporates this deep trench capacitor structure. The deep trench capacitor and memory device embodiments are formed on a semiconductor-on-insulator (SOI) wafer such that the insulator layer remains intact during subsequent deep trench etch processes and, optionally,... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080258269 - Semiconductor wafer and method for cutting the same: A semiconductor wafer and a method for cutting the same, enabling separation of the semiconductor wafer by natural cleavage planes, are disclosed. The cutting method according to an embodiment of the present invention comprises preparing a substrate including a semiconductor layer with at least one projection, formed on a predetermined... Agent: Ked & Associates, LLP

20080258270 - Mgo-based coating for electrically insulating semiconductive substrates and production method thereof: The present invention relates to a magnesium oxide-based (MgO) inorganic coating intended to electrically insulate semiconductive substrates such as silicon carbide (SiC), and to a method for producing such an insulating coating. The method of the invention comprises the steps of preparing a treatment solution of at least one hydrolysable... Agent: Brinks, Hofer, Gilson & Lione

20080258271 - Multi-dielectric films for semiconductor devices and methods of fabricating multi-dielectric films: A multi-dielectric film including at least one first dielectric film that is a composite film made of zirconium-hafnium-oxide and at least one second dielectric film that is a metal oxide film made of amorphous metal oxide. Adjacent ones of the dielectric films are made of different materials.... Agent: Myers Bigel Sibley & Sajovec

20080258272 - Etched leadframe structure: A leadframe structure is disclosed. The leadframe structure includes a first leadframe structure portion with a first thin portion and a first thick portion, where the first thin portion is defined in part by a first recess. It also includes a second leadframe structure portion with a second thin portion... Agent: Townsend And Townsend And Crew, LLP

20080258273 - Package structure with flat bumps for electronic device and method of manufacture the same: The invention discloses an ultra thin package structure of leadless electronic device and the packaging method, and includes lead support base adjacent to the chip support base; chip mounted on the chip support base; wires bonded between chip and lead support base; the molded body encapsulating the top surface and... Agent: Heslin Rothenberg Farley & Mesiti PC

20080258274 - Semiconductor package and method: A semiconductor package is disclosed. In one embodiment, the semiconductor package includes a leadframe including a chip position and a plurality of leadfingers. Each leadfinger includes a cutout in an inner edge providing a chip recess. The semiconductor package further includes a semiconductor chip located in the chip recess. The... Agent: Dicke, Billig & Czaja

20080258275 - Controlling warping in integrated circuit devices: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a... Agent: Ryan, Mason & Lewis, LLP

20080258280 - Lead frame, semiconductor device using the lead frame, and methods of manufacturing the same: Provided are a lead frame, semiconductor device, and methods of manufacturing the same. The lead frame may include a die pad having at least three pair of sides parallel with each other, and a plurality of inner leads spaced apart from a circumference of the die pad, arranged in a... Agent: Harness, Dickey & Pierce, P.L.C

20080258279 - Leadframe for leadless package, structure and manufacturing method using the same: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces... Agent: Wpat, PC Intellectual Property Attorneys

20080258276 - Non-leaded semiconductor package and a method to assemble the same: A method to assemble a non-leaded semiconductor package (1) comprises the following steps. A carrier tape (13) is attached to a metal foil (12). A plurality of leadframes (3) is formed in the metal foil (12), each leadframe (3) comprising a die pad (4) laterally surrounded by a plurality of... Agent: Dicke, Billig & Czaja

20080258278 - Partially patterned lead frames and methods of making and using the same in semiconductor packaging: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is... Agent: White & Case LLP Patent Department

20080258277 - Semiconductor device comprising a semiconductor chip stack and method for producing the same: A semiconductor device includes a semiconductor chip stack having at least one lower semiconductor chip as a base of the semiconductor chip stack, and at least one upper semiconductor chip. An insulating intermediate plate is arranged between the semiconductor chips. Connecting elements wire the semiconductor chips, the intermediate plate and... Agent: Edell , Shapiro & Finnan , LLC

20080258281 - Process for producing and apparatus for improving the bonding between a plastic and a metal: A semiconductor having a leadframe is disclosed. In one embodiment, a leadframe is disclosed to be fitted with a semiconductor chip and is to be encapsulated with a plastic compound has a metallic single-piece base body, to which an interlayer is applied. The interlayer has a surface including a matrix... Agent: Dicke, Billig & Czaja

20080258282 - Lead frame free package and method of making: A lead frame free packaged semiconductor device with an exposed heat sink is formed by die bonding the semiconductor device directly to the heat sink and bonding package leads directly to the semiconductor die, and optionally to the heat sink. In an alternative embodiment, a lead frame free packaged semiconductor... Agent: Hiscock & Barclay, LLP

20080258283 - Wiring board and semiconductor package using the same: l

20080258284 - Ultra-thin chip packaging: A packaging method involves attaching a first chip to a stable base, forming contact pads at locations on the stable base, applying a medium onto the stable base such that it electrically insulates sides of the first chip, forming electrical paths on the medium, attaching a second chip to the... Agent: Foley & Lardner LLP

20080258286 - High input/output, low profile package-on-package semiconductor system: A package-on-package system (100) has a first subsystem (191) interconnected with a second subsystem (192) by solder connectors (193). The first subsystem has an insulating, trace-laminated, sheet-like carrier (101), which is laminated (102) with an insulating trace-laminated frame (110) exposing a central portion (103) of the carrier. A first chip... Agent: Texas Instruments Incorporated

20080258287 - Semiconductor device and method of manufacturing the same: A semiconductor device includes: solder balls provided on an upper package; and pads provided on a lower package and directly connected to the solder balls, wherein at least one of the pads serves as a fiducial mark. Further, a shape of at least one of the pads is different from... Agent: Rankin, Hill & Clark LLP

20080258288 - Semiconductor device stack package, electronic apparatus including the same, and method of manufacturing the same: In a semiconductor device stack package and a method of forming the same, the package comprises: a substrate; a plurality of lower chips stacked on the substrate and having an active surface oriented in a direction toward the substrate; and at least one upper chip disposed on the lower chips... Agent: Mills & Onello LLP

20080258285 - Simplified substrates for semiconductor devices in package-on-package products: An insulating sheet-like substrate (601), which has on one surface (601a) a first patterned metal layer (605) with a first (603a) and a second (603b) array of contact pads. The pads of the first array have a first pitch center-to-center, and each pad has a first perimeter. The pads of... Agent: Texas Instruments Incorporated

20080258289 - Integrated circuit package system for package stacking: An integrated circuit package system comprising: forming an area array substrate; mounting surface conductors on the area array substrate; forming a molded package body on the area array substrate and the surface conductors; providing a step in the molded package body; and exposing a surface conductor by the step.... Agent: Law Offices Of Mikio Ishimaru

20080258290 - Semiconductor device and method for manufacturing the same: A COF which can effectively dissipate the heat by using a simple structure and its manufacturing method. A semiconductor device of COF, which is formed over the main surface of a flexible substrate having no device hole and where a semiconductor chip is mounted over the inner lead interconnection, is... Agent: Mcginn Intellectual Property Law Group, PLLC

20080258291 - Semiconductor packaging with internal wiring bus: A packaged semiconductor includes inner bond fingers, at least first and second semiconductor dies, and an interposer. The packaged semiconductor further includes wiring between the first and second semiconductor dies and the inner bond fingers, wiring between the interposer and the inner bond fingers, and wiring between the interposer and... Agent: Fitzpatrick Cella (marvell)

20080258292 - Macro-cell block and semiconductor device: The macro-cell block is a macro-cell block formed polygonal having a plurality of sides and formed in a semiconductor chip, and is characterized by comprising a signal terminal portion, a power terminal portion, and a ground terminal portion, which are connected to the outside of a semiconductor chip, wherein the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080258293 - Semiconductor device package to improve functions of heat sink and ground shield: The present invention provides a package structure and a method for forming the same. The structure comprises a substrate with contact pads and through holes filled with conducting metals for performing heat dissipation and ground shielding A chip with bonding pads is attached on the contact pad by an adhesive... Agent: The Maxham Firm

20080258294 - Heat-dissipating semiconductor package structure and method for manufacturing the same: A heat-dissipating semiconductor package structure and a method for manufacturing the same is disclosed. The method includes: disposing on and electrically connecting to a chip carrier at least a semiconductor chip and a package unit; disposing on the top surface of the package unit a heat-dissipating element having a flat... Agent: Edwards Angell Palmer & Dodge LLP

20080258295 - Self-contained cooling mechanism for integrated circuit using a reversible endothermic chemical reaction: A package for a semiconductor chip or other heat producing device has a supporting substrate to which the devices mount and electrically connect. An enclosure is formed over the heat producing devices and filled with a working fluid including a chemical compound that reacts endothermically to absorb heat produced by... Agent: Quarles & Brady LLP

20080258296 - Cut-out heat slug for integrated circuit device packaging: In a package, a heat slug, encapsulated by molding compound, encases an integrated circuit device (IC). In an example embodiment, a semiconductor package structure comprises a substrate (200) having conductive traces (235) and pad landings (265). The conductive traces have pad landings (265). An IC (230) is mounted on the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080258297 - Method of making solder pad: A method of making a solder pad includes providing a substrate having a metal layer formed on it, and applying a photo resist to the metal layer. The photo resist is patterned. A first etching operation is performed on the metal layer to form voids in the metal layer. A... Agent: Freescale Semiconductor, Inc. Law Department

20080258299 - Method of manufacturing a semiconductor device having an even coating thickness using electro-less plating, and related device: A method of manufacturing a semiconductor device includes forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity... Agent: Lee & Morse, P.C.

20080258298 - Semiconductor devices and methods of fabricating the same: Embodiments include a semiconductor device comprising: a pad formed on an insulating layer and having an electric connection region with external components; and a protective insulating layer which has an aperture for exposing the electric connection region. The protective insulating layer may include a first insulating layer and a second... Agent: Konrad Raynes & Victor, LLP

20080258300 - Wiring board manufacturing method, semiconductor device manufacturing method and wiring board: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and has a structure in which... Agent: Rankin, Hill & Clark LLP

20080258301 - Semiconductor device and manufacturing method of the same: A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring... Agent: Morrison & Foerster LLP

20080258302 - Methods of forming a denuded zone in a semiconductor wafer using rapid laser annealing: Methods for forming a denuded zone in an oxygen-containing semiconductor wafer using rapid laser annealing (RLA) are disclosed. The method includes scanning an intense beam of laser radiation over the surface of the wafer to raise the temperature of each point on the wafer surface to be at or near... Agent: Peters Verny , L.L.P.

20080258303 - Novel structure for reducing low-k dielectric damage and improving copper em performance: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a dielectric layer; a chemical mechanical polish (CMP) stop layer on the dielectric layer; a conductive wiring in the dielectric layer; and a metal cap over the conductive wiring.... Agent: Slater & Matsil, L.L.P.

20080258304 - Semiconductor device having multiple wiring layers: A semiconductor device includes: a substrate; and wiring layers on the substrate. Each wiring layer includes: an interlayer insulation film having a wiring groove with a via hole; a copper wiring in the groove and the hole; an barrier metal layer between an inner wall of the groove with the... Agent: Posz Law Group, PLC

20080258305 - Low fabrication cost, fine pitch and high reliability solder bump: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about... Agent: Mou-shiung Lin Room 301/302

20080258306 - Semiconductor device and method for fabricating the same: The present invention provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a chip having an active surface and an opposing non-active surface, wherein a plurality of bond pads are formed on the active surface, and first metal layers are formed on the bond... Agent: Wpat, PC Intellectual Property Attorneys

20080258307 - Integration type semiconductor device and method for manufacturing the same: A semiconductor device includes: a plurality of power MOS cells on a semiconductor substrate; a plurality of lead wires connecting to a source and a drain of each power MOS cell through a contact hole; a plurality of collecting electrodes connecting in parallel with the lead wires through a via... Agent: Posz Law Group, PLC

20080258308 - Method of controlled low-k via etch for cu interconnections: An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least... Agent: Katten Muchin Rosenman LLP

20080258310 - Semiconductor device having a tapered plug: A semiconductor device includes: first and second interlayer dielectric films consecutively deposited to overlie a silicon substrate; contact plugs penetrating the first interlayer dielectric film and having a top surface located within the second interlayer dielectric film; and via-plugs having a first portion, the diameter of which reduces from the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080258309 - Three-dimensional semiconductor device: A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface.... Agent: Slater & Matsil, L.L.P.

20080258311 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a first wiring layer, a second wiring layer and a third wiring layer. The first wiring layer is formed on a semiconductor substrate. The second and the third wiring layer wiring layers are arranged in a direction intersecting with the first wiring layer on respective sides... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258312 - Semiconductor device: The present invention enhances the reliability of a semiconductor device. The semiconductor device includes a package substrate having a dry resist film which covers some conductive portions out of a plurality of conductive portions formed on a main surface and a back surface and is formed of a film, a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080258313 - Connecting microsized devices using ablative films: A method of providing connectivity to a microsized device, the method includes the steps of providing an ablative base material having at least a top surface; providing a die having a first and second surface and having bonding pads at least upon the first surface; placing the die with the... Agent: Frank Pincelli Patent Legal Staff

20080258314 - Fabric type semiconductor device package and methods of installing and manufacturing same: A fabric type semiconductor device package is provided. The fabric type semiconductor device package comprises a fabric type printed circuit board comprising a fabric and a lead unit formed by patterning a conductive material on the fabric, a semiconductor device comprising an electrode unit bonded to the lead unit of... Agent: Barry E. Negrin, Esq. Pryor Cashman LLP

20080258316 - Power semiconductor module: A power semiconductor module having a surface of the power semiconductor chip and an external circuit pattern connected by an aluminum wire, and sealed with an epoxy resin, wherein wire diameter of the aluminum wire is 0.4±0.05 mmφ, and coefficient of linear expansion of the epoxy resin in a rated... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080258315 - Semiconductor device and production method of the same semiconductor device: The present invention aims to provide a semiconductor device which can enhance area efficiency, and the semiconductor device includes a plurality of electroconductive member regions formed in a predetermined layer, an insulating film region which is formed in the insulating layer which is an upper layer of the predetermined layer... Agent: Young & Thompson

20080258317 - Semiconductor device: A resin layer covering a semiconductor chip on a wiring board is composed of a first resin layer and a second resin layer, wherein the first resin layer and the second resin layer differ in their plan view pattern, satisfying a relation of a<b, where “a” is difference in length... Agent: Young & Thompson

20080258318 - Semiconductor device: Disclosed herewith is a semiconductor device capable of suppressing the peeling-off that might occur between an island and a resin layer due to a difference of the shrinkage between those items, thereby the reliability of the semiconductor device is improved. The semiconductor device of the present invention includes an island,... Agent: Mcginn Intellectual Property Law Group, PLLC

20080258125 - Resistive memory cell fabrication methods and devices: A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current... Agent: Dickstein Shapiro LLP

20080258126 - Memory cell sidewall contacting side electrode: A memory cell includes a memory cell layer over a memory cell access layer. The memory cell access layer comprises a bottom electrode. The memory cell layer comprises a dielectric layer and a side electrode at least partially defining a void with a memory element therein. The memory element comprises... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080258128 - Phase-changeable memory devices: A phase-changeable memory device includes a substrate having a contact region on an upper surface thereof. An insulating interlayer on the substrate has an opening therein, and a lower electrode is formed in the opening. The lower electrode has a nitrided surface portion and is in electrical contact with the... Agent: Myers Bigel Sibley & Sajovec

20080258127 - Precursor, thin layer prepared including the precursor, method of preparing the thin layer and phase-change memory device: A Te precursor containing Te, a 15-group compound (for example, N) and/or a 14-group compound (for example, Si), a method of preparing the Te precursor, a Te-containing chalcogenide thin layer including the Te precursor, a method of preparing the thin layer; and a phase-change memory device. The Te precursor may... Agent: Harness, Dickey & Pierce, P.L.C

20080258129 - Phase-change memory device: A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258130 - Beveled led chip with transparent substrate: A light emitting diode is disclosed that includes a transparent (and potentially low conductivity) silicon carbide substrate, an active structure formed from the Group III nitride material system on the silicon carbide substrate, and respective ohmic contacts on the top side of the diode. The silicon carbide substrate is beveled... Agent: Summa, Allan & Additon, P.A.

20080258131 - Light emitting diode: The present invention relates to a light emitting diode. More specifically, the present invention relates to a light emitting diode comprising an N-type semiconductor layer formed on a substrate, an active layer formed on the N-type semiconductor layer and a P-type semiconductor layer formed on the active layer, wherein the... Agent: Marger Johnson & Mccollom, P.C.

20080258132 - Quantum dot optoelectronic device having an sb-containing overgrown layer: A quantum dot optoelectronic device has an overgrown layer containing antimony (Sb). The optical characteristics and thermal stability of the optoelectronic device are thus greatly enhanced due to the improved crystal quality and carrier confinement of the quantum dot structure.... Agent: Troxell Law Office PLLC

20080258133 - Semiconductor device and method of fabricating the same: Disclosed is a semiconductor device. The semiconductor device includes a first type nitride-based cladding layer formed on a growth substrate having an insulating property, a multi quantum well nitride-based active layer formed on the first type nitride-based cladding layer and a second type nitride-based cladding layer, which is different from... Agent: Cantor Colburn, LLP

20080258134 - Method for making a semiconductor device including shallow trench isolation (sti) regions with maskless superlattice deposition following sti formation and related structures: A semiconductor device may include a semiconductor substrate having a surface, a shallow trench isolation (STI) region in the semiconductor substrate and extending above the surface thereof, and a superlattice layer adjacent the surface of the semiconductor substrate and comprising a plurality of stacked groups of layers. More particularly, each... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080258135 - Semiconductor structure having plural back-barrier layers for improved carrier confinement: A semiconductor structure having: a channel layer having a conductive channel therein; a pair of polarization generating layers; a spacer layer disposed between the pair of polarization generating layers. The polarization generating layers create polarization fields along a common, predetermined direction. Each one of the pair of polarizations layers may... Agent: Raytheon Company C/o Daly, Crowley, Mofford & Durkee, LLP

20080258136 - Logic circuit: The invention includes a two terminal switching device having two stable resistivity values for each applied voltage, which when a voltage of not more than a first threshold voltage (Vth1) is applied, becomes in a first state having a higher resistivity, whereas when a larger second threshold voltage (Vth2) or... Agent: Rabin & Berdo, PC

20080258137 - Thin film field effect transistors having schottky gate-channel junctions: An active electronic device has drain and source electrodes that make ohmic conduct with a layer of a semiconductor. The semiconductor layer may be a thin layer of an organic or amorphous semiconductor. The drain and source electrodes are on a first face of the layer of semiconductor at locations... Agent: Oyen, Wiggs, Green & Mutala LLP 480 - The Station

20080258138 - Thin film transistor array panel and fabricating method thereof, and flat panel display with the same: An organic thin film transistor array panel, for an embodiment, includes a plurality of pixel electrodes formed on a top layer to cover organic thin film transistors, with display areas defined by the areas of the pixel electrodes. Accordingly, the aperture ratio of the display device may be increased. A... Agent: Macpherson Kwok Chen & Heid LLP

20080258142 - Semiconductor device, its manufacture method and template substrate: The semiconductor device has: a ZnO-containing substrate containing Li; a zinc silicate layer formed above the ZnO-containing substrate; and a semiconductor layer epitaxially grown relative to the ZnO-containing substrate via the zinc silicate layer.... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080258139 - Structure with transistor: A structure with a transistor is disclosed comprising a substrate, a gas barrier layer on the substrate, and a transistor on the gas barrier layer. The transistor can include an oxide semiconductor layer. The oxide semiconductor layers can comprise In—Ga—Zn—O. A display, such as a liquid crystal display, can have... Agent: Squire, Sanders & Dempsey L.L.P.

20080258140 - Thin film transistor including selectively crystallized channel layer and method of manufacturing the thin film transistor: Provided are a thin film transistor (TFT) including a selectively crystallized channel layer, and a method of manufacturing the TFT. The TFT includes a gate, the channel layer, a source, and a drain. The channel layer is formed of an oxide semiconductor, and at least a portion of the channel... Agent: Harness, Dickey & Pierce, P.L.C

20080258141 - Thin film transistor, method of manufacturing the same, and flat panel display having the same: A thin film transistor (TFT), a method of manufacturing the TFT, and a flat panel display comprising the TFT are provided. The TFT includes a gate, a gate insulating layer that contacts the gate, a channel layer that contacts the gate insulating layer and faces the gate with the gate... Agent: Harness, Dickey & Pierce, P.L.C

20080258143 - Thin film transitor substrate and method of manufacturing the same: A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a first conductive pattern group including a gate electrode on a substrate, forming a gate insulating layer on the first conductive pattern group, forming a semiconductor layer and an ohmic contact layer on the gate insulating layer by... Agent: Cantor Colburn, LLP

20080258144 - Semiconductor wafer, semiconductor chip and method of manufacturing semiconductor chip: A semiconductor wafer of the present invention is provided with a substrate having a semiconductor element formation layer, a lowermost metal layer formed on the semiconductor element formation layer and an uppermost layer formed on the lowermost metal layer, and the semiconductor wafer also has plural chip regions and an... Agent: Volentine & Whitt PLLC

20080258145 - Semiconductor devices including an amorphous region in an interface between a device isolation layer and a source/drain diffusion layer: Semiconductor devices and methods for fabricating the same are disclosed in which an amorphous layer is formed in an interface between a device isolation layer and a source or drain region to stably thin a silicide layer formed in the interface. A leakage current of the silicide layer formed in... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080258146 - Thin-film transistor and fabrication method thereof: A fabrication method of a TFT includes successively forming four thin films containing a first conductive layer, an insulation layer, a semiconductor layer, and a second conductive layer on a substrate, performing a first PEP process to pattern the four thin films for forming a semiconductor island and a gate... Agent: North America Intellectual Property Corporation

20080258147 - Semiconductor device forming method: In thin film transistors (TFTs) having an active layer of crystalline silicon adapted for mass production, a catalytic element is introduced into doped regions of an amorphous silicon film by ion implantation or other means. This film is crystallized at a temperature below the strain point of the glass substrate.... Agent: Nixon Peabody, LLP

20080258149 - Liquid crystal display and panel therefor: A thin film transistor array panel according to an embodiment of the present invention includes: a gate line; a data line intersecting the gate line; a thin film transistor connected to the gate line and the data line; a pixel electrode connected to the thin film transistor; and a shielding... Agent: F. Chau & Associates, LLC

20080258148 - Thin film transistor and organic electroluminescence display using the same: In a thin film transistor, a semiconductor layer containing Si and Ge is applied, a Ge concentration of this semiconductor layer is high at the side of the insulating substrate, and crystalline orientation of the semiconductor layer indicates a random orientation in a region of 20 nm from the side... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080258151 - Light emitting device and method for manufacturing the same: Disclosed are a light emitting device and a method for manufacturing the same. A light emitting diode comprises a plurality of Un-GaN layers and a plurality of N-type semiconductor layers, an active layer on the N-type semiconductor layer, and a P-type semiconductor layer on the active layer, wherein at least... Agent: Birch Stewart Kolasch & Birch

20080258150 - Method to fabricate iii-n field effect transistors using ion implantation with reduced dopant activation and damage recovery temperature: Structures to reduce dopant activation temperatures for ion implantation in III-N transistors, using low aluminum content layers in proximity to the conducting channel, are disclosed. A method to increase the temperature at which structures can be annealed by annealing in an active nitrogen ambient, for example, in NH3 in a... Agent: Gates & Cooper LLP Howard Hughes Center

20080258152 - Sic semiconductor device having outer periphery structure: A SiC semiconductor device includes: a SiC substrate; a SiC drift layer on the substrate having an impurity concentration lower than the substrate; a semiconductor element in a cell region of the drift layer; an outer periphery structure including a RESURF layer in a surface portion of the drift layer... Agent: Posz Law Group, PLC

20080258153 - Silcon carbide semiconductor device having schottky barrier diode and method for manufacturing the same: An SiC semiconductor device is provided, which comprises: a substrate made of silicon carbide and having a principal surface; a drift layer made of silicon carbide and disposed on the principal surface; an insulating layer disposed on the drift layer and including an opening; a Schottky electrode contacting with the... Agent: Posz Law Group, PLC

20080258154 - Semiconductor device manufacturing method and display device: Disclosed herein is a semiconductor device manufacturing method for performing an annealing process of irradiating a semiconductor film on which element forming areas including thin film transistor forming areas are arranged in a two-dimensional pattern with energy beams using a plurality of irradiating optical systems, wherein in the annealing process,... Agent: Sonnenschein Nath & Rosenthal LLP

20080258155 - Semiconductor device, optical measuring and detecting device, and method of manufacturing the same: Disclosed is a semiconductor device which is capable of preventing operation of the signal processing part from being unstable due to light not blocked by the light blocking layer by being obliquely incident on the signal processing part and preventing the operation of the signal processing part from being unstable... Agent: Taft, Stettinius & Hollister LLP

20080258158 - Light emission device: A light emission device includes a plurality of semiconductor light emitting elements and a supporting substrate on which the plurality of semiconductor light emitting elements are flip-chip mounted. Each of the plurality of semiconductor light emitting elements has a substantially rectangular shape which has a first side and a second... Agent: Ditthavong Mori & Steiner, P.C.

20080258156 - Light-emitting diode apparatus: In a light-emitting diode apparatus, light emitted from a principal plane of an emission layer has a plurality of unequal luminous intensities depending on the in-plane azimuth angle of the principal plane of the emission layer, and at least one of a light-emitting diode chip and a package has a... Agent: Ditthavong Mori & Steiner, P.C.

20080258157 - Packaging method of led of high heat-conducting efficiency and structure thereof: A packaging method of LED of high heat-conducting efficiency and a structure thereof firstly is to provide a copper substrate having a plurality of indentations. An insulating layer is formed on the surface of the substrate and the bottom of the indentations. Meanwhile, a set of metallic circuits is formed... Agent: Hdsl

20080258159 - Method for preparing metal phosphide nanocrystal from phosphite compound and method for passivating nanocrystal core with the same: Disclosed herein is a method for the preparation of metal phosphide nanocrystals using a phosphite compound as a phosphorous precursor. More specifically, disclosed herein is a method for preparing metal phosphide nanocrystals by reacting a metal precursor with a phosphite compound in a solvent. A method is also provided for... Agent: Cantor Colburn, LLP

20080258160 - Led device comprising thin-film phosphor having two dimensional nano periodic structures: Disclosed herein is an LED device which comprises a light-emitting diode (LED) and a laminate formed on the LED, the laminate consisting of a substrate and a phosphor thin film laminated on the substrate, wherein the phosphor thin film has a two-dimensional nanoperiodic structure formed in a forward direction of... Agent: Christie, Parker & Hale, LLP

20080258164 - Light emitting device: Light emitting device 1 includes an LED chip 10, a mounting substrate 20 carrying the LED chip, a dome-shaped color conversion member 70, and encapsulation member 50. Color conversion member 70 is molded from a transparent resin material and a fluorescent material which is excited by a light emitted from... Agent: Cheng Law Group, PLLC

20080258165 - Light emitting diode chip: A substrate-free LED chip has a multilayer semiconductor structure at least 10 microns thick provided on a growth substrate. One or more arrays of parallel streets are etched into the multilayer semiconductor structure using a first pulsed laser beam. By scanning a second pulsed laser beam through the growth substrate... Agent: Goldeneye, Inc.

20080258162 - Package for a high-power light emitting diode: A package for a high-power light emitting diode (LED) has a packaging substrate, at least one LED chip, at least one pair of conductive wires and an encapsulant. The packaging substrate has a reflective base with a recess, a dissipating board and at least one pair of electrodes. The electrodes... Agent: Hershkovitz & Associates, LLC

20080258163 - Semiconductor light-emitting device with high light-extraction efficiency: The invention discloses a semiconductor light-emitting device and a fabricating method thereof. The semiconductor light-emitting device according to the invention includes a substrate, a multi-layer structure, a top-most layer, and at least one electrode. The multi-layer structure is formed on the substrate and includes a light-emitting region. The top-most layer... Agent: Birch Stewart Kolasch & Birch

20080258161 - Transparent ohmic contacts on light emitting diodes with carrier substrates: A light emitting diode is disclosed that includes an active structure formed of at least p-type and n-type epitaxial layers of Group III nitride on a conductive carrier substrate. A conductive bonding system joins the active structure to the conductive carrier substrate. A first transparent ohmic contact is on the... Agent: Summa, Allan & Additon, P.A.

20080258170 - Light emitting diode structure: The light emitting diode structure includes a substrate, a first electricity semiconductor layer formed on the substrate, a light-emitting layer formed on the first electricity semiconductor layer, a second electricity semiconductor layer formed on the light-emitting layer, a barrier layer formed on the second electricity semiconductor layer, and a contact... Agent: Raymond R. Moser Jr., Esq. MoserIPLaw Group

20080258167 - Package structure for light-emitting elements: The present invention discloses a package structure for light-emitting elements, wherein a horizontally-extending thermal conductive plate contacts a thermal conductive substrate having a larger heat-dissipating area. Via such a horizontal heat-dissipation mechanism, the heat generated by light-emitting elements is dissipated at a higher rate; thereby, the light-emitting elements have a... Agent: Sinorica, LLC

20080258166 - Semiconductor light emitting device and method for manufacturing the same: There is provided a semiconductor light emitting semiconductor device including an n-side electrode which has a structure capable of stably suppressing the contact resistance between the n-side electrode and a nitride semiconductor layer. Further, there is provided a light emitting device and a manufacturing method wherein an ohmic contact between... Agent: Rabin & Berdo, PC

20080258168 - Semiconductor light emitting device packages and methods: A submount for a light emitting device package includes a rectangular substrate. A first bond pad and a second bond pad are on a first surface of the substrate. The first bond pad includes a die attach region offset toward a first end of the substrate and configured to receive... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080258169 - Substrate for mounting light emitting element, light emitting module and lighting apparatus: A substrate for mounting light emitting elements having two or more conductive layers and an insulating layer provided between each conductive layer, which are formed on the outside of an enameled substrate, the enameled substrate being an enamel layer covering the surface of a core metal. The conductive layer provided... Agent: Sughrue Mion, PLLC

20080258171 - Semiconductor light emitting device excellent in heat radiation: A semiconductor light emitting device is provided which comprises: a semiconductor light emitting chip 2 mounted on a top surface 12 of a support plate 1, wiring conductors 3 disposed adjacent to side surfaces 11 of support plate 1, and a plastic encapsulant 6 for sealing side surfaces 11 of... Agent: Bachman & Lapointe, P.C.

20080258172 - Insulated gate bipolar transistor with built-in freewheeling diode: An insulated gate bipolar transistor includes a first main electrode on a first main surface and in contact with a base region of an insulated gate transistor at the first main surface, a first semiconductor layer of a first conductivity type on a second main surface, a second semiconductor layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258173 - Vertical p-n junction device and method of forming same: A P-N junction device and method of forming the same are disclosed. The P-N junction device may include a P-N diode, a PiN diode or a thyristor. The P-N junction device may have a monocrystalline or polycrystalline raised anode. In one embodiment, the P-N junction device results in a raised... Agent: Hoffman Warnick LLC

20080258174 - Optical device and method of fabricating the same: Disclosed is an optical device including an optical member and a contact layer stacked on at least one of top and bottom surfaces of the optical member. The contact layer has at least one transparent conducting oxynitride (TCON) layer. The TCON consists of at least one of indium (In), tin... Agent: Macpherson Kwok Chen & Heid LLP

20080258175 - Stressed mos device: A stressed MOS device is provided that includes a silicon substrate, a gate electrode and an epitaxial layer of stress inducing monocrystalline semiconductor material. The silicon substrate is characterized by a monocrystalline silicon lattice constant. The gate electrode overlies a silicon channel region at the surface of the silicon substrate.... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080258176 - Antimonide-based compound semiconductor with titanium tungsten stack: An apparatus in one example comprises an antimonide-based compound semiconductor (ABCS) stack, an upper barrier layer formed on the ABCS stack, and a gate stack formed on the upper barrier layer. The upper barrier layer comprises indium, aluminum, and arsenic. The gate stack comprises a base layer of titanium and... Agent: Patti, Hewitt & Arezina LLC

20080258177 - method of manufacturing a semiconductor device and a semiconductor device: Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080258178 - Method of forming a mos transistor: A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region,... Agent: North America Intellectual Property Corporation

20080258179 - Hybrid molecular electronic device for switching, memory, and sensor applications, and method of fabricating same: A hybrid molecular electronic device having switching, memory, and sensor application is disclosed. In one embodiment, the device resembles a conventional field-effect transistor (FET) formed on a silicon-on-insulator (SOI) substrate. Source and drain doped regions are formed in an upper surface of the SOI substrate, and a metallization layer which... Agent: Winstead PC

20080258180 - Cross-section hourglass shaped channel region for charge carrier mobility modification: A semiconductor structure and a method for fabricating the semiconductor structure include a semiconductor substrate having a cross-section hourglass shaped channel region. A stress imparting layer is located adjacent the channel region. The hourglass shape may provide for enhanced vertical tensile stress within the channel region when it is longitudinally... Agent: Scully Scott Murphy & Presser, PC

20080258181 - Hybrid substrates and methods for forming such hybrid substrates: Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one of the different crystal orientations into mutually aligned device and... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080258182 - Bicmos compatible jfet device and method of manufacturing same: A BiCMOS-compatible JFET device comprising source and drain regions (17, 18) which are formed in the same process as that used to form the emitter out-diffusion or a vertical bipolar device, wherein the semiconductor layer which forms the emitter cap in the bipolar device forms the channel (16) of the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080258183 - Method of manufacturing a device by locally heating one or more metallization layers and by means of selective etching: A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that... Agent: Maginot, Moore & Beck Chase Tower

20080258184 - Normally-off integrated jfet power switches in wide bandgap semiconductors and methods of making: Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single- or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant... Agent: Morris Manning Martin LLP

20080258185 - Semiconductor structure with dielectric-sealed doped region: Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are... Agent: Slater & Matsil, L.L.P.

20080258186 - Source and drain formation in silicon on insulator device: A silicon on insulator device has a silicon layer (10) over a buried insulating layer (12). A nickel layer is deposited over a gate (16), on sidewall spacers (22) on the sides of the gate (16), and in a cavity on both sides of the gate (16) in the silicon... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080258189 - Image sensor and method of manufacturing the same: An image sensor and a method of manufacturing the same are provided. The image sensor includes a semiconductor substrate, a metal line layer, a first conduction type conducting layer, a first pixel isolation layer, an intrinsic layer, and second conduction type conducting layer. The semiconductor substrate includes a circuit region.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080258188 - Metal oxide semiconductor device and method of fabricating the same: A method of fabricating an MOS device is provided. First, gates and source/drain regions of transistors are formed on a substrate. A photodiode doped region and a floating node doped region are formed in the substrate. Thereafter, a spacer stacked layer including a bottom layer, an inter-layer and a top... Agent: J C Patents, Inc.

20080258187 - Methods, systems and apparatuses for the design and use of imager sensors: An imager sensor cell design having readout circuitry contained within the photodiode region.... Agent: David J. Paul Mail Stop 1-525

20080258190 - Solid-state image sensing device and camera system using the same: A solid-state image sensing device includes a plurality of pixels. Each pixel has a photodiode, a first transistor, and a second transistor. The photodiode is constituted by a first-conductivity-type semiconductor region and a second-conductivity-type semiconductor region. The first and second conductivity types are opposite to each other. The first transistor... Agent: Fitzpatrick Cella Harper & Scinto

20080258191 - Capacitor device providing sufficient reliability: A capacitor device includes a dielectric layer configured to have a composition represented as (Ba1-x, Srx)Ti1-zScyO3+δ (0<x<1, 0.01<z<0.3, 0.005<y<0.02, −0.5<δ<0.5) and an in-plane deformation ∈ of crystal that satisfies −0.4<<0.4, an upper electrode and a lower electrode that are placed on respective sides of the dielectric layer, and a substrate... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080258193 - Ferroelectric memory and method of manufacturing the same: A ferroelectric memory that stores information by using a hysteresis characteristic of a ferroelectric, has a semiconductor substrate; a lower electrode formed above said semiconductor substrate; a ferroelectric film formed on said lower electrode; and an upper electrode formed on said ferroelectric film, wherein said upper electrode includes an AOx-type... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080258194 - Flip feram cell and method to form same: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric... Agent: Scully, Scott, Murphy & Presser, P.C.

20080258192 - Semiconductor device and manufacturing method thereof: This disclosure concerns a semiconductor device comprising an insulating film provided on a semiconductor substrate; a lower contact formed in the insulating film; a ferroelectric capacitor including a first lower electrode provided on the lower contact and connected to the lower contact, a second lower electrode provided on the first... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080258195 - Semiconductor device and method of manufacturing the same: A ferroelectric capacitor is formed above a semiconductor substrate (1), and thereafter, wirings (24a) are formed. A barrier film (25) covering the wirings (24a) is formed. A silicon oxide film (26) embedding gaps between the adjacent wirings (24a) is formed. The silicon oxide film (26) is polished until a surface... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080258196 - Semiconductor structure of a display device and method for fabricating the same: A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080258197 - Semiconductor-insulator-silicide capacitor: A semiconductor-insulator-silicide (SIS) capacitor is formed by depositing a thin silicon containing layer on a salicide mask dielectric layer, followed by lithographic patterning of the stack and metallization of the thin silicon containing layer and other exposed semiconductor portions of a semiconductor substrate. The thin silicon containing layer is fully... Agent: Scully, Scott, Murphy & Presser, P.C.

20080258198 - Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for cmos: s

20080258199 - Flash memory device and fabricating method thereof: A new device structure according to the present invention is compatible with existing fabrication process and is based on a recessed channel, which is capable of easily implementing highly-integrated/high-performance and 2-bit/cell. The proposed device has a structure suppressing the short channel effect while largely reducing the cell area and enabling... Agent: Greenblum & Bernstein, P.L.C

20080258200 - Memory cell having a shared programming gate: A semiconductor memory device includes a substrate, and a trench formed in the substrate. First and second floating gates, each associated with corresponding first and second memory cells, extend into the trench. Since the trench can be made relatively deep, the floating gates may be made relatively large while the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080258202 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a semiconductor substrate having a first trench, an element isolation insulating film, a floating gate electrode, a second gate insulating film and a control gate electrode. The element isolation insulating film includes a sidewall having such a height as to be in contact with... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258201 - Semiconductor memory device and method of manufacturing the same: A manufacturing method of a semiconductor memory device for manufacturing a first semiconductor device and a second semiconductor device wherein a cell array ratio is smaller than that of the first semiconductor device, said manufacturing method has forming the height of first element-isolating insulating films of first memory cell array... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258204 - Memory structure and operating method thereof: A memory structure including a substrate, a charge trapping layer, a block layer, a conducting layer and two doped regions is provided in the present invention. The charge trapping layer is disposed on the substrate. The block layer is disposed on the charge trapping layer. The conducting layer is disposed... Agent: J C Patents, Inc.

20080258205 - Non-volatile semiconductor memory device: An erase current of a non-volatile semiconductor memory device is decreased. A memory cell of the non-volatile semiconductor memory device comprises a source region and a drain region formed in a semiconductor substrate. Over a portion of the semiconductor substrate between the source region and the drain region, a select... Agent: Miles & Stockbridge PC

20080258203 - Stacked sonos memory: An integrated circuit includes a first SONOS memory cell and a second SONOS memory cell. The second memory cell is stacked on the first memory cell.... Agent: Dicke, Billig & Czaja

20080258207 - Block contact architectures for nanoscale channel transistors: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080258206 - Self-aligned gate structure, memory cell array, and methods of making the same: A self-aligned gate structure includes a first gate region and a second gate region. The first gate region extends in semiconductor substrate portions to a lesser depth than in isolation trenches that are adjacent to the semiconductor substrate portions. The first gate region comprises a first conductive material. The second... Agent: Edell, Shapiro & Finnan, LLC

20080258208 - Semiconductor component including compensation zones and discharge structures for the compensation zones: A semiconductor component including compensation zones and discharge structures for the compensation zones. One embodiment provides a drift zone of a first conduction type, at least one compensation zone of a second conduction type, complementary to the first conduction type, the at least one compensation zone being arranged in the... Agent: Dicke, Billig & Czaja

20080258209 - Semiconductor device and manufaturing method thereof: A semiconductor device comprises a plurality of semiconductor pillars laid out in matrix in a first and a second directions parallel with a main surface of a semiconductor substrate, and extending to a direction substantially perpendicular to the main surface; gate insulating films covering each surface of the plurality of... Agent: Sughrue Mion, PLLC

20080258210 - Semiconductor component and method of manufacture: A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in... Agent: Mr. Jerry Chruma Semiconductor Components Industries, L.L.C.

20080258211 - Semiconductor device and method for manufacturing the same: In a MIS-type semiconductor device having a trench gate structure, a withstand voltage is ensured without changing the thickness of a drift layer and on-resistance can be reduced without applying a high gate drive voltage. The lower half of a trench extending through a p-base region into an n-drift region... Agent: Rossi, Kimms & Mcdowell LLP.

20080258213 - Shielded gate field effect transistor: A FET includes a trench in a semiconductor region. The trench has a lower portion with a shield electrode therein, and an upper portion with a gate electrode therein, where the upper portion is wider than the lower portion. The semiconductor region includes a substrate of a first conductivity type... Agent: Townsend And Townsend And Crew, LLP

20080258212 - Trench metal oxide semiconductor with recessed trench material and remote contacts: Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20080258214 - Semiconductor device and method of fabricating the same: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can provide a trench MOS transistor having an up-drain structure. The semiconductor device can include a first conductive type well in a semiconductor substrate, a second conductive type well on the first conductive type... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080258215 - Ldmos device: An LDMOS transistor comprises source, channel and extended drain regions. The extended drain region comprises a plurality of islands that have a conductivity type that is opposite to the extended drain region. The islands have a depth less than a depth of the extended drain region.... Agent: Coats & Bennett/infineon Technologies

20080258216 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a field effect transistor including a semiconductor substrate having a channel-forming region, an insulating film formed on the semiconductor substrate, a gate electrode trench formed in the insulating film, a gate insulating film formed at the bottom of the gate electrode trench, a gate electrode formed... Agent: Sonnenschein Nath & Rosenthal LLP

20080258218 - Semiconductor device and method of manufacturing the same: A MIS transistor having an inclined stacked source/drain structure increased in speed is provided. The MIS transistor comprises: a gate electrode formed on a substrate; a first sidewall insulating film formed on the substrate and along a sidewall of the gate electrode; source/drain semiconductor regions formed on a main surface... Agent: Miles & Stockbridge PC

20080258217 - Semiconductor device structure for anti-fuse: The present invention discloses a semiconductor device, the device comprising a semiconductor layer on a substrate. A gate oxide and a gate electrode are formed on the semiconductor substrate. A gate conductive layer is formed on the gate electrode. A first doped region is formed in the semiconductor layer. A... Agent: Birch Stewart Kolasch & Birch

20080258220 - Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors: This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for... Agent: Scully, Scott, Murphy & Presser, P.C.

20080258219 - Method to selectively modulate gate work function through selective ge condensation and high-k dielectric layer: A semiconductor device is provided which comprises a semiconductor layer (109), a dielectric layer (111), first and second gate electrodes (129, 131) having first and second respective work functions associated therewith, and a layer of hafnium oxide (113) disposed between said dielectric layer and said first and second gate electrodes.... Agent: Fortkort & Houston P.C.

20080258221 - Substrate solution for back gate controlled sram with coexisting logic devices: A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level... Agent: Scully, Scott, Murphy & Presser, P.C.

20080258222 - Design structure incorporating a hybrid substrate: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes devices formed in a hybrid substrate characterized by semiconductor islands of different crystal orientations. An insulating layer divides the islands of at least one of the different crystal orientations... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080258223 - Esd protection device: An ESD protection device is provided. The ESD protection device of the present invention includes a semiconductor substrate/well, a first doped region, a second doped region and a third doped region. The first doped region doped with a first dopant is disposed in the semiconductor substrate/well. The second doped region... Agent: J C Patents, Inc.

20080258224 - Trenched mosfets with improved gate-drain (gd) clamp diodes: A MOSFET device that includes a first Zener diode connected between a gate metal and a drain metal of said semiconductor power device for functioning as a gate-drain (GD) clamp diode. The GD clamp diode includes multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a... Agent: Bo-in Lin

20080258225 - Mos transistors having high-k offset spacers that reduce external resistance and methods for fabricating the same: MOS transistors having high-k spacers and methods for fabricating such transistors are provided. One exemplary method comprises forming a gate stack overlying a semiconductor substrate and forming an offset spacer about sidewalls of the gate stack. The offset spacer is formed of a high-k dielectric material that results in a... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080258226 - Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material: Methods for manufacturing trench type semiconductor devices containing thermally unstable refill materials are provided. A disposable material is used to fill the trenches and is subsequently replaced by a thermally sensitive refill material after the high temperature processes are performed. Trench type semiconductor devices manufactured according to method embodiments are... Agent: Panitch Schwarze Belisario & Nadel LLP

20080258228 - Contact scheme for mosfets: A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a contact extending from a top surface of the first ILD into the first ILD; a second ILD over the first ILD; a... Agent: Slater & Matsil, L.L.P.

20080258229 - Semiconductor device and method for fabricating the same: A semiconductor device includes an N-type MOS transistor and a P-type MOS transistor. The N-type MOS transistor has a first gate insulating film and a first gate electrode. The P-type MOS transistor has a second gate insulating film and a second gate electrode. The first gate insulating film and the... Agent: Mcdermott Will & Emery LLP

20080258230 - Semiconductor device and method for manufacturing the same: There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258227 - Strained spacer design for protecting high-k gate dielectric: A semiconductor device pair is provided. The semiconductor device pair comprises a semiconductor substrate comprising a first gate structure with a first type polarity and a second gate structure with a second type polarity, the first and the second gate structures comprise a high-K gate dielectric. A plurality of oxygen-free... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080258231 - Semiconductor device: A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter... Agent: Ditthavong Mori & Steiner, P.C.

20080258232 - Semiconductor device and method for producing the same: A semiconductor device includes a substrate, an insulating film disposed on the substrate, a resistor groove disposed in the insulating film, and a resistor disposed in the resistor groove. The resistor is separated from all side surfaces of the resistor groove by a predetermined distance.... Agent: Sonnenschein Nath & Rosenthal LLP

20080258233 - Semiconductor device with localized stressor: A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped... Agent: Slater & Matsil, L.L.P.

20080258235 - Manufacturing method of semiconductor device and semiconductor device: A gate insulating film and a gate electrode of an nMOS transistor are laminated and formed in this order on a semiconductor substrate. A source/drain region of the nMOS transistor is formed in the upper surface of the semiconductor substrate. The source/drain region is silicided after siliciding all the regions... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258234 - Semiconductor structure for low parasitic gate capacitance: A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride... Agent: Scully, Scott, Murphy & Presser, P.C.

20080258236 - Method of manufacturing a semiconductor device: With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080258237 - Semiconductor device having multi-channel and method of fabricating the same: An embodiment of the present invention relates to a semiconductor device having a multi-channel and a method of fabricating the same. In an aspect, the semiconductor device includes a semiconductor substrate in which isolation layers are formed, a plurality of trenches formed within an active region of the semiconductor substrate,... Agent: Lowe Hauptman Ham & Berner, LLP

20080258239 - Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material: Methods for manufacturing trench type semiconductor devices involve refilling the trenches after high temperature processing steps are performed. The methods allow thermally unstable materials to be used as refill materials for the trenches of the device. Trench type semiconductor devices containing thermally unstable refill materials are also provided. In particular,... Agent: Panitch Schwarze Belisario & Nadel LLP

20080258238 - Semiconductor device manufactured using an oxygenated passivation process during high density plasma deposition: In one aspect, the method comprises forming trenches in a semiconductor substrate and filling the trenches with a dielectric material. The process of filling the trenches includes depositing the dielectric material with a plasma gas mixture, etching the dielectric material with a chemical etch including nitrogen fluoride and using a... Agent: Texas Instruments Incorporated

20080258240 - Integrated circuits and interconnect structure for integrated circuits: An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with respective ones of the N plane-like metal layers, where M is an integer greater than one, wherein the first plane-like metal layer and the N plane-like metal layers are located... Agent: Harness, Dickey & Pierce P.L.C

20080258241 - Integrated circuits and interconnect structure for integrated circuits: An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively. The first source region is arranged between first sides of the first and second drain regions and the second and third source regions are... Agent: Harness, Dickey & Pierce P.L.C

20080258243 - Field effect transistor: A field effect transistor includes: a first nitride semiconductor layer having a plane perpendicular to a (0001) plane or a plane tilted with respect to the (0001) plane as a main surface; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider bandgap than... Agent: Mcdermott Will & Emery LLP

20080258242 - Low contact resistance ohmic contact for a high electron mobility transistor and fabrication method thereof: A semiconductor device (100) is formed on a semi-insulating semiconductor substrate (101) including a channel layer (104), a spacer layer (105), an electron supply layer (106), and a barrier layer (108). A composite layer (110) is formed over the barrier layer (108). A metal (116) is deposited over the composite... Agent: Posz Law Group, PLC

20080258245 - Semiconductor constructions and transistor gates: One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined... Agent: Wells St. John P.s.

20080258244 - Semiconductor device: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate, a gate dielectric layer provided on the semiconductor substrate, a source region provided in the semiconductor substrate, a drain region provided in the semiconductor substrate, and a gate electrode provided on the gate dielectric layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258246 - Passive electrically testable acceleration and voltage measurement devices: Acceleration and voltage measurement devices and methods of fabricating acceleration and voltage measurement devices. The acceleration and voltage measurement devices including an electrically conductive plate on a top surface of a first insulating layer; a second insulating layer on a top surface of the conductive plate, the top surface of... Agent: Schmeiser, Olsen & Watts

20080258247 - Spin-transfer mram structure and methods: A spin-transfer MRAM bit includes a free magnet layer positioned between a pair of spin polarizers, wherein at least one of the spin polarizers comprises an unpinned synthetic antiferromagnet (SAF). The SAF may include two antiparallel fixed magnet layers separated by a coupling layer. To improve manufacturability, the layers of... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080258249 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same improve photosensitivity by imparting a color filter layer with the function of a microlens layer. The CMOS image sensor includes a semiconductor substrate; a plurality of photo-sensing elements formed in the semiconductor substrate; and a color filter layer comprised... Agent: Mckenna Long & Aldridge LLP

20080258248 - Image sensor and method for manufacturing the same: An image sensor and a method for manufacturing the same are provided. A photodiode region and transistor region are vertically-integrated to improve the fill factor and resolution of the image sensor. Unit pixels can be isolated by a metal isolation layer arranged between adjacent photodiode areas.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080258250 - Solid-state image capturing device, method of manufacturing the same, and electronic information device: A solid-state image capturing device is provided, in which a multilayered wiring section having a plurality of wiring layers laminated via respective interlayer insulation films is provided on a semiconductor substrate or a semiconductor region formed on the substrate where a plurality of light receiving sections for photoelectrically converting a... Agent: Edwards Angell Palmer & Dodge LLP

20080258251 - Image sensor: An image sensor including a second line formed at an upper part of a photodiode region as a transparent electrode for passing light. The second line is composed of a polymeric material having transparency and conductivity.... Agent: Sherr & Vaughn, PLLC

20080258252 - Circuit arrangement having a free-wheel diode: An object of the present invention is to reduce the conducting loss of an existing conversion circuit while suppressing its noise. The present invention is typically a circuit arrangement includes at least one switching device and a free-wheel diode connected in parallel with the switching device. The free-wheel diode is... Agent: Miles & Stockbridge PC

20080258253 - Integrated microprocessor system for safety-critical regulations: Disclosed is an integrated circuit arrangement for safety-critical applications, such as for regulating and controlling tasks in an electronic brake system for motor vehicles. The arrangement includes several electronic, cooperating functional groups (25, 25′), with electric lines (30) provided to interconnect the functional groups (25, 25′). The functional groups consist... Agent: Craig Hallacher Continental Teves, Inc.

20080258254 - Process for realizing an integrated electronic circuit with two active layer portions having different crystal orientations: A process for realizing an integrated electronic circuit makes it possible to obtain transistors with p-type conduction and transistors with n-type conduction, in respective active zones having crystal orientations adapted to each conduction type. In addition, each active zone is electrically insulated from a primary substrate of the circuit, so... Agent: Seed Intellectual Property Law Group PLLC

20080258255 - Electromigration aggravated electrical fuse structure: A fuse structure with aggravated electromigration effect is disclosed, which comprises an anode area overlaying a first plurality of contacts that are coupled to a positively high voltage during a programming of the fuse structure, a cathode area overlaying a second plurality of contacts that are coupled to a complementary... Agent: K & L Gates LLP

20080258256 - Semiconductor electrically programmable fuse element with amorphous silicon layer after programming and method of programming the same: A fuse link is formed between first and second terminals. The first and second terminals and fuse link have a polysilicon layer and a layer formed on the polysilicon layer and containing a metal element. At least a portion of the fuse link is an amorphous silicon layer.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258257 - Electronic device and use thereof: The integrated capacitor structure comprises a first branch with a first capacitor (60) and a second branch with a second capacitor (70). The second capacitor (70) has a higher capacitance density and a lower breakdown voltage than the first capacitor (60). The first branch has a shorter RC time constant... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080258259 - Semiconductor chip and semiconductor device: A semiconductor chip and a semiconductor device mounting the semiconductor chip capable of increasing a capacitance of a capacitor without reducing the number of signal bumps or power bumps of a package and the number of C4 solder balls of the semiconductor chip, and achieving a stable power supply with... Agent: Miles & Stockbridge PC

20080258258 - Semiconductor device: The invention provides a semiconductor device which has a capacitor element therein to achieve size reduction of the device, the capacitor element having larger capacitance than conventional. A semiconductor integrated circuit and pad electrodes are formed on the front surface of a semiconductor substrate. A second insulation film is formed... Agent: Morrison & Foerster LLP

20080258260 - Semiconductor device and method for manufacturing the same: A semiconductor device including a capacitor formed over a semiconductor substrate and including a lower electrode, a dielectric film formed over the lower electrode and an upper electrode formed over the dielectric film, an insulation film formed over the semiconductor substrate and the capacitor, and an electrode pad formed over... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080258261 - Split chip: This Invention is a design method and a system for a miniaturized silicon circuit whereby the circuit is split into two pieces. This process is known to the Inventor as a bifurcated circuit or disintegrated circuit and is titled the “Split Chip” by the Inventor. The Split Chip contemplates an... Agent: James Neil Rodgers

20080258262 - Semiconductor device with improved pads: A semiconductor device has: a circuit portion having semiconductor elements formed on a semiconductor substrate; insulating lamination formed above the semiconductor substrate and covering the circuit portion; a multilevel wiring structure formed in the insulating lamination and including wiring patterns and via conductors; and a pad electrode structure formed above... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080258263 - High current steering esd protection zener diode and method: A method of fabricating a N+/P+ zener diode where the reverse breakdown occurs in a controlled, and uniform manner leading to improved speed of operation and increase in current handling capability.... Agent: Pillsbury Winthrop Shaw Pittman LLP

20080258264 - Semiconductor device and method for manufacturing the same: Disclosed is a semiconductor device comprising a Ge semiconductor area, and an insulating film area, formed in direct contact with the Ge semiconductor area, containing metal, germanium, and oxygen.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258265 - Methods for forming an assembly for transfer of a useful layer: Methods for transferring of a useful layer from a support are described. In an embodiment, the method includes for facilitating transfer of a useful layer from a support by providing an interface in a first support to define a useful layer; and forming a peripheral recess on the first support... Agent: Winston & Strawn LLP Patent Department

20080258266 - Semiconductor device and manufacturing method thereof: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and... Agent: Mcdermott Will & Emery LLP

20080258267 - Method of producing semiconductor device and semiconductor device: A method of producing a semiconductor device which can reliably perform conductor filling to form a through hole electrode by a simple method is provided. A method of producing a semiconductor device of the present invention includes the steps of thinning a substrate from its back side in a state... Agent: Nixon & Vanderhye, PC

20080258268 - Trench structure and method of forming the trench structure: Disclosed are embodiments of an improved deep trench capacitor structure and memory device that incorporates this deep trench capacitor structure. The deep trench capacitor and memory device embodiments are formed on a semiconductor-on-insulator (SOI) wafer such that the insulator layer remains intact during subsequent deep trench etch processes and, optionally,... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080258269 - Semiconductor wafer and method for cutting the same: A semiconductor wafer and a method for cutting the same, enabling separation of the semiconductor wafer by natural cleavage planes, are disclosed. The cutting method according to an embodiment of the present invention comprises preparing a substrate including a semiconductor layer with at least one projection, formed on a predetermined... Agent: Ked & Associates, LLP

20080258270 - Mgo-based coating for electrically insulating semiconductive substrates and production method thereof: The present invention relates to a magnesium oxide-based (MgO) inorganic coating intended to electrically insulate semiconductive substrates such as silicon carbide (SiC), and to a method for producing such an insulating coating. The method of the invention comprises the steps of preparing a treatment solution of at least one hydrolysable... Agent: Brinks, Hofer, Gilson & Lione

20080258271 - Multi-dielectric films for semiconductor devices and methods of fabricating multi-dielectric films: A multi-dielectric film including at least one first dielectric film that is a composite film made of zirconium-hafnium-oxide and at least one second dielectric film that is a metal oxide film made of amorphous metal oxide. Adjacent ones of the dielectric films are made of different materials.... Agent: Myers Bigel Sibley & Sajovec

20080258272 - Etched leadframe structure: A leadframe structure is disclosed. The leadframe structure includes a first leadframe structure portion with a first thin portion and a first thick portion, where the first thin portion is defined in part by a first recess. It also includes a second leadframe structure portion with a second thin portion... Agent: Townsend And Townsend And Crew, LLP

20080258273 - Package structure with flat bumps for electronic device and method of manufacture the same: The invention discloses an ultra thin package structure of leadless electronic device and the packaging method, and includes lead support base adjacent to the chip support base; chip mounted on the chip support base; wires bonded between chip and lead support base; the molded body encapsulating the top surface and... Agent: Heslin Rothenberg Farley & Mesiti PC

20080258274 - Semiconductor package and method: A semiconductor package is disclosed. In one embodiment, the semiconductor package includes a leadframe including a chip position and a plurality of leadfingers. Each leadfinger includes a cutout in an inner edge providing a chip recess. The semiconductor package further includes a semiconductor chip located in the chip recess. The... Agent: Dicke, Billig & Czaja

20080258275 - Controlling warping in integrated circuit devices: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a... Agent: Ryan, Mason & Lewis, LLP

20080258280 - Lead frame, semiconductor device using the lead frame, and methods of manufacturing the same: Provided are a lead frame, semiconductor device, and methods of manufacturing the same. The lead frame may include a die pad having at least three pair of sides parallel with each other, and a plurality of inner leads spaced apart from a circumference of the die pad, arranged in a... Agent: Harness, Dickey & Pierce, P.L.C

20080258279 - Leadframe for leadless package, structure and manufacturing method using the same: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces... Agent: Wpat, PC Intellectual Property Attorneys

20080258276 - Non-leaded semiconductor package and a method to assemble the same: A method to assemble a non-leaded semiconductor package (1) comprises the following steps. A carrier tape (13) is attached to a metal foil (12). A plurality of leadframes (3) is formed in the metal foil (12), each leadframe (3) comprising a die pad (4) laterally surrounded by a plurality of... Agent: Dicke, Billig & Czaja

20080258278 - Partially patterned lead frames and methods of making and using the same in semiconductor packaging: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is... Agent: White & Case LLP Patent Department

20080258277 - Semiconductor device comprising a semiconductor chip stack and method for producing the same: A semiconductor device includes a semiconductor chip stack having at least one lower semiconductor chip as a base of the semiconductor chip stack, and at least one upper semiconductor chip. An insulating intermediate plate is arranged between the semiconductor chips. Connecting elements wire the semiconductor chips, the intermediate plate and... Agent: Edell , Shapiro & Finnan , LLC

20080258281 - Process for producing and apparatus for improving the bonding between a plastic and a metal: A semiconductor having a leadframe is disclosed. In one embodiment, a leadframe is disclosed to be fitted with a semiconductor chip and is to be encapsulated with a plastic compound has a metallic single-piece base body, to which an interlayer is applied. The interlayer has a surface including a matrix... Agent: Dicke, Billig & Czaja

20080258282 - Lead frame free package and method of making: A lead frame free packaged semiconductor device with an exposed heat sink is formed by die bonding the semiconductor device directly to the heat sink and bonding package leads directly to the semiconductor die, and optionally to the heat sink. In an alternative embodiment, a lead frame free packaged semiconductor... Agent: Hiscock & Barclay, LLP

20080258283 - Wiring board and semiconductor package using the same: l

20080258284 - Ultra-thin chip packaging: A packaging method involves attaching a first chip to a stable base, forming contact pads at locations on the stable base, applying a medium onto the stable base such that it electrically insulates sides of the first chip, forming electrical paths on the medium, attaching a second chip to the... Agent: Foley & Lardner LLP

20080258286 - High input/output, low profile package-on-package semiconductor system: A package-on-package system (100) has a first subsystem (191) interconnected with a second subsystem (192) by solder connectors (193). The first subsystem has an insulating, trace-laminated, sheet-like carrier (101), which is laminated (102) with an insulating trace-laminated frame (110) exposing a central portion (103) of the carrier. A first chip... Agent: Texas Instruments Incorporated

20080258287 - Semiconductor device and method of manufacturing the same: A semiconductor device includes: solder balls provided on an upper package; and pads provided on a lower package and directly connected to the solder balls, wherein at least one of the pads serves as a fiducial mark. Further, a shape of at least one of the pads is different from... Agent: Rankin, Hill & Clark LLP

20080258288 - Semiconductor device stack package, electronic apparatus including the same, and method of manufacturing the same: In a semiconductor device stack package and a method of forming the same, the package comprises: a substrate; a plurality of lower chips stacked on the substrate and having an active surface oriented in a direction toward the substrate; and at least one upper chip disposed on the lower chips... Agent: Mills & Onello LLP

20080258285 - Simplified substrates for semiconductor devices in package-on-package products: An insulating sheet-like substrate (601), which has on one surface (601a) a first patterned metal layer (605) with a first (603a) and a second (603b) array of contact pads. The pads of the first array have a first pitch center-to-center, and each pad has a first perimeter. The pads of... Agent: Texas Instruments Incorporated

20080258289 - Integrated circuit package system for package stacking: An integrated circuit package system comprising: forming an area array substrate; mounting surface conductors on the area array substrate; forming a molded package body on the area array substrate and the surface conductors; providing a step in the molded package body; and exposing a surface conductor by the step.... Agent: Law Offices Of Mikio Ishimaru

20080258290 - Semiconductor device and method for manufacturing the same: A COF which can effectively dissipate the heat by using a simple structure and its manufacturing method. A semiconductor device of COF, which is formed over the main surface of a flexible substrate having no device hole and where a semiconductor chip is mounted over the inner lead interconnection, is... Agent: Mcginn Intellectual Property Law Group, PLLC

20080258291 - Semiconductor packaging with internal wiring bus: A packaged semiconductor includes inner bond fingers, at least first and second semiconductor dies, and an interposer. The packaged semiconductor further includes wiring between the first and second semiconductor dies and the inner bond fingers, wiring between the interposer and the inner bond fingers, and wiring between the interposer and... Agent: Fitzpatrick Cella (marvell)

20080258292 - Macro-cell block and semiconductor device: The macro-cell block is a macro-cell block formed polygonal having a plurality of sides and formed in a semiconductor chip, and is characterized by comprising a signal terminal portion, a power terminal portion, and a ground terminal portion, which are connected to the outside of a semiconductor chip, wherein the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080258293 - Semiconductor device package to improve functions of heat sink and ground shield: The present invention provides a package structure and a method for forming the same. The structure comprises a substrate with contact pads and through holes filled with conducting metals for performing heat dissipation and ground shielding A chip with bonding pads is attached on the contact pad by an adhesive... Agent: The Maxham Firm

20080258294 - Heat-dissipating semiconductor package structure and method for manufacturing the same: A heat-dissipating semiconductor package structure and a method for manufacturing the same is disclosed. The method includes: disposing on and electrically connecting to a chip carrier at least a semiconductor chip and a package unit; disposing on the top surface of the package unit a heat-dissipating element having a flat... Agent: Edwards Angell Palmer & Dodge LLP

20080258295 - Self-contained cooling mechanism for integrated circuit using a reversible endothermic chemical reaction: A package for a semiconductor chip or other heat producing device has a supporting substrate to which the devices mount and electrically connect. An enclosure is formed over the heat producing devices and filled with a working fluid including a chemical compound that reacts endothermically to absorb heat produced by... Agent: Quarles & Brady LLP

20080258296 - Cut-out heat slug for integrated circuit device packaging: In a package, a heat slug, encapsulated by molding compound, encases an integrated circuit device (IC). In an example embodiment, a semiconductor package structure comprises a substrate (200) having conductive traces (235) and pad landings (265). The conductive traces have pad landings (265). An IC (230) is mounted on the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080258297 - Method of making solder pad: A method of making a solder pad includes providing a substrate having a metal layer formed on it, and applying a photo resist to the metal layer. The photo resist is patterned. A first etching operation is performed on the metal layer to form voids in the metal layer. A... Agent: Freescale Semiconductor, Inc. Law Department

20080258299 - Method of manufacturing a semiconductor device having an even coating thickness using electro-less plating, and related device: A method of manufacturing a semiconductor device includes forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity... Agent: Lee & Morse, P.C.

20080258298 - Semiconductor devices and methods of fabricating the same: Embodiments include a semiconductor device comprising: a pad formed on an insulating layer and having an electric connection region with external components; and a protective insulating layer which has an aperture for exposing the electric connection region. The protective insulating layer may include a first insulating layer and a second... Agent: Konrad Raynes & Victor, LLP

20080258300 - Wiring board manufacturing method, semiconductor device manufacturing method and wiring board: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and has a structure in which... Agent: Rankin, Hill & Clark LLP

20080258301 - Semiconductor device and manufacturing method of the same: A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring... Agent: Morrison & Foerster LLP

20080258302 - Methods of forming a denuded zone in a semiconductor wafer using rapid laser annealing: Methods for forming a denuded zone in an oxygen-containing semiconductor wafer using rapid laser annealing (RLA) are disclosed. The method includes scanning an intense beam of laser radiation over the surface of the wafer to raise the temperature of each point on the wafer surface to be at or near... Agent: Peters Verny , L.L.P.

20080258303 - Novel structure for reducing low-k dielectric damage and improving copper em performance: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a dielectric layer; a chemical mechanical polish (CMP) stop layer on the dielectric layer; a conductive wiring in the dielectric layer; and a metal cap over the conductive wiring.... Agent: Slater & Matsil, L.L.P.

20080258304 - Semiconductor device having multiple wiring layers: A semiconductor device includes: a substrate; and wiring layers on the substrate. Each wiring layer includes: an interlayer insulation film having a wiring groove with a via hole; a copper wiring in the groove and the hole; an barrier metal layer between an inner wall of the groove with the... Agent: Posz Law Group, PLC

20080258305 - Low fabrication cost, fine pitch and high reliability solder bump: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about... Agent: Mou-shiung Lin Room 301/302

20080258306 - Semiconductor device and method for fabricating the same: The present invention provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a chip having an active surface and an opposing non-active surface, wherein a plurality of bond pads are formed on the active surface, and first metal layers are formed on the bond... Agent: Wpat, PC Intellectual Property Attorneys

20080258307 - Integration type semiconductor device and method for manufacturing the same: A semiconductor device includes: a plurality of power MOS cells on a semiconductor substrate; a plurality of lead wires connecting to a source and a drain of each power MOS cell through a contact hole; a plurality of collecting electrodes connecting in parallel with the lead wires through a via... Agent: Posz Law Group, PLC

20080258308 - Method of controlled low-k via etch for cu interconnections: An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least... Agent: Katten Muchin Rosenman LLP

20080258310 - Semiconductor device having a tapered plug: A semiconductor device includes: first and second interlayer dielectric films consecutively deposited to overlie a silicon substrate; contact plugs penetrating the first interlayer dielectric film and having a top surface located within the second interlayer dielectric film; and via-plugs having a first portion, the diameter of which reduces from the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080258309 - Three-dimensional semiconductor device: A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface.... Agent: Slater & Matsil, L.L.P.

20080258311 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a first wiring layer, a second wiring layer and a third wiring layer. The first wiring layer is formed on a semiconductor substrate. The second and the third wiring layer wiring layers are arranged in a direction intersecting with the first wiring layer on respective sides... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080258312 - Semiconductor device: The present invention enhances the reliability of a semiconductor device. The semiconductor device includes a package substrate having a dry resist film which covers some conductive portions out of a plurality of conductive portions formed on a main surface and a back surface and is formed of a film, a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080258313 - Connecting microsized devices using ablative films: A method of providing connectivity to a microsized device, the method includes the steps of providing an ablative base material having at least a top surface; providing a die having a first and second surface and having bonding pads at least upon the first surface; placing the die with the... Agent: Frank Pincelli Patent Legal Staff

20080258314 - Fabric type semiconductor device package and methods of installing and manufacturing same: A fabric type semiconductor device package is provided. The fabric type semiconductor device package comprises a fabric type printed circuit board comprising a fabric and a lead unit formed by patterning a conductive material on the fabric, a semiconductor device comprising an electrode unit bonded to the lead unit of... Agent: Barry E. Negrin, Esq. Pryor Cashman LLP

20080258316 - Power semiconductor module: A power semiconductor module having a surface of the power semiconductor chip and an external circuit pattern connected by an aluminum wire, and sealed with an epoxy resin, wherein wire diameter of the aluminum wire is 0.4±0.05 mmφ, and coefficient of linear expansion of the epoxy resin in a rated... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080258315 - Semiconductor device and production method of the same semiconductor device: The present invention aims to provide a semiconductor device which can enhance area efficiency, and the semiconductor device includes a plurality of electroconductive member regions formed in a predetermined layer, an insulating film region which is formed in the insulating layer which is an upper layer of the predetermined layer... Agent: Young & Thompson

20080258317 - Semiconductor device: A resin layer covering a semiconductor chip on a wiring board is composed of a first resin layer and a second resin layer, wherein the first resin layer and the second resin layer differ in their plan view pattern, satisfying a relation of a<b, where “a” is difference in length... Agent: Young & Thompson

20080258318 - Semiconductor device: Disclosed herewith is a semiconductor device capable of suppressing the peeling-off that might occur between an island and a resin layer due to a difference of the shrinkage between those items, thereby the reliability of the semiconductor device is improved. The semiconductor device of the present invention includes an island,... Agent: Mcginn Intellectual Property Law Group, PLLC

20080251777 - Field effect device with a channel with a switchable conductivity: A field effect device includes a source electrode, a drain electrode, a channel formed between the source electrode and the drain electrode, and a gate electrode formed directly on the channel and arranged in a gap between the source electrode and the drain electrode. The channel includes a switching material... Agent: Ryan, Mason & Lewis, LLP

20080251778 - Four-terminal programmable via-containing structure and method of fabricating same: A semiconductor structure that includes two programmable vias each of which contains a phase change material that is integrated with a heating material. In particular, the present invention provides a structure in which two programmable vias, each containing a phase change material, are located on opposing surfaces of a heating... Agent: Scully, Scott, Murphy & Presser, P.C.

20080251779 - Apparatus of memory array using finfets: A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.... Agent: Schwegman, Lundberg & Woessner / Infineon

20080251780 - Light-emitting device and article: A device comprising a light transmissive element, a nano-wire light-emitting device, and a light transmissive controller communicating with the nano-wire light-emitting device. The nano-wire light-emitting device, and the light transmissive controller, are supported by the light transmissive element. An article includes two or more of the devices.... Agent: General Electric Company Global Research

20080251781 - Nitride semiconductor light emitting device: There is provided a nitride semiconductor light emitting device including: an n-type semiconductor region; an active layer formed on the n-type semiconductor region; a p-type semiconductor region formed on the active layer; an n-electrode disposed in contact with the n-type semiconductor region; a p-electrode formed on the p-type semiconductor region;... Agent: Mcdermott Will & Emery LLP

20080251782 - Random number generating device: The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080251783 - Random number generating device: The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080251785 - Display device and method of fabricating the same: A display device includes a thin film transistor (TFT) on a substrate, the TFT including source/drain electrodes, a cover layer on the source/drain electrodes, and a light source including at least one electrode, the electrode being electrically connected to the source/drain electrodes of the TFT through the cover layer, wherein... Agent: Lee & Morse, P.C.

20080251786 - Organic light emitting element and organic light emitting device: An organic light emitting element according to an exemplary embodiment includes: a first electrode; a hole injection layer contacting the first electrode; a first emission layer comprising at least two sublayers emitting different color lights and contacting the hole injection layer; a first impurity layer of a first conductive type... Agent: Macpherson Kwok Chen & Heid LLP

20080251784 - Organic semiconductor material, organic transistor, field effect transistor, switching device and thiazole compound: wherein B represents a unit having a thiazole ring, A1 and A2 each independently represent a unit having an alkyl group as a substituent, A3 represents a divalent linking group, nb represents an integer 1-20, n1 and n2 each independently represent an integer of 0-20, respectively, and n3 represents an... Agent: Cantor Colburn, LLP

20080251787 - Thin film transistor substrate and flat panel display comprising the same: A thin film transistor (TFT) substrate includes a TFT that including a gate electrode, a source electrode, and a drain electrode formed on an insulating substrate divided into a display area and a non-display area to provide test driving signals provided from the outside to the display area, a test... Agent: Mckenna Long & Aldridge LLP

20080251788 - Wafer-level package having test terminal: A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080251789 - Pixel structure and method for fabricating the same: A method for fabricating a pixel structure includes providing a substrate having a pixel area. A first metal layer, a gate insulator and a semiconductor layer are formed on the substrate and patterned by using a first half-tone mask or a gray-tone mask to form a transistor pattern, a lower... Agent: Jianq Chyun Intellectual Property Office

20080251790 - Pixel, a storage capacitor, and a method for forming the same: A pixel, a storage capacitor, and a method for forming the same. The storage capacitor formed on a substrate comprises a semiconductor layer, a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer. The semiconductor layer is formed on the substrate wherein the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080251791 - Thin film transistor substrate and method for fabricating same: An exemplary thin film transistor substrate (200) includes a base (201), a semiconductor pattern (202) formed on the base, a first gate insulating layer (203) formed on the semiconductor pattern, and a gate electrode (223) and a common capacitor electrode (245) formed on the first gate insulating layer. The semiconductor... Agent: Wei Te Chung Foxconn International, Inc.

20080251792 - Luminescent device and process of manufacturing the same: As the insulating films 117, 317 and 417 provided between TFT and EL element, a film containing a material for not only blocking the diffusion of an impurity ion such as an alkaline metal ion and an alkaline-earth metal ion but also aggressively absorbing an impurity ion such as an... Agent: Eric Robinson

20080251793 - Junction barrier schottky rectifiers having epitaxially grown p+-n junctions and methods of making: A junction barrier Schottky (JBS) rectifier device and a method of making the device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p+-n junctions and self-planarizing epitaxially over-grown second n-type drift regions between and, optionally, on top of the p-type regions. The... Agent: Morris Manning Martin LLP

20080251794 - Semiconductor light emitting device: The present invention provides a semiconductor light emitting device realizing lower detection level of spontaneous emission light by a semiconductor photodetector and improvement in light detection precision by selectively reflecting spontaneous emission light. The semiconductor light emitting device includes a semiconductor light emitting element for generating light including stimulated emission... Agent: Rader Fishman & Grauer PLLC

20080251795 - Photoelectric element package with temperature compensation: A photoelectric element package with temperature compensation includes a substrate, and a first light-emitting element, a second light-emitting element, a photosensitive element, and a drive element disposed on the substrate, all of which are disposed in an internal space formed by a first casing joined with a second casing. Alternatively,... Agent: Birch Stewart Kolasch & Birch

20080251797 - Array substrate and method for manufacturing the same: An array substrate is disclosed. The array substrate comprises a substrate, a gate metal layer, a gate insulation layer, a semiconductor layer, a patterned metal layer, a flat layer, and a pixel electrode. The patterned metal layer is disposed on the surface of the semiconductor layer comprising a source and... Agent: Bacon & Thomas, PLLC

20080251796 - Light emitting device and method of manufacturing the same: The present invention relates to a light emitting device and a method of manufacturing the light emitting device. According to the present invention, the light emitting device comprises a substrate, an N-type semiconductor layer formed on the substrate, and a P-type semiconductor layer formed on the N-type semiconductor layer, wherein... Agent: H.c. Park & Associates, PLC

20080251798 - Semiconductor device, led head and image forming apparatus: A semiconductor device is supplied which is able to efficiently liberate heat produced by semiconductor element toward external, prevent temperature rise, improve operation characteristic and maintain stable operation. The semiconductor device comprises a substrate and a semiconductor thin film layer which is accumulated on the substrate and contains semiconductor element,... Agent: Rabin & Berdo, PC

20080251799 - Light emitting device: A visible light emitting device includes: three types of LED elements stacked one on another; and first and second optical filters. Each of the LED elements has a light emitting layer configured to emit light of one of three primary colors. Each of the first and second optical filters is... Agent: Amin, Turocy & Calvin, LLP

20080251802 - Method for deposition of (al,in,ga,b)n: A method for growing an improved quality nitride thin film on a patterned substrate is disclosed, wherein the nitride film is grown at atmospheric pressure. A nitride template is disclosed, comprising a patterned substrate and a one or more nitride layer direct growth off of the patterned substrate, comprising no... Agent: Gates & Cooper LLP Howard Hughes Center

20080251801 - Method of producing group iii-v compound semiconductor, schottky barrier diode, light emitting diode, laser diode, and methods of fabricating the diodes: There are provided a method of producing a group III-V compound semiconductor, a Schottky barrier diode, a light emitting diode, a laser diode and methods of fabricating the diodes, that can achieve a reduced n type carrier density. The method of producing a group III-V compound semiconductor is a method... Agent: Drinker Biddle & Reath (dc)

20080251803 - Semiconductor light emitting device: Disclosed is a semiconductor light emitting device. The semiconductor light emitting device comprises a substrate comprising a reflective pattern with a valley, a first nitride semiconductor layer on the substrate, an air gap formed between the reflective pattern and the first nitride semiconductor layer, an active layer on the first... Agent: Birch Stewart Kolasch & Birch

20080251800 - Undoped and unintentionally doped buffer structures: A method of forming electronic device precursors and devices with reduced cracking in relevant layers is disclosed along with resulting structures. The method includes the steps of growing a transition layer of undoped Group III nitride on a substrate that is other than a Group III nitride, growing an active... Agent: Summa, Allan & Additon, P.A.

20080251804 - Nitride semiconductor light-emitting device: A nitride semiconductor light-emitting device includes a p-type contact layer, a p-type intermediate layer below the p-type contact layer, and a p-type cladding layer below the p-type intermediate layer. Band gap energy differences between the p-type contact layer and the p-type intermediate layer and also between the p-type intermediate layer... Agent: Leydig Voit & Mayer, Ltd

20080251805 - Heat dissipation package for heat generation element: A heat dissipation package is provided. Conducting leads of the package are located between two dissipating parts of a heat dissipation carrier to form the heat dissipation package with a structure of heat outside and electricity inside. Consequently, there is no limitation caused by electrical elements surrounding the heat dissipation... Agent: Jianq Chyun Intellectual Property Office

20080251806 - Patterned light emitting devices: Light-emitting devices, and related components, systems and methods are disclosed. A light-emitting device can include a multi-layer stack of materials including a light-generating region and a first layer supported by the light-generating region. During use of the light-emitting device, light generated by the light-generating region can emerge from the light-emitting... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.C.

20080251807 - Semiconductor light emitting device and method for manufacturing the same: Disclosed are a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises a substrate, in which concave-convex patterns are in at least a portion of a backside of the substrate, and a light emitting structure on the substrate and comprising a first... Agent: Birch Stewart Kolasch & Birch

20080251808 - Semiconductor light-emitting device, method for manufacturing the same, and light-emitting apparatus including the same: A nitride semiconductor light-emitting device includes a layered portion emitting light on a substrate. The layered portion includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The periphery of the layered portion is inclined, and the surface of the n-type semiconductor layer is exposed at the... Agent: Smith Patent Office

20080251809 - Light-emitting diode: Light-emitting diode (LED) comprising a translucent substrate of α-Al2O3 or SiC and a first layer of a light-emitting semiconductor material grown on a first side of said substrate, a first electrode and a second electrode, wherein said substrate is polycrystalline. The average grain size of the polycrystalline substrate is preferably... Agent: Philips Intellectual Property & Standards

20080251810 - Trenched semiconductor device: An IGBT is disclosed which has a set of inside trenches and an outside trench formed in its semiconductor substrate. The substrate has emitter regions adjacent the trenches, a p-type base region adjacent the emitter regions and trenches, and an n-type base region comprising a first and a second subregion... Agent: Woodcock Washburn LLP

20080251811 - Semiconductor device: An n− type semiconductor region is provided with an n− diffusion region serving as a drain region, and at one side of the n− diffusion region a p diffusion region and an n+ diffusion region serving as a source region are provided. At an other side of the n− diffusion... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080251812 - Heteroepitaxial crystal quality improvement: Methods and systems for improving heteroepitaxial crystal quality of semiconductor materials include forming a pattern on the semiconductor substrate over which the hetero-epitaxial layer is grown. The pattern provides predetermined sites for dislocation initiation and termination of dislocation propagation. The layer may be treated with a focused laser beam during... Agent: Macpherson Kwok Chen & Heid LLP

20080251813 - Hetero-integrated strained silicon n- and p- mosfets: The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions... Agent: Scully, Scott, Murphy & Presser, P.C.

20080251814 - Hetero-bonded semiconductor-on-insulator substrate with an unpinning dielectric layer: A hetero-bonded SOI substrate comprises a stack of a semiconductor handle substrate, an isolation insulator layer, a depinning dielectric layer, and a top non-silicon semiconductor layer. The depinning layer abuts both the top non-silicon semiconductor layer and the isolation insulator layer and relaxes Fermi level pinning in the top non-silicon... Agent: Scully, Scott, Murphy & Presser, P.C.

20080251815 - Method for manufacturing a transistor: The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.... Agent: Fay Kaplun & Marcin, LLP

20080251816 - Semiconductor memory device and method for fabricating the same: A semiconductor memory device is composed of a field effect transistor using the interface between a ferroelectric film and a semiconductor film as the channel and including a gate electrode to which a voltage for controlling the polarization state of the ferroelectric film is applied and source/drain electrodes provided on... Agent: Mcdermott Will & Emery LLP

20080251817 - Stressed field effect transistors on hybrid orientation substrate: A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has... Agent: Scully, Scott, Murphy & Presser, P.C.

20080251818 - Low noise jfet: Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely... Agent: Texas Instruments Incorporated

20080251819 - Semiconductor device and method of manufacturing the same: A semiconductor device may include a semiconductor substrate, a diffusion layer provided over the semiconductor substrate, source and drain diffusion regions provided in upper regions of the diffusion layer, a gate insulating film provided over the source and drain diffusion regions and the diffusion layer, a gate electrode provided on... Agent: Sughrue Mion, PLLC

20080251820 - Cmos image sensor and fabricating method thereof: A fabricating method of a CMOS image sensor includes the steps of: forming a transfer gate on a semiconductor substrate where a device isolation layer is formed; forming a first n- type ion implantation region for a photodiode beneath a surface of the semiconductor substrate, the first n-type ion implantation... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080251822 - Amplification-type solid-state image sensing device: According to an aspect of the invention, there is provided an amplification-type solid-state image sensing device which uses a semiconductor substrate formed by epitaxially depositing an n-type semiconductor layer on a p-type semiconductor substrate and has a photoelectric conversion unit formed in the n-type semiconductor layer including a first p-type... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080251821 - Method and device to reduce dark current in image sensors: A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel area and a logic area, forming a light sensing element in the pixel area, and forming a first transistor in the pixel area and a second transistor in the logic area. The step of forming... Agent: Haynes And Boone, LLP

20080251823 - Separation type unit pixel having 3d structure for image sensor and manufacturing method thereof: A separation type unit pixel of an image sensor, which can handle light that incidents onto a photodiode at various angles, and provides a zoom function in a mini camera module by securing an incident angle margin, and a manufacturing method thereof are provided. The separation type unit pixel having... Agent: Cantor Colburn, LLP

20080251824 - Semiconductor memory device and manufacturing method thereof: A semiconductor memory device and a manufacturing method thereof are provided which enable cell-contact plugs to be formed at high yields and the yields of semiconductor memory devices to be improved in the manufacturing process. The semiconductor memory device includes: a semiconductor substrate; MOS transistors which are formed on a... Agent: Mcginn Intellectual Property Law Group, PLLC

20080251825 - Pillar-type field effect transistor having low leakage current: A pillar-type field effect transistor having low leakage current is provided. The pillar-type field effect transistor includes a semiconductor pillar, a gate insulating layer formed on a portion of a surface of the semiconductor pillar, a gate electrode formed on the gate insulating layer, and source/drain regions formed on portions... Agent: The Rafferty Patent Law Firm

20080251827 - Checkerboard deep trench dynamic random access memory cell array layout: A checkerboard deep trench dynamic random access memory cell array layout is disclosed, which includes a substrate, a plurality of gate conductor lines disposed on the substrate, a plurality of checkerboard-arranged and staggered deep trench capacitor structures embedded in the substrate under the gate conductor lines, and a plurality of... Agent: North America Intellectual Property Corporation

20080251826 - Multi-layer semiconductor structure and manufacturing method thereof: A method for manufacturing a multi-layer semiconductor structure is disclosed. First, a first wafer comprising a first semiconductor device structure and a second wafer comprising a substrate and a single crystal silicon layer are provided, and the first and second wafers are combined in which a surface of the first... Agent: Wpat, PC Intellectual Property Attorneys

20080251828 - Enhanced atomic layer deposition: A method of enhanced atomic layer deposition is described. In an embodiment, the enhancement is the use of plasma. Plasma begins prior to flowing a second precursor into the chamber. The second precursor reacts with a prior precursor to deposit a layer on the substrate. In an embodiment, the layer... Agent: Schwegman, Lundberg & Woessner, P.A.

20080251829 - Memory device and fabrication method thereof: A fabrication method of a memory device is disclosed. A substrate having a trench is provided, comprising a trench capacitor, a conductive column, a collar dielectric layer and a top dielectric layer therein. A gate structure with spacers on sidewalls is disposed on the substrate and neighboring the trench. An... Agent: Quintero Law Office, PC

20080251830 - Semiconductor storage device and driving method thereof: This disclosure concerns a semiconductor storage device comprising a semiconductor layer provided on the insulation layer provided on the semiconductor substrate; a source layer and a drain layer provided in the semiconductor layer; a body provided between the source layer and the drain layer, the body being in an electrically... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080251832 - Logic compatible arrays and operations: An array of memory cells arranged in a plurality of rows and a plurality of columns are provided. The array includes a first program line in a first direction, wherein the first program line is connected to program gates of memory cells in a first row of the array; a... Agent: Slater & Matsil, L.L.P.

20080251831 - Semiconductor structure and process for reducing the second bit effect of a memory device: A non-volatile memory cell capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in association with at least one electrical dielectric layer, such as an oxide, with a P-type substrate and an N-type channel implanted in the well region of the... Agent: Akin Gump LLP - Silicon Valley

20080251833 - Integrated circuits and methods of manufacture: In various embodiments of the invention, integrated circuits and methods of manufacturing integrated circuits are provided. In an embodiment of the invention, an integrated circuit having at least one memory cell is provided. The memory cell includes a dielectric layer disposed above a charge storage region, a word line disposed... Agent: Slater & Matsil, L.L.P.

20080251834 - Non-volatile semiconductor memory device and its manufacturing method: In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon... Agent: Hogan & Hartson L.L.P.

20080251835 - Semiconductor memory device with charge traps: A memory cell in a semiconductor memory device has a pair of charge traps formed on opposite sides of a control electrode, above variable resistance regions in the semiconductor substrate. Each charge trap includes a tunnel oxide film, a dual-layer charge trapping film, and a top oxide film. The dual-layer... Agent: Rabin & Berdo, PC

20080251836 - Non-volatile memory device and method for fabricating the same: A method for fabricating a non-volatile memory device includes forming a charge tunneling layer composed of a hafnium silicate (HfSixOyNz) layer on a semiconductor substrate. A charge trapping layer composed of a hafnium oxide nitride (HfOxNy) layer is formed on the charge tunneling layer. A charge blocking layer composed of... Agent: Townsend And Townsend And Crew, LLP

20080251837 - Semiconductor device and manufacturing method thereof: A semiconductor device which includes both an E-FET and a D-FET and can facilitate control of the Vth in an E-FET and suppress a decrease in the Vf, and a manufacturing method of the same are provided. A semiconductor device which includes both an E-FET and a D-FET on the... Agent: Greenblum & Bernstein, P.L.C

20080251838 - Semiconductor device: A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080251840 - Electronically scannable multiplexing device: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control... Agent: Fleit, Kain, Gibbons, Gutman, Bongini & Bianco P.l

20080251839 - Semiconductor device and method for fabricating the same: A semiconductor device comprises a fin-type active region defined by a semiconductor substrate having a device isolation structure, a recess formed over the fin-type active region, and a gate electrode including a silicon germanium (Si1-xGex) layer for fill the recess (where 0<X<1 and X is a Ge mole fraction).... Agent: Townsend And Townsend And Crew, LLP

20080251841 - Mos transistor and manufacturing method thereof: The structure of the MOS transistor provided in this invention has LDD (lightly doped drain) and halo doped regions removed from the source, the drain or both regions in the substrate for improved linearity range when operated as a voltage-controlled resistor. The removal of the LDD and halo doped regions... Agent: North America Intellectual Property Corporation

20080251844 - Method for forming pattern, method for manufacturing semiconductor device and semiconductor device: A method for forming a pattern includes the step of forming an electrically conductive film by applying a liquid composition onto a first plate. The liquid composition includes an organic solvent and conductive particles surface-modified with a fatty acid or an aliphatic amine. Then, a second pattern, which is a... Agent: Sonnenschein Nath & Rosenthal LLP

20080251842 - P-channel fet whose hole mobility is improved by applying stress to the channel region and a method of manufacturing the same: A p-channel FET which has a buried insulating film in the noncontact part of each of the source/drain regions has been disclosed. Compressional stress produced by volume expansion at the time of oxidization for the formation of the buried oxide films is applied to the channel region of the FET.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080251845 - Semiconductor device and manufacturing method thereof: Manufacture of TFTs corresponding to various circuits makes structures thereof complex, which involves a larger number of manufacturing steps. Such an increase in the number of the manufacturing steps leads to a higher manufacturing cost and a lower manufacturing yield. In the invention, a high concentration of impurities is doped... Agent: Cook Alex Ltd

20080251843 - Semiconductor memory device and manufacturing method thereof: This disclosure concerns a semiconductor memory device including a substrate; an insulating film provided above the substrate; a semiconductor layer provided above the insulating film and extending in a plane which is parallel to a surface of the substrate; a first gate dielectric film provided on an inner wall of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080251846 - Method and structure for low capacitance esd robust diodes: A diode having a capacitance below 0.1 pF and a breakdown voltage of at least 500V. The diode has an anode of a first conductivity type and a cathode of a second conductivity type disposed below the anode. At least one of the cathode and anode have multiple, vertically abutting... Agent: International Business Machines Corporation Intellectual Property Law

20080251848 - Manufacturing method for homogenizing the environment of transistors and associated device: A semiconductor device is provided that includes a plurality of patterns. Each pattern includes at least one field effect transistor. Each field effect transistor includes a source region, a drain region, a channel region, and a gate region formed above the channel region. A portion of the plurality of patterns... Agent: Docket Clerk

20080251847 - Memory cell array in a semiconductor memory device: A memory cell array in a semiconductor device includes a semiconductor substrate having active areas and isolation areas in parallel, a plurality of select lines having generally a U like shape and is configured to cross over the active areas and the isolation areas, and a plurality of word lines... Agent: Lowe Hauptman Ham & Berner, LLP

20080251850 - Pmd liner nitride films and fabrication methods for improved nmos performance: Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in ail or a portion of the NMOS transistor to improve carrier mobility. The nitride layer (130) is initially deposited over the transistors at low... Agent: Texas Instruments Incorporated

20080251849 - Semiconductor device and method for manufacturing same: (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel... Agent: Young & Thompson

20080251852 - E-fuse and method: An e-fuse circuit, a method of programming the e-fuse circuit, and a design structure of the e-fuse circuit. The method includes in changing the threshold voltage of one selected field effect transistor of two field effect transistors connected to different storage nodes of the circuit so as to predispose the... Agent: Schmeiser, Olsen & Watts

20080251851 - Strain enhanced semiconductor devices and methods for their fabrication: A strain enhanced semiconductor device and methods for its fabrication are provided. One method comprises embedding a strain inducing semiconductor material in the source and drain regions of the device to induce a strain in the device channel. Thin metal silicide contacts are formed to the source and drain regions... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080251853 - Structure and method to optimize strain in cmosfets: A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N... Agent: Scully, Scott, Murphy & Presser, P.C.

20080251854 - Semiconductor device: In one aspect of the present invention, semiconductor device, may include a p-channel semiconductor active region, an n-channel semiconductor active region, an element isolation insulating layer which electrically isolates the p-channel semiconductor active region from the n-channel semiconductor active region, and an insulating layer made of a material different from... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080251855 - Low contact resistance cmos circuits and methods for their fabrication: A low contact resistance CMOS integrated circuit and method for its fabrication are provided. The CMOS integrated circuit comprises a first transition metal electrically coupled to the N-type circuit regions and a second transition metal different than the first transition metal electrically coupled to the P-type circuit regions. A conductive... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080251856 - Forming silicided gate and contacts from polysilicon germanium and structure formed: Methods of forming silicided contacts self-aligned to a gate from polysilicon germanium and a structure so formed are disclosed. One embodiment of the method includes: forming a polysilicon germanium (poly SiGe) pedestal over a gate dielectric over a substrate; forming a poly SiGe layer over the poly SiGe pedestal, the... Agent: Hoffman Warnick LLC

20080251857 - Semiconductor device with improved contact pad and method for fabrication thereof: A semiconductor device and method of its manufacture is disclosed. The device comprises an active semiconductor region (1A) comprising one or more conductive gates (11) and a contact region (1 B) remote from the active region (1A), typically comprising a field oxide region (3). An insulating layer (17) overlies the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080251858 - Field effect transistor and method for manufacturing the same: A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate... Agent: Ladas & Parry LLP

20080251859 - Semiconductor module: A component includes a first semiconductor chip attached to a first carrier and second semiconductor chip attached to a second carrier. The first carrier has a first extension, which forms a first external contact element. The second carrier has a second extension, which forms a second external contact element. The... Agent: Slater & Matsil LLP

20080251860 - Semiconductor memory device: The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode... Agent: Mcdermott Will & Emery LLP

20080251862 - Accumulation field effect microelectronic device and process for the formation thereof: A gated microelectronic device is provided that has a source with a source ohmic contact with the source characterized by a source dopant type and concentration. A drain with a drain ohmic contact with the drain characterized by a drain dopant type and concentration. An intermediate channel portion characterized by... Agent: Gifford, Krass, Sprinkle,anderson & Citkowski, P.c

20080251861 - Semiconductor apparatus and production method of the same: In order to provide a semiconductor apparatus and a production method of the semiconductor apparatus that achieves a small interface trap density by implantation of fluorine and that achieves both small property fluctuation and a small leak current, a semiconductor apparatus includes: a semiconductor substrate; a well layer formed on... Agent: Sughrue Mion, PLLC

20080251863 - High-voltage radio-frequency power device: A high-voltage RF power device includes a plurality of serially connected transistors. Each transistor includes a gate finger disposed on a substrate, a gate dielectric layer, a drain structure disposed on one side of the gate finger, and an N+ source region on the other side of the gate finger.... Agent: North America Intellectual Property Corporation

20080251864 - Stacked poly structure to reduce the poly particle count in advanced cmos technology: A method for implementing a stacked gate, comprising forming a gate dielectric on a semiconductor body, forming a first layer of gate electrode material on the gate dielectric, forming a second layer of gate electrode material on the first layer of gate electrode material, wherein the grain size distribution of... Agent: Texas Instruments Incorporated

20080251865 - Nanoelectromechanical systems and methods for making the same: Nanoelectromechanical systems are disclosed that utilize vertically grown or placed nanometer-scale beams. The beams may be configured and arranged for use in a variety of applications, such as batteries, generators, transistors, switching assemblies, and sensors. In some generator applications, nanometer-scale beams may be fixed to a base and grown to... Agent: Ropes & Gray LLP

20080251866 - Low-stress hermetic die attach: A low-stress hermetic die attach apparatus is disclosed. An example apparatus includes a hermetic package, a device disposed within the hermetic package, and one or more elongated structures greater than 2 thousandths of an inch (mils) in length connected to the package at one end and to the device at... Agent: Honeywell International Inc. Patent Services Ab-2b

20080251867 - Nanowire magnetic random access memory: An integrated array of non volatile magnetic memory devices, each having a first magnetic layer (10) with a fixed magnetization direction; a free magnetic layer (20) with a changeable magnetization direction; a spacer layer (30) separating the first magnetic layer and the free magnetic layer, and a switch (40) for... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080251868 - Standard component for calibration and electron-beam system using the same: The invention provides a standard component for calibration that enables a calibration position to be easily specified in order to calibrate accurately a scale factor in the electron-beam system, and provides an electron-beam system using it. High-accuracy metrology calibration capable of specifying a calibration position can be realized by forming... Agent: Stanley P. Fisher Reed Smith LLP

20080251870 - Detector for detecting electromagnetic waves: A detector for detecting electromagnetic waves, the detector having an antenna for receiving the electromagnetic waves, a semiconductor element, wherein a termination section of the semiconductor element establishes a termination resistor of the antenna, wherein the termination section is provided for heating a temperature-sensitive part of the semiconductor element, wherein... Agent: Ibm Microelectronics Intellectual Property Law

20080251872 - Image sensor package, method of manufacturing the same, and image sensor module including the image sensor package: An image sensor package, a method of manufacturing the same, and an image sensor module including the image sensor package are provided. In the image sensor package, an image sensor chip is installed onto a depression of a transmissive substrate. An adhesive bonds the image sensor chip to the transmissive... Agent: Marger Johnson & Mccollom, P.C.

20080251869 - Photosensitive chip package: A photosensitive chip package includes a substrate on which a photosensitive chip having a photo-active zone and a photo-inactive zone surrounding the photo-active zone is bonded. A light-transmissive film covers the photo-active zone of the photosensitive chip. Bonding wires are electrically connected with the photosensitive chip and the substrate. An... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080251871 - Semiconductor fabrication method and system: Embodiments of the present invention are generally directed to a method for manufacturing a semiconductor device. In one embodiment, the method includes providing a substrate that includes a via or interconnect. In this embodiment, the method also includes forming a sealed array, in which forming such an array includes attaching... Agent: Fletcher Yoder (micron Technology, Inc.)

20080251874 - Solid-state image capturing device, method for the same, and electronic information device: A solid-state image capturing device according to the present invention is provided, in which a plurality of conductive films is formed via respective insulation films, and an optical waveguide is formed above a light receiving section, a plurality of light receiving sections is provided in a surface portion of a... Agent: Edwards Angell Palmer & Dodge LLP

20080251873 - Solid-state imaging device, manufactoring method thereof and camera: A color filter in a solid-state imaging device 1 having an optical film thickness of approximately ¼ of a set wavelength λ, being sandwiched by a third layer and a fourth layer which are spacer layers in which only 3 layers are laminated and which consist of two types of... Agent: Greenblum & Bernstein, P.L.C

20080251875 - Semiconductor package: An exemplary semiconductor package includes a substrate, at least one passive component, an insulative layer and a chip. The substrate defines a cavity therein. The at least one passive component is disposed within the cavity, and is electrically connected to the substrate. The insulative layer is received in the cavity,... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang

20080251876 - Photoreceiver cell with color separation: A photoreceiver cell with separation of color components of light incident to its surface, formed in a silicon substrate of the conductivity of the first type with an ohmic contact and comprising: the first, second and third regions, which have mutual positioning and configuration, which provide formation of the first... Agent: Macpherson Kwok Chen & Heid LLP

20080251877 - Methods for fabricating complex micro and nanoscale structures and electronic devices and components made by the same: This invention provides processing steps, methods and materials strategies for making patterns of structures for electronic, optical and optoelectronic devices. Processing methods of the present invention are capable of making micro- and nano-scale electronic structures, such as T-gates, gamma gates, and shifted T-gates, having a selected non-uniform cross-sectional geometry. The... Agent: Greenlee Winner And Sullivan P C

20080251879 - Method for manufacturing simox substrate and simox substrate obtained by this method: The present invention comprises: a step of implanting oxygen ions into a wafer; a step of performing a first heat treatment to the wafer in a predetermined gas atmosphere at 1300 to 1390° C. to form a buried oxide layer and also form an SOI layer on a wafer front... Agent: Duane Morris LLP Patent Department

20080251880 - Mixed orientation and mixed material semiconductor-on-insulator wafer: The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations.... Agent: Snell & Wilmer LLP (oc)

20080251881 - Semiconductor device with double barrier film: A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080251878 - Structure incorporating semiconductor device structures for use in sram devices: Device structures embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes static random access memory (SRAM) devices. The design structure includes a dielectric region disposed between first and second semiconductor regions and a gate conductor structure extending between the first... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080251882 - Semiconductor device and method of fabricating the same: A semiconductor device includes a first insulating isolation film provided on a main surface of a semiconductor substrate, an active region surrounded by the first insulating isolation film, and a second insulating isolation film provided on the main surface of the semiconductor substrate, having a thickness smaller than that of... Agent: Mcdermott Will & Emery LLP

20080251883 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate formed with a plurality of first element isolation trenches having respective first opening widths and a plurality of second element isolation trenches having larger opening widths than the first opening widths, element isolation insulating films buried in the first element isolation trenches so... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080251886 - Fuse structure, and semiconductor device: A fuse structure includes a reference power layer disposed between first and second resistance-variable material layers. The first and second resistance-variable material layer may at least partially overlap each other in plan view. First and second insulating layers are disposed over and under the first and second resistance-variable material layers.... Agent: Mcginn Intellectual Property Law Group, PLLC

20080251885 - Fuse structure, semiconductor device, and method of forming the semiconductor device: There are provided a fuse structure and a semiconductor device having the fuse structure. The fuse structure includes an insulating layer having a hole, a resistance-variable material layer disposed on inner wall of the hole, a reference power layer that covers the resistance-variable material layer, and a plurality of leads... Agent: Mcginn Intellectual Property Law Group, PLLC

20080251884 - Method and system for controlling multiple electrical fuses with one program device: A fuse circuit comprising one or more one-time programmable electrical fuses; one or more unidirectional conductive devices each coupled to one of the fuses; a programming device coupled to the unidirectional conductive devices; and a selection module coupled to the electrical fuses for selecting a predetermined electrical fuse, wherein upon... Agent: K & L Gates LLP

20080251887 - Serial system for blowing antifuses: A serial system and method for blowing antifuses are disclosed. One embodiment of antifuse system includes a plurality of latch devices connected in series from input to output. The system also includes a plurality of antifuses. The antifuses are configured to receive an output signal from a corresponding one of... Agent: Knobbe Martens Olson & Bear LLP

20080251888 - Method and apparatus for self-contained automatic decoupling capacitor switch-out in integrated circuits: An integrated circuit (IC) includes power supply interconnects that couple to a power source. The integrated circuit includes electronic devices that perform desired functions and further includes decoupling capacitor circuits that provide noise reduction throughout the integrated circuit. In one embodiment, each decoupling capacitor circuit includes a decoupling capacitor and... Agent: Mark P. Kahler

20080251889 - Semiconductor device: A semiconductor device is disclosed. The device includes a substrate, a first metal layer, a dielectric layer, and a second metal layer. The first metal layer comprises a body-centered cubic lattice metal, and overlies the substrate. The dielectric layer overlies the first metal layer. The second metal layer overlies the... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080251890 - Method of forming buffer layer for nitride compound semiconductor light emitting device and nitride compound semiconductor light emitting device having the buffer layer: A method of forming a buffer layer for a nitride compound semiconductor light emitting device includes placing a sapphire (Al2O3) substrate in a reaction chamber; introducing a nitrogen source gas into a reaction chamber; and annealing the substrate in a state where the nitrogen source gas is introduced into the... Agent: H.c. Park & Associates, PLC

20080251891 - Semiconductor having passivated sidewalls: The layers of a semiconductor device have exposed edges. The layers that are susceptible to oxidation are protected from oxidation by coating them with a nitride passivation layer. The nitride passivation layer can be applied using plasma enhanced chemical vapor deposition (PECVD). A method of making a passivated sidewall semiconductor... Agent: Patti, Hewitt & Arezina LLC

20080251892 - Insulating film for semiconductor integrated circuit: The present invention relates to a polymeric compound comprising, as structural units, groups each represented by the following general formula (1); and an insulating film for a semiconductor integrated circuit which comprises the polymeric compound: —R1—C≡C—C≡C—, wherein R1 represents a group having a cage-shaped structure. The insulating film has a... Agent: Sughrue Mion, PLLC

20080251894 - Mounted body and method for manufacturing the same: A mounted body (100) of the present invention includes: a semiconductor element (10) having a surface (10a) on which element electrodes (12) are formed and a rear surface (10b) opposing the surface (10a); and a mounting board (30) on which wiring patterns (35) each having an electrode terminal (32) are... Agent: Hamre, Schumann, Mueller & Larson P.C.

20080251893 - Mounting clips for use with electromagnetic interference shielding and methods of using the same: According to various aspects, exemplary embodiments are provided of clips that may be compatible with surface mount technology. The clips may be surface mountable to a substrate for allowing repeated releasable attachment and detachment of a shielding structure thereto. In one exemplary embodiment, a clip generally includes a base member... Agent: Harness, Dickey, & Pierce, P.l.c

20080251895 - Apparatus for shielding integrated circuit devices: A high reliability radiation shielding integrated circuit apparatus comprising a plurality of package layers; a radiation shielding lid or base coupled to the plurality of package layers; wherein the circuit die are shielded from receiving an amount of radiation greater than the total dose of tolerance of the circuit die.... Agent: Maxwell Technologies, Inc.

20080251896 - Method of manufacturing a coaxial trace in a surrounding material, coaxial trace formed thereby, and semiconducting material containing same: A method of manufacturing a coaxial trace (100) within a surrounding material (190) includes: providing a first substrate (191, 410) and a second substrate (192, 1010) composed of the surrounding material; forming a first portion (101, 601) of the coaxial trace in the first substrate; forming a second portion (102,... Agent: Intel Corporation C/o Intellevate, LLC

20080251897 - Semiconductor device: In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control... Agent: Miles & Stockbridge PC

20080251898 - Semiconductor device: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that... Agent: Hamre, Schumann, Mueller & Larson P.C.

20080251899 - Semiconductor device: Provided is a semiconductor device in which a plurality of chips are packaged without increasing the thickness of the package. A plurality of semiconductor elements (a first and a second semiconductor elements) that are packaged in the semiconductor device are overlaid with each other. Specifically, the first semiconductor element is... Agent: Fish & Richardson P.C.

20080251900 - Conductor frame for an electronic component and method for the production thereof: Disclosed is a leadframe for at least one electronic component, comprising at least two electrical lead elements, each of which comprises at least one electrical lead tab and at least one retention tab. Provided between the at least one retention tab and the lead element is a score defining a... Agent: Fish & Richardson PC

20080251902 - Plastic package and method of fabricating the same: A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal... Agent: Oliff & Berridge, PLC

20080251901 - Stacked integrated circuit package system: A stacked integrated circuit package system is provided providing a lead frame having a die paddle, attaching a first integrated circuit on the die paddle of the lead frame, connecting first electrical interconnects between the first integrated circuit and the lead frame, encapsulating the first integrated circuit and the first... Agent: Law Offices Of Mikio Ishimaru

20080251903 - Semiconductor module: A module having a semiconductor chip with a first contact element on a first main surface and a second contact element on a second main surface is disclosed. The semiconductor chip is arranged on a carrier. An insulating layer and a wiring layer cover the second main surface and the... Agent: Dicke, Billig & Czaja

20080251904 - Curing layers of a semiconductor product using electromagnetic fields: A semiconductor product including a substrate, a semiconductor chip fitted to the substrate, and a layer, which contains coated particles, located adjacent to the semiconductor chip, wherein the coated particles have a ferromagnetic, ferrimagnetic or paramagnetic core and a coating.... Agent: Dickstein Shapiro LLP

20080251905 - Package-on-package secure module having anti-tamper mesh in the substrate of the upper package: A package-on-package (POP) secure module includes a first ball grid array (BGA) package, and a second BGA package. The first BGA includes an array of bond balls that is disposed on a side of a substrate member, and an array of lands that is disposed on the opposite side of... Agent: Imperium Patent Works

20080251906 - Package-on-package secure module having bga mesh cap: A package-on-package (POP) secure module includes a BGA mesh cap, a first BGA package, and a second BGA package. The first BGA package includes a first integrated circuit (for example, a microcontroller that includes tamper detect logic). The second BGA package includes a second integrated circuit (for example, a memory).... Agent: Imperium Patent Works

20080251907 - Electronic device with stress relief element: p

20080251908 - Semiconductor device package having multi-chips with side-by-side configuration and method of the same: The present invention provides a semiconductor device package with the die receiving through hole and connecting through hole structure comprising a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad. A die is disposed within the die receiving through hole. An adhesion... Agent: Bacon & Thomas, PLLC

20080251909 - Power semiconductor module for inverter circuit system: A double-face-cooled semiconductor module with an upper arm and a lower arm of an inverter circuit includes first and second heat dissipation members, each having a heat dissipation surface on one side and a conducting member formed on another side through an insulation member. On the conducting member on the... Agent: Crowell & Moring LLP Intellectual Property Group

20080251910 - Fabricating method of semiconductor package and heat-dissipating structure applicable thereto: A method for fabricating semiconductor packages is disclosed, including mounting and electrically connecting a semiconductor chip onto a chip carrier; mounting a heat-dissipating structure on the semiconductor chip; placing the heat-dissipating structure into a mold cavity for filling therein a packaging material to form an encapsulant, wherein the heat-dissipating structure... Agent: Edwards Angell Palmer & Dodge LLP

20080251911 - System and method having evaporative cooling for memory: A system, in one embodiment, may include an in-line memory module with a plurality of memory circuits disposed on a circuit board, wherein the circuit board may have an edge connector with a plurality of contact pads. The system also may include a heat spreader disposed along the plurality of... Agent: Hewlett Packard Company

20080251912 - Multi-chip module: A multi-chip module includes at least one integrated circuit chip that is electrically connected to first external terminals of the multi-chip module and at least one power semiconductor chip that is electrically connected to second external terminals of the multi-chip module. All first external terminals of the multi-chip module are... Agent: Slater & Matsil, L.L.P.

20080251914 - Semiconductor device: In a structure for connecting a semiconductor element having a fine pitch electrode at 50 pm pitch or less and a pad or wirings on a substrate, for preventing inter-bump short-circuit or fracture of a connected portion due to high strain generated upon heating or application of load during connection,... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080251913 - Semiconductor device including wiring substrate having element mounting surface coated by resin layer: In one embodiment of the present invention, there is provided a semiconductor device including a first semiconductor element mounted, through flip-chip bonding, on the element mounting surface of a first wiring substrate, and a resin layer that coats substantially the entire element mounting surface of the first wiring substrate. The... Agent: Young & Thompson

20080251915 - Structure of semiconductor chip and package structure having semiconductor chip embedded therein: A semiconductor chip is disclosed, which comprises a chip having an active surface; plural electrode pads disposed on the active surface of the chip; a first passivation layer disposed on the chip, which has openings corresponding to the electrode pads to expose the electrode pads, wherein the first passivation layer... Agent: Bacon & Thomas, PLLC

20080251917 - Solder pad and method of making the same: A solder pad structure includes a first metal layer disposed on an insulation layer, wherein the first metal layer is electrically connected with an underlying interconnection circuit layer through a conductive through hole disposed in the insulation layer. A solder resist layer having an opening exposing a central portion of... Agent: North America Intellectual Property Corporation

20080251916 - Ubm structure for strengthening solder bumps: A novel UBM structure for improving the strength and performance of individual UBM layers in a UBM structure is disclosed. In one aspect, a UBM structure for disposal onto an electrically conductive element comprised of aluminum is disclosed. In one embodiment, the UBM structure comprises a tantalum layer disposed over... Agent: Baker & Mckenzie On Behalf Of Tsmc

20080251918 - Wire bonds having pressure-absorbing balls: A semiconductor device with a chip having at least one metallic bond pad (101) over weak insulating material (102). In contact with this bond pad is a flattened metal ball (104) made of at least 99.999% pure metal such as gold, copper, or silver. The diameter (104a) of the flattened... Agent: Texas Instruments Incorporated

20080251920 - Dielectric film forming method: In a film forming sequence for a HDP-CVD oxide film, Ar gas is introduced into a reactive chamber and then source power (or RF power) is applied to excite plasma. After that, a carrier gas (He) is introduced into the reactive chamber. After a semiconductor substrate is heated by plasma... Agent: Foley And Lardner LLP Suite 500

20080251921 - Structure for a semiconductor device and a method of manufacturing the same: There is described a method of manufacturing a damascene interconnect (1) for a semiconductor device. A non conductive diffusion barrier (10) is formed over the wall(s) of a passage (7) defined by a porous low K di-electric material (6) and over the surface of a copper region (3) that closes... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080251919 - Ultra-low resistance interconnect: A method for fabricating a semiconductor interconnect device. A preferred embodiment comprises forming a low-k or very low-k dielectric layer on a wafer substrate and forming a recess in the dielectric layer that exposes a region on the substrate to which electrical contact is desired. A barrier layer is formed... Agent: Slater & Matsil, L.L.P.

20080251922 - Transitional interface between metal and dielectric in interconnect structures: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal... Agent: Slater & Matsil, L.L.P.

20080251924 - Post passivation interconnection schemes on top of the ic chips: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a... Agent: Mou-shiung Lin

20080251923 - Seal ring structures with reduced moisture-induced reliability degradation: A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an... Agent: Slater & Matsil, L.L.P.

20080251925 - Top layers of metal for integrated circuits: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses... Agent: Mou-shiung Lin Room 301/302

20080251926 - Method of fabricating organic silicon film, semiconductor device including the same, and method of fabricating the semiconductor device: An organic silicon film is formed by carrying out chemical vapor deposition with organic silicon compound being used as a raw material gas. The organic silicon compound contains at least silicon, hydrogen and carbon as a constituent thereof, and contains two or more groups having unsaturated bond, per a molecule... Agent: Young & Thompson

20080251928 - Carbonization of metal caps: An integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a conductive wiring in the dielectric layer; and a metal carbide cap layer over the conductive wiring.... Agent: Slater & Matsil, L.L.P.

20080251927 - Electromigration-resistant flip-chip solder joints: A semiconductor device contact structure practically eliminating the copper diffusion into the solder as well as the current crowding at the contact with the subsequent electromigration in the solder. A column-like electroplated copper stud (108) is on each contact pad. The stud is sized to provide low, uniform electrical resistance... Agent: Texas Instruments Incorporated

20080251930 - Semiconductor device and dummy pattern arrangement method: A semiconductor device includes a plurality of wiring patterns arranged in a first wiring layer of the semiconductor device and extending in a first direction, and a plurality of dummy patterns arranged in the first wiring layer and extending in a second direction different from the first direction, wherein each... Agent: Young & Thompson

20080251929 - Semiconductor device and semiconductor device manufacturing method: An inventive semiconductor device includes at least three interconnection layers sequentially stacked without intervention of a via layer. At least one of the interconnection layers includes an interconnection and a via which connects interconnections provided in interconnection layers underlying and overlying the one interconnection layer.... Agent: Rabin & Berdo, PC

20080251932 - Method of forming through-silicon vias with stress buffer collars and resulting devices: A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed.... Agent: Intel Corporation C/o Intellevate, LLC

20080251931 - Multi cap layer and manufacturing method thereof: A method for manufacturing a multi cap layer includes providing a substrate, forming a multi cap layer comprising a first cap layer and a second cap layer formed thereon on the substrate, forming a patterned metal hard mask layer on the multi cap layer, and performing an etching process to... Agent: North America Intellectual Property Corporation

20080251933 - Metal interconnect structure: A metal interconnect structure includes a plurality of first plugs adjacent to each other, a first metal line extending in a first direction and contacting each first plug to form a first section with a tapered second section in between, and a second plug adjacent to the second section, both... Agent: North America Intellectual Property Corporation

20080251940 - Chip package: A chip package includes a semiconductor chip, a flexible circuit film and a substrate. The substrate has a circuit structure in the substrate. The flexible circuit film is connected to the circuit structure of the substrate through metal joints, an anisotropic conductive film or wireboning wires. The semiconductor chip has... Agent: Megica Corporation

20080251939 - Chip stack package and method of fabricating the same: A chip stack package is provided, wherein semiconductor chips having different die sizes are stacked by arranging pads in a scribe region through a redistribution process, so that the thickness of the package can be reduced. A method of fabricating the chip stack package is also provided. In the chip... Agent: Marger Johnson & Mccollom, P.C.

20080251935 - Low shrinkage polyester thermosetting resins: The invention is based on the discovery that a certain polyester compounds are useful as b-stageable adhesives for the microelectonic packaging industry. The polyester compounds described herein contain ring-opening or ring-forming polymerizable moieties and therefore exhibit little to no shrinkage upon cure. In addition, there are provided well-defined b-stageable adhesives... Agent: The Law Office Of Jane K. Babin, Professional Corporation

20080251938 - Semiconductor chip package and method of manufacture: A semiconductor chip package and method of making the same. A first chip unit includes a first substrate and a first IC chip electrically connected to the first substrate. A second chip unit includes a second substrate and a second IC chip electronically connected to the second substrate. An adhesive... Agent: Sughrue Mion, PLLC

20080251936 - Semiconductor device: The generation of a wire bonding defect is reduced in the semiconductor device in which semiconductor chips are laminated. A wiring substrate, the first memory chip by which face-up mounting is done via the first filmy adhesive on the wiring substrate, the second memory chip by which face-up mounting is... Agent: Miles & Stockbridge PC

20080251934 - Semiconductor device structures and methods of fabricating semiconductor device structures for use in sram devices: Semiconductor device structures and methods of fabricating such semiconductor device structures for use in static random access memory (SRAM) devices. The semiconductor device structure comprises a dielectric region disposed between first and second semiconductor regions and a gate conductor structure extending between the first and second semiconductor regions. The gate... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080251937 - Stackable semiconductor device and manufacturing method thereof: A stackable semiconductor device and a manufacturing method thereof are disclosed. The method includes providing a wafer comprised of a plurality of chips, wherein a plurality of solder pads are formed on the active surface of each chip, and a plurality of grooves are formed between the solder pads of... Agent: Edwards Angell Palmer & Dodge LLP

20080251941 - Vertical system integration: The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use... Agent: Michael J. Ure

20080251943 - Flip chip with interposer, and methods of making same: A device is disclosed which includes a die comprising an integrated circuit and an interposer that is coupled to the die, the interposer having a smaller footprint than that of the die. A method is disclosed which includes operatively coupling an interposer to a die comprising an integrated circuit, the... Agent: Perkins Coie LLP Patent-sea

20080251944 - Semiconductor device: A semiconductor device has a semiconductor chip bonded to external connection pads or external connection terminals by flip-chip bonding and an underfill resin, and provides a semiconductor device which enables to lessen the warpage attributable to the underfill without involvement of an increase in the size of the semiconductor device.... Agent: Rankin, Hill & Clark LLP

20080251942 - Semiconductor device and manufacturing method thereof: Electrode pads (5) and a solder resist (7) are disposed on the upper surface of a wiring board (1), and apertures (7a) are formed in the solder resist (7) so as to expose the electrode pads (5). Electrodes (4) are disposed on the lower surface of a semiconductor element (2).... Agent: Sughrue Mion, PLLC

20080251945 - Semiconductor package that has electronic component and its fabrication method: A semiconductor device having at least an electronic component and its fabrication method are disclosed. The fabrication method comprises: applying a conductive material on each one of at least a paired solder pads arranged on a substrate by screen printing, with a recess formed in the conductive material on each... Agent: Edwards Angell Palmer & Dodge LLP

20080251946 - Semiconductor apparatus, manufacturing method thereof, semiconductor module apparatus using semiconductor apparatus, and wire substrate for semiconductor apparatus: A semiconductor apparatus of the present invention includes: (i) a wire substrate having an insulating substrate in which a plurality of wire patterns are provided, (ii) a semiconductor element installed on the wire substrate with the insulating resin interposed therebetween, and a plurality of connecting terminals provided in the semiconductor... Agent: Harness, Dickey & Pierce, P.L.C

20080251948 - Chip package structure: A chip package structure including a first substrate, a second substrate, a plurality of bumps, a first B-staged adhesive layer and a second B-staged adhesive layer is provided. The first substrate has a plurality of first bonding pads. The second substrate has a plurality of second bonding pads, and the... Agent: J C Patents, Inc.

20080251947 - Cof flexible printed wiring board and semiconductor device: A COF flexible printed wiring board, used for a semiconductor device, contains an insulating layer, a wiring pattern formed of a conductor layer on one side of the insulating layer, on which a semiconductor chip is to be mounted, and a heat-resistant releasing layer, wherein the releasing layer is formed... Agent: Sughrue Mion, PLLC

20080251949 - Molding apparatus, molded semiconductor package using multi-layered film, fabricating and molding method for fabricating the same: Example embodiments include molding apparatuses, semiconductor packages, a fabricating methods for fabricating the same. The molding apparatus may include a first mold die for adhering a partially completed package, a second mold die including a cavity formed such that the partially completed package is positioned inside the cavity and a... Agent: Harness, Dickey & Pierce, P.L.C

20080251950 - Semiconductor device and processing method of the same: A disclosed semiconductor device includes a semiconductor substrate including semiconductor integrated circuit forming areas; semiconductor integrated circuits formed on the semiconductor integrated circuit forming areas; and an alignment pattern formed on a periphery of at least one of the semiconductor integrated circuit forming areas.... Agent: Ladas & Parry LLP

20080251951 - Use of a dual tone resist to form photomasks and intermediate semiconductor device structures: An alignment mark mask element protects an underlying alignment mark during subsequent processing of a fabrication substrate. The alignment mark mask element is formed concurrent with formation of a photomask from a dual-tone photoresist that exhibits a pattern reversal upon exposure to an energy level. A portion of the dual-tone... Agent: Trask Britt, P.C./ Micron Technology

20080246014 - Memory structure with reduced-size memory element between memory material portions: A memory cell device includes a memory cell access layer, a dielectric material over the memory cell access layer, a memory material structure within the dielectric material, and a top electrode in electrical contact with the memory material structure. The memory material structure has upper and lower memory material portions... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080246015 - Method to form high efficiency gst cell using a double heater cut: Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation... Agent: Schwabe, Williamson & Wyatt, P.C.

20080246016 - Device with damaged breakdown layer: A device utilizing a breakdown layer in combination with a programmable resistance material, a phase-change material or a threshold switching material. The breakdown layer having damage.... Agent: Infineon Technologies Ag Patent Department

20080246018 - Light-emitting device: A light-emitting device includes a substrate, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer; wherein the active layer is a multi-quantum-well (MQW) active layer with a predetermined n-type doping profile. More specifically, the MQW active layer is doped with n-type dopants in the region near the... Agent: Bacon & Thomas, PLLC

20080246017 - Light-emitting device having semiconductor nanocrystal complexes: Light-emitting devices are provided that incorporate one or more underlying LED chips or other light sources and a layer having one or more populations of nanoparticles disposed over the light source. The nanoparticles may absorb some light emitted by the underlying source, and re-emit light at a different level. By... Agent: Kenyon & Kenyon LLP

20080246019 - Defect reduction by oxidation of silicon: A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a... Agent: Scully, Scott, Murphy & Presser, P.C.

20080246020 - Nanowire, method for fabricating the same, and device having nanowires: A nanowire according to the present invention includes: a nanowire body made of a crystalline semiconductor as a first material; and a plurality of fine particles, which are made of a second material, including a constituent element of the semiconductor, and which are located on at least portions of the... Agent: Mcdermott Will & Emery LLP

20080246021 - Single electron transistor and method of manufacturing the same: A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion... Agent: Lee & Morse, P.C.

20080246022 - Method for producing planar transporting resonance heterostructures: An electron transport device, including at least one transport layer in which at least one periodic dislocation and/or defect array is produced, and a mechanism for guiding electrons in the transport layer.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080246023 - Transistor based on resonant tunneling effect of double barrier tunneling junctions: The present invention relates to a transistor based on resonant tunneling effect of double barrier tunneling junctions comprising: a substrate, an emitter, a base, a collector and a first and a second tunneling barrier layers; wherein the first tunneling barrier layer is located between the emitter and the base, and... Agent: Perkins Coie LLP

20080246028 - Memory device, semiconductor device, and method for manufacturing memory device: Objects are to solve inhibition of miniaturization of a memory element and complexity of a manufacturing process thereof and to provide a nonvolatile memory device and a semiconductor device each having the memory device, in which data can be additionally written except at the time of manufacture and in which... Agent: Nixon Peabody, LLP

20080246024 - Method for patterning an organic material to concurrently form an insulator and a semiconductor and device formed thereby: A method for fabricating an electronic device includes forming a layer of precursor material for forming a semi-conductor material in a cured state and exposing the precursor material to light. The precursor is heated in the presence of the light to form an insulator in areas exposed to light and... Agent: Philips Intellectual Property & Standards

20080246026 - Organic light emitting diode display: An organic light emitting diode display includes a substrate on which a transistor area and a capacitor area are defined, a semiconductor layer formed at the transistor area, and a capacitor having a plurality of electrodes. The plurality of electrodes include a first electrode, a second electrode that is disposed... Agent: Stein, Mcewen & Bui, LLP

20080246027 - Organic light emitting display and manufacturing method thereof: An organic light emitting display and a fabricating method thereof, where the display has sub-pixels of various types, which have distinctive shapes formed therein according to type is disclosed. Pixels of a particular type e.g., red, green, or blue, can be identified through visual recognition of the distinctive pattern.... Agent: Knobbe Martens Olson & Bear LLP

20080246025 - Semiconductor device and method for manufacturing the same: It is an object to provide an element structure in which defects are not easily generated and a semiconductor device that has the element. An element has a structure in which a layer containing an organic compound is interposed between a pair of electrode layers of a first electrode layer... Agent: Eric Robinson

20080246029 - Thin film transistor, organic light emitting display device including the same, and method of manufacturing the organic light emitting display device: A thin film transistor, e.g., for use in an organic light emitting display, may include: a gate insulating layer disposed on a gate electrode located on a substrate; a semiconductor layer, disposed on the gate insulating layer; and a planarization layer disposed on the gate insulating layer, the source and... Agent: Lee & Morse, P.C.

20080246031 - Pcm pad design for peeling prevention: A semiconductor structure is provided. The semiconductor structure includes a semiconductor chip and a scribe line adjoining the semiconductor chip. A conductive feature is formed in the scribe line and exposed on the surface of the scribe lines, wherein the conductive feature has an edge facing the semiconductor chip. A... Agent: Slater & Matsil, L.L.P.

20080246032 - Test structure for detecting via contact shorting in shallow trench isolation regions: A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI... Agent: Cantor Colburn LLP - IBM Fishkill

20080246030 - Test structures and methods for inspection of semiconductor integrated circuits: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures... Agent: Weaver Austin Villeneuve Sampson LLP - Kla Tencor Kla Tencor

20080246034 - Thin film transistor for flat panel display and method of fabricating the same: A thin film transistor for a flat panel display, and more particularly to a thin film transistor for a flat panel display having a protrusion in a part of a gate electrode includes a substrate on which an insulating layer is deposited, a semiconductor layer, which is a layer having... Agent: Stein, Mcewen & Bui, LLP

20080246033 - Thin film transistor, organic light emitting device including thin film transistor, and manufacturing method thereof: The present invention relates to a thin film transistor, a method thereof and an organic light emitting device including the thin film transistor. According to an embodiment of the present invention, the thin film transistor includes a substrate, a control electrode, an insulating layer, a first electrode and a second... Agent: Cantor Colburn, LLP

20080246035 - Semiconductor device and display appliance using the semiconductor device: In order to provide a semiconductor device having a circuit for operating normally even when the amplitude of a signal voltage is smaller than the amplitude of a power source voltage, a correcting circuit is provided before a digital circuit to be operated normally. As for a signal outputted from... Agent: Cook Alex Ltd

20080246038 - Display device and control method of the same: A display device including a first gate line and a second gate line that extend in parallel with each other, a data line crossing the first and second gate lines to form a pixel region, a pixel electrode in the pixel region and including a main pixel electrode and a... Agent: H.c. Park & Associates, PLC

20080246037 - Flat display device and method of manufacturing the same: Provided is a flat display device, and more particularly, an active matrix (AM) flat display device having a thin film transistor (TFT). The flat display device includes a substrate, a plurality of TFTs (thin film transistors) provided on the substrate, each TFT comprising an active layer, a source electrode and... Agent: Robert E. Bushnell

20080246039 - Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor: The formation of contact holes and a capacitor is performed in a semiconductor integrated circuit such as an active matrix circuit. An interlayer insulator having a multilayer (a lower layer is silicon oxide; an upper layer is silicon nitride) each having different dry etching characteristic is formed. Using a first... Agent: Eric Robinson

20080246036 - Semiconductor device, television set, and method for manufacturing the same: An object of the invention is to provide a method for manufacturing a substrate having a film pattern such as an insulating film, a semiconductor film, or a conductive film with an easy process, and further, a semiconductor device and a television set having a high throughput or a high... Agent: Nixon Peabody, LLP

20080246040 - Light emitting device having light emitting elements: A light-emitting device operating on a high drive voltage and a small drive current. LEDs (1) are two-dimensionally formed on an insulating substrate (10) of e.g., sapphire monolithically and connected in series to form an LED array. Two such LED arrays are connected to electrodes (32) in inverse parallel. Air-bridge... Agent: H.c. Park & Associates, PLC

20080246041 - Method of fabricating soi nmosfet and the structure thereof: A method of fabricating a silicon-on-insulator (SOI) N-channel metal oxide semiconductor field effect transistor (nMOSFET), where the transistor has a structure incorporating a gate disposed above a body of the SOI substrate. The body comprises of a first surface and a second surface. The second surface interfaces between the body... Agent: Hoffman Warnick LLC

20080246043 - Light-emitting device: A pair of bonding electrodes of each of light-emitting semiconductor devices of RGB is disposed in a point symmetrical relationship, the devices are mounted on a common electrode of a package, and a bonding wire is suspended from a commonized bonding electrode of the respective devices to the common electrode.... Agent: Mcginn Intellectual Property Law Group, PLLC

20080246042 - Pixel structure and method for forming the same: A pixel structure comprising at least one transistor, a first storage capacitor, a first conductive layer, an interlayer dielectric layer, a second conductive layer, a passivation layer, and a third conductive layer is provided. The first storage capacitor is electrically connected to the transistor. The interlayer dielectric layer having at... Agent: Bacon & Thomas, PLLC

20080246044 - Led device with combined reflector and spherical lens: A light source and method for making the same are disclosed. The light source includes a substrate having a top surface, a die, and a first encapsulating layer. The die includes an LED attached to the top surface and electrically connected to traces in the substrate that power the LED.... Agent: Kathy Manke Avago Technologies Limited

20080246045 - Light-emitting diode packaging structure: A light-emitting diode packaging structure includes a thermally conductive substrate; a circuit layer provided on one surface of the substrate and having an electric connection element; at least one chip mounted on the circuit layer to electrically connect to the electric connection element; alight-reflective case enclosing at least part of... Agent: Birch Stewart Kolasch & Birch

20080246046 - Pixel structure for a solid state light emitting device: A light emitting device includes an active layer structure, which has one or more active layers with luminescent centers, e.g. a wide bandgap material with semiconductor nano-particles, deposited on a substrate. For the practical extraction of light from the active layer structure, a transparent electrode is disposed over the active... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080246047 - Semiconductor light-emitting device: A semiconductor light-emitting device comprises an N-type semiconductor layer, an active layer formed on the surface of the N-type semiconductor layer, a P-type semiconductor layer formed on the surface of the active layer, and a reflective layer formed on the surface of the P-type semiconductor layer. A plurality of ohmic... Agent: Wpat, PC Intellectual Property Attorneys

20080246048 - Semiconductor light-emitting device: A semiconductor light-emitting device, the device includes a substrate, a semiconductor stacked layer, a lead electrode and a lead, wherein the semiconductor stacked layer at least includes a N-type layer and a P-type layer, at least one of the N-type layer and the P-type layer has an opening, the opening... Agent: Park, Vaughan & Fleming LLP

20080246052 - Electronic component assembly with composite material carrier: The present invention relates to an electronic component assembly including a composite material carrier, a circuit carrier made of a dielectric material, a circuit with a conductive material formed on the circuit carrier, an intermediate layer between the circuit carrier and the composite material carrier, and an electronic component arranged... Agent: Bacon & Thomas, PLLC

20080246051 - Light emitting apparatus and method for manufacturing same: A light emitting apparatus includes: a light emitting element including a laminated body, an electrode provided on the laminated body, and a pad electrode provided on the electrode, the laminated body including a semiconductor light emitting layer; a mounting member having a metal bonding layer; and an alloy solder containing... Agent: Amin, Turocy & Calvin, LLP

20080246050 - Organic light-emitting device including transparent conducting oxide layer as cathode and method of manufacturing the same: An organic light-emitting device including a transparent conducting oxide layer as a cathode and a method of manufacturing the organic light-emitting device. The organic light-emitting device includes an anode disposed on a substrate. An organic functional layer including at least an organic light-emitting layer is disposed on the anode. The... Agent: Stein, Mcewen & Bui, LLP

20080246049 - Semiconductor device, method for fabricating an electrode, and method for manufacturing a semiconductor device: A semiconductor device includes a p-type nitride semiconductor layer (14); and a p-side electrode (18) including a palladium oxide film (30) connected to a surface of the nitride semiconductor layer (14).... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080246053 - P-type group iii nitride semiconductor and production method thereof: s

20080246054 - Self-supported nitride semiconductor substrate and its production method, and light-emitting nitride semiconductor device using it: A self-supported nitride semiconductor substrate of 10 mm or more in diameter having an X-ray diffraction half width of 500 seconds or less in at least one of a {20-24} diffraction plane and a {11-24} diffraction plane.... Agent: Sughrue Mion, PLLC

20080246055 - Semiconductor component including a monocrystalline semiconductor body and method: A semiconductor component comprising a monocrystalline semiconductor body, and to a method for producing the same is disclosed. In one embodiment, the semiconductor body has a semiconductor component structure with regions of a porous-mono crystalline semiconductor.... Agent: Dicke, Billig & Czaja

20080246056 - Silicide formation for esige using spacer overlapping esige and silicon channel interface and related pfet: Methods of forming a suicide in an embedded silicon germanium (eSiGe) source/drain region using a suicide prevention spacer overlapping an interface between the eSiGe and the silicon channel, and a related PFET with an eSiGe source/drain region and a compressive stress liner in close proximity to a silicon channel thereof,... Agent: Hoffman Warnick LLC

20080246057 - Silicon layer for stopping dislocation propagation: A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially... Agent: Slater & Matsil, L.L.P.

20080246058 - Gallium nitride material transistors and methods associated with the same: Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission... Agent: Wolf Greenfield & Sacks, P.C.

20080246059 - Device fabrication by anisotropic wet etch: A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes... Agent: Innovation Interface, LLC

20080246060 - Transistor: A transistor includes a nitride semiconductor layer and a gate electrode layer. The gate electrode layer includes a tantalum nitride layer being formed on the nitride semiconductor layer. The tantalum nitride layer forms a Schottky junction with the nitride semiconductor layer. The transistor also includes an insulating film formed on... Agent: Leydig Voit & Mayer, Ltd

20080246062 - Semiconductor based controllable high resistance device: t

20080246061 - Stress layer structure: A stress layer structure disposed on a substrate including a device region and a non-device region is provided. The device region includes active regions and a non-active region. The stress layer structure has stress patterns, at least one partition line, and at least one dummy stress pattern. Each of the... Agent: J C Patents, Inc.

20080246063 - Photodiode with multi-epi films for image sensor: The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a semiconductor substrate; a first epitaxy semiconductor layer disposed on the semiconductor substrate and having a first type of dopant and a first doping concentration; a second epitaxy semiconductor layer disposed over the first epitaxy semiconductor layer... Agent: Haynes And Boone, LLP

20080246065 - Imaging apparatus, imaging system, its controlling method, and storage medium storing its program: An idling time period after applying a bias to a conversion element until a start of an accumulation of the conversion element for deriving an image and an accumulation period from the start of the accumulation to a termination of the accumulation are measured. An offset correction of the image... Agent: Fitzpatrick Cella Harper & Scinto

20080246064 - Semiconductor device and electronic device using the same: To provide a semiconductor device which can detect low illuminance. A photoelectric conversion element, a diode-connected first transistor, and a second transistor are included. A gate of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the first... Agent: Eric Robinson

20080246066 - Optic wafer with reliefs, wafer assembly including same and methods of dicing wafer assembly: An optic wafer for assembly with an imager wafer, the optic wafer comprising a plurality of reliefs in a surface thereof coincident with street locations separating mutually adjacent optic element locations. A wafer assembly that includes the optic wafer and an imager wafer and methods of dicing a wafer assembly... Agent: Trask Britt, P.C./ Micron Technology

20080246067 - Dram device and method of manufacturing the same: In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation... Agent: Harness, Dickey & Pierce, P.L.C

20080246068 - Trench capacitors and memory cells using trench capacitors: A trench structure, a method of forming the trench structure, a memory cell using the trench structure and a method of forming a memory cell using the trench structure. The trench structure includes: a substrate; a trench having contiguous upper, middle and lower regions, the trench extending from a top... Agent: Schmeiser, Olsen & Watts

20080246069 - Folded node trench capacitor: A trench capacitor is filled with a set of two or more storage plates by consecutively depositing layers of dielectric and conductor and making contact to the ground plates by etching an aperture through the plates to the buried plate in the substrate and connecting the one or more ground... Agent: International Business Machines Corporation Dept. 18g

20080246070 - Methods and apparatus for forming a polysilicon capacitor: An embodiment relates generally to a method of forming a capacitor. The method includes depositing a first layer of polysilicon on a substrate and implanting a high dose of implant into the first layer of polysilicon. The method also includes depositing a layer of dielectric over the first layer of... Agent: Texas Instruments Incorporated

20080246071 - Mos varactors with large tuning range: A MOS varactor includes a shallow PN junction beneath the surface of the substrate of a MOS structure. In depletion mode, the depletion region of the MOS structure merges with the depletion region of the shallow PN junction. This increases the total width of the depletion region of the MOS... Agent: HorizonIPPte Ltd

20080246073 - Nonvolatile memory devices including a resistor region: Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on... Agent: Myers Bigel Sibley & Sajovec

20080246072 - Nonvolatile semiconductor memory device and manufacturing method of the same: In a nonvolatile semiconductor memory device including a memory cell column formed by connecting in series a plurality of memory cells each having a structure in which a charge-storage layer and a control gate are stacked via an insulating layer on a semiconductor substrate, a first selection transistor formed on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080246074 - Two-bits per cell not-and-gate (nand) nitride trap memory: A non-volatile memory array includes a semiconductor substrate having a main surface, a first source/drain region and a second source/drain region. The second source/drain region is spaced apart from the first source/drain region. A well region is disposed in a portion of the semiconductor substrate between the first source/drain region... Agent: Akin Gump LLP - Silicon Valley

20080246076 - Methods for nanopatterning and production of nanostructures: Methods for nanopatterning and methods for production of nanoparticles utilizing such nanopatterning are described herein. In exemplary embodiments, masking nanoparticles are disposed on various substrates and to form a nanopatterned mask. Using various etching and filling techniques, nanoparticles and nanocavities can be formed using the masking nanoparticles and methods described... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080246075 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device includes forming a plurality of gate electrodes for a plurality of memory cell transistors on a surface of a semiconductor substrate, each gate electrode including a polycrystalline layer on an upper portion thereof; filling a first silicon oxide film between the plurality of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080246078 - Charge trap flash memory device and memory card and system including the same: A charge trap flash memory device and method of making same are provided. The device includes: a tunnel insulating layer, a charge trap layer; a blocking insulating layer; and a gate electrode sequentially formed on a substrate. The charge trap layer includes: plural trap layers comprising a first material having... Agent: Mills & Onello LLP

20080246077 - Method of fabricating semiconductor memory device and semiconductor memory device fabricated by the method: In a method for fabricating a semiconductor memory device and a semiconductor memory device fabricated by the method, the method includes forming a multi-layered dielectric structure including a first dielectric layer with an ion implantation layer and a second dielectric layer without an ion implantation layer, over a semiconductor substrate;... Agent: Mills & Onello LLP

20080246079 - Power semiconductor device: A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080246080 - Shallow trench isolation (sti) based laterally diffused metal oxide semiconductor (ldmos): An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a first heavily doped region to represent a source region. A second heavily doped region represents a drain region of the semiconductor device. A third heavily doped region represents a gate region of... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080246081 - Self-aligned trench mosfet and method of manufacture: A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20080246082 - Trenched mosfets with embedded schottky in the same cell: A semiconductor power device includes trenched semiconductor power device comprising a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an insulation layer covering the trenched semiconductor power device... Agent: Bo-in Lin

20080246083 - Recessed drift region for hvmos breakdown improvement: A high-voltage metal-oxide-semiconductor (HVMOS) device having increased breakdown voltage and methods for forming the same are provided. The HVMOS device includes a semiconductor substrate; a gate dielectric on a surface of the semiconductor substrate; a gate electrode on the gate dielectric; a source/drain region adjacent and horizontally spaced apart from... Agent: Slater & Matsil, L.L.P.

20080246084 - Power semiconductor device and method for producing the same: A power semiconductor device includes: a first semiconductor substrate; a second semiconductor layer; a plurality of third semiconductor pillar regions and a plurality of fourth semiconductor pillar regions that are provided in an upper layer of the second semiconductor layer and alternatively arranged along a direction parallel to an upper... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080246085 - Power semiconductor device: A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer that are provided above the first semiconductor layer and alternatively arranged along a direction parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080246086 - Semiconductor devices having charge balanced structure: A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is... Agent: Duane Morris, LLPIPDepartment

20080246087 - Mos transistor for reducing short-channel effects and its production: The invention is related to a MOS transistor and its fabrication method to reduce short-channel effects. Existing process has the problem of high complexity and high cost to reduce short-channel effects by using epitaxial technique to produce an elevated source and drain structure. In the invention, the MOS transistor, fabricated... Agent: Rabin & Berdo, PC

20080246088 - Self-aligned lightly doped drain recessed-gate thin-film transistor: A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080246089 - Method of manufacturing thin film transistor: Disclosed is a method of manufacturing a thin film transistor, in which a semiconductor layer and a gate insulating film may be formed through ink jet printing using a single bank, thereby simplifying the manufacturing process and decreasing the manufacturing cost, leading to more economical thin film transistors. The thin... Agent: Harness, Dickey & Pierce, P.L.C

20080246090 - Self-aligned planar double-gate transistor structure: A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a... Agent: Scully, Scott, Murphy & Presser, P.C.

20080246091 - Semiconductor integrated circuit device: A semiconductor integrated circuit device capable of suppressing variations in transistor characteristics due to the well proximity effect is provided. Standard cell rows are arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction. In the standard cell rows, positions of the N... Agent: Mcdermott Will & Emery LLP

20080246092 - Semiconductor device structure with strain layer and method of fabricating the semiconductor device structure: A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and gate dummies not to overlap each other, the area of active dummy on which a strain layer dummy... Agent: Mills & Onello LLP

20080246093 - Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern: Disclosed is a method of fabricating a field effect transistor. In the method, a gate stack on a top surface of a semiconductor substrate is formed, and then a first spacer is formed on a sidewall of the gate stack. Next, a silicide self-aligned to the first spacer is deposited... Agent: International Business Machines Corporation Dept. 18g

20080246094 - Method for manufacturing sram devices with reduced threshold voltage deviation: A semiconductor device includes a semiconductor substrate; a gate dielectric layer disposed on the semiconductor substrate; a gate conductive layer doped with impurities selected from nitrogen, carbon, silicon, germanium, fluorine, oxygen, helium, neon, xenon or a combination thereof on the gate dielectric layer; and source/drain doped regions formed adjacent to... Agent: K & L Gates LLP

20080246095 - Ambipolar transistor design: An ambipolar transistor, including a p-type semiconductor region and an n-type semiconductor region near the p-type semiconductor region. Also a first terminal and second terminal contact both the p-type semiconductor region and the n-type semiconductor region. Furthermore, the p-type semiconductor region and the n-type semiconductor region substantially do not overlap... Agent: Oliff & Berridge, PLC.

20080246097 - Methods for reducing within chip device parameter variations: A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test... Agent: Schmeiser, Olsen & Watts

20080246096 - Semiconductor device including schottky barrier diode and method of manufacturing the same: A semiconductor device includes a substrate, a plurality of first columns having a first conductivity type, a plurality of second columns having a second conductivity type, a first electrode, and a second electrode. The first columns and the second columns are alternately arranged on the substrate to provide a super... Agent: Posz Law Group, PLC

20080246098 - Split-channel antifuse array architecture: Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080246099 - Low temperature poly oxide processes for high-k/metal gate flow: An integrated circuit device is disclosed as comprising a feature that is susceptible to oxidation. A poly-oxide coating is used over the feature susceptible to oxidation to protect the feature susceptible to oxidation from oxidizing. Various method can be used to form the poly-oxide coating include conversion of a ploy-silicon... Agent: Texas Instruments Incorporated

20080246100 - High-k dielectric film, method of forming the same and related semiconductor device: A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first silicon content and a top layer of metal-silicon-oxynitride having... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080246101 - Method of poly-silicon grain structure formation: A method for forming a poly-crystalline silicon film on a substrate by positioning a substrate within a processing chamber, heating the processing chamber to a first temperature between about 640° C. and about 720° C., stabilizing a deposition pressure between about 200 Torr and about 350 Torr, introducing a silicon... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080246102 - Semiconductor device and method for manufacturing the same: A semiconductor device includes an Nch transistor having a first gate electrode and a Pch transistor having a second gate electrode. The first gate electrode and the second gate electrode are made of materials causing stresses of different magnitudes.... Agent: Mcdermott Will & Emery LLP

20080246104 - High capacity low cost multi-state magnetic memory: One embodiment of the present invention includes multi-state current-switching magnetic memory element including a stack of two or more magnetic tunneling junctions (MTJs), each MTJ having a free layer and being separated from other MTJs in the stack by a seeding layer formed upon an isolation layer, the stack for... Agent: Law Offices Of Imam

20080246103 - Mr device with surfactant layer within the free layer: The dR/R ratios of TMR and GMR devices, having a FeCo/NiFe type of free layer, have been significantly increased by inserting a suitable surfactant layer within (as opposed to above or below) the free layer. Our preferred surfactant material has been oxygen but similar-acting materials could be substituted. The concept... Agent: Stephen B. Ackerman

20080246105 - Detector system and detector subassembly: A detector system (100) with a microelectronic semiconductor chip (20) and a separate optoelectronic detector chip (10) is specified, wherein the detector chip is positioned on the semiconductor chip. A detector subassembly with such a detector system is also specified.... Agent: Fish & Richardson PC

20080246106 - Integrated circuits having photonic interconnect layers and methods for fabricating same: Various embodiments of the present invention are directed to integrated circuits having photonic interconnect layers and methods for fabricating the integrated circuits. In one embodiment of the present invention, an integrated circuit comprises an electronic device layer and one or more photonic interconnect layers. The electronic device layer includes one... Agent: Hewlett Packard Company

20080246107 - Solid state imaging device and fabrication method of solid state imaging device: A solid state imaging device comprises: photoelectric conversion portions on or above a substrate; and color filters on or above the respective photoelectric conversion portions. Each of the photoelectric conversion portions comprises: a lower electrode on or above the substrate; a photoelectric conversion film on or above the lower electrode;... Agent: Sughrue-265550

20080246108 - Semiconductor device including power switch and power reinforcement cell: A semiconductor device according to one embodiment includes a cell disposition region in which plural basic cells are disposed and a basic power supply wiring. In the cell disposition region are disposed a primitive cell connected to the basic power supply wiring and a high current consumption cell connected to... Agent: Mcginn Intellectual Property Law Group, PLLC

20080246109 - Soi substrate, method for manufacturing the same, and semiconductor device: An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a... Agent: Eric Robinson

20080246110 - Structure for spanning gap in body-bias voltage routing structure: Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire.... Agent: Transmeta C/o Murabito, Hao & Barnes LLP

20080246111 - Semiconductor device and method of fabricating the same: A semiconductor device. The device includes an active region isolated by an isolation structure on a substrate, and a dielectric layer overlying the active region and the isolation structure. The dielectric layer comprises a lower part overlying the active region beyond the boundary of the active region and the isolation... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080246112 - Semiconductor structure including laminated isolation region: A semiconductor structure and a related method for fabrication thereof include an isolation region located within an isolation trench within a semiconductor substrate. The isolation region comprises; (1) a lower lying dielectric plug layer recessed within the isolation trench; (2) a U shaped dielectric liner layer located upon the lower... Agent: Scully, Scott, Murphy & Presser, P.C.

20080246113 - Semiconductor device including redistribution line structure and method of fabricating the same: The invention provides a semiconductor device. The semiconductor device includes a semiconductor chip having an active surface on which pads are disposed, a passivation layer pattern disposed to cover the active surface of the semiconductor chip and to expose the pads, a first insulation layer pattern disposed on the passivation... Agent: Marger Johnson & Mccollom, P.C.

20080246114 - Integrated passive device with a high resistivity substrate and method for forming the same: According to one aspect of the present invention, a method of forming a microelectronic assembly, such as an integrated passive device (IPD) (72), is provided. An insulating dielectric layer (32) having a thickness (36) of at least 4 microns is formed over a silicon substrate (20). At least one passive... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080246115 - Robust esd cell: An electric discharge device includes a bipolar transistor configuration comprising a base, an emitter, and a collector. At least one pinched resistor is formed in a region comprising both the base and emitter so as to produce a pinched resistive area that develops a voltage once the bipolar transistor experiences... Agent: Gauthier & Connors, LLP

20080246116 - Symmetrical programmable crossbar structure: A crossbar structure includes a first layer or layers including first p-type regions and first n-type regions, a second layer or layers including second p-type regions and second n-type regions, and a resistance programmable material formed between the first layer(s) and the second layer(s), wherein the first layer(s) and the... Agent: Blaise Mouttet

20080246117 - Surface patterned topography feature suitable for planarization: A method for manufacturing a semiconductor device that comprises implanting a first dopant type in a well region of a substrate to form implanted sub-regions that are separated by non-implanted areas of the well region. The method also comprises forming an oxide layer over the well region, such that an... Agent: Texas Instruments Incorporated

20080246118 - Method for realizing a contact of an integrated well in a semiconductor substrate, in particular for a base terminal of a bipolar transistor, with enhancement of the transistor performances: A method realizes a contact of a first well of a first type of dopant integrated in a semiconductor substrate next to a second well of a second type of dopant and forming with it a parasitic diode. The method comprises: formation of the first well; formation of the second... Agent: Seed Intellectual Property Law Group PLLC

20080246119 - Large tuning range junction varactor: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the... Agent: HorizonIPPte Ltd

20080246120 - Reduction of silicide formation temperature on sige containing substrates: A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element,... Agent: Scully, Scott, Murphy & Presser, P.C.

20080246121 - Method of fabricating a device with a concentration gradient and the corresponding device: A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate.... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20080246122 - Positive-intrinsic-negative (pin)/negative-intrinsic-positive (nip) diode: A positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode includes a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate is of a first conductivity. The PIN/NIP diode includes at least one trench formed in the first main surface which defines at least one mesa. The trench extends... Agent: Panitch Schwarze Belisario & Nadel LLP

20080246123 - Methods for controlling catalyst nanoparticle positioning and apparatus for growing a nanowire: A method for controlling catalyst nanoparticle positioning includes establishing a mask layer on a post such that a portion of a vertical surface of the post remains exposed. The method further includes establishing a catalyst nanoparticle material on the mask layer and directly adjacent at least a portion of the... Agent: Hewlett Packard Company

20080246124 - Plasma treatment of insulating material: A method is disclosed which includes forming an opening in an insulating material, performing a plasma process to introduce nitrogen into a portion of the insulating material to thereby form a nitrogen-containing region at least on an inner surface of the opening, and, after forming the nitrogen-containing region, performing an... Agent: Wells St. John P.s.

20080246125 - Semiconductor device and method for manufacturing semiconductor device: The present invention is a semiconductor device characterized by including a substrate, an insulating film consisting of a fluorine added carbon film formed on the substrate, a barrier layer consisting of a silicon nitride film and a film containing silicon, carbon, and nitride formed on the insulating film, and a... Agent: Masuvalley & Partners

20080246126 - Stacked and shielded die packages with interconnects: According to an example embodiment, a stacked die package 800 includes a first die (806), first active circuitry (808) disposed on an upper surface of the first die, and a first conductive pattern (820) disposed on the first active circuitry. The stacked die package further includes a second die (826)... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080246127 - Arrangement for high frequency application: A source mounted semiconductor device package is described which includes a semiconductor die having first and second opposing major surfaces, first and second major electrodes disposed on respective major surfaces and a control electrode disposed on the second major surface, and a thin metal clip electrically connected to the first... Agent: Ostrolenk Faber Gerb & Soffen

20080246128 - Bent lead transistor: A metal backing tab supports the semiconductor device and has an extending portion extending from an edge. A top leg, a middle leg and a bottom leg are all coupled to the semiconductor device and each has a lead terminal portion extending beyond the boundary of said molded housing. The... Agent: Law Offices Of Clement Cheng

20080246129 - Method of manufacturing semiconductor device and semiconductor device: The present invention provides a method of manufacturing a semiconductor device in which a plurality of wires are connected to the same electrode on a semiconductor chip, the method making it possible to inhibit an increase in electrode area. First, ball bonding is performed to compressively bond a first ball... Agent: Steptoe & Johnson LLP

20080246131 - Chip package structure: A chip package structure including a circuit pattern, a frame, a first adhesive layer, a plurality of leads, an insulating adhesive layer, a chip, a plurality of first bonding wires, a plurality of second bonding wires, and a molding compound is provided. The frame and leads are disposed around the... Agent: Jianq Chyun Intellectual Property Office

20080246130 - Semiconductor package structure having enhanced thermal dissipation characteristics: In an exemplary embodiment, a packaged device having enhanced thermal dissipation characteristics includes a semiconductor chip having a major current carrying or heat generating electrode. The semiconductor chip is oriented so that the major current carrying electrode faces the top of the package or away from the next level of... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20080246132 - Semiconductor device and method of manufacturing semiconductor device: This semiconductor device includes a semiconductor chip, and a lead arranged around the semiconductor chip to extend in a direction intersecting with the side surface of the semiconductor chip, and having at least an end farther from the semiconductor chip bonded to a package board, wherein a joint surface to... Agent: Rabin & Berdo, PC

20080246133 - Flip-chip image sensor packages and methods of fabricating the same: There is provided an imager package including an image sensor die attached to a transparent substrate such that sensitive image sensing components on the sensor die face the transparent substrate. In accordance with an embodiment of the present technique, the imager package may be coupled to an external package via... Agent: Fletcher Yoder (micron Technology, Inc.)

20080246136 - Chips having rear contacts connected by through vias to front contacts: A microelectronic unit is provided in which front and rear surfaces of a semiconductor element may define a thin region which has a first thickness and a thicker region having a thickness at least about twice the first thickness. A semiconductor device may be present at the front surface, with... Agent: Tessera Lerner David Et Al.

20080246134 - Package-borne selective enablement stacking: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices. In preferred embodiments, the plastic body of one or more leaded packaged ICs bear conductive traces that create circuitry to provide stacking related electrical interconnections between the constituent ICs of a stacked... Agent: Fish & Richardson P.C.

20080246135 - Stacked package module: A stacked package module is disclosed, which comprises: a first package structure comprising a first circuit board with a first chip embedded therein, wherein the first chip has a plurality of electrode pads; the first circuit board comprises a first surface, an opposite second surface, a plurality of exposed electro-connecting... Agent: Bacon & Thomas, PLLC

20080246137 - Integrated circuit device and method for the production thereof: An integrated circuit device includes a semiconductor chip and a control chip at different supply potentials. A lead chip island includes an electrically conductive partial region and an insulation layer. The semiconductor chip is arranged on the electrically conductive partial region of the lead chip island and the control chip... Agent: Dicke, Billig & Czaja

20080246138 - Packed system of semiconductor chips having a semiconductor interposer: A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the second surface, with terminals and attached non-reflow metal studs (215) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components... Agent: Texas Instruments Incorporated

20080246139 - Polar hybrid grid array package: A grid array package includes a rectangular pattern of electrical contacts around a perimeter of the package. The grid array package also includes a polar pattern of electrical contacts inside of, and concentric with, the rectangular pattern. The grid array package also includes additional electrical contacts arranged between the rectangular... Agent: Lemoine Patent Services, PLLC

20080246140 - Semiconductor device: A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, a first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080246141 - Semiconductor device: A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, which is provided with a stepped surface positioned at lower level at a portion of the base plate than a main surface of the base plate. A first dielectric plate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080246143 - Embedded metal heat sink for semiconductor: An embedded metal heat sink for a semiconductor device is described. The embedded metal heat sink for a semiconductor device comprises a metal thin layer, a metal heat sink and two bonding pads. The metal thin layer including a first surface and a second surface on opposite sides, wherein at... Agent: Lowe Hauptman Ham & Berner, LLP

20080246142 - Heat dissipation unit and a semiconductor package that has the heat dissipation unit: A heat dissipation unit and a semiconductor package having the same are disclosed. The semiconductor package includes a carrier; an electronic component mounted on and electrically connected to the carrier; a heat dissipation unit, which includes a flat section attached to the electronic component, extension sections connected to the flat... Agent: Edwards Angell Palmer & Dodge LLP

20080246144 - Method for fabricating contact pads: A method for fabricating a contact pad is disclosed. A first metal layer is disposed on a substrate for serving as a probing region. A second metal layer is disposed on the substrate thereafter to serve as an electrical connection region. Preferably, the first metal layer and the second metal... Agent: North America Intellectual Property Corporation

20080246145 - Mobile binding in an electronic connection: A method of creating an electrical contact involves locating a barrier material at a location for an electrical connection, providing an electrically conductive bonding metal on the barrier material, the electrically conductive bonding metal having a diffusive mobile component, the volume of barrier material and volume of diffusive mobile component... Agent: Foley & Lardner LLP

20080246146 - Wiring substrate and wiring substrate manufacturing method: A method of manufacturing a wiring substrate comprises: a first step of forming, on a support plate, an electrode pad made of metal; a second step of etching the support plate in such a manner that the support plate has a shape which includes a projection portion to be contacted... Agent: Rankin, Hill & Clark LLP

20080246147 - Novel substrate design for semiconductor device: A novel design and method of fabricating a semiconductor device. In a preferred embodiment, the present invention is a flip chip package including a BT substrate. On the side of the substrate facing the die, thin traces are formed of an enhanced conductive material. Conductive bumps such as eutectic solder... Agent: Slater & Matsil, L.L.P.

20080246148 - Electrical interconnect structures having carbon nanotubes therein and methods of forming same: Integrated circuit devices include electrically conductive interconnects containing carbon nanotubes. An electrical interconnect includes a first metal region. A first electrically conductive barrier layer is provided on an upper surface of the first metal region and a second metal region is provided on the first electrically conductive barrier layer. The... Agent: Myers Bigel Sibley & Sajovec

20080246150 - Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region: Devices are presented including: a substrate including a dielectric region and a conductive region; a molecular self-assembled layer selectively formed on the dielectric region; and a capping layer formed on the conductive region, where the capping layer is an electrically conductive material such as: an alloy of cobalt and boron... Agent: Kali Law Group, P.C.

20080246151 - Interconnect structure and method of fabrication of same: A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing... Agent: Schmeiser, Olsen & Watts

20080246149 - Semiconductor device and method for forming device isolation film of semiconductor device: A method for manufacturing a semiconductor device comprises growing a carbon nano tube (CNT) in a contact hole to form a contact plug, thereby preventing diffusion of a tungsten layer. The method does not require forming a titanium nitride (TiN) film deposited to improve an adhesive strength. The CNT has... Agent: Marshall, Gerstein & Borun LLP

20080246152 - Semiconductor device with bonding pad: A semiconductor device with a bonding pad is provided. The semiconductor device includes a first substrate having a device area and a bonding area, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are disposed on the upper surface of the first substrate in the... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080246153 - Organic silica-based film, method of forming the same, composition for forming insulating film for semiconductor device, interconnect structure, and semiconductor device: A method of forming an organic silica-based film, including: applying a composition for forming an insulating film for a semiconductor device, which is cured by using heat and ultraviolet radiation, to a substrate to form a coating; heating the coating; and applying heat and ultraviolet radiation to the coating to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080246154 - Top layers of metal for high performance ic's: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses... Agent: Mou-shiung Lin

20080246155 - Semiconductor device and method of fabricating the same: A semiconductor device according to an embodiment includes: a semiconductor substrate having a semiconductor element formed on a surface thereof; an interwiring insulating film formed above the semiconductor substrate; a wiring formed in the interwiring insulating film; a first intervia insulating film formed under the interwiring insulating film; a first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080246156 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080246158 - Method for realizing a nanometric circuit architecture between standard electronic components and semiconductor device obtained with said method: A method for realizing a nanometric circuit architecture includes: realizing plural active areas on a semiconductor substrate; realizing on the substrate a seed layer of a first material; realizing a mask-spacer of a second material on the seed layer in a region comprised between the active areas; realizing a mask... Agent: Seed Intellectual Property Law Group PLLC

20080246159 - Planarized passivation layer for semiconductor devices: A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a... Agent: HorizonIPPte Ltd

20080246160 - Standard cell and semiconductor device including the same: This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first... Agent: Mcdermott Will & Emery LLP

20080246157 - Surface mount devices with minimum lead inductance and methods of manufacturing the same: A device according to various aspects of the present invention generally includes a surface mount device having a top side, a bottom side, a plurality of sidewalls, and a circuit comprising one or more layers. The device includes a first conductive surface covering a portion of one of the sidewalls... Agent: Squire Sanders & Dempsey LLP

20080246161 - Damascene conductive line for contacting an underlying memory element: A damascene approach may be utilized to form an electrode to a lower conductive line in a phase change memory. The phase change memory may be formed of a plurality of isolated memory cells, each including a phase change memory threshold switch and a phase change memory storage element.... Agent: Trop Pruner & Hu, PC

20080246162 - Stack package, a method of manufacturing the stack package, and a digital device having the stack package: A chip stack package may include a substrate, semiconductor chips, a molding member and a controller. The substrate may have a wiring pattern. The semiconductor chips may be stacked on a first surface of the substrate. Further, the semiconductor chips may be electrically connected to the wiring pattern. The molding... Agent: Harness, Dickey & Pierce, P.L.C

20080246163 - Semiconductor device: A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the... Agent: Rabin & Berdo, PC

20080246164 - Soldering method, solder pellet for die bonding, method for manufacturing a solder pellet for die bonding, and electronic component: A pellet for use in die bonding of an electronic chip and a substrate in an electronic component generates minimized voids in spite of the pellet being made of a lead-free solder. The pellet forms a colorless transparent protective film comprising Sn-(30-50 at % 0)-(5-15 at % P) or Sn-(10-30... Agent: Michael Tobias

20080246165 - Novel interconnect for chip level power distribution: A semiconductor device (601) is provided which comprises a substrate (603); a semiconductor device (605) disposed on said substrate and having a first major surface; a first metal strap (615) which is in electrical contact with said substrate and which is adapted to provide power to a first region (608)... Agent: Fortkort & Houston P.C.

20080246166 - Semiconductor device and method of manufacturing same: A semiconductor device that improves adhesion between a resin and a die pad and prevents cracking of the resin includes: a semiconductor chip; a die pad on which the semiconductor chip is mounted; a bonding agent for bonding the semiconductor chip to the die pad; a plurality of inner leads... Agent: Young & Thompson

20080246167 - Layout structure for chip coupling: A layout structure disposed on the substrate of the liquid crystal display (LCD) for chip coupling is provided. The first and second orientations that are substantially perpendicular to the first orientation can be defined on the substrate. The layout structure includes a plurality of lines, which extend along the second... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080246168 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises a semiconductor layer including a plurality of paralleled linear straight sections extending in a first direction. The layer also includes a plurality of connecting sections each having a width in the first direction sufficient to form a wire-connectable contact therein and arranged to connect between adjacent... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080237563 - Diode/superionic conductor/polymer memory structure: A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer... Agent: Dickstein Shapiro LLP

20080237562 - Phase change memory devices and fabrication methods thereof: Phase change memory devices and fabrication methods thereof. A phase change memory device comprises a stacked heating element with a conductive portion and a relatively high resistive portion, wherein the relatively high resistive portion includes a nitrogen-containing metal silicide part. The heating stacked element such as a highly resistive nitrogen-containing... Agent: Quintero Law Office, PC

20080237564 - Phase-change memory device using sb-se metal alloy and method of fabricating the same: Provided are a phase-change memory device using a phase-change material having a low melting point and a high crystallization speed, and a method of fabricating the same. The phase-change memory device includes an antimony (Sb)-selenium (Se) chalcogenide SbxSe100-x phase-change material layer contacting a heat-generating electrode layer exposed through a pore... Agent: Rabin & Berdo, PC

20080237567 - Optimized solid electrolyte for programmable metallization cell devices and structures: A microelectronic programmable structure suitable for storing information and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure,... Agent: Snell & Wilmer L.L.P. (main)

20080237566 - Phase change memory device and method of fabricating the same: A phase change memory device and method of manufacturing the same is provided. A first electrode having a first surface is provided on a substrate. A second electrode having a second surface at a different level from the first surface is on the substrate. The second electrode may be spaced... Agent: Harness, Dickey & Pierce, P.L.C

20080237565 - Phase change memory device to prevent thermal cross-talk and method for manufacturing the same: A phase change memory device for preventing thermal cross-talk includes lower electrodes respectively formed in a plurality of phase change cell regions of a semiconductor substrate. A first insulation layer is formed on the semiconductor substrate including the lower electrodes having holes for exposing the respective lower electrodes. Heaters are... Agent: Ladas & Parry LLP

20080237568 - Methods of making nano-scale structures having controlled size, nanowire structures and methods of making the nanowire structures: Methods of making nanometer-scale semiconductor structures with controlled size are disclosed. Semiconductor structures that include one or more nanowires are also disclosed. The nanowires can include a passivation layer or have a hollow tube structure.... Agent: Hewlett Packard Company

20080237570 - Light emitting diode having well and/or barrier layers with superlattice structure: A light emitting diode (LED) having well and/or barrier layers with a superlattice structure is disclosed. An LED has an active region between an N-type GaN-based semiconductor compound layer and a P-type GaN-based semiconductor compound layer, wherein the active region comprises well and/or barrier layers with a superlattice structure. As... Agent: H.c. Park & Associates, PLC

20080237571 - Semiconductor light emitting device and nitride semiconductor light emitting device: The present invention is a semiconductor light emitting device including an n-type semiconductor layer, an active layer, a first p-type semiconductor layer between the n-type semiconductor layer and the active layer, and a second p-type semiconductor layer on the opposite side of the first p-type semiconductor layer from the active... Agent: Harness, Dickey & Pierce, P.L.C

20080237569 - Semiconductor light emitting element, method for manufacturing the same, and light emitting device: The present invention provides a semiconductor light emitting element with excellent color rendering properties, a method for manufacturing the semiconductor light emitting element, and a light emitting device. The semiconductor light emitting element includes: a semiconductor substrate that has a convex portion having a tilted surface as an upper face,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080237572 - Forming a type i heterostructure in a group iv semiconductor: In one embodiment, the present invention includes a method for forming a transistor that includes forming a first buffer layer of silicon germanium tin (SiGe(Sn)) on a silicon (Si) substrate, forming a barrier layer on the first buffer layer, the barrier layer comprising silicon germanium (Si1-xGex), and forming a quantum... Agent: Trop Pruner & Hu, PC

20080237573 - Mechanism for forming a remote delta doping layer of a quantum well structure: A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20080237574 - Metal-base nanowire transistor: A metal-base transistor is suggested. The transistor comprises a first and a second electrode (2, 6) and base electrode (6) to control current flow between the first and second electrode. The first electrode (2) is made from a semiconduction material. The base electrode (3) is a metal layer deposited on... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080237575 - Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications: A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing... Agent: Intel Corporation C/o Intellevate, LLC

20080237577 - Forming a non-planar transistor having a quantum well channel: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer... Agent: Trop Pruner & Hu, PC

20080237578 - Ultrahigh density patterning of conducting media: A nanoscale device and a method for creating and erasing of nanoscale conducting regions at the interface between two insulating oxides SrTiO3 and LaAlO3 is provided. The method uses the tip of a conducting atomic force microscope to locally and reversibly switch between conducting and insulating states. This allows ultra-high... Agent: Foley And Lardner LLP Suite 500

20080237576 - Voltage controlled computing element for quantum computer: A computing element for use in a quantum computer has at least three coupled quantum dots, and at least one gate for applying an electric field to manipulate the state of said qubit.... Agent: Marks & Clerk

20080237579 - Quantum computing device and method including qubit arrays of entangled states using negative refractive index lenses: A quantum computing device and method employs qubit arrays of entangled states using negative refractive index lenses. A qubit includes a pair of neutral atoms separated by or disposed on opposite sides of a negative refractive index lens. The neutral atoms and negative refractive index lens are selectively energized and/or... Agent: Renner Otto Boisselle & Sklar, LLP

20080237581 - Device with phase-separated dielectric structure: An electronic device including in any sequence: (a) a semiconductor layer; and (b) a phase-separated dielectric structure comprising a lower-k dielectric polymer and a higher-k dielectric polymer, wherein the lower-k dielectric polymer is in a higher concentration than the higher-k dielectric polymer in a region of the dielectric structure closest... Agent: Patent Documentation Center

20080237585 - Flat panel display device and method of fabricating the same: A flat panel display device including a first region having an organic light emitting diode and a thin film transistor and a second region having a capacitor is disclosed. The capacitor comprises first, second, and third electrodes, where the area of a third capacitor electrode is reduced, thereby ensuring a... Agent: Knobbe Martens Olson & Bear LLP

20080237583 - Method for manufacturing semiconductor device, semiconductor device, semiconductor circuit, electro-optical device, and electronic apparatus: A method for manufacturing a semiconductor device includes: forming a source electrode and a drain electrode on a substrate; forming an organic semiconductor layer including a π conjugated organic compound at least between the source electrode and the drain electrode; applying an application liquid on the organic semiconductor layer, the... Agent: Harness, Dickey & Pierce, P.L.C

20080237584 - Organic component and electric circuit comprising said component: m

20080237580 - Organic semiconductor element and organic el display device using the same: It is provided an organic semiconductor element having an FET which can control a channel length to a small value and does not cause a rise in contact resistance due to a step portion, and an organic light emitting display device with a large aperture using the same. A first... Agent: Rabin & Berdo, PC

20080237582 - Thin film transistor array panel and manufacture thereof: A method for a thin film transistor array panel includes forming a gate line and a pixel electrode on a substrate, forming a gate insulating layer covering the gate line, forming a data line including a source electrode and a drain electrode on the gate insulating layer, forming an interlayer... Agent: Macpherson Kwok Chen & Heid LLP

20080237590 - Design structure for electrically tunable resistor: A design structure for an electrically tunable resistor. In one embodiment, the design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and includes a resistor including: a first resistive layer; at least one second resistive layer; and an intermediate interdiffused layer of... Agent: Hoffman Warnick LLC

20080237587 - Method and circuit for stressing upper level interconnects in semiconductor devices: A device or method for effectively stressing an interconnect in a test current path of a semiconductor device, which test current path is other than a current path used during normal operation of the semiconductor device. An operational voltage is adjusted to a test voltage, the test current path is... Agent: Posz Law Group, PLC

20080237588 - Method and semiconductor structure for monitoring etch characteristics during fabrication of vias of interconnect structures: By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective openings may be used for generating a corresponding variation of... Agent: J. Mike Amerson, Williams. Morgan & Amerson, P.C.

20080237592 - Semiconductor device and its test method: A second semiconductor chip including the operation of receiving operation instructions given from a first semiconductor chip and outputting a signal corresponding to it is mounted on mounting means. Internal wirings for interconnecting the first and second semiconductor chips, and external terminals respectively connected to the internal wirings are provided... Agent: Stanley P. Fisher Reed Smith LLP

20080237589 - Semiconductor device comprising circuit substrate with inspection connection pads and manufacturing method thereof: A semiconductor device includes a first circuit substrate having a plurality of lower wiring lines and a plurality of upper wiring lines on the lower surface side and upper surface side thereof, respectively. A second circuit substrate is provided on a lower side of the first circuit substrate, the second... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080237586 - Semiconductor integrated test structures for electron beam inspection of semiconductor wafers: Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to... Agent: F. Chau & Associates, LLC

20080237591 - Vertical system integration: The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use... Agent: Michael J. Ure

20080237593 - Semiconductor device, method of fabricating the same, and apparatus for fabricating the same: There is provided a semiconductor device including a substrate and a semiconductor film deposited on the substrate, characterized in that the semiconductor film has a laterally grown crystal having an end with a surface projection height smaller than the thickness of the semiconductor film. There are also provided a semiconductor... Agent: Edwards Angell Palmer & Dodge LLP

20080237594 - Pixel structure and manufacturing method thereof: A method of manufacturing a pixel structure is provided. A first patterned conductive layer including a gate and a data line is formed on a substrate. A gate insulating layer is formed to cover the first patterned conductive layer and a semiconductor channel layer is formed on the gate insulating... Agent: Jianq Chyun Intellectual Property Office

20080237595 - Thin film transistor including titanium oxides as active layer and method of manufacturing the same: Disclosed herein is a method of manufacturing a thin film transistor including titanium oxides as an active layer and the structure of the thin film transistor film manufactured using the method. The thin film transistor includes: a substrate; an active layer formed on the substrate using polycrystalline or amorphous titanium... Agent: Ked & Associates, LLP

20080237596 - Liquid crystal display device and fabrication method thereof: A liquid crystal display (LCD) includes: a first substrate divided into a pixel part and first and second pad parts; a gate electrode and a gate line formed at the pixel part of the first substrate; an active pattern formed as an island on the gate electrode and having a... Agent: Mckenna Long & Aldridge LLP

20080237598 - Thin film field effect transistor and display: A thin film field effect transistor including, on a substrate, at least a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode, wherein an electric resistance layer is provided in electric connection between the active layer and at least one of the source... Agent: Birch Stewart Kolasch & Birch

20080237597 - Thin film transistor array panel and manufacturing method thereof: A TFT array panel includes: first and second gate members connected to each other; a gate insulating layer formed on the first and the second gate members; first and second semiconductor members formed on the gate insulating layer opposite the first and the second gate members, respectively; first and second... Agent: F. Chau & Associates, LLC

20080237599 - Memory cell comprising a carbon nanotube fabric element and a steering element: A rewritable nonvolatile memory cell is disclosed comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of... Agent: Dugan & Dugan, PC

20080237600 - Thin film transistor: One embodiment of the present invention is a thin film transistor, including: an insulating substrate; a gate electrode, a gate insulating layer and a semiconductor layer including an oxide, these three elements being formed over the insulating substrate in this order, and the gate insulating layer including: a lower gate... Agent: Squire, Sanders & Dempsey L.L.P.

20080237601 - Transistors and semiconductor constructions: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer... Agent: Wells, St John, Roberts, Gregory & Matkin P.s. Suite 1300

20080237602 - Three dimensional nand memory: A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell, such that a defined boundary exists between the semiconductor active region... Agent: Foley And Lardner LLP Suite 500

20080237603 - Method of forming cmos transistors with dual-metal silicide formed through the contact openings and structures formed thereby: Methods and associated structures of forming a microelectronic device are described. Those methods may include amorphizing at least one contact area of a source/drain region of a transistor structure by implanting through at least one contact opening, forming a first layer of metal on the at least one contact area,... Agent: Intel Corporation C/o Intellevate, LLC

20080237604 - Plasma nitrided gate oxide, high-k metal gate based cmos device: In accordance with the invention, there are CMOS devices and semiconductor devices and methods of fabricating them. The CMOS device can include a substrate including a first active region and a second active region and a first transistor device over the first active region, wherein the first transistor device includes... Agent: Texas Instruments Incorporated

20080237606 - Compound semiconductor device: A compound semiconductor device having a transistor structure, includes a substrate, a first layer formed on the substrate and comprising GaN, a second layer formed over the first layer and containing InN whose lattice constant is larger than the first layer, a third layer formed over the second layer and... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080237607 - Light emitting element and method of making same: A light emitting element has a substrate of gallium oxides and a pn-junction formed on the substrate. The substrate is of gallium oxides represented by: (AlXInYGa(1-X-Y))2O3 where 0≦x≦1, 0≦y≦1 and 0≦x+y≦1. The pn-junction has first conductivity type substrate, and GaN system compound semiconductor thin film of second conductivity type opposite... Agent: Scully Scott Murphy & Presser, PC

20080237605 - Semiconductor device and manufacturing method of the same: A semiconductor device includes: a first semiconductor layer which is made of a first group III nitride semiconductor; a cap layer which is formed on the first semiconductor layer, which is made of a second group III nitride semiconductor, and which has an opening for exposing the first semiconductor layer;... Agent: Mcdermott Will & Emery LLP

20080237610 - Compound semiconductor device including ain layer of controlled skewness: A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080237609 - Low micropipe 100 mm silicon carbide wafer: A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 100 mm and a micropipe density of less than about 25 cm−2.... Agent: Summa, Allan & Additon, P.A.

20080237608 - Molybdenum barrier metal for sic schottky diode and process of manufacture: A method for fabricating a diode is disclosed. In one embodiment, the method includes forming a Schottky contact on an epitaxial layer of silicon carbide (SiC) and annealing the Schottky contact at a temperature in the range of 300° C. to 700° C. The Schottky contact is formed of a... Agent: Murabito, Hao & Barnes LLP

20080237611 - Electroluminescent device having improved contrast: A method for increasing ambient light contrast ratio within an electroluminescent device, including: a reflective electrode and a transparent electrode having an EL unit formed there-between. The EL unit includes a light-emitting layer containing quantum dots. Additionally, the method includes locating a contrast enhancement element on a side of the... Agent: David Novais Patent Legal Staff

20080237613 - Ac light emitting device having photonic crystal structure and method of fabricating the same: Disclosed is an AC light emitting device having photonic crystal structures and a method of fabricating the same. The light emitting device includes a plurality of light emitting cells and metallic wirings electrically connecting the light emitting cells with one another. Further, each of the light emitting cells includes a... Agent: H.c. Park & Associates, PLC

20080237612 - Device having spacers: An electroluminescent device comprising: a substrate; one or more light-emitting elements formed over the substrate, the one or more light-emitting elements including first and second spaced-apart electrodes wherein at least one of the first and second electrodes is transparent and a light-emitting layer comprising quantum dots formed between the first... Agent: David Novais Patent Legal Staff

20080237615 - Light-emitting device: A light-emitting device including: a substrate; a light-emitting diode; and an optical resonance layer to resonate light emitted from the light-emitting diode. The optical resonance layer includes a first layer, including a polysilsesquioxane-based copolymer. A linking group connecting two different silicon (Si) atoms of the polysilsesquioxane-based copolymer can be —O—,... Agent: Stein, Mcewen & Bui, LLP

20080237614 - Semiconductor light-emitting device: A semiconductor light-emitting device of the present invention includes a first LED chip whose emitted light is wavelength-converted by a fluorescent substance layer formed by applying and curing a fluorescent substance material, and a second LED chip whose emitted light is not wavelength-converted by the fluorescent substance layer, wherein the... Agent: Nixon & Vanderhye, PC

20080237616 - Semiconductor light emitting device and method for manufacturing the same: A semiconductor light emitting device, includes an active layer radiating a light having a predetermined wavelength; a first semiconductor layer of a first conductivity type, provided on the active layer. A semiconductor substrate has a first principal surface in contact with the active layer, a second principal surface facing the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080237617 - Adhesive sheet for light-emitting diode device and light-emitting diode device: [Problem] To provide an adhesive sheet which is used for a light-emitting diode device, and which is free from cracks and peeling off of the adhered portions. [Means for Solving the Problem] An adhesive sheet for a light-emitting diode device, which comprises a thermoplastic polymer containing epoxy groups and a... Agent: 3m Innovative Properties Company

20080237619 - Led with porous diffusing reflector: