Active solid-state devices (e.g., transistors, solid-state diodes) inventions 09/08

20080230762 - Phase change memory elements having a confined portion of phase change material on a recessed contact: Methods of fabricating phase change memory elements include forming an insulating layer on a semiconductor substrate, forming a through hole penetrating the insulating layer, forming a lower electrode in the through hole and forming a recess having a sidewall comprising a portion of the insulating layer by selectively etching a... Agent: Myers Bigel Sibley & Sajovec

20080230763 - Metallic nanospheres embedded in nanowires initiated on nanostructures and methods for synthesis thereof: A nanostructure includes a nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there between. A nanostructure in another embodiment includes a substrate having an area with a nanofeature; and a nanowire extending from... Agent: Llnl/zilka-kotab John H. Lee, Assistant Laboratory Counsel

20080230764 - Composite quantum dot structures: A composite quantum dot structure (4) comprises a charge carrier confinement region, such as a quantum dot (2), a barrier (5) and an electrically conductive layer (3). This structure allows the dimensions of the conductive layer (3) to be substantially independent of the size of the region (2), so that... Agent: Banner & Witcoff, Ltd.

20080230766 - Light emitting device: A light emitting element includes a group III nitride semiconductor substrate that emits a light by absorbing a UV ray and a light emitting diode structure. The light emitting diode structure is formed of a group III nitride semiconductor grown on the group III nitride semiconductor substrate, and has a... Agent: Rabin & Berdo, PC

20080230765 - Light emitting diode: AC LED according to the present invention comprises a substrate, and at least one serial array having a plurality of light emitting cells connected in series on the substrate. Each of the light emitting cells comprises a lower semiconductor layer consisting of a first conductive compound semiconductor layer formed on... Agent: H.c. Park & Associates, PLC

20080230772 - Display device and method of manufacturing the display device: A method of manufacturing a display device includes a step of forming an island-shaped first electrode, a step of forming a first insulation film, a step of forming a second insulation film, a step of removing the first insulation film, which is exposed from the second insulation film, in a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080230769 - Electronic device, field effect transistor including the electronic device, and method of manufacturing the electronic device and the field effect transistor: Provided is an electronic device, a field effect transistor having the electronic device, and a method of manufacturing the electronic device and the field effect transistor. The electronic device includes: a substrate; a first electrode and a second electrode which are formed in parallel to each other on the substrate,... Agent: Robert E. Bushnell

20080230778 - Method for manufacturing an organic semiconductor device, as well as organic semiconductor device, electronic device, and electronic apparatus: An organic semiconductor device having a gate electrode, a source electrode, a drain electrode, an organic semiconductor layer, a gate insulation layer, and a substrate. The substrate of the semiconductor device having an underlayer including an organic polymer material having a liquid crystal core. The underlayer is oriented in a... Agent: Oliff & Berridge, PLC

20080230777 - Method of making an organic light emitting device: The invention relates to a method of making an organic electronic device and articles.... Agent: 3m Innovative Properties Company

20080230775 - Organic light emitting display device and method for manufacturing the same: An organic light emitting display device and a method for manufacturing the same are disclosed. The method for manufacturing the organic light emitting display device includes forming a switching element and a silicon nitride layer over a substrate, patterning and removing a portion of the silicon nitride layer formed on... Agent: Macpherson Kwok Chen & Heid LLP

20080230770 - Organic light-emitting display panel and method of manufacturing the same: An organic light-emitting display panel having a storage capacitor comprised of a storage electrode overlapping a power line with a first gate-insulating layer disposed therebetween, wherein the storage capacitor includes a groove portion formed on a lateral side of the power line overlapping the storage electrode so that the overlapping... Agent: Macpherson Kwok Chen & Heid LLP

20080230776 - Organic semiconductor material and organic transistor using the same:

20080230774 - Organic thin-film transistor manufacturing method, organic thin-film transistor, and organic thin-film transistor sheet: An organic thin-film transistor manufacturing method and an organic thin-film transistor manufactured by the method are disclosed, the method comprising the steps of a) forming a gate electrode on a substrate, b) forming a gate insulating layer on the substrate, c) forming an organic semiconductor layer on the substrate, d)... Agent: Cantor Colburn, LLP

20080230773 - Polymer composition for preparing electronic devices by microcontact printing processes and products prepared by the processes: The present invention is directed to methods for patterning substrates using contact printing processes and inks comprising an organic semiconductive or semiconductive polymer, inks for use with the processes, and products formed by the processes.... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080230767 - Semiconductor device and method of manufacturing the same: Disclosed are a semiconductor device, which forms two insulation layers having different patterns by one mask process, and a method of manufacturing the same. In a semiconductor device having double insulation layers, a photosensitive material is included in an upper insulation layer. During a manufacture of the semiconductor device, the... Agent: Christie, Parker & Hale, LLP

20080230771 - Thin film transistor and method for manufacturing the same: It is made possible to provide a thin film transistor having transistor characteristics that do not widely vary. A thin film transistor includes: a substrate; a pair of insulating layers formed at a distance from each other on the substrate; a source electrode formed on one of the insulating layers,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080230768 - Thin film transistor and organic light emitting device including thin film transistor: The present invention relates to a thin film transistor. The thin film transistor includes a semiconductor having first, second, third, fourth, and fifth electrode regions arranged in a direction and spaced apart from each other and first, second, third, and fourth offset regions disposed between the first, second, third, fourth,... Agent: H.c. Park & Associates, PLC

20080230779 - [100] or [110] aligned, semiconductor-based, large-area, flexible, electronic devices: Novel articles and methods to fabricate the same resulting in flexible, large-area, [100] or [110] textured, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices,... Agent: Dr. Amit Goyal

20080230780 - Group iii nitride semiconductor multilayer structure: The inventive Group III nitride semiconductor multilayer structure comprises a substrate; an AlxGa1-xN (0≦x≦1) buffer layer which is provided on the substrate and has a columnar or island-like crystal structure; and an AlxInyGa1-x-yN (0≦x≦1, 0≦y≦1, 0≦x+y≦1) single-crystal layer provided on the buffer layer, wherein the substrate has, on its surface,... Agent: Sughrue Mion, PLLC

20080230781 - Method of forming an oxygen- or nitrogen-terminated silicon nanocrystalline structure and an oxygen- or nitrogen-terminated silicon nanocrystalline structure formed by the method: Thereby, a silicon nanocrystalline structure can be formed on a silicon substrate by using a process of producing silicon integrated circuits with achieving high luminous efficiency, and terminating reliably with oxygen or nitrogen on the surface thereof. According to the method of the present invention, the particle diameter of the... Agent: Wenderoth, Lind & Ponack, L.L.P.

20080230782 - Photoconductive devices with enhanced efficiency from group iv nanoparticle materials and methods thereof: A device for generating a plurality of electron-hole pairs from a photon is disclosed. The device includes a substrate, a first electrode formed above the substrate, and a first doped Group IV nanoparticle thin film deposited on the first electrode. The device further includes an intrinsic layer deposited on the... Agent: Foley & Lardner LLP

20080230783 - Image sensor and method for manufacturing the same: An image sensor and a method for manufacturing the same are provided. The image sensor can include: a semiconductor substrate including a circuit area; a metal interconnection layer including a metal interconnection and a an interlayer dielectric layer on the semiconductor substrate; a first conductive-type pattern on the metal interconnection... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080230784 - Cascode circuit employing a depletion-mode, gan-based fet: A circuit includes an input drain, source and gate nodes. The circuit also includes a group III nitride depletion mode FET having a source, drain and gate, wherein the gate of the depletion mode FET is coupled to a potential that maintains the depletion mode FET in its on-state. In... Agent: Mayer & Williams PC

20080230786 - High temperature performance capable gallium nitride transistor: A transistor device capable of high performance at high temperatures. The transistor comprises a gate having a contact layer that contacts the active region. The gate contact layer is made of a material that has a high Schottky barrier when used in conjunction with a particular semiconductor system (e.g., Group-III... Agent: Koppel, Patrick & Heybl

20080230785 - Termination and contact structures for a high voltage gan-based heterojunction transistor: A semiconductor device is provided that includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between... Agent: Mayer & Williams PC

20080230787 - Silicon carbide semiconductor device, and method of manufacturing the same: The silicon carbide semiconductor device includes a trench formed from a surface of a drift layer of a first conductivity type formed on a substrate of the first conductivity type, and a deep layer of a second conductivity type located at a position in the drift layer beneath the bottom... Agent: Posz Law Group, PLC

20080230789 - Light emitting device, method of manufacturing the same and monolithic light emitting diode array: A light emitting device including: at least one light emitting stack including first and second conductivity type semiconductor layers and an active layer disposed there between, the light emitting stack having first and second surfaces and side surfaces interposed between the first and second surfaces; first and second contacts formed... Agent: Mcdermott Will & Emery LLP

20080230788 - Liquid crystal display panel: A liquid crystal display (LCD) panel is provided. The LCD panel includes an active device array substrate, an opposite substrate, and a liquid crystal layer. The active device array substrate includes a plurality of pixel units, and each of the pixel units has a reflective area and a transmissive area.... Agent: Jianq Chyun Intellectual Property Office

20080230790 - Semiconductor light emitting device: A semiconductor light emitting device has an outer lead disposed along an outer wall of a mold resin portion perpendicular to a light-emitting plane of a light emitting diode. An outer lead is also disposed at an outer wall of the mold resin portion parallel to and opposite to the... Agent: Morrison & Foerster LLP

20080230791 - Optoelectronic device: An optoelectronic device such as a light-emitting diode chip is disclosed. It includes a substrate, a multi-layer epitaxial structure, a first metal electrode layer, a second metal electrode layer, a first bonding pad and a second bonding pad. The multi-layer epitaxial structure on the transparent substrate comprises a semiconductor layer... Agent: Bacon & Thomas, PLLC

20080230793 - Patterned substrate for light emitting diode and light emitting diode employing the same: Disclosed herein are a patterned substrate for a light emitting diode and a light emitting diode employing the patterned substrate. The substrate has top and bottom surfaces. Protrusion patterns are arranged on the top surface of the substrate. Furthermore, recessed regions surround the protrusion patterns. The recessed regions have irregular... Agent: H.c. Park & Associates, PLC

20080230792 - Semiconductor light-emitting device with electrode for n-polar ingaain surface: One embodiment of the present invention provides a semiconductor light-emitting device, which comprises: an upper cladding layer; a lower cladding layer; an active layer between the upper and lower cladding layers; an upper ohmic-contact layer forming a conductive path to the upper cladding layer; and a lower ohmic-contact layer forming... Agent: Park, Vaughan & Fleming LLP

20080230794 - Pn junction type group iii nitride semiconductor light-emitting device: A pn junction type Group III nitride semiconductor light-emitting device 10 (11) of the present invention has a light-emitting layer 2 of multiple quantum well structure in which well layers 22 and barrier layers 21 including Group III nitride semiconductors are alternately stacked periodically between an n-type clad layer 105... Agent: Sughrue Mion, PLLC

20080230795 - Light emitting diode: A light emitting diode and a method of producing white light from the light emitting diode with an active region producing an emission falling in a primary wavelength range. A first part of the active region covered with a first conversion element for converting the emission falling in the primary... Agent: Grant A. Johnson IBM Corporation, Dept. 917

20080230796 - Surface mount type light-emitting diode package device and light-emitting element package device: The present invention discloses a surface mount type light-emitting diode package device and a light-emitting element package device. In the device, the encapsulation layer comprises an encapsulation material and at least one material having a refraction index different from the encapsulation material distributed therein. The distribution of the material having... Agent: North America Intellectual Property Corporation

20080230798 - Active matrix organic electroluminescent substrate and method of making the same: An active matrix organic electroluminescent substrate includes a substrate having a controlling element region and a luminescent region, a thin film transistor, a first passivation layer, a conductive layer electrically connected to the thin film transistor, and a second passivation layer disposed on the first passivation layer and the conductive... Agent: North America Intellectual Property Corporation

20080230797 - Led module and manufacturing method thereof: An LED module and a manufacturing method thereof are disclosed. The LED module includes a PCB and an LED chip connected with the PCB and a light congregating cup mounted on the PCB. Two ends of the light congregating cup define two hatches, the two hatches run-through each other and... Agent: Rosenberg, Klein & Lee

20080230799 - Semiconductor light-emitting device with electrode for n-polar ingaain surface: One embodiment of the present invention provides a semiconductor light-emitting device. The semiconductor light-emitting device includes a substrate, a p-type doped InGaAIN layer, an n-type doped InGaAIN layer, and an active layer situated between the p-type doped and n-type doped InGaAIN layers. The semiconductor light-emitting device further includes an n-side... Agent: Park, Vaughan & Fleming LLP

20080230800 - N-type group iii nitride semiconductor layered structure: An object of the present invention is to provide a low-resistance n-type Group III nitride semiconductor layered structure having excellent flatness and few pits. The inventive n-type group III nitride semiconductor layered structure comprises a substrate and, stacked on the substrate, an n-type impurity concentration periodic variation layer comprising an... Agent: Sughrue Mion, PLLC

20080230801 - Trench type power semiconductor device and method for manufacturing same: A method for manufacturing a trench type power semiconductor device is provided. The method includes: forming a first silicon oxide film on a silicon substrate; forming a thermal oxidation-resistant film on the first silicon oxide film; forming an opening in the first silicon oxide film and the thermal oxidation-resistant film;... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080230803 - Integrated contact interface layer: A semiconductor device that is fabricated by metamorphic epitaxial growth processes, and includes a combined graded base and active layer having a thickness less than 5000 Å. In one non-limiting embodiment, the semiconductor device is an HBT device that includes a combined doped graded buffer and sub-collector layer having a... Agent: MillerIPGroup, PLC Northrop Grumman Corporation

20080230804 - Semiconductor device and fabrication method of same: A semiconductor device having an electrode with reduced electrical contact resistance even where either electrons or holes are majority carriers is disclosed. This device has an n-type diffusion layer and a p-type diffusion layer in a top surface of a semiconductor substrate. The device also has first and second metal... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080230805 - Semiconductor device and method of manufacturing semiconductor device: In one aspect of the present invention, a semiconductor device may include a Si substrate, a gate electrode provided on the semiconductor via a gate dielectric layer, a first epitaxially grown layer provided on the Si substrate, a channel region provided in the Si substrate below the gate electrode, a... Agent: Amin, Turocy & Calvin, LLP

20080230802 - Semiconductor device comprising a heterojunction: A semiconductor device with a heterojunction. The device comprises a substrate and at least one nanostructure. The substrate and nanostructure is of different materials. The substrate may e.g. be of a group IV semiconductor material, whereas the nanostructure may be of a group III-V semiconductor material. The nanostructure is supported... Agent: Philips Intellectual Property & Standards

20080230806 - Hbt and field effect transistor integration: Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BIFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the... Agent: Lahive & Cockfield, LLP Floor 30, Suite 3000

20080230808 - Heterojunction bipolar transistor: A base layer made of SiGe mixed crystal includes a spacer layer formed in contact with a collector layer with no base impurities diffused therein and an intrinsic base layer formed in contact with an emitter layer with base impurities diffused therein. The spacer layer contains C at a low... Agent: Mcdermott Will & Emery LLP

20080230807 - Semiconductor device: A semiconductor device having sufficiently high heat dissipation performance while inhibiting an increase in the area of a chip is provided. In semiconductor device 1, a plurality of HBTs 20 and a plurality of diodes 30 are one-dimensionally and alternately arranged on semiconductor substrate 10. Anode electrode 36 of diode... Agent: Young & Thompson

20080230809 - Semiconductor device and method of fabricating the same: A sophisticated semiconductor device capable of being fabricated without introducing a high-precision exposure apparatus is obtained. This semiconductor device includes a conductive layer formed on a first conductivity type collector layer, a first conductivity type emitter electrode formed on the conductive layer and a protruding portion protruding from an outer... Agent: Mcdermott Will & Emery LLP

20080230810 - Insulated gate semiconductor device: An isolation region is provided around a sense part. The isolation region is provided to have a depth that suppresses spread of a region with an uneven current distribution, which occurs at a peripheral edge of the sense part. Thus, in the sense part, an influence of the region with... Agent: Morrison & Foerster LLP

20080230811 - Semiconductor structure: The invention relates to a semiconductor structure, especially for use in a semiconductor detector. The semiconductor structure includes a weakly doped semiconductor substrate (HK) of a first or second doping type, a highly doped drain region (D) of a second doping type, located on a first surface of the semiconductor... Agent: Caesar, Rivise, Bernstein, Cohen & Pokotilow, Ltd.

20080230812 - Isolated junction field-effect transistor: Various integrated circuit devices, in particular a junction field-effect transistor (JFET), are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have... Agent: Patentability Associates

20080230813 - Semiconductor device and manufacturing method therefor: An MMIC 100 is a semiconductor device which includes an FET formed on a GaAs substrate 10 and an MIM capacitor having a dielectric layer 20b arranged between a lower electrode 18b and an upper electrode 22b. A method for manufacturing the MMIC 100 is provided, in which a source... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080230814 - Methods for fabricating a semiconductor device: A method for fabricating a semiconductor device comprises providing a silicon-containing substrate with first, second, and third regions. First, second, and third gate stacks respectively overlie a portion of the silicon-containing substrate in the first, second, and third regions. A spacer is formed on opposing sidewalls of each of the... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080230815 - Mitigation of gate to contact capacitance in cmos flow: Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate... Agent: Texas Instruments Incorporated

20080230816 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device has forming a first silicon film over the first insulating film, forming a second silicon film over the first silicon film, a first etching the second silicon film in a depth, which the first silicon film is not exposed, in first condition, a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080230817 - Semiconductor photodetector device: A semiconductor photodetector device includes a light receiving operation section converting incident light to an electric signal and a current amplifying operation section amplifying the electric signal. The light receiving operation section includes: a first conductivity type semiconductor layer a formed on a first conductivity type semiconductor substrate; a second... Agent: Mcdermott Will & Emery LLP

20080230818 - Non-volatile memory device: According to an aspect of the present invention, there is provided a non-volatile memory including: a transistor formed on a semiconductor substrate, the transistor including: two diffusion layers and a gate therebetween; a first insulating film formed on a top and a side surfaces of the gate; a first and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080230819 - Spin transfer magnetic element with free layers having high perpendicular anisotropy and in-plan equilibrium magnetization: A method and system for providing a magnetic element that can be used in a magnetic memory is disclosed. The magnetic element includes pinned, nonmagnetic spacer, and free layers. The spacer layer resides between the pinned and free layers. The free layer can be switched using spin transfer when a... Agent: Strategic Patent Group, P.C.

20080230820 - Semiconductor device: Coexistence of the realization of high-capacity of a capacitive element and the area reduction of a semiconductor device is aimed at. A plurality of capacitive elements from which a kind differs mutually are accumulated and arranged on a semiconductor substrate, and they are connected in parallel. These capacitive elements are... Agent: Miles & Stockbridge PC

20080230821 - Semiconductor device: In a semiconductor device which can perform data communication through wireless communication, to suppress transmission and the like of an AC signal, the semiconductor device includes an input circuit to which a radio signal is input, a first circuit, which generates a constant voltage, such as a constant voltage circuit... Agent: Eric Robinson

20080230822 - Vertical trench memory cell with insulating ring: A method of forming a vertical transistor trench memory cell having an insulating ring is provided. The method includes forming a semiconductor material region in an etched portion of a semiconductor substrate; partially etching the semiconductor material region to form a deep trench, where the deep trench extends beyond the... Agent: International Business Machines Corporation Dept. 18g

20080230823 - Semiconductor device and manufacturing method therefor: In an MMIC 100 in which an FET as an active element and the MIM capacitor are formed on a GaAs substrate 10, for example, a source electrode 16a and a drain electrode 16b, which are ohmic electrodes of the FET, are manufactured simultaneously with a lower electrode 16c of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080230824 - Double gate non-volatile memory device and method of manufacturing: The present invention relates to a non-volatile memory device on a substrate layer comprising semiconductor source and drain regions, a semiconductor channel region, a charge storage stack and a control gate; the channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080230826 - Construction of flash memory chips and circuits from ordered nanoparticles: Methods, apparatus and systems form memory structures, such as flash memory structures from nanoparticles by providing a source of nanoparticles as a conductive layer. The particles are moved by application of a field, such as an electrical field, magnetic field and even electromagnetic radiation. The nanoparticles are deposited onto an... Agent: Mark A. Litman & Associates, P.A. York Business Center

20080230825 - Nonvolatile semiconductor memory device: The invention relates to a nonvolatile semiconductor memory device including a semiconductor layer which has a source region, a drain region, and a channel forming region which is provided between the source region and the drain region; and a first insulating layer, a first gate electrode, a second insulating layer,... Agent: Nixon Peabody, LLP

20080230827 - Scalable flash/nv structures and devices with extended endurance: Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel medium, a high K charge blocking and charge storing medium, and an injector medium. The high K... Agent: Schwegman, Lundberg & Woessner/micron

20080230828 - Gate structure of a non-volatile memory device and method of manufacturing same: A non-volatile memory device includes a substrate that is divided into a field region and an active region by isolation layer patterns. The active region has an active trench for increasing an effective area of the active region. A tunnel oxide layer is formed on the active region. A floating... Agent: Marger Johnson & Mccollom, P.C.

20080230829 - Memory device and method of fabricating the same: A memory device and a method of fabricating the same. The memory device includes a substrate and a first gate electrode overlying the substrate. Overlying a top surface of the first gate electrode, a second gate electrode comprises end portions extending to spaces adjacent to the substrate and sidewalls of... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080230830 - Nonvolatile memory device and method of fabricating the same: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions... Agent: Lowe Hauptman Ham & Berner, LLP

20080230831 - Semiconductor device and manufacturing method thereof: A charge retention characteristic of a nonvolatile memory transistor is improved. A first insulating film that functions as a tunnel insulating film, a charge storage layer, and a second insulating film are sandwiched between a semiconductor substrate and a conductive film. The charge storage layer is formed of two silicon... Agent: Eric Robinson

20080230832 - Transistor and method for fabricating the same: A method for fabricating a semiconductor device to enlarge a channel region is provided. The channel region is enlarged due to having pillar shaped sidewalls of a transistor. The transistor includes a fin active region vertically protruding on a substrate, an isolation layer enclosing a lower portion of the fin... Agent: Townsend And Townsend And Crew, LLP

20080230833 - Semiconductor component and method for producing a semiconductor component: A semiconductor component having a semiconductor body having first and second semiconductor regions of a first conduction type, and a third semiconductor region of a second conduction type, which is complementary to the first conduction type. The second semiconductor region is arranged between the first and third semiconductor region and... Agent: Dickstein Shapiro LLP

20080230834 - Semiconductor apparatus having lateral type mis transistor: A semiconductor apparatus comprises: a semiconductor substrate; and a lateral type MIS transistor disposed on a surface part of the semiconductor substrate. The lateral type MIS transistor includes: a line coupled with a gate of the lateral type MIS transistor; a polycrystalline silicon resistor that is provided in the line,... Agent: Posz Law Group, PLC

20080230837 - Radiation-hardened silicon-on-insulator cmos device, and method of making the same: A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire layer is greater than peak impurity... Agent: San Francisco Office Of Novak, Druce & Quigg LLP

20080230836 - Semiconductor device and boost circuit: A semiconductor device includes a transistor that is used for a charge pump circuit, being configured with a fully depleted silicon-on-insulator transistor.... Agent: Oliff & Berridge, PLC

20080230835 - Semiconductor device and manufacturing method thereof: It is an object to provide an element structure of a semiconductor device for having a sufficient contact area between an electrode in contact with a source region or a drain region and the source region or the drain region, and a method for manufacturing the semiconductor device with the... Agent: Nixon Peabody, LLP

20080230838 - Semiconductor memory device and manufacturing process therefore: For solving the problem, while maintaining a structure where an MOS type transistor in a memory cell region is in a floating state and an MOS type transistor in the region other than the memory cell region is not in a floating state, a film thickness of semiconductor layers having... Agent: Mcginn Intellectual Property Law Group, PLLC

20080230839 - Method of producing a semiconductor structure: The invention is related to a method of producing a semiconductor structure comprising the steps of: fabricating a gate stack structure and oxidizing at least a portion of the gate stack structure's sidewalls, wherein the step of oxidizing is carried out at a temperature below 500° C. using a process... Agent: Slater & Matsil, L.L.P.

20080230840 - Ultra shallow junction formation by epitaxial interface limited diffusion: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080230841 - Integrated circuit system employing stress memorization transfer: An integrated circuit system that includes: providing a gate and a spacer formed over a substrate; performing an implant that amorphizes the gate and a source/drain region defined by the spacer; removing the spacer; depositing a stress memorization layer over the integrated circuit system; and transferring a stress from the... Agent: Law Offices Of Mikio Ishimaru

20080230842 - Semiconductor device having high-k gate dielectric layer and method for manufacturing the same: A semiconductor device having a high-K gate dielectric layer includes a p-type well that is formed in an upper layer of a silicon substrate. Arsenic ions are implanted into an extreme surface layer of the p-type well and a heat treatment is performed to form a p-type low-concentration layer. A... Agent: Rohm Co., Ltd. C/o Keating & Bennett, LLP

20080230843 - Isolation structure for mos transistor and method for forming the same: A method for forming isolation structure for MOS transistor is disclosed, which includes forming a first photoresist layer over a sacrificed oxide layer of a semiconductor substrate, patterning the first photoresist layer to define a PMOS active region and a PMOS isolation region; implanting nitrogen ions into the PMOS isolation... Agent: Squire, Sanders & Dempsey L.L.P.

20080230844 - Semiconductor device with multiple silicide regions: A system and method for forming a semiconductor device with a reduced source/drain extension parasitic resistance is provided. An embodiment comprises implanting two metals (such as ytterbium and nickel for an NMOS transistor or platinum and nickel for a PMOS transistor) into the source/drain extensions after silicide contacts have been... Agent: Slater & Matsil, L.L.P.

20080230845 - Semiconductor device and method of forming the same: A semiconductor device may include, but is not limited to, a single crystal silicon diffusion layer, a polycrystal silicon conductor, and a diffusion barrier layer. The diffusion barrier layer separates the polycrystal silicon conductor from the single crystal silicon diffusion layer. The diffusion barrier layer prevents a diffusion of at... Agent: Young & Thompson

20080230846 - Method of manufacturing metal silicide contacts: A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed... Agent: Texas Instruments Incorporated

20080230847 - Semiconductor device and manufacturing method of the same: The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed... Agent: Miles & Stockbridge PC

20080230848 - Structure having dual silicide region and related method: A structure including a dual silicide region and a related method are disclosed. The structure may include a doped silicon, and a dual silicide region in the doped silicon, the dual silicide region including a first silicide region including a mid band gap metal, and a second silicide region including... Agent: Hoffman Warnick LLC

20080230849 - Device comprising doped nano-component and method of forming the device: A device comprising a doped semiconductor nano-component and a method of forming the device are disclosed. The nano-component is one of a nanotube, nanowire or a nanocrystal film, which may be doped by exposure to an organic amine-containing dopant. Illustrative examples are given for field effect transistors with channels comprising... Agent: Connolly Bove Lodge & Hutz LLP

20080230850 - Method of manufacturing a semiconductor device and semiconductor device: A method of manufacturing a semiconductor device has forming a first mask pattern exposing a region for forming a first transistor and a region for forming a second transistor, performing a first ion implantation using the first mask pattern, performing a second ion implantation using the first mask pattern, removing... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080230851 - Metal oxide semiconductor (mos) type semiconductor device and manufacturing method thereof: A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type transistor structure, an additional load capacitance is... Agent: Dla Piper US LLP

20080230852 - Fabrication of finfets with multiple fin heights: A semiconductor structure includes a first semiconductor strip extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the first semiconductor strip has a first height. A first insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the first semiconductor strip,... Agent: Slater & Matsil, L.L.P.

20080230853 - Transistor and method of manufacturing the same: In a transistor and a method of manufacturing the same, the transistor includes a channel layer arranged on a substrate, a source electrode and a drain electrode formed on the substrate so as to contact respective ends of the channel layer, a gate insulating layer surrounding the channel layer between... Agent: Robert E. Bushnell

20080230854 - Semiconductor device containing crystallographically stabilized doped hafnium zirconium based materials: A semiconductor device, such as a transistor or capacitor is provided. The device includes a substrate, a gate dielectric over the substrate, and a conductive gate dielectric film over the gate dielectric. The gate dielectric includes a doped hafnium zirconium oxide containing one or more dopant elements selected from Group... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080230855 - Gate strip with reduced thickness: A semiconductor structure with reduced inter-diffusion is provided. The semiconductor structure includes a semiconductor substrate; a first well region in the semiconductor substrate; a second well region in the semiconductor substrate; an insulating region between and adjoining the first and the second well regions; a gate dielectric layer on the... Agent: Slater & Matsil, L.L.P.

20080230856 - Intermediate probe structures for atomic force microscopy: An intermediate probe structure for atomic force microscopy is disclosed. The probe structure comprises a semiconductor substrate with one or more moulds formed on a surface of one side of the substrate. The probe structure further comprises one or more probe configurations formed on the one side of the semiconductor... Agent: Knobbe Martens Olson & Bear LLP

20080230857 - Sensor chip and substrate assembly for mems device: A sensor chip and substrate assembly for use in a MEMS device includes a substrate and a sensor chip. The substrate has a top surface, a bottom surface opposite to the top surface, and a passage obliquely penetrating through the top surface and the bottom surface. The sensor chip is... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080230858 - Multi-layer package structure for an acoustic microsensor: A multi-layer package structure for an acoustic microsensor, the package structure mainly utilizes a stack of multiple substrates for housing and protecting circuit elements such that integrated circuit element and acoustic microsensor arranged in recessions of a substrate can reduce volume of the package structure. By adding various sound hole... Agent: Wpat, PC

20080230859 - Saw devices, processes for making them, and methods of use: The design, fabrication, post-processing and characterization of a novel SAW (Surface Acoustic Wave) based bio/chemical sensor in CMOS technology is introduced. The sensors are designed in AMI 1.5 μm 2 metal, 2 poly process. A unique maskless post processing sequence is designed and completed. The three post-processing steps are fully... Agent: Juneau Partners

20080230860 - Integrated cirucit package and method for fabrication thereof: The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device, a barrier formed between... Agent: Birch Stewart Kolasch & Birch

20080230861 - Cmos front end process compatible low stress light shield: An improved imaging device having a pixel arrangement featuring a multilayer light shield. The multilayer light shield includes stacked layers of light-shielding and light-transparent material. The light-transparent material, such as a dielectric, is selected to have a stress, such as a tensile stress, that offsets the stress, such as a... Agent: Dickstein Shapiro LLP

20080230862 - Method, apparatus, material, and system of using a high gain avalanche photodetector transistor: Here, we demonstrate new material/structures for the photodetectors, using semiconductor material. For example, we present the Tunable Avalanche Wide Base Transistor as a photodetector. Particularly, SiC, GaN, AlN, Si and Diamond materials are given as examples. The desired properties of an optimum photodetector is achieved. Different variations are discussed, both... Agent: Maxvalueip Consulting

20080230863 - Methods and apparatus for manufacturing semiconductor devices: In accordance with the teachings of the present disclosure, methods and apparatus are provided for a semiconductor device having thin anti-reflective layer(s) operable to absorb radiation that may otherwise reflect off surfaces disposed inwardly from the anti-reflective layer(s). In a method embodiment, a method for manufacturing a semiconductor device includes... Agent: Texas Instruments Incorporated

20080230864 - Image sensor and method for manufacturing the same: Disclosed is an image sensor which includes a plurality of pixel patterns formed on corresponding metal interconnections of an interlayer dielectric and a dummy pixel pattern formed between adjacent pixel patterns of the plurality of the pixel patterns. The dummy pixel patterns are not formed connected to the metal interconnections.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080230865 - Image sensor and method for manufacturing the same: An image sensor and method of manufacturing the same are provided. According to an embodiment, the image sensor comprises: a circuit including an interconnection on a substrate; a lower electrode on the interconnection; a separated intrinsic layer on the lower electrode; a second conductive type conduction layer on the separated... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080230866 - Rfid temperature sensing wafer, system and method: A system and method for manufacturing semiconductor wafers comprising an RFID temperature sensor and generally described herein. Other embodiments may be described and claimed.... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20080230867 - Method of forming ohmic contact to a semiconductor body: A process for forming an ohmic contact on the back surface of a semiconductor body includes depositing a donor layer on the back surface of the semiconductor body followed by a sintering step to form a shallow intermetallic region capable of forming a low resistance contact with a contact metal.... Agent: Ostrolenk Faber Gerb & Soffen

20080230868 - Pattern enhancement by crystallographic etching: A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to... Agent: Scully, Scott, Murphy & Presser, P.C.

20080230869 - Ultra-thin soi vertical bipolar transistors with an inversion collector on thin-buried oxide (box) for low substrate-bias operation and methods thereof: The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such... Agent: Scully, Scott, Murphy & Presser, P.C.

20080230870 - Input protection circuit preventing electrostatic discharge damage of semiconductor integrated circuit: An input protection circuit comprises a semiconductor chip, an internal circuit disposed on the semiconductor chip, a first input/output terminal which is disposed on the semiconductor chip and connected to the internal circuit, a second input/output terminal which is disposed on the semiconductor chip, connected to the internal circuit and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080230871 - Semiconductor display device and method of manufacturing the same: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer... Agent: Nixon Peabody, LLP

20080230872 - Bipolar transistor and method for manufacturing the same: A bipolar transistor and a method for manufacturing the same. The bipolar transistor can include a collector region formed in a substrate, an epitaxial layer formed over the substrate including the collector region, a base region formed in the epitaxial layer, an emitter region formed in the base region, an... Agent: Sherr & Nourse, PLLC

20080230874 - Semiconductor device and method of producing semiconductor device: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080230873 - Semiconductor device with capacitor and/or inductor and method of making: An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die... Agent: Freescale Semiconductor, Inc. Law Department

20080230875 - Duv laser annealing and stabilization of sicoh films: A method of fabricating a dielectric film comprising atoms of Si, C, O and H (hereinafter SiCOH) that has improved insulating properties as compared with prior art dielectric films, including prior art SiCOH dielectric films that are not subjected to the inventive deep ultra-violet (DUV) is disclosed. The improved properties... Agent: Scully, Scott, Murphy & Presser, P.C.

20080230876 - Leadframe design for qfn package with top terminal leads: A semiconductor package includes a leadframe. A first lead finger has a lower portion, a connecting portion extending vertically upward from the lower portion, and a substantially flat, top portion. The top portion forms a top terminal lead structure. A second lead finger is electrically connected to the first lead... Agent: Quarles & Brady LLP

20080230877 - Semiconductor package having wire redistribution layer and method of fabricating the same: A semiconductor package and a method of fabricating the same. The method includes providing a semiconductor substrate on which a chip pad is formed. A wire redistribution layer connected to the chip pad is formed. An insulating layer which includes an opening exposing a portion of the wire redistribution layer... Agent: Stanzione & Kim, LLP

20080230878 - Leadframe based flip chip semiconductor package and lead frame thereof: A flip chip semiconductor package is disclosed according to the present invention, the flip chip semiconductor package comprises a chip that is mounted on and electrically connects to a leadframe via a plurality of solder bumps by means of flip chip, and an encapsulate that encapsulates the chip, the plurality... Agent: Edwards Angell Palmer & Dodge LLP

20080230879 - Methods and apparatus for flip-chip-on-lead semiconductor package: Fabrication of a semiconductor package includes placing a conductive material on a protrusion from a leadframe to form a first assembly, forming a non-conductive mask about the protrusion, and placing a die on the first assembly, the die having an active area. Fabrication can further include reflowing the conductive material... Agent: Paul D. Durkee Daly, Crowley, Mofford & Durkee, LLP

20080230880 - Leadframe array with riveted heat sinks: The invention provides improved rivet and heat sink arrangements in leadframes and IC packages. The invention discloses a semiconductor device leadframe array with numerous leadframes having integrated circuit sites provided for receiving individual integrated circuit chips. Support strips are arranged adjacent to and supporting the integrated circuit sites in an... Agent: Texas Instruments Incorporated

20080230882 - Chip package structure: A chip package structure includes a die pad of which at least a notch is formed on at least one side and opposite to a mold gate. The die pad contributes to accelerating the injection of an encapsulating material, so as to exhaust the air in the mold in time,... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20080230881 - Integrated circuit package system with lead support: An integrated circuit package system is provided including forming a paddle having an integrated circuit die thereover, an outer lead, and an inner lead between the paddle and the outer lead. The integrated circuit package system is also provided including placing a lead support over the inner lead without traversing... Agent: Law Offices Of Mikio Ishimaru

20080230885 - Chip hermetic package device and method for producing the same: A chip hermetic package device includes a substrate, a chip, a hermetic lid, a hermetic material and a post. The height of the post is larger than the thickness of the hermetic material. A method for producing a chip hermetic package includes the steps of: mounting the chip on the... Agent: Madson & Austin

20080230883 - Integrated circuit package system with molded strip protrusion: An integrated circuit package system includes an in-line strip, attaching an integrated circuit die over the in-line strip, and applying a molding material with a molded segment having a molded strip protrusion formed therefrom over the in-line strip.... Agent: Law Offices Of Mikio Ishimaru

20080230884 - Semiconductor device package having multi-chips with side-by-side configuration and method of the same: The present invention provides a semiconductor device package having multi-chips with side-by-side configuration comprising a substrate with die receiving through holes, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. A first die having first bonding... Agent: Abelman, Frayne & Schwab

20080230888 - Semiconductor device: A first memory chip (103a) and a second memory chip (103b) mounted in this order on one surface of a mounting board (101) each have a rectangular planar shape and include a plurality of electrode pads formed in a single line along one side of the rectangle. An electrode pad... Agent: Mcginn Intellectual Property Law Group, PLLC

20080230887 - Semiconductor package and the method of making the same: The present invention relates to semiconductor package and the method of making the same. The method of the invention comprises the following steps: (a) providing a first substrate; (b) mounting a first chip onto a surface of the first substrate; (c) forming a plurality of conductive elements on the surface... Agent: Volentine & Whitt PLLC

20080230886 - Stacked package module: A stacked package module is disclosed, which comprises: a first package structure comprising a first circuit board with a first chip embedded therein, wherein the first chip has a plurality of electrode pads, the first circuit board comprises a first surface, an opposite second surface, a plurality of first conductive... Agent: Bacon & Thomas, PLLC

20080230889 - Semiconductor package: A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using... Agent: Ostrolenk Faber Gerb & Soffen

20080230891 - Chip and wafer integration process using vertical connections: A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having... Agent: International Business Machines Corporation Dept. 18g

20080230890 - Structure and electronics device using the structure: A structure includes a circuit substrate including a first substrate and a second substrate. The first substrate has a region where an electronic component is to be mounted. The second substrate has a side surface connected to a first side surface of the first substrate. The structure further includes a... Agent: Procopio, Cory, Hargreaves & Savitch LLP

20080230892 - Chip package module: A chip package module is disclosed, which comprises a core plate and two rigid plates individually having a circuit layer. The core plate is sandwiched in between the two rigid plates to form a composite circuit board. Furthermore, the two rigid plates individually have a cavity to expose the surface... Agent: Bacon & Thomas, PLLC

20080230893 - Integrated circuit with package lid: Various integrated circuit packages, lids therefor and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing an integrated circuit package lid that has a surface adapted to face towards an integrated circuit, and forming a wetting film on the surface.... Agent: Timothy M Honeycutt Attorney At Law

20080230894 - Carbon nanotubes for active direct and indirect cooling of electronics device: A system for cooling a semiconductor device is disclosed. The system includes a lid encasing the semiconductor device, a first plurality of carbon nanotubes disposed within the lid, and a fluid system configured to pass a fluid through the lid. Furthermore, a second system for cooling a semiconductor device is... Agent: Osha Liang L.L.P./sun

20080230895 - Semiconductor package and the method for manufacturing the same: A method for manufacturing semiconductor packages is provided. The upper surface of a substrate has a plurality of slots and surface mount devices are positioned across the slots. In this circumstance, the space below the surface mount devices can be filled up with sealant as a result of the arrangement... Agent: Lowe Hauptman Ham & Berner, LLP

20080230896 - Copper die bumps with electromigration cap and plated solder: Embodiments of the invention include apparatuses and methods relating to copper die bumps with electromigration cap and plated solder. In one embodiment, an apparatus comprises an integrated circuit die, a plurality of copper bumps on a surface of the die, electromigration (EM) caps substantially covering a mating surface of the... Agent: Intel Corporation C/o Intellevate, LLC

20080230900 - Determining the placement of semiconductor components on an integrated circuit: Systems and methods are disclosed herein for determining the placement of a standard cell, representing a semiconductor component in a design stage, on an integrated circuit die. One embodiment of a method, among others, comprises analyzing regions of a semiconductor die with respect to the susceptibility of the region to... Agent: Avago Technologies, Ltd.

20080230897 - Method of manufacturing electronic device, substrate and semiconductor device: A method includes a step of forming a bump 104 having a projection 104B on an electrode pad 103 provided on a semiconductor chip 101, a step of exposing a part of the projection 104B to an upper surface of an insulating layer 105 formed on the semiconductor chip 101,... Agent: Rankin, Hill & Clark LLP

20080230899 - Semiconductor device and manufacturing method thereof: In a semiconductor device according to the present invention, a plurality of opening regions 5 to 8 are formed in an insulating film on a pad electrode 3. A metal layer 9 formed on the pad electrode 3 has a plurality of concave portions 10 to 13 formed therein by... Agent: Morrison & Foerster LLP

20080230898 - Semiconductor device and method for manufacturing thereof: A semiconductor device which includes a first semiconductor chip, a second semiconductor chip flip-chip bonded to the first semiconductor chip, a resin portion for sealing the first semiconductor chip and the second semiconductor chip such that a lower surface of the first semiconductor chip and an upper surface of the... Agent: Ingrassia Fisher & Lorenz, P.C.

20080230902 - Method of forming solder bump on high topography plated cu: A solder bump is formed on a high-topography, electroplated copper pad integrating a first and second passivation layer. A sacrifice layer is deposited over the second passivation layer. The sacrifice layer is lithographically patterned. A via is etched in the sacrifice layer. A solder bump is formed in the via.... Agent: Quarles & Brady LLP

20080230903 - Semiconductor chip, semiconductor device and method for producing the same: A semiconductor chip constitutes a semiconductor device in which a plurality of semiconductor chips are laminated. The semiconductor chip includes a plurality of terminals which are to be connected to another semiconductor chip. At least one terminal of the terminals has a higher height than that of another terminal.... Agent: Amin, Turocy & Calvin, LLP

20080230901 - Structure for controlled collapse chip connection with displaced captured pads: A structure, for controlled collapse chip connection (C4) between an integrated circuit (IC) and a substrate, that alleviates the adverse effects resulting from induced stresses in C4 solder joints, the structure includes: a first and second array defined on the ball limiting metallurgy (BLM) side of the IC; a first... Agent: Cantor Colburn LLP - IBM Fishkill

20080230906 - Contact structure having dielectric spacer and method: A contact structure and method of forming same are disclosed. The contact structure may include a metal body surrounded by a dielectric spacer, the metal body and the dielectric spacer positioned within an interlevel dielectric layer, wherein the metal body is electrically coupled to a silicide region below a lowermost... Agent: Hoffman Warnick LLC

20080230904 - Gallium nitride-based iii-v group compound semiconductor device and method of manufacturing the same: The present invention relates to a gallium nitride-based compound semiconductor device and a method of manufacturing the same. According to the present invention, there is provided a gallium nitride-based III-V group compound semiconductor device comprising a gallium nitride-based semiconductor layer and an ohmic electrode layer formed on the gallium nitride-based... Agent: Marger Johnson & Mccollom, P.C.

20080230907 - Integrated circuit system with carbon enhancement: An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; forming a via opening through the low-K dielectric layer to the interconnect layer; and forming a... Agent: Law Offices Of Mikio Ishimaru

20080230905 - Power semiconductor module, method for producing a power semiconductor module, and semiconductor chip: In a power semiconductor module, a copper-containing first soldering partner, a connection layer, and a copper-containing second soldering partner are arranged successively and fixedly connected with one another. The connection layer has a portion of intermetallic copper-tin phases of at least 90% by weight. For producing such a power semiconductor... Agent: Coats & Bennett/infineon Technologies

20080230908 - Semiconductor device: A semiconductor device includes: a pad that is formed on a semiconductor layer, contains Al, and has an interconnection portion that is formed outside a bonding area; an interconnection layer that contains Au and is electrically connected to the interconnection portion of the pad, an edge of the interconnection layer... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080230910 - Integrated circuit and method for producing the same: An integrated circuit provides a carrier substrate, a wiring level above a carrier substrate, wherein the wiring level comprises a first conductor track composed of a first conductive material and a second conductor track composed of the first conductive material, an insulating layer above the wiring level, wherein the insulating... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080230909 - Method for forming anti-stiction bumps on a micro-electro mechanical structure: A technique for forming anti-stiction bumps on a bottom surface of a micro-electro mechanical (MEM) structure includes a number of process steps. The MEM structure is fabricated from an assembly that includes a support substrate bonded to a single-crystal semiconductor layer, via an insulator layer. A plurality of holes are... Agent: Delphi Technologies, Inc.

20080230911 - Method of forming a silicide layer on a thinned silicon wafer, and related semiconducting structure: A semiconducting structure includes a thinned silicon substrate (110), a silicide layer (120) over the thinned silicon substrate, a metal layer (130) over the silicide layer, a solder interface layer (140) over the metal layer, and a cap layer (150) over the solder interface layer. The thinned silicon substrate is... Agent: Intel Corporation C/o Intellevate, LLC

20080230912 - Wafer-level stack package and method of fabricating the same: A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal... Agent: Marger Johnson & Mccollom, P.C.

20080230914 - Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board: A transition layer 38 is provided on a die pad 22 of an IC chip 20 and integrated into a multilayer printed circuit board 10. Due to this, it is possible to electrically connect the IC chip 20 to the multilayer printed circuit board 10 without using lead members and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080230913 - Stackable semiconductor device and fabrication method thereof: The invention provides a stackable semiconductor device and a fabrication method thereof, including providing a wafer having a plurality of dies mounted thereon, both the die and the wafer having an active surface and a non-active surface opposing one another respectively, wherein each die has a plurality of solder pads... Agent: Edwards Angell Palmer & Dodge LLP

20080230915 - Semiconductor package using wires consisting of ag or ag alloy: A semiconductor package using Ag or Ag alloy wire which can maintain superior reliability against a noble metal and lower its manufacturing cost is provided. The semiconductor package comprises a semiconductor substrate. A semiconductor chip is attached to the package substrate and has one or more pads which comprise a... Agent: Volpe And Koenig, P.C.

20080230916 - Semiconductor integrated circuit device and fabrication process thereof: A semiconductor IC device includes a buried interconnection in interconnection layers over a semiconductor substrate, in which electrical connection of interconnections are provided over and under an interconnection layer of an embedded interconnection from among the interconnection layers such that a first connecting conductor portion within a connecting hole extending... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080230917 - method of fabricating two-step self-aligned contact: A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region therein. Next, a lower hole corresponding to the contact region is formed in the first dielectric layer. Thereafter, a second dielectric layer is formed on the first dielectric... Agent: J C Patents, Inc.

20080230919 - Dual damascene with via liner: A dual damascene structure with improved profiles and reduced defects and method of forming the same, the method including forming a first dielectric over a conductive area; forming a first dielectric insulator over the first dielectric; forming a first opening in the first dielectric insulator; lining the opening with a... Agent: Tung & Associates

20080230918 - Semiconductor integrated circuit and design method of signal terminals on input/output cell: A semiconductor integrated circuit, including an input/output cell including signal terminals, wherein the signal terminal of the input/output cell is connected to an internal circuit via an interconnect wiring. The signal terminal of the I/O cell includes a plurality of (e.g., four) conductive layers. Each pair of adjacent ones of... Agent: Mcdermott Will & Emery LLP

20080230923 - Chip stack package and method of manufacturing the chip stack package: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode... Agent: Marger Johnson & Mccollom, P.C.

20080230922 - Semiconductor device and its manufacturing method: A technique for mounting a plurality of electronic parts on one surface of a wiring substrate is provided. A semiconductor device comprises a wiring substrate having connection pads disposed outside a parts mount; a plurality of electronic parts with the first surface having a plurality of electrodes and the second... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080230921 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a first semiconductor chip; a multilayer wiring which is formed on the first semiconductor chip and which is connected to the first semiconductor chip; a second semiconductor chip connected to the first semiconductor chip by way of the multilayer wiring; a sealing material which seals the... Agent: Drinker Biddle & Reath (dc)

20080230920 - Wire-bonded semiconductor component with reinforced inner connection metallization: A semiconductor component comprising a semiconductor chip (2) made of a doped silicon substrate, which chip is doped into a semiconductor device and structured, and comprises an inner connection metallization (7) in a contact window, and said inner connection metallization of said semiconductor chip is connected to the respective outer... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080230924 - Semiconductor device, semiconductor package for use therein, and manufacturing method thereof: A semiconductor package includes a substrate for mounting and fixing a semiconductor chip thereon and a connecting pattern. The substrate is provided with an elongate opening formed therein. The semiconductor chip is fixed with its surface being mounted on the substrate and with its electrode being aligned within the elongate... Agent: Volentine & Whitt PLLC

20080230925 - Solder-bumping structures produced by a solder bumping method: A method for solder bumping provides a substrate and forms a film on the substrate. The film has openings therethrough. A stencil is aligned on the film. The stencil has openings therethrough over the openings through the film. Solder paste is printed onto the substrate and into the openings through... Agent: Law Offices Of Mikio Ishimaru

20080230926 - Surface treatments for contact pads used in semiconductor chip packagages and methods of providing such surface treatments: An inorganic solder mask (48) for use as a surface treatment in masking a connection conductor (32) of a semi-conductor chip package (10) against solder wetting when mounting the chip package (10) to a printed wiring board (50) or other substrate. The connection conductor (32) is partially covered by a... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080230927 - Fully tested wafers having bond pads undamaged by probing and applications thereof: Methods and apparatus for producing fully tested unsingulated integrated circuits without probe scrub damage to bond pads includes forming a wafer/wafer translator pair removably attached to each other wherein the wafer translator includes contact structures formed from a soft crushable electrically conductive material and these contact structures are brought into... Agent: Raymond J. Werner

20080230928 - Module comprising a semiconductor chip: A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the... Agent: Slater & Matsil LLP

20080230929 - Overlay mark of semiconductor device and semiconductor device including the overlay mark: Provided are an overlay mark of a semiconductor device and a semiconductor device including the overlay mark. The overlay mark includes: reference marks formed in rectangular shapes comprising sides in which fine patterns are formed; and comparison marks formed as rectangular shapes which are smaller than the rectangular shapes of... Agent: Myers Bigel Sibley & Sajovec

20080224115 - Fabricating a set of semiconducting nanowires, and electric device comprising a set of nanowires: The method of fabricating a set of semiconducting nanowires (10) having a desired wire diameter (d) comprises the steps of providing a set of pre-fabricated semiconducting nanowires (10′), at least one pre-fabricated semiconducting nanowire having a wire diameter (d′) larger than the desired wire diameter (d), and reducing the wire... Agent: Philips Intellectual Property & Standards

20080224116 - Forming an intermediate electrode between an ovonic threshold switch and a chalcogenide memory element: An intermediate electrode between an ovonic threshold switch and a memory element may be formed in the same pore with the memory element. This may have many advantages including, in some embodiments, reducing leakage.... Agent: Trop Pruner & Hu, PC

20080224118 - Heat-shielded low power pcm-based reprogrammable efuse device: An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and... Agent: Cantor Colburn LLP-ibm Yorktown

20080224119 - Phase change memory element and method of making the same: Thin-film phase-change memories having small phase-change switching volume formed by overlapping thin films. Exemplary embodiments include a phase-change memory element, including a first phase change layer having a resistance, a second phase change layer having a resistance, an insulating layer disposed between the first and second phase change layers; and... Agent: Cantor Colburn, LLP - IBM Arc Division

20080224117 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device includes a first resistance change element having a first portion and a second portion, the first portion and the second portion having a first space in a first direction, and a second resistance change element formed to have a distance to the first resistance change element... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080224120 - Phase change device with offset contact: A programmable resistance memory combines multiple cells into a block that includes one or more shared electrodes. The shared electrode configuration provides additional thermal isolation for the active region of each memory cell, thereby reducing the current required to program each memory cell.... Agent: Ovonyx, Inc

20080224121 - Spontaneous emission of telecommunication wavelength emitters coupled to at least one resonant cavity: Systems and methods for devices that include a structure having at least one resonant cavity and at least one emitter having an emission frequency that is substantially in the telecommunication wavelengths are provided. The emission frequency can be coupled to the resonant frequency of resonant cavity so that emitted wavelengths... Agent: Wilmerhale/columbia University

20080224122 - Semiconductor nanowire and semiconductor device including the nanowire: A nanowire (100) according to the present invention includes a plurality of contact regions (10a, 10b) and at least one channel region (12), which is connected to the contact regions (10a, 10b). The channel region (12) is made of a first semiconductor material and the surface of the channel region... Agent: Mcdermott Will & Emery LLP

20080224123 - Methods for nanowire alignment and deposition: The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080224124 - Transistor on the basis of new quantum interference effect: A quantum interference transistor comprising a thin metal film having a protrusion and a thin insulating layer between the metal film and protrusion. A potential barrier is formed in the region beneath the protrusion as a result of quantum interference caused by the geometry of the film and protrusion. A... Agent: Borealis Technical Limited

20080224131 - Compound, a molecular switch employing the compound and a method of electronic switching: Classes of molecules are disclosed which can, for example, be used in molecular switches. The classes of molecules include at least three segments—an electronic donor (“D”), a switchable bridge (“B”), and an electronic acceptor (“A”)—chemically connected and linearly arranged (e.g., D-B-A). The electronic donor can be an aromatic ring system... Agent: Buchanan, Ingersoll & Rooney PC

20080224129 - Flat panel display device and method of manufacturing the same: A flat panel display device, more particularly, an Organic Light Emitting Diode (OLED) display device having uniform electrical characteristics and a method of fabricating the same include: a thin film transistor of which a semiconductor layer including a source, a drain, and a channel region formed in a super grain... Agent: Stein, Mcewen & Bui, LLP

20080224127 - Gate dielectric structures, organic semiconductors, thin film transistors and related methods: Gate dielectric structures comprising an organic polymeric component, and organic semiconductor components, as can be used to fabricate thin film transistor devices.... Agent: Reinhart Boerner Van Deuren S.c. Attn: Linda Kasulke, Docket Coordinator

20080224130 - Organic semiconductor copolymers containing oligothiophene and n-type heteroaromatic units: An exemplary organic semiconductor copolymer includes a polymeric repeat structure having a polythiophene structure and an electron accepting unit. The electron accepting unit has at least one electron-accepting heteroaromatic structure with at least one electron-withdrawing imine nitrogen in the heteroaromatic structure or a thiophene-arylene comprising a C2-30 heteroaromatic structure. Methods... Agent: Buchanan, Ingersoll & Rooney PC

20080224125 - Semiconductor device: The disclosed is a semiconductor device which comprises a circuit which is formed on a substrate and which includes an insulated gate type semiconductor field-effect transistor element or an TFT element, wherein as compared with the electrostatic capacitance per a unit area of a gate insulating film at a channel... Agent: Sughrue Mion, PLLC

20080224126 - Spin-coatable liquid for formation of high purity nanotube films: Certain spin-coatable liquids and application techniques are described, which can be used to form nanotube films or fabrics of controlled properties. A spin-coatable liquid for formation of a nanotube film includes a liquid medium containing a controlled concentration of purified nanotubes, wherein the controlled concentration is sufficient to form a... Agent: Wilmerhale/new York

20080224132 - Stacked organic photosensitive devices: A device is provided having a first electrode, a second electrode, a first photoactive region having a characteristic absorption wavelength λ1 and a second photoactive region having a characteristic absorption wavelength λ2. The photoactive regions are disposed between the first and second electrodes, and further positioned on the same side... Agent: Kenyon & Kenyon LLP

20080224128 - Thin film transistor for display device and manufacturing method of the same: Provided are a thin film transistor for display devices and a manufacturing method of the thin film transistor. The thin film transistor for display devices includes: a flexible substrate; a gate electrode layer formed on the flexible substrate; a first insulating layer formed on the flexible substrate and the gate... Agent: Harness, Dickey & Pierce, P.L.C

20080224133 - Thin film transistor and organic light-emitting display device having the thin film transistor: Disclosed is a thin film transistor including a P-type semiconductor layer, and an organic light-emitting display device having the thin film transistor. The present invention provides a thin film transistor including a substrate, a semiconductor layer, and a gate electrode and a source/drain electrode formed on the substrate, wherein the... Agent: Robert E. Bushnell

20080224135 - Method and structure for determining thermal cycle reliability: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure... Agent: Keusey, Tutunjian & Bitetto, P.C.

20080224134 - Test structures for identifying an allowable process margin for integrated circuits and related methods: A test structure for inspecting an allowable process margin in a manufacturing process for a semiconductor device is provided. The test structure includes a plurality of grounded conductive lines on a substrate and electrically grounded to the substrate. A plurality of floating conductive lines are provided, each of the plurality... Agent: Myers Bigel Sibley & Sajovec

20080224136 - Image sensor and fabrication method thereof: An image sensor contains a semiconductor substrate, a plurality of pixels defined on the semiconductor substrate, a photo conductive layer and a transparent conductive layer formed on the pixel electrodes of the pixels in order, and a shield device positioned between any two adjacent pixel electrodes. The shield device has... Agent: North America Intellectual Property Corporation

20080224137 - Image sensor and method for manufacturing the same: An image sensor and a method of manufacturing the same are provided. A metal wiring layer is formed on a semiconductor substrate including a circuit region, and first conductive layers are formed on the metal layer separated by a pixel isolation layer. An intrinsic layer is formed on the first... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080224138 - Image sensor and method of manufacturing the same: Disclosed is an image sensor, which includes a substrate having a transistor circuit and lower interconnections. First interconnections are formed separated from each other on the substrate and electrically connected to the CMOS circuitry through the lower interconnections. Planarized insulating layers are formed between the first interconnections to isolate unit... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080224140 - Semiconductor device and manufacturing method thereof: It is an object of the present invention to provide a semiconductor device mounted with a memory which can be driven in the ranges of a current value and a voltage value which can be generated from a wireless signal. It is another object to provide a write-once read-many memory... Agent: Eric Robinson

20080224139 - Thin film transistor: A thin film transistor including a substrate, a gate, a gate insulator layer, a semiconductor layer, an ohmic contact layer, a source and a drain is provided. The gate is disposed on the substrate while the gate insulator layer is disposed on the substrate and covers the gate. The semiconductor... Agent: Jianq Chyun Intellectual Property Office

20080224144 - Fabrication method of pixel structure and thin film transistor: A method of fabricating a thin film transistor is disclosed. First, a substrate is provided and a patterned polysilicon layer is formed on the substrate. A metal layer is formed on the patterned polysilicon layer. Then, a portion of the metal layer is removed so that the remaining metal layer... Agent: J C Patents, Inc.

20080224141 - Liquid crystal display and fabrication method thereof: A method for fabricating an LCD includes: providing a substrate with a thin film transistor (ITT) part defined thereon; forming a metallic film for a gate electrode on the substrate; etching the metallic film through a first printing process to form a gate electrode; sequentially forming a gate insulating layer,... Agent: Brinks Hofer Gilson & Lione

20080224142 - Semiconductor structure of liquid crystal display and manufacturing method thereof: A semiconductor structure of a liquid crystal display and the manufacturing method thereof are described. The manufacturing method includes the following steps. A patterned polysilicon layer and a first dielectric layer are formed on a substrate. A first patterned metal layer is formed to construct a gate electrode and a... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080224143 - Thin film transistor, organic light emitting diode display device having the same, flat panel display device, and semiconductor device, and methods of fabricating the same: A thin film transistor and a method of fabricating the same include: a semiconductor layer having a grain boundary disposed in a crystal growth direction and having a variation in height of a top surface of 15 nm or less formed by a thin beam directional crystallization method. Also, an... Agent: Stein, Mcewen & Bui, LLP

20080224145 - Semiconductor device formed on (111) surface of a si crystal and fabrication process thereof: A semiconductor device includes a Si crystal having a crystal surface in the vicinity of a (111) surface, and an insulation film formed on said crystal surface, at least a part of said insulation film comprising a Si oxide film containing Kr or a Si nitride film containing Ar or... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20080224146 - Semiconductor apparatus, solid state image pickup device using the same, and method of manufacturing them: The invention provides a semiconductor apparatus provided with at least one set of buried channel type first conductive type MOS transistor and surface channel type first conductive type MOS transistor on the same substrate, in which a first conductive type impurity region is provided below a gate electrode of the... Agent: Fitzpatrick Cella Harper & Scinto

20080224147 - Thin film transistor, display device using thereof and method of manufacturing the thin film transistor and the display device: A thin film transistor includes a gate electrode, a gate insulating film formed to cover the gate electrode, a semiconductor layer including a channel region formed over the gate electrode, a source electrode and a drain electrode including a region connected to the semiconductor layer, where at least a part... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080224148 - Semiconductor sensing device: A semiconductor sensing device in which a sensing layer is exposed to a medium being tested in an area below and/or adjacent to a contact. In one embodiment, the device comprises a field effect transistor in which the sensing layer is disposed below a gate contact. The sensing layer is... Agent: Hoffman Warnick LLC

20080224150 - Silicon carbide semiconductor device: The SiC semiconductor device includes a substrate of a first conduction type made of silicon carbide, a drift layer of the first conduction type made of silicon carbide, the drift layer being less doped than the substrate, a cell portion constituted by a part of the substrate and a part... Agent: Posz Law Group, PLC

20080224149 - Silicon carbide semiconductor device and manufacturing method thereof: The present invention provides a silicon carbide semiconductor device comprising a semiconductor substrate comprising silicon carbide, which contains a first conductivity type impurity diffused therein in a high concentration, a semiconductor layer formed over the semiconductor substrate and containing the first conductivity type impurity diffused therein in a low concentration,... Agent: Volentine & Whitt PLLC

20080224151 - Silicon carbide semiconductor device: A nitride-based semiconductor element having superior mass productivity and excellent element characteristics is obtained. This nitride-based semiconductor element comprises a substrate comprising a surface having projection portions, a mask layer formed to be in contact with only the projection portions of the surface of the substrate, a first nitride-based semiconductor... Agent: Mcdermott Will & Emery LLP

20080224153 - Electronic device, method of producing the same, light-emitting diode display unit, and method of producing the same: An electronic device includes a base having a first wiring thereon; a flexible film having a second wiring thereon; a plurality of elements each including a first connecting portion and a second connecting portion; and an adhesive agent layer, wherein each of the elements is sandwiched between the base and... Agent: Bell, Boyd & Lloyd, LLP

20080224152 - Flat panel display having a control frame pedestal and method of making same: A method for providing a flat panel display comprising the steps of: providing an anode assembly containing a plurality of pixels; applying a photoresist to a surface of the anode assembly; applying a mask that defines a control frame top surface; exposing the mask to UV radiation and causing the... Agent: HowardIPLaw Group

20080224154 - Semiconductor light-emitting device with metal support substrate: One embodiment of the present invention provides a semiconductor light-emitting device which includes a multi-layer structure. The multilayer structure comprises a first doped layer, an active layer, and a second doped layer. The semiconductor light-emitting device further includes a first Ohmic-contact layer configured to form a conductive path to the... Agent: Park, Vaughan & Fleming LLP

20080224155 - Light-emitting diode unit: An LED unit including a frame (17) and a plurality of LED elements (11, 12, 13) which emit three primary colors of light and are sealed in the frame (17), readable characteristic data such as drive conditions, characteristics of each of the plurality of LED elements (11, 12, 13) being... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080224157 - Graded dielectric layer: An optoelectronic device includes a passivation layer of a dielectric material having a graded composition that varies with depth, whether continuous or stepwise, to provide a first index of refraction proximate to a semiconductor or conductor material and provide a second index of refraction adjacent to a surrounding material, such... Agent: Intellectual Property / Technology Law

20080224160 - High-power light emitting diode and method of manufacturing the same: Provided is a method of manufacturing a high-power LED package, the method including the steps of: preparing a mold having an irregularity pattern; providing a transparent resin solid having an irregularity pattern provided on the surface thereof by using the mold; preparing an irregularity film with the irregularity pattern by... Agent: Mcdermott Will & Emery LLP

20080224163 - Light emitting device: A light emitting device can be characterized as including a light emitting diode configured to emit light and a phosphor configured to change a wavelength of the light. The phosphor substantially covers at least a portion of the light emitting diode. The phosphor includes a compound having a host material.... Agent: Marger Johnson & Mccollom, P.C.

20080224164 - Light emitting device with a nanocrystalline silicon embedded insulator film: A light emitting device using a silicon (Si) nanocrystalline Si insulating film is presented with an associated fabrication method. The method provides a doped semiconductor or metal bottom electrode. Using a high density plasma-enhanced chemical vapor deposition (HDPECVD) process, a Si insulator film is deposited overlying the semiconductor electrode, having... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080224158 - Light emitting device with undoped substrate and doped bonding layer: A light emitting device having a stack of layers bonded to an undoped substrate with a doped layer between the stack of layers and the undoped substrate. The stack of layers include a layer of first conductivity type over the doped layer, an overlying light emitting layer and a layer... Agent: Patent Law Group LLP

20080224162 - Light emitting diode package: A light emitting diode (LED) package including: an LED chip; a first lead frame having a heat transfer unit with a top where a groove for stably mounting the LED chip is formed; a second lead frame disposed separately from the first lead frame; a package body having a concave... Agent: Mcdermott Will & Emery LLP

20080224156 - Luminescent diode provided with a reflection- reducing layer sequence: A luminescence diode (1) having an active zone (7) which emits electromagnetic radiation in a main radiating direction (15). A reflection-reducing layer sequence (16) is arranged downstream of the active zone (7) in the main radiating direction (15). The reflection-reducing layer sequence includes a DBR mirror (13), which is formed... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20080224159 - Optical element, optoelectronic component comprising said element, and the production thereof: The invention relates to an optical element (1, 25) having a defined shape and comprising a thermoplastic material that has been further cross-linked during or following the shaping thereof. Such thermoplastic materials have an increased heat deflection temperature, distortion, but can be easily and economically shaped before the additional cross-linking... Agent: Nexsen Pruet, LLC

20080224161 - Semiconductor light emitting device and multiple lead frame for semiconductor light emitting device: A semiconductor light emitting device that is excellent in radiating heat and that can be molded into a sealing shape having intended optical characteristics by die molding is provided. The semiconductor light emitting device includes: a lead frame including a plate-like semiconductor light emitting element mounting portion having an LED... Agent: Nixon & Vanderhye, PC

20080224168 - Intride-based semiconductor light emitting diode and method of manufacturing the same: A nitride-based semiconductor LED includes a substrate; an n-type nitride semiconductor layer formed on the substrate; an active layer and a p-type nitride semiconductor layer that are sequentially formed on a predetermined region of the n-type nitride semiconductor layer; a transparent electrode formed on the p-type nitride semiconductor layer; a... Agent: Mcdermott Will & Emery LLP

20080224166 - Led interconnect spring clip assembly: An LED interconnect spring clip assembly includes a housing having a center cavity and a plurality of contact features. Each contact feature has a portion retained by the housing and another portion that is operable to contact a terminal of an LED package disposed within the center cavity of the... Agent: Visteon/brinks Hofer Gilson & Lione

20080224167 - Semiconductor device and optical apparatus: A semiconductor device includes a substrate, a semiconductor layer formed on the substrate, and an optically functional portion formed by using at least a portion of the semiconductor layer. The optically functional portion performs light emission or light reception. The semiconductor device further includes a first driving electrode that is... Agent: Fildes & Outland, P.C.

20080224169 - Submount for diode with single bottom electrode: A submount is used to mount a diode between two metal areas on the upper surface of a substrate. One of the areas is connected to a metal plate at the lower surface of the substrate through a via. The submount is clamped between two metal sheets. The top metal... Agent: Hung Chang Lin

20080224165 - Top-emitting light emitting diodes and methods of manufacturing thereof: Provided are a top-emitting nitride-based light emitting device having an n-type clad layer, an active layer and a p-type clad layer sequentially stacked thereon, comprising an interface modification layer formed on the p-type clad layer and a transparent conductive thin film layer made up of a transparent conductive material formed... Agent: Harness, Dickey & Pierce, P.L.C

20080224170 - Semiconductor wafer, light emitting diode print head, image forming apparatus, and method of producing semiconductor device: A nitride semiconductor wafer includes a substrate; a nitride compound semiconductor layer formed on the substrate; and an AlxGa1-xAs layer (x≧0.6) formed between the substrate and the nitride semiconductor layer. The nitride compound semiconductor layer is formed of a nitride compound in a group III to a group V.... Agent: Kubotera & Associates, LLC

20080224171 - Light emitting device with filtering layer: A light emitting device including, between an input mirror and an output mirror forming a cavity, the output mirror having a reflectivity strip, a stack itself including an etch stop layer and an active layer. The stop layer is adapted to filter at least wavelengths lower than the lower limit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080224172 - Electrostatic discharge protection device and method of fabricating same: A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the... Agent: Schmeiser, Olsen & Watts

20080224173 - Fabrication transistors: A method for fabricating transistors such as high electron mobility transistors, each transistor comprising a plurality of epitaxial layers on a common substrate, method comprising: (a) forming a plurality of source contacts on a first surface of the plurality of epitaxial layers; (b) forming at least one drain contact on... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080224174 - Semiconductor device and manufacturing method of the same: A technology which allows an improvement in the moisture resistance of a semiconductor device is provided. In a GaAs substrate as a semi-insulating substrate, a HBT is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080224175 - Semiconductor device structures for bipolar junction transistors and methods of fabricating such structures: Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure includes a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080224176 - Semiconductor integrated circuit: A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended... Agent: Mcdermott Will & Emery LLP

20080224177 - Semiconductor integrated circuit device: Repeaters are arranged at arbitrary positions to substantially improve transmission speed of a signal. In the semiconductor integrated circuit device 1, repeater regions 10 where repeaters are provided as relay points for wiring are provided in the central parts of the core power source regions 2, 3 and 5, on... Agent: Miles & Stockbridge PC

20080224178 - Resistive memory and method: A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.... Agent: Schwegman, Lundberg & Woessner / Infineon

20080224179 - Ccd array with integrated high voltage protection circuit: A CCD containing circuit and method for making the same. The circuit includes a CCD array and a protection circuit. The CCD array is constructed on an integrated circuit substrate and includes a plurality of gate electrodes that are insulated from the substrate by an insulating layer. The gate electrodes... Agent: The Law Offices Of Calvin B. Ward Suite 305

20080224180 - Radiation detecting system: A radiation detecting system includes at least a carrier collective electrode layer, a radiation-sensitive semiconductor layer, at least one charge transfer layer, and a voltage applying electrode formed on an insulating substrate and wherein at least one of the charge transfer layers includes chalcogenide compounds containing therein chalcogenide elements larger... Agent: Sughrue Mion, PLLC

20080224181 - Back irradiating type solid state imaging device: A back irradiating type solid state imaging device comprises: a first semiconductor substrate; a plurality of photoelectric converting devices that receives a light incident from a back side of the first semiconductor substrate and are formed in a two-dimensional array on a surface side of the first semiconductor substrate; a... Agent: Birch Stewart Kolasch & Birch

20080224182 - Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates: The present invention discloses the use of edge-angle-optimized solid phase epitaxy for forming hybrid orientation substrates comprising changed-orientation Si device regions free of the trench-edge defects typically seen when trench-isolated regions of Si are recrystallized to the orientation of an underlying single-crystal Si template after an amorphization step. For the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080224183 - Method for manufacturing a compound semiconductor field effect transistor having a fin structure, and compound semiconductor field effect transistor having a fin structure: In another embodiment, the invention provides a compound semiconductor field effect transistor having a fin structure. A first layer is formed on or above a substrate, wherein the first layer contains a first compound semiconductor material. A second layer is formed on the first layer, wherein the second layer comprises... Agent: Slater & Matsil LLP

20080224185 - Semiconductor device having a metal carbide gate with an electropositive element and a method of making the same: A semiconductor device structure is formed over a semiconductor substrate and has a gate dielectric over the semiconductor substrate and a gate over the gate dielectric. The gate, at an interface with the gate dielectric, comprises a transition metal, carbon, and an electropositive element. The transition metal comprises one of... Agent: Freescale Semiconductor, Inc. Law Department

20080224184 - Transistor manufacture: A method of making a source-gated transistor is described, in which a gate (4) is provided on substrate (2) followed by gate insulator (6) and semiconductor layer (8). The layer is patterned to align the source with the gate (4) using photoresist (12) and back illumination through the substrate (2)... Agent: Philips Intellectual Property & Standards

20080224186 - High dynamic range imaging cell with electronic shutter extensions: A pixel sensor cell of improved dynamic range comprises a coupling transistor that couples a capacitor device to a photosensing region (e.g., photodiode) of the pixel cell, the photodiode being coupled to a transfer gate and one terminal of the coupling transistor. In operation, the additional capacitance is coupled to... Agent: Scully, Scott, Murphy & Presser, P.C.

20080224191 - Image pickup device with prevention of leakage current: An image pickup device includes an active pixel sensor (APS), a row driver, and a leakage current breaker. The active pixel sensor includes an array of a plurality of pixels. The row driver selects at least one pixel to be activated to output signals. The leakage current breaker decreases the... Agent: Law Office Of Monica H Choi

20080224188 - Image sensor and method for manufacturing the same: An apparatus that can effectively operate in high temperatures including a CMOS image sensor, a thermoelectric semiconductor formed under the CMOS image sensor for selectively cooling the image sensor and a heat sink formed under the thermoelectric semiconductor.... Agent: Sherr & Nourse, PLLC

20080224189 - Image sensor and method for manufacturing the same: An image sensor and a method for manufacturing an image sensor that has an increased aspect ratio. An image sensor and a method for manufacturing an image sensor that have a relatively large process margin (e.g. even in high level pixels), which may reduce and/or eliminate restrictions in downscaling an... Agent: Sherr & Nourse, PLLC

20080224190 - Image sensor and method of fabricating the same: An image sensor with sufficient photoelectric conversion capacity and enhanced reliability and a method of fabricating the same, in which the image sensor includes a bare substrate; an epitaxial layer disposed on the bare substrate and including a first impurity distribution region of a first conductivity type, which is formed... Agent: F. Chau & Associates, LLC

20080224187 - Image sensor pixel and method of fabricating the same: A new structure of a photodiode of a pixel in CMOS image sensor and a method of fabricating the same are provided. The photodiode is fabricated by using one photo mask, so that the number of masks decreases and the fabrication processes are simplified. In addition, two conducting layers constituting... Agent: Cantor Colburn, LLP

20080224193 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and method for fabricating the same improve image characteristics by eliminating the thickness of a planarization layer. The CMOS image sensor includes a semiconductor substrate; a plurality of active devices, provided in a predetermined surface of the semiconductor substrate, for generating electrical charges according to an... Agent: Mckenna Long & Aldridge LLP

20080224192 - Packaging methods for imager devices: An imager device is disclosed which includes at least one photosensitive element positioned on a front surface of a substrate and a conductive structure extending at least partially through an opening defined in the substrate to conductively couple to an electrical contact or bond pad on the first surface. An... Agent: Dickstein Shapiro LLP

20080224194 - Semiconductor device and fabrication process thereof: A semiconductor device includes a semiconductor substrate formed with an active element, an oxidation resistant film formed over the semiconductor substrate so as to cover the active element, a ferroelectric capacitor formed over the oxidation resistance film, the ferroelectric capacitor having a construction of consecutively stacking a lower electrode, a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080224195 - Semiconductor device with ferro-electric capacitor: A semiconductor device has a ferro-electric capacitor with small leak current and less process deterioration even upon miniaturization. The semiconductor device includes: a semiconductor element formed in a semiconductor substrate; lamination of an interlayer insulating film and a lower insulating shielding film having a hydrogen/moisture shielding function, the lamination being... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080224196 - Semiconductor device and manufacturing process for the same: A semiconductor device includes a first inverter, a second inverter, and an inner wiring connecting the inverters, in which the inner wiring forms a capacitor element, and the capacitor element includes an interlayer insulation film having an aperture on a semiconductor substrate, a lower electrode covering a bottom wall and... Agent: Sughrue Mion, PLLC

20080224197 - Semiconductor device and method for manufacturing the same: It is disclosed a semiconductor device including a silicon substrate, provided with a plurality of cell active regions in a call region, an element isolation groove, formed in a portion, between any two of the plurality of cell active region, of the silicon substrate, a capacitor dielectric film, formed in... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080224198 - Apparatus for working and observing samples and method of working and observing cross sections: The apparatus for working and observing samples comprises a sample plate on which a sample is to be placed; a first ion beam lens barrel capable of irradiating a first ion beam over a whole predetermined irradiation range at one time; a mask that can be arranged between the sample... Agent: Brinks Hofer Gilson & Lione

20080224199 - Non-volatile memory module package capability of replacing: A non-volatile memory module package capability of replacing, it may connected to a solid memory module, which includes a control unit, a system interface, and a first connector, the control unit may obtains external signals by the system interface, and then transmitted to this non-volatile memory module by the control... Agent: Pro-techtor International Services

20080224200 - Method of fabricating nand-type flash eeprom without field oxide isolation: Methods are described for fabricating NAND-type EEPROMs without field oxide isolation. P+ implantations are employed to isolate adjacent memory cells.... Agent: Stout, Uxa, Buyan & Mullins LLP

20080224201 - Flash memory devices and methods of fabricating the same: Flash memory devices and methods of fabricating the same are disclosed. A disclosed method comprises doping at least one active region of a substrate, and forming an etching mask layer on the active region. The etching mask layer defines an opening exposing a portion of the active region. The disclosed... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080224202 - Non-volatile memory: A non-volatile memory includes a substrate, a number of isolation layers, a number of active layers, a number of floating gates, a number of control gates and a number of doped regions. The active layers are disposed in the substrate between the isolation layers, and the top surface of the... Agent: Jianq Chyun Intellectual Property Office

20080224203 - Semiconductor device having island region: A semiconductor device includes a semiconductor substrate which includes an active region defined by an isolation film, and a source region and a drain region defined in the active region and spaced apart from each other in the active region. The source region and the drain region each have a... Agent: F. Chau & Associates, LLC

20080224204 - Process for manufacturing a multi-drain electronic power device integrated in semiconductor substrate and corresponding device: A process manufactures a multi-drain power electronic device integrated on a semiconductor substrate of a first type of conductivity whereon a drain semiconductor layer is formed. The process includes: forming a first semiconductor epitaxial layer of the first type of conductivity of a first value of resistivity forming the drain... Agent: Seed Intellectual Property Law Group PLLC

20080224205 - Vertical thin-film transistor with enhanced gate oxide: A method is provided for forming a low-temperature vertical gate insulator in a vertical thin-film transistor (V-TFT) fabrication process. The method comprises: forming a gate, having vertical sidewalls and a top surface, overlying a substrate insulation layer; depositing a silicon oxide thin-film gate insulator overlying the gate; plasma oxidizing the... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080224206 - Metal oxide semiconductor field effect transistors (mosfets) including recessed channel regions and methods of fabricating the same: Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel... Agent: Myers Bigel Sibley & Sajovec

20080224207 - Insulated gate transistor: A charge storage layer of first conductive type is formed on the first principal surface of a semiconductor substrate. A base layer of second conductive type is formed on the charge storage layer. Each trench formed through the base layer and the charge storage layer is lined with an insulating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080224208 - Semiconductor device and method for fabricating the same: A semiconductor device includes a semiconductor substrate including an NMOS region and a PMOS region, a device isolation structure formed on the semiconductor substrate to define an active region, a recess channel structure formed in the active region, a gate insulating film disposed in the recess channel structure, and a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080224209 - Semiconductor device and method for fabricating the same: A semiconductor device includes a semiconductor substrate including an NMOS region and a PMOS region, active regions of the semiconductor substrate defined by a device isolation structure formed in the semiconductor substrate, the active regions including an NMOS active region defined in the NMOS region and a PMOS active region... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080224210 - Short channel lv, mv, and hv cmos devices: Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conductivity... Agent: Hiscock & Barclay, LLP

20080224211 - Monolithic mosfet and schottky diode device: A Schottky diode is integrated into a planar or trench topology MOSFET having parallel spaced source regions diffused into spaced base stripes. The diffusions forming the source and base stripes are interrupted to permit the drift region to extend to the top of the die and receive a Schottky barrier... Agent: Ostrolenk Faber Gerb & Soffen

20080224212 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device is provided. A first insulation layer and a second insulation layer are formed over the substrate having a gate. A spacer etching process is performed to form an etched first insulation layer and an etched second insulation layer. The etched first insulation layer... Agent: Townsend And Townsend And Crew, LLP

20080224213 - Process for making finfet device with body contact and buried oxide junction isolation: There is a FinFET device. The device has a silicon substrate, an oxide layer, and a polysilicone gate. The silicon substrate defines a planar body, a medial body, and a fin. The planar body, the medial body, and the fin are integrally connected. The medial body connects the planar body... Agent: Ohlandt, Greeley, Ruggiero & Perle, LLP

20080224214 - Semiconductor device and fabrication method: The present invention provides an SOI device which has high breakdown voltage, wide stable operation range, good thermal dissipation, and high effective conductance and good frequency characteristics, and a method for fabricating the device. In a semiconductor device, a BOX region is formed on a part of a surface layer... Agent: Rossi, Kimms & Mcdowell LLP.

20080224215 - Semiconductor thin film and its manufacturing method and semiconductor device and its manufacturing method: A semiconductor thin film is formed having a lateral growth region which is a collection of columnar or needle-like crystals extending generally parallel with a substrate. The semiconductor thin film is illuminated with laser light or strong light having equivalent energy. As a result, adjacent columnar or needle-like crystals are... Agent: Fish & Richardson P.C.

20080224216 - Strained hot (hybrid oreintation technology) mosfets: A strained HOT MOSFET. The MOSFET includes (a) a first semiconductor layer having a first crystallographic orientation; (b) a buried oxide layer on top of the first semiconductor layer; (c) a second semiconductor layer on top of the buried oxide layer, wherein the second semiconductor layer has a second crystallographic... Agent: Schmeiser, Olsen & Watts

20080224217 - Mugfet switch: An electronic circuit on a semiconductor substrate having isolated multiple field effect transistor circuit blocks is disclosed. In some embodiment, an apparatus includes a substrate, a first semiconductor circuit formed above the substrate, a second semiconductor circuit formed above the substrate, and a MuGFET device overlying the substrate and electrically... Agent: Schwegman, Lundberg & Woessner / Infineon

20080224218 - Cmos structure including differential channel stressing layer compositions: A CMOS structure includes an n-FET device comprising an n-FET channel region and a p-FET device comprising a p-FET channel region. The n-FET channel region includes a first silicon material layer located upon a silicon-germanium alloy material layer. The p-FET channel includes a second silicon material layer located upon a... Agent: Scully, Scott, Murphy & Presser, P.C.

20080224219 - Semiconductor device and method for manufacturing same: A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality... Agent: Harness, Dickey & Pierce, P.L.C

20080224220 - Electrostatic discharge protection device: The invention provides an electrostatic discharge (ESD) protection device with an increased capability to discharge ESD generated current with a reduced device area. The ESD protection device comprises a grounded gate MOS transistor (1) with a source region (3) and a drain region (4) of a first semiconductor type interposed... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080224221 - Cascode current mirror and method: A cascode amplifier (CA) (60) is described having a bottom transistor (T1new) with a relatively thin gate dielectric (67) and higher ratio (RB) of channel length (Lch1new) to width (W1new) and a series coupled top transistor (T2new) with a relatively thick gate dielectric (68) and a lower ratio (RT) of... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080224223 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a first gate electrode formed above a first active region in a substrate with a first gate insulating film interposed therebetween; and a second gate electrode formed above a second active region in the substrate with a second gate insulating film interposed therebetween. The first gate... Agent: Mcdermott Will & Emery LLP

20080224222 - Semiconductor device having a fin transistor and method for fabricating the same: A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and... Agent: Lowe Hauptman Ham & Berner, LLP

20080224224 - Tunnel field-effect transistor with gated tunnel barrier: A tunnel field effect transistor (TFET) is disclosed. In one aspect, the transistor comprises a gate that does not align with a drain, and only overlap with the source extending at least up to the interface of the source-channel region and optionally overlaps with part of the channel. Due to... Agent: Knobbe Martens Olson & Bear LLP

20080224225 - Mos transistors with selectively strained channels: The channels of first and second CMOS transistors can be selectively stressed. A gate structure of the first transistor includes a stressor that produces stress in the channel of the first transistor. A gate structure of the second transistor is disposed in contact with a layer of material that produces... Agent: Slater & Matsil, L.L.P.

20080224226 - Semiconductor device: A semiconductor device includes a semiconductor substrate, p-type first and n-type second semiconductor regions formed on the substrate so as to be insulated with each other, n-channel and p-channel MOS transistors formed on the first and second semiconductor regions, the n-channel transistor including a first pair of source/drain regions formed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080224227 - Bicmos performance enhancement by mechanical uniaxial strain and methods of manufacture: A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the... Agent: Slater & Matsil, L.L.P.

20080224228 - Capacitor top plate over source/drain to form a 1t memory device: A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed... Agent: HorizonIPPte Ltd

20080224229 - Semiconductor device and manufacturing method thereof: An object is to provide an antifuse with little power consumption at the time of writing. The antifuse is used for a memory element in a read-only memory device. The antifuse includes a first conductive layer, a multilayer film of two or more layers in which an amorphous silicon film... Agent: Eric Robinson

20080224230 - Mosfet device having screening layers formed between main gate and passing gate and method for manufacturing the same: A MOSFET device includes a semiconductor substrate having an active region including storage node contact forming areas and a device isolation region and having a device isolation structure which is formed in the device isolation region to delimit the active region; screening layers formed in portions of the device isolation... Agent: Ladas & Parry LLP

20080224231 - Transistors having v-shape source/drain metal contacts: A semiconductor structure. The semiconductor structure includes (a) a semiconductor layer, (b) a gate dielectric region, and (c) a gate electrode region. The gate electrode region is electrically insulated from the semiconductor layer. The semiconductor layer comprises a channel region, a first and a second source/drain regions. The channel region... Agent: Schmeiser, Olsen & Watts

20080224232 - Silicidation process for mos transistor and transistor structure: A silicidation process for a MOS transistor and a resulting transistor structure are described. The MOS transistor includes a silicon substrate, a gate dielectric layer, a silicon gate, a cap layer on the silicon gate, a spacer on the sidewalls of the silicon gate and the cap layer, and S/D... Agent: J C Patents, Inc.

20080224233 - Igfet device having a rf capability: An IGFET device includes: —a semiconductor body (2) having a major surface, —a source region (3) of first conductivity type abutting the surface, —a drain region (6,7) of the first conductivity-type abutting the surface and spaced from the source region with a channel (5) therefrom, —an active gate (8) overlying... Agent: Young & Thompson

20080224234 - Method for manufacturing semiconductor device and semiconductor device: A method for manufacturing a semiconductor device includes: forming a groove in a semiconductor substrate and embedding an element isolation film made of a silicon oxide film in the groove; forming a silicon nitride film on the element isolation film; forming an oxidized silicon nitride film on the surface of... Agent: Oliff & Berridge, PLC

20080224236 - Metal gate electrode for semiconductor devices: A gate electrode for semiconductor devices, the gate electrode comprising a mixture of a metal having a work function of about 4 eV or less and a metal nitride.... Agent: Dinsmore & Shohl LLP

20080224235 - Selectively depositing aluminium in a replacement metal gate process: A method for carrying out a replacement metal gate process comprises providing a transistor in a reactor, wherein the transistor includes a gate stack, removing at least a portion of the gate stack to expose a surface of a barrier layer, causing a temperature of the reactor be less than... Agent: Intel Corporation C/o Intellevate, LLC

20080224237 - Semiconductor devices: An embodiment of a semiconductor device includes a gate electrode overlying a substrate and a lightly doped epitaxial layer formed on the substrate. A high energy implant region forms a well in a source side of the lightly doped epitaxial layer. A self-aligned halo implant region is formed on a... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080224238 - Advanced high-k gate stack patterning and structure containing a patterned high-k gate stack: An advanced method of patterning a gate stack including a high-k gate dielectric that is capped with a high-k gate dielectric capping layer such as, for example, a rare earth metal (or rare earth like)-containing layer is provided. In particular, the present invention provides a method in which a combination... Agent: Scully, Scott, Murphy & Presser, P.C.

20080224240 - Atomic layer deposition of zrx hfy sn1-x-y o2 films as high k gate dielectrics: The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO2), hafnium oxide (HfO2) and tin oxide (SnO2) acting as a single dielectric layer with a formula of Zrx Hfy Sn1-x-y O2, and a method of fabricating such a dielectric layer is described that produces... Agent: Schwegman, Lundberg & Woessner/micron

20080224239 - Method for forming fully silicided gate electrode in a semiconductor device: A semiconductor MOS device includes a semiconductor substrate; a gate oxide layer disposed on the semiconductor substrate; a fully silicided gate electrode disposed on the gate oxide layer; a composite thin film interposed between the fully silicided gate electrode and the gate oxide layer; a spacer on sidewall of the... Agent: North America Intellectual Property Corporation

20080224241 - Electronic device, resonator, oscillator and method for manufacturing electronic device: An electronic device includes a substrate, a functional structural body formed on the substrate and a covering structure for defining a cavity part having the functional structural body disposed therein, wherein the covering structure is provided with a side wall provided on the substrate and comprising an interlayer insulating layer... Agent: Oliff & Berridge, PLC

20080224242 - Process for manufacturing a membrane of semiconductor material integrated in, and electrically insulated from, a substrate: A process for manufacturing an integrated membrane made of semiconductor material includes the step of forming, in a monolithic body of semiconductor material having a front face, a buried cavity, extending at a distance from the front face and delimiting with the front face a surface region of the monolithic... Agent: Seed Intellectual Property Law Group PLLC

20080224247 - Backside depletion for backside illuminated image sensors: A backside illuminated image sensor is provided which includes a substrate having a front side and a backside, a sensor formed in the substrate at the front side, the sensor including at least a photodiode, and a depletion region formed in the substrate at the backside, a depth of the... Agent: Haynes And Boone, LLP

20080224246 - Image sensor and method for fabricating the same: An image sensor is disclosed including a second semiconductor substrate including a metal interconnection and a second interlayer dielectric; a second via penetrating the second interlayer dielectric so that the second via is connected to the metal interconnection; a first semiconductor substrate on the second interlayer dielectric, the first semiconductor... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080224244 - Image sensor and method for manufacturing the same: An image sensor include an interlayer dielectric layer formed over a semiconductor substrate; a color filter array formed over the interlayer dielectric layer; a planarization layer formed over the color filter; and a microlens array having a continuous, gapless shape formed over the planarization layer and spatially corresponding to the... Agent: Sherr & Nourse, PLLC

20080224245 - Image sensor and method for manufacturing the same: An image sensor including an interlayer dielectric layer formed over a semiconductor substrate, a color filter layer formed over the interlayer dielectric layer, a planarization layer formed over the color filter, and a microlens array having a gapless, continuous shape and a multilayered structure formed over the planarization layer.... Agent: Sherr & Nourse, PLLC

20080224243 - Image sensor and method of manufacturing the same: An image sensor is provided. The image sensor can include a semiconductor substrate including a circuit region, an interlayer electric including a metal interconnection on the semiconductor substrate, a lower electrode on the metal interconnection, and a light receiving portion on the lower electrode. The light receiving portion can be... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080224248 - Image sensor module having build-in package cavity and the method of the same: The present invention provides an image sensor module having build-in package cavity and the Method of the same. An image sensor module structure comprising a substrate with a package receiving cavity formed within an upper surface of the substrate and conductive traces within the substrate, and a package having a... Agent: Abelman, Frayne & Schwab

20080224249 - Semiconductor device and method of manuafcturing the same: A semiconductor device includes a semiconductor substrate having first and second surfaces opposite each other, the first surface being an active surface by provided with an electronic element thereon, a pad electrode formed to be connected to the electronic element in a peripheral portion of the electronic element on the... Agent: Sonnenschein Nath & Rosenthal LLP

20080224250 - Image sensor and method of fabricating the same: Provided are an image sensor and a method of fabricating the same. The image sensor according to an embodiment includes a semiconductor substrate including a circuit region; a metal interconnection layer including a metal interconnection and an interlayer dielectric on the semiconductor substrate; a plurality of first pixel isolation layers... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080224251 - Optimal rasterization for maskless lithography: A lithographic system is provided in which an extent of overlap between pattern sections is adjusted in order to match a size of a pattern section to a size of a repeating portion of the pattern to be formed.... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080224252 - Semiconductor device having an element isolating insulating film: In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080224254 - Glass-based soi structures: Semiconductor-on-insulator (SOI) structures, including large area SOI structures, are provided which have one or more regions composed of a layer of a substantially single-crystal semiconductor (e.g., doped silicon) attached to a support substrate composed of an oxide glass or an oxide glass-ceramic. The oxide glass or oxide glass-ceramic is preferably... Agent: Corning Incorporated

20080224253 - Semiconductor device: A semiconductor device receiving as input a radio frequency signal having a frequency of 500 MHz or more and a power of 20 dBm or more is provided. The semiconductor device includes: a silicon substrate; a silicon oxide film formed on the silicon substrate; a radio frequency interconnect provided on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080224256 - Semiconductor-on-insulator(soi) structures including gradient nitrided buried oxide (box): A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor... Agent: Scully, Scott, Murphy & Presser, P.C.

20080224255 - Subground rule sti fill for hot structure: This invention provides a hybrid orientation (HOT) semiconductor-on-insulator (SOI) structure having an isolation region, e.g. a shallow trench isolation region (STI), and a method for forming the STI structure that is easy to control. The method of forming the isolation region includes an etch of the insulating material, selective to... Agent: International Business Machines Corporation Dept. 18g

20080224257 - Semiconductor device: A semiconductor device includes a silicon-on-insulator substrate having a supporting substrate, an electrically insulating layer on the supporting substrate, and a semiconductor layer on the insulating layer. The semiconductor layer includes element regions for providing semiconductor elements and an isolation region located around the element region and extending to the... Agent: Posz Law Group, PLC

20080224258 - Semiconductor structue with multiple fins having different channel region heights and method of forming the semiconductor structure: Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080224259 - Methods of fabricating passive element without planarizing and related semiconductor device: Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in... Agent: Hoffman Warnick LLC

20080224261 - Fuse/anti-fuse structure and methods of making and programming same: Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed... Agent: Ryan, Mason & Lewis, LLP

20080224260 - Programmable vias for structured asics: A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance... Agent: Connolly Bove Lodge & Hutz LLP

20080224262 - Semiconductor device: Provided is a semiconductor device having a high-frequency interconnect, first dummy conductor patterns, an interconnect, and second dummy conductor patterns. The first dummy conductor patterns are arranged in the vicinity of the high-frequency interconnect, and the second dummy conductor patterns are arranged in the vicinity of the interconnect. The minimum... Agent: Young & Thompson

20080224263 - Semiconductor device and method of manufacturing the same: A semiconductor device including a capacitor which includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode, the dielectric layer including: a first paraelectric film formed of a material containing a first metal element and at least one kind of... Agent: Mcginn Intellectual Property Law Group, PLLC

20080224264 - Capacitor and method for fabricating the same: A capacitor includes a lower electrode, a first dielectric layer formed over the lower electrode, a second dielectric layer formed over the first dielectric layer, wherein the second dielectric layer includes an amorphous high-k dielectric material, a third dielectric layer formed over the second dielectric layer, and an upper electrode... Agent: Townsend And Townsend And Crew, LLP

20080224265 - Semiconductor device and manufacturing method thereof: A first insulation film is provided on a semiconductor substrate. A high resistance element formed from polysilicon is provided on the first insulation film. A second insulation film is provided on the high resistance element. A hydrogen diffusion preventing film having a hydrogen diffusion coefficient smaller than that of the... Agent: Mcdermott Will & Emery LLP

20080224266 - Lateral bipolar transistor: A lateral bipolar transistor is described, including a semiconductor substrate, a gate structure on the substrate, an emitter and a collector of a first conductivity type in the substrate, and a base of a second conductivity type in the substrate. The gate structure has a structure enclosing one or more... Agent: Jianq Chyun Intellectual Property Office

20080224267 - Semiconductor devices including hydrogen implantation layers and methods of forming the same: Provided are semiconductor devices and methods of forming the same. The semiconductor devices include a substrate further including a hydrogen implantation layer and a gate structure formed on the hydrogen implantation layer to include a first insulating layer, a charge storage layer, a second insulating layer and a conductive layer.... Agent: Myers Bigel Sibley & Sajovec

20080224268 - Nitride semiconductor single crystal substrate: To provide a nitride semiconductor single crystal substrate comprising a Si substrate and a nitride semiconductor film which has semi-polar (10-1m) plane (m: natural number) and a thickness of 1 μm or more, the nitride semiconductor single crystal substrate being suitably used for a light-emitting device, the nitride semiconductor single... Agent: Foley And Lardner LLP Suite 500

20080224269 - Gettering structures and methods and their application: An embodiment of a semiconductor device includes a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a first semiconductor layer formed over the first insulation layer. At least one gettering region is formed in at least one of the first insulating layer and the first semiconductor... Agent: Harness, Dickey & Pierce, P.L.C

20080224270 - Silicon single crystal substrate and manufacture thereof: A semiconductor wafer for an epitaxial growth is disclosed comprising: a main face on which a vapor phase epitaxial layer grows; a back face provided on an opposite side of the wafer; a main chamfered part along a circumferential edge where the main face and a side face of the... Agent: Alston & Bird LLP

20080224271 - Semiconductor device and method of manufacturing same, wiring board and method of manufacturing same, semiconductor package, and electronic device: Passivation films 3a, 3b are formed to cover both surfaces of semiconductor substrate 1 which comprises terminal pads 2a, 2b on both surfaces. Openings 3c, 3d are provided at positions on passivation films 3a, 3b which match with terminal pads 2a, 2b. Throughholes 9 are formed inside of openings 3c,... Agent: Hayes Soloway P.C.

20080224272 - Active structure of a semiconductor device: An active structure of a semiconductor device. In one aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein one or more of the first to (n+1)th active regions are... Agent: Marshall, Gerstein & Borun LLP

20080224273 - Chemical oxide removal of plasma damaged sicoh low k dielectrics: A structure and method for removing damages of a dual damascene structure after plasma etching. The method includes the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure includes a dual damascene... Agent: Greenblum & Bernstein, P.L.C

20080224274 - Semiconductor device, semiconductor display device, and manufacturing method of semiconductor device: To achieve high performance of a semiconductor integrated circuit depending on not only a microfabrication technique but also another way. In addition, to achieve low power consumption of a semiconductor integrated circuit. A semiconductor device is provided in which crystal faces and/or crystal axes of single-crystalline semiconductor layers of a... Agent: Eric Robinson

20080224275 - Semiconductor device and method for manufacturing thereof: A semiconductor device includes bit lines provided in a semiconductor substrate; an ONO film that is provided along the surface of the semiconductor substrate and is made of a tunnel oxide film, a trap layer, and a top oxide film; and an oxide film that is provided on the surface... Agent: Ingrassia Fisher & Lorenz, P.C.

20080224276 - Semiconductor device package: The present invention provides a package structure and a method for forming the same; wherein the structure comprises a substrate with certain open through holes filled with conducting metals for performing electrical connection or heat dissipation, a chip with bonding pads attached on the contacting pad by an adhesive with... Agent: Abelman, Frayne & Schwab

20080224277 - Chip package and method of fabricating the same: A method of fabricating a chip package is provided. A thin metal plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts are provided. A chip is disposed on the thin metal plate, and a plurality of bonding wires for electrically connecting the... Agent: Jianq Chyun Intellectual Property Office

20080224278 - Circuit component and method of manufacture: An inductor, a semiconductor component including the inductor, and a method of manufacture. A leadframe has a plurality of conductive strips and a flag. A ferrite core is mounted on a die attach material disposed on the conductive strips and a semiconductor die is mounted on a die attach material... Agent: Mr. Jerry Chruma Semiconductor Components Industries, LLC

20080224280 - Lead frame, semiconductor device, and method of manufacturing the semiconductor device: To solve a problem in that a die processing cost increases when employing a method involving providing a suction hole in the die to fix an island onto a bottom surface, provided is a semiconductor device, which includes: a semiconductor chip, an island having a first surface, on which the... Agent: Young & Thompson

20080224281 - Semiconductor device and method of manufacturing same: A semiconductor device comprises: a semiconductor chip; a first frame; a solder layer which bonds the solder bonding metal layer of the semiconductor chip and the first frame; and a second frame bonded to the rear face of the semiconductor chip. The semiconductor chip includes: a semiconductor substrate; a first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080224279 - Vertical electrical interconnect formed on support prior to die mount: A die assembly includes a die mounted to a support, in which the support has interconnect pedestals formed at bond pads, and the die has interconnect terminals projecting beyond a die edge into corresponding pedestals. Also, a support has interconnect pedestals. Also, a method for electrically interconnecting a die to... Agent: Haynes Beffel & Wolfeld LLP

20080224282 - Semiconductor device and method of manufacturing the same: A technique for preventing cracks and residual resin on a semiconductor chip in a molding process in the assembly of semiconductor devices is provided. A distance from a bottom surface of a cavity of a lower mold die to a ceiling surface of a cavity of an upper mold die... Agent: Townsend And Townsend And Crew, LLP

20080224284 - Chip package structure: A chip package structure mainly including a substrate, a chip and a lead frame is provided. The chip is disposed on the substrate, and is electrically connected to the chip by flip-chip or wire-bonding technique. The chip is electrically connected to the lead frame through a redistribution layer on the... Agent: Jianq Chyun Intellectual Property Office

20080224283 - Leadframe-based semiconductor package and fabrication method thereof: A leadframe-based semiconductor package and a fabrication method thereof are provided. The leadframe-based semiconductor package includes a chip implanted with a plurality of first and second conductive bumps thereon, and a leadframe having a plurality of leads. The first conductive bumps are bonded to the leads to electrically connect the... Agent: Birch Stewart Kolasch & Birch

20080224285 - Power module having stacked flip-chip and method of fabricating the power module: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame;... Agent: Townsend And Townsend And Crew, LLP

20080224286 - Vertically mountable semiconductor device package: A semiconductor package that includes a die with electrodes on opposite surfaces thereof and respective conductive clip electrically and mechanically coupled to the electrode and configured for vertical mounting of the package.... Agent: Ostrolenk Faber Gerb & Soffen

20080224290 - Low cost lead-free preplated leadframe having improved adhesion and solderability: A leadframe with a structure made of a base metal (105), wherein the structure has a plurality of surfaces. On each of these surfaces are metal layers in a stack adherent to the base metal. The stack comprises a nickel layer (201) in contact with the base metal, a palladium... Agent: Texas Instruments Incorporated

20080224289 - Multi-chip stack structure and fabrication method thereof: A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a... Agent: Edwards Angell Palmer & Dodge LLP

20080224287 - Optoelectronic device alignment in an optoelectronic package: Using one or more reference indicators in die attaching an optoelectronic device to a lead during the assembly of an optoelectronic package. One example method of assembling an optoelectronic package includes detecting a reference indicator included in a first component of an optoelectronic package. The method also includes die attaching... Agent: Workman Nydegger

20080224288 - Portable object connectable package: A portable object connectable package 1, 11, 21, 31, 41, 51, 61, 71, 81 for an electronic device comprises: —a semiconductor die package 2, 12, 22, 32, 42, 52, 62, 72, 82 comprising a top surface 2A, 12A, 22A, 32A, 42A, 52A, 62A, 72A, 82A and an opposite bottom surface... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080224291 - Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components: Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and... Agent: Perkins Coie LLP Patent-sea

20080224292 - Interposer structure with embedded capacitor structure, and methods of making same: A device is disclosed which includes an interposer, at least one capacitor formed at least partially within an opening formed in the interposer and an integrated circuit that is operatively coupled to the interposer. A method is disclosed which includes obtaining an interposer having at least one capacitor formed at... Agent: Perkins Coie LLP Patent-sea

20080224293 - Method and apparatus for fabricating a plurality of semiconductor devices: A method includes the steps of providing a carrier comprising a plurality of cavities; placing at least one semiconductor element into each of the cavities; filling the plurality of cavities with a packaging material; and removing the carrier.... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20080224294 - Multi-chip package with a single die pad: A multi-chip package with a single die pad is provided. The multi-chip package includes a leadframe having a die pad and a plurality of leads surrounding the die pad. Each of the leads includes an upper lead, a lower lead and an intermediate lead substantially perpendicularly connected to the upper... Agent: Lowe Hauptman Ham & Berner, LLP

20080224295 - Package structure and stacked package module using the same: A package structure with chip embedded therein is disclosed, which comprises a circuit board having a first surface, an opposite second surface and a through cavity penetrating the circuit board, wherein the first surface of the circuit board has a plurality of first conductive pads and a plurality of wire... Agent: Bacon & Thomas, PLLC

20080224296 - Article and panel comprising semiconductor chips, casting mold and methods of producing the same: A panel with a reconfigured wafer including semiconductor chips arranged in rows and columns on semiconductor device positions includes: at least one semiconductor chip having a front, a rear and edge sides provided per semiconductor device position. The reconfigured wafer includes: a front side that forms a coplanar area with... Agent: Edell , Shapiro & Finnan , LLC

20080224297 - Apparatus comprising a device and method for producing it: An apparatus comprises a device layer structure, a device integrated into the device layer structure, an insulating carrier substrate and an insulating layer being continuously positioned between the device layer structure and the insulating carrier substrate, the insulating layer having a thickness which is less than 1/10 of a thickness... Agent: Maginot, Moore & Beck Chase Tower

20080224298 - Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components: Packaged semiconductor components, apparatus for packaging semiconductor devices, methods of packaging semiconductor devices, and methods of manufacturing apparatus for packaging semiconductor devices. One embodiment of an apparatus for packaging semiconductor devices comprises a first board having a front side, a backside, arrays of die contacts, arrays of first backside terminals... Agent: Perkins Coie LLP Patent-sea

20080224299 - Base substrate for chip scale packaging: A base substrate for chip scale package includes a carrier member made of electrical conductive metals with a first through opening; an active member laminated by a base layer made of electrical conductive metal and an intermediate layer made of electrical insulating or dielectric material, the active member having a... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080224300 - Semiconductor module with semiconductor chips and method for producing it: A semiconductor module has at least two semiconductor chips (4, 5) with at least one first and one second electrode (12, 13) on their first sides. Each semiconductor chip (4, 5) has a third electrode (14) on its second side (16). A chip arrangement within the semiconductor module (1) is... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20080224301 - Lead structure for a semiconductor component and method for producing the same: A lead structure for a semiconductor component includes: external leads for external connections outside a plastic housing composition, internal leads for electrical connections within the plastic housing composition, and a chip mounting island composed of the lead material. While leaving free contact pads of the internal leads, the top sides... Agent: Edell , Shapiro & Finnan , LLC

20080224303 - Power semiconductor module: A power semiconductor module with its thermal resistance and overall size reduced. Insulating substrates with electrode metal layers disposed thereon are joined to both the surfaces of a power semiconductor chip by using, for example, soldering. Metal layers are disposed also on the reverse surfaces of the insulating substrates and... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080224302 - Semiconductor module: A module includes a semiconductor chip and a conductive layer arranged over the semiconductor chip. The module also includes a spacer structure arranged to deflect the conductive layer away from the semiconductor chip.... Agent: Slater & Matsil LLP

20080224304 - Physical quantity sensor and semiconductor device having package and cover: A semiconductor device includes: a semiconductor chip; a package for accommodating the chip, wherein the package has a box shape with an opening and a bottom; and a cover for sealing the opening of the package. The semiconductor chip is disposed on the bottom of the package. The cover has... Agent: Harness, Dickey & Pierce, P.L.C

20080224305 - Method, apparatus, and system for phase change memory packaging: According to one embodiment, a die assembly is disclosed, comprising a package substrate and a plurality of stacked die on the package substrate, the plurality of stacked die including at least an uppermost die, a lowermost die, and at least one phase change memory die between the uppermost die and... Agent: Trop, Pruner & Hu, P.C.

20080224306 - Multi-chips package and method of forming the same: The present invention provides a structure of multi-chips package comprising: a substrate with a die receiving cavity formed within an upper surface of the substrate and a first through holes structure, wherein terminal pads are formed under the first through holes structure. A first die is disposed within the die... Agent: Birch Stewart Kolasch & Birch

20080224310 - Method for manufacturing semiconductor device and semiconductor device: A method for manufacturing a semiconductor device includes: preparing a wiring board having a base substrate and wiring that is plated on surface with a plating metal; pressing a bump that is formed on the active side of the semiconductor chip against an end part of the wiring of the... Agent: Oliff & Berridge, PLC

20080224311 - Semiconductor device: A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land... Agent: Sughrue Mion, PLLC

20080224309 - Semiconductor device mounted on substrate, and manufacturing method thereof: The semiconductor device mounted on the substrate, in which the substrate includes an electrode pad, the semiconductor device includes an electrode pad, the electrode pad of the semiconductor device and the electrode pad of the substrate are connected with a conductive adhesive, and a spacer is provided between the semiconductor... Agent: Dickstein Shapiro LLP

20080224307 - Semiconductor die with mask programmable interface selection: According to one exemplary embodiment, a semiconductor die with on-die preferred interface selection includes at least two groups of pads situated on an active surface of the semiconductor die, where each of the at least two groups of pads is coupled to its associated interface in the die. A set... Agent: Farjami & Farjami LLP

20080224308 - Semiconductor package and fabricating method thereof: Provided is a semiconductor device including a substrate, an electrode pad disposed on the substrate, an external terminal disposed on the electrode pad, a container extended from the electrode pad into the external terminal, and a conductive liquid disposed inside the container. The conductive liquid solidifies when exposed to air.... Agent: Marger Johnson & Mccollom, P.C.

20080224312 - Device having a bonding structure for two elements: A device and a method for bonding elements are described. A first solder ball is produced on a main surface of a first element. A second solder ball is produced on a main surface of a second element. Contact is provided between the first solder ball and the second solder... Agent: Knobbe Martens Olson & Bear LLP

20080224313 - Method for forming a seed layer for damascene copper wiring, and semiconductor wafer with damascene copper wiring formed using the method: A method for forming a seed layer for damascene copper wiring is provided. The method comprises the step of forming a seed layer, during damascene copper wiring formation, using an electroless plating solution comprising a water-soluble nitrogen-containing polymer and glyoxylic acid as a reducing agent, wherein the weight-average molecular weight... Agent: Flynn Thiel Boutell & Tanis, P.C.

20080224314 - Method and apparatus for forming a noble metal layer, notably on inlaid metal features: A cap layer for a metal feature such as a copper interconnect on a semiconductor wafer is formed by immersion plating a more noble metal (e.g. Pd) onto the copper interconnect and breaking up, preferably by mechanical abrasion, loose nodules of the noble metal that form on the copper interconnect... Agent: Freescale Semiconductor, Inc. Law Department

20080224315 - Semiconductor device and manufacturing method thereof: In a semiconductor device having a bonding wireless structure, a preform material is used for electrically connecting a metal plate serving as a connection with an electrode layer of a semiconductor chip. Thus, a multilayered metal layer needs to be provided in a junction part between the preform material and... Agent: Morrison & Foerster LLP

20080224316 - Electronic device and method for producing electronic devices:

20080224317 - Stable silicide films and methods for making the same: Highly thermally stable metal silicides and methods utilizing the metal silicides in semiconductor processing are provided. The metal silicides are preferably nickel silicides formed by the reaction of nickel with substitutionally carbon-doped single crystalline silicon which has about 2 atomic % or more substitutional carbon. Unexpectedly, the metal silicides are... Agent: Knobbe, Martens, Olson & Bear LLP

20080224319 - Micro electro-mechanical system and method of manufacturing the same: A micro electro-mechanical system, which can be stably formed so as to prevent sticking of a movable part and which has a narrow gap, and a method of manufacturing the same are provided. The micro electro-mechanical system includes at least one fixed electrode formed above a principal surface of a... Agent: Rabin & Berdo, PC

20080224318 - System and method for integrated circuit arrangement having a plurality of conductive structure levels: An integrated circuit arrangement includes a substrate with a multiplicity of integrated semiconductor components arranged therein, the substrate having a wiring interconnect near to the substrate, a middle wiring interconnect and a wiring interconnect remote from the substrate, which are arranged in this order at increasing distance from the substrate.... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080224321 - Cell data for spare cell, method of designing a semiconductor integrated circuit, and semiconductor integrated circuit: In a cell base design, when a circuit using a spare cell is corrected, a wiring length is shortened as much as possible, and the number of wiring layers which are affected by correction is reduced. Mask pattern data that expresses the configurations of a signal input terminal and a... Agent: Young & Thompson

20080224320 - Silicon chip having inclined contact pads and electronic module comprising such a chip: A semiconductor chip has an active face in which an integrated circuit region is implanted. The chip includes an inclined lateral contact pad extending beneath the plane of the active face and electrically linked to the integrated circuit region. An electronic module includes a substrate having a cavity in which... Agent: Seed Intellectual Property Law Group PLLC

20080224322 - Semiconductor device and manufacturing method thereof: This invention is directed to offer a semiconductor device having a stacked layer structure and its manufacturing method that bring high yield and reliability. Semiconductor dice judged as good dice are stacked on a base substrate in which through holes and through hole electrodes are formed. Next, a protection layer... Agent: Morrison & Foerster LLP

20080224324 - Semiconductor device and method of manufacturing the same: A semiconductor device of one embodiment has a substrate, a semiconductor chip mounted over the substrate by flip-chip bonding, and a semiconductor chip provided over the semiconductor chip, wherein a space resides between the substrate and the semiconductor chip.... Agent: Young & Thompson

20080224323 - Semiconductor module with semiconductor chips and method for producing it: A semiconductor module (1) which has semiconductor chips (2) each with one power supply electrode (6, 7) on its back, respectively for applying a supply potential (4, 5) and each with a power output electrode (8, 9) on its top side, respectively for transferring an output current to power outputs... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20080224325 - Wiring board, mounting structure for electronic components, and semiconductor device: A wiring board includes a main surface where an electronic component is mounted in a face-down manner so that a surface of the electronic component having plurality of external connecting terminals faces the main surface of the wiring board, the electronic component being fixed to the wiring board by an... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080224326 - Chip structure with bumps and testing pads: A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate. The dielectric layers are... Agent: Mou-shiung Lin Room 301/302

20080224327 - Microelectronic substrate including bumping sites with nanostructures: A microelectronic substrate and a package including the substrate. The substrate comprises: a wafer; circuitry disposed within the wafer and including a plurality of bonding pads; and a plurality of bumping sites disposed on respective ones of the bonding pads, each of the bumping sites comprising a nanolayer including columnar... Agent: Intel Corporation C/o Intellevate, LLC

20080224328 - Temporary chip attach using injection molded solder: An improved method for performing an improved Temporary Chip Attach utilizing an Injection Molded Solder (IMS) process to allow efficient testing of die for creating a Known Good Die Bank. The IMS is applied to the testing substrate to form a column on the substrate. The die to be tested... Agent: International Business Machines Corporation Dept. 18g

20080224329 - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the... Agent: Perkins Coie LLP Patent-sea

20080224330 - Power delivery package having through wafer vias: An integrated circuit chip package and a method of manufacture thereof are provided. In one embodiment, the integrated circuit chip package comprises a semiconductor die having power and ground routings, a plurality of through wafer vias disposed within the semiconductor die, the through wafer vias connected to the power and... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080224331 - Electronic device and method for manufacturing the same: An electronic device includes: a semiconductor chip that includes an integrated circuit, a plurality of electrodes electrically connected to the integrated circuit, and a passivation film formed in a manner that at least a portion of each of the plurality of electrodes is exposed; a resin layer that is formed... Agent: Harness, Dickey & Pierce, P.L.C

20080224332 - Transistor circuit formation substrate and method of manufacturing transistor: A specially designed mask controls the arrangement of conductive materials that form a source and drain of a transistor. Designing the mask can be costly and time-consuming, which means that the testing of a circuit involving a transistor can also be costly, time consuming and a barrier towards efficient circuit... Agent: Oliff & Berridge, PLC

20080224333 - Semiconductor device and method of manufacturing the same: A semiconductor device is disclosed that includes a wiring board having a via formed therein; a semiconductor element provided on the wiring board; a resist layer covering a surface of the wiring board, the resist layer having an opening in a part thereof positioned on the via; and a sealing... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080224334 - Molded beam for optoelectronic sensor chip substrate: A substrate on which a plurality of epoxy over molded integrated circuit dies are formed includes a beam formed on the substrate for providing stiffness to the substrate. The beam includes structure having a cross-sectional shape, for example, substantially in the shape of a trapezoid, “T” or “L”, and may... Agent: Locke Lord Bissell & Liddell LLP Attn: Michael Ritchie, Docketing

20080217600 - Multi-level data memorisation device with phase change material: P

20080217601 - Light emitting devices: Light-emitting devices, and related components, systems and methods are disclosed.... Agent: Wolf Greenfield & Sacks, P.c.

20080217602 - Quantum dot light emitting device: An inorganic light emitting device including a transparent substrate; a first electrode; a second electrode opposed to the first electrode; a polycrystalline inorganic light emitting layer including core/shell quantum dots within an inorganic semiconductor matrix and, wherein the first electrode is transparent and formed on the transparent substrate, the polycrystalline... Agent: Frank Pincelli Patent Legal Staff

20080217603 - Hot electron transistor and semiconductor device including the same: A hot electron transistor includes a collector layer, a base layer, an emitter layer, a collector barrier layer formed between the collector layer and the base layer, and an emitter barrier layer formed between the base layer and the emitter layer. An energy barrier between the emitter barrier layer and... Agent: Mcdermott Will & Emery LLP

20080217608 - Light-emitting element, light-emitting device, electronic device and quinoxaline derivative: The present invention provides light-emitting element having long lifetime, and light-emitting devices and electronic devices having long lifetime. A light-emitting element comprises a first layer and a second layer including a light-emitting substance between a first electrode and a second electrode. The first layer includes a first organic compound and... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd

20080217605 - Oligomers and polymers: An optionally substituted oligomer or polymer comprising a repeat unit of formula (I); wherein each Ar1 and Ar3 is the same or different and independently represents an optionally substituted aryl or heteroaryl; n is at least 1; Ar2 represents an optionally substituted aryl or heteroaryl comprising a linking ring to... Agent: Connolly Bove Lodge & Hutz, LLP

20080217606 - Organic light emitting diode containing a ir complex having a novel ligand as a phosphorescent emitter: An organic light emitting diode with Ir complex is disclosed in this specification, wherein the Ir complex is used as the phosphorous emitter. The chemical containing pyridyl triazole or pyridyl imidazole functional group is used as the auxiliary monoanionic bidentate ligand in the mentioned Ir complex, so that the CIE... Agent: Wpat, Pc

20080217604 - Organic semiconductor film, electron device using the same and manufacturing method therefor: An organic semiconductor film that can be used for an electron device, for example, particularly can be used for organic TFTs so as to allow the TFTs to have advanced performance, is provided and a manufacturing method therefor is provided. For instance, the organic semiconductor film contains the organic conductive... Agent: Hamre, Schumann, Mueller & Larson P.c.

20080217609 - Organic transistor, method for manufacturing the same, and electronic apparatus including the same: An organic transistor includes a source electrode and a drain electrode, an organic semiconductor layer disposed across between the source electrode and the drain electrode, a gate insulating layer, and a gate electrode opposing the source and drain electrodes with the organic semiconductor layer and the gate insulating layer therebetween.... Agent: Harness, Dickey & Pierce, P.L.C

20080217607 - Protein switches incorporating cytochrome c3 in monolayers and method for producing same: A biomolecular electronic switch includes a first electrical contact, a second electrical contact, a programmable monolayer of either cytochrome c or cytochrome c3 or bovine serum hormone sandwiched between the first and second electrical contacts and a substrate. These switches have high current-carrying capacities and are very fast. It appears... Agent: Office Of Command Counsel U.s. Army Materiel Command

20080217610 - Thin film transistor having n-type and p-type cis thin films and method of manufacturing the same: Provided is a thin film transistor (TFT) which uses CIS (CuInSe2), including Se, which is a chalcogen-based material, and can provide a rectifying function, and electric and optical switching functions of a diode. The TFT according to the present invention includes, a substrate, a gate electrode formed on a portion... Agent: Lahive & Cockfield, LLP Floor 30, Suite 3000

20080217611 - Ultraviolet sensor: A diode type ultraviolet sensor having a layered-structure body including a conductive layer composed of a sintered ceramic body having conductivity and a semiconductor layer composed of an oxide semiconductor including ZnO. The semiconductor layer is disposed on a principal surface of the conductive layer and forms a heterojunction with... Agent: Dickstein Shapiro LLP

20080217615 - Method for arranging chips of a first substrate on a second substrate: The invention relates to a method for arranging chips of a first substrate on a second substrate, in which the chips are grouped at least into first chips and into second chips, the first chips of the first substrate are singulated and the singulated first chips are arranged on the... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080217613 - Positional offset measurement pattern unit featuring via-plug and interconnections, and method using such positional offset measurement pattern unit: In a positional offset measurement pattern unit formed in an insulating layer, a first interconnection is formed in the insulating layer. A via-plug is formed in the insulating layer so as to be electrically connected to the first interconnection. A second interconnection is formed in the insulating layer at substantially... Agent: Young & Thompson

20080217612 - Structure and method of mapping signal intensity to surface voltage for integrated circuit inspection: Embodiments of the present invention provide a test structure for inspection of integrated circuits. The test structure may be fabricated on a semiconductor wafer together with one or more integrated circuits. The test structure may include a common reference point for voltage reference; a plurality of voltage dropping devices being... Agent: International Business Machines Corporation Dept. 18g

20080217614 - Systems and methods for controlling of electro-migration: Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson Pllc

20080217616 - Semiconductor integrated circuit device and a method of fabricating the same: A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to... Agent: Lee & Morse, P.c.

20080217621 - Active device array substrate: A method of fabricating an active device array substrate is provided. A substrate having scan lines, data lines and active devices formed thereon is provided. Each of the active devices is electrically connected to the corresponding scan line and data line. An organic material layer is formed over the substrate... Agent: Jianq Chyun Intellectual Property Office

20080217618 - Thin film circuits: A thin film circuit comprises a plurality of thin film transistors, each having a light shield portion (60) which is electrically isolated from the source (72), drain (70) and gate (76) electrodes. The light shield portion comprises a first, drain overlap portion in which the light shield portion overlaps the... Agent: Philips Intellectual Property & Standards

20080217619 - Thin film transistor and display device: The fully depleted thin film transistor (TFT) formed on a semiconductor film (103) on an insulator (101) is, in order to improve characteristics of the fully depleted thin film transistor, formed including a gate electrode formed over the semiconductor film having a gate insulating film (107) therebetween, source-drain regions (111)... Agent: Oliff & Berridge, Plc

20080217620 - Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same: A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, and including a channel region, source and drain regions, and edge regions having a first impurity formed at edges of the source and drain regions, and optionally, in the channel region; a gate insulating layer insulating... Agent: Stein, Mcewen & Bui, LLP

20080217617 - Thin film transistor, wiring board and methods of manufacturing the same: A gate electrode or a gate wiring of a thin-film transistor has a four-layer structure including an adhesive base layer, a catalyst layer, a wiring metal layer, and a wiring metal anti-diffusion layer which are laminated in this order. With this structure, adhesion and flatness are improved. In this case,... Agent: Birch Stewart Kolasch & Birch

20080217622 - Novel, semiconductor-based, large-area, flexible, electronic devices: Novel articles and methods to fabricate the same resulting in flexible, large-area, triaxially textured, single-crystal or single-crystal-like, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based... Agent: Dr. Amit Goyal

20080217623 - Optical sensor element and method for driving the same: v

20080217624 - Capacitor and light emitting display using the same: A capacitor including a polysilicon layer doped with impurities to be conductive, a first dielectric layer formed on the polysilicon layer, a first conductive layer formed on the first dielectric layer, a second dielectric layer formed on the first conductive layer, and a second conductive layer formed on the first... Agent: H.c. Park & Associates, Plc

20080217625 - Nitride semiconductor device and manufacturing method thereof: It is an object of the present invention to provide a nitride semiconductor device with low parasitic resistance by lowering barrier height to reduce contact resistance at an interface of semiconductor and metal. The nitride semiconductor device includes a GaN layer, a device isolation layer, an ohmic electrode, an n-type... Agent: Greenblum & Bernstein, P.L.C

20080217626 - Diamond semiconductor element and process for producing the same: An integrated optical waveguide has a first optical waveguide, a second optical waveguide, and a groove. The second optical waveguide is coupled to the first optical waveguide and has a refractive index that is different from the first optical waveguide. The groove is disposed so as to traverse an optical... Agent: Workman Nydegger

20080217627 - Sic-pn power diode: An integrated vertical SiC—PN power diode has a highly doped SiC semiconductor body of a first conductivity type, a low-doped drift zone of the first conductivity type, arranged above the semiconductor body on the emitter side, an emitter zone of a second conductivity type, applied to the drift zone, and... Agent: Lerner Greenberg Stemer LLP

20080217629 - Ac light emitting diode having improved transparent electrode structure: Disclosed is an AC light emitting diode having an improved transparent electrode structure. The light emitting diode comprises a plurality of light emitting cells formed on a single substrate, each of the light emitting cells having a first conductive type semiconductor layer, a second conductive type semiconductor layer positioned on... Agent: H.c. Park & Associates, Plc

20080217628 - Light emitting device: The present invention relates to a light emitting device having a light emitting diode package with a plurality of light emitting cells and an integrated electronic element formed on the same substrate. The light emitting device comprises a substrate, a light emitting cell block having a first array with a... Agent: Marger Johnson & Mccollom, P.c.

20080217630 - Light emission device: The invention relates to a light emission device, comprising at least two light-emitting semiconductor chips and a substrate. At least one first semiconductor chip (12) is fitted on the substrate and a second semiconductor chip (14) is fitted on the first semiconductor chip (12).... Agent: John C. Thompson

20080217631 - Semiconductor light emitting apparatus and the manufacturing method thereof: A semiconductor light emitting apparatus is provided. The semiconductor light emitting apparatus includes a light-emitting device, a transparent material and at least one transparent film. The light-emitting device is located in a package substrate. The transparent material covers the light-emitting device. The transparent film is located between the light-emitting device... Agent: Joe Mckinney Muncy

20080217632 - Gan-based iii-v compound semiconductor light-emitting element and method for manufacturing thereof: A GaN-based semiconductor laser element 10 has a laminated structure of: a stripe-shaped convex portion 18 made of a surface layer of a sapphire substrate 12, a buffer layer 14 and a first GaN layer 16, and on the sapphire substrate, a second GaN layer 20, an n-side cladding layer... Agent: Robert J. Depke Lewis T. Steadman

20080217636 - Electroluminescence device: An electroluminescence device comprising at least one electroluminescence light source (2) for emitting a primary radiation, preferably having wavelengths between 200 nm and 490 nm, and at least one light-converting element (3), arranged in the path of the rays of the primary radiation, for partial absorption of the primary radiation... Agent: Philips Intellectual Property & Standards

20080217641 - Light emitting devices having a roughened reflective bond pad and methods of fabricating light emitting devices having roughened reflective bond pads: Light emitting devices include an active region of semiconductor material and a first contact on the active region. The first contact is configured such that photons emitted by the active region pass through the first contact. A photon absorbing wire bond pad is provided on the first contact. The wire... Agent: Myers Bigel Sibley & Sajovec

20080217635 - Light emitting devices having current reducing structures and methods of forming light emitting devices having current reducing structures: A light emitting device includes a p-type semiconductor layer, an n-type semiconductor layer, and an active region between the n-type semiconductor layer and the p-type semiconductor layer. A non-transparent feature, such as a wire bond pad, is on the p-type semiconductor layer or on the n-type semiconductor layer opposite the... Agent: Myers Bigel Sibley & Sajovec, P.a.

20080217637 - Light emitting diode and method of fabricating the same: The present invention relates to a light emitting diode and a method of fabricating the same, wherein the distance between a fluorescent substance and a light emitting diode chip is uniformly maintained to enhance luminous efficiency. To this end, there is provided a light emitting diode comprising at least one... Agent: Marger Johnson & Mccollom, P.c.

20080217633 - Light emitting diode structure: Disclosed is a new LED structure comprising a substrate, and a light emitting die entrained on the substrate. The substrate is made of the lower temperature co-fired ceramic or high temperature co-fired ceramic. The substrate is provided with a printed circuit which can be electrically in connection with an electric... Agent: Lowe Hauptman Ham & Berner, LLP

20080217639 - Photonic crystal light emitting device using photon-recycling: A photonic crystal light emitting device including: a light emitting diode (LED) light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first and second conductive semiconductor layers; and a first photon-recycling light emitting layer formed on one surface... Agent: Mcdermott Will & Emery LLP

20080217638 - Semiconductor light emitting device and fabrication method thereof: A semiconductor light emitting device includes a first semiconductor layer having a bottom surface with uneven patterns, an active layer formed on the first semiconductor layer, a second semiconductor layer formed on the active layer, a second electrode formed on the second semiconductor layer, and a first electrode formed under... Agent: Birch Stewart Kolasch & Birch

20080217640 - Semiconductor light emitting device, led package using the same, and method for fabricating the same: A semiconductor light emitting device is provided which can prevent the reflectance of a metal film from deteriorating due to heat aging and can prevent wire bonding performance of the semiconductor light emitting element from deteriorating due to the diffusion of Ni contained in a Ni barrier metal layer to... Agent: Frishauf, Holtz, Goodman & Chick, Pc

20080217634 - Vertical light-emitting diode structure with omni-directional reflector: A vertical light-emitting diode (VLED) structure with an omni-directional reflector (ODR) that may offer increased light extraction and greater luminous efficiency when compared to conventional VLEDs is provided.... Agent: Patterson & Sheridan, L.l.p.

20080217644 - Containment structure and method: Containment structures for an organic composition, comprising a first zone having a first surface energy, and a second zone having a second surface energy different than the first surface energy, and methods for making the same.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20080217642 - Light emitting diode with a step section between the base and the lens of the diode: A light emitting diode 1 has a light emitting element 2, a lead section 3 that supplies power to the light emitting element 2, a base 4 that covers the lead section 3, a lens 5 having a convex light emitting surface and connected to the base 4 to cover... Agent: Kathy Manke Avago Technologies Limited

20080217643 - Light-emitting diode and heat radiating unit therefor: A light-emitting diode (LED) is mounted on a heat radiating unit therefor. The LED includes a metal carrier having two through holes, and a light-emitting chip packaged on the metal carrier and having a positive and a negative pin fixed to and insulated from the through holes by sintered glass.... Agent: Rosenberg, Klein & Lee

20080217646 - Nitride semiconductor light emitting device: The present invention presents a nitride semiconductor light emitting device including a substrate, a first n-type nitride semiconductor layer, a light emitting layer, a p-type nitride semiconductor layer, a p-type nitride semiconductor tunnel junction layer, an n-type nitride semiconductor tunnel junction layer, and a second n-type semiconductor layer, in which... Agent: Harness, Dickey & Pierce, P.L.C

20080217645 - Thick nitride semiconductor structures with interlayer structures and methods of fabricating thick nitride semiconductor structures: A semiconductor structure includes a substrate, a nucleation layer on the substrate, a compositionally graded layer on the nucleation layer, and a layer of a nitride semiconductor material on the compositionally graded layer. The layer of nitride semiconductor material includes a plurality of substantially relaxed nitride interlayers spaced apart within... Agent: Myers Bigel Sibley & Sajovec, P.a.

20080217648 - Light-emitting element and light-emitting device: An object is to provide a light-emitting element and a light-emitting device each of which consumes less power and has high emission efficiency, high performance, and high reliability. A light-emitting element has an EL layer provided with a light-emitting layer, which includes an inorganic light-emitting material containing a mixed-valence compound,... Agent: Nixon Peabody, LLP

20080217647 - Method of forming nitride semiconductor layer on patterned substrate and light emitting diode having the same: A method of forming high quality nitride semiconductor layers on a patterned substrate and a light emitting diode having the same are disclosed. After forming a nucleation layer on the patterned substrate, a first 3D and 2D growth layers are formed thereon in this order by growing nitride semiconductor layers... Agent: H.c. Park & Associates, Plc

20080217649 - Power semiconductor device and power conversion device using the same: A power semiconductor device having a low loss and a high reliability and a power conversion device using the power semiconductor device are provided. In the power semiconductor device, a plurality of MOS type trench gates are positioned to be spaced by at-least two types of intervals therebetween, a low-resistance... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080217650 - Semiconductor circuit including electrostatic discharge circuit having protection element and trigger transistor: A semiconductor circuit includes, a first pad for a first power source, a second pad for a second power source, a third pad for an input/output signal, a protection element arranged between the third pad and the second pad; and a transistor functioning as a trigger element for use in... Agent: Mcginn Intellectual Property Law Group, Pllc

20080217651 - Photodetector: A photodetector is provided. The photodetector includes a base piece; a germanium layer mounted on the base piece and including a first area and a second area; a first metal electrode mounted on the first area; an insulation layer mounted on the second area; and a second metal electrode mounted... Agent: Sutherland Asbill & Brennan LLP

20080217652 - Growth of assb-based semiconductor structures on inp substrates using sb-containing buffer layers: This invention provides high quality and low defect density Sb-containing alloys on lattice-mismatched substrates using Sb-containing buffer layers. More specifically, provided is a method of forming an epitaxial semiconductor alloy on a substrate, comprising: providing a substrate (such as InP); growing an Sb-containing buffer layer on the substrate; and growing... Agent: Greenlee Winner And Sullivan P C

20080217653 - Method of manufacturing a semiconductor device with an isolation region and a device manufactured by the method: A method of manufacturing a semiconductor device includes forming trench isolation structures, exposing some of the trench isolation structures 28 to leave others 30 masked, and then selectively etching a buried layer to form a cavity 32 under an active device region 34. The active device region 34 is supported... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080217654 - Semiconductor device and method of fabricating the same: A semiconductor device includes an element isolation film having an inclined portion and a flat portion, a protective film formed not on the inclined portion but on the flat portion of the element isolation film, and an outer base layer formed to extend from on a surface of an active... Agent: Mcdermott Will & Emery LLP

20080217655 - Integrated circuit with buried control line structures: An integrated circuit with buried control line structures. In one embodiment, the control lines are subdivided into sections, wherein regions free of switching transistors are provided at intervals along the control lines. Connections for feeding the control potentials into the sections of the control lines are provided at least in... Agent: Dicke, Billig & Czaja

20080217656 - I/o circuit with esd protecting function: For ensuring the complete turn-off state of an ESD protecting device and preventing leakage current from a chip, an alternative conducting path is formed in the chip for bypassing an external current. The chip further includes an internal circuit and a conducting circuit.... Agent: Kirton And Mcconkie

20080217657 - Power semiconductor device and method of manufacturing a power semiconductor device: A semiconductor power switch having an array of basic cells in which peripheral regions in the active drain region extend beside the perimeter of the base-drain junction, the peripheral regions being of higher dopant density than the rest of the second drain layer. Intermediate regions in the centre of the... Agent: Freescale Semiconductor, Inc. Law Department

20080217658 - Electrical antifuse with integrated sensor: The present invention provides structures for antifuses that utilize electromigration for programming. By providing a portion of antifuse link with high resistance without conducting material and then by inducing electromigration of the conducting material into the antifuse link, the resistance of the antifuse structure is changed. By providing a terminal... Agent: Scully, Scott, Murphy & Presser, P.c.

20080217659 - Device and method to reduce cross-talk and blooming for image sensors: An image sensor device includes a semiconductor substrate having a first type of conductivity, a first layer overlying the semiconductor substrate and having the first type of conductivity, a second layer overlying the first layer and having a second type of conductivity different than the first type of conductivity, and... Agent: Haynes And Boone, LLP

20080217660 - Solid image pick-up element and method of producing the same: A solid image pick-up element comprises: a photoelectric converting portion; a charge transmitting portion comprising a charge transmitting electrode that transmits a charge generated by the photoelectric converting portion; and a peripheral circuit portion connected to the charge transmitting portion, wherein a surface level of a field oxide film provided... Agent: Birch Stewart Kolasch & Birch

20080217661 - Two-dimensional time delay integration visible cmos image sensor: A two dimensional time delay integration CMOS image sensor having a plurality of pinned photodiodes, each pinned photodiode collects a charge when light strikes the pinned photodiode, a plurality of electrodes separating the plurality of pinned photodiodes, the plurality of electrodes are configured for two dimensional charge transport between two... Agent: Snell & Wilmer LLP (oc)

20080217662 - Space-efficient package for laterally conducting device: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the... Agent: Townsend And Townsend And Crew, LLP

20080217663 - Enhanced transistor performance by non-conformal stressed layers: NFET and PFET devices with separately strained channel regions, and methods of their fabrication is disclosed. A stressing layer overlays the device in a manner that the stressing layer is non-conformal with respect the gate. The non-conformality of the stressing layer increases the amount of stress that is imparted onto... Agent: Innovation Interface, Llc

20080217664 - Gate self aligned low noise jfet: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating... Agent: Texas Instruments Incorporated

20080217665 - Semiconductor device structure having enhanced performance fet device: A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate: a first layer below and second layers on a gate with spacers, source and drain regions adjacent to the gate, silicides on the gate and source and drain regions; disposing a stress layer over... Agent: International Business Machines Corporation Dept. 18g

20080217666 - Cmos image sensor and method of fabricating the same: A floating node structure of a CMOS image sensor disposed in a floating node region defined by an isolation structure of a substrate is described. The floating node structure comprises an n-doped region within the floating node region, a p-well surrounding the periphery and the bottom of the n-doped region... Agent: J C Patents, Inc.

20080217667 - Image sensing device: An image sensing device includes a substrate with a photo sensing and a transistor region, a photo diode, a transistor, a dielectric layer, a metal interconnect, a metal conductive line, a conformal passivation layer, a color filter, a lens planar layer, and a microlens. The photo diode is in the... Agent: Jianq Chyun Intellectual Property Office

20080217668 - Semiconductor device and method of manufacturing the same: After a ferroelectric capacitor (1) is formed and before a wiring (15) to be a pad is formed, an alumina film (11) is formed as a diffusion suppressing film suppressing diffusion of hydrogen and moisture. Subsequently, the wiring (15) is formed and an SOG film (16) is formed thereon. Then,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080217669 - Semiconductor memory device and method for fabricating semiconductor memory device: According to an aspect of the present invention, there is provided a semiconductor memory device comprising, a first transistor and a second transistor formed on a semiconductor substrate, a memory capacitor formed above the first transistor, the memory capacitor being connected to the first transistor, a dummy memory capacitor formed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080217670 - Methods of manufacturing a semiconductor device; method of manufacturing a memory cell; semiconductor device; semiconductor processing device; integrated circuit having a memory cell: Methods of manufacturing a semiconductor device, a method of manufacturing a memory cell, a semiconductor device, a semiconductor processing device, and a memory cell, are provided. In one embodiment a method of manufacturing a semiconductor device is provided including forming a metal doped chalcogenide layer using light irradiation at least... Agent: Slater & Matsil LLP

20080217671 - Methods for forming semiconductor structures with buried isolation collars and semiconductor structures formed by these methods: A semiconductor structure including a trench formed in a substrate and a buried isolation collar that extends about sidewalls of the trench. The buried isolation collar is constituted by an insulator formed from a buried porous region of substrate material. The porous region is formed from a buried doped region... Agent: Wood, Herron & Evans, L.l.p. (ibm)

20080217672 - Integrated circuit having a memory: An integrated circuit having a memory arrangement including capacitor elements and further capacitor elements is disclosed. One embodiment provides a substrate layer with contact pads and further contact pads; the capacitor elements being disposed in a first level on the substrate layer and connected with the contact pads; the further... Agent: Dicke, Billig & Czaja

20080217673 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a stack structure in which multiple channel layers are stacked on a substrate so as to be sandwiched between bit line layers, a gate electrode that is provided to the side of the lateral surface of an interior of a groove portion formed within the stack... Agent: Ingrassia Fisher & Lorenz, P.c.

20080217674 - Semiconductor memory device and method of fabrication of the same: A semiconductor memory device includes a first memory cell transistor. The first memory cell transistor includes a tunnel insulation film provided on a semiconductor substrate, a floating electrode provided on the tunnel insulation film, an inter-gate insulation film provided on the floating electrode, and a control electrode provided on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080217677 - Non-volatile semiconductor memory device with alternative metal gate material: A non-volatile semiconductor memory device comprises a substrate including a source region, a drain region and a channel region provided between the source region and the drain region with a gate stack located above the channel region with a metal gate located above the gate stack. The metal gate is... Agent: Buchanan, Ingersoll & Rooney Pc

20080217675 - Novel profile of flash memory cells: A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed... Agent: Slater & Matsil, L.l.p.

20080217676 - Zirconium silicon oxide films: Electronic apparatus and systems include structures having a dielectric layer containing a zirconium silicon oxide film. A zirconium silicon oxide film may be disposed in an integrated circuit, as well as in a variety of other electronic devices. Additional apparatus, systems, and methods are disclosed.... Agent: Schwegman, Lundberg & Woessner/micron

20080217681 - Charge trap memory device and method of manufacturing the same: Provided are a charge trap memory device and method of manufacturing the same. A charge trap memory device may include a tunnel insulating layer on a substrate, a charge trap layer on the tunnel insulating layer, and a blocking insulating layer formed of a material including Gd or a smaller... Agent: Harness, Dickey & Pierce, P.L.C

20080217678 - Memory gate stack structure: A memory gate stack structure (100) comprising a substrate layer (102) comprising a silicon-based material, a tunnel layer (104) formed on the substrate layer, a charge storage layer (106) formed on the tunnel layer and comprising a hafnium-aluminium-oxide-based material, a blocking layer (108) formed on the charge storage layer, and... Agent: Lipsitz & Mcallister, Llc

20080217679 - Memory unit structure and operation method thereof: A memory unit is proposed. The memory unit includes a Si substrate, a trapping layer formed on the Si substrate, a first and a second doping regions formed in the Si substrate on either side of the trapping layer, a gate formed on the trapping layer, a first oxide layer... Agent: J C Patents, Inc.

20080217680 - Non-volatile semiconductor memory using charge-accumulation insulating film: There is provided a non-volatile semiconductor memory having a charge accumulation layer of a configuration where a metal oxide with a dielectric constant sufficiently higher than a silicon nitride, e.g., a Ti oxide, a Zr oxide, or a Hf oxide, is used as a base material and an appropriate amount... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080217682 - Selective incorporation of charge for transistor channels: A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions... Agent: Keusey, Tutunjian & Bitetto, P.c.

20080217683 - Self-aligned double layered silicon-metal nanocrystal memory element, method for fabricating the same, and memory having the memory element: A nanocrystal memory element and a method for fabricating the same are proposed. The fabricating method involves selectively oxidizing polysilicon not disposed beneath and not covered with a plurality of metal nanocrystals, and leaving intact the polysilicon disposed beneath and thereby covered with the plurality of metal nanocrystals, with a... Agent: Wpat, Pc Intellectual Property Attorneys

20080217684 - Semiconductor device and manufacturing method thereof and power supply apparatus using the same: A semiconductor device comprises a trench-gate type field-effect transistor on a semiconductor substrate having a first main surface and a second main surface oppositely positioned in a thickness direction, wherein the trench-gate type field-effect transistor comprises a first semiconductor region at the first main surface side; a second semiconductor region... Agent: Townsend And Townsend And Crew, LLP

20080217685 - Semiconductor device and method for manufacturing the same: A semiconductor device includes an isolation layer for dividing a silicon substrate into an active region and an inactive region, a gate electrode formed over the silicon substrate, a gate oxide layer formed around a sidewall of the gate electrode to expose an upper portion of the sidewall of the... Agent: Sherr & Nourse, Pllc

20080217687 - Active device array substrate and repairing method thereof: A simple active device array substrate and an easy repairing method thereof are provided. The pattern layer of the drain electrode has an extended portion extending to the region between an adjacent pixel electrode and the substrate. Once the pixel is found to be a white defect, a laser beam... Agent: Joe Mckinney Muncy

20080217688 - Semiconductor device and manufacture method thereof: An object is to provide an element structure of a semiconductor device for increasing an etching margin for various etching steps and a method for manufacturing the semiconductor device having the element structure. An island-shaped semiconductor layer is provided over an insulator having openings. The island-shaped semiconductor layer includes embedded... Agent: Nixon Peabody, LLP

20080217689 - Semiconductor devices having silicon-on-insulator (soi) substrates and methods of manufacturing the same: Semiconductor devices are provided including gate patterns on a substrate and isolation regions on the substrate. Insulating patterns are provided in the substrate below the gate patterns. Source/drain regions are provided in the substrate. Related methods of fabricating semiconductor devices are also provided.... Agent: Myers Bigel Sibley & Sajovec

20080217686 - Ultra-thin soi cmos with raised epitaxial source and drain and embedded sige pfet extension: A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe... Agent: Scully, Scott, Murphy & Presser, P.c.

20080217692 - Asymmetrically stressed cmos finfet: A CMOS device comprising a FinFET comprises at least one fin structure comprising a source region; a drain region; and a channel region comprising silicon separating the source region from the drain region. The FinFET further comprises a gate region comprising a N+ polysilicon layer on one side of the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080217691 - Higher performance cmos on (110) wafers: A semiconductor (e.g., complementary metal oxide semiconductor (CMOS)) structure formed on a (110) substrate that has improved performance, in terms of mobility enhancement is provided. In accordance with the present invention, the inventive structure includes at least one of a single tensile stressed liner, a compressively stressed shallow trench isolation... Agent: Scully, Scott, Murphy & Presser, P.c.

20080217690 - Latch-up resistant semiconductor structures on hybrid substrates and methods for forming such semiconductor structures: Latch-up resistant semiconductor structures formed on a hybrid substrate and methods of forming such latch-up resistant semiconductor structures. The hybrid substrate is characterized by first and second semiconductor regions that are formed on a bulk semiconductor region. The second semiconductor region is separated from the bulk semiconductor region by an... Agent: Wood, Herron & Evans, L.l.p. (ibm)

20080217693 - Structure to improve mos transistor on-breakdown voltage and method of making the same: A novel MOS transistor structure and methods of making the same are provided. The structure includes a MOS transistor formed on a semiconductor substrate of a first conductivity type with a plug region of first conductivity type formed in the drain extension region of second conductivity type (in the case... Agent: Slater & Matsil, L.l.p.

20080217694 - Spacers for finfets (field effect transistors): A spacer structure for FinFETs. The structure includes (a) a substrate, (b) a semiconductor fin region on top of the substrate, (c) a gate dielectric region on side walls of the semiconductor fin region, and (d) a gate electrode region on top and on side walls of the semiconductor fin... Agent: Schmeiser, Olsen & Watts

20080217697 - Control of poly-si depletion in cmos via gas phase doping: A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are... Agent: Scully, Scott, Murphy & Presser, P.c.

20080217695 - Heterogeneous semiconductor substrate: A substrate comprising a first region of a first semiconductor and a second region of second semiconductor, wherein the first semiconductor and the second semiconductor are different, is disclosed. The substrate is particularly supportive of p-channel MOSFETs and n-channel MOSFETs having carrier mobility that is closer than in substrates comprising... Agent: Demont & Breyer, Llc

20080217696 - Method and structure for controlling stress in a transistor channel: A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves forming a shallow-trench-isolation oxide (STI) isolating the n-type device from the p-type device. The method further involves adjusting the shallow-trench-isolation oxide corresponding to at least one of... Agent: Greenblum & Bernstein, P.L.C

20080217698 - Methods and semiconductor structures for latch-up suppression using a conductive region: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate... Agent: Wood, Herron & Evans, L.l.p. (ibm)

20080217699 - Isolated bipolar transistor: An isolated bipolar transistor formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate... Agent: Patentability Associates

20080217700 - Mobility enhanced fet devices: NFET and PFET devices with separately stressed channel regions, and methods of their fabrication is disclosed. A FET is disclosed which includes a gate, which gate includes a metal in a first state of stress. The FET also includes a channel region hosted in a single crystal Si based material,... Agent: Innovation Interface, Llc

20080217701 - Design solutions for integrated circuits with triple gate oxides: An integrated circuit includes a first core circuit and a second core circuits. The first core circuit includes a first MOS device, wherein a first gate dielectric of the first MOS device has a first thickness. The second core circuit includes a second MOS device, wherein a second gate dielectric... Agent: Slater & Matsil, L.l.p.

20080217703 - Highly selective liners for semiconductor fabrication: A method for manufacturing an isolation structure is disclosed that protects the isolation structure during etching of a dichlorosilane (DCS) nitride layer. The method involves the formation of a bis-(t-butylamino)silane-based nitride liner layer within the isolation trench, which exhibits a five-fold greater resistance to nitride etching solutions as compared with... Agent: Texas Instruments Incorporated

20080217702 - Semiconductor device and method of fabricating isolation region: A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate; an isolation region including a liner film formed so as to contact a lower surface and a lower side surface of an inner wall of a trench formed in the semiconductor substrate, a first insulating... Agent: Foley And Lardner LLP Suite 500

20080217704 - Semiconductor device: In a semiconductor device including multiple unit cells arranged in an array, transistors are affected by a stress from an STI at different degrees depending on the position in the array. As a result, a variation occurs in transistor characteristic. In a semiconductor device according to the present invention, each... Agent: Mcginn Intellectual Property Law Group, Pllc

20080217705 - Trench formation in a semiconductor material: A semiconductor device is formed on a semiconductor layer. A gate dielectric layer is formed over the semiconductor layer. A layer of gate material is formed over the gate dielectric layer. The layer of gate material is patterned to form a gate structure. Using the gate structure as a mask,... Agent: Freescale Semiconductor, Inc. Law Department

20080217706 - Semiconductor device and method of manufacturing the same: There is provided a method of manufacturing a semiconductor device, including forming a structure including a first layer containing Si and a metal oxide layer in contact with the first layer, the metal oxide layer having a dielectric constant higher than that of silicon oxide, and heating the structure in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080217707 - Transistor having gate and body in direct self-aligned contact and related methods: A transistor having a directly contacting gate and body and related methods are disclosed. In one embodiment, the transistor includes a gate; a body; and a dielectric layer extending over the body to insulate the gate from the body along an entire surface of the body except along a portion... Agent: Hoffman Warnick Llc

20080217708 - Integrated passive cap in a system-in-package: According to an exemplary embodiment, a system-in-package includes at least one semiconductor die situated over a package substrate. The system-in-package further includes a wall structure situated on the at least one semiconductor die. The system-in-package further includes an integrated passive cap situated over the wall structure, where the integrated passive... Agent: Farjami & Farjami LLP

20080217709 - Mems package having at least one port and manufacturing method thereof: A plurality of individual MEMS packages are formed as a contiguous unit and each of the plurality of individual MEMS packages include at least one acoustic port. One or more separation boundaries from where to separate adjacent ones of the plurality of individual MEMS packages are determined. Each of the... Agent: Fitch Even Tabin And Flannery

20080217710 - Novel syaf structure to fabricate mbit mtj mram: A MTJ that minimizes error count (EC) while achieving high MR value, low magnetostriction, and a RA of about 1100 Ω-μm2 for 1 Mbit MRAM devices is disclosed. The MTJ has a composite AP1 pinned layer made of a lower amorphous Co60Fe20B20 layer and an upper crystalline Co75Fe25 layer to... Agent: Stephen B. Ackerman

20080217711 - Vertical spin transistor and method of manufacturing the same: A vertical spin transistor according to an embodiment of the present invention includes: a first source/drain layer including a layer formed of magnetic material; a protruding structure including, a channel layer formed on the first source/drain layer and including a layer formed of semiconductor, and a second source/drain layer formed... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080217712 - Apparatus and method for forming optical black pixels with uniformly low dark current: An apparatus and method for forming optical black pixels having uniformly low dark current. Optical Black opacity is increased without having to increase Ti/TiN layer thickness. A hybrid approach is utilized combining a Ti/TiN OB layer in conjunction with in-pixel metal stubs that further occlude the focal radius of each... Agent: Reed Smith, LLP

20080217713 - Two-dimensional semiconductor detector having mechanically and electrically joined substrates: The present invention relates to an industrial or medical radiation detector and a radiation imaging device equipped with the same. More specifically, the present invention relates to a technology for improving the detection properties and production efficiency for radiation detectors. The invention in claim 1 includes: a conductive support substrate;... Agent: Darby & Darby P.c.

20080217714 - Semiconductor device having tiles for dual-trench integration and method therefor: A method for forming a semiconductor device includes providing a semiconductor substrate having a first region and a second region. The first region has one or more first elements and the second region has one or more second elements. The first elements are different from the second elements. A tile... Agent: Freescale Semiconductor, Inc. Law Department

20080217715 - Wafer level package using silicon via contacts for cmos image sensor and method of fabricating the same: The present invention relates to a wafer level package of a CMOS image sensor using silicon via contacts and a method of manufacturing the same. A wafer level package of a CMOS image sensor includes: a wafer where image sensor elements including a plurality of electrode pads are formed; a... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080217717 - Cte matched multiplexor: e

20080217716 - Imaging apparatus, method, and system having reduced dark current: An imaging method, apparatus, and system having an image sensor having a p-type substrate to getter metallics and other contaminants, an n-type epitaxial layer arranged on the p-type substrate to reduce dark current, cross-talk, and blooming, and a p-type epitaxial layer arranged on the n-type epitaxial layer.... Agent: Dickstein Shapiro LLP

20080217718 - Method, apparatus, and system to reduce ground resistance in a pixel array: Methods, devices, and systems for an image sensor device are disclosed. An image sensor device comprises an array of image pixels wherein each pixel is configured for sensing light incident on the pixel. An image sensor device may further comprise a ground contact shared between at least two image pixels... Agent: Trask Britt, P.c./ Micron Technology

20080217720 - Dual isolation for image sensors: Methods, methods of making, devices, and systems for image sensors that include isolation regions are disclosed. A semiconductor imager includes a pixel array and peripheral circuitry arranged on at least one side of the pixel array. Array devices are formed as part of the pixel array and periphery devices are... Agent: Trask Britt, P.c./ Micron Technology

20080217719 - Method for reducing crosstalk in image sensors using implant technology: The present disclosure provides an image sensor semiconductor device. A semiconductor substrate having a first-type conductivity is provided. A plurality of sensor elements is formed in the semiconductor substrate. An isolation feature is formed between the plurality of sensor elements. An ion implantation process is performed to form a doped... Agent: Haynes And Boone, LLP

20080217721 - High efficiency rectifier: A high-efficiency power semiconductor rectifier device (10) comprising a δP++ layer (12), a P-body (14), an N-drift region (16), an N+ substrate (18), an anode (20), and a cathode (22). The method of fabricating the device (10) comprises the steps of depositing the N-drift region (16) on the N+ substrate... Agent: Spencer, Fane, Britt & Browne

20080217722 - Image sensor and method for manufacturing the same: Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a substrate provided with a transistor circuit, first and second interconnections separated from each other on the substrate, a first conductive-type conductive layer formed at side surfaces of the first interconnection, a second conductive-type... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080217723 - Backside illuminated cmos image sensor with pinned photodiode: A backside illuminated CMOS image sensor having an silicon layer with a front side and a backside, the silicon layer liberates charge when illuminated from the backside with light, an active pixel circuitry located on the front side of the semiconductor layer, a pinned photodiode adjacent to the active pixel... Agent: Snell & Wilmer LLP (oc)

20080217724 - Backside illuminated solid-state imaging device: A backside illuminated solid-state imaging device is provided and includes: a p-type semiconductor substrate; an imaging region that receives a subject light through a back side of the p-type semiconductor substrate to accumulate a signal corresponding to an amount of the received light; a signal reading element disposed in a... Agent: Birch Stewart Kolasch & Birch

20080217725 - Schottky diode structure with multi-portioned guard ring and method of manufacture: In one embodiment, a semiconductor structure comprises a multi-portioned guard ring that includes a first portion and a second portion formed in a region of semiconductor material. A conductive contact layer forms a first Schottky barrier with the region of semiconductor material. The conductive contact layer overlaps the second portion... Agent: Mr. Jerry Chruma Semiconductor Components Industries, L.l.c.

20080217726 - Integrated circuit system employing dipole multiple exposure: An integrated circuit system that includes: providing a first mask including a first feature; exposing the first mask to a radiation source to form an image of the first feature on a photoresist material that is larger than a structure to be formed, the photoresist material being formed over a... Agent: Law Offices Of Mikio Ishimaru

20080217727 - Radio frequency isolation for soi transistors: According to an exemplary embodiment, a structure includes at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, where the buried oxide layer overlies a bulk substrate. The structure further includes an electrically charged field control ring situated over the buried oxide layer and surrounding the at least... Agent: Farjami & Farjami LLP

20080217728 - Fusion bonding process and structure for fabricating silicon-on-insulator (soi) semiconductor devices: A method of fabricating a semiconductor-on-insulator device including: providing a first semiconductor wafer having an about 200 angstrom thick oxide layer thereover; etching the first semiconductor wafer to raise a pattern therein; doping the raised pattern of the first semiconductor wafer through the about 200 angstrom thick oxide layer; providing... Agent: The Plevy Law Firm

20080217729 - Isolation structures for integrated circuit devices: An isolated CMOS pair of transistors formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of... Agent: Patentability Associates

20080217731 - interconnect structure with dielectric air gaps: An interconnect structure with improved performance and capacitance by providing air gaps inside the dielectric layer by use of a multi-phase photoresist material. The interconnect features are embedded in a dielectric layer having a columnar air gap structure in a portion of the dielectric layer surrounding the interconnect features. The... Agent: International Business Machines Corporation Dept. 18g

20080217730 - Methods of forming gas dielectric and related structure: Methods of forming a gas dielectric and a related structure are disclosed. In one embodiment, the method includes providing a wiring level including at least one conductive portion within a sacrificial dielectric; forming a nanofiber layer over the wiring level; vaporizing the sacrificial dielectric by heating; evacuating the vaporized sacrificial... Agent: Hoffman Warnick Llc

20080217732 - Carbon memory: An integrated circuit including a memory cell and methods of manufacturing the integrated circuit are described. The memory cell includes a resistive memory element including a top contact, a bottom contact, and a carbon storage layer disposed between the top contact and the bottom contact. The memory cell operates at... Agent: Slater & Matsil LLP

20080217733 - Electrical fuse structure for higher post-programming resistance: The present invention provides an electrical fuse structure for achieving a post-programming resistance distribution with higher resistance values and to enhance the reliability of electrical fuse programming. A partly doped electrical fuse structure with undoped semiconductor material in the cathode combined with P-doped semiconductor material in the fuselink and anode... Agent: Scully, Scott, Murphy & Presser, P.c.

20080217735 - Metal e-fuse structure design: An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metal fuse in the dielectric layer; a dummy pattern adjacent the metal fuse; and a metal line in the dielectric layer, wherein a thickness of the metal fuse... Agent: Slater & Matsil, L.l.p.

20080217734 - Multi-level electrical fuse using one programming device: A multi-level electrical fuse system comprises at least one fuse box having at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.... Agent: Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080217736 - Electrical antifuse, method of manufacture and method of programming: An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance.... Agent: Whitham, Curtis & Christofferson, P.c.

20080217737 - Semiconductor device and method of manufacturing the same: A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over... Agent: Young & Thompson

20080217738 - Semiconductor device and method of manufacturing the same: s

20080217739 - Semiconductor packaging substrate structure with capacitor embedded therein: The present invention relates to a semiconductor packaging substrate structure with a capacitor embedded therein, which includes an inner circuit board, a patterned buffer layer, a high dielectric material layer, and a patterned metal layer. The buffer layer is disposed on at least one surface of the inner circuit board... Agent: Bacon & Thomas, Pllc

20080217740 - Semiconductor device and method of manufacturing the same: An object of the invention is to provide a resistor element whose contact area is self-alignedly formed to reduce the contact area size and contact resistance variation and which can be formed finely and with high precision at low cost. A thin metal film is deposited on a substrate surface... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080217741 - Silicide-interface polysilicon resistor: A silicide-interface polysilicon resistor is disclosed. The silicide-interface polysilicon resistor includes a substrate, an oxide layer located on top of the substrate, and a polysilicon layer located on top of the oxide layer. The polysilicon layer includes multiple semiconductor junctions. The silicide-interface polysilicon resistor also includes a layer of silicide... Agent: Dillon & Yudell LLP

20080217742 - Tailored bipolar transistor doping profile for improved reliability: Bipolar transistor device structures that improve bipolar device reliability with little or no negative impact on device performance. In one embodiment, the bipolar device has a collector of first conductivity type material formed in a substrate, a base of a second conductivity type material including an extrinsic base layer and... Agent: Scully, Scott, Murphy & Presser, P.c.

20080217743 - Method of manufacturing semiconductor device and semiconductor device: According to a method of manufacturing a semiconductor device, a short-circuit wiring is formed in a region on a wafer including a dicing region, and electrode pads for input and output signals of a plurality of devices disposed in a semiconductor device forming region are electrically short-circuited by the short-circuit... Agent: Scully Scott Murphy & Presser, Pc

20080217744 - Semiconductor device and method of manufacturing the same: A semiconductor device includes: a semiconductor chip including: a first main face having an edge portion, a second main face locating the opposite side to the first main face, a crystalline defect region present within a region including at least the edge portion being adjacent to the first main face,... Agent: Foley And Lardner LLP Suite 500

20080217745 - Nitride semiconductor wafer: A nitride semiconductor substrate having properties preferable for the manufacture of various nitride semiconductor devices is made available, by specifying or controlling the local variation in the off-axis angle of the principal surface of the nitride semiconductor substrate. The substrate, being misoriented, is manufactured to have an off-axis angle distribution... Agent: Judge Patent Associates

20080217746 - Insulating film: An insulating film for semiconductor devices is obtained by curing, on a substrate, a high molecular compound obtained by polymerizing a cage-type silsesquioxane compound having two or more unsaturated groups as substituents and having a cyclic siloxane structure, wherein the structure of the cage-type silsesquioxane compound is not broken by... Agent: Sughrue-265550

20080217747 - Introduction of metal impurity to change workfunction of conductive electrodes: Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice... Agent: Scully, Scott, Murphy & Presser, P.c.

20080217748 - Low cost and low coefficient of thermal expansion packaging structures and processes: A method for producing a chip carrier, the method includes selecting at least one core with a low coefficient of thermal expansion; selecting at least one build-up layer wherein each build-up layer includes a dielectric material and circuitry; and connecting selected cores and selected build-up layers together in a pre-determined... Agent: Cantor Colburn LLP-ibm Yorktown

20080217749 - Low capacitance transient voltage suppressor: A transient voltage suppressor includes a reverse bias transient voltage suppressor PN diode connected in series with a forward biased PIN diode, the series circuit formed by the PN diode and the PIN diode is connected between first and second terminals and in parallel with a reverse biased PIN diode.... Agent: William C. Cahill

20080217750 - Semiconductor device: A plurality of inner leads 14 are provided around a die pad 13. A grounded GND lead 16 is provided in a region between the die pad 13 and the plurality of inner leads 14. A semiconductor chip 17 and the plurality of inner leads 14 are connected to each... Agent: Mcdermott Will & Emery LLP

20080217751 - Substrate for mounting semiconductor element and method of manufacturing the same: The present invention provides a semiconductor element mounting substrate 101 including: a base substrate 1 having a region 2 for mounting a semiconductor element 11, the region 2 being set on the major surface of the base substrate 1; a plurality of wiring patterns 3 formed on the base substrate... Agent: Steptoe & Johnson LLP

20080217752 - Functional device package: A packaging structure for hermitically sealing a functional device by solder connection at a wafer level in which a first Si substrate having a concave portion metallized on its internal surface and a second Si substrate metallized at a position opposed to said concave portion are used, the metallization applied... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080217754 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a semiconductor chip 5 having a first surface 5a on which a first pole 5a1 of a semiconductor element is arranged and a second surface 5b on which a second pole 5b1 is arranged and which is opposed to the first surface 5a, a first conductive... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080217753 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor element 1, a thermal conductor 91 located opposite a major surface of the semiconductor element 1, and a mold resin member 6 molding the semiconductor element 1 and at least a part of the thermal conductor 91, wherein at least a part of a... Agent: Steptoe & Johnson LLP

20080217756 - Power semiconductor arrangement and method for producing it: Power semiconductor arrangement and method for producing it. One embodiment provides a power semiconductor module. The power semiconductor module has a baseplate with an electrically conductive structure, a housing and a connection element. The connection element is led out from the housing generally perpendicular to the baseplate and is fixed... Agent: Dicke, Billig & Czaja

20080217757 - Power semiconductor module: A power semiconductor module is disclosed, including a plate-type substrate fitted with at least one component, and a base plate provided for dissipating heat from the component via the substrate. In at least one embodiment, a supporting apparatus, which keeps the substrate in thermal contact with the base plate, has... Agent: Harness, Dickey & Pierce, P.L.C

20080217755 - Systems and methods for providing voltage compensation in an integrated circuit chip using a divided power plane: Systems and methods for providing power to on-chip components of an integrated circuit with improved uniformity through the use of a split power plane. One embodiment comprises a system having an integrated circuit chip, a power distribution network coupled to the integrated circuit chip, and a power plane coupled to... Agent: Law Offices Of Mark L. Berrier

20080217758 - Package substrate strip, metal surface treatment method thereof and chip package structure: A package substrate strip having a reserved plating bar and a metal surface treatment method thereof are provided. The metal surface treatment method forms a conductive layer connecting the reserved plating bar and bonding pads of the package substrate stripe and further forms an isolating layer covering the conductive layer.... Agent: Madson & Austin

20080217759 - Chip package substrate and structure thereof: A chip package substrate includes multiple pairs of connection pads. Both pads of a connection pad pair are separated from each other with a distance, which is smaller than the side length of a chip. An insulation layer is configured on the connection pads but exposes a portion of the... Agent: Abelman, Frayne & Schwab

20080217760 - Semiconductor device and method of manufacturing same: A semiconductor device includes an outer resin case having a peripheral wall and terminal mounting holes formed in the peripheral wall, and a layer assembly provided in the outer resin case. The layer assembly includes a semiconductor chip, an insulating circuit board on which the semiconductor chip is mounted, and... Agent: Kanesaka Berner And Partners LLP

20080217762 - Chip carrier structure having semiconductor chip embedded therein and metal layer formed thereon: The present invention provides a chip carrier structure having a semiconductor chip embedded therein and a protective metal layer formed thereon and a fabrication method thereof. The chip carrier structure includes a chip-embedded carrier structure, and a metal layer formed by electroplating on the bottom surface and side surfaces of... Agent: Schmeiser Olsen & Watts

20080217761 - Structure of semiconductor device package and method of the same: The present invention provides a semiconductor device package comprising a substrate with at lease a pre-formed die receiving cavity formed and terminal contact metal pads formed within an upper surface of the substrate. At lease a first die is disposed within the die receiving cavity. A first dielectric layer is... Agent: Birch Stewart Kolasch & Birch

20080217763 - Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces: Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces are disclosed. In one embodiment, a microelectronic assembly comprises a support member having a first side and a projection extending away from the first side. The assembly also includes a plurality of conductive traces at the first side of... Agent: Perkins Coie LLP Patent-sea

20080217764 - Piezoelectric cooling of a semiconductor package: In one embodiment, the present invention includes a semiconductor package having a plurality of fan blades embedded within a first surface of the package, where a first group of the fan blades extend from a first side of the package and a second group of the fan blades extend from... Agent: Trop Pruner & Hu, Pc

20080217766 - Acoustic transducer module: A module (100, 200, 300, 400, 500, 600, 900) may be electrically connected to a PCB (18, 918) residing in a device (14) or may be joined to the device (14) to form a portion of the housing (16, 916) of the device (14). The module may include a housing... Agent: Marshall, Gerstein & Borun LLP

20080217765 - Semiconductor component and method of manufacture: A semiconductor component comprising two stacked semiconductor dice and a method of manufacture. A leadframe having an active area that includes leadframe leads and a cavity is mounted to a support material such as an adhesive tape. A packaged semiconductor die that includes a first semiconductor die mounted to a... Agent: Jerry Chruma Semiconductor Components Industries, L.l.c.

20080217771 - Metallic electrode forming method and semiconductor device having metallic electrode: A metallic electrode forming method includes: forming a bed electrode on a substrate; forming a protective film with an opening on the bed electrode to expose the bed electrode from the opening; forming a metallic film covering the protective film and the opening; mounting the substrate on an adsorption stage,... Agent: Posz Law Group, Plc

20080217770 - Mounting configuration of electronic component: An electronic component mounting configuration in which an electronic component chip having a plurality of protrusion-shaped electrodes distributed on its entire mounting surface is mounted through protrusion-shaped electrodes on a printed circuit board is provided which is capable of improving reliability of an electronic component by relieving thermal stress. The... Agent: Dickstein Shapiro LLP

20080217772 - Semiconductor device manufacturing method and semiconductor device: The present invention provides a method for forming a semiconductor device, which comprises the steps of preparing a semiconductor wafer including an electrode pad, an insulating film formed with a through hole and a bedding metal layer which are formed in a semiconductor substrate, forming a first resist mask which... Agent: Rabin & Berdo, Pc

20080217769 - Semiconductor module, method of manufacturing semiconductor module, and mobile device: The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation... Agent: Fish & Richardson P.c.

20080217767 - Stacked-chip semiconductor device: A chip stacking semiconductor device which can be used without mounting a converter circuit and without altering the circuitry of the semiconductor chips even when semiconductor chips stacked in a plurality of stages are connected electrically. Through wiring (5) provided in the semiconductor chip (4) is supplied with power and... Agent: Hayes Soloway P.c.

20080217768 - System and method for increased stand-off height in stud bumping process: System and method for creating single stud bumps having an increased stand-off height. A preferred embodiment comprises a capillary for use in creating stud bumps in a flip chip assembly, comprising a hole section adapted to pass a wire, a chamfer section providing a transition from the hole section to... Agent: Texas Instruments Incorporated

20080217773 - Removal of integrated circuits from packages: Packaging is substantially entirely removed from an integrated circuit die. The method allows the batch processing of several integrated circuit dies, such that packaging is removed from each die approximately simultaneously.... Agent: Goodwin Procter LLP Patent Administrator

20080217774 - Semiconductor device: When a BGA package device is mounted to another substrate and tested for packaging strength, solder balls (8) frequently come detached in places where the edges of a semiconductor chip (1) align with the centers of the solder balls (8) on a BGA substrate (9) in the perpendicular direction of... Agent: Mcginn Intellectual Property Law Group, Pllc

20080217777 - Embedded barrier for dielectric encapsulation: A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs a combination of an embedded film, etchback, using either selective CoWP or a conformal cap such as a SiCNH film, to protect the... Agent: International Business Machines Corporation Dept. 18g

20080217775 - Method of forming contact plugs for eliminating tungsten seam issue: A method of forming a contact plug of an eDRAM device includes the following steps: forming a tungsten layer with tungsten seam on a dielectric layer to fill a contact hole; removing the tungsten layer from the top surface of the dielectric layer, recessing the tungsten layer in the contact... Agent: Birch Stewart Kolasch & Birch

20080217776 - Process for manufacturing integrated circuits formed on a semiconductor substrate and comprising tungsten layers: An embodiment is described for manufacturing integrated circuits formed on a semiconductor substrate, which embodiment comprises forming a cobalt suicide layer on said semiconductor substrate, forming a layer comprising tungsten on said silicide layer, said cobalt suicide layer forming a barrier against the migration of the silicon atoms of said... Agent: Graybeal, Jackson, Haley LLP

20080217778 - Method to create flexible connections for integrated circuits: A method of producing flexible interconnections for integrated circuits, and, in particular, the forming of flexible or compliant interconnections preferably by a laser-assisted chemical vapor deposition process in semiconductor or glass substrate-based carriers which are employed for mounting and packaging multiple integrated circuit chips and selectively, other devices in the... Agent: Scully, Scott, Murphy & Presser, P.c.

20080217780 - Eliminating metal-rich silicides using an amorphous ni alloy silicide structure: The present invention provides a method for producing thin nickel (Ni) monosilicide or NiSi films (having a thickness on the order of about 30 nm or less), as contacts in CMOS devices wherein an amorphous Ni alloy silicide layer is formed during annealing which eliminates (i.e., completely by-passing) the formation... Agent: Scully, Scott, Murphy & Presser, P.c.

20080217781 - Eliminating metal-rich silicides using an amorphous ni alloy silicide structure: The present invention provides a method for producing thin nickel (Ni) monosilicide or NiSi films (having a thickness on the order of about 30 nm or less), as contacts in CMOS devices wherein an amorphous Ni alloy silicide layer is formed during annealing which eliminates (i.e., completely by-passing) the formation... Agent: Scully, Scott, Murphy & Presser, P.c.

20080217779 - Semiconductor structure and the forming method thereof: The present invention provides a semiconductor structure and the forming method thereof. The structure includes a substrate having a plurality of stacks; a conformal layer on the substrate and a portion of sidewalls of the plurality of the stacks; and a plurality of plugs between the plurality of stacks. In... Agent: Ingrassia Fisher & Lorenz, P.c.

20080217782 - Method for preparing 2-dimensional semiconductor devices for integration in a third dimension: A method which is intended to facilitate and/or simplify the process of fabricating interlayer vias by selective modification of the FEOL film stack on a transfer wafer is provided. Specifically, the present invention provides a method in which two dimensional devices are prepared for subsequent integration in a third dimension... Agent: Scully, Scott, Murphy & Presser, P.c.

20080217783 - Semiconductor device: A semiconductor device is provided having an insulating layer structure with a low dielectric constant and excellent barrier properties against copper. This semiconductor device has a copper wiring layer and includes at least one layered structure having a copper wiring line, an amorphous carbon film with a density of 2.4... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080217784 - Substrate with feedthrough and method for producing the same: A substrate has at least one feedthrough with at least one channel from a first main surface of the substrate to a second main surface of the substrate. The at least one channel is closed off with a first material. The at least one closed-off channel is filled with an... Agent: Schwegman, Lundberg & Woessner / Infineon

20080217785 - Semiconductor device with grounding structure: Conductions and vias between different, stacked metallic layers of a semiconductor device may be mechanically damaged by mechanical strain. According to an exemplary embodiment of the present invention, this mechanical strain may be transferred through the layer structure to the substrate by a grid of grounding structures and isolation and... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080217787 - Micro-electromechanical device and manufacturing method thereof: A micro-electromechanical device includes a substrate, a first patterned conductive layer, a second patterned conductive layer and a first patterned blocking layer. The first patterned conductive layer is disposed on the substrate. The second patterned conductive layer is disposed on the first patterned conductive layer. The first patterned blocking layer... Agent: Birch Stewart Kolasch & Birch

20080217786 - Semiconductor device and method of manufacturing semiconductor device: m

20080217788 - Method of fabricating self-aligned contact: A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region thereon. Next, a lower opening corresponding to the contact region is formed in the first dielectric layer. Thereafter, a second dielectric layer is formed on the first dielectric... Agent: J C Patents, Inc.

20080217791 - Semiconductor device: In a semiconductor device of the present invention, an electrode pad is formed on a surface of a semiconductor substrate, and in the electrode pad, two different areas: a connection area of through wiring electrically connected to a through wiring; and a pad area for inspection that keeps away from... Agent: Scully Scott Murphy & Presser, Pc

20080217790 - Semiconductor device and manufacturing method thereof: A semiconductor device having a vertical conductive structure which includes a first inter-layer insulating film; a second inter-layer insulating film formed on the first inter-layer insulating film; a lower-layer contact plug which passes through the first inter-layer insulating film and the second inter-layer insulating film, wherein in the lower-layer contact... Agent: Sughrue Mion, Pllc

20080217789 - Semiconductor device and method of forming metal line of semiconductor device: A semiconductor device and a method of forming a metal line of a semiconductor device includes a first insulating layer formed over a semiconductor substrate an etch-stop layer formed over the first insulating layer, contact holes formed by etching the etch-stop layer and the first insulating layer, Contact plugs formed... Agent: Lowe Hauptman Ham & Berner, LLP

20080217793 - Method and device including reworkable alpha particle barrier and corrosion barrier: A method and device comprising an easily reworkable alpha particle barrier is provided. The easily reworkable alpha particle barrier is applied in the space between the surface of the chip and the surface of the substrate, and reduces soft error rate (SER). Further, the easily reworkable alpha particle barrier material... Agent: Greenblum & Bernstein, P.L.C

20080217792 - Semiconductor device and method of manufacturing the same: A manufacturing method of a semiconductor device includes: forming a columnar electrode on a semiconductor wafer; flip-chip bonding a second semiconductor chip onto the semiconductor wafer; forming a molding portion on the semiconductor wafer, the molding portion covering and molding the columnar electrode and the second semiconductor chip; grinding or... Agent: Ingrassia Fisher & Lorenz, P.c.

20080217794 - Overlay measurement target: In an overlay metrology method used during semiconductor device fabrication, an overlay alignment mark facilitates alignment and/or measurement of alignment error of two layers on a semiconductor wafer structure, or different exposures on the same layer. A target is small enough to be positioned within the active area of a... Agent: Silicon Valley Patent Group LLP

20080210921 - Silver selenide film stoichiometry and morphology control in sputter deposition: A method of sputter depositing silver selenide and controlling the stoichiometry and nodular defect formations of a sputter deposited silver-selenide film. The method includes depositing silver-selenide using a sputter deposition process at a pressure of about 0.3 mTorr to about 10 mTorr. In accordance with one aspect of the invention,... Agent: Dickstein Shapiro LLP

20080210922 - Storage nodes and methods of manufacturing and operating the same, phase change memory devices and methods of manufacturing and operating the same: In various embodiments, the present disclosure may provide a storage node. In various implementations, the storage node may include a bottom electrode having a non-planar bottom surface that conforms with and is connected to a non-planar top surface of a diode electrode of a memory device. The storage node may... Agent: Harness, Dickey & Pierce, P.L.C

20080210924 - Phase change memory devices including phase change layer formed by selective growth methods and methods of manufacturing the same: A phase change memory device including a phase change layer includes a storage node and a switching device. The switching device is connected to the storage node. The storage node includes a phase change layer selectively grown on a lower electrode. In a method of manufacturing a phase change memory... Agent: Harness, Dickey & Pierce, P.L.C

20080210923 - Semiconductor device and method of manufacturing the same: In a semiconductor device including a heater electrode formed in a contact hole formed in an interlayer insulation film to expose a lower electrode, the heater electrode includes at least three heater electrode layers which are successively laminated and successively increased in specific resistivity in a direction from the lower... Agent: Young & Thompson

20080210926 - Three-dimensional phase-change memory array: A three-dimensional phase-change memory array. In one embodiment of the invention, the memory array includes a first plurality of diodes, a second plurality of diodes disposed above the first plurality of diodes, a first plurality phase-change memory elements disposed above the first and second plurality of diodes and a second... Agent: Ovonyx, Inc

20080210925 - Three-terminal cascade switch for controlling static power consumption in integrated circuits: A switching circuit configured for controlling static power consumption in integrated circuits includes a plurality of three-terminal, phase change material (PCM) switching devices connected between a voltage supply terminal and a corresponding sub-block of integrated circuit logic. Each of the PCM switching devices further includes a PCM disposed in contact... Agent: Cantor Colburn LLP-ibm Yorktown

20080210927 - Buffer architecture formed on a semiconductor wafer: In one embodiment, the present invention includes an apparatus for forming a transistor that includes a silicon (Si) substrate, a dislocation filtering buffer formed over the Si substrate having a first buffer layer including gallium arsenide (GaAs) nucleation and buffer layers and a second buffer layer including a graded indium... Agent: Trop Pruner & Hu, PC

20080210932 - Memory element, memory device, and semiconductor device: On object of the invention is to provide a non-volatile memory device, in which data can be added to the memory device after a manufacturing process and forgery and the like by rewriting can be prevented, and a semiconductor device including the memory device. Another object of the invention is... Agent: Eric Robinson

20080210930 - Metal complex, light-emitting device, and image display apparatus: To provide a novel metal complex suitable as a compound for an organic EL device. A metal complex including a partial structure represented by the following general formula (1): in which R in the general formula (1) has a partial structure represented by the following general formula (2) or (3).... Agent: Fitzpatrick Cella Harper & Scinto

20080210931 - Methods for forming an undercut region and electronic devices incorporating the same: An electronic device having a substrate structure having an undercut region is provided and further included is a method for forming an undercut region of a substrate structure. The method includes forming a patterned protective layer over a first electrode. The method also includes forming the substrate structure over the... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20080210929 - Organic thin film transistor: An organic thin film transistor is formed using an organic semiconducting polymer that contains electrically conductive micro scale or nanoscale metallic plates, particulates, or rods dispersed in the polymer at a concentration less than the percolation threshold to form a semiconducting matrix. The electrically conductive particulates are dispersed to provide... Agent: Leveque Intellectual Property Law, P.C.

20080210928 - Semiconductor device: The present invention provides a semiconductor device which has a storage element having a simple structure in which an organic compound layer is sandwiched between a pair of conductive layers and a manufacturing method of such a semiconductor device. With this characteristic, a semiconductor device having a storage circuit which... Agent: Eric Robinson

20080210933 - Substituted anthracenes and electronic devices containing the substituted anthracenes: Substituted anthracene compounds and electronic devices containing the substituted anthracene compounds are provided.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20080210934 - Semiconductor device using titanium dioxide as active layer and method for producing semiconductor device: Means for Solving the Problems: The semiconductor device 10 according to the present invention includes TiO2 as an active layer thereof. The semiconductor device 10 according to the present invention includes a gate electrode 20, a TiO2 layer 12 which functions as a semiconductor active layer and forming a channel,... Agent: Greenblum & Bernstein, P.L.C

20080210935 - Semiconductor wafer, semiconductor device, and semiconductor device manufacturing method: A semiconductor wafer includes a plurality of chip areas, a scribe line area, a bonding pad, a probing pad, and a pad connection wiring. The plurality of chip areas are configured to be arranged in a matrix form. The scribe line area is configured to separate the plurality of chip... Agent: Cooper & Dunham, LLP

20080210936 - Hetero-crystalline semiconductor device and method of making same: A hetero-crystalline semiconductor device and a method of making the same include a non-single crystalline semiconductor layer and a nanostructure layer that comprises a single crystalline semiconductor nanostructure integral to a crystallite of the non-single crystalline semiconductor layer.... Agent: Hewlett Packard Company

20080210937 - Hetero-crystalline structure and method of making same: A hetero-crystalline device structure and a method of making the same include a first layer and a nanostructure integral to a crystallite in the first layer. The first layer is a non-single crystalline material. The nanostructure is a single crystalline material. The nanostructure is grown on the first layer integral... Agent: Hewlett Packard Company

20080210938 - Semiconductor device: A semiconductor device with superior long-term reliability is disclosed that alleviates current concentration into a switch structure arranged at an outermost portion. The semiconductor device comprises hetero semiconductor regions formed of polycrystalline silicon having a band gap width different from that of a drift region and hetero-adjoined with the drift... Agent: Young & Basile, P.C.

20080210939 - Method for fabricating an image sensor device with reduced pixel cross-talk: A method of fabricating an image sensor device (5) transferring an intensity of radiation (1) into an electrical current (i-i, a2) depending on said intensity, comprising the following steps in a vacuum deposition device: Depositing onto a dielectric, insulating surface a matrix of electrically conducting pads (7a, 7b) as rear... Agent: Birch Stewart Kolasch & Birch

20080210942 - Array substrate for liquid crystal display device and method of fabricating the same: An array substrate for a liquid crystal display device includes a gate line on a substrate; a gate insulating layer on the gate line; a data line crossing the gate line; a gate electrode connected to the gate line; an active layer on the gate insulating layer and overlapping the... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20080210941 - Dispaly device: The present invention provides a display device which can obviate the occurrence of a leak current in a thin film transistor. In a display device including a substrate, and gate signal lines, an insulation film, semiconductor layers and conductor layers which are sequentially stacked on the substrate, the conductor layer... Agent: Reed Smith LLP

20080210944 - Ejecting method and ejecting apparatus: In an ink jet apparatus for manufacturing a color filter 1, ink jet heads 22 having a plurality of nozzle 27 are disposed in a linear manner. Filter element member is ejected to a motherboard 12 from a plurality of nozzles 27 four times so as to form the filter... Agent: Oliff & Berridge, PLC

20080210943 - Thin film transistor array panel and manufacturing method thereof: A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having... Agent: Macpherson Kwok Chen & Heid LLP

20080210940 - Thin film transistor substrate and display device therefor: The invention relates to a thin film transistor substrate and a display device including the same, and provides a thin film transistor substrate and a display device including the same, which can prevent damage of elements due to static electricity by forming, in each unit pixel region where a pair... Agent: Macpherson Kwok Chen & Heid LLP

20080210945 - Thin film transistor, manufacturing method thereof, and semiconductor device: By a laser crystallization method, a crystalline semiconductor film in which grain boundaries are all in one direction is provided as well as a manufacturing method thereof. In crystallizing a semiconductor film formed over a substrate with linear laser light, a phase-shift mask in which trenches are formed in a... Agent: Eric Robinson

20080210946 - Image detector and radiation detecting system: The invention provides an image detector capable of improving the quality of detected images by reducing electronic noise, the image detector comprising, a plurality of scan lines disposed in parallel, a plurality of data lines provided so as to cross with the scan lines, thin film transistors connected with the... Agent: Sughrue Mion, PLLC

20080210947 - Solid-state imaging device: A solid-state imaging device having an arrangement in which well contact is achieved for each pixel is provided. In the solid-state imaging device, a well contact part is formed in an activation region of a photoelectric conversion portion. The well contact part fixes a well in which the photoelectric conversion... Agent: Robert J. Depke Lewis T. Steadman

20080210948 - High-heat-resistive semiconductor device: The outer surface of a wide-gap semiconductor device is coated with a synthetic polymer compound containing one or more silicon-containing polymer having a bridged structure formed by a siloxane (Si—O—Si bond structure). The synthetic polymer compound may include, for example, a silicon-containing polymer which has one or more reactive groups... Agent: Crowell & Moring LLP Intellectual Property Group

20080210949 - Semiconductor substrate and semiconductor device using the same: A semiconductor substrate includes: an AlN layer provided on a silicon substrate; an AlGaN layer that is provided on the AlN layer and has an Al composition ratio of 0.3 to 0.6; and a GaN layer provided on the AlGaN layer.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080210950 - Diamond-like carbon electronic devices and methods of manufacture: Materials, devices, and methods for enhancing performance of electronic devices such as solar cells, fuels cells, LEDs, thermoelectric conversion devices, and other electronic devices are disclosed and described. A diamond-like carbon electronic device can include a conductive diamond-like carbon cathode having specified carbon, hydrogen and sp2 bonded carbon contents. In... Agent: Thorpe North & Western, LLP.

20080210951 - Method for fabricating high-quality semiconductor light-emitting devices on silicon substrates: One embodiment of the present invention provides a semiconductor light-emitting device which includes: (1) a silicon (Si) substrate; (2) a silver (Ag) transition layer which is formed on a surface of the Si substrate, wherein the Ag transition layer covers the Si substrate surface; and (3) an InGaAlN, ZnMgCdO, or... Agent: Park, Vaughan & Fleming LLP

20080210952 - Photo interrupter, method of manufacturing the same, and electronic equipment using the same: A photo interrupter has a lead frame assembly that has a lead frame having connector terminals for external connection, a light-emitting mold, a light-receiving mold, and a connector mold. The photo interrupter also has an outer case having a connection section. The connector terminals are adapted to be accommodated in... Agent: Birch Stewart Kolasch & Birch

20080210954 - Alternating current light emitting device: The present invention relates to a light emitting device in which light emitting cells of a first light emitting cell block are connected in parallel to light emitting cells of a second light emitting cell block corresponding thereto. A light emitting device of the present invention comprises a substrate, and... Agent: Marger Johnson & Mccollom, P.C.

20080210955 - Group iii-v semiconductor device and method for producing the same: An object of the invention is to prevent short circuit at a side surface of a semiconductor device in the method for producing semiconductor devices including a laser lift-off step. The production method of the invention includes forming, on a sapphire substrate, a group III nitride semiconductor layer containing a... Agent: Mcginn Intellectual Property Law Group, PLLC

20080210956 - Light emitting diode employing an array of nanorods and method of fabricating the same: Disclosed are a light emitting diode employing an array of nanorods and a method of fabricating the same. The light emitting diode comprises an array of semiconductor nanorods positioned on a substrate. An upper electrode layer is deposited on the array of the nanorods such that an empty space remains... Agent: H.c. Park & Associates, PLC

20080210953 - Luminaire with a plurality of light-emitting diodes in decentralized arrangement: A luminaire with a plurality of light-emitting diodes in a decentralized arrangement. To improve the light emission pattern issued by the luminaire, the emission region defined by the light guide emission ends is smaller than the arrangement region defined by the totality of the light-emitting diodes.... Agent: Marshall, Gerstein & Borun LLP

20080210957 - Light emitting diode, method for manufacturing light emitting diode, integrated light emitting diode, method for manufacturing integrated light emitting diode, light emitting diode backlight, light emitting diode illumination device, light emitting diode: Disclosed herein is a light emitting diode includes: a first semiconductor layer of a first conductivity type; an active layer on the first semiconductor layer; a second semiconductor layer of a second conductivity type on the active layer; a first electrode configured to be electrically coupled to the first semiconductor... Agent: Sonnenschein Nath & Rosenthal LLP

20080210958 - Semiconductor white light emitting device and method for manufacturing the same: A semiconductor white light emitting device including: a semiconductor light emitting element having green and blue light emitting layers containing In; and a phosphor capable of emitting red light.... Agent: Rabin & Berdo, PC

20080210959 - Light emitting apparatus: In order to provide light emitting devices which have simple constructions and thus can be fabricated easily, and can stably provide high light emission efficiencies for a long time period, a light emitting device includes an n-type nitride semiconductor layer at a first main surface side of a nitride semiconductor... Agent: Mcdermott Will & Emery LLP

20080210960 - Display device: In one embodiment, a display device includes: a first electrode; a hole transfer layer which is formed on the first electrode, the hole transfer layer comprising a first host used as a hole transfer material and a first dopant used as an electron accepting material; an emitting material layer which... Agent: Macpherson Kwok Chen & Heid LLP

20080210969 - Fabrication of semiconductor devices for light emission: A semiconductor device for light emission having a plurality of epitaxial layers with an n-type layer for light emission and a p-type layer for light reflection. The p-type layer has at least one seed layer for an outer layer of a conductive metal. The at least at least one seed... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080210962 - Illumination device: An illumination device is specified which comprises an optoelectronic component having a housing body and at least one semiconductor chip provided for generating radiation, and a separate optical element, which is provided for fixing at the optoelectronic component and has an optical axis, the optical element having a radiation exit... Agent: Fish & Richardson PC

20080210961 - Light emitting device: A light emitting device includes: a die-mounting base having a mounting surface; a light emitting diode mounted on the mounting surface of the die-mounting base and having a top surface facing in a normal direction normal to the mounting surface of the die-mounting base; a first wavelength-converting layer of a... Agent: Rosenberg, Klein & Lee

20080210966 - Light emitting device: A light emitting device is configured to prevent leakage of light but can be reduced in thickness as compared with conventional devices, and can effectively prevent degradation in luminous flux (luminous flux drop). The light emitting device can include a light emitting element, an optically transparent sealing resin having a... Agent: Cermak Kenealy & Vaidya, LLP

20080210967 - Light emitting diode and method for making the same: A light emitting diode includes: a first semiconductor layer; a second semiconductor layer formed on the first semiconductor layer; a light-converting pattern of a phosphor material formed on the second semiconductor layer; and a reflective layer of a metallic material formed on the second semiconductor layer and enclosing the light-converting... Agent: Christie, Parker & Hale, LLP

20080210963 - Light emitting diode package structure and method of making the same: A light emitting diode package structure has a silicon substrate, a plurality of cup-structures on the silicon substrate, a plurality of conductive patterns disposed on the silicon substrate, one of a plurality of light emitting diodes respectively disposed on each cup-structure and a plurality of wires electrically connected to the... Agent: North America Intellectual Property Corporation

20080210968 - Light-emitting diode: A light-emitting diode includes: a light-transmitting substrate; a light-emitting element mounted on the upper surface of the light-transmitting substrate; and a light-transmitting resin that seals the light-emitting element. The outer surface of the light-transmitting resin is covered with a reflecting layer formed from a silver or aluminum thin film. The... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080210965 - Light-emitting diode incorporation the packing nano particules with high refractive index: Light-emitting diode packages with very high light extraction efficiency are disclosed. The packages utilize the intrinsically optically transparent nano particles with high refractive index, by the correct way of homogeneous packing, or adding additional transparent substance in the interspaces among the nano particles furthermore, to form a nano light-extracting layer... Agent: Chuan-yu Hung

20080210964 - Optical semiconductor device and method for manufacturing optical semiconductor device: An optical semiconductor device includes: a base substrate which has a concave portion; a light-emitting element which is provided in the concave portion, and which emits light; a prevention member which is provided to the base substrate in a manner of covering a side surface of the concave portion, and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080210970 - Fabrication of conductive metal layer on semiconductor devices: A method for fabrication of a light emitting device on a substrate, the light emitting device having a wafer with multiple epitaxial layers and an ohmic contact layer on the epitaxial layers remote from the substrate. The method includes the steps: (a) applying to the ohmic contact layer a seed... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080210971 - Nickel tin bonding system with barrier layer for semiconductor wafers and devices: A light emitting diode structure is disclosed that includes a light emitting active portion formed of epitaxial layers and carrier substrate supporting the active portion. A bonding metal system that predominates in nickel and tin joins the active portion to the carrier substrate. At least one titanium adhesion layer is... Agent: Summa, Allan & Additon, P.A.

20080210972 - Nitride-based semiconductor light emitting diode: Provided is a nitride-based semiconductor LED including a substrate; a first conductive-type nitride semiconductor layer formed on the substrate; an active layer formed on a predetermined region of the first conductive-type nitride semiconductor layer; a second conductive-type nitride semiconductor layer formed on the active layer; a transparent electrode formed on... Agent: Mcdermott Will & Emery LLP

20080210973 - Zinc-oxide-based semiconductor light-emitting device and method of fabricating the same: The invention discloses a zinc-oxide-based semiconductor light-emitting device and the fabrication thereof The method according to the invention, first, is to prepare a substrate. Next, by an atomic-layer-deposition-based process, a ZnO-based multi-layer structure is formed on or over the substrate where the ZnO-based multi-layer structure includes a light-emitting region.... Agent: Morris Manning Martin LLP

20080210974 - High voltage ldmos: A power semiconductor device having high avalanche capability comprises an N+ doped substrate and, in sequence, N− doped, P− doped, and P+ doped semiconductor layers, the P− and P+ doped layers having a combined thickness of about 5 μm to about 12 μm. Recombination centers comprising noble metal impurities are... Agent: Hiscock & Barclay, LLP

20080210975 - Method of fabricating heteroepitaxial microstructures: An efficient method of fabricating a high-quality heteroepitaxial microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a heteroepitaxial microstructure on the detached surface of the carrier substrate by depositing an epitaxial... Agent: Winston & Strawn LLP Patent Department

20080210976 - Semiconductor device having an implanted precipitate region and a method of manufacture therefor: The present invention provides a semiconductor device, a method of manufacture therefor and an integrated circuit including the same. The semiconductor device 100, among other things, may include a substrate 110 having a lattice structure and having an implanted precipitate region 120 located within the lattice structure. Additionally, the semiconductor... Agent: Texas Instruments Incorporated

20080210977 - Semiconductor device having a support substrate partially having metal part extending across its thickness: A semiconductor device includes a support substrate and a semiconductor layer formed on the underlying substrate. The support substrate has its metal part formed by plating and extending across its entire thickness, whilst it has the other region made of semiconductor part. In particular, the region of the support substrate... Agent: Rabin & Berdo, PC

20080210978 - Semiconductor device: A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality of drain contacts formed on the drain region to... Agent: Mcdermott Will & Emery LLP

20080210979 - Semiconductor integrated circuit and method for designing the same: A semiconductor integrated circuit, including: a semiconductor chip; an internal integrated circuit area formed at a center side of the semiconductor chip; and an I/O area formed at a peripheral side of the semiconductor chip except where the internal integrated circuit area exists, the I/O area having a first power... Agent: Harness, Dickey & Pierce, P.L.C

20080210980 - Isolated cmos transistors: Isolated CMOS transistors formed in a P-type semiconductor substrate include an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which... Agent: Patentability Associates

20080210981 - Integrated circuit having gates and active regions forming a regular grating: A semiconductor device includes a plurality of repeatable circuit cells connectable to one or more conductors providing at least electrical connection to the circuit cells and/or electrical connection between one or more circuit elements in the cells. Each of the circuit cells are configured having gates and active regions forming... Agent: Ryan, Mason & Lewis, LLP

20080210982 - Image sensor and method for manufacturing the same: An image sensor and manufacturing process thereof are provided. An image sensor according to an embodiment comprises a first wafer formed with a photodiode cell without a microlens and a second wafer formed with a circuit part including transistor and a capacitor. The first wafer is stacked on the second... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080210983 - Solid-state imaging device: A solid-state imaging device including: a plurality of photodiode parts (1); a plurality of vertical charge transfer parts (2) each of which reads out a signal charge and transfers the signal charge in a vertical direction; and a plurality of shade films (5) that have conductivity, which supplies a transfer... Agent: Hamre, Schumann, Mueller & Larson P.C.

20080210984 - Solid-state image capturing device and electronic information device: A device separation insulating film and a device separation semiconductor layer are provided for a device separation section for separating adjacent devices from each other, end portions of the device separation insulating film and end portions of the device separation semiconductor layer are provided to overlap each other in order... Agent: Edwards Angell Palmer & Dodge LLP

20080210985 - Solid-state imaging device and manufacturing method thereof: A solid-state imaging device, includes: a substrate where a region of a first conductivity type is formed on at least a portion of a surface thereof; a region of a second conductivity type formed on at least a portion of a surface of the region of the first conductivity type;... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080210986 - Global shutter pixel with charge storage region: An imaging method, apparatus, and system having pixels that store charge from a photosensor in a storage diode are disclosed. Charge accumulated in the photosensor during an integration period is transferred to and stored in the storage diode prior to readout in a global shutter imager.... Agent: Dickstein Shapiro LLP

20080210987 - Array of fet transistors having a nanotube or nanowire semiconductor element and corresponding electronic device, for the detection of analytes: In an array R of field-effect transistors for detecting analytes, each transistor of the array comprises a gate G, a semiconductor nanotube or nanowire element NT connected at one end to a source electrode S and at another end to a drain electrode D, in order to form, at each... Agent: Lowe Hauptman & Berner, LLP

20080210988 - Insulated-gate field effect transistor: In a heterostructure field effect transistor (MISHFET), a source ohmic electrode 105 and a drain ohmic electrode 106 are formed on an AlGaN barrier layer 104. A SiNx gate insulator 108, a p-type polycrystalline SiC layer 109, and a Pt/Au gate electrode 110 being an ohmic electrode are formed one... Agent: Birch Stewart Kolasch & Birch

20080210989 - Semiconductor device: A semiconductor device includes a p-type semiconductor layer made of a compound semiconductor provided on a substrate, a compound semiconductor layer provided on the p-type semiconductor layer, active regions that are provided on the compound semiconductor layer and are adjacent to each other across an isolation region, a connecting portion... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080210990 - Cmos image sensor and fabricating method thereof: A CMOS image sensor and fabricating method thereof by which capacitance of a floating diffusion region (FD) can be increased. The CMOS image sensor can include an epitaxial layer formed over a semiconductor substrate; a gate electrode formed over the epitaxial layer; a gate metal formed over a floating diffusion... Agent: Sherr & Nourse, PLLC

20080210991 - Cmos image sensor and method of manufacturing: A CMOS image sensor capable of preventing leakage current of a transfer transistor and a method of manufacturing thereof are disclosed. Embodiments relate to a complementary metal-oxide-silicon (CMOS) image sensor including a transfer transistor. The transfer transistor includes an epi-layer formed over a semiconductor substrate defined by a photodiode area,... Agent: Sherr & Nourse, PLLC

20080210992 - Cmos image sensor and method of manufacturing the same: A CMOS image sensor that can include a first shallow trench isolation layer and a second shallow trench isolation layer formed in an epitaxial layer on both sides of a predetermined region of the epitaxial layer; a poly gate contacting the first shallow trench isolation layer and the second shallow... Agent: Sherr & Nourse, PLLC

20080210996 - Frame shutter pixel with an isolated storage node: A frame shutter type device provides a separated well in which the storage node is located. The storage node is also shielded by a light shield to prevent photoelectric conversion.... Agent: Dickstein Shapiro LLP

20080210995 - Image sensor and method for fabricating the same: An image sensor and a method for fabricating the same are disclosed, in which an impurity implantation layer having a predetermined thickness is formed on a source diffusion layer, thereby controlling a substantial contact point between a contact plug and the source diffusion layer upward from a surface of a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080210997 - Solid-state image pickup device and manufacturing method thereof: A solid-state image pickup device is provided in which a pixel forming region 4 and a peripheral circuit forming region 20 are formed on the same semiconductor substrate, a first element isolation portion is formed by an element isolation layer 21 in which an insulating layer is buried into a... Agent: Robert J. Depke Lewis T. Steadman

20080210993 - Solid-state image pickup device and method: The invention provides a solid-state image pickup device and method for realizing a higher sensitivity and a higher S/N ratio especially in the low-luminance region while maintaining a wide dynamic range. Plural pixels are integrated in an array configuration on a semiconductor substrate with each pixel having photodiode PD, which... Agent: Texas Instruments Incorporated

20080210994 - Solid-state imaging devices: A solid-state imaging device includes: a substrate; a photoelectric transducer that is provided within the substrate and generates light-generated charge in accordance with incident light; a floating diffusion that retains the light-generated charge generated from the photoelectric transducer; a transfer and retention unit that is provided between the photoelectric transducer... Agent: Harness, Dickey & Pierce, P.L.C

20080210998 - Method for manufacturing material layer, method for manufacturing ferroelectric capacitor using the same, ferroelectric capacitor manufactured by the same method, semiconductor memory device having ferroelectric capacitor and manufacturing method thereof: Provided is a method for manufacturing a material layer capable of increasing the deposition rate of a noble metal layer on a ferroelectric layer, a method for manufacturing a ferroelectric capacitor using the same, a ferroelectric capacitor manufactured by the same method, and a semiconductor memory device having the ferroelectric... Agent: Harness, Dickey & Pierce, P.L.C

20080210999 - Semiconductor device and method of manufacturing the same: A semiconductor device includes: a semiconductor substrate; a memory cell selection transistor that is formed on the semiconductor substrate and has a source and a drain; a contact plug; a polysilicon interlayer film that is formed above the memory cell selection transistor and has a cylinder-shaped through-hole; and a storage... Agent: Sughrue Mion, PLLC

20080211000 - Semiconductor device having transistors each having gate electrode of different metal ratio and production process thereof: A semiconductor device with integrated MIS field-effect transistors includes a first transistor containing a first gate electrode having a composition represented by MAx and a second transistor containing a second gate electrode having a composition represented by MAy, wherein M is at least one metal element selected from the group... Agent: Mcginn Intellectual Property Law Group, PLLC

20080211001 - Semiconductor device and a method of manufacturing the same: Provided is a semiconductor device having, over the main surface of a semiconductor substrate, a main circuit region and a memory cell array of a flash memory. The memory cell array has a floating gate electrode for accumulating charges of data, while the main circuit region has a gate electrode... Agent: Miles & Stockbridge PC

20080211002 - Semiconductor device and method of manufacturing the same: This semiconductor device includes: a first cylinder interlayer insulating film; a second cylinder interlayer insulating film; a cylinder hole including a first cylinder hole and a second cylinder hole communicating with the first cylinder hole; and a capacitor including a lower electrode and an upper electrode. The first cylinder interlayer... Agent: Sughrue Mion, PLLC

20080211003 - Capacitor in semiconductor device and method of manufacturing the same: The present invention relates to a capacitor in semiconductor device and a method of manufacturing the same, wherein, owing to formation of a lower electrode and an upper electrode into a stack structure of a poly-silicon layer and an aluminum (Al) layer and formation of an alumina (Al2O3) film as... Agent: Marshall, Gerstein & Borun LLP

20080211004 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a silicon crystal layer on an insulating layer, the silicon crystal layer containing a crystal lattice mismatch plane, a memory cell array portion on the silicon crystal layer, the memory cell array portion including memory strings, each of the memory strings including nonvolatile memory cell transistors... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080211006 - Nonvolatile semiconductor memory device and method of manufacturing the same: A nonvolatile semiconductor memory including a semiconductor substrate having an upper surface; a plurality of memory cell transistors formed in the semiconductor substrate, each memory cell transistor including a gate electrode having a gate insulating layer on the upper surface of the semiconductor substrate, a floating gate electrode layer on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080211007 - Self-aligned trenches with grown dielectric for high coupling ratio in semiconductor devices: Self-aligned trench filling to isolate active regions in high-density integrated circuits is provided. A deep, narrow trench is etched into a substrate between active regions. The trench is filled by growing a suitable dielectric such as silicon dioxide. The oxide grows from the substrate to fill the trench and into... Agent: Vierra Magen/sandisk Corporation

20080211005 - Semiconductor device: There is provided a MOSFET-type semiconductor device having a coating insulating film formed to cover the surface portions of MOS transistors formed on a semiconductor substrate. The insulating film is formed of a silicon nitride film or silicon oxynitride film and the ratio (N—H/Si—H) of the density of N—H bonds... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080211008 - Manufacturing method of flash memory device: Embodiments relate to a manufacturing method of a flash memory device which improves electrical characteristics by reducing or preventing void generation. A manufacturing method of a flash memory device according to embodiments includes forming a plurality of gate patterns over a semiconductor substrate including a tunnel oxide layer, a floating... Agent: Sherr & Nourse, PLLC

20080211009 - Process for manufacturing an electronic device integrated on semiconductor substrate comprising non volatile floating gate memories and an associated circuitry and corresponding electronic device: b

20080211010 - Semiconductor device: A semiconductor device includes: a package; two semiconductor chip fixing parts located adjacently to each other in the package; and first and the second semiconductor chips, each of which is fixed on the semiconductor chip fixing part and has a field effect transistor formed therein. A gate lead G1, a... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080211011 - Nonvolatile semiconductor memory element and nonvolatile semiconductor memory device: It is made possible to provide a nonvolatile semiconductor memory element that can be miniaturized and can store multi-level data. A nonvolatile semiconductor memory element includes a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; and a gate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080211013 - Semiconductor memory device with vertical channel transistor and method of fabricating the same: In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars... Agent: Mills & Onello LLP

20080211012 - Structure and method for forming accumulation-mode field effect transistor with improved current capability: An accumulation-mode field effect transistor includes a drift region of a first conductivity type, channel regions of the first conductivity type over and in contact with the drift region, and gate trenches having sidewalls abutting the channel regions. The gate trenches extend into and terminate within the drift region. The... Agent: Townsend And Townsend And Crew, LLP

20080211015 - Method of manufacturing a semiconductor power device: A trench is formed in a semiconductor body, the side walls and the bottom of the trench covered with a first dielectric material layer, the trench filled with a second dielectric material layer, the first and the second dielectric material layers are etched via a partial, simultaneous, and controlled etching... Agent: Seed Intellectual Property Law Group PLLC

20080211016 - Trench mosgated device with deep trench between gate trenches: A trench gated MOSFET especially for operation in high radiation environments has a deep auxiliary trench located between the gate trenches. A boron implant is formed in the walls of the deep trench (in an N channel device); a thick oxide is formed in the bottom of the trench, and... Agent: Ostrolenk Faber Gerb & Soffen

20080211014 - Ultra dense trench-gated power device with the reduced drain-source feedback capacitance and miller charge: The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is... Agent: Hiscock & Barclay, LLP

20080211017 - Semiconductor device: A semiconductor substrate is formed with trenches, and each of the trenches includes: a gate electrode portion in which a gate electrode is arranged; and a gate lead portion which is brought into contact with an interconnect for electrically connecting the gate electrode to the outside. In the gate lead... Agent: Mcdermott Will & Emery LLP

20080211018 - Semiconductor device and method of manufacturing the same: This semiconductor device includes a trench gate transistor including a groove formed on a semiconductor, a gate electrode formed in the groove via a gate insulating film, and a source and a drain disposed near the gate electrode on the semiconductor substrate via the gate insulating film. The gate electrode... Agent: Sughrue Mion, PLLC

20080211019 - Field-effect transistor and method for manufacturing a field-effect transistor: A field-effect transistor and a method for manufacturing a field-effect transistor is disclosed. One embodiment includes a substrate having a surface along which a trench is implemented, wherein the trench has a trench bottom and a trench edge. A source area is implemented at the trench edge and a gate... Agent: Dicke, Billig & Czaja

20080211020 - Semiconductor apparatus: A semiconductor apparatus includes: a first first-conductivity-type semiconductor layer; a second first-conductivity-type semiconductor layer provided on a major surface of the first first-conductivity-type semiconductor layer; a third second-conductivity-type semiconductor layer forming a periodic array structure in combination with the second first-conductivity-type semiconductor layer in a lateral direction generally parallel to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080211021 - Manufacturing process of a vertical-conduction misfet device with gate dielectric structure having differentiated thickness and vertical-conduction misfet device thus manufacture: According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping. A first body region and a second body region, having a second type of conductivity, opposite to... Agent: Graybeal, Jackson, Haley LLP

20080211022 - Semiconductor device having a triple gate transistor and method for manufacturing the same: In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented... Agent: Mills & Onello LLP

20080211023 - Semiconductor memory device and manufacturing method of semiconductor memory device: A semiconductor memory device has a first semiconductor layer and a second semiconductor layer facing each other across a back gate insulation film, a first conductive type plate provided in the first semiconductor layer, a gate insulation film provided on a surface of the second semiconductor layer so as to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080211024 - Memory device and manufacturing method of the same: An easy-to-use and inexpensive memory device is provided while maintaining product specifications and productivity even when a memory is formed on the same substrate as other functional circuits. The memory device of the invention includes a memory cell formed on an insulating surface. The memory cell includes a semiconductor film... Agent: Eric Robinson

20080211025 - Soi field effect transistor and corresponding field effect transistor: A first SOI field effect transistor with predetermined transistor properties, comprising: a laterally delimited layer sequence with a gate-insulating layer and a gate region on an undoped substrate; a spacer layer having a predetermined thickness on at least a portion of the sidewalls of the laterally delimited layer sequence; and... Agent: Dickstein Shapiro LLP

20080211026 - Coupling well structure for improving hvmos performance: A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation... Agent: Slater & Matsil, L.L.P.

20080211028 - Electro-static discharge protection device, semiconductor device, and method for manufacturing electro-static discharge protection device: An electrostatic discharge protection device including a gate electrode formed on a substrate. First and second diffusion regions of a first conductivity type are formed in the substrate with the gate electrode located in between. A first silicide layer is formed in the first diffusion region. A silicide block region... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080211027 - Esd structure without ballasting resistors: An electrostatic discharge (ESD) structure connected to a bonding pad in an integrated circuit comprising: a P-type substrate with one or more first P+ regions connected to a low voltage supply (GND), a first Nwell formed in the P-type substrate, one or more second P+ regions disposed inside the first... Agent: L. Howard Chen Kirkpatrick & Lockhart Preston Gates Ellis, LLP

20080211029 - Semiconductor device and a method of manufacturing the same: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over... Agent: Miles & Stockbridge PC

20080211031 - Semiconductor device and method of manufacturing the same: A device isolation film is formed in a semiconductor substrate at a border portion between a first region and a second region for defining a first active region in the first region and a second active region in the second region. A gate insulating film and a gate electrode is... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080211030 - Semiconductor device and method of manufacturing thereof: A first conductive layer and a second conductive layer are formed on an upper surface of a semiconductor substrate. The second conductive layer formed at a higher location than the first conductive layer. An insulating film is formed over the semiconductor substrate to cover the first conductive layer and the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080211033 - Reducing oxidation under a high k gate dielectric: A metal layer is formed on a dielectric layer, which is formed on a substrate. After forming a masking layer on the metal layer, the exposed sides of the dielectric layer are covered with a polymer diffusion barrier.... Agent: Trop Pruner & Hu, PC

20080211032 - Semiconduct device and method of manufacturing such a semiconductor device: The invention relates to a CMOS device (10) with an NMOST I and PMOST 2 having gate regions (1D,2D) comprising a compound containing both a metal and a further element. According to the invention the first and second conducting material both comprise a compound containing as the metal a metal... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080211034 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a substrate and a p-channel MIS transistor. The p-channel MIS transistor includes: an n-type semiconductor region formed in the substrate; p-type first source and drain regions formed at a distance from each other in the n-type semiconductor region; a first gate insulating film formed on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080211036 - Bipolar resistive memory device having tunneling layer: A nonvolatile memory device includes a semiconductor substrate, a first electrode on the semiconductor substrate, a resistive layer on the first electrode, a second electrode on the resistive layer and at least one tunneling layer interposed between the resistive layer and the first electrode and/or the second electrode. The resistive... Agent: Myers Bigel Sibley & Sajovec

20080211035 - Semiconductor memory device and method of manufacturing the same: A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically... Agent: Mcdermott Will & Emery LLP

20080211037 - Semiconductor device and method of forming isolation layer thereof: A method of forming an isolation layer of a semiconductor device includes the steps of forming a gate insulating layer and a conductive layer on an active area of a semiconductor substrate; forming a spacer layer on side walls of the conductive layer; forming a trench on the semiconductor substrate... Agent: Marshall, Gerstein & Borun LLP

20080211039 - Nonvolatile memory devices having metal silicide nanocrystals, methods of forming metal silicide nanocrystals, and methods of forming nonvolatile memory devices having metal silicide nanocrystals: A nonvolatile memory device includes a semiconductor substrate. A charge storage insulating film containing metal silicide nanocrystals is on the substrate. A gate electrode is on the charge storage insulating film. Related methods of forming metal silicide nanocrystals, and methods of forming nonvolatile memory devices including metal silicide nanocrystals, are... Agent: Myers Bigel Sibley & Sajovec

20080211038 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device includes forming a preliminary gate pattern on a semiconductor substrate. The preliminary gate pattern includes a gate oxide pattern, a conductive pattern, and a sacrificial insulating pattern. The method further includes forming spacers on opposite sidewalls of the preliminary gate pattern, forming an... Agent: F. Chau & Associates, LLC

20080211040 - Nanosensors: Electrical devices comprised of nanowires are described, along with methods of their manufacture and use. The nanowires can be nanotubes and nanowires. The surface of the nanowires may be selectively functionalized. Nanodetector devices are described.... Agent: Wolf Greenfield & Sacks, P.C.

20080211043 - Method and system for flip chip packaging of micro-mirror devices: A package for a micro-electromechanical device includes a substrate adapted to support the micro-electromechanical device. The micro-electromechanical device is electrically coupled to a plurality of electrodes. The package also includes a thermally conductive structure coupled to the substrate, an electrical contact layer having a plurality of traces in electrical communication... Agent: Townsend And Townsend And Crew, LLP

20080211042 - Method for manufacturing semiconductor device, and semiconductor device: A method for manufacturing a semiconductor device 10 includes: a step of forming a structure 30 on an insulation layer 14 formed on a semiconductor substrate 14, the structure including a piezoelectric layer 22, a first electrode 20, and a second electrode 24; a step of exposing a section of... Agent: Oliff & Berridge, PLC

20080211041 - Micro electrical mechanical system device: A micro electrical mechanical system device includes a frame portion having an upper surface with a rectangular shape; a functional element; a beam portion extending from one of sides of the frame portion toward an opposite one and having a first side surface, a second side surface opposite to the... Agent: Takeuchi & Kubotera, LLP

20080211044 - Micro-electro-mechanical systems device: m

20080211045 - Module for optical apparatus and method of producing module for optical apparatus: An electric wiring of a module for an optical apparatus includes: a first through electrode passing through the solid-state image sensor; a first rewiring layer being formed in such a way as to be re-wired to a necessary area in the rear surface of the solid-state image sensor, and being... Agent: Nixon & Vanderhye, PC

20080211046 - Semiconductor device for image sensor: Embodiments relate to a semiconductor device for an image sensor method of fabricating a semiconductor device for an image sensor having a micro lens. According to embodiments, the method may include forming a lower insulating film having cavities on a substrate, forming an upper insulating film having cavities on the... Agent: Sherr & Nourse, PLLC

20080211047 - Solid-state imaging device and electronic apparatus using the same: A solid-state imaging device includes a semiconductor substrate, a first pixel with a green color filter, a second pixel with a blue color filter and a third pixel with a red color filter. The first pixel includes a first area for generating an electric signal by photoelectric conversion, disposed in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080211048 - Encapsulated optical package: A method for providing an encapsulated optoelectronic chip is provided. The optoelectronic chip is secured on a substrate. A translucent coating substance is then applied on said optoelectronic chip and the translucent coating substance is then polished away to enable an optical coupling.... Agent: Ogilvy Renault LLP

20080211049 - Method and device for integrating an illumination source and detector into the same ic package that allows angular illumination with a common planar leadframe: An optical navigation device includes an integrated package. The integrated package includes a planar leadframe, a light source die mounted on the leadframe, and a sensor die mounted on the leadframe to be coplanar with the light source die. The integrated package may be mounted at an angle or parallel... Agent: Kathy Manke Avago Technologies Limited

20080211051 - Component with a semiconductor junction and method for the production thereof: A component comprising a semiconductor junction (HU) is proposed which is formed from crystalline doped semiconductor layers. A semiconductor circuit (IC) is formed on the surface of the component, and a diode is formed internally and directly below the circuit. Integrated circuit and diode are connected to one another and... Agent: Nexsen Pruet, LLC

20080211050 - Image sensor with inter-pixel isolation: An image sensor with a plurality of photodiodes that each have a first region constructed from a first type of material and a second region constructed from a second type of material. The photodiodes also have an insulating region between the first and second regions. The photodiodes are arranged in... Agent: Irell & Manella LLP

20080211052 - Field effect transistor and method for fabricating the same: A method for fabricating a field effect transistor includes: forming an insulating film provided on a semiconductor layer, the insulating film having an opening via which a surface of the semiconductor layer is exposed and including silicon oxide; forming a Schottky electrode on the insulating film and in the opening,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080211053 - Superjunction semiconductor device: In accordance with an embodiment of the invention, a superjunction semiconductor device includes an active region and a termination region surrounding the active region. A central vertical axis of a boundary column of a second conductivity type material defines the boundary between the active region and the termination region. The... Agent: Townsend And Townsend And Crew, LLP

20080211054 - Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods: A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080211055 - Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit: Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition... Agent: Ryan, Mason & Lewis, LLP

20080211056 - Semiconductor device and a method of manufacturing the same and designing the same: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080211057 - Semiconductor having buried word line cell structure and method of fabricating the same: Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce the height of the semiconductor device and to reduce the degradation of the oxide layer caused by chlorine ions from the application... Agent: Harness, Dickey & Pierce, P.L.C

20080211059 - Electronic fuse having heat spreading structure: A semiconductor device includes a fuse transistor for fuse programming and a fuse block connected to the fuse transistor, wherein the fuse block comprises a fuse line and a heat spreading structure connected to the fuse line. The electrical fuse employs the heat spreading structure connected to the fuse line... Agent: Marger Johnson & Mccollom, P.C.

20080211058 - Semiconductor device and method of manufacturing same: A semiconductor device comprises one or more elements subjected to trimming, formed on a main surface side of a silicon substrate and that is/are to be laser trimmed, and an electrode lead of the element subjected to trimming disposed below the position of the element subjected to trimming. The electrode... Agent: Foley And Lardner LLP Suite 500

20080211060 - Anti-fuse which will not generate a non-linear current after being blown and otp memory cell utilizing the anti-fuse: An anti-fuse is formed with a transistor with a doped channel. The anti-fuse will not generate a non-linear current after the anti-fuse is blown. The anti-fuse is used in memory cells of one-time programmable (OTP) memory. The OTP memory utilizes a p-type transistor and an n-type transistor to program the... Agent: North America Intellectual Property Corporation

20080211061 - Method for the fabrication of gaas/si and related wafer bonded virtual substrates: A method of making a virtual substrate includes providing a device substrate of a first material containing a device layer of a second material different from the first material located over a first side of the device substrate, implanting ions into the device substrate such that a damaged region is... Agent: Hiscock & Barclay, LLP

20080211062 - Nitride semiconductor device and manufacturing method thereof: A semiconductor device and a manufacturing method thereof are provided which enable reduction and enhanced stability of contact resistance between the back surface of a nitride substrate and an electrode formed thereover. A nitride semiconductor device includes an n-type GaN substrate (1) over which a semiconductor element is formed, and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080211063 - Semiconductor wafer and manufacturing method of semiconductor device: A semiconductor wafer includes a semiconductor substrate, a semiconductor layer, and an oxide layer. The semiconductor layer is disposed on a surface of the semiconductor substrate and has a crystal structure similar to a crystal structure of the semiconductor substrate. The semiconductor layer includes an element section and a scribe... Agent: Posz Law Group, PLC

20080211064 - Deep trench based far subcollector reachthrough: A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far... Agent: Scully, Scott, Murphy & Presser, P.C.

20080211065 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a material layer of a semiconductor device includes providing a workpiece, and forming a ZrO2 layer over the workpiece. The method includes forming at least one monoclinic crystalline phase-minimizing material layer for the ZrO2... Agent: Slater & Matsil LLP

20080211066 - Barrier film and method of producing barrier film: A barrier film formed on top of a substrate, a barrier film formed so as to cover a functional element region fabricated on top of a substrate, or a barrier film formed on both a substrate and a functional element region, wherein the barrier film includes at least one layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080211067 - Semiconductor device: Disclosed is a semiconductor device which includes a semiconductor chip and a base substrate. The semiconductor chip includes a semiconductor substrate, an interconnect layer and a high-frequency interconnect. The interconnect layer is provided on the substrate. The high-frequency interconnect is formed within the interconnect layer. The semiconductor chip is mounted... Agent: Young & Thompson

20080211068 - Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product: A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of... Agent: North America Intellectual Property Corporation

20080211069 - Semiconductor package configuration with improved lead portion arrangement: A semiconductor device with improved reliability is provided. The semiconductor device in a QFN package configuration has a semiconductor chip mounted on a tab, leads which are alternately arranged around the tab and electrically connected to the electrodes of the semiconductor chip via bonding wires, and an encapsulating resin portion... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080211070 - Flip chip contact (fcc) power package: This invention discloses a power device package for containing, protecting and providing electrical contacts for a power transistor. The power device package includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip... Agent: Bo-in Lin

20080211071 - Memory ic package assembly having stair step metal layer and apertures: Disclosed is a low cost memory IC package assembly having a first metal layer bonded to the die and a dielectric insulating layer with circuits and with apertures to expose the first metal layer bonded thereto.... Agent: Law Office Of Ronald Shea

20080211072 - Testing and burn-in using a strip socket: A method and apparatus are provided for using a strip socket in testing or burn-in of semiconductor devices in a strip. In one example of the method, processing of semiconductor devices involves assembling the semiconductor devices into a strip, isolating a portion of each of the semiconductor devices of the... Agent: Haverstock & Owens LLP Attn: Thomas B. Haverstock

20080211073 - Airtight package: An airtight sealed package with a device sealed therein in an airtight manner under vacuum, the device being placed in a space defined in the airtight sealed package by a lid and a substrate, includes at least one pressure adjustment unit provided on at least one of the lid and... Agent: Scully Scott Murphy & Presser, PC

20080211074 - Ic card and method of manufacturing the same: An IC body is loaded to a case 2 made of thermosetting resin material and sealed with a sealing portion made of thermosetting resin material to be integrated, whereby an IC card is manufactured. The IC body comprises: a wiring substrate formed with an external connection terminal at a back... Agent: Miles & Stockbridge PC

20080211075 - Image sensor chip scale package having inter-adhesion with gap and method of the same: A structure of semiconductor device package having inter-adhesion with gap comprising: a chip with bonding pads and a sensor area embedded into a substrate with die window and inter-connecting through holes, wherein a RDL is formed over the substrate for coupling between the bonding pads and the inter-connecting through holes;... Agent: Kusner & Jaffe Highland Place Suite 310

20080211076 - Semiconductor device and manufacturing method thereof: A semiconductor device capable of elevating a yield rate of products to improve the productivity and also ensuring high reliability in production and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a semiconductor substrate 2, a MEMS part 3 formed on a surface of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080211079 - Heat dissipation methods and structures for semiconductor device: A semiconductor device with efficient heat dissipating structures is disclosed. The semiconductor device includes a first semiconductor chip that is flip-chip mounted on a first substrate, a heat absorption portion that is formed between the first semiconductor chip and the first substrate, an outer connection portion that connects the first... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20080211077 - Low profile chip scale stacking system and method: The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of... Agent: Fish & Richardson P.C.

20080211078 - Semiconductor packages and method of manufacturing the same: A stacked semiconductor package can be formed according to principles of the present invention by stacking a plurality of semiconductor packages. A method of manufacturing the stacked semiconductor packages provides a simple manufacturing process. The stacked semiconductor package embodying these principles preferably includes a base substrate, one or more lower... Agent: Marger Johnson & Mccollom, P.C.

20080211080 - Package structure to improve the reliability for wlp: The present invention provides a package structure to improve the reliability for WLP (Wafer Level Package). The package structure includes at least two areas. One area is harder than another. The hard area sustains more shears resulting from board drop test than the soft area in order to disperse the... Agent: Birch Stewart Kolasch & Birch

20080211081 - Planar multi semiconductor chip package and method of manufacturing the same: Provided are a planar multi semiconductor chip package in which a processor and a memory device are connected to each other via a through electrode and a method of manufacturing the planar multi semiconductor chip package. The planar multi semiconductor chip package includes: a substrate comprising a plurality of first... Agent: Marger Johnson & Mccollom, P.C.

20080211082 - Semiconductor device and a method of manufacturing the same: A semiconductor device and method having high output and having reduced external resistance is reduced and improved radiating performance. A MOSFET (70) has a connecting portion for electrically connecting a surface electrode of a semiconductor pellet and a plurality of inner leads, a resin encapsulant (29), a plurality of outer... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080211083 - Electronic package and manufacturing method thereof: An electronic package and a manufacturing method thereof are disclosed. The electronic package manufacturing method, which includes providing a printed circuit board (PCB) having one surface on which a first chip is mounted; attaching one surface of a second chip on the other surface of the PCB, a pad being... Agent: Staas & Halsey LLP

20080211084 - Integrated circuit package system with interposer: An integrated circuit package system includes: providing a mountable integrated circuit system having an encapsulation with a cavity therein and a first interposer exposed by the cavity; mounting a second interposer over the first interposer for only stacking a discrete device thereover, and with the second interposer over the encapsulation... Agent: Law Offices Of Mikio Ishimaru

20080211085 - Semiconductor package having insulating substrate: A semiconductor package having an insulating substrate includes a dielectric layer, a set of metal layers, a set of supporting elements, and an electronic component. The set of metal layers includes a first metal layer and a second metal layer respectively located on the upper surface and the lower surface... Agent: Rosenberg, Klein & Lee

20080211086 - Mounting method of electronic components, manufacturing method of electronic component-embedded substrate, and electronic component-embedded substrate: There is disclosed a fixing method of an electronic component or the like in which when the electronic component and a resin layer are fixed, warp and bend of the electronic component can be inhibited. During manufacturing of a semiconductor-embedded substrate 200 in which a semiconductor device 220 is embedded,... Agent: Oliff & Berridge, PLC

20080211087 - Chip module and method for producing a chip module: A chip module comprises a substrate, a chip arranged on one side of the substrate and conductor structures arranged on at least one side of the substrate and conductively connected to the chip. At least one stiffening element is arranged on one side of the substrate and a moulding cap... Agent: Dickstein Shapiro LLP

20080211088 - Semiconductor device: The semiconductor device includes a substrate, a first semiconductor element, a second semiconductor element, a first heat sink and a second heat sink. The first and the second semiconductor elements are provided on the substrate. The maximum power consumption of the first semiconductor element is lower than that of the... Agent: Young & Thompson

20080211089 - Interposer for die stacking in semiconductor packages and the method of making the same: Methods and apparatus for improved electrical, mechanical and thermal performance of stacked IC packages are described. An IC package comprises a substrate, a first die, a second die, and an interposer with an opening in a first surface of the interposer configured to accommodate the first die. The first IC... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080211090 - Packed semiconductor sensor chip for use in liquids: The present invention provides a packed semiconductor sensor chip (10) in which the sensing circuit (17) is positioned at substantially the same level or above the level of the packaging (13). Because of this, when the sensor is immersed in a fluid, in particular in a liquid, for the detection... Agent: Philips Intellectual Property & Standards

20080211091 - Power semiconductor module and method for producing the same: A method for producing a power semiconductor module including forming a contact between a contact region and a contact element as an ultrasonic welding contact via a sonotrode. The ultrasonic welding operation also being used for joining the contact regions with the contact ends and consequently for joining the contacts... Agent: Edell , Shapiro & Finnan , LLC

20080211092 - Electronic assembly having a multilayer adhesive structure: An electronic assembly comprising a first substrate, a number of bonds on the first substrate, a second substrate spaced apart from the first substrate, a number of bumps on the second substrate, each of the bumps including an insulating body and a conductive portion, the conductive portion extending from a... Agent: Akin Gump LLP - Silicon Valley

20080211093 - Semiconductor device having conductive bumps and fabrication method thereof: A semiconductor device having conductive bumps and a fabrication method thereof is proposed. The fabrication method includes the steps of forming a first metallic layer on a substrate having solder pads and a passivation layer formed thereon, and electrically connecting it to the solder pads; applying a second covering layer... Agent: Edwards Angell Palmer & Dodge LLP

20080211094 - Semiconductor device and method of manufacturing the same: A semiconductor device includes an electrode pad formed on a pad forming surface of a semiconductor integrated circuit chip, and a step formed on the pad forming surface to surround the electrode pad. A method of manufacturing the semiconductor device is also disclosed.... Agent: Sughrue Mion, PLLC

20080211095 - Semiconductor device and manufacturing method of the semiconductor device: A semiconductor device where an outside connection terminal of a semiconductor element and an electrode of a wiring board are connected to each other via a conductive adhesive, the conductive adhesive includes a first conductive adhesive; and a second conductive adhesive covering the first conductive adhesive; wherein the first conductive... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080211100 - Method and structure for reducing contact resistance between silicide contact and overlying metallization: A semiconductor structure in which the contact resistance in the contact opening is reduced as well as a method of forming the same are provided. This is achieved in the present invention by replacing conventional contact metallurgy, such as tungsten, or a metal silicide, such as Ni silicide or Cu... Agent: Scully, Scott, Murphy & Presser, P.C.

20080211099 - Semiconductor device: A semiconductor device (1) includes an insulating film (18) which is formed on an interlayer insulating film (10) and includes a low-permittivity film (14), and two wirings (24) formed in wiring grooves (26) formed in the insulating film (18). The two wirings have a length of “L”. The insulting film... Agent: Young & Thompson

20080211098 - Semiconductor device and method for fabricating the same: A semiconductor device in which the resistance of a copper wiring to electromigration is increased. The copper wiring is formed so that copper grains will be comparatively large in a central portion of the copper wiring and so that copper grains will be comparatively small in an upper portion and... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080211097 - Semiconductor device and method for manufacturing same: A semiconductor device includes an insulating interlayer formed above a silicon substrate and provided with a concave portion in a certain location, a barrier metal film covering an inner wall of the insulating interlayer, a lower layer copper interconnect provided so as to be in contact with the barrier metal... Agent: Young & Thompson

20080211096 - Switching element and reconfigurable logic integrated circuit: A switching element is of a configuration that includes: an ion conduction layer (40) for conducting metal ions, a first electrode (21) and a second electrode (31) provided in contact with the ion conduction layer, a third electrode (35) that can supply metal ions to the ion conduction layer, and... Agent: Sughrue Mion, PLLC

20080211101 - Interlayer wiring of semiconductor device using carbon nanotube and method of manufacturing the same: Provided is an interlayer wiring structure of a semiconductor device using carbon nanotubes, and a method of manufacturing the interlayer wiring structure. The interlayer wiring structure is a carbon nanotube bundle that connects a first electrode to a second electrode. The carbon nanotube bundle includes a plurality of carbon nanotubes... Agent: Robert E. Bushnell

20080211102 - Laterally grown nanotubes and method of formation: A semiconductor device has lateral conductors or traces that are formed of nanotubes such as carbon. A sacrificial layer is formed overlying the substrate. A dielectric layer is formed overlying the sacrificial layer. A lateral opening is formed by removing a portion of the dielectric layer and the sacrificial layer... Agent: Freescale Semiconductor, Inc. Law Department

20080211104 - High temperature, stable sic device interconnects and packages having low thermal resistance: A method of forming packages containing SiC or other semiconductor devices bonded to other components or conductive surfaces utilizing transient liquid phase (TLP) bonding to create high temperature melting point bonds using in situ formed ternary or quaternary mixtures of conductive metals and the devices created using TLP bonds of... Agent: Koppel, Patrick & Heybl

20080211105 - Method of assembling chips: A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is... Agent: Megica Corporation

20080211103 - Semiconductor device and a method of manufacturing the same: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu... Agent: Miles & Stockbridge PC

20080211108 - Semiconductor device and a method of manufacturing the same: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching... Agent: Miles & Stockbridge PC

20080211109 - Semiconductor device and method of visual inspection and apparatus for visual inspection: A semiconductor device having the structure, which is adopted for the highly precise visual inspection with a lower cost, is achieved. A semiconductor device is a semiconductor device having a region for forming an electric circuit, and includes seal rings provided in an interconnect layer and surrounding the region for... Agent: Young & Thompson

20080211107 - Via hole structure and manufacturing method thereof: A via hole structure and a manufacturing method thereof are provided. The via hole structure is disposed on a substrate. The substrate has a through hole, which passes through the substrate from a top surface to a bottom surface. The via hole structure comprises a conductive layer, several first conductive... Agent: Bacon & Thomas, PLLC

20080211106 - Via/contact and damascene structures and manufacturing methods thereof: A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed... Agent: Duane Morris LLPIPDepartment (tsmc)

20080211110 - Semiconductor apparatus and mobile apparatus: A semiconductor apparatus includes: a wiring board; a first semiconductor device mounted on the wiring board; a second semiconductor device which is stacked on the first semiconductor device and a projection part projects from the outer edge of the first semiconductor device; and a sealing resin layer which seals each... Agent: Fish & Richardson P.C.

20080211111 -