Active solid-state devices (e.g., transistors, solid-state diodes) inventions 08/08

20080203374 - Phase-change memory and fabrication method thereof: A phase-change memory is provided. The phase-change memory comprises a substrate. A first electrode is formed on the substrate. A circular or linear phase-change layer is electrically connected to the first electrode. A second electrode formed on the phase-change layer and electrically connected to the phase-change layer, wherein at least... Agent: Birch Stewart Kolasch & Birch

20080203375 - Memory cell with memory element contacting ring-shaped upper end of bottom electrode: A memory cell includes a bottom electrode, a top electrode and a memory element switchable between electrical property states by the application of energy. The bottom element includes lower and upper parts. The upper part has a generally ring-shaped upper end surrounding a non-conductive central region. The lateral dimension of... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080203376 - Phase change memories with improved programming characteristics: A phase change memory may be made with improved speed and stable characteristics over extended cycling. The alloy may be selected by looking at alloys that become stuck in either the set or the reset state and finding a median or intermediate composition that achieves better cycling performance. Such alloys... Agent: Trop Pruner & Hu, PC

20080203379 - Array of vertical bipolar junction transistors, in particular selectors in a phase change memory device: A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions of dielectric material are formed in a semiconductor body, thereby defining a plurality of active areas, insulated from each other and a plurality of bipolar transistors are formed in each active area. In particular, in each... Agent: Seed Intellectual Property Law Group PLLC

20080203377 - Methods of manufacturing non-volatile memory devices by implanting metal ions into grain boundaries of variable resistance layers, and related devices: Integrated circuit nonvolatile memory devices are manufactured by forming a variable resistance layer on an integrated circuit substrate. The variable resistance layer includes grains that define grain boundaries between the grains. Conductive filaments are formed along at least some of the grain boundaries. Electrodes are formed on the variable resistance... Agent: Myers Bigel Sibley & Sajovec

20080203378 - Semiconductor memory device and method of manufacturing the same: A phase change memory device including plural memory cells is disclosed. Each of the memory cells includes memory transistors and phase change film portions formed above or below the memory transistors. The phase change film portions correspond to the respective memory transistors respectively. Vias are provided in order to connect... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080203380 - Cnt devices, low-temperature fabrication of ctn and cnt photo-resists: A method is provided for growth of carbon nanotube (CNT) synthesis at a low temperature. The method includes preparing a catalyst by placing the catalyst between two metal layers of high chemical potential on a substrate, depositing such placed catalyst on a surface of a wafer, and reactivating the catalyst... Agent: Stmicroelectronics, Inc.

20080203381 - Forming arsenide-based complementary logic on a single substrate: In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first... Agent: Trop Pruner & Hu, PC

20080203382 - Semiconductor wafer, devices made therefrom, and method of fabrication: A main semiconductor region of semiconducting nitrides is formed on a silicon substrate via a buffer region of semiconducting nitrides to provide devices such as HEMTs, MESFETs and LEDs. In order to render the wafer proof against warping, the buffer region is divided into a first and a second multilayered... Agent: Woodcock Washburn LLP

20080203385 - Light emitting element and manufacturing method thereof, and light emitting device using the light emitting element: A light-emitting element has a layer including an organic material between a first electrode and a second electrode, and further has a layer including a metal oxide between the second electrode and the layer including the organic material, where these electrodes and layers are laminated so that the second electrode... Agent: Eric Robinson

20080203384 - Method of manufacturing an electrical element: The element (50) comprises a first electrode (51), a self-assembled system (52), which is or comprises a monolayer an a second electrode (54). A polymeric contact layer (53) that has been deposited wet-chemically is present between the self-assembled system (52) and the second electrode (54). Suitably, both the self-assembled system... Agent: Philips Intellectual Property & Standards

20080203383 - Multi-layer composite body having an electronic function: The invention relates to a multilayer composite body having an electronic function, in particular an electronic subassembly comprising a plurality of organic electronic components. The invention provides, for the first time, a possibility for a structure of an entire subassembly such as an RFID tag, the entire tag with all... Agent: Carella, Byrne, Bain, Gilfillan, Cecchi, Stewart & Olstein

20080203386 - Method of forming a patterned resist layer for patterning a semiconductor product: A first embodiment discloses a method of forming a patterned resist layer for patterning a substrate. A resist layer is formed on or above a substrate. An inorganic layer is formed on the resist layer. The resist layer covered with the inorganic layer is lithographically exposed. The resist layer covered... Agent: Slater & Matsil LLP

20080203387 - Thin film transistor and method of manufacturing the same: Provided are a thin film transistor and a method of manufacturing the same. The thin film transistor may include a gate; a channel layer; a source and a drain, the source and the drain being formed of metal; and a metal oxide layer, the metal oxide layer being formed between... Agent: Harness, Dickey & Pierce, P.L.C

20080203388 - Apparatus and method for detection of edge damages: Embodiments of the invention enable detection of edge damages in semiconductor devices. To this purpose, one or more continuity structures may be provided, where each structure comprises an undulating arrangement disposed between active circuits of the semiconductor device and a perimeter of the metallization layers. The continuity structure(s) forms one... Agent: Intel Corporation C/o Intellevate, LLC

20080203389 - Semiconductor apparatus having temperature sensing diode: A semiconductor apparatus is provided. The semiconductor apparatus includes a semiconductor substrate and a temperature sensing diode that is disposed on a surface part of the semiconductor substrate. A relation between a forward current flowing through the temperature sensing diode and a corresponding voltage drop across the temperature sensing diode... Agent: Marks & Clerk

20080203391 - Array substrate, display apparatus having the same: An array substrate includes a base substrate which includes a display area and a peripheral area adjacent to the display area, a plurality of fan-out lines arranged in the peripheral area to receive a driving signal from an exterior source, at least one fan-out line among the plurality of fan-out... Agent: Cantor Colburn, LLP

20080203392 - Display substrate, method of manufacturing the same and display device having the same: A display substrate includes a base substrate having a display area and a peripheral area which surrounds the display area, a pixel electrode formed on the display area, a pad part formed on the peripheral area, an adhesion part formed on the peripheral area and having a plurality of holes... Agent: Cantor Colburn, LLP

20080203390 - Method for manufacturing a signal line, thin film transistor panel, and method for manufacturing the thin film transistor panel: A method for manufacturing a thin film transistor array panel includes forming a gate line on a substrate; sequentially forming a gate insulating layer, a silicon layer, and a conductor layer including a lower layer and an upper layer on the gate line, forming a photoresist film, on the conductor... Agent: F. Chau & Associates, LLC

20080203393 - Thin film transistor array panel and fabrication: The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film... Agent: Macpherson Kwok Chen & Heid LLP

20080203394 - Method for fabrication of active-matrix display panels: The present invention provides a method of an active-matrix thin film transistor array, comprising of two levels of metallic interconnections formed from one layer of metallic conductor; and thin-film transistors with source, drain and gate electrodes either fully or partially replaced with metal, and wherein the pixel electrodes are polycrystalline... Agent: Cooper & Dunham, LLP

20080203396 - Electro-optical substrate, method for designing the same, electro-optical device, and electronic apparatus: An electro-optical substrate, including: a transparent substrate; a first light-shielding layer arranged on a first surface of the transparent substrate, in at least part of a region surrounding an opening in plan view; a first insulating layer arranged in a position facing the transparent substrate with the first light-shielding layer... Agent: Oliff & Berridge, PLC

20080203395 - Semiconductor device and manufacturing method thereof: A semiconductor device and a method for manufacturing the same are provided. First, a transparent substrate is provided. Next, a light-shielding layer is formed over the transparent substrate and a first buffer layer is formed to cover the light-shielding layer. A semiconductor layer is formed over the first buffer layer.... Agent: Jianq Chyun Intellectual Property Office

20080203401 - Method for manufacturing semiconductor device and semiconductor device manufactured therefrom: A method for producing a semiconductor device includes forming a first hetero-semiconductor layer as a hetero-junction to a surface of a silicon carbide epitaxial layer. This layer is composed of polycrystalline silicon having a band gap different from that of the silicon carbide epitaxial layer. An etching stopper layer composed... Agent: Young & Basile, P.C.

20080203399 - Polarization doped transistor channels in sic heteropolytypes: Heteropolytype SiC heterojunctions display an abrupt change in polarization leading to 2 dimensional electron or hole gases at the lattice matched interface, depending on the direction of polarization. These channels carry a large amount of electric current which can be modulated with a gate electrode, giving rise to transistor operation... Agent: Jones, Tullar & Cooper, P.C.

20080203400 - Semiconductor device and method of manufacturing same: A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080203402 - Sic semiconductor device and method for manufacturing the same: A SiC semiconductor device includes: a SiC substrate having a main surface; a channel region on the substrate; first and second impurity regions on upstream and downstream sides of the channel region, respectively; a gate on the channel region through a gate insulating film. The channel region for flowing current... Agent: Posz Law Group, PLC

20080203398 - Silicon carbide self-aligned epitaxial mosfet and method of manufacturing thereof: A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area... Agent: Volentine & Whitt PLLC

20080203397 - Switching device: A high voltage diamond based switching device capable of sustaining high currents in the on state with a relatively low impedance and a relatively low optical switching flux, and capable of being switched off in the presence of the high voltage being switched. The device includes a diamond body having... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080203404 - Optical semiconductor device: In an optical semiconductor device that emits or receives light substantially perpendicularly to or in parallel to an active surface formed on a semiconductor substrate, the optical semiconductor device, an electrode that is formed on the active surface side and connected to the active surface is stepped or tapered at... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080203403 - Semiconductor integrated circuit: The semiconductor integrated circuit (1) has a memory (4) and a logic circuit (5), which are mixedly palletized on a silicon substrate (2). The memory includes a partially-depleted type nMOS (6) having an SOI structure and formed on UTB (3). The partially-depleted type nMOS has a backgate region (14) under... Agent: Miles & Stockbridge PC

20080203405 - Method for preparing an electric circuit comprising multiple leds: The invention relates to a method for preparing an electric circuit comprising a plurality of Light-Emitting Diodes (LEDs). First, a continuous layer of a first semiconductor material is provided. On this a first pattern of a material of a second semiconductor type is applied. Next, a substrate comprising a second... Agent: Howrey LLP-eu

20080203406 - Layer assembly for a light-emitting component: The invention relates to a layer assembly for a light-emitting component, in particular a phosphorescent organic light-emitting diode, having a hole-injecting contact and an electron-injecting contact which are each connected to a light-emitting region, wherein, in the light-emitting region, one light-emitting layer is made up of a material (M1) and... Agent: Sutherland Asbill & Brennan LLP

20080203407 - Method for producing an optoelectronic semiconductor chip, and optoelectronic semiconductor chip: A method for producing an optoelectronic semiconductor chip based on a nitride semiconductor system is specified. The method comprises the steps of: forming a semiconductor section with at least one p-doped region; and forming a covering layer disposed downstream of the semiconductor section in a growth direction of the semiconductor... Agent: Cohen Pontani Lieberman & Pavane LLP

20080203408 - Process for producing (al, ga)lnn crystals: m

20080203409 - Process for producing (al, ga)n crystals:

20080203411 - Direct attachment of optically-active device to optical element: A system may include biasing of a substantially planar surface of an optically-active semiconductor device against a substantially planar surface of an optical element, and bonding of the substantially planar surface of the optically-active semiconductor device to the substantially planar surface of the optical element.... Agent: Buckley, Maschoff & Talwalkar LLC

20080203412 - Led assembly with molded glass lens: A LED assembly with a molded glass lens includes a base, at least one LED chip and a cover lens. The LED assembly feature on that the cover lens consists of a molded glass lens and a transparent resin layer. A molded glass lens is covered on a loading surface... Agent: Troxell Law Office PLLC

20080203415 - Led devices having lenses and methods of making same: Disclosed herein are LED devices having lenses and methods of making the devices. The LED devices are made using an optical layer comprising a plurality of lens features. The optical layer is disposed relative to the LED die such that at least one LED die is optically coupled to at... Agent: 3m Innovative Properties Company

20080203410 - Methods for the production of luminescent diode chips and luminescent diode chip: The invention relates to a method of making LED chips provided with a luminescence conversion material containing at least one phosphor. In the method, a layer composite is prepared that includes an LED layer sequence for a multiplicity of LED chips and comprises on a main surface at least one... Agent: Fish & Richardson PC

20080203413 - Optoelectronic components with adhesion agent: SiO2 layers are used as adhesion layers in the case of optoelectronic components. Durable adhesions can be produced with silicone rubbers. These materials normally have only an insufficient adhesive strength on materials as frequently used for optoelectronic components, such as LED modules. This then leads in further consequence to a... Agent: Marshall, Gerstein & Borun LLP

20080203418 - Semiconductor device: A semiconductor device comprises an active layer having a quantum well structure, the active layer including a well layer and a barrier layer and being sandwiched by a first conductivity type layer and a second conductivity type layer, wherein a first barrier layer is provided on side of the first... Agent: Morrison & Foerster LLP

20080203419 - Semiconductor light emitting apparatus: A semiconductor light emitting apparatus can be configured to reduce color variations and intensity variations with a simple configuration. The semiconductor light emitting apparatus can include a substrate having conductive members including chip mounting areas and electrode areas, a plurality of semiconductor light emitting device chips mounted in the chip... Agent: Cermak Kenealy & Vaidya, LLP

20080203416 - Surface mounting type light emitting diode and method for manufacturing the same: This invention provides a surface mounting type light emitting diode excellent in heat radiation performance, reliability and productivity. The surface mounting type light emitting diode includes a metallic base member, a semiconductor light emitting element having a bottom face fixedly bonded to a top face of the base member, and... Agent: Morrison & Foerster LLP

20080203417 - Surface mounting type light emitting diode and method for manufacturing the same: This invention provides a surface mounting type light emitting diode excellent in heat radiation performance, reliability and productivity. The surface mounting type light emitting diode includes an insulating base member, a semiconductor light emitting element having a bottom face fixedly bonded to a top face of the base member, and... Agent: Morrison & Foerster LLP

20080203414 - White light led device: Light-emitting diode (LED) devices which can produce a uniform white light with a broad emission spectrum and a high color rendering index (CRI) are provided. For example, the emission spectrum of LED devices as described herein may provide more red light and yield a higher CRI light when compared to... Agent: Patterson & Sheridan, L.L.P.

20080203420 - Collective substrate, semiconductor element mount, semiconductor device, imaging device, light emitting diode component and light emitting diode: A collective substrate (1) is produced by firing a ceramic green sheet and forming through-holes (11) in the resulting substrate. The through-holes (11) each have an interior surface including taper surfaces (11b, 11c) which are tapered as having an opening size progressively decreasing from a main surface (21) and an... Agent: Rabin & Berdo, PC

20080203422 - Structure of light emitting diode and method to assemble thereof: A structure of a light emitting diode is provided. The light emitting diode comprises a light emitting diode die; two conductive frames electronically and respectively connecting to the cathode and anode of the light emitting diode die, and two substrates. Each conductive frame has a fixing hole and each substrate... Agent: Raymond R. Moser Jr., Esq. MoserIPLaw Group

20080203421 - Structured substrate for a led: A substrate (1) made of a transparent material, preferably glass, which substrate has a planar first side (1a) for the application of an electroluminescent layered structure (21, 22, 23) for emitting light and having a structured second side (1b) for the effective coupling-out of light (6), comprising at least one... Agent: Philips Intellectual Property & Standards

20080203423 - Light-emitting diode: A light-emitting diode is provided which includes: a sheet-like substrate; a pair of electrode patterns formed to wrap round and cover substantially entire upper and lower surfaces of the substrate, said pair of electrode patterns comprising an upper electrode portion, a lower electrode portion and a side electrode portion; a... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080203424 - Diode and applications thereof: A diode with low substrate current leakage and suitable for BiCMOS process technology. A buried layer is formed on a semiconductor substrate. A connection region and well contact the buried layer. Isolation regions are adjacent to two sides of the buried layer, each deeper than the buried layer. The isolation... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20080203425 - Phototransistors, methods of making phototransistors, and methods of detecting light: A phototransistor (400) comprises an emitter (43) comprising antimony, a base (42) comprising antimony, and a collector (41) comprising antimony. Preferably, the emitter, the base and the collector each comprises at least one of AlInGaAsSb, AlGaAsSb, AlGaSb, GaSb and InGaAsSb. The base comprises an emitter-contacting portion (41b) with a base-contacting... Agent: Burr & Brown

20080203426 - Heterojunction semiconductor device and method of manufacturing: A metamorphic buffer layer is formed on a semi-insulating substrate by an epitaxial growth method, a collector layer, a base layer, an emitter layer and an emitter cap layer are sequentially laminated on the metamorphic buffer layer, and a collector electrode is provided in contact with an upper layer of... Agent: David R. Metzger Sonnenschein Nath & Rosenthal

20080203428 - Mos transistors having recessed channel regions and methods of fabricating the same: A MOS transistor having a recessed channel region is provided. A MOS transistor includes a source region and a drain region disposed in an active region of a semiconductor substrate and spaced apart from each other. A gate trench structure is disposed in the active region between the source and... Agent: Volentine & Whitt PLLC

20080203429 - Semiconductor device and a method of manufacturing the same: In a semiconductor device with a shared contact, a gate electrode is formed via a gate insulating film on a semiconductor substrate and a sidewall insulating film is formed on both side faces of the gate electrode. At least one of the surface parts of the semiconductor substrate adjacent to... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080203427 - Semiconductor device having a strained semiconductor alloy concentration profile: A new technique enables providing a stress-inducing alloy having a highly stress-inducing region and a region which is processable by standard processing steps suitable for use in a commercial high volume semiconductor device manufacturing environment. The regions may be formed by a growth process with a varying composition of the... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20080203430 - Enhancement mode insulated gate heterostructure field-effect transistor: Aspects of the present invention provide an enhancement mode (E-mode) insulated gate (IG) double heterostructure field-effect transistor (DHFET) having low power consumption at zero gate bias, low gate currents, and/or high reliability. An E-mode HFET in accordance with an embodiment of the invention includes: top and bottom barrier layers; and... Agent: Hoffman Warnick LLC

20080203431 - Gan-based nitric oxide sensors and methods of making and using the same: GaN-based heterojunction field effect transistor (HFET) sensors are provided with engineered, functional surfaces that act as pseudo-gates, modifying the drain current upon analyte capture. In some embodiments, devices for sensing nitric oxide (NO) species in a NO-containing fluid are provided which comprise a semiconductor structure that includes a pair of... Agent: Nixon & Vanderhye, PC

20080203433 - High electron mobility transistor and method of forming the same: A high electron mobility transistor includes first, second and third compound semiconductor layers. The second compound semiconductor layer has a first interface with the first compound semiconductor layer. The third compound semiconductor layer is disposed over the first compound semiconductor layer. The third compound semiconductor layer has at least one... Agent: Wood, Herron & Evans, LLP

20080203432 - Semiconductor device and method for fabricating the same: A transistor including a gate insulation layer, a gate, and source/drain regions, the transistor comprising a semiconductor layer formed under the gate insulation layer for use as a channel region in a substrate, wherein the semiconductor layer is formed of a material having a lower bandgap than silicon.... Agent: Townsend And Townsend And Crew, LLP

20080203434 - Semiconductor device with a bipolar transistor and method of manufacturing such a device: The invention relates to a semiconductor device (10) with a substrate and a semiconductor body of silicon comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) which are respectively of the N-type conductivity, the P-type conductivity and the N-type conductivity by... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080203436 - Semiconductor device and layout method of decoupling capacitor thereof: A semiconductor device and a layout method of a decoupling capacitor thereof are disclosed. The semiconductor device includes a main power/ground voltage voltage supplying line arranged in a first direction; a plurality of decoupling capacitor cells to reduce power noise generated by the power voltage and the ground voltage in... Agent: Mills & Onello LLP

20080203435 - Semiconductor device having elongated electrostatic protection element along long side of semiconductor chip: An electrostatic protection element is disposed commonly to a plurality of output circuits along a long side of an output circuit region. More preferably, the electrostatic protection element should be disposed between a Pch region and an Nch region of an output circuit.... Agent: Mcginn Intellectual Property Law Group, PLLC

20080203438 - Demultiplexers using transistors for accessing memory cell arrays: A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2N semiconductor regions which are parallel to one another and run in a first direction; (c) first N gate electrode lines, which (i) run in a second direction which is perpendicular to the first... Agent: Schmeiser, Olsen & Watts

20080203437 - Semiconductor integrated circuit device with reduced leakage current: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low... Agent: Stanley P. Fisher Reed Smith LLP

20080203439 - Semiconductor integrated circuit having plural transistors: A layout for placing a circuit having a plurality of transistors in a small-width region. A search section inputs data on a circuit and searches for a set of routes formed so that passage through a transistor occurs only one time and so that the combination of routes covers the... Agent: Young & Thompson

20080203442 - Hybrid orientation soi substrates, and method for forming the same: The present invention relates to a hybrid orientation semiconductor-on-insulator (SOI) substrate structure that contains a base semiconductor substrate with one or more first device regions and one or more second device regions located over the base semiconductor substrate. The one or more first device regions include an insulator layer with... Agent: Scully, Scott, Murphy & Presser, P.C.

20080203440 - Semiconductor device fabrication method and semiconductor device fabricated thereby: A method of fabricating a semiconductor device having a pair of shallow silicided source and drain junctions with minimal leakage is disclosed. The semiconductor device typically has a MISFET structure with NiSi regions partially making up the source and drain regions. The fabrication method includes the steps of providing silicon... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080203441 - Sic semiconductor device and method for manufacturing the same: A SiC semiconductor device having a MOS structure includes: a SiC substrate; a channel region providing a current path; first and second impurity regions on upstream and downstream sides of the current path, respectively; and a gate on the channel region through the gate insulating film. The channel region for... Agent: Posz Law Group, PLC

20080203443 - Independently-double-gated transistor memory (idgm): Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are... Agent: Robert Frohwerk

20080203444 - Multi-finger transistor and method of manufacturing the same: A multi-finger transistor and method of manufacturing the same are provided. The multi-finger transistor includes two active regions, a multi-finger gate, a plurality of source regions and a plurality of drain regions. The two active regions are defined in a unit cell of a substrate. The multi-finger gate includes a... Agent: Harness, Dickey & Pierce, P.L.C

20080203445 - Three-dimensional cascaded power distribution in a semiconductor device: An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a... Agent: Ryan, Mason & Lewis, LLP

20080203446 - Composite contact for semiconductor device: A composite contact for a semiconductor device is provided. The composite contact includes a DC conducting electrode that is attached to a semiconductor layer in the device, and a capacitive electrode that is partially over the DC conducting electrode and extends beyond the DC conducting electrode. The composite contact provides... Agent: Hoffman Warnick LLC

20080203447 - Low-temperature electrically activated gate electrode and method of fabricating same: A gate electrode structure is provided, which includes, from bottom to top, an optional, yet preferred metallic layer, a Ge rich-containing layer and a Si rich-containing layer. The sidewalls of the Ge rich-containing layer include a surface passivation layer. The inventive gate electrode structure serves as a low-temperature electrically activated... Agent: Scully, Scott, Murphy & Presser, P.C.

20080203449 - Source/drain stressor and method therefor: A method for forming a semiconductor device is provided. The method includes forming a gate structure overlying a substrate. The method further includes forming a sidewall spacer adjacent to the gate structure. The method further includes performing an angled implant in a direction of a source side of the semiconductor... Agent: Freescale Semiconductor, Inc. Law Department

20080203448 - Stressed dielectric devices and methods of fabricating same: A structure and a method of making the structure. The structure includes a field effect transistor including: a first and a second source/drain formed in a silicon substrate, the first and second source/drains spaced apart and separated by a channel region in the substrate; a gate dielectric on a top... Agent: Schmeiser, Olsen & Watts

20080203450 - Photoelectric conversion apparatus and image pickup system using photoelectric conversion apparatus: A photoelectric conversion apparatus includes: a first interlayer insulation film disposed on a semiconductor substrate; a first plug disposed in a first hole in the first interlayer insulation film, and serving to electrically connect between a plurality of active regions disposed in the semiconductor substrate, between gate electrodes of a... Agent: Fitzpatrick Cella Harper & Scinto

20080203451 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same are provided, in which an N type region of a photodiode is prevented from adjoining a device isolation film and a dark current is reduced. The CMOS image sensor includes an interlayer dielectric film formed between a gate poly... Agent: Mckenna Long & Aldridge LLP

20080203452 - Cmos image sensors including backside illumination structure and method of manufacturing image sensor: An image sensor having a backside illumination structure can include a photo diode unit in a first wafer, where the photo diode unit includes photo diodes and transfer gate transistors coupled to respective ones of the photo diodes. A wiring line unit can be included on a second wafer that... Agent: Myers Bigel Sibley & Sajovec

20080203453 - Semiconductor structures and memory device constructions: The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as... Agent: Knobbe Martens Olson & Bear LLP

20080203454 - Semiconductor device and method of manufacturing the same: To provide a semiconductor device having a memory element, and which is manufactured by a simplified manufacturing process. A method of manufacturing a semiconductor device includes, forming a first insulating film to cover a first semiconductor film and a second semiconductor film; forming a first conductive film and a second... Agent: Nixon Peabody, LLP

20080203456 - Dynamic random access memory devices and methods of forming the same: Dynamic random access memory (DRAM) devices include first node pads and second node pads alternately arranged in a first direction on a substrate to form a first pad column. A width of the second node pads in a second direction, perpendicular to the first direction, is greater than a width... Agent: Myers Bigel Sibley & Sajovec

20080203455 - Semiconductor device employing transistor having recessed channel region and method of fabricating the same: A semiconductor device employing a transistor having a recessed channel region and a method of fabricating the same is disclosed. A semiconductor substrate has an active region. A trench structure is defined within the active region. The trench structure includes an upper trench region adjacent to a surface of the... Agent: Marger Johnson & Mccollom, P.C.

20080203457 - Fast switching power insulated gate semiconductor device: An insulated gate semiconductor device (30) includes a gate (34), a source terminal (36), a drain terminal (38) and a variable input capacitance at the gate. A ratio between the input capacitance (Cfiss) when the device is on and the input capacitance Ciiss when the device is off is less... Agent: Alston & Bird LLP

20080203458 - Semiconductor memory device and method of fabricating the same: This patent relates to a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include a semiconductor substrate in which a tunnel insulating layer, and a first conductive layer. At least a portion of the semiconductor substrate is removed to form a trench. A... Agent: Marshall, Gerstein & Borun LLP

20080203460 - Manufacturing method for a nanocrystal based device covered with a layer of nitride deposited by cvd: i

20080203459 - Method of manufacturing a semiconductor device and semiconductor device: A carrier is structured with isolation regions in a precise fashion. First structures and second structures are formed above a carrier. At least one of the second structures is removed selectively with respect to the first structures. At least one recess in the carrier is formed according to the structure... Agent: Slater & Matsil, L.L.P.

20080203462 - Finfet-based non-volatile memory device: A non-volatile memory device on a substrate layer (2) comprises source and drain regions (3) and a channel region (4). The source and drain regions (3) and the channel region (4) are arranged in a semiconductor layer (20) on the substrate layer (2). The channel region (4) is fin-shaped and... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080203461 - Gate structure of nand flash memory having insulators each filled with between gate electrodes of adjacent memory cells and manufacturing method thereof: A semiconductor device includes first and second gate electrodes arranged adjacent to each other, an oxide film formed between the first and second gate electrodes, and a nitride film formed on control gates and upper surfaces and sidewalls of the oxide film. Each of the first and second gate electrodes... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080203463 - Non-volatile memory with erase gate on isolation zones: The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate (16), a control gate (19) and a separate erase gate (10). The erase gate (10) is provided in or on isolation zones (2) provided in the substrate (1).... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080203464 - Electrically alterable non-volatile memory and array: A memory device, array and method of arranging where the memory device includes a memory cell region including a plurality of memory cells. Each memory cell includes a source, a drain and a channel between the source and the drain, a channel dielectric, a charge storage region and an electrically... Agent: Harness, Dickey & Pierce P.L.C

20080203465 - Semiconductor device and method for manufacturing the same: The present invention provides a method for manufacturing a semiconductor device including the steps of forming a flash memory cell provided with a floating gate, an intermediate insulating film, and a control gate, forming first and second impurity diffusion regions, thermally oxidizing surfaces of a silicon substrate and the floating... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080203466 - Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080203467 - Nrom flash memory devices on ultrathin silicon: An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20080203468 - Finfet with reduced gate to fin overlay sensitivity: Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction.... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080203469 - Integrated circuit including an array of memory cells having dual gate transistors: An integrated circuit including an array of memory cells having dual gate transistors with curved current flow, and method for operation and fabrication is disclosed. In one embodiment, in a substrate an array of transistors is formed for selecting one of a plurality of memory cells by selecting a pair... Agent: Dicke, Billig & Czaja

20080203470 - Lateral compensation component: A transistor is provided which includes a lateral compensation component. The lateral compensation component includes a plurality of n (or n−) layer/p (or p−) layer pairs, wherein adjacent ones of said pairs are separated by one of an insulator region and/or an intrinsic silicon region.... Agent: Davidson, Davidson & Kappel, LLC Infineon Technologies Ag

20080203471 - Nitride semiconductor device and method for producing nitride semiconductor device: The nitride semiconductor device includes: a nitride semiconductor structure comprising an n-type first layer, a p-type second layer, and an n-type third layer, the nitride semiconductor structure comprising a mesa structure having a lateral surface which forms a wall surface extending from the first, second, to third layers; a gate... Agent: Rabin & Berdo, PC

20080203472 - Lateral mosfet and manufacturing method thereof: A lateral MOSFET according to the present invention has a trench gate structure having a cross sectional shape spreading toward an open end.... Agent: Sughrue Mion, PLLC

20080203473 - Lateral field-effect transistor having an insulated trench gate electrode: A field-effect transistor having cells (18) each having a source region (22), source body region (26), drift region (20), drain body region (28) and drain region (24) arranged longitudinally, laterally alternating with structures to achieve a reduced surface field. In embodiments, the structures can include longitudinally spaced insulated gate trenches... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080203474 - Semiconductor device having offset spacer and method of forming the same: A method of forming a semiconductor device having an offset spacer may include forming a gate electrode on a semiconductor substrate. An etch stop layer including a nitride may be formed on the entire surface of the semiconductor substrate having the gate electrode. First spacers may be formed on the... Agent: Harness, Dickey & Pierce, P.L.C

20080203475 - Semiconductor device and method of fabricating the same: An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080203478 - High frequency switch with low loss, low harmonics, and improved linearity performance: A switch element includes a field effect transistor (FET) structure formed on a substrate, the FET structure having a drain, a gate and a source, the drain having a drain capacitance, the gate having a gate capacitance, the source having a source capacitance and an electrical connection to couple the... Agent: Michael J. Tempel Smith Frohwein Tempel Greenlee Blaha LLC

20080203477 - Semiconductor device: Plural kinds of thin film transistors having different film thicknesses of semiconductor layers are provided over a substrate having an insulating surface. A channel formation region of semiconductor layer in a thin film transistor for which high speed operation is required is made thinner than a channel formation region of... Agent: Nixon Peabody, LLP

20080203479 - Semiconductor device: In a PMOS transistor, the source-drain region is divided into four parts along the gate width and has an arrangement of four independent source regions and an arrangement of four independent drain regions. A partial trench isolation insulating film is arranged in contact with the whole of the opposed surfaces... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080203476 - Semiconductor device having strip-shaped channel and method for manufacturing such a device: The invention relates to a semiconductor device (10) consisting of a substrate (11) and a semiconductor body (2) comprising a strip-shaped semiconductor region (3,3A,3B) of silicon in which a field effect transistor is formed, wherein a source region (4) of a first conductivity type, a channel region (33) of a... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080203480 - Integrated circuit using a superjunction semiconductor device: In an embodiment, an apparatus includes a source region, a gate region and a drain region supported by a substrate, and a drift region including a plurality of vertically extending n-wells and p-wells to couple the gate region and the drain region of a transistor, wherein the plurality of n-wells... Agent: Schwegman, Lundberg & Woessner / Infineon

20080203481 - Nonvolatile semiconductor memory and method of manufacturing the same: A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080203482 - Transistors having gate pattern for self-alignment with channel impurity diffusion region in active region and methods of forming the same: A transistor having a gate pattern suitable for self-alignment with a channel impurity diffusion region in an active region includes an active region and an isolation layer disposed in a semiconductor substrate. The isolation layer is formed to define the active region. An insulating layer covering the active region and... Agent: Mills & Onello LLP

20080203483 - Semiconductor device including a recessed-channel-array misfet: A semiconductor device includes RCA MISFETs formed in active regions of a semiconductor substrate, the active regions being defined by shallow-trench-isolation (STI) structure. The top surface of the insulating film is flush with the top surface of the active regions. The gate electrode of each MISFET includes a first portion... Agent: Young & Thompson

20080203488 - Cmos semiconductor device and method of fabricating the same: Example embodiments provide a complementary metal-oxide semiconductor (CMOS) semiconductor device and a method of fabricating the CMOS semiconductor device. The CMOS semiconductor device may include gates in the nMOS and pMOS areas, polycrystalline silicon (poly-Si) capping layers, metal nitride layers underneath the poly-Si capping layers, and a gate insulating layer... Agent: Harness, Dickey & Pierce, P.L.C

20080203489 - Ensuring migratability of circuits by masking portions of the circuits while improving performance of other portions of the circuits: Mechanisms for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency are provided. A mask layer is introduced to portions of the integrated circuit prior to a stress inducing layer being applied to the integrated circuit. In an exemplary embodiment, a... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080203484 - Field effect transistor arrangement and method of producing a field effect transistor arrangement: A field effect transistor arrangement and a fabrication method thereof. The field effect transistor arrangement includes: a substrate having a first crystal surface orientation; a first layer formed above at least a first portion of the substrate, the first layer having a second crystal surface orientation different from the first... Agent: Dickstein Shapiro LLP

20080203487 - Field effect transistor having an interlayer dielectric material having increased intrinsic stress: By providing a highly stressed interlayer dielectric material, the performance of at least one type of transistor may be increased due to an enhanced strain-inducing mechanism. For instance, by providing a highly compressive silicon dioxide of approximately 400 Mega Pascal and more as an interlayer dielectric material, the drive current... Agent: Williams, Morgan & Amerson

20080203486 - Method for differential spacer removal by wet chemical etch process and device with differential spacer structure: By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20080203485 - Strained metal gate structure for cmos devices with improved channel mobility and methods of forming the same: A gate structure for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack having a first gate dielectric layer formed over a substrate, and a first metal layer formed over the first gate dielectric layer. A second gate stack includes a second gate dielectric layer formed over the... Agent: Cantor Colburn LLP - IBM Fishkill

20080203490 - Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for bicmos integration: High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy,... Agent: Scully, Scott, Murphy & Presser, P.C.

20080203491 - Radiation hardened finfet: The embodiments of the invention provide a structure and method for a rad-hard FinFET or mesa. More specifically, a semiconductor structure is provided having at least one fin or mesa comprising a channel region on an isolation region. A doped substrate region is also provided below the fin, wherein the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080203492 - Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods: Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080203493 - Semiconductor memory device and fabrication process thereof: A SRAM includes a first CMOS inverter of first and second MOS transistors connected in series, a second CMOS inverter of third and fourth MOS transistors connected in series and forming a flip-flop circuit together with the first CMOS inverter, and a polysilicon resistance element formed on a device isolation... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080203494 - Apparatus and method for reducing noise in mixed-signal circuits and digital circuits: Apparatus and a method are provided for reducing noise in mixed-signal and digital circuits. One apparatus (200) includes a metal-oxide-semiconductor field-effect transistor (MOSFET) (210). MOSFET (210) includes a doped substrate (2210) with a source formed proximate a substrate tie (2224) and a substrate tie (2250) adjacent substrate (2210). A ground... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080203495 - Integration circuits for reducing electromigration effect: An integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii) electrically coupled to the... Agent: Schmeiser, Olsen & Watts

20080203496 - Semiconductor device: A gate electrode 20 and first field plates 22a to 22d and 23 are provided on a field oxide film 19. The gate electrode 20 and first field plates 22a to 22d and 23 are covered with an insulating film 24. A high-voltage wiring conductor 28 is provided on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080203497 - Semiconductor devices including assymetric source and drain regions having a same width and related methods: A semiconductor device may include an active region of a semiconductor substrate and first and second impurity regions in the active region. The active region may have a first conductivity type, the first and second impurity regions may have a second conductivity type opposite the first conductivity type, and the... Agent: Myers Bigel Sibley & Sajovec

20080203498 - Semiconductor device and manufacturing method of semiconductor device: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate; a first gate dielectric layer provided on the semiconductor substrate, the relative dielectric constant ratio of the first gate dielectric layer being no less than 8; a second gate dielectric layer provided on the semiconductor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080203500 - Semiconductor device and production method therefor: A semiconductor device provided with a MIS type field effect transistor comprising a silicon substrate, a gate insulating film having a high-dielectric-constant metal oxide film which is formed on the silicon substrate via a silicon containing insulating film, a silicon-containing gate electrode formed on the gate insulating film, and a... Agent: Mcginn Intellectual Property Law Group, PLLC

20080203499 - Semiconductor device having gate insulator including high-dielectric-constant materials and manufacture method of the same: A semiconductor device includes a semiconductor substrate, an insulating layer and a conductive layer disposed on the second insulator, the insulating layer including a first insulator containing silicon and oxygen, an intermediate region containing a metal element, silicon, oxygen and nitrogen, and a second insulator containing the metal element and... Agent: Rabin & Berdo, PC

20080203501 - Semiconductor device: A semiconductor device with higher reliability and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor layer overlapping with a gate electrode and having an impurity region outside a region which overlaps with the gate electrode; a first conductive layer which is provided on a side provided... Agent: Nixon Peabody, LLP

20080203502 - Self-addressable self-assembling microelectronic systems and devices for molecular biological analysis and diagnostics: A self-addressable, self-assembling microelectronic device is designed and fabricated to actively carry out and control multi-step and multiplex molecular biological reactions in microscopic formats. These reactions include nucleic acid hybridization, antibody/antigen reaction, diagnostics, and biopolymer synthesis. The device can be fabricated using both microlithographic and micro-machining techniques. The device can... Agent: O''melveny & Myers LLP Ip&t Calendar Department La-1118

20080203503 - Magnetic random access memory: A magnetic random access memory includes a first bit line and a second bit line, a source line formed for a group having the first bit line and the second bit line, adjacent to the first bit line, and running in a first direction in which the first bit line... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080203505 - Magnetic random access memory with selective toggle memory cells: A toggle MTJ is disclosed that has a SAF free layer with two or more magnetic sub-layers having equal magnetic moments but different anisotropies which is achieved by selecting Ni˜0.8Fe˜0.2 for one sub-layer and CoFeB or the like with a uni-axial anisotropy of 10 to 30 Oe for the higher... Agent: Saile Ackerman LLC

20080203504 - Magneto-resistance transistor and method thereof: A magneto-resistance transistor including a magneto-resistant element which may function as an emitter and a passive element which may function as a collector. The base may be interposed between the passive element and the magneto-resistant element, thereby coupling the passive element with the magneto-resistant element. A magnetic field of a... Agent: Rabin & Berdo, PC

20080203506 - Capacitive junction modulator, capacitive junction and method for making same: The invention concerns a capacitive junction including a region adapted to be traversed by an electromagnetic wave, and a dielectric layer interposed between two semiconductor material layers. The dielectric layer has a reduced thickness at the region, that is a thickness at the region less than its thickness at a... Agent: Brinks Hofer Gilson & Lione

20080203508 - Image sensing device having protection pattern on the microlens, camera module, and method of forming the same: An image sensing device having a protection pattern formed on microlenses is provided. The device includes a plurality of photodiodes provided in a semiconductor substrate. An insulating layer having a substantially flat top surface is disposed on the photodiodes. A plurality of microlenses are provided on the insulating layer and... Agent: Mills & Onello LLP

20080203507 - Image sensors for zoom lenses and fabricating methods thereof: An image sensor includes a semiconductor substrate on which a plurality of photo diodes are formed. A plurality of interlayer dielectrics are formed above the semiconductor substrate, and a plurality of metal lines are formed on each of the interlayer dielectrics. A plurality of micro lenses are formed above the... Agent: Harness, Dickey & Pierce, P.L.C

20080203509 - Photoelectric conversion devise and method of manufacturing the same: A photoelectric conversion device comprises a photoelectric conversion element disposed at a semiconductor substrate, and a multilayered wiring structure including a plurality of wiring layers disposed over the semiconductor substrate in such a manner to sandwich an interlayer insulation film therebetween. A diffusion suppressing film is disposed at least on... Agent: Fitzpatrick Cella Harper & Scinto

20080203510 - Optical module: An optical module of the present invention includes: a semiconductor device 14; a grounded metal member 10 for mounting the semiconductor device 14 thereon; a substrate 16 for mounting the grounded metal member 10 thereon; and a lead pin 18 fixed to and insulated from the grounded metal member 10... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080203512 - Image sensor chip package: A chip package includes a carrier (32), an image sensor chip (34), a plurality of wires (36), an adhesive means (3262) and a transparent cover (38). The carrier has a cavity (321) therein. The image sensor chip is received in the cavity, and the image sensor has a photosensitive area... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang

20080203511 - Sensor-type semiconductor package and method for fabricating the same: The present invention provides a sensor-type semiconductor package and a method for fabricating the same. The method includes the steps of: providing a wafer having a plurality of sensor chips for mounting the wafer on a carrier board having an insulation layer, a plurality of conductive traces, and a substrate;... Agent: Edwards Angell Palmer & Dodge LLP

20080203513 - Semiconductor integrated device having solid-state image sensor packaged within and production method for same: A semiconductor integrated device comprises: a light-shielding film which shields at least some part of a transfer section of the semiconductor integrated device from light; a first wiring formed in the same layer as the light-shielding film, with one end connected to a pad electrode and an other end extended... Agent: Hogan & Hartson L.L.P.

20080203514 - High performance cdxzn1-xte x-ray and gamma ray radiation detector and method of manufacture thereof: The present invention is a radiation detector that includes a crystalline substrate formed of a II-VI compound and a first electrode covering a substantial portion of one surface of the substrate. A plurality of second, segmented electrodes is provided in spaced relation on a surface of the substrate opposite the... Agent: The Webb Law Firm, P.C.

20080203515 - Photoelectric conversion device and electronic device, and method for manufacturing photoelectric conversion device: A photoelectric conversion device includes: a first substrate of which end portions are cut off so as to slope or with a groove shape; a photodiode and an amplifier circuit over the first substrate; a first electrode electrically connected to the photodiode and provided over one end portion of the... Agent: Eric Robinson

20080203516 - Image device and method of fabricating the same: An image device and a method of fabricating the image device include a substrate pattern formed to define an opening and to include a portion of a photodiode for receiving light. Stacked metal interconnection patterns and an interlayer dielectric layer are formed beneath the substrate pattern. A height of the... Agent: Volentine & Whitt PLLC

20080203517 - Semiconductor component having rectifying junctions and method for producing the same: A semiconductor component is proposed which has a semiconductor body having a first semiconductor zone of the first conduction type, at least one first rectifying junction with respect to the first semiconductor zone, at least one second rectifying junction with respect to the first semiconductor zone, wherein the three rectifying... Agent: Dickstein Shapiro LLP

20080203518 - Method for positioning sub-resolution assist features: The present application is directed to a method of selectively positioning sub-resolution assist features (SRAF) in a photomask pattern for an interconnect. The method comprises determining if a first interconnect pattern option will result in improved circuit performance compared with a second interconnect pattern option, where the first option is... Agent: Texas Instruments Incorporated

20080203519 - Microelectronic assembly with improved isolation voltage performance and a method for forming the same: A method for forming a microelectronic assembly and a microelectronic assembly are provided. First and second semiconductor devices (72) are formed over a substrate (20) having a first dopant type at a first concentration. First and second buried regions (28) having a second dopant type are formed respectively below the... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080203520 - Isolation structure for semiconductor integrated circuit substrate: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of... Agent: Patentability Associates

20080203521 - Semiconductor substrate, semiconductor device, method for manufacturing semiconductor substrate, and method for manufacturing semiconductor device: A semiconductor substrate comprising: a semiconductor base; dielectric layers of mutually different film thicknesses formed on the semiconductor base; and semiconductor layers of mutually different film thicknesses formed on the dielectric layers.... Agent: Edwards Angell Palmer & Dodge LLP

20080203522 - Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates: Device structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes latch-up resistant devices formed on a hybrid substrate. The hybrid substrate is characterized by first and second semiconductor regions that are formed on a bulk semiconductor region. The second... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080203523 - Localized temperature control during rapid thermal anneal: Disclosed herein are embodiments of a semiconductor structure and an associated method of forming the semiconductor structure with shallow trench isolation structures having selectively adjusted reflectance and absorption characteristics in order to ensure uniform temperature changes across a wafer during a rapid thermal anneal and, thereby, limit variations in device... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080203524 - Localized temperature control during rapid thermal anneal: Disclosed are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal and, thereby, to selectively control variations in device performance and/or to selectively optimize the anneal temperature of such... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080203525 - Capacitance trimming circuit of semiconductor device having vertically stacked capacitor layers and operation method thereof: A capacitance trimming circuit of a semiconductor device may include a plurality of capacitor layers and/or a plurality of fuses. The plurality of capacitor layers may be vertically stacked. The plurality of fuses may be arranged to correspond to the plurality of capacitor layers, and/or the plurality of fuses may... Agent: Harness, Dickey & Pierce, P.L.C

20080203526 - Semiconductor device equipped with thin-film circuit elements: A plurality of wirings, column-shaped electrodes, sealing films, and soldering balls, are provided on a third upper-layer insulating film formed on a silicon substrate. A spirally configured thin-film inductive element is disposed beneath the bottom surface of a ground insulating film formed beneath the silicon substrate. The inner and outer... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080203527 - Semiconductor device having gate electrode connection to wiring layer: A semiconductor device includes a semiconductor substrate having an electrode formed above a surface thereof; a first insulating resin layer that is provided over the semiconductor substrate and has a first opening defined at a position corresponding to the electrode; a first wiring layer that is provided on the first... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080203528 - Metal-insulator-metal capacitor and method for fabricating the same: A metal-insulator-metal (MIM) capacitor that includes a silicon nitride (SiN) dielectric film is disclosed. The MIM capacitor includes a bottom electrode, a top electrode and a dielectric layer positioned between the bottom electrode and the top electrode. The dielectric layer includes a silicon nitride film that has a plurality of... Agent: North America Intellectual Property Corporation

20080203530 - Semiconductor device and method of producing the same: A semiconductor device includes a silicon substrate; a first interlayer insulating film provided on the silicon substrate; and a capacitor that is provided on the first interlayer insulating film and that includes a lower electrode, a capacitor dielectric film made of a ferroelectric substance, and an upper electrode, wherein the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080203529 - Semiconductor device comprising multilayer dielectric film and related method: A semiconductor device including a multilayer dielectric film and a method for fabricating the semiconductor device are disclosed. The multilayer dielectric film includes a type-one dielectric film having a tetragonal crystalline structure, wherein the type-one dielectric film comprises a first substance. The multilayer dielectric film also comprises a type-two dielectric... Agent: Volentine & Whitt PLLC

20080203531 - Semiconductor device and manufacturing method thereof: In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080203532 - Semiconductor device and method of manufacturing the same: A semiconductor device having a transistor circuit and a bleeder resistance circuit is provided in which fluctuations in resistance value of a bleeder resistor are reduced. In the transistor circuit, a barrier metal film and a interconnect film are layered as a metal film on an interlayer insulating film above... Agent: Brinks Hofer Gilson & Lione

20080203533 - Semiconductor device: A semiconductor device includes a principal IGBT controllable in accordance with a gate voltage applied to a gate electrode thereof, a current detecting IGBT connected to the principal IGBT in parallel and a current detecting part including a detecting resistor capable of detecting a current passing through the current detecting... Agent: Mcdermott Will & Emery LLP

20080203534 - Complementary zener triggered bipolar esd protection: An electrostatic discharge (ESD) protection clamp (61) for I/O terminals (22, 23) of integrated circuits (ICs) (24) comprises an NPN bipolar transistor (25) coupled to an integrated Zener diode (30). Variations in the break-down current-voltage characteristics (311, 312, 313, 314) of multiple prior art ESD clamps (31) in different parts... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080203535 - Semiconductor device: A semiconductor device relating to the present invention comprises a base layer of an N-type impurity region. In the base layer, trenches are provided. In the each trench, a gate insulating film and a gate electrode are formed. A body layer of a P-type impurity region is formed in contact... Agent: Mcdermott Will & Emery LLP

20080203536 - Bipolar transistor using selective dielectric deposition and methods for fabrication thereof: A bipolar transistor structure and related methods for fabrication thereof are provided. A vertical spacer layer is selectively deposited after implanting an extrinsic base region into a semiconductor substrate while using an ion implantation mask located upon a screen dielectric layer located upon the semiconductor substrate. A portion of the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080203537 - Differential junction varactor: Structure and methods for a differential junction varactor. The structure includes: a silicon first region formed in a silicon substrate, the first region of a first dopant type; and a plurality of silicon second regions in physical and electrical contact with the first region, the plurality of second regions spaced... Agent: Schmeiser, Olsen & Watts

20080203538 - Semiconductor wafer with division guide pattern: A plurality of semiconductor elements and division regions are provided on a semiconductor subsubstrate. A modification region is provided in the semiconductor substrate. A division guide pattern is provided at least in a portion of each division region. A cleavage produced from a starting point corresponding to the modification region... Agent: Steptoe & Johnson LLP

20080203539 - Semiconductor components with conductive interconnects: A semiconductor component includes a semiconductor substrate having at least one conductive interconnect on the backside thereof bonded to an inner surface of a substrate contact. A stacked semiconductor component includes multiple semiconductor components in a stacked array having bonded connections between conductive interconnects on adjacent components. An image sensor... Agent: Stephen A Gratton The Law Office Of Steve Gratton

20080203540 - Structure and method for device-specific fill for improved anneal uniformity: Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080203541 - Semiconductor device and manufacturing method of the same: A protective insulation film covering a surface of a compound semiconductor region is formed to have a two-layer structure of a first insulation film and a second insulation film which have different properties. The first insulation film is a non-stoichiometric silicon nitride film while the second insulation film is a... Agent: Kratz, Quintos & Hanson, LLP

20080203542 - Ion-assisted oxidation methods and the resulting structures: Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions,... Agent: Trask Britt, P.C./ Micron Technology

20080203543 - Semiconductor integrated circuit substrate containing isolation structures: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of... Agent: Patentability Associates

20080203544 - Semiconductor wafer structure with balanced reflectance and absorption characteristics for rapid thermal anneal uniformity: Disclosed are embodiments of semiconductor wafer structures and associated methods of forming the structures with balanced reflectance and absorption characteristics. The reflectance and absorption characteristics are balanced by manipulating thin film interferences. Specifically, thin film interferences are manipulated by selectively varying the thicknesses of the different films. Alternatively, reflectance and... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080203545 - Semiconductor device and method of fabrication thereof: A ground line is exposed by removing a surface protecting film, which covers an uppermost metal wiring layer, and providing an opening portion at a portion of a top surface of a semiconductor chip, which portion is within a region contacted by a collet in a pick-up process and corresponds... Agent: Volentine & Whitt PLLC

20080203546 - Quad flat no-lead chip carrier with stand-off: A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed... Agent: John A. Jordan, Esq.

20080203547 - Insert molded leadframe assembly: An insert molded leadframe assembly (IMLA) for an electrical connector is disclosed. The IMLA may include an array of electrically conductive contacts, a dielectric leadframe housing overmolded onto the array of contacts, and a mass disposed within the leadframe housing. The additional mass may shift the IMLA's center of gravity,... Agent: Woodcock Washburn, LLP

20080203548 - High current semiconductor power device soic package: A high current semiconductor power SOIC package is disclosed. The package includes a relatively thick lead frame formed of a single gauge material having a thickness greater than 8 mils, the lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including... Agent: Schein & Cai LLP

20080203549 - Stackable integrated circuit package system with multiple interconnect interface: A stackable integrated circuit package system includes: forming a first integrated circuit die having a small interconnect and a large interconnect provided thereon; forming an external interconnect, having an upper tip and a lower tip, from a lead frame; mounting the first integrated circuit die on the external interconnect with... Agent: Law Offices Of Mikio Ishimaru

20080203550 - Component, power component, apparatus, method of manufacturing a component, and method of manufacturing a power semiconductor component: A component has a device applied to a device carrier, a first conducting layer grown onto the device and onto the device carrier, and an insulating material applied to the first conducting layer such that only a portion of the first conducting layer is covered.... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20080203551 - Multi-chip module and single-chip module for chips and proximity connectors: A single-chip module is described. The module includes a first semiconductor die having a first surface and a second surface. The first semiconductor die is configured to communicate by capacitive coupling using one or more of a plurality of proximity connectors coupled to the first semiconductor die. A cable coupled... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20080203554 - Semiconductor integrated circuit device: A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane... Agent: Sughrue Mion, PLLC

20080203553 - Stackable bare-die package: A stackable bare-die package primarily comprises a substrate, a chip, a plurality of bonding wires and an encapsulant. The substrate has a slot where a step is formed inside the slot where a plurality of inner fingers are disposed on the step. A plurality of outer pads are disposed on... Agent: Troxell Law Office PLLC

20080203552 - Stacked package and method of fabricating the same: Disclosed herein is a stacked package. The stacked package includes two or more of a first BGA package and a second BGA package and a circuit board having a circuit pattern. The first BGA package is mounted on one face of the circuit board, and the second BGA package is... Agent: Dickinson Wright PLLC

20080203555 - Universal substrate and semiconductor device utilizing the substrate: A universal substrate and a semiconductor device utilizing the substrate are disclosed in the present invention. The universal substrate mainly comprises a plurality of inner pads and a plurality of outer pads. A plurality of bifurcate wirings and a plurality of fuses are formed on a surface of the substrate.... Agent: Troxell Law Office PLLC

20080203556 - Through-wafer interconnection: A through-wafer interconnect and a method for fabricating the same are disclosed. The method starts with a conductive wafer to form a patterned trench by removing material of the conductive wafer. The patterned trench extends in depth from the front side to the backside of the wafer, and has an... Agent: Lee & Hayes, PLLC

20080203557 - Semiconductor module and method of manufacturing the same: Warp of a circuit device manufactured by the wafer level packaging technology is reduced. A semiconductor substrate used in a circuit device is provided with a circuit device and electrodes connected to the circuit device. A wiring layer having bumps connected to the electrodes is provided on a major surface... Agent: Fish & Richardson P.C.

20080203558 - Method of semiconductor device protection, package of semiconductor device: A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080203559 - Power device package and semiconductor package mold for fabricating the same: Provided are a power device package coupled to a heat sink using a bolt and a semiconductor package mold for fabricating the same. The power device package includes: a substrate; at least one power device mounted on the substrate; a mold member sealing the substrate and the power device; and... Agent: Townsend And Townsend And Crew, LLP

20080203560 - Semiconductor device: A semiconductor device is produced using a housing having a hollow cavity for embracing a semiconductor sensor chip (e.g., a microphone chip) for detecting pressure variations and an LSI chip for driving the semiconductor sensor chip, both of which are mounted on a chip mount surface. An opening allowing the... Agent: Pillsbury Winthrop Shaw Pittman LLP

20080203561 - High frequency device module and manufacturing method thereof: A high frequency device module of an embodiment of a current invention includes: an insulation substrate in which electrodes are provided on the front surface thereof and a grounding substrate is provided on the rear surface thereof; a high frequency device provided on the insulation substrate with a terminal of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080203562 - Method for designing semiconductor device and semiconductor device: A method for designing a semiconductor device and a semiconductor device of the present invention permits the achievement of a predetermined pattern area ratio while power supply lines are reinforced by connecting a dummy metal line, which is formed in an unoccupied region of a wiring layer for the purpose... Agent: Mcdermott Will & Emery LLP

20080203565 - Semiconductor device and method of manufacturing the same: The semiconductor device 1 includes interconnect layers 10, 20, an IC chip 30, via plugs 42, 44, a seal resin 50, and solder balls 60. The interconnect layer 10 includes a via plug 42. An end face of the via plug 42 on the side of the interconnect layer 20... Agent: Young & Thompson

20080203564 - Semiconductor device having stress alleviating portion positioned at outer circumference of chip, wiring substrate, and method for producing the same: A semiconductor device has a wiring substrate, a semiconductor chip, a conductive bump, and an under-fill resin. The wiring substrate has a solder resist layer, and a stress alleviating portion. The stress alleviating portion is mounted on the solder resist layer opposed to the outer circumference of the semiconductor chip.... Agent: Mcginn Intellectual Property Law Group, PLLC

20080203563 - Semiconductor package and manufacturing method thereof: A COF package in exemplary form includes a flexible base film, inner leads each made of metal and having a thickness d1, which are disposed at a peripheral edge of a semiconductor chip-mounted predetermined spot on the base film and protruded into the semiconductor chip-mounted predetermined spot, dummy patterns having... Agent: Taft, Stettinius & Hollister LLP

20080203568 - Semiconductor device: An improved reliability in a region of a junction between a bonding wire and an electrode pad at higher temperature is achieved. A semiconductor device 100 includes a semiconductor chip 102, AlCu pads 107, which are provided in the semiconductor chip 102 and which contain Al as a major constituent... Agent: Mcginn Intellectual Property Law Group, PLLC

20080203569 - Semiconductor device and manufacturing method thereof: A semiconductor device comprising: a semiconductor substrate which has a plurality of connection pads on a top surface thereof; an insulating film which is provided on the semiconductor substrate and which has a plurality of openings formed at portions corresponding to the connection pads; a plurality of re-wirings each of... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080203567 - Semiconductor package and semiconductor device using the same: A semiconductor package includes a print substrate which has a plurality of wiring layers. The print substrate has a wiring for connect pins extending internally across the plurality of wiring layers from one surface of the print substrate; a wiring for a non connect pin insulated in the thickness direction... Agent: Sughrue Mion, PLLC

20080203566 - Stress buffer layer for packaging process: A semiconductor package structure is provided. The semiconductor package structure includes a first module; a second module, wherein the first and the second modules each are selected from the group consisting essentially of a package substrate, a die and a package module; and an elastic die-attaching film having a hardness... Agent: Slater & Matsil, L.L.P.

20080203571 - Backside metallization for integrated circuit devices: A method of forming backside metallization on a substrate that includes a plurality of integrated circuit die formed on a front side of the substrate is disclosed. The method includes forming an adhesion layer of aluminum or an aluminum alloy on a backside surface of the substrate, forming a barrier... Agent: Williams, Morgan & Amerson

20080203572 - Semiconductor device and method of fabricating the same: The present invention provides a semiconductor device having interconnects, reduced in leakage current between the interconnects and improved in the TDDB characteristic, which comprises an insulating interlayer 108, and interconnects 160 filled in grooves formed in the insulating interlayer, comprising a copper layer 124 mainly composed of copper, having the... Agent: Young & Thompson

20080203570 - Structure including via having refractory metal collar at copper wire and dielectric layer liner-less interface and related method: Structures including a refractory metal collar at a copper wire and dielectric layer liner-less interface, and a related method, are disclosed. In one embodiment, a structure includes a copper wire having a liner-less interface with a dielectric layer thereabove; a via extending upwardly from the copper wire through the dielectric... Agent: Hoffman Warnick LLC

20080203573 - Semiconductor device: Provided is a semiconductor device including first and second wiring layers, and dummy and conductive patterns. The first and second wiring layers each have a hollow structure, and are stacked vertically adjacent to each other on a semiconductor substrate. The dummy pattern is formed in the first wiring layer, and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080203574 - Insulating film material, multilayer interconnection structure, method for manufacturing same, and method for manufacturing semiconductor device: o

20080203575 - Integrated circuit with re-route layer and stacked die assembly: An apparatus and a method of manufacture for a stacked-die assembly. A first die is placed on a substrate such that the backside of the die, i.e., the side opposite the side with the bond pads, is coupled to the substrate, preferably by an adhesive. Wire leads electrically couple the... Agent: Ira S. Matsil Slater & Matsil, L.L.P.

20080203578 - Circuit device, a method for manufacturing a circuit device, and a semiconductor module: A circuit device includes a semiconductor substrate on which a circuit element is formed, an electrode formed on a surface of the semiconductor substrate, an insulating layer formed on the electrode, a second wiring layer formed on the insulating layer, and a conductive bump which penetrates the insulating layer and... Agent: Fish & Richardson P.C.

20080203579 - Sacrificial metal spacer dual damascene: A method and structure for a dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, creating sacrificial tungsten sidewall spacers in the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080203576 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device including, forming a first insulating film above a silicon substrate, forming an impurity layer in the first insulating film by ion-implanting impurities into a predetermined depth of the first insulating film, and modifying the impurity layer to a barrier insulating film by annealing... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080203577 - Semiconductor integrated circuit device and fabrication method for the same: The semiconductor integrated circuit device includes: an active element, an interlayer insulting film, first and second metal patterns made of a first metal layer formed right above the active element, first and second buses made of a second metal layer formed right above the first metal layer, and contact pads... Agent: Mcdermott Will & Emery LLP

20080203580 - Semiconductor chip and shielding structure thereof: A semiconductor chip including a substrate, a metal interconnection structure and a circuit region is provided. The substrate has at least one dielectric ring on a substrate surface of the substrate. The metal interconnection structure is disposed on the substrate surface and has at least one guard ring, wherein the... Agent: J C Patents, Inc.

20080203581 - Integrated circuit: An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first interface layer on a first substrate, the first interface layer including a first signal path, a second interface layer on the first interface layer, the second interface layer including a second signal path, the second signal... Agent: Dicke, Billig & Czaja

20080203582 - Semiconductor device: A semiconductor device having a plurality of semiconductor chips mounted on lead frames is miniaturized by reducing its planar size and thickness. By disposing a rear surface of a first island and a top surface of a second island so as to at least partially overlap each other, a first... Agent: Fish & Richardson P.C.

20080203583 - Semiconductor package and fabrication method thereof: There is provided a semiconductor package comprising: a multilayer thin film structure including a plurality of dielectric layers and at least one or more redistribution layers; a semiconductor chip positioned at one side of the multilayer thin film structure and electrically connected to the redistribution layer; and a solder bump... Agent: Marger Johnson & Mccollom, P.C.

20080203584 - Stacked-type semiconductor package: Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tape. An electric length of the... Agent: Mcdermott Will & Emery LLP

20080203585 - Interconnections for flip-chip using lead-free solders and having reaction barrier layers: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally... Agent: David Aker

20080203586 - Integrated circuit and methods of manufacturing a contact arrangement and an interconnection arrangement: A contact arrangement is manufactured by providing a substrate that includes first regions that are arranged along a row direction and a second region. An interlayer is provided that covers the first regions and the second region. A buried mask including a first trim opening above the first regions is... Agent: Edell, Shapiro & Finnan, LLC

20080203587 - Semiconductor device including conductive lines with fine line width and method of fabricating the same: A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line... Agent: Volentine & Whitt PLLC

20080203588 - Packaged integrated circuit: A packaged integrated circuit has an integrated circuit over a support structure. A plurality of bond wires connected between active terminals of the integrated circuit and the support structure. An encapsulant overlies the support structure, the integrated circuit, and the bond wires. The encapsulant has a first open location in... Agent: Freescale Semiconductor, Inc. Law Department

20080203590 - Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same: An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080203589 - Variable fill and cheese for mitigation of beol topography: A method of designing features on a semiconductor wafer. A design of active or functional features is provided for chiplets separated by kerf areas on the wafer. The method then includes determining pattern density of the chiplet features, and applying a pattern of spaced dummy features on chiplet area not... Agent: Law Office Of Delio & Peterson, LLC.

20080197334 - Phase change memory cell with heater and method for fabricating the same: A memory device with a thin heater forms a programmable resistive change region in a sub-lithographic pillar of programmable resistive change material (“memory material”), where the heater is formed within the pillar between the top electrode and the programmable material. The device includes a dielectric material layer and vertically separated... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080197333 - Programmable resistive memory cell with self-forming gap: A memory device has a first electrode, a second electrode, and memory material defining an inter-electrode current path between the first electrode and the second electrode. A gap is formed by shrinkage of the shrinkable material between the memory material and a shrinkable material next to the memory material.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080197336 - Nonvolatile memory devices and methods of forming the same: A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond... Agent: Mills & Onello LLP

20080197337 - Phase-change tan resistor based triple-state/multi-state read only memory: The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN... Agent: Scully, Scott, Murphy & Presser, P.C.

20080197335 - Semiconductor device and fabrications thereof: A memory device is disclosed. A pillar structure comprises a first electrode layer, a dielectric layer overlying the first electrode layer, and a second electrode layer overlying the dielectric layer. A phase change layer covers a surrounding of the pillar structure. A bottom electrode electrically connects the first electrode layer... Agent: Birch Stewart Kolasch & Birch

20080197338 - Bottom electrode for memory device and method of forming the same: Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a metal plug. The invention can mitigate keyholes in the contacts by capping and encapsulating the conductive material used to form the contact. The exemplary cap... Agent: Dickstein Shapiro LLP

20080197339 - Nanocrystal powered nanomotor: A nanoscale nanocrystal which may be used as a reciprocating motor is provided, comprising a substrate having an energy differential across it, e.g. an electrical connection to a voltage source at a proximal end; an atom reservoir on the substrate distal to the electrical connection; a nanoparticle ram on the... Agent: Lawrence Berkeley National Laboratory

20080197341 - Method for making a multiple-wavelength opto-electronic device including a superlattice: A method for making a multiple-wavelength opto-electronic device which may include providing a substrates and forming a plurality of active optical devices to be carried by the substrate and operating at different respective wavelengths. Moreover, each optical device may include a superlattice comprising a plurality of stacked groups of layers,... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080197340 - Multiple-wavelength opto-electronic device including a superlattice: A multiple-wavelength opto-electronic device may include a substrate and a plurality of active optical devices carried by the substrate and operating at different respective wavelengths. Each optical device may include a superlattice comprising a plurality of stacked groups of layers, and each group of layers may include a plurality of... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080197347 - Active organic semiconductor devices and methods for making the same: Techniques for disposing an organic semiconductor film on a receiver substrate, comprising the steps of: depositing an organic semiconductor film onto a donor substrate, the semiconductor film having a first surface facing the donor substrate and having an exposed second surface; bringing the exposed second surface adjacent a receiver substrate... Agent: Jay M. Brown Law Office Of Jay M. Brown

20080197345 - Copolymer, organic insulating layer composition, and organic insulating layer and organic thin film transistor manufactured using the same: Disclosed herein is a copolymer, which may include side chains which may decrease the surface energy of an insulating layer, thereby improving the alignment of a semiconductor material, and side chains including photoreactive functional groups having an increased degree of cross-linking, thereby improving the characteristics of an organic thin film... Agent: Harness, Dickey & Pierce, P.L.C

20080197342 - Display device and method of manufacturing the same: A display device and its method of manufacture. The display device is formed to include a substrate having an upper surface, a recess region having a bottom surface and sidewalls, a light-emitting element and a switch element. The light-emitting element includes a first electrode disposed on the recess region, a... Agent: Rabin & Berdo, PC

20080197349 - Manufacturing method of thin-film transistor, thin film transistor sheet, and electric circuit: A thin-film transistor, a thin-film transistor sheet, an electric circuit, and a manufacturing method thereof are disclosed, the method comprising the steps of forming a semiconductor layer by providing a semiconductive material on a substrate, b) forming an insulating area, which is electrode material-repellent, by providing an electrode material-repellent material... Agent: Cantor Colburn, LLP

20080197346 - Nitrogen-containing heteroaromatic ligand-transition metal complexes, buffer layer comprising the complexes and organic thin film transistor comprising the buffer layer: Example embodiments provide a nitrogen-containing heteroaromatic ligand-transition metal complex, a buffer layer including the complex, which may improve the injection and transport of electrical charges, an organic thin film transistor and an electronic device including the buffer layer, in which the injection of electrons or holes and the transport of... Agent: Harness, Dickey & Pierce, P.L.C

20080197343 - Organic field effect transistor gate: An electronic device, in particular an RFID transponder, comprises at least one logic gate, in which the logic gate is formed from a plurality of layers, which are applied on a common substrate, which layers comprise at least two electrode layers and at least one of the layers, in particular... Agent: Carella, Byrne, Bain, Gilfillan, Cecchi, Stewart & Olstein

20080197344 - Semiconductor, semiconductor device, complementary transistor circuit device: A semiconductor device including a semiconductor 1, a first electrode 2, an insulating layer 3 interposed between the semiconductor 1 and the first electrode 2, the second electrode 4 which is in contact with the semiconductor 1 and is detached from the first electrode 2, and the third electrode 5... Agent: Millen, White, Zelano & Branigan, P.C.

20080197348 - Thin film transistor array, method for manufacturing the same, and active matrix type display using the same: One embodiment of the present invention is a thin film transistor array, having an insulating substrate and a stripe-shaped semiconductor layer for a plurality of transistors, the layer extending over the plurality of transistors. Another embodiment of the present invention is an active matrix type display, having the thin film... Agent: Squire, Sanders & Dempsey L.L.P.

20080197350 - Thin film transistor and method of forming the same: A thin film transistor (TFT) may include a channel layer, a source electrode, a drain electrode, a protective layer, a gate electrode, and/or a gate insulating layer. The channel layer may include an oxide semiconductor material. The source electrode and the drain electrode may face each other on the channel... Agent: Harness, Dickey & Pierce, P.L.C

20080197352 - Bump structure on substrate: A bump structure on a substrate including at least one first electrode, at least one first bump, at least one second bump is provided. The first electrode is disposed on the substrate. The first bump is disposed on the first electrode. The second bump is disposed on the substrate. The... Agent: Jianq Chyun Intellectual Property Office

20080197353 - Semiconductor device for which electrical test is performed while probe is in contact with conductive pad: A semiconductor device that comprises a conductive pad that is provided on the insulating film and that is obtained by forming a main conductive film and a surface conductive film harder than the main conductive film in that order.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080197351 - Testkey design pattern for gate oxide: A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one pair of source and drain respectively directly connected to each side of the conductive line. The pair of source... Agent: North America Intellectual Property Corporation

20080197355 - Electro-optical device substrate, method of manufacturing the same, electro-optical device and electronic apparatus: An electro-optical device that includes a transistor and an insulating film over the semiconductor layer of the transistor. The insulating film has an opening portion that overlaps the channel region. The gate electrode of the transistor includes a body portion arranged in the opening portion of the insulating film and... Agent: Workman Nydegger

20080197354 - Thin film transistor, an organic light emitting device including the same, and a manufacturing method thereof: A thin film transistor includes first and second ohmic contacts formed on a substrate, wherein each of the first and second ohmic contacts includes polycrystalline silicon; a semiconductor formed on the first and second ohmic contacts and the substrate, the semiconductor including microcrystalline silicon; a blocking member formed on the... Agent: F. Chau & Associates, LLC

20080197356 - Thin film transistor substrate and method of manufacturing the same: A thin film transistor (TFT) substrate and a method of manufacturing the same in which the surface of a data pattern is implanted with ions to increase the adhesion force with a passivation layer formed by a subsequent process. The TFT substrate includes: an active layer having a channel region... Agent: Macpherson Kwok Chen & Heid LLP

20080197357 - Display panel and manufacturing method: A display panel includes a semiconductor layer formed on a substrate, a first insulating layer formed on the semiconductor layer, a gate line including a gate electrode and formed on the first insulating layer, a second insulating layer formed on the gate line, and a data line including a source... Agent: Macpherson Kwok Chen & Heid LLP

20080197359 - Compound semiconductor device and method of manufacturing the same: A compound semiconductor device has a buffer layer formed on a conductive SiC substrate, an AlxGa1-xN layer formed on the buffer layer in which an impurity for reducing carrier concentration from an unintentionally doped donor impurity is added and in which the Al composition x is 0<x<1, a GaN-based carrier... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080197358 - Wide-bandgap semiconductor devices: A device 100 comprising a substrate 115 having crystal-support-structures 110 thereon, and a III-V crystal 210. The III-V crystal is on a single contact region 140 of one of the crystal-support-structures. An area of the contact region is no more than about 50 percent of a surface area 320 of... Agent: Hitt Gaines, PC Alcatel-lucent

20080197360 - Diode having reduced on-resistance and associated method of manufacture: A diode structure having a reduced on-resistance in the forward-biased condition includes semiconductor layers, preferably of silicon carbide. The anode and cathode of the device are located on the same side of the bottom semiconductor layer, providing lateral conduction across the diode body. The anode is positioned on a semiconductor... Agent: Summa, Allan & Additon, P.A.

20080197361 - Insulated gate silicon carbide semiconductor device and method for manufacturing the same: An insulated gate silicon carbide semiconductor device is provided having small on-resistance in a structure obtained by combining the SIT and MOSFET structures having normally-off operation. The device includes an n− semiconductor layer on an SiC n+ substrate, a p-type base region and highly doped p-region both buried in the... Agent: Rossi, Kimms & Mcdowell LLP.

20080197362 - Semiconductor led, opto-electronic integrated circuits (oeic), and method of fabricating oeic: A light emitting diode demonstrating high luminescence efficiency and comprising a Group IV semiconductor such as silicon or germanium equivalent thereto as a basic component formed on a silicon substrate by a prior art silicon process, and a fabricating method of waveguide thereof are provided. The light emitting diode of... Agent: Miles & Stockbridge PC

20080197363 - Light emitting device having a plurality of light emitting cells and method of fabricating the same: Disclosed is a light emitting device having a plurality of light emitting cells. The light emitting device comprises a thermally conductive substrate, such as a SiC substrate, having a thermal conductivity higher than that of a sapphire substrate. The plurality of light emitting cells are connected in series on the... Agent: H.c. Park & Associates, PLC

20080197365 - Light emitting device: A light emitting device includes: a chip-mounting base formed with a plurality of conductive contacts; a reflector mounted on the chip-mounting base and defining a central hole; a first light emitting chip mounted on the chip-mounting base within the central hole and in electrical contact with respective ones of the... Agent: Christie, Parker & Hale, LLP

20080197364 - Light-emitting device: A light-emitting device comprises a support frame and at least one blue light-emitting chip and at least one red light-emitting chip coupled onto the support frame; and a green phosphor covering the at least one blue light-emitting chip and the at least one red light-emitting chip. The green phosphor is... Agent: Troxell Law Office PLLC

20080197366 - White light emitting diode module: A white LED module includes a circuit board, a blue LED chip disposed on the circuit board, a green light source of an LED chip or phosphor disposed on the circuit board, and a red light source of an LED chip or phosphor disposed on the circuit board. At least... Agent: Mcdermott Will & Emery LLP

20080197367 - Method of super flat chemical mechanical polishing technology and semiconductor elements produced thereof: The present invention provides a method of super flat chemical mechanical polishing (SF-CMP) technology, which is a method characterized in replacing laser lift-off in a semiconductor fabricating process. SF-CMP has a main step of planting a plurality of polishing stop points before polishing the surface, which is characterized by hardness... Agent: Merchant & Gould PC

20080197369 - Double flip semiconductor device and method for fabrication: A double flip-chip semiconductor device formed by a double flip fabrication process. Epitaxial layers are grown on a substrate in the normal fashion with the n-type layers grown first and the p-type layers grown subsequently. The chip is flipped a first time and mounted to a sacrificial layer. The original... Agent: Koppel, Patrick & Heybl

20080197371 - Electro-optical element with controlled, in particular uniform functionality distribution: d

20080197373 - Light emitting diode: The present invention provides a light emitting diode which comprises a substrate, a light emitting layer including an N-type semiconductor layer and a P-type semiconductor layer formed on the substrate, and a wavelength conversion layer formed on the light emitting layer or on the back of the substrate. The wavelength... Agent: Marger Johnson & Mccollom, P.C.

20080197370 - Light emitting diode structure and manufacturing method thereof: A light emitting diode structure has a silicon substrate, a conductive layer, and a light emitting diode. The top surface of the silicon substrate has a cup-structure like paraboloid, and the bottom of the cup-structure has a plurality of through-holes penetrating the silicon substrate. The conductive layer fills up the... Agent: North America Intellectual Property Corporation

20080197368 - Optoelectronic component and package for an optoelectronic component: Optoelectronic components with a semiconductor chip, which is suitable for emitting primary electromagnetic radiation, a basic package body, which has a recess for receiving the semiconductor chip and electrical leads for the external electrical connection of the semiconductor chip and a chip encapsulating element, which encloses the semiconductor chip in... Agent: Fish & Richardson PC

20080197372 - Semiconductor structures and method for fabricating the same: A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate disposed thereon, an insulation layer disposed on the substrate and overlying the gate, a patterned semiconductor layer disposed on the insulation layer, a source and a drain disposed on the patterned semiconductor layer, a protective layer overlying... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080197374 - High-power light-emitting diode: A high-power light-emitting diode comprises a pillar, at least one light-emitting chip, a substrate, at least two conducting wires, and a transparent layer. The pillar has an integrally cast structure. The pillar has a block on which a recessed cup is formed. In addition, a screw bolt is extended from... Agent: Troxell Law Office PLLC

20080197375 - Lateral-type light-emitting diode and method of manufacture thereof: A lateral-type light-emitting diode and a method of manufacture thereof are disclosed. The manufacture method comprises the steps of: (1) forming an outer shell on a substrate on which two metal electrodes are mounted; (2) forming chips and bonding wires on the inside of the outer shell; (3) injecting a... Agent: Troxell Law Office PLLC

20080197376 - Method for producing an optical, radiation-emitting component and optical, radiation-emitting component: The invention related to a method for producing an optical and a radiation-emitting component by a molding process, and to an optical and a radiation-emitting component having well-defined viscosity.... Agent: Nexsen Pruet, LLC

20080197377 - Photonic semiconductor device and manufacturing method: A photonic semiconductor device which includes a semiconductor layer having a ridge-form protruding part formed on a semiconductor substrate. A resin layer is formed on surface parts on both sides of the protruding part so that the protruding part is embedded, and a first insulating film includes an opening that... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080197378 - Group iii nitride diodes on low index carrier substrates: A light emitting diode is disclosed that includes a layer of p-type Group III nitride and a layer of n-type Group III nitride on a transparent carrier substrate that has an index of refraction lower then the layer of Group III nitride adjacent the carrier substrate. A layer of transparent... Agent: Summa, Allan & Additon, P.A.

20080197379 - Semiconductor device and manufacturing method thereof: A carrier storage layer is located in a region of a predetermined depth from a surface of an N− substrate, a base region is located in a shallower region than the predetermined depth and an emitter region is located in a surface of the N− substrate. The carrier storage layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080197380 - Semiconductor component comprising a drift zone and a drift control zone: A semiconductor component is disclosed herein comprising a drift zone and a drift control zone. The drift control zone is arranged adjacent to the drift zone and is dielectrically insulated from the drift zone by a dielectric layer. The drift control zone includes at least one first semiconductor layer and... Agent: Harold C. Moore Maginot, Moore & Beck

20080197381 - Semiconductor device and method for manufacturing same: A semiconductor device is provided with a vertical MOSFET including an N-type drift region that has a {110} crystal plane serving as the main surface thereof, a trench gate structure formed in a trench that has a {100} crystal plane serving as a sidewall surface thereof, and plural P-type column... Agent: Young & Thompson

20080197382 - Metal-semiconductor field effect transistors (mesfets) having self-aligned structures and methods of fabricating the same: Metal-semiconductor field-effect transistors (MESFETS) are provided. A MESFET is provided having a source region, a drain region and a gate. The gate is between the source region and the drain region. A p-type conductivity layer is provided beneath the source region, the p-type conductivity layer being self-aligned to the gate.... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080197384 - Field effect transistor arrangement: A field effect transistor arrangement includes an electrically insulating layer, a source region, a drain region and a channel region arranged between source region and drain region, wherein the source region, the drain region and the channel region are in each case arranged on or above the electrically insulating layer,... Agent: Slater & Matsil, L.L.P.

20080197383 - Method of manufacturing a semiconductor element and semiconductor element: A method of manufacturing a semiconductor element. A dislocation region is formed between a first layer and a second layer, the dislocation region including a plurality of dislocations. First interstitials in the first layer are at least partially eliminated using the dislocations in the dislocation region. Vacancies are formed in... Agent: Dickstein Shapiro LLP

20080197385 - Insulated gate field effect transistor and method of manufacturing same, and image pickup device and method of manufacturing same: An insulated gate field effect transistor, a solid-state image pickup device using the same, and manufacturing methods thereof that suppress occurrence of a shutter step and suppress occurrence of punch-through and injection. An insulated gate field effect transistor having a gate electrode on a semiconductor substrate with a gate insulating... Agent: Sonnenschein Nath & Rosenthal LLP

20080197386 - Semiconductor device with an image sensor and method for the manufacture of such a device: The invention relates to a semiconductor device with a semiconductor body (12) with an image sensor comprising a two-dimensional matrix of pixels (1) each comprising a radiation-sensitive element (2) with a charge accumulating semiconductor region (2A) and coupled to a number of MOS field effect transistors (3), in which in... Agent: Philips Intellectual Property & Standards

20080197389 - Image sensor with improved charge transfer efficiency and method for fabricating the same: An image sensor includes: a first impurity region of the first conductive type aligned with one side of the gate structure and extending to a first depth from a surface portion of the semiconductor layer; a first spacer formed on each sidewall of the gate structure; a second impurity region... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080197388 - Pixel structure of cmos image sensor and method of forming the pixel structure: Provided is a pixel structure of a CMOS image sensor. The pixel structure may include a semiconductor substrate, a photo diode, and a color filter. The photo diode may have a trench structure formed in the semiconductor substrate. The color filter may be formed in the trench structure. The color... Agent: Harness, Dickey & Pierce, P.L.C

20080197387 - Solid-state imaging device and camera: A solid-state imaging device is provided. The solid-state imaging device includes: pixels arrayed; a photoelectric conversion element in each of the pixels; a read transistor for reading electric charges photoelectrically-converted in the photoelectric conversion elements to a floating diffusion portion; a shallow trench element isolation region bordering the floating diffusion... Agent: Rader Fishman & Grauer PLLC

20080197390 - Semiconductor apparatus and method for manufacturing semiconductor apparatus: According to an aspect of the present invention, there is provided a semiconductor apparatus including: a semiconductor substrate; a transistor including: a first diffusion layer formed on the semiconductor substrate, and a second diffusion layer formed on the semiconductor substrate; a ferroelectric capacitor including: a bottom electrode connected to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080197391 - Semiconductor device and method of manufacturing the same: A semiconductor device has a ferroelectric capacitor having a ferroelectric film, an interlayer insulating film having a first layer formed on the ferroelectric capacitor, a plug and a wiring connecting to the ferroelectric capacitor, and a dummy plug in the vicinity of the ferroelectric capacitor.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080197392 - Semiconductor memory device: A semiconductor memory device has bit lines, capacitors, bit contacts and capacitor contacts, wherein the bit lines are provided over a semiconductor substrate, the bit lines are connected to the semiconductor substrate through the bit contacts, the capacitors are connected to the semiconductor substrate through the capacitor contacts, and wherein... Agent: Young & Thompson

20080197393 - Semiconductor integrated circuit devices including gate patterns having step difference therebetween and a connection line disposed between the gate patterns and methods of fabricating the same: Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are... Agent: Marger Johnson & Mccollom, P.C.

20080197394 - Methods of manufacturing semiconductor structures: A method of manufacturing semiconductor structures is disclosed. In one embodiment, a first mask is provided above a substrate. The first mask includes first mask lines extending along a first axis. A second mask is provided above the first mask. The second mask includes second mask lines extending along a... Agent: Dicke, Billig & Czaja

20080197395 - Semiconductor device: In order to effectively miniaturize elements of a semiconductor device while improving the characteristics of each semiconductor element on a single chip of a silicon substrate or without impairing the characteristics, at least three different silicon surface directions are applied to the elements. Accordingly, at least the characteristics required for... Agent: Bruce L. Adams, Esq Adams & Wilks

20080197397 - Checkerboarded high-voltage vertical transistor layout: In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in... Agent: The Law Offices Of Bradley J. Bereznak

20080197396 - Gate metal routing for transistor with checkerboarded layout: In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in... Agent: The Law Offices Of Bradley J. Bereznak

20080197398 - Semiconductor device and method of manufacturing the same: A semiconductor device according to an embodiment of the present invention includes: a transistor including, a gate insulator formed of an insulating layer deposited on a substrate, and a gate electrode formed of an electrode layer deposited on the insulating layer; a capacitor including, a first capacitor electrode formed of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080197399 - Nanotip capacitor: A nanotip capacitor and associated fabrication method are provided. The method provides a bottom electrode and grows electrically conductive nanotips overlying the bottom electrode. An electrically insulating dielectric is deposited overlying the nanotips, and an electrically conductive top electrode is deposited overlying dielectric-covered nanotips. Typically, the dielectric is deposited by... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080197400 - Transistor constructions and processing methods: A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second conductive or semiconductive surface. A dielectric region is circumferentially surrounded by the first surface. The region is configured to reduce capacitive coupling between the first and second... Agent: Wells St. John P.s.

20080197402 - Methods of forming nonvolatile memory devices and memory devices formed thereby: Methods of forming non-volatile memory devices include forming a device isolation layer and a gate pattern of a non-volatile memory cell transistor, on a semiconductor substrate. This gate pattern includes a floating gate electrode and a control gate line that extends on the floating gate electrode and on the device... Agent: Myers Bigel Sibley & Sajovec

20080197401 - Nonvolatile memory devices and methods of manufacturing the same: A method of manufacturing a nonvolatile memory device is provided. The method includes forming an isolation layer in a semiconductor substrate defining an active region and forming a molding pattern on the isolation layer. A first conductive layer is formed on a sidewall and a top surface of the molding... Agent: F. Chau & Associates, LLC

20080197403 - Semiconductor device: A semiconductor device includes a semiconductor substrate, and nonvolatile memory cells, each of the cells including a channel region having a channel length and a channel width, a tunnel insulating film, a floating gate electrode, a control gate electrode, an inter-electrode insulating film between the floating and control gate electrodes,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080197404 - Method of fabricating semiconductor memory device and semiconductor memory device: A semiconductor memory device is fabricated by: forming a device isolation region in a recessed portion of a semiconductor substrate having an irregularly-shaped portion; forming a gate electrode wiring trench in a direction orthogonal to a longitudinal direction of an active region which is a projecting portion of the semiconductor... Agent: Rabin & Berdo, PC

20080197406 - Sensing fet integrated with a high-voltage vertical transistor: In one embodiment, a semiconductor device includes a main vertical field-effect transistor (FET) and a sensing FET. The main vertical FET and the sense FET are both formed on a pillar of semiconductor material. Both share an extended drain region formed in the pillar above the substrate, and first and... Agent: The Law Offices Of Bradley J. Bereznak

20080197405 - Trench diffusion isolation in power transistors: A semiconductor structure comprises a plurality of columns doped with alternating dopants. The columns are separated by trenches, and the dopant is diffused in the doped columns. The trenches are filled with semiconductor material. Other embodiments may be described and claimed.... Agent: Schwegman, Lundberg & Woessner / Infineon

20080197407 - Power semiconductor devices with barrier layer to reduce substrate up-diffusion and methods of manufacture: A method for controlling the thickness of an expitaxially grown semiconductor material includes providing a semiconductor substrate that is doped by dopants of a first type; forming a buffer layer atop the semiconductor substrate, the buffer layer being doped with dopants of a second type that has much less diffusivity... Agent: Townsend And Townsend And Crew, LLP

20080197408 - Isolated quasi-vertical dmos transistor: Various integrated circuit devices, in particular a quasi-vertical DMOS transistor, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a... Agent: Patentability Associates

20080197409 - Superjunction power mosfet: An embodiment of an MOS device includes a semiconductor substrate of a first conductivity type, a first region of the first conductivity type having a length Lacc and a net active dopant concentration of about Nfirst, a pair of spaced-apart body regions of a second opposite conductivity type and each... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080197410 - High voltage device with low on-resistance: A high-voltage transistor device has a first well region with a first conductivity type in a semiconductor substrate, and a second well region with a second conductivity type in the semiconductor substrate substantially adjacent to the first well region. A field ring with the second conductivity type is formed on... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080197411 - Mos transistor device in common source configuration: A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor.... Agent: Duane Morris, LLPIPDepartment

20080197412 - Multi-layer source/drain stressor: A method for forming a semiconductor device includes forming a recess in a source region and a recess in a drain region of the semiconductor device. The method further includes forming a first semiconductor material layer in the recess in the source region and a second semiconductor material layer in... Agent: Freescale Semiconductor, Inc. Law Department

20080197414 - Method of forming a thin film component: Embodiments of methods, apparatuses, devices, and/or systems for forming a thin film component are described.... Agent: Hewlett Packard Company

20080197413 - Thin film transistor and method of manufacturing the same: Provided are a thin film transistor and a method of manufacturing the same. The thin film transistor includes: a lower structure; a semiconductor layer formed on the lower structure and including a plurality of doping regions; a first insulating layer and a second insulating layer formed on the semiconductor layer... Agent: Cantor Colburn, LLP

20080197415 - Electrostatic discharge protection circuit having multiple discharge paths: The present invention relates to an electrostatic discharge protection circuit of a semiconductor memory device to protect an internal circuit from static electricity. The electrostatic discharge protection circuit includes a first trigger unit which provides a first trigger voltage in response to static electricity transferred from at least one of... Agent: Ladas & Parry LLP

20080197416 - Semiconductor protection circuit, method for fabricating the same and method for operating semiconductor protection circuit: A protection circuit protects a semiconductor device provided on a semiconductor substrate and including an interconnect from charge entering the interconnect during fabrication of the semiconductor device. The protection circuit includes a first metal interconnect connected to the interconnect; a forward diode and a backward diode connected in parallel to... Agent: Mcdermott Will & Emery LLP

20080197418 - Gate pullback at ends of high-voltage vertical transistor structure: In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of... Agent: The Law Offices Of Bradley J. Bereznak

20080197417 - Segmented pillar layout for a high-voltage vertical transistor: In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor... Agent: The Law Offices Of Bradley J. Bereznak

20080197419 - Cell structure for dual port sram: An integrated circuit and methods for laying out the integrated circuit are provided. The integrated circuit includes a first and a second transistor. The first transistor includes a first active region comprising a first source and a first drain; and a first gate electrode over the first active region. The... Agent: Slater & Matsil, L.L.P.

20080197420 - Method for fabricating dual-gate semiconductor device: A method for fabricating a dual-gate semiconductor device. A preferred embodiment comprises forming a gate stack having a first portion and a second portion, the first portion and the second portion including a different composition of layers, forming photoresist structures on the gate stack to protect the material to be... Agent: Slater & Matsil, L.L.P.

20080197421 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a p-type active region and an n-type active region which are formed in a semiconductor substrate and a p-type MISFET including a gate insulating film formed on the p-type active region and a first gate electrode including a first electrode formation film of which upper part... Agent: Mcdermott Will & Emery LLP

20080197422 - Planar combined structure of a bipolar junction transistor and n-type/p-type metal semiconductor field-effect transistors and method for forming the same: A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion... Agent: Nikolai & Mersereau, P.A.

20080197423 - Device and method for reducing a voltage dependent capacitive coupling: A device comprises a first means for separating a conductive layer from a semiconductor substrate and a second means for reducing a voltage dependent capacitive coupling between the conductive layer and the semiconductor substrate.... Agent: Maginot, Moore & Beck Chase Tower

20080197424 - Semiconductor structure including gate electrode having laterally variable work function: A semiconductor structure, such as a CMOS structure, includes a gate electrode that has a laterally variable work function. The gate electrode that has the laterally variable work function may be formed using an angled ion implantation method or a sequential layering method. The gate electrode that has the laterally... Agent: Scully, Scott, Murphy & Presser, P.C.

20080197425 - Semiconductor device: A semiconductor device has a trench isolation structure and a high voltage circuit section including at least one well region, a MOS transistor, and an interconnect for electrically connecting elements. An electrode for preventing inversion layer formation is formed in a region above the trench isolation region provided near an... Agent: Bruce L. Adams, Esq Adams & Wilks

20080197426 - Method for manufacturing insulated gate field effect transistor: Disclosed herein is a method for manufacturing an insulated gate field effect transistor, the method including the steps of: (a) preparing a base that includes source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a... Agent: Sonnenschein Nath & Rosenthal LLP

20080197427 - Method of forming double gate dielectric layers and semiconductor device having the same: A method of forming double gate dielectric layers composed of an underlying oxide layer and an overlying oxy-nitride layer is provided to prevent degradation of gate dielectric properties due to plasma-induced charges. In the method, the oxide layer is thermally grown on a silicon substrate under oxygen gas atmosphere to... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080197428 - Gate electrode structure, mos field effect transistors and methods of manufacturing the same: A gate electrode structure comprises at least one bi-layer, wherein each bi-layer comprises a plating film and a stress amplifier film. The plating film includes a poly-crystalline material. The stress amplifier film determines the crystallization result of the poly-crystalline material, wherein a mechanical stress induced through the plating layer is... Agent: Edell, Shapiro & Finnan, LLC

20080197429 - Semiconductor device and method of manufacturing same: A semiconductor device includes: a silicon oxide film; a metal silicate insulating film provided on the silicon oxide film and having a higher dielectric constant than the silicon oxide film; and a gate electrode provided on the metal silicate insulating film. A composition ratio of a metal element in the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080197430 - Biochemical semiconductor chip laboratory comprising a coupled address and control chip and method for producing the same: A biochemical semiconductor chip laboratory is disclosed including a coupled address and control chip for biochemical analyses and a method for producing the same. In at least one embodiment the semiconductor chip laboratory has a semiconductor sensor chip, which provides numerous analytical positions for biochemical samples in a matrix. The... Agent: Harness, Dickey & Pierce, P.L.C

20080197434 - Magnetic memory device: b

20080197431 - Magnetic memory element and magnetic memory apparatus: A magnetic memory element includes a laminated construction of an electrode, a first pinned layer, a first intermediate layer, a first memory layer, a second intermediate layer, a second memory layer, a third intermediate layer, a second pinned layer and electrode. The magnetization direction of the first memory layer takes... Agent: Nixon & Vanderhye, PC

20080197433 - Memory device and memory: Disclosed is a memory device including a memory layer retaining information thereon based on a magnetization state of a magnetic body, a fixed-magnetization layer having a fixed-magnetization direction formed on the memory layer through a non-magnetic layer, and two metal wiring lines formed adjacent to both ends of the fixed-magnetization... Agent: Bell, Boyd & Lloyd, LLP

20080197432 - Microchip assembly produced by transfer molding: The invention relates to a microchip assembly and an associated general production process, wherein an originally unshaped first component (1) is forged against the surface of a transfer molding form by an injected molten second component (5). The first component (1) may particularly comprise electrical tracks (3) on a carrier... Agent: Philips Intellectual Property & Standards

20080197436 - Electronic device, method for manufacturing the same, and silicon substrate for electronic device: An electronic device is formed by epitaxially growing a Si substrate on a Si layer of an SOI substrate in which the Si layer is deposited on a front surface of a substrate with an insulating layer interposed therebetween; forming an element on a front-surface side of the Si substrate;... Agent: Birch Stewart Kolasch & Birch

20080197437 - Solid-state imaging apparatus, manufacturing method therefor and electronic equipment using the same: Provided is a solid-state imaging apparatus having excellent reading accuracy. The solid-state imaging apparatus of the present invention includes a solid-state imaging element (light receiving element portion) (1a) of a solid-state imaging element chip (1) mounted on a film (11), and a resin (2b) having fluidity between the solid-state imaging... Agent: Mcginn Intellectual Property Law Group, PLLC

20080197435 - Wafer level image sensor package with die receiving cavity and method of making the same: The present invention provides a structure of package comprising a substrate with a die receiving cavity formed within an upper layer of the substrate, wherein terminal pads are formed on the upper surface of the substrate, the same plain as the micro lens. A die is disposed within the die... Agent: Bacon & Thomas, PLLC

20080197438 - Sensor semiconductor device and manufacturing method thereof: This invention discloses a sensor semiconductor device and a manufacturing method thereof, including: providing a wafer having a plurality of sensor chips, forming a plurality of grooves between bond pads on active surfaces of the adjacent sensor chips; forming conductive traces in the grooves for electrically connecting the bond pads;... Agent: Edwards Angell Palmer & Dodge LLP

20080197439 - Semiconductor device and method for manufacturing same: A semiconductor device including a Schottky diode of the trench-junction-barrier type having an integrated PN diode, and a corresponding method for manufacturing the device, are provided. An n layer is provided on an nt substrate, and trenches are provided in the n layer. The trenches are provided with p-doped regions.... Agent: Kenyon & Kenyon LLP

20080197440 - Nonvolatile memory: To provide a nonvolatile memory which realizes nonvolatile characteristic similar to a flash memory and a high-speed access equivalent to SRAM, has an integration degree exceeding that of DRAM, requires low voltage and low power consumption, and can be driven by a small-size battery, there are provided: (1) a non-volatile... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080197441 - Semiconductor component with vertical structures having a high aspect ratio and method: A semiconductor component with vertical structures having a high aspect ratio and method. In one embodiment, a drift zone is arranged between a first and a second component zone. A drift control zone is arranged adjacent to the drift zone in a first direction. A dielectric layer is arranged between... Agent: Dicke, Billig & Czaja

20080197442 - Semiconductor component with cell structure and method for producing the same: A semiconductor component comprises a semiconductor body comprising a first component electrode arranged on one of the surfaces of the semiconductor body, a second component electrode arranged on one of the surfaces of the semiconductor body, and a component control electrode arranged on one of the surfaces of the semiconductor... Agent: Dicke, Billig & Czaja

20080197444 - Integrated circuit and method including an isolation arrangement: An integrated circuit and method including an isolation arrangement. One embodiment provides a substrate having trenches and mesa regions and also auxiliary structures on the mesa regions. A first isolation structure covers side walls and a bottom region of the trenches and at least partially side walls of the auxiliary... Agent: Dicke, Billig & Czaja

20080197446 - Isolated diode: Various integrated circuit devices, in particular a diode, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material... Agent: Patentability Associates

20080197445 - Isolation and termination structures for semiconductor die: Various integrated circuit devices, including a lateral DMOS transistor, a quasi-vertical DMOS transistor, a junction field-effect transistor (JFET), a depletion-mode MOSFET, and a diode, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation... Agent: Patentability Associates

20080197443 - Semiconductor substrate comprising a pn-junction and method for producing said substrate: An SOI substrate comprising a carrier substrate, a dielectric layer and a semiconductor layer. A continuous pn junction is realized in the semiconductor layer, which pn junction can be produced by applying differently doped partial layers on the SOI substrate. In this way, it is possible to use an SOI... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20080197447 - Method for manufacturing a structure of semiconductor-on-insulator type: A method for manufacturing an insulated semiconductor layer, including: forming a porous silicon layer on a single-crystal silicon surface; depositing an insulating material so that it penetrates into the pores of the porous silicon layer; eliminating the insulating material to expose the upper surface of the porous silicon; and growing... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20080197448 - Shallow trench isolation fill by liquid phase deposition of sio2: To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080197449 - Wiring structure of semiconductor integrated circuit device, and method and device for designing the same: A method is provided for designing a wiring structure of a wiring layer of a semiconductor integrated circuit device. The method includes a wire width detecting step of detecting a wire width of each wire in a wiring pattern of layout data, a wire identifying step of identifying a wire... Agent: Mcdermott Will & Emery LLP

20080197450 - Amorphous carbon metal-to-metal antifuse with adhesion promoting layers: A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode.... Agent: Lewis And Roca LLP

20080197451 - High-voltage variable breakdown voltage (bv) diode for electrostatic discharge (esd) applications: Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered... Agent: Texas Instruments Incorporated

20080197452 - Group iii nitride semiconductor substrate: A Group III nitride semiconductor substrate is formed of a Group III nitride single crystal, and has a diameter of not less than 25.4 mm and a thickness of not less than 150 μm. The substrate satisfies that a ratio of Δα/α is not more than 0.1, where α is... Agent: Mcginn Intellectual Property Law Group, PLLC

20080197453 - Semiconductor device and manufacturing method of the same: In an MIS-type GaN-FET, a base layer made of a conductive nitride including no oxygen, here, TaN, is provided on a surface layer as a nitride semiconductor layer to cover at least an area of a lower face of a gate insulation film made of Ta2O5 under a gate electrode.... Agent: Kratz, Quintos & Hanson, LLP

20080197454 - Method and system for removing impurities from low-grade crystalline silicon wafers: Techniques are here disclosed for a solar cell pre-processing. The method and system remove impurities from low-grade crystalline semiconductor wafers and include forming a low-grade semiconductor wafer having a substrate having high impurity content. The process and system damage at least one surface of the semiconductor wafer either in the... Agent: HulseyIPIntellectual Property Lawyers, P.C.

20080197455 - Semiconductor device and manufacturing method therefor: A semiconductor device having a rectangular exterior appearance includes a substrate for arranging an integrated circuit on the surface thereof, at least one rewire electrically connected to the integrated circuit via at least one pad electrode, at least one electrode terminal formed on the rewire, and a resin layer for... Agent: Dickstein Shapiro LLP

20080197456 - Substrate polishing method, semiconductor device and fabrication method therefor: A substrate polishing method, a semiconductor device and a fabrication method for a semiconductor device are disclosed by which high planarization polishing can be achieved. In the substrate polishing method, two or more different slurries formed from ceria abrasive grains having different BET values from each other are used to... Agent: Rader Fishman & Grauer PLLC

20080197457 - Silicon wafer and its manufacturing method: A silicon wafer which achieves a gettering effect without occurrence of slip dislocations is provided, and the silicon wafer is subject to heat treatment after slicing from a silicon monocrystal ingot so that a layer which has zero light scattering defects according to the 90° light scattering method is formed... Agent: Greenblum & Bernstein, P.L.C

20080197459 - Encapsulated chip scale package having flip-chip on lead frame structure and method: In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20080197458 - Small outline package in which mosfet and schottky diode being co-packaged: The present invention provides a thin small outline package in which MOSPET and Schottky diode being co-packaged, which comprises a electrode S of MOSFET, a electrode 0 of MOSFET, a electrode D of MOSFET, electrode K and A of Schottky diode. The electrode D of MOSFF,T and electrode A of... Agent: Bo-in Lin

20080197460 - Packaged ic device comprising an embedded flex circuit, and methods of making same: A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a... Agent: Perkins Coie LLP Patent-sea

20080197461 - Apparatus for wire bonding and integrated circuit chip package: An apparatus for wire bonding and a capillary tool thereof are provided. An exemplary embodiment of a capillary tool capable of a wire bonding comprises a body having a first internal channel of a first diameter for accommodating a flow of a conductive wire. A compressible head is connected to... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080197462 - Semiconductor package: A semiconductor package is provided with a package main body including a base portion configured by joining thin plates integrally, and a semiconductor device accommodating portion provided on one surface of the base portion, electric terminals electrically connected to a semiconductor device in the accommodating portion and exposed to an... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080197463 - Electronic component and method for manufacturing an electronic component: An electronic component has at least two semiconductor devices, a contact clip and a leadframe with a device carrier portion and a plurality of leads. The contact clip extends between the first side of at least two semiconductor devices and at least one lead of the leadframe to electrically connect... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20080197464 - Integrated circuit device package with an additional contact pad, a lead frame and an electronic device: A semiconductor device package (10) comprising: a die attach pad (12); a plurality of contact pads provided in at least four rows at least two tie bars (18) for supporting the die attach pad; a semiconductor die mounted on the top surface of the die attach pad (12) and having... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080197466 - Semiconductor device and manufacturing method thereof: A semiconductor device includes: a semiconductor chip; a plurality of pellet-like electrically conductive members connected to electrodes of the semiconductor chip; and an encapsulation resin that encapsulates the semiconductor chip and the electrically conductive members. The electrically conductive members are embedded into the encapsulation resin. Surfaces of the electrically conductive... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080197465 - Semiconductor device and method of manufacturing the same: Variations in fastening positions of semiconductor elements are eliminated by forming protrusions on a die pad so as to enclose the semiconductor elements before an adhesive that fastens the semiconductor elements to the die pad is wetted and spread.... Agent: Steptoe & Johnson LLP

20080197467 - Conductive structure for a semiconductor integrated circuit and method for forming the same: A conductive structure for a semiconductor integrated circuit and method for forming the conductive structure are provided. The semiconductor integrated circuit has a pad and a passivation layer partially covering the pad to define a first opening portion having a first lateral size. The conductive structure electrically connects to the... Agent: Birch Stewart Kolasch & Birch

20080197469 - Multi-chips package with reduced structure and method for forming the same: The present invention provides a structure of multi-chips package and Method of the same comprising a substrate with a pre-formed die receiving cavity formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and an elastic dielectric layer filled into a... Agent: Bacon & Thomas, PLLC

20080197468 - Package structure and manufacturing method thereof: A package structure and a manufacturing method thereof are provided. The package structure includes a substrate, a first chip, a cap structure, a second chip and a sealant. The first chip is disposed in an opening of the substrate and is electrically connected to the substrate. The cap structure is... Agent: Birch Stewart Kolasch & Birch

20080197471 - Semiconductor chip mounting substrate, semiconductor chip mounting body, semiconductor chip stacked module, and semiconductor chip mounting substrate manufacturing method: There is provided a semiconductor chip mounting substrate including a substrate on which a mounting region for mounting a semiconductor chip and a connection region for interlayer connection of the semiconductor chip are formed, and a plurality of alignment marks for alignment at the time of stacking which are provided... Agent: Ratnerprestia

20080197472 - Semiconductor device and semiconductor module using the same: A semiconductor device includes a circuit board which has a first main surface having first connection pads, a second main surface having second connection pads, a first opening passing through a vicinity of the first connection pads, and a second opening passing through a vicinity of the second connection pads.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080197470 - Stacked electronic component and manufacturing method thereof: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080197473 - Chip holder with wafer level redistribution layer: A chip holder formed of silicon, glass, other ceramics or other suitable materials includes a plurality of recesses for retaining semiconductor chips. The bond pads of the semiconductor chip are formed on or over an area of the chip holder that surrounds the semiconductor chip thus expanding the bonding area.... Agent: Duane Morris LLPIPDepartment (tsmc)

20080197477 - Flip-chip grid ball array strip and package: The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed... Agent: Advanced Micro Devices, Inc. C/o Vedder Price P.C.

20080197475 - Packaging conductive structure and method for forming the same: A packaging conductive structure for a semiconductor substrate and a method for forming the structure are provided. The dielectric layer of the packaging conductive structure partially overlays the metallic layer of the semiconductor substrate and has a receiving space. The lifting layer and conductive layer are formed in the receiving... Agent: Birch Stewart Kolasch & Birch

20080197476 - Semiconductor device: The bump diameter of a bump electrode is reduced. An external connection substrate is bonded to a semiconductor chip, and is provided with, at an edge portion thereof, an external connection electrode protruding from the semiconductor chip, and continuing on both principal surfaces of the external connection substrate. The external... Agent: Morrison & Foerster LLP

20080197474 - Semiconductor device package with multi-chips and method of the same: The present invention provides a semiconductor device package with the multi-chips comprising a substrate with at least a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. At least a first die... Agent: Bacon & Thomas, PLLC

20080197478 - Semiconductor device package with die receiving through-hole and connecting through-hole and method of the same: The present invention provides a semiconductor device package with the die receiving through hole and connecting through holes structure comprising a substrate with a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the... Agent: The Maxham Firm

20080197480 - Semiconductor device package with multi-chips and method of the same: The present invention provides a semiconductor device package with the multi-chips comprising a substrate with a die receiving through hole, a conductive connecting through holes structure and coupled the first contact pads on an upper surface and second contact pads on a lower surface of the substrate through a conductive... Agent: Bacon & Thomas, PLLC

20080197479 - Semiconductor package, integrated circuit cards incorporating the semiconductor package, and method of manufacturing the same: One embodiment of a semiconductor package described herein includes a substrate having a first through-hole extending therethrough; a conductive pattern overlying the substrate and extending over the first through-hole; a first semiconductor chip facing the conductive pattern such that at least a portion of the first semiconductor chip is disposed... Agent: Marger Johnson & Mccollom, P.C.

20080197481 - Semiconductor sensor having flat mounting plate: A semiconductor sensor for detecting a rotational speed of a rotor is contained in a cylindrical housing, an opening of which is closed with a cover member. The cover member includes a mounting plate integrally molded therewith. Components including a bare sensing chip and other circuit chips are directly mounted... Agent: Posz Law Group, PLC

20080197482 - Semiconductor module, portable device and method for manufacturing semiconductor module: A semiconductor module is provided, which is capable of suppressing the deterioration of reliability and improving heat radiation. The semiconductor module includes: a semiconductor substrate in which electrodes of a circuit element are formed on its surface; a re-wiring pattern connected to the electrodes to ensure large pitch of the... Agent: Fish & Richardson P.C.

20080197483 - Lidless semiconductor cooling: A system for cooling a semiconductor includes a heat sink in thermal contact with the semiconductor, a thermal interface material (TIM) layer disposed between the heat sink and the semiconductor, and a picture frame support disposed between a substrate of the semiconductor and the heat sink, wherein the picture frame... Agent: Osha Liang L.L.P./sun

20080197484 - Method of manufacturing electronic component package, and wafer and substructure used for manufacturing electronic component package: In a method of manufacturing an electronic component package, first, there is fabricated a wafer incorporating a plurality of sets of external connecting terminals corresponding to a plurality of electronic component packages, and a retainer for retaining the plurality of sets of external connecting terminals, the wafer including a plurality... Agent: Oliff & Berridge, PLC

20080197485 - Module comprising a semiconductor chip comprising a movable element: The invention relates to a module comprising a carrier, a first semiconductor chip applied to the carrier and having a movable element and a second semiconductor chip applied to the first semiconductor chip, wherein an active first main surface of the first semiconductor chip faces the carrier and a first... Agent: Slater & Matsil LLP

20080197486 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a semiconductor substrate that has an integrated circuit and an electrode electrically connected to the integrated circuit; a first resin layer that is formed in a first region overlapping the integrated circuit over a surface of the semiconductor substrate where the electrode is formed; a wiring... Agent: Harness, Dickey & Pierce, P.L.C

20080197487 - Semiconductor device including a coupled dielectric layer and metal layer, method of fabrication thereof, and material for coupling a dielectric layer and a metal layer in a semiconductor device: A passivating coupling material for, on the one hand, passivating a dielectric layer in a semiconductor device, and on the other hand, for permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. In a particular example, the dielectric layer may be a porous material... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080197488 - Bowed wafer hybridization compensation: A planarizing method performed on a non-planar wafer involves forming electrically conductive posts extending through a removable material, each of the posts having a length such that a top of each post is located above a plane defining a point of maximum deviation for the wafer, concurrently smoothing the material... Agent: Morgan & Finnegan, L.L.P.

20080197490 - Conductive structure for a semiconductor integrated circuit and method for forming the same: A conductive structure for a semiconductor integrated circuit and method for forming the conductive structure are provided. The semiconductor integrated circuit has a pad and a passivation layer partially overlapping the pad to define the first lateral size of the first opening. The conductive structure electrically connects to the pad... Agent: Birch Stewart Kolasch & Birch

20080197489 - Packaging conductive structure and method for manufacturing the same: A packaging conductive structure for a semiconductor substrate and a method for manufacturing the structure are provided. The structure comprises an under bump metal (UBM) that overlays a pad of the semiconductor substrate. At least one auxiliary component is disposed on the UBM. Then, a bump conductive layer is disposed... Agent: Birch Stewart Kolasch & Birch

20080197491 - Semiconductor device and method for producing the same: The semiconductor device includes a silicon interposer made of a semiconductor and a first semiconductor chip mounted on one surface of the silicon interposer. The semiconductor device is provided with a through electrode penetrating the silicon interposer and having a side surface insulated from the silicon interposer; and a wiring... Agent: Young & Thompson

20080197492 - Semiconductor device, connecting member, method for manufacturing a semiconductor device and method for manufacturing a connecting member: A semiconductor device has a semiconductor element having a plurality of connection terminals, a circuit substrate electrically connected with the semiconductor element; and a connecting member arranged between the semiconductor element and the circuit substrate having a plurality of conductive projections each having a columnar portion, each of columnar portions... Agent: Kratz, Quintos & Hanson, LLP

20080197493 - Integrated circuit including conductive bumps: One embodiment provides an integrated circuit including an electrical contact and a conductive bump elongated via centrifugal forces. The conductive bump has a base and a top. The base is attached to the electrical contact and the top remains unattached.... Agent: Dicke, Billig & Czaja

20080197494 - Semiconductor device including copper wiring and via wiring having length longer than width thereof and method of manufacturing the same: A semiconductor device has an interconnect and a via material. The via material is provided under the interconnect and is in contact with an end portion of the interconnect. The interconnect and the via are made of copper as one piece. The via material has a top surface coupled to... Agent: Mcginn Intellectual Property Law Group, PLLC

20080197495 - Structure for reducing lateral fringe capacitance in semiconductor devices: A semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines at locations between the conductive lines.... Agent: Cantor Colburn LLP - IBM Fishkill

20080197497 - Barrier for use in 3-d integration of circuits: A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening.... Agent: Freescale Semiconductor, Inc. Law Department

20080197496 - Semiconductor device having at least two layers of wirings stacked therein and method of manufacturing the same: A semiconductor device according to the present invention is a semiconductor device having a first wiring formed in a first insulating layer and a second wiring formed in a second insulating layer formed on the first insulating layer and the first wiring. Here, at least one of the first wiring... Agent: Mcdermott Will & Emery LLP

20080197498 - Gate electrode silicidation process: A fully-silicided gate electrode is formed from silicon and a metal by depositing at least two layers of silicon with the metal layer therebetween. One of the silicon layers may be amorphous silicon whereas the other silicon layer may be polycrystalline silicon. The silicon between the metal layer and the... Agent: Freescale Semiconductor, Inc. Law Department

20080197500 - Interconnect structure with bi-layer metal cap: A structure and method of fabricating an interconnect structures with bi-layer metal cap is provided. In one embodiment, the method includes forming an interconnect feature in a dielectric material layer; and forming a bi-layer metallic cap on a top surface of the interconnect feature. The method further includes depositing a... Agent: International Business Machines Corporation Dept. 18g

20080197501 - Interconnection substrate and semiconductor device, manufacturing method of interconnection substrate: An interconnection substrate including therein one or more resin layers, each of the resin layers including therein a via-hole penetrating from a top surface to a bottom surface of the resin layer. A via-plug of metal particles is formed in the via-hole. Each of the metal particles has a flat... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080197502 - Semiconductor device having metal wirings of laminated structure: A semiconductor device that includes a metal wiring formed on the insulating film and having a main wiring portion laminated with a plurality of metal films and a metal protection film formed at least on the upper surfaces of the main wiring portion and made of a precious metal material.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080197499 - Structure for metal cap applications: An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared... Agent: Scully, Scott, Murphy & Presser, P.C.

20080197503 - Chip package: A chip package including a carrier, at least one chip disposed on the carrier, a plurality of wires electrically connecting the carrier and the chip, and an encapsulant wrapping the chip and the wires is provided. The chip has a semiconductor substrate, an interconnection structure, at least one first reference... Agent: J C Patents, Inc.

20080197507 - Electronic package structure and method: An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process,... Agent: Rosenberg, Klein & Lee

20080197505 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a semiconductor substrate that has an integrated circuit, a passivation film formed above the integrated circuit, and an electrode electrically connected to the integrated circuit, the passivation film having an uneven surface, the electrode having at least a portion exposed through the passivation film; a first... Agent: Harness, Dickey & Pierce, P.L.C

20080197506 - Semiconductor device manufacturing method, semiconductor device, and semiconductor wafer structure: A semiconductor device manufacturing method, includes the steps of forming an insulating film over a semiconductor substrate, thinning selectively a thick portion, whose film thickness is thicker than a reference value, of the insulating film, forming contact holes in a thinned portion of the insulating film 25, and forming conductive... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080197504 - Single-sided, flat, no lead, integrated circuit package: An integrated circuit package comprising an enclosure including a dielectric housing, a first electrical contact, and a second electrical contact. The dielectric housing, the first electrical contact, and the second electrical contact are configured to form a contact side of the enclosure. In addition, the first and second electrical contacts... Agent: Orion Law Group

20080197508 - Plated pillar package formation: A method involves plating pillars of electrically conductive material up from a seed layer located on a substrate, surrounding the pillars with a fill material so that the pillars and fill material collectively define a first package, and removing the substrate from the first package.... Agent: Morgan & Finnegan, L.L.P.

20080197509 - Semiconductor package having stacked semiconductor chips: A semiconductor package including: a package substrate on the surface of which plural connection terminals are provided; a semiconductor chip on the surface of which plural bonding pads are provided; plural bonding wires that connect between the plural connection terminals and the plural bonding pads; a resin formed to fill... Agent: Foley And Lardner LLP Suite 500

20080197510 - Semiconductor device and wire bonding method: A semiconductor device with improved bondability between a wire and a bump and cutting property of the wire to improve the bonding quality. In the semiconductor device, a wire is stacked on a pad as a second bonding point to form a bump having a sloped wedge and a first... Agent: Quinn Emanuel Urquhart Oliver & Hedges, LLP Koda/androlia

20080197511 - Bonding pad structure, electronic device having a bonding pad structure and methods of fabricating the same: An electronic device having a bonding pad structure and a method of fabricating the same is provided. The electronic device may include a first bonding pads formed on the substrate. A second bonding pad may be formed on the lower insulating layer. The second bonding pads may be spaced apart... Agent: Harness, Dickey & Pierce, P.L.C

20080197513 - Beol interconnect structures with improved resistance to stress: A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier... Agent: International Business Machines Corporation Dept. 18g

20080197512 - Process for manufacturing deep through vias in a semiconductor device, and semiconductor device made thereby: A process for manufacturing a through via in a semiconductor device includes the steps of: forming a body having a structural layer, a substrate, and a dielectric layer set between the structural layer and the substrate; insulating a portion of the structural layer to form a front-side interconnection region; insulating... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20080197514 - Die coat perimeter to enhance semiconductor reliability: A semiconductor packaging stress relief technique with enhanced reliability. Reliability is enhanced over conventional post wirebond assembly die coating processes by forming a peripheral wall on the semiconductor die isolating the stress sensitive area from remaining area in the semiconductor die, and depositing die coat material constraining the flow of... Agent: Gauthier & Connors, LLP

20080191186 - Phase change memory cell with filled sidewall memory element and method for fabricating the same: Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode, a top electrode overlying the bottom electrode, a via having a sidewall extending from a bottom electrode to a top electrode, and a memory element electrically coupling the bottom electrode to the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080191187 - Method for manufacturing a phase change memory device with pillar bottom electrode: A method for manufacturing a mushroom-cell type phase change memory is based upon manufacturing a pillar of bottom electrode material upon a substrate including an array of conductive contacts in electrical communication with access circuitry. A layer of electrode material is deposited making reliable electrical contact with the array of... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080191188 - Multi bit phase-change random access memory devices and methods of forming the same: A phase-change random access memory (PRAM) device includes a first electrode and a second electrode on a substrate. A phase change pattern is interposed between the first and second electrodes. An interlayer insulating layer having a contact hole is provided on the substrate. The phase change pattern may be disposed... Agent: Myers Bigel Sibley & Sajovec

20080191189 - Nanotube array electronic devices: p

20080191192 - Al(x)ga(1-x)n-cladding-free nonpolar iii-nitride based laser diodes and light emitting diodes: A method for fabricating AlxGa1-xN-cladding-free nonpolar III-nitride based laser diodes or light emitting diodes. Due to the absence of polarization fields in the nonpolar crystal planes, these nonpolar devices have thick quantum wells that function as an optical waveguide to effectively confine the optical mode to the active region and... Agent: Gates & Cooper LLP Howard Hughes Center

20080191190 - Epi-structure with uneven multi-quantum well and the method thereof: An Epi-Structure of light-emitting device, comprising: a first semiconductor conductive layer forming on a substrate; an active layer forming on a first semiconductor conductive layer with Multi-Quantum Well (MQW); and a second semiconductor conductive layer forming on the active layer; wherein a plurality of particles formed by at least one... Agent: Reed Smith LLP

20080191191 - Light emitting diode of a nanorod array structure having a nitride-based multi quantum well: The present invention relates to a GaN light emitting diode. The GaN LED according to the present invention uses a GaN nanorod in which a multi quantum well formed by alternately stacking a plurality of InGaN layers and a plurality of GaN barriers is inserted into a p-n junction interface... Agent: H.c. Park & Associates, Plc

20080191193 - In situ modification of group iv nanoparticles using gas phase nanoparticle reactors: A method for creating an organically capped Group IV semiconductor nanoparticle is disclosed. The method includes flowing a Group IV semiconductor precursor gas into a chamber. The method also includes generating a set of Group IV semiconductor precursor radical species from the Group IV semiconductor precursor gas with a laser... Agent: Foley & Lardner LLP

20080191195 - Nitride semiconductor device: According to the nitride semiconductor device with the active layer made of the multiple quantum well structure of the present invention, the performance of the multiple quantum well structure can be brought out to intensify the luminous output thereof thereby contributing an expanded application of the nitride semiconductor device. In... Agent: Volentine & Whitt Pllc

20080191194 - Semiconductor light sources, systems, and methods: A light-emitting diode includes a substrate, a lower cladding layer, an active layer having a quantum well of a thirty percent concentration of indium on the lower cladding layer, and an upper cladding layer. A method of manufacturing light-emitting diodes includes forming a lower cladding layer on a substrate, forming... Agent: Marger Johnson & Mccollom, P.c.

20080191196 - Nanowire heterostructures: The present invention generally relates to nanoscale heterostructures and, in some cases, to nanowire heterostructures exhibiting ballistic transport, and/or to metal-semiconductor junctions that that exhibit no or reduced Schottky barriers. One aspect of the invention provides a solid nanowire having a core and a shell, both of which are essentially... Agent: Wolf Greenfield & Sacks, P.c.

20080191201 - Composition containing thiazole rings, organic semiconductor polymer containing the composition, organic active layer containing the organic semiconductor polymer, organic thin film transistor containing the organic active layer, electronic device contain: Disclosed herein is a composition containing hetero arylene or arylene showing a p-type semiconductor property in addition to thiophene showing a p-type semiconductor property and thiazole rings showing a n-type semiconductor property at a polymer main chain, an organic semiconductor polymer containing the composition, an organic active layer containing the... Agent: Harness, Dickey & Pierce, P.L.C

20080191200 - Ion gels and electronic devices utilizing ion gels: An ion gel including an ionic liquid and a block copolymer. The block copolymer includes at least three blocks, and the block copolymer forms a self-assembled ion gel in the ionic liquid. Also, thin film transistors including an ion gel insulator layer, capacitors including an ion gel insulator layer, integrated... Agent: Shumaker & Sieffert, P. A.

20080191198 - Organic thin film transistor having surface-modified carbon nanotubes: An organic thin film transistor may comprise an organic semiconductor layer having surface-modified carbon nanotubes and an electrically-conductive polymer. The surfaces of the carbon nanotubes may be modified with curable functional groups, comprising oxirane groups and anhydride groups. A room-temperature solution process may be used to provide a relatively uniform... Agent: Harness, Dickey & Pierce, P.L.C

20080191199 - Polyacene and semiconductor formulation: The invention relates to novel polyacene compounds, organic semiconducting formulations and layers comprising them, a process for preparing the formulation and layer and electronic devices, including organic field effect transistors (OFETs), comprising the same.... Agent: Millen, White, Zelano & Branigan, P.c.

20080191197 - Semiconductor arrangement having a resistive memory: e

20080191202 - Semiconductor device and method for manufacturing the same: A semiconductor device is disclosed. The device includes: oppositely disposed plural electrodes; a semiconductor molecule disposed such that one end part thereof binds to a surface of the electrode in each of the opposing electrodes; and a conductor for electrically connecting at least a part of the other end part... Agent: Bell, Boyd & Lloyd, LLP

20080191203 - Method for producing gan film, semiconductor device, method for generating thin film of nitride of group iii element and semiconductor device having thin film of nitride of group iii element: A GaN layer (12) is formed on a planarized surface of a ZnO substrate (11) to provide a nitride semiconductor device (10) having the GaN layer. The GaN layer (12) is formed by a first film-forming step of allowing epitaxial growth of GaN at a temperature not higher than 300°... Agent: Bell, Boyd & Lloyd, LLP

20080191204 - Thin film transistors and methods of manufacturing the same: A transistor may include: a gate insulting layer; a gate electrode formed on the gate insulating layer; a channel layer formed on the gate insulating layer; and source and drain electrodes that contact the channel layer. The channel layer may have a double-layer structure, including upper and lower layers. The... Agent: Harness, Dickey & Pierce, P.L.C

20080191205 - Test structure for seal ring quality monitor: A semiconductor structure includes a daisy chain adjacent to an edge of a semiconductor chip. The daisy chain includes a plurality of horizontal metal lines distributed in a plurality of metallization layers, wherein the horizontal metal lines are serially connected; a plurality of connecting pads in a same layer and... Agent: Slater & Matsil, L.l.p.

20080191206 - Semiconductor device and method of fabricating the same: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate structure, a spacer, a first poly-SiGe layer being boron-doped and a second poly-SiGe layer being boron-doped. The substrate has two openings and the gate structure is disposed on the substrate between the openings. The spacer is disposed... Agent: J C Patents, Inc.

20080191210 - Electro-optic substrate, electro-optic device, method of designing the electro-optic substrate, and electronic device: To prevent the light that possibly penetrates an equivalent optical waveguide from reaching the channel part, on the condition that a first insulating layer is set to have a layer-thickness t (nm) and a refraction index n, a relation is to be expressed by the following expression. t<(0.61×λ)/(n×sin θ) A... Agent: Oliff & Berridge, Plc

20080191209 - Image sensor devices having light blocking layers and methods of fabricating image sensor devices having light blocking layers: An image sensor device includes an optical black pixel region and an active pixel region. The image sensor device includes a light receiving unit including a plurality of light sensitive semiconductor devices that are configured to detect light incident thereon, a pixel metal wire layer including a transparent material on... Agent: Myers Bigel Sibley & Sajovec

20080191208 - Pixel circuit and display device: A pixel circuit includes: a switching transistor whose conduction is controlled by a drive signal supplied to the control terminal; a drive wiring adapted to propagate the drive signal; and a data wiring adapted to propagate a data signal. The drive wiring is formed on a first wiring layer and... Agent: Rader Fishman & Grauer Pllc

20080191212 - Thin film transistor array panel and manufacturing methd thereof: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer;... Agent: Macpherson Kwok Chen & Heid LLP

20080191211 - Thin film transistor array substrate, method of manufacturing the same, and display device: A thin film transistor array substrate includes a gate electrode formed on a substrate, a gate insulating film formed over the gate electrode, a source electrode and a drain electrode that are formed on the gate insulating film and include a transparent conductive film and a metal film formed on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080191207 - Thin film transistor device, method of manufacturing the same, and display apparatus: A thin film transistor device includes a semiconductor layer including a source region, a drain region and a channel region formed above a substrate, a metal film formed in a prescribed area on the semiconductor layer, a gate insulating film formed on the metal film and the semiconductor layer, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080191213 - Thin film transistor, thin film transistor substrate including the same and method of manufacturing the same: A thin film transistor showing desirable contact characteristics during contact with indium tin oxide (ITO) or indium zinc oxide (IZO), in which a first conductive pattern including a gate electrode and a second conductive pattern including a source electrode and a drain electrode are formed without an etching process, a... Agent: F. Chau & Associates, Llc

20080191214 - Thin film transistor substrate, liquid crystal display device provided with such thin film transistor substrate and method for manufacturing thin film transistor substrate: A method for manufacturing a thin film transistor substrate includes (a) a step of forming a plurality of island-like semiconductor films (13) above an insulating transparent substrate (10); (b) a step of forming a gate insulating film (21) on each of the island-like semiconductor films (13); (c) a step of... Agent: Nixon & Vanderhye, Pc

20080191216 - Diode-like composite semiconductor device: A silicon-made low-forward-voltage Schottky barrier diode is serially combined with a high-antivoltage-strength high-electron-mobility transistor made from a nitride semiconductor that is wider in bandgap than silicon. The Schottky barrier diode has its anode connected to the gate, and its cathode to the source, of the HEMT. This HEMT is normally... Agent: Woodcock Washburn LLP

20080191215 - Semiconductor light emitting device: There is provided a semiconductor light emitting device that minimizes reflection or absorption of emitted light, maximizes luminous efficiency with the maximum light emitting area, enables uniform current spreading with a small area electrode, and enables mass production with high reliability and high quality. A semiconductor light emitting device according... Agent: Mcdermott Will & Emery LLP

20080191217 - Process for forming an interface between silicon carbide and silicon oxide with low density of states: An embodiment of a process for forming an interface between a silicon carbide (SiC) layer and a silicon oxide (SiO2) layer of a structure designed to conduct current is disclosed. A first epitaxial layer having a first doping level is homo-epitaxially grown on a substrate. The homo-epitaxial growth is preceded... Agent: Graybeal, Jackson, Haley LLP

20080191218 - Low-dielectric constant cryptocrystal layers and nanostructures: This invention provides a method for producing application quality low-dielectric constant (low-k) cryptocrystal layers on state-of-the-art semiconductor wafers and for producing organized Nanostructures from cryptocrystals and relates to optical and electronic devices that can be obtained from these materials. The results disclosed here indicate that modification of structure and chemical... Agent: Venable, Campillo, Logan & Meaney, P.c.

20080191220 - Roll-to-roll fabricated light sheet and encapsulated semiconductor circuit devices: A light active sheet, comprising a first substrate flexible sheet having an electrically conductive surface, a second transparent substrate flexible sheet having a transparent conductive layer disposed thereon, an electrically insulative adhesive flexible sheet and light active semiconductor elements fixed to the electrically insulative adhesive sheet. The light active semiconductor... Agent: Michaud-duffy Group LLP

20080191219 - Thermal transfer in solid state light emitting apparatus and methods of manufacturing: Provided are light emitting apparatus including a solid state light emitting element having a first side and a second side, the solid state light emitting element configured to emit light from the first side. Such apparatus further include an elongated thermally conductive element positioned to conduct thermal energy from the... Agent: Myers Bigel Sibley & Sajovec, P.a.

20080191221 - Method and device for wafer scale packaging of optical devices using a scribe and break process: A multilayered integrated optical and circuit device. The device has a first substrate comprising at least one integrated circuit chip thereon, which has a cell region and a peripheral region. Preferably, the peripheral region has a bonding pad region, which has one or more bonding pads and an antistiction region... Agent: Townsend And Townsend And Crew, LLP

20080191222 - Ac light emitting diode and method for fabricating the same: The present invention relates to an AC light emitting diode. An object of the present invention is to provide an AC light emitting diode wherein various designs for enhancement of the intensity of light, prevention of flickering of light or the like become possible, while coming out of a unified... Agent: H.c. Park & Associates, Plc

20080191223 - Cleaved facet (ga,al,in)n edge-emitting laser diodes grown on semipolar bulk gallium nitride substrates: A III-nitride edge-emitting laser diode is formed on a surface of a III-nitride substrate having a semipolar orientation, wherein the III-nitride substrate is cleaved by creating a cleavage line along a direction substantially perpendicular to a nonpolar orientation of the III-nitride substrate, and then applying force along the cleavage line... Agent: Gates & Cooper LLP Howard Hughes Center

20080191228 - Green phosphor of thiogallate, red phosphor of alkaline earth sulfide and white light emitting device thereof: The present invention relates to a white light emitting device in which a thiogallate based phosphor capable of emitting green light and an alkaline earth metal sulfide based phosphor capable of emitting red light are arranged on an upper surface of a light emitting diode for emitting ultraviolet rays or... Agent: Marger Johnson & Mccollom, P.c.

20080191231 - Led package, method of fabricating the same, and backlight unit having the same: Disclosed are a LED package, a method of fabricating the same, and a backlight unit having the same. The light emitting diode package comprises a light emitting diode, a printed circuit board provided with a circuit pattern used for driving the light emitting diode and a through hole formed in... Agent: Birch Stewart Kolasch & Birch

20080191229 - Light emitting device and phosphor of alkaline earth sulfide therefor: According to the light emitting device of the present invention, white light with a continuous spectrum ranging from green to red can be implemented such that more excellent color rendering and color reproducibility can be obtained. Therefore, the light emitting device of the present invention can used in an liquid... Agent: Marger Johnson & Mccollom, P.c.

20080191232 - Light emitting device with a lens of silicone: Disclosed herein is a light emitting device with a silicone lens. The light emitting device comprises a heat sink. A package body surrounds at least a portion of the heat sink, and a light emitting diode is mounted on the heat sink. Meanwhile, the light emitting diode is covered with... Agent: Marger Johnson & Mccollom, P.c.

20080191233 - Light-emitting diode and method for manufacturing the same: A light-emitting diode and method for manufacturing the same are described. The light-emitting diode comprises: a conductive substrate including a first surface and a second surface on opposite sides; a reflector structure comprising a conductive reflector layer bonding to the first surface of the conductive substrate and a conductive distributed... Agent: Bacon & Thomas, Pllc

20080191225 - Methods of forming packaged semiconductor light emitting devices having front contacts by compression molding: Methods of packaging a semiconductor light emitting device include providing a substrate having the semiconductor light emitting device on a front face thereof and a contact on a front face thereof, wherein the light emitting device is electrically connected to the contact on the front face of the substrate. The... Agent: Myers Bigel Sibley & Sajovec, P.a.

20080191226 - Nitride semiconductor light-emitting device and method for fabrication thereof: A nitride semiconductor light-emitting device includes a substrate, a nitride semiconductor layer incorporating therein a first electroconductive semiconductor layer, a light-emitting layer and a second electroconductive semiconductor layer, a transparent electrode contiguous to at least part of a first surface of the second electroconductive semiconductor layer, and a second electrode... Agent: Sughrue Mion, Pllc

20080191230 - Red phosphor and luminous element using the same: The present invention relates to a phosphor and a luminous element using the same. The present invention provides a phosphor for absorbing a portion of light emitted from a light source and emitting light with a wavelength different from that of the absorbed light. The phosphor comprises a fluorescent material... Agent: Marger Johnson & Mccollom, P.c.

20080191227 - Surface-mount type optical semiconductor device and method for manufacturing same: A small and thin surface-mount type optical semiconductor device having high air tightness, which can be manufactured at a reduced cost includes: a base 2 formed of a glass substrate; a recess 5 formed on a first main surface 3 of the base; a through hole 7 extending from a... Agent: Hamre, Schumann, Mueller & Larson P.c.

20080191224 - Transparent led chip: A light emitting diode is disclosed that includes a transparent substrate with an absorption coefficient less than 4 per centimeter, epitaxial layers having absorption coefficients of less than 500 per centimeter in the layers other than the active emission layers, an ohmic contact and metallization layer on at least one... Agent: Summa, Allan & Additon, P.a.

20080191234 - Yellow phosphor and white light emitting device using the same: wherein Q is one or more elements selected from a group consisting of Si, Al, and Se; 0≦x≦0.1; 0≦y≦0.5; z is 12 when y is 0, 12 when Q is one or more elements selected from a group consisting of Al and Sc, or 12+y when Q is Si; a... Agent: Knobbe Martens Olson & Bear LLP

20080191236 - Cooling device for a light-emitting semiconductor device and a method of manufacturing such a cooling device: A cooling device for cooling a light-emitting semiconductor device, such as a LED device (20), comprises a ceramic plate (15) having coolant-conveying channels (12) incorporated therein. The ceramic plate (15) is adapted for forming an integral part of the optical system of the light-emitting semiconductor device (20) and to cool... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20080191235 - Light emitting diode structure with high heat dissipation: A light emitting diode structure with a high heat dissipating effect includes a lead frame, a chip, two lead wires, an internal casing and an external casing. The lead frame has a first electrode and a second electrode, and the first electrode forms a cavity for installing the visible or... Agent: Hdsl

20080191237 - Submounts for semiconductor light emitting devices and methods of forming packaged light emitting devices including dispensed encapsulants: A submount for mounting an LED chip includes a substrate, a die attach pad configured to receive an LED chip on an upper surface of the substrate, a first meniscus control feature on the substrate surrounding the die attach pad and defining a first encapsulant region of the upper surface... Agent: Myers Bigel Sibley & Sajovec, P.a.

20080191238 - Bipolar mosfet devices and methods for their use: According to the invention there is provided a semiconductor device including: at least one cell including a base region of a first conductivity type having disposed therein at least one emitter region of a second conductivity type; a first well region of a second conductivity type; a second well region... Agent: Volentine & Whitt Pllc

20080191239 - Multilayer structure and fabrication thereof: A process for fabricating a multilayer structure is provided as well as the structure itself. In accordance with one embodiment, the process includes growing a growth layer on a silicon substrate by epitaxial growth, forming at least one pattern from the growth layer, depositing an oxide layer on the silicon... Agent: Edwards Angell Palmer & Dodge LLP

20080191240 - Avalanche photo diode: An avalanche photodiode including a first electrode; and a substrate including a first semiconductor layer of a first conduction type electrically connected to the first electrode, in which at least an avalanche multiplication layer, a light absorption layer, and a second semiconductor layer of a second conduction type with a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080191241 - Semiconductor photodetector device: A transmitted light absorption/recombination layer, a barrier layer, a wavelength selection/absorption layer, and an InP window layer having a p-type region are supported by an n-type substrate and arranged in that order. Light with a wavelength of 1.3 μm reaches the wavelength selection/absorption layer through the InP window layer. Then,... Agent: Leydig Voit & Mayer, Ltd

20080191242 - Method for manufacturing an electro-mechanical component and an electro-mechanical component, such as a strained si fin-fet: The present invention is an electro mechanical component, such as a nano-electro-mechanical component, having a first, a second and a third portion arranged such that the second portion is used to functionally connect the first and the third portion. In the present invention, the second portion is a bilayer having... Agent: Siemens Schweiz Ag I-47, Intellectual Property

20080191244 - Methods of fabricating integrated circuit devices including strained channel regions and related devices: A method of fabricating an integrated circuit device includes forming first and second gate patterns on surfaces of a semiconductor substrate in PMOS and NMOS regions, respectively, of the substrate. P-type source/drain regions are epitaxially grown on opposite sides of the first gate pattern in the PMOS region to exert... Agent: Myers Bigel Sibley & Sajovec

20080191243 - Semiconductor structure and method of forming the structure: Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080191245 - Bipolar junction transistor having a high germanium concentration in a silicon-germanium layer and a method for forming the bipolar junction transistor: A method for forming a germanium-enriched region in a heterojunction bipolar transistor and a heterojunction bipolar transistor comprising a germanium-enriched region. A base having a silicon-germanium portion is formed over a collector. Thermal oxidation of the base causes a germanium-enriched region to form on a surface of the silicon-germanium portion... Agent: Hitt Gaines, Pc Lsi Corporation

20080191246 - Method to improve writer leakage in a sige bipolar device: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein,... Agent: Hitt Gaines, Pc Lsi Corporation

20080191247 - Nonvolatile memory transistor having poly-silicon fin, stacked nonvolatile memory device having the transistor, method of fabricating the transistor, and method of fabricating the device: A nonvolatile memory transistor having a poly-silicon fin, a stacked nonvolatile memory device having the transistor, a method of fabricating the transistor, and a method of fabricating the device are provided. The device may include an active fin protruding upward from a semiconductor substrate. At least one first charge storing... Agent: Harness, Dickey & Pierce, P.L.C

20080191248 - Scalable power field effect transistor with improved heavy body structure and method of manufacture: A field effect transistor (FET) includes a semiconductor region of a first conductivity type and a well region of a second conductivity type extending over the semiconductor region. A gate electrode is adjacent to but insulated from the well region, and a source region of the first conductivity type is... Agent: Townsend And Townsend And Crew, LLP

20080191249 - Methods for planarization of dielectric layer around metal patterns for optical efficiency enhancement: A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency includes first depositing a first dielectric having an optically transparent property on and around... Agent: Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080191250 - Transistor having coupling-preventing electrode layer, fabricating method thereof, and image sensor having the same: A transistor having an electrode layer that can reduce or prevent a coupling effect, a fabricating method thereof, and an image sensor having the same are provided. The transistor includes a semiconductor substrate and a well of a first conductivity type formed on the semiconductor substrate. A heavily-doped first impurity... Agent: Myers Bigel Sibley & Sajovec

20080191255 - Ferroelectric random access memories (frams) having lower electrodes respectively self-aligned to node conductive layer patterns and methods of forming the same: A ferroelectric random access memory (FRAM) includes a semiconductor substrate and an interlayer insulating layer on the substrate. A diffusion preventive layer is on the interlayer insulating layer. The diffusion preventive layer and the interlayer insulating layer have two node contact holes formed therein. Node conductive layer patterns are aligned... Agent: Myers Bigel Sibley & Sajovec

20080191254 - Method of manufacturing semiconductor device, method of manufacturing semiconductor substrate and semiconductor substrate: A semiconductor substrate with an insulating film, a barrier layer containing a metal and formed over the insulating film in a region that includes a peripheral edge part of a semiconductor substrate, a capacitor lower electrode layer formed on the barrier layer and having an edge-cut on the peripheral edge... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080191251 - Non-volatile magnetic memory with low switching current and high thermal stability: One embodiment of the present invention includes a an embodiment of the present invention includes a non-volatile current-switching magnetic memory element including a bottom electrode; a pinning layer formed on top of the bottom electrode; a fixed layer formed on top of the pinning layer; a tunnel layer formed on... Agent: Law Offices Of Imam

20080191253 - Semiconductor device and method for manufacturing the same: There is provided a method for manufacturing a semiconductor device, including, forming a first insulating film on a semiconductor substrate, forming a capacitor on the first insulating film, forming a second insulating film covering the capacitor, forming a metal wiring on the second insulating film, forming a first capacitor protective... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080191252 - Semiconductor device and method for manufacturing the semiconductor device: A semiconductor device with a first insulating film formed on a semiconductor substrate; a capacitor formed on the first insulating film and including a lower electrode, a ferroelectric film and an upper electrode; a second insulating film formed on the capacitor and the first insulating film; a first contact hole... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080191256 - Polyoxometallates in memory devices: The invention relates to a DRAM memory device with a capacity associated with a field effect transistor, in which all or some of the molecules capable of storing the loads comprising a polyoxometallate are incorporated into the capacity, or a flash-type memory using at least one field effect transistor, in... Agent: Miller, Matthias & Hull

20080191257 - 3-d channel field-effect transistor, memory cell and integrated circuit: A field-effect transistor includes a source region, a drain region and a channel region between the source and the drain region. A gate electrode is also arranged between them, where a lower edge of the gate electrode is formed below a lower edge of at least one of the source... Agent: Edell, Shapiro & Finnan, Llc

20080191258 - Low voltage coefficient mos capacitors: A low voltage coefficient MOS capacitor includes first and second dielectric layers between first and second capacitor plates, with a common plate separating the dielectric layers. First and second terminals are coupled to first and second capacitor plates.... Agent: Horizon Ip Pte Ltd

20080191259 - Semiconductor device having high-voltage transistor and pip capacitor and method for fabricating the same: A semiconductor device having a high-voltage transistor and a polysilicon-insulator-polysilicon (PIP) capacitor, and a method for fabricating the same are provided. A current flow path of the high-voltage transistor is widened to reduce on-resistance of the device. Thus, electric characteristics of the device are enhanced. The semiconductor device includes a... Agent: Mckenna Long & Aldridge LLP

20080191260 - Semiconductor device and use thereof: The semiconductor device comprises a first and a second varactor which are connected in an anti-series configuration. This connection is done such that a first, substantially electrically conductive region is present between a second region with dopant of a first conductivity type and a third region with dopant of the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080191261 - Nonvolatile memory devices and methods of fabricating the same: Example embodiments may provide nonvolatile memory devices and example methods of fabricating nonvolatile memory devices. Example embodiment nonvolatile memory devices may include a switching device on a substrate and/or a storage node electrically connected to the switching device. A storage node may include a lower metal layer electrically connected to... Agent: Harness, Dickey & Pierce, P.L.C

20080191262 - Non-volatile memory and fabricating method thereof: The invention provides a non-volatile memory including a substrate, an active layer, device isolation layers and memory cells. The active layer disposed on the substrate protrudes from the substrate surface. Regarding the active layer, the device isolation layers are respectively disposed on the two sides thereof; the surface of the... Agent: Jianq Chyun Intellectual Property Office

20080191264 - Non-volatile memory devices and methods of operating and fabricating the same: Non-volatile memory devices highly integrated using an oxide based compound semiconductor and methods of operating and fabricating the same are provided. A non-volatile memory device may include one or more oxide based compound semiconductor layers. A plurality of auxiliary gate electrodes may be arranged to be insulated from the one... Agent: Harness, Dickey & Pierce, P.L.C

20080191263 - Nonvolatile memory devices and methods of fabricating the same: Provided are a nonvolatile memory device and a method of fabricating the same in which a channel length is effectively increased and high-integration may be possible. In the nonvolatile memory device, a semiconductor device may include an active region defined by a device isolation film. The active region may include... Agent: Harness, Dickey & Pierce, P.L.C

20080191266 - Highly reliable nand flash memory using a five side enclosed floating gate storage elements: A NAND flash memory system with an array of individual charge storage elements, such as floating gates, arranged in a NAND string, each element being capable of selectively storing data in the form of charge there-in during a program or an erase operation, and during a read operation sensing the... Agent: Mammen Thomas

20080191265 - Nanoparticles in a flash memory using chaperonin proteins: A method for fabricating a flash memory device where the flash memory device includes a substantially uniform size and spatial distribution of nanoparticles on a tunnel oxide layer to form a floating gate. The flash memory device may be fabricated by defining active areas in a substrate and forming an... Agent: Winstead Pc

20080191267 - Nonvolatile memory device and method for fabricating the same: A nonvolatile memory device and a method for fabricating the same decreases power consumption and prevents contamination of an insulating layer. The nonvolatile memory device includes a semiconductor substrate; a tunneling oxide layer formed on a predetermined portion of the semiconductor substrate; a floating gate formed on the tunneling oxide... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080191268 - Integrated circuit and method of manufacturing an integrated circuit: An integrated circuit and method of manufacturing an integrated circuit is disclosed. In one embodiment, the integrated circuit includes a gate structure which includes a polysilicon double layer. The polysilicon double layer having a first polysilicon layer and a second polysilicon layer formed above the first polysilicon layer, the first... Agent: Dicke, Billig & Czaja

20080191269 - Memory device with barrier layer: A memory device (100) may include a substrate (110), a dielectric layer (210) formed on the substrate (110) and a charge storage element (220) formed on the dielectric layer (210). The memory device (100) may also include an inter-gate dielectric (230) formed on the charge storage element (220), a barrier... Agent: Harrity & Snyder, L.l.p.

20080191270 - Nand-type non-volatile semiconductor memory device and method of manufacturing the same: A NAND-type non-volatile semiconductor memory device has a semiconductor substrate, an element isolation insulating film which is formed on a surface of the semiconductor substrate spaced apart at a predetermined distance from each other, a first insulating film which is formed between the element isolation insulating films on the semiconductor... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080191271 - Semiconductor device having fins fet and manufacturing method thereof: A line-form insulator is formed on a substrate and then the substrate is etched with the insulator used as a mask to form first trenches on both sides of the insulator. Side wall insulators are formed on the side walls of the first trenches, the substrate is etched with the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080191272 - Semiconductor device: A semiconductor device includes a gate electrode formed through a gate insulating film provided on a first impurity region and a drift layer, and this gate electrode consists of two regions including a first conductivity type second impurity region opposed to the first impurity region and a third impurity region... Agent: Ditthavong Mori & Steiner, P.c.

20080191273 - Mosfet device having improved avalanche capability: A power MOSFET that includes deep source field electrodes, the power MOSFET including one trench that includes an insulated gate and another trench that does not include an insulated gate, both trenches including a source field electrode, a source region adjacent the one trench and no source region adjacent the... Agent: Ostrolenk Faber Gerb & Soffen

20080191274 - Integrated mosfet and schottky device: A power semiconductor device that includes a trench power MOSFET with deep source field electrodes and an integrated Schottky diode.... Agent: Ostrolenk Faber Gerb & Soffen

20080191275 - Dotted channel mosfet and method: A improved MOSFET (50, 51, 75, 215) has a source (60) and drain (62) in a semiconductor body (56), surmounted by an insulated control gate (66) located over the body (56) between the source (60) and drain (62) and adapted to control a conductive channel (55) extending between the source... Agent: Ingrassia Fisher & Lorenz, P.c. (fs)

20080191277 - Isolated transistor: Various integrated circuit devices, in particular a transistor, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material... Agent: Patentability Associates

20080191276 - Semiconductor devices and fabrication methods thereof: Semiconductor devices and fabrication methods thereof. The semiconductor device includes a semiconductor substrate with a body region of a first doping type. A gate structure is patterned on the semiconductor substrate. A single spacer is formed on a first sidewall of the gate structure. A body region of a first... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080191280 - N-type carbon nanotube field effect transistor and method of fabricating the same: Provided are an n-type carbon nanotube field effect transistor (CNT FET) and a method of fabricating the n-type CNT FET. The n-type CNT FET may include a substrate; electrodes formed on the substrate and separated from each other; a CNT formed on the substrate and electrically connected to the electrodes;... Agent: Buchanan, Ingersoll & Rooney Pc

20080191278 - Semiconductor device, method for manufacturing the same, liquid crystal television, and el television: A method for manufacturing a semiconductor device by a small number of processes and by a means with high usability of materials to have high-definition and a gate insulating with a high step coverage property is disclosed. According to the present invention, a method for manufacturing a semiconductor device comprises... Agent: Nixon Peabody, LLP

20080191279 - Thin film transistor, electronic device having the same, and method for manufacturing the same: An object of the present invention is to provide a method for manufacturing a thin film transistor which enables heat treatment aimed at improving characteristics of a gate insulating film such as lowering of an interface level or reduction in a fixed charge without causing a problem of misalignment in... Agent: Eric Robinson

20080191281 - Stressed soi fet having tensile and compressive device regions: A method is provided for fabricating a field effect transistor (“FET”) having a channel region in a semiconductor-on-insulator (“SOI”) layer of an SOI substrate. Desirably, in such method, a sacrificial stressed layer is formed to overlie a first portion of an active semiconductor region but not overlie second portion of... Agent: International Business Machines Corporation Dept. 18g

20080191282 - Mugfet array layout: A circuit array includes a plurality cells, wherein each cell has at least one group of odd fins. The cells may be arranged in a repeating pattern that includes mirror images of the pattern. A plurality of fin forming regions are provided about which the fins are formed for the... Agent: Schwegman, Lundberg & Woessner / Infineon

20080191283 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a gate pattern formed over a semiconductor substrate, the substrate defining a cell region and a peripheral region. First and second contact plugs are formed in the cell region. Third and fourth contact plugs are formed in the peripheral region. A first separation structure is formed... Agent: Townsend And Townsend And Crew, LLP

20080191285 - Cmos devices with schottky source and drain regions: A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain... Agent: Slater & Matsil, L.l.p.

20080191284 - Method for improved fabrication of a semiconductor using a stress proximity technique process: An improved method for applying stress proximity technique process on a semiconductor device and the improved device is disclosed. In one embodiment, the method utilizes an additional set of sidewall spacers on one or more NFET devices during the fabrication process. This protects the one or more of the NFET... Agent: International Business Machines Corporation Dept. 18g

20080191286 - Methods for manufacturing a cmos device with dual dielectric layers: The present disclosure provides a dual workfunction semiconductor device and a method for manufacturing a dual workfunction semiconductor device. The method comprises providing a device on a first region and a device on a second region of a substrate. According to embodiments described herein, the method includes providing a dielectric... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080191287 - Method for fabricating strained-silicon cmos transistor: First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on... Agent: North America Intellectual Property Corporation

20080191288 - Semiconductor device and method of manufacturing the same: In a semiconductor device including a transistor having an embedded gate, and methods of manufacturing the same, a substrate is divided into first and second regions. A gate trench is formed in the first region, a first gate structure partially fills the gate trench and a passivation layer pattern is... Agent: Marger Johnson & Mccollom, P.c.

20080191289 - Fabrication of transistors with a fully silicided gate electrode and channel strain: Manufacturing a semiconductor device by forming first and second gates including patterning a silicon-containing layer on a substrate. Etched simultaneously the patterned silicon-containing layer of the first gate, and first substrate portions adjacent to the first gate to form a first gate electrode and source and drain openings. Forming SiGe... Agent: Texas Instruments Incorporated

20080191290 - Semiconductor devices and methods of manufacturing the same: Semiconductor devices and methods of manufacturing the same are disclosed. A disclosed semiconductor device comprises a semiconductor substrate; a gate formed on the semiconductor substrate; a gate oxide layer interposed between the semiconductor substrate and the gate; and source and drain regions formed within the substrate at opposite sides of... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080191291 - High voltage cmos devices: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent... Agent: Steven H. Slater Slater & Matsil, L.l.p.

20080191292 - Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks: A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the... Agent: Scully, Scott, Murphy & Presser, P.c.

20080191293 - Integrated passive device and method of fabrication: A device 20 includes substrates 22 and 24 coupled to form a volume 32 between the substrates. A surface 28 of the substrate 22 faces a surface 30 of the substrate 24. A metal-insulator-metal capacitor 34 is formed on one of the surfaces 28 and 30. A conductive element 58... Agent: Meschkow & Gresham, P.L.C

20080191294 - Sensor device having stopper for limitting displacement: A sensor includes: a first chip; a second chip disposed on the first chip through an adhesive member; and a stopper. The second chip is connected to the first chip through a bonding wire. The stopper limits a displacement of the second chip when the adhesive member is deformed. The... Agent: Posz Law Group, Plc

20080191295 - Non-volatile magnetic memory element with graded layer: One embodiment of the present invention includes a non-volatile magnetic memory element including layers any of which are graded.... Agent: Law Offices Of Imam

20080191298 - Ambient light detectors using conventional cmos image sensor process: A CMOS light detector configured to detect specific wavelengths of light includes a first sensor and a second sensor. The first sensor includes CMOS photocells that are covered by a colored filter layer of a first color that has a first transmittance that allows both light of the specific wavelengths... Agent: Fliesler Meyer LLP

20080191299 - Microlenses for irregular pixels: A digital camera includes an image sensor having a substrate having an array of pixels each pixel having a photosensitive region, and the array of pixels includes a subset of at least two pixels; primary microlenses each spanning or substantially spanning each pixel of the subset; and one or more... Agent: Frank Pincelli Patent Legal Staff

20080191296 - Optical transmission improvement on multi-dielectric structure in advance cmos imager: The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a sensor element disposed in a semiconductor substrate; an inter-level dielectric (ILD) disposed on the semiconductor substrate; and a trench disposed in the ILD, overlying and enclosing the sensor element, and filled with a first dielectric material.... Agent: Haynes And Boone, LLP

20080191300 - Pin referenced image sensor to reduce tilt in a camera module: The present invention relates to a camera module. The camera module includes a circuit panel having a top side, a bottom side and transparent region, the circuit panel having conductors. The module further includes sensor unit disposed on the bottom side of the circuit panel, and the sensor unit includes... Agent: Tessera Lerner David Et Al.

20080191301 - Solid-state image sensing device equipped with inner lens: A solid-state image sensing device having an effective pixel area and an optical black area disposed on one principal surface of a substrate, includes photoelectric converter elements, a wiring part containing a plurality of wiring layers disposed on the one principal surface of the substrate, in which in the optical... Agent: Fitzpatrick Cella Harper & Scinto

20080191297 - Wafer level image sensor package with die receiving cavity and method of the same: The present invention provides a structure of package comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and a through holes structure formed there through, wherein a terminal pads are formed under the through holes structure and the substrate includes a conductive trace... Agent: Kusner & Jaffe Highland Place Suite 310

20080191302 - Solid-state image pickup device and method for producing the same: A solid-state image pickup device includes an element isolation insulating film electrically isolating pixels on the surface of a well region; a first isolation diffusion layer electrically isolating the pixels under the element isolation insulating film; and a second isolation diffusion layer electrically isolating the pixels under the first isolation... Agent: Robert J. Depke Lewis T. Steadman

20080191303 - Mems thermal actuator and method of manufacture: A separated MEMS thermal actuator is disclosed which is largely insensitive to creep in the cantilevered beams of the thermal actuator. In the separated MEMS thermal actuator, a inlaid cantilevered drive beam formed in the same plane, but separated from a passive beam by a small gap. Because the inlaid... Agent: Jaquelin K. Spong

20080191304 - Schottky diode structure with silicon mesa and junction barrier schottky wells: A power diode having a silicon mesa atop the drift region includes a first contact positioned on the silicon mesa. The silicon mesa is highly doped p-type or n-type, and the anode may be formed on the mesa. The mesa may include two separate silicon layers, one of which is... Agent: Summa, Allan & Additon, P.a.

20080191305 - Bipolar schottky diode and method: A low leakage bipolar Schottky diode (20, 40, 87) is formed by parallel lightly doped N (32, 52, 103) and P (22, 42, 100) regions adapted to form superjunction regions. First ends of the P regions (22, 42, 100) are terminated by P+ layers (21, 41, 121) and second, opposed... Agent: Ingrassia Fisher & Lorenz, P.c. (fs)

20080191306 - Semiconductor system for voltage limitation: A semiconductor system for voltage limitation includes a first cover electrode, a highly p-doped semiconductor layer that is connected to the first cover electrode, a slightly n-doped semiconductor layer that is connected to the highly p-doped semiconductor layer and a second cover electrode. At least one p-doped semiconductor layer and... Agent: Kenyon & Kenyon LLP

20080191307 - Semiconductor device: A semiconductor structure includes a number of semiconductor regions, a pair of dielectric regions and a pair of terminals. The first and second regions of the structure are respectively coupled to the first and second terminals. The third region of the structure is disposed between the first and second regions.... Agent: Townsend And Townsend And Crew, LLP

20080191308 - Semiconductor device: Provided is a semiconductor device having a trench isolation structure and a high power supply voltage circuit section including at least a well region and a MOS transistor formed therein. The high power supply voltage circuit section includes a carrier capture region for preventing latch-up in a vicinity of an... Agent: Brinks Hofer Gilson & Lione

20080191309 - Methods and structure for charge dissipation in integrated circuits: Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation... Agent: Schmeiser, Olsen & Watts

20080191310 - By-product removal for wafer bonding process: A three-dimensional (3D) integrated circuit structure includes a first wafer and a second wafer, each comprising a substrate having devices formed thereon and an interconnect structure over the substrate; a composite layer comprising a first dielectric layer bonded to a second dielectric layer, wherein the composite layer is bonded to... Agent: Slater & Matsil, L.l.p.

20080191313 - Adaptive radio transceiver with floating mosfet capacitors: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such... Agent: Mcandrews Held & Malloy, Ltd

20080191314 - Capacitor below the buried oxide of soi cmos technologies for protection against soft errors: Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080191311 - Metal-insulator-metal capacitor and fabrication method thereof: The present invention provides a metal-insulator-metal capacitor, which comprises a semiconductor substrate; an interlayer dielectric layer disposed on the semiconductor substrate; and an insulation trench and two metal trenches all running through the interlayer dielectric layer and allowing the semiconductor substrate to be exposed; wherein the metal trenches being located... Agent: Squire, Sanders & Dempsey L.l.p.

20080191312 - Semiconductor circuit: A semiconductor memory device includes a substrate and an interconnect region carried by the substrate. A donor layer is coupled to the interconnect region through a bonding interface. An electronic device is formed with the donor layer, wherein the electronic device is formed after the bonding interface is formed. A... Agent: Schmeiser Olsen & Watts

20080191315 - Semiconductor device and method of manufacturing the same: In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed... Agent: Fish & Richardson P.c.

20080191316 - Semiconductor transistor device and method of manufacturing the same: A semiconductor transistor device includes a drift region, an insulating structure, a gate insulator, a gate electrode, a source, and a drain. The drift region includes a first lateral portion having a first dopant concentration and a second lateral portion having a second dopant concentration that is higher than the... Agent: Law Office Of Monica H Choi

20080191317 - Self-aligned epitaxial growth of semiconductor nanowires: Disclosed herein is a method of forming a nanostructure having nanowires by forming a mask with at least one opening on a surface of a substrate, to expose a portion of the surface of the substrate; depositing particles of a metal capable of catalyzing semiconductor nanowire growth on the exposed... Agent: Cantor Colburn LLP-ibm Yorktown

20080191318 - Semiconductor device and method of sawing semiconductor device: A method is disclosed for singulating die containing semiconductor device whereby a trench is etched at a first scribe region of a wafer comprising semiconductor devices, and sawing the wafer within the trench.... Agent: Larson Newman Abel Polansky & White, LLP

20080191319 - Semiconductor chip suppressing a void during a die attaching process and semiconductor package including the same: Provided are a semiconductor chip and a semiconductor package including the semiconductor chip. The semiconductor chip includes a void suppressing path formed in an upper surface of the semiconductor chip and extending to a scribe line formed at an edge of the semiconductor chip.... Agent: Marger Johnson & Mccollom, P.c.

20080191320 - Trench widening without merging: A semiconductor structure. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench comprises a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on the {100} side wall surfaces and the {110}... Agent: Schmeiser, Olsen & Watts

20080191321 - Semiconductor device and method for manufacturing the same: The present invention provides a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device including: ONO films that are formed on a semiconductor substrate and include trapping layers; word lines that are formed on the ONO films; and silicon oxide layers that are formed at portions... Agent: Ingrassia Fisher & Lorenz, P.c.

20080191322 - Prevention of backside cracks in semiconductor chips or wafers using backside film or backside wet etch: A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and... Agent: Scully, Scott, Murphy & Presser, P.c.

20080191324 - Chip package structure and method of fabricating the same: A method of fabricating a chip package structure includes the steps of providing a metal thin plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts. A chip is then disposed on the metal thin plate and a plurality of bonding wires is... Agent: Jianq Chyun Intellectual Property Office

20080191326 - Coreless packaging substrate and method for manufacturing the same: A coreless packaging substrate and a method for making the same are disclosed in the present invention. The coreless packaging substrate is made by first providing a metal adhesion layer having a melting point lower than that of the substrate, and removing a core board connected with the substrate therefrom... Agent: Bacon & Thomas, Pllc

20080191325 - Semiconductor device and packaging structure therefor: A semiconductor device includes two semiconductor chips having different guarantee temperatures, which are individually mounted on two stages distanced from each other and are sealed with a resin mold. One semiconductor chip includes a heating circuit causing a heating temperature that is higher than the guarantee temperature of another semiconductor... Agent: Dickstein Shapiro LLP

20080191323 - Semiconductor package and its manufacturing method: A semiconductor package and its manufacturing method disclosed herein include a lead frame, a chip, an encapsulant, and a passive component arranged on at least any one of the outer lead portions and a supporting finger of the lead frame, wherein the passive component are exposed to the encapsulant. After... Agent: Rosenberg, Klein & Lee

20080191327 - Light emitting device: The semiconductor device includes a semiconductor element, a lead frame electrically connected to the semiconductor element, and a package having an opening in a front surface with a part of the lead frame protruding from a bottom surface. The protruding lead frame branches into a plurality of end portions, and... Agent: Global Ip Counselors, LLP

20080191329 - Semiconductor package: The present invention relates to a semiconductor package, comprising a carrier, a semiconductor device, a first wire and a second wire. The carrier has a first electrically connecting portion and a second electrically connecting portion. The semiconductor device has a plurality of pads. The first wire electrically connects one of... Agent: Volentine & Whitt Pllc

20080191330 - Stacked semiconductor package: The present invention relates to a stacked semiconductor package, comprising a carrier, a first semiconductor device, a second semiconductor device, a plurality of first wires and a plurality of second wires. The carrier has a plurality of electrically connecting portions. The first semiconductor device has a plurality of first pads.... Agent: Volentine & Whitt Pllc

20080191328 - Surface mount electronic component and process for manufacturing same: A surface mount electronic component includes a set of a first lead terminal 2a and a second lead terminal 3b, a semiconductor element 6a die-bonded to an island portion 4a integrally formed at an end of the first lead terminal, a metal wire 7a electrically connecting the semiconductor element and... Agent: Hamre, Schumann, Mueller & Larson, P.c.

20080191332 - Semiconductor device: A semiconductor device, in which an integrated circuit portion and an antenna are easily connected, can surely transmit and receive a signal to and from a communication device. The integrated circuit portion is formed of a thin film transistor over a surface of a substrate so that the area occupied... Agent: Eric Robinson

20080191331 - System in package semiconductor device suitable for efficient power management and method of managing power of the same: Provided are a system in package (SIP) semiconductor device suitable for efficient power management, and a method of managing power of the SIP semiconductor device. The SIP semiconductor device includes chips including first and second chips. Each of the chips includes an alive block, a local interface, and an intellectual... Agent: Mills & Onello LLP

20080191335 - Cmos image sensor chip scale package with die receiving opening and method of the same: The present invention provides a structure of package comprising a substrate with a die through hole and a contact through holes structure formed there through, wherein a terminal pad is formed under the contact through hole structure and a contact pad is formed on a upper surface of the substrate.... Agent: Kusner & Jaffe Highland Place Suite 310

20080191334 - Glass dam structures for imaging devices chip scale package: Glass dam structures for imaging device chip scale package. An optoelectronic device chip scale package comprises a substrate configured as a support structure for the chip scale package. A semiconductor die with die circuitry is attached to the substrate. A glass encapsulant is disposed on the substrate encapsulating the semiconductor... Agent: Joe Mckinney Muncy

20080191333 - Image sensor package with die receiving opening and method of the same: The present invention provides a structure of package comprising a substrate with a die through hole and a contact through holes structure formed there through, wherein a terminal pad is formed under the contact through hole structure and a contact pad is formed on a upper surface of the substrate.... Agent: Bacon & Thomas, Pllc

20080191336 - Subminiature electronic device having hermetic cavity and method of manufacturing the same: The invention discloses a subminiature electronic device with a hermetic cavity and method of manufacturing the same. It particularly relates to a chip type or chip scale packaged electronic device produced in substrate level. Firstly, a sacrificial layer is coated onto each of the identical microstructures disposed on a large... Agent: Birch Stewart Kolasch & Birch

20080191337 - Semiconductor die package and embedded printed circuit board: A semiconductor die package having an enhanced degree of heating radiation from the semiconductor, thereby reducing mechanical and electrical failure from excessive temperatures. A semiconductor die has circuit patterns formed thereon; a bump pad deposited on the semiconductor die and supporting at least one of the bumps electrically connected to... Agent: Cha & Reiter, Llc

20080191338 - Semiconductor memory device, memory device support and memory module: In one embodiment, the semiconductor memory device includes at least a first semiconductor memory die, and a surface of the semiconductor memory device includes a plurality of connectors. At least one of the plurality of connectors is electrically connected to the first semiconductor memory die. The plurality of connectors include... Agent: Harness, Dickey & Pierce, P.L.C

20080191339 - Module with silicon-based layer: The invention concerns a module comprising a carrier element, a semiconductor device mounted on said carrier element and a silicon-based insulating layer. The silicon-based insulating layer is arranged on the side of the carrier element opposite to the semiconductor device. The invention further concerns a module comprising a semiconductor device,... Agent: Dicke, Billig & Czaja

20080191341 - Electronic apparatus and semiconductor package: According to one embodiment, an electronic apparatus is provided with a semiconductor package, a heat receiving plate, and a gap adjusting member. The semiconductor package includes a substrate and a silicon die mounted on the substrate. The heat receiving plate is opposed to the silicon die and thermally connected to... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080191340 - Power semiconductor module and method for its manufacture: A power semiconductor module 3 for mounting on a cooling element 4 has at least one substrate 2, on which one or more components 5, 6, 7 are mounted and a module housing 40. The module housing 40 surrounds at least partially the at least one substrate 2. The module... Agent: Coats & Bennett/infineon Technologies

20080191343 - Integrated circuit package having large conductive area and method for fabricating the same: An integrated circuit package having large conductive area and method for fabricating the same is provided. The package includes an integrated circuit chip having upper and lower surfaces and a photosensitive device formed on the upper surface. A bonding pad is subsequently formed on the upper surface of the integrated... Agent: Birch Stewart Kolasch & Birch

20080191342 - Multi-chip module: A multi-chip module is disclosed. In one embodiment, the multichip module includes a first chip, a second chip and a common chip carrier is disclosed. The first chip and the second chip are mounted on the common chip carrier. The second chip is mounted on the chip carrier in a... Agent: Dicke, Billig & Czaja

20080191344 - Integrated circuit packaging: An integrated circuit includes a substrate including an active area and a gas phase deposited packaging material encapsulating the active area.... Agent: Dicke, Billig & Czaja

20080191346 - Bump structure and manufacturing method thereof: A bump structure comprises: a plurality of landing pads, a passive element, and a plurality of conductive bumps on a wafer. A method for manufacturing the bump comprises: providing a wafer with a plurality of landing pads, wherein the landing pads comprise a first landing pad and a second landing... Agent: Birch Stewart Kolasch & Birch

20080191347 - Conductive ball-or pin-mounted semiconductor packaging substrate, method for manufacturing the same and conductive bonding material: There is disclosed a conductive ball- or pin-mounted semiconductor packaging substrate having a conductive ball or a conductive pin mounted on a conductive land or through-hole of the semiconductor packaging substrate, wherein the conductive ball or the conductive pin is electrically connected with the conductive land or through-hole through a... Agent: King & Schickli, Pllc

20080191345 - Integrated circuit package system with bump over via: An integrated circuit package system includes a substrate, forming a resist layer having an elongated recess over the substrate, forming a via in the substrate below the elongated recess, and forming an elongated bump in the elongated recess over the via.... Agent: Law Offices Of Mikio Ishimaru

20080191349 - Semiconductor device with magnetic powder mixed therein and manufacturing method thereof: A semiconductor device includes a semiconductor substrate on one side of which an integrated circuit and a plurality of connection pads connected to the integrated circuit are provided. An insulating film is provided on the plurality of connection pads except for parts of the connection pads and on the one... Agent: Frishauf, Holtz, Goodman & Chick, Pc

20080191348 - System for distributing electrical power for a chip: A system for distributing electrical power for a chip comprises a plurality of electrically conductive linear trunks arranged in a metallization layer of a chip, wherein the trunks are slanted with respect to the side edges of the chip. A further system for distributing electrical power for a chip comprises... Agent: Lee & Hayes, Pllc

20080191350 - Magnesium-doped zinc oxide structures and methods: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently processed to form magnesium-doped zinc oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure.... Agent: Schwegman, Lundberg & Woessner, P.a.

20080191351 - Molybdenum-doped indium oxide structures and methods: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain indium and monolayers that contain molybdenum are deposited onto a substrate and subsequently processed to form molybdenum-doped indium oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure.... Agent: Schwegman, Lundberg & Woessner, P.a.

20080191352 - Stacked contact with low aspect ratio: An integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer;... Agent: Slater & Matsil, L.l.p.

20080191354 - Circuitized substrate with p-aramid dielectric layers and method of making same: A circuitized substrate including a dielectric layer having a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin and not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on the dielectric layer. A method of making this substrate is also provided.... Agent: Lawrence R. Fraley Hinman, Howard & Kattell, LLP

20080191353 - Multilayered circuitized substrate with p-aramid dielectric layers and method of making same: A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the... Agent: Mark Levy Hinman, Howard & Kattell, LLP

20080191355 - Semiconductor device having buffer layer pattern and method of forming same: A semiconductor device having a buffer layer pattern and a related method of manufacture are disclosed. The semiconductor device comprises at least two bit line patterns formed on a semiconductor substrate having a buried insulating interlayer. Each bit line pattern is formed of a bit line and a bit line... Agent: Volentine & Whitt Pllc

20080191356 - Power semiconductor: The invention relates to a power semiconductor comprising a substrate (2) whose surfaces are provided with at least one electrically conducting layer (4, 6), at least one semiconductor chip (8) that is connected to an electrically conducting layer (6) of the substrate (2) in an electrically and thermally conducting manner... Agent: Henry M Feiereisen, Llc Henry M Feiereisen

20080191357 - Semiconductor device comprising electromigration prevention film and manufacturing method thereof: A semiconductor device includes a semiconductor substrate, a plurality of wiring lines which are provided on one side of the semiconductor substrate and which have connection pad portions, and a plurality of columnar electrodes respectively provided on the connection pad portions of the wiring lines, each of the columnar electrodes... Agent: Frishauf, Holtz, Goodman & Chick, Pc

20080191358 - Solder deposition on wafer backside for thin-die thermal interface material: A solder is deposited on the backside of a wafer. The wafer can be predeposited with a barrier layer such as a titanium base and other materials. Deposition is carried out by electroplating, electroless plating, chemical vapor deposition, and physical vapor deposition. The solder-deposited die is bonded with a heat... Agent: Schwegman, Lundberg & Woessner, P.a.

20080191359 - Panel, semiconductor device and method for the production thereof: A panel has a baseplate with an upper first metallic layer and a multiplicity of a vertical semiconductor components. The vertical semiconductor components in each case have a first side with a first load electrode and a control electrode and an opposite second side with a second load electrode. The... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20080191360 - Adhesive strip conductor on an insulating layer: A device is disclosed with at least one electrically insulating layer on which at least one conductor structure made of electrically conductive material is placed. In at least one embodiment, the conductor structure on the side facing the insulating layer has at least one elevation that is accommodated in at... Agent: Harness, Dickey & Pierce, P.L.C

20080191364 - Apparatus for stacking semiconductor chips, method for manufacturing semiconductor package using the same and semiconductor package manufactured thereby: The present invention relates to an apparatus for stacking semiconductor chips, a method for manufacturing a semiconductor package using the same and a semiconductor package manufactured thereby. The apparatus for stacking semiconductor chips may comprise two tables for supporting wafers, a picker for picking up semiconductor chips and a picker... Agent: Marger Johnson & Mccollom, P.c.

20080191363 - Architecture for face-to-face bonding between substrate and multiple daughter chips: An integrated circuit system includes a first integrated circuit die and a family of second integrated circuit dice. The first integrated circuit die have input/output circuits disposed thereon and further have a first array of face-to-face bonding structures disposed on a first face thereof. Each member of the family of... Agent: Lewis And Roca LLP

20080191361 - Electronic device comprising an integrated circuit: An electronic device (ICD) comprises a signal ground contact (LD1) for coupling the electronic device to signal ground, a die pad, and an integrated circuit. The die pad (DPD) is provided with a protrusion (PTR3) that is electrically coupled to the signal ground contact. The integrated circuit (PCH) has a... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080191362 - Semiconductor package having impedance matching device: A semiconductor package having an impedance matching device is disclosed, which is especially applicable to conventional system-in-package structures and system packaging design with high-density I/O design. The impedance matching device achieves impedance matching between a semiconductor chip and a signal transmission wiring on the substrate or between different systems integrated... Agent: Madson & Austin

20080191365 - Optical semiconductor device: An optical semiconductor device includes a first electrode joined to a first joining face of a mounting portion that is provided in one of a main surface and a back surface of a semiconductor chip, and a second electrode joined to a second joining face of the mounting portion that... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080191366 - Bumping process and bump structure: A bumping process comprises forming a passivation layer having a planarized surface covering a pad on a substrate, forming a hole penetrating through the passivation layer to expose a contact surface of the pad, and forming a bump on the contact surface and planarized surface. The planarized surface will provide... Agent: Rosenberg, Klein & Lee

20080191367 - Semiconductor package wire bonding: A stacked die semiconductor package comprises a die coupled to a substrate, the first die having a die bonding area, a bonding wire supporting layer affixed to a top surface of the first die, and a bonding wire bonded to the die bonding area and to a substrate bonding area... Agent: Klarquist Sparkman, LLP

20080185567 - Methods for forming resistive switching memory elements: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a... Agent: G. Victor Treyz

20080185568 - Nonvolatile memory devices and method of manufacturing the same: Example embodiments provide a nonvolatile memory device using resistive elements. The nonvolatile memory device may include a semiconductor substrate, a plurality of variable resistance patterns on the semiconductor substrate, and a plurality of heat sink patterns that are level with the variable resistance patterns and coupled to a ground voltage.... Agent: Harness, Dickey & Pierce, P.L.C

20080185569 - Phase change random access memories including a word line formed of a metal material and methods of forming the same: A phase change memory includes a word line disposed on a semiconductor substrate and a cell diode that physically contacts the semiconductor substrate and a corresponding word line. The word line may be formed of a metal, such as tungsten. Accordingly, no metal contact is included and the word line... Agent: Myers Bigel Sibley & Sajovec

20080185570 - Phase change material (pcm) memory devices with bipolar junction transistors and methods for making thereof: Methods for fabricating highly compact PCM memory devices are described herein. The methods may include forming a bipolar junction transistor (BJT) structure on a substrate including creating a base of the BJT structure on the substrate and creating an emitter of the BJT structure on top of the base opposite... Agent: Schwabe, Williamson & Wyatt, P.C.

20080185575 - Manufacture method of multilevel phase-change memory and operating method thereof: A manufacture method of a multilevel phase-change memory and operating method thereof are provided. The method includes providing a substrate, forming a bottom electrode on the substrate, forming a first heating layer on top of the bottom electrode, forming a second heating layer on top of the first heating layer,... Agent: Birch Stewart Kolasch & Birch

20080185574 - Method of forming non-volatile resistance variable devices: A method of forming a non-volatile resistance variable device includes forming a first conductive electrode material on a substrate. A metal doped chalcogenide comprising material is formed over the first conductive electrode material. Such comprises the metal and AxBy, where “B” is selected from S, Se and Te and mixtures... Agent: Dickstein Shapiro LLP

20080185572 - Methods for forming resistive switching memory elements: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a... Agent: G. Victor Treyz

20080185573 - Methods for forming resistive switching memory elements: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a... Agent: G. Victor Treyz

20080185571 - Resistive memory including buried word lines: An integrated circuit including a memory cell includes a vertical bipolar select device including a base and an emitter. The memory cell includes a resistive memory element coupled to the emitter and a buried metallized word line contacting the base.... Agent: Dicke, Billig & Czaja

20080185576 - Error corrected quantum computer: This invention concerns quantum error correction, that is the correction of errors in the transport and processing of qubits, by use of logical qubits made up of a plurality of physical qubits. The process takes place on a spatial array of physical qubit sites arranged with a quasi-2-dimensional topology having... Agent: Wood, Phillips, Katz, Clark & Mortimer

20080185577 - Diimide-based semiconductor materials and methods of preparing and using the same: Diimide-based semiconductor materials are provided with processes for preparing the same. Composites and electronic devices including the diimide-based semiconductor materials also are provided.... Agent: Kirkpatrick & Lockhart Preston Gates Ellis LLP (formerly Kirkpatrick & Lockhart Nicholson Graham)

20080185578 - Memory device: A memory device is provided, which includes a first conductive layer, a second conductive layer, and a memory layer interposed between the first conductive layer and the second conductive layer. The memory layer includes a first portion and a second portion, each of which includes at least a nanoparticle. The... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080185579 - Buried circumferential electrode microcavity plasma device arrays, electrical interconnects, and formation method: A preferred embodiment microcavity plasma device array of the invention includes a plurality of first metal circumferential metal electrodes that surround microcavities in the device. The first circumferential electrodes are buried in a metal oxide layer and surround the microcavities in a plane transverse to the microcavity axis, while being... Agent: Greer, Burns & Crain

20080185580 - Epitaxial growth of zno with controlled atmosphere: A ZnO crystal growth method has the steps of (a) preparing a substrate having a surface capable of growing ZnO crystal exposing a Zn polarity plane; (b) supplying Zn and O above the surface of the substrate by alternately repeating a Zn-rich condition period and an O-rich condition period; and... Agent: Masao Yoshimura, Chen Yoshimura, LLP

20080185586 - High performance sub-system design and assembly: A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively... Agent: Mou-shiung Lin

20080185585 - Imaging device equipped with a last copper and aluminum based interconnection level: A microelectronic device may include a substrate, a plurality of components on the substrate, an insulating layer adjacent the substrate, and a plurality of metallic interconnection levels within the insulating layer and for the plurality of components. The plurality of metallic interconnection levels may include at least one given metallic... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080185582 - Portable memory devices: Improved techniques to produce integrated circuit products are disclosed. The improved techniques permit smaller and less costly production of integrated circuit products. One aspect of the invention concerns covering test contacts (e.g., test pins) provided with the integrated circuit products using printed ink. Once covered with the ink, the test... Agent: Technology & Innovation Law Group, PC Attn: 1901

20080185584 - Semiconductor device test structures and methods: Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line disposed in a first conductive material layer, and a stress line disposed in the first conductive material layer proximate the feed line yet spaced apart from the feed line. The stress... Agent: Slater & Matsil LLP

20080185581 - Silicon-on-insulator (\"soi\") transistor test structure for measuring body-effect: According to one exemplary embodiment, a silicon-on-insulator (SOI) transistor test structure includes a gate situated over a semiconductor body and a doped halo under the gate. The SOI transistor test structure further includes at least two semiconductor body contacts situated on opposing sides of the doped halo, where one or... Agent: Farjami & Farjami LLP

20080185583 - Structure and method for monitoring and characterizing pattern density dependence on thermal absorption in a semiconductor manufacturing process: According to the present invention, there is disclosed a thermal detection device and method of using the device for characterizing and monitoring the dependence of pattern density on thermal absorption of a semiconductor. One or more of the devices can be disposed on a die of a test wafer. The... Agent: International Business Machines Corporation Dept. 18g

20080185587 - Display panel and method of manufacture: A display panel and a manufacturing method in which the display panel includes an alkali-containing glass substrate having a surface waviness of less about 0.06 μm, a gate electrode formed the substrate, a gate insulating layer formed on the gate electrode, a semiconductor formed on the gate insulating layer, a... Agent: Macpherson Kwok Chen & Heid LLP

20080185589 - Display substrate having the same and method of manufacturing the display substrate: A display substrate includes a thin-film transistor (TFT) layer, a color filter layer and a pixel electrode formed on a substrate. The TFT layer includes a gate line, a data line electrically insulated from the gate line and extending in a direction different from the gate line, a TFT electrically... Agent: Macpherson Kwok Chen & Heid LLP

20080185588 - Display substrate, display device and method of manufacturing the same: A flexible display substrate includes: a thin film transistor on the flexible substrate, the thin film transistor including a gate electrode, a gate insulating layer insulating the gate electrode, a channel layer on the gate insulating layer, a source electrode connected with the channel layer, and a drain electrode connected... Agent: Mckenna Long & Aldridge LLP

20080185591 - Structure and method for thin film device: Provided is a thin film device and an associated method of making a thin film device. For example, a thin film transistor with nano-gaps in the gate electrode. The method involves providing a substrate. Upon the substrate are then provided a plurality of parallel spaced electrically conductive strips. A plurality... Agent: Hewlett Packard Company

20080185590 - Thin film transistor array panel and method for manufacturing the same: A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080185592 - Semiconductor substrate with multiple crystallographic orientations: A pair of semiconductor structures and a method for fabricating a semiconductor structure each utilize a semiconductor substrate having a first crystallographic orientation, and a dielectric layer located thereupon. The method provides for epitaxially growing a semiconductor layer on the semiconductor substrate to encapsulate the dielectric layer. The method also... Agent: Scully Scott Murphy & Presser, PC

20080185594 - Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices: A method manufactures a vertical power MOS transistor on a semiconductor substrate comprising a first superficial semiconductor layer of a first conductivity type, comprising: forming trench regions in the first semiconductor layer, filling in said trench regions with a second semiconductor layer of a second conductivity type, to form semiconductor... Agent: Seed Intellectual Property Law Group PLLC

20080185593 - Power field effect transistor and manufacturing method thereof: A method of manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate having a wide band gap superficial semiconductor layer, including the steps of forming a screening structure on the superficial semiconductor layer that leaves a plurality of areas of the superficial semiconductor layer exposed, carrying... Agent: Seed Intellectual Property Law Group PLLC

20080185595 - Light emitting device for alternating current source: There is provided a light emitting device that can reduce the size of a light emitting device module by using a more simplified light emitting device that directly uses an alternating current source, prevent a decrease in luminous efficiency that is caused due to the use of a separate driving... Agent: Mcdermott Will & Emery LLP

20080185596 - System for displaying images: Embodiments of a system for displaying images include a light emitting device with a plurality of photo sensors. Each photo sensor includes a PIN diode composed of an N+ doped semiconductor region, a P+ doped semiconductor region, and an intrinsic semiconductor region formed therebetween. An insulated control gate overlaps the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080185598 - Light emitting device: A light emitting device includes: a heat dissipating seat of a metallic material; a chip-mounting base of a semiconductor material attached to the heat dissipating seat; an insulator layer formed on the chip-mounting base; a bonding layer of a metal formed on the insulator layer; and a light emitting chip... Agent: Greenblum & Bernstein, P.L.C

20080185597 - Light-emitting module: A light-emitting module includes a base, a connecting unit disposed on the base, a light-emitting unit disposed on the base, and a drive unit electrically coupled to and bridging the connecting unit and the light-emitting unit for driving the light-emitting unit. The base includes a plurality of first bonding pads... Agent: Foley And Lardner LLP Suite 500

20080185599 - Light emitting element and manufacturing method thereof: In order to provide a light emitting device which consistently emits light at the time of continuous driving in addition to obtain light emission having a high color purity in each of red, green and blue, a light emitting element according to the present invention, in which an organic compound... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080185605 - Light-emitting diode and method for producing it: An LED includes a circuit board (1), a light emitter (3) mounted on the circuit board (1), and a reflector (4) mounted on the circuit board (1), the light emitter (3) including an LED element mounted on the circuit board (1) and a light-transmitting resin (2) to seal the LED... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080185604 - Lighting emitting device employing nanowire phosphors: Disclosed is a light emitting device employing nanowire phosphors. The light emitting device comprises a light emitting diode for emitting light having a first wavelength with a main peak in an ultraviolet, blue or green wavelength range; and nanowire phosphors for converting at least a portion of light having the... Agent: H.c. Park & Associates, PLC

20080185603 - Optical device and method for manufacturing optical device, and camera module and endoscope module equipped with optical device: An optical device is equipped with a light receiving region 16a and a peripheral circuit region 22 located around the light receiving region 16a on a major surface of an light receiving element 11a; electrodes for external connection 15 electrically connected to the peripheral circuit region 22 formed on a... Agent: Steptoe & Johnson LLP

20080185600 - Phosphor particles with plural coatings for leds: A light emitting semiconductor device including a light emitting diode having a cascading phosphor is improved by the particles of phosphor being coated with a moisture barrier layer and a buffer layer. Either the buffer layer overlies the moisture barrier layer or the moisture barrier layer overlies the buffer layer.... Agent: Paul F. Wille Cantor Colburn LLP

20080185602 - Preparation of white light emitting diode using a phosphor: The present invention relates to a method for preparing a white light emitting diode (LED) using phosphors, especially to a white light emitting diode prepared by applying a tri-color phosphor material mixture of red, blue and green on a UV LED chip made of a packaging substrate, where white light... Agent: Frommer Lawrence & Haug

20080185601 - Process and silicone encapsulant composition for molding small shapes: A process includes the steps of: 1) heating a mold at a temperature ranging from 100° C. to 200° C.; 2) feeding a silicone encapsulant composition including a mold release agent, where the composition has a viscosity ranging from 100 cps to 3,000 cps at operating temperatures of the process,... Agent: Dow Corning Corporation Co1232

20080185606 - Semiconductor light emitting element: A semiconductor light emitting element including a light emitting section, a first electrode, and a second electrode on a semiconductor structure including first and second conductive type semiconductor layers, the first and the second electrodes being arranged on the first conductive type semiconductor layer and a second conductive type semiconductor... Agent: Birch Stewart Kolasch & Birch

20080185609 - Electrode and group iii nitride-based compound semiconductor light-emitting device having the electrode: An object of the invention is to prevent migration of silver contained in an electrode of a Group III nitride-based compound semiconductor light-emitting device. An n-type AlxGayIn1-x-yN layer, a light-emitting layer, and a p-type AlxGayIn1-x-yN layer are formed on a dielectric substrate such as a sapphire substrate. After formation of... Agent: Mcginn Intellectual Property Law Group, PLLC

20080185607 - Light emitting diode module and display device having the same: A light emitting diode (LED) module which includes a light emitting diode which includes a light emitting chip, a first electrode and a second electrode, the first and second electrodes being electrically connected to the light emitting chip. The light-emitting diode is supported on a printed circuit board. The printed... Agent: Macpherson Kwok Chen & Heid LLP

20080185608 - Ohmic contacts to nitrogen polarity gan: Contacting materials and methods for forming ohmic contact to the N-face polarity surfaces of Group-III nitride based semiconductor materials, and devices fabricated using the methods. One embodiment of a light emitting diode (LED) a Group-III nitride active epitaxial region between two Group-III nitride oppositely doped epitaxial layers. The oppositely doped... Agent: Koppel, Patrick & Heybl

20080185610 - Resin-sealed semiconductor light receiving element, manufacturing method thereof and electronic device using the same: A resin-sealed semiconductor light receiving element in which a light receiving element mounted on a circuit board is sealed with a transparent resin. A mounting face of the circuit board on which the light receiving element is mounted is sealed with a transparent epoxy resin so that a light receiving... Agent: Birch Stewart Kolasch & Birch

20080185611 - Preparation method of a coating of gallium nitride: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080185612 - Semiconductor device and manufacturing method: A semiconductor device has a Si substrate, a gate insulating film over the Si substrate, a gate electrode over the gate insulating film, a source region and a drain region in the Si substrate, wherein each of the source region and the drain region includes a first Si layer including... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080185613 - Iii-nitride semiconductor device: A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.... Agent: Ostrolenk Faber Gerb & Soffen

20080185614 - Integrated circuit assembly with passive integration substrate for power and ground line routing on top of an integrated circuit chip: An integrated circuit assembly (ICA) comprises: a digital and/or analog integrated circuit (S1) having a core with input and/or output pins and at least one power supply connection pad (PP) and one ground connection pad (GP) connected to a chosen one of the input and/or output pins and respectively connected... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080185615 - Method and apparatus for double-sided biasing of nonvolatile memory: Methods and apparatuses are disclosed for biasing the source-side and the drain-side of a nonvolatile memory to add electrons to the charge trapping structure.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080185616 - Semiconductor device-based sensors and methods associated with the same: Semiconductor device-based chemical sensors and methods associated with the same are provided. The sensors include regions that can interact with chemical species being detected. The chemical species may, for example, be a component of a fluid (e.g., gas or liquid). The interaction between the chemical species and a region of... Agent: Wolf Greenfield & Sacks, P.C.

20080185617 - Strained mos device and methods for forming the same: A semiconductor structure includes a semiconductor substrate having a top surface; a gate stack on the semiconductor substrate; and a stressor in the semiconductor substrate and adjacent the gate stack. The stressor comprises at least a first portion with a first top surface lower than the top surface of the... Agent: Slater & Matsil, L.L.P.

20080185622 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same are disclosed, in which light that transmits through a microlens is prevented from being beyond a photodiode region to minimize loss of incident light and to improve low illumination characteristics of the CMOS image sensor. The CMOS image sensor... Agent: Mckenna Long & Aldridge LLP

20080185621 - Cmos image sensors: A complementary metal-oxide semiconductor (CMOS) image sensor comprises a photodiode region generating electrical charges in response to incident light thereon. The CMOS image sensor further comprises a first floating diffusion layer adapted to receive the electrical charges from the photodiode region in response to a global transfer signal and a... Agent: Volentine & Whitt PLLC

20080185620 - Method of manufacturing a cmos image sensor: The present invention relates to the method of manufacturing an image sensor, the method comprising providing a semiconductor substrate, which comprises a pixel array area and a logic area, a plurality of the photodiodes are formed on the semiconductor substrate of the pixel array area, a multilevel interconnect process is... Agent: North America Intellectual Property Corporation

20080185619 - Pinned photodiode cmos pixel sensor: A multicolor CMOS pixel sensor formed in a p-type semiconductor region includes a first detector formed from an n-type region of semiconductor material located near the surface of the p-type region. A first pinned p-type region is formed at the surface of the p-type region over the first detector, and... Agent: Lewis And Roca, LLP

20080185618 - Structure for and method of fabricating a high-speed cmos-compatible ge-on-insulator photodetector: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by... Agent: Scully, Scott, Murphy & Presser, P.C.

20080185623 - Ferroelectric memory device and fabrication process thereof, fabrication process of a semiconductor device: A method for fabricating a ferroelectric memory device, including terminating a surface of the interlayer insulation film and a surface of the contact plug with an OH group; forming a layer containing Si, oxygen and a CH group on the surface of the interlayer insulation film and the contact hole... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080185624 - Storage capacitors for semiconductor devices: Methods of forming a storage capacitor include forming an interlayer insulation layer having an opening there through on a semiconductor substrate, forming a contact plug in the opening, forming a molding oxide layer on the interlayer insulation layer and the contact plug, selectively removing portions of the molding oxide layer... Agent: Myers Bigel Sibley & Sajovec

20080185625 - Source/drain to gate capacitive switches and wide tuning range varactors: A two-terminal capacitive circuit element 100 includes a MOS transistor including a source 126 and drain 127 separated by a body region 131, and a gate 105 separated from the body 129 by a gate insulator layer 110, and a bypass capacitor 125. The gate node (port2; 115) is AC... Agent: Akerman Senterfitt

20080185626 - Trench capacitor and method for fabricating the same: A trench capacitor with an isolation collar in a semiconductor substrate where the substrate adjacent to the isolation collar is free of dopants caused by auto-doping. The method of fabricating the trench capacitor includes the steps of forming a trench in the semiconductor substrate; depositing a dielectric layer on a... Agent: International Business Machines Corporation Dept. 18g

20080185627 - Rfid tag having non-volatile memory device having floating-gate fets with different source-gate and drain-gate border lengths: Non-volatile memory (NVM) devices are disclosed. In one aspect, a NVM device may include a substrate, and a field-effect transistor (FET). The FET may include a first doped region in the substrate and a second doped region in the substrate. The first and the second doped regions may define a... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080185628 - Semiconductor device and method of manufacturing the same: A semiconductor device in accordance with one embodiment of the invention can include a semiconductor substrate having a groove, a bit line, a pocket implantation region, a bottom insulating membrane, and a charge accumulation region. The bit line is formed on a side of the groove in the semiconductor substrate... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20080185631 - Dielectric layer for semiconductor device and method of manufacturing the same: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.... Agent: Marger Johnson & Mccollom, P.C.

20080185629 - Semiconductor device having variable operating information: A semiconductor device includes: a semiconductor substrate; multiple MOS type first transistors coupled in parallel with a current path; and a nonvolatile memory for memorizing operating information. Each transistor includes first and second electrodes and a gate electrode for controlling current flowing therebetween. Based on the operating information, each first... Agent: Posz Law Group, PLC

20080185630 - Stacked gate nonvolatile semiconductor memory and method for manufacturing the same: A stacked gate nonvolatile semiconductor memory includes at least a memory cell transistor and a selective gate transistor which are formed on a semiconductor substrate. The memory cell transistor includes a floating gate made of a semiconductor material below an interlayer insulating layer and a control gate made of a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080185633 - Charge trap memory device with blocking insulating layer having higher-dielectric constant and larger energy band-gap and method of manufacturing the same: A charge trap memory device according to example embodiments may include a tunnel insulating layer provided on a substrate. A charge trap layer may be provided on the tunnel insulating layer. A blocking insulating layer may be provided on the charge trap layer, wherein the blocking insulating layer may include... Agent: Harness, Dickey & Pierce, P.L.C

20080185632 - Method for improving erase saturation in non-volatile memory devices and devices obtained thereof: Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080185634 - Structures for and method of silicide formation on memory array and peripheral logic devices: A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage transistors. A second gate dielectric layer having... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080185635 - Semiconductor storage device and manufacturing method thereof: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of... Agent: Miles & Stockbridge PC

20080185637 - Insulated gate field effect transistor and a method of manufacturing the same: Disclosed herein is an insulated gate field effect transistor including: (A) a source/drain region and a channel formation region; (B) a gate electrode formed above the channel formation region; and (C) a gate insulating film; wherein the gate insulating film is composed of a gate insulating film main body portion... Agent: Sonnenschein Nath & Rosenthal LLP

20080185636 - Semiconductor structure including doped silicon carbon liner layer and method for fabrication thereof: A semiconductor structure and related method for fabrication thereof includes a liner layer interposed between: (1) a pedestal shaped channel region within a semiconductor substrate; and (2) a source region and a drain region within a semiconductor material layer located upon the liner layer and further laterally separated from the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080185641 - Recessed transistor and method of manufacturing the same: A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The... Agent: Harness, Dickey & Pierce, P.L.C

20080185640 - Semiconductor device: A first main electrode is provided on one surface thereof. On the other surface thereof, a second semiconductor layer of the first conduction type and a third semiconductor layer of the second conduction type are arranged alternately along the surface. A fourth semiconductor layer of the second conduction type and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080185638 - Semiconductor device and method of fabricating the same: A semiconductor device capable of inhibiting a fabricating process from complication while inhibiting the dielectric strength voltage of a insulating film from reduction is obtained. This semiconductor device includes a groove portion, an insulating film formed on a surface of the groove portion, a gate electrode and a source impurity... Agent: Ditthavong Mori & Steiner, P.C.

20080185639 - Semiconductor device and method of manufacturing the same: Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of... Agent: Brinks Hofer Gilson & Lione

20080185642 - Trench mosfet with deposited oxide: A trench type power semiconductor device which includes deposited rather than grown oxide in the trenches for the electrical isolation of electrodes disposed inside the trenches from the semiconductor body.... Agent: Ostrolenk Faber Gerb & Soffen

20080185643 - Semiconductor device having trench edge termination structure: In one embodiment, a device is formed in a region of semiconductor material. The device includes active cell trenches and termination trenches each having doped sidewall surfaces that compensate the region of semiconductor material during reverse bias conditions to form a superjunction structure. The termination trenches include a trench fill... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20080185644 - Fets with self-aligned bodies and backgate holes: A FET has a shallow source/drain region, a deep channel region, a gate stack and a back gate that is surrounded by dielectric. The FET structure also includes halo or pocket implants that extend through the entire depth of the channel region. Because a portion of the halo and well... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080185646 - Floating body dynamic random access memory with enhanced source side capacitance: A floating body dynamic random access memory (DRAM) structure has a shallow source (first source portion) and a deep source (second source portion), of which the deep source is thicker. A portion of the floating body extends beneath the shallow source to provide extra capacitance. Optionally, the portion of the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080185647 - Methods of forming semiconductor-on-insulator substrates, and integrated circuitry: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures... Agent: Wells St. John P.s.

20080185648 - One transistor dram device and method of forming the same: A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and... Agent: Myers Bigel Sibley & Sajovec

20080185645 - Semiconductor structure including stepped source/drain region: A semiconductor structure includes a stepped source and drain region located in part within a semiconductor substrate that preferably has a step in a direction of a gate electrode located over a channel region that adjoins the stepped source and drain region within the semiconductor substrate. A stepped portion of... Agent: Scully, Scott, Murphy & Presser, P.C.

20080185649 - Substrate backgate for trigate fet: Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080185650 - Finfet for device characterization: A method and system is disclosed for providing access to the body of a FinFET device. In one embodiment, a FinFET device for characterization comprises an active fin comprising a source fin, a depletion fin, and a drain fin; a side fin extending from the depletion fin and coupled to... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080185651 - Soi type semiconductor device having a protection circuit: An SOI type semiconductor device having a silicon substrate and a buried oxide layer formed on the silicon substrate includes an internal circuit formed in a first region having at least one FD type transistor having a SOI structure, the internal circuit performing a function of the semiconductor device and... Agent: Junichi Mimura Oki America Inc.

20080185652 - Simultaneous conditioning of a plurality of memory cells through series resistors: Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080185653 - Semiconductor integrated circuit device: To reduce the leak current in the MOSFET connected between the pad and the ground. There are provided a pad PAD for an input or output signal, an n-type MOSFET M1a connected between the pad PAD and the ground and having its gate terminal and backgate connected in common, and... Agent: Mcginn Intellectual Property Law Group, PLLC

20080185654 - Electronic device including a semiconductor fin having a plurality of gate electrodes and a process for forming the electronic device: An electronic device can include a semiconductor fin with a first gate electrode adjacent to a first wall, and a second gate electrode adjacent to a second wall. In one embodiment, a conductive member can be formed overlying the semiconductor fin, and a portion of the conductive member can be... Agent: Larson Newman Abel Polansky & White, LLP

20080185658 - Buried stress isolation for high-performance cmos technology: A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of the substrate, wherein the high-stress film comprises... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080185657 - Dual stress liner: A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second... Agent: International Business Machines Corporation Dept. 18g

20080185656 - Semiconductor device and method for manufacturing the same: It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080185655 - Smiconductor device, method for fabricating thereof and method for increasing film stress: A method for forming a semiconductor device is provided. The method comprises steps of providing a substrate having a first-conductive-type transistor and a second-conductive-type transistor formed thereon and then forming a stress layer over the substrate to conformally cover the first-conductive-type transistor and the second-conductive-type transistor. A cap layer is... Agent: J C Patents, Inc.

20080185659 - Semiconductor device and a method of fabricating the device: A semiconductor device having at least one transistor covered by an ultra-stressor layer, and method for fabricating such a device. In an NMOS device, the ultra-stressor layer includes a tensile stress film over the source and drain regions, and a compressive stress film over the poly region. In a PMOS... Agent: Slater & Matsil, L.L.P.

20080185660 - Semiconductor device and method of forming the same: The invention provides a semiconductor device and a method of forming the same. The method of forming the semiconductor device includes preparing a P-type semiconductor substrate including a low-voltage NMOS region, low-voltage PMOS region, high-voltage NMOS region, and high-voltage PMOS region; forming an N-well in the low-voltage PMOS region and... Agent: Mills & Onello LLP

20080185661 - Semiconductor device and method for fabricating the same: A first MIS transistor includes: a first gate insulating film formed on a first active region; a first gate electrode formed on the first gate insulating film; first sidewall insulating films formed on side surfaces of the first gate electrode; first source/drain regions formed at outer sides of the first... Agent: Mcdermott Will & Emery LLP

20080185662 - Structure and method for forming asymmetrical overlap capacitance in field effect transistors: A method for forming asymmetric spacer structures for a semiconductor device includes forming a spacer layer over at least a pair of adjacently spaced gate structures disposed over a semiconductor substrate. The gate structures are spaced such that the spacer layer is formed at a first thickness in a region... Agent: Cantor Colburn LLP - IBM Fishkill

20080185663 - Semiconductor device with increased channel length and width and method for manufacturing the same: A semiconductor device includes a semiconductor substrate having an active region including a channel portion. An isolation layer is formed in the semiconductor substrate to define the active region, and a gate is formed over the channel portion in the active region. The active region of the semiconductor substrate is... Agent: Ladas & Parry LLP

20080185664 - High voltage transistors: Some embodiments of the present invention provide high voltage transistors including a semiconductor substrate and a device isolation film defining an active region in the semiconductor substrate. A gate electrode extends along a central portion of the active region while maintaining a predetermined width on the semiconductor substrate. A second... Agent: Myers Bigel Sibley & Sajovec

20080185666 - Field effect transistors including variable width channels and methods of forming the same: A field effect transistor includes a first substrate region having a channel region and a second substrate region where a heavily doped region is formed. The channel region includes a first portion having a first width and a second portion having a second width larger than the first width. Related... Agent: Myers Bigel Sibley & Sajovec

20080185665 - Source and drain structures and manufacturing methods: A semiconductor structure includes a semiconductor substrate; a first gate dielectric on the semiconductor substrate; a first gate electrode over the first gate dielectric; a first lightly doped source or drain (LDD) region in the semiconductor substrate and adjacent the first gate dielectric, wherein the first LDD region comprises arsenic;... Agent: Slater & Matsil, L.L.P.

20080185667 - Thin film semiconductor device and method for manufacturing the same: An Mo film (6) is formed on a SiO2 film (5) by particularly using the film thickness and the deposition temperature (ambient temperature in a sputtering chamber) as the primary parameters and adjusting the film thickness to be within the range from 100 nm to 500 nm (more preferably 100... Agent: Nixon & Vanderhye, PC

20080185668 - Memory device and method of fabricating the same: A memory device may include a substrate, a bit line, at least a first lower word line, at least a first trap site, a pad electrode, at least a first cantilever electrode, and/or at least a first upper word line. The bit line may be formed on the substrate in... Agent: Harness, Dickey & Pierce, P.L.C

20080185669 - Silicon microphone: A silicon microphone includes a diaphragm that is able to flex over an aperture, an area allowing electrical connection to the diaphragm, a backplate parallel to and spaced apart from the diaphragm and extending over the aperture, the backplate being fixed, the backplate and diaphragm forming the parallel plates of... Agent: Ohlandt, Greeley, Ruggiero & Perle, LLP

20080185670 - Magnetic random access memory and method of manufacturing the same: A magnetic random access memory includes an interlayer dielectric film having a contact hole, a contact formed in the contact hole, a first barrier metal film formed on an upper surface of the contact and buried in the contact hole, a magnetoresistive effect element having one terminal connected to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080185672 - Miniaturized imaging device with integrated circuit connector system: A miniaturized imaging device and method of viewing small luminal cavities are described. The imaging device can be used as part of a catheter, and can include a lens, an SSID including an imaging array optically coupled to the lens; an umbilical including a conductive line; and an adaptor configured... Agent: Thorpe North & Western, LLP.

20080185671 - Sensor semiconductor package and fabrication: A sensor semiconductor package and a fabrication method thereof are provided in the present application. The fabrication method comprises steps of: forming a plurality of grooves on a wafer between bond pads on active surfaces of every adjacent chips; forming metal layers in the grooves for electrically connecting with the... Agent: Edwards Angell Palmer & Dodge LLP

20080185673 - Semiconductor chip module: One aspect includes a sensor chip module including a sensor chip and a module housing accommodating the sensor chip. The module housing defines a mounting plane of the sensor chip module. In one case, an active surface of the sensor chip is inclined with respect to the mounting plane of... Agent: Dicke, Billig & Czaja

20080185674 - Method of fabricating image sensor photodiodes using a multi-layer substrate and contact method and the structure thereof: The present invention relates to a photodiode of an image sensor using a three-dimensional multi-layer substrate, and more particularly, to a method of implementing a buried type photodiode and a structure thereof, and a trench contact method for connecting a photodiode in a multi-layer substrate and a transistor for signal... Agent: Brinks Hofer Gilson & Lione

20080185675 - Trench isolation structure and a method of manufacture therefor: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having a buffer layer (133) located on sidewalls... Agent: Texas Instruments Incorporated

20080185676 - Method for forming sti of semiconductor device: A method for forming a STI of a semiconductor device includes steps of sequentially forming a pad oxide film and a pad nitride film on the semiconductor device and carrying out a pattern process PR; etching the pad oxide film and the nitride film and carrying out a cleaning process;... Agent: Lowe Hauptman Ham & Berner, LLP

20080185677 - Low-voltage organic thin film transistor and fabrication method thereof: The present invention provides an organic thin film transistor (OTFT) being operatable at a low-voltage. The OTFT has a gate dielectric layer of ultra-thin metal oxide or a dual gate dielectric layer of metal oxide and organic dielectric. The metal oxide layer is self-grown to a thickness lower than 10... Agent: Ipla P.A.

20080185678 - Semiconductor device and method of manufacturing the same: A fuse element is laminated on a resistor and the resistor is formed in a concave shape below a region in which cutting of the fuse element is carried out with a laser. Accordingly, there can be provided a semiconductor device which occupies a small area, causes no damage on... Agent: Brinks Hofer Gilson & Lione

20080185679 - Inductor layout and manufacturing method thereof: An inductor layout and manufacturing method thereof are provided. The inductor layout includes a substrate and a conductive path. The substrate includes at least an active region, wherein the active region includes at least a circuit. The conductive path is disposed over the substrate and arranged near the edge of... Agent: Jianq Chyun Intellectual Property Office

20080185682 - High voltage metal-on-passivation capacitor: A capacitor is formed in an integrated circuit where the integrated circuit is fabricated using a fabrication process having multiple metal layers with the topmost metal layer being passivated by a passivation layer. The capacitor includes a first metal pad formed underneath the passivation layer using the topmost metal layer... Agent: Patent Law Group LLP

20080185681 - Integrated circuit comprising a capacitor with metal electrodes and process for fabricating such a capacitor: An integrated circuit (IC) includes at least one capacitor with metal electrodes. At least one of the electrodes (10 or 30) is formed from at least surface-silicided hemispherical grain silicon or silicon alloy. A fabrication process for obtaining such a capacitor with silicided metal electrodes is also provided.... Agent: Fleit, Kain, Gibbons, Gutman, Bongini & Bianco P.l.

20080185684 - Method and structure for integrating mim capacitors within dual damascene processing techniques: A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer... Agent: Cantor Colburn LLP - IBM Fishkill

20080185683 - Semiconductor memory device and manufacturing method thereof: A semiconductor memory device includes diffusion regions formed in an active region; cell contacts connected to the diffusion regions, respectively; pillars connected to the cell contacts, respectively; a bit line connected to the pillar; capacitor contacts connected to the pillars, respectively; and storage capacitors connected to the capacitor contacts, respectively.... Agent: Sughrue Mion, PLLC

20080185680 - Structure and method for making on-chip capacitors with various capacitances: A method for manufacturing a device includes forming trenches of different morphologies into a substrate. At the upper surfaces, the trenches have different orientations with respect to each other. In an aspect, windows for the trenches are aligned along the <100> and <110> directions of a silicon substrate. The trenches... Agent: Greenblum & Bernstein, P.L.C

20080185685 - Semiconductor device: Disclosed is a semiconductor device which has a circuit-forming region. The semiconductor device has a semiconductor substrate, a plurality of insulating interlayer films, a guard ring, and a first MIM capacitor. The insulating interlayer films, which are stacked one upon another, are provided over the semiconductor substrate. The guard ring... Agent: Young & Thompson

20080185686 - Electronic device with connection bumps: Flip-chip electronic devices (40, 70, 80, 90) employ bumps (42, 72, 82) for coupling to an external substrate. Device cells (43, 73, 83, 93) and bumps (42, 72, 82) are preferably arranged in clusters (46) where four bumps (42, 72, 82) substantially surround each device cell (43, 73, 83, 93)... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080185687 - Memory device and method for fabricating the same: A memory device includes a lower electrode layer formed over a substrate, a resistance layer including a metal nitride layer formed over the lower electrode layer, and an upper electrode layer formed over the resistance layer.... Agent: Townsend And Townsend And Crew, LLP

20080185688 - Layout of an integrated circuit: Various methods for determining a layout of an integrated circuit are described. For example, a method is described comprising determining a layout of an integrated circuit comprising a plurality of functional cells, wherein a maximum extent of each of the cells in a first direction is identical and wherein an... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20080185689 - Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus: A semiconductor device includes a substrate having a resin layer on at least a surface thereof; a thin-film circuit layer provided on the substrate, and a reinforcing section provided on the surface of the substrate so as to surround the thin-film circuit layer.... Agent: Advantedge Law Group, LLC

20080185690 - Defect reduction of non-polar and semi-polar iii-nitrides with sidewall lateral epitaxial overgrowth (sleo): A method of reducing threading dislocation densities in non-polar such as a-{11-20} plane and m-{1-100} plane or semi-polar such as {10-1n} plane III-Nitrides by employing lateral epitaxial overgrowth from sidewalls of etched template material through a patterned mask. The method includes depositing a patterned mask on a template material such... Agent: Gates & Cooper LLP Howard Hughes Center

20080185691 - Fin pin diode: Embodiments of the invention generally relate to the field of semiconductor devices, and more specifically to fin-based junction diodes. A portion of a doped semiconductor fin may protrude through a first doped layer. An intrinsic layer may be disposed on the protruding semiconductor fin. A second semiconductor layer may be... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20080185692 - Package-level electromagnetic interference shielding: A shielded electronic package, comprising a semiconductor device, an insulating housing surrounding the semiconductor device and a metal coating on the insulating housing. The metal coating covers all but those portions of the insulating housing that are adjacent to connective structures on one or more mounting sides of the insulating... Agent: Texas Instruments Incorporated

20080185693 - Integrated circuit package system with integral inner lead and paddle: An integrated circuit package system is provided including forming a paddle, an outer lead, and an inner lead between the paddle and the outer lead; forming a non-vertical paddle edge of the paddle and a non-vertical lead edge of the inner lead facing the non-vertical paddle edge; and encapsulating an... Agent: Law Offices Of Mikio Ishimaru

20080185694 - Processes of manufacturing portable electronic storage devices utilizing lead frame connectors: Portable electronic storage device (PESD) manufacturing methods utilizing lead frames are described. According to one exemplary embodiment, a process of manufacturing core unit of PESD comprises: producing a processed flash memory IC chip with several metal contact pads and at least one passive component located on top layer; pre-fabricating a... Agent: Roger H. Chu

20080185695 - Package-on-package device and method for manufacturing the same by using a leadframe: A POP device includes a leadframe, a first chip, an encapsulant and a second chip. The leadframe includes a die pad, a plurality of first and second leads. First leads have first top and bottom surfaces. Second leads include top leads, bottom leads and intermediate leads physically connected to top... Agent: Lowe Hauptman Ham & Berner, LLP

20080185697 - Chip package structure and method of fabricating the same: A method of fabricating a chip package structure includes the steps of providing a lead frame having a die pad, plural leads and at least one structure enhancement element. A chip is then disposed on the die pad and plural bonding wires are formed to electrically connect the chip to... Agent: Jianq Chyun Intellectual Property Office

20080185699 - Microelectromechanical system package and the method for manufacturing the same: A method for manufacturing a microelectromechanical system package is provided. A plurality of cavities is first formed on the upper and lower surfaces of a silicon wafer. Next, the lower surface of the silicon wafer is bonded to the microelectromechanical system wafer in such a manner that the active areas... Agent: Lowe Hauptman Ham & Berner, LLP

20080185696 - Semiconductor die package including leadframe with die attach pad with folded edge: A semiconductor die package is disclosed. The semiconductor die package comprises a leadframe structure with a die attach pad including a die attach surface, a folded edge structure and an opposite surface opposite to the die attach surface. A plurality of leads extending laterally away from the die attach pad.... Agent: Townsend And Townsend And Crew, LLP

20080185698 - Semiconductor package structure and carrier structure: A semiconductor package structure is disclosed. The structure comprises a die pad, a chip, leads, a recess, and an encapsulant. The chip is disposed on the die pad. The leads are disposed on a periphery of the die pad and electrically connected to the chip. The recess is formed on... Agent: J C Patents, Inc.

20080185700 - Adhesive film and method for manufacturing semiconductor device using same: The invention provides an adhesive tape which acts as a dicing tape which is excellent in dicing property and pickup property in a dicing step, and as an adhesive tape which is excellent in connection reliability in a step of bonding a semiconductor device with a supporting member. The adhesive... Agent: Buchanan, Ingersoll & Rooney PC

20080185701 - Hermetically sealed package and methods of making the same: Hermetically sealed packages having organic electronic devices are presented. A number of sealing mechanisms are provided to hermetically seal the package to protect the organic electronic device from environmental elements. A metal alloy sealant layer is employed proximate to the organic electronic device. Alternatively, a metal alloy sealant layer in... Agent: General Electric Company (pcpi) C/o Fletcher Yoder

20080185702 - Multi-chip package system with multiple substrates: A multi-chip package system is provided including providing a first carrier having a first integrated circuit die thereover, providing a second carrier, placing the first carrier coplanar with the second carrier, and molding a package encapsulation around and exposing the first carrier.... Agent: Law Offices Of Mikio Ishimaru

20080185704 - Carrier plate structure havign a chip embedded therein and the manufacturing method of the same: A carrier plate structure having a chip embedded therein, comprises an aluminum plate having plural through-holes extending from the upper surface to the lower surface of the aluminum plate, a cavity therein, and an aluminum oxide layer formed on the surface of the aluminum plate; a chip embedded in the... Agent: Bacon & Thomas, PLLC

20080185703 - Injection molded soldering process and arrangement for three-dimensional structures: A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an arrangement for implementing the injection molded soldering (IMS) process. Pursuant to an embodiment of the invention, the joining of the semiconductor chip layers with a... Agent: Scully, Scott, Murphy & Presser, P.C.

20080185705 - Microelectronic packages and methods therefor: A microelectronic package includes a microelectronic element having a first face including contacts, and a flexible substrate having a first surface and a second surface, conductive posts projecting from the first surface and conductive terminals accessible at the second surface, at least some of the conductive terminals and the conductive... Agent: Tessera Lerner David Et Al.

20080185706 - Package and method for making the same: The present invention relates to a package and a method for making the same. The package includes a substrate, a semiconductor element, and an underfill. The semiconductor element has a first surface. A plurality of bumps and at least one ring structure are disposed on the first surface, in which... Agent: Volentine & Whitt PLLC

20080185707 - Semiconductor package structure and method for manufacturing the same: A semiconductor package structure comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an optical component and a plurality of pads disposed on its active surface; pad extension traces are electrically connected to... Agent: Lowe Hauptman Ham & Berner, LLP

20080185710 - Chip package and process thereof: The chip package and the process thereof are disclosed. The chip package comprises a chip and a rigid cover. The chip has a plurality of bond pads formed thereon. The rigid cover is located on the chip and has a plurality of openings formed therein, wherein the openings expose the... Agent: J C Patents, Inc.

20080185709 - Semiconductor device including semiconductor elements and method of producing semiconductor device: A semiconductor device including a plurality of semiconductor elements on a substrate, the semiconductor device includes: a plurality of semiconductor elements being provided two-dimensionally on a first surface of the substrate via an adhesive layer; and a hard member on surfaces of the plurality of semiconductor elements, the surfaces being... Agent: Nixon & Vanderhye, PC

20080185708 - Stackable semiconductor package having metal pin within through hole of package: The present invention provides a stackable semiconductor having an interconnect board for providing electrical interconnections, the package includes a plurality of solders disposing onto the interconnect board; and a conducting metal pin passing through each solder and the interconnect board, the metal pins having at least one end disposes on... Agent: Troxell Law Office PLLC

20080185711 - Semiconductor package substrate: A semiconductor package substrate structure includes a circuit board with a plurality of first connection pads formed on at least a surface thereof; conductive posts formed on the surfaces of the first connection pads; and an insulative protection layer formed on the surface of the circuit board and having openings... Agent: Wpat, PC Intellectual Property Attorneys

20080185712 - Semiconductor device and method for manufacturing the same: A semiconductor device is provided in which the effect of the heat generated by a flip-chip mounted semiconductor on resin is suppressed. The semiconductor device includes: a substrate; a semiconductor chip which is mounted on the substrate with a front surface of the semiconductor chip facing downward; and a molding... Agent: Katten Muchin Rosenman LLP

20080185713 - Heat dissipating device with preselected designed interface for thermal interface materials: Embodiments of the invention includes a heat dissipating device. The heat dissipating device includes a main body having a surface, wherein the surface is plated or coated with at least two different metals to form a design effective for bonding to solder and for adhering to polymer in a polymer... Agent: Schwegman, Lundberg & Woessner, P.A.

20080185714 - Methods of forming channels on an integrated circuit die and die cooling systems including such channels: A method of forming channels on a die or other substrate. Also disclosed are liquid cooling systems including such channels.... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080185715 - Semiconductor device and method: A semiconductor device having a topology adjustment and a method for adjusting the topology of a semiconductor device. The semiconductor device includes a semiconductor wafer having first and second opposing sides with an active area formed on a first portion of the first side having a topology extending a first... Agent: Dicke, Billig & Czaja

20080185716 - Bump structure having a reinforcement member and manufacturing method thereof: A manufacturing method of a bump structure having a reinforcement member is disclosed. First, a substrate including pads and a passivation layer is provided. The passivation layer has first openings, and each first opening exposes a portion of the corresponding pad respectively. Next, an under ball metal (UBM) material layer... Agent: Jianq Chyun Intellectual Property Office

20080185718 - Nanostructure-based package interconnect: An embodiment of the present invention is an interconnect technique. A nanostructure bump is formed on a die. The nanostructure bump has a template defining nano-sized openings and metallic nano-wires extending from the nano-sized openings. The die is attached to a substrate via the nanostructure bump.... Agent: Intel/blakely

20080185717 - Semiconductor device including bump electrodes: A semiconductor device includes a semiconductor chip mounted on a printed circuit board with a chip electrode being coupled to a board electrode via a bump electrode. An insulating resin layer including therein conductive particles is interposed between the bump electrode and each of the chip electrode and board electrode.... Agent: Young & Thompson

20080185719 - Integrated circuit packaging system with interposer: An integrated circuit packaging system is provided including forming an interposer having a coupling slot, securing an upper die on the interposer, mounting the interposer over an integrated circuit, and coupling the integrated circuit to the upper die through the coupling slot.... Agent: Law Offices Of Mikio Ishimaru

20080185720 - Package structure and method for chip with two arrays of bonding pads on bga substrate for preventing gold bonding wires from collapse: A package structure and method for preventing gold bonding wires from collapsing are disclosed. The structure is especially useful for those chips whose two n×1 arrays of bonding pads are on the chip center to be packaged on a BGA substrate. According to the first preferred embodiment, two dies having... Agent: Birch Stewart Kolasch & Birch

20080185721 - Semiconductor device and method of manufacturing the same: A semiconductor device of the present invention includes a circuit board having a number of electrode portions on the front side and the underside, an electronic circuit element such as a semiconductor chip bonded to the electrode portions on the front side of the circuit board and composing an electronic... Agent: Steptoe & Johnson LLP

20080185722 - Formation process of interconnect structures with air-gaps and sidewall spacers: An integrated circuit structure having air gaps is provided. The integrated circuit includes a conductive line; a sidewall spacer on a sidewall of the conductive line, wherein the sidewall spacer comprises a dielectric material; an air-gap horizontally adjoining the sidewall spacer; and a dielectric layer on the air-gap.... Agent: Slater & Matsil, L.L.P.

20080185723 - Semiconductor device: An antifuse includes a first conductor pattern, a sidewall insulating film formed on a side of the first conductor pattern, and a second conductor pattern formed so that the sidewall insulating film is interposed between the first and second conductor patterns and so as to face the side of the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080185724 - Aluminum-based interconnection in bond pad layer: A semiconductor metal structure with an efficient usage of the chip area is provided. The structure includes a substrate, a copper-based interconnection structure over the substrate, the copper-based interconnection structure comprising a plurality of metallization layers connected by vias and in first dielectric layers, at least one aluminum-based layer over... Agent: Slater & Matsil, L.L.P.

20080185727 - Semiconductor device capable of selecting wiring connection mode by controlling via formation: In a semiconductor device including an upper-layer wiring and a lower-layer wiring that overlaps the upper-layer wiring, an wiring switching option includes a via extending from the upper-layer wiring toward the lower-layer wiring. The wiring switching option switches a wiring connection state according to whether the via extends from the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080185726 - Semiconductor package substrate: A semiconductor package substrate proposed by the invention includes a base body and a plurality of finger pads disposed on surface of the base body, wherein the finger pads are arranged in such a way that an angle is formed between connecting line of centers of two adjacent finger pads... Agent: Edwards Angell Palmer & Dodge LLP

20080185725 - Semiconductor substrate: A semiconductor substrate having a body and a plurality of finger pads formed thereon is disclosed. Each of the finger pads includes two expanding portions respectively and a connecting portion formed therebetween. The finger pads are alternately arranged on the body in a manner that one of the expanding portions... Agent: Edwards Angell Palmer & Dodge LLP

20080185730 - Memory cell device with coplanar electrode surface and method: A memory device described herein includes a bit line having a top surface and a plurality of vias. The device includes a plurality of first electrodes each having top surfaces coplanar with the top surface of the bit line, the first electrodes extending through corresponding vias in the bit line.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080185728 - Microelectronic circuit structure with layered low dielectric constant regions and method of forming same: A method for manufacturing a microelectronic circuit includes the steps of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material; forming a plurality of alternating layers of layer dielectric material and sacrificial material over the first wiring level; and forming a... Agent: Ryan, Mason & Lewis, LLP

20080185729 - Semiconductor element unit and complex thereof, semiconductor device and module thereof, assembled structure thereof and film substrate connection structure: A semiconductor device is provided with a film substrate that has through-vias that are formed by filling a conductive material in through-holes that pass through the front and rear of a film-shaped substrate body and wiring or terminals that connect to the through-vias, with a semiconductor element being mounted on... Agent: Sughrue Mion, PLLC

20080185733 - Lsi package provided with interface module, and transmission line header employed in the package: An LSI package encompasses a transmission line header embracing a header-base, a transmission line held by the header-base, and an interface IC chip mounted on the header-base, an interposer substrate having a plurality of board-connecting joints, which facilitate connection with the printed wiring board; an LSI chip mounted on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080185734 - Power control structure for managing a plurality of voltage islands: A power control method and power control structures are provided for managing a plurality of voltage islands of a functional chip. The power control structure includes a supply control and partition chip positioned between a substrate carrier and a functional chip including a plurality of voltage islands. The supply control... Agent: Ibm Corporation RochesterIPLaw Dept 917

20080185731 - Stacked structure of semiconductor chips, memory card, and method of manufacturing stacked structure of semiconductor chips: A stacked structure of semiconductor chips includes plural stacked semiconductor chips and plural tabular holding members which hold the respective semiconductor chips. At least two holding members among the holding members are arranged in places at ends of the semiconductor chips where inner side facets of the holding members are... Agent: Ratnerprestia

20080185732 - Stacked structure using semiconductor devices and semiconductor device package including the same: This invention provides a semiconductor device. The semiconductor device includes a bonding pad array comprising: a signal bonding pad, a control pin bonding pad and at least one stacking bonding pad on an active surface. At least one stacking bonding pad is adjacent to the control pin bonding pad. This... Agent: Marger Johnson & Mccollom, P.C.

20080185735 - Dynamic pad size to reduce solder fatigue: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with... Agent: Fortkort & Houston P.C.

20080185736 - Multiple selectable function integrated circuit module: An integrated circuit module has a common function known good integrated circuit die with selectable functions. The selectable functions are selected during packaging of the known good integrated circuit die. The known good integrated circuit die is mounted to a second level substrate. The second level substrate has wiring connections... Agent: Mou-shiung Lin

20080185737 - Integrated circuit system with pre-configured bond wire ball: An integrated circuit system is provided including forming a wire ball on a bond wire; forming a shaped ball from the wire ball; and attaching the shaped ball on an integrated circuit die.... Agent: Law Offices Of Mikio Ishimaru

20080185738 - Semiconductor device and method of manufacturing the same: A semiconductor device and a method for fabricating the same are disclosed. According to some embodiments, a semiconductor device comprises a lower structure formed on a semiconductor structure. The lower structure has chip pads. The semiconductor device further comprises a passivation layer located over the chip pads. The passivation layer... Agent: Marger Johnson & Mccollom, P.C.

20080185739 - Semiconductor substrate having enhanced adhesion and method for manufacturing the same: A semiconductor substrate for having enhanced adhesion to semiconductor device and its manufacturing method are provided. The wire circuit layout on the surface of the semiconductor substrate is of a specialized design and surface treatment for enhanced adhesion between the packaged adhered material and the substrate surface (the bonding pad... Agent: Lin & Associates Intellectual Property, Inc.

20080185740 - Semiconductor and method for producing the same: A semiconductor module and a method for producing the same is disclosed. One embodiment provides that an intermediate element has been or is formed, which has been or is formed for making electrical contact materially between a contact region provided and a connection region provided and in direct material and... Agent: Dicke, Billig & Czaja

20080185741 - Semiconductor device having dummy pattern: A memory device having dummy pattern comprises: an alignment mark, provided at a predetermined position on a semiconductor substrate, for aligning position in manufacturing process based on an optical detection signal obtained by scanning in a first direction or in a second direction orthogonal to the first direction in a... Agent: Mcginn Intellectual Property Law Group, PLLC