Active solid-state devices (e.g., transistors, solid-state diodes) inventions 07/08

20080179583 - Fabrication of phase change memory element with phase-change electrodes using conformal deposition: A phase change memory element with phase change electrodes, and method of making the same. Exemplary embodiments include a phase change bridge, including a bottom contact layer, a first insulating layer disposed on the bottom contact layer, a first phase change region disposed on the bottom contact layer adjacent the... Agent: Cantor Colburn, LLP - IBM Arc Division

20080179582 - Phase change memory element and method of making the same: Thin-film phase-change memories having small phase-change switching volume formed by overlapping thing films. Exemplary embodiments include a phase-change memory element, including a first phase change layer having a resistance, a second phase change layer having a resistance, an insulating layer disposed between the first and second phase change layers; and... Agent: Cantor Colburn, LLP - IBM Arc Division

20080179584 - Memory cell having a side electrode contact: Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode, a memory element and a side electrode. The bottom electrode contacts the memory element at a first contact surface on the bottom of the memory element. The side electrode contacts the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080179585 - Phase change memory device and method for fabricating the same: A phase change memory device is provided. The phase change memory device includes a substrate. A metal plug is disposed on the substrate and a phase change material film is disposed on the metal plug, wherein the metal plug is electrically connected to the phase change material film. A heating... Agent: Quintero Law Office, PC

20080179586 - Electronic device and method of making the same: An electronic device includes a primary nanowire of a first conductivity type, and a secondary nanowire of a second conductivity type extending outwardly from the primary nanowire. A doped region of the second conductivity type extends from the secondary nanowire into at least a portion of the primary nanowire.... Agent: Hewlett Packard Company

20080179587 - Nitride/zinc oxide based light-emitting diodes: A light-emitting nitride/zinc oxide based compound semiconductor device of double heterostructure. The double-heterostructure includes a light-emitting layer formed of an Al1-x-yInxGayN; 0≦x<1, 0<y≦1, and x+y=0.1 to 1 compound semiconductor doped an impurity. Single or multi quantum well light-emitting active layers Al1-x-yInxGayN/GaN; 0≦x<1, 0<y≦1, and x+y=0.1 to 1 are positioned between... Agent: Alston & Bird LLP

20080179588 - Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods: A semiconductor device which may include a semiconductor layer, and a superlattice interface layer therebetween. The superlattice interface layer may include a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080179589 - Systems, devices and methods involving superlattice infrared detector structures: Included are embodiments for providing an infrared detector structure. At least one embodiment of a device includes a substrate and an n-type layer coupled to the substrate, the n-type layer being configured as an n-type contact for a first electrical connection to a read out integrated circuit. Some embodiments include... Agent: U S Army Research Laboratory Attn Amsrl Cs Cc Ip

20080179590 - Logic devices comprising carbon nanotube patterns: Carbon nanotube devices comprising vertically aligned carbon nanotubes fabricated within vertically aligned holes within a substrate material form a pattern in the substrate material. Horizontal conducting interconnects are electrically coupled to the vertically aligned carbon nanotubes.... Agent: Xidex Corporation Suite 105

20080179591 - Phase change memory cell design with adjusted seam location: A memory cell comprises a lower electrode, a phase change feature, a spacer feature, and a dielectric layer. The lower electrode comprises a first surface region as well as a second surface region that is raised in relation to the first surface region. The phase change feature is disposed on... Agent: Ryan, Mason & Lewis, LLP

20080179592 - Display device: The present invention relates to a display device. The display device includes a display panel having gate lines and data lines, a driving chip mounted on the display panel, and a flexible printed circuit film (FPC) attached to the display panel. The display panel includes a plurality of first to... Agent: Macpherson Kwok Chen & Heid LLP

20080179597 - Display device: It is an object to provide a display device including a thin film transistor which can operate at high speed and is driven at a low voltage in a drive circuit region, and a thin film transistor having high voltage-resistance and high reliability in a pixel region. Accordingly, it is... Agent: Nixon Peabody, LLP

20080179598 - Display device and manufacturing method of the same: A display device includes an insulating substrate, a switching TFT formed on the substrate that receives a data voltage and that includes a first semiconductor layer, a driving TFT formed on the substrate that includes a control terminal connected to an output terminal of the switching TFT and a second... Agent: Macpherson Kwok Chen & Heid LLP

20080179594 - Flexible display device and fabricating method thereof: In the method of fabricating the flexible display device, an insulating protective layer is formed at one side of a glass substrate. A display device including a thin film transistor array and a pad part, which is connected to the thin film transistor array, is formed on the insulating protective... Agent: Morgan Lewis & Bockius LLP

20080179593 - Thin film transistor array panel and method of manufacturing the same: The TFT array panel includes an insulation substrate, a plurality of gate lines, a plurality of first dummy wiring lines, a gate insulating layer, and a plurality of data lines. The insulation substrate has a display area for displaying an image and a peripheral area outside the display area. The... Agent: F. Chau & Associates, LLC

20080179595 - Thin film transistor substrate: A thin film transistor (TFT) substrate includes: a plurality of gate wirings; a plurality of data wirings insulatedly crossing the gate wirings to define a plurality of pixels; a plurality of common voltage lines formed along edges of pixels and mutually connected in an extending direction of the gate wirings;... Agent: Morgan Lewis & Bockius LLP

20080179596 - Thin film transistor, organic light emitting device including thin film transistor, and manufacturing method thereof: The present invention relates to a thin film transistor (TFT), an organic light emitting diode (OLED) display having the TFT, and a manufacturing method thereof. The manufacturing method includes: forming a pair of ohmic contacts including amorphous silicon that contains an impurity; forming a semiconductor member including amorphous silicon; crystallizing... Agent: Macpherson Kwok Chen & Heid LLP

20080179599 - Thin film integrated circuit and method for manufacturing the same, cpu, memory, electronic card and electronic device: A salicide process is conducted to a thin film integrated circuit without worrying about damages to a glass substrate, and thus, high-speed operation of a circuit can be achieved. A base metal film, an oxide and a base insulating film are formed over a glass substrate. A TFT having a... Agent: Nixon Peabody, LLP

20080179600 - Thin film transistor, method of producing the same, and display device using the thin film transistor: It is an object to obtain a display device which has a thin film transistor using a semiconductor film, and in which initial failures are reduced, and a high-resolution display due to miniaturization of the thin film transistor is enabled. In a thin film transistor, a gate electrode 6 is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080179601 - Nitride-based semiconductor device and method of fabricating the same: A method of fabricating a nitride-based semiconductor device capable of reducing contact resistance between a nitrogen face of a nitride-based semiconductor substrate or the like and an electrode is provided. This method of fabricating a nitride-based semiconductor device comprises steps of etching the back surface of a first semiconductor layer... Agent: Mots Law, PLLC

20080179602 - Fault tolerant light emitters, systems incorporating fault tolerant light emitters and methods of fabricating fault tolerant light emitters: There is provided a light emitter comprising light emitting devices (for example, light emitting diodes) which are electrically interconnected to provide an array of at least two serially connected subsets of parallel connected light emitting devices, each subset comprising at least three light emitting devices. In some embodiments, the light... Agent: Burr & Brown

20080179603 - Light-emitting device having light-emitting elements: A light-emitting device operating on a high drive voltage and a small drive current. LEDs (1) are two-dimensionally formed on an insulating substrate (10) of e.g., sapphire monolithically and connected in series to form an LED array. Two such LED arrays are connected to electrodes (32) in inverse parallel. Air-bridge... Agent: Osha Liang L.L.P.

20080179604 - Led chip package structure with a plurality of thick guiding pins and a method for manufacturing the same: An LED chip package structure with thick guiding pin includes a plurality of conductive pins separated from each other, an insulative casing, a plurality of LED chips, and a packaging colloid. The insulative casing covers a bottom side of each conductive pin to form an injection concave groove for exposing... Agent: Rosenberg, Klein & Lee

20080179606 - Nitride semiconductor light emitting device: A nitride semiconductor light emitting device includes a substrate formed of silicon, an insulating film formed on the substrate and a single crystal thin film formed on the insulating film. On the single crystal film, a semiconductor laminated body including a light emitting layer of nitride semiconductor is formed.... Agent: Mcdermott Will & Emery LLP

20080179605 - Nitride semiconductor light emitting device and method for fabricating the same: A nitride semiconductor light emitting device includes: a dielectric layered film over a substrate, the dielectric layered film being formed by stacking a plurality of dielectric films having different compositions; a semiconductor thin film formed of a single crystal over the dielectric layered film; and a pn junction diode structure... Agent: Mcdermott Will & Emery LLP

20080179608 - Nitride semiconductor light-emitting device: A nitride semiconductor light-emitting device comprises a substrate, and a first n-type nitride semiconductor layer, an emission layer, a p-type nitride semiconductor layer, a metal layer and a second n-type nitride semiconductor layer stacked on the substrate successively from the side closer to the substrate, with an electrode provided on... Agent: Morrison & Foerster LLP

20080179607 - Non-polar and semi-polar light emitting devices: An (Al, Ga, In)N light emitting device, such as a light emitting diode (LED), in which high light generation efficiency is realized by fabricating the device on non-polar or semi-polar III-Nitride crystal geometries. Because non-polar and semi-polar emitting devices have significantly lower piezoelectric effects than c-plane emitting devices, higher efficiency... Agent: Gates & Cooper LLP Howard Hughes Center

20080179616 - Led package: There is provided an LED package. An LED package according to an aspect of the invention includes a package body including a concave part formed as a mounting section, first and second lead frames mounted to the package body to be exposed at a lower surface of the concave part,... Agent: Mcdermott Will & Emery LLP

20080179609 - Light emitting device including a filter: A semiconductor structure includes a light emitting region disposed between an n-type region and a p-type region. A wavelength converting material configured to absorb a portion of the first light emitted by the light emitting region and emit second light is disposed in a path of the first light. A... Agent: Patent Law Group LLP

20080179615 - Light-emitting diode device: A light-emitting diode (LED) device includes a substrate, at least one LED element and an optical modulation structure. The LED element is disposed on the substrate and generates a light beam. The optical modulation structure is disposed at one side of the LED element for adjusting a shape of an... Agent: Birch Stewart Kolasch & Birch

20080179612 - Light-emitting diode package and manufacturing method thereof: An LED package is provided. The LED package comprises a metal plate, circuit patterns, and an LED. The metal plate comprises grooves. The insulating layer is formed on the metal plate. The circuit patterns are formed on the insulating layer. The LED is electrically connected with the circuit pattern on... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080179614 - Light-emitting diode package and manufacturing method thereof: A light-emitting diode (LED) package includes a thermal-conducting substrate, a LED element, a package body, and an optical modulation device. The LED element is formed on the thermal-conducting substrate. The package body is formed on the LED element and the thermal-conducting substrate, and the optical modulation device is disposed on... Agent: Birch Stewart Kolasch & Birch

20080179610 - Semiconductor light emission device emitting polarized light and method for manufacturing the same: A semiconductor light emission device including: a nitride semiconductor stack having an active layer capable of emitting light, a growth surface of the nitride semiconductor stack being a substantially nonpolar plane or substantially semipolar plane; and a reflection section formed in a surface of the device opposite to a light... Agent: Rabin & Berdo, PC

20080179617 - Semiconductor light-emitting device: A semiconductor light-emitting device includes: a printed-wiring board 3; a light-emitting diode element 2 mounted on the printed-wiring board 3; and a resin body for sealing the light-emitting diode element 2. The resin body is composed of a first resin body 7 arranged around the light-emitting diode element 2, and... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080179613 - Silicon deflector on a silicon submount for light emitting diodes: The present invention deals with a process for the manufacturing of reflecting optical barriers comprising silicon and useful in combination with light emitting devices, wherein the process comprises anisotropic wet etching of the silicon material in such a manner that the rate of etching along the crystallographic (111) plane of... Agent: Philips Intellectual Property & Standards

20080179611 - Wafer level phosphor coating method and devices fabricated utilizing method: Methods for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs typically on a substrate. Pedestals are deposited on the LEDs with each of the pedestals in electrical contact with one of the LEDs. A coating is formed over the LEDs with the coating burying at least... Agent: Koppel, Patrick & Heybl

20080179618 - Ceramic led package: Light-emitting diode (LED) packages with improved heat transfer paths for LED dies encased therein when compared to conventional LED packages are provided. For some embodiments, the LED package includes a ceramic substrate having a top cavity with one or more LED dies disposed within and having a bottom cavity for... Agent: Patterson & Sheridan, L.L.P.

20080179619 - Edge-emitting light-emitting diode: An edge-emitting light-emitting diode comprises a base, a frame, and at least three chips. The base has a recessed cup on the front side. The frame is fixed on the recessed cup of the base. These chips are electrically connected to the frame inside the recessed cup. A depth between... Agent: Troxell Law Office PLLC

20080179620 - Light emitting diode package and manufacturing method thereof: A light emitting diode (LED) package including a carrier, an LED chip, a first transparent encapsulant, a transparent cap, and a second transparent encapsulant is provided. The carrier has a carrying surface and a ring frame disposed on the carrying surface, and the ring frame forms an encapsulant-containing space on... Agent: Jianq Chyun Intellectual Property Office

20080179621 - Light emitting semi-conductor diode (with high light output): A light-emitting semi-conductor diode comprising a light emitting chip at least partially surrounded by a transparent electronics protecting body on which a composite layer foil is disposed, the composite layer foil includes at its side facing away from the electronics protection body a carrier layer, which has a refraction index... Agent: Ronald S. Lombard Patents And Trademarks

20080179622 - Semiconductor component comprising an optically active layer, arrangement comprising a multiplicity of optically active layers and method for producing a semiconductor component: A semiconductor component comprising an optically active layer and characterized by at least one cooling element and at least one coupling element. Also disclosed is an arrangement comprising a multiplicity of optically active layers and a method for producing a semiconductor component.... Agent: Fish & Richardson PC

20080179623 - Semiconductor light emitting element: A semiconductor light emitting element includes: an {0001} n-type semiconductor substrate formed of a III-V semiconductor, which is in a range of 0° to 45° in inclination angle into a <1-100> direction, and which is in a range of 0° to 10° in inclination angle into a <11-20> direction; an... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080179624 - Semiconductor esd device and method of making same: A semiconductor device includes an ESD device region disposed within a semiconductor body of a first semiconductor type, an isolation region surrounding the ESD device region, a first doped region of a second conductivity type disposed at a surface of the semiconductor body within the ESD region, and a second... Agent: Slater & Matsil LLP

20080179625 - Cmos image sensor having transistor with conduction band offset: An image sensor includes a photo sensitive device and at lest one transistor such as a drive transistor for converting charge accumulated by the photo sensitive device into an electrical signal. That at least one transistor includes a channel region comprised of a plurality of differently doped regions that generates... Agent: Law Office Of Monica H Choi

20080179626 - Mos transistor and manufacturing methods thereof: A method for manufacturing a metal-oxide semiconductor (MOS) transistor includes providing a substrate having at least a gate structure and a shallow trench isolation (STI) formed thereon, performing a first etching process to form recesses in the substrate respectively at two sides of the gate structure, performing a selective epitaxial... Agent: North America Intellectual Property Corporation

20080179629 - Semiconductor device: In one aspect of the present invention, a semiconductor device may include an isolation region provided in a semiconductor substrate and defining an active region, a gate electrode provided on the semiconductor substrate via a gate dielectric layer in the active region, a channel region provided below the gate electrode,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080179627 - Strained mos devices using source/drain epitaxy: NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a material which causes a shift in the strain of the NMOS device channel in the tensile direction. While, the... Agent: Innovation Interface, LLC

20080179628 - Transistor with embedded silicon/germanium material on a strained semiconductor on insulator substrate: By combining a respectively adapted lattice mismatch between a first semiconductor material in a channel region and an embedded second semiconductor material in an source/drain region of a transistor, the strain transfer into the channel region is increased. According to one embodiment of the invention, the lattice mismatch may be... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20080179630 - Diode assembly:

20080179631 - Iii-nitride power semiconductor device: An enhancement mode III-nitride power semiconductor device that includes normally-off channels along the sidewalls of a recess and a process for fabricating the same, the device including a first power electrode, a second power electrode, and a gate disposed between the first power electrode and the second power electrode over... Agent: Ostrolenk Faber Gerb & Soffen

20080179632 - Selective links in silicon hetero-junction bipolar transistors using carbon doping and method of forming same: Bipolar transistors and methods of forming the bipolar transistors. The method including forming a P-type collector in a silicon substrate; forming an intrinsic base on the collector, the intrinsic base including a first N-type dopant species, germanium and carbon; forming an N-type extrinsic base over a first region and a... Agent: Schmeiser, Olsen & Watts

20080179633 - Solid image pickup device, image pickup system and method of driving solid image pickup device: The solid image pickup device of the present invention comprises a photoelectric conversion part, a charge-voltage conversion part for converting electric charges from the photoelectric conversion part to voltage signals, a signal amplifier for amplifying the voltage signals generated in the charge-voltage conversion part, charge transfer means for transferring photo-electric... Agent: Fitzpatrick Cella Harper & Scinto

20080179634 - Solid-state imaging device and solid-state imaging apparatus: A solid-state imaging device is provided. The imaging device includes an imaging portion which includes light receiving portions and vertical transfer registers, a horizontal transfer portion, an output part for outputting an electrical signal converted from electric charges transferred from the horizontal transfer portion, a first reference potential applying means,... Agent: Sonnenschein Nath & Rosenthal LLP

20080179635 - Fin interconnects for multigate fet circuit blocks: In an embodiment, an apparatus includes a first field effect transistor including a first source contact region, a first drain contact region and a first plurality of fins overlying a substrate, a first gate overlying the first plurality of fins, the first source contact region coupled to first ends of... Agent: Schwegman, Lundberg & Woessner / Infineon

20080179636 - N-fets with tensilely strained semiconductor channels, and method for fabricating same using buried pseudomorphic layers: The present invention relates to high performance n-channel field effect transistors (n-FETs) that each contains a strained semiconductor channel, and methods for forming such n-FETs by using buried pseudomorphic layers that contain pseudomorphically generated compressive strain.... Agent: Scully Scott Murphy & Presser, PC

20080179637 - Transistors having implanted channels and implanted p-type regions beneath the source region and methods of fabricating the same: A unit cell of a metal-semiconductor field-effect transistor (MESFET) includes a semi-insulating substrate having a surface, an implanted n-type channel region in the substrate, and implanted source and drain regions extending from the surface of the substrate into the implanted channel region. A gate contact is between the source and... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080179638 - Gap fill for underlapped dual stress liners: A gap fill nitride is formed in an underlapping region between a first semiconductor area with a first stress liner and a second semiconductor area with a second stress liner without plugging other tightly spaced structures. This is achieved by filling the tightly spaced structures with middle-of-line dielectric material such... Agent: Scully, Scott, Murphy & Presser, P.C.

20080179639 - Pixel sensor cell having asymmetric transfer gate and method of forming: A pixel sensor cell structure and method of manufacture. Disclosed is a pixel sensor cell comprising an asymmetric transfer gate for providing a pinning layer having an edge spaced a further distance from the gate channel region than an edge of a charge collection well. Potential barrier interference to charge... Agent: Ibm Microelectronics Intellectual Property Law

20080179643 - Cmos image sensor and method of manufacturing the same: Spin-on-glass (SOG) or resist is coated on a passivation film formed on a photodiode region, and then a surface layer of the passivation film together with the SOG or the resist is etched back, to thereby remove irregularities of the surface of the passivation film and to optically planarize the... Agent: Bruce L. Adam, Esq Adams & Wilks

20080179644 - Cmos image sensor with drive transistor having asymmetry junction region: An image sensor includes a photosensitive device and a drive transistor for generating an electrical signal from charge accumulated in the photosensitive device. The drive transistor includes a source region of a first conductivity type and an asymmetry junction region abutting a portion of the source region and being of... Agent: Law Office Of Monica H Choi

20080179642 - Cmos image sensor with pocket photodiode for minimizng image lag: A CMOS image sensor includes a photosensitive device, a floating diffusion region, a transfer transistor, and a pocket photodiode formed in a semiconductor substrate of a first conductivity type. The floating diffusion region is of a second conductivity type. The transfer transistor has a channel region disposed between the photosensitive... Agent: Law Office Of Monica H Choi

20080179641 - Color image sensors having pixels with cyan-type and yellow-type color characteristics therein: Color image sensors include pixels having varying color characteristics. One of the pixels is a cyan-type pixel, which includes primary and secondary photodetectors therein. The primary photodetector extends adjacent a portion of a surface of a semiconductor substrate that is configured to receive visible light incident thereon. The secondary photodetector... Agent: Myers Bigel Sibley & Sajovec

20080179640 - Method and structure to reduce dark current in image sensors: A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel region and a periphery region, forming a light sensing element on the pixel region, and forming at least one transistor in the pixel region and at least one transistor in the periphery region. The step... Agent: Haynes And Boone, LLP

20080179645 - Semiconductor device and method of producing the same: A semiconductor device has a conductive film formed over a substrate, an insulating film formed over the conductive film, and having a hole on the conductive film, and a conductive plug formed in the hole including a barrier metal film and a conductive film. A nitride concentration of the barrier... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080179646 - Semiconductor memory device: A semiconductor memory device, comprising: a semiconductor substrate; a memory cell section comprising a memory transistor provided on the semiconductor substrate, the memory transistor including a first gate electrode provided on the semiconductor substrate with a gate insulating film interposed therebetween, and a source and drain provided at both sides... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080179649 - Mounting structures for integrated circuit modules: A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring... Agent: Harness, Dickey & Pierce, P.L.C

20080179648 - Semiconductor device and method of fabricating the same: A semiconductor device having a semiconductor substrate including a first region and a second region is provided. The semiconductor device further includes a gate electrode on the first region and having a first sidewall and a second sidewall, a first source region in the first region proximate to the first... Agent: Lee & Morse, P.C.

20080179647 - Semiconductor device comprising a barrier insulating layer and related method: A semiconductor device comprising a barrier insulating layer and a related method of fabrication is disclosed. The semiconductor device semiconductor substrate includes a plurality of active regions, wherein active regions are defined by a device isolation layer and are disposed along a first direction; a plurality of bit line electrodes... Agent: Volentine & Whitt PLLC

20080179650 - Semiconductor device, fabrication method of semiconductor device, and semiconductor memory device: This semiconductor device has an MOS transistor equipped with a gate electrode formed on a semiconductor substrate, a source region next to one side of the gate electrode, and a drain region next to another side of the gate electrode, wherein an upper end of the source region and an... Agent: Young & Thompson

20080179651 - Semiconductor device including a tcam having a storage element formed with a dram: In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact... Agent: Mcdermott Will & Emery LLP

20080179652 - Semiconductor memory device and method of manufacturing the same: The semiconductor memory device includes: an interlayer insulating film that is formed on a semiconductor substrate; an insulating film that is formed on the interlayer insulating film and has a cylinder hole; and a capacitor that has an impurity-containing silicon film, a lower metal electrode, a capacitive insulating film and... Agent: Sughrue Mion, PLLC

20080179654 - Nonvolatile semiconductor memory: A memory cell has a floating gate electrode, a first inter-gate insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the first inter-gate insulating film. An FET has a lower gate electrode, a second inter-gate insulating film having an opening and arranged on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080179655 - Nonvolatile semiconductor memory device having multi-layered oxide/(oxy) nitride film as inter-electrode insulating film and manufacturing method thereof: A nonvolatile semiconductor memory device includes a first insulator, first conductor, element isolation insulator, second insulator and second conductor. The first insulator is formed on the main surface of a substrate and the first conductor is formed on the first insulator. The element isolation insulator is filled into at least... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080179653 - Semiconductor device and a method of manufacturing the same: A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080179656 - Semiconductor device, nonvolatile semiconductor memory device and manufacturing method of semiconductor device: In one aspect of the present invention, A semiconductor device, may include a transistor including a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a gate stacked above the semiconductor substrate with the insulating film placed in between, and element isolation trenches formed in the semiconductor substrate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080179657 - Semiconductor device having a selectively-grown semiconductor layer: A semiconductor device includes: a silicon substrate; a first trench formed on a surface portion of the silicon substrate to isolate a plurality of active regions from one another; a first element isolation layer embedded in the first trench; a plurality of selectively-grown silicon layers formed on the respective active... Agent: Sughrue Mion, PLLC

20080179658 - Method of making a semiconductor device having high voltage transistors, non-volatile memory transistors, and logic transistors: A semiconductor device is made on a semiconductor substrate. A first insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a high voltage transistor in a first region of the semiconductor substrate. After the first insulating layer is formed, a second insulating layer is... Agent: Freescale Semiconductor, Inc. Law Department

20080179659 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device relating to one embodiment of this invention includes a substrate, a plurality of memory strings formed on said substrate, said memory string having a first select gate transistor, a plurality of memory cells and a second select gate transistor, said first select gate transistor having... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080179660 - Contact forming method and related semiconductor device: Contact forming methods and a related semiconductor device are disclosed. One method includes forming a first liner over the structure and the substrate, the first liner covering sidewall of the structure; forming a dielectric layer over the first liner and the structure; forming a contact hole in the dielectric layer... Agent: Hoffman Warnick LLC

20080179661 - Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device: By forming an additional stressed dielectric material after patterning dielectric liners of different intrinsic stress, a significant increase of performance in transistors may be obtained while substantially not contributing to patterning non-uniformities during the formation of respective contact openings in highly scaled semiconductor devices. The additional dielectric layer may be... Agent: Williams, Morgan & Amerson

20080179662 - Closed trench mosfet with floating trench rings as termination: A semiconductor power device includes a plurality of closed N-channel MOSFET cells surrounded by trenched gates constituting substantially a square or rectangular cell. The trenched gates are further extended to a gate contact area and having greater width as wider trenched gates for electrically contacting a gate pad wherein the... Agent: Bo-in Lin

20080179663 - Semiconductor device: The relationship between a distance Ls between a base layer and an n type buffer layer formed on the surface of a drift layer and the thickness t of a semiconductor substrate in contact with the drift layer is set to Ls≦t≦2×Ls. A loss upon turn-off of a high breakdown... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080179664 - Semiconductor device with a vertical mosfet including a superlattice and related methods: A semiconductor device may include at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on a substrate. The vertical MOSFET may include at least one superlattice including a plurality of laterally stacked groups of layers transverse to the substrate. The vertical MOSFET(s) may further include a gate laterally... Agent: Christopher F. Regan, Esquire Allen, Dyer, Doppelt, Milbrath & Gilchrist, P. A.

20080179666 - Semiconductor device having a trench gate and method for manufacturing: A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second semiconductor area, a semiconductor body area between the first semiconductor area and the second semiconductor area, and a gate arranged in a trench and separated from the... Agent: Dicke, Billig & Czaja

20080179665 - Semiconductor memory devices and methods of forming the same: A memory cell transistor includes a semiconductor substrate having a first impurity region of first conductivity type (e.g., N-type) therein. A U-shaped semiconductor layer having a second impurity region of first conductivity type therein is provided on the first impurity region. A gate insulating layer is provided, which lines a... Agent: Myers Bigel Sibley & Sajovec

20080179667 - Sub-lithographic gate length transistor using self-assembling polymers: A semiconductor structure including at least one transistor located on a surface of a semiconductor substrate, wherein the at least one transistor has a sub-lithographic channel length, is provided. Also provided is a method to form such a semiconductor structure using self-assembling block copolymer that can be placed at a... Agent: Scully, Scott, Murphy & Presser, P.C.

20080179668 - Split gate with different gate materials and work functions to reduce gate resistance of ultra high density mosfet: This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of... Agent: Bo-in Lin

20080179669 - Integrated circuit having a semiconductor arrangement: An integrated circuit including a semiconductor arrangement, a power semiconductor component and an associated production method is disclosed. One embodiment includes a carrier substrate, a first interconnect layer, formed on the carrier substrate and has at least one cutout, an insulating filling layer, formed on the first interconnect layer and... Agent: Dicke, Billig & Czaja

20080179670 - Component arrangement including a mos transistor having a field electrode: A component arrangement including a MOS transistor having a field electrode is disclosed. One embodiment includes a gate electrode, a drift zone and a field electrode, arranged adjacent to the drift zone and dielectrically insulated from the drift zone by a dielectric layer a charging circuit, having a rectifier element... Agent: Dicke, Billig & Czaja

20080179671 - Semiconductor apparatus: A semiconductor apparatus includes: a first first-conductivity-type semiconductor layer; a second first-conductivity-type semiconductor layer provided on a major surface of the first first-conductivity-type semiconductor layer in a device region and a termination region outside the device region; a third second-conductivity-type semiconductor layer being adjacent to the second first-conductivity-type semiconductor layer,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080179672 - Lateral semiconductor component with a drift zone having at least one field electrode: A semiconductor component is described. In one embodiment, the semiconductor component includes a semiconductor body with a first side and a second side. A drift zone is provided, which is arranged in the semiconductor body below the first side and extends in a first lateral direction of the semiconductor body... Agent: Dicke, Billig & Czaja

20080179673 - Replacing symmetric transistors with asymmetric transistors: A semiconductor structure includes a symmetric metal-oxide-semiconductor (MOS) transistor comprising a first and a second asymmetric MOS transistor. The first asymmetric MOS transistor includes a first gate electrode, and a first source and a first drain adjacent the first gate electrode. The second asymmetric MOS transistor includes a second gate... Agent: Slater & Matsil, L.L.P.

20080179674 - Semiconductor device and method of fabricating the same: TFTs arranged in various circuits have structures that are suited for circuit functions, in order to improve operation characteristics and reliability of the semiconductor device, to lower consumption of electric power, to decrease the number of steps, to lower the cost of production and to improve the yield. The gradient... Agent: Eric Robinson

20080179675 - Semiconductor device and manufacturing method thereof: A semiconductor device having a novel structure by which the operating characteristics and reliability are improved and a manufacturing method thereof. An island-shaped semiconductor layer provided over a substrate, including a channel formation region provided between a pair of impurity regions; a first insulating layer provided so as to be... Agent: Nixon Peabody, LLP

20080179676 - Semiconductor memory device: While reducing the formation area of a SRAM cell, the variation in electrical characteristics of respective transistors is suppressed. In a SRAM cell formed in a SOI board, the electrical coupling between the drain region of a driver transistor (which is also a source/drain region of an access transistor), and... Agent: Miles & Stockbridge PC

20080179677 - Semiconductor storage device and manufacturing method thereof: Semiconductor storage devices in which a plurality of semiconductor element devices having different functions are disposed in the appropriate region of the partial SOI substrate and the interface between each gate insulator and each gate electrode is formed to be the same level, and manufacturing methods thereof are disclosed. According... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080179679 - Electronic device including insulating layers having different strains and a process for forming the electronic device: An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from... Agent: Larson Newman Abel Polansky & White, LLP

20080179680 - Pseudomorphic si/sige/si body device with embedded sige source/drain: The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the... Agent: Greenblum & Bernstein, P.L.C

20080179678 - Two-sided semiconductor-on-insulator structures and methods of manufacturing the same: Both sides of a semiconductor-on-insulator substrate are utilized to form MOSFET structures. After forming first type devices on a first semiconductor layer, a handle wafer is bonded to the top of a first middle-of-line dielectric layer. A lower portion of a carrier substrate is then removed to expose a second... Agent: Scully, Scott, Murphy & Presser, P.C.

20080179681 - Electrostatic discharage protection device having a dual triggered transistor: Disclosed is an electrostatic discharge protection device that has a low trigger voltage and protects an internal circuit from electrostatic discharge. The ESD protection device includes an NMOS transistor in which a first pad and a drain are connected to each other and a second pad and a source are... Agent: Ladas & Parry LLP

20080179682 - Circuit layout for different performance and method: A circuit includes a plurality of first MuGFET devices supported by a substrate and having a first performance level. A plurality of second MuGFET devices is supported by the substrate and have a second performance level. The first and second devices in one embodiment are arranged in separate areas that... Agent: Schwegman, Lundberg & Woessner / Infineon

20080179683 - Semiconductor device and method for producing the same: A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity... Agent: Mcdermott Will & Emery LLP

20080179686 - Cmos transistor and method of making the same: The CMOS transistor of the present invention includes deep halo doped regions in the substrate, which can avoid the occurrence of latch-up. In addition, the fabrication of the deep halo doped regions is integrated into the process of making the lightly doped drains or the source/drain doped regions, and therefore... Agent: North America Intellectual Property Corporation

20080179685 - Embedded memory in a cmos circuit and methods of forming the same: In some aspects, a memory circuit is provided that includes (1) a two-terminal memory element formed on a substrate; and (2) a CMOS transistor formed on the substrate and adapted to program the two-terminal memory element. The two-terminal memory element is formed between a gate layer and a first metal... Agent: Dugan & Dugan, PC

20080179688 - Method and apparatus for semiconductor device with improved source/drain junctions: A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the... Agent: Mark E. Courtney Slater & Matsil, L.L.P.

20080179684 - Method of fabricating a strained silicon channel complementary metal oxide semiconductor transistor and structure thereof: The present invention relates to a method of fabricating strained silicon channel complementary metal oxide semiconductor (CMOS) transistor by using an etching process and a planarization process such as a chemical mechanical polishing (CMP) process, and a structure thereof. The present invention is able to resolve the problem of overlap... Agent: North America Intellectual Property Corporation

20080179687 - Semiconductor device and method for manufacturing the same: A semiconductor device, wherein: the first MIS transistor includes a first fully-silicided gate electrode formed on a first gate insulating film and made of a first metal silicide film; and the second MIS transistor includes a second fully-silicided gate electrode formed on a second gate insulating film and made of... Agent: Mcdermott Will & Emery LLP

20080179689 - Metal salicide formation having nitride liner to reduce silicide stringer and encroachment: Disclosed herein are various embodiments of techniques for preventing silicide stringer or encroachment formation during metal salicide formation in semiconductor devices. The disclosed technique involves depositing a protective layer, such as a nitride or other dielectric layer, over areas of the semiconductor device where metal silicide formation is not desired... Agent: Baker & Mckenzie On Behalf Of Tsmc

20080179690 - Semiconductor device and method for fabricating the same: In a semiconductor device, a first p-type MIS transistor includes: a first gate insulating film formed on a first active region; a first gate electrode formed on the first gate insulating film; a first side-wall insulating film; a first p-type source/drain region; a first contact liner film formed over the... Agent: Mcdermott Will & Emery LLP

20080179691 - Device having pocketless regions and method of making the device: An example of the present application is directed to an integrated circuit having a first plurality of transistors and a second plurality of transistors. Each of the first plurality of transistors comprises a first gate structure oriented in a first direction and each of the second plurality of transistors comprises... Agent: Texas Instruments Incorporated

20080179692 - Mask rom devices and methods for forming the same: A mask read only memory (MROM) device includes first and second gate electrodes formed at on-cell and off-cell regions of a substrate, respectively. A first impurity region is formed at the on-cell region of the substrate so as to be adjacent the first gate electrode. A second impurity region including... Agent: F. Chau & Associates, LLC

20080179693 - Semiconductor device and method of manufacturing a semiconductor device: A semiconductor device includes a first active pattern protruding from a substrate, a second active pattern on the first active pattern, a gate electrode enclosing a sidewall of the second active pattern, a conductive layer pattern on the first active pattern, a first impurity region in the first active pattern,... Agent: Myers Bigel Sibley & Sajovec

20080179694 - Semiconductor device and method for fabricating the same: In FET, a second nitride semiconductor layer is provided on a first nitride semiconductor layer, and a source electrode and a drain electrode are each provided to have at least a portion thereof in contact with the second nitride semiconductor layer. A concave portion is formed in the upper surface... Agent: Mcdermott Will & Emery LLP

20080179695 - Low noise transistor and method of making same: A low noise transistor and a method of making a low noise transistor. A noise-reducing agent is introduced into the gate electrode and then moved into the gate dielectric of a transistor.... Agent: Slater & Matsil LLP

20080179697 - Electronic device including mems devices and holed substrates, in particular of the lga or bga type: An electronic device includes a substrate provided with a passing opening and a MEMS device including an active surface wherein a portion of the MEMS device is integrated sensitive to chemical/physical variations of a fluid. The active surface of the MEMS device faces the substrate and is spaced therefrom, the... Agent: Graybeal, Jackson, Haley LLP

20080179696 - Micromechanical device with microfluidic lubricant channel: A micromechanical device assembly includes a micromechanical device enclosed within a processing region and a lubricant channel formed through an interior wall of the processing region and in fluid communication with the processing region. Lubricant is injected into the lubricant channel via capillary forces and held therein via surface tension... Agent: Patterson & Sheridan, L.L.P.

20080179698 - Piezoresistive sensing structure: A piezoresistive sensing structure includes an assembly formed of a semiconductor material and including a cavity and a plurality of piezoresistive elements implanted into the assembly. The assembly includes a central mass coupled to a peripheral frame with a plurality of beams. Each beam is about 15 microns in width... Agent: Delphi Technologies, Inc.

20080179699 - Novel magnetic tunnel junction (mtj) to reduce spin transfer magnetization switching current: A MTJ that minimizes spin-transfer magnetization switching current (Jc) in a Spin-RAM to <1×106 A/cm2 is disclosed. The MTJ has a Co60Fe20B20/MgO/Co60Fe20B20 configuration where the CoFeB AP1 pinned and free layers are amorphous and the crystalline MgO tunnel barrier is formed by a ROX or NOX process. The capping layer... Agent: Stephen B. Ackerman

20080179701 - Ambient light sensor: An ambient light sensor includes a substrate, a buffer layer formed on the substrate, an absorption layer formed on the buffer layer for absorbing the visible light, and a filter layer formed on the absorption layer for filtering infrared light and high-energy photon insensitive to human eye. The absorption layer... Agent: Wpat, PC Intellectual Property Attorneys

20080179700 - Photodetector and manufacturing method thereof: A lateral photodiode, with improved response speed, includes a semiconductor substrate having active regions, and a p-type region and an n-type region arranged parallel to the surface of the substrate. The active regions are an n-layer and a p-layer respectively, and stacked in the thickness direction of the substrate to... Agent: Sughrue Mion, PLLC

20080179702 - Photoelectric conversion device and method of producing the same: A photoelectric conversion device includes a p-type layer, an i-type layer and an n-type layer each made of a silicon base semiconductor, stacked in this order, wherein the i-type layer contains n-type impurities in a concentration of 1.0×1016 to 2.0×1017 cm−3.... Agent: Nixon & Vanderhye, PC

20080179703 - Schottky barrier diodes for millimeter wave sige bicmos applications: The structure for millimeter-wave frequency applications, includes a Schottky barrier diode (SBD) with a cutoff frequency (FC) above 1.0 THz formed on a SiGe BiCMOS wafer. A method is also contemplated for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff... Agent: Greenblum & Bernstein, P.L.C

20080179704 - Semiconductor device including switching element and two diodes: A semiconductor device includes a transistor, a first diode, and a second diode. A collector of the transistor and a cathode of the first diode are electrically connected. The collector of the transistor and a cathode of the second diode are electrically connected, and an emitter of the transistor and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080179705 - Semiconductor device, method for manufacturing a semiconductor device and mask for manufacturing a semiconductor device: A semiconductor device with a substrate includes a structure. The structure has a first part and a second part. At least one section of the edge of the first part of the structure is at an essential constant distance measured parallel to the substrate to a first section of an... Agent: Slater & Matsil LLP

20080179706 - Electronically programmable fuse having anode and link surrounded by low dielectric constant material: An electronically programmable fuse (e-fuse) is disclosed. In one embodiment, the e-fuse includes a cathode surrounded only by silicon dioxide; an anode; and a polysilicon-silicide programmable link coupling the anode and the cathode, wherein the anode and the polysilicon-silicide programmable link are surrounded by a low dielectric constant (low-k) material... Agent: Hoffman Warnick LLC

20080179709 - Integrated circuit fuse: An integrated circuit and a fuse therefore are disclosed. The integrated circuit fuses includes a plurality of terminals coupled by a fuse element, wherein the fuse element is located in a non-last metal layer and/or wherein each terminal is fully-landed on an upper surface of a wire of the fuse... Agent: Hoffman Warnick LLC

20080179708 - Semiconductor device and method of disconnecting fuse element: A semiconductor device includes plural fuse elements which can be disconnected by irradiating a laser beam, and attenuation members which are located between the plural fuse elements as viewed two-dimensionally and can attenuate the laser beam. Each attenuation member includes plural columnar bodies. With this arrangement, the attenuation members including... Agent: Mcginn Intellectual Property Law Group, PLLC

20080179707 - Semiconductor device having a fuse element: A semiconductor device includes plural fuse elements that can be disconnected by irradiating a laser beam, lower-layer wirings that are located lower than the use elements, and plural through-hole electrodes for connecting between the fuse elements and the lower-layer wirings. The through-hole electrodes are provided at both ends of the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080179710 - Semiconductor wafer with improved crack protection: A method of manufacturing a semiconductor wafer for dicing includes providing a semiconductor wafer including a substrate and a plurality of upper layers on the substrate that form a formation of die areas. The formation is arranged so that adjacent die areas are separated by a path for a dicing... Agent: Freescale Semiconductor, Inc. Law Department

20080179711 - Substrate and semiconductor device using the same: According to the present invention, a plurality of semiconductor devices having semiconductor chips 13 molded on a semiconductor package substrate 1 by a molding resin 15 can be manufactured by forming recesses 10 around each semiconductor package substrate 1 composing a substrate 8 for a BGA package, and in the... Agent: Steptoe & Johnson LLP

20080179712 - Structure and method to form semiconductor-on-pores (sop) for high device performance and low manufacturing cost: A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein... Agent: Scully, Scott, Murphy & Presser, P.C.

20080179713 - Etching technique for creation of thermally-isolated microstructures: There is described a method for creating a thermally-isolated microstructure on a slab of mono-crystalline silicon which uses a hybrid dry-then-wet etch technique that when controlled, can produce microstructures without any silicon adhering underneath, microstructures having small masses of silicon adhering underneath, and microstructures that are still attached to the... Agent: Ogilvy Renault LLP

20080179714 - Integrated multiple gate dielectric composition and thickness semiconductor chip and method of manufacturing the same: A method comprises forming a material over a substrate and patterning the material to remove portions of the material and expose an underlying portion of the substrate. The method further includes performing an oxidation process to form an oxide layer over the exposed portion of the substrate and at an... Agent: Greenblum & Bernstein, P.L.C

20080179715 - Shallow trench isolation using atomic layer deposition during fabrication of a semiconductor device: A method for providing an isolation material, for example trench isolation for a semiconductor device, comprises forming a first dielectric such as silicon dioxide using an atomic layer deposition (ALD) process within a trench, partially etching the first dielectric, then forming a second dielectric such as a silicon dioxide using... Agent: Micron Technology, Inc.

20080179716 - Multilevel interconnects structure with shielding function and fabricating method thereof: A method of fabricating multilevel interconnects comprising providing a substrate having a pixel array area and a logical circuit area, forming a first dielectric layer on the substrate, performing a first metallizing process on the first dielectric layer to form a first patterned metal layer and a second patterned metal... Agent: North America Intellectual Property Corporation

20080179717 - Semiconductor package with electromagnetic shield: A semiconductor package with an electromagnetic shield is disclosed. The semiconductor package includes two substrates (102, 202; 103, 203) and an electromagnetic shield (101, 201). Each substrate has at least one die (108, 208; 112, 212) provided thereon. The electromagnetic shield is disposed between the two substrates for shielding electromagnetic... Agent: Madson & Austin

20080179718 - Semiconductor package with electromagnetic shielding capabilites: A semiconductor package with electromagnetic shielding capabilities is disclosed. The semiconductor package includes a substrate (101), a plurality of semiconductor dies (102), a plurality of shielding metal elements (103), a plurality of grounding metal elements (104) and a plurality of conductive metal elements (110). The semiconductor dies are disposed on... Agent: Madson & Austin

20080179719 - Semiconductor device: A semiconductor device (1) includes a wiring (10) and dummy conductor patterns (20). The wiring (10) is a wiring through which a current with a frequency of 5 GHz or higher flows. Near the wiring (10), the dummy conductor patterns (20) are formed. A planar shape of each of the... Agent: Young & Thompson

20080179722 - Electronic package structure: An electronic package structure including a first carrier, at least one first electronic element, at least one second electronic element, and an encapsulant is provided. The first carrier has a first carrying surface and a second carrying surface opposite to the first carrying surface. The first electronic element is disposed... Agent: Jianq Chyun Intellectual Property Office

20080179720 - Lead frame for chip packages with wire-bonding at single-side pads: A chip package and a lead frame used in the chip package are disclosed. The lead frame includes a plurality of first side leads and a plurality of second side leads where the first side leads have a plurality of first bent leads extending from a first edge and the... Agent: Troxell Law Office PLLC

20080179723 - Semiconductor device including a plural chips with protruding edges laminated on a die pad section that has a through section: A semiconductor device includes a die pad section having a surface and a back surface, a first semiconductor chip having a surface on which a first electrode section is formed, and a back surface fixed to the surface of the die pad section, a second semiconductor chip having a surface... Agent: Volentine & Whitt PLLC

20080179721 - Stacking of transfer carriers with aperture arrays as interconnection joints: A transfer carrier comprising a transfer substrate, two aperture arrays, a contact pattern and a semiconductor device. The transfer substrate located on the opposed sides of the transfer substrate to define a cavity on the transfer substrate, the aperture arrays has a top surface and a bottom surface. The two... Agent: Pai Patent & Trademark Law Firm

20080179724 - Microelectronics package and method: A lightwire segment in the form of an elongated substrate frame composed of a flat flexible thin elongated sheet of plastic dielectric material having a copper film laminated on at least one side; a plurality of cavities longitudinally spaced along the elongated substrate, a LED diode having first and second... Agent: Sinsheimer Juhnke Lebens & Mcivor, LLP

20080179725 - Package structure with circuits directly connected to semiconductor chip: A package structure with circuit directly connected to semiconductor chip, which comprises: a carrier board, a semiconductor chip, and at least a built-up structure. The carrier board is formed with a through cavity therein. The semiconductor chip is mounted in the through cavity of the carrier board, and a lateral... Agent: Lowe Hauptman Ham & Berner, LLP

20080179726 - Multi-chip semiconductor package and method for fabricating the same: A multi-chip semiconductor package and a method for fabricating the same are disclosed. The method includes electrically connecting a first chip mounted onto a substrate with the substrate through a plurality of first bonding wires; applying an adhesive layer on the substrate at a position proximate to the first chip... Agent: Edwards Angell Palmer & Dodge LLP

20080179729 - Encapsulant cavity integrated circuit package system: An encapsulant cavity integrated circuit package system including forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.... Agent: Law Offices Of Mikio Ishimaru

20080179728 - Laminated memory: A laminated memory is formed of first and second memory chips having different positions to dispose ID through electrodes for setting layer identification information of each layer. The memory chips are alternately stacked. By alternately stacking the layers, internal circuits for the layer identification information of each layer are connected... Agent: Mcginn Intellectual Property Law Group, PLLC

20080179727 - Semiconductor packages having immunity against void due to adhesive material and methods of fabricating the same: Provided are semiconductor packages having immunity against a void due to an adhesive material and methods of fabricating the same. The semiconductor packages and the methods of fabricating the same can eliminate voids between package bodies to minimize delamination of the package bodies from the semiconductor package during the life... Agent: Marger Johnson & Mccollom, P.C.

20080179731 - Anti-impact memory module: An anti-impact memory module mainly comprises a multi-layer PWB (Printed Wiring Board), a plurality of memory packages and a plurality of first anti-impact bars. The PWB has two longer sides and two shorter sides. A plurality of gold fingers are disposed along one of the longer sides. The first anti-impact... Agent: Troxell Law Office PLLC

20080179733 - Semiconductor multi-package module including tape substrate land grid array package stacked over ball grid array package: A single metal layer tape substrate includes a patterned metal layer affixed to a patterned dielectric layer. The dielectric layer is patterned to provide openings exposing lands and bond sites on bond fingers on the land side of the metal layer. The metal layer is patterned to provide circuit traces... Agent: Law Offices Of Mikio Ishimaru

20080179730 - Wafer level csp packaging concept: An electronics package includes a wafer die substrate containing electronic circuits and having a top surface and a bottom surface. A top protective layer is substantially thinner than the substrate and covers the top surface. A bottom protective layer is substantially thinner than the substrate and covers the bottom surface.... Agent: Bromberg & Sunstein LLP

20080179732 - Working method of metal material and semiconductor apparatus fabricated by the method: A method comprising constraining a circumference of a blank of a Cu—Mo alloy and one of surfaces to be worked with the use of a die, and using a working punch or a counter punch to apply working pressures to the other of the surfaces to be worked, thereby obtaining... Agent: Crowell & Moring LLP Intellectual Property Group

20080179734 - Stacked package, method of manufacturing the same, and memory card having the stacked package: A stacked package includes a printed circuit board (PCB), a plurality of semiconductor chips, plugs and a controller. The semiconductor chips are sequentially stacked on the PCB. The plugs electrically connect each of the semiconductor chips to the PCB. The controller is disposed in any one of the semiconductor chips.... Agent: Marger Johnson & Mccollom, P.C.

20080179735 - System in package device: A system in package device according to an example of the present invention includes a package substrate, an external terminal which is arranged on one face side or the other face side of the package substrate, a first chip which is arranged on the other face side of the package... Agent: SprinkleIPLaw Group

20080179736 - Chip cooling channels formed in wafer bonding gap: One embodiment in accordance with the invention is a system that can include a first wafer and a second wafer. The first wafer and the second wafer can be bonded together by a wafer bonding process that forms a gap between the first wafer and the second wafer. The gap... Agent: Hewlett Packard Company

20080179737 - Semiconductor device: A semiconductor device according to the present invention includes an island provided on one surface of a resin substrate, an external terminal provided on the other surface of the substrate, a thermal pad provided on the other surface of the substrate in opposed relation to the island, a heat conduction... Agent: Rabin & Berdo, PC

20080179739 - Flip chip package with anti-floating structure: A flip chip package with an anti-floating structure includes a leadframe, a flip chip, and a plurality of solders. The leadframe includes a plurality of leads and a fastening part. At least one locking hole is formed on an upper surface of the fastening part. The flip chip includes an... Agent: Volentine & Whitt PLLC

20080179738 - Wiring board and semiconductor device: A wiring board where an electronic component is mounted on a main surface via a bump and at least a part of the periphery of the electronic component is covered with resin, the wiring board includes a dam provided at least at a part of the periphery of an area... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080179740 - Package substrate, method of fabricating the same and chip package: A package substrate, including a base layer, a surface circuit layer, a plurality of conductive bumps, and a patterned solder mask layer, is provided. The surface circuit layer having a plurality of bonding pads is disposed on a surface of the base layer. The conductive bumps are disposed on the... Agent: J C Patents, Inc.

20080179741 - Increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride: By forming an aluminum nitride layer by a self-limiting process sequence, the interface characteristics of a copper-based metallization layer may be significantly enhanced while nevertheless maintaining the overall permittivity of the layer stack at a lower level.... Agent: Williams, Morgan & Amerson

20080179742 - Method and solution to grow charge-transfer complex salts: The present disclosure relates to methods and solutions for growing metal charge-transfer salts on a metal surface, such as a metal layer at the bottom of a via hole. The method makes use of a solution comprising a salt additive. The temperature during growth is in the range of −100°... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080179743 - Electrode, method for producing same and semiconductor device using same: There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101,... Agent: Foley And Lardner LLP Suite 500

20080179744 - Circuit structure and process thereof: A circuit structure has a first dielectric layer, a first circuit pattern embedded in the first dielectric layer and having a first via pad, a first conductive via passing through the first dielectric layer and connecting to the first via pad, and an independent via pad disposed on a surface... Agent: J C Patents, Inc.

20080179745 - Localized alloying for improved bond reliability: In some embodiments a method of forming a gold-aluminum electrical interconnect is described. The method may include interposing a diffusion retardant layer between the gold and the aluminum (1002), the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material; bringing into contact the diffusion... Agent: Zagorin O'brien Graham LLP (115)

20080179747 - Method of manufacturing semiconductor apparatus, and semiconductor apparatus: A method of manufacturing a semiconductor apparatus which includes the steps of forming a via hole and a wire trench reaching an underlying wire in an interlayer insulation film formed on the underlying wire, forming an diffusion barrier film on said underlying wire exposed through said via hole, on an... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080179746 - Wiring structures of semiconductor devices and methods of forming the same: A wiring structure of a semiconductor device comprises an insulating interlayer, a plug and a conductive pattern. The insulating interlayer has an opening therethrough on a substrate. The plug includes tungsten and fills up the opening. The plug is formed by a deposition process using a reaction of a source... Agent: Myers Bigel Sibley & Sajovec

20080179748 - Interconnects having sealing structures to enable selective metal capping layers: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the... Agent: Intel/blakely

20080179749 - Undoped polysilicon metal silicide wiring: Defect density of a polysilicon metal silicide wiring is reduced by employing a block of undoped polysilicon metal silicide in locations in which dopants are not needed in the underlying polysilicon. Furthermore, detection of presence of defects in the polysilicon metal wiring that adversely impacts device performance at high frequency... Agent: Scully, Scott, Murphy & Presser, P.C.

20080179750 - Interconnections of an integrated electronic circuit: An integrated electronic circuit includes superimposed insulating layers and metal elements distributed within said insulating layers. Each insulating layer comprises a first level within which the metal elements lie substantially in the plane of said first level, and a second level traversed by the metal elements in a direction substantially... Agent: Seed Intellectual Property Law Group PLLC

20080179751 - Manufacturing method of semiconductor devices and semiconductor device manufactured thereby: A manufacturing method for semiconductor devices includes a process of forming a conductive layer 4 on the other principle surface of a semiconductor wafer 10 having circuit elements 2 formed in one principle surface of the semiconductor wafer, a process of forming a protecting layer 5 on at least a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080179752 - Method of making semiconductor device and semiconductor device: A metal insulator semiconductor field effect transistor (MISFET) having a strained channel region is disclosed. Also disclosed is a method of fabricating a semiconductor device having a low-resistance junction interface. This fabrication method includes the step of forming a gate electrode above a silicon substrate with a gate insulator film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080179754 - Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device: A method of placing a dummy pattern in a wiring region includes calculating a density of a wiring pattern in the wiring region and calculating a value of a length of a periphery of the wiring pattern. The dummy pattern is then set such that a total of the pattern... Agent: Mcginn Intellectual Property Law Group, PLLC

20080179753 - Semiconductor device having thermally formed air gap in wiring layer and method of fabricating same: A semiconductor device is provided. A unit wiring level of the semiconductor device includes; first and second wiring layers spaced apart from each other on a support layer, a large space formed adjacent to the first wiring layer and including a first air gap of predetermined width as measured from... Agent: Volentine & Whitt PLLC

20080179756 - Semiconductor structures including conductive vias and methods of making semiconductor structures: Semiconductor structures are disclosed including a substrate comprising a semiconductor material and having opposed first and second surfaces, and at least one conductive via extending from the first surface to the second surface. The conductive vias can extend at angles relative to the first surface, such as acute angles or... Agent: Hewlett Packard Company

20080179755 - Structure and method for creating reliable deep via connections in a silicon carrier: A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization... Agent: David Aker

20080179757 - Stacked semiconductor device and method of manufacturing the same: A stacked semiconductor device includes a first semiconductor element mounted on a circuit substrate and a second semiconductor element stacked on the first semiconductor element via a spacer layer. An electrode pad of the first semiconductor element is electrically connected to a connection portion of the circuit substrate through a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080179758 - Stacked integrated circuit assembly: A stacked integrated circuit assembly includes a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC is disposed between the... Agent: Raytheon Company Patent Docket Administration

20080179759 - Method for manufacturing semiconductor device, semiconductor device, electro-optical device, and electronic apparatus: A method for manufacturing a semiconductor device includes: (a) transferring an electronic component that has an electrode and formed on a first substrate from the first substrate to a second substrate; and (b) forming a wiring line electrically coupling the electrode and a terminal on the second substrate. A cavity... Agent: Oliff & Berridge, PLC

20080179760 - Method for producing a device and device: A method for producing a device and a device is disclosed. In one embodiment, a component is surrounded by a material. A fluoropolymer-containing compound is produced at a surface of the material. A molding is produced from a material and a fluoropolymer-containing compound is produced at a surface of the... Agent: Dicke, Billig & Czaja

20080179761 - Semiconductor package having evaporated symbolization: The package (105) of a semiconductor chip has a surface (105a) of optical reflection and color, and is substantially free of indentations; the material of the package may be selected from a group consisting of polymers, molding compound, ceramics, metals, and semiconductors. The surface includes symbols, which contrast optically with... Agent: Texas Instruments Incorporated

20080179762 - Layered structure with laser-induced aggregation silicon nano-dots in a silicon-rich dielectric layer, and applications of the same: The present invention relates to a layered structure with laser-induced aggregation silicon nano-dots in a silicon-rich dielectric layer, where the laser-induced aggregation silicon nano-dots are formed by a laser-induced aggregation process applied to the silicon-rich dielectric layer, and applications of the same. In one embodiment, the silicon-rich dielectric layer is... Agent: Morris Manning Martin LLP

20080173860 - Phase change memory device and method of fabricating the same: Provided are a phase change memory device and a method of fabricating the same. The phase change memory device including a phase change layer in a storage node thereof includes: a bottom electrode; a bottom electrode contact layer formed of a phase change material disposed on the bottom electrode; a... Agent: Harness, Dickey & Pierce, P.L.C

20080173858 - Phase change memory devices including carbon-containing adhesive pattern, and methods of fabricating the same: Phase change memory devices include a heating electrode on a substrate and a phase change material pattern on the heating electrode. An adhesive pattern is disposed between the heating electrode and the phase change material pattern. The adhesive pattern contains carbon. Methods of fabricating phase change memory devices are also... Agent: Myers Bigel Sibley & Sajovec

20080173859 - Storage node and methods of forming the same, phase change memory device having a storage node and methods of fabricating and operating the same: A storage node, phase change memory device having a storage node, a method of fabricating the phase change memory device and a method of operating the phase change memory device are provided. The phase change memory device includes a switching device and a storage node connecting to the switching device.... Agent: Harness, Dickey & Pierce, P.L.C

20080173862 - Phase change memory device and method for forming the same: A phase change memory device includes a mold layer disposed on a substrate, a heating electrode, a filling insulation pattern and a phase change material pattern. The heating electrode is disposed in an opening exposing the substrate through the mold layer. The heating electrode is formed in a substantially cylindrical... Agent: Mills & Onello LLP

20080173861 - Phase change memory devices, methods of manufacturing and methods of operating the same: A phase change memory device includes a switching device and a storage node connected to the switching device. The storage node includes a bottom stack, a phase change layer disposed on the bottom stack and a top stack disposed on the phase change layer. The phase change layer includes a... Agent: Harness, Dickey & Pierce, P.L.C

20080173863 - Radiation-emitting body and method for producing a radiation-emitting body: A radiation-emitting body comprising a layer sequence having an active region for generating electromagnetic radiation, a coupling-out layer for coupling out the generated radiation, said coupling-out layer being arranged on a first side of the layer sequence, a reflection layer for reflecting the generated radiation, said reflection layer being arranged... Agent: Cohen Pontani Lieberman & Pavane LLP

20080173864 - Carbon nanotube transistor having low fringe capacitance and low channel resistance: A CNT transistor has source extension 36a and drain extension 36b that shunt electrical current and reduce the effective CNT resistance and allow significant reductions in fringe capacitances 28 30. The extensions 36a 36b are electrically conductive, and are electrically connected to the source electrode 22 and drain electrode 24.... Agent: Watchstone P+d, Plc

20080173865 - Printable thin-film transistor for flexible electronics: Fabrication of thin-film transistor devices on polymer substrate films that is low-temperature and fully compatible with polymer substrate materials. The process produces micron-sized gate length structures that can be fabricated using inkjet and other standard printing techniques. The process is based on microcrack technology developed for surface conduction emitter configurations... Agent: Fish & Richardson P.c.

20080173866 - Transistor, transistor circuit, electrooptical device and electronic apparatus: A transistor including a first gate electrode, a second gate electrode, a first gate insulating layer disposed between the first gate electrode and the second gate electrode, a first interlayer disposed between the first gate insulating layer and the second gate electrode and containing a first organic material, an organic... Agent: Oliff & Berridge, Plc

20080173867 - Semiconductor device, method for manufacturing the same, electro-optical device and electronic apparatus: A semiconductor device includes a substrate, a transparent oxide layer disposed on one surface side of the substrate, a gate disposed apart from the transparent oxide layer, and a gate insulating layer disposed between the transparent oxide layer and the gate. The transparent oxide layer includes a source, a drain,... Agent: Oliff & Berridge, Plc

20080173868 - Method and resulting structure for fabricating test key structures in dram structures: A method for fabricating test structures on a wafer for integrated circuits. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of integrated circuit chip structures on the semiconductor substrate and forming a plurality of MOS devices on a scribe line formed between... Agent: Townsend And Townsend And Crew, LLP

20080173869 - Method and structure for reducing prior level edge interference with critical dimension measurement: A method for reducing edge effect interference with critical dimension (CD) measurement of semiconductor via structures includes forming a test structure in a kerf region of a semiconductor wafer, the test structure including at least a via structure and a trench structure in contact with the via structure. The via... Agent: Cantor Colburn LLP - Ibm Fishkill

20080173871 - Display device and manufacturing method of display device: In a display device which includes MIS transistors having semiconductor layers thereof formed of an amorphous semiconductor and MIS transistors having semiconductor layers thereof including a polycrystalline semiconductor, the present invention can enhance crystallinity of the semiconductor layers formed of the polycrystalline semiconductor when the respective MIS transistors adopt the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080173872 - Liquid crystal display device and fabricating method thereof: A liquid crystal display device and a fabricating method thereof for simplifying a process and improving an aperture ratio are disclosed, including forming a first mask pattern group including a gate line, a gate electrode and a common line; forming a second mask pattern group including a semiconductor pattern and... Agent: Mckenna Long & Aldridge LLP

20080173870 - Thin film transistor substrate and method of producing the same: A thin film transistor substrate having low resistivity and reduced contact resistance includes a gate wiring line formed on an insulating substrate, a data wiring line crossing the gate wiring line while being insulated from the gate wiring line, and a pixel electrode connected to a portion of the data... Agent: Macpherson Kwok Chen & Heid LLP

20080173873 - Display device and manufacturing method of the same: The present invention provides a method for manufacturing a display device which can reliably form electrodes in a thin film transistor. A method for manufacturing a display device includes the steps of: preparing a substrate having a sequentially stacked body formed of a gate signal line, an insulation film, a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080173874 - Heterojunction bipolar transistor having (in) (al) gaassb/ingaas base-collector structure: A hetero junction bipolar transistor (HBT) has a (In)(Al)GaAsSb/InGaAs base-collector structure. A discontinuous base-collector conduction band forms a built-in electric field to infuse electrons into a collector structure effectively, while a discontinuous base-collector valence band prevents holes from spreading into the collector structure at the same time. Thus, a current... Agent: Troxell Law Office Pllc

20080173876 - Insulated gate silicon carbide semiconductor device: An insulated gate silicon carbide semiconductor device is provided having small on-resistance. The device combines a static induction transistor structure with an insulated gate field effect transistor structure. The advantages of both the SIT structure and the insulated gate field effect transistor structure are obtained. The structures are formed on... Agent: Rossi, Kimms & Mcdowell LLP.

20080173875 - Self-aligned methods based on low-temperature selective epitaxial growth for fabricating silicon carbide devices: Self-aligned fabrication of silicon carbide semiconductor devices is a desirable technique enabling reduction in the number of photolithographic steps, simplified alignment of different device regions, and reduced spacing between the device regions. This invention provides a method of fabricating silicon carbide (SiC) devices utilizing low temperature selective epitaxial growth which... Agent: Larry A. Schemmel

20080173877 - Semiconductor apparatus: Disclosed is a semiconductor apparatus having a channel region of a substrate irradiated with light via a transparent gate electrode and a transparent gate insulating film to decrease channel resistance.... Agent: Sughrue Mion, Pllc

20080173878 - Diode housing: A housing accommodating a semiconductor chip is set out. The housing and chip may be used for sending and/or receiving radiation. Popular applications of the housing may be in light emitting diodes. The housing includes a conductor strip that is punched into two electrically isolated portions. The housing further includes... Agent: Fish & Richardson Pc

20080173879 - Galvanic optocoupler and method of making: A galvanic optocoupler of the type monolithically integrated on a silicon substrate and having at least one luminous source and a photodetector interfaced by means of a galvanic insulation layer. The photodetector can be a phototransistor realized in the silicon substrate, and the galvanic insulation layer (40) is a passivation... Agent: Seed Intellectual Property Law Group Pllc

20080173880 - Light-emitting semiconductor device using group iii nitrogen compound: A light-emitting semiconductor device (10) consecutively includes a sapphire substrate (1), an AlN buffer layer (2), a silicon (Si) doped GaN n+-layer (3) of high carrier (n-type) concentration, a Si-doped (Alx3Ga1-x3)y3In1-y3N n+-layer (4) of high carrier (n-type) concentration, a zinc (Zn) and Si-doped (Alx2Ga1-x2)y2In1-y2N emission layer (5), and a Mg-doped... Agent: Mcginn Intellectual Property Law Group, Pllc

20080173881 - Led chip package structure using a ceramic material as a substrate and a method for manufacturing the same: An LED chip package structure using a ceramic material as a substrate includes a ceramic substrate, a conductive unit, a hollow ceramic casing, a plurality of LED chips, and a package colloid. The ceramic substrate has a main body, and a plurality of protrusions extended from three faces of the... Agent: Rosenberg, Klein & Lee

20080173882 - Low voltage diode with reduced parasitic resistance and method for fabricating: A method of making a diode begins by depositing an AlxGa1−xN nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer, an n− GaN layer, an AlxGa1−xN barrier layer, and an SiO2 dielectric layer. A portion of the dielectric layer is removed and a Schottky metal deposited... Agent: Koppel, Patrick & Heybl

20080173883 - High performance led package: A light emitting diode lamp is disclosed that includes a resin package that defines a recess in the shape of a solid polygon or another three-dimensional solid. The recess includes a floor, two side walls along the respective longer sides of the floor, and two end walls along the respective... Agent: Summa, Allan & Additon, P.a.

20080173889 - Light emitting diode chip package: A light emitting diode (LED) chip package including: a package body; an LED chip mounted on the package body and emitting an excited light; a phosphor layer including a phosphor absorbing the excited light and emitting a wavelength conversion light obtained by converting a wavelength of the excited light and... Agent: Mcdermott Will & Emery LLP

20080173888 - Light-emitting diode chip package body and packaging method thereof: AN LED chip package body provides an LED chip with a pad-installed surface, a plurality of pads disposed on the pad-installed surface and a rear surface formed opposite the pad-installed surface. The LED chip package body further has a light-reflecting coating disposed on the pad-installed surface of the LED chip... Agent: Rosenberg, Klein & Lee

20080173887 - Self-luminous device: A self-luminous device 1 is one embodiment which has an increased light extraction efficiency by optimizing the distribution of refractive index in semiconductor layers. The self-luminous device 1 includes a first layer (semiconductor layer 2), a light emitting layer 3 overlaying the first layer (semiconductor layer 2), and a second... Agent: Frishauf, Holtz, Goodman & Chick, Pc

20080173885 - Semiconductor light-emitting device and method of manufacturing the same: A semiconductor light-emitting device includes: a semiconductor layer including a light-emitting region and having an emission surface on its surface; an insulating layer arranged on a surface of the semiconductor layer opposite to; a first metal layer deposited on a surface of the insulating layer opposite to a surface where... Agent: Sonnenschein Nath & Rosenthal LLP

20080173886 - Solid state lighting devices comprising quantum dots: Solid state lighting devices containing quantum dots dispersed in polymeric or silicone acrylates and deposited over a light source. Solid state lighting devices with different populations of quantum dots either dispersed in matrix materials or not are also provided. Also provided are solid state lighting devices with non-absorbing light scattering... Agent: Kenyon & Kenyon LLP

20080173884 - Wafer level phosphor coating method and devices fabricated utilizing method: Methods for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs typically on a substrate. Pedestals are deposited on the LEDs with each of the pedestals in electrical contact with one of the LEDs. A coating is formed over the LEDs with the coating burying at least... Agent: Koppel, Patrick & Heybl

20080173891 - Led with light diverging arrangement: A LED includes a first substrate having a recess, a second substrate having a polarity opposing that of the first substrate, a LED chip die-bonded on the recess, a bonding wire interconnecting the LED chip and the second substrate, and a case formed around the first substrate, the second substrate,... Agent: Bruce H. Troxell

20080173890 - Multidirectional light-emitting diode: A multidirectional light-emitting diode comprises a frame, at least one light-emitting chip, at least two connection wires, and a transparent material for covering above-mentioned components, wherein the light-emitting chip is connected with the frame via the connection wires, and the light-emitting chip, the connection wires, and partial portion of the... Agent: Troxell Law Office Pllc

20080173892 - Package structure: A package structure including a carrier, a molding element and a chip is provided. A part of the carrier is enclosed by the molding element. The molding element has a top portion and a bottom portion opposite to the top portion, wherein the top portion has a cavity exposing a... Agent: Jianq Chyun Intellectual Property Office

20080173893 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device according to the present invention has a step of forming a plurality of MOSFETs each having a channel of a first conductivity type in a stripe on the first major surface of a wafer; a step of implanting an impurity of a first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080173894 - Semiconductor device: A semiconductor substrate has a second conductivity type cathode layer formed thereon. The cathode layer has a first conductivity type base layer formed thereon. A first anode region of the second conductivity type is formed in the surface of the base layer. A second anode region of the first conductivity... Agent: Amin, Turocy & Calvin, LLP

20080173895 - Gallium nitride on silicon with a thermal expansion transition buffer layer: A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate with a first thermal expansion coefficient (TEC), and forms a silicon-germanium (SiGe) film overlying the Si substrate. A buffer layer is deposited overlying the... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080173896 - Dynamic random access memory cell and manufacturing method thereof: A dynamic random access memory cell including a bottom oxide layer, a first semiconductor layer, a second semiconductor layer, an insulation layer, a gate and a doping layer is provided. The bottom oxide layer is disposed on a substrate. The first semiconductor layer disposed on the bottom oxide layer has... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080173897 - Iii nitride power device with reduced qgd: A III-nitride power switch that includes a III-nitride heterojunction, field dielectric bodies disposed over the heterojunction, and either gate conductive bodies that do not overlap the top surface of the field dielectric bodies or power contacts that do not overlap field dielectric bodies or both.... Agent: Ostrolenk Faber Gerb & Soffen

20080173898 - Field effect transistor and device thereof: A field effect transistor comprises a carrier transit layer in a stacked layer structure provided with a plurality of nitride semiconductor layers, a gate electrode provided on the stacked layer structure and a source electrode and a drain electrode placing the gate electrode in between. The stacked layer structure has... Agent: Birch Stewart Kolasch & Birch

20080173899 - Semiconductor device: There is provided a technology which allows sufficient protection of internal circuits from electrostatic discharge even when internal-circuit power source pads and internal-circuit GND pads are formed on an internal circuit region. Internal-circuit power source pads and internal-circuit GND pads are placed in the core region of a semiconductor chip.... Agent: Miles & Stockbridge Pc

20080173900 - Thin film transistor array panel: A thin film transistor array panel is provided, which includes a substrate including a display region, a chip region, and a pad region; a plurality of signal lines formed on the substrate for electrically connecting the pad region to the chip region and the display region, wherein the signal lines... Agent: Macpherson Kwok Chen & Heid LLP

20080173901 - Cmos devices having channel regions with a v-shaped trench and hybrid channel orientations, and method for forming the same: The present invention relates to a field effect transistor (FET) containing a channel extending perpendicularly across at least one V-shaped trench and along the interior surfaces thereof. In one aspect, a semiconductor device is provided that includes a semiconductor substrate having first and second device regions that are isolated from... Agent: Scully, Scott, Murphy & Presser, P.c.

20080173902 - Solid state imaging apparatus, imaging apparatus and solid state imaging apparatus manufacturing method: A solid state imaging apparatus comprises: a semiconductor substrate; a photoelectric converting portion on the semiconductor substrate; a light shielding film in a region excluding a light receiving surface of the photoelectric converting portion; and a P-type impurity layer between a lower surface of the light shielding film and the... Agent: Birch Stewart Kolasch & Birch

20080173903 - Solid-state image pickup element: A solid-state image pickup element equipped with a film stack, a color filter, and a microlens on a semiconductor substrate equipped with a light receiving section, comprises a first film with a high refractive index and a second film with a low refractive index adjacently arranged on the semiconductor substrate... Agent: Birch Stewart Kolasch & Birch

20080173904 - Cmos image sensors with a bonding pad and methods of forming the same: A CMOS image sensor with a bonding pad comprises a semiconductor substrate having a pixel region and a circuit region; a passivation layer having an opening over the semiconductor substrate; and a bonding pad in circuit region, the bonding pad without extending to an upper surface of the passivation layer.... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080173905 - Solid state imaging device and method of manufacturing the same: A solid state imaging device comprises: a photoelectric converting portion provided on a semiconductor substrate; a charge transfer path, formed in an adjacent position to the photoelectric converting portion, that receives a signal charge generated in the photoelectric converting portion and transfers the signal charge in a predetermined direction; and... Agent: Birch Stewart Kolasch & Birch

20080173906 - Enhanced mobility cmos transistors with a v-shaped channel with self-alignment to shallow trench isolation: The present invention provides structures and methods for a transistor formed on a V-shaped groove. The V-shaped groove contains two crystallographic facets joined by a ridge. The facets have different crystallographic orientations than what a semiconductor substrate normally provides such as the substrate orientation or orientations orthogonal to the substrate... Agent: Scully, Scott, Murphy & Presser, P.c.

20080173907 - Field effect transistor having a crank-shaped multigate structure: A field effect transistor of the present invention includes a pair of ohmic electrodes 2 and an n-type GaAs layer 1 formed between the pair of ohmic electrodes 2 and having recesses. Crank-shaped gate fingers 4 and 5 are formed within the recesses of the n-type GaAs layer 1 between... Agent: Leydig Voit & Mayer, Ltd

20080173908 - Multilayer silicon nitride deposition for a semiconductor device: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (131) of a first stressor material over the semiconductor structure, said first stressor... Agent: Fortkort & Houston P.c.

20080173910 - Image sensor and method for manufacturing the same: An image sensor that can include a photodiode formed on one side of a substrate to receive light and then generate signal charges based on the light; and a transistor converting the signal charges into predetermined voltage and transmitting the voltage to an output terminal, whereby the transistor directly contact... Agent: Sherr & Nourse, Pllc

20080173909 - Image sensor with gain control: An image sensor having a plurality of pixels; each pixel includes one or more photosensitive elements that collect charge in response to incident light; one or more transfer mechanisms that respectively transfer the charge from the one or more photosensitive elements; a charge-to-voltage conversion region having a capacitance, and the... Agent: Frank Pincelli Patent Legal Staff

20080173911 - Solid-state imaging device having wiring layer which includes lamination of silicide layer in order to reduce wiring resistance, and manufacturing method for the same: A silicide layer (first silicide layer, second silicide layer) is laminated on top laminate surfaces of gates of a transmission transistor and a reset transistor, respectively. Each of the first silicide layer and the second silicide layer respectively formed on each of the gates extends in a direction along the... Agent: Mcdermott Will & Emery LLP

20080173912 - Semiconductor device: A semiconductor device comprising a ferroelectric capacitor having improved reliability is disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a transistor formed on a semiconductor substrate, a ferroelectric capacitor formed above the transistor and comprising a lower electrode, a ferroelectric film and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080173913 - Semiconductor device: In one aspect of the present invention, a semiconductor device may include a support member, a FinFET provided on the support member, which has a first fin, a source region provided in the first fin, a drain region provided in the first fin, and a gate electrode provided on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080173914 - Semiconductor device and storage medium: A power source noise of a semiconductor device having a core cell configuring a logic circuit is reduced. Above the core cell configuring the logic circuit provided on a main surface of a semiconductor substrate are provided a first branch line for a first power source of the core cell,... Agent: Miles & Stockbridge Pc

20080173915 - Single-gate non-volatile memory and operation method thereof: A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and... Agent: Rosenberg, Klein & Lee

20080173916 - Semiconductor memory device and write method of the same: A write and erase method of a semiconductor memory device includes a floating gate type transistor having a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, and a control gate electrode opposing the floating gate electrode with... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080173918 - Post sti trench capacitor: A design structure for capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small... Agent: Whitham, Curtis & Christofferson, P.c.

20080173917 - Selective deposition method: The invention relates to a deposition method performing the following steps. A substrate is provided which is structured to comprise a first surface and a second surface, which differ in at least one of geometric orientation and vertical distance to a principle surface of the substrate. An etchable layer is... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20080173919 - Deposition method for a transition-metal-containing dielectric: The present invention relates to a method for depositing a dielectric material comprising a transition metal compound. After providing a substrate, a first pre-cursor comprising a transition metal compound and a second pre-cursor predominantly comprising at least one of water vapour, ammonia and hydrazine are successively applied on the substrate... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20080173920 - Memory having a vertical access device: Semiconductor memory devices having vertical access devices are disclosed. In some embodiments, a method of forming the device includes providing a recess in a semiconductor substrate that includes a pair of opposed side walls and a floor extending between the opposed side walls. A dielectric layer may be deposited on... Agent: Schwegman, Lundberg & Woessner, P.a.

20080173921 - Electronic device including trenches and discontinuous storage elements and processes of forming and using the same: An electronic device can include a substrate including a trench having a bottom and a first wall. The electronic device can also include a first gate electrode within the trench and adjacent to the first wall and overlying the bottom of the trench, a second gate electrode overlying the substrate... Agent: Larson Newman Abel Polansky & White, LLP

20080173922 - Electronic device including fins and discontinuous storage elements and processes of forming and using the same: An electronic device can include a substrate including a fin lying between a first trench and a second trench, wherein the fin is no more than approximately 90 nm wide. The electronic device can also include a first gate electrode within the first trench and adjacent to the fin, and... Agent: Larson Newman Abel Polansky & White, LLP

20080173923 - Electronic device including trenches and discontinuous storage elements and processes of forming and using the same: An electronic device can include a substrate including a first trench having a first bottom and a first wall. The electrode device can also include a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench, and a... Agent: Larson Newman Abel Polansky & White, LLP

20080173926 - Non-volatile two-transistor semiconductor memory cell and method for producing the same: The invention relates to a nonvolatile semiconductor memory cell and to an associated fabrication method, a source region (7), a drain region (8) and a channel region lying in between being formed in a substrate (1). In order to realize locally delimited memory locations (LB, RB), an electrically non-conductive charge... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080173924 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device that reduces the interval between gate electrodes. The semiconductor device includes a semiconductor substrate, a plurality of gate electrodes buried in the semiconductor substrate, a plurality of first insulation layers arranged respectively on the plurality of gate electrodes, a conductive layer formed on the surface of the... Agent: Ditthavong Mori & Steiner, P.c.

20080173925 - Structured, electrically-formed floating gate for flash memories: Semiconductor memory devices and methods to fabricate thereof are described. A first gate base is formed on a first insulating layer on a substrate. A first gate fin is formed on the first gate base. The first gate fin has a top and sidewalls. Next, a second insulating layer is... Agent: Intel/blakely

20080173928 - Nonvolatile semiconductor memory and process of producing the same: A nonvolatile semiconductor memory of an aspect of the present invention comprises a semiconductor substrate, a pillar-shaped semiconductor layer extending in the vertical direction with respect to the surface of the semiconductor substrate, a plurality of memory cells arranged in the vertical direction on the side surface of the semiconductor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080173927 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region; a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080173929 - Semiconductor memory device and method for manufacturing the same: According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: first device regions divided by first isolation films and second device regions divided by second isolation films a gate insulating film formed on the semiconductor substrate; a first element including:... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080173930 - Semiconductor memory device and method for manufacturing the same: The present invention provides a semiconductor memory device having a tunnel insulating film that does not degrade the endurance characteristics when writing/erasing is repeated, even if the tunnel insulating film is made thinner. The semiconductor memory device includes: a semiconductor substrate; a first insulating film formed on the semiconductor substrate,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080173931 - Multilevel-cell memory structures employing multi-memory layers with tungsten oxides and manufacturing method: The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080173932 - Nonvolatile semiconductor memory and method for manufacturing the same: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory including: a columnar semiconductor; a charge storage insulating film including: a first insulating film formed around the columnar semiconductor, a charge storage film formed around the first insulating film, and a second insulating film formed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080173933 - Semiconductor memory device: The semiconductor device includes a substrate having a conductive layer formed on its surface. The conductive layer has a columnar semiconductor formed thereon. The columnar semiconductor has an insulating layer formed therearound. The insulating layer has an electrode film formed therearound. The electrode film functions as an gate electrode of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080173934 - Integrated circuit system employing stress-engineered spacers: An integrated circuit system that includes: providing a substrate including a first region with a first device and a second device and a second region with a resistance device; configuring the first device, the second device, and the resistance device to include a first spacer and a second spacer; forming... Agent: Law Offices Of Mikio Ishimaru

20080173935 - Semiconducotor device and method for manufacturing the same: A semiconductor device includes a semiconductor substrate, a cell region, an outer peripheral region, a field plate, an outermost peripheral ring, outer peripheral region layer, an insulator film, and a Zener diode. The semiconductor substrate has a superjunction structure. The outer peripheral region is disposed at an outer periphery of... Agent: Posz Law Group, Plc

20080173936 - Access device having vertical channel and related semiconductor device and a method of fabricating the access device: An access device and a semiconductor device are disclosed. The access device includes a vertically oriented channel separating a lower source/drain region and an upper source/drain region, a gate dielectric disposed on the channel, and a unified gate electrode/connection line coupled to the channel across the gate dielectric, wherein the... Agent: Volentine & Whitt Pllc

20080173937 - Semiconductor memory devices including vertically oriented transistors and methods of manufacturing such devices: A semiconductor device includes a first active pattern including an upper portion and a lower portion formed on a substrate, a second active pattern formed on the first active pattern, and a gate surrounding the second active pattern. The upper portion of the first active pattern has a cross-sectional area... Agent: Myers Bigel Sibley & Sajovec

20080173938 - Manufacturing method of semiconductor device: A power MISFET, which has a desired gate breakdown voltage, can be manufactured will controlling an increase in parasitic capacitance. After depositing a polycrystalline silicon film on a substrate and embedding groove portions in the polycrystalline silicon film by patterning the polycrystalline silicon film in an active cell area, a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080173939 - Semiconductor device and method for fabricating the same: A semiconductor device includes a semiconductor substrate having an active region defined by a device isolation structure. A recessed channel is formed on the semiconductor substrate under the active region. A recessed junction region is formed between the recessed channel and the device isolation structure adjacent to the recessed channel.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080173940 - Reduced electric field dmos using self-aligned trench isolation: A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first... Agent: Schwegman, Lundberg & Woessner / Atmel

20080173941 - Etching method and structure in a silicon recess for subsequent epitaxial growth for strained silicon mos transistors: A semiconductor integrated circuit device comprising a semiconductor substrate, e.g., silicon wafer, silicon on insulator. The device has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. The device also has a channel region within a portion of the semiconductor substrate within a vicinity... Agent: Townsend And Townsend And Crew, LLP

20080173943 - Method of forming high voltage semiconductor device and the high voltage semiconductor device using the same: A method of forming a high voltage semiconductor device includes forming a thermal oxide layer on a semiconductor substrate where a trench is formed, forming a chemical vapor deposition (CVD) oxide layer on the thermal oxide layer, and etching the CVD oxide layer and the thermal oxide layer at different... Agent: Mills & Onello LLP

20080173942 - Structure and method of manufacturing a strained finfet with stressed silicide: A stressed semiconductor structure including at least one FinFET device on a surface of a substrate, typically a buried insulating layer of an initial semiconductor-on-insulator substrate, is provided. In a preferred embodiment, the at least one FinFET device includes a semiconductor Fin that is located on an unetched portion of... Agent: Scully, Scott, Murphy & Presser, P.c.

20080173944 - Mosfet on soi device: s

20080173945 - Esd protection scheme for semiconductor devices having dummy pads: A semiconductor device formed in a semiconductor substrate for dissipating electrostatic discharge and/or accumulated charge in an integrated circuit is provided. In one embodiment, the device comprises a semiconductor substrate; a plurality of layers of metal lines formed overlying the substrate; a plurality of via plugs through intermetal dielectric layers... Agent: Birch Stewart Kolasch & Birch

20080173946 - Cmos structure including dual metal containing composite gates: A CMOS structure and a method for fabricating the CMOS structure include a first transistor located within a first semiconductor substrate region having a first polarity. The first transistor includes a first gate electrode that includes a first metal containing material layer and a first silicon containing material layer located... Agent: Scully, Scott, Murphy & Presser, P.c.

20080173947 - Hybrid process for forming metal gates: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a... Agent: Slater & Matsil, L.l.p.

20080173949 - Complementary metal-oxide-semiconductor field effect transistor: A complementary metal-oxide-semiconductor field effect transistor (CMOSFET) is provided. The CMOSFET includes a substrate of a first conductivity type, a first epitaxial layer, a well, a second epitaxial layer of a second conductivity type, a first sinker, a second sinker, a first buried layer and a second buried layer. The... Agent: Jianq Chyun Intellectual Property Office

20080173948 - Semiconductor device and complementary metal-oxide-semiconductor field effect transistor: A semiconductor device includes a substrate, an epitaxial layer, a sinker, an active device, a first buried layer, and a second buried layer. The substrate has a first type conductivity. The epitaxial layer has a second type conductivity, and is located on the substrate. The sinker has the second type... Agent: Jianq Chyun Intellectual Property Office

20080173951 - Semiconductor device and complementary metal-oxide-semiconductor transistor: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a first sinker, a first buried layer, a second epitaxial layer, a second sinker and a second buried layer. The first and second epitaxial layers are disposed sequentially on the substrate. The first sinker and... Agent: Jianq Chyun Intellectual Property Office

20080173950 - Structure and method of fabricating electrical structure having improved charge mobility: A method of fabricating an electrical structure with increased charge carrier mobility is provided. The method includes forming an N-type field effect transistor (nFET) device and a P-type field effect transistors (pFET) device on a semiconductor substrate; forming a compressive stress film over said nFET device for exerting tensile stress... Agent: International Business Machines Corporation Dept. 18g

20080173952 - Semiconductor device and manufacturing method thereof: A semiconductor device and method of manufacturing the same are disclosed. An example semiconductor device includes a semiconductor substrate having a first well, a first source electrode, a drain electrode, and a first gate insulation layer formed on the semiconductor substrate, and a gate electrode formed on the first gate... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080173953 - Fully siliciding regions to improve performance: Structures and related methods including fully silicided regions are disclosed. In one embodiment, a structure includes a substrate; a partially silicided region located in an active region of an integrated circuit formed on the substrate; a fully silicided region located in a non-active region of the integrated circuit, and wherein... Agent: Hoffman Warnick Llc

20080173954 - Semiconductor device and method for fabricating the same: A semiconductor device includes a plurality of first MIS transistors and a plurality of second MIS transistors formed on a semiconductor substrate and a liner insulating film applying stress along the gate length direction. Each of the first MIS transistors includes first L-shaped sidewalls each having an L-shaped cross-sectional shape,... Agent: Mcdermott Will & Emery LLP

20080173955 - Static semiconductor memory device: A first transfer transistor includes a first diffusion layer connected to a first bit line, and a second diffusion layer connected to a first storage node, the first diffusion layer is provided in a substrate, the second diffusion layer is provided in a bottom part of a recess provided in... Agent: Amin, Turocy & Calvin, LLP

20080173956 - Mosfet using gate work function engineering for switching applications: This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by manufacturing a MOSFET with a higher gate work function by implementing a P-doped gate in an N-MOSFET device. The P-type gate increases the threshold voltage and shifts the C-Vds characteristics. The reduced Cgd... Agent: Bo-in Lin

20080173957 - Method of forming a semiconductor device having a symmetric dielectric regions and structure thereof: A method for forming a semiconductor device including forming a semiconductor substrate; forming a gate electrode over the semiconductor substrate having a first side and a second side, and forming a gate dielectric under the gate electrode. The gate dielectric has a first area under the gate electrode and adjacent... Agent: Freescale Semiconductor, Inc. Law Department

20080173958 - Semiconductor device with pre-anneal sandwich gate structure, and method of manufacturing: Various illustrative embodiments of methods for manufacturing a semiconductor device are described. These methods may include, for example, forming a first polysilicon layer above a substrate, wherein the first polysilicon layer comprises a doped portion, and forming a second polysilicon layer over a surface of the first polysilicon layer. Also,... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20080173959 - Z-axis microelectromechanical device with improved stopper structure: In a microelectromechanical device, a mobile mass is suspended above a substrate via elastic suspension elements and is rotatable about said elastic suspension elements, a cover structure is set above the mobile mass and has an internal surface facing the mobile mass, and a stopper structure is arranged at the... Agent: Seed Intellectual Property Law Group Pllc

20080173960 - Microelectromechanical systems contact stress sensor: A microelectromechanical systems stress sensor comprising a microelectromechanical systems silicon body. A recess is formed in the silicon body. A silicon element extends into the recess. The silicon element has limited freedom of movement within the recess. An electrical circuit in the silicon element includes a piezoresistor material that allows... Agent: Eddie E. Scott

20080173961 - Semiconductor device, magnetic sensor, and magnetic sensor unit: A semiconductor device, comprising a semiconductor chip; a pad electrode; an electrode portion; a wiring portion. An insulating portion is formed from electrically insulating material, covering the surface of the semiconductor chip and sealing the sensor element, wiring portion and electrode portion, in a state which exposes at least the... Agent: Dickstein Shapiro LLP

20080173962 - Indium tin oxide target, method of manufacturing the same and transparent electrode manufactured by using the same: An indium tin oxide (ITO) target including calcium of about 0.001% to about 10% by atom, compared with an indium atom, and an ITO transparent electrode for a display apparatus manufactured from an ITO target are provided. A method of manufacturing the ITO target, the method including: preparing a slurry... Agent: Mcdermott Will & Emery LLP

20080173963 - Guard ring structure for improving crosstalk of backside illuminated image sensor: The present disclosure provides a backside illuminated semiconductor device. The device includes a substrate having a front surface and a back surface; a plurality of sensor elements formed in the substrate, each of the plurality of sensor elements is designed and configured to receive light directed towards the back surface;... Agent: Haynes And Boone, LLP

20080173964 - Elevated pocket pixels, imaging devices and systems including the same and method of forming the same: An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including, but not limited to, v-shaped, u-shaped, or other shaped features. Light sensors having such an indentation feature can redirect incident light that is not absorbed by one portion... Agent: Dickstein Shapiro LLP

20080173965 - Method and structure to reduce optical crosstalk in a solid state imager: Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away and disposed of as waste during fabrication are left as conserved sections. These conserved sections are used to amend the properties and performance of the imager... Agent: Dickstein Shapiro LLP

20080173967 - Image sensor and method for manufacturing the same: Disclosed is an image sensor, which includes a dielectric layer on a substrate having a photodiode, a metal interconnection layer on the dielectric layer and an upper insulating layer on the metal interconnection layer. The metal interconnection layer includes a lower barrier layer, a bulk metal layer on the lower... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080173966 - Semiconductor device: A semiconductor device is disclosed. The semiconductor device provides a substrate comprising an image sensor region and a circuit region, wherein the circuit region comprises a pad region and a connecting region. A multilayer interconnect structure is formed on the substrate, wherein the multilayer interconnect structure comprises a plurality of... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080173968 - Diode: A diode is disclosed. One embodiment provides a semiconductor body having a front and a back, opposite the front in a vertical direction of the semiconductor body. The semiconductor body contains, successively in the vertical direction from the back to the front, a heavily n-doped zone, a weakly n-doped zone,... Agent: Dicke, Billig & Czaja

20080173969 - Configuration of high-voltage semiconductor power device to achieve three dimensionalcharge coupling: This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on... Agent: Bo-in Lin

20080173970 - Thermally decomposable spin-on bonding compositions for temporary wafer bonding: New spin-on, bonding compositions and methods of using those compositions are provided. The cured bonding compositions comprise a crosslinked oxazoline (either crosslinked with another oxazoline or with a crosslinking agent), and can be used to bond an active wafer to a carrier wafer or substrate to assist in protecting the... Agent: Hovey Williams LLP

20080173971 - Electrode isolation method and nanowire-based device having isolated electrode pair: Methods of creating isolated electrodes and integrating a nanowire therebetween each employ lateral epitaxial overgrowth of a semiconductor material on a semiconductor layer to form isolated electrodes having the same crystal orientation. The methods include selective epitaxial growth of a semiconductor feature through a window in an insulating film on... Agent: Hewlett Packard Company

20080173972 - Method of wafer thinning: A method for thinning a semiconductor wafer, the method includes selecting a semiconductor wafer having a buried stop layer; and planarizing the semiconductor wafer to the buried stop layer to produce a thin semiconductor wafer.... Agent: Cantor Colburn LLP-ibm Yorktown

20080173973 - Semiconductor integrated circuit device: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080173974 - Semiconductors device and method of manufacturing such a device: The invention relates to a semiconductor device (10) comprising a semiconductor body (1) with a high-ohmic semi-conductor substrate (2) which is covered with a dielectric layer (3, 4) containing charges, on which dielectric layer one or more passive electronic components (20) comprising conductor tracks (20) are provided, wherein, at the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080173975 - Programmable resistor, switch or vertical memory cell: Disclosed are embodiments of a device and method of forming the device that utilize metal ion migration under controllable conditions. The device embodiments comprise two metal electrodes separated by one or more different dielectric materials. One electrode is sealed from the dielectric material, the other is not. The device is... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080173976 - Air gap under on-chip passive device: A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric (“ILD”) layers... Agent: International Business Machines Corporation Dept. 18g

20080173978 - Mim capacitor and metal gate transistor: An embedded MIM capacitor in a logic circuit and method for forming the same are disclosed. The device includes a substrate, a bottom electrode, a dielectric film, and a top electrode. The substrate comprises an insulator region. The bottom electrode comprises a first conductor and overlies the insulator region. The... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080173977 - Post sti trench capacitor: A capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts... Agent: Whitham, Curtis & Christofferson, P.c.

20080173979 - Semiconductor device with leaning storage node contact and method for fabricating the same: A method for fabricating a semiconductor device including preparing a substrate provided with a first storage node contact, forming a second storage node contact over the first storage node contact, the second storage node contact leaning to one side, and forming a storage node of a capacitor over the second... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080173980 - Semiconductor device fabrication method and semiconductor device: A method for fabricating a semiconductor device is disclosed. The semiconductor device includes a capacitor and a support insulator. The capacitor includes a cylindrical electrode. The cylindrical electrode comprises upper and lower sections. The lower section has a roughened inner surface and an outer surface supported by the support insulator.... Agent: Sughrue Mion, Pllc

20080173981 - Integrated circuit (ic) chip with one or more vertical plate capacitors and method of making the capacitors: An Integrated Circuit (IC) chip with one or more vertical plate capacitors, each vertical plate capacitor connected to circuits on the IC chip and a method of making the chip capacitors. The vertical plate capacitors are formed with base plate pattern (e.g., damascene copper) on a circuit layer and at... Agent: Law Office Of Charles W. Peterson, Jr. Burlington

20080173982 - Resistance random access memory: A memory comprises a number of word lines in a first direction, a number of bit lines in a second direction, each coupled to at least one of the word lines, and a number of memory elements, each coupled to one of the word lines and one of the bit... Agent: Akin Gump LLP - Silicon Valley

20080173983 - Semiconductor device and method for manufacturing the same: Embodiments relate to a semiconductor device and a method for manufacturing a semiconductor device that may be capable of improving a step coverage of main chip and scribe lane regions during a formation of an interlayer dielectric are provided. In embodiments, the semiconductor device may include metal layers formed on... Agent: Sherr & Nourse, Pllc

20080173984 - Mechanically robust metal/low-k interconnects: A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the... Agent: Scully, Scott, Murphy & Presser, P.c.

20080173985 - Dielectric cap having material with optical band gap to substantially block uv radiation during curing treatment, and related methods: A dielectric cap and related methods are disclosed. In one embodiment, the dielectric cap includes a dielectric material having an optical band gap (e.g. greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons. The dielectric cap... Agent: Hoffman Warnick Llc

20080173986 - Multilayer silicon nitride deposition for a semiconductor device: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first... Agent: Fortkort & Houston P.c.

20080173987 - Semiconductor device: A high dielectric loss tangent layer is provided in a dielectric layer between a power-supply plane and a ground plane. The high dielectric loss tangent layer is arranged such that its edge is located between the edge of the power-supply plane and the edge of the ground plane. The edge... Agent: Mcginn Intellectual Property Law Group, Pllc

20080173988 - Gas phase precipitated polymers as highly insulating chip backside layer: A method for producing semiconductor chips has the following steps for this purpose: firstly, a semiconductor wafer having a multiplicity of semiconductor chip positions arranged in rows and columns is provided, wherein the semiconductor wafer has on its front side front sides of semiconductor chips with integrated circuits. The rear... Agent: Dicke, Billig & Czaja

20080173989 - Leadframe designs for plastic overmold packages: The specification describes a plastic overmolded package for high power devices that has a very low lead count, typically fewer than eight, and in a preferred embodiment, only two. The leads occupy essentially the same linear space as the multiple leads in a conventional package and thus have a wide-blade... Agent: Law Office Of Peter V.d. Wilde

20080173990 - Thermally enhanced single inline package (sip): In a method and system for fabricating a thermally enhanced semiconductor device (200, 300) is packaged as a through hole single inline package (SIP). A leadframe (210, 310, 410) having a die pad (220, 320, 420) to attach an IC die (230, 330), a first plurality of conductive leads (240,... Agent: Texas Instruments Incorporated

20080173991 - Pre-molded clip structure: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure... Agent: Townsend And Townsend And Crew, LLP

20080173992 - Semiconductor device including isolation layer: A semiconductor device includes a carrier, a semiconductor chip including an active area on a first face and a separate isolation layer applied to a second face, and an adhesion material coupling the isolation layer to the carrier with the second face facing the carrier.... Agent: Dicke, Billig & Czaja

20080173993 - Chip carrier substrate capacitor and method for fabrication thereof: A chip carrier substrate includes a capacitor aperture and a laterally separated via aperture, each located within a substrate. The capacitor aperture is formed with a narrower linewidth and shallower depth than the via aperture incident to a microloading effect within a plasma etch method that is used for simultaneously... Agent: Scully, Scott, Murphy & Presser, P.c.

20080173994 - Method of making release coatings for composite materials: A release film for soft composite materials is provided. The release film contains a film with a closely packed self-assembled monolayer. A method of applying soft composite materials to a substrate without loss of the soft composite material to the release film is also provided. The method is useful in... Agent: Connolly Bove Lodge & Hutz LLP

20080173997 - Electronic device and method of manufacturing the same: A method of manufacturing an electronic device includes the steps of: forming a conductive pattern on a film made of a resin material and thereby forming a base body on which a circuit chip is mounted; forming a reinforcing layer that suppresses expansion and contraction of the film in either... Agent: Greer, Burns & Crain

20080173995 - Memory card and manufacturing method of the same: There is a need to provide a large capacity memory card for a portable communication device. A memory card 1 includes: a wiring board 2 mainly composed of a glass epoxy resin; multiple semiconductor chips (3C and 3F) mounted on a main surface of the memory card 1; and a... Agent: Miles & Stockbridge Pc

20080173996 - Semiconductor card package and method of forming the same: A semiconductor card package and a method of manufacturing the semiconductor cared package are provided. The package may include a housing having a cavity. The cavity may have a size corresponding to at least one standard semiconductor package. External terminals may be exposed on the outside of the housing. Internal... Agent: Marger Johnson & Mccollom, P.c.

20080173998 - Chip arrangement and method for producing a chip arrangement: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second,... Agent: Merchant & Gould Pc

20080174001 - Semiconductor device: A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including a high frequency electrode that is mounted on the one side of the support substrate, a via hole that is provided... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080173999 - Stack package and method of manufacturing the same: A stack package and a method of manufacturing the same are provided. The stack package includes one or more interposers in which a semiconductor chip having a bonding pad are inserted, an interconnection terminal groove is formed due to a difference of the areas between the semiconductor chip and a... Agent: Marger Johnson & Mccollom, P.c.

20080174000 - Zigzag-stacked package structure: A die-stacked package structure, wherein a plurality of dies are stacked on the substrate with a rotation so that a plurality of metallic ends and the metal pad on each die on the substrate can all be exposed; a plurality of metal wires are provided for electrically connecting the plurality... Agent: Sinorica, Llc

20080174003 - Apparatus and method for reduced delamination of an integrated circuit module: An apparatus and method for reducing delamination of an integrated circuit module is disclosed. The integrated circuit module includes a laminate substrate. The integrated circuit module further includes an integrated circuit die operably coupled with the laminate substrate and a plastic semiconductor package overmolded with the laminate substrate. The laminate... Agent: Booth Udall, Plc

20080174004 - Semiconductor device using wiring substrate having a wiring structure reducing wiring disconnection: The semiconductor device concerning the present invention has a wiring substrate, a semiconductor chip, under-filling resin, a reinforcement ring, a heat spreader, a power supply pattern and a wiring layer under surface via land which are formed on the wiring substrate and spaced out by a clearance region, an insulating... Agent: Miles & Stockbridge Pc

20080174002 - Stress relieving layer for flip chip packaging: A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080174005 - Electronic device and method for manufacturing electronic device: An electronic device has a substrate that has first and second peripheral portions. The first peripheral portion provides a shearing position for separation. The electronic device has a plurality of wiring layers one of which forms a functional surface wiring on the substrate, an electronic element mounted on the substrate,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080174006 - Semiconductor device and method of manufacturing the same: a method of manufacturing a semiconductor device including (1) providing a metal plate having an upper surface and a back surface, the metal plate including a plurality of lids disposed in matrix, which are defined by a first groove formed from the upper surface, (2) providing a ceramic sheet having... Agent: Junichi Mimura Oki America Inc.

20080174007 - Heat sink with preattached thermal interface material and method of making same: A process of making an integrated heat spreader is disclosed. The integrated heat spreader is stamped with a thermal interface material under conditions to form a diffusion bonding zone between the integrated heat spreader and the thermal interface material. The thermal interface material can have one of several cross-sectional profiles... Agent: Schwegman, Lundberg & Woessner, P.a.

20080174008 - Structure of memory card and the method of the same: The present invention provides a structure of memory card comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and a through hole structure formed there through, traces formed within the substrate; a first die disposed within the die receiving cavity; a first dielectric... Agent: The Maxham Firm

20080174009 - Circuit board structure and fabrication method thereof: A circuit board structure and fabrication method thereof are disclosed, including: a circuit board with a circuit layer thereon; a reactant formed on the surface of the circuit layer, wherein the reactant is an organic metallic polymer having a polymer end and a metal ion end; and a dielectric layer... Agent: Pearne & Gordon LLP

20080174010 - Mems element fabrication method and mems element: A method of fabricating a MEMS element includes forming a MEMS element by forming a circuit layer on an element layer of an SOI substrate that is formed by laminating on a substrate, a first insulation layer and the element layer, and forming a second insulation layer including a conductive... Agent: Amin, Turocy & Calvin, LLP

20080174012 - Semiconductor device manufacturing method, semiconductor device, and wiring board: A semiconductor device manufacturing method includes (a) bonding a first surface of a metal plate to a substrate, (b) forming a plurality of metal posts that are arranged in vertical and lateral directions in a plan view and include a first metal post and a second metal post, by partially... Agent: Oliff & Berridge, Plc

20080174013 - Semiconductor device package and manufacturing method thereof: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The present... Agent: Muncy, Geissler, Olds & Lowe, Pllc

20080174011 - Semiconductor structure and method for forming the same: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate and an integrated circuit laid on the substrate. A barrier layer is formed to provide a flattened surface, so that the under bump metal can be formed thereon. In this way, discontinuities,... Agent: Birch Stewart Kolasch & Birch

20080174014 - Semiconductor device: A semiconductor device includes: a semiconductor substrate having an integrated circuit formed thereon and an electrode electrically coupled to the integrated circuit; a passivation film formed on a surface of the semiconductor substrate, the surface having the electrode formed thereon; a first metal layer formed so as to come into... Agent: Harness, Dickey & Pierce, P.L.C

20080174016 - Flexible printed wiring board and semiconductor device: A flexible printed wiring board is characterized by a laminate formed by directly laminating an electrodeposited copper foil having S side and M side, each of S side and M side having a different surface roughness, the surface roughness (Rzjis) of the deposition plain side being 1.0 μm or less,... Agent: The Webb Law Firm, P.c.

20080174015 - Removal of etching process residual in semiconductor fabrication: A semiconductor structure and methods for forming the same. A semiconductor fabrication method includes steps of providing a structure. A structure includes (a) a dielectric layer, (b) a first electrically conductive region buried in the dielectric layer, wherein the first electrically conductive region comprises a first electrically conductive material, and... Agent: Schmeiser, Olsen & Watts

20080174020 - Electronic device having metal pad structure and method of fabricating the same: An electronic device may include a protective insulating layer formed over a substrate. A plurality of metal pad structures may be spaced apart from one another. Each of the plurality of metal pad structures may pass through the protective insulating layer and/or have a top surface disposed at a higher... Agent: Harness, Dickey & Pierce, P.L.C

20080174017 - Hybrid interconnect structure for performance improvement and reliability enhancement: The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive... Agent: Scully, Scott, Murphy & Presser, P.c.

20080174018 - Semiconductor device and method for fabricating the same: An inventive semiconductor device includes: a lower interlayer dielectric film provided on a substrate; a lower interconnect made up of a lower barrier metal layer formed along a wall surface of a lower interconnect groove in the lower interlayer dielectric film, and a copper film; and an upper plug and... Agent: Mcdermott Will & Emery LLP

20080174019 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the semiconductor device are provided. The method includes: forming a base interlayer dielectric layer having a first metal wiring on a semiconductor substrate, and a diffusion stop layer on the base interlayer dielectric layer to expose the first metal wiring; forming a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080174021 - Semiconductor devices having metal interconnections, semiconductor cluster tools used in fabrication thereof and methods of fabricating the same: A method of fabricating a semiconductor device is provided. The method includes providing a semiconductor substrate having a conductive pattern and forming an insulating layer on the conductive pattern and the semiconductor substrate. The insulating layer is patterned to form an opening which exposes a portion of the conductive pattern.... Agent: Myers Bigel Sibley & Sajovec

20080174022 - Semiconductor device and fabrication method thereof: A semiconductor device. A dielectric layer is disposed on a substrate having a first region and a second region. A first metal layer and a second layer are embedded in the dielectric layer in the first and second regions, respectively, wherein the first and second metal layers are located at... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080174023 - Chip having side pad, method of fabricating the same and package using the same: A semiconductor device includes a first chip having a top surface, a bottom surface and a side surface connected to the top and bottom surfaces. The first chip includes a chip substrate; a lower conductive pattern over the chip substrate; an interlayer dielectric layer over the lower conductive pattern; and... Agent: Marger Johnson & Mccollom, P.c.

20080174024 - Method for realizing an electric linkage in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components: A method for realizes electric connections in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components. The method includes: providing a nanometric circuit architecture comprising a succession of conductive nanowires substantially parallel to each other and extended along a direction x; realizing, above the succession, an... Agent: Seed Intellectual Property Law Group Pllc

20080174025 - Semiconductor chip structure, method of manufacturing the semiconductor chip structure, semiconductor chip package, and method of manufacturing the semiconductor chip package: A semiconductor chip structure may include a semiconductor chip, a first insulation layer and a redistribution layer. The first insulation layer may be formed on the semiconductor chip. The first insulation layer may have at least one first groove formed at an upper surface portion of the first insulation layer.... Agent: Harness, Dickey & Pierce, P.L.C

20080174026 - Semiconductor device: A semiconductor device includes a semiconductor substrate provided with an integrated circuit and an electrode electrically coupled to the integrated circuit, a first resin layer formed on a surface of the semiconductor substrate, the surface provided with the electrode, a wiring electrically coupled to the electrode and formed on the... Agent: Harness, Dickey & Pierce, P.L.C

20080174029 - semiconductor device and method of forming metal pad of semiconductor device: A semiconductor device and a method of forming a metal pad of a semiconductor device is provided. The method includes forming a pre-metal dielectric (PMD) layer on a semiconductor substrate and a metal plug through the pre-metal dielectric layer. A metal layer may then be formed on the pre-metal dielectric... Agent: Workman Nydegger

20080174028 - Method and apparatus for a semiconductor structure forming at least one via: (b) a semiconductor layer disposed on at least a portion of the front or back surface of the semiconductor substrate, where the semiconductor layer is compositionally graded through its depth with one or more selected dopants, and the conductive material is configured to electrically couple the semiconductor layer to at... Agent: General Electric Company Global Research

20080174027 - Semiconductor interconnect structure with rounded edges and method for forming the same: Provided is a semiconductor interconnect structure formed from an original damascene or dual damascene structure. The original damascene or dual damascene structure includes a planar upper surface consisting of planar upper surfaces of conductive structures formed within openings formed in the dielectric, and planar upper surfaces of the dielectric. The... Agent: Duane Morris LLP Ip Department (tsmc)

20080174030 - Multichip stacking structure: The present invention provides a multi-chip stacking structure. The multichip stacking structure comprises: a chip carrier; a first and a second chip modules respectively having a plurality of first and a plurality of second chips, wherein each chips has a bond pad and the chips are stacked on the chip... Agent: Edwards Angell Palmer & Dodge LLP

20080174031 - Chip package reducing wiring layers on substrate and its carrier: An IC package primarily comprises a substrate, a die-attaching layer, a chip, at least a bonding wire, and a plurality of electrical connecting components. The substrate has a top surface and a bottom surface where the top surface includes a die-attaching area for disposing the die-attaching layer. The chip is... Agent: Joe Mckinney Muncy

20080169457 - Phase changeable memory devices including nitrogen and/or silicon: Phase-changeable memory devices and method of fabricating phase-changeable memory devices are provided that include a phase-changeable material pattern of a phase-changeable material that may include nitrogen atoms and/or silicon atoms. First and second electrodes are electrically connected to the phase-changeable material pattern and provide an electrical signal thereto. The phase-changeable... Agent: Myers Bigel Sibley & Sajovec

20080169458 - Nonvolatile memory and fabrication method thereof: Non-volatile memories formed on a substrate and fabrication methods are disclosed. A bottom electrode comprising a metal layer is disposed on the substrate. A buffer layer comprising a LaNiO3 film is disposed over the metal layer. A resistor layer comprising a SrZrO3 film is disposed on the buffer layer. A... Agent: Joe Mckinney Muncy

20080169459 - Storage node of a resistive random access memory device and method of manufacturing the same: Provided are a resistive random access memory device and a method of manufacturing the same. The resistive random access memory device includes a switching device and a storage node connected to the switching device, and the storage node includes a first electrode and a second electrode and a resistance change... Agent: Harness, Dickey & Pierce, P.L.C

20080169461 - Display device and method of manufacturing the same: A display device includes; an insulation substrate, a thin film transistor disposed on the insulation substrate and which includes a drain electrode, an insulation layer disposed on the thin film transistor and which includes a contact hole which exposes the drain electrode, a first electrode disposed on the insulation layer... Agent: Cantor Colburn, LLP

20080169464 - Metal-insulator- metal (mim) devices and their methods of fabrication: Two-terminal switching devices of MIM type having at least one electrode formed by a liquid phase processing method are provided for use in active matrix backplane applications; more specifically, MIM devices with symmetric current-voltage characteristics are applied for LCD active matrix backplane applications, and MIM devices with asymmetric current-voltage characteristics... Agent: Beyer Weaver LLP

20080169463 - Organic light emitting device and manufacturing method thereof: An organic light emitting device includes a substrate, first and second ohmic contacts formed on the substrate, a driving semiconductor formed on the substrate and the first and second ohmic contacts and including polysilicon, a driving input electrode electrically connected to the first ohmic contact, a driving output electrode electrically... Agent: Macpherson Kwok Chen & Heid LLP

20080169460 - Organic light emitting diodes display and aging method thereof: An organic light emitting diode display and an aging method thereof are presented. The method provides the organic light emitting diode display with improved reliability as a progressive dark defect is removed, and the lifetime and the white balance of the organic light emitting diode display is secured by executing... Agent: Knobbe Martens Olson & Bear LLP

20080169462 - Thin film transistor, electro-optical device, and electronic apparatus: A thin film transistor includes a source electrode and a drain electrode which are disposed to face each other, an organic semiconductor layer provided at least between the source electrode and the drain electrode, a plurality of gate lines extending over the source electrode, the organic semiconductor layer, and the... Agent: Advantedge Law Group, LLC

20080169467 - Semiconductor device: A transistor of a characteristic checking element has a gate electrode connected to a measurement pad disposed in a dicing line and to an internal measurement pad disposed inside a semiconductor device. In a P/W process, a gate insulating film of the transistor is broken by an electric voltage applied... Agent: Foley And Lardner LLP Suite 500

20080169465 - Semiconductor probe structure using impact-ionization metal oxide semiconductor device, information storing device therewith and manufacturing method thereof: A method of manufacturing a probe includes: forming a first slant face of the probe through an anisotropic etching process using a first etching mask pattern formed on a silicon substrate; forming a first semiconductor electrode region; forming a second etching mask pattern in an opposite direction of the first... Agent: Sughrue Mion, PLLC

20080169466 - Test cells for semiconductor yield improvement: A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially parallel to the first and second active regions, a fourth active region formed between the first and second active regions, and... Agent: Morrison & Foerster LLP

20080169468 - Method and apparatus for fabricating polycrystalline silicon film using transparent substrate: Provided is a method and apparatus for fabricating a polycrystalline silicon film using a transparent substrate. The method includes forming a light absorption layer on a surface of the transparent substrate; and heating the light absorption layer using irradiation of Rapid Thermal Process (RTP) light source, while depositing the polycrystalline... Agent: Volpe And Koenig, P.C.

20080169469 - Display device: A display device for improving an aperture ratio of the pixel is provided. In the display device, a transparent oxide layer, an insulating film, and a conductive layer are sequentially stacked on a pixel region on a substrate, the conductive layer has a gate electrode of a thin film transistor... Agent: Stanley P. Fisher Reed Smith LLP

20080169471 - Display substrate and method of manufacturing the same: A display substrate includes a gate line, a data line, a pixel electrode and a source pad part. The gate line is formed on a base substrate. The data line crosses the gate line to define a pixel area. The pixel electrode makes contact with the base substrate. The source... Agent: Macpherson Kwok Chen & Heid LLP

20080169470 - Thin film transistor array substrate and method of manufacturing the same: A thin film transistor (TFT) array substrate and a method of manufacturing the same that is capable of decreasing the number of usage of exposure masks to reduce the process time and the process costs and excessively etching a passivation film below a photoresist pattern to easily perform a lift-off... Agent: Seyfarth Shaw, LLP

20080169472 - Field effect transistor: Disclosed are embodiments of a field effect transistor that incorporates an elongated semiconductor body with a spiral-shaped center channel region wrapped one or more times around a gate and with ends that extend outward from the center region in opposite directions away from the gate. Source/drain regions are formed in... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080169473 - Thin film transistor array panel: A thin film transistor array panel includes an insulating substrate, a plurality of gate lines formed on the substrate, a plurality of data lines, and an insulating layer. Each of the gate lines include a plurality of gate electrodes. The data lines cross the gate lines with insulation therebetween. Each... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080169474 - Integrated nitride and silicon carbide-based devices and methods of fabricating integrated nitride-based devices: Monolithic electronic devices including a common nitride epitaxial layer are provided. A first type of nitride device is provided on the common nitride epitaxial layer including a first at least one implanted n-type region on the common nitride epitaxial layer. The first at least one implanted n-type region has a... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080169476 - Low 1c screw dislocation 3 inch silicon carbide wafer: A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 3 inches and a 1c screw dislocation density of less than about 2000 cm 2.... Agent: Summa, Allan & Additon, P.A.

20080169475 - Sic schottky barrier semiconductor device: A semiconductor device includes a first-conductivity-type SiC substrate, a first-conductivity-type SiC semiconductor layer formed on the substrate, whose impurity concentration is lower than that of the substrate, a first electrode formed on the semiconductor layer and forming a Schottky junction with the semiconductor layer, a barrier height of the Schottky... Agent: Charles N.j. Ruggiero, Esq. Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20080169477 - Package structure for optoelectronic device and fabrication method thereof: A package structure for an optoelectronic device. The package structure comprises a device chip reversely disposed on a first substrate, which comprises a second substrate and a first dielectric layer between the first and second substrates. The first dielectric layer comprises a pad formed in a corner of the first... Agent: Joe Mckinney Muncy

20080169478 - Photocoupler: A photocoupler includes a silicon substrate, a light receiving element embedded in the substrate, a transparent insulating film formed on the substrate to cover the light receiving element, and a light emitting element facing the light receiving element via the transparent insulating film. The light emitting element is an organic... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20080169479 - Light-emitting diode: A light-emitting diode includes a substrate (110), a reflective layer (120), a second diffraction grating (130), a first semiconductor layer (142), an active layer (144), a second semiconductor layer (146), a transparent electrode layer (148), and a first diffraction grating (150), arranged in that order. The first diffraction grating and... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang

20080169480 - Optoelectronic device package and packaging method thereof: An optoelectronic device package. The optoelectronic device package includes a substrate, a reflector formed on a first plane of the substrate, a cover bonded to the reflector to form a closed space, a plurality of microlenses formed on a first plane of the cover, a phosphor film formed on a... Agent: Joe Mckinney Muncy

20080169482 - Semiconductor light emitting device and a method for manufacturing the same: Disclosed is a semiconductor light emitting device comprising a reflective structure layer comprising a dopant layer and a roughness layer, a first conductive semiconductor layer on the reflective structure layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer.... Agent: Birch Stewart Kolasch & Birch

20080169481 - Semiconductor light emitting device having metal reflective layer: A semiconductor light emitting device including: a support substrate; a composite connection layer formed above the support substrate, the composite connection layer including a first connection layer and a second connection layer; a diffusion barrier layer formed above the composite connection layer; a semiconductor lamination structure formed above the diffusion... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080169483 - Substrate having thin film of gan joined thereon and method of fabricating the same, and a gan-based semiconductor device and method of fabricating the same: There is provided a method of producing a thin GaN film-joined substrate, including the steps of: joining on a GaN bulk crystalline body a substrate different in type or chemical composition from GaN; and dividing the GaN bulk crystalline body at a plane having a distance of at least 0.1... Agent: Mcdermott Will & Emery LLP

20080169484 - Strained transistor with optimized drive current and method of forming: A strain-induced layer is formed atop a MOS device in order to increase carrier mobility in the channel region. The dimension of the strain-induced layer in preferred embodiments may lead to an optimized drive current increase and improved drive current uniformity in an NMOS and PMOS device. An advantage of... Agent: Slater & Matsil, L.L.P.

20080169485 - Field effect transistor device and method of producing the same: A semiconductor device is disclosed. In one aspect, the device comprises a channel area, the channel area comprising a channel layer in which charge carriers can move when the transistor is turned on, in order to pass a current through the transistor. The device further comprises a source area and... Agent: Knobbe Martens Olson & Bear LLP

20080169486 - semiconductor integrated circuit device: To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to... Agent: Miles & Stockbridge PC

20080169487 - Layout structure of semiconductor integrated circuit: In a layout structure of a semiconductor integrated circuit, when transistors are arranged in a constant gate wiring pitch, a common source diffusion region is provided between two adjacent transistors, a CA via is provided on the common source diffusion region, and a source wiring connected to the CA via... Agent: Mcdermott Will & Emery LLP

20080169488 - Device selection circuitry constructed with nanotube technology: A memory system having electromechanical memory cells and decoders is disclosed. A decoder circuit selects at least one of the memory cells of an array of such cells. Each cell in the array is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon.... Agent: Wilmerhale/boston

20080169489 - Multi-walled tube and method of manufacture: A method of forming multi-wall tube from a single-wall piece of tube. The multi-wall tube is formed by relative motion between a die shoe and the single-wall tube to deform the material.... Agent: Krieg Devault LLP

20080169490 - Semiconductor device and manufacturing method thereof: Disclosed is a semiconductor device using an SOI substrate and improving carrier mobility of transistors. Over a thin Si layer formed over a Si substrate through a buried insulating film, a gate electrode is formed through a gate insulating film. On both sides of the gate electrode, S/D layers are... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080169491 - Solid-state imaging device, electronic module and electronic apparatus: A solid-state imaging device including an imaging area formed of a plurality of pixels arrayed in a two-dimensional matrix is provided. The solid-state imaging device includes: a photoelectric conversion portion including a charge accumulation region provided on a semiconductor substrate; a read transistor for reading electric charges from the photoelectric... Agent: Sonnenschein Nath & Rosenthal LLP

20080169492 - Spin transistor using stray magnetic field: Disclosed herein is a spin transistor including: a semiconductor substrate having a channel layer formed therein; first and second electrodes which are formed to be spaced apart from each other on the substrate at a predetermined distance along a longitudinal direction of the channel layer; a source and drain which... Agent: Perkins Coie LLP

20080169493 - Semiconductor devices and dynamic random access memories having a retrograde region and methods of forming the same: Semiconductor devices include an active region defined in a semiconductor substrate having first type impurity ions. A retrograde region is in the active region and has second type impurity ions. An upper channel region is on the retrograde region in the active region and has the first type impurity ions.... Agent: Myers Bigel Sibley & Sajovec

20080169494 - Self-aligned body contact for a semiconductor-on-insulator trench device and method of fabricating same: A structure and method of forming a body contact for a semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of... Agent: Schmeiser, Olsen & Watts

20080169495 - Fin differential mos varactor diode: The embodiments of the invention provide a structure, method, etc. for a fin differential MOS varactor diode. More specifically, a differential varactor structure is provided comprising a substrate with an upper surface, a first vertical anode plate, and a second vertical anode plate electrically isolated from the first vertical anode... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080169496 - Methods of forming nand cell units: Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern... Agent: Wells St. John P.s.

20080169498 - Non-volatile programmable memory cell and array for programmable logic array: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor,... Agent: Lewis And Roca, LLP

20080169497 - Non-volatile semiconductor memory and method for fabricating a non-volatile semiconductor memory: A non-volatile semiconductor memory includes memory cell transistors arranged in a matrix, wherein each of the memory cell transistors is a depletion mode MIS transistor.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080169499 - Flash memory using sti structure in element isolation region and manufacturing method thereof: A flash memory includes a memory cell portion and peripheral circuit portion. The memory cell portion has first gate dielectric films formed on the main surface of a semiconductor substrate and floating gate electrode layers formed on the first gate dielectric films. The peripheral circuit portion has second gate dielectric... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080169500 - Low voltage non-volatile memory cell with shared injector for floating gate: A non-volatile transistor memory array having memory cells, each with a control transistor and a floating gate memory transistor. The cells are arranged in symmetric quadrants with active regions appearing as tic-tac-toe style strips having a central shared drain erase region. Within the drain erase region is an avalanche diode... Agent: Schneck & Schneck

20080169501 - Flash memory device with hybrid structure charge trap layer and method of manufacturing same: A flash memory device including a hybrid structure charge trap layer and a related method of manufacture are disclosed. The charge trap layer includes at least one hybrid trap layer including a first trap layer formed from a first material having a first band gap energy, and a plurality of... Agent: Volentine & Whitt PLLC

20080169502 - Dual bit flash memory devices and methods for fabricating the same: Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall... Agent: Ingrassia Fisher & Lorenz, P.C.

20080169504 - Semiconductor constructions, methods of forming semiconductor constructions, and methods of recessing materials within openings: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F8. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded... Agent: Wells St. John P.s.

20080169503 - Semiconductor nanostructures, semiconductor devices, and methods of making same: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080169505 - Structure of trench mosfet and method for manufacturing the same: A trench MOSFET with copper metal connections is disclosed. A substrate is provided with a plurality of trenches. A gate oxide layer is formed on the sidewalls and bottoms of the trenches. A conductive layer is filled in the trenches to be used as a gate of the MOSFET. A... Agent: Alan D. Kamrath, Kamrath & Associates., P.A.,

20080169506 - Emitter-switched power actuator: A power actuator of the emitter-switched type is described, the power actuator comprising at least one high voltage bipolar transistor and a low voltage DMOS transistor connected in cascode configuration between a collector terminal of the bipolar transistor and a source terminal of the DMOS transistor and having respective control... Agent: Seed Intellectual Property Law Group PLLC

20080169507 - Discrete on-chip soi resistors: A semiconductor resistor, method of making the resistor and method of making an IC including resistors. Buried wells are formed in the silicon substrate of a silicon on insulator (SOI) wafer. At least one trench is formed in the buried wells. Resistors are formed along the sidewalls of the trench... Agent: Law Office Of Charles W. Peterson, Jr. Burlington

20080169508 - Stressed soi fet having doped glass box layer: A method is provided for fabricating a semiconductor-on-insulator (“SOI”) substrate including (i) an SOI layer of monocrystalline silicon separated from (ii) a bulk semiconductor layer by (ii) a buried oxide (“BOX”) layer, the BOX layer including a layer of doped silicate glass. In such method, a sacrificial stressed layer is... Agent: International Business Machines Corporation Dept. 18g

20080169509 - Semiconductor device: A semiconductor device includes a first well of a first conductive type formed in a surface portion of a semiconductor substrate; a first contact group connected with the first well; a second well of a second conductive type formed to surround the first well in the surface portion of the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080169510 - Performance enhancement on both nmosfet and pmosfet using self-aligned dual stressed films: In an integrated circuit comprising both PMOSFETs and NMOSFETs, carrier mobility is enhanced on both types of FETs using dual stressed films. The adverse impact of having both layers of stressed films along the boundary between different types of films is eliminated by utilizing self-alignment of the edges of a... Agent: Scully, Scott, Murphy & Presser, P.C.

20080169511 - Dual gate cmos fabrication: The invention relates to a method of fabricating a CMOS device, comprising providing a semiconductor substrate (101) having therein a layer of insulating material (102), the method comprising providing a layer (106) of a first material over the insulating layer (102), the thickness of the layer (106) of the first... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080169512 - Non-planar pmos structure with a strained channel region and an integrated strained cmos flow: A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-x Gex layer is patterned and subsequently etched to form a fin on... Agent: Intel/blakely

20080169513 - Emitter ballasting by contact area segmentation in esd bipolar based semiconductor component: Integrated circuits (ICs) utilize bipolar transistors in electro-static discharge (ESD) protection circuits to shunt discharge currents during ESD events to protect the components in the ICs. Bipolar transistors are subject to non-uniform current crowding across the emitter-base junction during ESD events, which results in less protection for the IC components... Agent: Texas Instruments Incorporated

20080169515 - Semiconductor devices and methods of forming the same: Semiconductor devices are disclose that include a first doped region and a second doped region spaced apart from each other and defined within a same well of a semiconductor substrate. A gate insulating layer and a gate electrode are stacked on a channel region between the first and second doped... Agent: Myers Bigel Sibley & Sajovec

20080169514 - Stack resistor structure for integrated circuits: A resistor structure for an integrated circuit includes a first set of contacts connected between a semiconductor layer and a first conductive layer; and a second set of plugs connected between the first conductive layer and a second conductive layer, wherein the first set of contacts and the second set... Agent: Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080169516 - Semiconductor devices for alleviating well proximity effects: A semiconductor device is disclosed for alleviating well proximity effects. The semiconductor device comprises a well in a substrate; and a transistor with an active region and a gate of 0.13 um or less in gate length, wherein the gate is entirely within or extended to outside of the well,... Agent: Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080169517 - Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices: A method for manufacturing electronic devices on a semiconductor substrate with wide band gap that includes the steps of: forming a screening structure on the semiconductor substrate to include at least a dielectric layer that leaves a plurality of areas of the semiconductor substrate exposed, carrying out at least a... Agent: Seed Intellectual Property Law Group PLLC

20080169519 - Process for manufacturing a power device on a semiconductor substrate and corresponding device: An electronic device includes a semiconductor substrate of a first conductivity type and a drain layer adjacent the semiconductor substrate and having a plurality of drains. The drain layer includes a first semiconductor layer of the first conductivity type adjacent the semiconductor substrate, and at least one second semiconductor layer... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080169518 - Semiconductor structure with field shield and method of forming the structure.: Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080169520 - Dieletric film layered product, semiconductor apparatus and production methods of the same: In order to provide a dielectric film which can avoid both boron leakage and an increase of the leak current, a semiconductor apparatus which has the dielectric film, a production method of the dielectric film and a production method of the semiconductor apparatus, a dielectric film layered product is applied... Agent: Young & Thompson

20080169521 - Mems structure using carbon dioxide and method of fabrication: A MEMS device is encapsulated in a carbon dioxide environment, which effectively insulates the MEMS device against arcing in high voltage applications. The carbon dioxide environment may have a pressure of between about 0.2 atm and about 4 atm. Carbon dioxide is shown to be more effective than other insulating... Agent: Jaquelin K. Spong

20080169522 - Moving element and method of manufacturing the same: A moving element includes at least a substrate including a support, a moving body, and an elastic body connecting the moving body to the support. The support includes a buried film formed in it. The buried film of the support is formed only near end faces of the support that... Agent: Scully Scott Murphy & Presser, PC

20080169524 - Image sensor and method of forming the same: A method for forming an image sensor is provided. The method includes providing a semiconductor substrate having a pixel region and a peripheral circuit region, forming a photoelectric transformation section at the semiconductor substrate of the pixel region, forming a plurality of interlayer dielectrics over the semiconductor substrate with interconnections... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080169523 - Imaging optical module designed to be associated with an optical semiconductor component and method of fabricating same: An imaging optical module is designed to be placed in front of an optical image sensor of a semiconductor component. The module includes at least one element which has a refractive index that varies between its optical axis and its periphery, over at least an annular part and/or over its... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20080169525 - Ground and power mesh in an integrated circuit chip: A chip device with a number of individually powered parts, such as photoreceptors. A mesh is provided to provide power to the individual photoreceptors. The mesh may be provided for ground and power and/or both. The mesh may be on different layers, so that one portion of the mesh is... Agent: Law Office Of Scott C Harris

20080169526 - Power semiconductor device: A power semiconductor device is provided having a field plate that employs a thick metal film in an edge termination structure and which permits edge termination structure width reduction even with large side etching or etching variation, which exhibits superior long-term forward blocking voltage capability reliability, and which allows minimal... Agent: Rossi, Kimms & Mcdowell LLP.

20080169527 - Semiconductor device and method of manufacturing such a device: According to the invention, the semiconductor region (5) is monocrystalline and of a second conductivity type, opposite to the first conductivity type. In this way the charge of an induced channel is locally compensated by the charge of the semiconductor regions (5). The device (10) has a very low high-frequency... Agent: Philips Intellectual Property & Standards

20080169528 - Subground rule sti fill for hot structure: This invention provides a hybrid orientation (HOT) semiconductor-on-insulator (SOI) structure having an isolation region, e.g. a shallow trench isolation region (STI), and a method for forming the STI structure that is easy to control. The method of forming the isolation region includes an etch of the insulating material, selective to... Agent: International Business Machines Corporation Dept. 18g

20080169529 - Efuse containing sige stack: An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a... Agent: International Business Machines Corporation Dept. 18g

20080169530 - X8r dielectric composition for use with nickel electrodes: Multilayer ceramic chip capacitors which satisfy X8R requirements and which are compatible with reducing atmosphere sintering conditions so that non-noble metals such as nickel and nickel alloys thereof may be used for internal and external electrodes are made in accordance with the invention. The capacitors exhibit desirable dielectric properties (high... Agent: Rankin, Hill & Clark LLP

20080169531 - Methods of forming nano line structures in microelectronic devices and related devices: A method of forming a microelectronic device includes forming a groove structure having opposing sidewalls and a surface therebetween on a substrate to define a nano line arrangement region. The nano line arrangement region has a predetermined width and a predetermined length greater than the width. At least one nano... Agent: Myers Bigel Sibley & Sajovec

20080169532 - Iii nitride single crystal, and manufacturing method therefor and semiconductor device therewith: A III nitride single-crystal manufacturing method in which a liquid layer (3) of 200 μm or less thickness is formed in between a substrate (1) and a III nitride source-material baseplate (2), and III nitride single crystal (4) is grown onto the face (1s) on the liquid-layer side of the... Agent: Judge Patent Associates

20080169533 - Die saw crack stopper: A novel die saw crack stopper that consists of placing formations into the scribe line of multiple metal layers of a die. These formations comprise multiple right-angle shapes that are interconnected at right angles. In an embodiment the formations have an overall shape that has a special meaning, such as... Agent: Slater & Matsil, L.L.P.

20080169534 - Reduced defect silicon or silicon germanium deposition in micro-features: A method is provided for reduced defect such as void free or reduced void Si or SiGe deposition in a micro-feature on a patterned substrate. The micro-feature includes a sidewall and the patterned substrate contains an isolation layer on the field area and on the sidewall and bottom of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080169535 - Sub-lithographic faceting for mosfet performance enhancement: The present invention provides structures and methods for providing multiple parallel V-shaped faceted grooves with sub-lithographic widths on a semiconductor substrate for enhanced performance MOSFETs. A self-aligning self-assembling material is used to pattern multiple parallel sub-lithographic lines. By employing an anisotropic etch that produces crystallographic facets on a semiconductor surface,... Agent: Scully, Scott, Murphy & Presser, P.C.

20080169536 - Semiconductor device and signal terminating method thereof: A semiconductor device may include a semiconductor chip including a signal terminating resistor coupled between a signal input pad and a first ground voltage pad, a semiconductor package including a signal input terminal and a first ground voltage terminal, the signal input terminal being electrically coupled to the signal input... Agent: Lee & Morse, P.C.

20080169537 - Semiconductor device: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080169538 - Semiconductor device: A semiconductor device of the present invention includes a semiconductor chip, a die pad to which the semiconductor chip is bonded with solder to be mounted thereon, a plurality of leads electrically conducted to the semiconductor chip, a stress reducing layer that is provided on a rear face of the... Agent: Fish & Richardson P.C.

20080169540 - Lead frame structure of light emitting diode: A lead frame structure of a light emitting diode is disclosed. The lead frame structure comprises a bonding zone, two wing-shaped reflective surfaces, a first electrode lead, and a second electrode lead. The first electrode lead and the second electrode lead are respectively connected to the bonding zone. The bonding... Agent: Pai Patent & Trademark Law Firm

20080169539 - Under bump metallurgy structure of a package and method of making same: A package for a semiconductor integrated circuit die comprises a redistributed layer formed over a first barrier layer electrically connected to a bonding pad of a die. A second barrier layer is formed over the redistributed layer. A multi-metal layer is formed over the second barrier layer for coupling to... Agent: Dla Piper US LLP

20080169541 - Enhanced durability multimedia card: A memory card comprising a leadframe having a plurality of contacts. Electrically connected to the leadframe is at least one semiconductor die. A body at least partially encapsulates the leadframe and includes opposed top and bottom surfaces, an opposed pair of longitudinal sides, and an opposed pair of lateral sides.... Agent: Stetina Brunda Garred & Brucker

20080169542 - Semiconductor device and manufacturing method thereof: A semiconductor device having a multilayer wiring structure and a manufacturing method thereof are provided. A semiconductor device and a manufacturing method thereof are provided in which the reliability and the manufacturing yield are high and the design constraint is small. Wirings are formed on a substrate. Low dielectric constant... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080169543 - Two dimensional stacking using interposers: A two dimensional stacking structure for integrated chip stacking on a printed circuit board having a controller electrically coupling on the printed circuit board, comprising a first integrated circuit package, a second integrated circuit package and two interposers. The first integrated circuit package is located beside the controller and electrically... Agent: Pai Patent & Trademark Law Firm

20080169544 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device includes: mounting a semiconductor chip on a substrate; forming an upper connection terminal on a side of the substrate on which the semiconductor chip is mounted; forming a resin seal portion that seals the semiconductor chip and the upper connection terminal so that... Agent: Wagner, Murabito & Hao LLP

20080169547 - Semiconductor modules with enhanced joint reliability: Provided is a semiconductor module with enhanced joint reliability. The semiconductor module includes a package, a printed circuit board (PCB), and conductive joint structures for electrically connecting the package with the PCB. The PCB includes at least one buffer layer that can alleviate the thermal deformation of the semiconductor module... Agent: Marger Johnson & Mccollom, P.C.

20080169548 - Semiconductor package having a semiconductor chip in a substrate and method of fabricating the same: Example embodiments relate to a semiconductor package having a semiconductor chip provided in a substrate and a method of fabricating the same. The semiconductor package may include a semiconductor substrate having a first through hole and a plurality of second through holes spaced apart from the first through hole. A... Agent: Harness, Dickey & Pierce, P.L.C

20080169546 - Stack type semiconductor chip package having different type of chips and fabrication method thereof: A stack type semiconductor chip package includes a first wafer mold, a protection substrate, and a second wafer mold that are stacked in a wafer level process. The first wafer mold includes a first chip having first pads and a first mold layer encapsulating the first chip. The protection substrate... Agent: Marger Johnson & Mccollom, P.C.

20080169549 - Stacked integrated circuit package system and method of manufacture therefor: An integrated circuit package system including providing a base substrate, attaching a base integrated circuit on the base substrate, attaching a core substrate over the base integrated circuit, attaching a substrate electrical connector between the core substrate and the base substrate, and applying an encapsulant having the core substrate partially... Agent: Law Offices Of Mikio Ishimaru

20080169545 - Stacked structure of semiconductor devices, semiconductor device package, and methods of fabricating the same: A stacked structure of semiconductor devices may include a plurality of stacked semiconductor devices, each having an upper surface and a lower surface and one or more via electrodes protruding from the upper surface to the lower surface. The via-electrodes may have upper parts (heads) protruding from the upper surface... Agent: Harness, Dickey & Pierce, P.L.C

20080169550 - Thin planar semiconductor device having electrodes on both surfaces and method of fabricating same: A thin, planar semiconductor device having electrodes on both surfaces is disclosed. This semiconductor device is provided with an IC chip and a wiring layer having one side that is electrically connected to surface electrodes of the IC chip. On this surface of the wiring layer, conductive posts are provided... Agent: Katten Muchin Rosenman LLP

20080169553 - Fabrication of a micro-electromechanical system (mems) device from a complementary metal oxide semiconductor (cmos): A method of fabricating a micro-electromechanical system (MEMS) device from a complementary metal oxide semiconductor (CMOS) having a silicon layer and an oxide layer, the oxide layer being on the silicon layer and containing at least one metal layer. The method includes etching the silicon layer of the CMOS to... Agent: Akerman Senterfitt

20080169551 - Ic chip package with near substrate scale chip attachment: An IC package with a near-substrate-scale die-attaching layer includes a substrate, a near-substrate-scale die-attaching layer, a chip, a plurality of bonding wires, an encapsulant, and a plurality of solder balls. A plurality of ball pads are formed on the bottom surface of the substrate for solder ball placement. The near-substrate-scale... Agent: Troxell Law Office PLLC

20080169552 - Semiconductor device and programming method: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the... Agent: Wagner, Murabito & Hao LLP

20080169554 - Plastic semiconductor packages having improved metal land-locking features: A semiconductor device having a plastic package with a linear array of metal lands (202, 212) with parallel perimeter portions (203a, 213a). Pairs of adjacent lands have their facing parallel perimeter portions oriented in parallel, defining a centerline. The land perimeters have flanges remote from the surface, each flange shaped... Agent: Texas Instruments Incorporated

20080169555 - Anchor structure for an integrated circuit: An integrated circuit product includes a die and an insulation layer. The insulation layer is operatively coupled to the die. The insulation layer includes a plurality of bump apertures. The insulation layer also includes an underfill anchor structure. Methods for making such an integrated circuit product are also described.... Agent: Advanced Micro Devices, Inc. C/o Vedder Price P.C.

20080169556 - Chip package module heat sink: A heat sink mechanism including multiple heat passages in the base of a casing of a chip package module penetrating through a substrate packed in the module; a metal material being deposited in each heat passage to become a heat sink conductor connecting the substrate and the surface of the... Agent: Troxell Law Office PLLC Suite 1404

20080169557 - System-in-package packaging for minimizing bond wire contamination and yield loss: A system-in-package (SiP) package is provided. In one embodiment, the SiP package comprises a substrate having a first surface and a second surface opposite the first surface, the substrate having a set of bond wire studs on bond pads formed on the second surface thereof; a first semiconductor chip having... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080169559 - Bump structure with annular support and manufacturing method thereof: A bump structure with an annular support suitable for being disposed on a substrate is provided. The substrate has at least one pad and a passivation layer that has at least one opening exposing a portion of the pad. The bump structure with the annular support includes an under ball... Agent: Jianq Chyun Intellectual Property Office

20080169558 - Redistribution circuit structure and manufacturing method thereof: A method of manufacturing a redistribution circuit structure is provided. First, a substrate is provided. The substrate has a plurality of pads and a passivation layer. The passivation layer has a plurality of first openings exposing a portion of each of the pads, respectively. A first patterned photoresist layer is... Agent: Jianq Chyun Intellectual Property Office

20080169561 - Semiconductor device and manufacturing method thereof: A polygonal semiconductor device includes a substrate and a wiring layer. The substrate includes semiconductor circuit elements. The wiring layer includes a dielectric sealing layer, a plurality of first electrodes, and a plurality of second electrodes. The first and second electrodes both extend through the dielectric sealing layer in its... Agent: Rabin & Berdo, PC

20080169560 - Semiconductor device and package including the same: Provided is a semiconductor device. The semiconductor device includes a first bump column on an active surface of the semiconductor device and including a plurality of first bumps spaced a first distance from an edge of the semiconductor device, a second bump column on the active surface and including a... Agent: Marger Johnson & Mccollom, P.C.

20080169562 - Semiconductor device having conductive bumps and fabrication method thereof: A semiconductor device having conductive bumps and a fabrication method thereof are provided. The fabrication method mainly including steps of: providing a semiconductor substrate having a solder pad and a passivation layer formed thereon with a portion of the solder pads exposed from the passivation layer; disposing a first metal... Agent: Edwards Angell Palmer & Dodge LLP

20080169563 - Semiconductor package and method of manufacturing the same: A semiconductor package is disclosed that includes a semiconductor device; a circuit board; and a connection mechanism including a first conductive terminal provided on the semiconductor device, and a second conductive terminal provided on the circuit board side, the connection mechanism electrically connecting the semiconductor device and the circuit board... Agent: Kratz, Quintos & Hanson, LLP

20080169564 - Multi-layer substrate and electronic device having the same: A multi-layer substrate includes a plurality of substrate main bodies, a plurality of layers which are alternately layered with the main bodies, a signal via hole which is connected with a signal line and includes a signal column which passes through at least one substrate main body; and a sub... Agent: Stanzione & Kim, LLP

20080169565 - Metal capping process for beol interconnect with air gaps: The embodiments of the invention provide a metal capping process for a BEOL interconnect with air gaps. More specifically an apparatus is provided comprising metal lines within a first dielectric. Metal caps are over the metal lines, wherein the metal caps contact the metal lines. In addition, air gaps are... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080169566 - Press-fit diode having a silver-plated wire termination: A press-fit diode, e.g., for rectifier applications, includes a diode chip, a base contact for pressing into a substrate, which base contact forms a first terminal of the press-fit diode, and a wire contact which forms a second terminal of the press-fit diode. An easily solderable corrosion-resistant press-fit diode is... Agent: Kenyon & Kenyon LLP

20080169569 - Bonding pad of semiconductor integrated circuit, method for manufacturing the bonding pad, semiconductor integrated circuit, and electronic device: According to the present invention, a bonding pad 10 of a semiconductor integrated circuit is arranged such that the opening pathways P through which metal wiring layers are connected have openings of at least two different widths including: a first width required to fill the opening pathway; and a second... Agent: Nixon & Vanderhye, PC

20080169567 - Spacer patterns using assist layer for high density semiconductor devices: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a... Agent: Vierra Magen/sandisk Corporation

20080169568 - Structure and method of making interconnect element having metal traces embedded in surface of dielectric: A multilayer interconnect element is provided which includes at least one dielectric element in which metal interconnect patterns are exposed at an outer surface thereof, the metal interconnect patterns having outer surfaces which are co-planar with an exposed outer surface of the dielectric element. In addition, multilayer interconnect elements are... Agent: Tessera Lerner David Et Al.

20080169572 - Interconnect structure encased with high and low k interlevel dielectrics: A structure for improving the electrostatic discharge robustness of an integrated circuit having an electrostatic discharge (ESD) device and a receiver network connected to a pad by interconnects. The interconnect between the pad and the ESD device has a high-k material placed adjacent to at least one surface of the... Agent: Ibm Microelectronics Intellectual Property Law

20080169570 - Method for manufacturing a semiconductor device using a reflow sputtering technique: An AlCu film is formed by simultaneously depositing AlCu within a via hole and on top of an interlayer dielectric film. The surface of the AlCu film is polished using a CMP process, and a TiN antireflection layer is formed thereon. The TiN antireflection layer having a flat surface prevents... Agent: Sughrue Mion, PLLC

20080169571 - Semiconductor device and method for manufacturing the same: A semiconductor device, and a method for manufacturing the semiconductor device, has forming a layer having an in-plane polishing amount distribution, and setting the approximate uniform thickness of the layer over the whole semiconductor wafer by the process such that the in-plane polishing amount distribution is approximately uniform.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080169573 - Circuit substrate and the semiconductor package having the same: The present invention relates to a circuit substrate comprising an upper surface, a first layout area, a second layout area, and a third layout area. The first layout area is on the upper surface, and has a plurality of first electrical contacts. The second layout area is on the upper... Agent: Volentine & Whitt PLLC

20080169574 - Direct die attachment: A method is presented for bare die attachment using conductive ink dots. Dielectric ink dots may be applied, for example as spacer bumps or for attaching. The conductive ink dots are not cured until die and substrate are placed on top of each other, and then cured to form a... Agent: Alston & Bird LLP

20080164452 - Scaled-down phase change memory cell in recessed heater: A semiconductor structure configurable for use as a nonvolatile storage element includes a first electrode, an insulating layer formed on at least a portion of an upper surface of the first electrode, and a pillar traversing the insulating layer and being recessed relative to an upper surface of the insulating... Agent: Ryan, Mason & Lewis, LLP

20080164453 - Uniform critical dimension size pore for pcram application: A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. A via... Agent: Law Office Of Ido Tuchman (yor)

20080164454 - Phase change memory device and method for fabricating the same: A phase change memory device is provided. The phase change memory device includes a substrate with a first electrode layer formed thereon. A first phase change memory structure is on the first electrode layer and electrically connected to the first electrode layer. A second phase change memory structure is on... Agent: Birch Stewart Kolasch & Birch

20080164455 - Programmable non-volatile resistance switching device: A memory element comprises a first number of electrodes and a second number of electrically conducting channels between sub-groups of two of said electrodes, the channels exhibiting an electrical resistance that is reversibly switchable between different states, wherein the first number is larger than two and the second number is... Agent: International Business Machines Corporation

20080164456 - Resistance variable memory device and method of fabrication: Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a resistance variable memory device is provided having at least one tin-chalcogenide layer proximate at least one chalcogenide glass layer. The invention also relates to methods of forming such a... Agent: Dickstein Shapiro LLP

20080164458 - Sapphire substrates and methods of making same: A sapphire substrate includes a generally planar surface having a crystallographic orientation selected from the group consisting of a-plane, r-plane, m-plane, and c-plane orientations, and having a nTTV of not greater than about 0.037 μm/cm2, wherein nTTV is total thickness variation normalized for surface area of the generally planar surface,... Agent: Larson Newman Abel Polansky & White, LLP

20080164457 - Semiconductor light emitting element: s

20080164459 - System and method for using pre-equilibrium ballistic charge carrier refraction: A method and system for using a method of pre-equilibrium ballistic charge carrier refraction comprises fabricating one or more solid-state electric generators. The solid-state electric generators include one or more of a chemically energized solid-state electric generator and a thermionic solid-state electric generator. A first material having a first charge... Agent: Orrick, Herrington & Sutcliffe, LLPIPProsecution Department

20080164465 - Electronic device: The electronic device comprises an organic semiconductor material in a monodomain structure on a substrate. Said semiconductor material is preferably part of a transistor, wherein the monodomain extends on the channel, i.e. from a source to a drain electrode. The material comprises a mesogenic unit with spacer groups and end... Agent: Philips Intellectual Property & Standards

20080164462 - Glass plate with glass frit structure: A light emitting device includes: a first substrate; a second substrate; a light emitting unit interposed between the first substrate and the second substrate; and a sealing material bonding the first substrate to the second substrate and sealing the light emitting unit. The sealing material comprises V+4. In addition, a... Agent: Knobbe Martens Olson & Bear LLP

20080164463 - Manufacturing method of thin film transistor and thin film transistor, and display: A manufacturing method of a thin film transistor made of a stack of an organic semiconductor layer, a gate insulating film and a gate electrode in this order on a substrate, which includes the steps of pattern coating a gate electrode material on the gate insulating film by printing; and... Agent: Sonnenschein Nath & Rosenthal LLP

20080164460 - Organic semiconductor light-emitting device and display using same: An organic semiconductor light-emitting device having the form of a field-effect transistor and a display using this device is provided. In the device, electrons and holes can be transported. The device comprises an organic semiconductor light-emitting layer capable of emitting light by recombination of holes and electrons, a hole injection... Agent: Rabin & Berdo, PC

20080164461 - Organic transistor: An organic transistor comprising source and drain electrodes; a gate electrode; an organic insulating layer between the gate electrode and the source and drain electrodes; and an organic semiconductive region between the insulating layer and the source and drain electrodes; wherein the organic semiconductive region comprises (a) a high mobility... Agent: Marshall, Gerstein & Borun LLP

20080164464 - Semiconductor device: The invention provides a semiconductor device where data can be written after the production and forgery caused by rewriting of data can be prevented, and which can be manufactured at a low cost using a simple structure and an inexpensive material. Further, the invention provides a semiconductor device having the... Agent: Eric Robinson

20080164466 - Light emitting devices with a zinc oxide thin film structure: The present invention relates to a sol-gel deposition/heat treatment process, which consistently produces polycrystalline direct bandgap semiconductor, e.g. ZnO, thin films exhibiting a photo luminescent (PL) spectrum at room temperature that is dominated by a single peak, e.g. in the ultraviolet part of the spectrum, in which the PL intensity... Agent: Teitelbaum & Maclean

20080164467 - Semiconductor light emitting device and its manufacture method: A semiconductor light emitting device manufacture method is provided which can manufacture a semiconductor light emitting device of high quality. A first substrate of an n-type ZnO substrate is prepared. A lamination structure including an optical emission layer made of ZnO based compound semiconductor is formed on the first substrate.... Agent: Masao Yoshimura, Chen Yoshimura, LLP

20080164468 - Reinforced semiconductor structures: Reinforced semiconductor structures are provided. An exemplary embodiment of a reinforced semiconductor structure comprises a semiconductor wafer comprising a plurality of dielectric layers formed thereon. At least one scribe line region is defined over the semiconductor wafer, separating the semiconductor wafer with at least two active regions thereover. A plurality... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080164469 - Semiconductor device with measurement pattern in scribe region: A semiconductor device includes pads disposed in a chip region of a semiconductor substrate and line patterns disposed in a scribe region of the semiconductor substrate and extending toward the pads. The line patterns each have a line-width that is less than a predetermined distance between adjacent pads. Thus, respective... Agent: Law Office Of Monica H Choi

20080164474 - Display device and electronic apparatus: A display device in which variations in luminance due to variations in characteristics of transistors are reduced, and image quality degradation due to variations in resistance values is prevented. The invention comprises a transistor whose channel portion is formed of an amorphous semiconductor or an organic semiconductor, a connecting wiring... Agent: Fish & Richardson P.C.

20080164473 - Highly sensitive photo-sensing element and photo-sensing device using the same: The present invention provides an image display unit integrated with a photo-sensor, comprising a photo-sensing element with high sensitivity and low noise and a polycrystalline silicon TFT prepared at the same time on an insulating substrate using planer process. After a first electrode 11 and a second electrode 12 of... Agent: Stanley P. Fisher Reed Smith Hazel & Thomas LLP

20080164472 - Method of patterning transparent conductive film, thin film transistor substrate using the same and fabricating method thereof: A method of patterning a transparent conductive film adaptive for selectively etching a transparent conductive film without any mask processes, a thin film transistor for a display device using the same and a fabricating method thereof are disclosed. In the method of patterning the transparent conductive film, an inorganic material... Agent: Morgan Lewis & Bockius LLP

20080164470 - Tft array substrate and manufacturing method thereof: A TFT array substrate and a manufacturing method thereof, where the TFT array substrate includes a substrate; a gate line and a gate electrode integrated therewith, which are covered by a gate insulating layer, a semiconductor layer, and a ohmic contact layer sequentially. An insulating layer is formed on the... Agent: Hasse & Nesbitt LLC

20080164471 - Thin film transistor substrate and method of producing the same: A thin film transistor substrate that has reduced production cost and defect rate is presented. The thin film transistor substrate includes a gate wiring line formed on an insulating substrate and including a gate electrode, a data wiring line formed on the gate wiring line and including a source electrode... Agent: Macpherson Kwok Chen & Heid LLP

20080164475 - Method of forming polysilicon, thin film transistor using the polysilicon, and method of fabricating the thin film transistor: A method of forming polysilicon, a thin film transistor (TFT) using the polysilicon, and a method of fabricating the TFT are disclosed. The method of forming the polysilicon comprises: forming an insulating layer on a substrate; forming a first electrode and a second electrode on the insulating layer; forming at... Agent: Robert E. Bushnell

20080164476 - Method of manufacturing p-type zno semiconductor layer using atomic layer deposition and thin film transistor including the p-type zno semiconductor layer: Provided are a method of manufacturing a transparent N-doped p-type ZnO semiconductor layer using a surface chemical reaction between precursors containing elements constituting thin layers, and a thin film transistor (TFT) including the p-type ZnO semiconductor layer. The method includes the steps of: preparing a substrate and loading the substrate... Agent: Ladas & Parry LLP

20080164477 - Thin film transistor, method of fabricating the same, and flat panel display device including the same: A thin film transistor, a method of fabricating the same, and a flat panel display device including the same, are provided. According to the method, low resistance regions and high resistance regions can be manufactured through one doping process. The thin film transistor includes: a substrate; a semiconductor layer disposed... Agent: Christie, Parker & Hale, LLP

20080164478 - Semiconductor device and method of manufacturing the same: In manufacturing a semiconductor device, static electricity is generated while contact holes are formed in an interlayer insulating film by dry etching. Damage to a pixel region or a driving circuit region due to travel of the static electricity generated is prevented. Gate signal lines are spaced apart from each... Agent: Fish & Richardson P.C.

20080164479 - Semiconductor device including poly-si and method of manufacturing the same: A semiconductor device including polysilicon (poly-Si) and method of manufacturing the same are provided. The semiconductor device includes a TaNx material layer and a poly-Si layer formed on the TaNx material layer. The semiconductor device including poly-Si may be manufactured by forming a TaNx material layer and forming a poly-Si... Agent: Harness, Dickey & Pierce, P.L.C

20080164480 - Fabrication of semiconductor devices: A method for fabrication of a semiconductor device on a substrate, the semiconductor having a wafer. The method includes the steps:(a) applying a seed layer of a thermally conductive metal to the wafer; (b) electroplating a relatively thick layer of the conductive metal on the seed layer, and(c) removing the... Agent: Blakely Sokoloff Taylor & Zafman

20080164481 - Image display apparatus with ambient light sensing system: An image display apparatus with an illuminance sensor, where the packaging cost, mechanical reliability due to packaging, and product yield are maintained. In the same semiconductor film as a thin-film-transistor (TFT) consisting of a pixel formed over an insulating substrate constituting a pixel, plural photo-sensors composed of a TFT for... Agent: Stanley P. Fisher Reed Smith LLP

20080164482 - Light-emitting device and method for manufacturing same: In a light emitting apparatus that includes a plurality of semiconductor light emitting devices 2 each having a light emitting face covered with a phosphor layer 3, a semiconductor assembly obtained by assembling a submount and the semiconductor light emitting devices is mounted on the substrate. Accordingly, chromaticity characteristics of... Agent: Wenderoth, Lind & Ponack L.L.P.

20080164483 - Semiconductor device and manufacturing method thereof, and liquid crystal display device: An active matrix substrate includes a glass substrate, a driver portion formed on the glass substrate in a protruding state, a stepped portion formed along a surface of the driver portion and a surface of the glass substrate, an insulating reentrant-angle compensating film formed on a surface of the stepped... Agent: Nixon & Vanderhye, PC

20080164484 - Light emitting apparatus: The present invention provides a light emitting apparatus comprising a three-color light emitting device unit including at least three light emitting diode (LED) chips for respectively emitting red, green and blue light; a white light emitting device unit including at least one blue LED chip with a fluorescent substance formed... Agent: Marger Johnson & Mccollom, P.C.

20080164485 - Light emitting device having a plurality of light emitting cells connected in series and method of fabricating the same: Disclosed are a light emitting device having a plurality of light emitting cells connected in series and a method of fabricating the same. The light emitting device includes a buffer layer formed on a substrate. A plurality of rod-shaped light emitting cells are located on the buffer layer to be... Agent: Marger Johnson & Mccollom, P.C.

20080164486 - Semiconductor light emitting device including gaas substrate and method for manufacturing the same: A semiconductor light emitting device including: a substrate made of GaAs; and a semiconductor layer formed on the substrate, in which part of the substrate on a side opposite to the semiconductor layer is removed by etching so that the semiconductor light emitting device has a thickness of not more... Agent: Rabin & Berdo, PC

20080164487 - Ceramic package for led: A ceramic light emitted diode (LED) package has a pair of discrete reflection walls to reflect light emission from the LED. With two opposite reflection walls and two opposite openings around the LED, light emitted from the LED package can be fanned out.... Agent: Lowe Hauptman Ham & Berner, LLP

20080164488 - Light emitting device and method of fabricating light emitting device: A second electrode (16) formed on a second main surface of a compound semiconductor layer (100) of a light emitting element (1) is arranged in contact with the second main surface of the compound semiconductor layer (100) and has a junction alloying layer (31) for reducing the resistance due to... Agent: Oliff & Berridge, PLC

20080164489 - Metalorganic chemical vapor deposittion (mocvd) growth of high performance non-polar iii-nitride optical devices: A method of device growth and p-contact processing that produces improved performance for non-polar III-nitride light emitting diodes and laser diodes. Key components using a low defect density substrate or template, thick quantum wells, a low temperature p-type III-nitride growth technique, and a transparent conducting oxide for the electrodes.... Agent: Gates & Cooper LLP Howard Hughes Center

20080164490 - Power semiconductor device: The power semiconductor device with a four-layer npnp structure can be turned-off via a gate electrode. The first base layer comprises a cathode base region adjacent to the cathode region and a gate base region adjacent to the gate electrode, but disposed at a distance from the cathode region. The... Agent: Buchanan, Ingersoll & Rooney PC

20080164492 - Process for transferring a layer of strained semiconductor material: A process for preparing a semiconductor wafer with a strained layer having an elevated critical thickness. A first wafer having a strained layer of a semiconductor material on a matching layer is provided, with the semiconductor material having a first lattice parameter corresponding to a relaxed state and a first... Agent: Winston & Strawn LLP Patent Department

20080164491 - Structure and method for mobility enhanced mosfets with unalloyed silicide: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed... Agent: Scully, Scott, Murphy & Presser, P.C.

20080164493 - Structures containing electrodeposited germanium and methods for their fabrication: Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated... Agent: Connolly Bove Lodge & Hutz LLP (for IBM Yorktown)

20080164494 - Bipolar transistor with silicided sub-collector: Embodiments of the invention provide a semiconductor device including a collector in an active region; a first and a second sub-collector, the first sub-collector being a heavily doped semiconductor material adjacent to the collector and the second sub-collector being a silicided sub-collector next to the first sub-collector; and a silicided... Agent: International Business Machines Corporation Dept. 18g

20080164495 - Heterojunction bipolar transistor (hbt) with self-aligned sub-lithographic metal-semiconductor alloy base contacts: A heterojunction bipolar transistor structure with self-aligned sub-lithographic extrinsic base region including a self-aligned metal-semiconductor alloy and self-aligned metal contacts made to the base is disclosed. The lateral dimension of the extrinsic base region is defined by the footprint of a sacrificial spacer, and its thickness is controlled by selective... Agent: Scully, Scott, Murphy & Presser, P.C.

20080164496 - Semiconductor integrated circuit: When dummy patterns are arranged to planarize LSI layout patterns, a plurality of dummy patterns 1 are arranged in a wiring layer in which signal wiring patterns 2 are formed, so as to be inclined at an angle of generally 45 degrees toward the associated signal wiring patterns 2. These... Agent: Mcdermott Will & Emery LLP

20080164497 - Circuit having a power transistor and a drive circuit: A circuit having a power transistor and drive circuit is disclosed. One embodiment provides a drive terminal and a load path. The power transistor is integrated in a first semiconductor body. A first sensor arrangement having a sensor transistor is integrated in the first semiconductor body. The sensor arrangement provides... Agent: Dicke, Billig & Czaja

20080164498 - Forming a semiconductor device having a metal electrode and structure thereof: A method for forming a semiconductor device includes forming a gate dielectric over a substrate, forming a metal electrode over the gate dielectric, forming a first sacrificial layer which includes polysilicon or a metal over the metal electrode, removing the first sacrificial layer, and forming a gate electrode contact over... Agent: Freescale Semiconductor, Inc. Law Department

20080164501 - Image sensor pixel having photodiode with multi-dopant implantation: An active pixel using a photodiode with multiple species of N type dopants is disclosed. The pixel comprises a photodiode formed in a semiconductor substrate. The photodiode is an N− region formed within a P-type region. The N− region is formed from an implant of arsenic and an implant of... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080164499 - Method of manufacturing cmos image sensor: A method of a CMOS image sensor is disclosed. A method of manufacturing a CMOS image sensor includes forming an epi layer formed over a semiconductor substrate including a pixel region and a peripheral region. At least one oxide film may be formed over the epi layer, including the peripheral... Agent: Sherr & Nourse, PLLC

20080164500 - Solid-state image sensing device and camera system using the same: A solid-state image sensing device includes a plurality of pixels. Each pixel has a photodiode, a first transistor, and a second transistor. The photodiode is constituted by a first-conductivity-type semiconductor region and a second-conductivity-type semiconductor region. The first and second conductivity types are opposite to each other. The first transistor... Agent: Fitzpatrick Cella Harper & Scinto

20080164503 - Ferroelectric memory devices having a protruding bottom electrode and methods of forming the same: A ferroelectric memory device and methods of forming the same are provided. Forming a ferroelectric device includes forming an insulation layer over a substrate having a conductive region, forming a bottom electrode electrically connected to the conductive region in the insulation layer, recessing the insulation layer, and forming a ferroelectric... Agent: Myers Bigel Sibley & Sajovec

20080164502 - Magnetic memory and manufacturing method for the same: The present invention to provide a new technique to reduce a variation in switching field of a magnetization free layer in a magnetic memory. The magnetic memory according to the present invention includes a magnetization free layer including a ferromagnetic layer having a shape magnetic anisotropy in a first direction... Agent: Young & Thompson

20080164505 - Metal-oxide-semiconductor field-effect transistor with electrostatic-discharge protection and voltage-stabilizing capacitor and method for manufacturing the same: The present invention relates to a metal-oxide-semiconductor field-effect transistor (MOSFET) with electrostatic-discharge (ESD) protection and a voltage-stabilizing capacitor, and a method for manufacturing the same and is applied to a chip, including a P-type substrate, a conductor layer, a first N-type doping region, a second N-type doping region, and an... Agent: Rosenberg, Klein & Lee

20080164504 - Phase change memory device and method for fabricating the same: A phase change memory device is provided. The phase change memory device comprises a substrate. An electrode layer is on the substrate. A phase change memory structure is on the electrode layer and electrically connected to the electrode layer, wherein the phase change memory structure comprises a cup-shaped heating electrode... Agent: Quintero Law Office, PC

20080164506 - Pn junction and mos capacitor hybrid resurf transistor: A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate; a source region and a drain region provided in the substrate; wherein the source region and the drain region are laterally spaced from each other; and... Agent: Hiscock & Barclay, LLP

20080164507 - Area-efficient gated diode structure and method of forming same: An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface thereof, and at least one trench electrode extending vertically through the active region and at least partially into the semiconductor... Agent: Ryan, Mason & Lewis, LLP

20080164508 - Memory devices and methods of manufacturing the same: The memory device includes a first tunnel insulation layer pattern on a semiconductor substrate, a second tunnel insulation layer pattern having an energy band gap lower than that of the first tunnel insulation layer pattern on the first tunnel insulation layer pattern, a charge trapping layer pattern on the second... Agent: F. Chau & Associates, LLC

20080164509 - Nonvolatile memory devices and methods of forming the same: A nonvolatile memory device includes a semiconductor substrate of a first conductivity type, a plurality of word lines on the semiconductor substrate, each the plurality of word lines including a floating gate of a second conductivity type. A ground select line and a string select line are disposed on respective... Agent: Myers Bigel Sibley & Sajovec

20080164510 - Semiconductor memory devices performing erase operation using erase gate and methods of manufacturing the same: A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one... Agent: Harness, Dickey & Pierce, P.L.C

20080164511 - Semiconductor device: A semiconductor device having spacer patterns formed at the sidewalls of gate electrodes and a method of fabricating the same are disclosed. The semiconductor device includes a gate pattern, including a plurality of gate electrodes, formed on a semiconductor substrate, a barrier insulation layer formed on the entire surface of... Agent: Sherr & Nourse, PLLC

20080164512 - Light erasable memory and method therefor: A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a... Agent: Freescale Semiconductor, Inc. Law Department

20080164513 - Non-volatile semiconductor memory device and a method of fabricating a non-volatile semiconductor memory device: The present invention relates to a memory device and a method of fabricating the same. The memory device comprises a substrate, a tunnel dielectric film on the substrate, pairs of source and drain regions formed in the substrate, and a number of separate storage blocks between each pair of the... Agent: Akin Gump LLP - Silicon Valley

20080164514 - Semiconductor device having three-demensional transistor and manufacturing method thereof: A semiconductor device includes an active region surrounded by an element isolation region; a gate electrode crossing the active region; and at least one slit provided at a boundary portion between the element isolation region and the active region and having a first region covered with the gate electrode and... Agent: Mcginn Intellectual Property Law Group, PLLC

20080164515 - High-density power mosfet with planarized metalization: A method for producing a power MOSFET. The method includes fabricating a plurality of layers of a power MOSFET to produce an upper surface active area and performing a chemical mechanical polishing process on the active area to produce a substantially planar surface. A metalization deposition process is then performed... Agent: Wagner, Murabito & Hao LLP Third Floor

20080164516 - Semiconductor device: A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor device also includes a body layer extending a first predetermined distance into the semiconductor layer of the second conductivity type and a pair of trenches... Agent: Townsend And Townsend And Crew, LLP

20080164517 - Semiconductor device and method for making the same: A semiconductor device according to the present invention includes: a first trench that is formed in a semiconductor substrate; a gate oxide film that is formed on a surface of the first trench; and a trench gate electrode that is formed so as to bury the first trench via the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080164519 - Power device with trenches having wider upper portion than lower portion: In accordance with an embodiment of the present invention, a FET is formed as follows. An exposed surface area of a silicon layer where silicon can be removed is defined. A portion of the silicon layer is removed to form a middle section of a trench extending into the silicon... Agent: Townsend And Townsend And Crew, LLP

20080164518 - Semiconductor device: A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and... Agent: Townsend And Townsend And Crew, LLP

20080164520 - Semiconductor device: A semiconductor device includes a semiconductor layer of a first conductivity type having a first surface and a second surface, a source region disposed on the first surface, a gate region disposed on the first surface adjacent the source region, and a drain region disposed on the first surface. The... Agent: Townsend And Townsend And Crew, LLP

20080164521 - Process for high voltage superjunction termination: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is... Agent: Panitch Schwarze Belisario & Nadel LLP

20080164522 - Semiconductor device and manufacturing method thereof: To provide a semiconductor device that has a three dimensional gate dielectric film, is easily manufactured, and a gate structure thereof can be easily miniaturize. A semiconductor device comprises: a three-dimensional gate dielectric film formed on a semiconductor substrate; a gate electrode that contacts the gate dielectric film and protrudes... Agent: Mcginn Intellectual Property Law Group, PLLC

20080164523 - Dynamic random access memory cell and manufacturing method thereof: A dynamic random access memory cell and a manufacturing method thereof are provided. First, a substrate on which a bottom oxide layer and a semiconductor layer are formed is provided. The semiconductor layer is formed on the bottom oxide layer. Next, a gate is formed on the semiconductor layer. Then,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080164524 - Optical mask employed for manufacturing array substrate, array substrate and method for manufacturing the same: The invention provides wiring, which can form or disconnect freely the adjacent exposure regions by employing the same optical mask under a condition that a plurality of array substrates are produced on one mother glass substrate; and an optical mask, which can be inspected by utilizing the same probe device... Agent: Nields & Lemack

20080164525 - Structure and method for mosfet gate electrode landing pad: A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080164526 - Method of trimming a hard mask layer, method for fabricating a gate in a mos transistor, and a stack for fabricating a gate in a mos transistor: A method of trimming hard mask is provided. The method includes providing a substrate, a hard mask layer, and a tri-layer stack on the substrate. The tri-layer stack includes a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer. The top photo resist layer,... Agent: North America Intellectual Property Corporation

20080164527 - Semiconductor device and method of manufacturing the same: The semiconductor comprises a channel layer including GaN, a barrier layer formed by laminating a first layer including AlXGa1-XN (0.05≦X≦0.25) and a second layer including AlYGa1-YN (0.20≦Y≦0.28, X<Y), source and drain electrodes provided spaced apart from each other on the barrier layer, and a gate electrode provided on the bottom... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080164528 - Self-aligned metal-semiconductor alloy and metallization for sub-lithographic source and drain contacts: A lateral double-gate FET structure with sub-lithographic source and drain regions is disclosed. The sub-lithographic source and drain regions are defined by a sacrificial spacer. Self-aligned metal-semiconductor alloy and metal contacts are made to the sub-lithographic source and drain using conventional silicon processing.... Agent: Scully, Scott, Murphy & Presser, P.C.

20080164531 - Dual interlayer dielectric stressor integration with a sacrificial underlayer film stack: A method for making a semiconductor device is provided by (a) providing a substrate (203) having first (205) and second (207) gate structures thereon; (b) forming an underlayer (231) over the first and second gate structures; (c) removing the underlayer from the first gate structure; (d) forming a first stressor... Agent: Fortkort & Houston P.C.

20080164532 - Embedded stressed nitride liners for cmos performance improvement: The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying... Agent: Scully, Scott, Murphy & Presser, P.C.

20080164530 - Integrated circuits with stress memory effect and fabrication methods thereof: Semiconductor devices with selective stress memory effect and fabrication methods thereof. The semiconductor device comprises a semiconductor substrate with a first region and a second region. Both the first region and the second region have a first doped region and a second doped region separated by an insulation layer. A... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080164529 - Semiconductor device and manufacturing method thereof: A semiconductor device having dual fully-silicided gate is provided, which includes a first transistor, a second transistor, a dielectric layer, and an interlayer insulating layer. The first transistor is disposed on the substrate, which includes a first silicided gate and a first source/drain. The second transistor is disposed on the... Agent: J C Patents, Inc.

20080164533 - Method of manufacturing a germanosilicide and a semiconductor device having the germanosilicide: Example embodiments relate to a method of manufacturing a germanosilicide and a semiconductor device having the germanosilicide. A method according to example embodiments may include providing a substrate having at least a portion formed of silicon germanium. A metal layer may be formed on the silicon germanium. A thermal process... Agent: Harness, Dickey & Pierce, P.L.C

20080164534 - Self-aligned contacts to source/drain regions: In some embodiments, when etching a dielectric to form a self-aligned contact opening to a source/drain region (160) of a transistor, the gate structure (220) is protected on top with a non-conformal layer (M3), possibly silicon, deposited so that it is thicker over the gate than over the source/drain region.... Agent: Macpherson Kwok Chen & Heid LLP

20080164535 - Curved finfets: A method of forming a transistor patterns a semiconductor fin on a substrate, such that the fin extends from the substrate. Then, the method forms a gate conductor over a central portion of the fin, leaving end portions of the fin exposed. Next, the end portions of the fin are... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080164536 - Transistors and methods of manufacture thereof: Transistors and methods of manufacture thereof are disclosed. A workpiece is provided, a gate dielectric is formed over the workpiece, and a gate is formed over the gate dielectric by exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (Si). The gate may comprise a... Agent: Slater & Matsil LLP

20080164537 - Integrated complementary low voltage rf-ldmos: Complementary RF LDMOS transistors have gate electrodes over split gate oxides. A source spacer of a second conductivity type extends laterally from the source tap of a first conductivity type to approximately the edge of the gate electrode above the thinnest gate oxide. A body of a first conductivity type... Agent: Hiscock & Barclay, LLP

20080164538 - Nitride read-only memory cell and method of manufacturing the same: A nitride read-only memory cell and a method of manufacturing the same are provided. First, a substrate is provided, and a first oxide layer is formed on the substrate. Next, a nitride layer is deposited on the first oxide layer via a first gas and a second gas. The flow... Agent: Bacon & Thomas, PLLC

20080164539 - Use of f-based gate etch to passivate the high-k/metal gate stack for deep submicron transistor technologies: A new, effective and cost-efficient method of introducing Fluorine into Hf-based dielectric gate stacks of planar or multi-gate devices (MuGFET), resulting in a significant improvement in both Negative and Positive Bias Temperature Instabilities (NBTI and PBTI) is provided. The new method uses an SF6 based metal gate etch chemistry for... Agent: Knobbe Martens Olson & Bear LLP

20080164540 - Method and apparatus for forming nickel silicide with low defect density in fet devices: A method and an apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is formed in the interior... Agent: International Business Machines Corporation Dept. 18g

20080164541 - Sensor platform using a non-horizontally oriented nanotube element: Sensor platforms and methods of making them are described. A platform having a non-horizontally oriented sensor element comprising one or more nanostructures such as nanotubes is described. Under certain embodiments, a sensor element has or is made to have an affinity for an analyte. Under certain embodiments, such a sensor... Agent: Wilmerhale/boston

20080164542 - Methods and systems for wafer level packaging of mems structures: A method of forming a package for a MEMS structure coupled to a substrate includes depositing an encapsulant material on the substrate and patterning the encapsulant material to form a plurality of encapsulated structures. The method also includes depositing a first capping layer on the substrate and forming one or... Agent: Townsend And Townsend And Crew, LLP

20080164543 - Package, in particular for mems devices and method of making same: A package includes a substrate provided with a passing opening and a MEMS device. The MEMS device includes an active surface wherein a portion of the MEMS device is integrated sensitive to the chemical/physical variations of a fluid. The active surface of the MEMS device faces the substrate and is... Agent: Stmicroelectronics, Inc.

20080164544 - Packaging for an interferometric modulator with a curved back plate: A package is made of a transparent substrate having an interferometric modulator and a back plate. A non-hermetic seal joins the back plate to the substrate to form a package, and a desiccant resides inside the package. A method of packaging an interferometric modulator includes providing a transparent substrate and... Agent: Knobbe, Martens, Olson & Bear, LLP

20080164545 - Mems microphone package and method thereof: A MEMS microphone package includes a carrier, an application specific IC, an encapsulant and a microphone chip. The application specific IC and the microphone chip are respectively disposed on first and second surfaces of the carrier, and the application specific IC and the microphone chip are electrically connected to the... Agent: North America Intellectual Property Corporation

20080164546 - Design of mems packaging: A micro-electromechanical device comprises a micro-electromechanical die, a package, and three pillars attaching the micro-electromechanical die to the package, at least one of the shape, position and orientation of the pillars is configured such that any strain transferred from the package to the die by deformation of the package is... Agent: Edell, Shapiro & Finnan, LLC

20080164548 - Low resistance high-tmr magnetic tunnel junction and process for fabrication thereof: One embodiment of the present invention includes a non-volatile magnetic memory element including a fixed layer, a barrier layer formed on top of the fixed layer, and a free layer formed on top of the barrier layer, wherein the electrical resistivity of the barrier layer is reduced by placing said... Agent: Law Offices Of Imam

20080164547 - Storage element and memory: A storage element includes a storage layer configured to hold information by use of a magnetization state of a magnetic material, with a pinned magnetization layer being provided on one side of the storage layer, with a tunnel insulation layer, and with the direction of magnetization of the storage layer... Agent: Sonnenschein Nath & Rosenthal LLP

20080164549 - Low dark current pixel with a guard drive active photodiode: A method and apparatus for reducing thermally generated dark current in a CMOS imaging device is disclosed. A photodiode within the imaging device is kept zero-biased, so that the voltage is equal at both ends of the photodiode. This zero-biasing is accomplished using several different techniques, including, alternatively: a transistor... Agent: Dickstein Shapiro LLP

20080164552 - Cmos image sensor: Embodiments relate to a CMOS image sensor and to a method for manufacturing a CMOS image sensor that may disperse stray beam between microlenses. According to embodiments, the method for manufacturing the CMOS image may include forming an interlayer dielectric layer on a semiconductor substrate including a plurality of photo... Agent: Sherr & Nourse, PLLC

20080164550 - Electronic assembly for image sensor device and fabrication method thereof: A package module for an image sensor device is disclosed. The package module comprises a device chip disposed between lower and upper substrates. A first conductive layer is over a first sidewall of the lower substrate and insulated from the device chip. A first protective layer is on the first... Agent: Joe Mckinney Muncy

20080164551 - Image sensor: Embodiments relate to an image sensor, and for directly manufacturing microlenses on color filter layers without forming a separate planarization layer, by forming the color filter layers having a relatively even step. According to embodiments, a method may include forming an interlayer dielectric layer on a semiconductor substrate formed with... Agent: Sherr & Nourse, PLLC

20080164553 - Isolation structures for cmos image sensor chip scale packages: Isolation structure for CMOS image sensor device chip scale packages and fabrication methods thereof. A CMOS image sensor chip scale package includes a transparent substrate configured as a support structure for the package. The transparent substrate includes a first cutting edge and a second cutting edge. A CMOS image sensor... Agent: Joe Mckinney Muncy

20080164554 - Apparatus comprising an avalanche photodiode: Avalanche photodiodes are provided, wherein the APDs provide both high optical coupling efficiency and low dark count rate. The APDs are formed such that their cap layer has an active region of sufficient width to enable high optical coupling efficiency but the APD still exhibits a low dark count rate.... Agent: Demont & Breyer, LLC

20080164555 - Apparatus comprising an avalanche photodiode: Avalanche photodiodes are provided, wherein the APDs provide both high optical coupling efficiency and low dark count rate. The APDs are formed such that their cap layer has an active region of sufficient width to enable high optical coupling efficiency but the APD still exhibits a low dark count rate.... Agent: Demont & Breyer, LLC

20080164556 - Semiconductor device: There is a problem that a reverse off-leak current becomes too large in a Schottky barrier diode. A semiconductor device of the present invention includes P-type first and second anode diffusion layers formed in an N-type epitaxial layer, N-type cathode diffusion layers formed in the epitaxial layer, a P-type third... Agent: Morrison & Foerster LLP

20080164557 - Semiconductor device and method of forming the same: There are provided a semiconductor device and a method of forming the same. The semiconductor device may include a semiconductor substrate including a digital circuit region and an analog circuit region, a device isolation layer on the boundary between the digital circuit region and the analog circuit region, a conductive... Agent: Harness, Dickey & Pierce, P.L.C

20080164559 - Integrated assist features for epitaxial growth: A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of... Agent: Fortkort & Houston P.C.

20080164558 - Method for fabricating shallow trench isolation structures using diblock copolymer patterning: A method of isolating semiconductor devices formed on a semiconductor substrate having a silicon on insulator (SOI) layer is provided. The method includes forming at least one shallow trench area on a pad nitride layer deposited on a surface of the SOI layer, wherein the at least one shallow trench... Agent: International Business Machines Corporation Dept. 18g

20080164560 - Planar oxidation method for producing a localised buried insulator: The invention relates to a method of producing a semiconductor device, comprising the following steps consisting in: forming first, second and third semiconductor layers (1, 2, 3), whereby the first and second layers (1, 3) contain a smaller concentration of oxidisable species than the second layer (2); forming a mask... Agent: Foley And Lardner LLP Suite 500

20080164561 - Shallow trench isolation process utilizing differential liners: A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.... Agent: Amd-mke C/o Foley Lardner LLP

20080164562 - Substrate with embedded passive element and methods for manufacturing the same: A substrate with an embedded passive element and methods for manufacturing the same are provided, wherein the substrate includes an interlayer circuit board having a first conductive circuit, a dielectric layer, a first electrode, a second electrode, and a second conductive circuit. The dielectric layer formed on the interlayer circuit... Agent: Volentine & Whitt PLLC

20080164566 - Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation of a semiconductor device, semiconductor devices, and systems including same: A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then formed in the... Agent: Micron Technology, Inc.

20080164564 - Micromechanical component having integrated passive electronic components and method for its production: A micromechanical component includes a substrate, on which at least one layer sequence is situated, which includes at least one micromechanical functional element, and on which at least one layer sequence is situated that is able to act as at least one macroelectronic, passive component.... Agent: Kenyon & Kenyon LLP

20080164565 - Semiconductor device and method of manufacturing the same: The semiconductor device according to the present invention includes a lower electrode made of a metallic material, a capacitance film made of an insulating material and laminated on the lower electrode, an upper electrode made of a metallic material, opposed to the lower electrode through the capacitance film, and having... Agent: Rabin & Berdo, PC

20080164563 - Thin film capacitor and manufacturing method therefor: A thin film capacitor including a substrate, a capacitor portion having an upper conductor, a lower conductor, and a dielectric thin film, and a resin protective layer for protecting the capacitor portion. A barrier layer is interposed between the capacitor portion and the resin protective layer. The barrier layer includes... Agent: Dickstein Shapiro LLP

20080164567 - Band gap reference supply using nanotubes: A current and/or voltage band gap reference circuit includes a current mirror circuit having first, second and third current outputs, a first resistive element, and first and second nanotube transistors. The nanotube diameter of the first transistor is different to the nanotube diameter of the second transistor, allowing variable band-gaps... Agent: Motorola, Inc.

20080164568 - Resistance random access memory and method of manufacturing the same: Provided are a resistance random access memory including a resistance layer having a metal oxide and/or a metal ion dopant, which may be deposited at room temperature and which may have variable resistance characteristics, and a method of manufacturing the same.... Agent: Harness, Dickey & Pierce, P.L.C

20080164569 - Terbium-doped, silicon-rich oxide electroluminescent devices and method of making the same: A method of fabricating an electroluminescent device includes, on a prepared substrate, depositing a rare earth-doped silicon-rich layer on gate oxide layer as a light emitting layer; and annealing and oxidizing the structure to repair any damage caused to the rare earth-doped silicon-rich layer; and incorporating the electroluminescent device into... Agent: David C. Ripma Sharp Laboratories Of America, Inc.

20080164570 - Zirconium and hafnium boride alloy templates on silicon for nitride integration applications: Semiconductor structures are provided comprising a substrate and a epitaxial layer formed over the substrate, wherein the epitaxial layer comprises B; and one or more element selected from the group consisting of Zr, Hf and Al and has a thickness greater than 50 nm. Further, methods for integrating Group III... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080164571 - Electronic components produced by a method of separating two layers of material from one another: A semiconductor body selected from the group consisting of a semiconductor layer, a semiconductor layer sequence or a semiconductor layer structure. The semiconductor body is transferred from a growth substrate to a support material by: exposing an interface between the growth substrate and the semiconductor body or a region in... Agent: Thomas Langer, Esq. Cohen, Pontani, Lieberman & Pavane

20080164572 - Semiconductor substrate and manufacturing method thereof: A semiconductor substrate whose surface roughness is reduced by optimizing an inclination (off angle) with respect to a {110} surface of the semiconductor substrate surface and a manufacturing method thereof are provided. The surface of the semiconductor substrate has the inclination (off angle) of 0 degree or more and 0.12... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080164574 - Integrated circuits with conductive features in through holes passing through other conductive features and through a semiconductor substrate: A backside contact pad is formed in an integrated circuit, possibly designed initially with just top side contact pads (150C), by forming an opening (220) through a top side contact pad (150C) and the semiconductor substrate (110). Conductive material (520, 540, 1110, 1130) is formed in the opening and in... Agent: Macpherson Kwok Chen & Heid LLP

20080164573 - Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density: Methods are provided for fabricating silicon carriers with conductive through-vias that allow high-yield manufacture of silicon carrier with, low defect density. In particular, methods are provided which enable fabrication of silicon, carries with via diameters such as 1 to 10 microns in diameter for a vertical thickness of less than... Agent: Frank Chau, Esg. F. Chau & Associates, LLC

20080164575 - Method for manufacturing a three-dimensional semiconductor device and a wafer used therein: A method for manufacturing a semiconductor device includes the steps of forming first and second semiconductor wafers each including an array of chips and elongate electrodes, forming a groove on scribe lines separating the chips from one another; coating a surface of one of the semiconductor wafers with adhesive; bonding... Agent: Young & Thompson

20080164576 - Process for manufacturing a microelectromechanical interaction system for a storage medium: A process for manufacturing an interaction system of a microelectromechanical type for a storage medium, the interaction system provided with a supporting element and an interaction element carried by the supporting element, envisages the steps of: providing a wafer of semiconductor material having a substrate with a first type of... Agent: Seed Intellectual Property Law Group PLLC

20080164577 - Patterned silicon submicron tubes: An array of submicron silicon (Si) tubes is provided with a method for patterning submicron Si tubes. The method provides a Si substrate, and forms a silicon dioxide film overlying the Si substrate. An array of silicon dioxide rods is formed from the silicon dioxide film, and Si3N4 tubes are... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080164578 - Sapphire substrates and methods of making same: A sapphire substrate includes a generally planar surface having a crystallographic orientation selected from the group consisting of a-plane, r-plane, m-plane, and c-plane orientations, and having a nTTV of not greater than about 0.037 μm/cm2, wherein nTTV is total thickness variation normalized for surface area of the generally planar surface,... Agent: Larson Newman Abel Polansky & White, LLP

20080164580 - Chemical vapor deposition method for the incorporation of nitrogen into materials including germanium and antimony: A chemical vapor deposition (CVD) method for depositing materials including germanium (Ge), antimony (Sb) and nitrogen (N) which, in some embodiments, has the ability to fill high aspect ratio openings is provided. The CVD method of the instant invention permits for the control of nitrogen-doped GeSb stoichiometry over a wide... Agent: Scully, Scott, Murphy & Presser, P.C.

20080164579 - Process for chemical vapor deposition of materials with via filling capability and structure formed thereby: A chemical vapor deposition (CVD) method for depositing materials including germanium (Ge) and antimony (Sb) which, in some embodiments, has the ability to fill high aspect ratio openings is provided. The CVD method of the instant invention permits for the control of GeSb stoichiometry over a wide range of values... Agent: Scully, Scott, Murphy & Presser, P.C.

20080164581 - Electronic device and process for manufacturing the same: An electronic device and a process for manufacturing the same are disclosed. In one aspect, the device comprises an electrode comprising a metal compound selected from the group of tantalum carbide, tantalum carbonitride, hafnium carbide and hafnium carbonitride. The device further comprises a high-k dielectric layer of a hafnium oxide... Agent: Knobbe Martens Olson & Bear LLP

20080164582 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a semiconductor device includes providing a workpiece, and forming a dielectric layer over the workpiece. The dielectric layer comprises a crystalline phase. The method includes forming an electrode material over the dielectric layer.... Agent: Slater & Matsil LLP

20080164583 - Chip package capable of minimizing electro-magnetic interference: A cap package includes a substrate on which a chip is mounted. A cap is made of silicon doped with non-metal dopant. The cap is capped on the substrate to define with the substrate an accommodation chamber that receives the chip inside. The chip is electrically connected with a conducting... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080164584 - Method and structure for reduction of soft error rates in integrated circuits: A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the... Agent: Schmeiser, Olsen & Watts

20080164585 - Semiconductor device: A semiconductor device is mounted on a package substrate which has a power supply line and a signal line formed of a normal or predetermined resistance material layer on a dielectric layer. A resistance material layer has a high resistance as compared with the normal resistance material layer and is... Agent: Young & Thompson

20080164586 - Thin semiconductor package having stackable lead frame and method of manufacturing the same: Provided is a thin semiconductor package comprising a semiconductor chip and a lead frame, the lead frame including a paddle portion configured for mounting the semiconductor chip in a manner that exposes bonding pads within an aperture formed in a center portion of the lead frame and a peripheral terminal... Agent: Harness, Dickey & Pierce, P.L.C

20080164587 - Molding compound flow controller: A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate... Agent: Klarquist Sparkman, LLP

20080164588 - High power semiconductor package: Provided is a high power semiconductor package including: an insulation substrate having first and second surfaces opposite to each other; an interconnection patterns formed on the first surface of the insulation substrate, the interconnection patterns including a plurality of first dimples; a power control semiconductor chip mounted on the first... Agent: Hiscock & Barclay, LLP

20080164589 - Power device package comprising metal tab die attach paddle (dap) and method of fabricating the package: A metal tab die attach paddle (DAP) disposed between the lead frame and a power device die in a power device package reduces the stress exerted on the semiconductor power device die caused by the different coefficients of thermal expansion (CTE) of the semiconductor power device die and the lead... Agent: Hiscock & Barclay, LLP

20080164590 - Semiconductor power device: In one embodiment the present invention includes a semiconductor power device. The semiconductor power device includes a single gauge lead frame, a semiconductor die, and a heat sink. The semiconductor die is attached to a first level of the lead frame. The heat sink is attached to a second level... Agent: Fountainhead Law Group PC

20080164591 - Microelectronic component assemblies with recessed wire bonds and methods of making same: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, a substrate, and at least one bond wire. The substrate has a reduced-thickness base adjacent terminals of the microelectronic component and a... Agent: Perkins Coie LLP Patent-sea

20080164592 - Apparatus and method for housing micromechanical systems: An apparatus for housing a micromechanical system includes a substrate with a surface on which the micromechanical system is formed, a transparent cover and a dry film layer arrangement between the surface of the substrate and the transparent cover. The dry film layer arrangement has an opening, so that the... Agent: Schoppe, Zimmerman , Stockeller & Zinkler

20080164593 - Method of packaging semiconductor devices: A method of packaging a semiconductor includes providing a support structure. An adhesive layer is formed overlying the support structure and is in contact with the support structure. A plurality of semiconductor die is placed on the adhesive layer. The semiconductor die are laterally separated from each other and have... Agent: Freescale Semiconductor, Inc. Law Department

20080164594 - Cap package for micro electro-mechanical system: A cap package for MEMS includes a substrate having a connection zone that is grounded, a chip mounted on the substrate, a cap capped on the substrate and provided with a through hole corresponding to the chip, and a conducting glue made of a non-metal material having a resistivity smaller... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080164596 - Semiconductor package, manufacturing method thereof and ic chip: A package may include a lower unit package and an upper unit package. Each of the unit packages may include a circuit substrate having a lower surface and an upper surface. Wire bonding pads may be provided of the lower surface of the circuit substrate, and chip bonding pads may... Agent: Harness, Dickey & Pierce, P.L.C

20080164595 - Stackable semiconductor package and the method for making the same: The present invention relates to a stackable semiconductor package and the method for making the same. The stackable semiconductor package comprises a first substrate, a semiconductor device, a plurality of stud bumps, a plurality of first wires, a second substrate, and a molding compound. The semiconductor device is disposed on... Agent: Volentine & Whitt PLLC

20080164597 - Plate structure having chip embedded therein and the manufacturing method of the same: A plate structure having a chip embedded therein, comprises an aluminum plate having at least one aluminum oxide layer formed on its surface, and a cavity therein; a chip embedded in the cavity, wherein the chip has an active surface; at least one electrode pad mounted on the active surface;... Agent: Bacon & Thomas, PLLC

20080164598 - Semiconductor module: A module includes a semiconductor chip, which has at least one movable element, a first substrate of a glass material or semiconductor material, which covers a first main surface of the semiconductor chip, and a second substrate of a glass material or semiconductor material, which covers a second main surface... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080164599 - Semiconductor module: A module (100) is described having a semiconductor chip (1) which has at least one contact pad (2). A first dielectric layer (3), which contains a fluorocarbon compound, as well as a first wiring layer (4) are applied to the semiconductor chip (1).... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080164600 - Ball grid array structures having tape-based circuitry: Semiconductor device packages formed in accordance with methods of packaging semiconductor dice in grid array-type semiconductor device packages using conventional lead frame or lead lock tape assembly equipment are disclosed. Circuitry-bearing structure having an electrically insulating layer that carries redistribution electrical connections having redistributed bond pads and conductive traces and... Agent: Trask Britt, P.C./ Micron Technology

20080164601 - Chip package structure: A chip package structure includes a circuit substrate, a chip, an adhesive layer, conductive wires, and a molding compound. The circuit substrate has a first, a second surface, a slot, and a solder mask layer disposed on the first surface. The solder mask layer has a first and a second... Agent: Jianq Chyun Intellectual Property Office

20080164602 - Cap package for micro electro-mechanical system capable of minimizing electro-magnetic interference: A cap package for MEMS includes a substrate, a cap made of a carbon added plastic material and capped on the substrate to define with the substrate an accommodation chamber, and a chip mounted on the substrate and located inside the accommodation chamber. The substrate has a conducting portion electrically... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080164603 - Method and apparatus for providing thermal management on high-power integrated circuit devices: An apparatus for providing thermal management on high-power integrated circuit devices is disclosed. Initially, contacts to active devices are formed. Phase change materials are then applied over potential hot spots that can be formed by the active devices. A layer of high-thermally conductive materials is deposited over the phase change... Agent: Dillon & Yudell LLP

20080164604 - Heat dissipating semiconductor package: A heat dissipating semiconductor package is disclosed, including a chip carrier; at least a semiconductor chip mounted and electrically connected to the chip carrier; and a heat dissipating member mounted on the semiconductor chip with a thermal interface material (TIM) interposed therebetween, wherein the TIM is provided with a plurality... Agent: Edwards Angell, Palmer & Dodge LLP

20080164605 - Multi-chip package: A multi-chip package including a substrate, a first chip, a plurality of conductive bodies, a second chip, and a plurality of conductive studs is provided. The substrate has a first surface. The first chip disposed on the first surface has a first orthogonal projection on the first surface. The conductive... Agent: J C Patents, Inc.

20080164606 - Spacers for wafer bonding: A deformable spacer for wafer bonding applications is disclosed. The spacer may be used to keep wafers separated until desired conditions are achieved.... Agent: Fish & Richardson P.C.

20080164607 - Electric power converter and mounting structure of semiconductor device: An electric power converter has a main circuit section including a semiconductor module and a cooling device; a control circuit substrate section electrically connected to a signal terminal of the semiconductor module, and having a control circuit; and a power wiring section connected to a main electrode terminal of the... Agent: Oliff & Berridge, PLC

20080164608 - Semiconductor device and method for producing the same: A semiconductor device includes a tape carrier substrate having a flexible insulating film base, a plurality of conductor wirings provided on the film base, and wiring bumps respectively formed so as to cover an upper surface and both side surfaces of the conductor wirings, and a semiconductor chip mounted on... Agent: Hamre, Schumann, Mueller & Larson P.C.

20080164609 - Injection molded solder ball method: Methods for making solder balls, which can be used to bump semiconductor wafers are disclosed. Methods for bumping semiconductor wafers with the solder balls are also disclosed. The solder balls can be made using an injection molded soldering (IMS) process.... Agent: Connolly Bove Lodge & Hutz LLP (for IBM Yorktown)

20080164610 - Substrate improving immobilization of ball pads for bga packages: A substrate improving immobilization of ball pads for BGA packages mainly comprises a substrate core, a plurality of ball pads and a solder resist layer. Each of the ball pads has a metal pad and at least a metal nail. The metal pads are adhered on a surface of the... Agent: Troxell Law Office PLLC

20080164611 - Method for making an integrated circuit having a via hole: An integrated circuit and a method for making an integrated circuit is disclosed. In one embodiment, at least one contact of an electrically conductive material is formed on a substrate. A layer is disposed on the substrate to a predetermined height of the contact. An electrically conductive via hole is... Agent: Dicke, Billig & Czaja

20080164612 - Highly conductive composition for wafer coating: A conductive composition for coating a semiconductor wafer comprises conductive filler that has an average particle size of less than 2 microns and a maximum particle size of less than 10 microns, a first resin that has a softening point between 80-260° C., solvent, curing agent, and a second resin,... Agent: National Starch And Chemical Company

20080164613 - Ultra-thin cu alloy seed for interconnect application: A copper interconnection structure which is electroplated onto a silicon layer or semiconductor substrate. The structure includes an ultra-thin copper seed alloy incorporating selectively minor amounts of a dopant material to facilitate a continuous deposition thereof onto the silicon layer or semiconductor substrate. The copper seed alloy may contain dopant... Agent: Scully, Scott, Murphy & Presser, P.C.

20080164614 - Semiconductor device: A semiconductor device including at least two layers of interlayer-insulator-films stacked above a substrate and at least partially formed by a low-relative-dielectric-constant-film having a relative-dielectric-constant of 3.4 or less respectively, a plurality of wirings provided at least one within each of the interlayer-insulator-film and at least partially located within the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080164615 - Connection between an i/o region and the core region of an integrated circuit: A connection between a first circuit within an I/O region of an integrated circuit chip and a second circuit within a core region of the chip. The first circuit is connected to a bonding pad through a first conductor in a first layer of an I/O region. The second circuit... Agent: Robert J. Stern

20080164616 - Strip conductor structure for minimizing thermomechanical loads: A semiconductor chip device including a surface on which at least one electrical contact surface is provided. A foil from an electrically insulating material is applied, especially by vacuum, to the surface and rests closely to the surface and adheres to the surface. The foil, in the area of the... Agent: Harness, Dickey & Pierce, P.L.C

20080164617 - Method of forming vertical contacts in integrated circuits: A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion... Agent: Michael L.wise Ryan, Mason & Lewis, LLP

20080164619 - Semiconductor chip package and method of manufacturing the same: Provided are a semiconductor chip package and a method of manufacturing the semiconductor package. The semiconductor chip package may include at least one semiconductor chip, whose upper surface includes a plurality of electrode pads on a substrate including a conductive pattern, and the conductive pattern and the electrode pads of... Agent: Harness, Dickey & Pierce, P.L.C

20080164618 - Semiconductor package system with die carrier having mold flow restricting elements: A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate... Agent: Klarquist Sparkman, LLP

20080164620 - Multi-chip package and method of fabricating the same: A multi-chip package including a carrier, at least one first chip, and a second chip is provided. The first chip is electrically connected to the carrier and disposed on the carrier. The second chip is electrically connected to the first chip and the carrier. A part of the second chip... Agent: J C Patents, Inc.

20080164621 - Electric power semiconductor device: An electric power semiconductor device including first and second circuit patterns formed on main surfaces of first and second insulating substrates, respectively, first and second semiconductor chips mounted on the first and second circuit patterns, respectively, a multilayer electrode plate assembly disposed between the first and second insulating substrates, having... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080164622 - Wiring board: A difference in delay of signal transmission due to the wiring within a board is minimized. A wiring board includes wiring for connecting terminals included in one of a plurality of semiconductor chips to terminals included in another one of the plurality of semiconductor chips, through branch points. Each of... Agent: Mcginn Intellectual Property Law Group, PLLC

20080164623 - Wafer, semiconductor device, and fabrication methods therefor: In order to fabricate a semiconductor device that can perform at its full capacity, in which (i) a single-crystal silicon integrated circuit is formed on an insulating substrate without an adhesive agent, and (ii) an active region of the single-crystal integrated circuit is not damaged by implantation of hydrogen ions,... Agent: Nixon & Vanderhye, PC

20080157050 - Phase-change memory and fabrication method thereof: A phase-change memory and fabrication method thereof. The phase-change memory comprises a transistor, and a phase-change material layer. In particular, the phase-change material layer is directly in contact with one electrical terminal of the transistor. Particularly, the transistor can be a field effect transistor or a bipolar junction transistor.... Agent: Quintero Law Office, Pc

20080157051 - Nonvolatile memory cell with concentric phase change material formed around a pillar arrangement: A memory cell comprises a first feature and a second feature. The second feature comprises a dielectric material and defines an opening at least partially overlying the first feature. A third feature is formed on the first feature and partially fills the opening in the second feature. What is more,... Agent: Ryan, Mason & Lewis, LLP

20080157052 - Resistance variable memory with temperature tolerant materials: A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb2Se3, and a metal-chalcogenide layer and methods of forming such a memory device.... Agent: Dickstein Shapiro LLP

20080157054 - Phase change memory device in which a distance between a lower electrode and a ground line is increased to secure the sensing margin of a cell and method for manufacturing the same: A phase change memory device includes a semiconductor substrate having active regions and an isolation structure; gate lines extending in a direction perpendicular to the active regions; a source region and a drain region formed in a surface of each active region; a dot type lower electrode including a first... Agent: Ladas & Parry LLP

20080157055 - Resistive random access memory device: Provided is a resistive random access memory (RRAM) device having a switching device and a storage node connected to the switching device, the storage node including a first electrode formed of a metal compound, the metal compound including metal with no more than a divalence and a metal compound having... Agent: Harness, Dickey & Pierce, P.L.C

20080157053 - Resistor random access memory cell device: A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080157056 - Manufacturing method of poly-wavelength light-emitting diode of utilizing nano-crystals and the light-emitting device therefor: A producing method of poly-wavelength light-emitting diode of utilizing nano-crystals and the light-emitting device thereof includes growing and processing a multiple-quantum-well layer based on stacking the mixture of at least two kinds of quantum wells to produce a two-wavelength light-emitting diode. Then, attaching nano-crystals on the two-wavelength light-emitting diode to... Agent: Rosenberg, Klein & Lee

20080157057 - Nanostructure having a nitride-based quantum well and light emitting diode employing the same: Disclosed are a nanostructure with an indium gallium nitride quantum well and a light emitting diode employing the same. The light emitting diode comprises a substrate, a transparent electrode and an array of nanostructures interposed between the substrate and the transparent electrode. Each of the nanostructures comprises a core nanorod,... Agent: Marger Johnson & Mccollom, P.c.

20080157058 - Dopant confinement in the delta doped layer using a dopant segregation barrier in quantum well structures: A device grade III-V quantum well structure and method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×108 cm−2 to be formed. In an embodiment of the present invention, a delta doped layer is disposed on a dopant... Agent: Intel/blakely

20080157059 - Optical semiconductor device having active layer of p-type quantum dot structure and its manufacture method: An active layer having a p-type quantum dot structure is disposed over a lower cladding layer made of semiconductor material of a first conductivity type. An upper cladding layer is disposed over the active layer. The upper cladding layer is made of semiconductor material, and includes a ridge portion and... Agent: Kratz, Quintos & Hanson, LLP

20080157060 - Semiconductor device having multiple lateral channels and method of forming the same: A semiconductor device having multiple lateral channels with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes a first... Agent: Glenn W. Boisbrun Slater & Matsil, L.l. P.

20080157061 - Field effect transistor array using single wall carbon nano-tubes: A field effect transistor array comprising a substrate and a plurality of single wall carbon nano-tubes disposed on a surface of the substrate. A plurality of electrodes are disposed over the nano-tubes such that the conductive strips are spaced-apart from each other. These electrodes form the contact point for the... Agent: U S Army Research Laboratory Attn Amsrl Cs Cc Ip

20080157062 - Spin transistor: A spin transistor 1 is a spin transistor 1 having a source S of a ferromagnetic material, a drain D of a ferromagnetic material, a semiconductor SM on which the source S and the drain D are disposed and which forms a Schottky contact with the source S, and a... Agent: Oliff & Berridge, Plc

20080157065 - Compositions, layers and films for optoelectronic devices, methods of production and uses thereof: Optoelectronic devices are described that include: a) a surface within the device, and b) at least one sufficiently light-transmissive crosslinked film, wherein the film is formed from at least one silicon-based material, at least one catalyst, and at least one solvent. Optoelectronic device are also disclosed, which include: a) a... Agent: Buchalter Nemer

20080157068 - Organic electronic device and method of manufacturing the same: An organic electronic device including: a first layer including a conductive or semiconductive organic material; a second layer including a conductive or semiconductive inorganic material, and in contact with the first layer; and an interface layer between the first layer and the second layer, wherein the interface layer includes a... Agent: Christie, Parker & Hale, LLP

20080157066 - Organic memory device and fabrication method thereof: The present disclosure relates to an organic memory device and a fabrication method thereof. The organic memory device comprises a first electrode, a second electrode, and an organic memory layer situated between the electrodes, wherein a metallic nanoparticle layer is further situated between the first electrode and the organic memory... Agent: Harness, Dickey & Pierce, P.L.C

20080157063 - Organic semiconductor compositions including plasticizers: A composition, comprising a solid mixture of organic semiconductor molecules and plasticizer molecules.... Agent: Hitt Gaines, Pc Alcatel-lucent

20080157070 - Organic semiconductor element having multi protection layers and process of making the same: An organic semiconductor element having multi protection layers and process of making the same are provided. Firstly, forming a first protection layer on the thin film transistor. Next, forming a second protection layer which is thick enough to serve as the photo spacers on said first protection layer. The multi... Agent: Rabin & Berdo, Pc

20080157064 - Organic thin film transistor and method for manufacturing the same: An organic thin film transistor including a substrate, a gate, a gate insulator, an adhesive layer, a metal nano-particle layer and an organic semiconductor layer is provided. The gate is disposed on the substrate. The gate insulator is disposed on the gate and the substrate. The adhesive layer is disposed... Agent: Jianq Chyun Intellectual Property Office

20080157071 - Thin film transistor and flat panel display including the same: A thin film transistor includes: a gate electrode; source and drain electrodes insulated from the gate electrode; an organic semiconductor layer that is insulated from the gate electrode and is electrically connected to the source and drain electrodes; an insulating layer that insulates the gate electrode from the source and... Agent: Stein, Mcewen & Bui, LLP

20080157067 - Thin film transistor device, image display device and manufacturing method thereof: In an image display device comprising a display part configured with a plurality of pixels and a peripheral integrated circuit which controls the display part, the display device is provided on a support substrate which has high durability for the impact and the bending, the pixel circuit is configured with... Agent: Miles & Stockbridge Pc

20080157069 - Thin film transistor for liquid crystal display device: A thin film transistor for an LCD device is disclosed, which comprises a gate electrode formed on a substrate; a gate insulation film formed of a high dielectric constant insulator having a bond structure of functional group, metal oxide, silicon and oxygen; and source and drain electrodes formed on the... Agent: Seyfarth Shaw, LLP

20080157072 - Memory device: A phase change memory cell is disclosed. The phase change memory cell includes a first thin film spacer and a second thin film spacer. The first thin film spacer defines a sub-lithographic dimension and is electrically coupled to a first electrode. The second thin film spacer defines a sub-lithographic dimension... Agent: Dicke, Billig & Czaja

20080157073 - Integrated transistor devices: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a lower oxide layer that is a mixture of Ga2O, Ga2O3, and other gallium oxide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium oxygen layer together positioned on upper surface (14)... Agent: Neifeld Ip Law, Pc

20080157077 - Integrated circuit and methods of measurement and preparation of measurement structure: A method for measuring an integrated circuit (IC) structure by measuring an imprint of the structure, a method for preparing a test site for the above measuring, and IC so formed. The method for preparing the test site includes incrementally removing the structure from the substrate so as to reveal... Agent: International Business Machines Corporation Dept. 18g

20080157074 - Method to measure ion beam angle: A device and method for measuring ion beam angle with respect to a substrate is disclosed. The method includes forming a plurality of shadowing structures extending substantially perpendicular from an upper surface of the substrate, directing an ion beam toward the substrate, the plurality of shadowing structures interrupting an incident... Agent: Texas Instruments Incorporated

20080157078 - Metrology structure and methods: A method of indicating the progress of a sacrificial material removal process, the method, comprising; freeing a portion of a member, the member being disposed in a cage and laterally surrounded by the sacrificial material; and preventing the freed portion of the member from floating away by retaining the freed... Agent: Hewlett Packard Company

20080157076 - Semiconductor device with test pads and pad connection unit: A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor... Agent: Law Office Of Monica H Choi

20080157075 - Test structure for estimating electromigration effects with increased robustness with respect to barrier defects in vias: By providing vias of increased mass flow blocking capability next to respective line segments of an electromigration test structure, the reliability of respective assessments may be enhanced, since electromigration-induced void formation in the test line segment under consideration may be efficiently decoupled from metal diffusion of neighboring test areas of... Agent: J. Mike Amerson, Williams, Morgan & Amerson, P.c.

20080157079 - Boron phosphide-based semiconductor light-emitting device and production method thereof: A boron phosphide-based semiconductor light-emitting device, comprising: a crystalline substrate; a first semiconductor layer formed on said crystalline substrate, said first semiconductor layer including a light-emitting layer, serving as a base layer and having a first region and a second region different from the first region; a boron phosphide-based semiconductor... Agent: Sughrue Mion, Pllc

20080157087 - Image sensor and method for manufacturing the same: Provided is an image sensor. The image sensor includes a semiconductor substrate, photodiode structures, color filters, and microlenses. The semiconductor substrate includes a first region having pixel regions and a second region around the first region. The pixel regions are arranged in a matrix configuration. Each of the photodiode structures... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080157084 - Mask device, method of fabricating the same, and method of fabricating organic light emitting display device using the same: A mask device, a method of fabricating the mask device with improved reliability, a method of manufacturing a large-sized division mask device by forming a striped aperture parallel to the roll direction, and a method of fabricating an organic light emitting display device (OLED) using the mask device. The mask... Agent: Stein, Mcewen & Bui, LLP

20080157086 - Method for manufacturing thin film transistor: A method for manufacturing a thin film transistor (TFT) is disclosed. The method is achieved by forming and defining a source and a drain of a thin film transistor through two lithographic processes cycles so that the channel length (L) of the thin film transistor can be reduced to 1.5... Agent: Bacon & Thomas, Pllc

20080157081 - Organic light emitting device and method for manufacturing the same: An organic light emitting device includes a substrate, first and second signal lines formed on the substrate, a switching thin film transistor (“TFT”) connected to the first and second signal lines and including a first semiconductor, a driving TFT including a second semiconductor, an etch stopper formed on the second... Agent: Cantor Colburn, LLP

20080157082 - Organic light emitting display and method of manufacturing the same: An organic light emitting display and a method of manufacturing the same that reduce the number of the masks needed and improve production yield by forming alignment marks during an SGS crystallization process for producing a thin film transistor includes a substrate having a display region and a non-display region,... Agent: Stein, Mcewen & Bui, LLP

20080157089 - Semiconductor device and manufacturing method thereof: [Solution] In a manufacturing method of a semiconductor device according to the invention, a first and a second TFTs 11 and 12 are formed over a substrate 10; an insulating film 13 is formed above the TFTs; a resist mask 14 for covering an area between adjacent pixel electrode formation... Agent: Eric Robinson

20080157088 - Thin film transistor array substrate and method for fabricating same: An exemplary TFT array substrate includes: an insulating substrate (201), a gate line (23) and a repair structure (272) arranged on the insulating substrate, a gate insulating layer (204) covering the gate line and the repair structure; a data line (27) arranged on the gate insulating layer corresponding to the... Agent: Wei Te Chung Foxconn International, Inc.

20080157085 - Thin film transistor substrate and fabricating method thereof: The present invention relates to a thin film transistor substrate and a fabricating method thereof. The thin film transistor according to one embodiment of the present invention comprises: a gate wire and a data wire formed to cross each other on an insulating substrate and define a pixel area; a... Agent: Birch Stewart Kolasch & Birch

20080157083 - Transistor, fabricating method thereof and flat panel display therewith: A transistor includes a substrate, an active region including a source region, a channel region, and a drain region which are crystallized using an SGS crystallization method and are formed on the substrate so that a grain size of a first annealed portion and a second annealed portion are different... Agent: Stein, Mcewen & Bui, LLP

20080157080 - Transparent and conductive nanostructure-film pixel electrode and method of making the same: A pixel electrode is provided, comprising a nanostructure-film deposited over an active matrix substrate, such that the pixel electrode makes electrical contact with an underlying layer. Similarly, auxiliary data pads and auxiliary gate pads are provided, which also comprise nanostructure-films deposited over an active matrix substrate, such that they make... Agent: Unidym

20080157091 - Methods of fabricating a semiconductor device using a cyclic selective epitaxial growth technique and semiconductor devices formed using the same: Devices and methods of fabricating a conductive pattern of such devices comprise a non-single crystalline semiconductor pattern formed on a single crystalline semiconductor substrate, an insulating spacer formed on a sidewall of the non-single crystalline semiconductor pattern, the non-single crystalline semiconductor pattern selectively recessed using a cyclic selective epitaxial growth... Agent: Mills & Onello LLP

20080157090 - Transplanted epitaxial regrowth for fabricating large area substrates for electronic devices: An epitaxial layer regrowth method and device. A single crystal seed layer is deposited on a support wafer. An exfoliation layer is implanted in the single crystal seed layer. Trenches are etched in a portion of the single crystal seed layer and a portion of the exfoliation layer. The single... Agent: Andrews Kurth LLP Intellectual Property Department

20080157092 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory according to an aspect of the invention comprises a semiconductor substrate which has an SOI region and an epitaxial region at its surface, a buried oxide film arranged on the semiconductor substrate in the SOI region, an SOI layer arranged on the buried oxide film, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080157093 - Capacitor having tapered cylindrical storage node and method for manufacturing the same: A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the... Agent: Ladas & Parry LLP

20080157094 - Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same: A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, including a source region, a drain region and a channel region, and made of a polycrystalline silicon layer; a gate electrode disposed to correspond to the channel region of the semiconductor layer; a gate insulating layer... Agent: Stein, Mcewen & Bui, LLP

20080157095 - Semiconductor devices having single crystalline silicon layers: Methods of manufacturing semiconductor devices having at least one single crystal silicon layer are provided. Pursuant to these methods, a first seed layer that includes silicon is formed. A first non-single crystalline silicon layer is then formed on the first seed layer. The first non-single crystalline silicon layer is irradiated... Agent: Myers Bigel Sibley & Sajovec

20080157096 - System and method for producing synthetic diamond: Synthetic monocrystalline diamond compositions having one or more monocrystalline diamond layers formed by chemical vapor deposition, the layers including one or more layers having an increased concentration of one or more impurities (such as boron and/or isotopes of carbon), as compared to other layers or comparable layers without such impurities.... Agent: Merchant & Gould Pc

20080157097 - Light-emitting diode structure and method for manufacturing the same: A light-emitting diode (LED) structure and a method for manufacturing the LED structure are disclosed for promoting the recognition rate of LED chips, wherein a roughness degree of the surface under a first electrode pad of a first conductivity type is made similar to that of the surface under a... Agent: Kinney & Lange, P.a.

20080157098 - Semiconductor device and method of manufacturing the same: The invention provides a semiconductor device with high reliability and smaller size and a method of manufacturing the same. A light emitting element as a device element is formed on the front surface of a semiconductor substrate, for example. In detail, an N-type semiconductor layer, a P-type semiconductor layer and... Agent: Morrison & Foerster LLP

20080157099 - Organic light emitting display and fabricating method thereof: An organic light emitting display and a fabricating method thereof in which an alignment mark is formed in the non-display region. The organic light emitting display includes a substrate having a display region and a non-display region; a buffer layer formed the overall substrate; a gate insulating layer; a gate... Agent: Stein, Mcewen & Bui, LLP

20080157103 - Laminating encapsulant film containing phosphor over leds: A process is described for wavelength conversion of LED light using phosphors. LED dies are tested for correlated color temperature (CCT), and binned according to their color emission. The LEDs in a single bin are mounted on a single submount to form an array of LEDs. Various thin sheets of... Agent: Patent Law Group LLP

20080157100 - Light-emitting diode assembly: A light emitting diode (LED) assembly includes at least an LED (102), a substrate (20), a heat dissipation apparatus (40) and at least one securing frame (30). The substrate forms a set of electrical circuitry (22) thereon. The at least one LED is arranged on a side of the substrate... Agent: Pce Industry, Inc. Att. Cheng-ju Chiang

20080157102 - Semiconductor layered structure and its method of formation, and light emitting device: In formation of a quantum dot structure in a light emitting layer, a matrix region (an n-type conductive layer and matrix layers) is formed on a growth underlying layer of AlN whose abundance ratio of Al is higher (or whose lattice constant is smaller) than that in the matrix region... Agent: Burr & Brown

20080157101 - Transistor array substrate and method of manufacturing the same: A transistor array substrate includes a first substrate including a pixel region and a transistor region. The pixel region includes a pixel electrode, a portion of a disconnected gate line and a portion of a disconnected data line. The transistor region includes first and second gate connecting portions respectively connected... Agent: Cantor Colburn, LLP

20080157104 - Liquid crystal panel having photo spacers for unimpeded display: An exemplary liquid crystal panel (3) includes a first substrate (31), a second substrate (32) parallel to the first substrate, and a liquid crystal layer (33) sandwiched between the first and second substrates. The first substrate includes first photo spacers (37) and a first alignment film (301) formed on the... Agent: Wei Te Chung Foxconn International, Inc.

20080157105 - Laterally configured electrooptical devices: A laterally configured electrooptical device including: a substrate having a surface; a first semiconductor layer of a first type semiconductor material; a second semiconductor layer formed of a second type semiconductor material different from the first type semiconductor material; a first electrode; and a second electrode. The lower surface of... Agent: Ratnerprestia

20080157106 - Nitride semiconductor laser element: A nitride semiconductor laser element comprises a substrate, a nitride semiconductor layer that is laminated on the substrate and that has a ridge on its surface, and an electrode that is electrically connected with the nitride semiconductor layer, wherein there is provided an insulating protective film produced by forming a... Agent: Global Ip Counselors, LLP

20080157107 - Light-emitting diode and method for manufacturing the same: A light-emitting diode (LED) and a method for manufacturing the same are described. The light-emitting diode comprises: a conductive substrate including a first surface and a second surface opposite to the first surface; a metal bonding layer deposed on the first surface of the conductive substrate; a reflective metal layer... Agent: Lowe Hauptman Ham & Berner, LLP

20080157109 - High efficiency light-emitting diode and method for manufacturing the same: A high efficiency light-emitting diode and a method for manufacturing the same are described. The high efficiency light-emitting diode comprises: a permanent substrate; a first contact metal layer and a second contact metal layer respectively deposed on two opposite surfaces of the permanent substrate; a bonding layer deposed on the... Agent: Lowe Hauptman Ham & Berner, LLP

20080157110 - Led chip having micro-lens structure: A light-emitting diode (LED) chip having a micro-lens structure includes a light-emitting structure and a light guide lens. The light-emitting structure emits a light from a light-emitting surface upon being applied with a current, and the light guide lens is stacked on the light-emitting surface and used for emitting the... Agent: Rabin & Berdo, Pc

20080157111 - Light-emitting devices: Light-emitting devices, and related components, systems and methods are disclosed.... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.c.

20080157108 - Light-emitting diode and method for manufacturing the same: A light-emitting diode (LED) and a method for manufacturing the same are described. The light-emitting diode comprises a substrate, a reflective structure, a buffer layer and an illuminant epitaxial structure. The reflective structure is deposed on a surface of the substrate, wherein the reflective structure includes a plurality of openings... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080157114 - Multiple lenses molded over led die: One or more LED dice are mounted on a support structure. The support structure may be a submount with the LED dice already electrically connected to leads on the submount. A mold has indentations in it corresponding to the positions of the LED dice on the support structure. The indentations... Agent: Patent Law Group LLP

20080157112 - Semiconductor lamp: A semiconductor lamp having a light-emitting semiconductor device, the semiconductor device comprising a carrier and at least one light-emitting semiconductor component on the carrier, and a heatsink. The heatsink has a first main face, the semiconductor device is located adjacent to the first main face, and the carrier faces the... Agent: Cohen Pontani Lieberman & Pavane LLP

20080157113 - Surface mount lateral light emitting apparatus and fabrication method thereof: A surface mount lateral light emitting apparatus, which includes a light emitting device; a first lead frame connected to the light emitting device; a second lead frame connected to the light emitting device; a first resin molding body in which a concave portion for mounting the light emitting device is... Agent: Squire, Sanders & Dempsey L.l.p.

20080157115 - High-efficiency light-emitting device and manufacturing method thereof: This invention provides a high-efficiency light-emitting device and the manufacturing method thereof. The high-efficiency light-emitting device includes a substrate; a reflective layer; a bonding layer; a first semiconductor layer; an active layer; and a second semiconductor layer formed on the active layer. The second semiconductor layer includes a first surface... Agent: Bacon & Thomas, Pllc

20080157116 - Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same: Provided are a thin film transistor capable of enhancing electrical and leakage current characteristics by reducing an amount of crystallization inducing metal remaining in a semiconductor layer, a method of fabricating the same, and an organic light emitting diode display device including the same. The method of the thin film... Agent: Robert E. Bushnell

20080157117 - Insulated gate bipolar transistor with enhanced conductivity modulation: A insulated gate bipolar transistors (IGBT) having an enhanced modulation layer provides reduced on-state power dissipation and better conductivity modulation than conventional devices. The IGBT includes an enhanced modulation layer disposed within a portion of the n− doped drift layer, in a n-type device, or p− doped drift layer, in... Agent: Andrews Kurth LLP Intellectual Property Department

20080157118 - Integrated circuit system employing strained technology: An integrated circuit system that includes: providing a substrate with a PMOS device and an NMOS device; forming an NMOS shallow recess within the substrate; forming a PMOS recess within the substrate; forming a strain inducing layer over the PMOS recess; forming a first dielectric layer over the NMOS device... Agent: Law Offices Of Mikio Ishimaru

20080157119 - Stack sige for short channel improvement: A semiconductor structure includes a first compound layer comprising an element, and a first impurity having a first impurity concentration; and a second compound layer comprising the element and a second impurity of a same conductivity type as the first impurity, wherein the second impurity has a second impurity concentration,... Agent: Slater & Matsil, L.l.p.

20080157121 - High speed high power nitride semiconductor device: A nitride semiconductor device has: a substrate; a semiconductor lamination formed on the substrate, and including a channel layer of nitride semiconductor; source and drain electrodes formed on the semiconductor lamination in ohmic contact with the channel layer; an insulating layer formed on the semiconductor lamination, and having an opening... Agent: Kratz, Quintos & Hanson, LLP

20080157122 - Integrated semiconductor structure including a heterojunction bipolar transistor and a schottky diode: An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer.... Agent: Mcnees Wallace & Nurick Llc

20080157123 - Epitaxial group iii nitride layer on (001)-oriented group iv semiconductor: Group III nitride layers have a wide range of uses in electronics and optoelectronics. Such layers are generally grown on substrates such as sapphire, SiC and recently Si(111). For the purpose inter alia of integration with Si-CMOS electronics, growth on Si(001) is indicated, which is possible only with difficulty because... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20080157124 - Semiconductor integrated circuit: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to... Agent: Mcdermott Will & Emery LLP

20080157126 - Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same: Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element... Agent: Wilmerhale/boston

20080157127 - Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same: Under one aspect, a nonvolatile nanotube diode includes: a substrate; a semiconductor element disposed over the substrate, the semiconductor element having an anode and a cathode and capable of forming an electrically conductive pathway between the anode and the cathode; a nanotube switching element disposed over the semiconductor element, the... Agent: Wilmerhale/boston

20080157125 - Transistor based antifuse with integrated heating element: The present invention provides structures for an integrated antifuse that incorporates an integrated sensing transistor with an integrated heater. Two terminals connected to the upper plate allow the heating of the upper plate, accelerating the breakdown of the antifuse dielectric at a lower bias voltage. Part of the upper plate... Agent: Scully, Scott, Murphy & Presser, P.c.

20080157128 - Methods for producing multiple distinct transistors from a single semiconductor: Provided are methods for producing multiple distinct transistors from a single semiconductor layer, and apparatus incorporating transistors so produced.... Agent: Foley Hoag, LLP Patent Group, World Trade Center West

20080157129 - Alternative sensingsensing circuit for mems microphone and sensingsensing method therefof: An alternative sensing circuit for a micro-electro-mechanical system (MEMS) microphone and a sensing method thereof are provided. The sensing circuit reads out output signals of an MEMS electret microphone or an MEMS condenser microphone. In considering different operating requirements of the different MEMS microphones, for example, low power consumption for... Agent: Jianq Chyun Intellectual Property Office

20080157130 - Expitaxial fabrication of fins for finfet devices: A fin for a finFET is described. The fin is a portion of a layer of material, where, another portion of the layer of material resides on a sidewall.... Agent: Intel/blakely

20080157132 - Method for forming the gate of a transistor: A method of forming a gate of a transistor can include forming a nitride film over a semiconductor substrate; forming a photoresist pattern defining a gate channel region of a transistor over the nitride film; forming a nitride pattern by etching the nitride film using the photoresist pattern as a... Agent: Sherr & Nourse, Pllc

20080157131 - Method of forming a selective spacer in a semiconductor device: A selective spacer for semiconductor and MEMS devices and method of manufacturing the same. In an embodiment, a selective spacer is formed adjacent to a first non-planar body having a greater sidewall height than a second non-planar semiconductor body in a self-aligned manner requiring no patterned etch operations. In a... Agent: Intel/blakely

20080157134 - Cmos image sensor and fabricating method thereof: A CMOS image sensor and method the same are disclosed. The method comprises forming an insulating interlayer including a plurality of photodiodes on a semiconductor substrate, forming a plurality of metal lines within the insulating interlayer, sequentially forming an oxide layer and a passivation layer on the insulating interlayer, forming... Agent: Workman Nydegger

20080157135 - Cmos image sensor and method of manufacturing thereof: A CMOS image sensor and a method of manufacturing thereof is capable of preventing a feed-through phenomenon. A CMOS image sensor includes a reset transistor which may include an epi-layer formed over a semiconductor substrate. The reset transistor also includes a channel layer formed over the epi-layer to form a... Agent: Sherr & Nourse, Pllc

20080157133 - Semiconductor device and fabricating method thereof: A semiconductor device and a fabricating method thereof are provided. A first device having a photodiode cell can be disposed adjacent to a second device having a transistor, and a connection electrode can electrically connect the first device and the second device.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080157136 - Thin-film transistor type photosensor: A photosensor includes a semiconductor thin film for photoelectric conversion having a first side portion and a second side portion. A source electrode extends in the longitudinal direction of the semiconductor thin film and has a side edge portion that overlaps the first side portion of the semiconductor thin film,... Agent: Frishauf, Holtz, Goodman & Chick, Pc

20080157141 - Cmos device and method of manufacturing the same: A method of manufacturing a CMOS device including: sequentially forming a first silicon oxide film and a first polysilicon film on a lower substrate; performing an ion implantation process with respect to the first polysilicon film to form a plurality of lower conductors spaced apart from one another at a... Agent: Sherr & Nourse, Pllc

20080157151 - Cmos image sensor: Embodiments of the invention relate to a CMOS image sensor. In detail, a CMOS image sensor can have improved sensitivity. The CMOS image sensor includes a photodiode on a semiconductor substrate, a drive transistor including a gate connected to the photodiode, a first grounded electrode and a second electrode connected... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080157144 - Cmos image sensor and fabricating method thereof: A method of fabricating a CMOS image sensor comprising forming an epitaxial layer on a semiconductor substrate, the epitaxial layer comprising a pixel and logic area, forming an STI layer in an insulating layer on the epitaxial layer, forming a plurality of wells and a gate pattern having a spacer... Agent: Workman Nydegger

20080157147 - Cmos image sensor and fabricating method thereof: A CMOS image sensor and method of manufacture reduces the problem of electron loss in a floating diffusion area. A method of fabricating a CMOS image sensor includes forming a gate electrode over a first conductive type semiconductor substrate. A second conductive type first diffusion layer is formed within the... Agent: Sherr & Nourse, Pllc

20080157152 - Cmos image sensor and manufacturing method thereof: The embodiment relates to a complementary metal oxide semiconductor (CMOS) image sensor and more particularly, to a CMOS image sensor and a manufacturing method thereof capable of improving electron storing capacity in a floating diffusion area. The CMOS image sensor includes a first gate electrode on a semiconductor substrate; a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080157138 - Cmos image sensor and method for fabricating the same: A complementary metal oxide semiconductor (CMOS) image sensor (CIS) and a method for fabricating the same. A method for fabricating a CIS includes implanting first conductive type dopants in a semiconductor substrate to form a photodiode region in a surface of the semiconductor substrate, implanting second conductive type dopants in... Agent: Workman Nydegger

20080157149 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor may include a gate electrode on a gate insulating layer in an active region of a semiconductor substrate; a photodiode region in the semiconductor substrate on one side of the gate electrode; a floating diffusion region in the semiconductor substrate on another side of the gate... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080157150 - Cmos image sensor and method for manufacturing the same: Embodiments relate to a Complementary Metal Oxide Semiconductor (CMOS) image sensor, and to a method for manufacturing the same, that improves the low-light level characteristics of the CMOS image sensor. The CMOS image sensor has a photosensor unit and a signal processing unit, and may include a semiconductor substrate having... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080157143 - Cmos image sensor and method of manufacturing thereof: A CMOS image sensor comprising an epitaxial layer formed on a semiconductor layer, a device isolating layer formed on the epitaxial layer in order to divide the isolating layer into an active region and a device isolating region, the active region including a photo diode region and a transistor region,... Agent: Workman Nydegger

20080157137 - Image sensor and fabricating method thereof: An image sensor and a method of fabricating an image sensor are provided. The image sensor can include a color filter layer formed on a substrate and a microlens array on the color filter layer. The microlens array includes a first set of microlenses formed of a low temperature oxide... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080157140 - Image sensor and fabricating method thereof: An image sensor including a semiconductor substrate having a photodiode, at least one interlayer dielectric layer formed over the semiconductor substrate and an oxide layer passes through the interlayer dielectric layer.... Agent: Sherr & Nourse, Pllc

20080157146 - Image sensor and method for fabricating the same: An image sensor includes: a photodiode and a transistor formed in a semiconductor substrate that is defined as a device isolation region and an active region; a first interlayer insulating film formed over the semiconductor substrate; a metal wire formed over the first interlayer insulating film; a second interlayer insulating... Agent: Sherr & Nourse, Pllc

20080157148 - Image sensor and method for manufacturing the same: An image sensor and manufacturing process thereof are provided. An image sensor according to an embodiment comprises a first wafer formed with a photodiode cell without a microlens and a second wafer formed with a logic circuit part. The first wafer is stacked on the second wafer such that a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080157139 - Image sensor and method of manufacturing the same: An image sensor including a first epitaxial layer having a first photodiode, a second epitaxial layer formed on and/or over the first epitaxial layer, the second epitaxial layer having a second photodiode and a first plug, and a third epitaxial layer formed on and/or over the second epitaxial layer, the... Agent: Sherr & Nourse, Pllc

20080157142 - Method for manufacturing of cmos image sensor: The present invention relates to a method for manufacturing a CMOS image sensor. The method comprises forming a photodiode and a transistor on a semiconductor substrate which is divided into a pixel region and a peripheral region, forming a plurality of oxide films and metal wiring on the semiconductor substrate,... Agent: Workman Nydegger

20080157145 - Method of fabricating image sensor: A method of fabricating a CMOS image sensor can include forming a first conductive type epitaxial layer on a heavily doped first conductive type substrate, forming a device isolation layer on a prescribed portion of the epitaxial layer, forming a gate electrode on an active area of the epitaxial layer... Agent: Sherr & Nourse, Pllc

20080157153 - Photoelectric conversion device, method for manufacturing the same and image pickup system: An object of the present invention is to provide a photoelectric conversion device, wherein improvement of charge transfer properties when charge is output from a charge storage region and suppression of dark current generation during charge storage are compatible with each other. This object is achieved by forming a depletion... Agent: Fitzpatrick Cella Harper & Scinto

20080157154 - Cmos image sensor and method for fabricating the same: A Complementary Metal Oxide Semiconductor (CMOS) image sensor and methods for fabricating the same. In one example embodiment of the invention, a method for manufacturing a Complementary Metal Oxide Semiconductor (CMOS) image sensor includes several acts. First, a metal pad is formed over a semiconductor substrate. Next, a protection film... Agent: Workman Nydegger

20080157156 - Method and structure for improved alignment in mram integration: A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment marks adjacent the first set of alignment marks. An opaque layer is formed over the lower level, including the... Agent: Cantor Colburn LLP-ibm Yorktown

20080157155 - Semiconductor device and method for manufacturing the same: According to one embodiment, after forming transistors on a semiconductor substrate, a stopper layer and an interlayer insulating film are formed. Then, a contact hole is formed in the interlayer insulating film and a copper film is formed on the interlayer insulating film to bury the inside of the contact... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080157157 - Semiconductor integrated circuit device: A DRAM capacitor uses ruthenium or ruthenium oxide as an upper electrode and hafnium dioxide or zirconium oxide as an insulation layer. The DRAM capacitor is intended to suppress diffusion of ruthenium, etc. into hafnium dioxide. Tantalum pentoxide or niobium oxide having a higher permittivity than that of the insulation... Agent: Miles & Stockbridge Pc

20080157158 - Semiconductor device capacitor fabrication method: A semiconductor device capacitor fabrication method that is capable of enabling the simultaneous use of an oxide capacitor and a PIP capacitor of a semiconductor device depending upon whether metal line terminals are used. The semiconductor device capacitor fabrication method can include forming an active region and a first gate... Agent: Sherr & Nourse, Pllc

20080157159 - Highly tunable metal-on-semiconductor varactor: A metal-on-semiconductor varactor with a high value of Cmax/Cmin comprises a semiconductor bottom plate with an array of semiconductor pillars. The pillars may be in an accumulation mode to provide a high capacitance or in a depletion mode to provide a low capacitance. The maximum capacitance in an accumulation mode... Agent: Scully, Scott, Murphy & Presser, P.c.

20080157161 - Apparatus, system, and method for multiple-segment floating gate: Various embodiments include a substrate and a memory cell coupled to the substrate. The memory cell may include an L-shaped floating gate. Other embodiments including additional apparatus, systems, and methods are disclosed.... Agent: Schwegman, Lundberg & Woessner, P.a.

20080157163 - Eeprom device and method of forming the same: There are provided EEPROM devices and methods of forming the same. The device includes: a substrate having an active region defined by a device isolation layer; a first sense line and a second sense line which straightly extend on the substrate and have a memory gate; a first word line... Agent: Mills & Onello LLP

20080157160 - Local interconnect having increased misalignment tolerance: A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first interlayer dielectric is formed between the pair... Agent: Harrity & Snyder, L.l.p.

20080157162 - Method of combining floating body cell and logic transistors: An integrated circuit having both floating body cells and logic devices fabricated in a bulk silicon substrate is described. The floating body cells have electrically floating bodies formed by oxidizing a lower portion of the cell bodies to electrically isolate them from the substrate.... Agent: Intel/blakely

20080157164 - Flash memory and method for fabricating thereof: Disclosed are methods for fabricating a flash memory. One method comprises forming an oxide layer on both a gate structure, which includes a floating gate and a control gate, on a cell area and a gate on a periphery area of a semiconductor substrate. An insulating layer having a thickness... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080157167 - Flash memory device: Embodiments relate to a flash memory device and to method of fabricating a flash memory device is disclosed. According to embodiments, a method may include forming a device isolation layer on a semiconductor substrate to define active regions, forming floating gate patterns on the active regions, forming the photoresist patterns... Agent: Sherr & Nourse, Pllc

20080157165 - Flash memory device and method of manufacturing the same: A flash memory device and a method of manufacturing a flash memory device are provided. The flash memory device includes a gate region on a semiconductor substrate, spacers on sidewalls of the gate region, and a passivation layer between the semiconductor substrate and a portion of each spacer.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080157166 - Method of fabricating flash memory device: A flash memory device including a cell region and a logic region formed over a semiconductor substrate; a pair of stacked gates formed spaced apart over the cell region; a pair of first spacers formed over the cell region in direct contact with at least one side of the stacked... Agent: Sherr & Nourse, Pllc

20080157168 - Semiconductor memory device and method of manufacturing the same: A nonvolatile memory includes a semiconductor substrate having a body member and a step member formed on the body member, a highly doped first well layer formed on the step member, a control electrode formed on the step member, a first and a second diffusion layers in the substrate, lightly... Agent: Junichi Mimura Oki America Inc.

20080157169 - Shield plates for reduced field coupling in nonvolatile memory: Shield plates for reduced coupling between charge storage regions in nonvolatile semiconductor memory devices, and associated techniques for forming the same, are provided. Electrical fields associated with charge stored in the floating gates or other charge storage regions of a memory device can couple to neighboring charge storage regions because... Agent: Vierra Magen/sandisk Corporation

20080157183 - Convex shaped thin-film transistor device: The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density, and a method of manufacturing such a semiconductor device. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided... Agent: Murabito, Hao & Barnes LLP

20080157171 - Dielectric barrier for nanocrystals: Electronic apparatus, systems, and methods of forming such electronic apparatus and systems include non-insulating nanocrystals disposed on a dielectric stack, where the non-insulating nanocrystals are arranged to store electric charge. The dielectric stack includes two dielectric layers having different electron barriers such that the non-insulating nanocrystals may be disposed on... Agent: Schwegman, Lundberg & Woessner, P.a.

20080157170 - Eeprom cell with adjustable barrier in the tunnel window region: An electrically programmable memory cell and corresponding method for fabricating the same, provide a reduced electron tunneling threshold to reduce parasitic substrate currents during cell programming. A floating gate of the cell is formed over an injector dopant region diffused within and encompassed by a first dopant region. Both dopant...