Active solid-state devices (e.g., transistors, solid-state diodes) inventions 06/08

20080149907 - Complementary resistive memory structure: A complementary resistive memory structure is provided comprising a common source electrode and a first electrode separated from the common source electrode by resistive memory material; and a second electrode adjacent to the first electrode and separated from the common source electrode by resistive memory material, along with accompanying circuitry... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080149908 - Doped phase change material and pram including the same: Provided are a doped phase change material and a phase change memory device including the phase change material. The phase change material, which may be doped with Se, has a higher crystallization temperature than a Ge2Sb2Te5 (GST) material. The phase change material may be InXSbYTeZSe100−(X+Y+Z). The index X of indium... Agent: Harness, Dickey & Pierce, P.L.C

20080149909 - Pillar phase change memory cell: A memory cell includes a first electrode, a storage location, and a second electrode. The storage location includes a phase change material and contacts the first electrode. The storage location has a first cross-sectional width. The second electrode contacts the storage location and has a second cross-sectional width greater than... Agent: Dicke, Billig & Czaja

20080149910 - Phase-change memory device having phase change material pattern shared between adjacent cells and electronic product including the phase-change memory: Provided is a phase-change memory device including a phase-change material pattern of which strips are shared by neighboring cells. The phase-change memory device includes a plurality of bottom electrodes arranged in a matrix array. The phase-change material pattern is formed on the bottom electrodes, and the strips of the phase-change... Agent: Volentine & Whitt Pllc

20080149911 - Programmable-resistance memory cell: A memory cell (10) comprising at least a source electrode (MS) formed on a substrate (6); at least a drain electrode (MD) formed on the substrate (6); at least a coupling layer (1) formed between the source electrode (MS) and the drain electrode (MD), and at least a gate electrode... Agent: Anne Vachon Dougherty

20080149913 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device is disclosed, which includes a first memory cell array formed on a semiconductor substrate and composed of a plurality of memory cells stacked in layers each having a characteristic change element and a vertical type memory cell transistor connected in parallel to each other, a plurality... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080149912 - Semiconductor memory device and programming method thereof: A semiconductor memory device according to the present invention has a storage unit that includes an interlayer insulation film, a lower electrode layer embedded in the interlayer insulation film, and a recording layer and an upper electrode layer provided on the interlayer insulation film. When a predetermined current is passed... Agent: Sughrue Mion, Pllc

20080149914 - Nanoelectronic structure and method of producing such: The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection... Agent: Foley And Lardner LLP Suite 500

20080149916 - Semiconductor light emitting device: A light emitting device with an increased light extraction efficiency includes a two-dimensional periodic structure in a surface thereof and has two layers that together form an asymmetric refractive index distribution with respect to the active layer, which is in between the two layers. The light emitting device includes a... Agent: Frishauf, Holtz, Goodman & Chick, Pc

20080149915 - Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission: Semiconductor light-emitting structures are shown on engineered substrates having a graded composition. The composition of the substrate may be graded to achieve a lattice constant on which a yellow-green light-emitting semiconductor material may be disposed. In some embodiments, the structure may be substantially free of aluminum.... Agent: Wolf Greenfield & Sacks, P.c.

20080149917 - Iii-nitride compound semiconductor light emitting device: The present invention relates to a III-nitride compound semiconductor light emitting device comprising an active layer with the multi-quantum wells interposed between an n-InxAlyGazN(x+y+z=1, 0<x<1, 0<y<1, 0<z≦1) layer and a p-InxAlyGazN(x+y+z=1, 0<x<1, 0<y<1, 0<z<1) layer, wherein the active layer comprises an alternate stacking of a quantum-well layer made of InxGa1-xN(0.05<x<1)... Agent: Darby & Darby P.c.

20080149918 - Iii-nitride compound semiconductor light emitting device: The present invention provides a III-nitride compound semiconductor light emitting device comprising an active layer (30) which emits light and is interposed between a lower contact layer (20) made of n-GaN and an upper contact layer (40) made of p-GaN, in which a sequential stack of a lattice mismatch-reducing layer... Agent: Darby & Darby P.c.

20080149919 - Structure and method for realizing a microelectronic device provided with a number of quantum wires capable of forming one or more transistor channels: A microelectronic device provided with one or more quantum wires, able to form one or more transistor channels, and optimized in terms of arrangement, shape, and/or composition. A method for fabricating the device includes forming, in one or more thin layers resting on a support, a first block and a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080149920 - Printing method for high performance electronic devices: A method of depositing elongated nanostructures that allows accurate positioning and orientation is described. The method involves printing or otherwise depositing elongated nanostructures in a carrier solution. The deposited droplets are also elongated, usually by patterning the surface upon which the droplets are deposited. As the droplet evaporates, the fluid... Agent: Patent Documentation Center

20080149921 - Electronic device and producing method therefor: Disclosed herein is an electronic device of a three-terminal type including, a control electrode, first and second electrodes, and an active layer provided between the first and second electrodes so as to face the control electrode with an insulating layer interposed therebetween, the active layer being formed from an aggregate... Agent: Bell, Boyd & Lloyd, LLP

20080149922 - Electronic devices with hybrid high-k dielectric and fabrication methods thereof: Electronic devices with hybrid high-k dielectric and fabrication methods thereof. The electronic device includes a substrate. A first electrode is disposed on the substrate. Hybrid high-k multi-layers comprising a first dielectric layer and a second dielectric layer are disposed on the substrate, wherein the first dielectric layer and the second... Agent: Quintero Law Office, Pc

20080149924 - Hermetically sealing a device without a heat treating step and the resulting hermetically sealed device: A method for hermetically sealing a device without performing a heat treatment step and the resulting hermetically sealed device are described herein. The method includes the steps of: (1) positioning the un-encapsulated device in a desired location with respect to a deposition device; and (2) using the deposition device to... Agent: Corning Incorporated

20080149923 - Light-emitting device: Light-emitting elements having high emission efficiency and long lifetime can be provided. By forming light-emitting devices including the light-emitting elements, the light-emitting devices having low power consumption and long lifetime can be provided. A light-emitting device comprises a light-emitting element including a light-emitting layer between a first electrode and a... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080149925 - Semiconductor device for measuring an overlay error, method for measuring an overlay error, lithographic apparatus and device manufacturing method: A semiconductor device for determining an overlay error on a semiconductor substrate includes a first and a second transistor. Each transistor includes two diffusion regions associated with a gate, the diffusion regions of each transistor being arranged in a first direction. The second transistor is arranged adjacent to the first... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20080149926 - Semiconductor device having test pattern for measuring epitaxial pattern shift and method for fabricating the same: A semiconductor device having a test pattern for measuring epitaxial pattern shift is provided. The test pattern includes a semiconductor substrate having a first pattern formed therein; a first impurity region formed in the semiconductor substrate; an epitaxial layer formed on the semiconductor substrate, the epitaxial layer having a second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080149927 - Semiconductor device, method and apparatus for testing same, and method for manufacturing semiconductor device: A semiconductor device wherein an electrode pad to be contacted a test probe for performing probe testing, a bonding area mark for defining a bonding area which performs wire boding on the electrode pad, and a probe area mark for defining a probe repair area for repairing or replacing the... Agent: Mcginn Intellectual Property Law Group, Pllc

20080149928 - Production method of semiconductor device and semiconductor device: The present invention provides a production method of a semiconductor device, which can improve characteristics of a semiconductor element including a single crystal semiconductor layer formed by transferring on an insulating substrate. The present invention is a production method of a semiconductor device comprising a single crystal semiconductor layer formed... Agent: Nixon & Vanderhye, Pc

20080149929 - Method of producing a semiconductor element and semiconductor element: In a method of producing a semiconductor element in a substrate, a plurality of carbide precipitates is formed in the substrate, doping atoms are implanted into the substrate, thereby forming crystal defects in the substrate, the substrate is heated, such that at least a part of the crystal defects is... Agent: Dickstein Shapiro LLP

20080149931 - Display device and manufacturing method thereof: The present invention is to reduce display unevenness in a display device caused by dispersion of energy density of a laser beam. It is difficult for a periodical pattern to be recognized as display unevenness in display image. The display device of the present invention can visually reduce the display... Agent: Nixon Peabody, LLP

20080149930 - Wire structure, method for fabricating wire, thin film transistor substrate, and method for fabricating the thing film transistor substrate: Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including copper, copper solid solution layer.... Agent: Macpherson Kwok Chen & Heid LLP

20080149932 - Semiconductor device: A semiconductor device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate and including a plurality of memory cells arranged on the semiconductor substrate, each of the plurality of the memory cells including a first insulating film provided on the semiconductor substrate, a charge storage... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080149933 - Display panel: A display panel includes a first substrate, a second substrate and a spacer. The first substrate includes a gate line, a data line crossing the gate line to define a pixel area, and a storage electrode formed in the pixel area. The second substrate is coupled with the first substrate... Agent: Macpherson Kwok Chen & Heid LLP

20080149937 - Connection structure, electro-optical device, and method for production of electro-optical device: The invention provides a connection structure including: a first electro-conductive film that is formed on a substrate; an insulation film that is formed on the first electro-conductive film, an end surface of the insulation film facing in a direction in which an end surface of the first electro-conductive film faces;... Agent: Workman Nydegger

20080149938 - Electronic device, thin film transistor structure and flat panel display having the same: The present invention provides an electronic device having more than two conductive layers that cross but not in contact with each other. At least one of the conductive layers comprises a width change part, a width of which changes in a length direction of at least one of the conductive... Agent: H.c. Park & Associates, Plc

20080149934 - Printed component circuit with fluidic template: A method forms a plurality of pillars, the pillars arranged such that positions of the pillars control flow of a liquid, the plurality of pillars forming a fluidic template, the method dispenses the liquid into the fluidic template such that the liquid assumes a shape corresponding to the fluidic template,... Agent: Marger Johnson & Mccollom/parc

20080149936 - Process for integratng a iii-n type component on a (001) nominal silicium substrate: A process is provided for integrating a III-N component, such as GaN, on a (001) or (100) nominal silicon substrate. There are arranged a texture of elementary areas each comprising an individual surface, with the texture comprising at least one hosting area intended to receive a III-N component. A mask... Agent: Fleit, Kain, Gibbons, Gutman, Bongini & Bianco P.l.

20080149935 - Thin film transistor substrate and fabricating method thereof: According to an embodiment, there is provided a thin film transistor substrate divided into a display area displaying the image and a non-display besides the display area, the thin film transistor substrate comprising: a common voltage line for MPS (mass production system) test and a grounding line for MPS (mass... Agent: Birch Stewart Kolasch & Birch

20080149939 - Electronic cooling device and fabrication method thereof: Provided are an electronic cooling device and a fabrication method thereof. The method may include forming an insulating layer on a semiconductor substrate, forming first and second silicide layers on the insulating layer, forming separate paired p-type and n-type semiconductors on each of the first and second silicide layers, forming... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080149941 - Compound semiconductor-on-silicon wafer with a silicon nanowire buffer layer: A compound semiconductor-on-silicon (Si) wafer with a Si nanowire buffer layer is provided, along with a corresponding fabrication method. The method forms a Si substrate. An insulator layer is formed overlying the Si substrate, with Si nanowires having exposed tips. Compound semiconductor is selectively deposited on the Si nanowire tips.... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080149940 - Nitride semiconductor device: A nitride semiconductor device includes: a substrate; a nitride semiconductor layer formed on a main surface of the substrate and having a channel region through which electrons drift in a direction parallel to the main surface; and a plurality of first electrodes and a plurality of second electrodes formed spaced... Agent: Mcdermott Will & Emery LLP

20080149942 - Iii-nitride light emitting device with reduced strain light emitting layer: In accordance with embodiments of the invention, strain is reduced in the light emitting layer of a III-nitride device by including a strain-relieved layer in the device. The surface on which the strain-relieved layer is grown is configured such that strain-relieved layer can expand laterally and at least partially relax.... Agent: Patent Law Group LLP

20080149943 - Semiconductor photodetector and radiation detecting apparatus: A photodiode array PD1 comprises an n-type semiconductor substrate one face of which is an incident surface of light to be detected; a plurality of pn junction-type photosensitive regions 3 as photodiodes formed on the side of a detecting surface that is opposite to the incident surface of the semiconductor... Agent: Drinker Biddle & Reath (dc)

20080149944 - Led with upstanding nanowire structure and method of producing such: The present invention relates to light emitting diodes, LEDs. In particular the invention relates to a LED comprising a nanowire as an active component. The nanostructured LED according to the embodiments of the invention comprises a substrate and at an upstanding nanowire protruding from the substrate. A pn-junction giving an... Agent: Foley And Lardner LLP Suite 500

20080149945 - Semiconductor light emitting device, light emitting module, lighting apparatus, display element and manufacturing method of semiconductor light emitting device: An LED array chip (2), which is one type of a semiconductor light emitting device, includes an array of LEDs (6), a base substrate (4) supporting the array of the LEDs (6), and a phosphor film (48). The array of LEDs (6) is formed by dividing a multilayer epitaxial structure... Agent: Snell & Wilmer L.l.p. (matsushita)

20080149947 - Bonding structure of circuit substrate and instant circuit inspection method thereof: The present invention provides a bonding structure of circuit substrates and an instant circuit inspection method thereof. The contact pad design of the bonding structure has an instant inspection ability of circuit connection in bonding two circuit substrates. In two bonded circuit substrates, the signal inputted at the circuit part... Agent: Rosenberg, Klein & Lee

20080149948 - Edge-emitting light-emitting diode arrays and methods of making and using the same: The present invention is directed to edge-emitting light-emitting diode arrays, a process to prepare the edge-emitting light-emitting diode arrays, and process products prepared by the process.... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080149949 - Lead frame for transparent and mirrorless light emitting diodes: A lead frame for a transparent and mirrorless light emitting diode (LED). The LED is comprised of a plurality of III-nitride layers, including an active region that emits light, wherein all of the layers except for the active region are transparent for an emission wavelength of the light, such that... Agent: Gates & Cooper LLP Howard Hughes Center

20080149946 - Semiconductor light emitting device configured to emit multiple wavelengths of light: In accordance with embodiments of the invention, a III-nitride structure includes a plurality of posts of semiconductor material corresponding to openings in a mask layer. Each post includes a light emitting layer. Each light emitting layer is disposed between an n-type region and a p-type region. A first light emitting... Agent: Patent Law Group LLP

20080149950 - Optical communication semiconductor device and method for manufacturing the same: An optical communication semiconductor device including: a first light emitting layer composed of a semiconductor; and a second light emitting layer which is laid on or above the first light emitting layer and composed of a semiconductor capable of emitting light having a emission peak at a wavelength different from... Agent: Rabin & Berdo, Pc

20080149951 - Light emitting device: A light emitting device including a carrying element having two electric conductors connectable to a power source, a light emitting element disposed on the carrying element and electrically connected to the two electric conductors, and at least one correction element electrically connected to the light emitting element, wherein the light... Agent: Birch Stewart Kolasch & Birch

20080149952 - Semiconductor light emitting device and method for manufacturing the same: The present invention provides a semiconductor light emitting device and a method for manufacturing the same. The semiconductor device comprises (i) a semiconductor layer with convex portions in a shape selected from a cone and a truncated cone and (ii) electrodes, wherein in the case of the convex portions with... Agent: Fitch, Even, Tabin & Flannery

20080149953 - Group iii-v semiconductor device and method for producing the same: The method of the invention for producing a group III-V semiconductor device includes forming, on a base, a plurality of semiconductor devices isolated from one another, each semiconductor device having at least an n-layer proximal to the base, and a p-layer distal to the base, and having a p-electrode formed... Agent: Mcginn Intellectual Property Law Group, Pllc

20080149954 - Light generating semiconductor device and method of making the same: In a method of making a semiconductor light generating device, a GaN-based semiconductor portion is formed on a GaN or AlGaN substrate. The GaN-based semiconductor portion includes a light generating film. An electrode film is formed on the GaN-based semiconductor film. A conductive substrate is bonded to a surface of... Agent: Mcdermott Will & Emery LLP

20080149955 - Nitride semiconductor: A nitride semiconductor device used chiefly as an LD and an LED element. In order to improve the output and to decrease Vf, the device is given either a three-layer structure in which a nitride semiconductor layer doped with n-type impurities serving as an n-type contact layer where an n-electrode... Agent: Nixon & Vanderhye, Pc

20080149960 - Light-emitting apparatus and method of producing the same: A light-emitting apparatus includes a package including a support having a central section and a peripheral section around the central section. The central section is raised upwardly from the peripheral section, providing a pedestal for supporting a light-emitting device. A light-emitting device secured on an upper surface of the pedestal... Agent: Nixon & Vanderhye, Pc

20080149958 - Light-radiating semiconductor component with a luminescence conversion element: The light-radiating semiconductor component has a radiation-emitting semiconductor body and a luminescence conversion element. The semiconductor body emits radiation in the ultraviolet, blue and/or green spectral region and the luminescence conversion element converts a portion of the radiation into radiation of a longer wavelength. This makes it possible to produce... Agent: Fish & Richardson Pc

20080149956 - Multi-grain luminescent ceramics for light emitting devices: A ceramic body is disposed in a path of light emitted by a light source. The light source may include a semiconductor structure comprising a light emitting region disposed between an n-type region and a p-type region. The ceramic body includes a plurality of first grains configured to absorb light... Agent: Patent Law Group LLP

20080149957 - Nitride phosphor, method for producing this nitride phosphor, and light emitting device that uses this nitride phosphor: In addition, the mean particle diameter of the nitride phosphor is preferably not less than 2 μm and not more than 15 μm. Additionally, the light emitting device includes a light source with a first light emission spectrum that emits light from the near ultraviolet range to the blue range,... Agent: Ditthavong Mori & Steiner, P.c.

20080149959 - Transparent light emitting diodes: A transparent light emitting diode (LED) includes a plurality of III-nitride layers, including an active region that emits light, wherein all of the layers except for the active region are transparent for an emission wavelength of the light, such that the light is extracted effectively through all of the layers... Agent: Gates & Cooper LLP Howard Hughes Center

20080149961 - Iii-nitride light emitting devices grown on templates to reduce strain: In a III-nitride light emitting device, the device layers including the light emitting layer are grown over a template designed to reduce strain in the device, in particular in the light emitting layer. Reducing the strain in the light emitting device may improve the performance of the device. The template... Agent: Patent Law Group LLP

20080149962 - Light emitting device package and method for manufacturing the same: A light emitting device package capable of achieving an enhancement in light emission efficiency and a reduction in thermal resistance, and a method for manufacturing the same are disclosed. The method includes forming a mounting hole in a first substrate, forming through holes in a second substrate, forming a metal... Agent: Birch Stewart Kolasch & Birch

20080149963 - Trench type mosfet and method of fabricating the same: A Trench MOSFET includes a trench region (16) provided on a semiconductor substrate. The semiconductor substrate includes a P-type semiconductor substrate (1), a P-type semiconductor epitaxial layer (2), an N-type semiconductor body region (3), and a P-type semiconductor source diffusion (7). The substrate (1), the epitaxial layer (2), the body... Agent: Harness, Dickey & Pierce, P.L.C

20080149964 - Semiconductor devices: A semiconductor device 10 comprises a heterojunction between a lower semiconductor layer 26 made of p-type gallium nitride and an upper semiconductor layer 28 made of n-type AlGaN, wherein the upper semiconductor layer 28 has a larger band gap than the lower semiconductor layer 26. The semiconductor device 10 further... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080149965 - Transistor and method for fabricating the same: A transistor includes: a first semiconductor layer and a second semiconductor layer with a first region and a second region, which are sequentially formed above a substrate; a first p-type semiconductor layer formed on a region of the second semiconductor layer other than the first and second regions; and a... Agent: Mcdermott Will & Emery LLP

20080149966 - Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner: Buffers are arranged in a concentrated manner in a region distant from pads. The region refers to a region in a main region of a semiconductor integrated circuit, except for a central processing unit, a non-volatile memory and a volatile memory. As the buffer requiring a large area is not... Agent: Mcdermott Will & Emery LLP

20080149967 - Back illuminated imaging device: A back illuminated imaging device 1 comprises a plurality charge blocking regions 19 which are arranged on a front surface 12 side, embedded in CCD charge transferring paths 21, and in which a first thickness T1 measured from the front surface 12 of first portions 19a extending along the CCD... Agent: Birch Stewart Kolasch & Birch

20080149968 - Method of manufacturing sensor with photodiode and charge transfer transistor: A method of manufacturing a photodiode sensor and an associated charge transfer transistor includes forming an insulation region on a substrate, forming the diode on a first side of the insulation region with the diode being self-aligned on the insulation region, and replacing the insulation region by a gate of... Agent: Hogan & Hartson LLP

20080149969 - Semiconductor device and manufacturing method thereof: A semiconductor device includes an active region formed on a semiconductor substrate, an element isolation region formed on the semiconductor substrate so as to surround the active region, and a gate electrode formed on the active region. A region that causes tensile stress so as to improve carrier mobility in... Agent: Mcdermott Will & Emery LLP

20080149970 - Multi-gated carbon nanotube field effect transistor: A multiple, independent top gated field effect transistor having an improved electron injection and reduced gate induced barrier lowering effects, and a method that allows for the destruction of metallic carbon nanotubes positioned between the source and drain of a top multi-gate transistor are provided. The field effect transistor comprises... Agent: Ingrassia Fisher & Lorenz, P.c. (mot)

20080149972 - Semiconductor device: ON resistance and leakage current of a vertical power MOSFET are to be diminished. In a vertical high breakdown voltage MOSFET with unit MOSFETs (cells) arranged longitudinally and transversely over a main surface of a semiconductor substrate, the cells are made quadrangular in shape, and in each of the cells,... Agent: Miles & Stockbridge Pc

20080149971 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device is provided. The method includes forming a gate insulating layer on a semiconductor substrate, forming a gate electrode on the gate insulating layer, forming spacers on sidewalls of the gate electrode, forming impurity regions in the semiconductor substrate using the gate electrode and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080149973 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device is provided. The method includes: forming a gate insulating layer on a semiconductor substrate having an isolation layer formed therein, forming a gate electrode on the gate insulating, implanting low-concentration impurity ions on the semiconductor substrate at a first side of the gate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080149974 - Cmos image sensor and fabricating method thereof: A CMOS image sensor and method of fabricating the same are disclosed. The method comprises forming a plurality of polysilicon patterns on a silicon epitaxial layer which correspond to a plurality of photodiodes in a dummy pixel area, depositing a metal with a high melting point metal on the plurality... Agent: Workman Nydegger

20080149975 - Method for manufacturing image sensor: A method of manufacturing an image sensor that may restrain the oxidization of a pad. A method of manufacturing an image sensor may include at least one of the following steps: Forming a photodiode structure including a pixel in an active region of a semiconductor substrate. Forming a conductive pad... Agent: Sherr & Nourse, Pllc

20080149976 - Vertical type cmos iamge sensor and method of manufacturing the same: A vertical type CMOS image sensor and a method of manufacturing the same including a P+-type red photodiode formed in a semiconductor substrate, a first silicon epilayer formed over the semiconductor substrate and including a P+-type green photodiode formed therein, a second silicon epilayer formed over the first silicon epilayer... Agent: Sherr & Nourse, Pllc

20080149977 - Semiconductor device and method for manufacturing the same: According to the present invention, there is provided a method for manufacturing a semiconductor device, including the steps of forming an insulating film on a silicon substrate, forming a first conductive film on the insulating film, forming an aluminum crystal layer on the first conductive film, forming a ferroelectric film... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080149978 - Memory device and method of fabricating a memory device: A memory device, comprising a semiconductor substrate with at least one storage cell, the storage cell comprising a storage element and a selection transistor, wherein the memory device further comprises a storage element contact assigned to the storage cell, the storage element contact extending from the selection transistor to the... Agent: Slater & Matsil LLP

20080149979 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device having a capacitor is provided. The method includes forming an isolation layer on a substrate on which a capacitor region and a transistor region are defined, forming a trench in the isolation layer, sequentially forming a first polysilicon layer, a dielectric layer, and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080149982 - Cmos transistor: A CMOS transistor comprises a substrate with a gate electrode arranged thereon between source and drain regions. A capacitor is provided on the gate electrode and a voltage applied to the gate electrode is dropped across a stack, including the gate electrode and the capacitor.... Agent: Texas Instruments Incorporated

20080149981 - Rf power transistor with large periphery metal-insulator-silicon shunt capacitor: An integrated MIS capacitor structure comprises a high quality factor shunt capacitor. The integrated MIS capacitor is configured with a large periphery and an external ground via to mitigate resistive losses in the bottom plate of the MIS shunt capacitor.... Agent: Freescale Semiconductor, Inc. Law Department

20080149980 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming an insulating material layer. The method includes forming an interface layer, removing a portion of the interface layer, annealing the interface layer, and forming a dielectric material over the interface layer.... Agent: Slater & Matsil LLP

20080149983 - Metal-oxide-semiconductor (mos) varactors and methods of forming mos varactors: MOS varactor having an entire accumulation and depletion regime of its CV characteristic curve in one bias regime (negative or positive). The MOS varactor may comprise a gate electrode, a well region of semiconductor material having a first conductivity type (e.g., p-type), contact regions to the well region that comprise... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20080149984 - Floating body memory cell having gates favoring different conductivity type regions: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for... Agent: Intel/blakely

20080149987 - Gate structures for flash memory and methods of making same: A process may include forming a polysilicon pinnacle above and on a polysilicon island and further forming a floating gate from the polysilicon pinnacle and polysilicon island. The floating gate can bear an inverted T-shape. The floating gate can also be disposed above an isolated semiconductive substrate such as in... Agent: Schwegman, Lundberg & Woessner, P.a.

20080149985 - Method for fabricating floating gates structures with reduced and more uniform forward tunneling voltages: An improved method for fabricating floating gate structures of flash memory cells having reduced and more uniform forward tunneling voltages. The method may include the steps of: forming at least two floating gates over a substrate; forming a mask over each of the floating gates, each of the masks having... Agent: Duane Morris LLP Ip Department (tsmc)

20080149988 - Semiconductor memory devices and methods for fabricating the same: Methods are provided for fabricating memory devices. A method comprises fabricating charge-trapping stacks overlying a silicon substrate and forming bit line regions in the substrate between the charge trapping stacks. Insulating elements are formed overlying the bit line regions between the stacks. The charge-trapping stacks are etched to form two... Agent: Ingrassia Fisher & Lorenz, P.c.

20080149986 - Zero interface polysilicon to polysilicon gate for flash memory: A system and method are disclosed for processing a zero angstrom oxide interface dual poly gate structure for a flash memory device. An exemplary method can include removing an oxide on a surface of a first poly layer and forming a second poly layer on the first poly layer in... Agent: Amin, Turocy & Calvin, LLP

20080149989 - Flash memory devices and methods for fabricating the same: Flash memory devices and methods for fabricating the same are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a substrate. A trench is etched into the... Agent: Ingrassia Fisher & Lorenz, P.c.

20080149994 - Flash memory with recessed floating gate: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected... Agent: Knobbe Martens Olson & Bear LLP

20080149990 - Memory system with poly metal gate: A memory system includes a substrate, forming an insulator over the substrate, forming a gate layer over the insulator, forming a stability layer over the gate layer, and forming a conductive layer over the stability layer.... Agent: Farjami & Farjami LLP

20080149991 - Non-volatile semiconductor storage device and method for manufacturing the same: A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080149995 - Nonvolatile memory device and methods of fabricating the same: A method of fabricating a nonvolatile memory device including forming a plurality of device isolation layers in a semiconductor substrate to define a plurality of active regions, sequentially depositing an insulating layer and a first conductive layer on the semiconductor substrate, and forming a hard mask pattern on the first... Agent: Lowe Hauptman Ham & Berner, LLP

20080149993 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080149992 - Storage device with multi-level structure: n

20080149996 - Flash nand memory cell array with charge storage elements positioned in trenches: NAND arrays of memory cells are described, as well as methods of forming and using them. Memory cell charge storage devices, such as conductive floating gates, are oriented vertically in trenches, with control gates positioned both in the trenches between charge storage elements and over a horizontal surface between the... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080149997 - Nonvolatile memory device and method of operating the same: Provided are a nonvolatile memory device and a method of operating the same, which have increased operation reliability and which facilitate increased integration. The nonvolatile memory device may include a semiconductor substrate, and at least one charge storage layer may be provided on a semiconductor substrate. At least one control... Agent: Harness, Dickey & Pierce, P.L.C

20080149998 - Flash memory devices and methods of fabricating the same: Flash memory devices and methods for fabricating the same. In one example embodiment, a method of fabricating a flash memory includes various acts. First, a tunnel oxide layer is formed on an active region of a semiconductor substrate. Next, a gate region is formed by sequentially forming a floating gate,... Agent: Workman Nydegger

20080150003 - Electron blocking layers for electronic devices: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and/or hybrid films... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080150004 - Electron blocking layers for electronic devices: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and/or hybrid films... Agent: Nanosys Inc.

20080150001 - Memory device having implanted oxide to block electron drift, and method of manufacturing the same: A memory device includes a substrate, a first gate stack overlying the substrate, a second gate stack overlying the substrate and spaced apart from the first gate stack, an oxide region formed at a first depth within the substrate and between the first and second gate stacks, and an impurity... Agent: Ingrassia Fisher & Lorenz, P.c.

20080150005 - Memory system with depletion gate: A memory system includes a substrate, forming a first insulator layer over the substrate, forming a charge-storage layer over the first insulator layer, forming a second insulator layer over the charge-storage layer, and forming a depletion gate having a depletion phenomenon over the second insulator layer.... Agent: Law Offices Of Mikio Ishimaru

20080150000 - Memory system with select gate erase: A memory system includes a substrate, forming a first insulator over the substrate, forming a charge trap layer, having a composition for setting a predetermined electrical charge level, over the first insulator, and forming a second insulator over the charge trap layer.... Agent: Law Offices Of Mikio Ishimaru

20080150008 - Non-volatile memory devices and methods of manufacturing the same: Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping... Agent: Myers Bigel Sibley & Sajovec

20080149999 - Semiconductor memory comprising dual charge storage nodes and methods for its fabrication: A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion.... Agent: Ingrassia Fisher & Lorenz, P.c.

20080150002 - Simultaneous formation of a top oxide layer in a silicon-oxide-nitride-oxide-silicon (sonos) transistor and a gate oxide in a metal oxide semiconductor (mos): A method for semiconductor fabrication. The method includes providing a silicon substrate and forming a tunnel oxide layer the silicon substrate. Thereafter, a nitride layer is formed over the tunnel oxide layer. The nitride layer and the tunnel oxide layer are etched except where at least one nonvolatile silicon oxide... Agent: Holme Roberts & Owen, LLP

20080150006 - Using implanted poly-1 to improve charging protection in dual-poly process: The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a... Agent: Eschweiler & Associates, Llc National City Bank Building

20080150007 - Variable salicide block for resistance equalization in an array: The present invention facilitates memory devices and operation of dual bit and single bit memory devices by providing systems and methods that employ a salicide block to vary and equalize the resistance of a memory array during fabrication. The present invention includes utilizing a common charge dissipation region to mitigate... Agent: Thomas G. Eschweiler, Esq. Eschweiler & Associates, Llc

20080150010 - Al-doped charge trap layer, non-volatile memory device and methods of fabricating the same: Provided is an aluminum (Al) doped charge trap layer, a non-volatile memory device and methods of fabricating the same. The charge trap layer may include a plurality of silicon nano dots that trap charges and a silicon oxide layer that covers the silicon nano dots, wherein the charge trap layer... Agent: Harness, Dickey & Pierce, P.L.C

20080150009 - Electron blocking layers for electronic devices: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and/or hybrid films... Agent: Nanosys Inc.

20080150011 - Integrated circuit system with memory system: A method for forming an integrated circuit system is provided including forming a substrate having a core region and a periphery region, forming a charge storage stack over the substrate in the core region, forming a gate stack with a stack header having a metal portion over the substrate in... Agent: Farjami & Farjami LLP

20080150012 - Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array: A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access transistor. Insulating trenches are formed between the rows of... Agent: Edell , Shapiro & Finnan , Llc

20080150017 - Semiconductor device: This semiconductor device includes a first conductivity type first semiconductor layer formed on the upper surface of a substrate, a first conductivity type second semiconductor layer formed on the first semiconductor layer, a first conductivity type third semiconductor layer formed on the second semiconductor layer, a second conductivity type fourth... Agent: Ditthavong Mori & Steiner, P.c.

20080150018 - Semiconductor device: A semiconductor device of the present invention includes a p+ type base layer that forms a principal surface, an n+ type source layer formed on the p+ type base layer, a contact hole that is provided to extend through the n+ type source layer, and an electric conductor plug that... Agent: Mcginn Intellectual Property Law Group, Pllc

20080150014 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device includes forming a recess gate over a semiconductor substrate. A gate spacer is formed on a sidewall of the recess gate. The semiconductor substrate in a landing plug contact region is soft-etched to form a recess having a rounded profile. A sidewall spacer... Agent: Marshall, Gerstein & Borun LLP

20080150016 - Semiconductor device and method for manufacturing the same: A semiconductor device including a well region formed in a silicon substrate; a trench exposing a predetermined portion of the uppermost surface of the semiconductor substrate; a body layer formed in the semiconductor substrate at the trench; a device isolation layer formed in the well region; a gate insulating layer... Agent: Sherr & Nourse, Pllc

20080150013 - Split gate formation with high density plasma (hdp) oxide layer as inter-polysilicon insulation layer: This invention discloses method of for manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of... Agent: Bo-in Lin

20080150015 - Transistor having recess channel and fabricating method thereof: A transistor includes a substrate including a trench, an insulation layer filled in a portion of the trench, the insulation layer having a greater thickness over an edge portion of a bottom surface of the trench than over a middle portion of the bottom surface of the trench, a gate... Agent: Morgan Lewis & Bockius LLP

20080150019 - Profiled gate field effect transistor with enhanced high harmonic gain: A field effect transistor that can be operated as a low voltage Class FN radio frequency (RF) amplifier with harmonic tuning is provided. The field effect transistor includes a common electrode, a gate, and multiple separate electrodes. The common electrode can comprise a source or drain, while the separate electrodes... Agent: Hoffman Warnick & D'alessandro, Llc

20080150021 - Trench-gate transistors and their manufacture: A trench-gate transistor (1) has an integral first layer of silicon dioxide (31) which extends from the upper surface (10a) of the semiconductor body (10) over top corners of each cell array trench (20), the integral first layer also providing a thin gate dielectric insulating layer (31A) for a thick... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080150020 - Trenched shield gate power semiconductor devices and methods of manufacture: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region. The active trench, which includes... Agent: Townsend And Townsend And Crew, LLP

20080150022 - Power transistor featuring a variable topology layout: A power transistor comprises a number of groups of gate fingers of various widths and can include uniform or non-uniform pitch. The widths may include any number of different widths. In one embodiment, there are included three widths W1, W2, and W3, in which W3>W2>W1. The groups of gate fingers... Agent: Freescale Semiconductor, Inc. Law Department

20080150023 - Semiconductor memory and manufacturing method thereof: In the semiconductor memory of the present invention, the impurity concentration of the high-doped region in the drain region is lower than that of the high-doped region in the source region. The drain region having a lower impurity concentration suppresses the GIDL leakage. The source region having a higher impurity... Agent: Mcginn Intellectual Property Law Group, Pllc

20080150026 - Metal-oxide-semiconductor field effect transistor with an asymmetric silicide: A MOSFET formed using asymmetric silicidation between source and drain induces higher leakage between the body and the source than between the body and the drain. Implementation of such a MOSFET on an SOI substrate reduces or eliminates floating body effect for consistent on-current and turn-on time. The asymmetry between... Agent: Scully, Scott, Murphy & Presser, P.c.

20080150025 - Methods of making semiconductor-based electronic devices on a wire and by forming freestanding semiconductor structures, and devices that can be made thereby: Various methods for forming active electronic devices, such as field-effect transistors, and devices made using these methods are disclosed. Some of the methods include growing freestanding nano-, micro- and milli-scale semiconducting structures that are used for the active semiconducting channels of the active electronic devices. Others of the methods include... Agent: Downs Rachlin Martin Pllc

20080150024 - Semiconductor device and method of manufacturing a semiconductor device: This invention relates to a semiconductor device (105) and a method of manufacturing this device. A preferred embodiment of the invention is a semiconductor device (105) comprising a silicon semiconductor substrate (110), an oxide layer (115) and an active layer (120). In the active layer, insulating areas (125) and an... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080150027 - Semiconductor device and method of manufacturing the same: It is an object to improve operation characteristics and reliability of a semiconductor device. A semiconductor device which includes an island-shaped semiconductor film having a channel-formation region, a first low-concentration impurity region, a second low-concentration impurity region, and a high-concentration impurity region including a silicide layer; a gate insulating film;... Agent: Fish & Richardson P.c.

20080150031 - Double gate fet and fabrication process: A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulating material, an active layer of crystalline semiconductor material,... Agent: Robert A. Parsons

20080150029 - Memory system with fin fet technology: A method for manufacturing a memory system is provided including forming a charge-storage layer on a first insulator layer including insulating the charge-storage layer from a vertical fin, forming a second insulator layer from the charge-storage layer, and forming a gate over the second insulator includes forming a fin field... Agent: Law Offices Of Mikio Ishimaru

20080150030 - Semiconductor device and manufacturing method of the same: m

20080150028 - Zero interface polysilicon to polysilicon gate for semiconductor device: A system and method are disclosed for processing a zero angstrom oxide interface dual poly gate structure for a semiconductor device. An exemplary method can include removing an oxide from a surface of a first poly layer and forming a second poly layer on the first poly layer in a... Agent: Amin, Turocy & Calvin, LLP

20080150032 - Semiconductor apparatus and manufacturing method thereof: A semiconductor apparatus according to the present invention includes a first well-region and a second well-region in a semiconductor substrate, and a plurality of transistors formed to the second well-region. Further, the semiconductor apparatus includes a through-hole region that is formed so as to pierce through the first well-region and... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080150034 - High voltage cmos device and method of fabricating the same: A method of fabricating a high voltage CMOS device is provided that does not require a separate mask for forming a photo align key when forming a high voltage deep well region. The method includes forming a relatively thick first oxide film pattern exposing a predetermined region of a semiconductor... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080150033 - Scalable strained fet device and method of fabricating the same: A CMOS FET device having an enhanced performance is described by taking advantage of known dual-stress-liner effects and by making use of compressive nitride in an appropriate geometric configuration to induce compressive stress in the n-FET channel, and a tensile stress in the p-FET. The stress enhancement is designed to... Agent: International Business Machines Corporation Dept. 18g

20080150035 - Semiconductor device and manufacturing method thereof: A semiconductor device includes an N-channel transistor having an N-type gate electrode and a P-channel transistor having a P-type gate electrode which are formed on a semiconductor substrate. The P-type gate electrode includes a first silicon layer formed as the lowest layer, and doped with a P-type impurity; a second... Agent: Sughrue Mion, Pllc

20080150036 - Semiconductor device and method of fabricating the same: A semiconductor device includes a semiconductor substrate including an NMOS region and a PMOS region, a gate insulating layer formed on the semiconductor substrate, an NMOS gate formed on the gate insulating layer of the NMOS region, and a PMOS gate formed on the gate insulating layer of the PMOS... Agent: F. Chau & Associates, Llc

20080150037 - Selective sti stress relaxation through ion implantation: A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are... Agent: Horizon Ip Pte Ltd

20080150040 - Field effect transistor: An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes,... Agent: Amin, Turocy & Calvin, LLP

20080150038 - Method of fabricating semiconductor device: Semiconductor devices may be fabricated according to a method that includes steps of forming isolation layers in and a gate electrode on a semiconductor substrate and forming sidewall spacers on both sides of the gate electrode. Ions may be implanted into the semiconductor substrate by using the gate electrode and... Agent: Workman Nydegger

20080150041 - Method of removing a spacer, method of manufacturing a metal-oxide-semiconductor transistor device, and metal-oxide-semiconductor transistor device: A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and... Agent: North America Intellectual Property Corporation

20080150039 - Semiconductor device: A semiconductor device, including: a semiconductor substrate; a first gate insulation film installed on the semiconductor substrate; a first gate electrode installed on the first insulation film; a silicon oxide film, installed beneath a periphery of the first gate electrode, being thicker than the first gate insulation film; a source... Agent: Harness, Dickey & Pierce, P.L.C

20080150042 - Integrated circuit system with memory system: A method for forming an integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a barrier metal layer over the spacer, and forming a metal plug over the outer doped... Agent: Farjami & Farjami LLP

20080150043 - Field effect transistor (fet) having nano tube and method of manufacturing the fet: A transistor includes: a semiconductor substrate; a channel region arranged on the semiconductor substrate; a source and a drain respectively arranged on either side of the channel region; and a conductive nano tube gate arranged on the semiconductor substrate to transverse the channel region between the source and the drain.... Agent: Robert E. Bushnell

20080150044 - Thin-film transistor, thin-film transistor sheet and their manufacturing method: Disclosed are a process of manufacturing a thin-film transistor sheet and a thin-film transistor sheet manufactured by the process, the process comprising the steps of providing a gate busline on a substrate, providing, on the surface of the substrate on the gate busline side, an insulation layer capable of receiving... Agent: Cantor Colburn, LLP

20080150045 - Annealing to improve edge roughness in semiconductor technology: A method for manufacturing a semiconductor device. The method comprises depositing a material layer on a semiconductor substrate and patterning the material layer with a patterning material. Patterning forms a patterned structure of a semiconductor device, wherein the patterned structure has a sidewall with a roughness associated therewith. The method... Agent: Texas Instruments Incorporated

20080150046 - Flash memory and method of fabricating the same: A method of fabricating a flash memory includes forming a first oxide film over a semiconductor substrate, forming a metal film over the first oxide film, forming a photoresist pattern on the metal film, etching the metal film using the photoresist pattern as a mask and forming a metal film... Agent: Sherr & Nourse, Pllc

20080150047 - Gate insulating layer in a semiconductor device and method of forming the same: A gate insulating layer in a semiconductor device and a method of forming the same. In one example embodiment, a gate insulating layer in a semiconductor device includes an oxide layer, a first oxynitride layer formed between a semiconductor substrate and the oxide layer, and a second oxynitride layer formed... Agent: Workman Nydegger

20080150048 - Manufacture method and structure of a nonvolatile memory: The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate dielectric layer so as... Agent: Wpat, Pc

20080150049 - Systems and methods for reducing contact to gate shorts: A method for reducing contact to gate shorts in a semiconductor device and the resulting semiconductor device are described. In one embodiment, a gate is formed on a substrate, a contact is formed on the gate and the substrate, and an insulator is formed between the gate and the contact.... Agent: Jennifer Hayes Blakely, Sokoloff, Taylor & Zafman LLP

20080150050 - Information sensing device and method of manufacturing the same: An information sensing device includes a substrate, an information sensing chip mounted on and electrically connected to the substrate, at least one electroconductive structure mounted on and electrically connected to the substrate and disposed on one side of the information sensing chip, and a molding compound material partially surrounding the... Agent: Joe Mckinney Muncy

20080150053 - Image sensor and fabricating method thereof: An image sensor and fabricating method thereof are provided. The image sensor can include a color filter on a semiconductor substrate, a microlens on the color filter layer, and a carbon-doped low temperature oxide layer on the microlens.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080150052 - Image sensor and manufacturing method thereof: An image sensor and fabricating method thereof are provided. A multi-layered interlayer insulating layer is formed on a substrate including a photodiode, and a metal line is formed in the interlayer insulating layer, such that the metal line passes through the interlayer insulating layer. A conductive barrier layer is formed... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080150055 - Image sensor and method for fabricating the same: An image sensor can include a plurality of photodiodes and a plurality of transistors formed in a semiconductor substrate; a first interlayer insulating layer formed over the semiconductor substrate; a plurality of metal lines formed over the first interlayer insulating layer, electrically connected with the photodiodes and the transistors; a... Agent: Sherr & Nourse, Pllc

20080150051 - Image sensor and method for manufacturing the same: An image sensor and method of manufacturing thereof are provided. In an embodiment, an image sensor can include a photodiode on a substrate, an interlayer dielectric formed on the substrate, an insulating layer micro-lens on the interlayer dielectric, and an organic micro-lens on the insulating layer micro-lens.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080150054 - Image sensor and method for manufacturing the same: An image sensor and a method for manufacturing the same. In one example embodiment of the invention, an image sensor includes a semiconductor substrate in which a plurality of photodiodes are formed, an insulating layer formed on the semiconductor substrate, a color filter layer formed on the insulating layer, a... Agent: Workman Nydegger

20080150058 - Image sensor and method for manufacturing the same: A method for manufacturing an image sensor that can include forming a pad electrode over a semiconductor substrate; forming a protective layer over the pad electrode; forming a via hole through the protective layer to expose a portion of the uppermost surface of the pad electrode; and then forming a... Agent: Sherr & Nourse, Pllc

20080150059 - Image sensor and method for manufacturing the same: An image sensor and a manufacturing method thereof are provided. An insulating layer structure can be formed on a photodiode region and can include a trench. A color filter structure can be formed on the insulating layer structure having color filters corresponding to photodiodes in the photodiode region. The upper... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080150060 - Image sensor and method for manufacturing the same: A method for manufacturing a sensor image may include forming a pixel array including a photodiode structure and an insulating film structure in an active area of a semiconductor substrate; forming a metal pad on the insulating film structure; forming a dielectric and/or etch stop film on the metal pad... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080150057 - Image sensor and method of manufacturing the same: An image sensor and a method of manufacturing the same are disclosed. An image sensor is formed by forming a photoelectric transformation element at a front surface of a semiconductor substrate in an active pixel sensor region and in an optical black region of the semiconductor substrate, subjecting a surface... Agent: Marger Johnson & Mccollom, P.c.

20080150062 - Image sensor fabricating method: An image sensor fabricating method includes forming a photoresist layer on a color filter layer, exposing the photoresist layer to form a pattern having a predetermined depth from a top surface of the photoresist layer, heat-treating the photoresist layer to form microlens precursors, and etching the microlens precursors to form... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080150056 - Method for manufacturing image sensor: A method is provided for manufacturing an image sensor. In the method, a plurality of wires and dielectric films are formed on a substrate including a photodiode. A color filter is formed on the dielectric film. A micro lens is formed on the color filter. A protection film is coated... Agent: Workman Nydegger

20080150063 - Process for making contact with and housing integrated circuits: A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by... Agent: Charles N. J. Ruggiero Ohlandt, Greeley, Ruggiero & Perle, L.l.p.

20080150061 - Producing optical microlenses on a semiconductor device: A system and method for producing optical microlenses on a front layer of a semiconductor device. The system and method includes depositing a final layer of a suitable material on a front layer of a semiconductor device. The system and method could also include producing crossed grooves in the final... Agent: Docket Clerk

20080150064 - Plastic electronic component package: A plastic package for an image sensor or other electronic component which comprises a plastic body, preferably of LCP material, molded around a leadframe and defining a cavity in which the image sensor is to be disposed. A lid assembly is provided having a transparent glass lid retained in a... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP

20080150065 - Semiconductor package: A semiconductor package has a substrate having a first heat transfer path for transferring heat from an optical functional element to a back surface of the substrate, a first heat dissipation unit dissipating the transferred heat therefrom, a second heat transfer path for transferring heat generated in an internal cavity... Agent: Rankin, Hill & Clark LLP

20080150066 - Vertical type cmos image sensor and fabricating method thereof: A vertical-type CMOS image sensor and a fabricating method thereof by which capacitance between an upper line and a dark shield layer can be effectively reduced. The vertical-type CMOS image sensor can include an inter-metal dielectric layer having a plurality of metal lines formed over a semiconductor substrate; a passivation... Agent: Sherr & Nourse, Pllc

20080150067 - Image sensor and method of manufacturing the same: An image sensor including a first epitaxial layer formed over a semiconductor substrate; first photodiodes formed spaced apart in the first epitaxial layer; a first isolation region electrically isolating the first photodiodes from each other; a second epitaxial layer formed over the first epitaxial layer; second photodiodes formed spaced apart... Agent: Sherr & Nourse, Pllc

20080150068 - Image sensor ic: Polycrystalline silicon thin films are each fixed to the same potential and are each formed under the protective film of each of a plurality of pixel regions for receiving red light, a plurality of pixel regions for receiving green light, and a plurality of pixel regions for receiving blue light,... Agent: Bruce L. Adams, Esq. Adams & Wilks

20080150069 - Semiconductor photodiode and method of making: A semiconductor photodiode (18) is formed as a pn-junction between a region (2) of a first conductivity type and a region (6) of a second conductivity type. The region (6) of the second conductivity type is approximately hemispherical. A mini guard ring (8), i.e. a ring of the second conductivity... Agent: Thelen Reid Brown Raysman & Steiner LLP

20080150070 - Image sensor ic: Provided is an image sensor IC in which a conductive material transmissive to light, which is fixed to the same potential, is formed under a protection film in a plurality of pixel regions. The conductive material transmissive to light for potential fixation is formed in each pixel, has a narrow... Agent: Bruce L. Adams, Esq. Adams & Wilks

20080150071 - Pinned photodiode with high storage capacity, method of manufacture and image sensor incorporating same: In a photodiode formed by a region of a first type inside a region of a second type, of a semiconductor substrate, the region of the first type includes a first zone including a dopant of the first type having a first concentration and a first depth. The region of... Agent: Hogan & Hartson LLP

20080150072 - Integrated circuit having tensile and compressive regions: An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active... Agent: Freescale Semiconductor, Inc. Law Department

20080150073 - Integrated circuit including a charge compensation component: A charge compensation component having a drift path between two electrodes, an electrode and a counterelectrode, and methods for producing the same. The drift path has drift zones of a first conduction type and charge compensation zones of a complementary conduction type with respect to the first conduction type. A... Agent: Dicke, Billig & Czaja

20080150074 - Integrated circuit system with isolation: An integrated circuit system is provided including providing a substrate, forming an isolation structure base in the substrate without removal of the substrate, and forming a first transistor in the substrate next to the isolation structure base.... Agent: Law Offices Of Mikio Ishimaru

20080150075 - Method and resultant structure for floating body memory on bulk wafer: A method for making floating body memory cells from a bulk substrate. A thin silicon germanium and overlying silicon layers are formed on the bulk substrate. Anchors and a bridge are formed to support the silicon layer when the silicon germanium layer is etched so that it can be replaced... Agent: Intel/blakely

20080150076 - Electrical fuse, semiconductor device having the same, and method of programming and reading the electrical fuse: Provided are an electrical fuse, a semiconductor device having the same, and a method of programming and reading the electrical fuse. The electrical fuse includes first and second anodes disposed apart from each other. A cathode is interposed between the first and second anodes. A first fuse link couples the... Agent: F. Chau & Associates, Llc

20080150078 - Integrated dram process/structure using contact pillars: A capacitor under bitline DRAM memory cell and method for its fabrication provides a high density memory cell with the capacitor formed in the PMD layer. The memory cell utilizes several variations of storage contact pillar structures as, for example, a storage plate of the memory cell capacitor formed within... Agent: Texas Instruments Incorporated

20080150077 - Semiconductor device and fabricating method thereof: Disclosed is a semiconductor device comprising a first substrate having a through-electrode and a capacitor cell, a second substrate having a circuit unit, and a connection electrode electrically connecting the capacitor cell with the circuit unit.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080150079 - Capacitor in semiconductor device and manufacturing method: The capacitor in a semiconductor device includes a substrate, a lower electrode formed over the substrate, a diffusion barrier formed over the lower electrode, a plurality of agglomerates formed over the diffusion barrier, a dielectric layer formed over the surface of the agglomerates to form an uneven surface, and an... Agent: Sherr & Nourse, Pllc

20080150080 - Protective diode for protecting semiconductor switching circuits from electrostatic discharges: The invention relates to an arrangement of a protective diode for protecting semiconductor switching circuits from electrostatic discharges. The aim of the invention is to create an arrangement by which means improved ESD protection with optimum chip surface use and an improved latch-up behaviour can be achieved. To this end,... Agent: Heslin Rothenberg Farley & Mesiti Pc

20080150082 - Power transistor featuring a double-sided feed design and method of making the same: A power transistor (210) comprises a plurality of unit cell devices (212), a base contact configuration, an emitter contact configuration, and a collector contact configuration. The plurality of unit cell devices is arranged along an axis (194), each unit cell device including base (80), emitter (82), and collector (84) portions.... Agent: Freescale Semiconductor, Inc. Law Department

20080150081 - Semiconductor device: A method comprising providing a substrate and forming a device on the substrate, wherein forming the device includes printing at least one region of inorganic semiconductor on the substrate.... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20080150083 - Semiconductor device and method of manufacturing the same: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By... Agent: Fish & Richardson P.c.

20080150084 - Phosphorus-stabilized transition metal oxide diffusion barrier: Method for controlling glass formation on a semiconductor substrate. By using a doped diffusion barrier material, such as a transition metal oxide paste, the subsequent diffusion of glass forming elements into the substrate may be stabilized and controlled.... Agent: Peacock Myers, P.c.

20080150085 - Gruppe-iii-nitrid-halbleiterbauelement mit hoch p-leitfahiger schicht: Group III nitride layers which are grown with standard c-axis orientation have a maximum hole concentration by means of magnesium doping of around 5×1017 cm−3. This restriction of the doping results in a limitation of the possible component power. The object is to achieve a higher hole concentration and thus... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20080150086 - Nitride based semiconductor device and process for preparing the same: A process for preparing a nitride based semiconductor device in accordance with the present invention comprises growing a high temperature AlN single crystal layer on a substrate; growing a first GaN layer on the high temperature AlN single crystal layer in a first V/III ratio, under a first pressure of... Agent: Mcdermott Will & Emery LLP

20080150087 - Semiconductor chip shape alteration: The invention is directed to an improved semiconductor chip that reduces crack initiation and propagation into the active area of a semiconductor chip. A semiconductor wafer includes dicing channels that separate semiconductor chips and holes through a portion of a semiconductor chip, which are located at the intersection of the... Agent: International Business Machines Corporation Dept. 18g

20080150088 - Method for incorporating existing silicon die into 3d integrated stack: An apparatus including a first die including a plurality of conductive through substrate vias (TSVs); and a plurality of second dice each including a plurality of contact points coupled to the TSVs of the first die, the plurality of second dice arranged to collectively include a surface area approximating a... Agent: Intel/blakely

20080150089 - Semiconductor device having through vias and method of manufacturing the same: A method of fabricating a semiconductor device is provided. The method may include forming an insulating layer on a wafer. The wafer may have an active surface and an inactive surface which face each other, and the insulating layer may be formed on the active surface. A pad may be... Agent: Harness, Dickey & Pierce, P.L.C

20080150090 - Damascene replacement metal gate process with controlled gate profile and length using si1-xgex as sacrificial material: A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered... Agent: Lsi Corporation

20080150091 - Multiple patterning using patternable low-k dielectric materials: A method of double patterning a semiconductor structure with a single material which after patterning becomes a permanent part of the semiconductor structure. More specifically, a method to form a patterned semiconductor structure with small features is provided which are difficult to obtain using conventional exposure lithographic processes. The method... Agent: Scully, Scott, Murphy & Presser, P.c.

20080150092 - Reduced leakage within a semiconductor device: Various embodiments of the present invention relate to systems, devices, and methods for treating a semiconductor substrate, such as a silicon wafer, in order to reduce current leakage therein. A semiconductor substrate is provided a plurality of heating treatments that create a denuded zone adjacent to a surface of the... Agent: North Weber & Baugh LLP

20080150094 - Flip chip shielded rf i/o land grid array package: A novel apparatus and method for providing a radio frequency (“RF”) input/output (“I/O”) land grid array (“LGA”) package structure. The package structure comprises grounded shield rings surrounding free-standing RF I/O interconnects. The free-standing RF I/O interconnects eliminate long leads and the shield rings provide ground protection thereby minimizing losses, inductance,... Agent: Tyco Technology Resources

20080150096 - Multi-chip module, manufacturing method thereof, mounting structure of multi-chip module, and manufacturing method of mounting structure: With respect to the central plane which horizontally cuts a multi-chip module, constituent materials of the same type are disposed in a plane symmetrical manner. Each of an upper structure and a lower structure, which sandwich the central plane which horizontally cuts the multi-chip module, includes a base and electronic... Agent: Nixon & Vanderhye, Pc

20080150095 - Semiconductor device package: A semiconductor device package includes a semiconductor device mounted to a substrate, a wall erected around the semiconductor device with a height taller than the height of the semiconductor device, at least one metal member provided in the wall or against the wall; and a lid secured to the metal... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20080150093 - Shielded stacked integrated circuit package system: A shielded stacked integrated circuit package system is provided including forming a first integrated circuit structure having a first substrate and a first integrated circuit die; mounting a shield over the first substrate and the first integrated circuit die; mounting a second integrated circuit structure having a second substrate and... Agent: Law Offices Of Mikio Ishimaru

20080150097 - Semiconductor device with reduced power noise: Provided are a semiconductor device with reduced power noise, which can be used in a high-speed device with an operating frequency of at or above about 1 GHz and does not have any spatial restriction due to signal patterns or other structures. The semiconductor device includes a power panel, an... Agent: Mills & Onello LLP

20080150099 - Local control of underfill flow on high density packages, packages and systems made therewith, and methods of making same: An article includes a mounting substrate, a passive component site on the mounting substrate, and an active component site on the mounting substrate. The article also includes a fluid flow barrier disposed local to the passive component site and spaced apart from the active component site. The fluid flow barrier... Agent: Blakely Sokoloff Taylor & Zafman

20080150098 - Multi-chip package: A multi-chip package including a carrier, a first chip, a second chip and a first conductive layer is provided. The first chip is disposed on the carrier and is electrically connected to the carrier through at least one first wire. The second chip is disposed on the first chip and... Agent: Bacon & Thomas, Pllc

20080150100 - Ic package encapsulating a chip under asymmetric single-side leads: A multi-chip IC package encapsulates a chip under asymmetric longer single-side leads. The package mainly comprises a plurality of leads that have asymmetric length at two sides of a leadframe, a plurality of die-attach tape strips, a first chip having a plurality of single-side pads under the longer side leads,... Agent: Troxell Law Office Pllc

20080150101 - Microelectronic packages having improved input/output connections and methods therefor: A microelectronic assembly includes a microelectronic package, such as a semiconductor package, having a plurality of conductive posts projecting from an exposed surface thereof. The assembly includes a microelectronic element, such as a dielectric film having a first surface and an array of contact pads accessible at the first surface.... Agent: Tessera Lerner David Et Al.

20080150102 - Semiconductor device and manufacturing method of semiconductor device: An electrical connection inside a semiconductor device is established by lead frames formed of plural conductor plates. The lead frames are disposed three-dimensionally so that the respective weld parts thereof are exposed toward a laser light source used in the laser welding. The laser welding is then performed by irradiating... Agent: Rossi, Kimms & Mcdowell LLP.

20080150107 - Flip chip in package using flexible and removable leadframe: A method for forming semiconductor packages is disclosed. The method involves providing a support substrate and forming at least one conductive layer thereon. The method also includes coupling the at least one conductive layer to a support face of a film substrate for securing the at least one conductive layer... Agent: Jianq Chyun Intellectual Property Office

20080150106 - Inverted lf in substrate: A semiconductor package, and method of making a semiconductor package, with a plurality of dies, wherein one die is attached to an inverted lead frame and another die is attached to a substrate. The leadframe is then attached to the substrate. More specifically, the semiconductor package includes a substrate, a... Agent: Sughrue Mion, Pllc

20080150104 - Leadframe with different topologies for mems package: A package for a micro-electromechanical (MEMS) device is described. A premolded leadframe base has opposing top and bottom surfaces. Each surface is defined by a topology having at least one electrically conductive portion and at least one electrically non-conductive portion, and the topology of the top surface differs from the... Agent: Hamilton, Brook, Smith & Reynolds, P.c.

20080150103 - Multi-die ic package and manufacturing method: A method for of manufacturing integrated circuit packages and a multi-chip integrated circuit package are disclosed. According to the method, a first die is attached onto a first side of a set of leads of a leadframe, and an adhesive is applied onto the set of leads at a second... Agent: Martine Penilla & Gencarella, LLP

20080150105 - Power semiconductor component stack using lead technology with surface-mountable external contacts and a method for producing the same: A power semiconductor component stack, using lead technology with surface-mountable external contacts, includes at least two MOSFET power semiconductor components each having a top side and an underside. The underside includes: a drain external contact area, a source external contact area and a gate external contact area. The top side... Agent: Edell , Shapiro & Finnan , Llc

20080150108 - Semiconductor package and method for manufacturing same: A semiconductor package includes: a semiconductor chip and a plurality of frames. A plurality of electrodes are formed on a surface of the semiconductor chip. The plurality of frames are connected to the plurality of electrodes. The plurality of frames are formed by dividing one conductive plate by etching.... Agent: Amin, Turocy & Calvin, LLP

20080150109 - Electronic component: An electronic component has a substrate made of silicon in which a flow path for circulating a refrigerant is formed, a conductive pattern formed on a first principal surface of the substrate, a via plug penetrating the substrate and also connected to the conductive pattern, and an elastically deformable external... Agent: Rankin, Hill & Clark LLP

20080150110 - Semiconductor package structure and method for manufacturing the same: A semiconductor package structure and a method for manufacturing the same are disclosed. The semiconductor package structure includes a substrate, an interposer (such as a circuitry laminate), a metal layer formed on the interposer, a first chip and a second chip, wherein the interposer is disposed on the substrate and... Agent: Joe Mckinney Muncy

20080150113 - Enabling uniformity of stacking process through bumpers: A stacked semiconductor chip assembly is disclosed, as are different embodiments relating to same. The stacked chip assembly preferably includes a plurality of units which include a substrate with microelectronic components mounted on each. The individual units desirably are thin and directly abut one another so as to provide a... Agent: Tessera Lerner David Et Al.

20080150111 - Memory device: wherein each die pad of a stacked memory die which connects said memory die individually to said control circuit comprises an increased distance (di) in comparison to die pads of said stacked memory die which connect said stacked memory die in parallel with corresponding die pads of other stacked memory... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20080150115 - Semiconductor device: An electronic component such as a semiconductor device is provided which is capable of preventing wiring breakage in a stress concentration region of surface layer wiring lines. In a semiconductor device provided with a support ball (5), no ordinary wiring line is formed in a region (7(A)) in the vicinity... Agent: Sughrue Mion, Pllc

20080150116 - Semiconductor package on package having plug-socket type wire connection between packages: A semiconductor package on package includes a tower package, an upper package stacked over the lower package, a plug wire combined to any one of an upper portion of the tower package and a lower portion of the upper package, and a socket wire combined to any one of the... Agent: F. Chau & Associates, Llc

20080150117 - Stacked-type semiconductor device package: A stacked-type semiconductor device package is provided. The stacked-type semiconductor device package includes a plurality of stacked semiconductor chip packages with joining electrodes exposed on sides of the semiconductor chip packages and a flexible printed circuit board (flexible PCB) on which the stacked semiconductor chip packages are mounted. The flexible... Agent: Marger Johnson & Mccollom, P.c.

20080150114 - Stacking packages with alignment elements: A stacked microelectronic assembly is disclosed, as are different embodiments related to the same. The stacked microelectronic assembly includes a plurality of stackable microelectronic units each having a semiconductor element mounted on a substrate, and also includes alignment elements which align and stack the units one atop another. The aligned... Agent: Tessera Lerner David Et Al.

20080150112 - Thermal spacer for stacked die package thermal management: In some embodiments, a thermal spacer for stacked die package thermal management is presented. In this regard, an apparatus is introduced having a top integrated circuit die, a bottom integrated circuit die, and a thermal spacer between the top and bottom integrated circuit dice, the thermal spacer comprising a heat... Agent: Intel Corporation C/o Intellevate, Llc

20080150118 - Method of manufacturing a semiconductor packages and packages made: The flexible package (100) has between a first (1) and a second side (2) a semiconductor device (20) with a thinned back substrate (10) and an interconnect structure. Contact means (31,33) for external contact and a first resin layer (52) are present at the first side (2) of the package... Agent: Philips Intellectual Property & Standards

20080150119 - Integrated circuit package system employing mold flash prevention technology: An integrated circuit package system that includes: providing a support structure including an integrated circuit and an electrical contact adjacent thereto; providing a first mold having a first cavity with a projection and a recess for collecting flash; engaging the first mold on the support structure with the first cavity... Agent: Law Offices Of Mikio Ishimaru

20080150120 - Semiconductor device and method of producing the same: In a semiconductor chip, a first semiconductor chip 21 is provided on a chip-mounting component 11, and bonding wires 36 connected to electrode pads 21E of the first semiconductor chip 21 are fixed by being covered with a first insulating adhesive 31. A second semiconductor chip 22 is mounted by... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080150121 - Microelectronic assemblies having compliancy and methods therefor: A method of making a microelectronic assembly includes providing a semiconductor wafer having contacts accessible at a first surface, forming compliant bumps over the first surface and depositing a sacrificial layer over the compliant bumps. The method includes grinding the sacrificial layer and the compliant bumps so as to planarize... Agent: Tessera Lerner David Et Al.

20080150122 - Routing density through asymmetric array of vias: Methods and apparatus to improve routing density through asymmetric array of vias are described. In one embodiment, a plurality of vias may be asymmetrically distributed relative to the distribution of a plurality of pads. Other embodiments are also described.... Agent: Caven & Aghevli C/o Intellevate, Llc

20080150123 - Semiconductor package with rigid and flexible circuits: The semiconductor package includes a rigid circuit board substrate having a substrate first side and an opposing substrate second side. The package also includes multiple electrical contacts coupled to the substrate at the substrate first side. An adhesive directly contacts the substrate second side. A semiconductor device directly contacts the... Agent: Morgan Lewis & Bockius LLP/rambus Inc.

20080150124 - Semiconductor device comprising a plastic housing, a semiconductor chip and an interposer, and method for producing the same: A semiconductor device includes a plastic housing and a semiconductor chip, wherein the semiconductor chip includes an active top side and a rear side. An interposer is arranged on the active top side of the semiconductor chip. At least a portion of the interposer is embedded into the plastic housing,... Agent: Edell, Shapiro & Finnan, Llc

20080150126 - Light emitting diode module with heat dissipation device: A light emitting diode (LED) module with a heat dissipation device includes a plurality of LEDs supported by the heat dissipation device. The heat dissipation device includes a plurality of heat spreaders each supporting at least one LED, a base supporting the heat spreaders, and a heat pipe sandwiched between... Agent: Pce Industry, Inc. Att. Cheng-ju Chiang

20080150127 - Microelectronic package, method of manufacturing same, and system containing same: A microelectronic package includes a substrate (110, 210, 310, 410, 510, 731), a die (120, 220, 320, 420, 520, 732), and a heat spreading region (130, 230, 330, 430, 530, 733). The die, which has an active side (121, 221, 321, 421, 521) and a passive side (122, 222, 322,... Agent: Intel Corporation C/o Intellevate, Llc

20080150125 - Thermal management of dies on a secondary side of a package: An apparatus including a first die mounted on a primary side of an electronic package and a second die mounted on a secondary side of the electronic package between the electronic package and a printed circuit board. The apparatus further comprising a thermal component thermally connected to the second die... Agent: Intel/blakely

20080150128 - Heat dissipating chip structure and fabrication method thereof and package having the same: A heat dissipating chip structure and a fabrication method thereof and a package having the same are provided. The fabrication method mainly includes: forming a metal layer on an non-active surface of a wafer having a plurality of chips with the metal layer thereof providing a better solder bonding with... Agent: Edwards Angell Palmer & Dodge LLP

20080150129 - Transceiver device: A transceiver device includes a dielectric substrate, a ring member that is welded onto the dielectric substrate thereby forming a plurality of cavities, a cover that is welded onto the ring member, and at least one semiconductor device that is arranged in each of the cavities. The ring member has... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080150131 - Semiconductor device manufactured by reducing hillock formation in metal interconnects: A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon... Agent: Texas Instruments Incorporated

20080150130 - Structure of dielectric layers in built-up layers of wafer level package: The present invention provides a structure of elastic dielectric layers with certain through holes adjacent to the angle of a RDL of WLP to absorb the stress. The elastic dielectric layer is made from silicone based materials with specific range of CTE, elongation rate and hardness, which can improve the... Agent: Kusner & Jaffe Highland Place Suite 310

20080150133 - Semiconductor chip assembly and fabrication method therefor: A semiconductor chip dual-sided assembly which has a higher degree of reliability of connections between semiconductor chips and a circuit substrate is realized. This is achieved by the assembly including a plurality of upper side pads (2a) provided on a substrate upper surface (1a); a plurality of lower side pads... Agent: Greenblum & Bernstein, P.L.C

20080150134 - Semiconductor device: A semiconductor device of the present invention includes a semiconductor chip; an internal pad for electrical connection formed on a surface of the semiconductor chip; a stress relaxation layer formed on the semiconductor chip and having an opening for exposing the internal pad; an under-bump layer formed so as to... Agent: Rabin & Berdo, Pc

20080150132 - Stack up pcb substrate for high density interconnect packages: An apparatus including a circuit device and a composite package substrate. A system including a computing device including a microprocessor, the microprocessor coupled to a printed circuit board through a first substrate and a second substrate, wherein the second substrate includes a thickness that is less that a thickness of... Agent: Intel/blakely

20080150135 - Mounting method for semiconductor parts on circuit substrate: A method for mounting a semiconductor part on a circuit substrate is provided, which includes preparing the semiconductor part having a surface thereof provided with a plurality of stud-bumps, preparing a solder substrate having a surface thereof on which solid-solders corresponding to respective ones of the plurality of stud-bumps are... Agent: Ibm Microelectronics Intellectual Property Law

20080150136 - Integrated circuit having a metal element: An integrated circuit is disclosed. The integrated circuit includes a substrate, a metal element, the metal element being arranged on the substrate and including a metal material. A composite element is located over to the metal element, the composite element including the metal material and an additive material.... Agent: Dicke, Billig & Czaja

20080150137 - Interconnect capping layer and method of fabrication: The present invention relates to an interconnect capping layer and a method of fabricating a capping layer for an interconnect. In particular, but not exclusively, the invention relates to a capping layer for a copper interconnect used to interconnect elements in an integrated circuit. Embodiments of the invention provide a... Agent: Horizon Ip Pte Ltd

20080150138 - Process integration scheme to lower overall dielectric constant in beol interconnect structures: Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in... Agent: Carr & Ferrell LLP

20080150139 - Semiconductor device and method of manufacturing the same: Disclosed are a semiconductor device and a method for manufacturing the same, capable of improving the performance of a barrier and inhibiting a discontinuous step coverage and an overhang. The semiconductor device includes an interlayer dielectric layer having a via hole disposed on a semiconductor substrate, a first layer disposed... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080150140 - Semiconductor device and method of manufacturing the same: Aimed at improving adhesiveness between upper and lower interconnects in semiconductor devices, a semiconductor device of the present invention includes a second dielectric multi-layered film formed on a substrate, and containing a lower interconnect; a first dielectric multi-layered film formed on the second dielectric multi-layered film, and having a recess;... Agent: Young & Thompson

20080150141 - Manufacturing method for an integrated semiconductor structure and corresponding semiconductor structure: providing a semiconductor substrate with a main surface; forming a wiring metal layer above said main surface; forming a doped getter layer on said wiring metal layer; and forming at least one additional wiring metal layer on said doped getter layer. The present invention also provides a corresponding integrated semiconductor... Agent: Eschweiler & Associates Llc

20080150142 - Multilevel wiring, laminated aluminum wiring, semiconductor device and manufacturing method of the same: A contact plug is formed in a contact hole which is formed in an interlayer insulation film and then a barrier metal layer and a main wiring layer, which form a wiring layer in all, are formed on both of the interlayer insulation film and the contact plug. After a... Agent: Mcginn Intellectual Property Law Group, Pllc

20080150143 - Semiconductor device pad having the same voltage level as that of a semiconductor substrate: A semiconductor device pad is configured to have the same voltage level as that of a semiconductor substrate. The pad includes a semiconductor substrate having a junction area doped with a high concentration of impurity ions, a polylayer portion at least a portion of which is electrically connected to the... Agent: Volentine & Whitt Pllc

20080150144 - Guard ring in semiconductor device and fabricating method thereof: A guard ring in a semiconductor device can include a plurality of first latticed metal plugs formed over a semiconductor substrate; a plurality of first latticed metal layer patterns formed over the plurality of first latticed metal plugs; a plurality of second latticed metal plugs formed over the plurality of... Agent: Sherr & Nourse, Pllc

20080150145 - Adhesion and electromigration performance at an interface between a dielectric and metal: Interconnect structures having improved adhesion and electromigration performance and methods to fabricate thereof are described. A tensile capping layer is formed on a first conductive layer on a substrate. A compressive capping layer is formed on the tensile capping layer. Next, an interlayer dielectric layer is formed on the compressive... Agent: Intel/blakely

20080150147 - High surface area aluminum bond pad for through-wafer connections to an electronic package: A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads.... Agent: Scully, Scott, Murphy & Presser, P.c.

20080150146 - Semiconductor device and method of fabricating the same: A semiconductor device such as a CMOS image sensor and a method of fabricating the same, in which a stable alignment mark is formed. The semiconductor device includes an isolation layer formed in a scribe lane region of a semiconductor substrate and having a groove, an insulating layer having a... Agent: Sherr & Nourse, Pllc

20080150148 - Methods of patterning a deposit metal on a substrate: An article includes a polymeric film having a major surface, a discontinuous layer of a catalytic material on the major surface, and a metal pattern on the catalytic material. The discontinuous layer of catalytic material has an average thickness of less than 200 angstroms. Methods of forming these articles are... Agent: 3m Innovative Properties Company

20080150149 - Redundant micro-loop structure for use in an intergrated circuit physical design process and method of forming the same: An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level... Agent: Schmeiser, Olsen & Watts

20080150152 - Carbon nanotube-based interconnection element: The upper conductor (220) forms a bridge above the lower conductor (210) and the cavity (240) forms, at a level where it emerges on the upper conductor (243), two vents on both sides of the latter.... Agent: Thelen Reid Brown Raysman & Steiner LLP

20080150151 - Multilayered interconnect structure and method for fabricating the same: In the multilayered interconnect structure, an upper-layer interconnect is formed in an interlayer dielectric film formed on a lower-layer interconnect of copper, and the lower-layer interconnect and the upper-layer interconnect of copper are connected to each other through a via formed in the interlayer dielectric film. A layer of the... Agent: Mcdermott Will & Emery LLP

20080150153 - Single mask via method and device: A method of connecting elements such as semiconductor devices and a device having connected elements such as semiconductor devices. A first element having a first contact structure is bonded to a second element having a second contact structure. A single mask is used to form a via in the first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080150150 - System and method for filling vias: System and method for filling vias in integrated circuits A preferred embodiment comprises forming a spacer layer on a substrate, forming a via with walls and a bottom in the spacer layer, depositing a conformal conductive layer on the spacer layer and on the walls and bottom of the via,... Agent: Texas Instruments Incorporated

20080150154 - Method for fabricating a circuit: A method for fabricating a circuit arrangement is provided. One embodiment provides a base layer, whereby the first layer is disposed on the base layer having at least one channel, whereby the first layer is fabricated from an electrically isolating material, whereby the base layer at least partially covers the... Agent: Dicke, Billig & Czaja

20080150158 - Integrated circuit package system with offset stacked die: An integrated circuit package system comprising: providing a first integrated circuit die; attaching a second integrated circuit die over the first integrated circuit die and offset from the first integrated circuit die in substantially one dimension; forming an interdie layer over the second integrated circuit die; attaching a third integrated... Agent: Law Offices Of Mikio Ishimaru

20080150157 - Semiconductor device and manufacturing method of the same: A semiconductor device, includes a wiring board; a first semiconductor element mounted on the wiring board; a second semiconductor element mounted on the first semiconductor element so that a position of the second semiconductor element is shifted relative to a position of the first semiconductor element; wherein a part of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080150156 - Stacked die package with stud spacers: A system may include a first integrated circuit die comprising a first upper surface, an integrated circuit package substrate comprising a second upper surface, a wire coupled to the a first upper surface and to the second upper surface, a plurality of elements coupled to the first upper surface, and... Agent: Buckley, Maschoff & Talwalkar Llc

20080150155 - Stacked-die packages with silicon vias and surface activated bonding: A system may include a first integrated circuit die including a plurality of silicon vias and a first surface activated bonding site coupled to the plurality of silicon vias, and a second integrated circuit die including a second surface activated bonding site coupled to the first surface activated bonding site.... Agent: Buckley, Maschoff & Talwalkar Llc

20080150160 - Dicing technique for flip-chip usp wafers: A method and a fused compound wafer including at least one first MEMS sensor and at least second MEMS sensor includes a first wafer. The first wafer includes at least one first MEMS sensor first subassembly and at least one second MEMS sensor first subassembly. A second wafer includes at... Agent: Honeywell International Inc. Patent Services Ab-2b

20080150162 - Semiconductor device: A semiconductor device having a semiconductor chip in which an electrode pad is formed on the side of a device surface, and an interposer in which flip-chip mounting of the semiconductor chip is performed by the electrode pad, wherein a flow path for circulating a refrigerant for cooling the semiconductor... Agent: Rankin, Hill & Clark LLP

20080150161 - Semiconductor device and method of protecting passivation layer in a solder bump process: A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer is formed over the substrate and intermediate conduction layer. An adhesive layer is formed... Agent: Quarles & Brady LLP

20080150159 - Semiconductor package with perforated substrate: A semiconductor package includes a substrate and a semiconductor chip which includes an active surface with a plurality of chip contact areas. The chip is electrically connected to the substrate. The substrate includes a sheet of core material, a plurality of upper conducting traces and upper contact pads on its... Agent: Dicke, Billig & Czaja

20080150164 - Carrier structure embedded with semiconductor chips and method for manufacturing the same: Carrier structure embedded with semiconductor chips and method for manufacturing the same are disclosed. The carrier structure comprises a metal plate and pluralities of semiconductor chips. An adhesive material is disposed on both surfaces of the metal plate, and pluralities of cavities are formed through the metal plate. The semiconductor... Agent: Bacon & Thomas, Pllc

20080150163 - Mounting structure for semiconductor element: A mounting structure for a semiconductor element is disclosed. The semiconductor element is bonded to a die pad through an adhesive film, which is formed by applying a predetermined amount of a paste adhesive onto the surface of the die pad and placing the semiconductor element on the die pad... Agent: Staas & Halsey LLP

20080150166 - Method for forming metal wiring in semiconductor device: Embodiments relate to a metal wiring in a semiconductor device that may be formed by depositing a metal layer on a semiconductor substrate, and performing ion bombardment on a surface of the metal layer to thereby forming the metal wiring. According to embodiments, the metal layer may be etched and... Agent: Sherr & Nourse, Pllc

20080150165 - Selective processing of semiconductor nanowires by polarized visible radiation: Methods, systems, and apparatuses for annealing semiconductor nanowires and for fabricating electrical devices are provided. Nanowires are deposited on a substrate. A plurality of electrodes is formed. The nanowires are in electrical contact with the plurality of electrodes. The nanowires are doped. A polarized laser beam is applied to the... Agent: Fiala & Weaver, P.l.l.c. C/o Intellevate

20080150167 - Semiconductor package and method of manufacturing the same: Provided are a semiconductor package and a method of manufacturing the semiconductor package, and more particularly, a semiconductor package with bonding wires and a method of manufacturing the semiconductor package. The semiconductor package includes a substrate including a finger, at least one semiconductor chip stacked on the substrate, the semiconductor... Agent: Marger Johnson & Mccollom, P.c.

20080150169 - Device package, a printed wiring board, and an electronic apparatus with efficiently spaced bottom electrodes including intervals between bottom electrodes of different lengths: A device package, such as a BGA, to be mounted on a printed wiring board (PWB) is disclosed. The bottom electrodes of the device package are arranged in an array such that intervals between the edges of the bottom electrodes become different from place to place. The intervals may be... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080150168 - Information storage medium on which is stored an interconnection program, interconnection method, interconnection apparatus, and semiconductor device: Conventionally, an excessively strict current limitation is often adopted. An interconnection apparatus includes an acquisition unit and a decision unit. The acquisition unit serves to acquire a current density and data rate of a region that a specific interconnect passes through. The decision unit serves to decide whether the temperature... Agent: Young & Thompson

20080150170 - Capillary-flow underfill compositions, packages containing same, and systems containing same: An underfill composition is formulated to increase the surface tension thereof for use in capillary underfilling of an integrated circuit die that is coupled to a mounting substrate. A method includes mixing a surface tension-increasing additive with a bulk polymer and a hardener and allowing the underfill composition to flow... Agent: Schwegman, Lundberg & Woessner, P.a.

20080142773 - Phase change memory cell and method of formation: A phase change memory element and methods for forming the same are provided. The memory element includes a first electrode and a chalcogenide comprising phase change material layer over the first electrode. A metal-chalcogenide layer is over the phase change material layer. The metal chalcogenide layer is tin-telluride. A second... Agent: Dickstein Shapiro LLP

20080142774 - Integrated circuit having resistive memory: An integrated circuit having resistive memory is disclosed. In one embodiment, the memory includes novel memory cells which have two electrodes and a layer arranged in between and including an active material which contains [1,2]dithiolo[4,3-[c]-1,2-dithiol-3,6-dithione, (2,4,7-trinitro-9-fluorenylidene)malonodinitrile and a polymer are disclosed. In one embodiment, a process for the production of... Agent: Dicke, Billig & Czaja, Pllc

20080142777 - Phase change memory device including resistant material and method of fabricating the same: A phase change memory device includes a lower electrode provided on a substrate, an interlayer insulating layer including a contact hole exposing the lower electrode, and covering the substrate, a resistant material pattern filling the contact hole, a phase change pattern interposed between the resistant material pattern and the interlayer... Agent: Volentine & Whitt Pllc

20080142776 - Phase change random access memory device with transistor, and method for fabricating a memory device: The invention relates to a memory device, in particular to a resistively switching memory device such as a Phase Change Random Access Memory (“PCRAM”). In one disclosed method, a nanowire of non-conducting material is formed serving as a mould for producing a nanotube of conducting material. A volume of switching... Agent: Dicke, Billig & Czaja

20080142775 - Programmable via structure and method of fabricating same: A programmable via structure is provided as well as a method of fabricating the same. The inventive programmable via a semiconductor substrate. An oxide layer such as a thermal oxide is located on a surface of the semiconductor substrate. A patterned heating material is located on a surface of the... Agent: Scully, Scott, Murphy & Presser, P.c.

20080142778 - Integrated circuit including a memory fabricated using self-aligned processing: An integrated circuit includes transistors in rows and columns providing an array, conductive lines in columns across the array, and resistivity changing material elements contacting the conductive lines and self-aligned to the conductive lines. The integrated circuit includes electrodes contacting the resistivity changing material elements, each electrode self-aligned to a... Agent: Dicke, Billig & Czaja

20080142783 - Deep ultraviolet light emitting devices and methods of fabricating deep ultraviolet light emitting devices: Light emitting devices and methods of fabricating light emitting devices that emit at wavelengths less than 360 nm with wall plug efficiencies of at least than 4% are provided. Wall plug efficiencies may be at least 5% or at least 6%. Light emitting devices and methods of fabricating light emitting... Agent: Myers Bigel Sibley & Sajovec, P.a.

20080142782 - Light emitting device: There is provided a light emitting device of a simpler structure, capable of ensuring a broad light emitting area and a high light emitting efficiency, while manufactured in a simplified and economically efficient process. The light emitting device including: a semiconductor layer; an active layer formed on the semiconductor layer,... Agent: Mcdermott Will & Emery LLP

20080142780 - Light-emitting diode chip: A thin-film light-emitting diode chip, in which the distance between a mirror layer (4) and a light-generating active zone (3) is set in such a way that a radiation emitted by the active zone (3) interferes with a light reflected from the mirror layer (4), the internal quantum efficiency of... Agent: Cohen, Pontani, Lieberman & Pavane

20080142779 - Nitride semiconductor light emitting device and fabricating method thereof: A nitride semiconductor light emitting device including: a first nitride semiconductor layer; an active layer formed on the first nitride semiconductor layer and including at least one barrier layer grown under hydrogen atmosphere of a high temperature; and a second nitride semi conductor layer formed on the active layer, and... Agent: Birch Stewart Kolasch & Birch

20080142781 - Nitride semiconductor light emitting device and fabrication method thereof: Provided is a nitride semiconductor light emitting device including: a first nitride semiconductor layer; an active layer formed above the first nitride semiconductor layer; and a delta doped second nitride semiconductor layer formed above the active layer. According to the present invention, the optical power of the nitride semiconductor light... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080142784 - Nanostructures and methods for manufacturing the same: A resonant tunneling diode, and other one dimensional electronic, photonic structures, and electromechanical MEMS devices, are formed as a heterostructure in a nanowhisker by forming length segments of the whisker with different materials having different band gaps.... Agent: Foley And Lardner LLP Suite 500

20080142785 - Strain-inducing semiconductor regions: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice... Agent: Intel/blakely

20080142786 - Insulated gate for group iii-v devices: A group III-V material device may have a capping layer on a barrier region, which may provide a high quality interface for a high-k gate dielectric. This may improve the performance of the device by reducing gate leakage and preserve the high-mobility properties of the quantum well channel region of... Agent: Intel Corporation C/o Intellevate, Llc

20080142787 - Fermionic bell-state analyzer and quantum computer using same: The Bell-state analyzer includes a semiconductor device having quantum dots formed therein and adapted to support Fermions in a spin-up and/or spin-down states. Different Zeeman splittings in one or more of the quantum dots allows resonant quantum tunneling only for antiparallel spin states. This converts spin parity into charge information... Agent: Opticus Ip Law, Pllc

20080142792 - Heteroacene compound, organic thin film comprising the compound, and electronic device comprising the thin film: A heteroacene compound includes a di-thieno-benzo-thieno-thiophene derivative, in which all six rings may be fused together, an organic thin film including the same, and an electronic device that includes the thin film as a carrier transport layer. The compound of example embodiments may have a compact planar structure to thus... Agent: Harness, Dickey & Pierce, P.L.C

20080142794 - Light-emitting element, light-emitting device, and electronic device: A light-emitting element disclosed in the present invention includes a light-emitting layer and a first layer between a first electrode and a second electrode, in which the first layer is provided between the light-emitting layer and the first electrode. The present invention is characterized by the device structure in which... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080142791 - Organic light emitting display and fabricating method thereof: An organic light emitting display including a substrate, a semiconductor layer formed on the substrate, an organic light emitting diode formed on the semiconductor layer, an encapsulant formed on a periphery of the substrate which is an outer periphery of the organic light emitting diode and the semiconductor layer; and... Agent: Robert E. Bushnell

20080142789 - Organic semiconductor light emitting device and display device using the same: An organic semiconductor light emitting device wherein efficiency of injecting a carrier from an organic semiconductor active layer to an organic semiconductor light emitting part is improved. The organic semiconductor light emitting device includes the organic semiconductor active layer having a source area and a drain area set at an... Agent: Rabin & Berdo, Pc

20080142793 - Organic semiconductors: Organic semiconducting devices and applications exhibit high performance largely due to a treatment substrate interacting with an asymmetric linear compound. According to an example, an organic compound arrangement includes a treated substrate and an asymmetric linear compound on the treated substrate. The compound includes an acene and a thiophene unit... Agent: Crawford Maunu Pllc

20080142790 - Phthalocyanine compound; organic semiconductor and method of producing the same, electronic device, organic photoelectric conversion device, organic field-effect transistor, and organic electroluminescence device, using the compound: wherein M is a metallic atom, or two hydrogen atoms which bond respectively to a nitrogen atom of an isoindole ring and to a nitrogen atom of an isoindoline ring; R1 to R16 each independently are a hydrogen atom or a substituent, in which at least two substituents of R1... Agent: Sughrue Mion, Pllc

20080142788 - Polythiophene electronic devices: wherein X is O or NR′; m represents the number of methylenes; M is a conjugated moiety; R and R′ are selected from the group consisting of at least one of hydrogen, a suitable hydrocarbon, and a suitable hetero-containing group; a represents the number of 3-substituted thiophene units; b represents... Agent: Patent Documentation Center

20080142795 - Ga2o3 semiconductor device: An n-side electrode 20 including at least a Ti layer is formed on a lower surface of an n-type β-Ga2O3 substrate 2 by utilizing a PLD method. This n-side electrode 20 has ohmic characteristics at 25° C. The n-side electrode 20 may have two layer including a Ti layer and... Agent: Mcginn Intellectual Property Law Group, Pllc

20080142797 - Thin film transistor, thin film transistor substate, and method of manufacturing the same: A thin film transistor substrate and a method of manufacturing the same are disclosed. The method of manufacturing a thin film transistor substrate includes forming a first conductive pattern group including a gate line, a gate electrode, and a lower gate pad electrode on a substrate, forming a gate insulating... Agent: Macpherson Kwok Chen & Heid LLP

20080142796 - Zno diode and method of forming the same: A zinc oxide (ZnO) group and method of forming the same are provided. The ZnO group diode may include a first electrode and a second electrode that are separated from each other, and an active layer formed of MxIn1-xZnO (wherein “M” is a Group III metal) between the first electrode... Agent: Harness, Dickey & Pierce, P.L.C

20080142798 - Semiconductor wafer: A semiconductor wafer comprises a plurality of die areas, at least a first scribe line area and at least a second scribe line area surrounding each die area, at least a first metal structure positioned in the first scribe line area, and at least a second metal structure positioned in... Agent: North America Intellectual Property Corporation

20080142799 - Semiconductor device having zener diode and method for manufacturing the same: Disclosed herewith is a semiconductor device comprising a trench gate electrode and a zener diode, as well as a method for manufacturing the same. The trench gate electrode is formed in a semiconductor body and includes a first polycrystalline silicon layer doped with impurities of a first conductivity type at... Agent: Mcginn Intellectual Property Law Group, Pllc

20080142803 - Display device and manufacturing method thereof: An edge portion 302 of a polysilicon layer 301 functioning as a channel layer is converted into a noncrystalline or fine crystalline area. Because a silicon semiconductor film at the channel edge portion 302 is in the fine crystalline or noncrystalline state, a current flowing there is extremely small, or... Agent: Reed Smith LLP

20080142805 - Electro luminescence display and method of testing the same: To increase the proportion of the perfects to the whole lot of final products and to reduce the cost for active matrix EL display devices by checking the operation of a TFT substrate before depositing an EL material. A capacitor for testing is connected to a drain terminal of a... Agent: Fish & Richardson P.c.

20080142801 - Electronic-ink display apparatus and the manufacturing method thereof: An electronic-ink display apparatus is provided. The electronic-ink display apparatus includes a thin film transistor (TFT) array substrate, an electronic-ink layer, a common electrode, a second substrate and an edge sealant. The TFT array substrate includes a first substrate and a dielectric layer located above the first substrate. The electronic-ink... Agent: Peter A. Nieves, Esq. Sheehan Phinney Bass & Green, Pa

20080142804 - Liquid crystal display device including driving circuit and method of fabricating the same: A method of fabricating an array substrate structure for a liquid crystal display device includes defining a display area and a non-display area on a substrate, the display area having a pixel TFT portion and a pixel electrode area, and the non-display area having an n-type driving TFT portion and... Agent: Mckenna Long & Aldridge LLP

20080142800 - Method of manufacturing thin film transistor, thin film transistor, and display unit: A method of manufacturing a thin film transistor capable of inhibiting the characteristics variation of the thin film transistor without deteriorating the characteristics thereof is provided. A crystalline silicon film is formed by indirect heat treatment through a photothermal conversion layer and a buffer layer. By patterning the buffer layer... Agent: Sonnenschein Nath & Rosenthal LLP

20080142802 - Tft-lcd pixel unit and method for manufacturing the same: A thin film transistor liquid crystal display (TFT-LCD) pixel unit and a method for manufacturing the same. The pixel unit comprises a gate line and a gate electrode formed on a substrate and a first gate insulating layer, an active layer, and a doped layer that are sequentially formed on... Agent: Hasse & Nesbitt Llc

20080142806 - Combination planar fet and finfet device: A semiconductor device. The device including: a planar FET formed in a single crystal-silicon substrate, the FET comprising a first channel region, first and second source drains on opposite sides of the first channel region and a gate, the gate over the channel region and electrically isolated from the channel... Agent: Schmeiser, Olsen & Watts

20080142807 - Organic light emitting display apparatus: An organic light emitting display apparatus with reduced infiltration of external moisture and oxygen comprises: a substrate comprising a plurality of TFT devices; and a display region formed on the substrate; wherein the display region comprises a base layer which comprises first electrodes electrically connected to the TFT devices and... Agent: Knobbe Martens Olson & Bear LLP

20080142808 - Thin film transistor and fabrication method thereof: A thin film transistor and a fabrication method thereof, in which one excimer laser annealing (ELA) makes a pixel portion and a driver portion different from each other in surface roughness and grain size. The thin film transistor includes: a substrate including a pixel portion and a driver portion; a... Agent: Stein, Mcewen & Bui, LLP

20080142809 - Light emitting device having vertical structure and method for manufacturing the same: A light emitting device having a vertical structure and a method for manufacturing the same, which are capable of damping impact generated during a substrate separation process and achieving an improvement in mass productivity, are disclosed. The light emitting device includes a semiconductor layer having a multilayer structure, a first... Agent: Mckenna Long & Aldridge LLP

20080142810 - Self assembled controlled luminescent transparent conductive photonic crystals for light emitting devices: A transparent conductive oxide contact layer to enhance the spectral output of a light emitting device and a methodology for its deposition. The transparent conductive oxide deposited on the light emitting device so as to have a columnar structure. The transparent conductive oxide contact layer may be preferably ZnO doped... Agent: William L. Botjer

20080142813 - Led and method for making the same: A light emitting diode device and a method for manufacturing the same are disclosed. The method comprises following steps: (A) providing a substrate; (B) forming a diamond layer on the surface of the substrate; (C) forming a doping region on the upper surface of the diamond layer; (D) bonding a... Agent: Bacon & Thomas, Pllc

20080142812 - Led and method for marking the same: A light emitting diode device and a method for manufacturing the same are disclosed. The method comprises following steps: (A) providing a substrate; (B) forming a SiC film on the surface of the substrate; (C) forming a diamond layer on the surface of the SiC film and removing the substrate,... Agent: Bacon & Thomas, Pllc

20080142811 - Mosfet devices and methods of fabrication: A vertical MOSFET is disclosed. The MOSFET includes a gate dielectric region, a drift region having a drift region dopant concentration profile of a first conductivity type, and a JFET region having a JFET region dopant concentration profile of the first conductivity type adjacent to the gate dielectric region and... Agent: General Electric Company (pcpi) C/o Fletcher Yoder

20080142814 - Light emitting diodes (leds) with improved light extraction by roughening: Systems and methods are disclosed for fabricating a semiconductor light-emitting diode (LED) device by forming an n-doped gallium nitride (n-GaN) layer on the LED device and roughening the surface of the n-GaN layer to extract light from an interior of the LED device.... Agent: Patterson & Sheridan, L.l.p.

20080142815 - Optical element, optical module holder including optical element, optical module, and optical connector: A transmitting surface section 21 and at least one reflective surface section 22 are provided. The transmitting surface section 21 refracts incident light emitted from a predetermined light-emitting position and transmits the light. The reflective surface section 22 reflects the incident light emitted from the light-emitting position such that the... Agent: Quinn Emanuel Urquhart Oliver & Hedges, LLP Koda/androlia

20080142816 - Tunable white point light source using a wavelength converting element: A uniform high brightness light source is provided using a plurality of light emitting diode (LED) chips with slightly different pump wavelengths with a wavelength converting element that includes at least two different wavelength converting materials that convert the light to different colors of light. The intensity of the light... Agent: Patent Law Group LLP

20080142817 - Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices: Methods of packaging light emitting devices include providing an epiwafer including a growth substrate and an epitaxial structure on the growth substrate, bonding a carrier substrate to the epitaxial structure of the epiwafer, forming a plurality of conductive vias through the carrier substrate, defining a plurality of isolated diodes in... Agent: Myers Bigel Sibley & Sajovec, P.a.

20080142818 - Flip chip type led lighting device manufacturing method: A flip chip type LED lighting device manufacturing method includes the step of providing a strip, the step of providing a submount, the step of forming a metal bonding layer on the strip or submount, the step of bonding the submount to the strip, and the step of cutting the... Agent: Rosenberg, Klein & Lee

20080142819 - Liquid crystal display and manufacturing method thereof: A liquid crystal display (LCD) and a manufacturing method thereof. The LCD comprises a color filter substrate, an array substrate disposed opposite to the color filter substrate, and a liquid crystal layer sealed between the two substrates, wherein a conductive nano-particle is introduced between the two substrates.... Agent: Hasse & Nesbitt Llc

20080142828 - Coaxial light-guide system consisting of coaxial light-guide fiber basing its refractive index profiles on radii and with its coaxial both semiconductor light sources and semiconductor detectors: A coaxial light-guide system includes a coaxial light-guide optical fiber which is fabricated by having refractive index profile set on radii. Thus the coaxial circular outer-cladding and the axial inter-cladding have the same refractive index. The light guide refractive index profile center is moved from the axis to the entire... Agent: Frenkel & Associates, P.c.

20080142824 - Electroluminescent device and fabrication method thereof: An electroluminescent device includes a substrate, a reflection layer, a patterned transparent conductive layer, at least one LED element, a first contact electrode and a second contact electrode. The reflection layer is formed on the substrate. The patterned transparent conductive layer is disposed on the reflection layer. The LED element... Agent: Birch Stewart Kolasch & Birch

20080142825 - Electroluminescent device and fabrication method thereof: An electroluminescent device includes a conduction substrate, a reflection layer, a patterned transparent conduction layer, at least one light emitting diode (LED) element, a first contact electrode and a second contact electrode. The reflection layer is disposed on the conduction substrate, and the patterned transparent conduction layer is formed on... Agent: Birch Stewart Kolasch & Birch

20080142826 - Electroluminescent device and manufacturing method thereof: An electroluminescent device includes a heat-conductive substrate, a heat-conductive adhering layer, a heat-conductive insulating layer, a reflective layer, a light-emitting diode element, a first contacting electrode and a second contacting electrode. The heat-conductive adhering layer is formed on the heat-conductive substrate. The heat-conductive insulating layer is formed on the heat-conductive... Agent: Birch Stewart Kolasch & Birch

20080142822 - Light emitting diode package and method of manufacturing the same: An LED package comprises a frame having a concave portion formed in the center thereof; one or more LED chips mounted on the bottom surface of the concave portion; and a lens filled in the concave portion, the lens having an upper surface formed of continuous prismatic irregularities forming concentric... Agent: Mcdermott Will & Emery LLP

20080142827 - Pixel, display using the same, and driving method for the same: A pixel may include a light emitting element, a first transistor, a second transistor, a storage capacitor, and a third transistor. The first transistor may be configured to transfer a data signal to a data line when a scan signal is supplied to a scan line. The second transistor may... Agent: Lee & Morse, P.c.

20080142830 - Programming optical device: A semiconductor light emitting device and a method to form the same are disclosed. The device has at least one porous or low density dielectric region formed in or on top of a bottom electrode, at least one top electrode on the porous or low density dielectric region, and one... Agent: L. Howard Chen Kirkpatrick & Lockhart Preston Gates Ellis, LLP

20080142820 - Reflective mounting substrates for light emitting diodes: A light emitting diode is disclosed that includes a light emitting active structure formed from the Group III nitride material system, a bonding structure supporting the Group III nitride active structure, and a mounting substrate supporting the bonding structure. The mounting substrate includes a material that reflects at least fifty... Agent: Summa, Allan & Additon, P.a.

20080142821 - Semiconductor light emitting device: It is an important factor in application to the illumination field and the like to obtain a characteristic excellent in power efficiency in a light emitting element. The present invention provides a semiconductor light emitting element including: first and second conductive type semiconductor layers; first and second electrodes respectively provided... Agent: Birch Stewart Kolasch & Birch

20080142823 - Semiconductor light emitting device and method of manufacturing the same: There are provided a semiconductor light emitting device using a phosphor film formed on a nanowire structure and a method of manufacturing the device, the device including: a substrate; a light emitting structure comprising a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer... Agent: Mcdermott Will & Emery LLP

20080142829 - Semiconductor light emitting devices including flexible silicone film having a lens therein: Semiconductor light emitting devices include an alumina substrate, a light emitting diode on a face of the substrate and flexible silicone film that includes a silicone lens on the face of the substrate. The light emitting diode emits light through the silicone lens.... Agent: Myers Bigel Sibley & Sajovec, P.a.

20080142833 - Interconnects for semiconductor light emitting devices: A semiconductor light emitting device including a light emitting layer disposed between an n-type region and a p-type region and contacts electrically connected to the n-type region and the p-type region is connected to a mount. A metal layer arbitrarily patterned to cover at least 20% of the area of... Agent: Patent Law Group LLP

20080142831 - Package structure: A package structure including a first lead, a second lead, an encapsulant, a light-emitting device and an electrostatic discharge (ESD) protection device is provided. The second lead is disposed beside the first lead, and parts of the first lead and the second lead are encapsulated by the encapsulant. The encapsulant... Agent: Jianq Chyun Intellectual Property Office

20080142832 - Side-view optical diode package and fabricating process thereof: A side-view optical diode package is mounted on a printed circuit board with at least a solder bump. The side-view optical diode package includes a silicon substrate, a holding space, a bonding surface and a positioning structure. The silicon substrate has a first surface and a second surface. The holding... Agent: Kirton And Mcconkie

20080142834 - Voltage-controlled bidirectional switch: A voltage-controlled vertical bidirectional monolithic switch, referenced with respect to the rear surface of the switch, formed from a lightly-doped N-type semiconductor substrate, in which the control structure includes, on the front surface side, a first P-type well in which is formed an N-type region, and a second P-type well... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.c.

20080142841 - Bulk non-planar transistor having strained enhanced mobility and methods of fabrication: A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a... Agent: Michael A. Bernadicou Blakely, Sokoloff, Taylor & Zafman LLP

20080142840 - Metal gate transistors with epitaxial source and drain regions: An MOS transistor formed on a heavily doped substrate is described. Metal gates are used in low temperature processing to prevent doping from the substrate from diffusing into the channel region of the transistor.... Agent: Intel/blakely

20080142836 - Method for growth of alloy layers with compositional curvature in a semiconductor device: A method and system for providing an alloy layer in a semiconductor device are described. The method and system ramping a first gas including a first constituent of the alloy layer from a first level to a second level different from the first level while the alloy layer is grown.... Agent: Sawyer Law Group LLP

20080142843 - Nmos device, pmos device, and sige hbt device formed on soi substrate and method of fabricating the same: Provided are an NMOS device, a PMOS device and a SiGe HBT device which are implemented on an SOI substrate and a method of fabricating the same. In manufacturing a Si-based high speed device, a SiGe HBT and a CMOS are mounted on a single SOI substrate. In particular, a... Agent: Lowe Hauptman Ham & Berner, LLP

20080142842 - Relaxed silicon germanium substrate with low defect density: A structure for an integrated circuit is disclosed. The structure includes a crystalline substrate and four crystalline layers. The first crystalline layer of first lattice constant is positioned on the crystalline substrate. The second crystalline layer has a second lattice constant different from the first lattice constant, and is positioned... Agent: Haynes And Boone, LLP

20080142838 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080142839 - Semiconductor device, method of manufacturing the same, and method of evaluating semiconductor device: A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080142835 - Stress enhanced transistor and methods for its fabrication: A stress enhanced MOS transistor and methods for its fabrication are provided. A semiconductor-on-insulator structure is provided which includes a semiconductor layer having a first surface. A strain-inducing epitaxial layer is blanket deposited over the first surface, and can then be used to create a source region and a drain... Agent: Ingrassia Fisher & Lorenz, P.c. (amd)

20080142837 - Vertical type semiconductor device and manufacturing method of the device: A vertical semiconductor element comprises: an electro-conductive substrate 1; a GaN layer 3, as a nitride compound semiconductor layer, which is selectively grown as convex shape on an one surface of the electro-conductive substrate 1 through a buffer layer 9; a source electrode 25 as a first electrode formed on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080142844 - Semiconductor heterostructure: A semiconductor heterostructure that includes a support substrate with a first in-plane lattice parameter, a buffer structure formed on the support substrate and having on top in a relaxed state a second in-plane lattice parameter, and a multi-layer stack of ungraded layers formed on the buffer structure. This semiconductor hetero-structure... Agent: Winston & Strawn LLP Patent Department

20080142845 - Hemt including mis structure: A HEMT has a drain region adapted to be electrically connected to a high voltage of an electric source, a source region adapted to be electrically connected to a low voltage of the electric source. A first semiconductor region is disposed between the drain region and the source region. A... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080142846 - Nitride semiconductor substrate and manufacturing method thereof: The present invention relates to a nitride semiconductor substrate such as gallium nitride substrate and a method for manufacturing the same. The present invention forms a plurality of trenches on a lower surface of a base substrate that are configured to absorb or reduce stresses applied larger when growing a... Agent: Greer, Burns & Crain

20080142848 - Methods and apparatus for inline variability measurement of integrated circuit components: An integrated circuit device is provided including at least one first array configuration of integrated circuit components comprising a m×n array of FETs, without specified internal connections between the integrated circuit components, wherein m is greater than two. The integrated circuit device further includes at least one second array configuration... Agent: Ryan, Mason & Lewis, LLP

20080142847 - Semiconductor apparatus having a large-size bus connection: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the... Agent: Arent Fox LLP

20080142850 - Memory elements and cross point switches and arrays of same using nonvolatile nanotube blocks: Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and... Agent: Wilmerhale/boston

20080142849 - Semiconductor esd device and method of making same: An ESD protection device includes a semiconductor body, a gate formed over a channel in the semiconductor body, the channel being doped with a first concentration of dopants of a first conductivity type. A first source/drain region is formed on the surface of the semiconductor body adjacent to a first... Agent: Slater & Matsil LLP

20080142851 - Charge transfer device and solid state imager device: A charge transfer device includes a charge transfer unit transferring signal charges, and an electric charge-voltage conversion unit detecting signal charges transferred from a last stage of the charge transfer unit via an output gate unit. An electrode in a last stage of the charge transfer unit is divided into... Agent: Sonnenschein Nath & Rosenthal LLP

20080142852 - Semiconductor device structure with active regions having different surface directions: Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and a first surface orientation atop a... Agent: Hoffman, Warnick & D'alessandro Llc

20080142853 - Multi-channel transistor structure and method of making thereof: A method of forming an electronic device includes, forming a first channel coupled to a first current electrode and a second current electrode and forming a second channel coupled to the first current electrode and the second current electrode. The method also includes the second channel being substantially parallel to... Agent: Larson Newman Abel Polansky & White, LLP

20080142854 - Circuit and method for suppressing gate induced drain leakage: An electrical circuit comprising a first metal oxide silicon (MOS) n type field effect transistor (NFET) or p type field effect transistor (PFET) and a second MOS NFET or PFET of the same conductivity type as the first NFET or PFET, wherein the drain of the first NFET or PFET... Agent: Edell, Shapiro & Finnan, Llc

20080142855 - Mos transistor, method for manufacturing the mos transistor, cmos semiconductor device including the mos transistor, and semiconductor device including the cmos semiconductor device: A MOS transistor includes a silicon substrate, a gate insulating film disposed on the silicon substrate, a gate electrode disposed on the gate insulating film, source/drain regions disposed at both sides of the gate electrode, and a stress-generating region containing a stress-generating substance. The stress-generating region is disposed within the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080142858 - Cmos image sensor structure: A CMOS image sensor (CIS) process is described. A semiconductor substrate is provided, and then a gate dielectric layer, a gate material layer and a thickening layer are sequentially formed on the substrate, wherein the thickening layer includes at least a hard mask layer. The thickening layer is defined to... Agent: Jianq Chyun Intellectual Property Office

20080142857 - Image sensor: Embodiments relate to an image sensor and a method for manufacturing an image sensor that may prevent a photoresist pattern from remaining on gates by forming a floating diffusion area faster than the gates. According to embodiments, since the gates may not be influenced by an ion implantation process, current... Agent: Sherr & Nourse, Pllc

20080142856 - Solid-state imaging device and electronic device: There is provided a solid-state imaging device including an imaging region having a plurality of pixels arranged in a two-dimensional matrix and a peripheral circuit detecting output signals from the pixels. An impurity concentration in a transistor of each pixel is lower than an impurity concentration in a transistor of... Agent: Sonnenschein Nath & Rosenthal LLP

20080142859 - Methods of forming ferroelectric media with patterned nano structures for data storage devices: Methods and associated structures of forming a microelectronic device are described. Those methods may forming a conductive layer on a substrate, patterning the conductive layer, forming at least one nanodot on the patterned conductive layer, and forming a thin film ferroelectric material on the at least one nanodot.... Agent: Intel Corporation C/o Intellevate, Llc

20080142860 - Method and system for utilizing dram components in a system-on-chip: A system-on-chip semiconductor circuit includes a logic circuit having at least one first transistor with a thin gate dielectric, at least one dynamic random access memory cell coupled with the logic circuit having at least one storage capacitor and at least one thick gate dielectric access transistor, and an analog... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20080142861 - Symmetric capacitor structure: A structure comprising a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The... Agent: Schmeiser, Olsen & Watts

20080142862 - Method of fabricating a trench capacitor having increased capacitance: The present invention pertains to a method of fabricating a trench capacitor having increased capacitance. To tackle a difficult problem of etching deeper trenches having very high aspect ratio, an epitaxial silicon growth process is employed in the fabrication of next-generation trench DRAM devices. A large-capacitance trench capacitor is first... Agent: North America Intellectual Property Corporation

20080142863 - Semiconductor device and method for fabricating the same: A semiconductor device includes a capacitor which has: a lower electrode formed along an opening provided above a semiconductor substrate to have a concave cross section; a capacitor insulating film formed on the inner and top surfaces of the lower electrode; and an upper electrode formed on the capacitor insulating... Agent: Mcdermott Will & Emery LLP

20080142864 - Semiconductor device and method for manufacturing the same: According to the method for manufacturing a semiconductor device, a surface of a lower insulating film (55) is planarized by CMP or the like, and an upper insulating film (56) and a protective metal film (59) are formed on the lower insulating film (55). Accordingly, the upper insulating film (56)... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080142865 - Semiconductor device and method for manufacturing the same: There is provided a semiconductor device including a silicon substrate, a source/drain region formed in a surface layer of the silicon substrate, a first insulating film provided with a first hole on the first source/drain region, a conductive film formed on an inner surface of the first hole, a filler... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080142866 - Integrated circuit memory devices and capacitors having carbon nanotube electrodes: An integrated circuit capacitor includes first and second electrodes and at least one dielectric layer extending between the first and second electrodes. The first electrode includes at least one carbon nanotube. The capacitor further includes an electrically conductive catalyst material. This catalyst material may be selected from the group consisting... Agent: Myers Bigel Sibley & Sajovec

20080142868 - Floating body memory and method of fabricating the same: A floating body memory includes a semiconductor substrate having a cell region and a peripheral circuit region. A floating body cell is located in the cell region and a first floating body is located in the peripheral circuit region of the semiconductor substrate. A peripheral gate pattern is positioned on... Agent: Volentine & Whitt Pllc

20080142869 - Non-volatile memory device and method of forming the same: Example embodiments relate to a non-volatile memory device and a method of forming the same. A non-volatile memory device according to example embodiments may include a conductive pattern provided on the semiconductor substrate. A tunnel insulator may be provided on the conductive pattern. A memory gate structure may be provided... Agent: Harness, Dickey & Pierce, P.L.C

20080142867 - Non-volatile memory device with polysilicon spacer and method of forming the same: Non-volatile memory device with polysilicon spacer and method of forming the same. A dielectric layer lines a sidewall of a polysilicon gate. A polysilicon spacer is patterned on the dielectric layer adjacent to the sidewall of the polysilicon gate. A protection spacer is patterned on the dielectric layer and disposed... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080142870 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory according to an example of the present invention includes first and second diffusion layers, a channel formed between the first and second diffusion layers, a gate insulating film formed on the channel, a floating gate electrode formed on the gate insulating film, an inter-gate insulating film... Agent: Amin, Turocy & Calvin, LLP

20080142871 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device is provided which has insulating film side wall spacers having a barrier function. The semiconductor device comprises: a gate oxide film and a gate electrode formed on and above a semiconductor substrate; source/drain regions formed in the semiconductor substrate; and first laminated side wall spacers having two... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080142872 - Non-volatile memory devices including stepped source regions and methods of fabricating the same: A non-volatile memory device includes a semiconductor substrate having a first section including a substantially planar first top surface, a second section including a substantially planar second top surface, and a sidewall extending between the first and second top surfaces. The second top surface of the substrate is closer to... Agent: Myers Bigel Sibley & Sajovec

20080142874 - Integrated circuit system with implant oxide: A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a... Agent: Farjami & Farjami LLP

20080142873 - Integrated circuit system with metal and semi-conducting gate: A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer... Agent: Farjami & Farjami LLP

20080142875 - Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes: Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an adjacent second trench in a semiconductor substrate, the first trench and the second trench each defining a first sidewall and... Agent: Wagner, Murabito & Hao LLP

20080142877 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory having an LDD structure includes a control gate located above a channel region, insulating layers formed on the both side surface of the control gate, and I-letter shaped charge-storage layers formed on the insulating layers wherein a bottom surface of the each charge-storage layer are located... Agent: Junichi Mimura Oki America Inc.

20080142876 - Nonvolatile semiconductor storage device and manufacturing method of the same: A charge trapping layer in an element isolation region and that in an isolation region between a memory transistor and a selection transistor are removed so that the charges are not injected or trapped in the regions. Also, in an element isolation region, gate electrodes of each memory transistor are... Agent: Mattingly, Stanger, Malur & Brundidge, P.c.

20080142878 - Charge trap memory device and a method of manufacturing the same: Provided are a charge trap memory device and a method of manufacturing the same. The charge trap memory device may comprise a gate structure including a plurality of metal oxide nanodots discontinuously arranged as a charge trap site on a substrate.... Agent: Harness, Dickey & Pierce, P.L.C

20080142879 - Integrated circuit system employing differential spacers: An integrated circuit system that includes: providing a substrate with an NFET device and a PFET device; forming an NFET first liner and an NFET first spacer over the NFET device; forming a PFET first liner and a PFET first spacer over the PFET device; forming a punch-through suppression layer... Agent: Law Offices Of Mikio Ishimaru

20080142880 - Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the... Agent: Mayer & Williams Pc

20080142881 - Semiconductor device including a fin-channel recess-gate misfet: A fin-channel recess-gate MISFET has a fin channel including a first portion configured by a portion of a silicon substrate and a second portion configured by a pair of silicon layers selectively grown on the silicon substrate. The first portion is disposed below the recess of the recess gate and... Agent: Scully Scott Murphy & Presser, Pc

20080142882 - Transistors: The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate... Agent: Wells St. John P.s.

20080142883 - Power transistor with trench sinker for contacting the backside: A power transistor includes a first semiconductor region of a first conductivity type extending over and in contact with a second semiconductor region of the first conductivity type. Gate trenches extend into the first semiconductor region. Well regions of a second conductivity type extend over the first semiconductor region and... Agent: Townsend And Townsend And Crew, LLP

20080142884 - Semiconductor device: Embodiments relate to a semiconductor device, and to a semiconductor device and a method for manufacture that may improve a performance of a MOSFET device. According to embodiments, a semiconductor device may include a gate pattern formed of a gate dielectric layer formed in an active area of a semiconductor... Agent: Sherr & Nourse, Pllc

20080142885 - Semiconductor device with improved source and drain and method of manufacturing the same: A semiconductor device includes a gate, extension layers, source drain layers, and silicide layers. The gate is formed on one of a n-type semiconductor substrate and a n-type through a gate insulation film. The extension layers are p-type semiconductors and formed under sidewalls which are formed on both sides of... Agent: Young & Thompson

20080142887 - Silicon nitride film and semiconductor device, and manufacturing method thereof: An object of the present invention is to apply an insulating film of cure and high quality that is suitably applicable as gate insulating film and protective film to a technique that the insulating film is formed on the glass substrate under a temperature of strain point or lower, and... Agent: Eric Robinson

20080142886 - Treatment method of semiconductor, method for manufacturing mos, and mos structure: The method of the present invention includes providing a semiconductor substrate with a recess; performing a pre-cleaning step on the semiconductor substrate; and performing a first reduction step, a lateral etching step and a second reduction step on the semiconductor substrate. The MOS structure includes a semiconductor substrate, a gate... Agent: North America Intellectual Property Corporation

20080142888 - Isolation spacer for thin soi devices: A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.... Agent: Haynes And Boone, LLP

20080142889 - Strapping contact for charge protection: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured... Agent: Harrity & Snyder, L.l.p.

20080142891 - Bulk finfet device: A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode... Agent: Schmeiser, Olsen & Watts

20080142890 - Multiple-gate mosfet device with lithography independnet silicon body thickness and methods for fabricating the same: Multi-gate MOS transistors and fabrication methods are described, in which the transistor semiconductor body thickness or width is lithography independent, allowing scaled triple and quad-gate devices having semiconductor bodies smaller than a lateral gate length dimension. A form structure is provided over a semiconductor wafer starting structure, and spacers are... Agent: Jacqueline J. Garner Texas Instruments Incorporated

20080142893 - Gate electrode structures: Gate electrode structures used in field effect transistors and integrated circuits and methods of manufacture are disclosed. Improved work function and threshold modulation are provided by the methods and structures.... Agent: Diehl Servilla Llc

20080142894 - Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow: A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt... Agent: Connolly Bove Lodge & Hutz LLP

20080142892 - Interconnect feature having one or more openings therein and method of manufacture therefor: Provided is a metallization system, a method for manufacture therefore, and a semiconductor device. The metallization system, in one embodiment, comprises a dielectric layer, as well as an interconnect feature located over the dielectric layer. The interconnect feature, in this embodiment, includes one or more openings extending therethrough, the one... Agent: Texas Instruments Incorporated

20080142897 - Integrated circuit system having strained transistor: An integrated circuit system is provided including forming a circuit element on a wafer, forming a stress formation layer having a non-uniform profile over the wafer, and forming an interlayer dielectric over the stress formation layer and the wafer.... Agent: Law Offices Of Mikio Ishimaru

20080142896 - Selective stress engineering for sram stability improvement: An integrated circuit (IC) structure including a SRAM cell is provided in which the performance of the pass-gate transistors is degraded in order to increase the beta ratio of the transistors within the SRAM cell. In particular, the increased beta ratio is obtained in the present invention by intentionally improving... Agent: Scully, Scott, Murphy & Presser, P.c.

20080142898 - Semiconductor integrated circuit: An integrated circuit includes: a first well of a first conductivity type; a second well of a second conductivity type coming into contact with the first well at a well boundary extending in a gate length direction; a first transistor having a first active region of the second conductivity type... Agent: Mcdermott Will & Emery LLP

20080142895 - Stress engineering for sram stability: An IC is provided that includes at least one SRAM cell in which the performance of the SRAM cell is enhanced, yet maintaining good stability and writability. In particular, the present invention provides an IC including at least one SRAM cell wherein the gamma ratio is about 1 or greater.... Agent: Scully, Scott, Murphy & Presser, P.c.

20080142899 - Radiation immunity of integrated circuits using backside die contact and electrically conductive layers: Radiation hardened integrated circuit devices may be fabricated using conventional designs and process, but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. An exemplary BGR structure includes a high-dose buried guard ring (HBGR) layer which is contacted to ground through the backside of... Agent: Zagorin O'brien Graham LLP

20080142900 - Abrupt metal-insulator transition device, circuit for removing high-voltage noise using the abrupt metal-insulator transition device, and electrical and/or electronic system comprising the circuit: Provided are an abrupt metal-insulator transition (MIT) device for bypassing super-high voltage noise to protect an electric and/or electronic system, such as, a high-voltage switch, from a super-high voltage, a high-voltage noise removing circuit for bypassing the super-high voltage noise using the abrupt MIT device, and an electric and/or electronic... Agent: Cantor Colburn, LLP

20080142901 - Manufacturing method of semiconductor device: A method of manufacture of a semiconductor device includes forming a gate insulating film and gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080142902 - Method for fabricating ultra-high tensile-stressed film and strained-silicon transistors thereof: A metal-oxide-semiconductor (MOS) transistor device is disclosed. The MOS transistor device comprises a semiconductor substrate; a gate structure on the semiconductor substrate; source/drain regions on the semiconductor substrate adjacent to the gate structure; an ultra-high tensile-stressed nitride film having a hydrogen concentration of less than 1E22 atoms/cm3 covering the gate... Agent: North America Intellectual Property Corporation

20080142903 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the same is disclosed, in which a spacer containing nitrogen therein has a tensile stress and enables device reliability improvement by improving the On-current without regard to the kind of transistor. The semiconductor device includes a semiconductor substrate; a gate insulating layer... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080142904 - Field effect transistor with buried gate pattern: A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate... Agent: Law Office Of Monica H Choi

20080142905 - Semiconductor device: A semiconductor device including: a semiconductor layer including an element formation region including an element; a dielectric layer above the semiconductor; an electrode pad above the dielectric; a passivation layer above the pad and having an opening exposing part of the pad; and a bump in the opening and covering... Agent: Harness, Dickey & Pierce, P.L.C

20080142906 - Semiconductor device: A semiconductor device comprising: a semiconductor layer including an element formation region, and first and second spaced apart isolation regions; an element in the element formation region; an interlayer dielectric layer above the semiconductor layer; an electrode pad above the interlayer dielectric layer; a passivation layer above the electrode pad... Agent: Harness, Dickey & Pierce, P.L.C

20080142907 - Isolated multigate fet circuit blocks with different ground potentials: An electronic circuit on a semiconductor substrate having isolated multiple gate field effect transistor circuit blocks is disclosed. In some embodiments, an electronic circuit has a substrate having a buried oxide insulating region. A MuGFET device may be formed above the buried oxide region and coupled to a first source... Agent: Schwegman, Lundberg & Woessner / Infineon

20080142908 - Method of using iii-v semiconductor material as gate electrode: A method of using an III-V semiconductor material as a gate electrode is provided. The method includes steps of providing a substrate; forming a gate dielectric layer on the substrate; and forming the III-V semiconductor material on the gate dielectric layer.... Agent: Volpe And Koenig, P.c.

20080142909 - Ultra dense trench-gated power device with reduced drain source feedback capacitance and miller charge: The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is... Agent: Hiscock & Barclay, LLP

20080142910 - Semiconductor device: Embodiments relate to a semiconductor device and fabricating method thereof. In embodiments, a method of fabricating a semiconductor device may include forming a first gate insulating layer on a semiconductor substrate, performing first plasma nitridation on the first gate insulating layer, forming a second gate insulating layer on the first... Agent: Sherr & Nourse, Pllc

20080142911 - Electromagnetic bandgap motion sensor device and method for making same: A high-frequency Electromagnetic Bandgap (EBG) motion sensor device, and a method for making such a device are provided. The device includes a substantially planar substrate including multiple conducting vias forming a periodic lattice in the substrate. The vias extend from the lower surface of the substrate to the upper surface... Agent: Delphi Technologies, Inc.

20080142912 - Mems resonator and manufacturing method of the same: A method is for manufacturing a microeletromechanical system resonator having a semiconductor device and a microelectromechanical system structure unit formed on a substrate. The method includes: forming a lower electrode of an oxide-nitride-oxide capacitor unit included in the semiconductor device using a first silicon layer; forming, using a second silicon... Agent: Oliff & Berridge, Plc

20080142914 - Proof-mass with supporting structure on integrated circuit-mems platform and method of fabricating the same: Provided is a micro-electromechanical-system (MEMS) device including a substrate; at least one semiconductor layer provided on the substrate; a circuit region including at least one chip containing drive/sense circuitry, the circuit region provided on the at least one semiconductor layer; a support structure attached to the substrate; at least one... Agent: Morgan Lewis & Bockius LLP

20080142913 - Z offset mems devices and methods: A microelectromechanical system (MEMS) device with a mechanism layer and a base. The top surface of the base is bonded to the mechanism layer and defines a gap in the top surface of the base. A portion of the mechanism layer is deflected into the gap until it contacts the... Agent: Honeywell International Inc. Patent Services Ab-2b

20080142915 - Ferroelectric memory device and fabrication process thereof, fabrication process of a semiconductor device: A ferroelectric memory device includes a field effect transistor formed over a semiconductor substrate and including first and second diffusion regions, an interlayer insulation film formed over the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080142916 - Obstacle sensor operating by collimation and focusing of the emitted wave: An obstacle sensor operating by collimation and focusing of the emitted wave comprises: a device (I) for insulating the electromagnetic waves emitted by a generator (1); a device for the automatic control (12, 12′) of the transmitter and of the sensor status; a device (15′÷15″′) for amplifying the power of... Agent: Bucknam And Archer

20080142917 - Image sensor module, method of manufacturing the same, and camera module having the same: Provided is an image sensor module including a lower substrate having a plurality of electrode pads formed on the outer portion of the top surface thereof; an upper substrate installed on the top surface of the lower substrate, the upper substrate having a window formed in the central portion thereof... Agent: Staas & Halsey LLP

20080142919 - Cmos image sensors with light shielding patterns and methods of forming the same: An image sensor includes a semiconductor substrate including an active pixel region and an optical black region, a wiring pattern on the active pixel region and on the optical black region, and a light shielding pattern on the wiring pattern in the optical black region, the light shielding pattern including... Agent: Myers Bigel Sibley & Sajovec

20080142918 - Printed electronic substrate having photochromic barrier layer: A protective photochromic barrier film for a light-sensitive printed electronic substrate. Light-sensitive semiconductor devices on a dielectric substrate are electrically connected by conductors. A barrier layer containing photochromic dyes covers some or all of the light-sensitive semiconductor devices. Upon exposure to visible, infrared, or ultraviolet light, the photochromic dyes change... Agent: Motorola, Inc.

20080142920 - Highly sensitive photo-sensing element and photo-sensing device using the same: According to the present invention, a highly sensitive photo-sensing element and a sensor driver circuit are prepared by planer process on an insulating substrate by using only polycrystalline material. Both the photo-sensing element and the sensor driver circuit are made of polycrystalline silicon film. As the photo-sensing element, a photo... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080142921 - Method of fabricating semiconductor device: To fabricate a Schottky barrier diode in which a decrease in on current due to parasitic resistance is suppressed, variations in on current are suppressed, and an increase in off current is suppressed. The fabricating method includes the steps of forming an island-shape semiconductor film; doping the island-shape semiconductor film... Agent: Nixon Peabody, LLP

20080142922 - Semiconductor chip: Provided is a semiconductor chip (1) including: at least one fuse element (21); a fuse opening (17) formed above the fuse element (21); and a discharge electrode (31) that is formed below a bottom portion (17a) of the fuse opening (17), and is formed in one of the same layer... Agent: Mcginn Intellectual Property Law Group, Pllc

20080142923 - Semiconductor structure and method of manufacture: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a semiconductor structure having a silicon-on-insulator (SOI) substrate and a dielectric region is disclosed. The dielectric region is adjacent to the active layer of the SOI substrate and the dielectric region includes a portion... Agent: Hvvi Semiconductors, Inc.

20080142924 - Decoupling capacitor circuit: The invention discloses a decoupling capacitor circuit, comprising a plurality of coupled deep trench capacitors connected in series and a plurality of push-pull circuits. The decoupling capacitor circuit controls the voltage across each deep trench capacitor via the push-pull circuit so that it will not be influenced by the defect... Agent: Joe Mckinney Muncy

20080142925 - Programmable-resistance memory cell: The present invention relates to a memory cell comprising: a resistive structure; at least two electrodes coupled to the resistive structure, and at least one hydrogen reservoir structure, wherein the application of an electrical signal to one of the at least two electrodes causes the electrical resistance of the resistive... Agent: Ibm Corporation, T.j. Watson Research Center

20080142926 - Directionally controlled growth of nanowhiskers: Nanowhiskers are grown in a non-preferential growth direction by regulation of nucleation conditions to inhibit growth in a preferential direction. In a preferred implementation, <001> III-V semiconductor nanowhiskers are grown on an (001) III-V semiconductor substrate surface by effectively inhibiting growth in the preferential <111>B direction. As one example, <001>... Agent: Foley And Lardner LLP Suite 500

20080142927 - Scribe-line structures and methods of forming the same: Scribe-line structures and methods of forming such scribe-line structures on a face of a semiconductor substrate are provided. By means of the scribe-line structures and the methods of this invention, physical shock and cracking tendencies along a semiconductor substrate can be minimized during performance of a cutting process on the... Agent: Mills & Onello LLP

20080142928 - Semiconductor component with through-vias: A semiconductor device includes a semiconductor substrate having an upper surface and a lower surface opposed to the upper surface. Integrated circuitry is formed at the upper surface of the semiconductor substrate. A plurality of active through-vias are electrically coupled to the integrated circuitry and extend from the upper surface... Agent: Slater & Matsil LLP

20080142929 - Method of producing a porous dielectric element and corresponding dielectric element: A porous dielectric element is produced by forming a first dielectric and a second dielectric. The second dielectric is dispersed in the first dielectric. The second dielectric is then removed from the second dielectric by using a chemical dissolution. The removal of the second dielectric from the first dielectric leaves... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20080142930 - Porous composition of matter, and method of making same: A low-k organic dielectric material having stable nano-sized porous is provided as well as a method of fabricating the same. The porous low-k organic dielectric material is made from a composition of matter having a vitrification temperature (Tv-comp) which includes a b-staged thermosetting resin having a vitrification temperate (Tv-resin), a... Agent: Scully, Scott, Murphy & Presser, P.c.

20080142931 - Method of impurity introduction, impurity introduction apparatus and semiconductor device produced with use of the method: l

20080142932 - Semiconductor device with plastic housing composition and method for producing the same: A semiconductor device with a plastic housing composition includes a semiconductor chip and an internal wiring. The plastic housing composition is electrically conductive and electrically connected to a first contact pad of the internal wiring. A first side of the semiconductor chip is electrically insulated from the plastic housing composition... Agent: Edell , Shapiro & Finnan , Llc

20080142933 - Semiconductor device and fabricating method thereof: A semiconductor device and fabricating method thereof are provided. A first substrate with an inductor cell and a through-electrode is connected to a second substrate having an RF device circuit unit. A connecting electrode can electrically connect the inductor cell to the RF device circuit unit.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080142934 - Integrated circuit package with elevated edge leadframe: An integrated circuit package system includes an elevated edge leadframe array, isolating leadframes of the elevated edge leadframe array, validating integrated circuit die attached to the leadframes, and forming integrated circuit packages including the integrated circuit die.... Agent: Law Offices Of Mikio Ishimaru

20080142935 - Lead-frame circuit package:

20080142936 - Semiconductor device package diepad having features formed by electroplating: Embodiments in accordance with the present invention relate to the fabrication of packages for semiconductor devices, and in particular to the use of electroplating techniques to form features on the surface of a metal lead frame. In accordance with one embodiment, electroplating is used to fabricate non-integral pin portions shaped... Agent: Townsend And Townsend And Crew, LLP

20080142937 - Leadframe on heat sink (lohs) semiconductor packages and fabrication methods thereof: The invention relates to leadframe semiconductor packages mounted on a heat-sink and fabrication thereof. A system in package (SiP) comprises a leadframe having extension leads, configured with divisional heat sinks serving as power and ground nets. A set of semiconductor dies is attached by adhesive on the central region of... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080142938 - Integrated circuit package system employing a support structure with a recess: An integrated circuit package system that includes: providing an electrical interconnect system including a support structure and a lead-finger system; and processing a top edge of the support structure to include a recess for preventing mold bleed.... Agent: Law Offices Of Mikio Ishimaru

20080142939 - Tools structure for chip redistribution and method of the same: The present invention discloses a tool structure for chip redistribution and method of chip redistribution. The tool structure comprises a base substrate, a separable adhesion film formed on the base substrate, and the patterned glues placed on the separable adhesion film for fixating the dice covered by the core paste... Agent: Kusner & Jaffe Highland Place Suite 310

20080142941 - 3d electronic packaging structure with enhanced grounding performance and embedded antenna: The present invention proposes a 3D electronic packaging structure with enhanced grounding performance and embedded antenna, and the packaging unit can achieve multi-chip stacking through the signal contacts on the top and bottom surfaces of the unit. A single or multiple grounding layers are on the back of the substrate... Agent: Kusner & Jaffe Highland Place Suite 310

20080142943 - Integrated circuit package system with thermo-mechanical interlocking substrates: An integrated circuit package system includes providing a plurality of substrates; inserting a receptor in one of the substrates, the receptor held in and not extending through the one of the substrates; inserting a conductive post in another of the substrates; mounting the one of the substrates and the another... Agent: Law Offices Of Mikio Ishimaru

20080142942 - Method and apparatus for multi-chip packaging: A method and apparatus are provided for multi-chip packaging. A multi-chip package (100) includes a substrate (105) and a plurality of semiconductor dice (110, 120, 130). A first semiconductor die (110) is physically coupled to an upper face of the substrate (105), the first semiconductor die (110) being a smallest... Agent: Ingrassia Fisher & Lorenz, P.c.

20080142945 - Semiconductor package with redistribution layer of semiconductor chip directly contacted with substrate and method of fabricating the same: Provided are a semiconductor package in which wiring layers connected to a semiconductor chip electrically contact circuit patterns of a substrate and a method of manufacturing the same. The semiconductor package includes the substrate and the semiconductor chip. The substrate includes a first concave portion disposed on the upper surface... Agent: Marger Johnson & Mccollom, P.c.

20080142944 - Stacked package and method for manufacturing the package: In a stacked package in which a plurality of packages having semiconductor elements mounted on substrates are stacked, while being electrically connected together, by use of connection sections, wherein the connection sections are formed from pillar-like members and solder joint sections and the upper package is supported on the lower... Agent: Drinker Biddle & Reath (dc)

20080142940 - Stacked-flip-assembled semiconductor chips embedded in thin hybrid substrate: A semiconductor system having a substrate (101) including a rigid insulating interposer (110) with a high modulus and a top (140) and a bottom (150) low-modulus tape with flip-attached semiconductor chips (120, 130). The assembled chips, with the passive surfaces facing each other, are located in an opening (114) of... Agent: Texas Instruments Incorporated

20080142947 - Chip package and method of manufacturing the same: A chip package including a metal layer, a film-like circuit layer, a chip, a lead matrix and an encapsulant is provided. The film-like circuit layer disposed on the metal layer includes an insulating film disposed on the metal layer and a circuit layer disposed on the insulating film. The circuit... Agent: Jianq Chyun Intellectual Property Office

20080142949 - Semiconductor assembly for improved device warpage and solder ball coplanarity: A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is substantially coplanar with the chip, without warpage. One of the chip sides is attached to the first substrate surface using adhesive material (504), which has... Agent: Texas Instruments Incorporated

20080142948 - Semiconductor device: On a case member of a semiconductor device, a screw block terminal or the like for connection to external equipment is attached. The screw block terminal or the like arranged on a region inside a base plate is attached to a terminal attachment member. Terminal attachment member has wall-like bodies,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080142946 - Wafer level package with good cte performance: The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die... Agent: Kusner & Jaffe Highland Place Suite 310

20080142950 - Semiconductor integrated circuit package having electrically disconnected solder balls for mounting: Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any circuit of the die, i.e., “dummy” solder balls, and are used to temporarily hold the die in position with... Agent: Schwegman, Lundberg & Woessner/micron

20080142951 - Circuit board structure with embedded semiconductor chip: The invention provides a printed circuit board having an embedded semiconductor chip, includes: a carrier board having a first and an opposing second surface and a through hole penetrating the first and second surfaces; a semiconductor chip disposed in the through hole and having an active surface and an inactive... Agent: Schmeiser Olsen & Watts

20080142952 - Semiconductor package: There is provided a semiconductor package including: a substrate having a plurality of electrode pads on a surface thereof; a semiconductor chip mounted on the substrate, the semiconductor chip electrically connecting with the plurality of electrode pads; and a stiffener arranged on the substrate so as to surround the semiconductor... Agent: Ibm Microelectronics Intellectual Property Law

20080142953 - Semiconductor device: With a conventional semiconductor device, there occurs deterioration in adhesion strength of bonded parts between a lid and a substrate. A semiconductor device according to an embodiment of the invention includes a substrate, a semiconductor chip with one of surfaces thereof, facing downward, mounted on the substrate, and a lid... Agent: Young & Thompson

20080142955 - Heat-dissipating structure and heat-dissipating semiconductor package having the same: A heat-dissipating structure and a heat-dissipating semiconductor package having the same are disclosed in the present invention. The heat-dissipating semiconductor package includes a chip carrier, a flip chip semiconductor chip attached and electrically connected to the chip carrier, and a heat sink bonded to the flip chip semiconductor chip via... Agent: Edwards Angell Palmer & Dodge LLP

20080142954 - Multi-chip package having two or more heat spreaders: A multi-chip package may include at least one integrated circuit die disposed on a substrate, and a local heat spreader is thermally coupled with the die. A global heat spreader is thermally coupled with this local heat spreader. The global heat spreader may also be coupled with one or more... Agent: Intel Corporation C/o Intellevate, Llc

20080142960 - Circuit device with at least partial packaging and method for forming: A circuit device is placed within an opening of a conductive layer which is then partially encapsulated with an encapsulant so that the active surface of the circuit device is coplanar with the conductive layer. At least a portion of the conductive layer may be used as a reference voltage... Agent: Freescale Semiconductor, Inc. Law Department

20080142958 - Hermetic seal and reliable bonding structures for 3d applications: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned... Agent: Scully, Scott, Murphy & Presser, P.c.

20080142959 - Method and structure for optimizing yield of 3-d chip manufacture: The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip... Agent: Whitham, Curtis & Christofferson, P.c.

20080142956 - Stress management in bga packaging: The present semiconductor structure includes a substrate having a planar surface, a semiconductor chip attached to the planar surface of the substrate, the chip preferably being of the same thickness as or thinner than the substrate, and a package body attached to the substrate and to the semiconductor chip. The... Agent: Paul J. Winters

20080142957 - Three-dimensional package and method of making the same: The present invention relates to a three-dimensional package and method of making the same. The package includes a first substrate, a first chip, a second substrate, a second chip, a spacer, and a first molding compound. The first chip is electrically connected to the first substrate. The second substrate is... Agent: Volentine & Whitt Pllc

20080142961 - Ceramic package substrate with recessed device: A ceramic package substrate has a recess. This allows a device in that recess to be close to a die attached to the substrate's top side, for better performance. The device may be an array capacitor, an in-silicon voltage regulator, or another device or devices.... Agent: Intel Corporation C/o Intellevate, Llc

20080142962 - Integrated circuit packages, systems, and methods: An integrated circuit package includes a first capacitor supported by a surface of a substrate, and a second capacitor supported by the surface of the substrate. The first capacitor is within a die shadow region, and the second capacitor lies outside of the die shadow region.... Agent: Schwegman, Lundberg & Woessner, P.a.

20080142963 - Semiconductor package having non-ceramic based window frame: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds.... Agent: Hogan & Hartson L.l.p.

20080142965 - Chip package: A chip package includes: a circuit board formed with conductive traces; a semiconductor chip formed with conductive pads; a bridging member sandwiched between the circuit board and the semiconductor chip and including an elastic dielectric body and spaced apart flexible conductive lines, each of which extends through the elastic dielectric... Agent: Davidson Berquist Jackson & Gowdey LLP

20080142966 - Metal particles-dispersed composition and flip chip mounting process and bump-forming process using the same: There is provided a composition that is suitably used for a flip chip mounting process or a bump-forming process. The composition comprises a first component 3a, a second component 3b, metal particles 1,1′ and a convection additive. The metal particles 1,1′ are dispersed in the second component 3b. The convection... Agent: Wenderoth, Lind & Ponack L.l.p.

20080142967 - Semiconductor device: A semiconductor device including: a semiconductor layer including an element formation region including an element; an interlayer dielectric layer above the semiconductor layer; an electrode pad above the interlayer dielectric layer; a passivation layer above the electrode pad and having an opening exposing at least part of the electrode pad;... Agent: Harness, Dickey & Pierce, P.L.C

20080142964 - Tubular-shaped bumps for integrated circuit devices and methods of fabrication: An integrated circuit die includes one or more tubular-shaped conductive bumps disposed on one side thereof. The tubular-shaped bumps may comprise copper, and may be used for input/output (I/O) signaling. The die may also include solid bumps for I/O and/or power delivery. The tubular-shaped bumps are relatively more compliant than... Agent: Intel Corporation C/o Intellevate, Llc

20080142969 - Microball mounting method and mounting device: The objective of the invention is to present a mounting method by which mounting at higher densities and finer pitches can be handled so as to mount extremely small conductive balls. The mounting method of the present invention may be used to prepare porous base member 210 and mask set... Agent: Texas Instruments Incorporated

20080142968 - Structure for controlled collapse chip connection with a captured pad geometry: A structure for controlled collapse chip connection disposed above a substrate. The substrate has two faces, with the second face being disposed substantially parallel to the first face. A contact pad in signal communication with the integrated circuit is disposed on the second face. A first passivation layer forms a... Agent: Cantor Colburn LLP - Ibm Fishkill

20080142970 - Nanowire chemical mechanical polishing: A planarized nanowire structure and a method for planarizing a nanowire structure are presented. The method provides nanowires with tips, formed overlying a substrate. A first insulator layer is deposited partially covering the nanowires. The first insulator layer is coated with a spin-on insulator layer, completely covering the nanowires. In... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080142971 - Interconnect structure and method of manufacturing a damascene structure: An interconnect structure is provided, including a layer of dielectric material having at least one opening and a first barrier layer on sidewalls defining the opening. A ruthenium-containing second barrier layer overlays the first barrier layer, the second barrier layer having a ruthenium zone, a ruthenium oxide zone, and a... Agent: Buchanan, Ingersoll & Rooney Pc

20080142973 - Method of forming wiring structure and semiconductor device: A micronized wiring structure is obtained by optimizing film forming modes of barrier metal films as being adapted respectively to a via-hole and a wiring groove, wherein sputtering processes are adopted herein, which are specifically the multi-step sputtering process for formation of the barrier metal film over the via-hole, and... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080142972 - Methods and systems for low interfacial oxide contact between barrier and copper metallization: The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a... Agent: Larry Williams

20080142974 - Semiconductor device and method for manufacturing same: This invention discloses a semiconductor device including an insulating film having a recess therein; an electric conductor formed inside the recess; a manganese silicate film formed on an upper surface of the conductor, the manganese silicate film being formed of a reaction product of a manganese with a silicon oxide... Agent: Sonnenschein Nath & Rosenthal LLP

20080142975 - Dummy patterns and method of manufacture for mechanical strength of low k dielectric materials in copper interconnect structures for semiconductor devices: A method for fabricating a semiconductor device. The method includes providing a semiconductor substrate including a surface region. The method forms a first interlayer dielectric overlying the surface region and forms an interconnect layer overlying the first interlayer dielectric layer. The method also forms a low K dielectric layer overlying... Agent: Townsend And Townsend And Crew, LLP

20080142976 - Interposer and electronic device using the same: Means for Solution: This interposer (10) comprises the silicon substrate (12), a plurality of through-hole conductors (20) formed on the above-described silicon substrate, and a capacitor (15) formed with the upper electrodes (14) and the lower electrodes (18) formed by extending the land portions of the above-described through-hole conductors and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080142977 - Semiconductor device having a multilayer interconnection structure: A semiconductor device has a multilayer interconnection structure, wherein the multilayer interconnection structure comprises at least a first interconnection layer and a second interconnection layer formed over the first interconnection layer, the first interconnection layer comprises a first conductor pattern embedded in a first interlayer insulation film and constituting a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080142978 - Chip structure and process for forming the same: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric... Agent: Mou-shiung Lin

20080142979 - Chip structure and process for forming the same: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric... Agent: Mou-shiung Lin

20080142980 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20080142981 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20080142982 - Semiconductor constructions, semiconductor processing methods, methods of forming contact pads, and methods of forming electrical connections between metal-containing layers: Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire lateral periphery of the component, and may... Agent: Wells St. John P.s.

20080142983 - Device having contact pad with a conductive layer and a conductive passivation layer: A method and apparatus is disclosed for sequential processing of integrated circuits, particularly for conductively passivating a contact pad with a material which resists formation of resistive oxides. In particular, a tank is divided into three compartments, each holding a different solution: a lower compartment and two upper compartments divided... Agent: Knobbe Martens Olson & Bear LLP

20080142987 - Computer automated design system, a computer automated design method, and a semiconductor integrated circuit: A computer automated design system includes a subject routing module configured to set a first grid area and a first diagonal grid area and route a first wire in the first grid area and a first diagonal wire extending diagonally to a longitudinal direction of the first wire and a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080142984 - Multi-layer electrode structure: An electrode structure including two parallel electrical paths. A plurality of electrode layers, generally tabular in form is formed in a stack, the outermost layers providing electrical contacts, and defining a first electrical current path through the stack. Two sidewall conductor layers are formed to abut either end of the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080142986 - Semiconductor integrated circuit: A conductive pattern is provided in the vicinity of a bonding pad and connection is made therebetween using pillar-shaped leading interconnections. By providing an insulating film, in addition to the pillar-shaped leading interconnections, between the conductive pattern and the bonding pad, the impact at the time of bonding is weakened... Agent: Mcginn Intellectual Property Law Group, Pllc

20080142985 - Wiring substrate with improvement in tensile strength of traces: A wiring substrate with tensile-strength enhanced traces primarily comprises a core layer, a plurality of connecting pads, a plurality of traces, and a solder resist where the connecting pads and the traces are disposed on a top of the core layer. The solder resist is formed over the top of... Agent: Troxell Law Office Pllc

20080142988 - Method for selective removal of damaged multi-stack bilayer films: A method for removing a damaged low dielectric constant material following an etch process, an ashing process, or a wet cleaning process is described. A dry, non-plasma removal process is implemented to remove a thin layer of damaged material on a feature following formation of the feature. The dry, non-plasma... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080142989 - Semiconductor device and manufacturing method of semiconductor device: In one aspect of the present invention, A method for manufacturing a semiconductor device may include forming a first wiring in a first insulating layer on a base member, forming a second insulating layer on the first insulating layer, forming a first hole in the second insulating layer so as... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080142991 - Thin passivation layer on 3d devices: Embodiments of the invention include a device with stacked substrates. Conducting interconnecting structures of one substrate are bonded to conducting interconnecting structures of another substrate. A passivating layer may be on the conducting interconnecting structures between the substrates and may be formed by an atomic layer deposition process or a... Agent: Intel/blakely

20080142990 - Three-dimensional integrated circuits with protection layers: A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having... Agent: Slater & Matsil, L.l.p.

20080142994 - Contact pad and bump pad arrangement for high-lead or lead-free bumps: A semiconductor package assembly comprises a first conductive pad on a semiconductor substrate; a second conductive pad on a package substrate; a bump physically coupled between the first conductive pad and the second conductive pad, wherein the bump is substantially lead-free or high-lead-containing; the bump has a first interface with... Agent: Steven H. Slater Slater & Matsil, L.l.p.

20080142993 - Flip-chip mounting substrate: It is a flip-chip mounting substrate according to the invention has a wiring pattern in which bonding pads and predetermined parts of lead wires continuously extending from the bonding pads are exposed from an insulating layer or a solder resist. In the flip-chip mounting substrate, exposed parts of the wiring... Agent: Rankin, Hill & Clark LLP

20080142992 - Molding compound adhesion for map-molded flip-chip: A semiconductor device whose semiconductor device components have particularly reliable adhesion to a plastic housing composition surrounding them is intended to be produced by a simplest possible method. An adhesion promoting solution is introduced into the interspace between the front side of the flip-chips and the top side of the... Agent: Edell , Shapiro & Finnan , Llc

20080142995 - Layout and process to contact sub-lithographic structures: An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed... Agent: Keusey, Tutunjian & Bitetto, P.c.

20080142996 - Controlling flow of underfill using polymer coating and resulting devices: According to one embodiment, a polymer coating is disposed on a surface of a package substrate. The polymer coating comprises a material capable of inhibiting the flow of an underfill material into a keep-out zone (KOZ). In a further embodiment, a die is disposed on the substrate and a layer... Agent: Intel Corporation C/o Intellevate, Llc

20080142997 - Metal structure: A semiconductor wafer comprises a plurality of die areas, at least a first scribe line area and at least a second scribe line area surrounding each die area, at least a first metal structure positioned in the first scribe line area, and at least a second metal structure positioned in... Agent: North America Intellectual Property Corporation

20080142998 - Zero-order overlay targets: A zero-order overlay target comprises a first zero-order line array fabricated on a first layer of a semiconductor structure, the first zero-order line array having a first pitch, and a second zero-order line array fabricated on a second layer of the semiconductor structure, the second zero-order line array having a... Agent: Fulbright & Jaworski L.l.p.

20080135824 - Method and structure of a multi-level cell resistance random access memory with metal oxides: A method and structure of a bistable resistance random access memory comprise a plurality of programmable resistance random access memory cells where each programmable resistance random access memory cell includes multiple memory members for performing multiple bits for each memory cell The bistable RRAM includes a first resistance random access... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080135825 - Phase-change memory device and method of fabricating the same: Provided are a phase-change memory device and a method of fabricating the same. The phase-change memory device includes a transistor disposed on a semiconductor substrate and including a gate electrode and first and second impurity regions disposed on both sides of the gate electrode; a bit line electrically connected to... Agent: Lahive & Cockfield, LLP

20080135826 - Controlled nanowire in permanent integrated nano-templates and method of fabricating sensor and transducer structures: This invention presents a novel method to form uniform or heterogeneous, straight or curved and size-controllable nanostructures including, for example, nanotubes, nanowires, nanoribbons, and nanotapes, including SiNW, using a nanochannel template. In the case of semiconductor nanowires, doping can be included during growth. Electrode contacts are present as needed and... Agent: Nixon Peabody, LLP

20080135827 - Mim transistor: The invention concerns a conducting layer having a thickness of between 1 and 5 atoms, an insulated gate being formed over a part of the conducting layer.... Agent: Seed Intellectual Property Law Group Pllc

20080135828 - Photoelectric converting film stack type solid-state image pickup device: A photoelectric converting film stack type solid-state image pickup device comprising: a semiconductor substrate in which a signal read circuit is formed; and at least one photoelectric converting film interposed between two electrode films, said at least one photoelectric converting film being stacked above the semiconductor substrate, wherein a signal... Agent: Sughrue-265550

20080135829 - Nitride semiconductor light emitting device and fabrication method thereof: Provided is a nitride semiconductor light emitting device including: a first nitride semiconductor layer; an active layer formed above the first nitride semiconductor layer; and a “C (carbon)”-doped second nitride semiconductor layer formed above the active layer. According to the present invention, the crystallinity of the active layer is enhanced,... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080135830 - Semiconductor structures with structural homogeneity: Semiconductor structures are formed with semiconductor layers having reduced compositional variation. Top surfaces of the semiconductor layers are substantially haze-free.... Agent: Goodwin Procter LLP Patent Administrator

20080135831 - Optoelectronic circuit employing a heterojunction thyristor device to convert a digital optical signal to a digital electrical signal: An optoelectronic circuit includes a resonant cavity formed on a substrate and into which is injected an input digital optical signal that encodes bits of information (each bit representing an OFF logic level or an ON logic level). A heterojunction thyristor device, formed in the resonant cavity, produces an output... Agent: Gordon & Jacobson, P.c.

20080135832 - Apparatus and method for control of tunneling in a small-scale electronic structure: A microelectronic structure comprising a channel dimensioned such that tunneling is a significant transport mode for charge carriers. The charge carriers have a coherence length depending on the channel material and the carrier type and a wavelength. A potential varying spatially along the length of the channel is applied, the... Agent: Martin D. Moynihan Prtsi

20080135835 - Composite material and light emitting element: An object of the invention is to provide a composite material with which a light emitting element can be manufactured to have superior heat resistance, and another is to have durability high enough to be driven stably for a long time. Another object is to provide a composite material with... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080135833 - Configurationally controlled n,n'-dicycloalkyl-substituted naphthalene-based tetracarboxylic diimide compounds as n-type semiconductor materials for thin film transistors: A thin film transistor comprises a layer of organic semiconductor material comprising a configurationally controlled N,N′-dicycloalkyl-substituted naphthalene-1,4,5,8-bis-carboximide compound having a substituted or unsubstituted alicyclic ring independently attached to each imide nitrogen atom with the proviso that at least one of the two alicyclic rings is necessarily a 4-substituted cyclohexyl ring... Agent: Andrew J. Anderson Patent Legal Staff

20080135839 - Method of fabricating thin film transistor: A method of fabricating a thin film transistor, in which source and drain electrodes are formed through a solution process, even all stages which include formation of electrodes on a substrate, formation of an insulator layer, and formation of an organic semiconductor layer are conducted through the solution process. In... Agent: Buchanan, Ingersoll & Rooney Pc

20080135837 - Method of fabricating thin film transistor having multilayer structure and active matrix display device including the thin film transistor: Provided are a method of fabricating a multilayered thin film transistor using a plastic substrate and an active matrix display device including the thin film transistor fabricated by the method. The method includes: preparing a substrate formed of plastic; forming a buffer insulating layer on the plastic substrate; forming a... Agent: Ladas & Parry LLP

20080135834 - Prevention of oxidation of carrier ions to improve memory retention properties of polymer memory cell: Improving memory retention properties of a polymer memory cell are disclosed. The methods include providing a semiconducting polymer layer containing at least one organic semiconductor and at least one of a carrier ion oxidation preventer and an electrode oxidation preventer. The oxidation preventers may contain at least one of 1)... Agent: Amin, Turocy & Calvin, LLP

20080135836 - Self-aligned process to manufacture organic transistors: Semiconducting device and method of manufacturing a semiconducting device in which organic thin film transistors (TFTs) and other components are fabricated on a substrate (206), using a hybrid technology of lithographic and printing steps. A lithographically defined resist pattern (211, 311) provides barriers and cavities which serve to guide subsequently... Agent: Philips Intellectual Property & Standards

20080135838 - Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same: Provided are a thin film transistor, a method of fabricating the thin film transistor, and an organic light emitting diode display device (OLED display device) including the thin film transistor having improved characteristics of the thin film transistor. The thin film transistor includes: a substrate; a semiconductor layer disposed on... Agent: Stein, Mcewen & Bui, LLP

20080135841 - Semiconductor wafer, method of manufacturing the same and method of manufacturing semiconductor chip: A semiconductor wafer 10 has a plurality of semiconductor chip areas 10a and a scribe area 10b, each of the semiconductor chip areas 10a having semiconductor elements and electrode pads (electrode portions) 16a electrically connected to the respective semiconductor elements, the scribe area 10b having monitor elements and electrode pads... Agent: Steptoe & Johnson LLP

20080135840 - Test structure: A test structure to detect vertical leakage in a multi-layer flip chip pad stack or similar semiconductor device. The test structure is integrated into the semiconductor device when it is fabricated. A metal layer includes at least two portions that are electrically isolated from each other; one portion being disposed... Agent: Slater & Matsil, L.l.p.

20080135842 - Method for manufacturing array board for display device: An array for a display device is formed by adhering a positive dry film resist, which has a positive photoresist resin layer over a supporting film, to a substrate such that the photoresist resin layer adheres on a surface of the substrate. The supporting film is then released from the... Agent: Birch Stewart Kolasch & Birch

20080135844 - Semiconductor device and its manufacturing method: An object of the present invention is to provide an active matrix type display unit having a pixel structure in which a pixel electrode formed in a pixel portion, a scanning line (gate line) and a data line are suitably arranged, and high numerical aperture is realized without increasing the... Agent: Fish & Richardson P.c.

20080135843 - Thin film transistor structure: A thin film transistor (TFT) structure is provided. The TFT comprises a gate, a first electrode, a second electrode, a dielectric layer, and a channel layer. By overlapping the area between the first electrode and the gate, the TFT structure acquires a parasitic capacitor that is unaffected by manufacture deviations.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080135846 - Thin film transistor substrate and method of manufacture: A thin film transistor (“TFT”) substrate in which the size of a pixel TFT formed in a display area is reduced using a single slit mask, and the length of the channel area of a protection TFT constituting an electrostatic discharge protection circuit formed in a non-display area is formed... Agent: Macpherson Kwok Chen & Heid LLP

20080135847 - Thin film transistor, method of fabricating the same, and organic light emitting display device including the same: A thin film transistor (TFT) having improved characteristics, a method for fabricating the same, and an organic light emitting display device (OLED) including the same. The TFT is constructed with a substrate, a semiconductor layer disposed on the substrate and including a channel region, source and drain regions, a gate... Agent: Robert E. Bushnell

20080135845 - Thin-film transistor substrate and method of manufacturing the same: A thin-film transistor substrate includes a gate line, a capacitor dielectric layer, a gate insulation layer, an active pattern, a data line, a protection layer, and a pixel electrode. The gate wiring including a gate electrode, a lower storage electrode, and a gate metal pad is disposed on a substrate.... Agent: H.c. Park & Associates, Plc

20080135850 - Process for manufacturing a semiconductor device, a semiconductor device and a high-frequency circuit: A process for manufacturing a semiconductor device, provides that a silicide layer is formed, an amorphous semiconductor layer is applied both to the silicide layer and to an open monocrystalline semiconductor region, adjacent to the silicide layer, and during a subsequent temperature treatment, the amorphous semiconductor layer is crystallized proceeding... Agent: Muncy, Geissler, Olds & Lowe, Pllc

20080135848 - Semiconductor device: When a semi-conductor film is irradiated with conventional pulsed laser light, unevenness, which is called as ridge, is caused on the surface of the semiconductor film. In the case of a top-gate type TFT, element characteristics are changed depending on the ridge. In particular, there is a problem in that... Agent: Nixon Peabody LLP

20080135849 - Thin film transistor and method of manufacturing the same: A thin film transistor includes a polysilicon layer formed over a substrate having a channel region, a source region and a drain region, a conductive layer formed in an upper layer of the polysilicon layer for covering at least a part of the source region and the drain region, an... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080135851 - Display and method of manufacturing the same: The present invention provides a display comprising a panel having a display region for displaying an image and a peripheral region defined therein, a plurality of thin film transistors (TFTs) formed in the display region, p-type and n-type TFTs formed in the peripheral region, and at least one photo diode... Agent: Macpherson Kwok Chen & Heid LLP

20080135853 - Dislocation reduction in non-polar iii-nitride thin films: Lateral epitaxial overgrowth of non-polar III-nitride seed layers reduces threading dislocations in the non-polar III-nitride thin films. First, a thin patterned dielectric mask is applied to the seed layer. Second, a selective epitaxial regrowth is performed to achieve a lateral overgrowth based on the patterned mask. Upon regrowth, the non-polar... Agent: Gates & Cooper LLP Howard Hughes Center

20080135854 - Field effect transistor including a group iii-v compound semiconductor layer: A field effect transistor (FET) includes a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having a band gap energy greater than that of the first semiconductor layer. The first and second semiconductor layers are made of a... Agent: Birch Stewart Kolasch & Birch

20080135852 - Gallium nitride-based semiconductor stacked structure, method for fabrication thereof,gallium nitride-based semiconductor device and lamp using the device: A gallium nitride-based semiconductor stacked structure includes a single crystal substrate, a low-temperature buffer layer grown at a low temperature in a region contiguous to the single crystal substrate and a gallium nitride-based semiconductor layer overlying the low-temperature buffer layer. The low-temperature buffer layer possesses therein a single crystal layer... Agent: Sughrue Mion, Pllc

20080135855 - Alternative doping for group iii nitride leds: A light emitting diode is disclosed that is formed in the Group III nitride material system. The diode includes respective n-type and p-type layers for current injection and light emission. At least one n-type Group III nitride layer in the diode has dopants selected from the group consisting of elements... Agent: Summa, Allan & Additon, P.a.

20080135856 - Light emitting device having vertical topology and method for manufacturing the same: A light emitting device having a vertical topology, which is capable of achieving an enhancement in light emission efficiency and reliability, and a method for manufacturing the same are disclosed. The light emitting device includes a first-conductivity-type semiconductor layer, a light emitting layer arranged over the first-conductivity-type semiconductor layer, and... Agent: Birch Stewart Kolasch & Birch

20080135857 - Array substrate, method of manufacturing the same, and method of repairing line in the same: An array substrate includes a substrate, a gate line on the substrate, a data line crossing the gate line to define a pixel region, a thin film transistor connected to the gate and data lines, a pixel electrode in the pixel region, and a common electrode including first, second, third,... Agent: Mckenna Long & Aldridge LLP

20080135858 - Light emitting element and light emitting device using the element: An object of the present invention is to provide a high-efficiency white light emitting element having a spectrum in a wide wavelength range. Another object is to provide a white light emitting element in which chromaticity of white color is hard to change over time. Still another object is to... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080135859 - Vertical structure led device and method of manufacturing the same: A method of manufacturing a vertical structure light emitting diode device, the method including: sequentially forming a first conductivity type III-V group compound semiconductor layer, an active layer, and a second conductivity type III-V group compound semiconductor layer on a substrate for growth; bonding a conductive substrate to the second... Agent: Mcdermott Will & Emery LLP

20080135864 - High light extraction efficiency light emitting diode (led) with emitters within structured materials: Light Emitting Diodes (LEDs) where the emission region, usually a (Al,In,Ga)N layer, is structured for efficient light extraction, are disclosed. The structuring is designed for light extraction from thin films, such as a photonic crystal acting as a diffraction grating. In addition, the structuring controls the in-plane emission and allows... Agent: Gates & Cooper LLP Howard Hughes Center

20080135865 - Illuminating device: An illumination device comprising a connection carrier (1), at least one light-emitting diode (10), an electrically insulating layer (3) and a fixing device (4) is specified. The connection carrier (1) has a first main area (1a) and a second main area (1b) remote from the first main area. The light-emitting... Agent: Cohen Pontani Lieberman & Pavane LLP.

20080135862 - Light-emitting semiconductor device, light-emitting system and method for fabricating light-emitting semiconductor device: A chip-type light-emitting semiconductor device includes: a substrate 4; a blue LED 1 mounted on the substrate 4; and a luminescent layer 3 made of a mixture of yellow/yellowish phosphor particles 2 and a base material 13 (translucent resin). The yellow/yellowish phosphor particles 2 is a silicate phosphor which absorbs... Agent: Mcdermott Will & Emery LLP

20080135866 - Method of forming three dimensional features on light emitting diodes for improved light extraction: A method is disclosed for obtaining a high-resolution lenticular pattern on the surface of a light emitting diode. The method comprises imprinting a patterned sacrificial layer of etchable material that is positioned on a semiconductor surface that is in turn adjacent a light emitting active region, and thereafter etching the... Agent: Summa, Allan & Additon, P.a.

20080135863 - Optical semiconductor device and optical transmission device: An optical semiconductor device comprising: an internal lead; an optical semiconductor element mounted on the internal lead and electrically connected to the internal lead; a sealing resin for sealing the optical semiconductor element and the internal lead, the sealing resign provided with an attachment hole formed by side surfaces and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080135860 - Rules for efficient light sources using phosphor converted leds: An LED lamp including an LED and one or more phosphors, wherein for each phosphor, a figure of merit (FOM) defined as the product of (incident LED flux)×(excitation cross-section of the phosphor)×(phosphor material decay time) is less than 0.3. Such an arrangement provides a light emitting device with improved lumen... Agent: Fay Sharpe LLP

20080135861 - Spatial localization of light-generating portions in leds: Light-emitting devices (e.g., LEDs) and methods associated with such devices are provided. In some embodiments, the device includes a distribution of light-generating portions (including active regions) that are spatially localized and separated (e.g., horizontally or vertically) from one or more patterned light extraction portions. This arrangement can allow light generated... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.c.

20080135869 - Light emitting chip package and light source module: A light emitting chip package having a carrier, at least one light emitting chip and a thermal enhanced cover is provided. The carrier includes a plurality of through holes. The light emitting chip is disposed on the carrier. The light emitting chip has an active surface, a back surface opposite... Agent: Jianq Chyun Intellectual Property Office

20080135868 - Nitride semiconductor light emitting element and method for manufacturing the same: In an element structure of a nitride semiconductor light emitting element, the laminate including a light emitting part having a laminate structure of a first n-type layer 13, a p-type clad layer 15 and an active layer 14 sandwiched between them, and a second n-type layer 16 present at the... Agent: Wenderoth, Lind & Ponack, L.l.p.

20080135867 - Semiconductor device having current spreading layer: A semiconductor device has a current spreading layer between a semiconductor material and an electrode for connecting the semiconductor material to an electrical power supply. The current spreading layer has two or more sub-layers of a first conductive material with patterned regions of a second conductive material distributed between the... Agent: Wells St. John P.s.

20080135870 - Semiconductor device and method of manufacturing the same: A punch-through type IGBT generally has a thick p++-type collector layer. Therefore, the FWD need be externally attached to the IGBT when the IGBT is used as a switching element in an inverter circuit for driving a motor load, and thus the number of processes and components increases. In the... Agent: Morrison & Foerster LLP

20080135871 - Semiconductor component: A semiconductor component is disclosed. One embodiment provides a semiconductor body having a cell region with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side. A drift zone of the first conduction type in the cell... Agent: Dicke, Billig & Czaja

20080135872 - Trench polysilicon diode: Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body... Agent: Murabito Hao & Barnes LLP Third Floor

20080135873 - Inducement of strain in a semiconductor layer: Strain is induced in a semiconductor layer. Embodiments include inducing strain by, for example, creation of free surfaces.... Agent: Goodwin Procter LLP Patent Administrator

20080135874 - Patterned strained semiconductor substrate and device: A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive... Agent: Greenblum & Bernstein, P.L.C

20080135875 - Relaxed low-defect sgoi for strained si cmos applications: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the... Agent: Scully, Scott, Murphy & Presser, P.c.

20080135876 - Trench capacitors with insulating layer collars in undercut regions: Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the first layer opposite to the substrate. A mask is... Agent: Myers Bigel Sibley & Sajovec

20080135878 - Germanium semiconductor device and method of manufacturing the same: A germanium semiconductor device and a method of manufacturing the same are provided. The method includes the steps of: forming an isolation layer on a substrate using a shallow trench; forming a silicon-nitride layer on the substrate, and selectively etching the silicon nitride layer to expose source and drain regions;... Agent: Rabin & Berdo, Pc

20080135879 - Method of fabricating cmos transistor and cmos transistor fabricated thereby: In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by reducing the number of masks required. The method includes... Agent: Mills & Onello LLP

20080135877 - Semiconductor manufacturing method and semiconductor device: A production method for a semiconductor device according to the present invention includes: step (A) of providing a substrate including a semiconductor layer having a principal face, the substrate having a device isolation structure (STI) formed in an isolation region 70 for partitioning the principal face into a plurality of... Agent: Mark D. Saralino (mei) Renner, Otto, Boisselle & Sklar, LLP

20080135880 - Nitride semiconductor heterojunction field effect transistor: In the nitride semiconductor heterojunction field effect transistor of the present invention, the floating gate layer (32), as the third layer, is formed between the control gate electrode (34) and the AlGaN layer (11), and the potential for the electrons in the AlGaN layer (11), which is substantially neighboring the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080135881 - Semiconductor device, layout design method thereof, and layout design device using the same: A semiconductor device having a multilayer structure, each layer including: a dummy pattern for ensuring a flatness thereof; a pad area in which a bonding pad is formed; an input-output circuit area in which an input-output circuit is formed, the input-output circuit area being adjacent to the pad area in... Agent: Harness, Dickey & Pierce, P.L.C

20080135882 - Semiconductor element: s

20080135883 - Circuitry and method: A circuitry for differential amplifying, logical inversion, NAND and/or NOR operations is provided, which includes at least one depletion mode transistor having JFET characteristics. A method for determining the properties of an electrochemical circuitry is provided, including at least one semi-finished transistor, by applying a solidified electrolyte to selected sets... Agent: Harness, Dickey & Pierce, P.L.C

20080135884 - Solid-state imaging device and method for manufacturing same: A solid-state imaging device is provided and includes a photoelectric conversion unit and a charge transfer unit including charge transfer electrodes for transferring charges generated in the photoelectric conversion unit. Each of the charge transfer electrodes includes a first electrode of a first layer conductive film and a second electrode... Agent: Birch Stewart Kolasch & Birch

20080135885 - Solid-state imaging apparatus: A solid-state imaging apparatus includes a pixel array comprising a plurality of light receiving elements disposed in a charge transfer direction, the plurality of light receiving elements converting a light signal into an electric signal, a first charge transfer unit and a second charge transfer unit arranged on each side... Agent: Young & Thompson

20080135887 - Field effect transistor and fabrication method thereof: On a silicon wafer (1) to which carbon is intentionally added, an element separation insulation film (2) is selectively formed. A well (3) is formed in an element active region defined by the element separation insulation film (2). When the element separation insulation film (2) and the well (3) are... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080135888 - Finfet and method of manufacturing the same: A FinFET may include a semiconductor fin having a top surface and a sidewall having different crystal planes. A gate dielectric layer on the top surface and on the sidewall has different thicknesses. A gate electrode is formed on the gate dielectric layer across the top surface and sidewall of... Agent: Lee & Morse, P.c.

20080135886 - Semiconductor device and manufacturing method thereof: A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile... Agent: Charles N.j. Ruggiero, Esq. Ohlandt, Greeley, Ruggiero & Perle, L. L. P.

20080135889 - Structure and method for forming a planar schottky contact: A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is... Agent: Townsend And Townsend And Crew, LLP

20080135892 - Carbon nanotube field effect transistor and method of making thereof: This invention relates to field effect transistors having carbon nanotube contacts and to a method of making these field effect transistors. The field effect transistors have better contacts as the source and drains as well as the bridge are made of carbon nanotubes. The fabrication of the proposed embodiment becomes... Agent: National Research Council Of Canada 1200 Montreal Road

20080135890 - Field-effect transistor and method of manufacturing same: Disclosed is a manufacturing method for forming a FET on a glass substrate at low temperatures. A polycrystalline silicon layer 2 is formed on a glass substrate 1, germanium layers 11, 12 are formed on the polycrystalline silicon layer in regions that are to become a source and a drain,... Agent: Dickstein Shapiro LLP

20080135893 - Thin film transistor, method of fabricating the same, and display device including the same: A thin film transistor includes a substrate, a semiconductor layer on the substrate, a thermal oxide layer on the semiconductor layer, a gate electrode on the thermal oxide layer, the gate electrode positioned to correspond to a channel region of the semiconductor layer, an interlayer insulating layer on the substrate,... Agent: Lee & Morse, P.c.

20080135891 - Transistor device formed on a flexible substrate including anodized gate dielectric: A transistor device is formed on a flexible substrate such that device processing remains at a low temperature. A first gate dielectric layer is formed over gate metal by annodization, eliminating relatively high-temperature dielectric deposition processes and difficulties with in-process substrate deformation. A second gate dielectric layer may optionally be... Agent: Jas Ip Consulting

20080135894 - Transistor with improved tip profile and method of manufacture thereof: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving... Agent: Michael A. Bernadicou Blakely, Sokoloff, Taylor & Zafman LLP

20080135895 - Active pixel image sensor with common gate amplifier: A method and apparatus to operate a pixel circuit within an active pixel image sensor in a common gate amplifier mode.... Agent: Gauthier & Connors, LLP

20080135897 - method and system for image sensor and lens on a silicon back plane wafer: An improved image sensor, e.g., CCD, CID, CMOS. The image sensor includes a substrate, e.g., silicon wafer. The sensor also includes a plurality of photo diode regions, where each of the photo diode regions is spatially disposed on the substrate. The sensor has an interlayer dielectric layer overlying the plurality... Agent: Townsend And Townsend And Crew, LLP

20080135896 - Imaging method, apparatus, and system providing improved imager quantum efficiency: A method, apparatus, and system that provides one or more charge collecting protection regions in a pixel array, each formed below a storage region of a pixel cell, but not below at least one photosensor of one pixel of the array. The storage region includes a floating diffusion region and/or... Agent: Dickstein Shapiro LLP

20080135898 - Photodiode and photo integrated circuit having the same: A photodiode comprises a support substrate, an insulating layer formed over the support substrate, a silicon semiconductor layer formed over the insulating layer and having a device forming area and device isolation areas which surround the device forming area, a device isolation layer formed in the device isolation areas, a... Agent: Taft, Stettinius & Hollister LLP

20080135899 - Image sensor and method for manufacturing the same: An image sensor may comprise photodiodes on a semiconductor; color filters on the photodiodes; a planarization layer covering the color filters; and microlenses on the planarization layer, including alternate hydrophilic microlenses and hydrophobic microlenses contacting the edges of the hydrophilic microlenses, corresponding to respective color filters.... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080135900 - Method of forming organic ferroelectric film, method of manufacturing memory element, memory device, and electronic apparatus: A method of forming an organic ferroelectric film configured to include an organic ferroelectric material with a crystalline property as a principal material includes (a) forming a low crystallinity film having a crystallinity lower than a crystallinity of the organic ferroelectric film on one surface of a substrate, and (b)... Agent: Oliff & Berridge, Plc

20080135901 - Semiconductor memory and method of manufacturing the same: A semiconductor memory, comprising: a first memory cell transistor disposed on a semiconductor substrate; a second memory cell transistor disposed on the semiconductor substrate and having a first source-drain region in common with the first memory cell transistor; a first ferroelectric capacitor disposed with a via in between above a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080135902 - Barrier region for memory devices: One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory... Agent: Eschweiler & Associates, Llc National City Bank Building

20080135903 - Transistor gates including cobalt silicide, semiconductor device structures including the transistor gates, precursor structures, and methods of fabrication: A method for fabricating a transistor gate with a conductive element that includes cobalt silicide includes use of a sacrificial material as a place-holder between sidewall spacers of the transistor gate until after high temperature processes, such as the fabrication of raised source and drain regions, have been completed. In... Agent: Trask Britt, P.c./ Micron Technology

20080135904 - Cmos inverter based logic memory: A single-poly electrically erasable/programmable CMOS logic memory cell for mobile applications includes a CMOS inverter that share a single polysilicon floating gate, and an enhanced control capacitor including a control gate capacitor and an optional isolated P-well (IPW) capacitor formed below the control gate capacitor. The control gate capacitor includes... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080135905 - Selective coupling of voltage feeds for body bias voltage in an integrated circuit device: An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be... Agent: Transmeta C/o Murabito, Hao & Barnes LLP

20080135906 - Method and structure for fabricating capacitor devices for integrated circuits: A dynamic random access memory device including a capacitor structure, e.g., trench, stack. The device includes a substrate (e.g., silicon, silicon on insulator, epitaxial silicon) having a surface region. The device includes an interlayer dielectric region overlying the surface region. In a preferred embodiment, the interlayer dielectric region has an... Agent: Townsend And Townsend And Crew, LLP

20080135907 - Semiconductor device having a trench gate and method of fabricating the same: A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. Impurities are doped... Agent: Quintero Law Office, Pc

20080135908 - Semiconductor device and method of manufacturing the same: Provided are a semiconductor device and a method of manufacturing the semiconductor device, for example, a semiconductor device using carbon nanotubes or nanowires as lower electrodes of a capacitor, and a method of manufacturing the semiconductor device. The semiconductor device may include a lower electrode including a plurality of tubes... Agent: Harness, Dickey & Pierce, P.L.C

20080135909 - Display device and method of producing the same: In a thin film transistor using a polycrystalline semiconductor film, when a storage capacitor is formed, it is often that a polycrystalline semiconductor film is used also in one electrode of the capacity. In a display device having a storage capacitor and thin film transistor which have a polycrystalline semiconductor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080135910 - Semiconductor device and method of fabricating the same: In a semiconductor device and a method of fabrication thereof, a semiconductor device comprises a substrate including transistors and partitioned into a memory region and a logic region. A bit line is electrically connected to at least one of the transistors in the memory region. A logic capacitor is formed... Agent: Mills & Onello LLP

20080135911 - Nrom fabrication method: A method of fabricating an oxide-nitride-oxide (ONO) layer in a memory cell to retain charge well in the nitride layer includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer and oxidizing a top oxide layer, thereby causing oxygen to be introduced into the... Agent: Empk & Shiloh, LLP

20080135912 - Memory device and method of fabricating the same: A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first... Agent: Harness, Dickey & Pierce, P.L.C

20080135913 - Memory device protection layer: A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on... Agent: Harrity & Snyder, L.l.p.

20080135914 - Nanocrystal formation: In one embodiment, a method for forming a metallic nanocrystalline material on a substrate is provided which includes exposing a substrate to a pretreatment process, forming a tunnel dielectric layer on the substrate, exposing the substrate to a post-treatment process, forming a metallic nanocrystalline layer on the tunnel dielectric layer,... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080135915 - Non-volatile memory and method of fabricating the same: A non-volatile memory and method of fabricating the same are provided. The method of fabricating a non-volatile memory comprises forming a tunnel insulating layer, a first conductive layer and a first patterned hard mask layer on a semiconductor substrate sequentially. A first conductive pattern is formed by etching the first... Agent: Birch Stewart Kolasch & Birch

20080135916 - Non-volatile memory device and method of fabricating the same: Provided are example embodiments of a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a control gate electrode arranged on a semiconductor substrate, a gate insulating layer interposed between the semiconductor substrate and the control gate electrode, a storage node layer interposed... Agent: Harness, Dickey & Pierce, P.L.C

20080135917 - Method to form uniform tunnel oxide for flash devices and the resulting structures: Thin oxide films are grown on silicon which has been previously treated with a gaseous or liquid source of chloride ions. The resulting oxide is of more uniform thickness than obtained on untreated silicon, thereby allowing a given charge to be stored on a floating gate formed over said oxide... Agent: Macpherson Kwok Chen & Heid LLP

20080135920 - Gated diode nonvolatile memory process: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080135918 - P-channel nand in isolated n-well: A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities.... Agent: Harrity & Snyder, L.l.p.

20080135921 - Semiconductor device and method for manufacturing the same: An epitaxial layer is formed on an n+ semiconductor substrate by epitaxial growth. A gate trench is formed to the surface of gate trench so that the bottom of gate trench reaches middle of the epitaxial layer. A gate insulator is formed on the inner wall of gate trench and... Agent: Mcginn Intellectual Property Law Group, Pllc

20080135919 - Sonos flash memory and method for fabricationg the same: A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) flash memory, comprising: preparing a silicon substrate including a silicon oxide-silicon nitride-silicon oxide (ONO) layer, a first polysilicon layer and a first etch stop layer in sequence; etching the first etch stop layer along a direction of bit line; selectively etching the first... Agent: Squire, Sanders & Dempsey L.l.p.

20080135922 - Nonvolatile semiconductor memory device and method for manufacturing the same: A nonvolatile semiconductor memory device includes: a memory element, the memory element including: a semiconductor substrate; a first insulating film formed on a region in the semiconductor substrate located between a source region and a drain region, and having a stack structure formed with a first insulating layer, a second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080135923 - Non-volatile semiconductor memory devices: A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater... Agent: Myers Bigel Sibley & Sajovec

20080135924 - Multilayered box in fdsoi mosfets: A fully depleted MOSFET has a semiconductor-on-insulator substrate that includes a substrate material, a BOX positioned on the substrate material, and an active layer positioned on the BOX. The BOX includes a first layer of material with a first dielectric constant and a first thickness and a second layer of... Agent: Robert A. Parsons

20080135928 - Mos device resistant to ionizing radiation: An embodiment of a MOS device resistant to ionizing-radiation, has: a surface semiconductor layer with a first type of conductivity; a gate structure formed above the surface semiconductor layer, and constituted by a dielectric gate region and a gate-electrode region overlying the dielectric gate region; and body regions having a... Agent: Graybeal, Jackson, Haley LLP

20080135925 - Semiconductor device: MOS FETs are formed by a drain layer 101, a drift layer 102, P-type body areas 103, N+-type source areas 105, gate electrodes 108, a source electrode film 110, and a drain electrode film 111. In parallel to the MOS FETs, the drain layer 101, the drift layer 102, the... Agent: Nixon & Vanderhye, Pc

20080135926 - Semiconductor device: A semiconductor device includes: a drift layer having a superjunction structure; a semiconductor base layer selectively formed in a part of one surface of the drift layer; a first RESURF layer formed around a region having the semiconductor base layer formed thereon; a second semiconductor RESURF layer of a conductivity... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080135927 - Semiconductor device and manufacturing method thereof: An insulated gate semiconductor device, specifically, a trench lateral MOSFET having improved hot carrier resistance can be provided without increasing the number of processes and device pitch and without degrading device breakdown voltages and on-resistance characteristics RonA. A junction depth Xj of a p base region of a TLPM (trench... Agent: Rossi, Kimms & Mcdowell LLP.

20080135929 - Power semiconductor device: A power semiconductor device includes: a semiconductor substrate; a gate insulating film; a control electrode insulated from the semiconductor substrate by the gate insulating film; a first main electrode provided on a lower surface side of the semiconductor substrate; and a second main electrode provided on an upper surface side... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080135930 - Power semiconductor device: A power semiconductor device includes: a semiconductor substrate having a plurality of trenches formed in an upper surface thereof; a buried insulating film; a buried field plate electrode; a control electrode; a first main electrode provided on a lower side of the semiconductor substrate; and a second main electrode provided... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080135931 - Power semiconductor devices having termination structures and methods of manufacture: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region, source regions having the first... Agent: Townsend And Townsend And Crew, LLP

20080135932 - Semiconductor device and method for manufacturing same: A semiconductor device having plural active and passive elements on one semiconductor substrate is manufactured in the following cost effective manner even when the active and passive elements include double sided electrode elements. When the semiconductor substrate is divided into plural field areas, an insulation separation trench that penetrates the... Agent: Posz Law Group, Plc

20080135933 - Reduced electric field dmos using self-aligned trench isolation: A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first... Agent: Schneck & Schneck

20080135934 - Laterally diffused metal oxide semiconductor transistors: A laterally diffused metal oxide semiconductor transistor. The laterally diffused metal oxide semiconductor transistor includes a substrate, a drain formed thereon, a source formed on the substrate, comprising a plurality of individual sub-sources respectively corresponding to various sides of the drain, a plurality of channels formed in the substrate between... Agent: Birch Stewart Kolasch & Birch

20080135935 - Dual structure finfet and method of manufacturing the same: Provided are a dual structure FinFET and a method of fabricating the same. The FinFET includes: a lower device including a lower silicon layer formed on a substrate and a gate electrode vertically formed on the substrate; an upper device including an upper silicon layer formed on the lower device... Agent: Ladas & Parry LLP

20080135938 - Embedded substrate interconnect for underside contact to source and drain regions: A semiconductor topography (10) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line (16) arranged within an insulating layer (22) of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a first conductive line (16) within an insulating layer (22)... Agent: Larson Newman Abel Polansky & White, LLP

20080135936 - Semiconductor device and manufacturing method thereof: The method of manufacturing a semiconductor device includes: forming a gate insulating film on a semiconductor substrate; forming a thin silicon layer on the gate insulating film; and forming a metal film on the thin silicon layer, having a work function at the interface with respect to the gate insulating... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080135937 - Tft containing coalesced nanoparticles: A thin film transistor comprising: (a) an insulating layer; (b) a gate electrode; (c) a semiconductor layer; (d) a source electrode; and (e) a drain electrode, wherein the insulating layer, the gate electrode, the semiconductor layer, the source electrode, and the drain electrode are in any sequence as long as... Agent: Patent Documentation Center

20080135939 - Fabrication method of semiconductor package and structure thereof: A fabrication method of semiconductor and a structure thereof are disclosed herein. The present invention includes: providing a substrate; disposing a mask on the substrate, wherein the mask has a plurality of patterned openings to expose portions of the substrate; forming a metal layer on the exposed portions of the... Agent: Rosenberg, Klein & Lee

20080135940 - Semiconductor device: A semiconductor device includes an NMOS switching element having an N-type drain diffusion region coupled to an input and/or output terminal, and an N-type source diffusion region and a P-type substrate contact diffusion region coupled to a ground line; and an NMOS protection element having an N-type drain diffusion region... Agent: Cooper & Dunham, LLP

20080135941 - Modulated trigger device: A trigger device. The device includes: a MOSFET comprising a source, a drain, a gate and a body; a modulating layer under the body; body and modulating layer contacts, the body contact separated from the source, drain and modulating contact by dielectric isolation in the body; the modulating layer contact... Agent: Schmeiser, Olsen & Watts

20080135942 - Semiconductor device, manufacturing method thereof, and sram cell: An SRAM cell includes a semiconductor substrate; a first transistor formed in a main plane of the semiconductor substrate; a second transistor formed in the main plane of the semiconductor substrate; and a first wiring layer connecting a gate electrode of the first transistor with a diffusion region of the... Agent: Mcginn Intellectual Property Law Group, Pllc

20080135943 - Gate structure and method for fabricating the same, and method for fabricating memory and cmos transistor layout: A method for fabricating a gate structure is provided. A pad oxide layer, a pad conductive layer and a dielectric layer are sequentially formed over a substrate. A portion of the dielectric layer is removed to form an opening exposing a portion of the pad conductive layer. A liner conductive... Agent: Jianq Chyun Intellectual Property Office

20080135944 - Semiconductor device: A semiconductor device has an n-channel MIS transistor and a p-channel MIS transistor on a substrate. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, a lower layer gate electrode which is formed via a gate insulating film above the p-type semiconductor region and which is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080135945 - Semiconductor device having a silicided gate electrode and method of manufacture therefor: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device (100), among other possible elements, includes a gate oxide (140) located over a substrate (110), and a silicided gate electrode (150) located over the gate oxide (140),... Agent: Texas Instruments Incorporated

20080135946 - Read only memory cell having multi-layer structure for storing charges and manufacturing method thereof: An exemplary read only memory cell (200) includes a semiconductor layer (220), a gate stack (230), and a gate electrode (240). The gate stack includes a tunnel film (231), a charge storing layer (232), and a block layer (233) sequentially stacked adjacent to the semiconductor layer. The gate electrode is... Agent: Wei Te Chung Foxconn International, Inc.

20080135948 - Device patterned with sub-lithographic features with variable widths: A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths and exposing sidewalls... Agent: Graham S. Jones, Ii

20080135947 - Organic inverter including surface-treated layer and method of manufacturing the same: An organic inverter and a method of manufacturing the same are provided, which regulates threshold voltages depending on positions when an inverter circuit is manufactured on a substrate using an organic semiconductor. To form a depletion load transistor and an enhancement driver transistor at adjacent positions of the same substrate,... Agent: Ladas & Parry LLP

20080135949 - Stacked silicon-germanium nanowire structure and method of forming the same: A method of forming a stacked silicon-germanium nanowire structure on a support substrate is disclosed. The method includes forming a stacked structure on the support substrate, the stacked structure comprising at least one channel layer and at least one interchannel layer deposited on the channel layer; forming a fin structure... Agent: Seed Intellectual Property Law Group Pllc

20080135950 - Semiconductor device: Embodiments relater to a semiconductor device and a method of fabricating the same. A source/drain area may be formed by using the spacer having the dual structure of the oxide layer and nitride layer. After etching a part of the oxide layer, the salicide layer may be formed on the... Agent: Sherr & Nourse, Pllc

20080135952 - Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first... Agent: Mark Seeley C/o Intel Corporation

20080135951 - Semiconductor device and method of forming the same: It is known to provide a reoxidation step in the manufacture of a MOSFET that serves a number of structural purposes in relation to the MOSFET. However, the need to provide materials of high dielectric constant for gate insulator layers of MOSFETs to accommodate a drive for smaller integrated circuits... Agent: Freescale Semiconductor, Inc. Law Department

20080135953 - Noise reduction in semiconductor devices: Some embodiments discussed relate to an integrated circuit and methods of making it, comprising a semiconductor substrate and a support layer disposed on the semiconductor substrate, wherein the support layer is doped using a noise-reducing dopant and a gate insulator disposed on the support layer, and a gate stack disposed... Agent: Schwegman, Lundberg & Woessner / Infineon

20080135954 - Semiconductor device and method of producing the semiconductor device: A film with small hysteresis and high voltage resistance is obtained by reducing the carbon content in a gate insulating film on a SiC substrate. Specifically, the carbon content in the gate insulating film is set to 1×1020 atoms/cm3 or less. For this, using a plasma processing apparatus, a silicon... Agent: Foley And Lardner LLP Suite 500

20080135955 - Semiconductor device and method for fabricating the same: A semiconductor device includes low concentration source/drain regions and high concentration source/drain regions each being formed in a semiconductor substrate, a gate insulation film formed on part of the semiconductor substrate located between the low concentration source/drain regions when viewed from the top and a gate electrode formed of metal... Agent: Mcdermott Will & Emery LLP

20080135956 - Articles and assembly for magnetically directed self assembly and methods of manufacture: A functional block for assembly includes at least one element and a magnetic film attached to the element and having a magnetic remanence (MR/MS) of less than about 0.2, having a coercive field (Hc) of less than about 100 Oersteds (100 Oe) and having a permeability (μ) of greater than... Agent: General Electric Company Global Research

20080135958 - Magnetic random access memory and manufacturing method of the same: A magnetic random access memory includes a magnetoresistive effect element which has a fixed layer, a recording layer and a non-magnetic layer provided between the fixed layer and the recording layer and in which the magnetization directions of the fixed layer and the recording layer are brought into a parallel... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080135957 - Mram cell structure: Disclosed herein is an improved memory device wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via... Agent: Baker & Mckenzie On Behalf Of Tsmc

20080135959 - Semiconductor component comprising magnetic field sensor: The invention relates to a semiconductor component (100) comprising a semiconductor chip (10) configured as a wafer level package, a magnetic field sensor (11) being integrated into said semiconductor chip.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080135960 - Semiconductor device and electronic device: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a... Agent: Miles & Stockbridge Pc

20080135961 - Semiconductor device: A semiconductor device has an electrode pad, a capacitor and a substrate. The substrate has a given area on which the electrode pad and the capacitor are arranged. The electrode pad and the capacitor are arranged on the substrate so that each of at least two sides of the capacitor... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080135965 - Electrical/optical integration scheme using direct copper bonding: An electro-optic semiconductor package and fabrication method provides enhanced performance. An integrated circuit (IC) having one or more IC contact pads is provided, where the IC contact pads are connected to an IC on the IC wafer. An intermediate wafer having one or more intermediate contact pads is provided, where... Agent: Intel/blakely

20080135962 - Image sensor and fabricating method thereof: An image sensor and fabricating method thereof which reduces a light intensity differential between a pixel center and a pixel edge and prevents crosstalk. The image sensor can include a plurality of convex lens provided within a passivation layer and in vertical alignment with a corresponding photodiode, each convex lens... Agent: Sherr & Nourse, Pllc

20080135964 - Photoelectic conversion device and manufacturing method: A photoelectric conversion device is provided which is capable of improving the light condensation efficiency without substantially decreasing the sensitivity. The photoelectric conversion device has a first pattern provided above an element isolation region formed between adjacent two photoelectric conversion elements, a second pattern provided above the element isolation region... Agent: Fitzpatrick Cella Harper & Scinto

20080135963 - Solid-state imaging device, method of making the same, and imaging apparatus: A solid-state imaging device includes the following elements. A photoelectric conversion section is arranged in a semiconductor layer having a first surface through which light enters the photoelectric conversion section. A signal circuit section is arranged in a second surface of the semiconductor layer opposite to the first surface. The... Agent: Sonnenschein Nath & Rosenthal LLP

20080135966 - Smart card capable of sensing light: A smart card is formed of a memory having light-sensing cells to sense externally supplied light and generate a detection signal in response to the externally supplied light being sensed by the light-sensing cells, and a reset control circuit generating a reset signal in response to the detection signal, the... Agent: F. Chau & Associates, Llc

20080135967 - Semiconductor device and method of manufacturing the same: The invention is directed to providing a semiconductor device receiving a blue-violet laser, of which the reliability and yield are enhanced. A device element converting a blue-violet laser into an electric signal is formed on a front surface of a semiconductor substrate. An optically transparent substrate is attached to the... Agent: Morrison & Foerster LLP

20080135968 - Light sensors with infrared suppression: Embodiments of the present invention are directed to light sensors, that primarily respond to visible light while suppressing infrared light. Such sensors are especially useful as ambient light sensors because such sensors can be used to provide a spectral response similar to that of a human eye. Embodiments of the... Agent: Fliesler Meyer LLP

20080135970 - High voltage shottky diodes: High voltage schottky diodes are provided including a first conductivity type semiconductor substrate and a second conductivity type well region defined by the substrate. A first conductive film is provided on a surface of the substrate including the well. A conductive electrode is provided on at least one side of... Agent: Myers Bigel Sibley & Sajovec

20080135969 - Semiconductor device: The semiconductor device includes a first conductive type semiconductor substrate; a Schottky electrode forming a Schottky interface between a surface of the semiconductor substrate and itself; a leakage suppression structure, formed in a surface region of the semiconductor substrate, for suppressing a leakage current by generating a depletion layer when... Agent: Rabin & Berdo, Pc

20080135971 - High voltage semiconductor device and method of manufacture thereof: A drift diffusion layer of a low concentration is formed so as to surround a collector buffer layer having a relatively high concentration including a high-concentration collector diffusion layer in a plane structure. Thereby, current crowding in corner portions of the high-concentration collector diffusion layer is suppressed while maintaining a... Agent: Steptoe & Johnson LLP

20080135972 - Lateral insulated gate bipolar transistor having a retrograde doping profile in base region and method of manufacture thereof: In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5,... Agent: Steptoe & Johnson LLP

20080135973 - Semiconductor device comprising high-withstand voltage mosfet and its manufacturing method: The high-withstand voltage MOSFET comprises a trench portion formed at the high-withstand voltage active region on a semiconductor substrate, two polysilicon layers formed on the high-withstand voltage active region on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active... Agent: Nixon & Vanderhye, Pc

20080135974 - Method and apparatus for performing metalization in an integrated circuit process: A reverse fill pattern is used in an integrated circuit (IC) that comprises a metal layer having slots formed therein in the shape of rhombuses. The distribution of rhombic slots ensures that electrical current is evenly distributed in the conductor, even at the edge regions of the conductor. This even... Agent: Gardner Groff Greenwald & Villanueva. Pc

20080135975 - Semiconductor wafer, method of manufacturing the same and semiconductor device: A modified layer 5 and an altered layer 8 are formed outside a dicing point of a dicing area 3. Thus without forming another interface between different physical properties on the dicing point, it is possible to prevent chipping from progressing along a crystal orientation from an interface between a... Agent: Steptoe & Johnson LLP

20080135976 - Semiconductor device and method of manufacturing the same: A plurality of trenches are provided in a semiconductor layer and integrated by thermal oxidation to form an insulating region having void parts therein. The thickness of the insulating region can be controlled by the depth of the trenches. This makes it possible to form the insulating region having a... Agent: Morrison & Foerster LLP

20080135977 - Semiconductor component including a semiconductor chip and a passive component: The invention relates to a semiconductor component (1) having a semiconductor chip (2), and a passive component (3), with the semiconductor component (1) having a coil (6) as the passive component (3). The semiconductor chip (2) and the passive component (3) are embedded in a plastic encapsulation compound (4) with... Agent: Edell , Shapiro & Finnan , Llc

20080135979 - Semiconductor device which includes a capacitor and an interconnection film coupled to each other and a manufacturing method thereof: A semiconductor device includes a semiconductor substrate and a capacitor which is disposed on a principal surface of the semiconductor substrate. The capacitor includes a lower electrode film disposed on the principal surface of the semiconductor substrate, a dielectric film disposed on the lower electrode and an upper electrode film... Agent: Volentine & Whitt Pllc

20080135978 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes a power supply line connected to a power supply terminal, a ground line connected to a ground terminal and a plurality of capacitors connected in parallel between the power supply line and the ground line. The plurality of capacitors include a first capacitor arranged... Agent: Foley And Lardner LLP Suite 500

20080135980 - Method for making junction and processed material formed using the same: An object of this invention is to provide a method for making a junction which is simple in the process, high in the throughput, and can make a shallow junction with high accuracy. After the suitable state of a substrate surface adapted to the wavelength of an electromagnetic wave to... Agent: Mcdermott Will & Emery LLP

20080135981 - Substrate laser marking: A method for forming a feature in a substrate, where residue within the feature can be easily removed. An upper sidewall portion of the feature is formed, where the upper sidewall portion forms a void in the substrate. The upper sidewall portion has an upper sidewall angle. A lower sidewall... Agent: Lsi Corporation

20080135982 - Semiconductor devices including mesa structures and multiple passivation layers: A semiconductor device including a semiconductor structure defining a mesa having a mesa surface and mesa sidewalls, and first and second passivation layers. The first passivation layer may be on at least portions of the mesa sidewalls, at least a portion of the mesa surface may be free of the... Agent: Myers Bigel Sibley & Sajovec

20080135983 - Nanolaminate-structure dielectric film forming method: Nanolaminate-structure SrO/TiO films are formed on a lower electrode of a capacitor by molecular layer deposition kept in a rate-determined state by a surface reaction. The nanolaminate-structure SrO/TiO films are formed by alternately laminating one or more and 20 or less SrO molecular layers and one or more and 20... Agent: Whitham, Curtis & Christofferson & Cook, P.c.

20080135984 - Semiconductor device: Embodiments relate to a Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) and a method of fabricating a MOSFET. According to embodiments, a method of forming a MOSFET may include forming a first gate insulating layer on a semiconductor substrate, nitrifying the first gate insulating layer, forming a second gate insulating layer... Agent: Sherr & Nourse, Pllc

20080135986 - Method of forming pre-metal dielectric layer of semiconductor device: A method of forming a pre-metal dielectric (PMD) layer of a semiconductor device using a chemical mechanical polishing (CMP) process which can be suitable for easily recognizing an alignment key. Such a method can reduce or otherwise eliminate alignment key erosion due to CMP by previously forming an alignment key... Agent: Sherr & Nourse, Pllc

20080135985 - Two-step oxidation process for semiconductor wafers: An efficient method for the thermal oxidation of preferably silicon semiconductor wafers using LOCOS (local oxidation of silicon) processes is described. The mechanical stresses of the wafers are to be reduced. To this end, an oxidation method is proposed that comprises providing a substrate (1) having a front side (12)... Agent: Duane Morris, LLP Ip Department

20080135987 - Gate conductor structure: A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap... Agent: International Business Machines Corporation Dept. 18g

20080135988 - Method to reduce semiconductor device leakage: Various embodiments of the present invention relate to systems, devices, and methods for treating a semiconductor substrate, such as a silicon wafer, in order to reduce current leakage therein. A semiconductor substrate is provided a plurality of heating treatments that create a denuded zone adjacent to a surface of the... Agent: North Weber & Baugh LLP

20080135989 - Integrated circuit package system employing structural support: An integrated circuit package system that includes: providing an electrical interconnect system including a support structure and a lead-finger system; stacking a first device over the support structure; stacking a second device over the first device; connecting the first device and the second device to the lead-finger system; stacking a... Agent: Law Offices Of Mikio Ishimaru

20080135992 - Semiconductor device having plurality of leads: A method of making a semiconductor device including a semiconductor chip having a plurality of pads, and a lead frame having a plurality of leads. Each of the plurality of leads has a mounting surface for mounting the semiconductor device, a wire connection surface having a thick portion, and a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080135991 - Semiconductor device package featuring encapsulated leadframe with projecting bumps or balls: Embodiments of the present invention relate to semiconductor device packages featuring encapsulated leadframes in electrical communication with a supported die through electrically conducting bumps or balls. By eliminating the need for a separate diepad and lateral isolation between an edge of the diepad and adjacent non-integral leads or pins, embodiments... Agent: Townsend And Townsend And Crew, LLP

20080135990 - Stress-improved flip-chip semiconductor device having half-etched leadframe: A semiconductor device (100) with a metal bump (203) on each interior contact pad (202) has a metallic leadframe with lead segments (220) with the first surface (220a) in one plane. The second surface (220b) is castellated across the segment width in two planes so that regions of a first... Agent: Texas Instruments Incorporated

20080135993 - Lead frame of through-hole light emitting diode: A lead frame of a through-hole light emitting diode (LED) is used to carry an LED chip, and a lens is used to package the chip and a portion of the lead frame. The lead frame includes at least two leads. One lead is used to carry the chip and... Agent: Morris Manning Martin LLP

20080135994 - Ldo regulator with ground connection through package bottom: A low dropout (LDO) regulator device includes an LDO regulator integrated circuit housed in a 4-pin quad flat no-lead (QFN) package where the exposed die paddle is used as the ground terminal. The LDO regulator integrated circuit is formed on a semiconductor substrate. The 4-pin QFN package includes four perimeter... Agent: Patent Law Group LLP

20080135995 - Electronic component: An electronic component is disclosed. In one embodiment, the electronic component includes a frame having a base layer, a first layer, a second layer including palladium placed on the first layer, and a third layer including gold placed on the second layer. A semiconductor chip is positioned on the frame.... Agent: Dicke, Billig & Czaja

20080135996 - Lead frame: A connecting tape made of insulating material is adhered between a stage unit 21 and a stage unit 22. The stage units 21 and 22 form united stage units by that. Therefore, edge parts 211 and 221 of the stage units 21 and 22 are bound by the connecting tape... Agent: Dickstein Shapiro LLP

20080135997 - Wire bond interconnection: A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond... Agent: Law Offices Of Mikio Ishimaru

20080135998 - Method for encapsulating a device in a microcavity: Manufacturing a semiconductor device involves forming (200) a sacrificial layer where a micro cavity is to be located, forming (210) a metal layer of thickness greater than 1 micron over the sacrificial layer, forming (220) a porous layer from the metal layer, the porous layer having pores of length greater... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080135999 - Package device: The present invention relates to a package device including a first substrate, a plurality of first chips positioned on the first substrate, a second substrate positioned on the first substrate, a second chip positioned on the second substrate, an adhesive layer positioned on the second chip, and a heat spreader... Agent: North America Intellectual Property Corporation

20080136000 - Micromechanical component having multiple caverns, and manufacturing method: A micromechanical component having at least two caverns is provided, the caverns being delimited by the micromechanical component and a cap, and the caverns having different internal atmospheric pressures. The micromechanical component and cap are hermetically joined to one another at a first specifiable atmospheric pressure, then an access to... Agent: Kenyon & Kenyon LLP

20080136001 - Carrierless chip package for integrated circuit devices, and methods of making same: Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each... Agent: Perkins Coie LLP Patent-sea

20080136004 - Multi-chip package structure and method of forming the same: To pick and place standard first chip size package on a base with a second chip for obtaining an appropriate stacking chip size package than the original chip size package. The package structure has a larger chip size package than the size of the traditional stacking package. Moreover, the terminal... Agent: Kusner & Jaffe Highland Place Suite 310

20080136002 - Multi-chips package and method of forming the same: The present invention provides a structure of multi-chips package comprising: a substrate with a die receiving cavity formed within an upper surface of the substrate and a first through holes structure, wherein a terminal pads is formed under the first through holes structure. A first die is disposed within the... Agent: Kusner & Jaffe Highland Place Suite 310

20080136003 - Multi-layer semiconductor package: A semiconductor package comprises a base substrate with a semiconductor die mounted on a top side of the base substrate and an interposer substrate mounted on top of the die. The bottom side of the interposer substrate can be electrically coupled to the top side of the base substrate through... Agent: Klarquist Sparkman, LLP

20080136008 - Stack package and stack packaging method: Provided are a stack package and a stack packaging method. The stack package includes: a first package; and a second package stacked on the first package, wherein external leads of the first package and the second package are directly connected to one another and inner leads thereof are arranged in... Agent: Marger Johnson & Mccollom, P.c.

20080136005 - Stackable integrated circuit package system: A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first... Agent: Law Offices Of Mikio Ishimaru

20080136006 - Stacked integrated circuit package-in-package system: A stacked integrated circuit package-in-package system is provided including forming a substrate having a top surface and a bottom surface, mounting a first device over the top surface, stacking a second device over the first device in an offset configuration, connecting a first internal interconnect between the first device and... Agent: Law Offices Of Mikio Ishimaru

20080136007 - Stacked integrated circuit package-in-package system: A stacked integrated circuit package-in-package system is provided including forming a substrate with a top contact, mounting a first device having a first terminal over the substrate, stacking a second device having a second terminal over the first device in an offset configuration, connecting the first terminal to the top... Agent: Law Offices Of Mikio Ishimaru

20080136010 - Integrated circuit package with improved power signal connection: An integrated circuit (IC) package includes a substrate and an IC die mounted on a first side of the substrate. The IC package also includes a plurality of capacitors mounted on a second side of the substrate. The second side is opposite to the first side. The IC package further... Agent: Buckley, Maschoff & Talwalkar Llc

20080136009 - Semiconductor device with hollow structure: A device comprising a chip, which is held in casting compound and on which a hollow structure is arranged is disclosed.... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080136011 - Semiconductor device: A semiconductor device includes a first semiconductor chip having first connecting pads arranged at first interval and a second semiconductor chip having second connecting pads arranged at second interval, the second interval being larger than the first interval, in which the first semiconductor chip includes the first connecting pads not... Agent: Mcginn Intellectual Property Law Group, Pllc

20080136012 - Imagine sensor package and forming method of the same: An image sensor package comprises a substrate, a chip mounted over the substrate, A molding material is formed surrounding the chip to expose a micron lens area, wherein the molding material includes via structure passing there through. A protection layer is formed on the micro lens area to prevent the... Agent: Kusner & Jaffe Highland Place Suite 310

20080136013 - Multilayer substrate and method of manufacturing the same: A multilayer substrate includes an insulating base member having a plurality of resin films, an electric element embedded in the insulating base member, and a spacer. The resin films are made of a thermoplastic resin and stacked and attached to each other. At least one resin film has a through... Agent: Posz Law Group, Plc

20080136014 - Semiconductor package and method for manufacturing the same: A semiconductor package includes a semiconductor chip, a first substrate layer and a second substrate layer. The semiconductor chip has an active surface and a plurality of pads disposed on the active surface. The first substrate layer is formed on the active surface of the semiconductor chip and has a... Agent: Lowe Hauptman Ham & Berner, LLP

20080136015 - High power semiconductor device: A high power semiconductor package includes a substrate including a base metal layer, a base insulation layer formed on the base metal layer, and a plurality of conductive patterns formed on the base insulation layer. In one embodiment one or more high power semiconductor chips are mounted on the substrate,... Agent: Hiscock & Barclay, LLP

20080136016 - Packaged integrated circuit with enhanced thermal dissipation: A semiconductor package (10) uses a plurality of thermal conductors (56-64) that extend upward within an encapsulant (16) from one or more thermal bond pads (22, 24, 26) on a die (14) to disperse heat. The thermal conductors may be bond wires or conductive stud bumps and do not extend... Agent: Freescale Semiconductor, Inc. Law Department

20080136017 - Semiconductor device, method for manufacturing the same, and semiconductor device mounting structure: A semiconductor device of the present invention includes: a wiring board 4 in which a conductive wiring 6 is formed on an insulating substrate 5 having an opening 5a; a semiconductor element 2 that has a circuit forming region 2a and an electrode pad 3, and is mounted on the... Agent: Hamre, Schumann, Mueller & Larson P.c.

20080136022 - Direct via wire bonding and method of assembling the same: A method for electrically connecting an integrated circuit to a via in a substrate is disclosed. The method can include deforming a ball over the via to form a bump and attaching a bond wire to the bump. The method also can include attaching the bond wire to the integrated... Agent: Klarquist Sparkman, LLP

20080136018 - Function element and manufacturing method thereof, and function element mounting structure: The semiconductor device is manufactured by forming a lower electrode layer 2 having a predetermined pattern on a semiconductor substrate 1 and forming an upper electrode layer 3 on a part of the top surface of the lower electrode layer 2, while holes 2X extending in the direction of thickness... Agent: Hogan & Hartson L.l.p.

20080136023 - Method for manufacturing semiconductor device and semiconductor device: A method for manufacturing a semiconductor device includes the steps of providing an element forming layer on a first surface of a semiconductor substrate, and providing an external connection terminal on a second surface of the semiconductor substrate opposite to the first surface so that the external connection terminal is... Agent: Sonnenschein Nath & Rosenthal LLP

20080136021 - Method of manufacturing hybrid structure of multi-layer substrates and hybrid structure thereof: Disclosed is a method of manufacturing a hybrid structure of multi-layer substrates. The method comprises steps of: separating a border district of at least one metal layer connecting with a border district of the corresponding dielectric layer from adjacent metal layers and adjacent dielectric layers for each multi-layer substrate and... Agent: Madson & Austin

20080136024 - Semiconductor device: In a semiconductor device provided by preventing connection failure caused by misalignment of a semiconductor element having fine and narrow-pitched bumps, a guide for preventing the misalignment is formed by an insulating resin layer around a connection electrode. The insulating resin layer has a thickness defined in relation to an... Agent: Scully Scott Murphy & Presser, Pc

20080136025 - Semiconductor device: A semiconductor device in accordance with the present invention is a mounted body of a semiconductor chip with a plurality of electrode pads arranged in a plurality of stages and a tape wiring board, the average pitch of the electrode pads on the entire semiconductor chip can be reduced, while... Agent: Steptoe & Johnson LLP

20080136020 - Semiconductor device and method of manufacturing the same: A first electronic circuit component and a second electronic circuit component are electrically connected to an electro-conductive member via a first solder and a second solder, respectively. The electro-conductive member is formed in a resin film. The electro-conductive member is configured as containing a second diffusion barrier metal film. The... Agent: Young & Thompson

20080136019 - Solder bump/under bump metallurgy structure for high temperature applications: Solder bump structures, which comprise a solder bump on a UBM structure, are provided for operation at temperatures of 250° C. and above. According to a first embodiment, the UBM structure comprises layers of Ni—P, Pd—P, and gold, wherein the Ni—P and Pd—P layers act as barrier and/or solderable/bondable layers.... Agent: Greenberg Traurig LLP (la)

20080136027 - Method of bonding wire of semiconductor package: Provided is a method of bonding a wire of a semiconductor package, by which a loop height may be reduced and/or a bonding reliability may be enhanced. In the method, a ball bump may be formed on a bonding pad on a semiconductor chip using a capillary through which a... Agent: Harness, Dickey & Pierce, P.L.C

20080136026 - Structure and process for wl-csp with metal cover: A wafer level package comprises a wafer having a plurality of dice formed thereon; a thinner metal cover with a cavity formed therein attached on the wafer by an adhesive material to improve thermal conductivity of the package. A protection film is formed on back side of the metal cover... Agent: Kusner & Jaffe Highland Place Suite 310

20080136029 - Germanium-containing dielectric barrier for low-k process: A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a conductive wiring in the first dielectric layer; and a copper germanide nitride layer over the conductive wiring.... Agent: Slater & Matsil, L.l.p.

20080136031 - Metal line pattern of semiconductor device and method of forming the same: A method of forming a metal line pattern for a semiconductor device is provided. The method includes forming a preliminary structure on a semiconductor substrate, having a lower barrier metal layer, a metal layer, and an upper barrier and/or passivation layer having a first thickness; removing a top surface of... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080136028 - Semiconductor constructions comprising a layer of metal over a substrate: The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid. The supercritical fluid has H2, at least one H2-activating catalyst, and at least one metal-containing precursor dispersed therein. A metal-containing film is formed across the... Agent: Wells St. John P.s.

20080136030 - Semiconductor device comprising a doped metal comprising main electrode: A semiconductor device is provided comprising a main electrode (4) and a dielectric (3) in contact with the main electrode (4), the main electrode (4) comprising a material having a work function and a work function modulating element (6) for modulating the work function of the material of the main... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080136032 - Method for filling a contact hole and integrated circuit arrangement with contact hole: A method in which a base layer is deposited in a contact hole region under a protective gas, where base layer contains a nitride as main constituent. After the deposition of the base layer, a covering layer is deposited under gaseous nitrogen. An adhesion promoting layer results which is simple... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080136034 - Chip structure and process for forming the same: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric... Agent: Mou-shiung Lin

20080136033 - Packaging board and manufacturing method therefor, semiconductor module and mobile apparatus: An advantage of the present invention is to suppress moisture infiltrating from a pad electrode portion from spreading over the surface of a wiring pattern and improve the reliability of a packaging board. The wiring pattern of the packaging board is formed on an insulating substrate and includes a wiring... Agent: Fish & Richardson P.c.

20080136035 - High-aspect-ratio metal-polymer composite structures for nano interconnects: A low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures can be used as IC-package interconnects that can lead to reliable, low-cost and high-performance nano wafer-level packaging. High-aspect-ratio low CTE polyimide structures with low stress, high toughness and strength were... Agent: Troutman Sanders LLP

20080136036 - On die signal detector without die power: In general, in one aspect, the disclosure describes an apparatus having on die circuitry coupled to at least one input port to receive a signal. A resistor is coupled to the on die circuitry and an off die power supply When a signal of sufficient amplitude is received by the... Agent: Ryder Ip Law C/o Intellevate

20080136037 - Method for manufacturing semiconductor device and semiconductor device: A method for manufacturing a semiconductor device, the method including: the first step of forming an insulating film over a substrate of which surface side has a first conductive layer, and forming a recess in the insulating film by dry etching; the second step of carrying out plasma treatment for... Agent: Sonnenschein Nath & Rosenthal LLP

20080136038 - Integrated circuits with conductive features in through holes passing through other conductive features and through a semiconductor substrate: A backside contact pad is formed in an integrated circuit, possibly designed initially with just top side contact pads (150C), by forming an opening (220) through a top side contact pad (150C) and the semiconductor substrate (110). Conductive material (520, 540, 1110, 1130) is formed in the opening and in... Agent: Macpherson Kwok Chen & Heid LLP

20080136039 - Interconnect assemblies, and methods of forming interconnects: There is disclosed an interconnect assembly. In an embodiment, the interconnect assembly includes conductive contact bumps extending from a bumped flex circuit assembly, and conductive contact pads attached to a rigid printed circuit assembly, having a contact surface having a hole and an abutment zone adjacent to the hole, wherein... Agent: Verigy, Ltd.

20080136042 - Metal wiring of semiconductor device and forming method thereof: A metal wiring of a semiconductor device and a forming method thereof are provided. A dielectric layer is formed on a semiconductor substrate including a lower metal wiring. A SOG (spin on glass) coating layer is formed on the dielectric layer to inhibit material from another layer from infiltrating into... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080136040 - Methods of forming electrical interconnects using non-uniformly nitrified metal layers and interconnects formed thereby: Methods of forming electrical interconnects include forming a first electrically insulating layer on a semiconductor substrate and then forming an opening in the first electrically insulating layer. A step is performed to line a sidewall of the opening with a nitrified first metal layer having a non-uniform nitrogen concentration therein.... Agent: Myers Bigel Sibley & Sajovec

20080136043 - Multilayer wiring structure, semiconductor device, pattern transfer mask and method for manufacturing multilayer wiring structure: A multilayer interconnection structure according to this invention is applied to a case where a plurality of interconnections are formed at a fine pitch and a via is connected to at least one of the interconnections. In the multilayer interconnection structure, a region facing the via is locally narrowed in... Agent: Sughrue Mion, Pllc

20080136041 - Structure and method of making interconnect element having metal traces embedded in surface of dielectric: An interconnect element is provided which includes a dielectric element having a major surface. Metal interconnect patterns are embedded in recesses which extend inwardly from the major surface, the outer surfaces of the interconnect patterns being substantially co-planar with the major surface and extending in one or more directions of... Agent: Tessera Lerner David Et Al.

20080136044 - Semiconductor package and method of manufacturing the same: Provided are a semiconductor package in which bonding pads of a semiconductor chip are electrically connected to interconnection portions by wire-bonding, and a method of manufacturing the semiconductor package. The semiconductor package includes: a substrate; an interconnection portion that is disposed on the substrate and comprises conductive patterns having a... Agent: Mills & Onello LLP

20080136045 - Stacked die in die bga package: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.... Agent: Whyte Hirschboeck Dudek S.c.

20080136046 - Electronic device and method of manufacturing the same, chip carrier, circuit board, and electronic instrument: An external terminal is formed on an interconnect pattern formed on a substrate by using a soldering material. Subsequently, a chip component having an electrode is mounted on the substrate. An interconnect for electrically connecting the electrode and the interconnect pattern is formed at a temperature lower than a melting... Agent: Oliff & Berridge, Plc

20080136047 - Semiconductor device: A semiconductor device having a wafer level chip size package may include a semiconductor substrate having an integrated circuit formed thereon; a plurality of electrode pads formed on the semiconductor substrate; at least one rewiring layer which may include rewiring formed adjacent to the plurality of electrode pads; and a... Agent: Cantor Colburn, LLP

20080136048 - Epoxy resin composition for semiconductor encapsulation and semiconductor device using the same: s

20080136049 - Method of improving overlay performance in semiconductor manufacture: A method for registering a pattern on a semiconductor wafer with an oxide surface includes etching into the surface four sets of two trenches each. Each trench in a set is parallel to the other. The trenches are configured such that each set forms one side of a box shape.... Agent: Akin Gump LLP - Silicon Valley

20080128674 - Differential negative resistance memory: The invention relates to a DNR (differential negative resistance) exhibiting device that can be programmed to store information as readable current amplitudes and to methods of making such a device. The stored data is semi-volatile. Generally, information written to a device in accordance with the invention can maintain its memory... Agent: Dickstein Shapiro LLP

20080128673 - Transistor of phase change memory device and method for manufacturing the same: A transistor for a phase change memory device includes a semiconductor substrate in which active regions are delimited by an isolation structure. A groove is defined on a surface of a gate forming area of each active region. Portions of the isolation structure, which are adjacent to the gate forming... Agent: Ladas & Parry LLP

20080128675 - Phase change memory cell having a tapered microtrench: A phase change memory includes a cup-shaped heater element formed above a body. A tapered phase change region is formed on the cup-shaped heater element. The cup-shaped heater element is formed by depositing a stop layer of a first dielectric material over the body. A first sacrificial layer is deposited... Agent: Trop Pruner & Hu, Pc

20080128676 - Phase-change random access memory device and method of manufacturing the same: Provided are a Phase-change Random Access Memory (PRAM) device and a method of manufacturing the same. In particular, a PRAM device including a heating layer, wherein the heating layer comprises first and second heating layers having different physical properties from each other and a method of manufacturing the same are... Agent: Townsend And Townsend And Crew, LLP

20080128677 - Storage node including diffusion barrier layer, phase change memory device having the same and methods of manufacturing the same: A phase change memory device and a method of manufacturing the phase change memory device are provided. The phase change memory device may include a switching element and a storage node connected to the switching element, wherein the storage node includes a bottom electrode and a top electrode, a phase... Agent: Harness, Dickey & Pierce, P.L.C

20080128678 - Nitride semiconductor light emitting device and fabrication method thereof: The present invention relates to a nitride semiconductor light emitting device including: a first nitride semiconductor layer having a super lattice structure of AlGaN/n-GaN or AlGaN/GaN/n-GaN; an active layer formed on the first nitride semiconductor layer to emit light; a second nitride semiconductor layer formed on the active layer; and... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080128679 - Metal silicate halide phosphors and led lighting devices using the same: The present invention relates to metal silicate halide (halosilicate) phosphors, the phosphors with an oxide coating, methods of making the phosphors, and light emitting diode- (LED-) based lighting devices modified with the phosphors.... Agent: Patent Docket Administrator Lowenstein Sandler P.c.

20080128687 - Electrochemical device and methods for producing the same: Methods of producing electrochemical transistor devices are provided, wherein a solidified electrolyte is arranged in direct contact with at least a portion of an organic material having the ability to electrochemically altering its electrical conductivity through change of redox state thereof, such that a current between a source contact and... Agent: Harness, Dickey & Pierce, P.L.C

20080128682 - Ferrodielectric memory device and method for manufacturing the same: The present invention relates to a ferrodielectric memory device and a method for manufacturing the same that provide stable memory operations by considerably enhancing characteristics of hysteresis and remanent polarization in ferrodielectrics applied to memory devices. In the present invention, PVDF having a crystal structure of β-phase is used as... Agent: Bruce E. Lilling Lilling & Lilling Pllc

20080128688 - Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires: The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as... Agent: Nanosys Inc.

20080128684 - Method for fabricating an organic thin film transistor by oxidation and selective reduction of organic semiconductor material: Disclosed is a method for fabricating an organic thin film transistor by oxidation and selective reduction of an organic semiconductor material. According to the method, stability of interfaces between a semiconductor layer and source/drain electrodes of an organic thin film transistor may be guaranteed. Therefore, an organic thin film transistor... Agent: Harness, Dickey & Pierce, P.L.C

20080128686 - Organic light emitting display (oled) and its method of fabrication: An Organic Light Emitting Display (OLED) and its method of fabrication, is capable of omitting a process of patterning a second pixel electrode by forming a first pixel electrode, forming a pixel-defining layer including an opening on the first pixel electrode, and forming the second pixel electrode and a third... Agent: Robert E. Bushnell

20080128683 - Organic light emitting display and fabricating method thereof: An organic light emitting display includes a substrate, a semiconductor layer arranged on the substrate, an organic light emitting diode arranged on the semiconductor layer, an encapsulant arranged on an top surface periphery of the substrate, which is an outer periphery of the semiconductor layer and the organic light emitting... Agent: Robert E. Bushnell Suite 300

20080128685 - Organic semiconductor device, manufacturing method of same, organic transistor array, and display: A major object of the present invention is to provide an organic semiconductor device which is provided with an organic semiconductor transistor having good transistor performance and is producible with high productivity. To achieve the object, the present invention provides an organic semiconductor device comprising: a substrate, a source electrode... Agent: Ladas & Parry LLP

20080128680 - Silylethynylated heteroacenes and electronic devices made therewith: Novel silylethynylated heteroacenes and electronic devices made with those compounds are disclosed.... Agent: King & Schickli, Pllc

20080128681 - Vertical organic transistor: A vertical organic transistor and a method for fabricating the same are provided, wherein an emitter, a grid with openings and a collector are sequentially arranged above a substrate. Two organic semiconductor layers are interposed respectively between the emitter and the grid with openings and between the grid with openings... Agent: Sinorica, Llc

20080128689 - Flat panel displays comprising a thin-film transistor having a semiconductive oxide in its channel and methods of fabricating the same for use in flat panel displays: Provided is a method of fabricating a semiconductive oxide thin-film transistor (TFT) substrate. The method includes forming gate wiring on an insulation substrate; and forming a structure in which a semiconductive oxide film pattern and data wiring are stacked on the gate wiring, wherein the semiconductive oxide film pattern is... Agent: Macpherson Kwok Chen & Heid LLP

20080128695 - Flip chip semiconductor die internal signal access system and method: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive... Agent: Murabito Hao & Barnes LLP

20080128694 - Manufacturing method for semiconductor chips and semiconductor wafer: In a semiconductor wafer that has semiconductor devices arranged in a plurality of device-formation-regions and a TEG placed in dividing regions that define the device-formation-regions, a TEG-placement portion is arranged in the dividing regions partially expanded in width, and the TEG is placed in the TEG-placement portion. And, a protective... Agent: Wenderoth, Lind & Ponack L.l.p.

20080128696 - Methods for discretized processing and process sequence integration of regions of a substrate: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is... Agent: Martine Penilla Gencarella, LLP

20080128692 - Multi-purpose poly edge test structure: A test structure in accordance with the present invention allows for testing of both Vbd TDDB, and leakage current between adjacent gate features. The test structure comprises a plurality of parallel polysilicon gate structures overlying a substrate. Traces placing alternate gates in electrical communication with a polysilicon edge are connected... Agent: Townsend And Townsend And Crew, LLP

20080128693 - Reliability test structure for multilevel interconnect: Embodiments in accordance with the present invention relate to structures and methods allowing stress-induced electromigration to be tested in multiple interconnect metallization layers. An embodiment of a testing structure in accordance with the present invention comprises at least two segments of a different metal layer through via structures. Each segment... Agent: Townsend And Townsend And Crew, LLP

20080128690 - Scribe based bond pads for integrated circuits: A method and system for utilizing a semiconductor wafer is disclosed. The wafer comprises a plurality of semiconductor die and a plurality of scribe areas interspersed between. The method and system comprises forming bond out pads in the scribe areas such that the bond out pads are disposed on the... Agent: Schwegman, Lundberg & Woessner / Atmel

20080128691 - Test structures for development of metal-insulator-metal (mim) devices: In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor... Agent: Paul J. Winters

20080128697 - Tfa image sensor with stability-optimized photodiode: The invention relates to a TFA image sensor with stability-optimized photodiode for converting electromagnetic radiation into an intensity-dependent photocurrent with an intermetal dielectric, on which, in the region of the pixel matrix, a lower barrier layer is situated and a conductive layer is situated on the barrier layer, and vias... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.c.

20080128698 - Many million pixel image sensor: A CMOS image sensor with a many million pixel count. Applicants have developed techniques for combining its continuous layer photodiode CMOS sensor technology with CMOS integrated circuit lithography stitching techniques to provide digital cameras with an almost unlimited number of pixels. A preferred CMOS stitching technique exploits the precise alignment... Agent: Trex Enterprises Corp.

20080128701 - Electronic device, thin film transistor structure and flat panel display having the same: The invention provides an electronic device configured to prevent or reduce electrostatic discharge from causing a pixel to malfunction. An electronic device manufactured according to the principles of the invention may include multiple conductive layers that cross but do not contact each other, wherein at least one of the conductive... Agent: H.c. Park & Associates, Plc

20080128700 - Pixel structure: A method for fabricating a pixel structure is provided. First, a gate, a scan line, and a first terminal are formed on a substrate. A gate insulating layer is formed over the substrate to cover the gate, the scan line, and the first terminal. After defining the semiconductor layer, the... Agent: Jianq Chyun Intellectual Property Office

20080128699 - Thin film transistor substrate and fabricating method thereof: A thin film transistor substrate and fabricating method thereof by which the size of the thin film transistor substrate is reduced by constructing data signal supply lines, each of which supplies a pixel data voltage to a data line, with different metal lines, respectively includes gate and data lines crossing... Agent: F. Chau & Associates, Llc

20080128702 - Semiconductor device: A semiconductor device has a so-called SOI structure in which an element is constituted by a semiconductor layer on an insulating surface, and the semiconductor layer is extremely thin as 5 nm to 30 nm. The semiconductor device is provided with a field effect transistor that includes in addition to... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080128703 - Semiconductor device and manufacturing method thereof: An object is to provide a semiconductor device with improved reliability and for which a defect due to an end portion of a semiconductor layer provided in an island-shape is prevented, and a manufacturing method thereof. A structure includes an island-shaped semiconductor layer provided over a substrate, an insulating layer... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080128704 - Image display system and manufacturing method of multi-gate thin film transistor: An image display system has a multi-gate thin film transistor (TFT) disposed on a transparent substrate. The multi-gate TFT includes a silicon film layer, a first electrode and a reflecting layer. The silicon film layer is formed on the transparent substrate and has a first crystallization zone and a second... Agent: Birch Stewart Kolasch & Birch

20080128705 - Semiconductor device and electro-optical device: A semiconductor device and an electro-optical device that ensures a stable output are provided even when there is a change in a source-drain current in a saturated operation region of a thin film transistor due to kink effects. The thin film transistor has a multi-gate structure with a polycrystalline silicon... Agent: Oliff & Berridge, Plc

20080128708 - Gan single crystal substrate and method for processing surface of gan single crystal substrate: The surface of a gallium nitride single crystal substrate is processed, e.g., comprising steps by planarizing the top side and the bottom side of a gallium nitride original substrate positioned on a support bed; radiating light having wavelengths ranging from 370 to 800 nanometers (nm) onto the planarized gallium nitride... Agent: Lerner, David, Littenberg, Krumholz & Mentlik

20080128707 - Semiconductor device and method for fabricating the same: A semiconductor device includes: an AlN layer provided on a substrate; a Si-doped GaN layer provided on the AlN layer; an undoped GaN layer provided on the Si-doped GaN layer; and an operation layer provided on the undoped GaN layer.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080128706 - Semiconductor device and method of its manufacture: Method of high-yield manufacturing superior semiconductor devices includes: a step of preparing a GaN substrate having a ratio St/S—of collective area (St cm2) of inversion domains in, to total area (S cm2) of the principal face of, the GaN substrate—of no more than 0.5, with the density along the (0001)... Agent: Judge Patent Associates

20080128709 - Inclusion of nitrogen at the silicon dioxide-silicon carbide interface for passivation of interface defects: t

20080128710 - Producing sic packs on a wafer plane: A method for producing at least one semiconductor component group, in particular a SiC semiconductor component group, includes the step of producing a number of semiconductor components on a substrate, particularly on a wafer. The individual semiconductor components are tested for detecting operative semiconductor components. At least one semiconductor component... Agent: Lerner Greenberg Stemer LLP

20080128712 - Raised sti structure and superdamascene technique for nmosfet performance enhancement with embedded silicon carbon: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing... Agent: Whitham , Curtis, & Christofferson, P.c.

20080128711 - Silicon carbide semiconductor device: A silicon carbide semiconductor device includes a semiconductor element disposed in a semiconductor substrate having a first conductive type silicon carbide layer and a silicon substrate. The device includes: a trench on the silicon carbide layer to reach the silicon substrate; and a conductive layer in the trench between the... Agent: Posz Law Group, Plc

20080128713 - Silicon light emitting diode, silicon optical transistor, silicon laser and its manufacturing method: A light-emitting device according to the present invention includes a first electrode unit 9 for injecting an electron, a second electrode unit 10 for injecting a hole, and light-emitting units 11 and 12 electrically connected to the first electrode unit 9 and the second electrode unit 10 respectively, wherein the... Agent: Miles & Stockbridge Pc

20080128717 - Light emitting diode package and backlight unit having the same: A light-emitting diode (“LED”) package and a backlight unit having the same are disclosed. The LED package includes a package substrate, at least two LED chips arranged on the package substrate spaced apart from each other and having different brightness characteristics, a plurality of electrodes mounted on the package substrate... Agent: Macpherson Kwok Chen & Heid LLP

20080128714 - Low side emitting light source and method of making the same: A light source having a die, a substrate, and a housing is disclosed. The die has a semiconducting light emitting device thereon, the die having a top surface and a bottom surface, light being emitted through the top surface. The die is characterized by a maximum dimension. The substrate has... Agent: Kathy Manke Avago Technologies Limited

20080128715 - Optimization utility for developing embedded systems: A method and apparatus for optimizing the development of an embedded system for a target device. The method may include selecting a set of packages corresponding to the class of an embedded system from various packages available for installation, and integrating the set of packages into a root file system.... Agent: Blakely Sokoloff Taylor & Zafman

20080128716 - Semiconductor light-emitting device and manufacturing method thereof: A semiconductor light-emitting device includes a substrate having two main surfaces; and an active layer forming part, which is made of a compound semiconductor material, formed on one of the main surfaces, and includes an active layer. A plurality of holes, which pass through the active layer, are formed from... Agent: Wood, Herron & Evans, LLP

20080128719 - Lcd pixel array structure and fabrication method thereof: Only five photomasks are used to fabricate a LCD pixel array structure. A gate dielectric layer of the LCD pixel array structure is formed by two deposition steps to increase the storage capacity of the storage capacitor.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080128718 - Light emitting device: A light emitting device, comprises: a first semiconductor light emitting element; a second semiconductor light emitting element; a first metal member mounting on its top face the first semiconductor light emitting element; a second metal member mounting on its top face the second semiconductor light emitting element; and a resin... Agent: Global Ip Counselors, LLP

20080128720 - Light emitting device: A light emitting device is closed. More particularly, a light emitting device capable improving light-extraction efficiency is disclosed. The light emitting device includes a plurality of layers including a reflector layer. The reflector layer has the maximum reflectivity at an incidence angle more than zero degrees and less than an... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20080128721 - Light emitting device and method of manufacturing the same: Herein disclosed a method of manufacturing a light emitting device, including the steps of: (A) sequentially forming a first compound semiconductor layer of a first conduction type, an active layer, and a second compound semiconductor layer of a second conduction type different from said first conduction type, over a substrate;... Agent: Sonnenschein Nath & Rosenthal LLP

20080128722 - Fabrication of semiconductor devices: A method for fabrication of a semiconductor device, the semiconductor device having a plurality of epitaxial layers on a substrate. The plurality of epitaxial layers include an active region in which light is able to be generated. The method comprises applying at least one first ohmic contact layer to a... Agent: Blakely Sokoloff Taylor & Zafman

20080128737 - Horizontal emitting, vertical emitting, beam shaped, distributed feedback (dfb) lasers by growth over a patterned substrate: A structure using integrated optical elements is comprised of a substrate, a buffer layer grown on the substrate, one or more patterned layers formed on the buffer layer and one or more active layers formed on or between the patterned layers, for instance by Lateral Epitaxial Overgrowth (LEO), and including... Agent: Gates & Cooper LLP Howard Hughes Center

20080128732 - Light emitting device: A light emitting device has a light emitting element, and a high-refractive index layer that contacts an emission surface of the light emitting element. The high-refractive index layer has transparent fine particles uniformly arranged along the emission surface. The fine particles has a refractive index high than that of a... Agent: Mcginn Intellectual Property Law Group, Pllc

20080128724 - Light emitting device and process for manufacturing the same: A light emitting device in which the bottom surface of a cup portion is configured to have an opening, and one electrode of a light emitting element is electrically connected to the cup portion, and the other electrode of the light emitting element is electrically connected to a lead which... Agent: Reed Smith LLP

20080128727 - Light recycling systems and methods: Light-emitting devices and/or systems are described. In some embodiments, light-emitting devices and/or systems can recycle at least some light generated by a light-generating region of the light-emitting device. In one embodiment, a light-emitting system comprises a light-emitting device including a light-generating region, a polarization manipulation region that alters a polarization... Agent: Wolf Greenfield & Sacks, P.c.

20080128734 - Light-emitting device: A light emitting device having a transparent substrate, a light emitting stack, and a transparent adhesive layer is provided. The light emitting stack is disposed above the transparent substrate and comprises a diffusing surface. The transparent adhesive layer is disposed between the transparent substrate and the diffusing surface of the... Agent: Bacon & Thomas, Pllc

20080128723 - Low thermal resistance high power led: A light source having a circuit carrier and a die is disclosed. The circuit carrier includes top and bottom conducting layers sandwiching an insulating substrate. The bottom layer has a first surface adjacent to the insulating substrate and a second surface includes a portion of a bottom surface of the... Agent: Kathy Manke Avago Technologies Limited

20080128728 - Polarized light-emitting devices and methods: Light-emitting devices and/or systems are described. In one embodiment, a light-emitting device comprises a light-emitting material stack including a light-generating region and a light emission surface, and a polarizer configured to receive at least some light emitted from the light emission surface of the light-emitting material stack, wherein the polarizer... Agent: Wolf Greenfield & Sacks, P.c.

20080128726 - Red nitride phosphor and production method thereof: A red phosphor where the crystal phase constituting the phosphor is monoclinic Eu-activated CaAlSiN3. A red phosphor which is Eu-activated CaAlSiN3 powder having an average particle diameter of 10 μm or less as measured in the non-pulverized state by the laser scattering particle size distribution analysis. A light-emitting device comprising... Agent: Ip Group Of Dla Piper Us LLP

20080128729 - Semiconductor light emission device emitting polarized light and method for manufacturing the same: A semiconductor light emission device includes: a nitride semiconductor stack including an active layer capable of emitting light, a growth surface of the nitride semiconductor stack