Active solid-state devices (e.g., transistors, solid-state diodes) inventions 05/08

20080121858 - Mim device and electronic apparatus: An MIM device includes a lower electrode of a metal nitride film, a hysteresis film of an oxide film containing Nb formed on the lower electrode, and an upper electrode of a metal nitride film formed on the hysteresis film.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080121859 - Forced ion migration for chalcogenide phase change memory device: Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase change memories. The devices tested included GeTe/SnTe, Ge2Se3/SnTe, and Ge2Se3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the... Agent: Pedersen & Company, PLLC

20080121860 - Semiconductor memory cell and method of forming same: A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is... Agent: Stanley P. Fisher Reed Smith LLP

20080121862 - Bottom electrode geometry for phase change memory: A PCRAM cell has a gradated or layered resistivity bottom electrode with higher resistivity closer to a phase change material, to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current... Agent: Leffert Jay & Polglaze, P.A.

20080121863 - Phase change memory device and method for fabricating the same: A phase change memory device is provided. The phase change memory device includes a substrate comprising a stacked structure. The stacked structure comprises a plurality of insulating layers and conductive layers. Any two of the conductive layers are spaced apart by one of the conductive layers. A first electrode structure... Agent: Quintero Law Office, PC

20080121864 - Resistive random access memory and method of manufacturing the same: Example embodiments relate to a resistive random access memory (RRAM) and a method of manufacturing the RRAM. A RRAM according to example embodiments may include a lower electrode, which may be formed on a lower structure (e.g., substrate). A resistive layer may be formed on the lower electrode, wherein the... Agent: Harness, Dickey & Pierce, P.L.C

20080121861 - Self-aligned structure and method for confining a melting point in a resistor random access memory: A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080121865 - Nonvolatile memory device, array of nonvolatile memory devices, and methods of making the same: A nonvolatile memory device including a lower electrode, a resistor structure disposed on the lower electrode, a middle electrode disposed on the resistor structure, a diode structure disposed on the middle electrode, and an upper electrode disposed on the diode structure. A nonvolatile memory device wherein the resistor structure includes... Agent: Harness, Dickey & Pierce, P.L.C

20080121866 - Avalanche photodiode detector: An avalanche photodiode detector is provided. The avalanche photodiode detector comprises an absorber region having an absorption layer for receiving incident photons and generating charged carriers; and a multiplier region having a multiplication layer; wherein the multiplier region is on a mesa structure separate from the absorber region and is... Agent: Klein, O'neill & Singh, LLP

20080121867 - Avalanche photodiode: Additionally, the configuration is in such a way that, by removing at least the light absorption layer among the layers which are layered on the peripheral portion, of the substrate, on which the second conductivity type conductive region and the second semiconductor layer around the second conductivity type conductive region... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080121868 - Schottky barrier tunnel transistor and method for fabricating the same: A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the... Agent: Blakely Sokoloff Taylor & Zafman

20080121875 - Array substrate for liquid crystal display device and method of fabricating the same: An organic thin film transistor includes source and drain electrodes spaced apart from each other on a substrate, an organic semiconductor layer between the source and drain electrodes on the substrate, a gate insulating layer including an organic insulating material on the organic semiconductor layer, the gate insulating layer having... Agent: Seyfarth Shaw, LLP

20080121872 - Display apparatus and method of manufacturing thereof: A display apparatus, such as an organic light emitting diode (“OLED”) display, is driven by thin film transistors (“TFTs”), including a driving TFT and a switching TFT, and a pixel electrode. The display apparatus includes an amorphous silicon layer for the switching TFT and a microcrystalline silicon or polycrystalline silicon... Agent: Cantor Colburn, LLP

20080121871 - Mononuclear star-branched polymer dielectric material and organic thin film transistor: wherein, X represents H or CH3; R represents H, alkyl or is selected from a group consisting of acetoxyl, t-butyl, t-butyldimethyl silyl, acid labile groups and acid stable groups; “a” is an integer from 1 to 5; y and z are molar ratio and are the numbers satisfying y+z=1, 0<y≦1... Agent: Jianq Chyun Intellectual Property Office

20080121873 - Organic thin film transistor material, organic thin film transistor, field-effect transistor, switching element, organic semiconductor material and organic semiconductor film: where A composed of a condensed ring formed with a 6 membered aromatic cycle or a 6 membered aromatic heterocycle represents C—R, N or P; at least one of As is N or P; R represents a hydrogen atom, a halogen atom or a substituent; and R may be bonded... Agent: Lucas & Mercanti, LLP

20080121869 - Organic thin film transistor with dual layer electrodes: A thin-film transistor (TFT) with dual-layer source and drain electrodes is provided. Each source and drain electrode comprises a first layer and a second layer. The first layer has a work function which differs from the energy level of the semiconductor by at least 0.5 eV and the second layer... Agent: Fay Sharpe / Xerox - Rochester

20080121874 - Semiconductor device: The present invention is to provide a semiconductor device in which the step can be simplified, the manufacturing cost can be suppressed, and the decrease in yield can be suppressed. A semiconductor device of the present invention includes an antenna, a storage element, and a transistor, wherein a conductive layer... Agent: Eric Robinson

20080121876 - Surface-stabilized semiconductor device: A high electron mobility transistor is disclosed which has a main semiconductor region formed on a silicon substrate. The main semiconductor region is a lamination of a buffer layer on the substrate, an electron transit layer on the buffer layer, and an electron supply layer on the electron transit layer.... Agent: Woodcock Washburn LLP

20080121870 - Transition-metal charge transport materials, methods of fabrication thereof, and methods of use thereof: Briefly described, embodiments of this disclosure include transition-metal charge-transport materials, methods of forming transition-metal charge-transport materials, and methods of using the transition-metal charge-transport materials.... Agent: Christopher B. Linder Thomas, Kayden, Horstemeyer & Risley

20080121877 - Thin film transistor with enhanced stability: Electronic devices such as transistors are disclosed. The electronic device includes an electrically conductive gate electrode, an anodized layer disposed on the gate electrode, a dielectric layer disposed on the anodized layer, and a semiconductor oxide layer that has a channel region. The channel region is disposed on the dielectric... Agent: 3m Innovative Properties Company

20080121879 - High density integrated circuit apparatus, test probe and methods of use thereof: The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an... Agent: Ibm Corporation

20080121878 - Interposer, semiconductor chip mounted sub-board, and semiconductor package: e

20080121880 - Method of measuring thickness of layer in image sensor and pattern for the same: A method of measuring thickness of a layer in an image sensor and pattern for the same are disclosed, by which layer thickness measurement of an image sensor is enabled in the course of fabrication. Embodiments relate to a method of measuring thickness of a layer in an image sensor... Agent: Sherr & Nourse, PLLC

20080121881 - Semiconductor device: A semiconductor device includes a power device formed on a semiconductor substrate; a plurality of transistors formed on the semiconductor substrate; a first insulating film formed on the semiconductor substrate so as to cover the power device and the plurality of transistors; an interconnect layer formed on the first insulating... Agent: Mcdermott Will & Emery LLP

20080121882 - Method to reduce junction leakage through partial regrowth with ultrafast anneal and structures formed thereby: Methods and associated structures of forming a microelectronic device are described. Those methods may include creating an amorphous region in source/drain regions of a substrate by ion implantation with an electrically neutral dopant, annealing with a first anneal that removes defects without completely re-crystallizing the amophous region, ion implantation of... Agent: Intel Corporation C/o Intellevate, LLC

20080121883 - Semiconductor device and manufacturing method thereof: A disclosed semiconductor device includes a gate electrode that is arranged on a substrate via a gate dielectric film. A gate electrode head is formed on the gate electrode, which gate electrode head is wider than the gate electrode, and extends between a first side wall dielectric film and a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080121884 - Patterned-print thin-film transistors with top gate geometry: A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to... Agent: JasIPConsulting

20080121886 - Flat panel display and method of fabricating the same: Exemplary embodiments provide a flat panel display and method for forming the same including a substrate having a pixel driving circuit region and an emission region, a thin film transistor in the pixel driving circuit region, and a pixel electrode on the same layer as the source and drain electrodes.... Agent: Lee & Morse, P.C.

20080121885 - Thin film transistor array panel of active liquid crystal display and fabrication method thereof: A thin film transistor (TFT) array panel structure and a fabrication method thereof are provided. The method includes the following steps. An insulating substrate is provided, on which a first metal layer is deposited to form a plurality of gate electrodes, a plurality of lower electrodes of storage capacitors, a... Agent: Apex Juris, PLLC Tracy M Heims

20080121890 - Deposition method of insulating layers having low dielectric constant of semiconductor device, a thin film transistor substrate using the same and a method of manufacturing the same: The present invention relates to a process for vapor depositing a low dielectric insulating film, a thin film transistor using the same, and a preparation method thereof, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while... Agent: F. Chau & Associates, LLC

20080121887 - Non-volatile memory device and fabrication method thereof and memory apparatus including thereof: A non-volatile memory device is capable of reducing an excessive leakage current due to a rough surface of a polysilicon and of realizing improved blocking function by forming the first oxide film including a silicon oxy-nitride (SiOxNy) layer using nitrous oxide (N2O) plasma, and by forming silicon-rich silicon nitride film,... Agent: Stein, Mcewen & Bui, LLP

20080121888 - Nonvolatile memory cell, array thereof, fabrication methods thereof and device comprising the same: A nonvolatile memory cell is capable of reducing an excessive current leakage due to a rough surface of a polysilicon and of performing even at a low temperature process by forming the first oxide film including a silicon oxynitride (SiOxNy) layer using nitrous oxide plasma and by forming a plurality... Agent: Stein, Mcewen & Bui, LLP

20080121889 - Semiconductor device, method for manufacturing semiconductor device, and electro-optical apparatus: A semiconductor device includes a thin-film transistor including a polycrystalline silicon layer, disposed above a substrates serving as an active layer. The thin-film transistor includes a first thin-film transistor section including a first channel region disposed in a drain-side portion of the polycrystalline silicon layer and also includes a second... Agent: Oliff & Berridge, PLC

20080121893 - Display panel: A display panel includes gate lines formed on a substrate, storage electrode lines formed on the substrate and being parallel to the gate lines, data lines insulated from the gate lines and crossing the gate lines, a plurality of thin film transistors (TFTs) connected with the gate lines and the... Agent: F. Chau & Associates, LLC

20080121892 - Low temperature poly silicon liquid crystal display: The invention discloses an LTPS LCD comprising a plurality of NMOS elements and PMOS elements on a substrate. Each element comprises a SiNx layer underlying or capping a gate electrode. The SiNx layer features an appropriate length extending from the bottom edge of the gate electrode. The SiNx layer can... Agent: Liu & Liu

20080121894 - Method of manufacturing display device: A TFT device having a pixel portion and a driving circuit portion formed on a glass substrate; wherein at least the active layer (active region) of a transistor constituting said driving circuit comprises polycrystalline silicon including crystals that do not have crystal grain boundaries which cross the direction of current... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080121891 - Method of measuring degree of crystallinity of polycrystalline silicon substrate, method of fabricating organic light emitting display using the same, and organic light emitting display fabricated using the same: A method of measuring a degree of crystallinity of a polycrystalline silicon substrate includes obtaining a Raman spectrum graph by irradiating a polycrystalline silicon substrate with a laser beam; and calculating a degree of crystallinity of the polycrystalline silicon substrate from the Raman spectrum graph using the following formula: (degree... Agent: Stein, Mcewen & Bui, LLP

20080121895 - Methods of fabricating semiconductor devices including implanted regions for providing low-resistance contact to buried layers and related devices: Methods of fabricating a semiconductor device include forming a first semiconductor layer of a first conductivity type and having a first dopant concentration, and forming a second semiconductor layer on the first semiconductor layer. The second semiconductor layer has a second dopant concentration that is less than the first dopant... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080121896 - Nitride semiconductor material, semiconductor element, and manufacturing method thereof: The nitride semiconductor material according to the present invention includes a group III nitride semiconductor and a group IV nitride formed on the group III nitride semiconductor, where an interface between the group III nitride semiconductor and the group IV nitride has a regular atomic arrangement. Moreover, an arrangement of... Agent: Greenblum & Bernstein, P.L.C

20080121897 - Boron aluminum nitride diamond heterostructure: A heterostructure having a heterojunction comprising: a diamond layer; and a boron aluminum nitride (B(x)Al(1-x)N) layer disposed in contact with a surface of the diamond layer, where x is between 0 and 1.... Agent: Raytheon Company C/o Daly, Crowley, Mofford & Durkee, LLP

20080121898 - Display system: A display system provides a first semiconductor light source that is electrically connected in a first plane. A second semiconductor light source is electrically connected in a second plane separate from the first plane. A third semiconductor light source is electrically connected in the first plane at least a distance... Agent: Apple C/o Mofo Sd

20080121900 - Light emitter assembly: A plurality of disc-shaped substrates carry light emitters and are axially stacked, spaced apart, in a metal housing to dissipate the heat produced by the light emitters. The housing comprises mutually connected elongate planar ribs that abut the light emitters or substrates for thermally connecting the light emitters to the... Agent: Wells St. John P.s.

20080121901 - Light emitting device: A light emitting device is disclosed. A light emitting device according to an embodiment of the present invention may include a substrate comprising a light emitting region and a non-light emitting region, a second electrode disposed over the substrate, a sub-pixel disposed in the light emitting region and comprising a... Agent: Ked & Associates, LLP

20080121899 - Transparent electrode for led array: An array of light emitting diodes coupled between a substrate and a transparent electrode include a pair of equipotential bus bars supplying electrical current simultaneously to at least two light emitting diodes, each located in its own area of transparent conductive material. In accordance with another aspect of the invention,... Agent: Paul F. Wille Cantor Colburn LLP

20080121903 - Method for manufacturing light-emitting diode, light-emitting diode, lightsource cell unit, light-emitting diode backlight, light-emitting diode illuminating device, light-emitting diode display, and electronic apparatus: A light-emitting diode which has a significantly high luminous efficiency and which can be manufactured at a reasonable cost by one epitaxial growth and a manufacturing method thereof are provided. The above method includes: preparing a substrate provided with convex portions on one major surface, the convex portions being formed... Agent: Sonnenschein Nath & Rosenthal LLP

20080121902 - Small footprint high power light emitting package with plurality of light emitting diode chips: A light emitting package includes a support (12, 112, 212) defining a support surface (14). A first light emitting diode chip (20, 120, 220) is secured to the supporting surface and is configured to emit light having a first spectral distribution. A second light emitting diode chip (22, 122, 123,... Agent: Fay Sharpe LLP

20080121904 - Semiconductor light-emitting device, semiconductor light-emitting apparatus, and method of manufacturing semiconductor light-emitting device: There is obtained a semiconductor light-emitting device capable of obtaining a high light reflectance through the use of a high-reflection metal layer formed on the side of an electrode on one side and capable of preventing migration of atoms from the high-reflectance metal layer. Semiconductor layers of the opposite conduction... Agent: Bell, Boyd & Lloyd, LLP

20080121905 - Planar flip & small chips integrated led chip and its manufacture method: A planar flip bonded & small chips integrated LED chip comprising a plurality of LED bare chips and silicon substrates; the LED bare chip comprising a substrate, a N type epitaxial layer, and a P type epitaxial layer; the silicon substrate having two separated deposited metal layers facing each LED... Agent: Kamrath & Associates P.A.

20080121908 - Fabrication of reflective layer on semconductor light emitting devices: Fabrication of Reflective Layer on Semiconductor Light emitting diodes A method for fabrication of a reflective layer on a semiconductor light emitting diode, the semiconductor light emitting diode having a wafer with multiple epitaxial layers on a substrate; the method comprising applying a first ohmic contact layer on a front... Agent: Blakely Sokoloff Taylor & Zafman

20080121907 - Light emitting diode and fabricating method thereof: An LED includes a substrate, a first type doping semiconductor layer, a first electrode, a light emitting layer, a second type doping semiconductor layer, a second electrode, a first dielectric layer and a first conductive plug. The first type doping semiconductor layer is formed on the substrate, and the light... Agent: Jianq Chyun Intellectual Property Office

20080121906 - Method for fabrication of semiconductor light-emitting device and the device fabricated by the method: A method for producing a semiconductor light-emitting device includes stacking at least a first conductive type semiconductor layer (2), an active layer (3) and a second conductive type semiconductor layer (4) on a substrate (1) to form a wafer, then forming on a side of growth surfaces of the semiconductor... Agent: Sughrue Mion, PLLC

20080121909 - Semiconductor device: A semiconductor device has first and second III-V compound semiconductor layers one of which functions as a photosensitive layer or as a light emitting layer, which are doped with a p-type impurity in a low concentration, and which are joined to each other to make a heterojunction. An energy gap... Agent: Drinker Biddle & Reath (dc)

20080121914 - Flip-chip light emitting diodes and method of manufacturing thereof: Provided are a flip-chip nitride-based light emitting device having an n-type clad layer, an active layer and a p-type clad layer sequentially stacked thereon, comprising a reflective layer formed on the p-type clad layer and at least one transparent conductive thin film layer made up of transparent conductive materials capable... Agent: Harness, Dickey & Pierce, P.L.C

20080121917 - High efficiency white, single or multi-color light emitting diodes (leds) by index matching structures: Light emitting diode (LED) structures with an overstructure material having a refractive-index matched to the active layer and ways to produce such materials are disclosed. Various implementations of such structures to provide very high extraction efficiency and color control such as white light emission are also disclosed.... Agent: Gates & Cooper LLP Howard Hughes Center

20080121918 - High light extraction efficiency sphere led: This invention is related to LED Light Extraction for optoelectronic applications. More particularly the invention relates to (Al, Ga, In)N combined with optimized optics for highly efficient (Al, Ga, In)N based light emitting diodes applications, and its fabrication method. A further extension is the general combination of a shaped high... Agent: Gates & Cooper LLP Howard Hughes Center

20080121913 - Inverted-pyramidal photonic crystal light emitting device: A light-emitting device (LED) is described which exhibits high extraction efficiency and an emission profile which is substantially more directional than from a Lambertian source. The device comprises a light generating layer disposed between first and second layers of semiconductor material, each having a different type of doping. An upper... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080121916 - Method of forming a metal contact and passivation of a semiconductor feature: A method of forming a metal contact and passivation of a semiconductor feature, and devices made using the method. The method comprises the steps of forming a dielectric mask on a semiconductor substrate utilising photolithography processes; etching the semiconductor substrate such that one or more features are formed underneath respective... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080121911 - Optical preforms for solid state light emitting dice, and methods and systems for fabricating and assembling same: A preform is attached to a solid state light emitting die. One or more optical elements, such as a photoluminescent element, a refracting element, a filtering element, a scattering element, a diffusing element or a reflecting element, is included in and/or on the preform. For example, the preform may be... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080121912 - Pyramidal photonic crystal light emitting device: A light-emitting device (LED) is described which exhibits high extraction efficiency and an emission profile which is substantially more directional than from a Lambertian source. The device comprises a light generating layer disposed between first and second layers of semiconductor material, each having a different type of doping. An upper... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080121915 - Semiconductor device and display device having alignment mark: A semiconductor device includes a semiconductor substrate and an alignment mark. The alignment mark is provided on the semiconductor substrate and optically detectable. The alignment mark includes a bright area and a dark area. The bright area outputs light reflected from a surface of the semiconductor substrate. The dark area... Agent: Mcginn Intellectual Property Law Group, PLLC

20080121910 - Semiconductor devices having low threading dislocations and improved light extraction and methods of making the same: Semiconductor device structures are provided that are suitable for use in the fabrication of electronic devices such as light emitting diodes. The semiconductor device structures include a substrate having a roughened growth surface suitable for supporting the growth of an epitaxial region thereon. The device structure can include an epitaxial... Agent: Summa, Allan & Additon, P.A.

20080121919 - Wavelength-converted semiconductor light emitting device: A material such as a phosphor is optically coupled to a semiconductor structure including a light emitting region disposed between an n-type region and a p-type region, in order to efficiently extract light from the light emitting region into the phosphor. The phosphor may be phosphor grains in direct contact... Agent: Patent Law Group LLP

20080121920 - Flip-chip packaging structure for light emitting diode and method thereof: A packaging structure and method for a light emitting diode is provided. The present invention uses flip-chip and eutectic bonding technology to attach a LED to a thermal and electrical conducting substrate. The flip-chip packaging structure comprises a thermal and electrical conducting substrate having an insulating layer formed in an... Agent: Wpat, PC Intellectual Property Attorneys

20080121921 - Leadframe-based packages for solid state light emitting devices and methods of forming leadframe-based packages for solid state light emitting devices: A modular package for a light emitting device includes a leadframe having a top surface and including a central region having a bottom surface and having a first thickness between the top surface of the leadframe and the bottom surface of the central region. The leadframe may further include an... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080121922 - Light emitting diode package with large viewing angle: A light emitting diode package with large viewing angle includes a substrate, a LED chip, transparent housing body, and phosphor matrix. The substrate has an upper surface with a first electrode and a second electrode and a lower surface opposite to the upper surface. The LED chip with a positive... Agent: Pro-techtor International Services

20080121923 - Method for producing an optoelectronic component, and an optoelectronic component: A method for producing an optoelectronic component comprising the steps of providing a semiconductor layer sequence having at least one active region, wherein the active region is suitable for emitting electromagnetic radiation during operation, and applying at least one layer on a first surface of the semiconductor layer sequence by... Agent: Cohen Pontani Lieberman & Pavane LLP

20080121924 - Apparatus for manufacturing group iii nitride compound semiconductor light-emitting device, method of manufacturing group iii nitride compound semiconductor light-emitting device, group iii nitride compound semiconductor light-emitting device, and lamp: A Group III nitride compound semiconductor light-emitting device manufacturing apparatus with a simple structure, which it is capable of easily optimizing the density of a dopant element in the crystals of a Group III nitride compound semiconductor and forming layers with high efficiency using a sputtering method. The manufacturing apparatus... Agent: Sughrue Mion, PLLC

20080121925 - Low voltage triggered silicon controlled rectifier: Disclosed is a low voltage triggered silicon controlled rectifier (LVTSCR) . The LVTSCR includes a first-type semiconductor substrate; a second-type well formed in a predetermined region of the semiconductor substrate; first to third diffusion regions sequentially formed in the well; fourth to sixth diffusion regions sequentially formed at an outside... Agent: Ladas & Parry LLP

20080121927 - Group iii nitride semiconductor devices and methods of making: A device having an electrode-insulator layer-group III nitride layer structure, wherein an interface between the insulator layer and the group III nitride semiconductor layer lies along a non-polar plane of the group III nitride semiconductor layer is provided.... Agent: General Electric Company (pcpi) C/o Fletcher Yoder

20080121926 - Integrated circuit system with carbon and non-carbon silicon: An integrated circuit system includes a substrate, a carbon-containing silicon region over the substrate, a non-carbon-containing silicon region over the substrate, and a silicon-carbon region, including the non-carbon-containing silicon region and the carbon-containing silicon region.... Agent: Law Offices Of Mikio Ishimaru

20080121928 - Semiconductor photocathode: A semiconductor photocathode has first and second III-V compound semiconductor layers doped with a p-type impurity and joined to each other to make a heterojunction. The second III-V compound semiconductor layer functions as a light absorbing layer, an energy gap of the second III-V compound semiconductor layer is smaller than... Agent: Drinker Biddle & Reath (dc)

20080121930 - Monocrystalline extrinsic base and emitter heterojunction bipolar transistor and related methods: A heterostructure bipolar transistor (HBT) and related methods are disclosed. In one embodiment, the HBT includes a heterostructure bipolar transistor (HBT) including: a substrate; a monocrystalline emitter atop the substrate; a collector in the substrate; at least one isolation region adjacent to the collector; a monocrystalline silicon germanium (SiGe) intrinsic... Agent: Hoffman, Warnick & D'alessandro LLC

20080121929 - Silicide formation on sige: A semiconductor structure includes a first silicon-containing layer comprising an element selected from the group consisting essentially of carbon and germanium wherein the silicon-containing layer has a first atomic percentage of the element to the element and silicon, a second silicon-containing layer comprising the element over the first silicon-containing layer,... Agent: Slater & Matsil, L.L.P.

20080121932 - Active regions with compatible dielectric layers: A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric... Agent: Intel/blakely

20080121933 - Method of manufacturing a semiconductor device and products made thereby: Methods of manufacturing a semiconductor device and resulting products. The semiconductor device includes a semiconductor substrate, a hetero semiconductor region hetero-adjoined with the semiconductor substrate, a gate insulation layer contacting the semiconductor substrate and a heterojunction of the hetero semiconductor region, a gate electrode formed on the gate insulation layer,... Agent: Young & Basile, P.C.

20080121934 - Semiconductor device having schottky junction and method for manufacturing the same: A semiconductor device includes: a nitride semiconductor layer including a channel layer, a Schottky electrode that contacts the nitride semiconductor layer and contains indium, and an ohmic electrode that contacts the channel layer. The nitride semiconductor layer includes a layer that contacts the Schottky electrode and contains AlGaN, InAlGaN or... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080121931 - Semiconductor structure and method of making same: The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate... Agent: Greenblum & Bernstein, P.L.C

20080121935 - Compound semiconductor device and method for fabricating the same: In a HEMT with a spacer layer composed of a 3 nm-thick intrinsic InAlAs layer, a supply layer composed of a 4 nm-thick n-type InAlAs layer, and a barrier layer composed of a 5 nm-thick intrinsic InAlAs layer, the spacer layer and supply layer exist between a channel layer and... Agent: Kratz, Quintos & Hanson, LLP

20080121937 - Heterojunction bipolar transistor with monocrystalline base and related methods: A heterostructure bipolar transistor (HBT) and related methods are disclosed. In one embodiment, the HBT includes a substrate; a polysilicon emitter atop the substrate; a collector in the substrate; at least one isolation region adjacent to the collector; an intrinsic base including monocrystalline silicon germanium extending over each isolation region;... Agent: Hoffman, Warnick & D'alessandro LLC

20080121936 - Self-alignment scheme for a heterojunction bipolar transistor: Embodiments herein present a structure, method, etc. for a self-alignment scheme for a heterojunction bipolar transistor (HBT). An HBT is provided, comprising an extrinsic base, a first self-aligned silicide layer over the extrinsic base, and a nitride etch stop layer above the first self-aligned silicide layer. A continuous layer is... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080121938 - Nitride semiconductor based bipolar transistor and the method of manufacture thereof: In a nitride semiconductor based bipolar transistor, a contact layer formed so as to contact an emitter layer is composed of n-type InAlGaN quaternary mixed crystals, the emitter layer and the contact layer are selectively removed so that the barrier height with the emitter formed thereon is small, and the... Agent: Steptoe & Johnson LLP

20080121939 - Methods of automatically generating dummy fill having reduced storage size: The disclosure relates generally to production of lithography masks such as used in mass production of monolithic integrated circuits (IC's). Layers of such IC's often need to be filled with dummy-fill. In accordance with the disclosure, dummy-objects are first generated by a conventional flat-fill technique and then they are automatically... Agent: Macpherson Kwok Chen & Heid LLP

20080121940 - Semiconductor device and fabricating method thereof: A flash memory device with a system in package (SIP) structure and a fabricating method thereof are provided. In the semiconductor device of an embodiment, a flash memory device is formed by forming cell transistors and high voltage transistors on different wafers, and connecting each of vertically stacked chips in... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080121941 - Diagonal deep well region for routing body-bias voltage for mosfets in surface well regions: Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.... Agent: Murabito, Hao & Barnes LLP Third Floor

20080121942 - Memory formation with reduced metallization layers: A semiconductor structure includes a static random access memory (SRAM) cell comprising a first pull-up MOS device, a first pull-down MOS device and a first pass-gate MOS device, a first metallization layer, and an inter-layer dielectric (ILD) underlying the first metallization layer, wherein the ILD comprises an upper portion and... Agent: Slater & Matsil, L.L.P.

20080121943 - Top layers of metal for integrated circuits: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses... Agent: Saile Ackerman LLC

20080121944 - Verification architecture of infrared thermal imaging array module: The present invention relates to a verification architecture of an infrared thermal imaging array module, which includes the following steps. Perform specification design of thermal imaging module, epitaxy, and verification of optical characteristics for calibrating epitaxial parameters. Perform a fabrication process of single-device-type sensing device and verification of changing-temperature optoelectronic... Agent: Rosenberg, Klein & Lee

20080121945 - Magnetic switching element and a magnetic memory: A magnetic switching element includes a ferromagnetic layer which is substantially pinned in magnetization in one direction; and a magnetic semiconductor layer provided within a range where a magnetic field from the ferromagnetic layer reaches, where the magnetic semiconductor layer changes its state from a paramagnetic state to a ferromagnetic... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080121946 - Method of forming sensor for detecting gases and biochemical materials, integrated circuit having the sensor, and method of manufacturing the integrated circuit: A method of forming a sensor for detecting gases and biochemical materials that can be fabricated at a temperature in a range from room temperature to 400° C., a metal oxide semiconductor field effect transistor (MOSFET)-based integrated circuit including the sensor, and a method of manufacturing the integrated circuit are... Agent: Ladas & Parry LLP

20080121947 - Solar-powered mems acoustic sensor and system for providing physical security in a geographical area with use thereof: A MEMS microphone is fabricated into an integrated physical device which also comprises a solar cell. The solar cell provides power to the MEMS microphone, and may do so with use of a capacitor, which may also be incorporated into the device, and serves to provide power to the MEMS... Agent: Lucent Technologies Inc. Docket Administrator - Room 3j-219

20080121948 - Finfet drive strength de-quantization using multiple orientation fins: A fin-type field effect transistor (FINFET) includes a plurality of fins forming drain-source regions and a gate region disposed about the fins. At least a first one of the fins has a first crystal orientation, and at least a second one of the fins has a second crystal orientation that... Agent: Ryan, Mason & Lewis, LLP

20080121950 - Semiconductor device: The channel length direction of n channel MISFET where the silicide region of nickel or a nickel alloy was formed on the source and the drain is arranged so that it may become parallel to the crystal orientation <100> of a semiconductor substrate. Since it is hard to extend the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080121949 - Semiconductor structures incorporating multiple crystallographic planes and methods for fabrication thereof: A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped... Agent: Scully, Scott, Murphy & Presser, P.C.

20080121951 - Cmos image sensor process and structure: A CMOS image sensor (CIS) process is described. A semiconductor substrate is provided, and then a gate dielectric layer, a gate material layer and a thickening layer are sequentially formed on the substrate, wherein the thickening layer includes at least a hard mask layer. The thickening layer is defined to... Agent: Jianq Chyun Intellectual Property Office

20080121952 - Cmos image sensor: Embodiments relate to a CMOS image sensor and a method of fabricating the same. In embodiments, a recessed gate of a transfer transistor (Tx) may be formed. In embodiments, a device isolation layer may be formed on a semiconductor substrate including an epitaxial layer, a recessed gate electrode pattern of... Agent: Sherr & Nourse, PLLC

20080121953 - Enhanced local interconnects employing ferroelectric electrodes: A ferroelectric device employs ferroelectric electrodes as local interconnect(s). One or more circuit features are formed within or on a semiconductor body. A first dielectric layer is formed over the semiconductor body. Lower contacts are formed within the first dielectric layer. A bottom electrode is formed over the first dielectric... Agent: Texas Instruments Incorporated

20080121954 - Ferroelectric storage device and method of fabricating the same: A ferroelectric layer is formed on a semiconductor substrate, a first hard mask layer is formed on the ferroelectric layer, and a second hard mask layer is formed on the first hard mask layer. A plurality of parallel isolation trenches are formed by etching the second hard mask layer, first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080121957 - Non-volatile memory device and method of manufacturing non-volatile memory device: A non-volatile memory device including a ferroelectric capacitor is disclosed. A method of manufacturing a non-volatile memory device including a ferroelectric capacitor is also disclosed. A first electrode is formed on an insulating film provided on a semiconductor substrate. A first ferroelectric film is formed on the first electrode. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080121958 - Semiconductor device and manufacturing method of the same: A stacked film of a first insulation film being a silicon oxide film with an extremely low moisture content, and a second insulation film being a silicon oxide film with a higher moisture content than the first insulation film, therefore, with a low in-plane film thickness distribution rate is formed,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080121959 - Semiconductor device and semiconductor product: The embodiments discussed herein reduce, in a semiconductor device having a ferroelectric capacitor, the film thickness of an interlayer insulation film covering the ferroelectric capacitor without degrading yield, and reduce the invasion of water into the ferroelectric capacitor. A semiconductor device includes a first interlayer insulation film formed on a... Agent: Staas & Halsey LLP

20080121956 - Semiconductor device having ferroelectric memory cell and method for fabricating the same: According to an aspect of the invention, there is provided, a semiconductor device having a ferroelectric memory cell, comprising a semiconductor substrate, a transistor being formed on the semiconductor substrate, an inter-layer insulator being formed over the transistor to cover the transistor, a ferroelectric capacitor including a lower electrode formed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080121955 - Silicon-based ferroelectric memory material and memory: There is provided a silicon-based ferroelectric memory material, which includes a mesoporous silica with the nanopores thereon, and high-density arrays of nanocrystalline silicon or germanium quantum dots formed on the inner wall of the nanopores of the mesoporous silica. The silicon-based ferroelectric memory material is substantially composed of silicon and... Agent: Birch Stewart Kolasch & Birch

20080121960 - Semiconductor device and method of forming the same: A semiconductor device may include a MOS transistor having source and drain regions in a semiconductor substrate, a first inter-layer insulator having first contact holes that reach the source and drain regions over the MOS transistor. Cell contact plugs in the first contact holes contact with the source and drain... Agent: Young & Thompson

20080121961 - Transistor and memory cell array: A transistor, which is formed in a semiconductor substrate having a top surface, includes first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode for controlling an electrical current flowing in the channel. The gate electrode is disposed in a lower portion... Agent: Edell, Shapiro & Finnan, LLC

20080121964 - Semiconductor device and method of manufacturing the same: In one embodiment of the present invention, provided is a semiconductor device having a silicon substrate provided with a DRAM region containing first transistors and capacitor elements, and with a logic region containing second transistors. A minimum gate length of the second transistors provided in the logic region is smaller... Agent: Young & Thompson

20080121963 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming an insulating material layer. The method includes forming a barrier layer and forming a rare earth element-containing material layer over the barrier layer.... Agent: Slater & Matsil LLP

20080121962 - Tantalum aluminum oxynitride high-k dielectric and metal gates: Electronic apparatus and methods of forming the electronic apparatus may include a tantalum aluminum oxynitride film for use in a variety of electronic systems and devices. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer... Agent: Schwegman, Lundberg & Woessner, P.A.

20080121965 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory of an aspect of the present invention comprises a plurality of memory cell transistors which are connected in series to one another with a first gate spacing, every two adjacent transistors of the memory cell transistors sharing a source/drain diffusion layer, and a first select gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080121966 - Nanocrystal non-volatile memory cell and method therefor: A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and... Agent: Freescale Semiconductor, Inc. Law Department

20080121967 - Nanocrystal non-volatile memory cell and method therefor: A method of forming a semiconductor device, which is preferably a memory cell, includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, wherein each of the plurality of discrete storage elements has a diameter value that is... Agent: Freescale Semiconductor, Inc. Law Department

20080121971 - Apparatus and associated method for making a floating gate cell with increased overlay between the control gate and floating gate: A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell... Agent: Baker & Mckenzie LLP Patent Department

20080121970 - Finned memory cells and the fabrication thereof: Methods and apparatus are provided. For an embodiment, a plurality fins is formed in a substrate so that the fins protrude from a substrate. After the plurality fins is formed, the fins are isotropically etched to reduce a width of the fins and to round an upper surface of the... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20080121973 - Fully logic process compatible non-volatile memory cell with a high coupling ratio and process of making the same: A fully logic process compatible non-volatile memory cell has a well on a substrate, a pair of source and drain outside the well, a channel between the source and drain, a control gate in the well, and a floating gate having a first portion above the channel, and a second... Agent: Rosenberg, Klein & Lee

20080121969 - Non-volatile memory cell device and methods: A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the second dielectric layer encases the nanodots. In addition, an intergate dielectric layer is formed over the second dielectric layer. To form sidewalls of the... Agent: Brooks, Cameron & Huebsch , PLLC

20080121972 - Semiconductor device and method of manufacturing the same: A semiconductor device including a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate; a first gate electrode layer formed on the first gate insulating film; an element isolation insulating film formed so as to isolate a plurality of the first gate electrode layers; a second gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080121968 - Sensing memory device: A sensing memory device disposed on a substrate is provided, which includes a first conductive layer, a second conductive layer and a charge trapping layer. The second conductive layer covers the first conductive layer. The charge trapping layer is disposed between the first conductive layer and the second conductive layer.... Agent: Jianq Chyun Intellectual Property Office

20080121974 - Self-aligned split gate memory cell and method of making: A method for forming a split gate memory cell (10,11) using a semiconductor substrate (12) includes forming a select gate structure (48) and a sacrificial structure (50) over the substrate. An opening is between the select gate structure and the sacrificial structure. The opening is lined with a storage layer... Agent: Freescale Semiconductor, Inc. Law Department

20080121975 - Split-gate memory cells and fabrication methods thereof: Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080121976 - Non-volatile memory cell devices and methods: A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of the intergate dielectric layer is removed with a... Agent: Brooks, Cameron & Huebsch , PLLC

20080121978 - Nonvolatile memory element: A nonvolatile memory element includes a laminated gate provided above a semiconductor substrate with a tunnel insulating film disposed therebetween and having a floating gate electrode, a gate-gate insulating film and a control gate electrode sequentially stacked. The gate-gate insulating film includes a first silicon oxide film, a first aluminum... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080121979 - Nonvolatile semiconductor memory device and method for manufacturing the same: A nonvolatile semiconductor memory device includes: a tunneling insulating film; a floating gate electrode; an inter-electrode insulating film, in which an interface facing the floating gate electrode and an interface facing a control gate electrode are defined as the first interface and the second interface, respectively; and a control gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080121977 - Semiconductor device and method of manufacturing having the same: A semiconductor device includes a substrate having a trench, a liner layer pattern on sidewalls and a bottom surface of the trench, the liner layer pattern including a first oxide layer pattern and a second oxide layer pattern, a diffusion blocking layer pattern on the liner layer pattern, and an... Agent: Lee & Morse, P.C.

20080121980 - Bottom dielectric structures and high-k memory structures in memory devices and methods for expanding a second bit operation window: Methods and structures are described for increasing a memory operation window in a charge trapping memory having a plurality of memory cells in which each memory cell is capable of storing multiple bits per memory cell. In a first aspect of the invention, a first method to increase a memory... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080121983 - Gate and method of forming the same, and memory device and method of manufacturing the same: A gate of a memory device may include a charge trapping structure having a tunnel oxide layer, a charge storing layer, and a blocking layer on a semiconductor substrate; a conductive pattern on the charge trapping structure, the conductive pattern including metal nitride; an ohmic film on the conductive pattern;... Agent: Lee & Morse, P.C.

20080121981 - Memory system with protection layer to cover the memory gate stack and methods for forming same: A memory system is provided including forming a memory gate stack having a charge trap layer over a semiconductor substrate, forming a protection layer to cover the memory gate stack, and forming a protection enclosure for the charge trap layer with the protection layer and the memory gate stack.... Agent: Law Offices Of Mikio Ishimaru

20080121982 - Semiconductor structure, semiconductor memory device and method of manufacturing the same: A semiconductor structure includes first and second conductive lines which cross each other. The second conductive lines are electrically insulated from the first conductive lines via an insulating material. The second conductive lines include first and second sections. First sections are arranged beneath crossing first conductive lines and include a... Agent: Edell, Shapiro & Finnan, LLC

20080121984 - Flash memory structure and method for fabricating the same: A flash memory structure comprises a silicon substrate having at least one concave structure, two doped regions positioned in the semiconductor substrate and at two sides of the concave structure, at least one carrier-trapping region positioned in the concave structure, and a conductive layer positioned above the concave structure. The... Agent: Oliff & Berridge, PLC

20080121985 - Structure and method to improve short channel effects in metal oxide semiconductor field effect transistors: Disclosed are embodiments of improved MOSFET and CMOS structures that provides for increased control over short channel effects. Also disclosed are embodiments of associated methods of forming these structures. The embodiments suppress short channel effects by incorporating buried isolation regions into a transistor below source/drain extension regions and between deep... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080121988 - Circuit configuration and manufacturing processes for vertical transient voltage suppressor (tvs) and emi filter: A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.... Agent: Bo-in Lin

20080121989 - Mos-gated device having a buried gate and process for forming same: An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper... Agent: Hiscock & Barclay, LLP

20080121987 - Nanodot and nanowire based mosfet structures and fabrication processes: Novel nanodot and nanowire based MOSFET device structures and their fabrication processes are invented. These devices can be fabricated with the processes that do not need the extremely high lithographic resolution. The MOSFET devices remain functional even the nanodots and nanowires with varying sizes are randomly distributed. The activated number... Agent: Yijian Chen

20080121986 - Trenched mosfet device configuration with reduced mask processes: A semiconductor power device comprising a termination area that includes a trenched gate runner electrically connected to a trenched gate of said semiconductor power device. The semiconductor power device further includes a trenched field plate disposed in a trench opened in the termination area and the trenched field plate is... Agent: Bo-in Lin

20080121990 - Semiconductor device and manufacture method therefor: A semiconductor device is provided which is suitable for a DRAM with word lines and configured to have a trench gate transistor and suppress an increase in the capacitance of a word line without affecting the transistor characteristics. The semiconductor device includes a trench gate transistor which is provided with:... Agent: Mcginn Intellectual Property Law Group, PLLC

20080121991 - Semiconductor component arrangement and method for producing thereof: A semiconductor component arrangement and method for producing thereof is disclosed. One embodiment provides at least one power semiconductor component integrated in a semiconductor body and at least one logic component integrated in the semiconductor body. The logic component includes a trench extending into the semiconductor body proceeding from a... Agent: Dicke, Billig & Czaja

20080121992 - Semiconductor device including diffusion barrier region and method of fabricating the same: A semiconductor device includes a substrate having an n-type transistor region and a p-type transistor region. The n-type transistor region includes a first gate electrode, first source/drain regions located adjacent to the first gate electrode, a first channel region located between the first source/drain regions, and a first diffusion barrier... Agent: Volentine & Whitt PLLC

20080121993 - Power switching semiconductor devices including rectifying junction-shunts: A semiconductor device includes a drift layer having a first conductivity type and a body region adjacent the drift layer. The body region has a second conductivity type opposite the first conductivity type and forms a p-n junction with the drift layer. The device further includes a contactor region in... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080121994 - Deep junction soi mosfet with enhanced edge body contacts: A semiconductor structure is provided that has body contacts that are located at the edges of the device channel and a buried insulating region under the device channel that is shallower than the buried insulating regions under the source/drain junctions. A method of forming such a semiconductor structure is also... Agent: Scully, Scott, Murphy & Presser, P.C.

20080121995 - Bi-directional mosfet power switch with single metal layer: A bi-directional power switch is formed as a monolithic semiconductor device. The power switch has two MOSFETs formed with separate source contacts to the external package and a common drain. The MOSFETs have first and second channel regions formed over a well region above a substrate. A first source is... Agent: Quarles & Brady LLP

20080121998 - Apparatus and method for selectively recessing spacers on multi-gate devices: Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed.... Agent: Intel Corporation C/o Intellevate, LLC

20080121997 - Multi-gate semiconductor device and method for forming the same: A semiconductor device includes a substrate (20), a source region (58) formed over the substrate, a drain region (62) formed over the substrate, a first gate electrode (36) over the substrate adjacent to the source region and between the source and drain regions, and a second gate electrode (38) over... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080121996 - Transistor with carbon nanotube channel and method of manufacturing the same: A transistor with a carbon nanotube channel and a method of manufacturing the same. At least two gate electrodes are formed on a gate insulating layer formed on a carbon nanotube channel and are insulated from each other. Thus, the minority carrier may be reduced or prevented from flowing into... Agent: Harness, Dickey & Pierce, P.L.C

20080121999 - Semiconductor device which has mos structure and method of manufacturing the same: In the semiconductor device which has a MOS structure concerning the present invention, a PMOS transistor has the structure in which the gate insulating film, first metal layer, second metal layer, and polysilicon layer was formed in the order concerned. An NMOS transistor has the structure by which a gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080122001 - Integrated circuit having doped semiconductor body and method: An integrated circuit and method for making an integrated circuit including doping a semiconductor body is disclosed. One embodiment provides defect-correlated donors and/or acceptors. The defects required for this are produced by electron irradiation of the semiconductor body. Form defect-correlated donors and/or acceptors with elements or element compounds are introduced... Agent: Dicke, Billig & Czaja

20080122000 - Strained semiconductor device and method of making same: A method of making a semiconductor device is disclosed. A semiconductor body, an STI region, a gate and a silicided source/drain region are provided. The STI area is etched, and a liner is formed at the upper surface.... Agent: Slater & Matsil LLP

20080122005 - Ion implantation device and a method of semiconductor manufacturing by the implantation of molecular ions containing phosphorus and arsenic: An ion implantation device and a method of manufacturing a semiconductor device is described, wherein ionized phosphorus-containing molecular clusters are implanted to form N-type transistor structures. For example, in the fabrication of Complementary Metal-Oxide Semiconductor (CMOS) devices, the clusters are implanted to provide N-type doping for Source and Drain structures... Agent: Patent Administrator Katten Muchin Rosenman LLP

20080122003 - Non-conformal stress liner for enhanced mosfet performance: A semiconductor device is provided wherein at least one offset spacer is reduced and a non-conformal stress liner is thereafter deposited. By depositing the non-conformal stress liner in accordance with the present invention in close stress proximity to the FET, the carrier mobility and the performance of said device is... Agent: Scully, Scott, Murphy & Presser, P.C.

20080122004 - Semiconductor device and method of fabricating the same: A semiconductor device and a fabricating method thereof are provided. The semiconductor device can include a first chip having transistors of only the NMOS type, a second chip having transistors of only the PMOS type, and an interconnection electrically connecting the first and second chips to each other. By forming... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080122002 - Stress enhanced cmos circuits and methods for their fabrication: A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS transistor in a channel width direction, the PMOS transistor and the NMOS transistor separated by an isolation region. A compressive... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080122006 - Modular bipolar-cmos-dmos analog integrated circuit and power transistor technology: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of... Agent: Patentability Associates

20080122007 - Semiconductor device and fabrication process thereof: A semiconductor device includes a first polycrystalline semiconductor gate electrode structure formed in a first device region of a substrate via a gate insulation film and having a stacked structure in which a lower polycrystalline semiconductor layer and an upper polycrystalline semiconductor layer are stacked consecutively, the first polycrystalline gate... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080122009 - Dummy active area implementation: Areas of a semiconductor substrate where semiconductor devices are not to be formed are filled in with dummy active areas. Whole dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, and partial dummy active areas are formed in areas of... Agent: Texas Instruments Incorporated

20080122008 - Memory cell: A memory cell includes diffusion regions formed in a substrate. Each of the diffusion regions extends along a vertical direction in a layout view at a substrate level. A first gate electrode structure at a gate electrode level is generally dogleg shaped. The first gate electrode structure extends in an... Agent: Slater & Matsil LLP

20080122010 - Transistor having source/drain region only under sidewall spacer except for contacts and method: A transistor and related method are disclosed. The transistor may include a gate, a sidewall spacer formed along the gate, and a source/drain region positioned only under the sidewall spacer except for a portion at which a contact is positioned. The transistor may be ultra-low power and sub-threshold voltage or... Agent: Hoffman, Warnick & D'alessandro LLC

20080122011 - Variable width offset spacers for mixed signal and system on chip devices: MOSFET gate structures comprising multiple width offset spacers are provided. A first and a second gate structure are formed on a semiconductor substrate. A pair of first offset spacers are formed adjacent either side of the first gate structure. Each of the first offset spacers comprises a first silicon oxide... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080122012 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device, includes forming a gate insulating film on a semiconductor substrate; forming a polycrystalline silicon film on the gate insulating film; forming a silicon nitride film on the polycrystalline silicon film; anisotropically etching the silicon nitride film, the polycrystalline silicon film, the gate insulating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080122014 - Semiconductor device: In a semiconductor device, such as a MOSFET or the like, which is a high-frequency LSI achieving a low noise figure and a high maximum oscillation frequency and which has unit cells with a ring-shaped gate electrode arranged in an array, gate drawing wires connecting together the gate electrode and... Agent: Mcdermott Will & Emery LLP

20080122013 - Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure: Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080122015 - Modulated-vt transistor: A semiconductor field effect transistor can be used with RF signals in an amplifier circuit. The transistor includes a source region and a drain region with a channel region interposed in between the source and drain regions. The transistor is structured such that the threshold voltage for current flow through... Agent: Slater & Matsil LLP

20080122016 - Semiconductor device and fabricating method thereof: A semiconductor device includes: a semiconductor substrate including source/drain regions and a channel between the source/drain regions; a gate oxide layer pattern on the channel; a metal nitride layer pattern on the gate oxide layer pattern; a silicide on the metal nitride layer pattern; and a spacer on a side... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080122017 - Semiconductor device and fabricating method thereof: A semiconductor device, such as a positive channel metal-oxide semiconductor (PMOS) transistor, and a fabricating method thereof are provided. The semiconductor device includes: a gate insulation layer and a gate electrode, a semiconductor substrate, a spacer formed on side walls of the gate insulation layer and the gate electrode, a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080122018 - work function adjustment on fully silicided (fusi) gate: A fully silicided gate with a selectable work function includes; a gate dielectric over the substrate; and a first metal silicide layer over the gate dielectric, and a second metal silicide layer wherein the first metal silicide has a different phase then the second metal silicide layer. The metal silicide... Agent: Duane Morris LLPIPDepartment (tsmc)

20080122019 - Semiconductor device and method of manufacturing the same: Disclosed is a method of manufacturing a semiconductor device. The method comprises consecutively depositing and patterning polysilicon and mask material on a substrate to form a polysilicon layer and a mask layer, reducing a width of the polysilicon layer, depositing and etching insulating material on the substrate to form a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080122020 - Microelectromechanical devices and fabrication methods: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging. An embodiment further includes location of a piezoelectric material as... Agent: Courtney Staniford & Gregory LLP

20080122021 - Image sensor: Embodiments relate to an image sensor and a method of manufacturing the same. In embodiments, an image sensor may include a photodiode structure having a plurality of pixels, aligned on a semiconductor substrate, an inorganic micro-lens group including an inorganic substance, aligned at positions corresponding to a first pixel group... Agent: Sherr & Nourse, PLLC

20080122022 - Solid state imaging device and method of manufacturing the same: A solid state imaging device comprises: a photoelectric converting portion; a charge transferring portion including a charge transfer electrode for transferring an electric charge generated in the photoelectric converting portion; and a shielding film formed through an insulating film containing nitrogen on the charge transferring portion, wherein the insulating film... Agent: Birch Stewart Kolasch & Birch

20080122023 - Method of manufacturing cmos image sensor: An image sensor and a method of manufacturing a CMOS image sensor in which a high-temperature annealing is conducted without causing cracking in a passivation layer. The method may include forming a first passivation insulating layer on and/or over a semiconductor substrate including a metal pad and a plurality of... Agent: Sherr & Nourse, PLLC

20080122024 - Semiconductor substrate, semiconductor device, method for manufacturing semiconductor substrate and method for manufacturing semiconductor device: A semiconductor substrate comprising a semiconductor base, a dielectric layer formed in at least a part of an area on the semiconductor base, and a single crystal semiconductor layers having mutually different film thicknesses, disposed on the dielectric layer and formed by epitaxial growth.... Agent: Edwards Angell Palmer & Dodge LLP

20080122025 - Electronic device including a conductive structure extending through a buried insulating layer: An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting... Agent: Larson Newman Abel Polansky & White, LLP

20080122027 - Semiconductor device and method of cutting electrical fuse: A semiconductor device includes a semiconductor substrate, and an electrical fuse including a first conductor including a first cutting target region, and a second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on the semiconductor substrate,... Agent: Young & Thompson

20080122026 - Structure for creation of a programmable device: The invention is directed to an improved eFUSE that prevent rupturing of the fuse link, reduces current through the fuse link, and optimizes electromigration through the fuse link through the use of a feedback circuit.... Agent: International Business Machines Corporation Dept. 18g

20080122028 - Inductor formed on a semiconductor substrate and method for forming the same: An inductor formed on a semiconductor substrate is provided in the present invention. The inductor comprises a metal layer and an insulator layer. The metal layer constitutes the coil of the inductor. The insulator layer comprises at least one insulator slot, and each insulator slot is encompassed in the metal... Agent: Jianq Chyun Intellectual Property Office

20080122029 - Inductor utilizing pad metal layer: An inductor utilizing a pad metal layer. The inductor comprises a metal spiral, a metal bridge, and a metal interconnect. The metal bridge is formed with the pad metal layer and a plurality of vias and has one end connected to the metal spiral. The metal interconnect is connected to... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080122030 - Methods for enhancing trench capacitance and trench capacitor: Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form... Agent: Hoffman, Warnick & D'alessandro LLC

20080122033 - Semiconductor device and manufacturing the same: In a semiconductor device and a method of manufacturing the semiconductor device, an electric element is formed. A first insulation interlayer is formed on the electric element. A capacitor structure is formed on the first insulation interlayer. The capacitor structure vertically disposed relative to the electric element. The capacitor structure... Agent: Mills & Onello LLP

20080122032 - Semiconductor devices with mim-type decoupling capacitors and fabrication method thereof: A semiconductor device. The semiconductor device includes a substrate having an array region and a decoupling region, a first dielectric layer overlying the substrate, a second dielectric layer overlying the first dielectric layer, a plurality of active components formed in the first dielectric layer within the array region, a first... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080122031 - Vertical electrical device: A vertical electrical device includes a region in a substrate extending from a surface of the substrate, the region having an inner wall and an outer wall circumscribing the inner wall. An inner electrically conductive layer is disposed on the inner wall and an outer electrically conductive layer is disposed... Agent: Koppel, Patrick & Heybl

20080122034 - Multiple function thin-film resistor-capacitor array: A multiple function thin-film resistor-capacitor array is used for an optical fiber receiving module. A dielectric thin film with desired pattern and thickness is form on surface of a silicon substrate by semiconductor manufacture process. Resistors of different resistances and capacitors of different capacitances or the combination thereof, and circuit... Agent: Hdsl

20080122035 - Semiconductor device: A semiconductor device is provided that includes: a base insulating film; a metal thin-film resistor that is provided on the base insulating film; a lower-layer insulating film that is formed under the base insulating film; and a wiring pattern that is formed on the lower-layer insulating film. In this semiconductor... Agent: Dickstein Shapiro LLP

20080122036 - Reverse-biased pn diode decoupling capacitor: This invention discloses a decoupling capacitor in an integrated circuit, comprising a plurality of dedicated PN diodes with a total junction area greater than one tenth of a total active area of functional devices for which the dedicated PN diodes are intended to protect, a N-type region of the dedicated... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080122037 - Prevention of backside cracks in semiconductor chips or wafers using backside film or backside wet etch: A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and... Agent: Scully Scott Murphy & Presser, PC

20080122038 - Guard ring structure with metallic materials: A semiconductor device and a method for making the semiconductor device having a guard ring formed by a trench filled with a metallic material is described. Using the trench, crack and moisture propagation may be eliminated or prevented from propagating from a dicing area to an active circuit area of... Agent: Banner & Witcoff, Ltd.

20080122039 - Intergrated circuit device, chip, and method of fabricating the same: A method of manufacturing an integrated circuit (IC) chip is provided. The method includes the following steps. First, a substrate is provided. The substrate is divided into an internal region and an external region by a die seal ring region. A plurality of circuit units is then formed in the... Agent: Jianq Chyun Intellectual Property Office

20080122041 - Semiconductor device and method for producing such a device: A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end... Agent: Dicke, Billig & Czaja

20080122040 - Varying pitch adapter and a method of forming a varying pitch adapter: A varying pitch adapter that converts a first pitch to a second pitch. The adapter comprises a substrate, a plurality of first conductive vias, at least one second conductive via, a first dielectric layer and a second dielectric layer. The substrate has a first main surface and a second main... Agent: Panitch Schwarze Belisario & Nadel LLP

20080122042 - Applications of polycrystalline wafers: A wafer comprising polycrystalline silicon is used in various applications, including as a handling wafer, a test wafer, a dummy wafer, or as a substrate in a bonded die. Use of polycrystalline material instead of single-crystal may lower expenses.... Agent: Intel Corporation C/o Intellevate, LLC

20080122043 - Layered semiconductor wafer with low warp and bow, and process for producing it: Semiconductor wafers with a diameter of at least 200 mm comprise a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, the semiconductor wafer having been produced by means of a layer transfer process comprising at least one RTA step, wherein the semiconductor wafer has a... Agent: Brooks Kushman P.C.

20080122044 - Method manufacturing capacitor dielectric: A method of forming a dielectric layer in a capacitor adapted for use in a semiconductor device is disclosed. The method includes forming a first ZrO2 layer, forming an interfacial layer using a plasma treatment on the first ZrO2 layer, and forming a second ZrO2 layer on the interfacial layer.... Agent: Volentine & Whitt PLLC

20080122045 - Dual liner capping layer interconnect structure: A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer... Agent: International Business Machines Corporation Dept. 18g

20080122046 - Semiconductor device manufacturing method, wafer, and wafer manufacturing method: A semiconductor device manufacturing method capable of making in-plane temperature distribution on a wafer uniform at heat treatment time. Before heat treatment is performed by irradiating the wafer with lamp light from the side of a device formed area where semiconductor devices are to be formed, an SiN film with... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080122047 - Collective and synergistic mram shields: Various structures chip packages are disclosed including a magnetoresistive random access memory (“MRAM”) device and a magnetic shield structure. The magnetic shield structure may be made from material having either ferromagnetic or diamagnetic material and may be shaped and incorporated into the chip package to divert stray magnetic fields away... Agent: Tessera Lerner David Et Al.

20080122048 - Stamped leadframe and method of manufacture thereof: A stamped leadframe for a leadless package and a method of manufacturing the same are provided wherein the leadframe has at least a die pad, a frame, tie bars connecting the die pad to the frame and a plurality of leads. Each lead comprises a first portion and a second... Agent: Ostrolenk Faber Gerb & Soffen

20080122049 - Leadframe finger design to ensure lead-locking for enhanced fatigue life of bonding wire in an overmolded package: In a method and system for fabricating a semiconductor device (200, 300 or 400), a portion of a metal sheet to form a leadframe (210, 310 or 410) having a lead finger (220, 320 or 430) is removed to form a lead finger lock (260, 360 or 460). The lead... Agent: Texas Instruments Incorporated

20080122050 - Semiconductor device and production method for semiconductor device: A power semiconductor device in which a semiconductor element is die-mount-connected onto a lead frame in a Pb-free manner. In a die-mount-connection with a large difference of thermal expansion coefficient between a semiconductor element 1 and a lead frame 2, the connection is made with an intermetallic compound 200 having... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080122053 - Integrated circuit package and a method for forming an integrated circuit package: A method of forming an integrated circuit package, such as a Flip Chip package, in which a void is provided in the underfill material in the central region of the package between the chip or die and the substrate on which the chip or die is mounted. This reduces delamination... Agent: Slater & Matsil LLP

20080122052 - Member for semiconductor device and production method thereof: A member for a semiconductor device of low price, capable of forming a high quality plating layer on a surface, having heat conductivity at high temperature (100° C.) of more than or equal to 180 W/m·K and toughness that will not cause breaking due to screwing, and will not cause... Agent: Mcdermott Will & Emery LLP

20080122051 - Module comprising polymer-containing electrical connecting element: The invention relates to a module having a carrier element with electrical contact elements and a component applied to the carrier element with electrical connections on the side remote from the carrier element. The electrical connections of the component are electrically connected to contact elements of the carrier element via... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080122054 - Circuit module having force resistant construction: Impact resistant circuit modules are disclosed for enclosing a die having a sensor area. Preferred modules include a flexible circuit and a die coupled thereto. The flexible circuit is preferably folded over compressible material to help absorb applied forces. A gap may be provided between sides of the die and... Agent: Fish & Richardson P.C.

20080122055 - Method and system for fabricating semiconductor components with lens structures and lens support structures: A method for fabricating semiconductor components with lens structures and lens support structures includes the steps of providing semiconductor substrates on a substrate, attaching a carrier to the substrate configured to support the substrate during various processes, thinning the carrier to form lens support structures having desired geometrical characteristics, singulating... Agent: Stephen A Gratton The Law Office Of Steve Gratton

20080122056 - Semiconductor device package: Provided is a semiconductor device package comprising a printed circuit board, the printed circuit board including a window at a central portion and a connection part, a semiconductor chip including center-type bonding pads, wherein the semiconductor chip is mounted on an upper surface of the printed circuit board such that... Agent: Mills & Onello LLP

20080122057 - Silicon carrier having increased flexibility: An apparatus and method providing flexibility to a silicon chip carrier which, in at least one embodiment, comprises multiple chips and a silicon chip carrier having thinned regions between some adjacent chips, thus, allowing for increased flexibility and reduced package warpage.... Agent: Ference & Associates LLC

20080122058 - Partially stacked semiconductor devices: Embodiments of the present invention provide partially stacked semiconductor devices and methods of making the same. In one embodiment, a first LSI chip is strategically buried or embedded in a second LSI chip. One embodiment of a method of making a partially stacked semiconductor device may comprise digging a trench... Agent: SprinkleIPLaw Group

20080122059 - Stacked chip package structure and fabricating method thereof: A stacked chip package structure including a carrier, a first chip, a second chip, a barrier layer, and a metal piece is provided. The carrier has an upper surface and a corresponding lower surface. The first chip is disposed on the upper surface of the carrier, and electrically connected to... Agent: J C Patents, Inc.

20080122061 - Semiconductor chip embedded in an insulator and having two-way heat extraction: A semiconductor chip (101) embedded in an insulating layer (102) of a sheet-like substrate (110), made of alternating layers of thermally insulating and conductive materials, has the heat flowing from the active chip surface through metal bumps (111, etc.) to a first metal layer (144) positioned in proximity, and from... Agent: Texas Instruments Incorporated

20080122060 - Semiconductor device including corrosion resistant wiring structure: A semiconductor device packaged in a non-hermetic package includes a semiconductor substrate; a wiring metal film on the semiconductor substrate; a plating power supply film on the wiring metal film; an Au plated portion on the plating power supply film; a metal film covering the Au plated portion; and an... Agent: Leydig Voit & Mayer, Ltd

20080122062 - Wafer level package configured to compensate size difference in different types of packages: A wafer level package including a semiconductor chip having a plurality of bonding pads on a front surface thereof; a lower insulation layer formed on the semiconductor chip to expose the bonding pads; re-distribution lines formed on the lower insulation layer to be connected to the bonding pads at first... Agent: Ladas & Parry LLP

20080122063 - Semiconductor device: A conventional semiconductor device has a problem that power-conversion energy efficiency in a DC-DC converter circuit is influenced by MOSFET characteristics. In a semiconductor device of the present invention, three MOSFET elements are fixed onto a die pad. Moreover, source electrodes of the MOSFET elements are commonly connected to one... Agent: Morrison & Foerster LLP

20080122064 - Semiconductor device: An aspect of the semiconductor device comprising a package substrate which has a plurality of pads to which a power supply voltage is applied on an upper surface thereof, a first memory chip which is arranged on the package substrate and has a first power supply pad provided on a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080122065 - Integrated circuit package system with pedestal structure: An integrated circuit package system includes providing a substrate having a bond finger thereon and forming a pedestal on a portion of the bond finger. A first die is mounted on the substrate and adjacent to the bond finger. A portion of the first die, a portion of the bond... Agent: Law Offices Of Mikio Ishimaru

20080122066 - Semiconductor device: A semiconductor device having a CSP packaging structure, which exhibits a reduced thermal stress exerted on a semiconductor chip without deteriorating electrical characteristics, is provided. A semiconductor device comprises an electroconductive cap, functioning as an external coupling terminal and including a metallic member and a composite material; and a semiconductor... Agent: Mcginn Intellectual Property Law Group, PLLC

20080122067 - Heat spreader for an electrical device: A heat spreader for electrical device is disclosed, a portion of said heat spreader is above and corresponding to a chip which is coupled with a base of electrical device. An embodiment for the heat spreader comprised of: a first portion, second portion, connecting portion, supporting portion and a side... Agent: Chung-cheng Wang

20080122069 - Heat sink: The first cavity and the second cavity not only position tightly the heat sink onto the chip module but also conduct heat efficiently from the chip module to the heat sink and to protect electronic elements disposed on the chip module. The heat-dissipating efficiency of the heat sink is increased,... Agent: Rosenberg, Klein & Lee

20080122068 - Thermally enhanced semiconductor package: A semiconductor package has a substrate having a first surface, a second surface, and a through hole opening. A heat spreader has a first surface, a second surface, and a plurality of notches formed on the second surface. A semiconductor die is coupled to the first surface of the heat... Agent: Weiss & Moy PC

20080122070 - Heat dissipating semiconductor package and fabrication method therefor: A heat dissipating semiconductor package and a fabrication method therefor are provided. The fabrication method for the heat dissipating semiconductor package mainly includes steps of: containing a substrate having a chip mounted thereon in an aperture of a carrier; mounting a heat dissipating sheet having supporting portions on the carrier... Agent: Edwards Angell Palmer & Dodge LLP

20080122071 - Heat dissipating semiconductor package and fabrication method therefor: A heat dissipating semiconductor package and the fabrication method therefor are provided. The fabrication method for the heat dissipating semiconductor package mainly includes steps of: containing a substrate having a chip mounted thereon in an aperture of a carrier, wherein the carrier has an electroconductive layer; allowing a heat dissipating... Agent: Edwards Angell Palmer & Dodge LLP

20080122072 - Balanced semiconductor device packages including lead frame with floating leads and associated methods: A semiconductor device assembly or package includes at least one semiconductor device that is positioned adjacent to floating leads. Such an assembly or package may include at least two semiconductor devices that face opposite directions from one another, with each being oriented such that bond pads thereof are at an... Agent: Trask Britt

20080122073 - Mems module package: A MEMS module package includes a substrate, a cap capped on the substrate and defining with the substrate an accommodation chamber, a micro-electromechanical chip mounted on the substrate within the accommodation chamber, a plurality of passive components mounted on the substrate within the accommodation chamber and electrically connected to the... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080122074 - Multi-chip electronic circuit module and a method of manufacturing: An integrated circuit module has a substrate with an exposed surface. An integrated circuit die has a first surface and a second surface opposite the first surface, and has a plurality of bonding pads on the second surface. The integrated circuit die is positioned with its first surface on the... Agent: Dla Piper US LLP

20080122075 - Semiconductor module with at least two substrates: A semiconductor module includes a module package including a first substrate having a first semiconductor device and a second substrate having a second semiconductor device. A first outer conductor extends from the module package and is connected to the first substrate and a second outer conductor extends from the module... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080122076 - Conductive wiring for semiconductor devices: A conductive wiring for a semiconductor device is provided including a semiconductor substrate and a plurality of lower conductive structures on the semiconductor substrate. An insulating layer is provided that electrically insulates the plurality of lower conductive structures from one another. A first insulation interlayer pattern is provided on the... Agent: Myers Bigel Sibley & Sajovec

20080122077 - Chip and manufacturing method and application thereof: The present invention provides a chip and its manufacturing methods and applications. Regarding the chip, there are several solder bumps on the backside of the chip. The difference of the invented chip from the convention chips is that the solder bumps are embedded in an insulting layer and a thermal-plastic... Agent: J C Patents, Inc.

20080122084 - Flip-chip assembly and method of manufacturing the same: A flip-chip assembly comprises a semiconductor chip, a substrate, a first buffer layer, a second buffer layer and a conductive bump. The semiconductor chip includes a first region and a second region adjacent to the first region. The substrate is disposed under the semiconductor chip. The first buffer layer is... Agent: Marger Johnson & Mccollom, P.C.

20080122081 - Method of fabricating electronic device having sacrificial anode, and electronic device fabricated by the same: According to an example embodiment, a method of fabricating an electronic device may include preparing a substrate with a first area and a second area. A metal interconnection may be formed on the substrate extending from the first area to the second area. An insulating layer may be formed on... Agent: Harness, Dickey & Pierce, P.L.C

20080122079 - Package substrate and manufacturing method thereof: The package substrate of the present invention comprises a carrying board, bump pads, wire bonding pads, a solder mask, metallic bumps, and a metallic protective layer. The solder pads and the wire bonding pads are disposed on the surface of the carrying board. The solder mask is patterned to expose... Agent: Lowe Hauptman Ham & Berner, LLP

20080122085 - Semiconductor device and a method of manufacturing the same: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in... Agent: Miles & Stockbridge PC

20080122082 - Semiconductor device and semiconductor package containing the same: According to the present invention, a semiconductor device, having an electrode pad as a part of wirings on the uppermost layer thereof, includes a passivation film and a bump electrode for external connection. The passivation film is formed on the electrode pad, and the bump electrode is formed on the... Agent: Volentine & Whitt PLLC

20080122080 - Semiconductor die with reduced bump-to-pad ratio: According to one exemplary embodiment, a semiconductor die includes at least one pad ring situated on an active surface of the semiconductor die, where the at least one pad ring includes a number of pads. The semiconductor die further includes a number of bumps including at least one shared bump.... Agent: Farjami & Farjami LLP

20080122083 - Semiconductor module and method of manufacturing the same: A semiconductor module preferably includes a semiconductor package and a printed circuit board (PCB). The semiconductor package can include an outer terminal. The PCB can include a terminal land that is electrically connected to the outer terminal. The PCB preferably has a recess configured to at least partially expose the... Agent: Marger Johnson & Mccollom, P.C.

20080122078 - Systems and methods to passivate on-die redistribution interconnects: An integrated circuit apparatus comprises a semiconductor substrate having a plurality of devices formed thereon, one or more metallization layers to interconnect the plurality of devices, and a bond pad formed over the one or more metallization layers and electrically coupled to at least one of the metallization layers. A... Agent: Intel Corporation C/o Intellevate, LLC

20080122087 - Semiconductor device with no base member and method of manufacturing the same: A semiconductor device includes a semiconductor component which has a semiconductor substrate provided with an integrated circuit on an under side of the semiconductor substrate and a plurality of external connection electrodes provided on the underside of the semiconductor substrate, and a plurality of interconnections each of which includes one... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080122086 - Solder bump structure and method of manufacturing same: Solder bump structures for semiconductor device packaging is provided. In one embodiment, a semiconductor device comprises a substrate having a bond pad and a first passivation layer formed thereabove, the first passivation layer having an opening therein exposing a portion of the bond pad. A metal pad layer is formed... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080122088 - Electronic packaging materials for use with low-k dielectric-containing semiconductor devices: Electronic packaging materials for use with Low-k dielectric-containing semiconductor devices are provided.... Agent: Loctite Corporation

20080122089 - Interconnect structure with line resistance dispersion: A semiconductor device is provided. The semiconductor device includes a region of closely packed lines and a region including an isolated line, separated by a region of carbon doped silicon oxide. As the surface of the semiconductor device is etched, the etching rate varies depending on the material being etched.... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20080122090 - Interconnect structures with liner repair layers and methods for forming such interconnection structures: Interconnect structures that include a conformal liner repair layer bridging breaches in a liner formed on roughened dielectric material in an insulating layer and methods of forming such interconnect structures. The conformal liner repair layer is formed of a conductive material, such as a cobalt-containing material. The conformal liner repair... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080122091 - Semiconductor device and method for producing a semiconductor device: A semiconductor device exhibits a first metal layer, made of a first metal, with at least one contiguous subsection. At least one second metal layer, made of a second metal, is placed on the contiguous subsection of the first metal layer. The second metal is harder than the first metal.... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20080122094 - Method of manufacturing semiconductor device and semiconductor device: In a method of manufacturing a semiconductor device according to the present invention, a wiring trench is formed on the surface of an insulating film, and the inner surface of this wiring trench is thereafter coated with an alloy film made of an alloy material containing copper and a prescribed... Agent: Rabin & Berdo, PC

20080122093 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device can include a lower metal wiring formed over a semiconductor substrate. A first metal barrier layer can be formed over the lower metal wiring and an interlayer insulating layer formed over the first metal barrier... Agent: Sherr & Nourse, PLLC

20080122092 - Semiconductor device and method of manufacturing the same: A semiconductor device and a fabricating method thereof are provided. An interlayer dielectric layer on a semiconductor substrate can have a via hole and can also have a trench over the via hole. A barrier layer can be provided on the interlayer dielectric layer having the via hole, a metal... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080122097 - Method of forming metal wiring in semiconductor device: A method for forming a metal wiring of a semiconductor device capable of efficiently preventing a hillock phenomenon occurred in a subsequent annealing process of a metal wiring process. The method for forming a metal wiring of a semiconductor device includes forming an Al growth stop film on the upper... Agent: Sherr & Nourse, PLLC

20080122096 - Methods for lateral current carrying capability improvement in semiconductor devices: A semiconductor structure and methods for forming the same. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically... Agent: Schmeiser, Olsen & Watts

20080122099 - Chip structure and process for forming the same: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric... Agent: Mou-shiung Lin

20080122098 - Nonvolatile semiconductor memory and method for fabricating the same: A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080122100 - Novel bond pad design to minimize dielectric cracking: An improved via arrangement for a bonding pad structure is disclosed comprising an array of vias surrounded by a line via. The line via provides a barrier to cracks in the dielectric layer encompassing the via array. Although cracks are able to spread relatively unhindered between the vias of the... Agent: Duane Morris LLPIPDepartment (tsmc)

20080122101 - Manufacturing method of semiconductor device and semiconductor device produced therewith: A method of the invention includes: a step of supplying reactive plasma on a surface of a dielectric thin film in which a plurality of pores are arranged around a skeleton mainly made of a Si—O bond, to perform a pretreatment; a step of forming a conductive film on the... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20080122102 - Semiconductor device having oxidized metal film and manufacture method of the same: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080122103 - Embedded nano uv blocking barrier for improved reliability of copper/ultra low k interlevel dielectric electronic devices: An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films including an Ultra-Violet (UV) blocking... Agent: International Business Machines Corporation Dept. 18g

20080122104 - Damascene interconnect structure having air gaps between metal lines and method for fabricating the same: An exemplary damascene interconnect structure includes a substrate (20), a first dielectric layer (21) on the substrate, a plurality of trenches (27) formed in the first dielectric layer, and a plurality of metal lines (24) filled in the trenches. The first dielectric layer includes multi sub-dielectric layers (211, 212, 213).... Agent: Wei Te Chung Foxconn International, Inc.

20080122106 - Method to generate airgaps with a template first scheme and a self aligned blockout mask: A structure and method to produce an airgap on a substrate having a dielectric layer with a pattern transferred onto the dielectric layer and a self aligned block out mask transferred on the dielectric layer around the pattern.... Agent: Rademaker Nugent & Affleck,llp

20080122107 - Poly silicon hard mask: A method of forming an opening on a low-k dielectric layer using a polysilicon hard mask rather than a metal hard mask as used in prior art. A polysilicon hard mask is formed over a low-k dielectric layer and a photoresist layer is formed over the polysilicon hard mask. The... Agent: Duane Morris LLPIPDepartment (tsmc)

20080122108 - Rotation joint and semiconductor device having the same: Provided are a rotation joint capable of compensating for a mismatch due to thermal expansion and a semiconductor device having the same. The rotation joint can include a support member and a first contact member coupled to a first portion of the support member such that a surface of the... Agent: Marger Johnson & Mccollom, P.C.

20080122105 - Structure for preventing pad peeling and method of fabricating the same: A method of fabricating the structure for preventing the pad peeling is provided. A semiconductor substrate in which an active circuit structure has been formed is provided. Then, a dielectric layer with an opening is formed on the semiconductor substrate. The opening is formed in the dielectric layer above the... Agent: Jianq Chyun Intellectual Property Office

20080122110 - Contact aperture and contact via with stepped sidewall and methods for fabrication thereof: A semiconductor structure includes a semiconductor device including a contact region. The semiconductor structure also includes a passivation layer passivating the semiconductor device including the contact region. A narrow bottomed stepped sidewall contact aperture is located within the passivation layer to expose the contact region. A corresponding narrow bottomed stepped... Agent: Scully, Scott, Murphy & Presser, P.C.

20080122109 - Porous and dense hybrid interconnect structure and method of manufacture: A method for manufacturing a structure includes depositing a dense dielectric over the entire wafer, which includes areas that require low dielectric capacitance and areas that require high mechanical strength. The method further includes masking areas of the dense dielectric over the areas that require high mechanical strength and curing... Agent: Greenblum & Bernstein, P.L.C

20080122111 - Semiconductor device and fabricating method thereof: A semiconductor device and fabricating method thereof for preventing damage to a low-k dielectric by a metal line process. The method can include sequentially forming a first etch stop layer, a first insulating layer and a second etch stop layer over a semiconductor substrate; forming a plurality of first insulating... Agent: Sherr & Nourse, PLLC

20080122112 - Semiconductor device and method for fabricating the same: A semiconductor device has a porous low-dielectric-constant film formed on a substrate and having an opening and a fine particle film composed of a plurality of aggregately deposited fine particles each having a diameter of not less than 1 nm and not more than 2 nm and formed on a... Agent: Mcdermott Will & Emery LLP

20080122114 - Bonding structures and methods of forming bonding structures: A semiconductor structure includes a first substrate and a second substrate bonded over the first substrate. The first substrate includes a passivation layer formed over the first substrate. The passivation layer includes at least one first opening exposing a first bonding pad formed over the first substrate. The second substrate... Agent: Duane Morris LLPIPDepartment (tsmc)

20080122116 - Method of forming metal layer wiring structure on backside of wafer, metal layer wiring structure formed using the method, method of stacking chip package, and chip package stack structure formed using the method: Provided are a method of forming a metal layer wiring structure on the backside of a wafer, a metal layer wiring structure formed using the method, a method of stacking a chip package, and a chip package stack structure formed using the method. The method of stacking a chip package... Agent: Marger Johnson & Mccollom, P.C.

20080122113 - Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device and methods for forming the same: Semiconductor device assemblies and systems that include at least one semiconductor device assembly include two or more semiconductor devices stacked one over another. Conductive pathways that extend around at least one side of at least one of the semiconductor devices provide electrical communication between conductive elements of the semiconductor devices,... Agent: Trask Britt

20080122115 - Three-dimensional wafer stacking with vertical interconnects: Described are three-dimensional stacked semiconductor structures having one or more vertical interconnects. Vertical stacking relies on vertical interconnects and wafer bonding using a patternable polymer. The polymer is preferably lithographically patternable and photosensitive. Curing of the polymer is preselected from about 35% to up to about 100%, depending on a... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20080122117 - Fusible i/o interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps: Methods are disclosed for electrically connecting I/O bond-pads on a chip to corresponding I/O bond-pads on a substrate. In an exemplary method a respective stud-bump is formed on each I/O bond-pad on the substrate. The stud-bumps can be made of a fusible material, or a layer of fusible material can... Agent: Klarquist Sparkman, LLP

20080122118 - Silica nanoparticles thermoset resin compositions: A themosettable material having excellent processability, and which cures to form a thermoset composition having a low coefficient of thermal expansion and a high glass transition temperature includes functionalized nanoscopic silica particles dispersed in a curable resin comprising a polyepoxide having at least three epoxide groups per molecule. The composition... Agent: Delphi Technologies, Inc.

20080122119 - Method and apparatus for creating rfid devices using masking techniques: A method for creating a plurality of semiconductor assemblies that includes the steps of creating a plurality of quasi-wafers, each quasi-wafer comprising a plurality of semiconductor devices; transferring the plurality of semiconductor devices on each quasi-wafers onto a carrier having a functional adhesive; and bonding the plurality of semiconductor devices... Agent: Jeffer, Mangels, Butler & Marmaro, LLP

20080122120 - Electronic component, manufacturing method of the electronic component, electronic component assembly body, and electronic device: An electronic component, includes a main body part inserted in an opening part formed in a board; and a pair of leads each of the leads having an end connected to the main body part and another end connected to a pad formed on the board; wherein the main body... Agent: Staas & Halsey LLP

20080122121 - Semiconductor device having a interlayer insulation film with low dielectric constant and high mechanical strength: The method includes the steps of forming a porous insulation film and wires on the substrate, the wires embedded in the porous insulation film having a portion adjacent to the wires and a remote portion spaced apart from the wires; and applying an energy beam to the remote portion to... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080122122 - Semiconductor package with encapsulant delamination-reducing structure and method of making the package: A semiconductor package and method of making the package uses at least one encapsulant delamination-reducing structure positioned on an upper major surface of a semiconductor chip to provide a structural interface between the semiconductor chip and an encapsulant formed over the semiconductor chip.... Agent: Kathy Manke Avago Technologies Limited

20080122123 - Compact led with a self-formed encapsulating dome: A light source including a die, substrate, and droplet of encapsulating material is disclosed. The die includes a semiconductor light-emitting device that is connected to first and second conducting traces on a first surface of the substrate. The droplet of encapsulant material overlies the die and is formed from a... Agent: Kathy Manke Avago Technologies Limited

20080122125 - Methods to reduce the critical dimension of semiconductor devices and partially fabricated semiconductor devices having reduced critical dimensions: A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed... Agent: Trask Britt, P.C./ Micron Technology

20080122124 - Overlay mark, method for forming the same and application thereof: An overlay mark for checking the alignment accuracy between a lower layer and a lithography process for defining an upper layer is described, including a part of the lower layer having two first x-directional trenches, two first y-directional trenches, two second x-directional trenches and two second y-directional trenches therein, and... Agent: J C Patents, Inc.

20080122126 - Bose-einstein condensate bottling plant: This is a method for creating Bose-Einstein condensates using low-cost technology at room temperature. The method includes a convenient way for separating the condensate into parts that remain entangled and storing the parts in reliable and stable containers that are suitable for easy transportation. The containers have a convenient method... Agent: Itai Aaronson

20080116437 - Phase change memory device and method of forming the same: A phase change memory device includes a current restrictive element interposed between an electrically conductive element and a phase change material. The current restrictive element includes a plurality of overlapping film patterns, each of which having a respective first portion proximal to the conductive element and a second portion proximal... Agent: F. Chau & Associates, Llc

20080116438 - Resistive random access memory having a solid solution layer and method of manufacturing the same: A resistive random access memory (RRAM) having a solid solution layer and a method of manufacturing the RRAM are provided. The RRAM includes a lower electrode, a solid solution layer on the lower electrode, a resistive layer on the solid solution layer, and an upper electrode on the resistive layer.... Agent: Harness, Dickey & Pierce, P.L.C

20080116439 - Forming self-aligned nano-electrodes: A nano-electrode or nano-wire may be etched centrally to form a gap between nano-electrode portions. The portions may ultimately constitute a single electron transistor. The source and drain formed from the electrode portions are self-aligned with one another. Using spacer technology, the gap between the electrodes may be made very... Agent: Trop Pruner & Hu, Pc

20080116441 - Nonvolatile phase change memory cell having a reduced contact area: A nonvolatile memory cell having a contact area between a phase-change material such as a chalcogenide and a heat source which is smaller than photolithographic limits is described. To form this cell, a conductive or semiconductor pillar is exposed at a dielectric surface and recessed by selective etch. A thin,... Agent: Eschweiler & Associates Llc

20080116442 - Phase change memory cell having a sidewall contact: A memory cell includes a first electrode and a second electrode forming an opening. The opening is defined by a first sidewall, a second sidewall, and a surface extending between the first sidewall and the second sidewall. The memory cell includes phase change material contacting the first electrode and the... Agent: Dicke, Billig & Czaja

20080116443 - Phase change memory device with hole for a lower electrode defined in a stable manner and method for manufacturing the same: A phase change memory device is manufactured by forming a first insulation layer on a semiconductor substrate having a plurality of phase change cell forming regions; defining a groove by etching the first insulation layer; forming a lower electrode in the groove; recessing the lower electrode; forming a second insulation... Agent: Ladas & Parry LLP

20080116440 - Resistance random access memory structure for enhanced retention: A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080116445 - Phase change memory device in which a phase change layer is stably formed and prevented from lifting and method for manufacturing the same: A phase change memory device includes a semiconductor substrate having a plurality of phase change cell regions; a lower electrode formed in each of the phase change cell regions on the semiconductor substrate; an insulation layer formed on the semiconductor substrate to cover the lower electrode and defined with a... Agent: Ladas & Parry LLP

20080116446 - Electron emission element and electron emission element fabrication method: An electron emitting device 2 comprises an electron emitting portion 6 made of diamond. At an electron emission current value of 10 μA or more, a deviation of the electron emission current value over one hour is within ±20% in the electron emitting device 2. The number of occurrence of... Agent: Mcdermott Will & Emery LLP

20080116447 - Non-volatile memory transistor with quantum well charge trap: Quantum well charge trap transistors are disclosed featuring an ion implanted region below a stack of high-low-high bandgap materials arranged in a sandwich structure. Source and drain electrodes on either side of implanted region, as well as a control gate above the stack allow for electrical control. The implanted region,... Agent: Schneck & Schneck

20080116448 - Protected qubit based on superconducting current mirror: A qubit implementation based on exciton condensation in capacitively coupled Josephson junction chains is disclosed. The qubit may be protected in the sense that unwanted terms in its effective Hamiltonian may be exponentially suppressed as the chain length increases. Also disclosed is an implementation of a universal set of quantum... Agent: Woodcock Washburn LLP (microsoft Corporation)

20080116449 - Processing relational database problems using analog processors: Systems, methods and articles solve queries or database problems through the use of graphs. An association graph may be formed based on a query graph and a database graph. The association graph may be solved for a clique, providing the results to a query or problem and/or an indication of... Agent: Seed Intellectual Property Law Group Pllc

20080116452 - Aromatic enediyne derivative, organic semiconductor thin film, electronic device and methods of manufacturing the same: Disclosed are a novel aromatic enediyne derivative, an organic semiconductor thin film using the same, and an electronic device. Example embodiments pertain to an aromatic enediyne derivative which enables the formation of a chemically and electrically stable and reliable semiconductor thin film using a solution process, e.g., spin coating and/or... Agent: Harness, Dickey & Pierce, P.L.C

20080116450 - Mobility engineered electroluminescent devices: An electroluminescent (EL) device, including a semiconductor structure, a first electrode, and a second electrode. The semiconductor structure includes: a first higher mobility semiconductor layer having a first mobility; a second higher mobility semiconductor layer having a second mobility; and a lower mobility semiconductor layer formed between the first higher... Agent: Ratnerprestia

20080116451 - Molecular electronic device including electrode having conductive polymer electrode layer: Provided is a molecular electronic device including an electrode including a conductive polymer electrode layer. The molecular electronic device includes a first electrode; a functional molecular active layer, self-assembled on the first electrode, including an electroactive functional group having a cyclic compound; and a second electrode disposed on the functional... Agent: Rabin & Berdo, Pc

20080116453 - Transition metal complex and light-emitting device: o

20080116454 - Photodiode having hetero-junction between semi-insulating zinc oxide semiconductor thin film and silicon: A photodiode which eliminates sensitivity reduction in a short wavelength region such as blue, an unavoidable problem posed by doping, resolves response reduction by the scattering of acceptor ions or impurities due to doping of impurities at the same time, and has very high sensitivity and fast response in a... Agent: Rader Fishman & Grauer Pllc

20080116455 - Technique for aging induced performance drift compensation in an integrated circuit: An improved compensation circuit that compensates for lifetime performance drifts due to aging of integrated circuits to improve the circuit performance. In one example embodiment, this is achieved by applying a body bias voltage VBB to the integrated circuit to compensate for the lifetime performance drift due to hot carrier... Agent: Texas Instruments Incorporated

20080116457 - Driving device for unit pixel of organic light emitting display and method of manufacturing the same: Provided are a driving device for a unit pixel of an organic light emitting display having an improved structure and a method of manufacturing the same.... Agent: Cantor Colburn, LLP

20080116458 - El display device, driving method thereof, and electronic equipment provided with the el display device: An EL display device capable of performing clear multi-gradation color display and electronic equipment provided with the EL display device are provided, wherein gradation display is performed according to a time-division driving method in which the luminescence and non-luminescence of an EL element (109) disposed in a pixel (104) are... Agent: Eric Robinson

20080116459 - Thin film transistor array substrate and method for fabricating same: An exemplary TFT array substrate (20) includes: an insulating substrate (201); a common electrode (220), a common line (224), a gate line (23), and a gate electrode (281) arranged on the insulating substrate; a gate insulating layer (204) covering the common electrode, the common line, the gate line, and the... Agent: Wei Te Chung Foxconn International, Inc.

20080116460 - Non-volatile memory device and fabrication method of non-volatile memory device and memory apparatus including non-volatile memory device: A non-volatile memory device is capable of reducing an excessive leakage current due to a rough surface of a polysilicon and realizing improved blocking function with an oxide film that is thinner by forming a first oxide film and a second oxide film including a silicon oxy-nitride (SiOxNy) layer using... Agent: Stein, Mcewen & Bui, LLP

20080116461 - Semiconductor device and manufacturing method thereof: A manufacturing method of a semiconductor device, includes the following steps: providing a substrate with an insulated surface; forming an amorphous silicon layer on the insulated surface; imposing a catalytic metal element on the amorphous silicon layer; heating and catalyzing the amorphous silicon layer to form a poly-silicon layer; forming... Agent: Birch Stewart Kolasch & Birch

20080116463 - Light-emitting apparatus and production method thereof: Provided is a light-emitting apparatus which can prevent a shadow mask from contacting a light-emitting medium to suppress damage of the medium, by using a conductive layer formed on a device isolation layer as a pressing member for the shadow mask, and can attain more secure conduction between a second... Agent: Fitzpatrick Cella Harper & Scinto

20080116462 - Semiconductor device: An output side of a driver output circuit of an LCD driver includes a first protective element having an n-type semiconductor region and a p-type semiconductor region formed in the n-type semiconductor region, and a second protective element having a p-type semiconductor region and an n-type semiconductor region formed in... Agent: Miles & Stockbridge Pc

20080116465 - Light emitting transistor: Provided is a light emitting transistor comprising a first conductivity-type collector layer formed on a substrate; a second conductivity-type base layer formed on the collector layer; and a first conductivity-type emitter layer formed on the base layer. At least one of the collector layer, the base layer, and the emitter... Agent: Mcdermott Will & Emery LLP

20080116466 - High-powered diode holder and a package thereof: A high-powered diode holder and a package thereof are disclosed. The high-powered diode holder includes a base and a plurality of metal electrodes. The base is made of ceramic. In the interior part of one end of the base, there is a functional area that is indented inwards. In the... Agent: Rosenberg, Klein & Lee

20080116468 - Led backlight using discrete rgb phosphors: An LED backlight apparatus includes a plurality of radiation emitting diodes, each diode emits radiation having a peak wavelength of about less than 430 nm. Each diode is located on a back surface of a housing. The housing may have an opening. A screen covers the opening and the screen... Agent: Fay Sharpe LLP

20080116467 - Light emitting device including luminescent ceramic and light-scattering material: A ceramic body comprising a wavelength converting material is disposed in the path of light emitted by the light emitting region of a semiconductor structure comprising a light emitting region disposed between an n-type region and a p-type region. A layer of transparent material is also disposed in the path... Agent: Patent Law Group LLP

20080116469 - Liquid crystal display panel and manufacture method thereof: A liquid crystal display (LCD) panel, including a first substrate, a second substrate, a liquid crystal layer, a patterned sealant, several first stop structures, several second stop structures and several seal spacers, is provided. The first substrate is opposite to the second substrate. The liquid crystal layer and the patterned... Agent: J C Patents, Inc.

20080116470 - Semiconductor light emitting device: The semiconductor light emitting device includes a plurality of transparent light emitting elements of the same size which are arranged in a layered manner on an electric substrate by using a wire bonding. On one of the light emitting elements including a bonding wire connected to a bonding pad of... Agent: Scully Scott Murphy & Presser, Pc

20080116473 - Semiconductor light emitting device: A semiconductor light emitting device is provided which allows emission light from a light source to efficiently outgo from the semiconductor light emitting device so that the light emission intensity of the semiconductor light emitting device is increased. A penetrating opening is formed in the substantially central part of a... Agent: Ditthavong Mori & Steiner, P.c.

20080116472 - Semiconductor light emitting element and method of manufacturing the same: A semiconductor light emitting element including a conductive substrate, a bonding metal layer formed on the conductive substrate, a barrier layer formed on the bonding metal layer, a reflective layer formed on the barrier layer, an ohmic electrode layer formed on the reflective layer, a second conductivity type semiconductor layer... Agent: Morrison & Foerster LLP

20080116471 - Semiconductor light-emitting device and method of manufacturing the same: A semiconductor light-emitting device has an n-type DBR layer (3), an n-type cladding layer (4), an active layer (5), a p-type cladding layer (6), a p-type intermediate layer (7), a p-type contact layer (8), a p-type transparent substrate (9), ohmic electrodes (10 and 11), and a reflecting layer (12). The... Agent: Morrison & Foerster LLP

20080116474 - Thin film transistor array and method of manufacturing the same: A thin film transistor array and method of manufacturing the same include a pixel electrode formed of a transparent conductive layer on a substrate, a gate line formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate electrode connected to the gate line and... Agent: Macpherson Kwok Chen & Heid LLP

20080116475 - Outdoor high power light-emitting diode illuminating equipment: The invention provides a light-emitting diode illuminating equipment. The light-emitting diode illuminating equipment of the invention includes a heat-dissipating plate device, a plurality of heat-dissipating fins, a diode light-emitting apparatus, a plurality of heat-conducting devices, and a shield device. The heat-dissipating fins extend from a surface of the heat-dissipating plate... Agent: Reed Smith LLP

20080116444 - Initializing phase change memories: A thin film phase change memory may be provided with a layer which changes between amorphous and crystalline states. The threshold voltage of that layer may be increased in a variety of fashions. As a result of the threshold increase, it is possible to transition cells, initially fabricated in the... Agent: Timothy N. Trop Trop, Pruner & Hu, P.c.

20080116456 - Gallium nitride material structures including substrates and methods associated with the same: Gallium nitride material-based semiconductor structures are provided. In some embodiments, the structures include a composite substrate over which a gallium nitride material region is formed. The gallium nitride material structures may include additional features, such as strain-absorbing layers and/or transition layers, which also promote favorable stress conditions. The reduction in... Agent: Wolf Greenfield & Sacks, P.c.

20080116464 - Silicon-rich nickel-silicide ohmic contacts for sic semiconductor devices: A method of producing an ohmic contact and a resulting ohmic contact structure are disclosed. The method includes the steps of forming a deposited film of nickel and silicon on a silicon carbide surface at a temperature below which either element will react with silicon carbide and in respective proportions... Agent: Summa, Allan & Additon, P.a.

20080116477 - Nitride semiconductor light emitting device: A nitride semiconductor light emitting device includes a substrate, and a first n-type nitride semiconductor layer, a light emitting layer, a first p-type nitride semiconductor layer, a second p-type nitride semiconductor layer, a p-type nitride semiconductor tunnel junction layer, an n-type nitride semiconductor tunnel junction layer and a second n-type... Agent: Morrison & Foerster LLP

20080116476 - Nitride semiconductor light-emitting device: In a nitride semiconductor light-emitting device having an active layer between an n-type nitride semiconductor layer and a p-type nitride semiconductor layer, the active layer has a multiple quantum well structure including a plurality of InxGa1-xN (0<x≦1) quantum well layers and a plurality of InyGa1-yN (0≦y<1) barrier layers stacked alternately,... Agent: Morrison & Foerster LLP

20080116478 - Process for producing iii group nitride compound semiconductor light emitting device, iii group nitride compound semiconductor light emitting device and lamp: A process for producing a group III nitride compound semiconductor light emitting device, the group III nitride compound semiconductor light emitting device and a lamp, having excellent producability and excellent light emitting characteristics are provided. Such a process for producing a group III nitride semiconductor light emitting device is a... Agent: Sughrue Mion, Pllc

20080116479 - Semiconductor light-emitting element and method for fabricating the same: A method for fabricating a semiconductor light-emitting element according to the present invention includes the steps of (A) providing a striped masking layer on a first Group III-V compound semiconductor, (B) selectively growing a second Group III-V compound semiconductor over the entire surface of the first Group III-V compound semiconductor... Agent: Mark D. Saralino (mei) Renner, Otto, Boisselle & Sklar, LLP

20080116480 - Method and device for electrostatic discharge protection: Electrostatic discharge (ESD) protection is provided for an integrated circuit. In an aspect, a dynamic region having doped regions is formed on an epitaxy layer and substrate, and interconnects contact the dynamic region. In an aspect, the dynamic region operates as a back-to-back SCR that snaps back in both positive... Agent: Delphi Technologies, Inc.

20080116481 - Selective deposition of a dielectric on a self-assembled monolayer-adsorbed metal: Methods and apparatuses to selectively deposit a dielectric on a self-assembled monolayer (“SAM”) adsorbed metal are described. A wafer includes a device having a first electrode. A first self-assembled monolayer is deposited on the wafer covering the first electrode. Next, a portion of the first self-assembled monolayer is removed to... Agent: Intel/blakely

20080116482 - Method to form selective strained si using lateral epitaxy: Embodiments for FET devices with stress on the channel region by forming stressor regions under the source/drain regions or the channel region and forming a selective strained Si using lateral epitaxy over the stressor regions. In a first example embodiment, a lateral epitaxial layer is formed over a stressor region... Agent: Horizon Ip Pte Ltd

20080116483 - High-quality sgoi by annealing near the alloy melting point: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed... Agent: Scully, Scott, Murphy & Presser, P.c.

20080116484 - Method of enhancing hole mobility: A semiconductor device is provided comprising an oxide layer over a first silicon layer and a second silicon layer over the oxide layer, wherein the oxide layer is between the first silicon layer and the second silicon layer. The first silicon layer and the second silicon layer comprise the same... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080116485 - Sb-based cmos devices: A group III-V material CMOS device may have NMOS and PMOS portions that are substantially the same through several of their layers. This may make the CMOS device easy to make and prevent coefficient of thermal expansion mismatches between the NMOS and PMOS portions.... Agent: Intel Corporation C/o Intellevate, Llc

20080116486 - Semiconductor device: A semiconductor device includes: a first semiconductor layer of p-type AlxGa1-xN (0≦x≦1); a second semiconductor layer of n-type AlyGa1-yN (0<y<1, x<y) formed on the first semiconductor layer; a control electrode formed on the second semiconductor layer; a first main electrode connected to the first semiconductor layer and the second semiconductor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080116487 - Methods of fabricating transistors having high carrier mobility and transistors fabricated thereby: Transistors having a high carrier mobility and devices incorporating the same are fabricated by forming a preliminary semiconductor layer in a semiconductor substrate at both sides of a gate pattern. A source/ drain semiconductor layer having a heterojunction with the semiconductor substrate is formed by irradiating a laser beam onto... Agent: Myers Bigel Sibley & Sajovec

20080116488 - Transistor structure and manufacturing method thereof: An HBT structure and manufacturing method thereof, in which the HBT structure includes an emitter, an intrinsic base, a collector, an insulating sidewall, and a stress-inducting base formed by selective epitaxial growth to locally induce a stress to the HBT structure. Compressive or tensile stress is additionally induced from outside... Agent: Patents+tms, P.c.

20080116489 - Heterojunction bipolar transistor: A heterojunction bipolar transistor includes a first conductivity type subcollector layer, a first collector layer containing a first conductivity type impurity, a third collector layer containing a higher concentration of the first conductivity type impurity than the first collector layer, a second collector layer containing a lower concentration of the... Agent: Young & Thompson

20080116490 - Sensing method and nanosensing device for performing the same: A sensing method includes exposing a nano-transducer having a controlled surface to a sample including at least one species. Adsorption of the species on the nano-transducer is transduced to a measurable signal as a function of time. Desorption of the species from the nano-transducer is also transduced to a measurable... Agent: Hewlett Packard Company

20080116491 - Nanoscopic wire-based devices and arrays: Electrical devices comprised of nanoscopic wires are described, along with methods of their manufacture and use. The nanoscopic wires can be nanotubes, preferably single-walled carbon nanotubes. They can be arranged in crossbar arrays using chemically patterned surfaces for direction, via chemical vapor deposition. Chemical vapor deposition also can be used... Agent: Wolf Greenfield & Sacks, P.c.

20080116492 - High voltage gan transistors: A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field... Agent: Koppel, Patrick & Heybl

20080116494 - Method for manufacturing a semiconductor device: The invention relates to a method for manufacturing a semiconductor device. A silicon substrate comprising at least one structured area in which a dopant is implanted is provided. A contact modifying material is provided on the surface of the at least one structured area. A silicide layer is formed on... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20080116493 - Multi-layer spacer with inhibited recess/undercut and method for fabrication thereof: A semiconductor structure includes a multi-layer spacer located adjacent and adjoining a sidewall of a topographic feature within the semiconductor structure. The multi-layer spacer includes a first spacer sub-layer comprising a deposited silicon oxide material laminated to a second spacer sub-layer comprising a material that is other than the deposited... Agent: Scully, Scott, Murphy & Presser, P.c.

20080116495 - Display device: The present invention provides a display device having an illuminance detection circuit. The illuminance detection circuit includes: a photosensor which changes an optical current in response to illuminance of an external light; a capacitor which discharges a charge when the optical current flows in the photosensor; a comparator which compares... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080116496 - Integrating a dram with an sram having butted contacts and resulting devices: A novel SOC structure and method of making the same are provided. An SOC comprises a logic region, an SRRM and a DRAM region. The storage capacitor in a DRAM cell is formed in the first dielectric layer in an MIM (metal-insulator-metal) configuration, having a large vertical surface area. A... Agent: Slater & Matsil, L.l.p.

20080116497 - Chip-packaging compositions including catalysts and hardeners, packages made therewith, and methods of assembling same: A chip-packaging composition includes a thermosetting resin and at least one of an N-hetero cyclic carbene adduct, an imidazole, and a cycloaliphatic amine hardener. The chip-packaging composition is applied to flip-chip technology during no-flow underfill mounting of the flip-chip to a mounting substrate. The mounting substrate can be further mounted... Agent: Schwegman, Lundberg & Woessner, P.a.

20080116498 - Method of forming a semiconductor device having a capacitor and a resistor: A semiconductor device comprising the following. A structure having: a capacitor; a first resistor; and a second resistor each within at least a portion of an oxide structure and a metal-oxide semiconductor electrode not within at least a portion of the oxide structure. The capacitor comprising: a lower capacitor first... Agent: Saile Ackerman Llc

20080116499 - Gated diode nonvolatile memory process: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Various embodiments may include or exclude a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080116500 - Semiconductor device and method for manufacturing the same: A semiconductor device which does not reduce writing property of a memory element and a method for manufacturing the same are proposed even in the case of forming a silicon film at a step portion formed by a surface of a substrate and a wiring formed over the substrate. The... Agent: Eric Robinson

20080116501 - Pixel structure and repair method thereof: A pixel structure includes a backup thin film transistor with a float gate electrode or a float drain electrode and a working thin film transistor. When the pixel of the working thin film transistor does not work, the backup thin film transistor replaces the working thin film transistor to drive... Agent: Jianq Chyun Intellectual Property Office

20080116502 - Non-volatile memory with epitaxial regions for limiting cross coupling between floating gates: A memory system is disclosed that includes a set of non-volatile storage elements. Each of the non-volatile storage elements includes source/drain regions at opposite sides of a channel in a substrate and a floating gate stack above the channel. The memory system also includes a set of shield plates positioned... Agent: Vierra Magen/sandisk Corporation

20080116503 - Semiconductor memory device including a stacked gate having a charge storage layer and a control gate, and method of manufacturing the same: A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080116504 - Flash memory cell and method for manufacturing the same: A flash memory cell and a method for manufacturing the same are provided. The flash memory cell includes a tunnel oxide layer pattern, a floating gate on the tunnel oxide layer pattern, a first nitride layer pattern on the floating gate, an oxide-nitride-oxide (ONO) layer pattern on the first nitride... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080116506 - Charge trapping devices with field distribution layer over tunneling barrier: A memory cell comprising: a semiconductor substrate with a surface with a source region and a drain region disposed below the surface of the substrate and separated by a channel region; a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed above the channel... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080116505 - Non-volatile memory cells formed in back-end-of line processes: An integrated circuit device includes a substrate; a bottom electrode over the substrate wherein the bottom electrode is in or over a lowest metallization layer over the substrate; a blocking layer over the bottom electrode; a charge-trapping layer over the blocking layer; an insulation layer over the charge-trapping layer; a... Agent: Slater & Matsil, L.l.p.

20080116507 - Nonvolatile semiconductor memory device and method for manufacturing the same: A nonvolatile semiconductor memory device includes: a source region and a drain region formed at a distance from each other in a semiconductor substrate; a tunnel insulating film formed on the semiconductor substrate between the source region and the drain region; a charge storage film formed on the tunnel insulating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080116508 - Semiconductor memory device: A semiconductor memory device of the invention includes a substrate, a convex semiconductor formed convexly on the substrate, a channel region formed within the convex semiconductor, source and drain regions formed within the convex semiconductor so as to sandwich the channel region, a resistance transition region formed so as to... Agent: Rabin & Berdo, Pc

20080116509 - Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements: Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080116510 - Mos-gated device having a buried gate and process for forming same: An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper... Agent: Hiscock & Barclay, LLP

20080116511 - Semiconductor device with trench transistors and method for manufacturing such a device: According to one embodiment, a method for manufacturing a semiconductor device includes forming trenches in a first side of a semiconductor material and forming a thick oxide layer on the trenches and on the first side. A part of the first side and the trenches is masked using a first... Agent: Davidson, Davidson & Kappel, Llc

20080116512 - Semiconductor device and method of making the same: A semiconductor device includes a first conductivity type layer and a second conductivity type layer, which are alternately and repeatedly positioned, adjacent to each other, in a column-like fashion on a first conductivity type substrate. The balance of the net charge amount of the impurity between the first conductivity type... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080116513 - Modular bipolar-cmos-dmos analog integrated circuit and power transistor technology: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of... Agent: Patentability Associates

20080116514 - Method and structure for reducing floating body effects in mosfet devices: A field effect transistor (FET) device includes a bulk substrate, a gate insulating layer formed over the bulk substrate, source and drain regions formed in an active device area associated with the bulk substrate, the source and drain regions each defining a p/n junction with respect to a body region... Agent: Cantor Colburn LLP - Ibm Fishkill

20080116515 - Mugfet with increased thermal mass: Some embodiments discussed herein include a semiconductor having a source region, a drain region and an array of fins operatively coupled to a gate region controlling current flow through the fins between the source region and the drain region. The semiconductor also has at least one cooling element formed at... Agent: Schwegman, Lundberg & Woessner / Infineon

20080116516 - Thin film transistor array substrate and fabricating method thereof: A TFT array substrate is provided. The TFT array substrate includes a substrate, a patterned first metallic layer, a patterned semiconductor layer, a patterned transparent conductive layer, a patterned dielectric layer, and a patterned second metallic layer. Elements of each TFT of the TFT array substrate are arranged vertically, so... Agent: Jianq Chyun Intellectual Property Office

20080116517 - Dual stress device and method: A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a... Agent: Greenblum & Bernstein, P.L.C

20080116518 - Metal-oxide-semiconductor device and manufacturing method thereof: The present invention provides a device for ESD protection and voltage stabilizing in order to let chip space be put in better utilization. During different conditions (i.e. ESD current occurrences and normal operation), identical elements of the device are used both for ESD protection and for voltage stabilization. The chip... Agent: Rosenberg, Klein & Lee

20080116519 - Integrated circuit used in smart power technology: An integrated circuit used in smart power technology, in particular, for use in automobile applications, which includes: high-voltage terminals for connection to a high voltage, a smart circuit device having low-voltage components, and an ESD protective circuit, connected between the high-voltage terminals, which has a MOSFET whose source and drain... Agent: Kenyon & Kenyon LLP

20080116520 - Termination structures for semiconductor devices and the manufacture thereof: A semiconductor device has a semiconductor body (22) comprising an active area (7) and a termination structure (16) surrounding the active area. The termination structure comprises a plurality of lateral transistor devices (2a to 2d) connected in series and extending from the active area towards a peripheral edge (42) of... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080116521 - Cmos integrated circuits that utilize insulating layers with high stress characteristics to improve nmos and pmos transistor carrier mobilities and methods of forming same: A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic... Agent: Myers Bigel Sibley & Sajovec

20080116522 - Cmos structure including topographic active region: A CMOS structure includes a first device located using a first active region within a semiconductor substrate, where the first active region is planar and has a first crystallographic orientation. The CMOS structure also includes a second device that is located using a second active region within the semiconductor substrate,... Agent: Scully, Scott, Murphy & Presser, P.c.

20080116523 - Cmos transistor and method of manufacture thereof: A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. An aluminum-based material is used as a gate dielectric material of a PMOS device, and a hafnium-based material is used as a gate dielectric material of an NMOS device. A thin layer of silicon... Agent: Slater & Matsil LLP

20080116525 - Complementary metal-oxide-semiconductor device: A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed... Agent: Jianq Chyun Intellectual Property Office

20080116524 - Dual stress liner: A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second... Agent: International Business Machines Corporation Dept. 18g

20080116526 - Semiconductor device and method for manufacturing the same: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to... Agent: Mcdermott Will & Emery LLP

20080116527 - Methods of improving operational parameters of pair of matched transistors and set of transistors: Methods of improving operational parameters between at least a pair of matched transistors, and a set of transistors, are disclosed. One embodiment of a method includes a method of improving at least one of a threshold voltage (Vt) mismatch and current drive between at least a pair of matched transistors... Agent: Hoffman, Warnick & D'alessandro Llc

20080116528 - Semiconductor device and method of manufacturing the same: A semiconductor device according to the present invention comprises a semiconductor substrate of a first conductive type, a first element region and a second element region provided on the semiconductor substrate, a retrograde well formed from a first impurity of a second conductive type and provided at a deep section,... Agent: Mcdermott Will & Emery LLP

20080116529 - Shallow trench isolation structure for shielding trapped charge in a semiconductor device: A semiconductor structure comprising a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom... Agent: Schmeiser, Olsen & Watts

20080116530 - Semiconductor devices having transistors with different gate structures and related methods: A semiconductor device may include a semiconductor substrate and first and second transistors. The first transistor may have a first gate structure on the semiconductor substrate, and the first gate structure may include a first gate insulating layer between a first gate electrode and the semiconductor substrate. The first gate... Agent: Myers Bigel Sibley & Sajovec

20080116531 - Semiconductor device: A semiconductor device and a method of manufacturing the same, wherein first and second gate electrodes are formed to have a spacer shape. The length of an underlying dielectric film can be automatically controlled. A gate oxide film and a third gate electrode are formed between the first and second... Agent: Marshall, Gerstein & Borun LLP

20080116532 - Method of manufacturing semiconductor device, and semiconductor device: First, in a first step, a gate electrode is formed over a silicon substrate, with a gate insulation film therebetween. Next, in a second step, etching with the gate electrode as a mask is conducted so as to dig down a surface layer of the silicon substrate. Subsequently, in a... Agent: Sonnenschein Nath & Rosenthal LLP

20080116533 - Semiconductor device in wafer assembly: An apparatus and method for holding a semiconductor device in a wafer. A bar is connected to the wafer. A first sidewall comprises a first end and a second, and is connected to the bar at its first end. A first tab comprises a first end and a second end,... Agent: Ami Chand Applied Nanostructures, Inc

20080116534 - Substrate contact for a mems device: One embodiment of the present invention sets forth a substrate contact for a MEMS device die, where the substrate contact is formed through an electrically insulative layer in the device die that is positioned between a handle wafer layer and a MEMS device layer formed on the handle wafer layer.... Agent: Patterson & Sheridan, L.l.p.

20080116535 - Methods and apparatus for a dual-metal magnetic shield structure: A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component (e.g., a magnetoresistive random access memory, or “MRAM”) includes a stress-relief layer (e.g., electroplated Ni) formed over the semiconductor device in a shield region substantially corresponding to the electromagnetic-field-susceptible region, and a magnetic shield layer (e.g., an electroplated... Agent: Ingrassia Fisher & Lorenz, P.c. (fs)

20080116536 - Organic hybrid planar-nanocrystalline bulk heterojunctions: A photosensitive optoelectronic device having an improved hybrid planar bulk heterojunction includes a plurality of photoconductive materials disposed between the anode and the cathode. The photoconductive materials include a first continuous layer of donor material and a second continuous layer of acceptor material. A first network of donor material or... Agent: Kenyon & Kenyon LLP

20080116537 - Cmos imager array with recessed dielectric: A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein “m” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense... Agent: Scully, Scott, Murphy & Presser, P.c.

20080116538 - Multigate schottky diode: C

20080116539 - Schottky device and process of making the same: A Schottky device and a semiconductor process of making the same are provided. The Schottky device comprises a substrate, a deep well, a Schottky contact, and an Ohmic contact. The substrate is doped with a first type of ions. The deep well is doped with a second type of ions,... Agent: Nixon Peabody LLP - Patent Group

20080116540 - Stacked switchable element and diode combination with a low breakdown switchable element: A device (10) comprises a semiconductor diode (12) and a switchable element (14) positioned in stacked adjacent relationship. The semiconductor diode (12) and the switchable element (14) are electrically connected in series with one another. The switchable element (14) is switchable from a low-conductance state to a high-conductance state in... Agent: Paul J. White Nrel

20080116541 - Structure for integrating an rf shield structure in a carrier substrate: A structure for shielding high frequency passive elements includes a first face of a semi-conductive substrate in parallel with a second face of a non-conductive substrate. The first face of the semi-conductive substrate is substantially parallel to a second face thereof. A passive element is disposed in the non-conductive substrate... Agent: Cantor Colburn LLP - Ibm Fishkill

20080116542 - Gate dielectric having a flat nitrogen profile and method of manufacture therefor: The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated circuit including the flat nitrogen profile. In one embodiment, the method of manufacturing the gate dielectric includes forming a gate dielectric layer (410) on a substrate... Agent: Texas Instruments Incorporated

20080116543 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming a material layer. The method includes forming at least one first layer of a first material, and forming at least one second layer of a second material over the at least one first... Agent: Slater & Matsil LLP

20080116544 - Packaged semiconductor chips with array: A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the... Agent: Tessera Lerner David Et Al.

20080116545 - Packaged semiconductor chips: A chip-sized wafer level packaged device including a portion of a semiconductor wafer including a device, a packaging layer formed over the portion of the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer and a ball grid array formed... Agent: Tessera Lerner David Et Al.

20080116546 - Lead frame unit, semiconductor package having a lead frame unit, stacked semiconductor package having a semiconductor package and methods of manufacturing the same: A lead frame unit, a semiconductor package having a lead frame unit, a stacked semiconductor package having a semiconductor package, and methods of manufacturing the same are provided. The lead frame unit in a stacked semiconductor package may include a die pad supporting a semiconductor chip, an inner lead electrically... Agent: Harness, Dickey & Pierce, P.L.C

20080116547 - Ic package keeping attachment level of leads on chip during molding process: An IC package keeping the attachment level of leads on chip during molding process, mainly comprises a plurality of leads of a Lead-On-Chip (LOC) leadframe, a chip adhered under the leads, a plurality of bonding wires electrically connecting the chip to the leads, a plurality of first supporting columns disposed... Agent: Troxell Law Office Pllc

20080116549 - Transmission type photo interrupter and manufacturing method for same: A transmission type photo interrupter has a light emitting element, a light receiving element, a lead frame, and a connector terminal, which are integrally molded with light-shielding resin. The light emitting chip and the light receiving chip are mounted on the same surface of the lead frame and rotated in... Agent: Birch Stewart Kolasch & Birch

20080116548 - Wire bond and method of forming same: In a semiconductor package having a plurality of wire bond interconnections between a semiconductor chip and a chip carrier, a wire bond (20) including a first stitch bond (22) formed at a first location (24) on a bonding site (26), and a second stitch bond (40) formed at a second... Agent: Freescale Semiconductor, Inc. Law Department

20080116550 - Integrated battery pack with lead frame connection: An integrated battery package, that contains semiconductor chips, for example to control and regulate battery charging and to monitor the package operation, uses a single lead frame to interconnect several internal chips, to internally connect said control chips to the battery and to connect the whole package assembly externally. The... Agent: Saile Ackerman Llc

20080116552 - Electronic system with lead free interconnections and method of fabrication: An electronic system (1) having an interconnect structure (30, 45). In one embodiment a system (1) includes a first electronic device (2) with a first plurality of contact pads (15) each having a noble metal (18) formed along a first surface (19), and a second electronic device (3) with a... Agent: General Electric Company Global Research

20080116551 - Method for producing a laser diode component, housing for a laser diode comoponent, and laser diode component itself: A method for producing a laser diode component having an electrically insulating housing basic body (1) and electrical connecting conductors (5a, 5b), which are led out from the housing basic body and are accessible from outside the housing basic body (1). The housing basic body (1) is produced from a... Agent: Cohen, Pontani, Lieberman & Pavane

20080116553 - Wirebond package design for high speed data rates: A wirebond package design that reduces power supply noise and noise coupling using common mode shielding. The package design having lanes with wirebond connections. The wirebond connections have wirebond pads staggered along a longitudinal axis. The wirebond pads accommodate a plurality of shields that isolate differential pairs and adjacent lanes.... Agent: Downs Rachlin Martin Pllc

20080116554 - Packaging micro devices: A method for applying anti-stiction material to a micro device includes encapsulating a micro device in a chamber, vaporizing anti-stiction material in a container to form vaporized anti-stiction material, transferring the vaporized anti-stiction material from the container to the chamber, and depositing the vaporized anti-stiction material on a surface of... Agent: Fish & Richardson P.c.

20080116558 - Decoupling capacitor, wafer stack package including the decoupling capacitor, and method of fabricating the wafer stack package: A decoupling capacitor, a wafer stack package including the decoupling capacitor, and a method of fabricating the wafer stack package are provided. The decoupling capacitor may include a first electrode formed on an upper surface of a first wafer, a second electrode formed on a lower surface of a second... Agent: Marger Johnson & Mccollom, P.c.

20080116556 - Package structure having through hole in spacer thereof: A package structure having through hole in spacer is provided. The package structure includes a substrate, a first chip, a spacer and a sub-package. The first chip is disposed on the substrate, to which an active surface of the first chip is electrically connected. The spacer, having a first side,... Agent: Bacon & Thomas, Pllc

20080116555 - Package structure of memory card and manufacturing method thereof: A package structure of a memory card includes a Printed Circuit Board (PCB) and at least one chip package. Plural solder pads are set on the upper surface of the PCB, and an exposed golden finger is set on the bottom surface of the PCB. Every chip package includes at... Agent: Bacon & Thomas, Pllc

20080116559 - Semiconductor device, stacked semiconductor device and interposer substrate: A semiconductor device has a semiconductor element; an interposer substrate having a wiring pattern electrically connected to the semiconductor element and an insulating substrate formed with the wiring pattern; a connection layer for adhering between the semiconductor element and the interposer substrate; and a solder ball external terminal arranged on... Agent: Foley And Lardner LLP Suite 500

20080116557 - Semiconductor package having improved heat spreading performance: A semiconductor package having a structure in which heat produced in the interior of the package is effectively spread to the outside of the package is provided. The semiconductor package includes one or more semiconductor chips, one or more substrates (PCBs) having the semiconductor chips respectively attached thereto,a plurality of... Agent: Marger Johnson & Mccollom, P.c.

20080116562 - Carrier structure for semiconductor chip and method for manufacturing the same: A carrier structure for a semiconductor chip and a method for manufacturing the same are disclosed. The method includes the following steps: providing a carrier board having at least one through cavity, wherein a removable film is formed on the surface of the carrier board, and a semiconductor chip is... Agent: Bacon & Thomas, Pllc

20080116561 - Chip carrier film having leads with improved strength and semiconductor package utilizing the film: A semiconductor chip carrier film with enhanced lead strengths primarily comprises a flexible dielectric layer, a plurality of leads on the dielectric layer, a reinforced metal layer and a solder mask partially covering the leads. Therein, at least one of the leads has a bend covered by the reinforced metal... Agent: Troxell Law Office Pllc

20080116560 - Method of packaging a device having a tangible element and device thereof: Forming a packaged device having a semiconductor device having a first major surface and a second major surface includes forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the first semiconductor device... Agent: Freescale Semiconductor, Inc. Law Department

20080116563 - Semiconductor package having structure for warpage prevention: A semiconductor package includes a substrate having a plurality of connection pads and a plurality of ball lands; a semiconductor chip attached to one surface of the substrate and having a plurality of bonding pads that are connected to the respective connection pads of the substrate; a first molding structure... Agent: Ladas & Parry LLP

20080116564 - Wafer level package with die receiving cavity and method of the same: The present invention provides a structure of package comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and a through hole structure formed there through, wherein a terminal pad is formed under the through hole structure and the substrate includes a conductive trace... Agent: Kusner & Jaffe Highland Place Suite 310

20080116565 - Circuit board structure with embedded semiconductor chip and method for fabricating the same: The present invention provides a circuit board structure with an embedded semiconductor chip and a method for fabricating the same. The circuit board structure includes a carrier board having a first surface, a second surface, and a through hole penetrating the carrier board from the first surface to the second... Agent: Sawyer Law Group LLP

20080116566 - Electronic component and method for manufacturing the same: A method of manufacturing an electronic component includes the steps of: a) forming via holes penetrating through a first semiconductor substrate and a second semiconductor substrate which are bonded together by way of a connection layer; b) pattern-etching the second semiconductor substrate using the connection layer as an etch-stop layer... Agent: Rankin, Hill & Clark LLP

20080116568 - Direct semiconductor contact ebullient cooling package: The semiconductor package as well as a method for making it and using it is disclosed. The semiconductor package comprises a semiconductor chip having at least one heat-generating semiconductor device and a volumetrically expandable chamber disposed to sealingly surround the semiconductor chip, the volumetrically expandable chamber filled entirely with a... Agent: Gates & Cooper LLP

20080116569 - Embedded chip package with improved heat dissipation performance and method of making the same: A Chip-in Substrate Package (CiSP) includes a double-sided metal clad laminate including a dielectric interposer, a first metal foil laminated on a first side of the dielectric interposer, and a second metal foil laminated on a second side of the dielectric interposer. A recessed cavity is etched into the second... Agent: North America Intellectual Property Corporation

20080116567 - Flip chip assembly having improved thermal dissipation: An assembly comprises a stiffener, a circuit substrate and an IC chip. The stiffener has a surface with a first region and a second region. The circuit substrate covers at least a portion of the first region of the stiffener, while the IC chip overlies at least a portion of... Agent: Ryan, Mason & Lewis, LLP

20080116570 - Heatplates for heatsink attachment for semiconductor chips: An apparatus for heatsink attachment. The apparatus includes a substrate, a semiconductor chip on top of and physically attached to the substrate, and a lid on top of the substrate. The lid includes a first thermally conductive material. The apparatus further includes a heatsink on top of the lid. The... Agent: Schmeiser, Olsen & Watts

20080116571 - Structures to enhance cooling of computer memory modules: A spring-like cooling structure for an in-line chip module is formed from a continuous sheet of a thermally conducting material having a front side and a back side, the sheet folded at substantially a one-hundred and eighty degree angle, wherein a length of the structure substantially correlates to a length... Agent: Michael Buchenhorner, P.a.

20080116572 - Semiconductor memory modules, methods of arranging terminals therein, and methods of using thereof: Example embodiments may provide a semiconductor memory module having shorter length of terminal stubs, a method of arranging terminals to reduce or minimize length of each stub, and methods of using the same. Example embodiment semiconductor memory modules may include first and second semiconductor memory devices each having terminals in... Agent: Harness, Dickey & Pierce, P.L.C

20080116573 - Method of packaging a device having a multi-contact elastomer connector contact area and device thereof: Forming a packaged device having a semiconductor device having a first major surface and a second major surface includes forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the first semiconductor device... Agent: Freescale Semiconductor, Inc. Law Department

20080116574 - Bga package with encapsulation on bottom of substrate: A BGA package with encapsulation on substrate bottom comprises a chip, a substrate, a molding compound and a plurality of solder balls. The substrate has a SMT surface placing a plurality of ball pads. The molding compound encapsulates a solder resist layer on the SMT surface of the substrate and... Agent: Troxell Law Office Pllc

20080116575 - Nitride semiconductor device and method of manufacturing the same: A nitride semiconductor device according to the present invention includes a P-type contact layer and a P-type electrode provided on the P-type contact layer. The P-type electrode includes a AuGa film provided on the P-type contact layer, a Au film provided on the AuGa film, a Pt film 4 provided... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080116576 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming a barrier layer. The method of forming the barrier layer includes providing a workpiece, forming a first material layer over the workpiece, the first material layer comprising a nitride-based metal compound. A second... Agent: Slater & Matsil LLP

20080116577 - Semiconductor device and production method therefor: A semiconductor device provided with: a first interconnection layer provided on a semiconductor substrate; an interlevel insulation film provided over the first interconnection layer; a barrier layer provided between the first interconnection layer and the interlevel insulation film; and a second interconnection layer of gold provided as an uppermost interconnection... Agent: Rabin & Berdo, Pc

20080116578 - Initiation layer for reducing stress transition due to curing: An integrated circuit includes an etch stop layer over a substrate; a UV blocker layer on the etch stop layer, wherein the UV blocker layer has a high extinction coefficient; and a low-k dielectric layer on the UV blocker layer.... Agent: Slater & Matsil, L.l.p.

20080116579 - Method of manufacturing multilevel interconnect structure and multilevel interconnect structure: A method of manufacturing a multilevel interconnect structure using a screen printing method is disclosed. In the multilevel interconnect structure, an interlayer insulating film having a through hole with a conductive bump therein, and a second interconnect line are stacked on a substrate with a first interconnect line formed thereon.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080116580 - Semiconductor package and fabrication method thereof: A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer and the insulation layer to expose the metal carrier; forming... Agent: Edwards Angell Palmer & Dodge LLP

20080116581 - Post passivation interconnection schemes on top of the ic chips: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Megica Corporation

20080116582 - Interconnect structures with improved electromigration resistance and methods for forming such interconnect structures: Interconnect structures including liner layers that are non-planar with at least the adjacent insulating layer and at least one capping layer on conductive features embedded in the insulating layer. The interconnect structure includes an insulating layer of a dielectric material having a top surface and a bottom surface between the... Agent: Wood, Herron & Evans, L.l.p. (ibm)

20080116583 - Semiconductor device and method of forming the same: A semiconductor device includes a semiconductor substrate, source and drain regions on the semiconductor substrate, and contact plugs connected to the source and drain regions. The contact plugs includes first impurity-diffused epitaxial layers that contact with the source and drain regions.... Agent: Sughrue Mion, Pllc

20080116585 - Multi-chip structure: A multi-chip structure including a first chip and a second chip is provided. The first chip has a buffer area, an interconnection area, and a first surface. The buffer area is electrically insulated from the interconnection area. The second chip is disposed on the first surface. The second chip is... Agent: J C Patents, Inc.

20080116584 - Self-aligned through vias for chip stacking: An electronic component includes a first component and a second component, each having a surface that includes a plurality of exposed contacts separated by an insulating material. A sandwich layer is disposed between the surface of the first component and the surface of the second component. The surface of the... Agent: Slater & Matsil LLP

20080116587 - Conductor polymer composite carrier with isoproperty conductive columns: A carrier comprises a metallic panel, a conductive column, a circuit, and an electrically insulating filling. The conductive column is within the panel and travels from a first surface to a second surface of the panel. The circuit is located on first surface of the panel and in communication with... Agent: Thelen Reid Brown Raysman & Steiner LLP

20080116586 - Methods for manufacturing thermally enhanced flip-chip ball grid arrays: Methods for fabricating flip-chips are disclosed. In an exemplary method, a flip-chip is mounted, active-surface downward, onto a substrate such that a back-side of the flip-chip is facing upward and electrical connections are made between the chip and an upward-facing surface of the substrate. An adhesive is applied to selected... Agent: Klarquist Sparkman, LLP

20080116588 - Assembly and method of placing the assembly on an external board: The assembly comprises an electronic device (20) that is attached to a first side (11) of a carrier substrate (10) with solder connections (18). The first side (11) of the substrate (10) is provided with bond pads (15) and a solder resist layer (16). The space between the substrate (10)... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080116589 - Ball grid array package assembly with integrated voltage regulator: An integrated voltage regulator may be provided on the bottom of a ball grid array processor package. This may be done despite the fact that conventionally integrated voltage regulator chips are too thick to fit in the area normally available between the motherboard and the ball grid array package because... Agent: Trop Pruner & Hu, Pc

20080116590 - Semiconductor device: A semiconductor device includes a resin package, a lower pad embedded in the package, an upper pad embedded in the package at a distance from the lower pad, a lower semiconductor element bonded to the lower pad, and an upper semiconductor element bonded to the upper pad and facing the... Agent: Hamre, Schumann, Mueller & Larson, P.c.

20080116591 - Semiconductor device and method for manufacturing same: A semiconductor device comprises a semiconductor element having electrodes, a metal member, wires that electrically connect the semiconductor element and the metal member and/or electrodes within the semiconductor element, wherein the wires constitute at least a first wire loop and a second wire loop, the first wire loop is bonded... Agent: Global Ip Counselors, LLP

20080111120 - Non-volatile memory devices having cell diodes and methods of fabricating the same: An integrated circuit memory cell includes a substrate having a first semiconductor region of first conductivity type (e.g., N-type) therein, which may define a portion of a word line within the substrate. An electrically insulating layer is provided on the substrate. The electrically insulating layer has an opening therein that... Agent: Myers Bigel Sibley & Sajovec

20080111121 - Phase change memory device and method of fabricating the same: A phase change memory device and a method of fabricating the same are disclosed. The phase change memory device includes a first conductor pattern having a first conductivity type and a sidewall. A second conductor pattern is connected to the sidewall of the first conductor pattern to form a diode.... Agent: Marger Johnson & Mccollom, P.c.

20080111122 - Organic light emitting apparatus: An organic light emitting apparatus comprising a substrate and a plurality of organic light emitting devices having different emission colors to each other formed on the substrate, each of the plurality of organic light emitting devices including a cathode, an electron injection layer which is in contact with the cathode,... Agent: Fitzpatrick Cella Harper & Scinto

20080111123 - High efficiency light-emitting diodes: High efficiency LEDs produced using a direct-bandgap AlGaInNSbAsP material system grown directly on GaP substrates.... Agent: Townsend And Townsend And Crew, LLP

20080111128 - Composition and organic insulating film prepared using the same: Disclosed is a composition, an organic insulating film including the same, an organic thin film transistor including the organic insulating film, an electronic device including the organic thin film transistor and methods of fabricating the same. In the composition, an organic polymer material having a carboxyl group and an organic... Agent: Harness, Dickey & Pierce, P.L.C

20080111129 - Composition and organic insulator prepared using the same: Disclosed is a composition for preparing an organic insulator, including an organic silane material, having a vinyl group, an acetylene group or an acryl group as a functional group for participating in a crosslinking reaction, a crosslinking agent, and a solvent for dissolving the above components. The organic insulator of... Agent: Harness, Dickey & Pierce, P.L.C

20080111130 - Electro-optic device manufacturing method, electro-optic device, liquid crystal device, organic electroluminescent device, and electronic apparatus: An electro-optic device manufacturing method comprises providing a first partition on a substrate in a form of a pattern; depositing a metal material onto the substrate, forming a pixel electrode and a signal line on a top surface of the first partition, and forming a gate wire in an area... Agent: Oliff & Berridge, Plc

20080111127 - Ferrocene-containing conductive polymer, organic memory device using the same and fabrication method of the organic memory device: Disclosed are a ferrocene-containing conductive polymer, an organic memory device using the conductive polymer and a method for fabricating the organic memory device. The conductive polymer may include a fluorenyl repeating unit, a thienyl repeating unit and a diarylferrocenyl repeating unit. The organic memory device may possess the advantages of... Agent: Harness, Dickey & Pierce, P.L.C

20080111124 - Metallocenyl dendrimer, organic memory device using the same and fabrication method of the organic memory device: Disclosed are a metallocenyl dendrimer, an organic memory device using the metallocenyl dendrimer and a method for fabricating the organic memory device. The metallocenyl dendrimer may be composed of a dendrimer and metallocenes as redox species linked to the dendrimer. The organic memory device may possess the advantages of shorter... Agent: Harness, Dickey & Pierce, P.L.C

20080111125 - Organic light emitting display and fabricating method thereof: A thin organic light emitting device that can be used in thin devices like mobile phones and personal digital assistants. An organic light emitting display (OLED) includes a layer that blocks UV rays so that the diode and the transistor are shielded from UV rays during and after production. In... Agent: Robert E. Bushnell

20080111126 - Organic light emitting display and fabrication method thereof: An organic light emitting display includes: a substrate, a buffer layer arranged on the substrate, a semiconductor layer arranged on the buffer layer, a gate insulating layer arranged on the semiconductor layer, a gate electrode arranged on the gate insulating layer, an inter-layer dielectric layer arranged on the gate electrode,... Agent: Robert E. Bushnell

20080111131 - Organic thin film transistor, method of fabricating the same, and display device including the same: An organic thin film transistor (OTFT) includes an organic semiconductor layer on a substrate, source/drain electrodes spaced apart from each other on the substrate, a mixed layer between the source/drain electrodes and the organic semiconductor layer, the mixed layer including an organic material and a metal oxide or metal salt,... Agent: Lee & Morse, P.c.

20080111132 - Thin film transistor array substrate and fbricating method thereof: A thin film transistor array substrate and a fabricating method thereof are disclosed. First, a substrate is provided. A patterned transparent conductive layer is then formed on the substrate. Next, a patterned first metal layer is formed to form a plurality of scan lines and a plurality of gates. Thereafter,... Agent: Jianq Chyun Intellectual Property Office

20080111133 - Thin film transistor and method of fabricating the same: A thin film transistor includes a substrate; a semiconductor layer disposed on the substrate, and including polycrystalline silicon having a constant directivity and a uniformly distributed crystal grain boundary; a gate insulating layer; a gate electrode; an interlayer insulating layer; and source and drain electrodes. The thin film transistor is... Agent: Stein, Mcewen & Bui, LLP

20080111135 - Organic light emitting diode display device and method of manufacturing the same: An organic light emitting diode display device (OLED display device) having uniform electrical characteristics and a method of manufacturing the same. The OLED display device includes: a substrate; a semiconductor layer disposed on the substrate, and including source and drain regions and a channel region formed using metal induced lateral... Agent: Stein, Mcewen & Bui, LLP

20080111136 - Tft-lcd pixel unit and method for manufacturing the same: A thin film transistor liquid crystal display (TFT-LCD) pixel unit and a method for manufacturing the same. The pixel unit comprises a gate line and a gate electrode formed on a substrate and a first gate insulating layer, an active layer, and a doped layer sequentially that are formed on... Agent: Hasse & Nesbitt Llc

20080111137 - Thin film transistor substrate with bonding layer and method for fabricating the same: An exemplary thin film transistor substrate (30) includes a bas substrate (31) and a gate electrode (32) formed on the bas substrate. The gate electrode includes a bonding layer (321) formed on the bas substrate and an electrically conductive layer (322) formed on the bonding layer. The bonding layer includes... Agent: Wei Te Chung Foxconn International, Inc.

20080111138 - Pixel structure and method for fabricating the same: A pixel structure is disclosed. The pixel structure includes a substrate, a first data line having at least one end formed on the substrate, a first insulation layer overlying the first data line and exposing a part of the end of the first data line, a shielding electrode disposed on... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080111139 - Vertical light emitting device and method of manufacturing the same: Provided is a vertical light emitting device having improved light extraction efficiency and a method of manufacturing the same. The vertical light emitting device may include a p type electrode, a p type semiconductor layer, an active layer, and an n type semiconductor layer which may be sequentially formed on... Agent: Harness, Dickey & Pierce, P.L.C

20080111141 - Light emitting diode assembly and method of fabrication: An LED assembly comprises an LED and a lens disposed adjacent to a light emitting surface of the LED. The area of cross-section of the lens projected onto the light emitting surface of the LED is substantially equal to or less than the area of the LED's light emitting surface.... Agent: Buchanan, Ingersoll & Rooney Pc

20080111140 - Light-emitting diode: A light-emitting diode comprises: a coupling base; a plurality of light-emitting chips; and a sealant, wherein a plurality of frame pairs having an amount corresponding to that of the light-emitting chips are mounted inside the coupling base. The frame pairs have a plurality of first and second frames having different... Agent: Troxell Law Office Pllc

20080111142 - Semiconductor light emitting device and method of manufacturing it: A semiconductor light emitting device capable of precisely detecting a cleavage position is provided. A second light emitting device is layered on a first light emitting device. The second light emitting device has stripe-shaped opposed electrodes that are respectively arranged oppositely to respective p-side electrodes of the first light emitting... Agent: Robert J. Depke Lewis T. Steadman

20080111143 - Light-emitting module of vehicular lamp: A light-emitting module includes a semiconductor light-emitting element with a generally oblong shape, and a planar electrode formed on a surface of the semiconductor light-emitting element. The planar electrode has a generally right triangular electrode portion that is defined by an oblique cut-off line on any one of four corners... Agent: Osha Liang L.l.p.

20080111144 - Light emitting diode and laser diode using n-face gan, inn, and aln and their alloys: The present invention allows the growth of InGaN with greater compositions of Indium than traditionally available now, which pushes LED and LD wavelengths into the yellow and red portions of the color spectrum. The ability to grow with Indium at higher temperatures leads to a higher quality AlInGaN. This also... Agent: Gates & Cooper LLP Howard Hughes Center

20080111146 - Standing transparent mirrorless light emitting diode: An (Al, Ga, In)N light emitting diode (LED) in which multi-directional light can be extracted from one or more surfaces of the LED before entering a shaped optical element and subsequently being extracted to air. In particular, the (Al, Ga, In)N and transparent contact layers (such as ITO or ZnO)... Agent: Gates & Cooper LLP Howard Hughes Center

20080111145 - White light emitting diode device: The present invention relates to a white light emitting diode device, which comprises a light emitting diode device; a base case, which is provided with a fillister for placing the LED and a rabbet; and a covering element, which is installed over the fillister and fixed on the rabbet and... Agent: Birch Stewart Kolasch & Birch

20080111134 - Semiconductor device, method of making the same and liquid crystal display device: To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080111148 - Led reflective package: An LED package which employs a high temperature plastic or polymeric material which is compatible with widely used gold-tin eutectic solder and which can replace the higher cost ceramic used in conventional LED packages. The novel LED package has a high thermal conductivity substrate, a high reflectivity for visible light... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP

20080111149 - Light-emitting diode chip package body and packaging method thereof: AN LED chip package body provides an LED chip with a pad-installed surface, a plurality of pads disposed on the pad-installed surface and a rear surface formed opposite the pad-installed surface. The LED chip package body further has a light-reflecting coating disposed on the pad-installed surface of the LED chip... Agent: Rosenberg, Klein & Lee

20080111147 - Phosphor-converted led devices having improved light distribution uniformity: A New Phosphor-converted LED Device (“NPCLD”) is disclosed. The NPCLD may include a lens over a phosphor body, in which the lens and the phosphor body each have a substantially convex upper surface. The NPCLD may alternatively include first and second lenses, the first lens having a substantially flat interface... Agent: Kathy Manke Avago Technologies Limited

20080111150 - Replaceable through-hole high flux led lamp: The present invention is a through-hole LED light source with capability of emitting a beam angle of less than 75 degrees. The light source presents a three-dimensional lead frame with a well, into which at least one LED is mounted, and an optical housing which serves as a directional lens.... Agent: Geoffrey E. Dobbin, Patent Attorney

20080111151 - Power module, method of producing same, and air conditioner: A power module includes a power semiconductor, a non-power semiconductor, one resin substrate and a cooling device. The power semiconductor and the non-power semiconductor configure a power supply circuit for performing power conversion. Both the power semiconductor and the non-power semiconductor are mounted on the resin substrate. The cooling device... Agent: Global Ip Counselors, LLP

20080111152 - Sub-pixel nbn detector: A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb,... Agent: Peacock Myers, P.c.

20080111153 - Electronic device including a heterojunction region and a process for forming the electronic device: An electronic device can include a first transistor having a first channel region further including a heterojunction region that, in one aspect, is at most approximately 5 nm thick. In another aspect, the first transistor can include a p-channel transistor including a gate electrode having a work function mismatched with... Agent: Larson Newman Abel Polansky & White, LLP

20080111155 - Electronic device including a transistor having a metal gate electrode and a process for forming the electronic device: An electronic device includes an n-channel transistor and a p-channel transistor. The p-channel transistor has a first gate electrode with a first work function and a first channel region including a semiconductor layer immediately adjacent to a semiconductor substrate. In one embodiment, the first work function is less than the... Agent: Larson Newman Abel Polansky & White, LLP

20080111154 - Integration of a sige- or sigec-based hbt with a sige- or sigec-strapped semiconductor device: The present invention provides an integrated semiconductor device that includes a semiconductor substrate, a first device containing a heterojunction bipolar transistor (HBT) located in a first region of the semiconductor substrate, wherein the HBT includes a base region containing a first portion of a SiGe or SiGeC layer, and a... Agent: Scully, Scott, Murphy & Presser, P.c.

20080111156 - High performance fet devices and methods thereof: Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to... Agent: George Sai-halasz

20080111157 - High electron mobility transistor semiconductor device and fabrication method thereof: In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in... Agent: Posz Law Group, Plc

20080111158 - Apparatuses and methods for efficient power rail structures for cell libraries: An integrated circuit has a power rail formed of a first wire in a lower metal layer and a second wire in an upper metal layer and that run in the same direction in their respective layers. A number of vias connect the first and second wires, to form a... Agent: Blakely Sokoloff Taylor & Zafman

20080111159 - Image sensor including spatially different active and dark pixel interconnect patterns: An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical... Agent: Scully, Scott, Murphy & Presser, P.c.

20080111160 - Semiconductor device and interconnect structure: A semiconductor device is described, including a substrate, a transistor, a hard mask layer and an anti-reflection layer. The substrate includes a first area and a second area, wherein the second area includes a photosensing area. The transistor is disposed on the substrate in the first area and the hard... Agent: Jianq Chyun Intellectual Property Office

20080111161 - Protective structure for semiconductor sensors: A protective structure for a semiconductor sensor integrated in a semiconductor substrate for use in a state that is in direct contact with a measuring medium has a semiconducting layer that is applied to the semiconductor substrate, a metal layer and an insulating layer. The insulating layer is disposed between... Agent: Schoppe, Zimmerman , Stockeller & Zinkler

20080111162 - Structure and method for dual surface orientations for cmos transistors: The present invention provides structures and methods for providing facets with different crystallographic orientations than what a semiconductor substrate normally provides. By masking a portion of a semiconductor surface and exposing the rest to an anisotripic etch process that preferentially etches a set of crystallographic planes faster than others, new... Agent: Scully, Scott, Murphy & Presser, P.c.

20080111163 - Field effect transistor with a fin structure: A field effect transistor with a fin structure having a first and a second source/drain region; a body region formed within the fin structure and between the first and the second source/drain region; a metallically conductive region formed within a part of the first source/drain region, the metallically conductive region... Agent: Dickstein Shapiro LLP

20080111164 - Integrated circuit device and method of producing the same: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a... Agent: Staas & Halsey LLP

20080111167 - Method for manufacturing semiconductor device and semiconductor device: Disclosed herein is a method for manufacturing a semiconductor device, the method including the step of forming a gate electrode that contains a metal over a semiconductor substrate with intermediary of a gate insulating film, the step including the sub-steps of, forming a first gate electrode layer that defines a... Agent: Sonnenschein Nath & Rosenthal LLP

20080111166 - Removable spacer: A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that deposits material on the sides of... Agent: Beyer Weaver LLP

20080111165 - Transfer transistor of cmos image sensor: A transfer transistor of a CMOS image sensor is described, including a substrate of a first type, a gate dielectric layer on the substrate, a gate on the gate dielectric layer, a first doped region of the first type, a buried channel region of the first or second type, a... Agent: Jianq Chyun Intellectual Property Office

20080111168 - Transistor and method for manufacturing same: An improved coupling stability between the source region and the source electrode of the transistor is achieved. In the method for manufacturing the MOSFET, the p-type base region is formed in a semiconductor layer, and after the p-type base region is formed in the surface portion of the n+ type... Agent: Young & Thompson

20080111169 - Cmos image sensor devices: A pixel comprises a substrate comprising a first well region formed in a top portion of the substrate, having a first conductivity type. A plurality of shallow trench isolation (STI) structures is formed in the first well region of the substrate, defining a pixel region over the substrate. A second... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080111170 - Low-voltage image sensor and sensing method thereof: Provided are an image sensor and a method of sensing the same. The image sensor includes: a light receiving device; a signal conversion unit including a transfer transistor having a plurality of transfer gates and for converting photocharges generated by the light receiving device into a voltage to output the... Agent: Rabin & Berdo, Pc

20080111171 - Node structures under capacitor in ferroelectric random access memory device and methods of forming the same: In a node structure under a capacitor in a ferroelectric random access memory device and a method of forming the same, top surfaces of the node structures are disposed at substantially the same level as a top surface of an interlayer insulating layer surrounding the node structures, and thus crystal... Agent: Mills & Onello LLP

20080111172 - Semiconductor device and method for manufacturing the same: The present invention provides a method for manufacturing a semiconductor device, including the steps of: forming a first ferroelectric film on a first conductive film by a film-forming method including at least a step of forming a film by a sol-gel method; forming a second ferroelectric film on the first... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080111173 - Semiconductor device and method for manufacturing the same: A ferroelectric capacitor is formed over a semiconductor substrate (10), and thereafter, interlayer insulating films (48, 50, 52) covering the ferroelectric capacitor are formed. Next, a contact hole (54) reaching a top electrode (40) is formed in the interlayer insulating films (48, 50, 52). Next, a wiring (58) electrically connected... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080111174 - Memory device and a method of manufacturing the same: A memory device comprises an array of memory cells, the memory cells being at least partially formed in a semiconductor substrate having a surface, each of the memory cells including an access transistor and a storage capacitor for storing data, the storage capacitor including a first and a second capacitor... Agent: Edell, Shapiro & Finnan, Llc

20080111175 - Method for etching single-crystal semiconductor selective to amorphous/polycrystalline semiconductor and structure formed by same: A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor. The method then includes etching the single-crystal semiconductor sidewalls to widen the of the upper trench portion beyond the... Agent: Law Office Of Delio & Peterson, Llc.

20080111176 - Tunable capacitor: Disclosed are embodiments of a transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080111177 - Non-volatile memory cell and non-volatile memory device using said cell: A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two... Agent: Empk & Shiloh, LLP

20080111178 - Nonvolatile semiconductor memory device and method for manufacturing the same: It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080111179 - Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same: A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having a single gate structure containing a lamination of a third polycrystalline silicon film and... Agent: Pollock, Vande Sande & Priddy

20080111180 - Split gate flash memory device having self-aligned control gate and method of manufacturing the same: In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain... Agent: Mills & Onello LLP

20080111181 - Nonvolatile memory devices, methods of operating the same and methods of forming the same: A nonvolatile memory (NVM) device includes a floating gate on a semiconductor substrate and a gate insulating layer between the semiconductor substrate and the floating gate. A tunnel insulating layer is disposed between the semiconductor substrate and the floating gate. The tunnel insulating layer is thinner than the gate insulating... Agent: Mills & Onello LLP

20080111182 - Forming buried contact etch stop layer (cesl) in semiconductor devices self-aligned to diffusion: A buried contact etch stop layer (CESL) is disposed between adjacent diffusions in a semiconductor device, such as between bitlines in a memory array. The CESL may be self-aligned to the diffusions, and may prevent misaligned bitline (BL) contacts from contacting silicon outside of the corresponding bitlines. The bitline contacts... Agent: Empk & Shiloh, LLP

20080111183 - Flash memory device and method of manufacturing the same: A flash memory device and a method of manufacturing the same comprises source and drain diffusion regions formed at fixed intervals in an active area of a silicon semiconductor substrate, charge storage layers of multi-layers formed on the substrate, and a control gate formed on the charge storage layers, wherein... Agent: Sherr & Nourse, Pllc

20080111184 - Process for fabrication of finfets: A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the... Agent: Scully, Scott, Murphy & Presser, P.c.

20080111185 - Asymmetric multi-gated transistor and method for forming: In one embodiment, there is an asymmetric multi-gated transistor that has a semiconductor fin with a non-uniform doping profile. A first portion of the fin has a higher doping concentration while a second portion of the fin has a lower doping concentration. In another embodiment, there is an asymmetric multi-gated... Agent: Hoffman, Warnick & D'alessandro Llc

20080111186 - Field-effect transistor structure and method therefor: A transistor structure comprising a single-crystal gate conductor disposed on a single-phase high-K dielectric gate dielectric is disclosed. The transistor structure is particularly suitable for fully-depleted silicon-on-insulator electronics.... Agent: Demont & Breyer, Llc

20080111187 - Semiconductor memory device and manufacturing method thereof: This disclosure concerns a semiconductor memory device comprising a semiconductor substrate; a buried insulating film provided on the semiconductor substrate; a semiconductor layer provided on the buried insulating film; an N-type source layer formed in the semiconductor layer; an N-type drain layer formed in the semiconductor layer; a body region... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080111189 - Hybrid crystallographic surface orientation substrate having one or more soi regions and/or bulk semiconductor regions: A substrate for a semiconductor device is disclosed including, in one embodiment, a plurality of semiconductor-on-insulator (SOI) wafers bonded to one another in a single stack. A distal end of the stack includes a first SOI region with a first semiconductor layer having a thickness and a first surface orientation.... Agent: Hoffman, Warnick & D'alessandro Llc

20080111188 - Integrated circuit structure and method of manufacturing a memory cell: An integrated circuit structure is formed on a substrate. The integrated circuit structure includes a logic area and a memory cell area. The memory cell area includes a charge storage area and a non-charge storage area. A dielectric layer is formed on the substrate in the charge storage area. A... Agent: North America Intellectual Property Corporation

20080111190 - Integration of a floating body memory on soi with logic transistors on bulk substrate: A method and the resultant memory is described for forming an array of floating body memory cells and logic transistors on an SOI substrate. The floating bodies for the cells are formed over the buried oxide, the transistors in the logic section are formed in the bulk silicon.... Agent: Intel/blakely

20080111191 - Electronic circuit, electronic device, method of driving electronic device, electro-optical device and electronic apparatus: An electronic circuit that drives a driven element to which driving voltage or driving current is supplied. The electronic circuit includes a signal line, a unit circuit connected to the signal line, and a voltage supply line. The unit circuit includes a driving transistor, a switching element, and a capacitive... Agent: Oliff & Berridge, Plc

20080111192 - High-voltage-withstanding semiconductor device and fabrication method thereof: There is provided a high-voltage-withstanding semiconductor device a fabrication method thereof capable of suppressing Vt fluctuation induced by plasma damage in a via hole forming step. In the high-voltage-withstanding semiconductor device, a gate electrode of a transistor having a gate insulating film formed on a semiconductor substrate and having a... Agent: Volentine & Whitt Pllc

20080111193 - Serpentine ballasting resistors for multi-finger esd protection device: This invention discloses a ballasting resistor for an electrostatic discharge (ESD) device that comprises at least one first active region forming a source/drain of an ESD discharge transistor, at least one resistive element with a serpentine shape formed in a single layer of a semiconductor structure, wherein the resistive element... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20080111194 - Semiconductor device including a finfet: A FinFET includes a silicon layer deposited on a silicon substrate and configuring source/drain regions and a channel region. The gate of the FinFET includes a pair of first electrode layers sandwiching therebetween the channel region in the horizontal direction with an intervention of first gate insulation films, and a... Agent: Young & Thompson

20080111195 - Multi-gate field effect transistor: A planar, double-gate transistor structure comprising upper and lower gate stacks that each comprises a single-phase high-K dielectric gate dielectric is disclosed. The transistor structure is particularly suitable for fully-depleted silicon-on-insulator electronics having gate-lengths less than 65 nm.... Agent: Demont & Breyer, Llc

20080111196 - Semiconductor device having a contact pad: A DRAM device includes contact pads having a bottom in contact with a corresponding source/drain region 21 and a top in contact with a bottom of an overlying contact plug. The source/drain region has a recess caused by misalignment of the contact pad with respect to the source/drain region, the... Agent: Mcginn Intellectual Property Law Group, Pllc

20080111197 - Semiconductor device including a misfet having divided source/drain regions: A MISFET includes source/drain regions each including a plurality of divided substrate regions divided by intervening insulation films, and a selectively-grown silicon layer formed on the divided substrate regions and intervening insulation film to electrically couple together the divided substrate regions. The resultant MISFET has a reduced junction capacitance across... Agent: Scully Scott Murphy & Presser, Pc

20080111198 - Stacked semiconductor device and method of manufacturing the same: A stacked semiconductor device includes a first gate structure formed on a substrate, a first insulating interlayer covering the first gate structure on the substrate, a first active pattern formed through and on the first insulating interlayer and contacting the substrate, a second gate structure formed on the first active... Agent: Mills & Onello LLP

20080111199 - Semiconductor device having a pair of fins and method of manufacturing the same: Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins... Agent: Harness, Dickey & Pierce, P.L.C

20080111200 - Forming conductive stud for semiconductive devices: Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact area of the semiconductor device, the opening being away from... Agent: International Business Machines Corporation Dept. 18g

20080111201 - Semiconductor device and method for manufacturing the same: Provided is a method for manufacturing a semiconductor device. In the method, a gate oxide layer, a gate polysilicon layer, and a capping oxide layer are sequentially formed on a semiconductor substrate. A photoresist pattern is formed on the capping oxide layer. The capping oxide layer, gate polysilicon layer, and... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080111202 - Forming conductive stud for semiconductive devices: Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact area of the semiconductor device, the opening being away from... Agent: International Business Machines Corporation Dept. 18g

20080111203 - Wafer-level packaging of micro devices: An encapsulated device includes a micro device on a substrate, a cover bonded to the substrate thereby forming a chamber to encapsulate the micro device, and a desiccant material on the cover and in the chamber. An anti-stiction material is absorbed in the desiccant material.... Agent: Fish & Richardson P.c.

20080111204 - Image sensor and method for manufacturing the same: A method for manufacturing an image sensor includes forming first to third photodiodes and first to third color filters corresponding thereto; forming a photoresist film including photosensitive materials on the upper surfaces of the first to third color filters; forming a first exposed part by exposing the photoresist film with... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080111205 - Photodiode: A photodiode that can separately detect the intensities of the three wavelength ranges of ultraviolet light of 400 nm or below includes an insulating layer; and a plurality of silicon semiconductor layers having different thicknesses formed on the insulating layer, wherein each of the plurality of silicon semiconductor layers has... Agent: Rabin & Berdo, Pc

20080111206 - Substrate with two sided doping and method of producing the same: A method of processing a substrate having first and second surfaces applies a first dopant in liquid form on the first surface of the substrate, and applies a second dopant in liquid form on the second surface of the substrate. The method then causes the first and second dopants to... Agent: Bromberg & Sunstein LLP

20080111207 - High-voltage semiconductor device and method of fabricating the same: A high-voltage semiconductor device includes a semiconductor layer having a plurality of pillars of a first conductivity type defined by a plurality of trenches which extend from a top surface of the semiconductor layer toward a bottom surface thereof. A charge compensation layer of a second conductivity type is disposed... Agent: Townsend And Townsend And Crew, LLP

20080111208 - Semiconductor devices having a gate electrode and methods of fabricating the same: An integrated circuit device includes an integrated circuit substrate and a first gate pattern on the substrate. A non-conductive barrier layer pattern is on the first gate pattern. The barrier layer pattern has openings at selected locations therein extending to the first gate pattern. A second gate pattern is on... Agent: Myers Bigel Sibley & Sajovec

20080111209 - Semiconductor device and its manufacturing method: A semiconductor device includes: a first element isolation film that is formed by a LOCOS oxidation method on a semiconductor substrate for isolating a first element region from other regions; a second element isolation film embedded in a groove formed in the semiconductor substrate for isolating a second element region... Agent: Oliff & Berridge, Plc

20080111210 - Antifuse structure having an integrated heating element: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a... Agent: Scully, Scott, Murphy & Presser, P.c.

20080111212 - Capacitance structure of a semiconductor device and method for manufacturing the same: A capacitance structure of a semiconductor device and a method for manufacturing the structure are provided. The capacitance structure comprises a plurality of capacitance elements and a plurality of supports. Each of the capacitance elements has a column, and each of the supports is disposed between two adjacent columns by... Agent: Nixon Peabody LLP - Patent Group

20080111211 - On-chip capacitors for addressing power supply voltage drops: Herein described are at least a layout of an integrated circuit chip that is resistant to the negative effects of IR power supply voltage drops and a method of implementing the integrated circuit chip. The integrated circuit chip layout comprises one or more capacitors positioned in between adjacent functional blocks.... Agent: Mcandrews Held & Malloy, Ltd

20080111213 - Through-wafer interconnects for photoimager and memory wafers: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and... Agent: Perkins Coie LLP Patent-sea

20080111214 - Hybrid orientation substrate and method for fabrication thereof: A method for fabricating a hybrid orientation substrate provides for: (1) a horizontal epitaxial augmentation of a masked surface semiconductor layer that leaves exposed a portion of a base semiconductor substrate; and (2) a vertical epitaxial augmentation of the exposed portion of the base semiconductor substrate. The resulting surface semiconductor... Agent: Scully, Scott, Murphy & Presser, P.c.

20080111216 - Component arrangement comprising a carrier: A component arrangement comprising a carrier, a component in a housing with electrical contacts and a moulding compound that encloses the carrier, the semiconductor component in the housing and the electrical contacts, wherein the component is applied on the carrier, and wherein the carrier is provided with holes, and a... Agent: Infineon Technologies Ag Patent Department

20080111215 - Integrated circuit package system: An integrated circuit package system is provided including forming an external interconnect having a lead body and a lead tip, forming a lead protrusion in the lead tip, connecting a device and the external interconnect, and encapsulating the device and the external interconnect.... Agent: Law Offices Of Mikio Ishimaru

20080111217 - Integrated circuit package system with heat sink: An integrated circuit package system is provided including forming a paddle, forming a ring with a recess in the paddle, mounting a device in the recess, forming a slot in the ring, and mounting a heat sink in the slot over the device.... Agent: Law Offices Of Mikio Ishimaru

20080111220 - Electronic assembly and circuit board: A circuit board assembled with an electronic package having a first and a second inner leads is provided. The first inner lead has a first and a second ends. The circuit board includes an insulating layer, a first pad, a second pad, an extension portion, a conductive via, and a... Agent: J C Patents, Inc.

20080111218 - Integrated circuit package system with encapsulation lock: An integrated circuit package system is provided including forming a paddle having holes with a hole size in a range about tens to hundreds of micrometers, mounting a device over the paddle, and filling an encapsulation in the holes.... Agent: Law Offices Of Mikio Ishimaru

20080111219 - Package designs for vertical conduction die: Embodiments in accordance with the present invention relate to packaging designs for vertical conduction semiconductor devices which include low electrical resistance contacts with a top surface of the die. In one embodiment, the low resistance contact may be established by the use of Aluminum ribbon bonding with one side of... Agent: Townsend And Townsend And Crew, LLP

20080111221 - Radiation hardened lateral mosfet structure: A power MOSFET is provided on a semiconductor die to withstand radiation exposure. The semiconductor die is mounted on a die flag of a leadframe. The MOSFET includes a substrate and epitaxial layer formed over the substrate. A source region is formed in a surface of the semiconductor die. The... Agent: Quarles & Brady LLP

20080111222 - Bridge stack integrated circuit package system: An integrated circuit package system is provided including mounting a first device on a carrier, mounting a second device over the first device and the carrier in an offset face-to-face configuration, and connecting the first device and the second device at an overlap.... Agent: Law Offices Of Mikio Ishimaru

20080111223 - Wafer level chip size packaged chip device with a double-layer lead structure and method of fabricating the same: The present invention disclosed a wafer level chip size packaged chip device with a double-layer lead structure and methods of fabricating the same. The double-layer lead is designed to meet a tendency of increasing quantity per area of peripheral arrayed compatible pads on a semiconductor chip, and also to save... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.a.

20080111226 - Integration using package stacking with multi-layer organic substrates: Example embodiments of the invention may provide for a multi-package system. The multi-package system may include a first package having a plurality of first organic dielectric layers, where the first package includes at least one first conductive layer positioned between two of the plurality of first organic dielectric layers, and... Agent: Sutherland Asbill & Brennan LLP

20080111224 - Multi stack package and method of fabricating the same: Embodiments of the present invention provide a MSP having an upper and lower package, with a recess opening in the substrate of the upper package. The upper package may also include multiple stacked semiconductor chips. A lower package may include a substrate and at least one semiconductor chip. During assembly,... Agent: Volentine & Whitt Pllc

20080111225 - Semiconductor device package: Provided is a semiconductor device package. The semiconductor device package includes: stacked semiconductor chips having bonding pads; a PCB (printed circuit board) mounting the stacked semiconductor chips thereon, and including bonding electrodes that correspond to the bonding pads; and interposers respectively covering the stacked semiconductor chips and interposed between the... Agent: Marger Johnson & Mccollom, P.c.

20080111227 - Semiconductor package structure for vertical mount and method: In one embodiment, a semiconductor package structure includes a plurality of upright clips having ends with mounting surfaces for vertically mounting the package to a next level of assembly. A semiconductor chip is interposed between the upright clips together with one or more spacers.... Agent: Mr. Jerry Chruma Semiconductor Components Industries, L.l.c.

20080111229 - Semiconductor package and method for manufacturing the same: Provided are a semiconductor package and a method for manufacturing the same. The semiconductor package includes: a substrate having a top surface on which a lead is formed and a bottom surface opposite to the top surface; a semiconductor chip attached to the top surface of the substrate and having... Agent: Marger Johnson & Mccollom, P.c.

20080111228 - Wafer level chip size packaged chip device with an n-shape junction inside and method of fabricating the same: The present invention provide a wafer level chip size packaged chip device with a N-shape junction at which external leads electrically connect to peripheral arrayed compatible pads and a method of fabricating the same. In the wafer level chip size package, with such an n-shape junction instead of a conventional... Agent: Allen Dyer Doppelt Milbrath And Gilchrist Pa 1401 Citrus Ctr.

20080111230 - Wiring film having wire, semiconductor package including the wiring film, and method of fabricating the semiconductor package: A wiring film including wires, a semiconductor package including the wiring film, and a method of fabricating the semiconductor package are provided. The wiring film comprises a base film and first wires arranged on a first surface of the base film. First bumps are respectively positioned at ends of the... Agent: Marger Johnson & Mccollom, P.c.

20080111231 - Semiconductor device comprising a housing and a semiconductor chip partly embedded in a plastic housing composition, and method for producing the same: One aspect of the invention relates to a semiconductor device including a housing and a semiconductor chip partly embedded in a plastic housing composition. Another aspect relates to a method for producing the same. The plastic housing composition has at least one host component having a softening temperature and an... Agent: Dicke, Billig & Czaja

20080111232 - Semiconductor package: A semiconductor package that includes a conductive clip having an interior surface that includes a plurality of spaced raised portions, a semiconductor device having a first major surface that includes a plurality of spaced depressions each receiving one of the raised portions in the interior thereof, and a conductive adhesive... Agent: Ostrolenk Faber Gerb & Soffen

20080111233 - Semiconductor package with embedded die: A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar... Agent: Klarquist Sparkman, LLP

20080111234 - Electronic assembly with hot spot cooling: A composite of two or more thermal interface materials (“TIMs”) is placed between a die and a heat spreader to improve cooling of the die in an integrated circuit package. The two or more TIMs vary in heat-dissipation capability depending upon the locations of die hot spots. In an embodiment,... Agent: Schwegman, Lundberg & Woessner, P.a.

20080111235 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor package, a circuit board and an interval maintaining member. The semiconductor package has a body and a lead protruded from the body. The circuit board has a first land electrically connected to the lead. The interval maintaining member is interposed between the circuit board... Agent: Mills & Onello LLP

20080111236 - Low fabrication cost, high performance, high reliability chip scale package: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is... Agent: Megica Corporation

20080111237 - Semiconductor device manufactured using an electrochemical deposition process for copper interconnects: A method of manufacturing a semiconductor device that comprises forming an insulating layer over a semiconductive substrate 110 and forming a copper interconnect. Forming the interconnect includes etching an interconnect opening in the insulating layer and filling the opening with copper plating. Filling with copper plating includes using a first... Agent: Texas Instruments Incorporated

20080111238 - Integrated circuit processing system: An integrated circuit processing system is provided including providing a substrate having an integrated circuit, forming an interconnect layer over the integrated circuit, applying a low-K dielectric layer over the interconnect layer, applying an ultra low-K dielectric layer over the low-K dielectric layer, forming an opening through the ultra low-K... Agent: Law Offices Of Mikio Ishimaru

20080111239 - Interconnect structure having enhanced electromigration reliabilty and a method of fabricating same: An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner at least partially within a metal interconnect. In one embodiment, a “U-shaped” EM preventing liner is provided that abuts... Agent: Scully, Scott, Murphy & Presser, P.c.

20080111241 - Semiconductor device and manufacturing method thereof: The present invention provides a semiconductor device which is characterized as follows. The semiconductor device includes: an interlayer insulating film formed above a semiconductor substrate and provided with a hole above an impurity diffusion region; a conductive plug formed in the hole and electrically connected to the impurity diffusion region;... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080111240 - Semiconductor device and method for fabricating the same: A semiconductor device and fabricating method thereof are provided. A carbon interconnection line can be formed on an interlayer insulating layer such that the carbon interconnection line is electrically connected to a conductive metal layer disposed in a contact hole of the semiconductor device.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080111242 - Integrated circuit chips with fine-line metal and over-passivation metal: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node... Agent: John Chen

20080111243 - High performance system-on-chip using post passivation process: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting... Agent: Mou-shiung Lin

20080111244 - Copper-metallized integrated circuits having an overcoat for protecting bondable metal contacts and improving mold compound adhesion: A semiconductor device having copper interconnecting metallization (111) protected by a first (102) and a second (120) overcoat layer (homogeneous silicon dioxide), portions of the metallization exposed in a window (103) opened through the thicknesses of the first and second overcoat layers. A patterned conductive barrier layer (130) is positioned... Agent: Texas Instruments Incorporated

20080111245 - Electric element, memory device, and semiconductor integrated circuit: An electric element includes a first electrode (1), a second electrode (3), and a variable-resistance film (2) connected between the first electrode (1) and the second electrode (3). The variable-resistance film (2) contains Fe (iron) and O (oxygen) as constituent elements. The content of oxygen in the variable-resistance film (2)... Agent: Mcdermott Will & Emery LLP

20080111246 - Method and apparatus for strapping two polysilicon lines in a semiconductor integrated circuit device:

20080111247 - Electronic device and method of fabricating the same: There is provided a method of fabricating an electronic device including flip-chip mounting a device chip on a substrate, and supplying solder between adjacent device chips by supplying the solder on the device chips and applying heat and pressure on the solder, and a contact angle of the device chip... Agent: Arent Fox LLP

20080111248 - Flip chip and wire bond semiconductor package: A semiconductor package (100, 150, 200, 250), and method of forming the package, including a substrate (102, 102′, 202, 202′) having an opening (104, 104′, 204, 204′) formed therein. Contact pads (112, 112′, 212, 212′) are formed about a periphery of the opening on a first side of the substrate... Agent: Freescale Semiconductor, Inc. Law Department

20080111249 - Semiconductor device and method for manufacturing same: In conventional semiconductor devices, an insufficient supply of the resin to the end portions of the components that should be encapsulated is caused, resulting in an insufficient permeation of the resin into gaps between the components and the substrate, causing a spreading resin-wet. A semiconductor device 1 includes a mounting... Agent: Young & Thompson

20080111250 - Structure and method for enhancing resistance to fracture of bonding pads: The present invention provides bond pads structures between semiconductor integrated circuits and the chip package with enhanced resistance to fracture and improved reliability. Mismatch in the coefficient of temperature expansion (CTE) among the materials used in bond structures induces stress and shear on them that may result in fractures within... Agent: Scully, Scott, Murphy & Presser, P.c.

20080111251 - Method of manufacturing an electronic component comprising an integrated circuit and a winding assembly: A method of manufacturing an electronic component comprising an integrated circuit and a core, includes the steps of providing the integrated circuit having at least two accessible contacts, providing the core, assembling the integrated circuit and the core together by means of an adhesive substance, winding a wire on the... Agent: Griffin & Szipl, Pc

20080111252 - Low loop height ball bonding method and apparatus: In accordance with the invention, a bump is formed on top of a die bond pad by forming a ball bond there. Then, without severing the wire, the capillary undergoes a set of coordinated motions to fold the wire on top of the ball bond. The wire is then bonded... Agent: Kulicke And Soffa Industries, Inc.

20080111253 - Integrated circuit having a distributed network of landing pads: An electrical device comprising an integrated circuit (IC) having an uppermost layer that includes landing pads that are distributed throughout one side of the IC.... Agent: Texas Instruments Incorporated

20080111254 - Pattern film, method of manufacturing the pattern film, and printed circuit board and semiconductor package having the pattern film: A pattern film in accordance with one aspect of the present invention includes a first film and a second film. A first pattern array is built in the first film. The second film is attached to the first film. Further, a second pattern array is built in the second film.... Agent: Marger Johnson & Mccollom, P.c.

20080111255 - Semiconductor integrated circuit and multi-chip module: In a semiconductor integrated circuit requiring a large number of pads, an internal circuit is arranged in the center portion, and a plurality of two kinds of I/O circuits for inputting and outputting signals from and to the outside and many pads are arranged along four sides of the semiconductor... Agent: Mcdermott Will & Emery LLP

20080105863 - Light emitting diode and manufacturing method of the same: A light emitting diode comprises a permanent substrate having a chip holding space formed on a first surface of the permanent substrate; an insulating layer and a metal layer sequentially formed on the first surface of the permanent substrate and the chip holding space, wherein the metal layer further comprises... Agent: Wpat, PC

20080105864 - Ferroelectric memory device and method for manufacturing the same: Disclosed relates to a ferroelectric memory device that is manufactured easily, operates at low voltage and has excellent data preservation period, and a method of manufacturing the same. In the present invention, a ferroelectric layer (60) is formed on a part corresponding to a channel region (4) on the silicon... Agent: Bruce E. Lilling Lilling & Lilling PLLC

20080105866 - Method of fabricating organic thin film transistor using self assembled monolayer-forming compound containing dichlorophosphoryl group: Disclosed is a method of fabricating an organic thin film transistor including a substrate, a gate electrode, a gate insulating layer, metal oxide source/drain electrodes, and an organic semiconductor layer, in which the surface of the metal oxide source/drain electrodes or of the metal oxide source/drain electrodes and gate insulating... Agent: Harness, Dickey & Pierce, P.L.C

20080105865 - Pyrene based compound and light emitting transistor element using the same: (wherein R1 represents a group selected from a heteroaryl group which may have a substituent, an aryl group which may have a substituent except a phenyl group which does not have any substituent, an alkyl group which may have a substituent and has a main chain having 1 to 20... Agent: Wenderoth, Lind & Ponack, L.L.P.

20080105869 - Printed circuit board for mounting semiconductor device package, and method of testing and fabricating semiconductor device package using the same: Provided is a printed circuit board for a semiconductor device. The printed circuit board includes an upper surface ball out structure configured the same as a ball array of a semiconductor device package mounted on the upper surface of the printed circuit board, and a lower surface ball out structure... Agent: Marger Johnson & Mccollom, P.C.

20080105870 - Two-terminal switching devices and their methods of fabrication: Two-terminal switching devices characterized by high on/off current ratios and by high breakdown voltage are provided. These devices can be employed as switches in the driving circuits of active matrix displays, e.g., in electrophoretic, rotataing element and liquid crystal displays. The switching devices include two electrodes, and a layer of... Agent: Beyer Weaver LLP

20080105871 - Thin film transistor array substrate having lightly doped amorphous silicon layer and method for fabricating same: An exemplary thin film transistor (TFT) array substrate (200) includes: a substrate (210), a gate electrode (220) disposed on the substrate, a gate insulating layer (230) disposed on the substrate having the gate electrode, a lightly doped amorphous silicon (a-Si) layer (241) disposed on the gate insulating layer, a first... Agent: Wei Te Chung Foxconn International, Inc.

20080105872 - Pixel structure: A pixel structure is provided. A scan line is disposed on a substrate and a gate insulating layer is disposed thereon. A semiconductor layer is disposed on the gate insulating layer and a data line, a source electrode and a drain electrode are disposed thereon. The source electrode and the... Agent: Jianq Chyun Intellectual Property Office

20080105873 - Tft lcd array substrate and manufacturing method thereof: A TFT LCD array substrate and a manufacturing method thereof. The TFT LCD array substrate comprises a substrate. A gate line and a gate electrode that is formed integrally with the gate line are formed on the substrate. A first insulating layer and a semiconductor layer are formed sequentially on... Agent: Hasse & Nesbitt LLC

20080105874 - Thin film transistor, manufacturing method thereof, and tft lcd using the same: A thin film transistor (TFT) that comprises a gate electrode on a substrate, a gate insulation layer on the gate electrode, an active layer having a source region, a drain region, and a channel region on the gate insulation layer, and a source electrode and a drain electrode formed over... Agent: Hasse & Nesbitt LLC

20080105875 - Method for forming pattern, thin film transistor, display device and method for manufacturing the same, and television device: A method for forming a pattern according to the invention comprises the steps of: forming a mask over a substrate having light-transmitting properties; forming a first region having a substance including a light-absorbing material over the substrate and the mask; forming a second region by irradiating the substance with light... Agent: Nixon Peabody, LLP

20080105878 - Semiconductor storage device and method of manufacturing the same: A nonvolatile semiconductor storage device is provided in which memory cells comprising PN junction diodes having satisfactory rectifying characteristics are arranged in three dimensions. The semiconductor storage device includes: a first wire which extends in one direction; a second wire which extends in a direction intersecting the first wire; and... Agent: Mcginn Intellectual Property Law Group, PLLC

20080105882 - Surface textured leds and method for making the same: A light-emitting device that includes an LED and a light extraction layer and the method for making the same are disclosed. The LED includes a substrate on which an active layer is sandwiched between a p-type layer and an n-type layer, the active layer generating light in a band of... Agent: Kathy Manke Avago Technologies Limited

20080105884 - Light-emitting diode: A light-emitting diode comprises: a coupling base; several light-emitting chips; and an adhesive for sealing the coupling base, wherein the coupling base has a coupling part and at least two frame pairs mounted therein. The light-emitting chips are fixed on the coupling part. The light-emitting chips are electrically connected with... Agent: Troxell Law Office PLLC Suite 1404

20080105888 - Light-emitting diode package structure: A light-emitting diode (LED) package structure including a lead frame, an LED chip, and a circuit board is provided. The lead frame includes a first lead and a second lead. The LED chip is disposed on the first lead and electrically connected to the first lead and the second lead.... Agent: Jianq Chyun Intellectual Property Office

20080105889 - Nitride semiconductor light emitting device and method of manufacturing the same: There are provided a method of manufacturing a nitride semiconductor light emitting device and the nitride semiconductor light emitting device manufactured by the method, the method including: forming a light emitting structure by sequentially growing a first conductivity nitride layer, an active layer and a second conductivity type nitride layer... Agent: Mcdermott Will & Emery LLP

20080105887 - Package design for producing white light with short-wavelength leds and down-conversion materials: A broad bandwidth light source including: a solid state light emitting device that generates short wavelength light; and quantum dot material and phosphor material that are each irradiated by some of the short wavelength light. The short wavelength light has a spectrum with a first peak wavelength shorter than about... Agent: Ratnerprestia

20080105886 - Semiconductor component emitting electromagnetic radiation and component housing: An optoelectronic component includes a component housing and a body comprising a carrier substrate and a radiation emitting layer sequence. In certain embodiments, the body is arranged in a reflector cup of the component housing and is electrically conductively connected to external electrical leads of the component housing. The component... Agent: Fish & Richardson PC

20080105891 - Method for determining self-heating free i-v characterstics of a transistor: According to one exemplary embodiment, a method for determining a self-heating free drain current in a transistor corresponding to a channel temperature not affected by a drain DC current includes measuring at least three unique drain currents of a transistor corresponding to at least three unique ambient temperatures. The method... Agent: Farjami & Farjami LLP

20080105861 - Multi-value recording phase-change memory device, multi-value recording phase-change channel transistor, and memory cell array: A multi-value recording phase-change memory device that can stably record multi-value information, and that can reproduce information with high reliability, comprises a first electrode layer 26, a second electrode layer 28, and a memory layer 30 provided between the first and second electrode layers 26 and 28 and containing a... Agent: Staas & Halsey LLP

20080105862 - Thin film fuse phase change ram and manufacturing method: A memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080105867 - Compositons of electrically conductive polymers and non-polymeric fluroinated organic acids: Compositions are provided comprising at least one conductive polymer and at least one non-polymeric fluorinated organic acid, salt or ester, wherein the conductive polymer is selected from a polythiophene, a polypyrrole, a polyaniline, and combinations thereof. Electronic devices and applications having at least one layer comprising such compositions are further... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20080105868 - Organic semiconductor device, process for producing the same, and organic semiconductor apparatus: The present invention provides an organic semiconductor device, which can be produced uniformly on a large substrate, having a high mobility and capable of greatly modulating the drain current by varying the voltage applied to a gate electrode. The present invention provides an organic semiconductor device having at least a... Agent: Fitzpatrick Cella Harper & Scinto

20080105877 - Display device and manufacturing method thereof: A display device with improved reliability and a manufacturing method of the same with improved yield. A display device according to the invention comprises a display area including a first electrode, an insulating layer covering an edge of the first electrode, a layer containing an organic compound, which is formed... Agent: Eric Robinson

20080105876 - Thin film transistor and manufacturing method thereof: A method for manufacturing a thin film transistor is provided. In the method, a gate electrode is formed on a substrate. A crystalline gate insulating layer is formed on an entire surface of the substrate having the gate electrode formed thereon. A microcrystalline silicon layer and a doped amorphous silicon... Agent: Brinks Hofer Gilson & Lione

20080105879 - Process and system for laser annealing and laser-annealed semiconductor film: In a laser annealing process for transforming a noncrystalline semiconductor film into a laterally-crystallized film: irradiation of a region with laser light and a shift of the position of the region to be irradiated are repeated, where the shift is made so that each region to be irradiated contains a... Agent: Sughrue Mion, PLLC

20080105881 - Compound semiconductor substrate grown on metal layer, method for manufacturing the same, and compound semiconductor device using the same: The present invention relates to a compound semiconductor substrate and a method for manufacturing the same. The present invention provides the manufacturing method which coats spherical balls on a substrate, forms a metal layer between the spherical balls, removes the spherical balls to form openings, and grows a compound semiconductor... Agent: Greer, Burns & Crain

20080105880 - Silicon nitride passivation with ammonia plasma pretreament for improving reliability of algan/gan hemts: This invention pertains to an electronic device and to a method for making it. The device is a heterojunction transistor, particularly a high electron mobility transistor, characterized by presence of a 2 DEG channel. Transistors of this invention contain an AlGaN barrier and a GaN buffer, with the channel disposed,... Agent: Naval Research Laboratory Associate Counsel (patents)

20080105883 - Method and system for electrically coupling a chip to chip package: A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the chip and the chip package have at least one such converter physically disposed on them. Each... Agent: Karen Lenaburg, Esq. Dorsey & Whitney LLP

20080105885 - Light-emitting device: A light-emitting device includes a first compound semiconductor layer, an active layer, and a second compound semiconductor layer; a second electrode formed on the second compound semiconductor layer; an insulating layer covering the second electrode; a first opening provided to pass through the insulating layer, the second electrode, the second... Agent: Sonnenschein Nath & Rosenthal LLP

20080105890 - Reflective electrode and compound semiconductor light emitting device including the same: Provided are a reflective electrode and a compound semiconductor light emitting device, such as an LED or an LD, including the same. The reflective electrode, which is formed on a p-type compound semiconductor layer, includes: a first electrode layer forming an ohmic contact with the p-type compound semiconductor layer; a... Agent: Buchanan, Ingersoll & Rooney PC

20080105892 - Light-emitting diode chip package body and packaging method thereof: AN LED chip package body provides an LED chip with a pad-installed surface, a plurality of pads disposed on the pad-installed surface and a rear surface formed opposite the pad-installed surface. The LED chip package body further has a light-reflecting coating disposed on the pad-installed surface of the LED chip... Agent: Rosenberg, Klein & Lee

20080105893 - Light-emitting diode chip package body and packaging method thereof: AN LED chip package body provides an LED chip with a pad-installed surface, a plurality of pads disposed on the pad-installed surface and a rear surface formed opposite the pad-installed surface. The LED chip package body further has a light-reflecting coating disposed on the pad-installed surface of the LED chip... Agent: Rosenberg, Klein & Lee

20080105894 - Semiconductor device: A semiconductor device for adequately removing heat generated by a semiconductor element is provided. A semiconductor device 100 is equipped with a substrate 2, having a bottom surface 2b and an element mounting surface 2a which is positioned on the opposite side of bottom surface 2b, and a semiconductor element... Agent: Darby & Darby P.C.

20080105895 - Thyristor semiconductor device and switching method thereof: The objective of this invention is to provide a semiconductor device having a thyristor that can shorten the turn-off time. A first electroconductive type first semiconductor region 20 is formed on a substrate, and a second electroconductive type second semiconductor region 22, a second electroconductive type third semiconductor region 23,... Agent: Texas Instruments Incorporated

20080105896 - Power semiconductor module: A power semiconductor module of the present invention comprises: a heat sink 1; a circuit substrate 2 mounted on the heat sink 1; a conductive pattern 10 provided on the circuit substrate 2; a low dielectric constant film 11 covering the conductive pattern 10; a case 7 provided on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080105898 - Fet channel having a strained lattice structure along multiple surfaces: A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and... Agent: Harrington & Smith, PC

20080105897 - Structure and method of fabricating finfet with buried channel: A method of manufacturing a fin structure comprises forming a first structure of a first material type on a wafer and forming a buried channel of a second material adjacent sidewalls of the first structure. The second material type is different than the first material type. The structure includes a... Agent: Greenblum & Bernstein, P.L.C

20080105899 - Semiconductor device with epitaxially grown layer and fabrication method: A fabrication method and a related semiconductor device are disclosed. The method includes; forming a gate structure on a semiconductor substrate, the gate structure comprising a stacked combination a gate dielectric pattern, a gate, a capping layer pattern and an epitaxial blocking layer pattern, forming sidewall spacers on the gate... Agent: Volentine & Whitt PLLC

20080105900 - Fet channel having a strained lattice structure along multiple surfaces: A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and... Agent: Harrington & Smith, PC

20080105901 - Atomic layer deposition in the formation of gate structures for iii-v semiconductor: A semiconductor structure and method wherein a recess is disposed in a surface portion of a semiconductor structure and a dielectric film is disposed on and in contract with the semiconductor. The dielectric film has an aperture therein. Portions of the dielectric film are disposed adjacent to the aperture and... Agent: Raytheon Company C/o Daly, Crowley, Mofford & Durkee, LLP

20080105902 - Rectifier: In the rectifier, a barrier layer and a channel layer constitute a heterojunction portion, and a two-dimensional electron gas channel is generated in the vicinity of a boundary between the channel layer and the barrier layer. A Schottky gate electrode is connected to an anode ohmic electrode and extends from... Agent: Birch Stewart Kolasch & Birch

20080105903 - Group iii nitride based semiconductor and production method therefor: A GaN layer 2 is epitaxially grown on a sapphire substrate 1 having C-plane as a main plane (FIG. 1A). Then, the layer is wet-etched by use of a 25% aqueous TMAH solution at 85° C. for one hour, to thereby form an etch pit 4 (FIG. 1B) Then, a... Agent: Mcginn Intellectual Property Law Group, PLLC

20080105904 - Method for variability constraints in design of integrated circuits especially digital circuits which includes timing closure upon placement and routing of digital circuit or network: In a standard cell, dummy transistors have p-type and n-type dummy gate electrodes. The dummy transistors are in an OFF state all the time. The gate length of each of the dummy gate electrodes is extended over an end portion of a diffusion region toward the inside of the standard... Agent: Mcdermott Will & Emery LLP

20080105905 - High-quality cmos image sensor and photo diode: Provided are a high-quality CMOS image sensor and a photo diode, which can be fabricated in sub-90 nm regime using nanoscale CMOS technology. The photo diode includes: a p-type well; an internal n-type region formed under a surface of the p-type well; and a surface p-type region including a highly... Agent: Ladas & Parry LLP

20080105907 - Semiconductor chip, semiconductor device and methods for producing the same: A semiconductor chip (1) is provided having an adhesion-promoting-layer-free three-layer metallization (2). The three-layer metallization (2) has an aluminum layer (4) applied directly on the semiconductor chip (1), a diffusion barrier layer (5) applied directly on the aluminum layer (4), and a solder layer (6) applied directly on the diffusion... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20080105906 - Solid state imaging apparatus method for fabricating the same and camera using the same: A solid state imaging apparatus includes a plurality of photoelectric conversion sections formed in an imaging area of a silicon substrate, and an embedded layer embedded in an isolation trench formed in at least one part of the silicon substrate located around the photoelectric conversion sections. The embedded layer is... Agent: Mcdermott Will & Emery LLP

20080105908 - Image sensor and method of forming the same: An image sensor and a method of forming the same includes a semiconductor substrate including a light receiving area and an optical black area defined by a boundary between them; photodiodes in at least one of the light receiving area and the optical black area of the semiconductor substrate; an... Agent: Mills & Onello LLP

20080105909 - Pixel circuit included in cmos image sensors and associated methods: Example embodiments relate to a pixel structure of a CMOS image sensor, and associated methods. The pixel structure may include a substrate of a first-conductivity, a photodiode region of a second conductivity in the first-conductivity substrate, and a capacitor electrode on the second-conductivity photodiode region.... Agent: Lee & Morse, P.C.

20080105910 - Field effect transistor and semiconductor device, and method for manufacturing same: Current drive efficiency is deteriorated in the conventional FET. The FET 20 includes an electrode film 24a provided over the semiconductor substrate 10 and a stressor film 24b that is provided on the electrode film 24a and constitutes a gate electrode 24 together with the electrode film 24a. Each of... Agent: Young & Thompson

20080105911 - Semiconductor device and method for manufacturing the same: A ferroelectric capacitor (42) is formed over a semiconductor substrate (10), and thereafter, a barrier film (46) directly covering the ferroelectric capacitor (42) is formed. Then, an interlayer insulating film (48) is formed and flattened. Then, an inclined groove is formed in the interlayer insulating film (48), and a barrier... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080105912 - Semiconductor memory device: A semiconductor memory device comprises a MOSFET formed in the surface of a semiconductor substrate; and a trench capacitor provided in a trench formed in the surface of the semiconductor substrate. The MOSFET includes a gate electrode formed on a gate insulator in the surface of the semiconductor substrate, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080105913 - Semiconductor structures: The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The bitlines can be formed within trenches having faceted top portions. The invention also includes semiconductor structures containing trenches with faceted top portions, and containing bitlines... Agent: Wells St. John P.s.

20080105914 - Titanium oxide extended gate field effect transistor: A titanium oxide extended gate field effect transistor (EGFET) device and fabricating method thereof. Titanium oxide is formed on an EGFET by sputtering, coating a detection membrane therefor. Current-voltage relationships at different pH values are also measured via a current measuring system. Sensitivity parameter of the titanium oxide EGFET is... Agent: Quintero Law Office, PC

20080105915 - Non-volatile memory device and method of manufacturing the same: A semiconductor device may include a tunnel insulating layer disposed on an active region of a substrate, field insulating patterns disposed in surface portions of the substrate to define the active region, each of the field insulating patterns having an upper recess formed at an upper surface portion thereof, a... Agent: Lee & Morse, P.C.

20080105916 - Nonvolatile semiconductor memory device and manufacturing method thereof: This disclosure concerns a memory device comprising an element formation area having a recess in a side of the active area (AA) so that a width of a part below an upper surface of the AA is smaller than a width of the upper surface of the AA in a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080105917 - Split-gate memory cells and fabrication methods thereof: Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080105919 - Non-volatile memory device having separate charge trap patterns and method of fabricating the same: A non-volatile memory device prevents charge spreading. The non-volatile memory device includes an isolation trench in a semiconductor substrate, an isolation layer partially filling the isolation trench between first and second fins defined by the isolation trench, a control gate electrode crossing the first and second fins, a first charge... Agent: Lee & Morse, P.C.

20080105918 - Nonvolatile memory devices and methods of fabricating the same: A nonvolatile memory device includes a semiconductor substrate including a cell region and a peripheral circuit region, a cell gate on the cell region, and a peripheral circuit gate on the peripheral circuit region, wherein the cell gate includes a charge storage insulating layer on the semiconductor substrate, a gate... Agent: Lee & Morse, P.C.

20080105920 - Semiconductor devices and fabrication process thereof: A semiconductor device has an insulated gate transistor provided with a semiconductor substrate and a gate electrode arranged on the semiconductor substrate via a gate insulating film. The gate electrode includes an electrically-conductive buffer film for preventing any damage, which would occur if a main gate electrode portion were formed... Agent: David R. Metzger Sonnenschein Nath & Rosenthal LLP

20080105921 - Thin film transistor and manufacturing method thereof: The present invention provides a step in which a channel-length of a TFT can be controlled with higher reproducibility. In addition, the present invention provides a step in which a short channel-length of the TFT can be manufactured. Further, the present invention provides a structure of the TFT in which... Agent: Eric Robinson

20080105922 - Method of manufacturing a semiconductor device and semiconductor device obtainable with such a method: A method of manufacturing a semiconductor device comprising a dual gate field effect transistor is disclosed, in which method a semiconductor body with a surface and of silicon is provided with a source region and a drain region of a first conductivity type and with a channel region of a... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080105923 - Semiconductor integrated circuit device and manufacturing method thereof: After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film (10)... Agent: Miles & Stockbridge PC

20080105925 - Process charging and electrostatic damage protection in silicon-on-insulator technology: A SOI device features a conductive pathway between active SOI devices and a bulk SOI substrate. The conductive pathway provides the ability to sink plasma-induced process charges into a bulk substrate in the event of process charging, such as interlayer dielectric deposition in a plasma environment, plasma etch deposition, or... Agent: Intel Corporation C/o Intellevate, LLC

20080105924 - Semiconductor device and method for manufacturing the same: A semiconductor device comprising a substrate, a gate structure disposed on the substrate, and a source/drain area disposed in the substrate is provided. The source/drain area comprises a silicon layer and a glass layer below the silicon layer, so as to define a shallow junction depth to avoid the possible... Agent: Holland & Knight LLP

20080105926 - Thin film transistor and fabrication method thereof: A thin film transistor and a fabrication method thereof are provided. First, a gate is formed on a substrate. Next, a gate insulating layer is formed to cover the gate and then a channel layer is formed on a portion of the gate insulating layer above the gate. Afterwards, a... Agent: Jianq Chyun Intellectual Property Office

20080105927 - Memory devices and methods of manufacturing the same: The memory device includes upper gate structures and lower gate structures formed on an active region of a substrate, and an insulation layer. Each of the upper gate structures may have a blocking layer pattern and a control gate electrode. Each of the lower gate structures may have a tunnel... Agent: Lee & Morse, P.C.

20080105928 - Low ohmic layout technique for mos transistors: A transistor driver circuit with a plurality of transistors, each having source and drain regions formed in a substrate. At least first and second interconnect layers are formed on top of the substrate. A first plurality of contacts connect the source regions to one of the first or second interconnect... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080105929 - Semiconductor integrated circuit: According to an aspect of the present invention, there is provided a semiconductor IC that includes a plurality of standard cells arranged in a first direction on a semiconductor substrate, and a first diffusion layer connected to a first power source and a second diffusion layer connected to a second... Agent: Foley And Lardner LLP Suite 500

20080105930 - Semiconductor integrated circuit device and related fabrication method: Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral... Agent: Volentine & Whitt PLLC

20080105931 - Semiconductor devices having fin-type active areas and methods of manufacturing the same: A semiconductor device having a fin type active area includes a plurality of active regions, a first device isolation layer and a recessed second device isolation layer disposed in a direction of gate electrodes of the semiconductor device. A recessed second device isolation layer and a first device isolation layer... Agent: Harness, Dickey & Pierce, P.L.C

20080105932 - Partial finfet memory cell: A semiconductor structure includes a semiconductor substrate, a planar PMOS device at a surface of the semiconductor substrate, and an NMOS device at the surface of the semiconductor substrate, wherein the NMOS device is a Fin field effect transistor (FinFET).... Agent: Slater & Matsil, L.L.P.

20080105933 - Method for forming a semiconductor device and semiconductor device thus obtained: A semiconductor device is disclosed that comprises a fully silicided electrode formed of an alloy of a semiconductor material and a metal, a workfunction modulating element for modulating a workfunction of the alloy, and a dielectric in contact with the fully silicided electrode. At least a part of the dielectric... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080105934 - Semiconductor device: The present gate structure comprises a gate oxide layer positioned on a substrate, a conductive stack positioned on the gate oxide layer, a passivation layer positioned on the sidewall of the conductive stack, and a cap layer positioned on the conductive stack. The conductive stack includes a polysilicon layer, a... Agent: Oliff & Berridge, PLC

20080105935 - Micromachine device: A micromachine device includes a pad 107a and a pad 107b formed of a polysilicon doped with impurities.... Agent: Mcdermott Will & Emery LLP

20080105937 - Method for processing a mems/cmos cantilever based memory storage device: A Seek and Scan Probe (SSP) memory device is disclosed. The memory device includes a moving part having microelectromechanical (MEMS) structures fabricated on a first wafer and CMOS and memory medium components fabricating on a second wafer bonded to the first wafer.... Agent: Intel/blakely

20080105936 - Surface pressure distribution sensor: [Solving Means] In the present invention, a first lead line group is placed adjacent to a first line group on a first substrate, a second lead line group connected to a second line group is placed on a second substrate, the second lead line group extends over a boundary portion... Agent: Beyer Weaver LLP

20080105938 - Magnetic memory cell and magnetic random access memory: A magnetic memory cell and a magnetic random access memory that are highly reliable and low-power consuming. An upper electrode having a connecting area smaller than the area of a ferromagnetic free layer of a magnetic memory cell is connected to the ferromagnetic free layer. A current is applied to... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080105939 - Coated package with filter profile: Method for packaging a photo detector integrated circuit (IC) and a pigment filter and resulting package are described. An encapsulated package (e.g., an epoxy-encapsulated package) that includes a first surface is provided. A filter layer is then coated directly onto the first surface. The filter layer provides optical filtering properties... Agent: Avago Technologies, Ltd. C/o Klaas, Law, O'meara & Malkin, P.C.

20080105940 - Soi-based inverse nanotaper optical detector: A photodetector integrated within a silicon-on-insulator (SOI) structure is formed directly upon an inverse nanotaper endface coupling region to reduce polarization sensitivity at the detector's input. The photodetector may be germanium-based PN (PIN) junction photodetector, a SiGe photodetector, a metal/silicon Schottky barrier photodetector, or any other suitable silicon-based photodetector. The... Agent: Wendy W. Koba

20080105941 - Sensor-type semiconductor package and fabrication: The invention provides a sensor-type semiconductor package and fabrication method thereof. The fabrication method includes steps of: attaching a sensor chip to a chip carrier; electrically connecting the sensor chip and a chip carrier via a plurality of bonding wires; mounting a light-permeable body to the sensor chip with an... Agent: Edwards Angell Palmer & Dodge LLP

20080105942 - Sensor-type semiconductor package and fabrication method thereof: A sensor-type semiconductor package and a fabrication method thereof are provided. The fabrication method of the sensor-type semiconductor package includes steps of: providing a wafer having sensor chips; attaching light-permeable bodies to the sensor chips, wherein each light-permeable body has a covering layer and an adhesive layer; singulating the wafer... Agent: Edwards Angell Palmer & Dodge LLP

20080105943 - Organic-based electronic component containing pixels: The invention relates to an organic-based electronic component, especially a component with reduced pixel crosstalk. According to the invention, the crosstalk is reduced by a grid electrode.... Agent: Young & Thompson

20080105944 - Crosstalk improvement through p on n structure for image sensor: The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a semiconductor substrate having a first type of dopant; a semiconductor layer having a second type of dopant different from the first type of dopant and disposed on the semiconductor substrate; and an image sensor formed in... Agent: Haynes And Boone, LLP

20080105945 - Method of forming a nanocluster charge storage device: An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer... Agent: Freescale Semiconductor, Inc. Law Department

20080105946 - Solid state field emission charge storage: Solid state field emission charge storage device is formed by a midgap metal plate and another conductive plate acting as capacitor plates in tunneling relation to a floating charge storage reservoir on a substrate. The plates can be reversibly biased for tunneling of holes or electrons. The devices are tiny... Agent: Schwegman, Lundberg & Woessner / Atmel

20080105947 - Semiconductor device, wiring of semiconductor device, and method of forming wiring: A semiconductor device includes a substrate, an element formed in the substrate, an insulation film formed on the substrate, wiring layers, and an electrode pad. The wiring layers are multilayered and electrically coupled to the element through the insulation film. The electrode pad is electrically coupled to a top wiring... Agent: Posz Law Group, PLC

20080105948 - Fuse structures and integrated circuit devices: Fuse structures and integrated circuit devices are disclosed. An exemplary embodiment of a fuse structure comprises a first and second metal pads formed at different positions in a first dielectric layer and a conductive line formed in a second dielectric layer underlying the first dielectric layer, electrically connecting the first... Agent: Birch Stewart Kolasch & Birch

20080105949 - High power insulated gate bipolar transistors: An insulated gate bipolar transistor (IGBT) includes a substrate having a first conductivity type, a drift layer having a second conductivity type opposite the first conductivity type, and a well region in the drift layer and having the first conductivity type. An epitaxial channel adjustment layer is on the drift... Agent: Myers Bigel Sibley & Sajovec

20080105950 - Semiconductor substrate, method of manufacturing the semiconductor substrate, semiconductor device and pattern forming method: A semiconductor substrate comprises a semiconductor layer comprising a group III nitride as a main component. A scattering portion for scattering an incident beam of light incident on one plane of the semiconductor layer is provided on another plane or inside of the semiconductor layer.... Agent: Nixon Peabody, LLP

20080105951 - Electronic device and method for manufacturing thereof: An electronic device, including a substrate, a functional structure constituting a functional element formed on the substrate, and a cover structure forming a cavity portion in which the functional structure is disposed, is disclosed. In the electronic device, the cover structure includes a laminated structure of an interlayer insulating film... Agent: Oliff & Berridge, PLC

20080105952 - Manufacturing method of semiconductor chips and semiconductor device having the semiconductor chips: The present invention provides a method for manufacturing a semiconductor chip having through electrodes, comprising the steps of forming, in a semiconductor wafer having front and back surfaces formed with circuits, a plurality of electrode forming holes for forming the through electrodes, superimposing bump forming masks formed with a plurality... Agent: Rabin & Berdo, PC

20080105954 - Group iii nitride based semiconductor device having trench structure or mesa structure and production method therefor: A GaN layer 2 was grown on a C-plane sapphire substrate 1, and a T-shaped USG film 3 was formed on the GaN layer 2 so that side surfaces of the USG film 3 were arranged parallel to A-plane and M-plane of the GaN layer 2. Thereafter, by using the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080105953 - Rotational shear stress for charge carrier mobility modification: A semiconductor structure and its method of fabrication utilize a semiconductor substrate having an active region mesa surrounded by an isolation trench. A first isolation region having a first stress is located in the isolation trench. A second isolation region having a second stress different than the first stress is... Agent: Scully, Scott, Murphy & Presser, P.C.

20080105955 - Method for epitaxial growth of (110)-oriented srtio3 thin films on silicon without template: A process and structure utilizes pulsed laser deposition technique to grow SrTiO3 (STO) films with single (110) out-of-plane orientation upon a surface of all (100), (110) and (111)-oriented silicon (Si) substrates. No designed buffer layer is needed beneath the STO thin films. The in-plane alignments for the epitaxial STO films... Agent: Cooper & Dunham, LLP

20080105956 - Semiconductor element and process of manufacturing semiconductor element: Shown are embodiments where a process of manufacturing a semiconductor element on a semiconductor wafer is shown. The semiconductor element is obtained by dividing the function-providing semiconductor wafer into functional elements. The function-providing semiconductor wafer is, at its first main surface, mechanically coupled to a handling wafer. The thinning is... Agent: Schwegman, Lundberg & Woessner, P.A.

20080105957 - Thin, thermally enhanced flip chip in a leaded molded package: Embodiments of the invention are directed to semiconductor die packages. One embodiment of the invention is directed to a semiconductor die package including, (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead... Agent: Townsend And Townsend And Crew, LLP

20080105958 - High temperature, high voltage sic void-led electronic package: An electronic package designed to package silicon carbide discrete components for silicon carbide chips. The electronic package allows thousands of power cycles and/or temperature cycles between −55° C. to 300° C. The present invention can also tolerate continuous operation at 300° C., due to high thermal conductivity which pulls heat... Agent: Michael A. Sileo, Jr.

20080105959 - Semiconductor device and manufacturing method of the same: The yield of a semiconductor device is improved. Inside the resin sealing body which forms a semiconductor device, the semiconductor chip is sealed in the state where it has arranged aslant to the upper and lower sides of a resin sealing body. In the suspension lead which supports the die... Agent: Miles & Stockbridge PC

20080105960 - Integrated circuit package and method for manufacturing an integrated circuit package: An integrated circuit package includes: an integrated circuit having a surface at least partially covered by a metal layer; at least one connection point; at least one connector electrically connecting the integrated circuit with the at least one connection point; and encapsulating material encapsulating the at least one connector, at... Agent: Slater & Matsil LLP

20080105962 - Chip package: A chip package and a process thereof are provided. The chip package includes a first package unit and a second package unit. The first package unit includes a carrier; a chip, disposed on the carrier and electrically connected thereto; a first encapsulant, disposed on the carrier and covering the chip;... Agent: J C Patents, Inc.

20080105961 - Ligands of the molecule fit (agt-121) and their pharmaceutical use: Identification of molecules which modulate inter alia obesity, anorexia, weight maintenance, inflammation and/or metabolic energy levels in a subject are described which particularly relate to a protein molecule called “FIT”, previously known as “AGT-121”. Ligands of “FIT” as well as antagonists of “FIT”-ligand interaction are proposed to modulate inter alia... Agent: Knobbe Martens Olson & Bear LLP

20080105963 - Stackable electronic device assembly: A stackable chip assembly is disclosed, as are many different embodiments relating to same. The chip assembly preferably includes at least two substrates with components mounted on each. The substrates are preferably situated with respect to one another such that components on one substrate extend towards the other substrate and... Agent: Tessera Lerner David Et Al.

20080105965 - Stacked integrated circuit package-in-package system: A stacked integrated circuit package-in-package system is provided forming a first device having a first integrated circuit package comprises forming a first substrate with a first integrated circuit thereon, electrically connecting first electrical interconnects between the first integrated circuit and a top side of the first substrate, encapsulating a first... Agent: Law Offices Of Mikio Ishimaru

20080105964 - Substrate, semiconductor device using the same, method for inspecting semiconductor device, and method for manufacturing semiconductor device: A substrate including therein a plurality of conductor layers laminated via insulating layers, the substrate mounting at least one semiconductor integrated circuit, wherein the substrate includes a first electrode terminal connected to the semiconductor integrated circuit, a second electrode terminal connected to a terminal on an upper substrate arranged in... Agent: Mcdermott Will & Emery LLP

20080105967 - Fan out type wafer level package structure and method of the same: To pick and place standard dice on a new base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover,... Agent: Kusner & Jaffe Highland Place Suite 310

20080105966 - Semiconductor module including components in plastic casing: A semiconductor module includes components in a plastic casing. The semiconductor module includes a plastic package molding compound and a semiconductor chip. Also provided in the module are a first principal surface including an upper side of the plastic package molding compound and at least one active upper side of... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20080105968 - Integrated circuit interconnect lines having reduced line resistance: The present invention provides integrated circuit fabrication methods and devices wherein shunted interconnect lines are formed. The shunted interconnect lines are formed in a dielectric stack comprising (1) a first dielectric layer having dense interconnect lines that form a first dielectric layer dense line subset and (2) a sequentially deposited... Agent: Applied Materials, Inc.

20080105969 - Semiconductor constructions and semiconductor device fabrication methods: A method of fabricating a semiconductor device includes etching a substrate formed on a backside of a semiconductor wafer to form a recess in the substrate, and forming a sputter film in the recess, the sputter film including a first material having a coefficient of thermal expansion (CTE) which is... Agent: Mcginn Intellectual Property Law Group, PLLC

20080105970 - Vertical integration of passive component in semiconductor device package for high electrical performance: A high performance package and methods for its assembly are disclosed. A semiconductor package system of the invention is assembled in a method including the steps of affixing one or more spacers to a package substrate and affixing one or more passive components to the substrate adjacent to the spacers... Agent: Yisheng Tung Texas Instruments Incorporated

20080105972 - Method for making a circuit plate: A method for making a circuit plate includes: forming first holes in an insulating layer; forming a conductive layer on the insulating layer such that a portion of the conductive layer fills the first holes; grinding the conductive layer such that the portion of the conductive layer remains in the... Agent: Ladas & Parry LLP

20080105971 - Semiconductor device and manufacturing method of the same: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080105974 - Package structure and package substrate thereof: A package structure and a package substrate thereof are provided. The package structure includes a package substrate, a chip and a molding compound. The package substrate has an upper surface and a lower surface. The lower surface has a molding area and a pad area. The molding area has at... Agent: J C Patents, Inc.

20080105973 - Semiconductor assembly with one metal layer after base metal removal: A method for packaging an integrated circuit. A barrier metal pattern is disposed on a baseplate. A conductive layer is disposed on the barrier metal pattern. A photoresist having a pattern is applied to the conductive layer. A via is then disposed on the conductive layer. An integrated circuit is... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080105975 - Gold wire for connecting semiconductor chip: Gold wire for connecting a semiconductor chip basically containing praseodymium in 0.0004 mass % to 0.02 mass % in range and, considering the bonding characteristics, containing beryllium or aluminum or both in limited ranges and, considering the precipitates formed in the gold wire, further containing auxiliary additive elements of calcium,... Agent: Robert T. Tobin Kenyon & Kenyon

20080105976 - Metal filled through via structure for providing vertical wafer-to-wafer interconnection: A vertical wafer-to-wafer interconnect structure is provided in which a first wafer and a second wafer are mated by way of metal studs that extend from a surface of the first wafer. The metal studs extend from the surface of the first wafer into a corresponding through via of the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080105977 - Interconnect layers without electromigration: A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region... Agent: Schmeiser, Olsen & Watts

20080105978 - Method for forming an ultra low dielectric film by forming an organosilicon matrix and large porogens as a template for increased porosity: Ultra low K nanoporous dielectric films may be formed by chemical vapor deposition of silicon-containing components and large non-silicon containing porogens having labile groups. In accordance with one embodiment of the present invention, a low K nanoporous film may be formed by the oxidative reaction between trimethylsilane (the silicon-containing component)... Agent: Townsend And Townsend And Crew LLP / Amat

20080105979 - Method for selective deposition of a thin self-assembled monolayer: A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface... Agent: Knobbe Martens Olson & Bear LLP

20080105980 - Method for manufacturing semiconductor device having damascene mim type capacitor: A method for manufacturing a semiconductor device having a damascene metal/insulator/metal (MIM)-type capacitor and metal lines including providing a semiconductor device; sequentially forming a first interlayer insulating film and a second interlayer insulating film over the semiconductor substrate; simultaneously forming a vias hole and a lower metal line in a... Agent: Sherr & Nourse, PLLC

20080105981 - Semiconductor device having projecting electrode formed by electrolytic plating, and manufacturing method thereof: A semiconductor device includes a semiconductor substrate, and a plurality of wiring lines provided on one side of the semiconductor substrate, each of the wiring lines having a connection pad portion. An overcoat film is provided on the wiring lines and the one side of the semiconductor substrate, The overcoat... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080105982 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device having an interconnection part formed of multiple carbon nanotubes is disclosed. The method includes the steps of (a) forming a growth mode control layer controlling the growth mode of the carbon nanotubes, (b) forming a catalyst layer on the growth mode control layer,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080105983 - Method of forming metal line of semiconductor device, and semiconductor device: A semiconductor device includes a first barrier metal layer and a second barrier metal layer, a third barrier metal layer, and a metal line. The first barrier metal layer and the second barrier metal layer are formed and on a top surface of an insulating layer over a semiconductor substrate... Agent: Marshall, Gerstein & Borun LLP

20080105984 - Semiconductor chip stack package with reinforcing member for preventing package warpage connected to substrate: Provided is a semiconductor chip stack package with a reinforcing member connected to a substrate for preventing package warpage. The semiconductor chip stack package includes a first substrate including first circuit patterns on one surface thereof; a first unit semiconductor chip including a plurality of semiconductor chips stacked vertically on... Agent: Marger Johnson & Mccollom, P.C.

20080105985 - Component stacking for integrated circuit electronic package: Component stacking for increasing packing density in integrated circuit packages. In one aspect of the invention, an integrated circuit package includes a substrate, and a plurality of discrete components connected to the substrate and approximately forming a component layer parallel to and aligned with a surface area of the substrate.... Agent: Sawyer Law Group LLP

20080105986 - Electronic device, a chip contacting method and a contacting device: An electronic device includes a chip (10) and a carrier substrate (16), wherein the carrier substrate (16) has a conductive structure (18) and the chip (10) has a pair of bonding pads (13) on a side facing the carrier substrate (16). The bonding pads (13) are in electrical contact with... Agent: Texas Instruments Incorporated

20080105988 - Electrical component having external contacting: An electrical component includes at least one first semiconductor substrate, at least one contact means for the external contacting, and at least one bonding wire. The contact means has a first side and, diametrically opposite, a second side. The semiconductor substrate is situated on the first side of the contact... Agent: Kenyon & Kenyon LLP

20080105987 - Semiconductor device having interposer formed on chip: A semiconductor device having an interposer formed on a semiconductor chip is disclosed. The semiconductor chip includes a substrate which has external electrodes used for signal transfer or power supply with respect to the exterior and power supply pads arranged in an area on the substrate in which the external... Agent: Amin, Turocy & Calvin, LLP

20080099752 - Carbon filament memory and fabrication method: An integrated circuit is described, including a memory element including a first carbon layer rich in a first carbon material and a second carbon layer rich in a second carbon material. The memory element stores information by reversibly forming a conductive channel in the second carbon layer, wherein the conductive... Agent: Slater & Matsil LLP

20080099753 - Phase change memory devices having dual lower electrodes and methods of fabricating the same: A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked... Agent: Marger Johnson & Mccollom, P.C.

20080099755 - Gallium nitride-based device and method: A gallium nitride-based device has a first GaN layer and a type II quantum well active region over the GaN layer. The type II quantum well active region comprises at least one InGaN layer and at least one GaNAs layer comprising 1.5 to 8% As concentration. The type II quantum... Agent: Philip D. Freedman PC

20080099754 - Method for providing a nanoscale, high electron mobility transistor (hemt) on insulator: A method and resulting high electron mobility transistor comprised of a substrate and a relaxed silicon-germanium layer formed over the substrate. A dopant layer is formed within the relaxed silicon-germanium layer. The dopant layer contains carbon and/or boron and has a full-width half-maximum (FWHM) thickness value of less than approximately... Agent: Schneck & Schneck

20080099757 - Organic field effect transistor and semiconductor device: It is an object to provide an organic field effect transistor including an electrode which can reduce an energy barrier at an interface between a conductive layer and a semiconductor layer, and a semiconductor device including the organic field effect transistor. A composite layer containing an organic compound and an... Agent: Eric Robinson

20080099758 - Organic polymer semiconductor, method of preparing the same, and ambipolar organic thin film transistor using the same: Disclosed are an organic polymer semiconductor, an ambipolar organic thin film transistor using the same, an electronic device comprising the ambipolar organic thin film transistor and methods of fabricating the same. Example embodiments relate to an organic polymer semiconductor, which may include an aromatic ring derivative having p-type semiconductor properties... Agent: Harness, Dickey & Pierce, P.L.C

20080099760 - Picture element driving circuit of display panel and display device using the same: The present invention provides a picture element driving circuit of an active matrix display device, with a configuration of no through-holes, including two or more FETs. A display device of the present invention has a structure in which a first field-effect transistor and a second field-effect transistor are provided, insulation... Agent: Stanley P. Fisher Reed Smith LLP

20080099756 - Semiconductor memory with organic selection transistor: An integrated semiconductor memory with a cell array is disclosed. In one embodiment the memory includes a multiplicity of memory cells arranged in rows and columns. In at least one memory cell, an organic selection transistor is integrated in a stack arrangement above an organic storage element.... Agent: Dicke, Billig & Czaja

20080099762 - Differential voltage defectivity monitoring circuit: A circuit uses a differential voltage response to identify fabrication process defects that would result if an IC design is fabricated (without re-designing to correct such defects). The circuit includes two stacks, whose respective outputs may be compared by a comparator, and comparator's output used to determine defectivity. In some... Agent: Silicon Valley Patent Group LLP

20080099761 - Test structure for opc-related shorts between lines in a semiconductor device: OPC results may be efficiently evaluated on the basis of a test structure containing a plurality of line features with opposing end portions. Thus, for different line parameters, the effect of OPC may be determined for a given critical tip-to-tip distance by determining the leakage behavior of the test assemblies,... Agent: Williams, Morgan & Amerson

20080099764 - Array substrate for liquid crystal display device and method of fabricating the same: An array substrate for an LCD device includes a gate line crossing a data line to define a pixel region. A thin film transistor (TFT) includes a gate electrode connected to the gate line, insulating and active layers on the gate electrode, a source electrode connected to the data line,... Agent: Brinks Hofer Gilson & Lione

20080099763 - Display panel: The invention discloses a display panel. A substrate comprising a chip bonding region and a cut cross-section is provided. A first conductive layer is disposed on the chip bonding region. An insulating layer is disposed on the substrate between the first conductive layer and the cut cross-section, covering a sidewall... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080099765 - Thin film transistor substrate and fabricating method thereof: A thin film transistor substrate and fabricating method thereof, the thin film transistor substrate including a substrate, a gate line and a gate electrode, each including a metal adhesion layer and a Cu alloy layer disposed on the substrate, an active layer and an ohmic contact layer disposed over the... Agent: Cantor Colburn, LLP

20080099770 - Integrated heat spreaders for light emitting devices (leds) and related assemblies: A light emitting device (LED) assembly may include an electrically insulating substrate and a thermally conductive layer on a surface of the insulating substrate. A light emitting device may be on the thermally conductive layer so that the thermally conductive layer is between the light emitting device and the electrically... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080099771 - Light emitting diode and wafer level package method, wafer level bonding method thereof, and circuit structure for wafer level package: This invention discloses a light emitting diode, a wafer level package method, a wafer level bonding method, and a circuit structure for a wafer level package. The light emitting diode includes a package carrier, a conducting material, at least one light emitting diode structure and a package material. The package... Agent: Rosenberg, Klein & Lee

20080099772 - Light emitting diode matrix: A light source includes a light emitting diode (LED) module having a continuous substrate, a layer of n-type semiconductor material formed above the substrate, and a layer of p-type semiconductor material formed above the n-type semiconductor material. A p-n junction is formed between the p-type and n-type semiconductor materials. The... Agent: Fish & Richardson PC

20080099775 - Light emitting diode module and apparatus thereof: A light emitting diode (LED) module employs a one-piece integrated column heat conductive electrode to carry at least one LED chip, so as to quickly remove the heat generated by the LED chip while emitting light. The LED module includes at least one LED chip, a column heat conductive electrode,... Agent: Seyfarth Shaw LLP

20080099774 - Method for high-volume production of light emitting diodes with attached lenses: A method for high-volume production of light emitting diodes with attached lenses involves providing pre-fabricated lenses, wherein the pre-fabricated lenses are held by a common transfer structure, simultaneously attaching the pre-fabricated lenses to respective ones of light emitting diodes, and releasing the pre-fabricated lenses from the common transfer structure. In... Agent: Kathy Manke Avago Technologies Limited

20080099776 - Nitride semiconductor light emitting device and method of manufacturing the same: There are provided a nitride semiconductor light emitting device and a method of manufacturing the same, the device including: a first conductivity type nitride semiconductor layer formed on a substrate; an active layer formed on the first conductivity type nitride semiconductor layer; a second conductivity type nitride semiconductor layer formed... Agent: Mcdermott Will & Emery LLP

20080099778 - Led package structure for increasing light-emitting effiency and method of packaging the same: An LED package structure for increasing light-emitting efficiency includes: a substrate unit, and a plurality of fluorescence colloid units, LED units, conductive units and opaque units. The substrate unit has a main body and a plurality of through holes passing through the main body. Each fluorescence colloid unit is received... Agent: Rosenberg, Klein & Lee

20080099777 - Light-emitting devices and related systems: Light-emitting devices can include a package that supports one or more light-emitting die (e.g., light-emitting diode die, laser diode die) and which can ensure mechanically stability, can facilitate electrical and/or thermal coupling with light-emitting die, and can manipulate the manner by which light generated by the die is emitted out... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.C.

20080099779 - Smd diode holding structure and package thereof: An SMD diode holding structure includes a plastic and a plurality of metal holders. Two ends of the plastic from a function area and a notch. The metal holder has a base portion and a connecting pin portion. The top and bottom surfaces of the base portion are exposed to... Agent: Rosenberg, Klein & Lee

20080099759 - Manufacturing method of semiconductor device and semiconductor device: A method of manufacturing a semiconductor device includes steps of forming a gate electrode over a light-transmitting substrate, forming a gate insulating layer containing an inorganic material over the gate electrode and the substrate, forming an organic layer containing a photopolymerizable reactive group over the gate insulating layer, polymerizing selectively... Agent: Nixon Peabody, LLP

20080099766 - Switching device for a pixel electrode: The invention discloses a switching device for a pixel electrode of display device. The switching device comprises a gate formed on a substrate; a gate-insulating layer formed on the gate; a first buffer layer formed between the substrate and the gate and/or between the gate and the gate-insulating layer, wherein... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080099767 - Gan related compound semiconductor element and process for producing the same and device having the same: A GaN related compound semiconductor element includes: a channel layer made of a GaN related compound semiconductor; and a source layer and a drain layer, which are disposed in a manner of sandwiching the channel layer. The source layer includes two adjacent ridge portions which are formed by selective growth.... Agent: Cantor Colburn, LLP

20080099768 - Diamond transistor and method of manufacture thereof: A method of manufacturing a transistor, typically a MESFET, includes providing a substrate including single crystal diamond material having a growth surface on which further layers of diamond material can be deposited. The substrate is preferably formed by a CVD process and has high purity. The growth surface has a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080099769 - Production of an integrated circuit including electrical contact on sic: Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on... Agent: Dicke, Billig & Czaja

20080099773 - Light emitting diode: In a light emitting diode, a light-emitting region is including an active layer provided between a first conductivity type cladding layer formed on the semiconductor substrate and a second conductivity type cladding layer. A transparent conductive film made of a metal oxide is located over the light-emitting region. A layer... Agent: Foley And Lardner LLP Suite 500

20080099780 - Method for producing group iii - group v vertical light-emitting diodes: A method of producing one or more vertical light-emitting diode (VLED) dies having a light-emitting diode (LED) stack comprising Group III-Group V combinations of elements (e.g., GaN, AlN, InN, AlGaN, InGaN, and InAlGaN) and a metal substrate is provided. The techniques include forming an InGaN or InAlGaN interface layer above... Agent: Patterson & Sheridan, L.L.P.

20080099781 - Method of manufacturing iii group nitride semiconductor thin film and method of manufacturing iii group nitride semiconductor device using the same: A method of manufacturing a III group nitride semiconductor thin film and a method of manufacturing a nitride semiconductor light emitting device employing the III group nitride semiconductor thin film manufacturing method, the III group nitride semiconductor thin film manufacturing method including: growing a first nitride single crystal on a... Agent: Mcdermott Will & Emery LLP

20080099782 - Nitride semiconductor light emitting diode: Provided is a nitride semiconductor light emitting diode (LED) including a substrate; an n-type nitride semiconductor layer formed on the substrate; an active layer formed on a portion of the n-type nitride semiconductor layer; a p-type nitride semiconductor layer formed on the active layer; a p-type contact layer formed on... Agent: Mcdermott Will & Emery LLP

20080099783 - Semiconductor integrated circuit and method for manufacturing the same: A semiconductor integrated circuit includes a power transistor formed on a semiconductor substrate, a plurality of first metal patterns and a plurality of second metal patterns which are formed right above the power transistor and function as a first electrode and as a second electrode of the power transistor, respectively,... Agent: Mcdermott Will & Emery LLP

20080099784 - Array quad flat no-lead package and method of forming same: An array QFN package (10) includes a first semiconductor package (12) and a lead frame (14) having a plurality of leads (16). A first IC die (22) is attached on a first side to the first semiconductor package (12) and is electrically connected to the leads (16) of the lead... Agent: Freescale Semiconductor, Inc. Law Department

20080099785 - Defect reduction using aspect ratio trapping: Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls.... Agent: Goodwin Procter LLP Patent Administrator

20080099786 - Low noise and high performance lsi device, layout and manufacturing method: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be... Agent: Mills & Onello LLP

20080099788 - Semiconductor device and method for manufacturing the same: The external base electrode has a two-layered structure where a p-type polysilicon film doped with a medium concentration of boron is laminated on a p-type polysilicon film doped with a high concentration of boron. Therefore, since the p-type polysilicon film doped with a high concentration of boron is in contact... Agent: Miles & Stockbridge PC

20080099787 - Semiconductor structure and method of manufacture: A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first... Agent: Greenblum & Bernstein, P.L.C

20080099789 - Self-aligned method of forming a semiconductor memory array of floating gate memory cells with source side erase, and a memory array made thereby: A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a substrate of semiconductor material having a first conductivity type, source and drain regions formed in the substrate, a block of conductive material disposed over and electrically connected to... Agent: Dla Piper US LLP

20080099790 - Layout structure: A layout structure is provided with a conducting line extending in a conducting line direction, the conducting line being arranged within a substrate area, a fill element being arranged within the substrate area at a predetermined distance from the conducting line, the fill element having a fill element axis extending... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080099791 - Memory cell device with circumferentially-extending memory element: A memory cell device, including a memory material switchable between electrical property states by the application of energy, has bottom and top electrode members and a dielectric material between the two. The bottom and top electrode members have outer, circumferentially-extending surfaces aligned with one another. A memory element, comprising the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080099792 - Memory devices and methods of fabricating the same: Memory devices include a semiconductor substrate and a plurality of wordlines on the semiconductor substrate. A ground select line is on the semiconductor substrate on a first side of the wordlines and a string select line is on the semiconductor substrate on a second side of the wordlines. The wordlines... Agent: Myers Bigel Sibley & Sajovec

20080099793 - Photodiode module and apparatus including multiple photodiode modules: Various embodiments of the present invention are directed to a photodiode module including a structure configured to selectively couple light to a dielectric-surface mode of a photonic crystal of the photodiode module. In one embodiment of the present invention, a photodiode module includes a semiconductor structure having a p-region and... Agent: Hewlett Packard Company

20080099794 - Semiconductor device comprising nmos and pmos transistors with embedded si/ge material for creating tensile and compressive strain: By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer... Agent: J. Mike Amerson, Williams, Morgan & Amerson, P.C.

20080099795 - Finfet transistor and circuit: A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated... Agent: Schmeiser, Olsen & Watts

20080099796 - Device with patterned semiconductor electrode structure and method of manufacture: A method of forming a semiconductor device can include forming a first layer of semiconductor material in contact with a first area of a substrate. The first area can be adjacent to at least one electrical isolation structure that extends into the substrate and has a top portion extending above... Agent: Bradley T. Sako Haverstock & Owens, LLP

20080099797 - Method and device for sensing radiation: A device is disclosed for sensing radiation, having a gate region and a substrate, wherein one of the gate region and the substrate is configured as an input for radiation. A channel region, connecting a source region and a drain region of the transistor device is provided. The device is... Agent: Darryl G. Walker

20080099798 - Methods and devices for amplifying a signal: A junction field effect transistor (JFET) device is disclosed for amplifying an input signal. The JFET device includes a first gate region and a substrate/well/bulk region that may form a second gate region. The JFET device also includes a first source/drain region and a second source/drain region. The first source/drain... Agent: Darryl G. Walker

20080099800 - Integrated matching network and method for manufacturing integrated matching networks: An integrated matching network and method for manufacturing an integrated matching network are provided. The method includes forming (405) a first die on a substrate, forming (410) a second die on the substrate, and forming (415) a metallization layer on the first and second dies. The second die has a... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080099799 - Micropad for bonding and a method therefor: A semiconductor process is taught for performing electroless plating of copper overlying at least a portion of a layer comprising cobalt, nickel, or both cobalt and nickel. The cobalt and/or nickel comprising layer may be formed using electroless plating. For some embodiments, a tin layer is then formed overlying the... Agent: Freescale Semiconductor, Inc. Law Department

20080099801 - Metal-oxide-semiconductor transistor and method of forming the same: A method of manufacturing a MOS transistor device. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next,... Agent: North America Intellectual Property Corporation

20080099802 - Transmission line transistor: A transistor comprises a gate, a source, and a drain. The gate is configured as a gate transmission line having a first characteristic impedance, and has an input at a first end thereof, and an output at a second end thereof. The source is configured as a source transmission line... Agent: Kathy Manke Avago Technologies Limited

20080099804 - Image sensor having curved micro-mirrors over the sensing photodiode and method for fabricating: The invention involves the integration of curved micro-mirrors over a photodiode active area (collection area) in a CMOS image sensor (CIS) process. The curved micro-mirrors reflect light that has passed through the collection area back into the photo diode. The curved micro-mirrors are best implemented in a backside illuminated device... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080099803 - Thin film transistor: A thin film transistor is disclosed comprising comprises a substrate, a dielectric layer, and a semiconductor layer. The semiconductor layer, which is crystalline zinc oxide preferentially oriented with the c-axis perpendicular to the plane of the dielectric layer or substrate, is prepared by liquid depositing a zinc oxide nanodisk composition.... Agent: Fay Sharpe / Xerox - Rochester

20080099805 - Cmos imaging sensor: A CMOS image sensor and active pixel cell design that provides an output signal representing an incident illumination light level that is adapted for time domain analysis. Thus, the noise sources associated with charge integration and the contribution of dark current to it, is avoided. The active pixel cell design... Agent: Scully, Scott, Murphy & Presser, P.C.

20080099806 - Image sensor having heterojunction bipolar transistor and method of fabricating the same: Provided are image sensor having a heterojunction bipolar transistor (HBT) and a method of fabricating the same. The image sensor is fabricated by use of silicon-germanium bipolar junction transistor complementary metal oxide semiconductor (SiGe BiCMOS) technology. In the image sensor, a PD employs a floating-base-type SiGe HBT unlike a pn-junction-based... Agent: Ladas & Parry LLP

20080099807 - Low-voltage image sensor and method of driving transfer transistor thereof: Provided are a low-voltage image sensor and a method of driving a transfer transistor thereof, which are obtained by changing the structure and driving method of a typical transfer transistor of a 4-transistor CMOS transistor, and can eliminate the influence of a voltage or physical structure of a diffusion node... Agent: Ladas & Parry LLP

20080099808 - One transistor dram cell structure and method for forming: A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a Schottky diode junction with the body... Agent: Freescale Semiconductor, Inc. Law Department

20080099809 - Semiconductor device having a capacitance element and method of manufacturing the same: A dielectric film is formed by depositing an amorphous strontium oxide film to a thickness of one to several atomic layers on a first electrode layer, then depositing an amorphous titanium oxide film to a thickness of one to several atomic layers on the amorphous strontium oxide film, and then... Agent: Sughrue Mion, PLLC

20080099810 - Semiconductor device and semiconductor device manufacturing method: A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080099811 - Single transistor memory device having source and drain insulating regions and method of fabricating the same: A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both... Agent: Volentine & Whitt PLLC

20080099812 - Semiconductor device: A semiconductor device in which a DRAM and a SRAM are mixedly mounted is provided. The DRAM and the SRAM have a stack-type structure in which a bitline is formed below a capacitive element. A cross couple connection of the SRAM is formed in a layer or below the layer... Agent: Sughrue Mion, PLLC

20080099813 - Semiconductor device and semiconductor device manufacturing method: A semiconductor device including a semiconductor substrate having a logic formation region in which a memory device is formed and a logic formation region in which a logic device is formed; a first impurity region formed in an upper surface of said semiconductor substrate in the logic formation region; a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080099814 - Integrated circuit and method for production: An array of vertical transistor cells formed in a substrate for selecting one of a plurality of memory cells by selecting a word line and a bit line is disclosed. In one embodiment, for minimizing the area of a cell and reducing complexity in production a plurality of parallel insulating... Agent: Dicke, Billig & Czaja

20080099815 - Semiconductor device having a vertical transistor and method for manufacturing the same: A semiconductor device having a vertical transistor comprises a silicon substrate; a drain region, a channel region and a source region vertically stacked on the silicon substrate; a buried type bit line formed under the drain region in the silicon substrate to contact with the drain region and to extend... Agent: Townsend And Townsend And Crew, LLP

20080099816 - Memory cell and method for forming the same: A semiconductor memory cell structure having 4F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080099817 - Method for obtaining extreme selectivity of metal nitrides and metal oxides: Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H2F2. The etchant can be used to selectively remove metal nitride layers relative to doped or undoped oxides, tungsten, polysilicon, and titanium nitride.... Agent: Knobbe Martens Olson & Bear LLP

20080099818 - Non-volatile memory and manufacturing method and erasing method thereof: A non-volatile memory is provided, including a control gate, a floating gate, a gate oxide layer, a source region, a drain region, a first dielectric layer, a second dielectric layer, and an erase gate. The control gate is disposed in a substrate. The floating gate comprising a coupling part and... Agent: Jianq Chyun Intellectual Property Office

20080099819 - Nonvolatile semiconductor storage apparatus and method for manufacturing the same: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage apparatus including: a substrate; a columnar semiconductor disposed perpendicular to the substrate; a charge storage laminated film disposed around the columnar semiconductor; a first conductor layer that is in contact with the charge storage laminated... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080099824 - Flash memory device and method of fabricating the same: A flash memory device and a method of fabricating the same are provided. The flash memory device may include an isolation layer provided in a semiconductor substrate to define an active region. A floating gate may be provided on the active region. The floating gate may be spaced a first... Agent: Harness, Dickey & Pierce, P.L.C

20080099821 - Flash memory device and method of manufacturing the same: A method of manufacturing semiconductor devices includes providing a semiconductor substrate including first active areas and isolation areas alternately arranged to be parallel to each other and second active areas connecting the first active areas to each other. A tunnel insulating layer, a charge storage layer, and an isolation mask... Agent: Townsend And Townsend And Crew, LLP

20080099820 - Growth of metallic nanodots using specific precursors: A technique to form metallic nanodots in a two-step process involving: (1) reacting a silicon-containing gas precursor (e.g., silane) to form silicon nuclei over a dielectric film layer; and (2) using a metal precursor to form metal nanodots where the metal nanodots use the silicon nuclei from step (1) as... Agent: Schneck & Schneck

20080099823 - Non-volatile memory device and method of manufacturing the same: A method of manufacturing a non-volatile memory device includes forming a trench using the shallow trench isolation (STI) method; forming a first insulating layer on a semiconductor device including the trench; forming a conductive layer on the semiconductor device including the trench; etching the conductive layer to form a conductive... Agent: Townsend And Townsend And Crew, LLP

20080099822 - Nonvolatile memory devices and methods of fabricating the same: A nonvolatile memory device may include a semiconductor substrate, a floating gate electrode on the semiconductor substrate that includes an acute-angled tip at an upper end, and a control gate electrode insulated from the floating gate electrode and facing at least a portion of the floating gate electrode, wherein an... Agent: Lee & Morse, P.C.

20080099825 - Nonvolatile semiconductor memory device and method of producing the same: A nonvolatile semiconductor memory device includes a semiconductor substrate having a principal surface, memory transistors, and selection transistors. Each of the memory transistors has a floating gate and a control gate that are formed by lamination with each other on the principal surface. Each of the selection transistors has a... Agent: Mcdermott Will & Emery LLP

20080099830 - Cylindrical channel charge trapping devices with effectively high coupling ratios: A memory cell comprising: a source region and a drain region separated by a semiconductor channel region, the channel region having a channel surface having an area A1 including a first cylindrical region, a first dielectric structure on the channel surface, a dielectric charge trapping structure on the first dielectric... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080099827 - Modifiable gate stack memory element: An apparatus and method for storing information are provided, including using a transistor having a channel, a gate oxide layer, a gate electrode, and a modifiable gate stack layer. The on-resistance of the transistor is changed by causing a non-charge-storage based physical change in the modifiable gate stack layer, to... Agent: Slater & Matsil LLP

20080099829 - Mosfet devices and systems with nitrided gate insulators and methods for forming</