Active solid-state devices (e.g., transistors, solid-state diodes) inventions 04/08

20080093590 - Phase change memory device and method of forming the same: Provided are a phase change memory device and a method of forming the same. According to the phase change memory, a first plug electrode and a second plug electrode are spaced apart from each other in a mold insulating layer. A phase change pattern is disposed on the mold insulating... Agent: Mills & Onello LLP

20080093592 - Phase-change memory and method of manufacturing the same: A structure of a phase-change memory which enables low-current rewrite and a method of manufacturing the same are provided. The phase-change memory comprises: an interlayer insulating film and a plug formed over a main surface of a silicon substrate; a phase-change film formed over the plug; and an upper electrode... Agent: Townsend And Townsend And Crew, LLP

20080093591 - Storage nodes, phase change memory devices, and methods of manufacturing the same: A storage node may include a bottom electrode contact layer, a phase change layer connected to the bottom electrode contact layer, and a top electrode layer connected to the phase change layer. The bottom electrode contact layer may protrude toward the phase change layer. A phase change memory device may... Agent: Harness, Dickey & Pierce, P.L.C

20080093593 - Semiconductor light emitting device: A semiconductor light emitting device may include an n-type contact layer on a substrate. An active layer may be on the n-type contact layer and/or include two or more quantum well layers and two or more barrier layers. A p-type contact layer may be on the active layer. Energy band... Agent: Harness, Dickey & Pierce, P.L.C

20080093595 - Thin film transistor for cross point memory and method of manufacturing the same: A thin film transistor used as a selection transistor for a three-dimensional stacking cross point memory and a method of manufacturing the thin film transistor are provided. The thin film transistor includes a substrate, a gate, a gate insulation layer, a channel, a source and a drain. The gate may... Agent: Harness, Dickey & Pierce, P.L.C

20080093597 - Semiconductor device: A semiconductor device is provided in which function modes thereof can be changed without difficulty and failure analysis can be conducted in an apparatus in which the semiconductor device is mounted. A semiconductor device uses a ball grid array package and includes: a semiconductor chip that is provided within the... Agent: Young & Thompson

20080093596 - Semiconductor device and method of fabricating the same: A semiconductor device includes a wiring layer that is formed on a substrate and includes a first pad contact region and a second pad contact region, a passivation layer that includes a first opening and a second opening on the wiring layer and a protrusion pattern dividing the first opening... Agent: F. Chau & Associates, LLC

20080093602 - Image display unit and method for manufacutre the same: The present invention provides an image display unit, which can be manufactured in shorter time by designing a thin-film transistor, by which it is possible to reduce the number of processes of ion implantation and photolithographic processes. A gate electrode GT is designed in a laminated structure of a thin... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080093606 - Light emitting chip package and manufacturing method thereof: A method for manufacturing a light emitting chip package includes bonding a patterned metal plate having at least a thermal enhanced plate and many contacts around the same to a substrate and bonding a film-like circuit layer to the patterned metal plate. Many conductive wires are formed to connect the... Agent: Jianq Chyun Intellectual Property Office

20080093607 - Light emitting diode device, method of fabrication and use thereof: A light emitting diode device which, in use, has its light emitting region occupying a plane substantially perpendicular to a plane occupied by the surface on which the device is mounted. The primary light emission directions of the light emitting region are parallel to the surface on which the device... Agent: Wells St. John P.s.

20080093612 - Semiconductor light emitting device: A plurality of semiconductor layers including an active layer 6 and a light extract layer 4, and a reflective metal film 11 are formed in a semiconductor light emitting device. The light extract layer 4 is formed of a plurality of layers 23, 24 having different composition ratios. An irregularity... Agent: Mcginn Intellectual Property Law Group, PLLC

20080093613 - Imager device with electric connections to electrical device: An imager device is disclosed including a first substrate having an array of photo-sensitive elements formed thereon, a first conductive layer formed above the first substrate, a first conductive member extending through the first substrate, the first conductive member being conductively coupled to the first conductive layer, a standoff structure... Agent: Williams, Morgan & Amerson

20080093615 - Method for obtaining a better color rendering with a photoluminescence plate: The present invention is a method for obtaining a better color rendering with a photoluminescence plate, and the better color rendering is obtained by using UV radiating on the photoluminescence plate stacked with a red photoluminescence plate, a green photoluminescence plate and a blue photoluminescence plate. Therefore, the color rendering... Agent: Nikolai & Mersereau, P.A.

20080093617 - Multiple reflection layer electrode, compound semiconductor light emitting device having the same and methods of fabricating the same: Provided are a multiple reflection layer electrode, a compound semiconductor light emitting device having the same and methods of fabricating the same. The multiple reflection layer electrode may include a reflection layer on a p-type semiconductor layer, an APL (agglomeration protecting layer) on the reflection layer so as to prevent... Agent: Harness, Dickey & Pierce, P.L.C

20080093619 - Semiconductor light emitting device: A first conductivity type cladding layer 2, a first side multilayer 9, an active layer 4, a second side multilayer 10, and a second conductivity type cladding layer 3 are provided in a semiconductor light emitting device. The first side multilayer 9 is provided between the first conductivity type cladding... Agent: Mcginn Intellectual Property Law Group, PLLC

20080093618 - Vertical light emitting diode and method of manufacturing the same: Provided is a vertical LED including an n-electrode; an n-type GaN layer formed under the n-electrode, the n-type GaN layer having a surface coming in contact with the n-electrode, the surface having a Ga+N layer containing a larger amount of Ga than that of N; an active layer formed under... Agent: Mcdermott Will & Emery LLP

20080093620 - Led package and manufacturing method thereof: A light emitting diode (LED) package including a carrier, an adhering layer and an LED chip is provided. The adhering layer is disposed on the carrier. The LED chip is disposed on the adhering layer and electrically connected to the carrier. The material of the adhering layer comprises a lead-free... Agent: J C Patents, Inc.

20080093589 - Resistance variable devices with controllable channels: A memory element having a first electrode is provided, wherein the first electrode comprises at least one conductive nanostructure. The memory element further includes a second electrode and a resistance variable material layer between the first and second electrodes. The first electrode electrically is coupled to the resistance variable material.... Agent: Dickstein Shapiro LLP

20080093594 - Organic semiconductor device, manufacturing method of the same, organic transistor array, and display: The present invention mainly intends to provide an organic semiconductor device having an organic semiconductor transistor reduced in off current. In order to achieve the object, the present invention provides an organic semiconductor device comprising a substrate and an organic semiconductor transistor provided with a gate electrode formed on the... Agent: Ladas & Parry LLP

20080093599 - Array substrate with reduced pixel defect, method of manufacturing the same and liquid crystal display panel having the same: An array substrate includes a transparent substrate, a switching element, an insulating layer and a pixel electrode. The switching element includes a gate electrode formed on the transparent substrate and connected to a gate line, a channel layer formed on the gate electrode and extended in a first direction, a... Agent: Macpherson Kwok Chen & Heid LLP

20080093598 - Substrate for display device, manufacturing method for same and display device: The present invention provides the substrate for a display device, comprising a scan line, a signal line and a switching element on an insulating substrate, and further comprising an interlayer insulation film and a pixel electrode, the switching element is provided at an intersection of the scan line and the... Agent: Sharp Kabushiki Kaisha C/o Keating & Bennett, LLP

20080093600 - Thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer;... Agent: Macpherson Kwok Chen & Heid LLP

20080093601 - Integrated circuit devices including a transcription-preventing pattern and methods of manufacturing the same: Integrated circuit devices are provided including a first single-crystalline layer and an insulating layer pattern on the first single-crystalline layer. The insulating layer pattern has an opening therein that partially exposes the first single-crystalline layer. A seed layer is in the opening. A second single-crystalline layer is on the insulating... Agent: Myers Bigel Sibley & Sajovec

20080093603 - Lower substrate, display apparatus having the same and method of manufacturing the same: In a lower substrate, a display apparatus having the lower substrate and a method of manufacturing the lower substrate, the lower substrate includes a pixel area and a circuit area. An image is displayed in the pixel area. A first signal electrode is disposed in a circuit area. A first... Agent: F. Chau & Associates, LLC

20080093604 - Pixel structure: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region... Agent: Jianq Chyun Intellectual Property Office

20080093605 - Method for monolithically integrating silicon carbide microelectromechanical devices with electronic circuitry: A device and method of forming electronics and microelectromechanical on a silicon carbide substrate having a slow etch rate is performed by forming circuitry on the substrate. A protective layer is formed over the circuitry having a slower etch rate than the etch rate of the silicon carbide substrate. Microelectromechanical... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20080093608 - Engineered structure for solid-state light emitters: An engineered structure of a light emitting device comprises multiple layers of alternating active and buffer materials disposed between AC or DC electrodes, which generate an electric field. The active layers comprise luminescent centers, e.g. group IV semiconductor nanocrystals, in a host matrix, e.g. a wide bandgap semiconductor or dielectric... Agent: Teitelbaum & Maclean

20080093610 - Nitride semiconductor light emitting device and fabrication method thereof: A nitride semiconductor light emitting device comprises a first nitride semiconductor layer, an active layer of a single or multiple quantum well structure formed on the first nitride semiconductor layer and including an InGaN well layer and a multilayer barrier layer, and a second nitride semiconductor layer formed on the... Agent: Birch Stewart Kolasch & Birch

20080093609 - Silicon nitride layer for light emitting device, light emitting device using the same, and method of forming silicon nitride layer for light emitting device: Provided are a silicon nitride layer for a light emitting device, light emitting device using the same, and method of forming the silicon nitride layer for the light emitting device. The silicon nitride layer of the light emitting device includes a silicon nitride matrix and silicon nanocrystals formed in the... Agent: Ladas & Parry LLP

20080093611 - Method for production of a radiation-emitting semiconductor chip: A method for micropatterning a radiation-emitting surface of a semiconductor layer sequence for a thin-film light-emitting diode chip. The semiconductor layer sequence is grown on a substrate. A mirror layer is formed or applied on the semiconductor layer sequence, which reflects back into the semiconductor layer sequence at least part... Agent: Cohen, Pontani, Lieberman & Pavane

20080093616 - Light-emitting diode illumination source: The invention provides light emitting diode illumination source having excellent properties as an illumination source such as a flat spectral distribution in the wavelength region from green to red and a sufficient emission intensity in the red region, comprising a light emitting diode having multiple peaks with a half-value width... Agent: Sughrue Mion, PLLC

20080093614 - Semiconductor light emitting device, lighting module, illumination apparatus, surface mount led, and bullet led: Disclosed is a semiconductor light emitting device (10) that includes an LED chip (14) mounted on a base substrate (12) and a phosphor (16) covering the LED chip (14). The LED chip (14) is substantially in the shape of a regular hexagonal prism and the phosphor (16) is substantially in... Agent: Snell & Wilmer L.L.P. (matsushita)

20080093622 - Light-emitter-based devices with lattice-mismatched semiconductor structures: Some aspects for the invention include a method and a structure including a light-emitting device disposed over a second crystalline semiconductor material formed over a semiconductor substrate comprising a first crystalline material.... Agent: Goodwin Procter LLP Patent Administrator

20080093621 - N-type group iii nitride semiconductor layer stacked structure: An object of the present invention provides an n-type Group III nitride semiconductor stacked layer structure of a low resistance having excellent flatness generating few cracks and pits in the uppermost surface. The inventive n-type Group III nitride semiconductor stacked layer structure comprises a first n-type layer which includes a... Agent: Sughrue Mion, PLLC

20080093623 - Insulated gate semiconductor device and method for manufacturing same: In an insulated gate semiconductor device (1) having an N− type base region (11), P+ type collector regions (12), P type base regions (13), and N+type emitter regions (14), an N+ type collector-short region (15) which extends toward the N− type base region (11) farther than the P+ type collector... Agent: Townsend And Townsend And Crew, LLP

20080093624 - Integrated circuit esd protection: A protective device in a semiconductor may comprise a substrate of a first conductivity type, an epitaxial layer formed on top of the substrate, a body area formed within the epitaxial layer of a second conductivity type extending from a top surface into the epitaxial layer, a first area of... Agent: Coats & Bennett/infineon Technologies

20080093625 - Photoconductive device: A semiconductor structure includes a GaAs or InP substrate, an InxGa1-xAs epitaxial layer grown on the substrate, where x is greater than about 0.01 and less than about 0.53, and a wider bandgap epitaxial layer grown as a cap layer on top of the InxGa1-xAs epitaxial layer.... Agent: Brinks Hofer Gilson & Lione

20080093629 - Metal oxide field effect transistor with a sharp halo: Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080093628 - Methods of forming semiconductor devices having multiple channel mos transistors and related intermediate structures: In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is partially etched... Agent: Myers Bigel Sibley & Sajovec

20080093626 - Nitride semiconductor device: A nitride semiconductor device includes: a first nitride semiconductor layer formed of non-doped AlxGa1-XN (0≦X<1); a second nitride semiconductor layer formed on the first nitride semiconductor layer of non-doped or n-type AlYGa1-YN (0<Y≦1, X<Y), and having a smaller lattice constant than that of the first nitride semiconductor layer; a third... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080093627 - Semiconductor mos transistor device and method for making the same: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the... Agent: North America Intellectual Property Corporation

20080093630 - Heterostructure field effect transistor: A HEMT has a substrate (2), buffer layer (4), channel layer (8), spacer layer (10), delta doped layer (12), Schottky barrier layer (14) and cap layer (18) and metal layer (20), the latter forming a Schottky barrier with the underlying semiconductor. The channel may be of GaInAs and the barrier... Agent: Philips Intellectual Property & Standards

20080093631 - Contact structure for semiconductor devices: A semiconductor device has a substrate of one type of semiconductor material, such as silicon. A contact structure is formed on the substrate, and the contact structure is formed of a compound of a metal and a second type of semiconductor material, such as germanium. The contact structure according to... Agent: Kenyon & Kenyon LLP

20080093632 - Size-reduced layout of cell-based integrated circuit with power switch: An integrated circuit is provided with a first power line, a plurality of additional power lines intersecting with the first power line, a plurality of power switch transistors each having a drain connected with the first power line and a source connected with one of the additional power lines, a... Agent: Mcginn Intellectual Property Law Group, PLLC

20080093633 - Complementary metal-oxide-semiconductor (cmos) image sensor and fabricating method thereof: A complementary metal-oxide-semiconductor (CMOS) image sensor including a substrate, a p type well, a light emitting diode, a p type gate structure and a plurality of n type gate structures is provided. The substrate has a photo sensitive region and a transistor device region, and the p type well is... Agent: Jianq Chyun Intellectual Property Office

20080093634 - Silicon-on-insulator based radiation detection device and method: Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the buried insulator layer. Active layer may be fully depleted. A transistor is... Agent: Hoffman, Warnick & D'alessandro LLC

20080093635 - Junction fet and method of manufacturing the same: A shallow channel region is selectively formed by ion implantation and diffusion. Since the channel region forms pn junctions with a p type semiconductor layer having a relatively low impurity concentration, a reduction of a junction capacitance leads to improvement in high-frequency characteristics. Moreover, since a gate region can also... Agent: Morrison & Foerster LLP

20080093636 - Scalable process and structure for jfet for small and decreasing line widths: A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms or less on... Agent: Perkins Coie LLP

20080093637 - Vertical junction field effect transistor with mesa termination and method of making the same: A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n-type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type... Agent: Merchant & Gould PC

20080093638 - Semiconductor device: In a J-FET for large current use, there has been a limitation on reduction in a chip size or enlargement of the operation regions because two operation regions are arranged in line along a diagonal line of a chip. To eliminate the limitation, in this invention, gate regions are extended... Agent: Morrison & Foerster LLP

20080093639 - Method for forming gate insulating layer of mos transistor: A method for forming a gate insulating layer of a Metal Oxide Semiconductor (MOS) transistor includes forming an oxide layer on a semiconductor substrate, implanting plasma nitrogen ions into the oxide layer, and performing heat treatment on the nitrogen ion-implanted oxide layer to eliminate damage to a surface of the... Agent: Sherr & Nourse, PLLC

20080093640 - Method for tuning epitaxial growth by interfacial doping and structure including same: A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of this scheme into the process integration... Agent: Scully, Scott, Murphy & Presser, P.C.

20080093641 - Method of manufacturing a multi-path lateral high-voltage field effect transistor: High-Voltage Lateral MOSFET and Lateral Double-diffused MOS (LDMOS) for HV power applications with multiple paths for conduction in the drain extension and methods of fabrication are described.... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080093642 - Image sensor and fabricating method thereof: Embodiments relate to an image sensor having a gate spacer and a fabricating method by which damage in a photodiode area can be prevented. Embodiments relate to a method of fabricating an image sensor including forming a gate electrode over a substrate having a prescribed photodiode area. A first oxide... Agent: Sherr & Nourse, PLLC

20080093643 - Non-volatile memory device and fabrication method: Provided is a non-volatile memory device capable of operating with two cells at each one unit. The memory cell unit includes a common source region on an active region, a select gate covering the common source region, a first memory gate on the active region adjacent to one side of... Agent: Volentine & Whitt PLLC

20080093644 - Dram arrays, vertical transistor structures, and methods of forming transistor structures and dram arrays: The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars. After the etching, dopant is implanted within the trenches to... Agent: Wells St. John P.s.

20080093645 - Fabrication process for increased capacitance in an embedded dram memory: An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080093646 - Non-volatile memory device and method for fabricating the same: A non-volatile memory device comprises a semiconductor substrate having source/drain regions formed at both ends of a channel region, a gate structure forming an offset region by being separated a predetermined distance from the source region and comprising a charge accumulation region and a control gate sequentially deposited in the... Agent: Mills & Onello LLP

20080093647 - Split gate non-volatile memory devices and methods of forming the same: Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080093651 - Flash memory devices and methods for fabricating flash memory devices: A flash memory device includes a cell string having a plurality of cell transistors connected in series, and a string selection transistor and a ground selection transistor connected to both ends of the cell string, respectively, wherein the cell transistor has a channel impurity concentration higher than a channel impurity... Agent: Lee & Morse, P.C.

20080093649 - Non-volatile memory device and methods of manufacturing and operating the same: A non-volatile memory device and methods of manufacturing and operating the same are provided. In a method of manufacturing a non-volatile memory device, a substrate having a stepped portion that may include a first horizontal face, a second horizontal face lower than the first horizontal face, and a vertical face... Agent: Harness, Dickey & Pierce, P.L.C

20080093648 - Non-volatile memory devices including double diffused junction regions and methods of fabricating the same: A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between... Agent: Myers Bigel Sibley & Sajovec

20080093650 - Nonvolatile memory device and method of forming the same: Provided is a nonvolatile memory device and a method of forming the nonvolatile memory device. The nonvolatile memory device includes a floating gate formed on a first active region doped with a first-conductivity-type dopant. The floating gate is doped with the first-conductivity-type dopant. Therefore, the thickness of a tunnel insulation... Agent: Mills & Onello LLP

20080093652 - Semiconductor device and method of manufacturing same: A semiconductor device comprising: a transistor region formed on a semiconductor substrate and having a plurality of memory cell arrays formed of a plurality of memory cell transistors and select transistors one each of which is disposed on one and the other sides of said plurality of memory cell transistors;... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080093653 - Nonvolatile memory devices and methods for forming same: Non-volatile memory devices include a substrate with first and second semiconductor active regions therein. These active regions are separated from each other by a trench isolation region, which has a recess therein that extends along its length. First and second floating gate electrodes are provided. These first and second floating... Agent: Myers Bigel Sibley & Sajovec

20080093654 - Non-volatile two-transistor programmable logic cell and array layout: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within... Agent: Sierra Patent Group, Ltd.

20080093655 - Semiconductor device and method for forming the same: Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor substrate includes a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region; a plurality of device isolation patterns defining the cell region, the peripheral region, and the... Agent: Mills & Onello LLP

20080093656 - Semiconductor devices and methods of fabricating the same: A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the... Agent: Lee & Morse, P.C.

20080093657 - Nonvolatile memory devices and methods of fabricating the same: A method of fabricating a nonvolatile memory device includes forming at least one insulating layer on at least one of a semiconductor substrate and a layer including a semi-conductive material, and performing a plasma process using fluorine on the semiconductor. In some cases, an interface between the insulating layer and... Agent: Lee & Morse, P.C.

20080093658 - Method for nitriding tunnel oxide film, method for manufacturing non-volatile memory device, non-volatile memory device, control program and computer-readable recording medium: When nitriding a tunnel oxide film in a nonvolatile memory device a nitrided region is formed in the surface portion of the tunnel oxide film by a plasma processing using a process gas containing nitrogen gas.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080093659 - Electrically programmable resistor and methods: Methods of electrically programming a diffusion resistor by using trapped charge in a trapped charge region adjacent to the resistor to vary the resistance of the resistor, and the resistor, are disclosed. In one embodiment, a method includes forming a diffusion resistor in a substrate; forming a trapped charge region... Agent: Hoffman, Warnick & D'alessandro LLC

20080093660 - Flash memory device and method for manufacturing the same: A flash memory device includes a semiconductor substrate, a gate insulating layer having a first width formed on the semiconductor substrate to trap carriers tunneled from the semiconductor substrate and a metal electrode on the gate insulating layer to receive a voltage required for tunneling. The metal electrode having a... Agent: F.chau & Associates, LLC

20080093661 - Non-volatile memory device having a charge trapping layer and method for fabricating the same: A non-volatile memory device comprises a substrate, a tunneling layer over the substrate, a charge trapping layer comprising a stoichiometric silicon nitride layer and a silicon-rich silicon nitride layer over the tunneling layer, a blocking layer over the charge trapping layer, and a control gate electrode over the blocking layer.... Agent: Townsend And Townsend And Crew, LLP

20080093663 - Nonvolatile memory device and method for forming the same: A method of forming a memory device includes forming a first insulating pattern and a polysilicon pattern in a peripheral region of a substrate, forming a cell gate insulating pattern including a second insulating pattern, a charge storage pattern, and a third insulating pattern in a cell region of the... Agent: Lee & Morse, P.C.

20080093662 - Semiconductor memory device including recessed control gate electrode: A semiconductor memory device may include a semiconductor substrate, at least one control gate electrode, at least one storage node layer, at least one tunneling insulating layer, at least one blocking insulating layer, and/or first and second channel regions. The at least one control gate electrode may be recessed into... Agent: Harness, Dickey & Pierce, P.L.C

20080093664 - Memory device and method of manufacturing the same: In a memory device and a method of manufacturing the memory device, the memory device includes a first gate electrode enclosed by a first gate insulating layer, a second gate electrode enclosed by a second gate insulating layer that can be an ONO layer, and a channel region vertically extending... Agent: Mills & Onello LLP

20080093665 - Semiconductor apparatus and method of manufacturing the same: A vertical power MOSFET includes a semiconductor substrate including a trench, a gate electrode layer having a prescribed impurity concentration and being formed inside the trench, and a cap insulating layer having a lower impurity concentration than the impurity concentration of the gate electrode layer and covering the gate electrode... Agent: Mcginn Intellectual Property Law Group, PLLC

20080093666 - Semiconductor device and manufacturing method thereof: A semiconductor device having a simple structure with selectively formed full-silicide (FUSI) and partial silicide gate electrodes and a manufacturing method thereof are provided. According to one aspect, there is provided a semiconductor device includes a first field effect transistor (MOSFET), and a second MOSFET, the first MOSFET including a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080093667 - Metal-oxide-semiconductor device having trenched diffusion region and method of forming same: An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A... Agent: Ryan, Mason & Lewis, LLP

20080093669 - Semiconductor device and method of manufacturing the same: The present invention aims at offering the semiconductor device which has the structure which are a high speed and a low power, and can be integrated highly. The present invention is a semiconductor device formed in the SOI substrate by which the BOX layer and the SOI layer were laminated... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080093668 - Method for the manufacture of a semiconductor device and a semiconductor device obtained through it: The invention relates to a semiconductor device (10) having a semiconductor body (2), comprising a field effect transistor, a first gate dielectric (6A) being formed on a first surface at the location of the channel region (5) and on it a first gate electrode (7), a sunken ion implantation (20)... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080093670 - Signal and/or ground planes with double buried insulator layers and fabrication process: The present invention describes a method including the steps of providing a single crystal semiconductor substrate, forming a layer of rare earth silicide on a surface of the semiconductor substrate, forming a first layer of insulating material on the layer of rare earth silicide, forming a layer of electrically conductive... Agent: Robert A. Parsons

20080093671 - Semi-conductor element comprising an integrated zener diode and method for the production thereof: In order to protect a semiconductor component against overvoltages, the steps which are used for production of bipolar transistors and CMOS structures in the semiconductor component are used for integrated parallel production of a zener diode. This has a first and a second n-doped zone, which extend between the surface... Agent: Thomas Langer Cohen Pontani Lieberman & Pavane

20080093672 - String contact structure for high voltage esd: The present invention relates to an electrostatic discharge (ESD) protection scheme and particularly to a string contact structure for an improved ESD performance. In an embodiment, the invention provides a method for forming an ESD protection circuit for protecting an internal circuit from damage due to an ESD voltage appearing... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20080093673 - Semiconductor device and fabrication method thereof: A semiconductor device includes a first MIS transistor on a first active region of a semiconductor substrate, the first MIS transistor including: a first gate insulating film provided on the first active region; a first gate electrode provided on the first gate insulating film; a first stressor insulating film provided... Agent: Mcdermott Will & Emery LLP

20080093674 - Fin field effect transistor and method of manufacturing the same: In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern... Agent: Mills & Onello LLP

20080093675 - Mos devices with continuous contact etch stop layer: A semiconductor structure includes a substrate, a gate stack on the substrate, a source/drain region adjacent the gate stack, a source/drain silicide region on the source/drain region, a protection layer on the source/drain silicide region, wherein a region over the gate stack is substantially free from the protection layer, and... Agent: Slater & Matsil, L.L.P.

20080093676 - Semiconductor device and fabrication method thereof: A semiconductor device having a field effect transistor (FET) with enhanced performance by reduction of electrical contact resistance of electrodes and resistance of the electrodes per se is disclosed. The FET includes an n-type FET having a channel region formed in a semiconductor substrate, a gate electrode insulatively overlying the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080093678 - Nand type non-volatile memory device and method of forming the same: A NAND type non-volatile memory device and a method for forming the same. Well bias lines are disposed substantially parallel to other wiring lines at equal intervals. Active regions that are electrically connected to the well bias line are disposed substantially parallel to other active regions at the same equal... Agent: F. Chau & Associates, LLC

20080093677 - Semiconductor devices and methods of fabricating the same: Provided are semiconductor devices and methods of fabricating the same. A semiconductor device may include a semiconductor substrate with a device isolation layer defining HVE and HVD active regions. Gate insulation layer patterns may be disposed on the HVE and HVD active regions. Gate electrodes may be disposed on the... Agent: Myers Bigel Sibley & Sajovec

20080093679 - Semiconductor device: At least part of an element isolation region, an interlayer insulating film, and a protection insulating film, other than a gate insulating film (silicon oxide film), is formed of carbon fluoride (CFx, 0.3<x<0.6) or hydrocarbon (CHy, 0.8<y<1.2).... Agent: Foley And Lardner LLP Suite 500

20080093680 - Oxide-nitride stack gate dielectric: A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is... Agent: Evan Law Group, LLC

20080093681 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a semiconductor substrate; an isolation region formed on a semiconductor substrate, the top surface of the isolation region being located above the top surface of the semiconductor substrate; a fully silicided gate line continuously formed to cover part of the top surface of an active region... Agent: Mcdermott Will & Emery LLP

20080093682 - Polysilicon levels for silicided structures including mosfet gate electrodes and 3d devices: Semiconductor structures having a silicided gate electrode and methods of manufacture are provided. A device comprises a first silicided structure formed in a first active region and a second silicided structure formed in a second active region. The two silicided structures have different metal concentrations. A method of forming a... Agent: Slater & Matsil, L.L.P.

20080093683 - Semiconductor scheme for reduced circuit area in a simplified process: An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20080093687 - Flexible fingerprint sensor: A flexible pressure sensor has a first set of substantially parallel conductors in the x direction, a second set of substantially parallel conductors in the y direction, and a composite material disposed between the first set and second set of conductors. The composite material is capable of returning to substantially... Agent: Chalker Flores, LLP

20080093685 - Mems device: A microelectromechanical system (MEMS) device includes a semiconductor substrate, a MEMS including a fixed electrode and a movable electrode formed on the semiconductor substrate through an insulating layer, and a well formed in the semiconductor substrate below the fixed electrode. The well is one of an n-type well and a... Agent: Harness, Dickey & Pierce, P.L.C

20080093684 - Mems device and fabrication method thereof: A micro electro mechanical system (MEMS) device includes: a fixed electrode made of silicon and provided above a semiconductor substrate; a movable electrode made of silicon and arranged in a mechanically movable manner by having a gap from the semiconductor substrate; and a wiring layered part that is provided around... Agent: Harness, Dickey & Pierce, P.L.C

20080093686 - Electromechanical non-volatile memory devices: Electromechanical non-volatile memory devices are provided including a semiconductor substrate having an upper surface including insulation characteristics. A first electrode pattern is provided on the semiconductor substrate. The first electrode pattern exposes portions of a surface of the semiconductor substrate therethrough. A conformal bit line is provided on the first... Agent: Myers Bigel Sibley & Sajovec

20080093689 - Flip-chip assembly of protected micromechanical devices: A low-cost ceramic package, in land-grid array or ball-grid array configuration, for micromechanical components is fabricated by coating the whole integrated circuits wafer with a protective material, selectively etching the coating for solder ball attachment, singulating the chips, flip-chip assembling a chip onto the opening of a ceramic substrate, underfilling... Agent: Texas Instruments Incorporated

20080093691 - Mem switching device and method for making same: A MEM device and method for fabricating a MEM device. A MEM device comprising a lever mechanism residing along a substrate is disclosed. A contact material is deposited on a first surface of the lever mechanism. In one arrangement, the first surface is disposed towards the substrate. A first contact... Agent: Steven Weseman Associate General Counsel, I.p.

20080093690 - Micromechanical component having a monolithically integrated circuit and method for manufacturing a component: A micromechanical component and a method for manufacturing such a component, the component having a micromechanical structure and an integrated circuit, the micromechanical structure being monolithically integrated into the circuit, the circuit being provided in a circuit area of the substrate, and the micromechanical structure being provided in a sensor... Agent: Kenyon & Kenyon LLP

20080093688 - Process for modifying offset voltage characteristics of an interferometric modulator: An interferometric modulator manufactured according to a particular set of processing parameters may have a non-zero offset voltage. A process has been developed for modifying the processing parameters to shift the non-zero offset voltage closer to zero. For example, the process may involve identifying a set of processing parameters for... Agent: Knobbe, Martens, Olson & Bear, LLP

20080093692 - Audio processing device with encapsulated electronic component: The invention regards an audio processing device with at least one encapsulated electronic component mounted and electrically connected to electric leads in a mounting substrate. Further electric components are mounted for connection with the encapsulated electronic component through the substrate and the encapsulation material is moulded onto the substrate. According... Agent: Dykema Gossett PLLC

20080093693 - Nanowire sensor with variant selectively interactive segments: A nanowire sensor is operable to detect one or more species. The nanowire sensor includes a nanowire having a plurality of variant selectively interactive segments. Each of the variant selectively interactive segments are configured to simultaneously interact with the species to modulate the conductance of the nanowire for detecting the... Agent: Hewlett Packard Company

20080093694 - Method for manufacturing a semcoductor component and a semiconductor component, in particular a diaphragm sensor: In a method for manufacturing a semiconductor component having a semiconductor substrate, a flat, porous diaphragm layer and a cavity underneath the porous diaphragm layer are produced to form unsupported structures for a component. In a first approach, the semiconductor substrate may receive a doping in the diaphragm region that... Agent: Kenyon & Kenyon LLP

20080093695 - Image sensor and fabricating method thereof: An image sensor including a substrate having a plurality of semiconductor devices formed thereon, an interconnection layer disposed on the substrate, and a plurality of isolated photo-diodes embedded in the interconnection layer is provided. The isolated photo-diodes are located above the semiconductor devices and electrically connected to the semiconductor devices... Agent: Jianq Chyun Intellectual Property Office

20080093696 - Solid state imaging device and manufacturing method thereof: A light shielding film, an insulating layer, a planarizing layer, and a color filter are formed consecutively on a semiconductor substrate having plural photodiodes in a matrix arrangement. A transparent conductive film is formed on the color filter, and micro-lenses are formed directly on the conductive film such that they... Agent: Birch Stewart Kolasch & Birch

20080093697 - Semiconductor device and manufacturing method thereof: A second impurity region is surrounded by a first impurity region at a first main surface. A third impurity region of the first main surface sandwiches the second impurity region with the first impurity region. Fourth and fifth impurity regions of a second main surface sandwich the first impurity region... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080093698 - Nanostructure arrays and methods for forming same: A method for forming an array of elongated nanostructures, includes in one embodiment, providing a substrate, providing a template having a plurality of pores on the substrate, and removing portions of the substrate under the plurality of pores of the template to form a plurality of cavities. A catalyst is... Agent: General Electric Company Global Research

20080093699 - Semiconductor device and method of manufacturing the same: The semiconductor device includes a plurality of transistors at least having different channel widths from each other. Threshold voltages of those transistors are set to be substantially equal to each other, by using both of substantially the same channel dose for each of those transistors, and work function control using... Agent: Young & Thompson

20080093701 - Semiconductor device and method for fabricating the same: A semiconductor device includes a device isolation layer on a semiconductor substrate defining an active region in the semiconductor substrate, a low voltage well of a first conductivity type in the active region of the semiconductor substrate, a high voltage impurity region of a second conductivity type in the active... Agent: Lee & Morse, P.C.

20080093700 - Semiconductor device and method for operating the same: A method for operating a semiconductor device is described, the semiconductor device including a high-voltage device and a control circuit coupled to each other on a single chip and the high-voltage device including a source, a drain and a gate. This method applies a drain voltage of about 20V or... Agent: Jianq Chyun Intellectual Property Office

20080093702 - Semiconductor device having a passive device: The present invention relates to a semiconductor device having a passive device. The semiconductor device includes a substrate and at least one passive device. The substrate has at least one via. The via has at least two conductive elements therein. The conductive elements are not electrically connected to each other.... Agent: Volentine & Whitt PLLC

20080093703 - Electrical fuse and method of making: A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a substrate, forming a trench feature in the substrate, depositing fuse material in the trench feature, depositing... Agent: Greenblum & Bernstein, P.L.C

20080093704 - Semiconductor device having moisture-proof dam and method of fabricating the same: A semiconductor device having a moisture-proof dam and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating layer provided on a substrate having a fuse region. A fuse guard dam is provided on the interlayer insulating layer to surround the fuse region. A cover... Agent: Myers Bigel Sibley & Sajovec

20080093705 - Semiconductor device preventing bridge between fuse pattern and guard ring: A semiconductor device having a fuse structure that can prevent a bridge between a fuse pattern and a guard ring, and a method of fabricating the same are provided. The fuse pattern formed on a multiple-layered metal interconnect layer is stepped shape increasing a vertical distance between the fuse pattern... Agent: Volentine & Whitt PLLC

20080093706 - Semiconductor device and method of manufacturing the same: Provided is a semiconductor device that solves the problem of a conventional semiconductor device. In the conventional semiconductor device, a resistor is connected with a wiring layer via a contact hole, so that a reduction in parasitic capacitance of the resistor and a substrate is hard to be accomplished. In... Agent: Morrison & Foerster LLP

20080093707 - Semiconductor device provided with floating electrode: A semiconductor device has a first conductivity-type first semiconductor region, a second conductivity-type second semiconductor region and a second conductivity-type third semiconductor region both located on or above the first semiconductor region, a second conductivity-type fourth semiconductor region between the second semiconductor region and the third semiconductor region, and a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080093708 - Semiconductor device and manufacturing method thereof: A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate... Agent: Morrison & Foerster LLP

20080093709 - Manufacturing method of semiconductor device and semiconductor device: A semiconductor substrate in a state that an inter-layer insulation film is formed is loaded in a chamber, air in the chamber is purged by introducing a large amount of a nitrogen gas in the chamber, and an atmospheric gas in the chamber is substituted with a nitrogen gas. After... Agent: Mcdermott Will & Emery LLP

20080093710 - Hard mask arrangement, contact arrangement and methods of patterning a substrate and manufacturing a contact arrangement: An interlayer is disposed on a pattern surface of a substrate. A buried hard mask may be provided on the interlayer. The buried hard mask includes a template opening having a template length along a line axis and a template width perpendicular thereto. The buried hard mask is filled with... Agent: Edell, Shapiro & Finnan, LLC

20080093711 - Dielectric layers and methods of forming the same: High dielectric constant (high-k) materials are formed directly over oxidation-susceptible conductors such as silicon. A discontinuous layer is formed, with gaps between grains of the high-k material. Exposed conductor underneath the grain boundaries is oxidized or nitridized to form, e.g., silicon dioxide or silicon nitride, when exposed to oxygen or... Agent: Knobbe Martens Olson & Bear LLP

20080093712 - Chip with light protection layer: In the case of a chip (1) having an integrated circuit (2), a dielectric mirror coating (3) having at least two dielectric layers (6, 7, . . . H, I, H) is applied as light protection means for the at least one integrated circuit (2) on at least one portion... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080093713 - Metal clad fiber optics for enhanced heat dissipation: An integrated optical I/O and semiconductor chip with a direct liquid jet impingement cooling assembly are disclosed. Contrary to other solutions for packaging an optical I/O with a semiconductor die, this assembly makes use of a metal clad fiber, e.g. copper, which will actually enhance cooling performance rather than create... Agent: International Business Machines Corporation

20080093714 - Semiconductor device and method of fabricating the same: A semiconductor device and method of fabricating the same reduce the likelihood of the occurrence of electrical defects. The device includes a first interlayer insulating film on a semiconductor substrate; a contact pad spacer on the first interlayer insulating film; and a contact pad in the first interlayer insulating film... Agent: Mills & Onello LLP

20080093715 - Leadframe and mold compound interlock in packaged semiconductor device: An interference interlock between leadframe features and a mold compound is provided in a packaged semiconductor device by exposing at least one predetermined surface area to an etching process prior to a molding step. This produces an etched recess with a recessed wall delimited by a step wall, generally perpendicular... Agent: Texas Instruments Incorporated

20080093716 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device of the present invention includes a lead frame having an island portion having a roughened upper surface and side faces, and an unroughened lower surface, and also having a plurality of leads having roughened inner lead portions and unroughened outer lead portions; a semiconductor chip placed on... Agent: Young & Thompson

20080093717 - Leadframe of a leadless flip-chip package and method for manufacturing the same: A leadframe of a leadless flip-chip package includes a plurality of inner leads, a nonconductive ink layer and a solder mask layer. The inner leads have a plurality of bump-connecting terminals, a plurality of outer terminals and a plurality of redistribution lead portions. A half-etched recession is formed on lower... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080093718 - Semiconductor component and method of manufacture: A semiconductor component having a semiconductor chip mounted on a packaging substrate and a method for manufacturing the semiconductor component that uses batch processing steps for fabricating the packaging substrate. A heatsink is formed using an injection molding process. The heatsink has a front surface for mating with a semiconductor... Agent: Hvvi Semiconductors, Inc.

20080093719 - Chip package structure: A chip package structure including a chip, a leadframe, multiple bonding wires and an encapsulant is provided. The chip has an active surface and multiple contacts. The contacts are located on one side of the active surface. The chip is fixed under the leadframe. The leadframe has multiple first inner... Agent: J C Patents, Inc.

20080093720 - Single chip usb packages with contact-pins cover: A low-profile Universal-Serial-Bus (USB) assembly includes a modular USB core component that is retractably mounted into an external housing. The modular USB core component includes a PCBA in which all passive components and unpackaged IC chips are attached to a single side of a PCB opposite to the metal contacts.... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080093721 - Chip package for image sensor and method of manufacturing the same: A chip package for an image sensor includes a first semiconductor chip having a first surface where a photographing device and a first circuit pattern are formed and a second surface that is opposite to the first surface where a second circuit pattern is formed. The first and second circuit... Agent: Drinker Biddle & Reath LLP Attn: Patent Docket Dept.

20080093722 - Encapsulation type semiconductor device and manufacturing method thereof: An encapsulation type semiconductor device and a manufacturing method of the encapsulation type semiconductor device are disclosed. The encapsulation type semiconductor device includes a substrate provided with a concave portion which concaves in a direction from a first principal surface portion to a second principal surface portion. A first semiconductor... Agent: SprinkleIPLaw Group

20080093723 - Passive placement in wire-bonded microelectronics: A microelectronic assembly includes a first microelectronic device electrically coupled with a second microelectronic device via wire bond attachment, the first microelectronic device being structurally coupled with the second microelectronic device via a polymer adhesive, and one or more passive(s) coupled with the first microelectronic device wherein at least one... Agent: Intel Corporation C/o Intellevate, LLC

20080093725 - Semiconductor package preventing warping and wire severing defects, and method of manufacturing the semiconductor package: Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package includes a circuit substrate having a slit inside the circuit substrate, a semiconductor chip formed on an upper surface of the circuit substrate, a wire connecting the semiconductor chip and the circuit substrate through the... Agent: Marger Johnson & Mccollom, P.C.

20080093724 - Stackable micropackages and stacked modules: The present invention provides a system and method for devising stackable assemblies that may be then stacked to create a stacked circuit module. One or more integrated circuit (IC) die are disposed on one or more sides of a redistribution substrate that is preferably flexible circuitry. In some preferred embodiments,... Agent: Fish & Richardson P.C.

20080093726 - Continuously referencing signals over multiple layers in laminate packages: A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the voltage reference. A reference plane adjustment engine analyzes a... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080093727 - Metallised film for sheet contacting: An embodiment of the present invention discloses a method for contacting at least one electrical contact surface on a surface of a substrate and/or at least one component arranged on the substrate, especially a semiconductor chip. The method includes the following steps: at least one insulating film consisting of an... Agent: Harness, Dickey & Pierce, P.L.C

20080093728 - Integrated circuit component with passivation layer and methods for making the same: The invention relates to a semiconductor component (1) comprising a semiconductor chip (3) provided with a passivation layer (2), and to methods for producing the same. In this case, the passivation layer (2) covers the topmost interconnect structure (4) of the semiconductor chip (1) whilst leaving contact areas (5) free.... Agent: Edell , Shapiro & Finnan , LLC

20080093729 - Semiconductor arrangement, semiconductor module, and method for connecting a semiconductor chip to a ceramic substrate: A semiconductor arrangement has a silicon body with a first surface and a second surface and a thick metal layer arranged on at least one surface of the silicon body. The thickness of the thick metal-layer is at least 10 micrometers (μm).... Agent: Coats & Bennett/infineon Technologies

20080093730 - Semiconductor module and semiconductor device: Electrode plates (52, 54) acting as a heat sink are arranged to sandwich a power transistor (Q1) and a diode (D1). Electrode plates (52, 54) at their surfaces opposite cooling elements (62, 64) at a portion opposite power transistor (Q1) and diode (D1) are formed to be smaller in thickness... Agent: Oliff & Berridge, PLC

20080093731 - Cooled integrated circuit: The invention relates to an integrated circuit (1) having a plurality of substrate layers (2), active and/or passive components (3) embedded in the substrate layers (2), high-frequency lines conducted to the components (3) through the substrate layers (2), and cooling channels (6) for the dissipation of heat. The inventive circuit... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20080093732 - Packaging for high power integrated circuits using supercritical fluid: A package for a semiconductor chip or other heat producing device has a supporting substrate to which the devices mount and electrically connect. An enclosure is formed over the heat producing devices and filled with a supercritical fluid that transports heat from the devices to a heat sink in thermal... Agent: Quarles & Brady LLP

20080093733 - Chip package and manufacturing method thereof: A chip package including a carrier, at least one chip, a heat spreader, and a thermal interface material (TIM) is provided. The chip is disposed on the carrier and is electrically connected to the carrier. The heat spreader is disposed on the carrier, wherein the heat spreader and the carrier... Agent: J C Patents, Inc.

20080093734 - High density ic module: A system a method for assembling dual-die integrated circuit packages using thermocompression bonding or thermosonic bonding to bond a second die to a substrate opposite a first die bonded to the substrate. The second die is bonded using heat conducted through the first die to the substrate, and optionally through... Agent: Fish & Richardson P.C.

20080093735 - Potted integrated circuit device with aluminum case: An integrated circuit device includes a die, a lead, and an electrically-conductive structure that is arranged to facilitate electrical communication between the die and the lead. The device also includes a potting material, in which the electrically conductive structure, the die, and at least part of the lead are embedded.... Agent: Mayer & Williams PC

20080093736 - Semiconductor device: A semiconductor die has a top surface and a bottom surface. A source contact, a gate contact and a gate finger are formed on the top surface. The source contact has a slit and the gate finger is disposed in the slit of the source contact. A drain contact is... Agent: Young & Thompson

20080093740 - Capacitive semiconductor sensor: A capacitive semiconductor sensor includes a sensor chip, a circuit chip, a plurality of bumps, and a plurality of dummy bumps. The sensor chip includes a dynamic quantity detector, which has a detection axis in one direction. The circuit chip includes a signal processing circuit. The sensor chip and the... Agent: Posz Law Group, PLC

20080093738 - Chip structure and wafer structure: A chip structure including a substrate, at least one pad, at least one protruding pattern, a passivation layer, and at least one bump is provided. The substrate has a circuit unit. The pad and the protruding pattern are disposed on the circuit unit, and the pad is surrounded by the... Agent: Jianq Chyun Intellectual Property Office

20080093737 - Integrated circuit with a reduced pad bump area and the manufacturing method thereof: An integrated circuit with a reduced pad bump area and the manufacturing method thereof are disclosed. The integrated circuit includes a semiconductor substrate, an interconnection layer, a passivation layer, and at least a bump. The semiconductor substrate has a semiconductor device thereon. The interconnection layer is disposed on the semiconductor... Agent: J C Patents, Inc.

20080093739 - Semiconductor mounting substrate and method for manufacturing the same: A semiconductor mounting substrate according to the present invention comprises: a substrate; a semiconductor device, mounted on this substrate; solder bumps, which connect the semiconductor device and the substrate; a first resin, filled in a space between the semiconductor device and the substrate; and electronic components, mounted on a face... Agent: Wenderoth, Lind & Ponack L.L.P.

20080093741 - Semiconductor device and method of fabricating the same: In a semiconductor device and a method of fabricating the same, the semiconductor device includes a contact pad in a first interlayer insulating layer on a semiconductor substrate, a contact hole in a second interlayer insulating layer on the first interlayer insulating layer, selectively exposing the contact pad, a contact... Agent: Mills & Onello LLP

20080093744 - Anodization: Embodiments of anodization are disclosed.... Agent: Hewlett Packard Company

20080093743 - Sub-lithographic nano interconnect structures, and method for forming same: A method to form interconnect structures including nano-scale, e.g., sub-lithographic, lines and vias for future generation of semiconductor technology using self-assembly block copolymers that can be placed at a specific location using a pre-fabricated hard mask pattern is provided. The inventive method provides an interconnect structure in which the line... Agent: Scully, Scott, Murphy & Presser, P.C.

20080093742 - System for shielding integrated circuits: A method for adding an additional layer to an integrated circuit, the method including providing an integrated circuit having an interconnect layer, depositing, over substantially all of an exposed surface of the integrated circuit, an additional layer of material whose conductivity can be altered, and selectively altering the conductivity of... Agent: Welsh & Katz, Ltd

20080093745 - High performance system-on-chip using post passivation process: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting... Agent: Mou-shiung Lin

20080093746 - Semiconductor wafer having embedded electroplating current paths to provide uniform plating over wafer surface: A semiconductor wafer having multi-layer metallization structures that are fabricated to include embedded interconnection structures which serve as low-resistance electroplating current paths to conduct bulk electroplating current fed to portions of a metallic seed layer at peripheral surface regions of the wafer to portions of the metallic seed layer at... Agent: F. Chau & Associates, LLC

20080093747 - Three dimensional device integration method and integrated device: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080093748 - Semiconductor package and fabrication process thereof: A semiconductor package mainly includes a chip, a substrate, an encapsulant, a plurality of external terminals and a stress release layer. The substrate has an upper surface and a lower surface. The chip is disposed on the upper surface of the substrate by a chip-attached layer and electrically connected to... Agent: Troxell Law Office LLP

20080093749 - Partial solder mask defined pad design: A solder ball pad that includes a substrate and a bonding pad attached to the substrate. The bonding pad has a bonding pad surface and a bonding pad edge. The solder ball pad also includes a solder mask attached to the substrate in which the solder mask at least partially... Agent: Texas Instruments Incorporated

20080087875 - Protection for the epitaxial structure of metal devices: Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased... Agent: Patterson & Sheridan, L.L.P.

20080087886 - Array substrate for liquid crystal display device and method of fabricating the same: An array substrate for a liquid crystal display device includes a data line formed on a substrate including a pixel region; a source electrode extending from the data line; a drain electrode separated from the source electrode; a pixel electrode contacting the drain electrode and formed of a transparent conductive... Agent: Brinks Hofer Gilson & Lione

20080087889 - Method of fabricating an organic electroluminescent device and system of displaying images: A method for fabricating organic electroluminescent devices is disclosed. The method comprises providing a substrate divided into first and second regions, forming an amorphous silicon layer on the substrate, forming a protection film on the amorphous silicon layer within the second region, performing an excimer laser annealing process on the... Agent: Liu & Liu

20080087888 - Semiconductor device and method for manufacturing semiconductor: A method for easily forming a region with conductivity and high wettability without a step for removing a photocatalytic reaction layer, which is formed over a conductive layer, is proposed. The photocatalytic reaction layer is formed over a photocatalytic conductive layer, and the photocatalytic conductive layer is irradiated with ultraviolet... Agent: Eric Robinson

20080087879 - Tetrasubstituted coronenes: Tetrasubstituted coronenes are provided. Also provided are electronic devices in which the active layer includes a tetrasubstituted coronene.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20080087878 - Use of perylene diimide derivatives as air-stable n-channel organic semiconductors: The present invention relates to the use of of perylene diimide derivatives as air-stable n-type organic semiconductors.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080087890 - Methods to form dielectric structures in semiconductor devices and resulting devices: Methods of forming dielectric structures with a high dielectric constant (high “k”) may be used to fabricate gate dielectrics in integrated circuits and in other devices such as spintronic devices. A dielectric structure may be formed by atomic layer deposition of separate layers of zirconium oxide, hafnium oxide, and titanium... Agent: Schwegman, Lundberg & Woessner, P.A.

20080087893 - Lcd tft array plate and fabricating method thereof: Lift-off method and half-tone photolithography are used to fabricate LCD TFT array plate. Only two photo masks are used to respectively define a first and a second metal layers to accomplish the LCD TFT array plate.... Agent: Rabin & Berdo, PC

20080087895 - Polysilicon thin film transistor and method of fabricating the same: A method of fabricating a polycrystalline silicon thin film transistor is disclosed. One embodiment of the method includes: forming an amorphous silicon layer on a panel; scanning a continuous wave laser beam having a wavelength range of about 600 to about 900 nm between a visible light range of a... Agent: Knobbe Martens Olson & Bear LLP

20080087897 - Compound semiconductor element resistible to high voltage: A compound semiconductor element is provided which electrically connects an electrode 3 formed on one main surface 2a of a compound semiconductor region 2 with a substrate 5 to fix an electric potential of substrate 5 at an electric potential of electrode 3, thereby preventing fluctuation in electric potential of... Agent: Bachman & Lapointe, P.C.

20080087901 - Optical coupling type semiconductor device, method for producing optical coupling type semiconductor device, and electronic device: In an embodiment of an optical coupling type semiconductor device according to the present invention, in an optical coupling type semiconductor device that is provided with lead frames on which a light emitting element and a light receiving element have been respectively separately mounted and a resin sealing member that... Agent: Birch Stewart Kolasch & Birch

20080087904 - Thin film transistor panel and manufacturing method thereof: A thin film transistor array panel includes interconnection members interposed between the underlying gate pads made of an Al-containing metal and the overlying contact assistants made of a transparent conductor such as ITO thereon to prevent corrosion of Al due to ITO, or gate-layer signal transmission lines. Gate-layer signal transmission... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080087907 - Light emitting diode package: A light emitting diode package including: a package substrate having a mounting area and first and second wiring structures partially exposed in the mounting area; a light emitting diode having first and second electrodes, the light emitting diode mounted on the mounting area of the package substrate to allow the... Agent: Mcdermott Will & Emery LLP

20080087876 - Method for fabricating lateral semiconductor device: A lateral junction semiconductor device and method for fabricating the same comprising the steps of taking a semiconductor structure having a stack formed by a plurality of layers of semiconductor material arranged in a series of substantially parallel planes, the semiconductor material within a first layer having an excess of... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080087877 - Nitride semiconductor light emitting device and fabrication method thereof: A nitride semiconductor light emitting device includes a first nitride semiconductor layer, a first Al-doped nitride semiconductor buffer layer formed on the first nitride semiconductor layer, an activation layer formed on the first Al-doped nitride semiconductor buffer layer, and a second nitride semiconductor layer formed on the activation layer. Another... Agent: Birch Stewart Kolasch & Birch

20080087887 - Compound for molecular electronic device: n

20080087880 - Electronic device and manufacturing method thereof: An object of the invention is to provide an electronic device which can be easily manufactured using a wet method. One of electronic devices according to the invention has a first layer and a second layer. The first layer contains a first compound including a conjugated double bond. Here, the... Agent: Nixon Peabody, LLP

20080087885 - Organic field-effect transistor and method of making same based on polymerizable self-assembled monolayers: An organic field-effect transistor and a method of making the same include a self-assembled monolayer (SAM) of bifunctional molecules disposed between a pair of electrodes as a channel material. The pair of electrodes and the SAM of bifunctional molecules are formed above an insulating layer, in which each of the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080087884 - Organic semiconductor material and organic thin-film transistor: wherein A1 and C1 each represent an unsubstituted or substituted thiazole ring, and B1 represents an unsubstituted or substituted benzene ring or an unsubstituted or substituted polycondensed aromatic ring. Accordingly, there are provided an organic semiconductor material having high ON current and excellent storage stability and an organic thin-film transistor... Agent: Fitzpatrick Cella Harper & Scinto

20080087883 - Organic transistor using self-assembled monolayer: Disclosed are a method for inexpensively reducing the contact resistance between an electrode and an organic semiconductor upon a p-type operation of the organic semiconductor; and a method for inexpensively operating, as an n-type semiconductor, an organic semiconductor that is likely to work as a p-type semiconductor. In addition, also... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080087882 - Process for making contained layers and devices made with same: There is provided a process for forming a contained second layer over a first layer, including the steps: forming the first layer having a first surface energy; forming an intermediate layer over and in direct contact with the first layer, said intermediate layer having a second surface energy which is... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20080087881 - Semiconductor multilayer substrate, method for producing same and light-emitting device: The present invention provides a semiconductor multilayer substrate used as a high-brightness semiconductor light-emitting device, a method for producing the same, and a light-emitting device. The semiconductor multilayer substrate comprises a semiconductor layer containing an inorganic particle made of substance other than metal nitrides. The method for producing a semiconductor... Agent: Fitch, Even, Tabin & Flannery

20080087891 - Semiconductor-on-diamond devices and methods of forming: The present invention provides semiconductor-on-diamond devices, and methods for the formation thereof. In one aspect, a mold is provided which has an interface surface configured to inversely match a configuration intended for the device surface of a diamond layer. An adynamic diamond layer is then deposited upon the diamond interface... Agent: Thorpe North & Western, LLP.

20080087892 - High performance transistor with a highly stressed channel: A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate wherein the first semiconductor plate has a substantially greater lattice... Agent: Steven H. Slater Slater & Matsil, L.L.P.

20080087894 - Semiconductor thin film and semiconductor device: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor... Agent: Eric Robinson

20080087896 - Trench schottky barrier diode with differential oxide thickness: A fabrication process for a trench Schottky diode with differential oxide thickness within the trenches includes forming a first nitride layer on a substrate surface and subsequently forming a plurality of trenches in the substrate including, possibly, a termination trench. Following a sacrificial oxide layer formation and removal, sidewall and... Agent: Ostrolenk Faber Gerb & Soffen

20080087898 - High-heat-resistant semiconductor device: In a wide gap semiconductor device of SiC or the like used at a temperature of 150 degrees centigrade or higher, the insulation characteristic of a wide gap semiconductor element is improved and a high-voltage resistance is achieved. For these purposes, a synthetic high-molecular compound, with which the outer surface... Agent: Crowell & Moring LLP Intellectual Property Group

20080087899 - Optically-regulated optical emission using colloidal quantum dot nanocrystals: The present invention relates to the emission of light which occurs in proportion with an electrical signal, an optical signal, or the combination of both. The emission of light may occur due to the passage of current through a light-emitting polymer, or due to energy transfer of excitons from this... Agent: Courtney Staniford & Gregory LLP

20080087900 - Integrated-type led and manufacturing method thereof: The present invention provides an integrated-type LED and method for manufacturing the same. This integrated-type LED comprises a base board which having a preplaced circuit and at least one LED chip. P electrode and N electrode of the LED chip are respectively connected, conducting and fixing on the base board;... Agent: Charles E. Baxley, Esq.

20080087902 - Light emitting device having a plurality of light emitting cells and package mounting the same: Disclosed is a light emitting device having a plurality of light emitting cells and a package having the same mounted thereon. The light emitting device includes a plurality of light emitting cells which are formed on a substrate and each of which has an N-type semiconductor layer and a P-type... Agent: Marger Johnson & Mccollom, P.C.

20080087903 - Method for producing a light emitting diode arrangement, and light emitting diode arrangement: A method for producing a light emitting diode arrangement. A plurality of LED modules (110, 120, 130) are provided, which in each case comprise at least one radiation emitting semiconductor component (1000) on a carrier body (1300). At least one separately fabricated connection carrier (200) is provided. The LED modules... Agent: Cohen Pontani Lieberman & Pavane LLP Thomas Langer

20080087905 - Nitride compound semiconductor light emitting device and method for producing the same: A nitride compound semiconductor light emitting device includes: a GaN substrate having a crystal orientation which is tilted away from a <0001> direction by an angle which is equal to or greater than about 0.05° and which is equal to or less than about 2°, and a semiconductor multilayer structure... Agent: Morrison & Foerster LLP

20080087906 - Algaas-based light emitting diode having double hetero junction and manufacturing method of the same: A high-speed response AlGaAs light emitting diode which has an emission peak wavelength of 880 nm or more and is provided with double hetero junction. The LED is provided with at least three layers of a P-type clad layer composed of a P-type AlGaAs compound, a P-type light emitting layer... Agent: Oliff & Berridge, PLC

20080087908 - Optical element and optoelectronic component comprising such an optical element: An optical element (1) is specified comprising an optical body (2) containing a plastic material. The optical body (2) is completely encapsulated by a protective layer (3) containing a silicon oxide. An optoelectronic component comprising such an optical element is furthermore described.... Agent: Cohen Pontani Lieberman & Pavane LLP Thomas Langer

20080087910 - Reflector packages and semiconductor light emitting devices including the same: Reflectors for a semiconductor light emitting device include a lower sidewall portion defining a reflective cavity. A substantially horizontal shoulder portion extends outwardly from the sloped lower sidewall portion. The horizontal shoulder portion has a circumferentially extending moat formed therein. An upper sidewall portion extends upwardly from the horizontal shoulder... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080087909 - Single or multi-color high efficiency light emitting diode (led) by growth over a patterned substrate: A single or multi-color light emitting diode (LED) with high extraction efficiency is comprised of a substrate, a buffer layer formed on the substrate, one or more patterned layers deposited on top of the buffer layer, and one or more active layers formed on or between the patterned layers, for... Agent: Gates & Cooper LLP Howard Hughes Center

20080087911 - Light emitting diode system, method for producing such a system, and backlighting device: A light-emitting diode system (1) comprising at least one light-emitting diode component (2), in which a light-emitting diode chip is arranged in a light-emitting diode housing (21) on a heat sink (22) which can be thermally connected at the rear side (25) of the light-emitting diode housing (21). A carrier... Agent: Cohen Pontani Lieberman & Pavane LLP

20080087912 - Semiconductor device and method for fabricating the same: A resurf region of a second conductivity type and a base region of a first conductivity type adjacent to each other are formed in surface portions of a semiconductor substrate of the first conductivity type. An emitter region of the second conductivity type is formed in the base region to... Agent: Mcdermott Will & Emery LLP

20080087913 - Semiconductor device and method for producing the same: A semiconductor device includes a vertical transistor and an external contact plane. The transistor includes: a first side with a first load electrode and a control electrode, and an opposite second side with a second load electrode. The first side of the transistor faces the external contact plane. A dielectric... Agent: Edell , Shapiro & Finnan , LLC

20080087914 - Extreme ultraviolet (euv) detectors based upon aluminum nitride (aln) wide bandgap semiconductors: Disclosed are detector devices and related methods. In an Al EUV detector a low temperature AlN layer is deposed above an AlN buffer layer. In one embodiment, the low temperature AlN layer is deposed at about 800° C. Pulsed NH3 is used when growing an AlN epilayer above the low... Agent: Lathrop & Gage Lc

20080087915 - Nitride semiconductor device and method for fabricating the same: A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of... Agent: Mcdermott Will & Emery LLP

20080087916 - Field-effect transistor and method of manufacturing the same: A low-cost field-effect transistor with a moisture-resistant gate covered by a thick moisture-resistant insulating film which suppresses an increase in gate capacitance, and a method of manufacturing the field-effect transistor. The field-effect transistor, has one of a T-shaped gate electrode and Γ-shaped gate electrode, a drain electrode, and a source... Agent: Leydig Voit & Mayer, Ltd

20080087917 - Iii-nitride power semiconductor device having a programmable gate: A III-nitride semiconductor device which includes a charged floating gate electrode.... Agent: Ostrolenk Faber Gerb & Soffen

20080087918 - Symmetric bipolar junction transistor design for deep sub-micron fabrication processes: Described herein are embodiments of a bipolar junction transistor including a plurality of base terminal rings having an emitter terminal ring between any two base terminal rings of the plurality of base terminal rings, and a collector terminal ring surrounding the plurality of base terminal rings and the emitter terminal... Agent: Michael A. Bernadicou Blakely, Sokoloff, Taylor & Zafman LLP

20080087919 - Method for forming nitride crystals: A method for growing a nitride crystal and a crystalline composition selected from one of AlN, InGaN, AlGaInN, InGaN, and AlGaNInN is provided. The composition comprises a true single crystal, grown from a single nucleus, at least 1 mm in diameter, free of lateral strain and tilt boundaries, with a... Agent: Dilworth & Barrese, LLP

20080087920 - Semiconductor integrated circuit with leakage current suppressed: In a semiconductor integrated circuit, a cell arrangement area is provided on a semiconductor substrate to allow a plurality of basis cells to be arranged. A basic power supply line is provided in an upper layer than the cell arrangement area to supply a power. A switch cell is configured... Agent: Mcginn Intellectual Property Law Group, PLLC

20080087921 - Image sensor device suitable for use with logic-embedded cis chips and methods for making the same: An image sensor device is provided. A substrate has a photosensor region formed therein and/or thereon. An interconnection structure is formed over the substrate, and includes metal lines formed in inter-metal dielectric (IMD) layers. At least one IMD-level micro-lens is/are formed in at least one of the IMD layers over... Agent: Slater & Matsil, L.L.P.

20080087922 - Image sensor with improved color crosstalk: An image sensor comprises a substrate of a first conductivity type. First and second pixels are arrayed over the substrate. A potential barrier is formed in a region of the substrate corresponding to the first pixel but not in a region of the substrate corresponding to the second pixel. The... Agent: Morgan Lewis & Bockius LLP

20080087923 - Semiconductor device and manufacturing method thereof: A semiconductor device and manufacturing method thereof capable of improving an operating speed of a MOSFET using an inexpensive structure. The method comprises the steps of forming a stress film to cover a source, drain, sidewall insulating layer and gate of the MOSFET and forming in the stress film a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080087924 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and a method for manufacturing the same. In one example embodiment, a CMOS image sensor includes a field region and an active region, a second conductive bottom region, a first conductive well region, a second conductive top region, and a first conductive high concentration region. The... Agent: Workman Nydegger

20080087925 - Solid-state imaging device and method for driving the same: During an exposure time period (long accumulation time period) of a low shutter speed shooting mode, a second reference voltage Vss2, which is different from a first reference voltage Vss1 (a ground voltage) corresponding to a reference voltage of a peripheral circuit, is applied to a well (5) where a... Agent: Mcdermott Will & Emery LLP

20080087926 - Ferroelectric random access memory and methods of fabricating the same: A method of forming a ferroelectric random access memory includes sequentially forming a conductive pattern, an etch-stop layer, a ferroelectric capacitor and an interlayer dielectric on a semiconductor substrate, which includes a first region and a second region. The ferroelectric capacitor is formed on the first region and the conductive... Agent: Volentine & Whitt PLLC

20080087928 - Semiconductor device: The semiconductor device according to the present invention comprises a plurality of actually operative capacitors 36a formed, arranged in an actually operative capacitor part 26 over a semiconductor substrate 10 and each including a lower electrode 30, a ferroelectric film 32 and an upper electrode 34; a plurality of dummy... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080087927 - Semiconductor memory device with dual storage node and fabricating and operating methods thereof: A semiconductor memory device with a dual storage node structure as well as methods of fabricating and operating such a device are provided. The semiconductor memory device includes a substrate, a first transistor formed on the substrate, a first storage node connected to a source region of the first transistor,... Agent: Harness, Dickey & Pierce, P.L.C

20080087929 - Static random access memory with thin oxide capacitor: An SRAM includes an SRAM cell with a semiconductor substrate material, and a capacitor. The capacitor includes a first electrode adjacent the substrate material, a thin oxide adjacent the first electrode and a second electrode adjacent the thin oxide.... Agent: Davidson, Davidson & Kappel, LLC

20080087930 - Capicitor using binary metal electrode, semiconductor device having the capacitor and method of fabricating the same: A capacitor includes a first electrode having a conductive pattern and an anti-oxidation pattern contacting the conductive pattern and a second electrode overlapping the first electrode. The capacitor further includes a capacitor dielectric layer disposed between the first and second electrodes, and having a blanket dielectric layer and a partial... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080087931 - Method of fabricating semiconductor device having capacitor: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating... Agent: F. Chau & Associates, LLC

20080087932 - Nand flash memory devices having 3-dimensionally arranged memory cells and methods of fabricating the same: A NAND flash memory device includes a lower semiconductor layer and an upper semiconductor layer located over the lower semiconductor layer, a first drain region and a first source region located in the lower semiconductor layer, and a second drain region and a second source region located in the upper... Agent: Volentine & Whitt PLLC

20080087933 - Semiconductor memory device and method of manufacturing the same: Example embodiments relate to a semiconductor memory device including a channel layer pattern on a substrate, the channel layer pattern having a sidewall and an upper face, a spacer on the sidewall of the channel layer pattern, and a gate electrode covering the sidewall of the channel layer pattern, the... Agent: Lee & Morse, P.C.

20080087934 - Nonvolatile memory device, method of fabricating and method of operating the same: A nonvolatile memory device may include a semiconductor substrate; first and second floating gate electrodes formed on the semiconductor substrate; a control gate electrode formed on the first and second floating gate electrodes that may include a line body and a first leg, second leg, and third leg extending vertically... Agent: Harness, Dickey & Pierce, P.L.C

20080087936 - Nonvolatile semiconductor memory device to realize multi-bit cell and method for manufacturing the same: A nonvolatile semiconductor memory device that realizes a multi-bit cell and a method for manufacturing the same includes manufacturing the nonvolatile semiconductor memory device to be capable of storing multi-bit data, for example, 4-bit data, in a single memory cell and, as a result, the integration degree of a NOR... Agent: Sherr & Nourse, PLLC

20080087938 - Mask rom, mask rom embedded eeprom and method of fabricating the same: Example embodiments are directed to a mask ROM, a mask ROM embedded EEPROM and a method of fabricating the same. The mask ROM may include a select gate pattern and a memory gate pattern disposed between a source region and a drain region at each of the on-cell and the... Agent: Harness, Dickey & Pierce, P.L.C

20080087937 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a first insulating film provided on a surface of a semiconductor substrate, a charge accumulation layer provided on the first insulating film, a second insulating film provided above the charge accumulation layer and contains silicon and nitrogen, a third insulating film provided on the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080087935 - Semiconductor device and method of fabricating the same: A semiconductor device includes an element isolation region formed in the surface of a semiconductor substrate, a plurality of memory cell transistors having respective gate electrodes formed in an element forming region and a selective gate transistor located at an end of a row of a predetermined number of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080087939 - Nonvolatile semiconductor memory and manufacturing method for the same: A nonvolatile semiconductor memory device comprising: a gate electrode portion comprising: a floating gate electrode formed above a main surface of a semiconductor substrate of a first conductivity type, separated from the substrate by a tunnel insulating film; an inter-electrode insulating film formed on the floating gate electrode and formed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080087940 - Nonvolatile memory device and method of fabricating the same: A nonvolatile memory device, includes a semiconductor substrate having a bottom part, a second vertical part positioned vertically on the bottom part, and a first vertical part having a width smaller than a width of the second vertical part and positioned on the second vertical part to have a boundary... Agent: Lee & Morse, P.C.

20080087941 - Nonvolatile memory devices having stacked structures and methods of fabricating the same: A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A... Agent: Myers Bigel Sibley & Sajovec

20080087942 - Vertical channel memory and manufacturing method thereof and operating method using the same: A vertical channel memory including a substrate, a channel, a multi-layer structure, a gate, a first terminal and a second terminal is provided. The channel is protruded from the substrate and has a top surface and two vertical surfaces. The multi-layer structure is disposed on the two vertical surfaces of... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080087944 - Charge trap memory device: A charge trap memory device may include a tunnel insulating layer formed on a substrate. A charge trap layer may be formed on the tunnel insulating layer, wherein the charge trap layer is a higher-k dielectric insulating layer doped with one or more transition metals. The tunneling insulating layer may... Agent: Harness, Dickey & Pierce, P.L.C

20080087943 - Nonvolatile semiconductor memory device and method of fabricating the same: A nonvolatile semiconductor memory device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, a source/drain region formed at each side of the gate electrode in the substrate, a first silicon oxide film formed on a gate electrode sidewall so... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080087945 - Silicon lanthanide oxynitride films: Electronic apparatus and methods of forming the electronic apparatus include a silicon lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The silicon lanthanide oxynitride film may be arranged as a layered structure having one or more monolayers. Metal electrodes may be disposed on a... Agent: Schwegman, Lundberg & Woessner, P.A.

20080087946 - Vertical channel transistor structure and manufacturing method thereof: A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is protruded from the substrate. The cap layer is deposited on the channel. The cap layer and the channel substantially have the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080087947 - Cathode cell design: An n-channel insulated gate semiconductor device with an active cell (5) comprising a p channel well region (6) surrounded by an n type third layer (8), the device further comprising additional well regions (11) formed adjacent to the channel well region (6) outside the active semiconductor cell (5) has enhanced... Agent: Buchanan, Ingersoll & Rooney PC

20080087948 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a semiconductor substrate including an active region and a gate region, and a gate channel formed in a portion of the active region that overlaps the gate region. The gate channel includes a recessed multi-bulb structure.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080087949 - Semiconductor device and method of manufacturing the same: A p-type epitaxial layer is formed on an n+-type substrate and then a buried n-type region is formed at a boundary between the n+-type substrate and the p-type epitaxial layer by ion implantation. Subsequently, a trench is formed so as to reach the n+-type substrate, passing through the p-type epitaxial... Agent: Sughrue Mion, PLLC

20080087950 - Semiconductor device manufacturing method: Before forming a gate trench, a buried oxide film forming an element isolation region is selectively etched, thereby exposing a side-wall shoulder portion, having a rounded shape, of an active region. This reduces a range in which an end portion of the buried oxide film serves as a mask when... Agent: Mcginn Intellectual Property Law Group, PLLC

20080087953 - Power metal oxide silicon field effect transistor: A power metal oxide silicon field effect transistor in which sources are connected to each other, a single source supplies electrons to two channels, a contact surface between the source and a channel is variously changed to be maximized such that large current flows in a small area, and an... Agent: Sherr & Nourse, PLLC

20080087951 - Insulated gate semiconductor device and method for producing the same: The invention has an object to provide an insulation gate type semiconductor device and a method for producing the same in which high breakdown voltage and compactness are achieved. The semiconductor device has a gate trench and a P floating region formed in the cell area and has a terminal... Agent: Kenyon & Kenyon LLP

20080087952 - Semiconductor component having a transition region: A semiconductor component is disclosed. One embodiment provides a semiconductor component including a semiconductor body having a cell array region with trenches and an edge region with pn junction. A transition region with at least one trench is formed between the cell array region and the edge region.... Agent: Dicke, Billig & Czaja

20080087954 - Semiconductor device having nitridated oxide layer and method therefor: A semiconductor device includes a substrate (12), a first insulating layer (14) over a surface of the substrate (12), a layer of nanocrystals (13) over a surface of the first insulating layer (14), a second insulating layer (15) over the layer of nanocrystals (13). A nitriding ambient is applied to... Agent: Freescale Semiconductor, Inc. Law Department

20080087955 - Suction-mountable display device: A deformable device mountable by suction on a smooth mounting surface. The device includes a body having an outer surface, a non-circular periphery extending around the body, surrounding the outer surface of the body and an inner surface opposite the outer surface having a concave portion. The device also includes... Agent: Alston & Bird LLP

20080087956 - Devices, methods, and systems with mos-gated trench-to-trench lateral current flow: A DMOS transistor is fabricated with its source/body/deep body regions formed on the walls of a first set of trenches, and its drain regions formed on the walls of a different set of trenches. A gate region that is formed in a yet another set of trenches can be biased... Agent: Groover & Associates

20080087957 - Semiconductor device and method for fabricating semiconductor device: According to an aspect of the present invention, there is provided a semiconductor device including a first conductive type semiconductor substrate, a gate electrode formed over the semiconductor substrate via a gate insulator, a first conductive impurity region buried in the semiconductor substrate, the first conductive impurity region being both... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20080087958 - Semiconductor device with doped transistor: A semiconductor device provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the... Agent: Law Offices Of Mikio Ishimaru

20080087960 - Low temperature process for tft fabrication: Method of fabricating a thin-film transistor (TFT) in which a gate metal is deposited onto a substrate in order to form the gate of the thin-film transistor. The substrate may be an insulative substrate or a color filter. In a first method, the gate metal is subjected to an H2... Agent: Robert J. Stern

20080087959 - Manufacturing method of semiconductor-on-insulator region structures: A single-crystal silicon region on insulator on silicon intended to receive at least one component, the insulator having overthicknesses.... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20080087961 - Method of reducing stacking faults through annealing: Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation.... Agent: International Business Machines Corporation Dept. 18g

20080087962 - Electrostatic discharge protection devices and methods for protecting semiconductor devices against electrostatic discharge events: Methods and devices are provided for protecting semiconductor devices against electrostatic discharge events. An electrostatic discharge protection device comprises a silicon substrate, a P+-type anode region disposed within the silicon substrate, and an N-well device region disposed within the silicon substrate in series with the P+-type anode region. A first... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080087963 - Tapered voltage polysilicon diode electrostatic discharge circuit for power mosfets and ics: An electrostatic discharge (ESD) protection network for power MOSFETs includes parallel branches, containing polysilicon zener diodes and resistors, used for protecting the gate from rupture caused by high voltages caused by ESD. The branches may have the same or independent paths for voltage to travel across from the gate region... Agent: Hiscock & Barclay, LLP

20080087964 - Semiconductor device with a gate region having overlapping first conduction type and second conduction type dopants: A method to impede the constitution of the area wherein the silicide film that is defying to form on a gate electrode. Form an element isolation film, and then a gate dielectric film in a P-channel and an N-channel transistor forming region respectively. Then form a semiconductor film that constructs... Agent: Harness, Dickey & Pierce, P.L.C

20080087965 - Structure and method of forming transistor density based stress layers in cmos devices: A method for increasing carrier mobility of transistors included in an semiconductor device includes forming a stress inducing layer over a plurality of transistors, the transistors formed in regions of varying transistor density, wherein the stress inducing layer is formed at a varying thickness depending on the transistor density, such... Agent: Cantor Colburn LLP - IBM Fishkill

20080087966 - Semiconductor device and method for manufacturing same: Disclosed herein is a semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the device having: a first insulating layer and a second insulating layer; and gate electrode contact plugs. Each of the gate electrodes of the N-channel insulated gate field... Agent: Sonnenschein Nath & Rosenthal LLP

20080087967 - Semiconductor device having reduced-damage active region and method of manufacturing the same: A semiconductor device according to example embodiments may include a substrate having an NMOS area and a PMOS area, isolation regions and well regions formed in the substrate, gate patterns formed on the substrate between the isolation regions, source/drain regions formed in the substrate between the gate patterns and the... Agent: Harness, Dickey & Pierce, P.L.C

20080087968 - Fin-type field effect transistor: Disclosed herein are improved fin-type field effect transistor (FinFET) structures and the associated methods of manufacturing the structures. In one embodiment FinFET drive current is optimized by configuring the FinFET asymmetrically to decrease fin resistance between the gate and the source region and to decrease capacitance between the gate and... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080087969 - Planar-type semiconductor device and method of manufacturing the same: A planar-type semiconductor device including a plurality of device isolation areas defining an active area formed over a semiconductor substrate; at least one drift area formed in the semiconductor substrate; a well region formed in the semiconductor substrate; a gate pattern formed over the semiconductor substrate and between the plurality... Agent: Sherr & Nourse, PLLC

20080087970 - Wet chemical treatment to form a thin oxide for high k gate dielectrics: Described herein are methods of forming a thin silicon dioxide layer having a thickness of less than eight angstroms on a semiconductor substrate to form the bottom layer of a gate dielectric. A silicon dioxide layer having a thickness of less than eight angstroms may be formed by two different... Agent: Blakely Sokoloff Taylor & Zafman

20080087971 - Method for manufacturing capacitive sensor, and capacitive sensor: In the method for manufacturing a capacitance sensor according to the present invention, after a protection layer is pattern-formed on the surface of a silicon substrate, a first metal layer is formed on the surface of a silicon substrate so as to be opposed to a protection layer non-formed area... Agent: Rabin & Berdo, PC

20080087972 - Copper doped magnetic semiconductors: A semi-conducting material, a method for producing the material, and ways of implementing the material, wherein said material is doped with Cu or CuO, and is ferromagnetic at least at one temperature in the range between −55° C. and 125° C. Typically the material may comprise GaP or GaN.... Agent: Ladas & Parry LLP

20080087973 - Three-dimensional resonant cells with tilt up fabrication: A composite material for providing at least one of a negative effective permeability and a negative effective permittivity for incident radiation of at least one wavelength is described. The composite material comprises a plurality of three-dimensional resonant cells disposed across a first substrate. Each three-dimensional resonant cell comprises a base... Agent: Hewlett Packard Company

20080087974 - Camera module and method of fabricating the same: Provided are a camera module and a method of fabricating the same. The method includes preparing a lens structure including upper connection portions. Lower connection portions are formed in a predetermined region of a substrate. The lower connection portions define a chip region and fit in the upper connection portions,... Agent: Marger Johnson & Mccollom, P.C.

20080087975 - Chip package and chip packaging method: A chip package and a chip packaging method for use in optical applications are disclosed. The packaging method includes the steps of: a) providing a substrate having a first surface and a second surface; b) bonding first passive devices on the first surface; c) adhering a first chip to the... Agent: Bacon & Thomas, PLLC

20080087976 - Solid-state imaging device and method for fabricating the same: A method for fabricating a solid-state imaging device comprises: a step of forming a photodiode protection insulation film 6a; a step of forming a dummy protection insulation film 6c corresponding to the photodiode protection insulation film 6a both in the peripheral circuit region 1b and the scribe lane region 1c;... Agent: Mcdermott Will & Emery LLP

20080087977 - Solid-state imaging device and method of manufacturing the same: The present invention provides a solid-state imaging device having an element isolation layer that is formed by embedding a conductive material into a trench-processed groove portion provided in a semiconductor base, in which a predetermined voltage is applied to the element isolation layer.... Agent: Sonnenschein Nath & Rosenthal LLP

20080087978 - Semiconductor structure and method of manufacture: A structure and method comprises a deep sub-collector located in a first epitaxial layer and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The device further comprises a reach-through structure penetrating from a surface of the device through the first and second... Agent: Greenblum & Bernstein, P.L.C

20080087979 - Integrated circuit with back side conductive paths: An integrated circuit has a substrate with a back side and a front side. The front side has both a working area and a front side contact in electrical communication with the working area. In a similar manner, the back side has first and second back side contacts. A first... Agent: Bromberg & Sunstein LLP

20080087980 - Semiconductor device and method for fabricating a semiconductor device: A semiconductor structure has an active region on a substrate, and recessed portions are formed at lower edges of lateral portions of the semiconductor structure. Patterned first insulation layers for device isolation are buried into the recessed portions. Second insulation layers for device isolation are formed on sidewalls of the... Agent: Blakely Sokoloff Taylor & Zafman

20080087981 - Semiconductor device and method of fabricating the same: A semiconductor device includes a semiconductor substrate formed with at least two element isolation trenches having a first opening width and a second opening width larger than the first opening width, respectively, a non-coating type silicon oxide film formed along an inner surface of each element isolation trench so as... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080087982 - Semiconductor device and manufacturing method thereof: An object is to provide technology for manufacturing a higher-reliability memory device and a semiconductor device that is equipped with the memory device at low cost. A semiconductor device of the present invention has a first conductive layer, a first insulating layer that is provided to be in contact with... Agent: Eric Robinson

20080087983 - Bipolar transistor having variable value emitter ballast resistors: Methods of forming and structures of a relatively large bipolar transistor is provided. The method includes forming a collector in a semiconductor region. Forming a base contiguous with a portion of the collector. Forming a plurality of emitters contiguous with portions of the base. Forming a common emitter interconnect and... Agent: Fogg & Powers LLC

20080087984 - Compound semiconductor modified surface by use of pulsed electron beam and ion implantation through a deposited metal layer: Thermally sensitive at elevated, near melting point temperature, compound semiconductor materials single crystals including Group III-Nitride, other Group III-V, Group II-VI and Group IV-IV are produced by a variety of methods. When produced as single crystal layers by epitaxy methods or is necessary to expose them to elevated temperatures or... Agent: Andreas A. Melas

20080087985 - Forming high-k dielectric layers on smooth substrates: A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.... Agent: Trop Pruner & Hu, PC

20080087986 - Materials, structures and methods for microelectronic packaging: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition... Agent: Intel/blakely

20080087987 - Semiconductor packaging structure having electromagnetic shielding function and method for manufacturing the same: A semiconductor packaging structure having electromagnetic shielding function is disclosed, in which the packaging structure includes a carrier and a semiconductor substrate disposed thereon. The semiconductor substrate has a patterned passivation layer and a patterned metal layer disposed thereon, in which the patterned metal layer is electrically connected to at... Agent: North America Intellectual Property Corporation

20080087989 - Semiconductor device package of stacked semiconductor chips with spacers provided therein: A semiconductor device package includes a plurality of stacked semiconductor chips and a spacer interposed therebetween. The spacer includes a first spacer and a second spacer stacked on one another. The first and the second spacers have different principal surfaces. If the second spacer has a larger principal surface than... Agent: Sughrue Mion, PLLC

20080087988 - Semiconductor package preventing generation of static electricity therein: A semiconductor package includes a chip including a conductive pattern thereon, a conductive network attached on a surface of the chip to absorb static electricity, at least one conductive rod attached to the conductive network, wherein the at least one conductive rod is formed substantially perpendicularly to the conductive network,... Agent: F. Chau & Associates, LLC

20080087990 - Semiconductor device: A semiconductor device that can prevent reduction in the amplitude of electromagnetic waves transmitted from a reader/writer, and can prevent heating of an element forming layer due to a change in a magnetic field. The semiconductor device of the invention has an element forming layer formed over a substrate, and... Agent: Eric Robinson

20080087991 - Vertical light source package: A vertical light source package uses leadframes with leads that extend in the same predefined direction. The leadframes are at least partially positioned in a structural body of the vertical light source package. The vertical light source package includes a light emitting device, such as a vertical-cavity surface-emitting laser, that... Agent: Kathy Manke Avago Technologies Limited

20080087992 - Semiconductor package having a bridged plate interconnection: A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, and a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source contacts. A bridged source plate interconnection has a bridge portion, valley portions disposed on either side of... Agent: Fortune Law Group LLP

20080087993 - Semiconductor device and method of manufacturing the same: A semiconductor device in accordance with the present invention includes IC chips (semiconductor elements) (2, 3, 4) having solder bumps (24) (projecting electrodes) formed on electrode pads, and a first wiring board (1) having connection terminals (7) to which the respective solder bumps (24) of the IC chips (2, 3,... Agent: Steptoe & Johnson LLP

20080087994 - Semiconductor apparatus: A semiconductor apparatus equipped with at least one semiconductor element includes a metallic plate bonded to an upper surface of the semiconductor element and a conductor plate, bonded to the metallic plate and serving as an electric current path of the semiconductor apparatus. The conductor plate and the metallic plate... Agent: Kanesaka Berner And Partners LLP

20080087995 - Flexible film semiconductor package and method for manufacturing the same: Provided are a semiconductor package and a manufacturing method thereof. The semiconductor package includes a flexible film with a film wire region formed of a film substrate region on which a semiconductor chip is mounted, and a plurality of sub film wires branching and extending from the film substrate region... Agent: Marger Johnson & Mccollom, P.C.

20080087996 - Semiconductor device and manufacturing method of the same: An object of the invention is to improve a reliability of a semiconductor device. The semiconductor device comprises a semiconductor chip, a tab having an outside dimension smaller than that of the semiconductor chip, a plurality of wires, a plurality of inner leads which extend around the semiconductor chip and... Agent: Miles & Stockbridge PC

20080087997 - Semiconductor package substrate and method, in particular for mems devices: A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of... Agent: Graybeal, Jackson, Haley LLP

20080087998 - Interconnection between different circuit types: A hybrid-scale electronic circuit, an internal electrical connection and a method of electrically interconnecting employ an interconnect having a tapered shape to electrically connect between different-scale circuits. The interconnect has a first end with an end dimension that is larger than an end dimension of an opposite, second end of... Agent: Hewlett Packard Company

20080087999 - Micro bga package having multi-chip stack: A micro BGA package comprises a first chip, a second chip, a single-layer PCB, a plurality of bonding wires, an encapsulant and a plurality of solder balls. The second chip is smaller than the first chip in size and stacked on the active surface of the first surface by facing... Agent: Troxell Law Office PLLC

20080088002 - Chip package structure: A chip package structure includes a substrate having a cavity, wherein the substrate includes a plurality of first contacts and second contacts disposed on a surface thereof, and the first contacts are located within the cavity and the second contacts are located outside the cavity. The substrate further includes a... Agent: J C Patents, Inc.

20080088001 - Package on package and method thereof: A package on package (POP) and method thereof are provided. The example POP may include a first semiconductor package including a first substrate, the first substrate being a flexible substrate having at least one folded portion, a first semiconductor chip mounted on and electrically connected to the first substrate and... Agent: Harness, Dickey & Pierce, P.L.C

20080088000 - Semiconductor integrated circuit device having reduced terminals and i/o area: In a semiconductor integrated circuit device including a semiconductor integrated circuit board having a mask ROM area and an internal bus and a programmable ROM which is mounted on the semiconductor integrated circuit board and which has a plurality of ROM connecting terminals, the ROM connecting terminals are electrically connected... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080088003 - Stacked modules and method: The present invention stacks integrated circuits into modules that conserve board surface area. In a precursor assembly devised as a component for a stacked circuit module in accordance with a preferred embodiment of the present invention, one or more stiffeners are disposed at least partially between a flex circuit and... Agent: Fish & Richardson P.C.

20080088006 - Device having several contact areas and contacting method: A device has a first terminal, second terminal and at least four lateral faces provided with contact areas, of which two respective ones each are mutually opposite. The contact areas of the mutually opposite lateral faces are connected to different ones of the first and second terminals.... Agent: Schoppe, Zimmerman , Stockeller & Zinkler

20080088005 - Sip package with small dimension: A SIP package with a small dimension integrates one or more small size chips. The small size chips are disposed on a back side of a carrying chip and are encapsulated by an encapsulant. The SIP package further includes a substrate having a slot, an encapsulant and a plurality of... Agent: Troxell Law Office PLLC

20080088004 - Wafer level package structure with build up layers: The present invention discloses a structure of wafer level packaging. To use the elastic materials with low k dielectric constant and larger elongation properties as dielectric layers materials used for build up layers of semiconductor device packaging, it can improve the reliability, especially in the board level temperature cycling test.... Agent: Kusner & Jaffe Highland Place Suite 310

20080088008 - Semiconductor package having pad arrangement: A semiconductor package includes a semiconductor chip, multiple first outer connection pads positioned along a first edge of the semiconductor chip in a first direction, and multiple first outer connection leads electrically connected to the first outer connection pads. Multiple first power pads extend from the first edge of the... Agent: Volentine & Whitt PLLC

20080088007 - System, device and method for reducing cross-talk in differential signal conductor pairs: Systems, devices and methods are disclosed herein for reducing crosstalk between pairs of differential signal conductors. One or more ground traces connected to one or more over- or under-lying ground planes by vias are located between pairs of differential signal conductors. The electrical shielding provided by the combination of the... Agent: Kathy Manke Avago Technologies Limited

20080088009 - I/o architecture for integrated circuit package: A circuit package may include an upper surface of first conductive elements and second conductive elements. The first conductive elements may receive input/output signals from respective conductive elements of an integrated circuit die, and the second conductive elements may receive a first plurality of the input/output signals from respective ones... Agent: Buckley, Maschoff & Talwalkar LLC

20080088010 - Electronic device with integrated micromechanical contacts and cooling system: An electronic device can comprise a semiconductor die on which can be formed a micromechanical system. The micromechanical system can comprise a plurality of electrically conductive elongate, contact structures, which can be disposed on input and/or output terminals of the semiconductor die. The micromechanical system can also comprise a cooling... Agent: N. Kenneth Burraston Kirton & Mcconkie

20080088011 - Semiconductor package on which a semiconductor device can be stacked and fabrication method thereof: A semiconductor package on which a semiconductor device can be stacked and fabrication method thereof are provided. The fabrication method includes the steps of mounting and electrically connecting at least one semiconductor chip on the substrate, mounting an electrical connecting structure consisting of an upper layer circuit board and a... Agent: Edwards Angell Palmer & Dodge LLP

20080088013 - Chip and manufacturing method thereof: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The... Agent: Rabin & Berdo, PC

20080088012 - Semiconductor device and wire bonding method therefor: In a semiconductor device, first wires each having a relatively low loop height are formed between a first lead and a plurality of first electrode pads aligned in a first line, and then second wires each having a relatively high loop height are formed between a second lead and a... Agent: Dickstein Shapiro LLP

20080088014 - Stacked imager package: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the... Agent: John A. Jordan, Esq.

20080088016 - Chip with bump structure: A chip with a bump structure comprises a chip, a plurality of pads and a plurality of bumps. The chip includes a microcircuit fabricated by integrated circuit technique. The pads are metallized portions of the chip for electrical connection. The bumps are metal bulges on the pads of the chip... Agent: G. Link Co., Ltd.

20080088015 - Method of manufacturing semiconductor device, semiconductor device, and mounting structure of semiconductor device: A method of manufacturing a semiconductor device, including the following steps, forming a resin layer on a surface of a semiconductor chip, the surface is provided with a bump formed thereon, the resin layer having photosensitivity and adhesiveness, exposing an upper surface of the bump by removing a part of... Agent: Harness, Dickey & Pierce, P.L.C

20080088017 - Semiconductor integrated circuit device: An unoccupied space on a BGA package is utilized effectively to reduce cost. In a semiconductor integrated circuit device in which the lower surface 1a of a BGA package 1 has many ball-shaped terminals 2 arranged in a central section D1 and a peripheral section D2 thereon in a grid... Agent: Bacon & Thomas, PLLC

20080088018 - Semiconductor package accomplishing fan-out structure through wire bonding: Provided is a semiconductor package accomplishing a fan-out structure through wire bonding in which a pad of a semiconductor chip is connected to a printed circuit board through wire bonding. A semiconductor package can be produced without a molding process and can be easily stacked on another semiconductor package while... Agent: Marger Johnson & Mccollom, P.C.

20080088019 - Structure and manufacturing method of a chip scale package: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip... Agent: Saile Ackerman LLC

20080088020 - Semiconductor device and manufacturing method of the same: Provided is a semiconductor device and a manufacturing method of the same which improve adhesion of a semiconductor substrate to a metal wire, the semiconductor substrate having a via hole formed from a bottom surface of the semiconductor substrate up to the metal wire on a top surface of the... Agent: Greenblum & Bernstein, P.L.C

20080088022 - Implementation of a metal barrier in an integrated electronic circuit: A metal barrier is realized on top of a metal portion of a semiconductor product, by forming a metal layer on the surface of the metal portion, with this metal layer comprising a cobalt-based metal material. Then, after an optional deoxidation step, a silicidation step and a nitridation step of... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20080088021 - Semiconductor device and manufacturing method of semiconductor device: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate, a silicide layer provided on the semiconductor substrate, a dielectric layer provided on the semiconductor substrate, a contact layer provided on the silicide layer, a metal layer provided in the dielectric layer and electrically connected... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080088023 - Semiconductor device with bonding pad support structure: A semiconductor device having bonding pads on a semiconductor substrate includes: an upper copper layer that is formed on the lower surface of the bonding pads with a barrier metal interposed and that has a copper area ratio that is greater than layers in which circuit interconnects are formed; and... Agent: Young & Thompson

20080088024 - Semiconductor device: A semiconductor device comprises a semiconductor substrate that is provided with an integrated circuit; a multi-layered member that is installed in the semiconductor substrate, including a plurality of conductive members and an insulation member; and an external terminal formed on a part of the surface of the multi-layered member. A... Agent: Harness, Dickey & Pierce, P.L.C

20080088025 - Semiconductor devices having elongated contact plugs: A method of manufacturing a semiconductor device includes forming conductive structures on a substrate. Each of the conductive structures has a line shape that extends along a first direction parallel to the substrate. Insulating spacers are formed on upper sidewalls of the conductive structures. An insulating interlayer is formed that... Agent: Myers Bigel Sibley & Sajovec

20080088026 - Enhanced interconnect structure: The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can be either partially embedded in the cap layer or completely embedded in the capping... Agent: International Business Machines Corporation Dept. 18g

20080088027 - Dry etchback of interconnect contacts: A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The... Agent: International Business Machines Corporation Dept. 18g

20080088028 - Substrate and manufacturing method of package structure: A substrate board and a manufacturing method of a package structure are provided. The substrate board includes a first surface, a die-attaching area, a cutting area, a plurality of first pads and a first solder mask. The die-attaching area for attaching a die is located on the first surface. The... Agent: Birch Stewart Kolasch & Birch

20080088029 - Semiconductor device having contact barrier and method of manufacturing the same: A semiconductor device having a contact barrier for insulating contacts with a large aspect ratio and having a fine pitch between adjacent conductive lines and a method of manufacturing the same are provided. The semiconductor device includes a buried contact formed in a region between two adjacent first conductive lines... Agent: Marger Johnson & Mccollom, P.C.

20080088030 - Attaching and interconnecting dies to a substrate: An electronics module can include a wiring substrate with openings. The wiring substrate can have traces, and semiconductor dies can be attached by a first relatively weak adhesive to the wiring substrate. Electrical connections through the openings can electrically connect the traces and the terminals. Another adhesive can more strongly... Agent: N. Kenneth Burraston Kirton & Mcconkie

20080088031 - Semiconductor package structure and method of fabricating the same: A semiconductor package structure and a method of fabricating the same are disclosed. A method of fabricating the semiconductor package structure can be characterized as including forming semiconductor chips on a semiconductor substrate. Each of the semiconductor chips includes chip pads. Through-vias are formed through the semiconductor chips. Redistribution structures... Agent: Marger Johnson & Mccollom, P.C.

20080088032 - Stacked modules and method: The present invention stacks integrated circuits into modules that conserve board surface area. In a precursor assembly devised as a component for a stacked circuit module in accordance with a preferred embodiment of the present invention, one or more stiffeners are disposed at least partially between a flex circuit and... Agent: Fish & Richardson P.C.

20080088033 - Microelectronic packages and methods therefor: A microelectronic package includes a microelectronic element having contacts, a flexible substrate spaced from and overlying the microelectronic element and a plurality of conductive posts extending from the flexible substrate and projecting away from the microelectronic element. The conductive posts are electrically interconnected with the microelectronic element. Each conductive post... Agent: Tessera Lerner David Et Al.

20080088034 - Semiconductor device and method for manufacturing the same: It is an object of the present invention to provide a technique for making a semiconductor device thinner without using a back-grinding method for a silicon wafer. According to the present invention, an integrated circuit film is mounted, thereby making a semiconductor device mounting the integrated circuit film thinner. The... Agent: Fish & Richardson P.C.

20080088035 - Circuit board assembly: A circuit board assembly includes a circuit board and a semiconductor chip mounted on the board. The semiconductor chip includes a plurality of solder spots arrayed thereon in a matrix pattern. The solder spots except those located at corners of the pattern are jointed to the board via tin balls... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20080088036 - Dicing die-bonding film: A dicing die-bonding film has a supporting substrate, an adhesive layer formed on the supporting substrate, and a die-bonding adhesive layer formed on the adhesive layer, and further has a mark for recognizing the position of the die-bonding adhesive layer. It is possible to provide a dicing die-bonding film in... Agent: Knobbe Martens Olson & Bear LLP

20080088037 - Semiconductor package and method for manufacturing the same: Provided are a semiconductor package and a method for manufacturing the same. The semiconductor package includes a semiconductor chip, a substrate attached to the semiconductor chip, a wire electrically connecting the semiconductor chip to the substrate, an external connection terminal electrically connecting the semiconductor chip to the outside, and an... Agent: Mills & Onello LLP

20080088038 - Bond pad structures and integrated circuit chip having the same: Bonding pad structures and integrated circuits having the same are provided. An exemplary embodiment of a bond pad structure comprises a bond pad layer. A passivation layer partially covers the bond pad layer from edges thereof and exposes a bonding surface, wherein the passivation layer is formed with a recess... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080088039 - Substrate with heat-dissipating dummy pattern for semiconductor packages: A semiconductor packaging substrate with heat-dissipating dummy patterns primarily comprises a dielectric, a plurality of leads, at least a dummy pattern and a plurality of heat-conducting bars where the leads and the dummy pattern are formed on the dielectric. At least one of the leads is a high-power lead. The... Agent: Troxell Law Office PLLC Suite 1404

20080088040 - Method for fabricating conformal electrodes using non-wettable surface and liquid metal: A diode device is disclosed that comprises a non-wettable electrode, a wettable electrode and a liquid metal disposed between the electrodes. The diode device may additionally comprise a non-wettable housing, preferably cylindrical. The diode device may additionally comprise a piston means able to change a volume of the liquid metal.... Agent: Borealis Technical Limited

20080083916 - Nonvolatile memory device and fabrication method thereof: A nonvolatile memory device and a method for its fabrication may ensure uniform operating characteristics of ReRAM The ReRam may include a laminated resistance layer that determines phase of ReRAM on an upper edge of a lower electrode for obtaining a stable threshold drive voltage level.... Agent: Marshall, Gerstein & Borun LLP

20080083917 - Self-aligned masks using multi-temperature phase-change materials: A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer, patterning the second layer using the multi-temperature phase-change material as a mask, reflowing the multi-temperature phase-change material, and patterning... Agent: Marger Johnson & Mccollom/parc

20080083918 - Storage element: A storage element includes resistance changing elements 10 having recording layers 2, 3 provided between two electrodes 1, 4 and in which resistance values of the recording layers 2, 3 are reversibly changed with application of electric potential with different polarities to these two electrodes 1, 4, at least part... Agent: Wolf Greenfield & Sacks, P.c.

20080083919 - Light emitting diode: On a GaAs substrate 1, a light emitting part 4, an intermediate layer 5 of AlGaInP and a current spreading layer 6 are sequentially formed. The light emitting part 4 includes a first conductivity type AlGaInP based lower cladding layer 41, an AlGaInP based light emitting layer 42, and a... Agent: Foley And Lardner LLP Suite 500

20080083920 - Composition for preventing leaning in formation of capacitor, and method for manufacturing capacitor using the same: A method for manufacturing a capacitor of a semiconductor device by using a composition to prevent leaning of a capacitor. The method includes forming a barrier film and a capacitor oxide film over a semiconductor substrate including an interlayer insulation film with contact plugs for storage nodes; etching the capacitor... Agent: Townsend And Townsend And Crew, LLP

20080083921 - Semiconductor memory device and method of forming the same: A semiconductor memory device and a method of forming the same are disclosed. The semiconductor memory device may include a first electrode. A monolayer is coupled to the first electrode. An organic memory layer is coupled to the monolayer. A second electrode is coupled to the organic memory layer.... Agent: Marger Johnson & Mccollom, P.c.

20080083922 - Radio frequency test key structure: A radio frequency test key structure comprises a substrate, a bottom metal layer and a top metal layer. A narrow testing region is defined on the substrate. The bottom metal layer is positioned on the substrate and in the narrow testing region, and including an opening to expose parts of... Agent: North America Intellectual Property Corporation

20080083923 - Semiconductor device: Provided is a semiconductor device including a bonding pad allowing a probe contact region and a bonding region to be clearly distinguished and thereby controlled. The semiconductor device includes the bonding pad and a slit via region provided to a lower layer of the bonding pad. The slit via region... Agent: Young & Thompson

20080083925 - Solid-state imaging device: A solid-state imaging device comprises pixels including: a light receiving portion comprising intra-substrate photoelectric conversion portions, formed in a silicon substrate, that detect light rays of different color, an on-substrate photoelectric conversion portion, stacked above the intra-substrate photoelectric conversion portions, that detects light rays of a color differing from the... Agent: Sughrue-265550

20080083926 - Printing device structures using nanoparticles: The specification and drawings present a new apparatus and method for printing transistor or diode structures using nanoparticles (e.g., silicon nanoparticles). Si-based electronic structures (e.g., transistors, diodes) can be printed in a simple low cost process and thus being a potential alternative to obtain a low cost manufacturing process for,... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20080083927 - Display device and method of manufacturing the same: A display device includes a substrate, a gate insulating film provided over the substrate and disposed between a semiconductor layer and a first conductive layer including a capacitor electrode and a gate electrode, an interlayer insulating film formed over the semiconductor layer, the first conductive layer and the gate insulating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080083929 - Ac/dc light emitting diodes with integrated protection mechanism: A highly reliable, high voltage AC/DC LED device with integrated protection mechanism is disclosed. The protection element can be a current-limiting resistor, monolithically integrated on LED chip, or a discrete resistor assembled in the lamp package or submount. The protection elements may also include other parts integrated on a submount.... Agent: Lathrop & Gage Lc

20080083930 - Transparent ohmic contacts on light emitting diodes with growth substrates: A light emitting diode is disclosed that includes a growth substrate, a substantially transparent ohmic contact on a first surface of the growth substrate, a Group III nitride, light-emitting active region on a second surface of the growth substrate, a p-type Group III nitride contact layer on the active region... Agent: Summa, Allan & Additon, P.a.

20080083931 - Light emitting device: A light emitting device includes a package having a recess defined by an inner wall and a bottom surface and a lead terminal exposed at the bottom surface of the recess and protruded outward from the package. The lead terminal exposed at the bottom surface of the recess portion including... Agent: Global Ip Counselors, LLP

20080083924 - Thin film transistor having chalcogenide layer and method of fabricating the thin film transistor: Provided are a thin film transistor (TFT) having a chalcogenide layer and a method of fabricating the TFT. The TFT includes an amorphous chalcogenide layer, a crystalline chalcogenide layer, source and drain electrodes, and a gate electrode. The amorphous chalcogenide layer forms a channel layer. The crystalline chalcogenide layer is... Agent: Ladas & Parry LLP

20080083928 - Crystallization apparatus and method, manufacturing method of electronic device, electronic device, and optical modulation element: A manufacturing method of an electronic device includes positioning a processed substrate with respect to a substrate stage of a crystallization apparatus and supporting it with at least one positioning mark previously provided on the processed substrate being used as a references, applying a modulated light beam to a predetermined... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080083932 - Iii-nitride heterojunction semiconductor device and method of fabrication: A III-nitride heterojunction power semiconductor device having a barrier layer that includes a region of reduced nitrogen content.... Agent: Ostrolenk Faber Gerb & Soffen

20080083933 - Semiconductor device and method for fabricating the same: A semiconductor device has a Group III nitride semiconductor layer and a gate electrode formed on the Group III nitride semiconductor layer. The gate electrode contains an adhesion enhancing element. A thermally oxidized insulating film is interposed between the Group III nitride semiconductor layer and the gate electrode.... Agent: Mcdermott Will & Emery LLP

20080083935 - Local collector implant structure for heterojunction bipolar transistors: A bipolar transistor structure includes an intrinsic base layer formed over a collector layer, an emitter formed over the intrinsic base layer, and an extrinsic base layer formed over the intrinsic layer and adjacent the emitter. A ring shaped collector implant structure is formed within an upper portion of the... Agent: Cantor Colburn LLP - Ibm Fishkill

20080083934 - Local collector implant structure for heterojunction bipolar transistors and method of forming the same: A bipolar transistor structure includes an intrinsic base layer formed over a collector layer, an emitter formed over the intrinsic base layer, and an extrinsic base layer formed over the intrinsic layer and adjacent the emitter. A ring shaped collector implant structure is formed within an upper portion of the... Agent: Cantor Colburn LLP - Ibm Fishkill

20080083936 - Interconnect layer of a modularly designed analog integrated circuit: A method of constructing an integrated circuit involves selecting modular tiles and then generating a functional circuit layout using the tiles. Modular tiles that perform predetermined functions and that have approximately the same length and width dimensions are selected from a library of validated tiles. The tiles have input-output terminals... Agent: Imperium Patent Works

20080083937 - Semiconductor integrated circuit: Wiring of a PDP address driver IC is disclosed which affords an adequate permitted current capacity. In the PDP address driver IC that drives the PDP, a layer, in which a planar high voltage ground wiring layer and a planar high voltage power wiring layer are formed, is provided atop... Agent: Rossi, Kimms & Mcdowell LLP.

20080083939 - Active pixel sensor having two wafers: A vertically-integrated active pixel sensor includes a sensor wafer connected to a support circuit wafer. Inter-wafer connectors or connector wires transfer signals between the sensor wafer and the support circuit wafer. The active pixel sensor can be fabricated by attaching the sensor wafer to a handle wafer using a removable... Agent: F-p, Patent Legal Staff Eastman Kodak Company

20080083938 - Image sensors and methods of fabricating image sensors: A semiconductor structure includes a transistor formed over a substrate. The transistor includes a transistor gate and at least one source/drain region. The semiconductor structure includes a pre-determined region coupled to the transistor. The semiconductor structure further includes a resist protection oxide (RPO) layer formed over the pre-determined region, wherein... Agent: Duane Morris LLP Ip Department (tsmc)

20080083940 - Solid-state image pickup device: A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion... Agent: Robert J. Depke Lewis T. Steadman

20080083941 - Self-aligned strap for embedded trench memory on hybrid orientation substrate: Structures including a self-aligned strap for embedded trench memory (e.g., trench capacitor) on hybrid orientation technology (HOT) substrate, and related method, are disclosed. One structure includes a hybrid orientation substrate including a semiconductor-on-insulator (SOI) section and a bulk semiconductor section; a transistor over the SOI section; a trench capacitor in... Agent: Hoffman, Warnick & D'alessandro Llc

20080083943 - Dual-gate memory device and optimization of electrical interaction between front and back gates to enable scaling: A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor... Agent: Macpherson Kwok Chen & Heid LLP

20080083942 - Single-poly non-volatile memory cell: A non-volatile memory cell includes a floating gate transistor having a floating gate coupled to a metal layer capacitor defined in one or more metal layers. Within each metal layer, the metal layer capacitor includes a first plate coupled to the floating gate and a second plate separated from the... Agent: Jonathan W. Hallman Macpherson Kwok Chen & Heid LLP

20080083944 - Nand-type flash memory devices including selection transistors with an anti-punchthrough impurity region and methods of fabricating the same: A NAND-type flash memory device including selection transistors is provided. The device includes first and second impurity regions formed in a semiconductor substrate, and first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions. The first and second selection gate patterns are... Agent: Myers Bigel Sibley & Sajovec

20080083945 - Semiconductor memory array of floating gate memory cells with program/erase and select gates: A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an electrically conductive floating gate having a first portion... Agent: Dla Piper Us LLP

20080083946 - Memory cell system with charge trap: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, and slot plane antenna plasma oxidizing the charge trap layer for forming a second insulator layer.... Agent: Farjami & Farjami LLP

20080083947 - Semiconductor device and method of fabricating the same: A semiconductor device includes a first barrier insulating film formed on upper surfaces of impurity diffusion regions and sidewalls of gate electrodes, a first insulating film formed on the first barrier insulating film so as to bury each region between the gate electrodes, a second barrier insulating film formed continuously... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080083948 - Sige selective growth without a hard mask: MOS transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an... Agent: Slater & Matsil, L.l.p.

20080083950 - Fused nanocrystal thin film semiconductor and method: A thin film semiconductor and a method of its fabrication use induced crystallization and aggregation of a nanocrystal seed layer to form a merged-domain layer. The nanocrystal seed layer is deposited onto a substrate surface within a defined boundary. A reaction temperature below a boiling point of a reaction solution... Agent: Hewlett Packard Company

20080083949 - Mosfet with body contacts: A semiconductor structure includes a metal oxide semiconductor field effect transistor that includes a body contact region that extends from body region located beneath a channel region that separates a pair of source/drain regions within the metal oxide semiconductor field effect transistor. The body contact region is recessed with respect... Agent: Scully, Scott, Murphy & Presser, P.c.

20080083951 - Fets with self-aligned bodies and backgate holes: Embodiments of the invention disclose a design structure for a FET with a shallow source/drain region, a deep channel region, a gate stack and a back gate that is surrounded by dielectric. The FET structure also includes halo or pocket implants that extend through the entire depth of the channel... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080083952 - Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof: Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from... Agent: Scully, Scott, Murphy & Presser, P.c.

20080083953 - Method of manufacturing a semiconductor device: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the... Agent: Eric Robinson

20080083954 - Semiconductor device and manufacturing method thereof: An object is to provide a semiconductor device mounted with memory which can be driven in the ranges of a current value and a voltage value which can be generated from a wireless signal. Another object is to provide write-once read-many memory to which data can be written anytime after... Agent: Eric Robinson

20080083955 - Intrinsically stressed liner and fabrication methods thereof: A stressed liner for improving carrier mobility in a transistor and a method for fabricating the same is disclosed. The stressed liner includes an intrinsically stressed conductive film encapsulated between two insulating layers such as silicon nitride, silicon oxide, or oxynitride. The stressed liner may be compressively-stressed or tensile-stressed depending... Agent: Hoffman, Warnick & D'alessandro Llc

20080083956 - Semiconductor device and manufacturing method thereof: In a MIS transistor of which gate length is 10 nm or less, a gate insulator comprising a silicon oxide film formed on a silicon substrate and a high-k film formed on the silicon oxide film has a nitrided region including more nitrogen at the lateral side than at the... Agent: Reed Smith LLP

20080083957 - Micro-electromechanical system package: A micro-electromechanical system package includes a substrate, a group of components, isolative stuff and a conductive shield. The substrate is made with an upper face and a lower face. The group is mounted on the upper face of the substrate. The isolative stuff seals the group and the upper face... Agent: Kamrath & Associates P.a.

20080083958 - Micro-electromechanical system package: A micro-electromechanical system package includes a substrate, a set of components, at least one solder pad, a frame, a peripheral shield and a top shield. The set is provided on the substrate. At least one solder pad is attached to the substrate opposite to the set. A frame is provided... Agent: Kamrath & Associates P.a.

20080083959 - Stacked structures and methods of forming stacked structures: A stacked structure includes a first die bonded over a second die. The first die has a first die area defined over a first surface. At least one first protective structure is formed over the first surface, around the first die area. At least one side of the first protective... Agent: Duane Morris LLP Ip Department (tsmc)

20080083960 - Package structure and packaging method of mems microphone: A package structure of a micro-electromechanical system (MEMS) type microphone is disclosed. The MEMS microphone comprises a substrate, a MEMS chip, an acoustic wave cover, and an encapsulant. The substrate has connection pads. The MEMS chip is electrically coupled to the connection pads. The MEMS chip includes an acoustic wave... Agent: Jianq Chyun Intellectual Property Office

20080083961 - Semiconductor microphone unit: A semiconductor microphone unit includes a semiconductor microphone chip having a diaphragm covering an inner hole of a support. The support is adhered onto the surface of a support substrate whose thermal expansion coefficient higher than the thermal expansion coefficient of the support via a thermosetting adhesive in such a... Agent: Dickstein Shapiro LLP

20080083962 - Force input control device and method of fabrication: Method of fabricating 3-dimensional force input control device are disclosed. These roughly follow a process of providing a first substrate having side one and side two, fabricating stress-sensitive IC components and signal processing IC on the side one of the first substrate, fabricating closed trenches on the side two of... Agent: Fitch Even Tabin And Flannery

20080083963 - P-i-n semiconductor diodes and methods of forming the same: An arrangement of pillar shaped p-i-n diodes having a high aspect ration are formed on a semiconductor substrate. Each device is formed by an intrinsic or lightly doped region (i-region) positioned between a P+ region and an N+ region at each end of the pillar. The arrangement of p-i-n diodes... Agent: International Business Machines Corporation Dept. 18g

20080083964 - Semiconductor image sensor die and production method thereof, semiconductor image sensor module, image sensor device, optical device element, and optical device module: A semiconductor image sensor die includes a substrate, an imaging area, a surrounding circuit area, a plurality of electrode portions, a translucent member, a transparent adhesive, and a bump. The imaging area, the surrounding circuit area, and the electrode portion are provided on an upper surface of the substrate. The... Agent: Mcdermott Will & Emery LLP

20080083965 - Wafer level chip scale package of image sensor and manufacturing method thereof: Provided are a wafer level chip scale package of an image sensor and a manufacturing method thereof. The wafer level chip scale package includes: a wafer including an image sensor and a pad on the top surface thereof and inclined surfaces on both ends thereof; expansion pads formed on the... Agent: Staas & Halsey LLP

20080083966 - Schottky barrier semiconductor device: The present invention provides a Schottky barrier semiconductor device having a semiconductor substrate 101, a low-concentration semiconductor layer 102, trenches 103 formed in the low-concentration semiconductor layer 102 and extending to the semiconductor substrate 101, and a mesa portion 102a formed between the trenches 103. This provides a high durability... Agent: Steptoe & Johnson LLP

20080083967 - Capacitor integrated in semiconductor device: Provided is a capacitor integrated in a semiconductor device which allows a large capacitance per unit area; small production variations in a capacitance; a high Q-value; and a high self-resonant frequency. To attain this, each of a first wiring layer and a second wiring layer includes a wire group on... Agent: Wenderoth, Lind & Ponack L.l.p.

20080083968 - Bipolar transistor and method of manufacturing the same: The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080083969 - Rectifier circuit, semiconductor device using the rectifier circuit, and driving method thereof: An object of the present invention is to provide a rectifier circuit which can suppress loss of power due to parasitic capacitance or parasitic inductance of a semiconductor element. The rectifier circuit matches or mismatches impedance between a circuit of a previous stage and the rectifier circuit in accordance with... Agent: Eric Robinson

20080083970 - Method and materials for growing iii-nitride semiconductor compounds containing aluminum: A method for growing III-nitride films containing aluminum using Hydride Vapor Phase Epitaxy (HVPE) is disclosed, and comprises using corrosion-resistant materials in an HVPE system, the region of the HVPE system containing the corrosion-resistant materials being an area that contacts an aluminum halide, heating a source zone with an aluminum-containing... Agent: Gates & Cooper LLP Howard Hughes Center

20080083971 - Electronic device and lead frame: A lead frame facilitates the handling, positioning, attachment, and/or continued integrity of multiple dies, without the use of multiple separate parts, such as jumpers. The lead frame includes a number of structures, each of which is attached to at least one lead. At least one receiving surface, arranged to receive... Agent: Mayer & Williams Pc

20080083972 - Microelectronic component assemblies and microelectronic component lead frame structures: The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead frame structure may include a set of leads extending in a first direction and a dam bar. Each of the leads may have an outer length and... Agent: Perkins Coie LLP Patent-sea

20080083973 - Lead frame for an optical semiconductor device, optical semiconductor device using the same, and manufacturing method for these: There is provided a lead frame for an optical semiconductor device, an optical semiconductor device using such lead frame, and a manufacturing method for these, where the optical semiconductor device exhibits favorable brightness over a long period of time by preventing discoloration and degeneration of a plating layer provide on... Agent: Mcdermott Will & Emery LLP

20080083974 - Light-emitting device: A light-emitting device comprises: a coupling base, at least one light-emitting chip, a layer of glue, and a lens, wherein the coupling base is designed for coupling with at least one light-emitting chip. The light-emitting chip is electrically connected with a plurality of frames mounted inside the coupling base. The... Agent: Troxell Law Office Pllc

20080083977 - Edge connect wafer level stacking: In accordance with an aspect of the invention, a stacked microelectronic package is provided which may include a plurality of subassemblies, e.g., a first subassembly and a second subassembly underlying the first subassembly. A front face of the second subassembly may confront the rear face of the first subassembly. Each... Agent: Tessera Lerner David Et Al.

20080083975 - Stacked structures and methods of fabricating stacked structures: A stacked structure includes a first die coupled to a first substrate and having a first conductive structure formed through the first die. A second die is mounted over the first die. The second die is coupled to the first substrate by the first conductive structure. At least one first... Agent: Duane Morris LLP Ip Department (tsmc)

20080083976 - Edge connect wafer level stacking: A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second... Agent: Tessera Lerner David Et Al.

20080083978 - Semiconductor device: A semiconductor device having a first semiconductor chip with an SDRAM and a second semiconductor chip with a an MPU controlling the SDRAM. The contour size of the semiconductor device is reduced to a smaller size without impairing the testability of the first semiconductor chip. The two semiconductor chips are... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080083980 - Cmos image sensor chip scale package with die receiving through-hole and method of the same: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad; a die having micro lens area disposed within the die receiving through hole; a transparent cover covers the micro lens area; a surrounding... Agent: Kusner & Jaffe Highland Place Suite 310

20080083979 - Wafer holder and semiconductor manufacturing apparatus equipped with wafer holder: The wafer holder of the present invention is a ceramic wafer holder in which a heating body and a high-frequency electrode are embedded, and a diameter of the high-frequency electrode embedded in the ceramic is greater than the diameter of an upper high-frequency electrode disposed opposite the high-frequency electrode. A... Agent: Global Ip Counselors, LLP

20080083981 - Thermally enhanced bga packages and methods: BGA packages have thermal properties which are enhanced by a heat channel through the substrate. Solder ball attachment points are provided at the surface of the heat channel for receiving solder balls. A BGA includes an IC operably coupled to a substrate having a top surface for receiving the IC... Agent: Texas Instruments Incorporated

20080083982 - Method and system for initiating proximity warning alarm for electronic devices and prohibiting operation thereof: A system for tracking the location of electronic devices and prohibiting unauthorized operation thereof includes a control unit, configured for wireless communication with an electronic device, the electronic device having a basic input/output system (BIOS) associated therewith. The control unit is configured to remotely disable the electronic device in the... Agent: Cantor Colburn LLP - Ibm Fishkill

20080083983 - Bump electrode including plating layers and method of fabricating the same: In one aspect, a bump electrode of a semiconductor device is formed by providing a substrate including a pad electrode, forming a seed layer over the pad electrode, and forming a mask layer over the seed layer which includes an opening aligned over the pad electrode. A barrier plating layer... Agent: Volentine & Whitt Pllc

20080083984 - Wiring board: In a conventional wiring board, it is not possible to effectively attract electric charges provided by a charged body to a side surface of a wiring board and, therefore, it cannot be said that sufficient measures against static electricity have been taken for the wiring board. A wiring board including:... Agent: Mcginn Intellectual Property Law Group, Pllc

20080083985 - Low fabrication cost, fine pitch and high reliability solder bump: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about... Agent: Mou-shiung Lin

20080083987 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20080083988 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20080083986 - Wafer-level interconnect for high mechanical reliability applications: The structure described herein incorporates an interconnect positioned between two spaced electrical contacts. The interconnect comprises a lead (Pb)-free solder alloy consisting essentially of nickel (Ni), tin (Sn), silver (Ag), and copper (Cu). The nickel (Ni) content is sufficient to produce a smooth interfacial IMC layer in an under bump... Agent: Greenberg Traurig LLP (la)

20080083989 - Semiconductor device and method for fabricating the same: A semiconductor device includes insulation films (6 and 8) formed over a silicon substrate (1), a buried wire (14) formed in the insulation films (6 and 8), and a barrier metal film (A1) formed between each of the insulation films (6 and 8) and the buried wire (14). The barrier... Agent: Mcdermott Will & Emery LLP

20080083990 - Semiconductor device and method of manufacturing the same: A semiconductor device including a copper layer, an aluminum containing layer, and a barrier metal layer having a laminated structure of a titanium layer and a titanium oxide layer formed between the copper layer and the aluminum containing layer.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080083991 - Sub-lithographic local interconnects, and methods for forming same: The present invention relates to a semiconductor device having first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device contains a first sub-lithographic interconnect structure having a width ranging from about 20... Agent: Scully, Scott, Murphy & Presser, P.c.

20080083992 - Novel bonding and probing pad structures: A pad structure includes a first metal-containing layer formed over a substrate. A first passivation layer is formed over the first metal-containing layer. The first passivation layer has a first opening partially exposing the first metal-containing layer. A pad layer is formed over the first passivation layer, covering the first... Agent: Duane Morris LLP Ip Department (tsmc)

20080083993 - Gold-tin solder joints having reduced embrittlement: A metal interconnection for two workplaces such as a semiconductor chip and an insulating substrate. The first workpiece (101) has a first contact pad (201) with a gold stud (110); the second workplace (103) is covered with an insulating layer (213) and a window in the layer to a second... Agent: Texas Instruments Incorporated

20080083994 - Method for producing a semiconductor component and substrate for carrying out the method: A semiconductor component includes a substrate (1) having a chip side and a solder ball side. A semiconductor chip (2) is mounted with an adhesive (3) on the chip side of the substrate. The semiconductor chip is electrically conductively connected to a conductor structure of the substrate (1). Ball pads... Agent: Slater & Matsil LLP

20080083995 - Epoxy resin composition for encapsulating semiconductor device and thin semiconductor device: s

20080083996 - Semiconductor device and an information management system therefor: Individual two-dimensional barcodes are provided for individual chips arrayed on a wafer, individual lead frames to each of which chips are bonded and individual packaged products constituted of resin sealed semiconductor chips based upon chip ID information, to enable information management to be implemented separately for individual chips, individual frames... Agent: Volentine & Whitt Pllc

20080078982 - Current focusing memory architecture for use in electrical probe-based memory storage: An apparatus comprising a substrate, an electrode coupled to the substrate, a modifiable layer coupled to the electrode, and a current focusing layer coupled to the modifiable layer. The current focusing layer comprises a conductive region and an insulating region. A method comprising forming a modifiable layer on an electrode... Agent: Intel/blakely

20080078983 - Layer structures comprising chalcogenide materials: The invention provides a layer structure comprising a first layer, the first layer comprising chalcogenide material, and a second layer being deposited onto the first layer, the second layer comprising silver and another material which decreases the mobility of silver atoms or ions or alternately the second layer being a... Agent: Slater & Matsil LLP

20080078984 - Semiconductor device and method of fabricating the same: A semiconductor device such as a phase change memory device includes a semiconductor substrate including an active region, a conductive pattern disposed to expose the active region, an interlayer dielectric pattern provided on the conductive pattern and including an opening formed on the exposed active region and a contact hole... Agent: Marger Johnson & Mccollom, P.C.

20080078986 - Nitride semiconductor light emitting device and manufacturing method of the same: There is provided a nitride semiconductor light emitting device and a manufacturing method of the same. The nitride semiconductor light emitting device including: a substrate for growing a nitride single crystal, the substrate having electrical conductivity; a p-type nitride semiconductor layer formed on the substrate; an active layer formed on... Agent: Mcdermott Will & Emery LLP

20080078987 - Uv-assisted dielectric formation for devices with strained germanium-containing layers: A method of forming a semiconductor device includes providing a substrate in a vacuum processing tool, the substrate having a strained Ge-containing layer on the substrate and a Si-containing layer on the strained Ge-containing layer, maintaining the substrate at a temperature less than 700° C., and exposing the Si-containing layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080078989 - Quantum well design for a coherent, single-photon detector with spin resonant transistor: A spin coherent, single photon detector has a body of semiconductor material with a quantum well region formed in barrier material in the body. The body has first and second electrodes formed thereon, the first electrode forming an isolation electrode for defining, when negatively energized, an extent of the quantum... Agent: Richard P. Berg, Esq. C/o Ladas & Parry

20080078990 - Copolymer, composition for forming banks, and method for forming banks using the composition: Disclosed are a copolymer of a perfluoropolyether derivative and a photosensitive polymer, a composition for forming banks comprising the copolymer, and a method for forming banks using the composition. Also disclosed is an organic thin film transistor including the composition and an electronic device including the organic thin film transistor.... Agent: Harness, Dickey & Pierce, P.L.C

20080078991 - Organic light emitting display and fabricating method thereof and moving device therefor: An organic light emitting display includes: a substrate; a buffer layer disposed on a top surface of the substrate; a semiconductor layer disposed on the buffer layer; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer; an inter-layer dielectric layer disposed... Agent: Christie, Parker & Hale, LLP

20080078993 - Thin film transistor array panel and manufacturing method thereof: A manufacturing method for a thin film transistor array panel including forming a gate electrode, forming an insulating layer on the gate electrode, sequentially forming a lower conducting layer and a upper conducting layer on the insulating layer, etching the upper conducting layer to form a first source electrode and... Agent: Macpherson Kwok Chen & Heid LLP

20080078992 - Thin film transistor substrate having structure for compensating for mask misalignment: A thin film transistors (TFTs) substrate is structured to maintain as constant across the area of the substrate a kickback voltage due to Miller capacitance between the drain and gate of each TFT even in the presence of manufacturing induced misalignments between the drain electrodes and corresponding gate lines. Each... Agent: Macpherson Kwok Chen & Heid LLP

20080078995 - Chip structure: A chip structure including a substrate, a plurality of chip bonding pads and a plurality of test-bonding-pad sets is provided. The substrate has an active surface and the chip bonding pads are disposed on the active surface. At least part of the chip bonding pads is arranged along a first... Agent: J C Patents, Inc.

20080078994 - Microelectronic die having electrical connections to allow testing of guard wall for damage and method of testing guard wall for damage: A microelectronic die includes: a die substrate; an integrated circuit supported in an active area of the substrate; a plurality of bond pads disposed at a surface of the substrate, at least some of the bond pads being coupled to the integrated circuit; a guard wall supported in the substrate... Agent: Intel Corporation C/o Intellevate, LLC

20080078996 - Semiconductor device and method of manufacturing the same: A semiconductor device in accordance with one embodiment of the present invention includes: a strained semiconductor layer formed on a substrate; and a strain measuring region, provided on the substrate, for measuring a strain of the semiconductor layer. The semiconductor device may further include: a reference information measuring region, provided... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080079001 - Display device and electronic device: An object of the invention is to provide a circuit technique which enables reduction in power consumption and high definition of a display device. A switch controlled by a start signal is provided to a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap... Agent: Fish & Richardson P.C.

20080079002 - Display substrate, method of manufacturing the same and display device having the same: A display substrate includes a gate line, a storage capacitor, a source line, a switching element, a pixel electrode, and a color filter. The gate line is formed on a base substrate. The storage capacitor has a storage line substantially parallel to the gate line. The source line crosses the... Agent: H.c. Park & Associates, PLC

20080078999 - Multi-domain vertical alignment pixel structure and fabrication method thereof: A multi-domain vertical alignment pixel structure including an active device, a passivation layer, a first pixel electrode, a second pixel electrode, a capacitor-coupling electrode and a semiconductor layer is provided. The active device is disposed on the substrate and has an insulating layer, the passivation layer covers the active device... Agent: Jianq Chyun Intellectual Property Office

20080079003 - Dual crystal orientation circuit devices on the same substrate: Embodiments of the invention provide a substrate with a device layer having different crystal orientations in different portions or areas. One layer of material having one crystal orientation may be bonded to a substrate having another crystal orientation. Then, a portion of the layer may be amorphized and annealed to... Agent: Intel/blakely

20080079006 - Signal line for a display device, etchant, thin film transistor panel, and method for manufacturing the same: A thin film panel includes a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, a data line, including a source electrode, and a drain electrode formed on the gate insulating layer or... Agent: Cantor Colburn, LLP

20080079005 - System for displaying images and method for fabricating the same: Systems for displaying images are provided. An exemplary embodiment of a system comprises an active matrix organic electroluminescent device, having a substrate, and a plurality of scan lines and data lines disposed on the substrate, for defining a plurality of pixel regions. Each pixel structure comprises: a switching thin film... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080079007 - Thin-film semiconductor device, display, and method for manufacturing thin film semiconductor device: The present invention is to provide a thin film semiconductor device including a semiconductor thin film and an interlayer insulating film configured to cover the semiconductor thin film. In the interlayer insulating film, a hydrogen supply part and a blocking part against contamination are deposited in that order from a... Agent: Sonnenschein Nath & Rosenthal LLP

20080079008 - Silicon carbide semiconductor device and method for manufacturing the same: A SiC semiconductor substrate is disclosed which includes a SiC single crystal substrate, a nitrogen (N)-doped n-type SiC epitaxial layer in which nitrogen (N) is doped and a phosphorus (P)-doped n-type SiC epitaxial layer in which phosphorus (P) is doped The nitrogen (N)-doped n-type SiC epitaxial layer and the phosphorus... Agent: Rossi, Kimms & Mcdowell LLP.

20080079010 - Thin film transistor panel and manufacturing method thereof: A thin film transistor array panel including a substrate, a gate line and a gate-layer signal transmitting line of a gate driving circuit portion formed on the substrate, a gate insulating layer formed on the gate line and the gate-layer signal transmitting line and having a first contact hole exposing... Agent: F. Chau & Associates, LLC

20080079011 - Electrophoretic display device and method of fabricating the same: A display substrate includes a thin film transistor and a pixel electrode. The thin film transistor includes source and drain electrodes, an active layer covering the source and drain electrodes, and a gate electrode formed on the active layer. The pixel electrode includes the same material as that of the... Agent: Macpherson Kwok Chen & Heid LLP

20080079012 - Illuminated devices utilizing transparent light active sheet material with integrated light emitting diode (led), and methods and kit therefor: A transparent lighting system for a conveyance includes a transparent light active sheet material and an adhesive disposed on the transparent light active sheet material. The transparent light active sheet material includes top and bottom electrically conductive transparent substrates, a pattern of light emitting diode (LED) chips sandwiched between the... Agent: Posz Law Group, PLC

20080079013 - Light emitting diode structure: A light emitting diode structure including a substrate, a first type doped semiconductor layer, an insulating layer, light emitting layers, a second type doped semiconductor layer, a first pad and a second pad is provided. The first type doped semiconductor layer is disposed on the substrate. The insulating layer having... Agent: Jianq Chyun Intellectual Property Office

20080079016 - Long-wavelength resonant-cavity light-emitting diode: An efficient long-wavelength light-emitting diode has a resonant-cavity design. The light-emitting diode preferably has self-organized (In,Ga)As or (In,Ga)(As,N) quantum dots in the light-emitting active region, deposited on a GaAs substrate. The light-emitting diode is capable of emitting in a long-wavelength spectral range of preferably 1.15-1.35 μm. The light-emitting diode also... Agent: Brown & Michaels, PC 400 M & T Bank Building

20080079015 - Optoelectronic component having a luminescence conversion layer: An optoelectronic component having an active layer that emits electromagnetic radiation when the component is on and a luminescence conversion layer disposed after said active layer in a radiation direction of said electromagnetic radiation, the luminescence conversion layer is followed in the radiation direction by a light-scattering translucent layer. The... Agent: Fish & Richardson PC

20080079014 - System and method for light source with discontinuity-containing diffusant: A discontinuity-containing, light-diffusing substrate is placed within an LED light source. In one embodiment, the substrate is placed between an LED light source and a light guide. The light diffusing substrate may include a plurality of air bubbles, grooves or both, effective to mix the colored light and yield a... Agent: Kathy Manke Avago Technologies Limited

20080079019 - Light emitting diode package structure: A light emitting diode (LED) package structure is disclosed. The LED package structure comprises a lead frame which has a chip carrier part, a pair of extended parts, a first electrode and a second electrode. The chip carrier part has an arc frame, a bulge, a first surface and a... Agent: Quintero Law Office, PC

20080078985 - Electrochemical memory with internal boundary: Non-volatile resistance change memories, systems, arrangements and associated methods are implemented in a variety of embodiments. According to one embodiment, a memory cell having two sections with outwardly-facing portions, the outwardly-facing portions electrically coupled to electrodes is implemented. The memory cell has an ionic barrier between the two sections. The... Agent: Crawford Maunu PLLC

20080078988 - Strained si/sige/soi islands and processes of making same: A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A thermal oxidation completes the vertical isolation by use... Agent: Schwegman, Lundberg & Woessner, P.A. Attn: Marvin L. Beekman

20080078997 - Method for forming a bipolar transistor device with self-aligned raised extrinsic base: Disclosed are embodiments of a method of fabricating a bipolar transistor with a self-aligned raised extrinsic base. In the method a dielectric pad is formed on a substrate with a minimum dimension capable of being produced using current state-of-the-are lithographic patterning. An opening is aligned above the dielectric pad and... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080078998 - Semiconductor device: A semiconductor device (npn bipolar transistor) includes an n-type collector layer, a base layer constituted by a p+ diffusion layer, a SiGe layer and a p-type silicon film, an n-type emitter layer and a charge transport prevention film formed between the n-type collector layer and the n-type emitter layer and... Agent: Mcdermott Will & Emery LLP

20080079000 - Display panel and method for manufacturing the same: A display panel has a protection film having a recess. The recess is arranged above a storage electrode and corresponds to a location of the storage electrode in a plan view. A width of the recess is larger in plan view than a width of the storage electrode, and a... Agent: H.c. Park & Associates, PLC

20080079004 - Field insulator fet device and fabrication mehtod thereof: A FinFET and a fabrication method thereof. The FinFET device includes an SOI substrate realized through a substrate, a buried oxide layer formed on the substrate, and a silicon epitaxial layer formed on predetermined areas of the buried oxide layer. A gate oxide layer is formed on the silicon epitaxial... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20080079009 - Semiconductor device: A semiconductor device includes a substrate composed of 3C-SiC, a GaN-based semiconductor layer provided on the substrate, a first electrode provided on the GaN-based semiconductor layer, a second electrode coupled to the substrate, and a control electrode controlling a current flowing between the first electrode and the second electrode.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080079017 - Method of uniform phosphor chip coating and led package fabricated using method: Methods for fabricating LED packages comprising providing an LED chip and covering at least part of it with a liquid medium. An optical element is provided and placed on the liquid medium. The optical element is allowed to settle to a desired level and the liquid medium is cured. LED... Agent: Koppel, Patrick & Heybl

20080079018 - Porcelain enamel substrate for mounting light emitting device and method of manufacturing the same, light emitting device module, illumination device, display unit and traffic signal: A porcelain enamel substrate mounts a light emitting device in which a porcelain enamel layer is coated onto a surface of a core metal, and a reflective cup portion that has a flat bottom surface and a sloping portion that surrounds this bottom surface is provided on a light emitting... Agent: Sughrue Mion, PLLC

20080079020 - High breakdown voltage diode and method of forming same: A multiple layer overvoltage protection device is provided. The method begins by providing a substrate having a first impurity concentration of a first conductivity type to define a mid-region layer. A dopant of a second conductivity type is introduced into the substrate with a second impurity concentration less than the... Agent: Mayer & Williams PC

20080079021 - Arrangement for cooling a power semiconductor module: An arrangement for cooling a power semiconductor module, the power semiconductor module having a substrate with a ceramic plate and may have a metallization thereon, the arrangement has a container for the intake of a coolant with a heat-conducting plate; the heat-conducting plate having two sides, one side joined to... Agent: Coats & Bennett/infineon Technologies

20080079022 - Optical device having photoelectric conversion layer: An optical device has a photoelectric conversion layer that is formed of a tetrahedral bonded semiconductor, including germanium atoms as main components. A substrate has a lattice constant that is smaller than that of germanium. The plane direction of the substrate is a {111} face. A semiconductor lattice extends in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080079023 - Nitride semiconductor device and method for fabricating the same: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second... Agent: Mcdermott Will & Emery LLP

20080079024 - Semiconductor heterostructures having reduced dislocation pile-ups and related methods: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer... Agent: Goodwin Procter LLP Patent Administrator

20080079025 - Exposure device, exposure system, light-emitting element circuit board and image forming apparatus: An exposure device includes a circuit board, a light-emitting element member, a driving signal generating unit and a first voltage supply unit. The light-emitting element member is disposed on the circuit board. The light-emitting element includes plural light-emitting elements arranged in a line and plural switching elements disposed so as... Agent: Morgan Lewis & Bockius LLP

20080079026 - Semiconductor integrated circuit: A semiconductor integrated circuit includes: a macro cell having a plurality of circuit elements; a first macro cell power supply line for supplying a first potential to the macro cell; and a second macro cell power supply line formed in a same wiring layer as a wiring layer of the... Agent: Mcdermott Will & Emery LLP

20080079027 - Field effect devices having a gate controlled via a nanotube switching element: Field effect devices having a gate controlled via a nanotube switching element. Under one embodiment, a non-volatile transistor device includes a source region and a drain region of a first semiconductor type of material and each in electrical communication with a respective terminal. A channel region of a second semiconductor... Agent: Wilmerhale/boston

20080079028 - Semiconductor devices in which a cell gate pattern and a resistor pattern are formed of a same material and methods of forming the same: A semiconductor device is formed by providing a semiconductor substrate comprising a cell region, a peripheral circuit region, and a resistor region, forming a device isolation layer on the semiconductor substrate so as to define an active region, forming a first insulating layer and a polysilicon pattern on the active... Agent: Myers Bigel Sibley & Sajovec

20080079029 - Multi-terminal electrically actuated switch: A multi-terminal electrically actuated switch comprises a source electrode, a drain electrode, and an active region physically connected to both electrodes. The active region comprises at least one primary active region comprising at least one material that can be doped or undoped to change its electrical conductivity, and a secondary... Agent: Hewlett Packard Company

20080079030 - Method for making multi-step photodiode junction structure for backside illuminated sensor: A method of making a backside illuminated sensor is provided. A substrate is provided and a high energy ion implantation is performed over the substrate to implant a first doped region. A layer is formed over the substrate and a self-align high energy ion implantation is performed over the substrate... Agent: Haynes And Boone, LLP

20080079031 - Solid state imaging device: Light guides are formed above each light receiving element. These light guides are made of a high refractive index material, and surrounded by a material of lower refractive index. The light guides are each made up of a light introduction region leading with a constant width from a light entrance... Agent: Birch Stewart Kolasch & Birch

20080079032 - Anti-blooming structures for back-illuminated imagers: An anti-blooming structure for a back-illuminated imager is disclosed. In one embodiment, the anti-blooming structure is formed in a substrate of a first conductivity type having a back side and a front side, comprising a channel region of a second conductivity type formed in the substrate; a barrier region of... Agent: Patent Docket Administrator Lowenstein Sandler P.C.

20080079033 - Stressed field effect transistor and methods for its fabrication: A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080079034 - Semiconductor device including field-effect transistor: A semiconductor device includes a semiconductor region, source and drain regions, gate insulating film, and gate electrode. The semiconductor region has a plane orientation of (001). The source and drain regions are formed away from each other in the semiconductor region, and a channel region is formed in the semiconductor... Agent: Foley And Lardner LLP Suite 500

20080079035 - Symmetric blocking transient voltage suppressor (tvs) using bipolar transistor base snatch: A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient.... Agent: Bo-in Lin

20080079036 - Transistors having buried p-type layers coupled to the gate and methods of fabricating the same: A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080079037 - Field effect device including inverted v shaped channel region and method for fabrication thereof: A semiconductor structure includes a semiconductor layer that includes an inverted V shaped channel region that allows avoidance of a raised source/drain region within the semiconductor structure. In one embodiment, a generally conventional gate electrode is located over a planar surface of the semiconductor layer over the inverted V shaped... Agent: Scully, Scott, Murphy & Presser, P.C.

20080079039 - Field effect transistor comprising a stressed channel region and method of forming the same: A method of forming a field effect transistor comprises providing a substrate comprising, at least on a surface thereof, a first semiconductor material. A recess is formed in the substrate. The recess is filled with a second semiconductor material. The second semiconductor material has a different lattice constant than the... Agent: Williams, Morgan & Amerson

20080079041 - Gate-all-around type semiconductor device and method of manufacturing the same: The gate-all-around (GAA) type semiconductor device may include source/drain layers, a nanowire channel, a gate electrode and an insulation layer pattern. The source/drain layers may be disposed at a distance in a first direction on a semiconductor substrate. The nanowire channel may connect the source/drain layers. The gate electrode may... Agent: Harness, Dickey & Pierce, P.L.C

20080079038 - Semiconductor devices with gate insulation layers having different thicknesses and methods of forming the same: Methods of forming a semiconductor device include an active region and a shallow trench isolation region in a semiconductor substrate, and forming a gate insulation layer on the active region. The gate insulation layer includes a first part spaced apart from the shallow trench isolation region and a second part... Agent: Myers Bigel Sibley & Sajovec

20080079040 - Transistor and method for manufacturing the same: A transistor includes a semiconductor substrate including an active region defined by a device isolation layer, gate lines disposed at specified intervals on the active region of the semiconductor substrate, and trenches of a valley structure etched to a specified depth in the semiconductor substrate in contact with end portions... Agent: Marshall, Gerstein & Borun LLP

20080079042 - Manufacturing method of complementary metal oxide silicon image sensor: A manufacturing method of a CMOS image sensor including at least one of the following steps. Forming an under-structure including a photodiode, a metal wire, and an interlayer insulation film for insulation between a metal pad and the metal wire. Forming a passivation layer on and/or over the under-structure. Selectively... Agent: Sherr & Nourse, PLLC

20080079043 - Light sensing pixel of image sensor with low operating voltage: The image sensor includes a light sensing pixel that includes the transfer transistor for transferring a light-induced charge generated by the photodiode. The light sensing pixel, to dispose the depletion region between the channel of the transfer transistor and a diffusion node, i.e., to operate in the similar pinch-off state,... Agent: Ladas & Parry LLP

20080079044 - Photo detecting apparatus: In a photo detecting apparatus, a first capacitance is caused by a photo detecting element and the first capacitance is charged or discharged by current flowing through the photo detecting element. A second capacitance is connected in parallel with the photo detecting element, and the second capacitance charges or discharges... Agent: Ditthavong Mori & Steiner, P.C.

20080079045 - Reduced crosstalk cmos image sensors: CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A CMOS image sensor has a substrate, an epitaxial layer above the substrate, and a plurality of pixels extending into the epitaxial layer for receiving light.... Agent: Ratnerprestia

20080079046 - Semiconductor apparatus and method for manufacturing the same: According to an aspect of the present invention, there is provided a semiconductor apparatus including: a semiconductor substrate; an element isolation region formed in the semiconductor substrate so as to extend in a first direction; a gate electrode formed in the semiconductor substrate so as to extend in a second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080079047 - Memory device and method of reading/writing data from/into a memory device: In an embodiment of the invention a memory device is provided including a plurality of memory cells, each of which comprises a first electrode, a second electrode and an active material arranged between the first electrode and the second electrode, the first electrodes being arranged parallel to each other and... Agent: Slater & Matsil LLP

20080079048 - Semiconductor device with bulb-type recessed channel and method for fabricating the same: A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The... Agent: Townsend And Townsend And Crew, LLP

20080079049 - Embedded semiconductor device including planarization resistance patterns and method of manufacturing the same: An embedded semiconductor device which a logic region and the memory region are planarized with planarization resistance patterns and a method of manufacturing the same are disclosed. The embedded semiconductor device includes a substrate, gates formed on the substrate, source/drain regions formed on both sides of the gates in the... Agent: F. Chau & Associates, LLC

20080079050 - Semiconductor devices and methods for fabricating the same: Semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device comprises a substrate with a plurality of isolation structures formed therein, defining first and second areas over the substrate. A transistor is formed on a portion of the substrate in the first and... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080079051 - Varactor with halo implant regions of opposite polarity: A metal oxide semiconductor varactor may be formed with HALO implants regions having an opposite polarity from the polarity of the well of the varactor. The HALO implant regions can be angled away from the source and drain. The HALO implant regions can stop the depletion from continuing as the... Agent: Trop Pruner & Hu, PC

20080079055 - Non-volatile memory device: A non-volatile memory device including a semiconductor substrate, an insulating layer, a channel boosting capacitor and a plug. A plurality of memory cells connected in series between a source select line and a drain select line are formed in the semiconductor substrate. The insulating layer is formed on the semiconductor... Agent: Marshall, Gerstein & Borun LLP

20080079052 - Non-volatile memory with local boosting control implant: A substrate of a non-volatile storage system includes selected regions in which additional ions are deeply implanted during the fabrication process. NAND strings are formed over the selected regions such that end word lines of the NAND strings are over the deeply implanted ions. The presence of the deeply implanted... Agent: Vierra Magen/sandisk Corporation

20080079054 - Nonvolatile memory device and method of manufacturing the same: A semiconductor device includes a graded SiGe layer and a strained Si layer that are formed on a Si surface. A gate is formed on the strained Si layer. The gate includes a tunnel oxide layer, a floating gate, a dielectric layer and a control gate is formed.... Agent: Townsend And Townsend And Crew, LLP

20080079056 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device, e.g., a charge trapping type non-volatile memory device, may include a charge trapping structure formed in a first area of a substrate and a gate structure formed in a second area of the substrate. The charge trapping structure may include a tunnel oxide layer pattern, a... Agent: Harness, Dickey & Pierce, P.L.C

20080079053 - Transistor surround gate structure with silicon-on-insulator isolation for memory cells, memory arrays, memory devices and systems and methods of forming same: A transistor surround gate structure and a method of forming thereof on a semiconductor assembly are described. The transistor surround gate structure is formed on a partial silicon-on-insulator in one direction and on a full silicon-on insulator in a second direction and may be scaled to 4f2 line width for... Agent: Micron Technology, Inc.

20080079057 - Aging device: An aging device includes a semiconductor substrate, an element isolation insulating layer which is formed in a recessed portion of the semiconductor substrate and which has an upper surface higher than an upper surface of the semiconductor substrate, first and second element regions isolated by the element isolation insulating layer,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080079058 - Nonvolatile semiconductor memory and a fabrication method for the same: A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectively, and which are aligned along a bit line direction; device... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080079059 - Method of manufacturing a nonvolatile semiconductor memory device and select gate device having a stacked gate structure: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate area floating gate via a first gate... Agent: Yider Wu

20080079060 - Dual function finfet structure and method for fabrication thereof: A dual function finFET structure includes a semiconductor fin located over a substrate. The semiconductor fin has a first side and a second side opposite the first side. A gate dielectric layer is located laterally adjoining the first side of the semiconductor fin, and a control gate is located further... Agent: Scully Scott Murphy & Presser, PC

20080079062 - Dual bit flash memory devices and methods for fabricating the same: Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall... Agent: Ingrassia Fisher & Lorenz, P.C.

20080079061 - Flash memory cell structure for increased program speed and erase speed: According to one exemplary embodiment, a structure, for example a flash memory cell, comprises a transistor gate dielectric stack situated on a semiconductor substrate. The transistor gate dielectric stack includes a bottom oxide layer, a silicon-rich nitride layer situated on the bottom oxide layer, a low silicon-rich nitride layer situated... Agent: Farjami & Farjami LLP

20080079063 - Bottom-gate sonos-type cell having a silicide gate: A bottom-gate thin film transistor having a silicide gate is described. This transistor is advantageously formed as SONOS-type nonvolatile memory cell, and methods are described to efficiently and robustly form a monolithic three dimensional memory array of such cells. The fabrication methods described avoid photolithography over topography and difficult stack... Agent: Foley And Lardner LLP Suite 500

20080079064 - Semiconductor device and method of manufacturing the same: A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping... Agent: Bacon & Thomas, PLLC

20080079067 - Bulb-shaped recess gate of a semiconductor device and method for fabricating the same: A recess gate of a semiconductor device includes: a substrate having a bulb-shaped recess pattern formed therein, wherein the bulb-shaped recess pattern includes a first ball pattern and a second ball pattern formed therein, the first ball pattern having a different diameter than the second ball pattern; a gate insulation... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080079066 - Insulated gate semiconductor device: An IGBT comprises trenches arranged in strips, first emitter diffusion layers formed so as to extend in a direction intersecting the trenches, and contact regions formed to have a rectangular shape. The portions of the contact regions on the first emitter diffusion layers have a smaller width than the other... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080079065 - Novel u-shape metal-oxide-semiconductor (umos) gate structure for high power mos-based semiconductor devices: A U-shape Metal-Oxide-Semiconductor (UMOS) device comprises a P-base layer, an N+ source region disposed in the P-base layer where the source region has a first surface coplanar with a first surface of the P-base layer, a dielectric layer extending through the P-base layer and forming a U-shape trench having side... Agent: Macpherson Kwok Chen & Heid, LLP

20080079069 - Power semiconductor device: The power semiconductor device has an n+ buffer layer 56 provided on the p+ collector layer 55; an n− layer 57 provided on the n+ buffer layer 56; a p base region 58 provided selectively in the top side of the n− layer 57; an n+ emitter region 59 provided... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080079068 - Semiconductor device having asymmetric bulb-type recess gate and method for manufacturing the same: A semiconductor device includes a silicon substrate; a device isolation structure formed in the silicon substrate to delimit an active region which has a pair of gate forming areas, a drain forming area between the gate forming areas, and source forming areas outside the gate forming areas; an asymmetric bulb-type... Agent: Ladas & Parry LLP

20080079070 - Semiconductor device having buried gate line and method of fabricating the same: A semiconductor device having a buried gate line with a shaped gate trench and a method of fabricating the same are disclosed. The semiconductor device includes a trench isolation layer provided in a semiconductor substrate to define a multi-surfaced active region/channel. A gate line extending to the trench isolation layer... Agent: Volentine & Whitt PLLC

20080079071 - Semiconductor device for preventing reciprocal influence between neighboring gates and method for manufacturing the same: A semiconductor device has a pair of gate forming areas, a drain forming area between the gate forming areas, and source forming areas outside of the gate forming areas in the active region. Recess gates are formed in the respective gate forming areas of the active region and depressed inward... Agent: Ladas & Parry LLP

20080079072 - High-voltage semiconductor device structure: A high-voltage semiconductor device structure is provided, which includes a drain structure having two curved structures that are insulatedly adjacent to each other and alternatively arranged, and a source structure, a drain extension structure, and a gate structure formed between the two curved structures. By using the curved structures with... Agent: Morris Manning Martin LLP

20080079073 - Semiconductor device: A transistor structure that improves an ESD withstand voltage is offered. There is formed a P-type insulating isolation layer that divides an N-type epitaxial layer into a plurality of regions and isolates neighboring regions from each other. A diffusion layer doped with high concentration N-type impurities and an electrode extraction... Agent: Morrison & Foerster LLP

20080079075 - Composition for dielectric thin film, metal oxide dielectric thin film using the same and preparation method thereof: This invention pertains to a composition for a dielectric thin film, which is capable of being subjected to a low-temperature process. Specifically, the invention is directed to a metal oxide dielectric thin film formed using the composition, a preparation method thereof, a transistor device comprising the dielectric thin film, and... Agent: Cantor Colburn, LLP

20080079074 - Soi semiconductor components and methods for their fabrication: SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080079076 - Semiconductor device having reduced standby leakage current and increased driving current and method for manufacturing the same: A semiconductor device includes a semiconductor substrate having an active region which includes a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate to expose side surfaces of a portion of the active region including the gate forming zone, such... Agent: Ladas & Parry LLP

20080079077 - Semiconductor device and manufacturing method thereof: A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the... Agent: Sughrue Mion, PLLC

20080079078 - Insulated-gate semiconductor device: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below... Agent: Morrison & Foerster LLP

20080079079 - Insulated-gate semiconductor device: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below... Agent: Morrison & Foerster LLP

20080079080 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the same are provided. A gate insulating film is formed under a vacuum condition to prevent deterioration of reliability of the device due to degradation of a gate insulating material and to have stable operating characteristics. The semiconductor device includes an element... Agent: Mckenna Long & Aldridge LLP

20080079081 - Semiconductor apparatus and manufacturing method: A semiconductor apparatus comprises a cell section including at least two transistors. A layer interval insulation coat is formed at least overlying the gate electrode use polysilicon and the gate contact use polysilicon. A source electrode metal coat is formed overlying the semiconductor substrate and insulated from the gate electrode... Agent: Cooper & Dunham, LLP

20080079082 - Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer: A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors... Agent: Ladas & Parry

20080079083 - Semiconductor device and a method of manufacture therefor: The present invention provides a semiconductor device, and an integrated circuit including the semiconductor device. The semiconductor device, in one embodiment, includes: (1) a gate structure located over a substrate, the gate structuring including a gate dielectric and gate electrode; (2) source/drain regions located within the substrate proximate the gate... Agent: Hitt Gaines, PC Lsi Corporation

20080079085 - semiconductor device comprising isolation trenches inducing different types of strain: By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20080079084 - Enhanced mobility mosfet devices: Semiconductor devices having enhanced mobility regions and methods of forming such devices are disclosed. In some embodiments, a method includes providing a SiGe layer on a supporting substrate, and forming isolation structures within the SiGe layer that define a first region and a second region. The conductivity of the SiGe... Agent: Schwegman, Lundberg & Woessner, P.A.

20080079086 - Semiconductor device and method of manufacturing the same: A semiconductor device and a method of manufacturing the semiconductor device, in which the semiconductor device includes a semiconductor substrate in which PMOS transistor regions and NMOS transistor regions are formed, a PMOS transistor including P-type source and drain regions and a gate electrode, and an NMOS transistor formed on... Agent: F. Chau & Associates, LLC

20080079087 - Semiconductor devices including multiple stress films in interface area and methods of producing the same: A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having... Agent: Myers Bigel Sibley & Sajovec

20080079088 - Semiconductor device and method for manufacturing the same: A semiconductor device includes an active region and a dummy active region formed in a semiconductor substrate to have a distance from each other, an isolation region formed between the active region and the dummy active region and has a top surface lower than top surfaces of the active region... Agent: Mcdermott Will & Emery LLP

20080079089 - Semiconductor device free of gate spacer stress and method of manufacturing the same: A semiconductor device that prevents gate spacer stress and physical and chemical damages on a silicide region, and a method of manufacturing the same, according to an exemplary embodiment of the present invention, includes a substrate, isolation regions formed in the substrate, a gate pattern formed between the isolation regions... Agent: F. Chau & Associates, LLC

20080079090 - Semiconductor device including recessed spherical silicide contact part and method of manufacturing the same: A semiconductor device and fabrication method thereof protect an overgrown metal silicide layer from external damage. The semiconductor device includes: isolation regions formed on a substrate; source/drain regions in the substrate between the isolation regions; a first interlayer insulating film on the substrate, the isolation regions and the source/drain regions;... Agent: Mills & Onello LLP

20080079091 - Nand-type nonvolatile memory device and related method of manufacture: In a NAND type nonvolatile memory device, a first insulating layer covers a common drain region formed in a string active region and a peripheral active region. A second insulating layer covers the first insulating layer. A bit line plug penetrates the first and second insulating layers and is connected... Agent: Volentine & Whitt PLLC

20080079092 - Semiconductor device and method of manufacturing the same: A semiconductor device is provided comprising a supporting substrate, an insulating layer on the substrate, and a first semiconductor layer on the insulating layer. A first high breakdown-voltage transistor is formed in the first semiconductor layer, a second semiconductor layer is formed on the insulating layer and a second high... Agent: Harness, Dickey & Pierce, P.L.C

20080079093 - Transistor including bulb-type recess channel and method for fabricating the same: A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080079094 - Methods for inducing strain in non-planar transistor structures: Methods for inducing compressive strain in channel region of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include forming trenches in a semiconductor body adjacent to gate structure spacers. The semiconductor body can be situated on a substrate and in a... Agent: Intel/blakely

20080079096 - High-voltage-resistant mos transistor and method for manufacturing the same: A high-voltage-resistant MOS transistor having high electrical strength and a method for manufacturing the same, whereby to effectively decrease cost of manufacturing, are provided. The gate electrode includes a pair of separate opposition parts and a combination part sandwiched by the pair of opposition parts so that the opposition parts... Agent: Rabin & Berdo, PC

20080079095 - Metal oxide semiconductor device and method for manufacturing the same: A Metal Oxide Semiconductor device includes a semiconductor substrate; a gate electrode formed on the surface of the substrate, having an offset spacer on each side; source/drain electrodes in the substrate having lightly doped regions respectively; metal silicide located on the gate electrode and the source/drain electrodes; and first impurity... Agent: Squire, Sanders & Dempsey L.L.P.

20080079097 - Semiconductor device and method of fabricating the same: According to an aspect of the invention, there is provided a semiconductor device including a first semiconductor element formed on a semiconductor substrate and using electrons as carriers, and a second semiconductor element formed on the semiconductor substrate and using holes as carriers, a first insulating film and a second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080079098 - Semiconductor device and fabricating method thereof: Provided are a semiconductor device and a fabricating method thereof. In the method, a first wafer including a core region is fabricated. A second wafer including an input/output region is fabricated. Subsequently, the first wafer is coupled to the second wafer. Since an embodiment does not require a process for... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080079099 - Semiconductor device and manufacturing method thereof: A method for improving productivity when manufacturing a semiconductor device. A lower electrode, insulating films, an upper electrode and insulating films are formed on a semiconductor substrate in a sensor region. A cavity is formed between the insulator films above the lower electrode. The lower electrode, insulating film, the cavity... Agent: Miles & Stockbridge PC

20080079100 - Fingerprint sensor and interconnect: Particular embodiments of the present invention are directed to a flexible fingerprint sensor interconnect apparatus that includes a fingerprint sensor chip having at least one die contact and a multilayer flexible substrate. Furthermore, the apparatus includes at least one conductive trace in the multilayer flexible substrate, and the at least... Agent: Baker Botts L.L.P.

20080079101 - Insulation frame device for a stator in a motor: An insulation frame device for a stator in a motor includes a main member with a bore, extension plates and circular plates. The main member extends from a lateral side of the insulation frame. The extension plates extend radially from the circumferential outer surface of the main member. The outer... Agent: G. Link Co., Ltd.

20080079102 - Image sensor structure and method of fabricating the same: A method for fabricating an image sensor structure is provided. The method of fabricating an image sensor structure includes providing a substrate. An image sensor interconnect structure is formed on the substrate. A patterned stop layer is formed on the image sensor interconnect structure. An electrode layer, a first doped... Agent: Birch Stewart Kolasch & Birch

20080079103 - Microlens structure: The present invention provides a microlens structure for a semiconductor device, including a substrate with at least a dielectric layer thereon, at least a micro bump positioned on the dielectric layer surface, and an optical film on the micro bump surface and dielectric layer surface, the micro bump and the... Agent: North America Intellectual Property Corporation

20080079104 - Sensing devices and methods for forming the same: A sensing device includes an optical cavity having two substantially opposed reflective surfaces. At least one nanowire is operatively disposed in the optical cavity. A plurality of metal nanoparticles is established on the at least one nanowire.... Agent: Hewlett Packard Company

20080079105 - Sensor-type package and fabrication method thereof: A sensor-type package and a fabrication method thereof are provided. A sensor-type chip is mounted on a substrate and is electrically connected to the substrate via bonding wires. A light-pervious body is attached to the sensor-type chip, and has one surface covered with a covering layer and another surface formed... Agent: Edwards Angell Palmer & Dodge LLP

20080079106 - Solid-state imaging device: A solid-state imaging device according to the present invention includes a semiconductor substrate; a light-receiving element formed in the semiconductor substrate and photoelectrically converting incident light; and a plurality of wiring layers stacked on top of each other on a surface of the semiconductor substrate where the light-receiving element is... Agent: Greenblum & Bernstein, P.L.C

20080079107 - Field effect transistor having source and/or drain forming schottky or schottky-like contact with strained semiconductor substrate: The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effect transistor minimizes carrier surface scattering, which enables the strained substrate to provide... Agent: David J. King Spinnaker Semiconductor

20080079108 - Method for improving sensitivity of backside illuminated image sensors: A method for improving sensitivity of backside illuminated image sensor. A substrate having a first conductivity type and a first potential. A depletion region having a second conductivity type is formed within the substrate. The depletion region is extended. The thickness of the substrate is reduced. First type conductivity ions... Agent: Haynes And Boone, LLP

20080079109 - Thermoelectric device and method for making the same: A thermoelectric device includes: a first insulator substrate; a plurality of first pads of copper foil attached to the first insulator substrate; a second insulator substrate; a plurality of second pads of copper foil attached to the second insulator substrate; and a plurality of alternately disposed p-type and n-type semiconductor... Agent: Trop Pruner & Hu, PC

20080079110 - Semiconductor device: There is a problem that a reverse off-leak current becomes too large in a Schottky barrier diode. A semiconductor device of the present invention includes a P-type first anode diffusion layer formed in an N-type epitaxial layer, a second anode diffusion layer which is formed so as to surround the... Agent: Morrison & Foerster LLP

20080079112 - Semiconductor device and manufacturing method thereof: A through electrode is formed prior to fabricating a semiconductor device by using a standard manufacturing method. Aside face of the through electrode is insulated from a semiconductor substrate by an insulating film, while the top face thereof is covered with a protective insulating film. These insulating films covering the... Agent: Sughrue Mion, PLLC

20080079111 - Semiconductor devices containing nitrided high dielectric constant films: A semiconductor device containing a substrate, a nitrided high-k film on the substrate, where the nitrided high-k film contains an oxygen-containing film, and a nitrogen-containing film that is oxidized through at least a portion of the thickness thereof. The nitrogen-containing film and the oxygen-containing film contain the same one or... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20080079113 - Fuse structure including cavity and methods for fabrication thereof: A fuse structure comprises a cavity interposed between a substrate and a fuse material layer. The cavity is not formed at a sidewall of the fuse material layer, or at a surface of the fuse material layer opposite the substrate. A void may be formed interposed between the substrate and... Agent: Scully, Scott, Murphy & Presser, P.C.

20080079115 - Electronic device including an inductor and a process of forming the same: An electronic device can include an inductor overlying a shock-absorbing layer. In one aspect, the electronic device can include a substrate, an interconnect level overlying the substrate, and the shock-absorbing layer overlying the interconnect level. The inductor can include conductive traces and looped wires. The conductive traces can be attached... Agent: Larson Newman Abel Polansky & White, LLP

20080079116 - Mos varactor: An MOS varactor may be formed without tip implants or HALO implants. As a result, parasitic resistance may be reduced, jitter may be improved, and the quality factor may be increased, as well as the tunable range of the varactor.... Agent: Trop Pruner & Hu, PC

20080079114 - Striped on-chip inductor: Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one... Agent: Driggs, Hogg, Daugherty & Del Zoppo Co., L.p.a.

20080079117 - Integrated capacitor structure: A semiconductor component including an integrated capacitor structure having at least two groups of at least partly electrically conductive planes and which is patterned in such a way that in at least each group of planes at least one plane has a plurality of strip elements, first strip elements including... Agent: Schwegman, Lundberg & Woessner / Infineon

20080079118 - Reworkable passive element embedded printed circuit board: A reworkable passive element embedded printed circuit board (PCB) including a board member, first and second fillings, and a first passive element. The board member has first and second through holes which are spaced apart from each other. The first and second fillings are buried in the first and second... Agent: Volentine & Whitt PLLC

20080079119 - Semiconductor device and method for manufacturing the same: A p-n junction is formed at the interface of a low-concentration n-type impurity layer 3 and a p-type diffusion region 5 in the vicinity of the upper major surface of an n-type semiconductor substrate 2 of a semiconductor device 1. A mask 15 composed of an absorber is placed on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080079120 - Interconnect structure using through wafer vias and method of fabrication: A device and a method are described which hermetically seals at least one microstructure within a cavity. Electrical access to the at least one microstructure is provided by through wafer vias formed through a via substrate which supports the at least one microstructure on its front side. The via substrate... Agent: Jacquelin K. Spong

20080079121 - Through-silicon via and method for forming the same: A method for forming a through-silicon via includes the steps of defining a groove in each chip of a wafer which has a plurality of semiconductor chips; applying liquid polymer on the wafer to fill the groove; forming an insulation layer on a sidewall of the groove through patterning the... Agent: Ladas & Parry LLP

20080079122 - Termination structures for super junction devices: A semiconductor device 10 is provided. A first layer 12 has a first dopant type; a second layer 14 is provided over the first layer 12; and a third layer 16 is provided over the second layer and has the first dopant type. A plurality of first and second semiconductor... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080079123 - Method of fabricating a mixed microtechnology structue and a structure obtained thereby: A method of fabricating a mixed microtechnology structure includes providing a provisional substrate including a sacrificial layer on which is formed a mixed layer including at least first patterns of a first material and second patterns of a second material different from the first material, where the first and second... Agent: Brinks Hofer Gilson & Lione

20080079124 - Interdigitated leadfingers: One embodiment of the present Invention includes an integrated circuit (IC) package. The IC package comprises a semiconductor die comprising at least one IC. The semiconductor die can include a plurality of conductive elements disposed on a first surface of the semiconductor die. The IC package also comprises a die... Agent: Texas Instruments Incorporated

20080079125 - Microelectronic die assembly having thermally conductive element at a backside thereof and method of making same: A microelectronic die assembly. The die assembly includes a microelectronic die, and a thermally conductive element attached to the backside of the die with a thermal interface material. The thermally conductive element has lateral dimensions smaller than, substantially equal to, or larger than lateral dimensions of the die by up... Agent: Blakely Sokoloff Taylor & Zafman

20080079126 - Plastic surface mount large area power device: A low profile, 1 or 2 die design, surface mount high power microelectronic package with coefficient of expansion (CTE) matched materials such as Silicon die to Molybdenum conductor (bond pads). The CTE matching of the materials in the package enables the device to withstand repeated, extreme temperature range cycling without... Agent: Jackson Walker LLP

20080079127 - Pin array no lead package and assembly method thereof: A microelectronics package comprising: a die, a lead frame comprising: a substrate having a first side and a second side, an array of contacts positioned on the first side and the second side, and an aperture extending through the substrate between the contacts, wherein at least one contact is electrically... Agent: Texas Instruments Incorporated

20080079128 - Lead frame type stack package and method o fabricating the same: A lead frame type stack package in which a lead of the package is well connected to a semiconductor module, and a method of fabricating the same are provided. A lead of an upper package and a lead of a lower package are connected using laser soldering. Since leads of... Agent: Marger Johnson & Mccollom, P.C.

20080079129 - Shape memory based mechanical enabling mechanism: Semiconductor packages and methods to fabricate thereof are described. A decoupling assembly is disposed between a package substrate and a circuit board. The decoupling assembly engages in response to a stimulus such that a semiconductor die is de-coupled from a socket and a circuit board. The decoupling assembly engages in... Agent: Intel Corporation C/o Intellevate, LLC

20080079130 - Integrated circuit package system employing bump technology: An integrated circuit package system that includes: providing an electrical interconnect system including a first lead-finger system and a second lead-finger system; connecting a first device to the first lead-finger system with a wire bond; stacking a second device over the first device; and connecting the second device to the... Agent: Law Offices Of Mikio Ishimaru

20080079131 - Stack package and method for manufacturing the same: A stack package comprises a substrate having a circuit pattern; at least two semiconductor chips stacked on the substrate, having a plurality of through-via interconnection plugs and a plurality of guard rings which surround the respective through-via interconnection plugs, and connected with each other by the medium of the through-via... Agent: Ladas & Parry LLP

20080079132 - Inverted csp stacking system and method: Two or more integrated circuits are stacked into a high density circuit module. The lower IC is inverted. Electrical connection to the integrated circuits is made by module contacts on a flexible circuit extending along the lower portion of the module. In one embodiment, the flexible circuit provides a balanced... Agent: Fish & Richardson P.C.

20080079134 - Chip package, chip structure and manufacturing process thereof: A chip structure including an integrated circuit (IC) element, a plurality of bumps and at least one spacer is provided. The IC element has a plurality of contacts. The bumps are disposed on the contacts respectively. The spacer is disposed on the IC element and between two of the bumps... Agent: Jianq Chyun Intellectual Property Office

20080079133 - Stack type semiconductor device package: A stack type semiconductor device package is disclosed having first and second semiconductor device packages mounted in a mirror arrangement on opposing first and second surfaces of an interposer, wherein the first and second semiconductor device packages and the first and second surfaces of the interposer are, respectively, adapted for... Agent: Volentine & Whitt PLLC

20080079135 - Package assembly pinout with superior crosstalk and timing performance: An integrated circuit package (212) for electrically connecting an integrated circuit (216) to a substrate (214) includes a package assembly (218) having an outer periphery (324) and a pinout (220) that includes a first pin array (334), a second pin array (336) and a third pin array (338). The first... Agent: The Law Office Of Steven G. Roeder

20080079136 - Method and apparatus for supplying power to a semiconductor device using a capacitor dc shunt: A power shunt for use within a semiconductor device of a type having a motherboard and an integrated circuit package electrically coupled to the motherboard and of a type having a spaced portion located between the motherboard and the package. The power shunt comprises a capacitor within the spaced portion... Agent: Marger Johnson & Mccollom, P.C. - Intel

20080079137 - Chip packaging overflow proof device: A chip packaging overflow proof device includes a chip disposed on a substrate; a circuit connected to the chip being provided to each of both sides of the substrate; both of the substrate and the chip being placed in a packaging base; a socket being each provided on both sides... Agent: Troxell Law Office PLLC

20080079138 - Semiconductor device: A semiconductor device that mounts a semiconductor chip in a multilayer substrate, including, inner layer conductive patterns formed in the multilayer substrate; extending conductive portions formed to extend on inner layer conductive patterns in the thickness direction, in the chip mounting area into which the semiconductor chip is mounted; and... Agent: Rabin & Berdo, PC

20080079139 - Micro-via structure design for high performance integrated circuits: In some embodiments, a micro-via structure design for high performance integrated circuits is presented. In this regard, an integrated circuit chip package is introduced having a dielectric layer, a plated throughhole in the dielectric layer, and a micro-via coupled with the plated throughhole, wherein the micro-via forms a path around... Agent: Intel/blakely

20080079140 - Electronic system modules and method of fabricaton: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection... Agent: Townsend And Townsend And Crew, LLP

20080079141 - Micro electro-mechanical system module package capable of minimizing interference of noises: A MEMS module package includes a housing with an accommodation chamber and an opening in communication with the accommodation chamber. The housing has a substrate and an electrically insulative cap capped on the substrate and defining with the substrate the accommodation chamber therebetween. A micro electro-mechanical chip is installed on... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080079142 - Wafer-level mems package and manufacturing method thereof: The present invention is related in general to a wafer-level packaging technique for micro-electro-mechanical systems (MEMS). A cap structure is provided encapsulating a MEMS element formed on a base substrate. A channel communicates etching holes provided on said cap structure, for the passage of an etching fluid to a chamber... Agent: Harness, Dickey & Pierce, P.L.C

20080079144 - Dual-chip integrated heat spreader assembly, packages containing same, and systems containing same: A method includes mating a first heat spreader and a second heat spreader, such that the first heat spreader at a mating surface and second heat spreader at a mating surface become parallel and adjacent. The mated first heat spreader and second heat spreader have at least one convection channel... Agent: Schwegman, Lundberg & Woessner, P.A.

20080079143 - Scalable interchangeable multiband power package mounting apparatus: A miniature multiple die packaging assembly suitable for use in a radio is provided. The assembly includes a heatsink having contact with a chassis of the radio, a circuit board containing a plurality of active devices having leads to a perimeter of the circuit board, and a mating board having... Agent: Motorola, Inc

20080079145 - Power semiconductor arrangement: One aspect relates to a power semiconductor arrangement includes a power semiconductor module which is mechanically connected to a heat sink. In order to improve the thermal cycling stability of the connection between a baseplate of the module and a circuit carrier connected thereto, recesses are provided in the baseplate.... Agent: Dicke, Billig & Czaja

20080079146 - Semiconductor-embedded substrate and manufacturing method thereof: A semiconductor-embedded substrate device according to the present invention can relax a thermal stress during fabrication or use and therefore has sufficient heat radiation properties and reliability. A semiconductor-embedded substrate (100) is a multilayer substrate obtained by stacking resin layers and has, inside of the resin layer (2), a semiconductor... Agent: Oliff & Berridge, PLC

20080079147 - Embedded array capacitor with side terminals: In some embodiments, an embedded array capacitor with side terminals is presented. In this regard, an integrated circuit package is introduced having a plurality of micro-vias, a plurality of dielectric layers, and an array capacitor with side terminals coupled with the micro-vias and embedded in the dielectric layers. Other embodiments... Agent: Intel Corporation C/o Intellevate, LLC

20080079148 - Package for mixed signal mcu with minimal pin count: A minimal pin package for a mixed signal integrated circuit for a mixed signal processor based integrated circuit includes a semiconductor chip having a plurality of bond pads disposed thereon with a digital processor digitally interfaceable with at least one of the bond pads. An analog circuit block is provided... Agent: Howison & Arnott, L.l.p

20080079149 - Circuit board arrangement and method for producing a circuit board arrangement: A circuit board arrangement has a circuit board and a number of die elements, which are electrically conductively coupled to the circuit board by means of contacting elements. The die elements are arranged laterally partially overlapping one another on the circuit board, the contacting elements of the respective die elements... Agent: Slater & Matsil LLP

20080079150 - Die arrangement and method for producing a die arrangement: Die arrangement, having a die with a plurality of electronic circuits electrically coupled to one another, at least one first electrical connection region, having at least one electrical connection, and a first passivation layer, which is applied whilst leaving free at least the one first electrical connection region. A second... Agent: Slater & Matsil LLP

20080079151 - Semiconductor module, method for manufacturing the semiconductor module and portable device carrying the same: A semiconductor wafer is prepared where a semiconductor substrate having electrodes and protective film on the surface are formed and arranged in a matrix shape. Then, on the surface of the semiconductor wafer, namely, the semiconductor substrate, an insulating layer is held between the substrate and a copper sheet, integrally... Agent: Fish & Richardson P.C.

20080079152 - Semiconductor wafer and method of manufacturing the same and method of manufacturing semiconductor device: A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating... Agent: Townsend And Townsend And Crew, LLP

20080079153 - Method for forming semiconductor device: A method for forming a semiconductor device including forming a metal layer over a semiconductor substrate; forming a nitride layer over the metal layer; performing a first etching process on the nitride layer; depositing an oxide layer over the nitride layer pattern and forming a photoresist pattern on the oxide... Agent: Sherr & Nourse, PLLC

20080079155 - Hard mask for low-k interlayer dielectric patterning: Described herein are embodiments of a hard mask including a surface to reduce adhesion to an anti-reflective material deposited on a surface, wherein the surface to reduced adhesion provides use of a process to remove the anti-reflective material deposited on the surface that minimizes damage to an interlayer dielectric layer... Agent: Michael A. Bernadicou Blakely, Sokoloff, Taylor & Zafman LLP

20080079154 - Laminated structure, very-large-scale integrated circuit wiring board, and method of formation thereof: The present invention makes it possible to coat the low dielectric constant material of silicon compound in a simple all-wet process with a firmly adhering barrier layer and an electroless copper plating layer as the wiring layer. the advantage of requiring. Thus, the laminated structure formed in this way includes... Agent: Birch Stewart Kolasch & Birch

20080079156 - Metal line in semiconductor device and method for forming the same: A metal line in a semiconductor device includes an insulation layer having trenches formed therein, a barrier metal layer formed over the insulation layer and the trenches, a metal layer formed over the barrier metal layer, wherein the metal layer fills the trenches, and an anti-galvanic corrosion layer formed on... Agent: Townsend And Townsend And Crew, LLP

20080079157 - Electronic device and method of manufacturing the same: The electronic device includes a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the lower surface of the first interconnect layer. The first interconnect layer includes a via plug (first conductive plug). An end face of the via plug on the side of... Agent: Young & Thompson

20080079158 - metal fill region of a semiconductor chip: Disclosed is a metal fill region of a semiconductor chip including a plurality of layer sets of the semiconductor chip, each set including a first metal fill layer, a second metal fill layer, and an insulation layer included disposed in planes parallel to each other, a plurality of metal fill... Agent: Cantor Colburn LLP - IBM Rochester Division

20080079159 - Focused stress relief using reinforcing elements: In a method and system for relieving stress induced within a dielectric layer of a semiconductor device (100), areas in the dielectric layer (236, 238, 242) where the stress exceeds a threshold are identified. The areas, which are in parallel alignment with electrical interconnects such as conductive bumps (130), include... Agent: Texas Instruments Incorporated

20080079161 - Metal layer structure of semiconductor device: A metal layer structure of a semiconductor memory device is disclosed. The metal layer structure includes: a first metal layer to be connected to a contact plug; and a plurality of a second metal layers that are formed in parallel at a second spaced distance around the first metal layer,... Agent: Marshall, Gerstein & Borun LLP

20080079160 - System for separation of an electrically conductive connection: An integrated component includes a semiconductor substrate; at least one interconnect applied on the semiconductor substrate; an insulating layer applied on the at least one interconnect; and at least one opening through the insulating layer which interrupts the at least one interconnect into a first section and a second section.... Agent: Brinks Hofer Gilson & Lione Infineon

20080079162 - Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip, a solder ball for external connection, wiring for electrically connecting the semiconductor chip and the solder ball, a stress relieving layer provided on the semiconductor chip, and a stress transmission... Agent: Oliff & Berridge, PLC

20080079163 - Electronic device and method of manufacturing the same: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer... Agent: Young & Thompson

20080079164 - Electronic device and method of manufacturing the same: The electronic device includes a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the lower surface of the first interconnect layer. The first interconnect layer includes a via plug (first conductive plug). An end face of the via plug on the side of... Agent: Young & Thompson

20080079165 - Barrier formation and structure to use in semiconductor devices: Embodiments of barriers to use in semiconductor devices are presented herein.... Agent: Lee & Hayes, PLLC

20080079166 - Managing forces of semiconductor device layers: Embodiments of semiconductor devices and methods of making such devices are presented herein.... Agent: Lee & Hayes, PLLC

20080079167 - High-density 3-dimensional resistors: Interconnect, i.e., BEOL structures comprising at least one thin film resistor that is located at the same level as that of a neighboring conductive interconnect are provided. The present invention also provides a method of fabricating such interconnect structures utilizing processing steps that are compatible with current interconnect processing. Moreover,... Agent: Scully, Scott, Murphy & Presser, P.C.

20080079169 - Manufacturing method for semiconductor device, semiconductor device, substrate processing system, program and memory medium: The objective of the present invention is to prevent damage to an interlayer insulation film when forming a structure having a first wiring and a second wiring, which is laminated on the first wiring and connected to the first wiring, and are filled in the interlayer insulation film. After forming... Agent: Masuvalley & Partners

20080079168 - Semiconductor element comprising a supporting structure and production method: One or more embodiments are related to a semiconductor component comprising a supporting structure arranged in a first layer sequence, a second layer arranged above the first layer sequence, and a bonding pad. The layer sequence may comprise a plurality of layers of a dielectric and the bonding pad is... Agent: Infineon Technologies Ag Patent Department

20080079170 - Semiconductor device: An electronic component for microwave transmission includes a high resistivity substrate on which is at least located several metallization layers divided into portions. A first set of piled up portions defines a ground ribbon and a second set of piled up portions defines a power ribbon. At least a first... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20080079171 - Semiconductor device having an epitaxial-grown contact plug: A method for manufacturing a semiconductor device includes the steps of epitaxially growing silicon to form a first contact layer in a first opening exposing therethrough a portion of a silicon substrate; forming a dielectric film having a second opening exposing therethrough the top surface of the first contact layer;... Agent: Sughrue Mion, PLLC

20080079172 - Method for fabricating and beol interconnect structures with simultaneous formation of high-k and low-k dielectric regions: A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second ILD layer. A plurality of columnar air gaps is formed in... Agent: Ibm Corporation RochesterIPLaw Dept 917

20080079173 - Integrated circuit package system with pad to pad bonding: An integrated circuit package system includes an integrated circuit die, a first controlled bump over the integrated circuit die, a second controlled bump over the integrated circuit die, and a connector between the first controlled bump and the second controlled bump.... Agent: Law Offices Of Mikio Ishimaru

20080079174 - Substrate slot design for die stack packaging: In some embodiments, a substrate slot design for die stack packaging is presented. In this regard, an apparatus is introduced having a top integrated circuit die, a bottom integrated circuit die, and a substrate, including a slot through which the bottom integrated circuit die is wirebonded to contacts on a... Agent: Intel Corporation C/o Intellevate, LLC

20080079175 - Layer for chip contact element: A chip (1) or a semiconductor wafer having a contact element (2) for electrical contact-connection is described. In this case, the contact element (2) is covered with an organic layer (3).... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080079176 - Method and structure to enhance temperature/humidity/bias performance of semiconductor devices by surface modification: A method is disclosed of repairing wirebond damage on semiconductor chips such as high speed semiconductor microprocessors, application specific integrated circuits (ASICs), and other high speed integrated circuit devices, particularly devices using low-k dielectric materials. The method involves surface modification using reactive liquids. In a preferred embodiment, the method comprises... Agent: International Business Machines Corporation Dept. 18g