Active solid-state devices (e.g., transistors, solid-state diodes) inventions 03/08

20080073635 - Semiconductor memory and method of manufacturing the same: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080073636 - Nonvolatile memory device and fabrication method thereof: A nonvolatile memory device and its fabrication method of the present invention may ensure a margin of the threshold drive voltage during a design process of the device by forming a resistance layer determining phase of ReRAM along an upper edge of a lower electrode, and improve operating characteristics of... Agent: Marshall, Gerstein & Borun LLP

20080073637 - Phase-change material layer and phase-change memory device including the phase-change material layer: A phase-change memory device includes a substrate having a contact region, an insulating interlayer on the substrate, a lower electrode electrically connected to the contact region, a phase-change material layer pattern formed on the lower electrode, and an upper electrode formed on the phase-change material layer pattern. The phase-change material... Agent: Myers Bigel Sibley & Sajovec

20080073638 - Programmable resistance memory devices and systems using the same and methods of forming the same: A programmable resistance memory element and method of forming the same. The memory element includes a first electrode, a dielectric layer over the first electrode and a second electrode over the dielectric layer. The dielectric layer and the second electrode each have sidewalls. A layer of programmable resistance material, e.g.,... Agent: Dickstein Shapiro LLP

20080073639 - Dislocation-free insb quantum well structure on si using novel buffer architecture: A device grade III-V quantum well structure formed on a silicon substrate using a composite buffer architechture and the method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×108 cm−2 to be formed on silicon substrates. In an... Agent: Intel/blakely

20080073641 - Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.... Agent: Goodwin Procter LLP Patent Administrator

20080073647 - Semiconductor device: An object is to provide a semiconductor device in which damages of an element such as a transistor are reduced even when physical force such as bending is externally applied to generate stress in the semiconductor device. A semiconductor device includes a semiconductor film including a channel formation region and... Agent: Nixon Peabody, LLP

20080073648 - Thin film transistor array panel and manufacturing method thereof: A thin film transistor array panel includes a gate electrode formed on a substrate, a gate insulator covering the gate electrode, a source electrode including a first transparent material and disposed on the gate insulator, a drain electrode including a second transparent material and disposed on the gate insulator, and... Agent: Cantor Colburn, LLP

20080073654 - Display device and fabrication method thereof: Improvement in characteristics of a SELAX-TFT and throughput of ELA crystallization is achieved. When a thin film transistor using pseudo single crystal semiconductor and a thin film transistor using particulate polysilicon semiconductor are formed on a single substrate, the film thickness of an amorphous semiconductor film before crystallization in the... Agent: Reed Smith LLP

20080073653 - Semiconductor apparatus and method of manufacturing the same: It is an object of the present invention to provide a technology of controlling a threshold voltage of a thin film transistor in which an amorphous oxide film is applied to a channel layer. There is provided a semiconductor apparatus including a plurality of kinds of transistors, each of the... Agent: Fitzpatrick Cella Harper & Scinto

20080073658 - Semiconductor body and semiconductor chip comprising a semiconductor body: A semiconductor body (2), comprising a semiconductor layer sequence with an active region (3) suitable for generating radiation. The semiconductor layer sequence comprises two contact layers (6, 7), between which the active region is arranged. The contact layers are assigned a respective connection layer (12, 13) arranged on the semiconductor... Agent: Cohen, Pontani, Lieberman & Pavane

20080073660 - Semiconductor light-emitting devices: A semiconductor laser device comprises an n-type cladding layer, a p-type cladding layer, and an active layer which is sandwiched between the n-type cladding layer and the p-type cladding layer. The p-type cladding layer contains magnesium as a dopant impurity. Further, an n-type diffusion blocking layer of a nitride compound... Agent: Leydig Voit & Mayer, Ltd

20080073661 - Light emitting device and display device using the same: A small-size and high-efficiency light emitting device capable of easily emitting green light includes a resonator including a photonic crystal having a refractive-index periodic structure and an isolated defect member formed in the photonic crystal to disturb the refractive-index periodic structure, and an active member provided inside the resonator and... Agent: Fitzpatrick Cella Harper & Scinto

20080073663 - Light emitting diode having a reflective film and method for making the same: An exemplary light emitting diode (30) includes a light output unit (31), an optical lens (33) and a reflective film (35). The optical lens includes a light input surface (331) facing the light output unit, a top interface (333) opposite to the light input surface, and a light output surface... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20080073662 - Method of manufacturing high power light-emitting device package and structure thereof: A method of manufacturing high power light-emitting device packages and structure thereof, wherein the method thereof includes the steps of: (a) forming a plurality of lead frames, each of the lead frames includes a heat-dissipating element and a plurality of leads; (b) electroplating an outer surface of the lead frames... Agent: Rosenberg, Klein & Lee

20080073640 - Method of manufacturing semiconductor device: The method of manufacturing the semiconductor device comprises the step of forming quantum dots 16 on a base layer 10 by self-assembled growth; the step of irradiating Sb or GaSb to the surface of the base layer 10 before or in the step of forming quantum dots 16; the step... Agent: Kratz, Quintos & Hanson, LLP

20080073642 - Semi-conductor component, component, method for the production thereof and use of inorganic-organic hybrid polymers for producng semi-conductor components: The invention relates to a semiconductor component having a metal-insulator structure (MIS) which contains as basic components a substrate, a layer made of an organic semiconductor material and a dielectric layer as insulator. The substrate and/or the dielectric layer made of an inorganic-organic hybrid polymer is chosen from these basic... Agent: Millen, White, Zelano & Branigan, P.C.

20080073643 - Films and structures for metal oxide semiconductor light emitting devices and methods: Semiconductor films and structures, such as films and structures utilizing zinc oxide or other metal oxides, and processes for forming such films and structures, are provided for use in metal oxide semiconductor light emitting devices and other metal oxide semiconductor devices, such as ZnO based semiconductor devices.... Agent: Jacobs & Kim LLP

20080073644 - Thin film transistor array substrate, method for manufacturing the same and system for inspecting the substrate: Disclosed is a thin film transistor substrate and a system for inspecting the same. The thin film transistor substrate comprises gate wiring formed on an insulation substrate and including gate lines, and gate electrodes and gate pads connected to the gate lines; a gate insulation layer covering the gate wiring;... Agent: Macpherson Kwok Chen & Heid LLP

20080073645 - Thin films and methods of making them: Thin, smooth silicon-containing films are prepared by deposition methods that utilize a silicon containing precursor. In preferred embodiments, the methods result in Si-containing films that are continuous and have a thickness of about 150 Å or less, a surface roughness of about 5 Å rms or less, and a thickness... Agent: Knobbe, Martens, Olsen & Bear LLP

20080073646 - P-channel nanocrystalline diamond field effect transistor: An electrically conducting p-channel diamond lattice field effect transistor (DLFET) composed of nanocrystalline diamond having at least about 1020 atoms/cm3 of boron in conduction channel is disclosed, along with methods of making the same. The nanocrystalline diamond may be characterized by having an average grain size diameter of less than... Agent: Marshall, Gerstein & Borun LLP

20080073650 - Fabrication method for polycrystalline silicon thin film and apparatus using the same: The present invention relates to a fabrication method for polycrystalline silicon thin film in which amorphous silicon is crystallized by laser using a mask having a mixed structure of laser transmission pattern group and laser non-transmission pattern group, wherein the mask comprises two or more of dot pattern groups in... Agent: H.c. Park & Associates, PLC

20080073651 - Liquid crystal display device: A horizontal electric field applying type thin film transistor substrate of a LCD device having an increased aperture ratio as well as a simplified manufacturing process. The device includes a gate line having a double layered structure including a transparent first conductive layer and an opaque second conductive layer, a... Agent: Mckenna Long & Aldridge LLP

20080073649 - Thin film transistor substrate and manufacturing method thereof: A thin film transistor substrate and a method of manufacturing the TFT substrate that are capable of simplifying manufacturing processes and protecting a gate driver from being eroded. The thin film transistor substrate includes an insulation substrate including a display area and a non-display area, a gate metal pattern including... Agent: F. Chau & Associates, LLC

20080073652 - Iii-v hemt devices: The semiconductor device has a stacked structure in which a p-GaN layer 32, an SI-GaN layer 62, and an AlGaN layer 34 are stacked, and has a gate electrode 44 that is formed at a top surface side of the AlGaN layer 34. A band gap of the AlGaN layer... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080073656 - Low temperature polysilicon thin film transistor: A low temperature polysilicon thin film transistor and method of manufacturing the same is provided. The low temperature polysilicon thin film transistor comprises a channel region. Among others, one feature of the method according to the present invention is the performance of a plasma treatment to adjust the threshold voltage... Agent: Jianq Chyun Intellectual Property Office

20080073655 - Optoelectronic semiconductor chip: An optoelectronic semiconductor chip comprises a growth substrate with a structured growth area (2) having a multiplicity of elevations (4) and depressions (3), and an active layer sequence (5) applied to the growth area (2).... Agent: Cohen Pontani Lieberman & Pavane LLP Suite 1210

20080073657 - Nitride semiconductor crystal with surface texture: A nitride semiconductor light emitting device is formed by: forming a resist pattern on a first nitride semiconductor layer formed on a substrate, the resist pattern having a region whose inclination angle relative to a substrate surface changes smoothly as viewed in a cross section perpendicular to the substrate surface;... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080073659 - Semiconductor light emitting device: A semiconductor light emitting device is provided, in which the light emitting efficiency of a LED is improved. A semiconductor light emitting device (11) includes a light emitting layer (16) made of a GaN-based semiconductor sandwiched with an n-type GaN-based semiconductor layer (17) and a p-type GaN-based semiconductor layer (15),... Agent: Rabin & Berdo, PC

20080073664 - Semiconductor device and method of fabricating the same: A semiconductor device capable of stabilizing operations thereof is provided. This semiconductor device comprises a substrate provided with a region having concentrated dislocations at least on part of the back surface thereof, a semiconductor element layer formed on the front surface of the substrate, an insulator film formed on the... Agent: Mcdermott Will & Emery LLP

20080073665 - Modified gold-tin system with increased melting temperature for wafer bonding: A semiconductor structure and a bonding method are disclosed that includes a device wafer, a substrate wafer, and a metal bonding system between the device wafer and the substrate wafer. The metal bonding system includes gold, tin, and nickel, and includes at least one discrete layer of gold and tin... Agent: Summa, Allan & Additon, P.A.

20080073666 - Power mosfet integration: A method for integration is disclosed herein. The method includes forming an N-type double drain (NDD) layer, and fabricating at least one transistor from a controller circuitry and a transistor switch on a single chip. The controller circuitry is operable for controlling the transistor switch.... Agent: Patent Prosecution O2mirco , Inc.

20080073667 - Tri-gate field-effect transistors formed by aspect ratio trapping: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of... Agent: Goodwin Procter LLP Patent Administrator

20080073668 - Field-effect heterostructure transistors: An apparatus includes a field-effect transistor (FET). The FET includes a region of first semiconductor and a layer of second semiconductor that is located on the region of the first semiconductor. The layer and region form a semiconductor heterostructure. The FET also includes source and drain electrodes that are located... Agent: Lucent Technologies Inc., Docket Administrator

20080073669 - Structure and method for manufacturing high performance and low leakeage field effect transistor: There is provided a field effect transistor (FET) including a source side semiconductor; a drain side semiconductor; and a gate. The source side semiconductor is made of a high mobility semiconductor material, and the drain side semiconductor is made of a low leakage semiconductor material. In one embodiment, the FET... Agent: Joseph P. Abate Intellectual Property Law

20080073670 - Gallium nitride high electron mobility transistor having inner field-plate for high power applications: A gallium nitride high electron mobility transistor, in which an inner field-plate is disposed between the gate and drain of the high electron mobility transistor, so that an electric field is distributed between gate and drain regions to reduce a peak value and to reduce gate leakage current while maintaining... Agent: Bachman & Lapointe, P.C.

20080073671 - Semiconductor device: The present invention miniaturizes a HEMT element used as a switching element in a radio frequency module. A single gate electrode 17 is formed in an active region defined by an element separation portion 9 on a main surface of a substrate 1 comprising GaAs. The gate electrode 17 is... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080073672 - Semiconductor integrated circuit: A nonvolatile semiconductor memory concerning an example of the present invention comprises a cell array, a plurality of conducting wires extending from the cell array to a lead area, and a plurality of contact holes to arranged in the lead area so that a distance from the end of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080073673 - Semiconductor integrated circuit and semiconductor integrated circuit design method: The height H of several kinds of basic cell are made the same and several kinds of macro cell which have a length which is an integral multiplication of the height H of this basic cell, are prepared, the basic cell and macro cell are mixed and the circuit of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080073674 - Thin film transistor array panel and method for manufacturing the same: The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and... Agent: David W. Heid Macpherson Kwok Chen & Heid LLP

20080073675 - Transistor with start-up control element: A transistor having a start-up control element is provided. The transistor includes an N-type depletion mode transistor and an N-type enhancement mode transistor. The N-type depletion mode transistor includes a drain for electrically connecting to an external power supply, and a gate normally grounded. The N-type enhancement mode transistor includes... Agent: Tung & Associates

20080073676 - Method for fabricating semiconductor device and semiconductor device: An n-channel MOS transistor and a p-channel MOS transistor are formed on a semiconductor substrate 100. The p-channel MOS transistor includes a gate electrode 102a, a first offset sidewall 103a formed on side surfaces of the gate electrode 102a so as to contain fine particles 110 of group IV semiconductor... Agent: Mcdermott Will & Emery LLP

20080073679 - amplification type solid-state image pickup device driving method: A plurality of pixel groups X(n) each comprising a plurality of pixels are set, and switched capacitor amplification parts are provided in correspondence to the pixel groups, respectively. Each of the switched capacitor amplification parts has a charge detection node to which output terminals of the transfer transistors of a... Agent: Edwards Angell Palmer & Dodge LLP

20080073678 - High-sensitivity image sensor and fabrication method thereof: A method of fabricating a high-sensitivity image sensor and the same are disclosed. The disclosed method comprises: etching predetermined regions of active silicon and a buried oxide layer of a SOI substrate by using a mask to expose an N-type silicon substrate; implanting P-type ions into the exposed N-type silicon... Agent: Greenblum & Bernstein, P.L.C

20080073677 - Solid-state imaging device and method of manufacturing the same: A solid-state imaging device with a semiconductor substrate; a pixel formation region in the substrate and including a pixel made of a photoelectric conversion element; and an element isolation portion in the substrate and including an element isolation insulating layer and an impurity element isolation region. The element isolation insulating... Agent: Sonnenschein Nath & Rosenthal LLP

20080073681 - Semiconductor apparatus and method for manufacturing the semiconductor apparatus: According to an aspect of the present invention, there is provided a semiconductor apparatus including a semiconductor substrate, a transistor formed on the semiconductor substrate, an insulating film disposed on the semiconductor substrate, a ferroelectric capacitor and an upper mask. The ferroelectric capacitor includes a lower electrode disposed on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080073680 - Semiconductor device and fabrication process thereof: A semiconductor device includes a conductive oxygen diffusion barrier film formed over a substrate, a metal oxide film formed over the conductive oxygen diffusion barrier film for suppressing diffusion of Pb, a lower electrode containing Pt formed over the metal oxide film, a ferroelectric film containing Pb and formed over... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080073682 - Non-volatile semiconductor memory device and method for fabricating the same: According to an aspect of the present invention, there is provided a non-volatile semiconductor memory device, including a ferroelectric capacitor being stacked a first electrode, a ferroelectric film and a second electrode in order, a first protective film with hydrogen barrier performance, the first protective film being formed under the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080073685 - Semiconductor device and method for manufacturing the same: Ferroelectric capacitors (42) are formed over a semiconductor substrate (10), then, a barrier film (46) directly covering the ferroelectric capacitors (42) is formed. Thereafter, wirings (56a etc.) connected to the ferroelectric capacitors (42) are formed. Further, a barrier film (58) is formed at a position higher than the wirings (56a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080073683 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device includes a semiconductor substrate having a first region and a second region, a transistor placed in the first region of the semiconductor substrate, a first insulating film formed on the semiconductor substrate in the first and second regions and on the transistor, a first ferroelectric capacitor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080073684 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device includes a semiconductor substrate having a first region and a second region, a transistor placed in the first region of the semiconductor substrate, a first insulating film formed on the semiconductor substrate in the first and second regions and on the transistor, a first ferroelectric capacitor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080073686 - Thin-film transistor array and method for manufacturing the same: A thin-film transistor (TFT) array and a method for manufacturing the same, disposing a storage capacitor in a data-line region so that the storage capacitor does not occupy any area of a pixel region so as to increase the aperture ratio. The thin-film transistor array comprises a first conductive layer,... Agent: Wpat, PC

20080073687 - Memory array buried digit line: A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer... Agent: Knobbe Martens Olson & Bear LLP

20080073688 - One-transistor random access memory technology compatible with metal gate process: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM... Agent: Slater & Matsil, L.L.P.

20080073690 - Flash memory device including multilayer tunnel insulator and method of fabricating the same: A flash memory device may include a lower tunnel insulation layer disposed on a substrate, an upper tunnel insulation layer disposed on the lower tunnel insulation layer, a floating gate disposed on the upper tunnel insulation layer, an intergate insulation layer disposed on the floating gate; and a control gate... Agent: Lee & Morse, P.C.

20080073689 - Program/erase schemes for floating gate memory cells: A flash memory cell includes a substrate, a blocking layer over the substrate, a floating gate over the blocking layer, a retention layer over the floating gate, a control gate over the retention layer, a tunneling layer over the control gate, a top gate over the tunneling layer, and a... Agent: Slater & Matsil, L.L.P.

20080073691 - Semiconductor device and method of manufacturing same: A semiconductor device includes: a semiconductor layer; an insulating film provided on the semiconductor layer; and a charge storage layer provided on the insulating film. The semiconductor layer has a channel formation region in its surface portion. The insulating film contains silicon, germanium, and oxygen. The charge storage layer is... Agent: Pearne & Gordon LLP

20080073693 - Semiconductor devices having tunnel and gate insulating layers and methods of forming the same: A semiconductor device includes a semiconductor substrate having a surface, buried isolation regions protruding from the surface of the semiconductor substrate, and a first insulating layer on the surface of the semiconductor substrate between the isolation regions and including a fluorine, nitrogen, and/or heavy hydrogen impurity. A floating electrode is... Agent: Myers Bigel Sibley & Sajovec

20080073692 - Semiconductor chip and method of forming the same: A method of forming a semiconductor device includes sequentially first and second tungsten silicide layers on a silicon layer. The first tungsten silicide layer is in a substantially amorphous state and a ratio of tungsten to silicon in the first tungsten silicide layer is about 1:4.5˜about 1:9.... Agent: Marger Johnson & Mccollom, P.C.

20080073694 - Memory cell arrangements and methods of manufacturing memory cell arrangements: A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between... Agent: Slater & Matsil LLP

20080073697 - Semiconductor device and method of fabricating the same: A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate; an isolation structure formed in a trench, formed in the semiconductor substrate, through a semiconductor oxide film; a floating gate formed on the semiconductor substrate between the isolation structures through an insulating film; a gate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080073696 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate including a first region and a second region being adjacent to the first region; a floating gate electrode layer formed above the semiconductor substrate in the first region, the floating gate electrode layer including a first width; a dummy gate electrode layer formed... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080073695 - Semiconductor memory and method for manufacturing a semiconductor memory: A semiconductor memory including a plurality of cell units arranged in a row direction, each of the cell units includes: a semiconductor region; a first buried insulating film provided on the semiconductor region; a second buried insulating film provided on the first buried insulating film, which has higher dielectric constant... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080073698 - Nonvolatile semiconductor memory element and nonvolatile semiconductor memory device: The channel of each nonvolatile semiconductor memory element has a plate-like shape, and a charge accumulating layer is formed on one face of the channel region, with an insulating film being interposed in between. A control gate electrode is then formed on the charge accumulating layer, with another insulating film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080073700 - Manufacturing method of flash memory device: A method for manufacturing a flash memory device includes: forming a floating gate on a tunnel oxide film formed on a semiconductor substrate; forming an ONO film on the floating gate; performing a well implant process to form a well on the semiconductor substrate; and performing an ashing process and... Agent: Sherr & Nourse, PLLC

20080073699 - Semiconductor device and method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes: forming a first film on a base body; crystallizing the first film by heating; thinning the crystallized first film; and forming a second film on the thinned first film. The first film is made of a material having a high dielectric constant... Agent: Pearne & Gordon LLP

20080073701 - Nonvolatile semiconductor memory device and method of manufacturing the same: A nonvolatile semiconductor memory device includes an array of nonvolatile memory cell transistors, each of which is configured such that a tunnel insulation film, a floating gate electrode, a floating gate insulation film and a control gate electrode are stacked on a surface of a semiconductor substrate. A mean roughness... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080073704 - Nonvolatile semiconductor memory device: The present invention provides a nonvolatile semiconductor memory device including memory cells capable of electrically writing information, and each of the memory cells includes a first insulating film formed on the channel provided between source/drain diffusion layers, an electric charge accumulation layer formed on the first insulating film and is... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080073703 - Nonvolatile semiconductor memory device and method for fabricating the same: A nonvolatile semiconductor memory device includes: diffusion-layer bit lines extending in the column direction in a substrate; an insulating film on the bit line formed on each of the diffusion-layer bit lines and extending in the column direction; a charge trapping layer formed on a region of the substrate positioned... Agent: Mcdermott Will & Emery LLP

20080073702 - Nrom fabrication method: A method of fabricating an oxide-nitride-oxide (ONO) layer in a memory cell to retain charge well in the nitride layer includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer and oxidizing a top oxide layer, thereby causing oxygen to be introduced into the... Agent: Empk & Shiloh, LLP

20080073705 - Semiconductor device: A gate dielectric functioning as a charge-trapping layer of a non-volatile memory cell with a structure of an insulator gate field effect transistor is formed by laminating a first insulator formed of a silicon oxide film, a second insulator formed of a silicon nitride film, a third insulator formed of... Agent: Miles & Stockbridge PC

20080073706 - High withstand voltage trenched mos transistor and manufacturing method thereof: A high withstand voltage transistor includes: a gate electrode provided in a trench formed on a semiconductor substrate; a source and a drain which are respectively formed on a side of the gate electrode and another side of the gate electrode, and which are a predetermined distance away from the... Agent: Harness, Dickey & Pierce, P.L.C

20080073707 - Power mosfet with recessed field plate: A trench MOSFET contains a recessed field plate (RFP) trench adjacent the gate trench. The RFP trench contains an RFP electrode insulated from the die by a dielectric layer along the walls of the RFP trench. The gate trench has a thick bottom oxide layer, and the gate and RFP... Agent: Patentability Associates

20080073708 - Semiconductor device and method of forming the same: A semiconductor device and a method of forming the semiconductor device are provided. The semiconductor device may include, but is not limited to, a semiconductor substrate and a third array of semiconductor elements. The semiconductor substrate may include a first array of separate grooves, a second array of separate active... Agent: Young & Thompson

20080073709 - Semiconductor device and method of manufacturing the same: A semiconductor device in which the reliability of a gate dielectric film is high and a channel length is sufficiently secured and a method of manufacturing the same are provided. The semiconductor device comprises a trench gate transistor. The trench gate transistor comprises: a trench provided in a semiconductor substrate;... Agent: Mcginn Intellectual Property Law Group, PLLC

20080073710 - Semiconductor device with a vertical mosfet and method for manufacturing the same: The size of a gate contact region is decreased by connecting a gate connection electrode embedded in a trench and a gate wiring formed over the gate connection electrode, without forming another conductive film different from the gate connection electrode or the gate wiring. The semiconductor body includes an active... Agent: Young & Thompson

20080073711 - Method of manufacturing a semiconductor integrated circuit device having a columnar laminate: For improving the filling properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X direction. After a first insulating film... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080073712 - Power mosfet, semiconductor device including the power mosfet, and method for making the power mosfet: A metal oxide semiconductor field effect transistor includes a semiconductor substrate; a well region containing an impurity of a first conductivity type disposed on the semiconductor substrate, the well region including a source region and a drain region formed by adding an impurity of a second conductivity type, the source... Agent: Sonnenschein Nath & Rosenthal LLP

20080073713 - Method of fabricating semiconductor device having stress enhanced mos transistor and semiconductor device fabricated thereby: A method of fabricating a semiconductor device having a stress enhanced MOS transistor is provided. A MOS transistor may be formed in a desired, or alternatively, a predetermined region of a semiconductor substrate. A first sacrificial pattern, formed over the source and drain regions of a MOS transistor, may expose... Agent: Harness, Dickey & Pierce, P.L.C

20080073714 - Semiconductor device: A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE... Agent: Miles & Stockbridge PC

20080073715 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device including at least one step of: forming a transistor on and/or over a semiconductor substrate; forming silicide on and/or over a gate electrode and a source/drain region of the transistor; removing an uppermost oxide film from a spacer of the transistor; and forming... Agent: Sherr & Nourse, PLLC

20080073718 - Mask for forming a thin-film transistor, thin-film transistor substrate manufactured using the same and method of manufacturing a thin-film transistor substrate using the same: A mask that is capable of forming a thin-film transistor (TFT) with improved electrical characteristics is presented. The mask includes a drain mask pattern, a source mask pattern and a light-adjusting pattern. The drain mask pattern blocks light for forming a drain electrode. The source mask pattern blocks light for... Agent: Macpherson Kwok Chen & Heid LLP

20080073716 - Optical semiconductor device having ridge structure formed on active layer containing p-type region and its manufacture method: A p-type cladding layer (3) of p-type semiconductor is formed over a substrate. An active layer (5) including a p-type semiconductor region is disposed over the p-type cladding layer. A buffer layer (10) of non-doped semiconductor is disposed over the active layer. A ridge-shaped n-type cladding layer (11) of n-type... Agent: Kratz, Quintos & Hanson, LLP

20080073717 - Semiconductor devices having substrate plug and methods of forming the same: A semiconductor device includes a device isolation layer disposed in a substrate and defining an active region, a first gate pattern on the active region, a first insulating layer on the substrate and the first gate pattern, a first body region on the first insulating layer, and a first substrate... Agent: Lee & Morse, P.C.

20080073719 - Semiconductor device: A semiconductor integrated circuit device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and... Agent: Neil Steinberg

20080073720 - Electrostatic discharge protection device: An electrostatic discharge (ESD) protection device for providing an ESD path between two circuitries is provided. Each circuitry has a power supply terminal and a ground terminal. The protection device comprises an equivalent MOS, a first terminal, and a second terminal. The equivalent MOS comprises a source, a drain and... Agent: Birch Stewart Kolasch & Birch

20080073721 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes at least one MOS transistor that is formed in a main region of the circuit device. The main region has one conductivity type. The semiconductor integrated circuit device also includes a guard ring region formed surrounding the MOS transistor and in contact with the... Agent: Volentine & Whitt PLLC

20080073722 - Circuit for storing information in an integrated circuit and method therefor: A circuit has a storing portion, a write portion and a read portion. In one embodiment, read portion has a transistor which has a substantially thinner gate oxide than the transistors in the storing portion and the transistors in the write portion. In an alternate embodiment, circuit has a plurality... Agent: Freescale Semiconductor, Inc. Law Department

20080073724 - Double layer etch stop layer structure for advanced semiconductor processing technology: A semiconductor device and a method for forming the same provides a double layer contact etch stop layer selectively formed over PMOS transistors with only a single silicon nitride contact etch stop layer formed over NMOS transistors on the same chip. The composite contact etch stop layer structure formed over... Agent: Duane Morris LLPIPDepartment (tsmc)

20080073723 - Selective anisotropic wet etching of workfunction metal for semiconductor devices: Embodiments of an apparatus and methods for providing a workfunction metal gate electrode on a substrate with doped metal oxide semiconductor structures are generally described herein. Other embodiments may be described and claimed.... Agent: Intel Corporation C/o Intellevate, LLC

20080073725 - Buried guard ring structures and fabrication methods: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction... Agent: Zagorin O'brien Graham LLP

20080073727 - Semiconductor device: A semiconductor device is provided. A transistor is formed on a substrate, and a metal silicide layer is formed on the surface of a gate conductor layer and a source/drain region. Next, a surface treatment process is performed to selectively form a protection layer on the surface of the metal... Agent: Jianq Chyun Intellectual Property Office

20080073726 - Semiconductor integrated circuit device and process for manufacturing the same: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080073728 - Semiconductor device and manufacturing method thereof: Semiconductor devices whose current characteristics can be prevented from varying even if a phase shift mask is used for patterning gate electrodes of MISFETs, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, there is provided a semiconductor device comprising a first transistor including... Agent: Amin, Turocy & Calvin, LLP

20080073729 - Semiconductor integrated circuit device using four-terminal transistors: In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080073730 - Semiconductor device and method for formimg the same: A method for forming a semiconductor device includes forming at least one gate electrode having a bent structure along a first direction on a semiconductor substrate, the gate electrode having first and second vertical portions, forming at least one semiconductor fin along a second direction on the semiconductor substrate, the... Agent: Lee & Morse, P.C.

20080073731 - High withstand voltage transistor and manufacturing method thereof, and semiconductor device adopting high withstand voltage transistor: A high withstand voltage transistor is capable of preventing its gate oxidized film from being damaged by a surge voltage/current, and includes: a gate electrode provided in a trench formed on a semiconductor substrate; a source and a drain which are respectively formed on a side of the gate electrode... Agent: Harness, Dickey & Pierce, P.L.C

20080073732 - Method of manufacturing semiconductor device: Embodiments relate to a method of manufacturing a semiconductor device, which may facilitate high integration of the device and may prevent undercut form occurring. In embodiments, the method may include forming a gate insulating film on a semiconductor substrate, forming, on the gate insulating film, a gate electrode having a... Agent: Sherr & Nourse, PLLC

20080073733 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a MIS transistor having a gate electrode which is fully silicided with metal. The edge parts of the gate electrode are lower in height than the other part thereof. Sidewall spacers are formed to cover the side and top surfaces of the edge parts of the... Agent: Mcdermott Will & Emery LLP

20080073734 - Camera module and method of fabricating the same: Example embodiments may provide a camera module including a high-resolution lens member and/or an image sensor chip that may be integrally formed, and a method of fabricating a camera module. Example embodiment camera modules may include a semiconductor package including an image sensor chip. A transparent substrate may include an... Agent: Harness, Dickey & Pierce, P.L.C

20080073735 - Image sensor and fabrication method thereof: An image sensor comprises a lower structure having at least one photodiode and interconnection, a passivation layer on the lower structure, a color filter array on the passivation layer, and a micro-lens array comprising an oxide layer on the color filter array.... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080073736 - Image sensor and method of fabricating the same: Disclosed is an image sensor. The image sensor includes a lower structure having a photodiode and an interconnection, a passivation layer on the lower structure, a thermo-setting resin layer on the passivation layer, a color filter array on the thermo-setting resin layer, a micro-lens array on the color filter array,... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080073737 - Photoelectric conversion device, method of manufacturing photoelectric conversion device, and image pickup system: s

20080073738 - Light-receiving diode: An improved structure of light-receiving diode is disclosed. The light-receiving diode generally comprises: a support frame on which a transimpedance amplifier and a light-receiving chip having a built-in capacitor are located; and a plurality of pins. The light-receiving chip is attached to the support frame via a conducting spacer, and... Agent: Troxell Law Office PLLC

20080073739 - Electronic component package, electronic component using the package, and method for manufacturing electronic component package: An electronic component package that provides a high shielding performance and that can prevent failures such as short-circuiting with a component contained therein. A package includes a shield case formed of a metal plate and shaped to have a bottom portion, the bottom portion having a through hole; a resin... Agent: Ostrolenk Faber Gerb & Soffen

20080073740 - Backside-illuminated photodetector: The present invention is directed to provide a back illuminated photodetector having a sufficiently small package as well as being capable of suppressing the scattering of to-be-detected light. A back illuminated photodiode 1 comprises an N-type semiconductor substrate 10, a P+-type impurity semiconductor region 11, a recessed portion 12, a... Agent: Drinker Biddle & Reath (dc)

20080073741 - Methods and materials useful for chip stacking, chip and wafer bonding: Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.... Agent: The Webb Law Firm, P.C.

20080073742 - Stacked image package: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the... Agent: John A. Jordan, Esq.

20080073743 - Templated growth of semiconductor nanostructures, related devices and methods: Photodetector arrangements, designs and fabrication techniques are described related to semiconductor nanostructures. Arrangements and techniques are described which utilize a nano-patterned template for growing semiconductor nanostructures and/or heterostructures. Resulting photodetectors are also described.... Agent: Buchanan, Ingersoll & Rooney PC

20080073744 - Photodetector in germanium on silicon: A photodetector structure includes a silicon-based waveguide in which optical signals to be detected travel in a given direction and are confined therein and a germanium layer disposed in contact with a portion of the silicon-based waveguide so that an evanescent tail of the propagating optical signal in the waveguide... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080073745 - High-voltage mos device improvement by forming implantation regions: A high-voltage semiconductor structure includes a high-voltage well region overlying a substrate, an isolation region extending from a top surface of the high-voltage well region into the high-voltage well region, a low-voltage well region having at least a portion underlying and adjoining the isolation region wherein the low-voltage well region... Agent: Slater & Matsil, L.L.P.

20080073746 - Semiconductor device: According to the present invention, there is provided a semiconductor device having a gate field plate structure, which includes a semiconductor substrate; a gate insulation film formed on the semiconductor substrate; a protective insulation film formed on the semiconductor substrate; a gate electrode formed on the gate insulation film; and... Agent: Rabin & Berdo, PC

20080073747 - Electromagnetic shielding using through-silicon vias: An isolation structure for electromagnetic interference includes a semiconductor substrate, a first integrated circuit in the semiconductor substrate, a second integrated circuit in the semiconductor substrate, and an isolation structure in a direct path between the first and the second integrated circuits, wherein the isolation structure comprises a through-silicon via.... Agent: Slater & Matsil, L.L.P.

20080073748 - Dielectric spacers for metal interconnects and method to form the same: Dielectric spacers for a plurality of metal interconnects and a method to form such dielectric spacers are described. In one embodiment, the dielectric spacers are adjacent to neighboring metal interconnects having flared profiles and are discontiguous from one another. In another embodiment, the dielectric spacers provide a region upon which... Agent: Intel/blakely

20080073749 - Antifuse structure having an integrated heating element: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a... Agent: Scully, Scott, Murphy & Presser, P.C.

20080073750 - Semiconductor storage apparatus and method for manufacturing the same: According to an aspect of the present invention, there is provided a semiconductor storage apparatus including: a semiconductor substrate; and a ferroelectric capacitor including: a bottom electrode disposed above the semiconductor substrate, a ferroelectric layer disposed on the bottom electrode, and a top electrode disposed on the ferroelectric layer. The... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080073751 - Memory cell and method of manufacturing thereof: A memory cell includes a substrate, a first electrode disposed over the substrate a resistance element disposed over the first electrode, a second electrode disposed over the resistance element, the second electrode comprising an alloy, the alloy being formed from a first metal layer deposited on the resistance element, a... Agent: Slater & Matsil LLP

20080073752 - Semiconductor apparatus: A semiconductor apparatus includes a semiconductor device formed to a first surface of a semiconductor substrate, a blocking film provided in a first via-hole, the first via-hole formed with a concave shape to the first surface of the semiconductor substrate, a first via line connected to an electrode of the... Agent: Sughrue Mion, PLLC

20080073753 - Test line placement to improve die sawing quality: A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed... Agent: Slater & Matsil, L.L.P.

20080073754 - Coating compositions for photolithography: Underlying coating compositions are provided that comprise one or more resins comprising one or more modified imide groups. These coating compositions are particularly useful as antireflective layers for an overcoated photoresist layer. Preferred systems can be thermally treated to increase hydrophilicity of the composition coating layer to inhibit undesired intermixing... Agent: Peter F. Corless Rohm And Haas Electronic Materials LLC

20080073755 - Semiconductor devices and fabrication methods thereof: Semiconductor devices and fabrication methods thereof. A first dielectric layer with a first conductor line along a first direction is disposed on a semiconductor substrate, wherein the top surface of the first conductor line is lower than the top surface of the first dielectric layer. A second dielectric layer comprising... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080073756 - Module with a shielding and/or heat dissipating element: A module (100) comprises a component (10) and a shielding element (11), which is mounted on a main surface (12) of the component (10) and has a welding contact (13).... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20080073758 - Method and apparatus for directing molding compound flow and resulting semiconductor device packages: Flow diverting structures for preferentially impeding, redirecting or both impeding and redirecting the flow of flowable encapsulant material, such as molding compound, proximate a selected surface or surfaces of a semiconductor die or dice during encapsulation are disclosed. Flow diverting structures may be included in or associated with one or... Agent: Trask Britt, P.C./ Micron Technology

20080073757 - Semiconductor dies and methods and apparatus to mold lock a semiconductor die: Semiconductor dies and methods to mold lock a semiconductor die are disclosed. A disclosed example semiconductor die includes a top surface, a bottom surface, and a plurality of sides joining the top surface and the bottom surface. At least one of the sides includes an interference structure to mold lock... Agent: Texas Instruments Incorporated

20080073759 - Semiconductor package: Provided is a semiconductor package including a high integration semiconductor chip and having a minimum area to be mounted on a circuit board. The semiconductor package includes a semiconductor chip, a plurality of inner leads, and an encapsulant. The plurality of inner leads include upper and bottom surfaces and are... Agent: Marger Johnson & Mccollom, P.C.

20080073760 - Capacitor assembly with shielded connections and method for forming the same: A capacitor assembly (82) is formed on a substrate (20). The capacitor assembly a first conductive plate (38) and a second conductive plate (60) formed over the substrate such that the second conductive plate is separated from the first conductive plate by a distance. A conductive trace (40) is formed... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080073761 - Semiconductor package and stacked semiconductor package: A semiconductor package including at least one semiconductor chip and inner leads may be provided. The semiconductor package may include a semiconductor chip. A plurality of inner leads having upper surfaces and lower surfaces, may be electrically connected to the semiconductor chip, and may be spaced apart from the semiconductor... Agent: Harness, Dickey & Pierce, P.L.C

20080073762 - Semiconductor device package: A lead-exposed semiconductor device package may include a die pad; a semiconductor chip having bonding pads mounted on the die pad; a plurality of leads arranged to be adjacent to at least one edge of the die pad and to electrically connect external to the package; a locking member provided... Agent: Harness, Dickey & Pierce, P.L.C

20080073763 - Semiconductor device and method of manufacturing the same: An object of the present invention is to improve heat dissipation of a semiconductor device, thereby preventing a semiconductor device from being destroyed by heat generation. To this end, provided is a semiconductor device including a lead frame, a semiconductor chip, and an island to which the semiconductor chip is... Agent: Fish & Richardson P.C.

20080073764 - Lead frame having a die stage smaller than a semiconductor device and a semiconductor device using the same: A lead frame has a die stage for mounting a semiconductor chip whose electrodes are electrically connected with leads via bonding wires, wherein they are enclosed in a molded resin, thus producing a semiconductor device. The outline of the die stage is shaped so as to be smaller than the... Agent: Dickstein Shapiro LLP

20080073765 - Ic chip package having automated tolerance compensation: An IC chip package and related method are disclosed. The IC chip package may include a printed circuit board (PCB) coupled to a chip module by a land grid array (LGA) connector, a metal stiffener including a fluid-based pressure compensator contacting an underside of the PCB, and at least two... Agent: Hoffman, Warnick & D'alessandro LLC

20080073766 - System for manufacturing microelectronic, microoptoelectronic or micromechanical devices: The specification teaches a system for manufacturing microelectronic, microoptoelectronic or micromechanical devices (microdevices) in which a contaminant absorption layer improves the life and operation of the microdevice. In an embodiment, a system for manufacturing the devices includes efficiently integrating a getter material in multiple microdevices.... Agent: Technology & Intellectual Property Strategies Group PC (dba Tips Group)

20080073767 - Pressure-contact semiconductor device: A pressure-contact semiconductor device (100) includes thermal buffer plates (2) and main electrode blocks (3) having flanges (4), by which semiconductor substrate (1) having a pair of electrodes is sandwiched, disposed opposed to each side thereof, wherein the semiconductor substrate (1) is sealed in a gastight space by joining the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080073768 - Electronic component device: An electronic component device of the present invention includes: a silicon package unit having a structure in which a through electrode provided to a silicon substrate while an electrode post connected to the through electrode is provided upright on an upper side of the silicon substrate; an electronic component mounted... Agent: Kratz, Quintos & Hanson, LLP

20080073770 - Integrated circuit package system with stacked die: An integrated circuit package system comprising forming a trace frame including: fabricating a sacrificial substrate; forming a first series of bonding pads along a length of the sacrificial substrate; forming a second series of the bonding pads along a width of the sacrificial substrate; forming conductive traces for connecting the... Agent: Law Offices Of Mikio Ishimaru

20080073769 - Semiconductor package and semiconductor device: The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip... Agent: North America Intellectual Property Corporation

20080073771 - Semiconductor package and semiconductor system in package using the same: Disclosed are a semiconductor package and semiconductor system in package using the same. The semiconductor package includes: a printed circuit board (PCB); a semiconductor die disposed on the PCB and having conductive posts formed on an upper surface of the semiconductor die; and a molding formed on the PCB to... Agent: Cha & Reiter, LLC

20080073772 - Stacked semiconductor package and method of manufacturing the same: Provided are highly reliable, high density stacked semiconductor packages including a plurality of semiconductor chips and a method of manufacturing the highly reliable, high density semiconductor package. An embodiment of the stacked semiconductor package includes upper and lower semiconductor packages that are sequentially stacked. The upper and lower semiconductor packages... Agent: Marger Johnson & Mccollom, P.C.

20080073773 - Electronic device and production method: An electronic device and production method is disclosed. One embodiment provides an integrated component, a housing body, and an electrically conductive first layer region arranged outside the housing body.... Agent: Dicke, Billig & Czaja

20080073774 - Chip package and chip package array: A chip package including a multilayer substrate, an adhesive core layer and a chip is provided. The multilayer substrate has a plurality of material layers. The adhesive core layer is disposed on the multilayer substrate. The chip is disposed in the adhesive core layer. The chip has an active surface... Agent: Jianq Chyun Intellectual Property Office

20080073775 - Surface adapting cap with integral adapting material for single and multi chip module assembly: A surface adapting cap with an integrated adapting thermally conductive material on single and multi chip module provides reduced gap tolerance and hence better thermal performance of the semiconductor device which enhances the reliability of the semiconductor device. In one of the embodiments the cap is modified with an integrated,... Agent: Ibm Corporation, T.j. Watson Research Center

20080073776 - Sintered metallic thermal interface materials for microelectronic cooling assemblies: A microelectronic cooling assembly and method for fabricating the same are described. In one example, a microelectronic cooling assembly includes a microelectronic device, a heat spreader, and a thermal interface material (TIM) that thermally joins the microelectronic device and heat spreader, the TIM comprising a sintered metallic nanopaste.... Agent: Intel Corporation C/o Intellevate, LLC

20080073777 - Multiple integrated circuit die package with thermal performance: A multi-die package comprises a heat spreader disposed on a printed circuit substrate, at least one integrated circuit die disposed on a top side of the heat spreader and at least one other integrated circuit die disposed on a bottom side of the heat spreader wherein the dies are connected... Agent: Stephen B. Ackerman Saile Ackerman LLC

20080073778 - Two-way heat extraction from packaged semiconductor chips: One embodiment of the invention is a semiconductor device (500) with a first (500a) and a second (500b) surface, a package including a plastic molding compound (501), and a semiconductor chip (502) inside the package. A first metal sheet (510, 401) covers at least portions of the first package surface... Agent: Texas Instruments Incorporated

20080073779 - Stacked semiconductor package and method of manufacturing the same: Provided are highly reliable, high density stacked semiconductor packages including a plurality of semiconductor chips and a method of manufacturing the stacked semiconductor package. An embodiment of the stacked semiconductor package includes upper and lower semiconductor packages which are sequentially stacked. The upper and lower semiconductor packages include inner leads... Agent: Marger Johnson & Mccollom, P.C.

20080073780 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a semiconductor element including a semiconductor substrate having an element region, a laminated film formed on the semiconductor substrate and including a low dielectric constant insulating film, and a laser-machined groove provided to cut at least the low dielectric constant insulating film. The semiconductor element is... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080073781 - Integrated circuit package system for chip on lead: An integrated circuit package system includes providing an integrated circuit die having planar dimensions; forming a lead extended across one of the planar dimensions of the integrated circuit die; and applying an adhesive layer over the lead of a side opposite the integrated circuit die.... Agent: Law Offices Of Mikio Ishimaru

20080073782 - Semiconductor package comprising alignment members: A semiconductor package comprising alignment members is provided. The semiconductor package includes a semiconductor die, first connection terminals disposed on a first surface of the semiconductor die, and a tape substrate including a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first... Agent: Volentine & Whitt PLLC

20080073783 - Method for forming a bump, semiconductor device and method of fabricating same, semiconductor chip, circuit board, and electronic instrument: A method for forming a bump includes the steps of forming a resist layer so that a through-hole formed therein is located on a pad; and forming a metal layer to be electrically connected to the pad conforming to the shape of the through-hole. The metal layer is formed so... Agent: Harness, Dickey & Pierce, P.L.C

20080073784 - Circuit substrate for preventing warpage and package using the same: In one embodiment, a circuit substrate comprises a substrate; and a warpage preventing pattern disposed on the substrate. The warpage preventing pattern comprises a first pattern at a first corner of the substrate and a second pattern at a second corner of the substrate. The first corner and the second... Agent: Marger Johnson & Mccollom, P.C.

20080073785 - Semiconductor device having sealing film and manufacturing method thereof: A semiconductor device includes a plurality of wiring lines which are provided on an upper side of a semiconductor substrate and which have connection pad portions, Columnar electrodes are provided on the connection pad portions of the wiring lines. A first sealing film is provided around the columnar electrodes on... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080073786 - Semiconductor device and method of manufacturing the same: In a semiconductor device of the present invention, of wires 5a, 5b and 5c which are vertically arranged to connect a plurality of electrodes 3 formed on a major surface of a semiconductor chip 2 and internal electrodes 4 of conductor portions arranged around the semiconductor chip 2, the wires... Agent: Steptoe & Johnson LLP

20080073787 - Method forming metal interconnection filling recessed region using electro-plating technique: A metal (e.g., copper) interconnect and related method of fabrication are disclosed in which the metal interconnect is formed by electro-plating a seed layer formed on a recess in a substrate before a metal layer is electro-plated to fill the recess.... Agent: Volentine & Whitt PLLC

20080073788 - Semiconductor device and method of fabricating the same: A semiconductor device includes a substrate in which a conductive layer is formed; anti-reflective coating layers formed over the conductive layer; and an anti-diffusion layer interposed between the anti-coating layers and the conductive layers.... Agent: Sherr & Nourse, PLLC

20080073789 - Method of identifying and/or programming an integrated circuit: A chip and a method of fabricating the chip for low cost chip identification circuitry. In one embodiment, a method of manufacturing an integrated circuit includes formation of a multi-level metallization structure including a pad level comprising programming pads. A plurality of active devices are formed on a substrate, and... Agent: Ryan, Mason & Lewis, LLP

20080073790 - Method of fabricating a wire bond pad with ni/au metallization: A method for sealing an exposed surface of a wire bond pad with a material that is capable of preventing a possible chemical attack during electroless deposition of Ni/Au pad metallurgy is provided. Specifically, the present invention provides a method whereby a TiN/Ti or TiN/Al cap is used as a... Agent: Scully, Scott, Murphy & Presser, P.C.

20080073791 - Wire pad of semiconductor device: A semiconductor device includes a low-k layer formed over a semiconductor device; a first TEOS film formed over the low-k layer; a SiCN layer formed over the first TEOS film; an undoped silicate glass film formed over the SiCN layer; a nitride film formed over the USG film; a second... Agent: Sherr & Nourse, PLLC

20080073792 - Electronic device and method for production: An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of... Agent: Dicke, Billig & Czaja

20080073793 - Al-ni-based alloy wiring material and element structure using the same: The present invention provides Al—Ni-based wiring material that allows, in a display device including thin film transistors and transparent electrode layers, direct bonding to the transparent electrode layer made of ITO, IZO or the like as well as direct bonding to the semiconductor layer, such as n+-Si.... Agent: Richard S. Roberts

20080073794 - Semiconductor apparatus and fabrication method thereof: A semiconductor device (3) is provided with a first electrode (A), a lead (4) has a second electrode (B), and a metallic film (6) electrically interconnects the first electrode (A) and the second electrode (B), allowing for a more reduced internal resistance, high reliability, and facilitated fabrication.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080073796 - Electrically optimized and structurally protected via structure for high speed signals: An electrically optimized and structurally protected micro via structure for high speed signals in multilayer interconnection substrates is provided. The via structure eliminates the overlap of a contact with the reference planes to thereby reduce the via capacitance and thus, the via impedance mismatch in the via structure. As a... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080073795 - Integrated circuit interconnection devices and methods: Integrated circuit interconnection devices and methods are provided. An interconnection to connect components can comprise a first portion, a second portion, and a joining portion. The first portion can extend from a first component, and the first portion can be made with a single conductor. The second portion can extend... Agent: Troutman Sanders LLP

20080073797 - Semiconductor die module and package and fabricating method of semiconductor package: A semiconductor die module, a semiconductor package, and a fabrication method of the semiconductor package. A method for manufacturing a semiconductor package includes the steps of: preparing a printed circuit board in which a hole is formed to extend through a core, and an insulation layer and a circuit pattern... Agent: Cha & Reiter, LLC

20080073798 - Semiconductor device and manufacturing method thereof: The present invention relates to a semiconductor device including a semiconductor chip encapsulated by an encapsulation resin and a manufacturing method thereof, and an object of the invention is to provide the semiconductor chip and its manufacturing method in which the reduction in size may be attempted. It includes a... Agent: Rankin, Hill & Clark LLP

20080073799 - Mould having nano-scaled holes: A mould includes a base having a first surface and a second surface opposite to the first surface; and a plurality of nano-scaled holes defined through the base. Each nano-scaled hole extends from the first surface to the second surface of the base and is parallel to each other and... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20080073800 - Methods of connecting an antenna to a transponder chip: A transponder chip or chip module in a recess in a substrate, and an antenna wire mounted to the surface of the substrate and having end portions spanning the recess. The end portions are spaced wider than the chip, to allow the chip to be inserted into the recess from... Agent: Gerald E. Linden

20080067487 - Phase change memory device: A phase change memory device comprises an insulating layer and a phase change layer formed on the insulating layer. A phase change layer has a pad portion. The pad portion is formed with at least one slit.... Agent: Sughrue Mion, PLLC

20080067488 - Phase change memory device: A phase change memory device comprises an Insulating layer and a phase change layer formed on the insulating layer. The phase change layer has a plurality of linear portions. The linear portions extend in a first direction are spaced from each other in a second direction perpendicular to the first... Agent: Sughrue Mion, PLLC

20080067486 - Ring heater for a phase change memory device: A ring shaped heater surrounds a chalcogenide region along the length of a cylindrical solid phase portion thereof defining a change phase memory element. The chalcogenide region is formed in a sub-lithographic pore, so that a relatively compact structure is achieved. Furthermore, the ring contact between the heater and the... Agent: Seed Intellectual Property Law Group PLLC

20080067490 - Phase-change memory device having heater electrode with improved heat generation efficiency: A phase-change memory device according to the present invention includes a phase-change layer, a stacked heater electrode electrically connected to the phase-change layer, and a contact plug electrically connected to the stacked heater electrode. The stacked heater electrode includes at least a first electrode portion made of a first electrically... Agent: Mcginn Intellectual Property Law Group, PLLC

20080067492 - Three-dimensional phase-change memory: A three-dimensional phase-change memory array. In one embodiment of the invention, the memory array includes a first plurality of diodes, a second plurality of diodes disposed above the first plurality of diodes, a first plurality phase-change memory elements disposed above the first and second plurality of diodes and a second... Agent: Philip H. Schlazer Energy Conversion Devices, Inc.

20080067495 - Tunnel effect transistors based on silicon nanowires: Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents a nanowire-based TFET with a germanium (Ge) tunnel barrier in an otherwise silicon... Agent: Knobbe Martens Olson & Bear LLP

20080067497 - Light emitting device and manufacturing method thereof: Disclosed are a light emitting device and a manufacturing method thereof. The light emitting device comprises a first conductive semiconductor layer, an active layer on the first conductive semiconductor, a second conductive semiconductor layer on the active layer, and a dot-shaped roughness layer on the second conductive semiconductor layer.... Agent: Birch Stewart Kolasch & Birch

20080067499 - Silicon/germanium superlattice thermal sensor: A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080067505 - Composition for preparing organic insulating film, organic insulating film prepared by using the same and organic thin film transistor comprising the organic insulating film: Disclosed are a composition comprising an organic insulating polymer in which a photo-reactive functional group showing an increased crosslinking degree is introduced into a side-chain, an organic insulating film comprising the composition, an organic thin film transistor (OTFT) comprising the organic insulating film, an electronic device comprising the organic thin... Agent: Harness, Dickey & Pierce, P.L.C

20080067506 - Electro-optical device, electronic apparatus, and method of manufacturing the same: An electro-optical device includes a substrate having a plurality of pixel electrodes thereon, a bank structure formed on the substrate and provided with a plurality of pixel apertures corresponding to the plurality of pixel electrodes, an injection layer formed in each of the plurality of pixel apertures for injecting electrons... Agent: Oliff & Berridge, PLC

20080067502 - Electronic packages with fine particle wetting and non-wetting zones: Spreading or keep out zones may be formed in integrated circuit packages by altering the roughness of package surfaces. The surface roughness can be altered by applying or growing particles having a dimension less than 500 nanometers. Hydrophilic surfaces may be made hemi-wicking and hydrophobic surfaces may be made hemi-wicking... Agent: Trop Pruner & Hu, PC

20080067503 - Insulating organic polymer, organic insulating layer formed using the insulating polymer, and organic thin film transistor comprising the insulating layer: Disclosed is an insulating organic polymer having side chains that enable the formation of a highly hydrophobic insulating layer with decreased surface energy. Decreased surface energy of an organic insulating layer formed using the insulating organic polymer may lead to an increase in the degree of alignment of a semiconductor... Agent: Harness, Dickey & Pierce, P.L.C

20080067504 - Organic thin film transistor comprising phosphate-based self-assembled monolayer and method of manufacturing the same: Disclosed is an organic thin film transistor including a phosphate-based self-assembled monolayer and a method of manufacturing the same. Example embodiments relate to an organic thin film transistor, which may include a single bond type phosphate-based self-assembled monolayer without intermolecular cross-linking, between source/drain electrodes and an organic semiconductor layer, thus... Agent: Harness, Dickey & Pierce, P.L.C

20080067507 - Organic thin-film transistor: An organic thin-film transistor, including a layer exposing a benzene ring, having a surface separation of from 2.8 to 3.0 Å; and an organic semiconductive layer located overlying the layer exposing a benzene ring.... Agent: Cooper & Dunham, LLP

20080067508 - Field-effect transistor and method for manufacturing the same: A method for manufacturing a field-effect transistor includes the steps of forming a source electrode and a drain electrode each containing hydrogen or deuterium; forming an oxide semiconductor layer in which the electrical resistance is decreased if hydrogen or deuterium is added; and, causing hydrogen or deuterium to diffuse from... Agent: Fitzpatrick Cella Harper & Scinto

20080067512 - Array substrate and display apparatus having the same: In an array substrate and a display apparatus, a gate line receives a gate pulse during a present 1H period and a data line receives a pixel voltage having a polarity inverted at every frame. When a thin film transistor is turned on in response to the gate pulse during... Agent: H.c. Park & Associates, PLC

20080067511 - Liquid crystal display: A liquid crystal display includes a substrate, a plurality of pixels including a plurality of switching elements, a plurality of gate lines connected to the switching elements and extending in a row direction, and a gate driver including a circuit portion connected to the gate lines and a wiring portion... Agent: F. Chau & Associates, LLC

20080067510 - Liquid crystal display panel: A liquid crystal display panel including an active device array substrate, a second substrate, a sealant, and a liquid crystal layer is provided. The active device array substrate has a display area and a peripheral area surrounding the display area, and includes a first substrate, pixels, signal lines, floating lines,... Agent: Jianq Chyun Intellectual Property Office

20080067515 - Method of manufacturing laterally crystallized semiconductor layer and method of manufacturing thin film transistor using the same method: Provided are a method of manufacturing a laterally crystallized semiconductor layer and a method of manufacturing a thin film transistor (TFT) using the method. The method of manufacturing the laterally crystallized semiconductor layer comprises: forming a semiconductor layer on a substrate; irradiating laser beams on the semiconductor layer; splitting the... Agent: Cantor Colburn, LLP

20080067517 - Semiconductor device and method for forming the same: A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern... Agent: Lee & Morse, P.C.

20080067518 - Pixel structure and repairing method thereof: The pixel structure and the repairing method of the TFT array substrate are provided. The pixel has a semiconductor electrode which is partially overlapped with a floating metal located in the first conductive layer. Both the data line and the drain electrode have protruded regions partially overlapped with the semiconductor... Agent: Birch Stewart Kolasch & Birch

20080067519 - Display device and method of manufacturing the same: The invention provides a display device having a thin film transistor and a storage capacitor storing a display signal applied to a pixel electrode through this thin film transistor on a substrate, where dielectric strength between electrodes forming the storage capacitor is enhanced for increasing the yield. In the storage... Agent: Morrison & Foerster LLP

20080067521 - Electro-optical device and electronic apparatus: An electro-optical device in which a plurality of thin films are laminated on a substrate and a transistor is formed by a part of the plurality of laminated thin films includes a light-shielding insulating layer that forms a part of the plurality of thin films and is laminated on the... Agent: Advantedge Law Group, LLC

20080067520 - Organic electro-luminescent display and method of fabricating the same: An organic electro-luminescent display and a method of fabricating the same include an organic light emitting diode, a driving transistor which drives the organic light emitting diode, and a switching transistor which controls an operation of the driving transistor, wherein active layers of the switching and driving transistors are crystallized... Agent: Cantor Colburn, LLP

20080067526 - Flexible circuits having improved reliability and thermal dissipation: A flexible circuit that includes mounted electrical components, where bonding wires providing an electrical connection to the electrical components are aligned perpendicularly to the primary plane in which the flexible circuit bends and multiple redundant vias for electrical and thermal connections. The flexible circuit may include an array of light... Agent: Kathy Manke Avago Technologies Limited

20080067531 - Light emitting diode having light diffusion member and method for manufacturing the same: An exemplary light emitting diode (100) includes a light output unit (101), an optical lens (102) and a diffusing layer (103). The optical lens is mounted on the light output unit. The optical lens has a light input surface (1021) facing the light output unit, a recessed top interface (1022)... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20080067530 - Organic laser: A device comprising an organic light emitting layer may be optically pumped to create excited states within the layer. When an electric field is applied across the layer, the excited states may dissociate into geminate polaron pairs within the organic layer. The dissociated states may change back to excitons when... Agent: Kenyon & Kenyon LLP

20080067535 - Side view led package structure: A side view light emitting diode (LED) package structure includes a package housing, a side view LED chip and a thermal conductive member. The side view LED chip is enclosed by the package housing and an emitting direction of the side view LED chip is perpendicular to a thickness direction... Agent: Birch Stewart Kolasch & Birch

20080067538 - Electrode structure of a transistor, and pixel structure and display apparatus comprising the same: An electrode structure of a transistor, and a pixel structure and a display apparatus comprising the electrode structure of the transistor are disclosed. The electrode structure of the transistor comprises a first electrode and a second electrode. The first electrode has at least two first portions and at least one... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080067537 - Support for flip-chip bonding a light emitting chip: In a light emitting device, a light emitting chip (12, 112) includes a stack of semiconductor layers (14) and an electrode (24, 141, 142) disposed on the stack of semiconductor layers. A support (10, 10′, 110, 210) has a generally planar surface (30) supporting the light emitting chip in a... Agent: Fay Sharpe LLP

20080067485 - Increasing adherence of dielectrics to phase change materials: A phase change material is formed over a dielectric material. An impurity is introduced into the dielectric to improve the adherence of said dielectric to said phase change material.... Agent: Trop Pruner & Hu, PC

20080067489 - Snse-based limited reprogrammable cell: Methods and apparatus for providing a memory device that can be programmed a limited number of times. According to exemplary embodiments, a memory device and its method of formation provide a first electrode, a second electrode and a layer of a chalcogenide or germanium comprising material between the first electrode... Agent: Dickstein Shapiro LLP

20080067491 - Phase change material memory device: A lower electrode may be covered by a protective film to reduce the exposure of the lower electrode to subsequent processing steps or the open environment. As a result, materials that may have advantageous properties as lower electrodes may be utilized despite the fact that they may be sensitive to... Agent: Timothy N. Trop Trop, Pruner & Hu, P.C.

20080067494 - Back-gated field emission electron source: A field emitter device consistent with certain embodiments has a substantially planar conductor forming a gate electrode. A conductive stripe forms a cathode on the insulating layer. An insulating layer covers at least a portion of the surface between the cathode and the gate. An anode is positioned above the... Agent: Miller Patent Services

20080067493 - Diamond electron emission cathode,electron emission source,electron microscope,and electron beam exposure device: An object of the present invention is to provide an electron emission cathode and an electron emission source using diamond and having a high brightness and a small energy width that are suitable for electron ray and electron beam devices and vacuum tubes, in particular, electron microscopes and electron beam... Agent: Mcdermott Will & Emery LLP

20080067496 - Universal gates for ising tqft via time-tilted interferometry: Experiments suggest that the mathematically weakest non-abelian TQFT may be physically the most robust. Such TQFT's—the v=5/2 FQHE state in particular—have discrete braid group representations, so one cannot build a universal quantum computer from these alone. Time tilted interferometry provides an extension of the computational power (to universal) within the... Agent: Woodcock Washburn LLP (microsoft Corporation)

20080067498 - Method for forming quantum dot, and quantum semiconductor device and method for fabricating the same: The method for forming a quantum dot according to the present invention comprises the step of forming an oxide in a dot-shape on the surface of a semiconductor substrate 10, the step of removing the oxide to form a concavity 16 in the position from which the oxide has been... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080067500 - Electromagnetic wave detecting element and electromagnetic wave detection device using the same: It is possible to improve the negative resistance characteristic that can be expected when an SNS (superconductor-normal conductor-superconductor) structure is used as a structure unit for series connection. On the top of a first superconducting electrode, a second superconducting electrode is superimposed so as to sandwich an insulation film between... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080067501 - Spin transistor based on the spin-filter effect, and non-volatile memory using spin transistors: A spin transistor comprises a spin injector for injecting, from a first nonmagnetic electrode carriers with a spin parallel to a spin band forming the band edge of a first ferromagnetic barrier layer, to a second nonmagnetic electrode layer, as hot carriers. It also comprises a spin analyzer whereby, due... Agent: Reed Smith LLP Suite 1400

20080067509 - Chip comprising at least one test contact configuration: In a chip (2) comprising a semiconductor body (6) and an integrated circuit (7) formed in the semiconductor body (6) and a passivation layer (14) designed to protect the integrated circuit (7) and a test contact configuration (15), the test contact configuration (15) has a test contact layer (16) lying... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080067513 - Display device: A display device includes a substrate, a gate line formed over the substrate, a first insulating film formed over the substrate and the gate line, a semiconductor film formed over the first insulating film, a drain electrode formed over the semiconductor film, a source electrode formed over the semiconductor film,... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080067514 - Flat panel display device with polycrystalline silicon thin film transistor: The present invention relates to a flat panel display device comprising a polycrystalline silicon thin film transistor and provides a flat panel display device having improved characteristics by having a different number of grain boundaries included in polycrystalline silicon thin film formed in active channel regions of a driving circuit... Agent: H.c. Park & Associates, PLC

20080067516 - Method for manufacturing a tft transistor: An embodiment of a process for manufacturing a TFT transistor on a substrate comprising the steps of: forming an amorphous silicon layer on the substrate, carrying out a crystallization process of the amorphous silicon layer to form a layer of polycrystalline silicon defining an active area of the TFT transistor... Agent: Bryan A. Santarelli Graybeal Jackson Haley LLP

20080067522 - Gallium nitride-based semiconductor stacked structure, production method thereof, and compound semiconductor and light-emitting device each using the stacked structure: A gallium-nitride-based semiconductor stacked structure includes a low-temperature-deposited buffer layer and an active layer. The low-temperature-deposited buffer layer is composed of a Group III nitride material that has been grown at low temperature and includes a single-crystal layer in an as-grown state, the single-crystal layer being present in the vicinity... Agent: Sughrue Mion, PLLC

20080067523 - High electron mobility transistor (hemt) made of layers of group xiii element nitrides and manufacturing method thereof: The invention relates to a new High Electron Mobility Transistor (HEMT), made essentially of layers of Group XIII element(s) nitride(s). Contrary to currently available transistors of this type, the transistor according to the invention is produced on a homosubstrate made of gallium-containing nitride, has no nucleation layer and its buffer... Agent: Smith Patent Office

20080067524 - Micropipe-free silicon carbide and related method of manufacture: Micropipe-free, single crystal, silicon carbide (SiC) and related methods of manufacture are disclosed. The SiC is grown by placing a source material and seed material on a seed holder in a reaction crucible of the sublimation system, wherein constituent components of the sublimation system including the source material, reaction crucible,... Agent: Volentine & Whitt PLLC

20080067525 - Light emitting devices: Light-emitting devices, and related components, systems and methods are disclosed.... Agent: Wolf Greenfield & Sacks, P.C.

20080067527 - Photo-radiation source: A method of manufacturing a photo-radiation source comprising the steps of providing a first planar conductor; disposing a formation of light emitting chips on the first planar conductor, each chip having a cathode and an anode, one of the cathode and anode of each chip being in contact with the... Agent: Michaud-duffy Group LLP

20080067528 - Liquid crystal display device having touch screen function and method of fabricating the same: The present invention relates to an LCD device having a touch screen function. The LCD device of the present invention includes a plurality of gate lines, a plurality of data lines intersecting the gate lines, and a plurality of signal lines that are insulated from and juxtaposed with the data... Agent: Cantor Colburn, LLP

20080067529 - Manufacturing a semiconductor device: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the... Agent: Eric Robinson

20080067533 - Flexible circuit light-emitting structures: Light-emitting structures, and related components, systems, and methods associated therewith are provided. In one embodiment, a light-emitting structure includes at least one LED, a contact bond pad supported by the at least one LED, and a flexible circuit member bonded to the contact bond pad.... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.C.

20080067536 - Image display device and light emission device: An image display device including a light emission section which emits light to an intensity adjusting section and a wavelength conversion section which change the intensity and wavelength of the emitted light. Phosphors and phosphor like materials are employed in wavelength conversion and a liquid crystal is employed for the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080067534 - Light emitting device: This disclosure relates to a light-emitting apparatus comprising a submount, a chip carrier formed on the submount, a light-emitting chip formed on the chip carrier, a reflecting cup formed on the submount and enclosing the light-emitting chip and the chip carrier, and a transparent encapsulating material for encapsulating the light-emitting... Agent: Bacon & Thomas, PLLC

20080067532 - Semiconductor materials and devices: A method of growing semiconductor materials in the Indium, Aluminium, Gallium Nitride (InAlGaN) material system and to devices made therefrom, in particular optical devices in the ultraviolet to green region of the visible spectrum. Certain optical devices, for example Vertical Cavity Surface Emitting Lasers (VCSELs) require great precision in the... Agent: Alston & Bird LLP

20080067539 - Semiconductor light emitting element and method of making the same: A semiconductor light emitting element includes a substrate with upper and lower surfaces, a first nitride semiconductor layer on the upper surface of the substrate, a second nitride semiconductor layer arranged farther from the substrate than the first nitride semiconductor layer is, an active layer between the first and second... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20080067540 - Semiconductor device: A semiconductor device for adequately removing heat generated by a semiconductor element is provided. A semiconductor device 100 is equipped with a substrate 2, having a bottom surface 2b and an element mounting surface 2a which is positioned on the opposite side of bottom surface 2b, and a semiconductor element... Agent: Darby & Darby P.C.

20080067541 - Nitride-based semiconductor device and method of fabricating the same: A method of fabricating a nitride-based semiconductor device capable of reducing contact resistance between a nitrogen face of a nitride-based semiconductor substrate or the like and an electrode is provided. This method of fabricating a nitride-based semiconductor device comprises steps of etching the back surface of a first semiconductor layer... Agent: Mots Law, PLLC

20080067542 - Semiconductor devices: The semiconductor device has a collector electrode, a p+ collector region formed on the collector electrode, an n− drift region formed on the collector region, a p− body region formed on the drift region, and a plurality of n+ emitter regions formed within the body region. The emitter regions are... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080067543 - Method of manufacturing single crystalline gallium nitride thick film: A method of manufacturing a single crystalline gallium nitride (GaN) thick film by using a hydride gas phase epitaxy (HVPE), more particularly, the method of manufacturing c-plane ({0001}) of a single crystalline GaN thick film by using the HVPE. A GaN film is grown on a substrate by providing a... Agent: Mcdermott Will & Emery LLP

20080067545 - Semiconductor device including field effect transistor and method of forming the same: A semiconductor device having a field effect transistor according to example embodiments may include a first semiconductor pattern disposed to fill a first recess region and a second semiconductor pattern disposed to fill a second recess region. The first recess region may be shallower than the second recess region and... Agent: Harness, Dickey & Pierce, P.L.C

20080067544 - Method for producing a strained layer on a substrate and layered structure: The invention relates to a method for producing a strained layer. Said method comprises the following steps: placing the layer on a substrate and straining it, structuring the strained layer, relaxing the layer, producing directional off-sets in the layer to be strained. A layered structure produced in this manner has... Agent: K.f. Ross P.C.

20080067546 - Semiconductor device: A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed... Agent: Mcdermott Will & Emery LLP

20080067547 - Epitaxial nucleation and buffer sequence for via-compatible inas/algasb hemts: A high electron mobility transistor having a first and a second layer with a ternary metamorphic buffer between the first and second layers, the first layer composed of a first material and the second layer composed of a second material, the first and second material having different lattice constants.... Agent: Ketan S. Vakil, Esq. Snell & Wilmer L.L.P.

20080067548 - Iii-nitride power semiconductor device: A III-nitride power semiconductor device that includes a two dimensional electron gas having a low field region under the gate thereof.... Agent: Ostrolenk Faber Gerb & Soffen

20080067549 - Semiconductor component: Semiconductor components such as transistor components, for example, which exist on high Al-containing active layers or layers supplying charge carriers, having a new layer construction providing increased charge carrier mobility.... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20080067550 - Flash memory device using double patterning technology and method of manufacturing the same: Provided are a flash memory device and a method of manufacturing the same. The flash memory device includes strings. Each of the strings has a string selection line, a ground selection line, and an odd number of word lines formed between the string selection line and the ground selection line.... Agent: F. Chau & Associates, LLC

20080067551 - Semiconductor device having pseudo power supply wiring and method of designing the same: Inverters are connected between a pseudo power supply wiring and a main power supply wiring, while inverters are connected between a main power supply wiring VDD and a pseudo power supply wiring. Connected to the sources of transistors are switching areas for switching to the main power supply wiring or... Agent: Foley And Lardner LLP Suite 500

20080067552 - Semiconductor integrated circuit device and method for desiging the same: A semiconductor integrated circuit device has a plurality of design patterns composed of circuit elements or wires formed on a substrate. The respective finished sizes of the plurality of design patterns have a plurality of minimum size values which differ from one design pattern to another depending on the geometric... Agent: Jack Q. Lever, Jr. Mcdermott, Will & Emery

20080067553 - Electromechanical memory array using nanotube ribbons and method for making same: Electromechanical circuits, such as memory cells, and methods for making same are disclosed. The circuits include a structure having electrically conductive traces and supports extending from a surface of the substrate, and nanotube ribbons suspended by the supports that cross the electrically conductive traces, wherein each ribbon comprises one or... Agent: Wilmerhale/boston

20080067554 - Nand flash memory device with 3-dimensionally arranged memory cell transistors: A NAND flash memory device includes a plurality of stacked semiconductor layers, device isolation layer patterns disposed in predetermined regions of each of the plurality of semiconductor layers, the device isolation layers defining active regions, source and drain impurity regions in the active regions, a source line plug structure electrically... Agent: Lee & Morse, P.C.

20080067555 - Self-assembled monolayer based silver switches: The present invention is a two-state switching device based on two electrodes separated by a self-assembled monolayer. At least one of the electrodes may be composed of silver and the other electrode of any electrically conductive material, such as metals, especially gold or platinum. In the high-resistance OFF state, the... Agent: Stevens Davis Miller & Mosher, LLP

20080067556 - X-y address type solid state image pickup device and method of producing the same: In an X-Y address type solid state image pickup device represented by a CMOS image sensor, a back side light reception type pixel structure is adopted in which a wiring layer is provided on one side of a silicon layer including photo-diodes formed therein, and visible light is taken in... Agent: Robert J. Depke Lewis T. Steadman

20080067557 - Mos devices with partial stressor channel: A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate and adjacent the gate electrode. The stressor has a tilted sidewall on... Agent: Slater & Matsil, L.L.P.

20080067558 - Semiconductor device: A semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate having an operation layer on the top surface thereof; a source electrode and a drain electrode disposed on the operation layer; a gate electrode disposed between the source electrode and the drain electrode; and a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080067559 - Heterogeneous integration of low noise amplifiers with power amplifiers or switches: A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier having a substrate wafer selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb), the substrate wafer having a first end and a second end, a conducting layer above the first... Agent: Snell & Wilmer L.L.P.

20080067560 - High voltage depletion layer field effect transistor: In a high voltage junction field effect transistor comprising a first well (11) of a first conductivity type in a substrate (10) of a second conductivity type, comprising a source (14) and a drain (15) in the first well, which are each of the first conductivity type, and comprising a... Agent: Cohen, Pontani, Lieberman & Pavane

20080067561 - Quantum interference device: A quantum interference transistor comprising an source region for emitting electron waves into a vacuum, a drain region for collecting the electron waves, a repeating nanostructure in a region between the source and drain regions for introducing a constant phase shift between a plurality of electron waves, and a gate... Agent: Borealis Technical Limited

20080067563 - Semiconductor device: A semiconductor device includes: a substrate including a compound semiconductor, a semiconductor layer formed on a surface of the substrate, a plurality of gate electrodes formed on the semiconductor layer, a plurality of source electrodes formed on the semiconductor layer, a plurality of drain electrodes formed on the semiconductor layer,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080067562 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a substrate including a compound semiconductor, a semiconductor layer formed on a surface of the substrate and a constituent of the semiconductor layer including a nitride semiconductor different from a constituent of the substrate, a via hole provided in the substrate and configured to extend from... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080067564 - Semiconductor device: A semiconductor device includes: a semiconductor element provided on a semiconductor layer; a light-blocking wall provided around the semiconductor element; and a wiring layer electrically coupled to the semiconductor element and extended from an aperture not having the light-blocking wall to an outside of the light-blocking wall; wherein the wiring... Agent: Harness, Dickey & Pierce, P.L.C

20080067565 - Solid-state imaging device: A solid-state imaging device having an arrangement in which well contact is achieved for each pixel is provided. In the solid-state imaging device, a well contact part is formed in an activation region of a photoelectric conversion portion. The well contact part fixes a well in which the photoelectric conversion... Agent: Robert J. Depke Lewis T. Steadman

20080067566 - Contact structure having conductive oxide layer, ferroelectric random access memory device employing the same and methods of fabricating the same: A ferroelectric memory device may include a substrate, an interlayer insulating layer on the semiconductor substrate, a contact plug penetrating the interlayer insulating layer, the contact plug being formed of a sequentially stacked metal plug and buffer plug, a conductive protection pattern covering the contact plug, the conductive protection pattern... Agent: Lee & Morse, P.C.

20080067567 - Semiconductor device: According to an aspect of the present invention, there is provided a semiconductor device including: a substrate; an insulating film disposed on the substrate; a plug electrode disposed in the insulating film; and a capacitor unit including: a lower electrode that is disposed on the insulating film and that covers... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080067568 - Capacitor with hemispherical silicon-germanium grains and a method for making the same: A method of forming hemispherical silicon-germanium grains within a capacitor which includes providing the semiconductor substrate and forming the capacitor surface in the substrate is provided. The method also includes forming a layer of grained silicon-germanium on the surface of the capacitor. Another aspect of the present invention is seen... Agent: Morrison & Foerster LLP

20080067569 - Memory device with vertical transistor and fabrication method thereof: A method for fabricating a vertical transistor. At least one deep trench is formed in a silicon substrate. A conductive structure and a trench top insulator are successively formed in the deep trench, in which the conductive structure comprises a first doping region and the trench top insulator is below... Agent: Quintero Law Office, PC

20080067570 - Display apparatus: A display apparatus includes scanning lines; signal lines crossing the scanning lines; thin-film transistors connected to the scanning lines and the signal lines; capacitors connected to the thin-film transistors; interlayer insulating films disposed over the scanning lines with the signal lines, the thin-film transistors, and the capacitors disposed between or... Agent: Sonnenschein Nath & Rosenthal LLP

20080067571 - Semiconductor memory device and method of manufacturing the same: A memory device includes a charge trapping layer on a substrate, an insulating layer on the substrate adjacent to the charge trapping layer and exposing an upper surface of the charge trapping layer, a dielectric layer on the exposed charge trapping layer and on the insulating layer, and an electrode... Agent: Lee & Morse, P.C.

20080067572 - Array of non-volatile memory cells with floating gates formed of spacers in substrate trenches: In order to reduce the integrated circuit area that is occupied by an array of a given number of flash memory cells, floating gate charge storage elements are positioned along sidewalls of substrate trenches, preferably being formed of doped polysilicon spacers. An array of dual floating gate memory cells includes... Agent: Davis Wright Tremaine LLP

20080067573 - Stacked memory and method for forming the same: A stacked memory includes at least two semiconductor layers each including a memory cell array. A transistor is formed in a peripheral circuit region of an uppermost semiconductor layer of the at least two semiconductor layers. The transistor is used to operate the memory cell array.... Agent: Lee & Morse, P.C.

20080067576 - Nonvolatile semiconductor memory and manufacturing method thereof: A nonvolatile semiconductor memory according to examples of the present invention comprises a memory cell and a peripheral transistor. The memory cell has a first intergate insulating film having a multilayer structure and provided on a floating gate electrode and an isolation insulating layer. The peripheral transistor has a second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080067574 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a first conductor and a second conductor electrically connected to each other to have the same potential. At least one of the first and second conductors has a fully silicided (FUSI) structure. A step having an overhang is formed at least at part of a boundary... Agent: Mcdermott Will & Emery LLP

20080067575 - Semiconductor device and method of manufacturing the same: A semiconductor device comprising a first insulating film provided on a semiconductor substrate in a cell transistor region, a first conductive film provided on the first insulating film, an inter-electrode insulating film provided on the first conductive film, a second conductive film provided on the inter-electrode insulating film and having... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080067579 - Flash memory device and method for manufacturing the same: A method for manufacturing a flash memory device includes: a) forming a stack gate pattern composed of a tunnel oxide layer, a floating gate, ONO layers, and a control gate on a semiconductor substrate; b) conformably forming a first sidewall oxide layer made of a silicon oxide layer along both... Agent: Sherr & Nourse, PLLC

20080067577 - Multi-trapping layer flash memory cell: A semiconductor device includes a semiconductor substrate, a top gate over the semiconductor substrate, and a stacked gate between the top gate and the semiconductor substrate. The stacked gate includes a first tunneling layer, a first storage layer adjoining the first tunneling layer, and an additional layer adjoining the first... Agent: Slater & Matsil, L.L.P.

20080067578 - Nonvolatile memory having modified channel region interface: The technology relates to nonvolatile memory with a modified channel region interface, such as a raised source and drain or a recessed channel region.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080067580 - Memory device and method of manufacturing the same: In a memory device and a method of manufacturing the memory device, a pair of channel layers included in the memory device may be formed on a sidewall of the sacrificial single crystalline layer pattern located on a protrusion of a semiconductor substrate. Accordingly, an etch damage may be reduced... Agent: Harness, Dickey & Pierce, P.L.C

20080067581 - Non-volatile memory device and method of manufacturing the same: A non-volatile memory device includes a tunnel insulating layer pattern on a channel region of a substrate, a charge trapping layer pattern on the tunnel insulating layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode including a conductive layer pattern on the blocking... Agent: Lee & Morse, P.C.

20080067582 - Semiconductor device and method of manufacturing the semiconductor device: A semiconductor device includes a pair of first source/drain regions disposed on a silicon substrate. A first silicon epitaxial layer pattern defines a gate forming region that exposes the silicon substrate between the pair of first source/drain regions. A first gate insulation layer is disposed on the silicon substrate in... Agent: Lowe Hauptman Ham & Berner, LLP

20080067583 - Nonvolatile semiconductor memory device and manufacturing method thereof: A nonvolatile semiconductor memory device includes a substrate, and a plurality of memory strings, the memory string including a first selection transistor including a first pillar shaped semiconductor formed perpendicular to the substrate, a first gate insulating film formed around the first pillar shaped semiconductor, and a first gate electrode... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080067584 - Inverted-trench grounded-source fet structure with trenched source body short electrode: This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region... Agent: Bo-in Lin

20080067585 - High-voltage bipolar-cmos-dmos integrated circuit devices and modular methods of forming the same: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and... Agent: Patentability Associates

20080067586 - High-voltage bipolar-cmos-dmos integrated circuit devices and modular methods of forming the same: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and... Agent: Patentability Associates

20080067587 - Method for producing an electronic component, method for producing a thyristor, method for producing a drain-extended mos filed-effect transistor, electronic component, drain-extended mos field-effect transistor, electronic component arrangement: In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from... Agent: Brinks Hofer Gilson & Lione Infineon

20080067588 - High-voltage bipolar-cmos-dmos integrated circuit devices and modular methods of forming the same: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and... Agent: Patentability Associates

20080067589 - Transistor having reduced channel dopant fluctuation: According to one exemplary embodiment, a transistor includes a source and a drain separated by a channel. The transistor further includes a gate dielectric layer situated over the channel. The channel is situated in a well formed in a substrate. A pocket implant is not formed between the source and... Agent: Farjami & Farjami LLP

20080067591 - Semiconductor device and method of producing the same: A semiconductor device includes a semiconductor substrate having an insulation layer and a semiconductor layer formed on the insulation layer; a channel area formed in the semiconductor layer; a gate electrode formed on the channel area; a source area formed in the semiconductor layer and having a depth not reaching... Agent: Takeuchi & Kubotera, LLP

20080067593 - Semiconductor device: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below... Agent: Mcdermott Will & Emery LLP

20080067590 - Semiconductor device and manufacturing method of the same: It is an object of the present invention to provide a technology which can form a sidewall without deteriorating device characteristics. A gate insulating film formed of a high dielectric constant film and a polysilicon film are formed on a semiconductor substrate. By patterning the polysilicon film, silicon gate electrodes... Agent: Stanley P. Fisher Reed Smith LLP

20080067592 - Wiring substrate and method of manufacturing thereof, and thin film transistor and method of manufacturing thereof: The invention includes a first step for forming a first conductive layer composed of a high melting point metal to be in contact with an insulating layer; and a second step for forming a second conductive layer by discharging a composition containing a conductive material so as to be in... Agent: Nixon Peabody, LLP

20080067594 - Insulated-gate field-effect thin film transistors: A semiconductor thin film Gated-FET device, comprising: a resistive thin film channel region positioned between a source and a drain region, said channel region comprising a lower level of said source and drain majority carrier type; and a gate region coupled to the channel region by a dielectric region, wherein... Agent: Raminda U. Madurawe

20080067595 - Electrooptical device and electronic equipment having resin film in light emitting region and sealing region: The present invention provides a color filter substrate that can include color filters 12, which are formed in at least a display region and each of which are composed of colored portions, and a light shielding layer on a substrate main body. The light shielding layer can be formed on... Agent: Oliff & Berridge, PLC

20080067596 - Method of fabricating a semiconductor device: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate,... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080067597 - Method of manufacturing a semiconductor device: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the... Agent: Eric Robinson

20080067598 - Layout structure of electrostatic discharge protection circuit and production method thereof: A layout structure of an electrostatic discharge protection circuit and a fabrication process thereof are provided. The electrostatic discharge protection circuit includes a substrate, a protection element and a resistor, wherein a part of or all of the area of the resistor is disposed in the region of the protection... Agent: Jianq Chyun Intellectual Property Office

20080067599 - Semiconductor device and method of manufacturing the same: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080067600 - Storage elements with disguised configurations and methods of using the same: In a first aspect, a first apparatus is provided. The first apparatus is an element of an integrated circuit (IC) having (1) a metal-oxide-semiconductor field-effect transistor (MOSFET) having source/drain diffusion regions; (2) an electrical fuse (eFuse) coupled to the MOSFET such that a portion of the eFuse serves as a... Agent: Ibm Corporation Intellectual Property Law Dept. 917

20080067601 - Esd protection apparatus and circuit thereof: The present invention provides several embodiments with layout patterns for ESD protection. An apparatus with a layout pattern may be configured to protect I/O pads or the power rail. The layout pattern may designed to increase the current paths for ESD stress currents. For example, more rings may be applied.... Agent: Baker & Mckenzie LLP Patent Department

20080067602 - Multi-pad shared current dissipation with heterogenic current protection structures: Current protection in integrated circuit having multiple pads. Different types of current protection structures may be associated with different pads. A common current discharge or charge path may be used to provide current to or draw current from various of these heterogenic current protection structures. Since a common current discharge... Agent: Workman Nydegger

20080067603 - Thin film transistor array panel and method of manufacture: A method of manufacturing a thin film transistor array panel, including: forming gate lines on a substrate; forming a gate insulating layer on the gate lines; forming semiconductor layers on the gate insulating layer; forming data lines and drain electrodes on the semiconductor layers; depositing a passivation layer on the... Agent: Macpherson Kwok Chen & Heid LLP

20080067604 - Field effect transistor arrangement, memory device and methods of forming the same: Sacrificial structures are provided on a substrate. A template fills a space between the sacrificial structures. The sacrificial structures are removed, where openings are formed in the template. A polysilicon layer is deposited in a single continuous deposition process. First portions of the polysilicon layer fill the openings. A second... Agent: Edell, Shapiro & Finnan, LLC

20080067605 - Single well excess current dissipation circuit: A current dissipation circuit that dissipates excess current to or from a circuit node when that monitored circuit node experiences abnormal voltage conditions, rather than having that excess current being dissipated through other protected circuitry. The current dissipation circuit may use single well technology, and may even provide reverse voltage... Agent: Workman Nydegger

20080067606 - Semiconductor device having different metal gate structures: A semiconductor includes a channel region in a semiconductor substrate, a gate dielectric film on the channel region, and a gate on the gate dielectric film. The gate includes a doped metal nitride film, formed from a nitride of a first metal and doped with a second metal which is... Agent: Volentine & Whitt PLLC

20080067607 - Tunnel effect transistors based on elongate monocrystalline nanostructures having a heterostructure: Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents an elongate monocrystalline nanostructure-based TFET with a heterostructure made of a different semiconducting... Agent: Knobbe Martens Olson & Bear LLP

20080067608 - Storage elements with disguised configurations and methods of using the same: In a first aspect, a first apparatus is provided. The first apparatus is an element of an integrated circuit (IC) having (1) a metal-oxide-semiconductor field-effect transistor (MOSFET) having source/drain diffusion regions; (2) an electrical fuse (eFuse) coupled to the MOSFET such that a portion of the eFuse serves as a... Agent: Ibm Corporation, Intellectual Property Law

20080067609 - Semiconductor device including field effct transistor and method of forming the same: A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped with dopants and a metal germanosilicide layer disposed on the... Agent: F. Chau & Associates, LLC

20080067610 - Mask rom and fabricating method thereof: A mask ROM and fabrication method thereof are disclosed, in which a bit line is formed of a conductive material such as polysilicon, by which a device size can be minimized, and by which resistance characteristics are enhanced.... Agent: Mckenna Long & Aldridge LLP

20080067611 - Semiconductor device and manufacturing method thereof: A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region; and a first gate electrode formed on the isolation region and the active region and including a first region on the isolation region. The first region has a pattern width... Agent: Mcdermott Will & Emery LLP

20080067612 - Semiconductor device including nickel alloy silicide layer having uniform thickness and method of manufacturing the same: A semiconductor device including a nickel alloy silicide layer having a uniform thickness includes isolation regions formed in a substrate, gate electrodes respectively formed on the substrate between the isolation regions, source/drain regions respectively formed between the gate electrodes and the isolation regions, spacers formed on lateral surfaces of the... Agent: F. Chau & Associates, LLC

20080067613 - Field effect transistor with raised source/drain fin straps: Therefore, disclosed above are embodiments of a multi-fin field effect transistor structure (e.g., a multi-fin dual-gate FET or tri-gate FET) that provides low resistance strapping of the source/drain regions of the fins, while also maintaining low capacitance to the gate by raising the level of the straps above the level... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080067614 - Metal oxide semiconductor transistor and method for manufacturing the same: A metal oxide semiconductor (MOS) transistor includes a source region having at least one source contact; a drain region having at least one drain contact; and a gate provided between the source region and the drain region, wherein the number of source contacts included in the source region is different... Agent: Townsend And Townsend And Crew, LLP

20080067616 - Semiconductor device: Embodiments relate to a semiconductor device in which a first oxide layer may be formed in a channel area under the gate electrode. An electric field loaded on the gate electrode may be reduced when electrons are implanted from the source to the drain, the acceleration of electrons may be... Agent: Sherr & Nourse, PLLC

20080067615 - Semiconductor device and method for fabricating thereof: A semiconductor device including at least one of: A well region formed by implanting impurities between isolation layers in a semiconductor substrate. A drift region formed at an upper portion of the well region. A gate pattern formed on the semiconductor substrate while overlapping with one side of the drift... Agent: Sherr & Nourse, PLLC

20080067617 - Semiconductor device and manufacturing method thereof: A transistor structure that improves ESD withstand voltages is offered. A high impurity concentration drain layer is formed in a surface of an intermediate impurity concentration drain layer at a location separated from a drain-side end of a gate electrode. And a P-type impurity layer is formed in a surface... Agent: Morrison & Foerster LLP

20080067618 - Nano-piezoelectronics: A semiconducting device includes a substrate, a piezoelectric wire, a structure, a first electrode and a second electrode. The piezoelectric wire has a first end and an opposite second end and is disposed on the substrate. The structure causes the piezoelectric wire to bend in a predetermined manner between the... Agent: Bryan W. Bockhop, Esq. Bockhop & Associates, LLC

20080067619 - Stress sensor for in-situ measurement of package-induced stress in semiconductor devices: A stress sensor is disclosed herein. The stress sensor includes a plurality of carbon nanotubes in a substrate, and first and second contacts electrically connectable with the plurality of carbon nanotubes. Methods of making and using the stress sensor are also disclosed.... Agent: Blakely Sokoloff Taylor & Zafman

20080067620 - Avalanche photodiode: A photodiode designed to capture incident photons includes a stack of at least three superposed layers of semiconductor materials having a first conductivity type The stack includes: an interaction layer designed to interact with incident photons so as to generate photocarriers, a collection layer to collect the photocarriers; a confinement... Agent: Burr & Brown

20080067621 - Image sensor structure and method of fabricating the same: A method for fabricating an image sensor structure is provided. The method of fabricating an image sensor structure comprises a substrate. An image sensor interconnect structure, a separator layer and a patterned electrode layer are formed on the substrate in sequence. The separator layer, not covered by the patterned electrode... Agent: Birch Stewart Kolasch & Birch

20080067622 - High density photodiodes: The present invention is a front-side contact, back-side illuminated (FSC-BSL) photodiode arrays and front-side illuminated, back-side contact (FSL-BSC) photodiode arrays having improved characteristics, including high production throughput, low-cost manufacturing via implementation of batch processing techniques; uniform, as well as high, photocurrent density owing to presence of a large continuous homogeneous,... Agent: Patentmetrix

20080067623 - Lateral silicided diodes: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may... Agent: Schmeiser, Olsen & Watts

20080067624 - Lateral high-voltage devices with optimum variation lateral flux by using field plate: A semiconductor lateral voltage-sustaining region and devices based thereupon. The voltage-sustaining region is made by using the Metal-Insulator-Semiconductor capacitance formed by terrace field plate to emit or to absorb electric flux on the semiconductor surface, so that the effective electric flux density emitted from the semiconductor surface to the substrate... Agent: Morgan & Finnegan, L.L.P.

20080067625 - Semiconductor device: An improved semiconductor device having a gate electrode buried in a trench that a short circuit is hardly generated between a gate electrode and a source electrode at a termination of the gate electrode. A trench is formed in a semiconductor substrate. A gate electrode and a buried insulating film... Agent: Mcginn Intellectual Property Law Group, PLLC

20080067626 - Method for fabricating a trench structure, and a semiconductor arrangement comprising a trench structure: A semiconductor device, in which a first trench section is produced proceeding from a surface of a semiconductor body into the semiconductor body. A semiconductor layer is produced above the surface and above the first trench section. A further trench section is produced in the semiconductor layer in such a... Agent: Dicke, Billig & Czaja

20080067627 - Fuse structure and method for manufacturing same: A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first... Agent: Slater & Matsil LLP

20080067628 - Techniques for providing decoupling capacitance: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mote vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or... Agent: Ryan, Mason & Lewis, LLP

20080067629 - Electrical fuse having resistor materials of different thermal stability: An electrical fuse has a substrate and a resistor. The resistor has a first area and a second area embedded in the first area. The first area is formed of a first material and the second area is formed of a second material having a lower thermal stability than that... Agent: Banner & Witcoff, Ltd.

20080067631 - Creating increased mobility in a bipolar device: The mobility of charge carriers in a bipolar (BJT) device is increased by creating compressive strain in the device to increase mobility of electrons in the device, and creating tensile strain in the device to increase mobility of holes in the device. The compressive and tensile strain are created by... Agent: International Business Machines Corporation Dept. 18g

20080067630 - Method for producing a composite material, associated composite material and associated semiconductor circuit arrangements: A method for producing a composite material, associated composite material and associated semiconductor circuit arrangements is disclosed. A plurality of first electrically conducting material particles are applied to a carrier substrate and a second electrically conducting material is galvanically deposited on a surface of the first material particles in such... Agent: Slater & Matsil LLP

20080067632 - Em rectifying antenna suitable for use in conjunction with a natural breakdown device: A rectenna capable of power conversion from electromagnetic (EM) waves of high frequencies is provided. In one embodiment, a rectenna element generates currents from two sources—based upon the power of the incident EM wave and from an n-type semiconductor, or another electron source attached to a maximum voltage point of... Agent: Macpherson Kwok Chen & Heid LLP

20080067633 - Semiconductor device and manufacturing method for the same: A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region including second impurity atoms, provided shallower than the first diffusion region from a... Agent: Foley And Lardner LLP Suite 500

20080067635 - Chip-mounted film package: A chip-mounted film package includes a base film, an effective film package defined on the base film by a cutting line, a driving chip mounted on the effective film package, a plurality of input pads arranged on an input area of the effective film package and connected to the driving... Agent: Morgan Lewis & Bockius LLP

20080067634 - Reduced footprint packaged microelectronic components and methods for manufacturing such microelectronic components: The present disclosure describes microfeature workpieces, microelectronic component packages, and methods of forming microelectronic components and microelectronic component packages. In one particular example, a microelectronic component package includes a substrate and a microelectronic component that has a first surface with a surface area greater than that of a second surface.... Agent: Perkins Coie LLP Patent-sea

20080067636 - Insulating film and semiconductor device using this film: An insulating film includes a first metal, oxygen, fluorine and one of a second metal or nitrogen, and satisfies {k×[X]−[F]}/2≦8.4 atomic %, wherein the fluorine amount [F], the one element amount [X], and a valence number difference k between the first and second metals or between oxygen and nitrogen.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080067637 - Simultaneous bidirectional cable interface: A cable connection with at least one cable as a wire conducted signal interconnection between two cables module circuits connected to respective ends of the cable connection. Conductors of the cable may be directly and permanent electrical connected at each end to the respective contacts at the respective cable module... Agent: Banner & Witcoff, Ltd.

20080067638 - Chip-scale packaging leadframe for memory chip: A chip-scale packaging leadframe for a memory chip is provided, where the external leads of at least a pair of the VDD leads and at least a pair of the VSS leads are arranged on two parallel and opposing sides, namely, the first side and the third side, respectively, while... Agent: Birch Stewart Kolasch & Birch

20080067639 - Integrated circuit package system with encapsulation lock: An integrated circuit package system is provided including forming a paddle having a depression from a paddle top surface and an external interconnect, forming a lead tip and a lead body of the external interconnect, connecting a device over the paddle top surface and the external interconnect, and filling a... Agent: Law Offices Of Mikio Ishimaru

20080067640 - Integrated circuit package system with encapsulation lock: An integrated circuit package system is provided including forming an external interconnect and a tie bar, forming a lead tip and a lead body of the external interconnect, forming a hole in the external interconnect, forming a slot in the tie bar, connecting an integrated circuit die and the external... Agent: Law Offices Of Mikio Ishimaru

20080067641 - Package semiconductor and fabrication method thereof: A package structure of semiconductor includes a lead frame, at least one chip, a controlling component and a passive component. Wherein, the controlling component and the chip are configured on the die pad of the lead frame, and encapsulating glue is encapsulated the lead frame, the chip and controlling component... Agent: Rosenberg, Klein & Lee

20080067643 - Semiconductor device and method of manufacturing the same: In this invention, it is possible to improve the semiconductor device manufacturing yield. In a leadless package type semiconductor device manufacturing process, there is used a press frame wherein a front end portion each lead is subjected to a coining work. A semiconductor chip-side front end portion of the lead... Agent: Miles & Stockbridge PC

20080067644 - Microelectronic component assemblies and microelectronic component lead frame structures: The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead frame structure may include a set of leads extending in a first direction and a dam bar. Each of the leads may have an outer length and... Agent: Perkins Coie LLP Patent-sea

20080067642 - Packaged microelectronic components: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be... Agent: Perkins Coie LLP Patent-sea

20080067645 - Heat spreader for semiconductor package: A heat spreader (50) for a semiconductor package (100) includes a heat dissipating portion (52) having a recessed periphery (54). A thermosetting resin (58) is disposed in the recessed periphery (54). The heat spreader (50) may include a heat absorbing portion (56) coupled to the heat dissipating portion (52).... Agent: Freescale Semiconductor, Inc. Law Department

20080067648 - Locking feature and method for manufacturing transfer molded ic packages: The invention discloses integrated circuits (ICs), molded IC packages, and to leadframe arrays, package arrays and methods for their manufacture. Leadframe arrays and package arrays used for the manufacture of IC packages by transfer molding processes include a locking feature adapted for encapsulation. The locking feature is situated in a... Agent: Texas Instruments Incorporated

20080067647 - Semiconductor device: A semiconductor device comprises: a semiconductor chip that is sealed in a package; and a lead that is connected to a power supply voltage source, wherein the semiconductor chip includes a boost converter including: a switch that controls a connection between a first terminal connected to the lead and a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080067646 - Semiconductor leadframe for uniform mold compound flow: A semiconductor device (400) with a plastic package (401) having on its surface (401a) a mark (402) identifying the location, where the runner for the molding compound was broken off. The device further exhibits a leadframe with a pad, which has a planar area (403) and a tab (404). The... Agent: Texas Instruments Incorporated

20080067649 - Semiconductor device, lead-frame product used for the same and method for manufacturing the same: A semiconductor device includes a semiconductor element; a group of back-inner terminals coupled with the semiconductor element through bonding wires and arranged in an area array shape so as to be exposed inside of the bottom; a group of back-outer terminals arranged outside the group of back-inner terminals; a group... Agent: Greenblum & Bernstein, P.L.C

20080067650 - Electronic component package with emi shielding: An electronic component package having an EMI shielded space is disclosed. The package comprises a substrate having an electronic component located on its surface and a conductive enclosure having a top and downwardly extending sides enclosing the component and defining a shielded space. A vent opening is provided through the... Agent: Wells St. John P.s.

20080067652 - Integrated mems packaging: A micro-electromechanical systems (MEMS) package that includes a substrate onto which is disposed or otherwise formed an active MEMS device, a first barrier wall for preventing sealant from contaminating the MEMS device, a second barrier wall for preventing sealant from contaminating unintended areas of the substrate, and a cap for... Agent: Ogilvy Renault LLP

20080067651 - Method and apparatus for prevention of solder corrosion utilizing forced air: Disclosed is a multi-chip module with solder corrosion prevention including one or more chips connected to a substrate by soldering, the substrate situated on a printed circuit board. The multi-chip module also includes a molecular sieve desiccant chamber containing a quantity of molecular sieve desiccant and a first cover to... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080067654 - Electronic component package and electronic component device: An electronic component package includes, a die pad on which an electronic component is mounted, a radiation plate disposed to be connected to part of the die pad and bent downward, a plurality of leads disposed side by side on a periphery of the die pad, each lead composed of... Agent: Kratz, Quintos & Hanson, LLP

20080067653 - Reduction in thickness of semiconductor component on substrate: It is an object to reduce a thickness of a semiconductor component (chip) on a substrate to a predetermined thickness regardless of a variation in thickness of a substrate in a semiconductor product. In a semiconductor product mounted on a base plate, a surface of a semiconductor component on a... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20080067655 - Device comprising an encapsulated microsystem and production method thereof:

20080067657 - Integrated circuit devices with multi-dimensional pad structures: Integrated circuits with multi-dimensional pad structures are provided. An exemplary embodiment of an integrated circuit device with multi-dimensional pad structures comprises an integrated circuit (IC) stack structure comprising a plurality of device layers, wherein one of the devices comprise a first pad exposed by an edge surface thereof.... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080067661 - Resin wiring substrate, and semiconductor device and laminated semiconductor device using the same: On a surface of a resin base material (11), a first resin coating film (19) having a larger thickness and a larger area than a second resin coating film (20) formed on the other surface of the resin base material (11) is continuously formed. The second resin coating film (20)... Agent: Steptoe & Johnson LLP

20080067660 - Semiconductor device package: A semiconductor device package includes a semiconductor chip having bonding pads; a printed circuit board (PCB) including an insulation pattern with a groove and bonding electrodes corresponding to the bonding pads, the groove corresponding to the edge of the semiconductor chip and being formed to partially expose a lower portion... Agent: Marger Johnson & Mccollom, P.C.

20080067658 - Stacked die semiconductor package: A stacked die semiconductor package comprises a first integrated circuit chip, a first circuit tape coupled to the first integrated circuit chip, a second integrated circuit chip coupled to the first circuit tape, and at least one component coupled to the first circuit tape. The at least one component may... Agent: Klarquist Sparkman, LLP

20080067656 - Stacked multi-chip package with emi shielding: A stacked multi-chip package with an EMI shielded component has first and second substrates mounted together by a grid array of metallic connecting nodes, such as a solder Ball Grid Array. Each substrate has a conductive plane associated with it. An electronic component is mounted between the first and second... Agent: Wells St. John P.s.

20080067659 - Stacked semiconductor package, method of fabrication, and method of wire-bond monitoring: A stacked semiconductor package may include a wiring substrate. A first semiconductor chip may be disposed on the wiring substrate and wire-bonded to the wiring substrate. An interposer chip may be disposed on the wiring substrate and sire bonded to the wiring substrate. The interposer chip may include a circuit... Agent: Harness, Dickey & Pierce, P.L.C

20080067662 - Modularized die stacking system and method: An IC die and a flexible circuit structure are integrated into a lower stack element that can be stacked with either further integrated lower stack element iterations or with pre-packaged ICs in any of a variety of package types. A die is positioned above the surface of portions of a... Agent: Fish & Richardson P.C.

20080067664 - Cap wafer, semiconductor chip having the same, and fabrication method thereof: A cap wafer, fabrication method, and a semiconductor chip are provided. The cap wafer includes a cap wafer substrate; a penetrated electrode formed to penetrate the cap wafer substrate; and an electrode pad connected with a lower portion of the penetrated electrode on a lower surface of the cap wafer... Agent: Sughrue Mion, PLLC

20080067663 - Wafer level chip package and a method of fabricating thereof: Wafer level chip packages including risers having sloped sidewalls and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies.... Agent: Tessera Lerner David Et Al.

20080067665 - Via structure: In one embodiment, the invention may include a semiconductor package substrate with a plated-through hole (PTH) via. One or more conduits for transmitting signals can be located in the PTH via. The PTH via may shield the signals in the conduits from environmental noise (e.g., EMI). Other embodiments are described... Agent: Trop Pruner & Hu, PC

20080067666 - Circuit board structure with embedded semiconductor chip and method for fabricating the same: A circuit board structure having an embedded semiconductor chip and a method for fabricating the same are disclosed. The circuit board structure includes: a carrier board formed with at least one through hole; a semiconductor chip received in the through hole of the carrier board, the semiconductor chip having an... Agent: Sawyer Law Group LLP

20080067667 - Semiconductor device with a semiconductor chip stack and plastic housing, and methods for producing the same: The invention relates to a semiconductor device (1) comprising a semiconductor chip stack (2) and a plastic housing (3), and to methods for producing the semiconductor device (1). The semiconductor device (1) is constructed on a device carrier (4), on which a first semiconductor chip (5) is fixed by its... Agent: Edell , Shapiro & Finnan , LLC

20080067668 - Microelectronic package, method of manufacturing same, and system containing same: A microelectronic package includes a substrate (110), a die (120) electrically connected to the substrate, and a heat dissipation device (130) coupled to the die. The heat dissipation device includes a capacitor (250, 310). In one embodiment the heat dissipation device is a microchannel having a base (131) and a... Agent: Intel Corporation C/o Intellevate, LLC

20080067669 - Systems, devices and methods for controlling thermal interface thickness in a semiconductor die package: Disclosed are various embodiments of systems, devices and methods for controlling the thickness of a thermal interface layer in a semiconductor die package. In one embodiment, spherical inclusions of at least a first substantially uniform diameter are suspended in a thermal material, which is then dispensed or metered onto the... Agent: Kathy Manke Avago Technologies Limited

20080067670 - Underfill film having thermally conductive sheet: An underfill film for an electronic device includes a thermally conductive sheet. The electronic device may include a printed circuit board, an electrical component, an underfill, and the thermally conductive sheet. The underfill is situated between the circuit board and the component. The thermally conductive sheet is situated within the... Agent: Law Offices Of Michael Dryja

20080067671 - Semiconductor device and method for manufacturing the same: After a semiconductor chip is cut out, an In-10 atom % Ag pellet is placed on a metal film. Next, an epoxy sheet on a stiffener is stuck to a ceramic substrate. At this time, the In alloy pellet is sandwiched between a central protrusion portion and the metal film.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080067672 - Semiconductor device and method for fabricating the same: A semiconductor device with a structure having superior heat sink characteristics. A first heat sink member is located over a wiring board by using an adhesive material. A semiconductor element is stuck over the first heat sink member by using an adhesive material. The semiconductor element and electrodes located over... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080067673 - Semiconductor device: A semiconductor device comprises: a semiconductor element; a mounting substrate with the semiconductor element mounted thereon; a first high thermal conductivity member formed on a surface of the mounting substrate; and a first cooling member thermally connected to at least a part of the first high thermal conductivity member. The... Agent: Foley And Lardner LLP Suite 500

20080067674 - System in package (sip) integrated circuit and packaging method thereof: The present invention discloses a system in package (SIP) integrated circuit and a packaging method thereof. The SIP integrated circuit includes one or more first block dices produced by a first process and one or more second block dices produced by a second process. The first block dices are electrically... Agent: J C Patents, Inc.

20080067675 - Castellation wafer level packaging of integrated circuit chips: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When... Agent: Ropes & Gray LLP Patent Docketing 39/361

20080067676 - Electrical interconnection structure formation: An electrical interconnection structure. The electrical structure comprises a substrate comprising electrically conductive pads and a first dielectric layer over the substrate and the electrically conductive pads. The first dielectric layer comprises vias. A metallic layer is formed over the first dielectric layer and within the vias. A second dielectric... Agent: Schmeiser, Olsen & Watts

20080067677 - Structure and manufacturing method of a chip scale package: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip... Agent: Saile Ackerman LLC

20080067678 - Semiconductor devices having contact holes including protrusions exposing contact pads and methods of fabricating the same: Semiconductor devices are provided including a semiconductor substrate and a first interlayer insulating layer on the semiconductor substrate. A contact pad is provided in the first interlayer insulating layer and a second insulating layer is provided on the first interlayer insulating layer. A contact hole is provided in the second... Agent: Myers Bigel Sibley & Sajovec

20080067680 - Semiconductor device and fabrication process thereof: A semiconductor device includes a first interconnection pattern embedded in a first insulation film, a second insulation film covering the first interconnection pattern over the first insulation film, an interconnection trench formed in an upper part of the second insulation film, a via-hole extending downward from the interconnection trench at... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080067679 - Semiconductor device and method for manufacturing the same, and processing liquid: A semiconductor device has interconnects protected with an alloy film having a minimum thickness necessary for producing the effect of preventing diffusion of oxygen, copper, etc., formed more uniformly over an entire surface of a substrate with less dependency to the interconnect pattern of the substrate. The semiconductor device includes,... Agent: Wenderoth, Lind & Ponack, L.L.P.

20080067681 - Interconnection structure and manufacturing method thereof: An interconnection structure is provided. The interconnection structure includes a substrate, a conductive barrier layer, a dielectric layer and a carbon nanotube. A conductive region is disposed in the substrate. The conductive barrier layer is disposed over the conductive region and the conductive barrier layer includes iron, cobalt or nickel.... Agent: J C Patents, Inc.

20080067682 - Bonding pad for contacting a device: A bonding pad on a substrate has a first metal structure establishing an electrical connection between a device and a bonding area, and a second metal structure arranged at the bonding area. The first metal structure extends, within the bonding area, at least over part of the bonding area between... Agent: Slater & Matsil LLP

20080067683 - Ta-tan selective removal process for integrated device fabrication: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080067684 - Semiconductor device: A semiconductor device including at least one conductive structure is provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal salicide layer and a protection layer. The refractory metal salicide layer is disposed over the silicon-containing conductive layer. The protection layer is disposed over the refractory metal salicide... Agent: Jianq Chyun Intellectual Property Office

20080067685 - Semiconductor device manufacturing method: A semiconductor device manufacturing method includes forming a conductive layer pattern on a semiconductor substrate, forming a seed layer having a high silicon content ratio on the conductive layer pattern, and forming an interlayer dielectric to bury the conductive layer pattern on the seed layer.... Agent: Marshall, Gerstein & Borun LLP

20080067687 - Pad over active circuit system and method with meshed support structure: An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incurred during a bonding process,... Agent: Zilka-kotab, PC

20080067686 - Post passivation interconnection schemes on top of ic chip: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin

20080067689 - Deep via construction for a semiconductor device and a method of manufacturing same: An integrated circuit semiconductor device comprises a substrate, a deep via within the substrate, a metal fill located within the deep via and defining an upper surface, and an interconnect wiring. The contact area electrically connects the metal fill to the interconnect wiring, the contact area being located laterally of... Agent: Coats & Bennett, PLLC

20080067688 - Power-via structure for integration in advanced logic/smart-power technologies: A via structure is disclosed for use in a multi-layered semiconductor device, for forming electrical contacts between prescribed layers of the vertically aligned structures. The via structures include a plurality of adjacent frame shaped hole structures which extend between the prescribed layers of the device, and which are filled with... Agent: Brinks Hofer Gilson & Lione Infineon

20080067690 - Semiconductor device: A semiconductor device includes a seal ring formed on an outer circumference of an element forming region when seen from the top in a multilayer interconnect structure formed on a silicon layer, and dummy metal structures formed on a further outer circumference of the seal ring. The more inner circumference... Agent: Sughrue Mion, PLLC

20080067692 - Semiconductor devices having contact pad protection for reduced electrical failures and methods of fabricating the same: A semiconductor device includes contact pads formed in a first interlayer insulating layer on a semiconductor substrate, contact pad protecting patterns covering edges of a surface of the contact pads, and conductive lines positioned on a second interlayer insulating layer covering the contact pad protecting patterns and selectively connected to... Agent: Myers Bigel Sibley & Sajovec

20080067691 - Transistor structure and control unit comprising the same: A transistor structure and a control unit comprising the same transistor structure for use with the drive circuit of a liquid crystal display (LCD) are provided. The transistor structure comprises a first conductive layer, a second conductive layer, and a top gate to form a reinforced capacitance thereamong, thereby, significantly... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080067693 - Post passivation interconnection schemes on top of ic chip: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin

20080067694 - Post passivation interconnection schemes on top of ic chip: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin

20080067696 - Method and apparatus for prevention of solder corrosion: Disclosed a multi-chip module with solder corrosion prevention including one or more chips connected to a substrate by soldering, the substrate disposed on a printed circuit board. The multi-chip module also includes a quantity of molecular sieve desiccant, and a first cover to contain the one or more chips, the... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080067695 - Semiconductor assembly with component attached on die back side: One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal routes being attached to the die... Agent: Klarquist Sparkman, LLP

20080067697 - Integrated circuit wire patterns including integral plug portions and methods of fabricating the same: An integrated circuit device includes a substrate including a trench therein and a conductive plug wire pattern in the trench. The conductive plug wire pattern includes a recessed portion that exposes portions of opposing sidewalls of the trench, and an integral plug portion that protrudes from a surface of the... Agent: Myers Bigel Sibley & Sajovec

20080067698 - Integrated circuit package system with encapsulation lock: An integrated circuit package system is provided including forming an external interconnect having a lead tip and a lead body, forming a recess in the lead body from a lead body top surface, connecting an integrated circuit die and the external interconnect, and molding the external interconnect with the recess... Agent: Law Offices Of Mikio Ishimaru

20080067699 - Semiconductor apparatus and method of producing the same: With a semiconductor apparatus package of the present invention and a method of producing the semiconductor apparatus package, the semiconductor apparatus package includes a circuit board and a semiconductor device sealed with sealing resin. The circuit board has a groove in a section of a surface of the circuit board.... Agent: Nixon & Vanderhye, PC

20080061282 - Semiconductor device and method of producing the same: A phase change memory includes a sidewall insulation film and a heater electrode which are formed in a contact hole formed in an interlayer insulation film on a lower electrode. The heater electrode has a recessed structure. In a recessed area surrounded by the sidewall insulation film, the heater electrode... Agent: Sughrue Mion, PLLC

20080061284 - Nanowire mosfet with doped epitaxial contacts for source and drain: A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.... Agent: Scully, Scott, Murphy & Presser, P.C.

20080061285 - Metal layer inducing strain in silicon: A metal layer, especially a metal compound, induces strain into a gate channel of a MOS transistor. Compressive strain of over 4 GPa is available from sputter deposited TiN. The amount of strain can be controlled at least up to 11 GPa, for example, by wafer biasing. The compressive strain... Agent: Law Offices Of Charles Guenzer Attn: Applied Materials, Inc.

20080061287 - Polyacene compound and organic semiconductor thin film: The present invention provides an organic semiconductor material which exhibits a high mobility, and excellent solubility in solvents and oxidation resistance. The present invention also provides an organic semiconductor thin film exhibiting a high mobility, and an organic semiconductor device exhibiting excellent electronic characteristics. A transistor structure is formed by... Agent: Birch Stewart Kolasch & Birch

20080061288 - Wiring pattern, electronic device, organic semiconductor device, layered wiring pattern, and layered wiring substrate using the wiring pattern: A wiring pattern is disclosed including: a variable wettability layer including a material whose critical surface tension changes in response to energy provided thereto, the wettability changing layer including a high surface energy part exhibiting a high critical surface tension and a low surface energy part exhibiting low critical surface... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080061291 - Semiconductor device for measuring an overlay error, method for measuring an overlay error, lithographic apparatus and device manufacturing method: A semiconductor device for determining an overlay error on a semiconductor substrate includes a first and a second transistor. Each transistor includes two diffusion regions associated with a gate, the diffusion regions of each transistor being arranged in a first direction. The second transistor is arranged adjacent to the first... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20080061295 - Tft-lcd array substrate and method for manufacturing the same: A TFT-LCD array substrate and a method for manufacturing the same are disclosed. In the TFT-LCD array substrate, a first insulating layer, a semiconductor layer, and an ohmic contact layer are formed sequentially on the gate line and the gate electrode, and the ohmic contact layer is formed on the... Agent: Hasse & Nesbitt LLC

20080061297 - Substrates and methods for fabricating the same: An embodiment of the invention provides a substrate. The substrate comprises a single crystal substrate. An epitaxial buffer film is on the single crystal substrate. An epitaxial ZnGa2O4 is on the epitaxial buffer film.... Agent: Quintero Law Office, PC

20080061302 - Light emitting diode and method of fabricating the same: A light emitting diode comprises an N-type semiconductor layer comprising a horizontal lattice defect layer, an active layer on the N-type semiconductor layer, and a P-type semiconductor layer on the active layer.... Agent: Birch Stewart Kolasch & Birch

20080061304 - Semiconductor light emitting device: A semiconductor light emitting device for emission of light having a predetermined bandwidth in a primary direction of emission includes a light generating region for the generation of light; and a 1-dimensional photonic crystal structure having a photonic bandgap covering at least a segment of said bandwidth. The 1-dimensional photonic... Agent: Buchanan, Ingersoll & Rooney PC

20080061305 - Dual view display panel: Provided is a dual view display panel including: a first vertical cell line, a second vertical cell line, a third vertical cell line, and a fourth vertical cell line. Each of the first and fourth vertical cell lines have a red cell, a blue cell and a green cell that... Agent: Robert E. Bushnell

20080061306 - Semiconductor light emitting device: A semiconductor light emitting device includes a multi-layer stack of materials including a layer of p-doped material, a layer of n-doped material, and a light generating region therebetween; a first thermal conduction path between the light generating region and the exterior of the device; and a second thermal conduction path... Agent: Buchanan, Ingersoll & Rooney PC

20080061308 - Semiconductor light emitting device and method of fabricating the same: A semiconductor light emitting device comprises a first electrode contact layer, an active layer on the first electrode contact layer, a second electrode contact layer on the active layer, and a first roughness layer on/under at least one of the first and second electrode contact layers.... Agent: Birch Stewart Kolasch & Birch

20080061310 - Light emitting diode device, and manufacture and use thereof: A light emitting diode device includes a multi-layer stack of materials including a p-layer, a n-layer, and a light generating region for emission of light in a primary emission direction towards one of the p- and n-layers; a substantially transparent layer located at or adjacent said one of the p-... Agent: Buchanan, Ingersoll & Rooney PC

20080061309 - Semiconductor device with under-filled heat extractor: Structure (40, 61-13, 61-15, 61-18, 61-19) and method (60-5 . . . 60-19, 100, 200) are provided for a semiconductor device (40, 61-13, 61-15, 61-18, 61-19) with under-filled heat extractor(s) (46, 46′, 78, 78′). The device (40, 61-13, 61-15, 61-18, 61-19) comprises a substrate (48, 72) with upper (37) and... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080061314 - Light emitting device with high heat-dissipating capability: A light emitting device includes: a heat dissipating unit including a metallic first heat sink having a chip-mounting area, a thermally conductive bonding layer, and a metallic second heat sink overlapping and attached to the first heat sink through the bonding layer such that the bonding layer is sandwiched between... Agent: Christie, Parker & Hale, LLP

20080061315 - Nitride semiconductor light-emitting element and method of manufacturing the same: There is provided a nitride semiconductor light-emitting element including a transparent conductor, a first conductivity-type nitride semiconductor layer, a light-emitting layer, and a second conductivity-type nitride semiconductor layer, the first conductivity-type nitride semiconductor layer, the light-emitting layer, and the second conductivity-type nitride semiconductor layer being successively stacked on the transparent... Agent: Morrison & Foerster LLP

20080061313 - Photosensitive chip package: A photosensitive chip package includes a substrate, a photosensitive chip bonded on the substrate and having a photo-active zone and a photo-inactive zone surrounding the photo-active zone, a plurality of bonding wires electrically connected with the photosensitive chip and the substrate, and an encapsulant covering the photo-inactive zone of the... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080061312 - Underfill for light emitting device: A light emitting chip is disposed on a support surface. A plurality of bonding bumps are disposed in a gap between the light emitting chip and the support surface. The plurality of bonding bumps provide at least one electrical power input path to the light emitting chip. An underfill comprising... Agent: Fay Sharpe LLP

20080061283 - Memory cell array with low resistance common source and high current drivability: In the present resistive memory array, included are a substrate, a plurality of source regions in the substrate, and a conductor connecting the plurality of source regions, the conductor being positioned adjacent to the substrate to form, with the plurality of source regions, a common source. I one embodiment, the... Agent: Paul J. Winters

20080061286 - Liquid metal contact as possible element for thermotunneling: The use of liquid metal contacts for devices based on thermotunneling has been investigated. Electric and thermal characteristics of low wetting contact Hg/Si, and high wetting contacts Hg/Cu were determined and compared. Tunneling I-V characteristics for Hg/Si were obtained, whilst for Hg/Cu, I-V characteristics were ohmic. The tunneling I-V characteristic... Agent: Borealis Techincal Limited

20080061290 - Organic fet having improved electrode interfaces and a fabrication method therefor: The present invention relates to an organic FET in which the interfaces (electrode interfaces) between a semiconductor layer and a source electrode and between a semiconductor layer and a drain electrode are improved by employing a novel technique to increase ON-state current (driving current) and to reduce contact resistance. The... Agent: Mcdermott Will & Emery LLP

20080061289 - Process for synthesizing halogenated derivatives of fluorescein for use in the production of non-volatile memory devices: A process performs solid phase synthesis of halogenated derivatives of fluorescein, and includes reacting fluorescein with a halide MX, wherein M is an alkali metal and X is a halogen, and Oxone® (2 KHSO5.KHSO4.K2SO4), at a temperature higher than or equal to 150° C. A structure uses a halogenated derivative... Agent: Seed Intellectual Property Law Group PLLC

20080061292 - Method of doping impurities, and electronic element using the same: The invention provides a method of doping impurities that includes a step of doping impurities in a solid base substance by using a plasma doping method, a step of forming a light antireflection layer that functions to reduce light reflection on the surface of the solid base substance, and a... Agent: Mcdermott Will & Emery LLP

20080061293 - Semiconductor device with heterojunctions and an inter-finger structure: A semiconductor device including, on at least one surface of a crystalline semiconductor substrate, at least one first amorphous semiconductor region doped with a first type of conductivity. The semiconductor substrate includes, on the same at least one surface, at least one second amorphous semiconductor region doped with a second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080061294 - Thin-film transistor substrate, display device, cad program and transfer method for thin-film transistor substrate: where Ca represents a capacitor between each of the semiconductor layer patterns and the metal table, Cb represents a capacitor between each of the semiconductor layer patterns and the gate electrode lines, Ce represents a capacitor between each of the gate electrode lines and the metal table, L represents a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080061296 - Thin film transistor array panel for liquid crystal display and method of manufacturing the same: A method for manufacturing a thin film transistor array panel is disclosed. A gate wiring pattern is formed on an insulating substrate. A gate insulating layer is formed on the gate wiring pattern. A semiconductor pattern is formed on the gate insulating layer. A transparent conductive layer is formed on... Agent: Howrey & Simon Attn: Docket Department

20080061298 - Semiconductor element and semiconductor memory device using the same: A semiconductor memory device includes a plurality of memory cells, each including, a source region formed of a semiconductor material, a drain region formed of the semiconductor material, and a first region formed of the semiconductor material and located between the source region and the drain region. First and second... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080061299 - Semiconductor device and a method for manufacturing the same: A thin film transistor of the present invention has an active layer including at least source, drain and channel regions formed on an insulating surface. A high resistivity region is formed between the channel region and each of the source and drain regions. A film capable of trapping positive charges... Agent: Eric Robinson

20080061300 - Flexible backplane and methods for its manufacture: The present invention is directed to a flexible backplane for direct drive display devices and methods for its manufacture. The flexible backplane has many advantages. Because there is no need for a polyimide layer and only one layer of metal foil is used, the backplanes may be manufactured at a... Agent: Howrey LLP

20080061301 - Method of manufacturing a semiconductor device: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the... Agent: Eric Robinson

20080061303 - Compound semiconductor device and method for manufacturing same: A compound semiconductor device includes a laminated body including a crystal substrate and a compound semiconductor multilayer film. The laminated body has a major surface, a first side face, a second side face, a third side face, and a fourth side face. The first and the second side faces are... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080061307 - Method of fabricating light emitting device and thus-fabricated light emitting device: A light emitting device wafer having a light emitting layer section 24 having an AlGaInP-base double heterostructure, and a GaP light extraction layer 20 disposed on the light emitting layer section so as to allow a first main surface thereof to compose a first main surface of the wafer is... Agent: Snider & Associates

20080061311 - Led with current confinement structure and surface roughening: An LED having a p-type layer of material with an associated p-contact, an n-type layer of material with an associated n-contact and an active region between the p-type layer and the n-type layer, includes a confinement structure that is formed within one of the p-type layer of material and the... Agent: Koppel, Patrick & Heybl

20080061317 - Patterned strained semiconductor substrate and device: A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive... Agent: Greenblum & Bernstein, P.L.C

20080061316 - Strained-channel fin field effect transistor (fet) with a uniform channel thickness and separate gates: A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first... Agent: Mcginn Intellectual Property Law Group, PLLC

20080061318 - Vertical memory device and method: Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the... Agent: Kacvinsky LLC C/o Intellevate

20080061319 - Systems and methods for distributing io in a semiconductor device: Various systems and methods for implementing multi-mode semiconductor devices are discussed herein. For example, a multi-mode semiconductor device is disclosed that includes a device package with a number of package pins. In addition, the device includes a semiconductor die or substrate with at least two IO buffers. One of the... Agent: Hamilton And Desanctis

20080061321 - Low power electrically alterable nonvolatile memory cells and arrays: A method of providing a memory cell includes providing a body of a semiconductor material having a first conductivity type, arranging a filter of a conductor-filter system in contact with a first conductor of the conductor-filter system, arranging at least portion of a second conductor of a conductor-insulator system in... Agent: Harness, Dickey & Pierce P.L.C

20080061320 - Transistor, memory cell array and method of manufacturing a transistor: A transistor of an integrated circuit includes a first and second source/drain regions, a channel region connecting the first and second source/drain regions, and a gate electrode configured to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, that is defined in... Agent: Edell , Shapiro & Finnan , LLC

20080061322 - Transistor, memory cell array and method of manufacturing a transistor: A transistor includes a first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, the gate groove being defined in a top surface of... Agent: Edell , Shapiro & Finnan , LLC

20080061323 - Examination apparatus for biological sample and chemical sample: A wireless sensor chip suitable for the compact, high-sensitive, and low-cost examination apparatus for easily examining a biological material such as gene at low cost is provided. A sensor chip is formed on an SOI substrate, and an n type semiconductor layer on which a PMOS transistor is formed and... Agent: Stanley P. Fisher Reed Smith Hazel & Thomas LLP

20080061324 - Semiconductor device: A semiconductor device 20 formed on a semiconductor chip substrate 30 has a plurality of circuit blocks made up of circuits each containing at least a metal oxide semiconductor (MOS) transistor 36, the circuit blocks being covered on top with a protective film 41 to protect the circuits. A plurality... Agent: Steptoe & Johnson LLP

20080061325 - Device and method of manufacture for a low noise junction field effect transistor: A microelectronic product and the method for manufacturing the product are provided. A source and drain are spaced from one another in a first direction and are connected to opposing ends of a channel to provide a set voltage. First and second gates are spaced from one another in a... Agent: Stephen M. De Klerk Blakely, Sokoloff, Taylor & Zafman LLP

20080061326 - Semiconductor device: As a discrete semiconductor chip, there has been known one that enables flip-chip mounting by providing first and second electrodes in a current path above a first surface of a semiconductor substrate. However, there is a problem that a horizontal current flow in the substrate increases resistance components. A first... Agent: Morrison & Foerster LLP

20080061327 - Semiconductor device and its manufacturing method: A semiconductor device and its manufacturing method are disclosed. The nitrogen flow is gradually changed to form a semiconductor device with a gate or a source/drain having a nitrified gradient layer structure. Different extents of nitrification inside the nitrified gradient layer structure provide protection and buffering to prevent the undercut... Agent: Bacon & Thomas, PLLC

20080061329 - Reflection type cmos image sensor and method of manufacturing the same: A complementary metal oxide semiconductor (CMOS) image sensor including a semiconductor substrate having an inclined groove with an inclined surface and a light reception surface perpendicular to the semiconductor substrate, and a device forming area adjacent the light reception surface. A reflection film selectively formed on and/or over the inclined... Agent: Sherr & Nourse, PLLC

20080061328 - Cmos image sensor using surface field effect: A CMOS image sensor including a photodiode having a well having a first conductive type formed in a semiconductor substrate, a first ion-implantation layer formed in the semiconductor substrate having a conductive type being opposite to the first conductive type of the well, and a second ion-implantation layer having the... Agent: Sherr & Nourse, PLLC

20080061330 - Methods for fabricating image sensor devices: Image sensor devices and methods for fabricating the same are provided. An exemplary embodiment of an image sensor device comprises a support substrate. A passivation structure is formed over the support substrate. An interconnect structure is formed over the passivation structure. A first semiconductor layer is formed over the interconnect... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080061331 - Semiconductor device and manufacturing method thereof: An impurity-doped PZT film in an amorphous state doped with La, Ca, Sr, Si, Nb and/or the like is formed on a Pt film composing a bottom electrode film. Next, crystallization annealing for the impurity-doped PZT film is performed. Next, a PZT film is formed on the impurity-doped PZT film... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080061335 - Semiconductor memory and method for manufacturing the semiconductor memory: According to an aspect of the present invention, there is provided a semiconductor memory including a lower electrode, a first insulating region formed in the same layer as the lower electrode, a ferroelectric film formed on the lower electrode and on the first insulating region, an upper electrode formed on... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080061334 - Semiconductor memory device and method for forming the same: A semiconductor memory device and a method for forming the same. The method includes forming an insulating layer on a semiconductor substrate having a conductive region, forming a contact hole that exposes the conductive region by etching the insulating layer, forming a barrier metal layer that covers a sidewall and... Agent: Harness, Dickey & Pierce, P.L.C

20080061333 - Semiconductor memory device and method of fabricating semiconductor memory device: According to an aspect of the present invention, there is provided a semiconductor memory device, comprising a memory cell portion, the memory cell portion having a ferroelectric capacitor and a memory cell transistor, the ferroelectric capacitor having a plurality of electrode films and a ferroelectric film, the plurality of electrode... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080061332 - Spin mosfet: A spin MOSFET includes: a semiconductor substrate; a first magnetic film formed on the semiconductor substrate and including a first ferromagnetic layer, a magnetization direction of the first ferromagnetic layer being pinned; a second magnetic film formed on the semiconductor substrate to separate from the first magnetic film and including... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080061336 - Spin transistor based on the spin-filter effect, and non-volatile memory using spin transistors: A spin transistor comprises a spin injector for injecting, from a first nonmagnetic electrode carriers with a spin parallel to a spin band forming the band edge of a first ferromagnetic barrier layer, to a second nonmagnetic electrode layer, as hot carriers. It also comprises a spin analyzer whereby, due... Agent: Reed Smith LLP

20080061337 - Integrated memory cell array: The present invention provides an integrated memory cell array comprising: a semiconductor substrate; a plurality of cell transistor devices including: a pillar formed in said semiconductor substrate; a gate trench surrounding said pillar; a first source/drain region formed in an upper region of said pillar; a gate dielectric formed on... Agent: Eschweiler & Associates LLC

20080061339 - Semiconductor device having capacitance element, arranged close to mos transistor and having dielectric made of electrostrictive material: A semiconductor device includes a single-crystal semiconductor substrate; and a stress applying device for applying a desired mess to specific one or more parts on or in the single-crystal semiconductor substrate. Typically, the stress applying device includes a capacitance element, which is arranged in the vicinity of the specific one... Agent: Sughrue Mion, PLLC

20080061338 - Method for processing a structure of a semiconductor component, and structure in a semiconductor component: A method is used for processing a structure of a semiconductor component. The structure has at least one partial structure to be etched, in particular a sublithographic partial structure. The at least one partial structure has at least one structure to be etched with at least one lateral etch stop... Agent: Slater & Matsil, L.L.P.

20080061340 - Memory cell array and method of forming the memory cell array: A memory cell array having a plurality of memory cells is disclosed. In one embodiment, each memory cell includes a storage capacitor and an access transistor, a plurality of bit lines orientated in a first direction, a plurality of word lines orientated in a second direction, the second direction being... Agent: Dicke, Billig & Czaja

20080061341 - Memory device having wide area phase change element and small electrode contact area: A memory cell device of the type that includes a memory material switchable between electrical property states by application of energy, situated between first and second (“bottom” and “top”) electrodes has a top electrode including a larger body portion and a stem portion. The memory material is disposed as a... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080061342 - Semiconductor device and method for making the same: A method for forming a semiconductor device is provided. The method comprises providing a substrate with recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions and... Agent: Quintero Law Office, PC

20080061343 - Metal-oxide-metal structure with improved capacitive coupling area: A stacked metal-oxide-metal (MOM) capacitor structure and method of forming the same to increase an electrode/capacitor dielectric coupling area to increase a capacitance, the MOM capacitor structure including a plurality of metallization layers in stacked relationship; wherein each metallization layer includes substantially parallel spaced apart conductive electrode line portions having... Agent: Tung & Associates

20080061344 - Semiconductor device: In a pair of adjacent stack contact and stack contact in the semiconductor device, the plugs and the plugs are disposed so that a center-to-center distance of the plugs extending through a second interlayer insulating film, which is thicker than the first interlayer insulating film, is larger than a center-to-center... Agent: Young & Thompson

20080061345 - Semiconductor device and method for manufacturing the same: The semiconductor device has an insulation layer formed over a semiconductor substrate, a conductor plug 46 buried in the insulation layer, a capacitor formed above the insulation layer and the conductor plug and including a lower electrode formed of the first conduction film and the second conduction film formed over... Agent: Staas & Halsey LLP

20080061347 - Configuration and method of manufacturing the one-time programmable (otp) memory cells: This invention discloses an one time programmable (OTP) memory. The OTP memory includes a first and a second metal oxide semiconductor (MOS) transistors connected in parallel and controlled by a single polysilicon stripe functioning as a gate wherein the OTP memory further includes a drift region for counter doping a... Agent: Bo-in Lin

20080061346 - One-transistor memory cell with bias gate: One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage... Agent: Schwegman, Lundberg & Woessner, P.A.

20080061351 - Nanowire electromechanical switching device, method of manufacturing the same and electromechanical memory device using the nanowire electromechanical switching device: A nanowire electromechanical switching device is constructed with a source electrode and a drain electrode disposed on an insulating substrate and spaced apart from each other, a first nanowire vertically grown on the source electrode and to which a V1 voltage is applied, a second nanowire vertically grown on the... Agent: Robert E. Bushnell

20080061348 - Nonvolatile memory structure and method of forming the same: Example embodiments are directed to a method of forming a nonvolatile memory structure and a nonvolatile memory structure including a plurality of charge storage patterns, wherein an electrical coupling distance (Lc) between adjacent charge storage patterns is larger than a direct geometric distance (Ls) between adjacent charge storage patterns.... Agent: Harness, Dickey & Pierce, P.L.C

20080061350 - Nonvolatile semiconductor memory and method of manufacturing the same and manufacturing method thereof: There is provided a nonvolatile semiconductor memory of an aspect of the present invention includes a semiconductor substrate, first and second isolation insulating layers provided in the semiconductor substrate, a channel region between the first and second isolation insulating layers, a gate insulating film on the channel region, a floating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080061349 - Nonvolatile semiconductor memory with resistance elements and method of manufacturing the same: A nonvolatile semiconductor memory of an aspect of the present invention comprises a memory cell transistor and a resistance element arranged on a semiconductor substrate. The memory cell transistor includes a floating gate electrode constituted of a first conductive material arranged on a gate insulating film on a surface of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080061353 - Flash memory device: A flash memory device and method of fabricating the same, wherein a width at the top of a floating gate is narrower than that at the bottom of the floating gate. The area of the floating gate can be reduced while maintaining the overlap area between the control gate and... Agent: Marshall, Gerstein & Borun LLP

20080061352 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a word line structure that extends in a first direction on an active region defined on a substrate. First and second contact pads are formed on the active region at both sides of the word line structure. Bit line structures are electrically connected to the first... Agent: Marger Johnson & Mccollom, P.C.

20080061356 - Eeprom device and methods of forming the same: An EEPROM device is provided with an active region including a first region, a second region having a lower top surface than a top surface of the first region, and a sidewall disposed at the boundary between the first and second regions. A tunneling region of charges for a program... Agent: F. Chau & Associates, LLC

20080061354 - Semiconductor device with split gate memory cell and fabrication method thereof: A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080061355 - Method of reducing memory cell size for floating gate nand flash: In accordance with the present invention, a new method, its structure and manufacturing method is described to reduce memory cell size about the half of the conventional method for a non-volatile NAND Flash cell. The control gates in a string of the NAND Flash cell array is formed as the... Agent: Townsend And Townsend And Crew, LLP

20080061357 - Semiconductor device with double barrier film: A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080061358 - Method of reducing memory cell size for non-volatile memory device: In accordance with the present invention, a new method, its structure and manufacturing method is proposed to reduce memory cell size about the half of the conventional method for a non-volatile NAND Flash cell. The control gates in a string of the NAND Flash cell array is formed as the... Agent: Townsend And Townsend And Crew, LLP

20080061360 - Non-volatile memory device and method of manufacturing the same: In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate... Agent: Harness, Dickey & Pierce, P.L.C

20080061361 - Non-volatile memory device and method of manufacturing the same: In a non-volatile memory device, active fin structures extending in a first direction may be formed on a substrate. A tunnel insulating layer may be formed on surfaces of the active fin structures and bottom surfaces of trenches that may be defined by the active fin structures. A charge trapping... Agent: Harness, Dickey & Pierce, P.L.C

20080061359 - Dual charge storage node with undercut gate oxide for deep sub-micron memory cell: An embodiment of the present invention is directed to a memory cell. The memory cell includes a stack formed over a substrate. The stack includes a gate oxide layer and an overlying polycrystalline silicon layer. The stack further includes first and second undercut regions formed under the polycrystalline silicon layer... Agent: Wagner, Murabito & Hao LLP

20080061362 - Self-aligned trench field effect transistors with regrown gates and bipolar junction transistors with regrown base contact regions and methods of making: Junction field-effect transistors with vertical channels and self-aligned regrown gates and methods of making these devices are described. The methods use techniques to selectively grow and/or selectively remove semiconductor material to form a p-n junction gate along the sides of the channel and on the bottom of trenches separating source... Agent: Merchant & Gould PC

20080061363 - Integrated transistor device and corresponding manufacturing method: The present invention provides an integrated transistor device comprising: a semiconductor substrate; a pillar formed in said semiconductor substrate; a gate trench surrounding said pillar; a first source/drain region formed in an upper region of said pillar; a gate dielectric formed on the bottom of said gate trench and surrounding... Agent: Eschweiler & Associates LLC

20080061364 - Trench type mos transistor and method for manufacturing the same: A trench type MOS transistor and a method for manufacturing the trench type MOS transistor are disclosed. In one aspect, the total capacitance between a gate electrode and a drain region of the trench type MOS transistor can be reduced. In particular, a PN junction is formed in the gate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080061365 - Trench fet with self aligned source and contact: A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the... Agent: Ostrolenk Faber Gerb & Soffen

20080061366 - Complementary metal-oxide-semiconductor device and fabricating method thereof: A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed... Agent: Jianq Chyun Intellectual Property Office

20080061367 - High-voltage bipolar-cmos-dmos integrated circuit devices and modular methods of forming the same: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and... Agent: Patentability Associates

20080061368 - High-voltage bipolar-cmos-dmos integrated circuit devices and modular methods of forming the same: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and... Agent: Patentability Associates

20080061369 - Semiconductor device using filled tetrahedral semiconductor: A semiconductor device provided with a filled tetrahedral semiconductor is formed by introducing impurity atoms S for substituting the component atoms of sites of lattice points and impurity atoms I to be inserted into interstitial sites of a host semiconductor where component atoms are bonded to form a tetrahedral bonding... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080061370 - Semiconductor device and method of manufacturing the same: A semiconductor device has plural columnar gate electrodes for plural MOSFETs formed in a row separately on a semiconductor substrate, and a semiconductor region which is formed in a part between the neighboring two columnar gate electrodes of the plural columnar gate electrodes to form a channel of the MOSFETs.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080061371 - Field effect transistor (fet) devices and methods of manufacturing fet devices: In one aspect, a semiconductor substrate is provided having a cell area and a peripheral circuit area, and a mask layer is formed over the cell area and the peripheral circuit area of the semiconductor substrate. A FinFET gate is fabricated by forming a first opening in the mask layer... Agent: Volentine & Whitt PLLC

20080061372 - Semiconductor device: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below... Agent: Mcdermott Will & Emery LLP

20080061373 - System-in-package type static random access memory device and manufacturing method thereof: A device may include at least one of the following: A first substrate including a plurality of N-channel metal oxide semiconductor transistors, with the N-channel MOS transistors including an access transistor and a drive transistor. A second substrate including a plurality of P-channel metal oxide semiconductor transistors used as pull-up... Agent: Sherr & Nourse, PLLC

20080061374 - Semiconductor resistor and semiconductor process of making the same: A semiconductor resistor and a semiconductor process of making the same are provided. The semiconductor resistor comprises a substrate, a deep well, at least two contact regions, and a doped region. The substrate is doped with a first type of ions. The deep well is doped with a second type... Agent: Nixon Peabody LLP - Patent Group

20080061376 - Modular bipolar-cmos-dmos analog integrated circuit & power transistor technology: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of... Agent: Patentability Associates

20080061375 - Modular bipolar-cmos-dmos analog integrated circuit and power transistor technology: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of... Agent: Patentability Associates

20080061377 - Modular bipolar-cmos-dmos analog integrated circuit and power transistor technology: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of... Agent: Patentability Associates

20080061378 - Semiconductor device: A semiconductor device has a plurality of fuse element portions each of which including a first fuse interconnect having a fuse to be portion, a second fuse interconnect connected to an internal circuit, a first impurity diffusion layer for electrically connecting the first fuse interconnect and the second fuse interconnect,... Agent: Mcginn Intellectual Property Law Group, PLLC

20080061379 - Mos devices with graded spacers and graded source/drain regions: An MOS device includes a gate stack overlying a semiconductor substrate and a graded source/drain region adjacent to the gate stack. The graded source/drain region includes a first grade having a first depth, a second grade spaced further apart from a channel region than the first grade, and a third... Agent: Slater & Matsil, L.L.P.

20080061380 - Method for manufacturing semiconductor device, and semiconductor device: The present invention provides a technique for efficiently forming a high-breakdown voltage transistor and a low-breakdown voltage transistor on the same substrate while reducing the deterioration of each transistors' characteristics. At first, an insulating film is formed. The insulating film portions above the drain and source formation regions for the... Agent: Oliff & Berridge, PLC

20080061381 - Method of manufacturing semiconductor integrated circuit device having capacitor element: In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080061382 - Transistors, semiconductor integrated circuit interconnections and methods of forming the same: Provided are transistors, semiconductor integrated circuit interconnections and methods of forming the same. The transistors, semiconductor integrated circuit interconnections and methods of forming the same may improve electrical characteristics between gate electrodes or interconnection electrodes and simplify a semiconductor fabrication process related to gate electrodes or interconnection electrodes. A material... Agent: Harness, Dickey & Pierce, P.L.C

20080061383 - Semiconductor device having fin field effect transistor and manufacturing method thereof: A semiconductor device in which the concentration of the electric field at upper end portions (corner portions) of a fin-shaped active region is eased and deterioration of the threshold voltage of the FinFET is suppressed, and that has a high current driving performance, and a manufacturing method thereof are provided.... Agent: Mcginn Intellectual Property Law Group, PLLC

20080061384 - Semiconductor device: Diffusion layers 2-5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2-5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6,... Agent: Townsend And Townsend And Crew, LLP

20080061385 - Manufacturing method of a semiconductor device: A manufacturing method of a semiconductor device including at least one of the following steps. Forming a gate insulating layer, a gate electrode layer, a spacer, a source region and a drain region on and/or over a substrate on which a predetermined lower structure is formed. Making the upper portion... Agent: Sherr & Nourse, PLLC

20080061386 - Semiconductor device including a gate electrode having a polymetal structure: A semiconductor device includes a gate electrode including a polysilicon layer, a tungsten silicide layer, a tungsten nitride layer, and a tungsten layer, which are arranged in this order as viewed from a silicon substrate. The polysilicon layer is doped with phosphor, and the tungsten silicide layer is doped with... Agent: Young & Thompson

20080061387 - Micro-actuator and locking switch: A micro-electromechanical actuator employs metal for the hot arm and silicon for at least the flexible portion of the cold arm. The cold arm made of silicon is coupled to a metal wire that moves with it and is used to carry the signal to be switched when at least... Agent: Lucent Technologies Inc. Docket Administrator - Room 3j-219

20080061388 - Devices and circuits based on magnetic tunnel junctions utilizing a multilayer barrier: Devices having magnetic or magnetoresistive tunnel junctions (MTJS) have a multilayer insulator barrier layer to produce balanced write switching currents in the device circuitry, or to produce the magnetic devices with balanced critical spin currents required for spin torque transfer induced switching of the magnetization, or both for the MTJs... Agent: Fish & Richardson, PC

20080061389 - Semiconductor substrate for photosensitive chip: A circuit layout for a photosensitive chip includes a semiconductor substrate, a plurality of first circuit lines and a plurality of second circuit lines. The semiconductor substrate has a matrix of photosensitive units. Each photosensitive unit has a first blocking region, a second blocking region and a photosensitive region formed... Agent: Jianq Chyun Intellectual Property Office

20080061390 - Method and apparatus for reducing smear in back-illuminated imaging sensors: A method for fabricating a back-illuminated semiconductor imaging device and resulting imaging device is disclosed, which includes the steps providing a substrate having a front surface and a back surface; growing an epitaxial layer substantially overlying the front surface of the substrate; forming at least one barrier layer substantially within... Agent: Patent Docket Administrator Lowenstein Sandler P.C.

20080061391 - Method of manufacturing image sensor: Embodiments relate to a method of manufacturing an image sensor which includes forming a plurality of lower layers over a semiconductor substrate. A first passivation layer may be formed over the lower layers to protect the lower layers. The first passivation layer may be formed in a pixel region and... Agent: Sherr & Nourse, PLLC

20080061392 - Photo-sensitive chip module package: A photo-sensitive chip module package includes a substrate, a photo-sensitive chip installed on the substrate and having a photo-sensitive zone, a plurality of passive components installed on the substrate, and a plurality of bonding wires electrically connected with the photo-sensitive chip and the passive components to the substrate. A cap... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080061393 - Photosensitive chip molding package: A photosensitive chip molding package includes a lead frame, a photosensitive chip mounted on the lead frame and having an photo-active zone and a photo-inactive zone surrounding the photo-active zone, a plurality of bonding wires electrically connected with the photosensitive chip and the lead frame, and an encapsulant molded on... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080061394 - Electro-optical device and electronic apparatus: An electro-optical device includes semiconductor layers disposed between a first substrate and an electro-optical layer. The semiconductor layers are provided at positions corresponding to crossover regions of scanning lines and data lines. Island light shielding films are disposed between the second substrate and the electro-optical layer. The island light shielding... Agent: Oliff & Berridge, PLC

20080061395 - Tileable multi-layer detector: A detector assembly is presented. The detector assembly includes a first detector layer having a top side and a bottom side, where the first detector layer includes a plurality of first coupling gaps. Additionally, the detector assembly includes a first interconnect structure operationally coupled to the first detector layer and... Agent: General Electric Company Global Research

20080061396 - Stacked dual mosfet package: A stacked dual MOSFET package is disclosed. The package includes a first conductive tab; a high side MOSFET die coupled to the first conductive tab such that a drain of the high side MOSFET die is electrically coupled to the first conductive tab; a second conductive tab electrically coupled to... Agent: Fortune Law Group LLP

20080061397 - Semiconductor device: A semiconductor device that can suppress noise transmission through a seal ring provided between two device regions. The semiconductor device includes a logic unit and an analog unit. The semiconductor device further includes a silicon substrate, an insulating interlayer, a seal ring surrounding the outer periphery of the logic unit... Agent: Young & Thompson

20080061398 - Method for forming trench isolation structure: This invention provides a base material with a siliceous film, which is free from voids and cracks in the interior of groove(s) in a trench isolation structure and has excellent adhesion between a substrate and a siliceous film, and a process for producing the base material with a siliceous film.... Agent: Az Electronic Materials Usa Corp. Attention: Industrial Property Dept.

20080061399 - Semiconductor device and method for fabricating the same: A semiconductor device according to the present invention includes a semiconductor substrate; a capacitor having a lower electrode formed on said semiconductor substrate, a capacity insulating film formed on said lower electrode, and an upper electrode formed on said capacity insulating film; contact holes formed on said upper electrode and... Agent: Rabin & Berdo, PC

20080061400 - High-voltage bipolar-cmos-dmos integrated circuit devices and modular methods of forming the same: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and... Agent: Patentability Associates

20080061401 - Modified transistor: A bipolar-junction transistor is disclosed comprising a first layer, a second layer, and a third layer, the surfaces of the layers modified for more precise control of electron function. The surfaces are modified to have a periodically repeating structure of indents where the indentations are of dimensions so as to... Agent: Borealis Technical Limited

20080061402 - Packaged stacked semiconductor device and method for manufacturing the same: The present invention provides a packaged stacked semiconductor device which includes bumps serving as external electrode terminals, the bumps being provided on both a front surface and a back surface of the device, and which is sacked on another semiconductor device, substrate, or board having electrode terminals so that the... Agent: Mcglew & Tuttle, PC

20080061403 - Dielectric layers for metal lines in semiconductor chips: A semiconductor structure and methods for forming the same. The structure includes (a) a substrate; (b) a first device and a second device each being on the substrate; (c) a device cap dielectric layer on the first and second devices and the substrate, wherein the device cap dielectric layer comprises... Agent: Schmeiser, Olsen & Watts

20080061404 - Electronic circuit package and fabricating method thereof: An electronic circuit package and fabricating method thereof. The method includes: integrating a radio frequency circuit device and a semiconductor die on a printed circuit board; forming a bumper pad of metal on the printed circuit board around the radio frequency circuit device; forming a molding on the printed circuit... Agent: Cha & Reiter, LLC

20080061405 - Shielding noisy conductors in integrated passive devices: The specification describes a thin film Integrated Passive Device (IPD) design that achieves isolation between conductive runners by shielding the top and bottom regions of a noisy runner with metal shield plates. The shield plates are derived from metal interconnect layers. The invention can be implemented by merely modifying the... Agent: Law Office Of Peter V.d. Wilde

20080061406 - Semiconductor package having electromagnetic shielding part: A semiconductor package includes a semiconductor chip; and an encapsulant for covering the semiconductor chip, such that the encapsulant includes a molding part for covering the semiconductor chip to protect the semiconductor chip from the external environment; and an electromagnetic shielding part for covering an outer surface of the molding... Agent: Ladas & Parry LLP

20080061407 - Semiconductor device package and manufacturing method: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The... Agent: Birch Stewart Kolasch & Birch

20080061408 - Integrated circuit package: A novel, small outline molded, high voltage, lead frame based integrated circuit package is described. The integrated circuit die has at least one high voltage I/O pad that is electrically connected to an associated high voltage lead/pin in the lead frame. All of the pins of the lead frame that... Agent: Beyer Weaver LLP

20080061409 - Micro electro-mechanical system module package: A MEMS module package includes a substrate, a silicon chip attached on the substrate and having an active zone and an inactive zone surrounding around the active zone, a plurality of bonding wires electrically connected the silicon chip and the substrate, and an encapsulant formed between the inactive zone of... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080061410 - Electronic device having wiring substrate and lead frame: An electronic device includes: a first substrate and a second substrate; a lead frame disposed between the first and the second substrates for electrically connecting therebetween; and a first groove and a second groove disposed on the first and the second substrates, respectively. The first and the second grooves correspond... Agent: Posz Law Group, PLC

20080061411 - Chip-stacked package structure for lead frame having bus bars with transfer pads: A chip-stacked structure for packaging with lead-frame having bus bar formed with transfer pads is disclosed. The structure includes a lead-frame, an offset multi-chip-stacked structure, and an encapsulant. The lead frame includes a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a... Agent: Reed Smith LLP

20080061412 - Chip-stacked package structure with leadframe having multi-piece bus bar: The present invention provides a chip-stacked package structure with leadframe having multi-piece bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner... Agent: Reed Smith LLP

20080061413 - Semiconductor component having a semiconductor die and a leadframe: A semiconductor component has a leadframe, a semiconductor die and an encapsulation element. The leadframe has a die pad having a first side, at least one lead spaced at a distance from the die pad and at least one support bar remnant protruding from the die pad, each having a... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20080061415 - Semiconductor device, method for manufacturing semiconductor device, and electric equipment system: A semiconductor device of the present invention includes: a plurality of semiconductor chips each having a chip size package structure; and a substrate bonded via an adhesive material to an opposite surface in each of the plurality of semiconductor chips that is opposite to a connection surface that is provided... Agent: Hamre, Schumann, Mueller & Larson P.C.

20080061416 - Die attach paddle for mounting integrated circuit die: An electrical package for an integrated circuit die which comprises a die-attach paddle for mounting the integrated circuit die. The die-attach paddle has at least one down-set area located on a periphery of the die-attach paddle. The down-set area has an upper surface and a lower surface, with the upper... Agent: Schneck & Schneck

20080061414 - Method of producing a semiconductor package: A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material.... Agent: Sughrue Mion, PLLC

20080061417 - Mounting structure for ic tag and ic chip for mounting: With a mounting structure for an IC tag where an IC chip for mounting (10) is mounted so as to be electrically connected to antenna patterns (44a), (44b), the assembly process that mounts the IC chip for mounting (10) on the antenna patterns (44a), (44b) is simplified, which makes it... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080061418 - Three dimensional device integration method and integrated device: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080061419 - Three dimensional device integration method and integrated device: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080061420 - Integrated passive devices with high q inductors: The specification describes flip bonded dual substrate inductors wherein a portion of the inductor is constructed on a base IPD substrate, a mating portion of the inductor is constructed on a cover (second) substrate. The cover substrate is then flip bonded to the base substrate, thus mating the two portions... Agent: Law Firm Of Peter V.d. Wilde

20080061421 - Stacked chip package structure with leadframe having bus bar: The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads... Agent: Reed Smith LLP

20080061423 - Method for producing a circuit module comprising at least one integrated circuit: An integrated circuit module comprises a chip, the chip comprising a substrate with a first main area and a second main area, the first main area comprising two half-sets of pads, the chip further comprising an integrated circuit with components and two half-sets of connection lines, the connection lines connecting... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080061422 - Spacer spraying method and liquid crystal display manufactured by the same: A display device includes an array substrate, which includes a plurality of gate wires, a plurality of data wires, which cross the gate wires, and a plurality of pixel electrodes, which are defined by the gate wires and the data wires; a counter substrate, which includes a common electrode formed... Agent: H.c. Park & Associates, PLC

20080061424 - Semiconductor apparatus: A semiconductor apparatus comprising a silicon substrate; an device housing space including a concave portion formed in the silicon substrate and a hole perforating through the bottom surface of the concave portion; a plurality of laminated semiconductor devices provided in the device housing space; a first lid which lids the... Agent: Drinker Biddle & Reath (dc)

20080061425 - Chip package structure and fabricating method thereof: A chip package structure comprising a chip, a packaging cover panel and an adhesion layer is provided. The chip has an active surface. An image-sensing device is disposed on the active surface and a plurality of contact pads is disposed around the image-sensing device. The package cover panel is disposed... Agent: Jianq Chyun Intellectual Property Office

20080061426 - Electronic circuit unit: The present invention relates to an electronic circuit unit having at least one semiconductor (15), that is situated on a substrate, and whose electrical connections are in electrical contact with printed circuit traces of the substrate, and having a housing, that accommodates the substrate, which has contact paths which are... Agent: Kenyon & Kenyon LLP

20080061427 - Packaging structure and fabricating method thereof: A packaging structure including an interposer structure, a first electronic component, and a second electronic component is provided. The interposer structure includes a first dielectric layer, a plurality of contacts, a capacitive element, and an interconnection. The contacts are disposed on the upper and lower surfaces of the first dielectric... Agent: Jianq Chyun Intellectual Property Office

20080061428 - Package for sealing an integrated circuit die: A die has a part that is sealed with a cap. The seal can be hermetic or non-hermetic. If hermetic, a layer of glass or metal is formed in the surface of the die, and the cap has a layer of glass or metal at a peripheral area so that,... Agent: Wilmerhale/boston

20080061429 - Instruments and method relating to thermal cycling: The invention relates to a device for thermal cycling of biological samples, a heat sink used in such a device and a method. The heat sink comprises a base plate designed to fit in a good thermal contact against a generally planar thermoelectric element included in the device, and a... Agent: Birch Stewart Kolasch & Birch

20080061431 - Power semiconductor module: A semiconductor module of the present invention comprises a first conductive layer (film) and a second conductive layer (film) which are separately formed on the main surface of a packed substrate, a thermal diffusion plate connected by solder to the upper surface of the first conductive layer, a semiconductor element... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080061430 - Structure of heat dissipated submount: A structure of a submount for thermal package has a high heat dissipation and a low spreading thermal resistance. The submount has a specific ratio of height to side length.... Agent: Troxell Law Office PLLC

20080061432 - Semiconductor device tape carrier, manufacturing method for semiconductor device, semiconductor device, and semiconductor module device: The present invention provides a semiconductor device tape carrier formed of an insulative tape 1 of a thin film, which becomes a semiconductor device by conducting a plurality of wire patterns 11 on its surface to a bump 23 of a semiconductor element 21 and being sealed by an insulative... Agent: Harness, Dickey & Pierce, P.L.C

20080061433 - Methods and substrates to connect an electrical member to a substrate to form a bonded structure: Methods and substrates to connect an electrical member to a substrate to form a bonded structure are disclosed. An illustrated example bonded structure has conductive bumps of a ball grid array on an electrical member engaging enlarged contact pads of a substrate to prevent improper bump reflow and electrical shorts.... Agent: Texas Instruments Incorporated

20080061434 - Substrate for semiconductor package and method of manufacturing the same: A substrate for a semiconductor package and a method of manufacturing the same are provided. More particularly, the substrate for the semiconductor package and the method for manufacturing the same include metal pieces, with some of the metal pieces having one end embedded within an insulating layer for insulating an... Agent: Marger Johnson & Mccollom, P.C.

20080061435 - Structure of mounting electronic component and method of mounting the same: The structure of mounting an electronic component on a circuit board is capable of securely flip-chip-bonding the electronic component having bumps, whose separations are very short, to the circuit board without displacement. The structure of mounting an electronic component on a circuit board is characterized in that bumps of the... Agent: Arent Fox LLP

20080061436 - Wafer level chip scale package and method for manufacturing the same: Provided is a wafer level chip scale package that reduces the parasitic capacitance generated between ball pads and the solder balls, and enhances the joint reliability between the ball pads and the solder balls. The wafer level chip scale package provides a conductive pattern in each ball pad section, on... Agent: Marger Johnson & Mccollom, P.C.

20080061437 - Packaging board, semiconductor module, and portable apparatus: A technology is provided for a packaging board adapted to mount a device capable of improving handleability and securing connection reliability. The packaging board includes: a pad electrode formed on a substrate; an insulating layer covering the substrate, having an opening at least in part in an area over the... Agent: Fish & Richardson P.C.

20080061438 - Method of forming metal line in semiconductor device: A method of forming a metal line in a semiconductor device is disclosed. The method of forming a metal line in a semiconductor device includes forming an interlayer insulating film over a substrate. A via hole may be formed by selectively patterning the interlayer insulating film. A metal film may... Agent: Sherr & Nourse, PLLC

20080061439 - Low dielectric constant film produced from silicon compounds comprising silicon-carbon bond: A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also... Agent: Patterson & Sheridan, LLP

20080061440 - Copper alloy bonding wire for semiconductor device: The present invention provides a semiconductor-device copper-alloy bonding wire which has an inexpensive material cost, ensures a superior ball joining shape, wire joining characteristic, and the like, and a good loop formation characteristic, and a superior mass productivity. The semiconductor-device copper-alloy bonding wire contains at least one of Mg and... Agent: Darby & Darby P.C.

20080061441 - Flexible via design to improve reliability: An integrated circuit includes a metallization layer, a first metal line in the metallization layer, and a first via electrically connected to the first metal line. The first via has a first via width and a first pitch from a nearest via on a neighboring metal line, wherein the first... Agent: Slater & Matsil, L.L.P.

20080061442 - Interconnect structures and methods for fabricating the same: Interconnect structures are provided. An exemplary embodiment of an interconnect structure comprises a substrate with a low-k dielectric layer thereon. A via opening and a trench opening are formed in the low-k dielectric layer, wherein the trench opening is formed over the via opening and-the via opening exposes a portion... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080061443 - Method of manufacturing semiconductor device: A method for manufacturing a semiconductor device including at least one of the following steps. Forming a first semiconductor substrate including a first conductive pattern. Adhering a second semiconductor including a second conductive pattern on the first semiconductor substrate using adhesive paste. Forming a through hole by patterning the first... Agent: Sherr & Nourse, PLLC

20080061444 - Post passivation interconnection schemes on top of ic chip: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin

20080061445 - Semiconductor device and method for manufacturing the same: The semiconductor device includes a silicon substrate, a device isolation insulating film dividing an active region of the silicon substrate into plural pieces, a gate electrode formed on the active region, a source/drain region which is formed in the active region on both sides of the gate electrode, and which... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080061446 - Semiconductor device with contact structure and manufacturing method thereof: A plurality of gate lines are formed on a substrate. After depositing a gate insulating layer, a semiconductor layer and a doped amorphous silicon layer are sequentially formed thereon. A lower insulating layer made of silicon nitride and an upper insulating layer made of a photosensitive organic material are deposited... Agent: F. Chau & Associates, LLC

20080061447 - Wire-bonded package with electrically insulating wire encapsulant and thermally conductive overmold: The specification discloses an apparatus comprising a die mounted on a substrate, the die being connected to the substrate by a plurality of wires, and a mold cap encapsulating the die and the plurality of wires, the mold cap comprising an electrically insulating portion encapsulating the wires and at least... Agent: Intel/blakely

20080061448 - System and method for thermal expansion pre-compensated package substrate: A system and method for manufacturing a thermal expansion pre-compensated package system. The system including a substrate having a first and a second planar surface. The first planar surface being opposed to the second planar surface. The system further including a mold compound having a third and a fourth planar... Agent: Cantor Colburn LLP - IBM Research Triangle Park

20080061449 - Semiconductor component arrangement: A semiconductor component arrangement having a semiconductor component, a mount, and an adhesive, wherein the adhesive connects the semiconductor component to the mount and the adhesive contains a marker substance. Also disclosed is a method for inspecting the connection of a semiconductor component to a mount. The semiconductor component is... Agent: Infineon Technologies Ag Patent Department

20080061450 - Bonding wire and bond using a bonding wire: A bonding wire and a bond using such a bonding wire. The contour of the cross-sectional area of the bonding wire has a shape deviating from a circle shape and from a rectangle shape having two sides of different length.... Agent: Kenyon & Kenyon LLP

20080061451 - Semiconductor package and fabrication method thereof: A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes the steps of providing a semiconductor chip having an active surface and a non-active surface opposing to the active surface, roughening a peripheral portion of the non-active surface so as to divide the non-active surface into... Agent: Edwards Angell Palmer & Dodge LLP

20080061452 - Bonded wafer and method of manufacturing the same: The present invention provides a method of manufacturing a bonded wafer. When bonding the top wafer through an insulating film exceeding about 1,000 Angstroms in thickness to the base wafer, a top wafer and a base wafer in which the total number of particles having a size of equal to... Agent: Greenblum & Bernstein, P.L.C

20080054245 - Memory device including phase-changeable material region and method of fabricating the same: A memory device includes first and second electrodes and a phase-changeable material region disposed between the first and second electrodes and including first and second portions contacting respective ones of the first and second electrodes and a third portion interconnecting the first and second portions and configured to preferentially heat... Agent: Myers Bigel Sibley & Sajovec

20080054244 - Phase change memory device and method of forming the same: In one embodiment, a phase change memory device includes an insulation structure over a substrate. The insulation structure ahs an opening defined therethrough. A first layer pattern is formed on sidewalls and a bottom of the opening. A second layer pattern is formed on the first layer pattern and substantially... Agent: Marger Johnson & Mccollom, P.C.

20080054246 - Semiconductor device: A semiconductor device including a contact plug connected to a diffusion layer of a cell transistor, a heater electrode connected to a phase-change film, and a buffer plug connecting between the contact plug and the heater electrode.... Agent: Sughrue Mion, PLLC

20080054248 - Variable period variable composition supperlattice and devices including same: An optical semiconductor device such as a light emitting diode is formed on a transparent substrate having formed thereon a template layer, such as AlN, which is transparent to the wavelength of emission of the optical device. A variable period variable composition superlattice strain relief region is provided over the... Agent: Jonathan A. Small JasIPConsulting

20080054250 - Structure and methods for forming sige stressors: A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the stressor comprises an impurity of a first conductivity type; and a portion of the semiconductor substrate adjoining... Agent: Slater & Matsil, L.L.P.

20080054251 - High operating temperature split-off band infrared detectors: Systems and methods for at or near room temperature of infrared detection are disclosed. Embodiments of the disclosure include high temperature split-off band infrared detectors. One embodiment, among others, comprises a first barrier and a second barrier with an emitter disposed between the first and second barrier, each barrier being... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080054256 - Molecular electronic device including organic dielectric thin film and method of fabricating the same: Provided are a molecular electronic device and a method of fabricating the molecular electronic device. The molecular electronic device includes a substrate, an organic dielectric thin film formed over the substrate, a molecular active layer formed on the organic dielectric thin film and having a charge trap site, and an... Agent: Ladas & Parry LLP

20080054254 - Programmable polyelectrolyte electrical switches: An apparatus includes a first solid electrode on a substrate, a polyelectrolyte layer over a part of the first solid electrode, a second solid electrode on a portion of the polyelectrolyte layer, and an anchoring layer on the part of the first solid electrode. The polyelectrolyte layer is either chemically... Agent: Lucent Technologies Inc. Docket Administrator - Room 3j-219

20080054255 - Substrate structures and fabrication methods thereof: Substrate structures and fabrication methods thereof. A substrate structure includes a bendable substrate and an inorganic electrode structure on the bendable structure, wherein the inorganic electrode structure includes a conductive layer or a semiconductor layer. The inorganic electrode structure includes carbon nanotubes, carbon nanofibers, a nanolinear material, or a micro-linear... Agent: Quintero Law Office, PC

20080054257 - Thin-film transistor and fabrication method thereof: A thin-film transistor and fabrication method thereof are provided. A controlled micro-line is formed by inkjet printing in combination with the coffee ring effect. At least two organic thin-film transistors are formed on two ring ridges of the coffee rings. For example, N-type and P-type soluble semiconductor materials may be... Agent: Quintero Law Office, PC

20080054262 - Semiconductor device: A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage... Agent: Miles & Stockbridge PC

20080054263 - Semiconductor device and method of fabricating the same: A semiconductor device having increased reliability includes a fuse region and a monitoring region. Fuses are located on an insulation film in the fuse region and are exposed through fuse windows. A monitoring pattern is located on the insulation film in the monitoring region. The monitoring pattern includes sub-patterns that... Agent: Marger Johnson & Mccollom, P.C.

20080054261 - Semiconductor package having test pads on top and bottom substrate surfaces and method of testing same: A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising... Agent: Volentine & Whitt PLLC

20080054264 - Thin film transistor array substrate and manufacturing method thereof: A thin film transistor array substrate and the manufacturing method thereof are disclosed herein. A first patterned metal layer, an insulating layer, a patterned layer, and a second patterned metal layer are sequentially formed on a substrate. Then, a plurality of scan lines and a plurality of source lines are... Agent: Birch Stewart Kolasch & Birch

20080054267 - Display apparatus and manufacturing method of the same: A display apparatus includes a silicon oxide film and a silicon nitride film as a base layer placed on an insulating substrate, a polycrystalline silicon electrode placed on the base layer, a gate insulating film placed on the polycrystalline silicon electrode, and a gate metal electrode placed on the gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080054268 - Display device and method of manufacturing the display device: A display device according to an embodiment of the present invention includes: an interlayer insulating film; a signal line formed above the interlayer insulating film in the display region and supplying a signal or power from a peripheral region to a TFT; a passivation film formed above the signal line;... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080054270 - Semiconductor memory device and the production method: A semiconductor memory device that is configured with a Si substrate layer, a SiC layer and a Si oxide layer, including a structure in which the SiC layer is layered onto the Si substrate layer and the Si oxide layer is layered onto the SiC. Wherein, the Si oxide layer... Agent: Ditthavong Mori & Steiner, P.C.

20080054271 - Nitride semiconductor light emitting diode: A nitride semiconductor light emitting diode (LED) comprises an n-type nitride semiconductor layer; an electron emitting layer formed on the n-type nitride semiconductor layer, the electron emitting layer being composed of a nitride semiconductor layer including a transition element of group III; an active layer formed on the electron emitting... Agent: Lowe Hauptman Ham & Berner, LLP

20080054273 - Semiconductor device, light emitting diode print head, and image forming apparatus: A semiconductor device includes a plurality of light emitting elements formed of a thin layer of a compound semiconductor and arranged in a row in one direction with an equal interval therebetween. Each of the light emitting elements includes a light emitting area formed on a surface thereof; a first... Agent: Takeuchi & Kubotera, LLP

20080054274 - Edge-emitting light-emitting diode: An edge-emitting light-emitting diode comprises a base, a frame, and at least two chips. The base has a recessed cup on the front side. The frame is fixed on the inside of the recessed cup. The chips are electrically connected to the frame inside the recessed cup. The frame has... Agent: Troxell Law Office PLLC Suite 1404

20080054275 - Integrated optocoupler with organic light emitter and inorganic photodetector: An optocoupler has an organic light emitter and an inorganic photodetector with a detector area, the detector area being optically coupled to the organic light emitter. The organic light emitter converts an electrical input signal into a light signal and the inorganic photodetector converts the light signal into an electrical... Agent: Schoppe, Zimmerman , Stockeller & Zinkler

20080054276 - Reflex coupler with integrated organic light emitter: A reflex coupler has an organic light emitter for generating a light signal and an inorganic photodetector with a detector area. The organic light emitter and the detector area are optically coupled as a result of radiation returned from an object onto which the light signal impinges, and the organic... Agent: Schoppe, Zimmerman , Stockeller & Zinkler

20080054279 - Phosphor position in light emitting diodes: A method of forming an LED lamp with a desired distribution of phosphor is disclosed. The method includes the steps of mixing a plurality of phosphor particles in an uncured polymer resin for which the viscosity can be controlled in response to temperature to form a substantially uniform suspension of... Agent: Summa, Allan & Additon, P.A.

20080054284 - Encapsulant profile for light emitting diodes: A light emitting packaged diode ids disclosed that includes a light emitting diode mounted in a reflective package in which the surfaces adjacent the diode are near-Lambertian reflectors. An encapsulant in the package is bordered by the Lambertian reflectors and a phosphor in the encapsulant converts frequencies emitted by the... Agent: Summa, Allan & Additon, P.A.

20080054281 - High-efficient light engines using light emitting diodes: A light emitting apparatus having a light source for emitting short wavelength radiation and an optic device configured to receive the radiation emitted from the light source. A device directs at least some of the short wavelength radiation emitted from the light source into the optic device and a down... Agent: Ratnerprestia

20080054285 - Light emitting device and manufacturing method thereof: Disclosed is a light emitting device. The light emitting device comprises a substrate, a light emitting diode on the substrate, a molding member sealing the light emitting diode in a double sealing structure and comprising a flat upper surface.... Agent: Birch Stewart Kolasch & Birch

20080054280 - Light emitting packages and methods of making same: In a light emitting package (8), at least one light emitting chip (12, 14, 16, 18) is supported by a board (10). A light transmissive encapsulant (30) is disposed over the at least one light emitting chip and over a footprint area (32) of the board. A light transmissive generally... Agent: Fay Sharpe LLP

20080054283 - Polarized light emitting diode and method of forming the same: Example embodiments are directed to a polarized light emitting diode and method of forming the same. The polarized light emitting diode may include a support layer, a semiconductor layer structure, and/or a polarization control layer. The semiconductor layer structure may be formed on the support layer and may include a... Agent: Harness, Dickey & Pierce, P.L.C

20080054289 - Light emitting device and methods for forming the same: The present invention provides a light emitting device, which includes a transparent substrate, an epitaxial stack structure having a first portion and a second portion on the transparent substrate, a II/V group compound contact layer on the first portion of the epitaxial stack structure, a nitride-crystallized layer on the II/V... Agent: Snell & Wilmer L.L.P. (main)

20080054290 - Light emitting device and the manufacture method thereof: This invention provides a light-emitting element and the manufacture method thereof. The light-emitting element is suitable for flip-chip bonding and comprises an electrode having a plurality of micro-bumps for direct bonding to a submount. Bonding within a relatively short distance between the light-emitting device and the submount can be formed... Agent: Bacon & Thomas, PLLC

20080054287 - Semiconductor light emitting device: A semiconductor light emitting device includes: a body having a recess, a step being provided on a side wall of the recess; a semiconductor light emitting element mounted in the recess; and a resin layer. The resin layer covers at least a portion of an inner surface of the recess... Agent: Amin, Turocy & Calvin, LLP

20080054243 - Switching elements and production methods thereof: The present invention provides switching elements having a readout margin suitable for data storage units of nonvolatile memories, which are obtained by improving the resistance ratio of metal oxide thin films having reversible variable resistance properties. The present invention provides switching elements having a metal oxide consisting of a transition... Agent: Klarquist Sparkman, LLP

20080054247 - Semiconductor layer structure with superlattice: The semiconductor layer structure includes a superlattice (9) composed of stacked layers (9a, 9b) of III-V compound semiconductors of a first (a) and at least one second type (b). Adjacent layers of different types in the superlattice (9) differ in composition with respect to at least one element, at least... Agent: Fish & Richardson PC

20080054249 - Quantum dot based optoelectronic device: A device having an optically active region includes a silicon substrate and a SiGe cladding layer epitaxially grown on the silicon substrate. The SiGe cladding layer includes a plurality of arrays of quantum dots separated by at least one SiGe spacing layer, the quantum dots being formed from a compound... Agent: VistaIPLaw Group LLP

20080054252 - Semiconductor layer structure with over lattice: The semiconductor layer structure includes an active layer (6) and a superlattice (9) composed of stacked layers (9a, 9b) of III-V compound semiconductors of a first (a) and at least one second type (b). Adjacent layers of different types in the superlattice (9) differ in composition with respect to at... Agent: Fish & Richardson PC

20080054253 - Single-electron tunnel junction for a complementary metal-oxide device and method of manufacturing the same: A method of providing a p-type substrate, disposing a pad oxide layer on the p-type substrate, disposing a nitride layer on the pad oxide layer, forming a nitride window in the nitride layer, disposing a field oxide in the nitride window, disposing a polysilicon gate over the field oxide, and... Agent: Texas Instruments Incorporated

20080054258 - Use of perylene diimide derivatives as air-stable n-channel organic semiconductors: The present invention relates to the use of perylene diimide derivatives as air-stable n-type organic semiconductors.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080054259 - Semiconductor component with an electric contact arranged on at least one surface: A semiconductor component includes at least one surface, at least one trench formed in the at least one surface and at least one edge structured and arranged on the at least one surface and formed by the at least one trench. Additionally, the semiconductor component includes an electric contact arranged... Agent: Greenblum & Bernstein, P.L.C

20080054260 - Semiconductor integrated circuit device, method for testing the semiconductor integrated circuit device, semiconductor wafer and burn-in test apparatus: A wafer test is performed to a wafer, and then a protective film is applied to part of a chip surface of each good chip other than terminals. For defective chips, a protective film is applied to an entire chip surface as well as terminals and, while keeping that state,... Agent: Mcdermott Will & Emery LLP

20080054265 - Display device and electronic device: The invention provides a display device and an electronic device, each of which has one of a structure in which a substrate provided with a light emitting element which performs bottom light emission and a substrate provided with a light emitting element which performs top light emission are attached, and... Agent: Fish & Richardson P.C.

20080054266 - Thin film semiconductor device and method for manufacturing thin film semiconductor device: A thin film semiconductor device is provided. The semiconductor device includes a semiconductor thin film configured to have an active region turned into a polycrystalline region through irradiation with an energy beam, and a gate electrode configured to be provided to traverse the active region. Successive crystal grain boundaries extend... Agent: Bell, Boyd & Lloyd, LLP

20080054269 - Method of fabricating a semiconductor device: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate,... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080054272 - Semiconductor light-emitting device and method of manufacturing the same: A semiconductor light-emitting device capable of preventing fusion bonding between electrodes or damage to an electrode, and a method of manufacturing the same are provided. A semiconductor light-emitting device includes a semiconductor layer and a first electrode on a first surface of a semiconductor substrate in order from the semiconductor... Agent: Rader Fishman & Grauer PLLC

20080054277 - Semiconductor laser device: The semiconductor laser device includes an active layer, a p-type cladding layer, and a p-type cap layer. The layers are sequentially stacked so that the semiconductor laser device is provided. The p-type cap layer includes both a p-type dopant and an n-type dopant. In another aspect, the p-type cap layer... Agent: Leydig Voit & Mayer, Ltd

20080054278 - Light-emitting device: A light-emitting device includes a substrate, a first nitride semiconductor stack formed on the substrate, a nitride light-emitting layer formed on the first nitride semiconductor stack, a second nitride semiconductor stack formed on the nitride light-emitting layer, and a first transparent conductive oxide layer formed on the second nitride semiconductor... Agent: Quintero Law Office, PC

20080054286 - Light emitting device packages, light emitting diode (led) packages and related methods: Light emitting device packages, light emitting diode (LED) packages and related methods are disclosed. According to one aspect, a light emitting device package is provided. The package includes a mounting pad adapted for attachment of a light emitting device. A lens coupler is attached to the mounting pad and defines... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20080054282 - Oxynitride-based fluorescent material and method for production thereof: An oxynitride-based fluorescent material is formed of what results from substituting Eu for part of M of a general formula 2MO.Si3N4, wherein M denotes one or more elements selected from among Be, Mg, Ca, Sr and Ba. The oxynitride-based fluorescent material can be produced by a method comprising mixing an... Agent: Sughrue Mion, PLLC

20080054288 - Lighting device package: The present invention provides a lighting device package with one or more light-emitting elements operatively coupled to a substrate and a frame disposed at least in part around the one or more light-emitting elements. The frame and substrate define a cavity in which the one or more light-emitting elements are... Agent: Walker & Jocke, L.p.a.

20080054293 - Nitride semiconductor and method for manufacturing the same: A method of manufacturing a nitride semiconductor substrate is provided. A partial surface treatment process is performed to rough a portion of a surface of a substrate. Next, a nitride semiconductor layer is formed over the substrate. Since the nitride semiconductor layer simply grows on the unroughened surface of the... Agent: Jianq Chyun Intellectual Property Office

20080054294 - Nitride semiconductor substrate and method of manufacturing the same: The present invention relates to a method of forming a nitride semiconductor substrate. This method includes steps of providing a substrate and then forming an epitaxy layer on the substrate. A patterned mask layer is formed on the epitaxy layer, wherein the patterned mask layer exposes a portion of the... Agent: Jianq Chyun Intellectual Property Office

20080054292 - Nitride semiconductor substrate, method for forming a nitride semiconductor layer and method for separating the nitride semiconductor layer from the substrate: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure.... Agent: Jianq Chyun Intellectual Property Office

20080054296 - Nitride-based semiconductor light emitting device and method of manufacturing the same: Provided is a nitride-based semiconductor light emitting device having increased efficiency and power characteristics and method of manufacturing the same. The method may include forming a sacrificial layer on a substrate, forming a passivation layer on the sacrificial layer, forming a plurality of masking dots of a metal nitride on... Agent: Harness, Dickey & Pierce, P.L.C

20080054291 - Vertical semiconductor light-emitting device and method of manufacturing the same: Provided is a vertical semiconductor light-emitting device and a method of manufacturing the same. The method may include sequentially forming a lower clad layer, an active layer, and an upper clad layer on a substrate to form a semiconductor layer and forming first electrode layers on the upper clad layer.... Agent: Harness, Dickey & Pierce, P.L.C

20080054297 - Electrostatic discharge protection circuit using a double-triggered silicon controlling rectifier: An ESD protection circuit using a double-triggered silicon controller rectifier (SCR). The double-triggered silicon controller rectifier (SCR) includes N+ diffusion areas, P+ diffusion areas, a first N-well region, a second N-well region and a third N-well region formed in a P-substrate. The N+ diffusion areas and the P+ diffusion areas... Agent: Jianq Chyun Intellectual Property Office

20080054298 - Power module with laminar interconnect: A power module includes a substrate that includes an upper layer, an electrical insulator and a thermal coupling layer. The upper layer includes an electrically conductive pattern and is configured for receiving power devices. The electrical insulator is disposed between the upper layer and the thermal coupling layer. The thermal... Agent: General Electric Company Global Research

20080054299 - Image sensor and fabricating method thereof: An image sensor includes a photo diode formed over a semiconductor substrate. At least one IMD layer is formed on the semiconductor substrate. A dielectric medium fills a through-hole formed in the IMD layer over the photo diode. The dielectric medium may be made with materials with a higher refractive... Agent: Sherr & Nourse, PLLC

20080054300 - Body contact structure and method for the reduction of drain lag and gate lag in field effect transistors: A field effect transistor is formed on a substrate and includes a semiconductor channel region formed over the substrate and a metallic source region formed on the channel region. A metallic drain region is formed on the channel region and a metallic gate region formed on the channel region between... Agent: Kathy Manke Avago Technologies Limited

20080054302 - Field effect transistor and method of manufacturing the same: Disclosed is a field effect transistor including: an electron supplying layer made of AlGaAs; an interface stabilizing layer, provided on the electron supplying layer, and not containing Al; an etching stop layer, provided on the interface stabilizing layer, and made of TnGaP; and a contact layer, provided on the etching... Agent: Sughrue Mion, PLLC

20080054301 - Mos transistor with in-channel and laterally positioned stressors: A strained channel transistor can be provided by combining a stressor positioned in the channel region with stressors positioned on opposite sides of the channel region. This produces increased strain in the channel region, resulting in correspondingly enhanced transistor performance.... Agent: Slater & Matsil, L.L.P.

20080054303 - Field effect transistor with enhanced insulator structure: A III-nitride based field effect transistor obtains improved performance characteristics through manipulation of the relationship between the in-plane lattice constant of the interface of material layers. A high mobility two dimensional electron gas generated at the interface of the III-nitride materials permits high current conduction with low ON resistance, and... Agent: Ostrolenk Faber Gerb & Soffen

20080054304 - Semiconductor device including a lateral field-effect transistor and schottky diode: A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above... Agent: Slater & Matsil, L.L.P.

20080054305 - Multiple-transistor semiconductor structure: A semiconductor structure is fabricated with two different portions. The first portion forms a first transistor, while the second portion forms a second transistor. Notably, portions of the first transistor also a make up portions of the second transistor. That is, both the first transistor and the second transistor are... Agent: Dla Piper US LLP

20080054306 - Demultiplexers using transistors for accessing memory cell arrays: A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2N semiconductor regions which are parallel to one another and run in a first direction; (c) first N gate electrode lines, which (i) run in a second direction which is perpendicular to the first... Agent: Schmeiser, Olsen & Watts

20080054307 - Power supply wiring configuration in semiconductor integrated circuit: A first intermediate power supply wiring is arranged on an upper layer of a lowest power supply wiring arranged along a first direction. A second intermediate power supply wiring is arranged on an upper layer of the first power supply wiring. A third intermediate power supply wiring is arranged on... Agent: Mcdermott Will & Emery LLP

20080054308 - Crosstalk reduction in electrical interconnects using differential signaling: An electrical device includes a plurality of interconnects passing through a plane. The interconnects have a longitudinal axis substantially perpendicular to the plane and including an arrangement pattern which reduces or eliminates cross-talk between nearest neighboring interconnects, wherein the interconnects include a first differentially driven signal conductor pair and at... Agent: Keusey, Tutunjian & Bitetto, P.C.

20080054309 - High voltage device and manufacturing method thereof: A high voltage device includes a semiconductor substrate and a gate. The semiconductor substrate includes a first doped region having a first conductive type, a second doped region having a second conductive type, a third doped region having the second conductive type, a fourth doped region surrounding the third doped... Agent: Egbert Law Offices

20080054310 - Capacitorless dram memory cell comprising a partially-depleted mosfet device comprising a gate insulator in two parts: The capacitorless DRAM memory cell is constituted by a partially-depleted MOSFET device successively comprising a base substrate, a buried insulator, a floating substrate from semiconducting material including a channel, the gate insulator and a gate. The gate comprises a first zone doped by a first type of dopant and a... Agent: Oliff & Berridge, PLC

20080054311 - Solid-state imaging device and method for manufacturing solid-state imaging device: A plurality of optical sensors (4) are arranged in a surface region of a semiconductor substrate (6) in a matrix pattern, and electric charge generated by the optical sensors (4) is transferred by first and second transfer electrodes (12 and 14) embedded under the optical sensors (4). The semiconductor substrate... Agent: Robert J. Depke Lewis T. Steadman

20080054312 - Junction field effect transistor and production method for the same: A junction field effect transistor of the present invention includes: a first conductivity type semiconductor substrate; a second conductivity type epitaxial layer formed on the semiconductor substrate; a first conductivity type epitaxial layer formed on the second conductivity type epitaxial layer; a second conductivity type source region which penetrates the... Agent: Rabin & Berdo, PC

20080054313 - Device structures including backside contacts, and methods for forming same: The present invention relates to device structures having backside contacts that extend from a back surface of a substrate through the substrate to electrically contact frontside semiconductor devices. The substrate preferably further includes one or more alignment structures located therein, each of which is sufficiently visible at the back surface... Agent: Scully, Scott, Murphy & Presser, P.C.

20080054314 - Field effect transistor having a stressed contact etch stop layer with reduced conformality: By forming a highly non-conformal stressed overlayer, such as a contact etch stop layer, the efficiency of the stress transfer into the respective channel region of a field effect transistor may be significantly increased. For instance, non-conformal PECVD techniques may be used for forming highly stressed silicon nitride in a... Agent: Williams, Morgan & Amerson

20080054315 - Method for manufacturing semiconductor device by using two step pocket implant process: Embodiments relate to a method for manufacturing a semiconductor device by forming a gate pattern over a semiconductor substrate. A material, which has a higher atomic weight than that of a pocket implant dopant, is implanted at an angle or tilt into the respective pocket implant areas at both sides... Agent: Sherr & Nourse, PLLC

20080054316 - Strained fully depleted silicon on insulator semiconductor device: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor... Agent: Law Offices Of Mikio Ishimaru

20080054317 - Image sensor and method for manufacturing the same: An image sensor is provided. The image sensor includes a transistor region over a substrate, an interlayer insulating layer having a via hole over the transistor region, a silicon layer over the interlayer insulating layer, and a photodiode over the silicon layer.... Agent: Sherr & Nourse, PLLC

20080054321 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor for converting an optical signal into an electric signal includes a plurality of unit pixels, each having a photodiode on one side of an active region, a plurality of gate electrodes over the active region, and source/drain region on opposed sides of the gate electrodes, the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080054318 - Golf bag with a carrying system, a lockable stand system, and a recessed stand system: A golf bag is provided including a carrying system having two members attached to a surface of the golf bag and arranged to form an “X” pattern. A casing is affixed to the golf bag and defines a recess in a surface of the golf bag. A stand system is... Agent: Volpe And Koenig, P.C.

20080054320 - Method, apparatus and system providing suppression of noise in a digital imager: Method, apparatus and systems are disclosed in which a digital imager has optically black reference pixels in at least one row of a pixel array. The signals from the reference pixels in one row of the array are used as reference signals to cancel out the row-wise noise from pixel... Agent: Dickstein Shapiro LLP

20080054319 - Transparent-channel thin-film transistor-based pixels for high-performance image sensors: A pixel circuit, and method of forming a pixel circuit, an imager device, and a processing system include a photo-conversion device, a floating diffusion region for receiving and storing charge from the photo-conversion device, and a transparent transistor for use in operation of the pixel, wherein the transparent transistor is... Agent: Dickstein Shapiro LLP

20080054322 - Memory and manufacturing method thereof: A memory is provided. The memory includes a substrate, a number of parallel bit lines, a number of parallel word lines and at least a oxide-nitride-oxide (ONO) structure. The bit lines are disposed in the substrate. The word lines are disposed on the substrate. The word lines are crossed with... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080054323 - Thin film phase change memory cell formed on silicon-on-insulator substrate: A memory cell comprises a semiconductor feature and a phase change material. The semiconductor feature defines a groove that divides the semiconductor feature into a first electrode and a second electrode. The phase change material at least partially fills this groove and acts to electrically couple the first and second... Agent: Ryan, Mason & Lewis, LLP

20080054324 - Integrated circuit including a gate electrode: An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and... Agent: Dicke, Billig & Czaja

20080054325 - Semiconductor device having lateral mos transistor and zener diode: A semiconductor device includes: a semiconductor substrate; a lateral MOS transistor disposed in the substrate; a Zener diode disposed in the substrate; and a capacitor disposed in the substrate. The transistor includes a drain and a gate, and the diode and the capacitor are coupled in series between the drain... Agent: Posz Law Group, PLC

20080054326 - Low resistance contact structure and fabrication thereof: Embodiments of the present invention provide a method of fabricating a contact structure in a layer of dielectric material between a semiconductor device and a back-end-of-line interconnect. The method includes creating at least one contact opening in said layer of dielectric material; forming a first TiN film through a chemical-vapor... Agent: International Business Machines Corporation Dept. 18g

20080054327 - Voltage controller: A voltage controller having an input distribution network with imbedded input switches, a number of charge storage elements such as capacitors, an output distribution network with imbedded output switches, and a switch actuator which controls the input switches and output switches to provide for the controlled charging and discharging of... Agent: J. David Nelson Nelson Snuffer Dahle & Poulsen, P.C.

20080054329 - Semiconductor device and method of fabricating the same: A semiconductor device and methods of fabricating the same, wherein insulation layers are interposed to sequentially dispose the semiconductor device on a semiconductor substrate. The semiconductor device includes a first conductive plate, a second conductive plate, a third conductive plate, and a fourth conductive plate. At least two of the... Agent: F. Chau & Associates, LLC

20080054328 - Semiconductor device and method of manufacturing the same: The method includes the steps of forming an upper electrode of a capacitor by patterning a second conductive film; forming a capacitor dielectric film by patterning a ferroelectric film; and forming a lower electrode by patterning a first conductive film. A step of forming the first conductive film includes the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080054330 - Tantalum lanthanide oxynitride films: Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a tantalum... Agent: Schwegman, Lundberg & Woessner, P.A.

20080054335 - Embedded nv memory and method of manufacturing the same: Disclosed in a non-volatile (NV) memory device and a method of manufacturing the same. The method includes forming transistor and EEPROM regions by implanting first and second conductive impurity ions into a semiconductor substrate, depositing a gate oxide on an entire surface of the semiconductor substrate, forming a first gate... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080054334 - Flash memory device: Embodiments relate to a flash memory device and a method of manufacturing a flash memory device, which may increase a coupling coefficient between a control gate and a floating gate by increasing a surface area of floating gate. In embodiments, a flash memory device may be formed by forming a... Agent: Sherr & Nourse, PLLC

20080054331 - Non-volatile memory cell with metal capacitor: According to one exemplary embodiment, a memory cell in a semiconductor chip includes a non-volatile memory transistor, a control gate, and a floating gate. The control gate is capacitively coupled to the floating gate of the non-volatile memory transistor by a metal capacitor. The metal capacitor can be formed in... Agent: Farjami & Farjami LLP

20080054333 - Semiconductor device and manufacturing method thereof: Provided are a semiconductor device and a manufacturing method thereof. A pair of adjacent gate structure can be formed on a substrate. Mask patterns exposing a portion located between the gate structures are formed. The substrate portion located between the gate structures can be etched using the mask patterns as... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080054332 - Method of depositing nanolaminate film for non-volatile floating gate memory devices by atomic layer deposition: Disclosed herein is a method of depositing a nanolaminate film for next-generation non-volatile floating gate memory devices by atomic layer deposition. The method includes the steps of: introducing a substrate into an atomic layer deposition reactor; forming on the substrate a first high-dielectric-constant layer by alternately supplying an oxygen source... Agent: H.c. Park & Associates, PLC

20080054338 - Flash memory device: Embodiments relate to a flash memory device and a method of manufacturing a flash memory device that may improve a reliability of process by obtaining a Depth of Focus (DOF) in an exposure process. In embodiments, a method may include sequentially stacking an oxide film, a floating gate poly film,... Agent: Sherr & Nourse, PLLC

20080054337 - Flash memory device and method for manufacturing the flash memory device: Disclosed is a flash memory device comprising a semiconductor substrate in which a channel region is formed, an ONO (oxide-nitride-oxide) layer on the semiconductor substrate, a floating gate on the ONO layer, an anti-reflection layer on the floating gate; and a control gate on the anti-reflection layer. The channel region... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080054339 - Flash memory device with single-poly structure and method for manufacturing the same: A flash memory device has a single-poly structure. A method for manufacturing the flash device includes forming an oxide layer over a semiconductor substrate having a P-well region or N-well region. A shallow trench isolation (STI) may be formed in the semiconductor substrate and the oxide layer. A drift region... Agent: Sherr & Nourse, PLLC

20080054336 - Scalable electrically eraseable and programmable memory: A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080054342 - Memory array having floating gate semiconductor device: A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the... Agent: Stephen A. Gratton

20080054340 - Nonvolatile semiconductor memory device including improved gate electrode: A floating gate is formed on a semiconductor substrate via a gate insulating film. Diffused layers are formed as sources or drain regions on opposite sides of the floating gate in the semiconductor substrate. First and second control gates are formed opposite to both of the diffused layers on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080054341 - Semiconductor memory device and method for manufacturing same: A semiconductor memory device includes a plurality of memory transistors. Each of the memory transistors has: a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The floating gate electrode includes, in a cross section taken along a bit line direction, a first conductive film, first sidewall... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080054345 - Electrically erasable and programmable read only memory device and method of manufacturing the same: An electrically erasable and programmable read only memory (EEPROM) device and a method of manufacturing the EEPROM device are provided. First and second gate structures having the same structure are formed on a tunnel insulating layer formed on a substrate, such that the first and second gate structures are spaced... Agent: Mills & Onello LLP

20080054344 - Method of fabricating flash memory device: A method of fabricating a flash memory which increases a coupling ratio between a floating gate and a control gate in a cell. The method comprises sequentially forming a tunnel oxide film, and polysilicon and first insulation films for a floating gate on an active area of a semiconductor substrate;... Agent: Sherr & Nourse, PLLC

20080054343 - Semiconductor device and method for fabricating the same: A semiconductor device and methods of fabricating the same are provided. The semiconductor device can include a tunnel oxide layer on a semiconductor substrate, a floating gate having a top surface with concave-convex shapes on the tunnel oxide layer, an ONO (oxide/nitride/oxide) layer on the floating gate, and a control... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080054346 - Semiconductor device: A semiconductor device capable of realizing low-voltage drivability and large storage capacity (miniaturization) by achieving large threshold voltage shifts and long retention time while at the same time suppressing variations in characteristics among memory cells is disclosed. The device includes a semiconductor memory cell having a channel region formed in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080054347 - Composite stressors in mos devices: A semiconductor device includes a semiconductor substrate, a gate stack on the semiconductor substrate, and a stressor adjacent the gate stack and having at least a portion in the semiconductor substrate, wherein the stressor comprises an element for adjusting a lattice constant of the stressor. The stressor includes a lower... Agent: Slater & Matsil, L.L.P.

20080054348 - Semiconductor device and a method of fabricating the same: A semiconductor device may include a semiconductor substrate with a well area; a conductive body in the well area; a source in the body; a drift region and a drain in a vertical region of the well area other than the body; and a gate electrode between the source and... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080054349 - Reduced-resistance finfets by sidewall silicidation and methods of manufacturing the same: In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided... Agent: Ibm Corporation, Intellectual Property Law

20080054351 - Power semiconductor device and manufacturing method therefor: The semiconductor device includes a set of L-shaped trench gates 3 each formed, from the top-side surface of a p base layer 2, perpendicularly with respect to a first main surface of an n− layer 1, to reach into a location of the n− layer 1. At the lower ends... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080054352 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device including: a semiconductor region having a first semiconductor face and a second semiconductor face connected to the first semiconductor face and having an inclination with respect to the first semiconductor face; a gate insulating film formed on the first and on the second semiconductor faces; a gate... Agent: Sonnenschein Nath & Rosenthal LLP

20080054350 - Vertical field effect transistor arrays and methods for fabrication thereof: Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar.... Agent: Scully Scott Murphy & Presser, PC

20080054354 - Photo mask, semiconductor integrated circuit device, and method of manufacturing the same: A photo mask, a semiconductor integrated circuit, and a method of manufacturing the same are provided. The photo mask includes light transmitting rows and recess trenches, respectively, that include a short region in every other light transmitting row. In the semiconductor integrated circuit, the short region may include a dummy... Agent: Marger Johnson & Mccollom, P.C.

20080054353 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate and recess trenches formed on the semiconductor substrate. The recess trenches are arranged to extend along a first direction. Terminal regions of adjacent ones of the recess trenches are offset relative to each other along a second direction substantially perpendicular to the first... Agent: Marger Johnson & Mccollom, P.C.

20080054355 - Semiconductor device and method of manufacturing the same: s

20080054356 - Semiconductor device and manufacturing method thereof: Under a sidewall formed over a side wall of a gate electrode, a low-concentration LDD region and a high-concentration LDD region which is extremely shallow and apart from a region under the gate electrode are formed. Further, a source/drain region is formed outside these LDD regions. Since the extremely shallow... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080054357 - Semiconductor structure with enhanced performance using a simplified dual stress liner configuration: A semiconductor structure including an nFET having a fully silicided gate electrode wherein a new dual stress liner configuration is used to enhance the stress in the channel region that lies beneath the gate electrode is provided. The new dual stress liner configuration includes a first stress liner that has... Agent: Scully, Scott, Murphy & Presser, P.C.

20080054358 - Thin film transistor and method of manufacturing thin film and thin film transistor: A method of manufacturing a thin film including the steps of: providing a film manufacturing apparatus including a first discharge electrode, a second discharge electrode placed opposed to the first discharge electrode and a high frequency power source, which supplies high frequency power between the first discharge electrode and a... Agent: Brinks Hofer Gilson & Lione

20080054360 - Method and apparatus for regulating photo currents: A method and apparatus for regulating photocurrents is described. A photocurrent regulator may include a transistor having an associated cross-sectional area. The photocurrent regulator is coupled between an integrated circuit and a voltage source. When a dose rate event occurs within the integrated circuit, the photocurrent regulator, via the cross-sectional... Agent: Honeywell International Inc.

20080054359 - Three-dimensional semiconductor structure and method for fabrication thereof: A three-dimensional integrated circuit includes a first device located over a substrate. The first device has a first structure that has a minimum linewidth. The first structure is laterally separated from a first alignment mark also located over the substrate. The three-dimensional integrated circuit also includes a second device located... Agent: Scully, Scott, Murphy & Presser, P.C.

20080054361 - Method and apparatus for reducing flicker noise in a semiconductor device: Some embodiments discussed relate to an integrated circuit and methods for making it, comprises a semiconductor substrate and a plurality of fins disposed on the semiconductor substrate and a gate insulator disposed on the plurality of fins and a gate stack disposed on the gate insulator and the plurality of... Agent: Schwegman, Lundberg & Woessner / Infineon

20080054362 - Semiconductor device and method of manufacturing the same: The method of manufacturing a semiconductor device, including a first region where a transistor including a gate electrode of a stacked structure is formed, a second region where a transistor including a gate electrode of a single-layer structure is formed, and a third region positioned in a boundary part between... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080054363 - Dual gate cmos semiconductor device and method for manufacturing the same: A dual gate Complementary Metal Oxide Semiconductor (CMOS) device includes a gate electrode of PMOS transistor implanted with germanium and indium ions and formed on a gate insulating film; a gate electrode of NMOS transistor not implanted with germanium and indium ions and formed on the gate insulating film; a... Agent: Sherr & Nourse, PLLC

20080054364 - Semiconductor device having cmos device: A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor. The n-channel MIS transistor includes a first source region formed in a semiconductor region on a substrate, a first drain region formed in the semiconductor region apart from the first source region, a first gate insulating film,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080054365 - Semiconductor device and manufacturing method therefor: A element isolation insulating film is formed around the device regions in the silicon substrate. The device regions are formed an n-type diffusion layer region, a p-type diffusion layer region, a p-type extension region, an n-type extension region, a p-type source/drain region, an n-type source/drain region, and a nickel silicide... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080054366 - Cmos semiconductor device having tensile and compressive stress films: A CMOS semiconductor device includes: an isolation region formed in the surface layer of a semiconductor substrate to define an NMOSFET active region and a PMOSFET active region adjacent to each other; an NMOSFET structure formed in the NMOSFET active region; a PMOSFET structure formed in the PMOSFET active region;... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080054367 - Method of forming semiconductor device: Embodiments relate to a method of forming a 90 nm semiconductor device, including forming an isolation film within a semiconductor substrate in which a pMOS region and an nMOS region are defined. A first mask is formed to shield the nMOS region by using a DUV photoresist having a thickness... Agent: Sherr & Nourse, PLLC

20080054368 - Cmos devices adapted to prevent latchup and methods of manufacturing the same: In a first aspect, a first apparatus is provided. The first apparatus is a semiconductor device on a substrate that includes (1) a first metal-oxide-semiconductor field-effect transistor (MOSFET); (2) a second MOSFET coupled to the first MOSFET, wherein portions of the first and second MOSFETs form first and second bipolar... Agent: Ibm Corporation, Intellectual Property Law

20080054369 - Semiconductor device with a field stop zone and process of producing the same: Embodiments discussed herein relate to processes of producing a field stop zone within a semiconductor substrate by implanting dopant atoms into the substrate to form a field stop zone between a channel region and a surface of the substrate, at least some of the dopant atoms having energy levels of... Agent: Schwegman, Lundberg & Woessner, P.A.

20080054370 - Semiconductor device and method of fabricating the same: A semiconductor device include an emitter layer, an emitter electrode containing a metal-semiconductor compound of a metal and a semiconductor, formed on a surface of the emitter layer, and a first reaction suppression layer formed between the emitter layer and the emitter electrode and suppressing permeation of the metal diffused... Agent: Mcdermott Will & Emery LLP

20080054371 - Transistor having a locally provided metal silicide region in contact areas and a method of forming the transistor: By performing a silicidation process on the basis of a patterned dielectric layer, such as an interlayer dielectric material, the respective metal silicide portions may be provided in a highly localized manner at the respective contact regions, while the overall amount of metal silicide may be significantly reduced. In this... Agent: Williams, Morgan & Amerson

20080054372 - Small-pitch three-dimensional mask-programmable memory: The present invention discloses a small-pitch three-dimensional mask-programmable memory (SP-3DmM). It is an ultra-low-cost and ultra-high-density semiconductor memory. SP-3DmM comprises a mask-programmable memory level stacked above the substrate. This memory level comprises diodes but no transistors or antifuses. Its minimum line pitch is smaller than the minimum gate pitch of... Agent: Guobiao Zhang

20080054373 - Power semiconduction device and circuit module having such power semiconduction device: A power semiconductor device includes a semiconductor chip, a first conductive piece, a second conductive piece and an encapsulating resin. The semiconductor chip includes a first electrode and a second electrode. The first conductive piece is in contact with the first electrode of the semiconductor chip. The second conductive piece... Agent: Madson & Austin

20080054374 - Semiconductor device having fin field effect transistor and manufacturing method thereof: A semiconductor device including fin-FETs capable of suppressing both OFF-current resulting from the short channel effect and junction leakage, and a manufacturing method thereof are provided. A semiconductor device comprises: an active region defined to have a crank shape by an STI region formed on a semiconductor substrate, the active... Agent: Mcginn Intellectual Property Law Group, PLLC

20080054375 - Threshold voltage adjustment for long-channel transistors: A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at... Agent: Trask Britt, P.C./ Micron Technology

20080054376 - Semiconductor and method for manufacturing the same: A semiconductor device and a method of fabricating same are provided. According to an embodiment, a gate insulating layer and a gate are sequentially formed on a substrate, and a pocket ion implant region is formed at sides and below a portion of the gate at a predetermined depth in... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080054377 - Semiconductor device and method of manufacturing the same: A semiconductor device and a fabricating method thereof are provided. Barrier patterns are formed between a gate and spacers, and between LDD regions and the spacers, thereby inhibiting impurities of the LDD regions from diffusing into the gate.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080054378 - Semiconductor apparatus and method of manufacturing the semiconductor apparatus: A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080054379 - Semiconductor device: Input circuit ensuring a noise margin for a reference voltage. A semiconductor chip 11a comprises a pad 14 that inputs a reference voltage Vref, an input circuit 13, a resistance element R1 connected between an input terminal of the input circuit 13 and the pad 14, a capacitance element C1... Agent: Sughrue Mion, PLLC

20080054380 - Semiconductor device and method for manufacturing the same: A semiconductor device according to an embodiment includes device isolating layers having a top surface lower than a sheet height of a semiconductor substrate; a gate insulating layer and a gate electrode sequentially stacked on the upper surface of an active region of the semiconductor substrate between the device isolating... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080054381 - Gate electrode of semiconductor device and method of forming same: A method of forming a gate electrode of a semiconductor device includes at least one of the following steps: Forming a gate oxide layer over a wafer substrate. Forming a polysilicon layer over the gate oxide layer. Forming a TiSiN layer over the polysilicon layer. Forming a WSix layer over... Agent: Sherr & Nourse, PLLC

20080054382 - Apparatus and method for microfabricated multi-dimensional sensors and sensing systems: A universal microelectromechanical MEMS nano-sensor platform having a substrate and conductive layer deposited in a pattern on the surface to make several devices at the same time, a patterned insulation layer, wherein the insulation layer is configured to expose one or more portions of the conductive layer, and one or... Agent: Dinsmore & Shohl, LLP

20080054383 - Pressure sensor: A differential pressure sensor includes a micro-electromechanical sensor die fabricated as a plurality of sensor die sites on a semiconductor wafer, and then singularized, the sensor die having a top face surface including die electrical output pads exposed to a first test fluid source and a bottom side surface exposed... Agent: Panitch Schwarze Belisario & Nadel LLP

20080054384 - Semiconductor device and method of manufacturing same: A lead frame which is disposed in an outer package is composed of three members. The lead frame is provided with contact electrodes, connector terminals, and conductive interconnections which are connected to the respective connector terminals. The arrangement order of the contact electrodes is such that contact electrodes are connected... Agent: Rossi, Kimms & Mcdowell LLP.

20080054385 - Magnetoresistive random access memory device with alternating liner magnetization orientation: An arrangement of magnetic liners for the bit lines or word lines of an MRAM device that reduces or eliminates stray magnetic fields at the ends of the magnetic liners, thereby reducing the occurrence of offset fields over portions of the MRAM device due to the magnetic liners is described.... Agent: Slater & Matsil LLP

20080054387 - Image sensor and method for manufacturing the same: An image sensor is provided. The image sensor includes a first passivation layer, a color filter layer, microlenses, an uppermost conducting layer, a second passivation layer, and a third passivation layer. The first passivation layer is formed on a substrate including a predetermined pixel portion and a logic pad portion.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080054388 - Photoelectric conversion device and image sensing system: A photoelectric conversion device is disclosed. The photoelectric conversion device includes a semiconductor substrate having a plurality of photoelectric converters, a multilayer wiring structure arranged on the semiconductor substrate, and a planarized layer arranged on the multilayer wiring structure. The multilayer wiring structure includes a first wiring layer, an interlayer... Agent: Fitzpatrick Cella Harper & Scinto

20080054389 - Planar layer of image sensor, method for manufacturing planer layer, and image sensor including planar layer: An image sensor formed using a method for manufacturing a planar layer in a process for forming microlenses may be used in a complementary metal oxide semiconductor (CMOS) image sensor. Embodiments provide a planar layer that can improve the operation performance of an image sensor, a manufacturing method thereof, and... Agent: Sherr & Nourse, PLLC

20080054386 - Recessed color filter array and method of forming the same: A recessed color filter array using patterned metal as an etch stop and a method of forming the same. In one embodiment, at least one metal etch stop is formed in a semiconductor dielectric layer at the same time as the formation of one or more layers of metal interconnect... Agent: Dickstein Shapiro LLP

20080054390 - Led controller and method using variable drive currents: A system and method is disclosed for illuminating a plurality of emitters such as light emitting diodes (LEDs). The system comprises a plurality of LEDs and a circuit to provide a digital signal. An LED drive circuit is included comprising a first converter for converting the digital signal to one... Agent: Koppel, Patrick & Heybl

20080054391 - Monolithic silicon-based photonic receiver: An integrated circuit, and method for manufacturing the integrated circuit, where the integrated circuit can include a phototransistor comprising a base having a SiGe base layer of a predetermined germanium composition and a thickness of more than 65 nm and less than about 90 nm. The integrated circuit can further... Agent: Burns & Levinson, LLP

20080054392 - Bridge for semiconductor internal node: A method and apparatus for forming connections within a semiconductor device is disclosed. The semiconductor device incorporates a contact bridge between transistor contacts in close proximity. The contact bridge comprises a plurality of metal pillars each having a lower end in electrical contact with first and second transistor elements, respectively;... Agent: International Business Machines Corporation Dept. 18g

20080054393 - Methods of fabricating passive element without planarizing and related semiconductor device: Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in... Agent: Hoffman, Warnick & D'alessandro LLC

20080054394 - Resistance type memory device: A resistance type memory device disposed on a substrate including a first conductive layer, a second conductive layer and a variable resistance material layer is described. These conductive layers are composed of single or separate electrodes. The variable resistance material layer is disposed between the first conductive layer and the... Agent: Jianq Chyun Intellectual Property Office

20080054395 - Semiconductor device and method of manufacturing the semiconductor device: A semiconductor device is provided with a conductor wire and a fuse wire formed in an insulating film over a semiconductor substrate, a first under-pad-wire insulating film formed above the insulating film, a second under-pad-wire insulating film formed on the first under-pad-wire insulating film, a pad wire formed in an... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080054397 - Inductor and method for manufacturing the same: A method for manufacturing an inductor according to the embodiment comprises the steps of: forming a first photoresist pattern; forming an impurity region forming the inductor by implanting an impurity ion to the substrate by means of the first photoresist pattern and a pad region applying current across the impurity... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080054396 - Semiconductor device and fabricating method thereof: A semiconductor device and a fabrication method thereof are provided. An inductor device provided with an inductor cell and a second device having a RF device circuit unit are provided next to each other in the same plane and are electrically connected to each other through a connecting electrode.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080054398 - Method for making high-performance rf integrated circuits: A new method and structure is provided for the creation of a semiconductor inductor. Under the first embodiment of the invention, a semiconductor substrate is provided with a scribe line in a passive surface region and active circuits surrounding the passive region. At least one bond pad is created on... Agent: Mou-shiung Lin Science-based Industrial Park

20080054400 - Capacitor and method of manufacturing the same: Example embodiments relate to a capacitor including p-type doped silicon germanium and a method of manufacturing the capacitor. The capacitor may include a lower electrode, a dielectric layer, an upper electrode, a barrier layer and a capping layer. The lower electrode may have a cylindrical shape. The dielectric layer may... Agent: Harness, Dickey & Pierce, P.L.C

20080054401 - Capacitor structure of semiconductor device: A capacitor structure of a semiconductor device includes: a plurality of first metal elements connected in a vertical direction by first vias; a plurality of second metal elements connected in the vertical direction by second vias and arranged alternately with the first metal elements in a horizontal direction; dielectric materials... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080054399 - Semiconductor device with reliable high-voltage gate oxide and method of manufacture thereof: A semiconductor device including a capacitor and a proximate high-voltage gate having a boron-barrier layer that ideally serves as part of both the capacitor dielectric and the (high voltage) HV gate oxide. The boron-barrier layer is preferably formed over a poly oxide layer that is in turn deposited on a... Agent: Slater & Matsil, L.L.P.

20080054402 - Semiconductor device and method of manufacturing the same: There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080054403 - Thin film capacitors and methods of making the same: An apparatus including a first electrode; a second electrode; a first and second ceramic material disposed between the first electrode and the second electrode, the second ceramic material having a greater electrical conductivity than the first ceramic material. A method including forming a first ceramic material film and a different... Agent: Intel/blakely

20080054404 - Method for designing semiconductor device and semiconductor device: A method for designing a semiconductor device includes: based on information on layout of a resistive element and information on layout of wiring disposed on a layer above the resistive element when seen in section, determining whether or not the resistive element and the wiring overlap each other when seen... Agent: Harness, Dickey & Pierce, P.L.C

20080054405 - Semiconductor devices including resistor elements and related methods: A semiconductor device may include a resistance pattern including a resistance material on a substrate. The resistance pattern may include first and second spaced apart base elements, a bridge element, and first, second, third, and fourth extension elements. The first and second base elements may be substantially parallel, and the... Agent: Myers Bigel Sibley & Sajovec

20080054406 - Method to improve performance of a bipolar device using an amorphizing implant: The invention, in one aspect, provides a semiconductor device that comprises a bipolar transistor located over and within a semiconductor substrate, a collector located within a tub of the bipolar transistor and having an amorphous region formed at least partially therein, a base located over the collector, and an emitter... Agent: Hitt Gaines, PC Lsi Corporation

20080054407 - Semiconductor device and manufacturing method thereof: A semiconductor device and a method for manufacturing the semiconductor device are provided. The method includes forming a collector region of a second conductivity type in a semiconductor substrate of a first conductivity type; forming a base region of the first conductivity type in the collector region, and forming an... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080054408 - Conduction through a flexible substrate in an article: An article includes a first electrically-conductive circuit-path and a second electrically-conductive circuit-path. A portion of the first circuit-path is positioned proximally adjacent a portion of the second circuit-path at a first predetermined hole location. A first electrically-insulating barrier layer is interposed between the first circuit-path and second circuit-path at the... Agent: Kimberly-clark Worldwide, Inc. Catherine E. Wolf

20080054409 - Fabricating method of semiconductor device: A method of fabricating semiconductor device that includes at least one of: Forming a first oxide film on and/or over a semiconductor substrate to partially fill at least one trench formed in the semiconductor substrate. Removing a portion of the first oxide film that is over the semiconductor substrate (e.g.... Agent: Sherr & Nourse, PLLC

20080054410 - Semiconductor device and fabricating method thereof: A semiconductor device for a system-in-a-package (SiP) is provided. The semiconductor device is defined with a plurality of circuit areas where a circuit is to be formed and a scribe lane partitioning a boundary between the circuit areas. A circuit unit is formed in the circuit areas, and a through-electrode... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080054411 - Semiconductor device and method for manufacturing the device: Embodiments relate to a semiconductor device and a method for manufacturing the device, which suppresses off-current by improving the problem of leakage current due to hump characteristics, making it possible to maximize the reliability of the device. Embodiments relate to a method for manufacturing a semiconductor device including forming a... Agent: Sherr & Nourse, PLLC

20080054412 - Reduction of carrot defects in silicon carbide epitaxy: Single crystal silicon carbide epitaxial layer on an off-axis substrate are manufactured by placing the substrate in an epitaxial growth reactor, growing a first layer of epitaxial silicon carbide on the substrate, interrupting the growth of the first layer of epitaxial silicon carbide, etching the first layer of epitaxial silicon... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080054413 - Self-aligned dual segment liner and method of manufacturing the same: A method of forming a dual segment liner covering a first and a second set of semiconductor devices is provided. The method includes forming a first liner and a first protective layer on top thereof, the first liner covering the first set of semiconductor devices; forming a second liner, the... Agent: International Business Machines Corporation Dept. 18g

20080054414 - Method of manufacturing semiconductor device having impurity region under isolation region: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming... Agent: Mcdermott Will & Emery LLP

20080054415 - n-channel field effect transistor having a contact etch stop layer in combination with an interlayer dielectric sub-layer having the same type of intrinsic stress: By forming a tensile silicon dioxide layer on the basis of a sub-atmospheric deposition technique, the strain-inducing mechanism of a tensile contact etch stop layer for N-channel transistors may be significantly improved. Consequently, for otherwise identical stress conditions, the performance of a respective N-channel transistor may be significantly enhanced.... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20080054416 - Photodefinable buffer coating materials: Embodiments of buffer coatings for semiconductor and integrated circuit manufacturing are presented herein.... Agent: Lee & Hayes, PLLC C/o Intellevate

20080054418 - Chip carrier with signal collection tape and fabrication method thereof: A chip carrier for carrying a chip including a carrier and at least one signal collection tape is provided. The carrier has a surface, a die pad and a plurality of inner leads surrounding the die pad, and the signal collection tape is disposed on the surface of the carrier,... Agent: J C Patents, Inc.

20080054417 - Semiconductor die package including stacked dice and heat sink structures: A semiconductor package including stacked packages is disclosed. The semiconductor die package includes a first heat sink structure, a first semiconductor die attached to the first heat sink structure and having a first exterior surface, an intermediate conductive element attached to the first semiconductor die, a second semiconductor die attached... Agent: Townsend And Townsend And Crew, LLP

20080054419 - Semiconductor package: According to the present invention, a semiconductor package includes a semiconductor chip; a base member on which the semiconductor chip is mounted; a plurality of leads formed on the base member, the leads including inner ends electrically connected to the semiconductor chip and outer ends; and an index for identifying... Agent: Volentine & Whitt PLLC

20080054421 - Integrated circuit package system with interlock: An integrated circuit package system is provided including forming a first external interconnect and a die paddle having a slot, forming an inner terminal from a peripheral region of the die paddle, connecting an integrated circuit die and the peripheral region for ground connection, and molding through the slot.... Agent: Law Offices Of Mikio Ishimaru

20080054422 - Semiconductor device: A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result,... Agent: Miles & Stockbridge PC

20080054420 - Semiconductor package structure and method of manufacture: In one embodiment, a semiconductor package includes a lead frame having a lead portion and pad portion that are offset with respect to each other. The lead portion includes a deep formed impression. An up-bent portion connects the lead portion to the pad portion.... Agent: Bradley J. Botsch Semiconductor Components Industries, LLC

20080054423 - Apparatus and method for packaging circuits: Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A. Attn: Timothy B. Clise

20080054425 - Power electronic package having two substrates with multiple electronic components: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and a plurality of electronic components mounted on each of the substrates. The substrates are coupled each other at a plurality of bonding regions so that mechanical separation between the substrates is controlled by the number... Agent: Posz Law Group, PLC

20080054426 - Semiconductor device and manufacturing method thereof: With the objective of enabling a reduction in the size of a final semiconductor device and its thinning, and attaining facilitation of a manufacturing process, the semiconductor device includes a circuit chip having a flat mounted surface, a circuit chip smaller in size than the former circuit chip, and a... Agent: Rabin & Berdo, PC

20080054424 - Semiconductor package and method therefor: In one embodiment, a semiconductor package is formed to include a tamper barrier that is positioned between at least a portion of the connection terminals of the semiconductor package and an edge of the semiconductor package.... Agent: Bradley J. Botsch Semiconductor Components Industries, LLC

20080054427 - Semiconductor devices and manufacturing method therefor: A non-contact identification semiconductor device is provided with a semiconductor chip including a receiving circuit that receives an inquiry to the non-contact identification semiconductor device, a memory that stores identification information of multiple bits and a sending circuit that sends the identification information. An antenna coupled to said semiconductor chip... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080054428 - A stacked-die electronics package with planar and three-dimensional inductor elements: An apparatus and a method for producing three-dimensional integrated circuit packages. In one embodiment, an electronics package with at least two dice are stacked one atop another is disclosed. A top die is of smaller size compared with a bottom die such that after a die attach operation, wire-bond pads... Agent: Schneck & Schneck

20080054431 - Embedded package in package: A stacked chip semiconductor package may be formed in a “package in package” arrangement. The internal package may include two substrates. One substrate may have two dice stacked on each of two opposed sides and the other substrate may have two dice stacked on it as well. The two stacked... Agent: Trop Pruner & Hu, PC

20080054432 - High density stacked die assemblies, structures incorporated therein and methods of fabricating the assemblies: A stacked semiconductor die assembly includes at least two partially offset semiconductor dice with bond pads located adjacent at least one peripheral side thereof supported on a redistribution element formed of a material of substantially similar CTE to that of the dice, and a paddle-less lead frame secured to the... Agent: Trask Britt

20080054433 - Multi-chip package with spacer for blocking interchip heat transfer: A multi-chip package comprises a semiconductor chip stack structure comprising a semiconductor chip stack including a first semiconductor chip having a first power rating and a second semiconductor chip having a second power rating, the first and second semiconductor chips being stacked one on top of another; and a heat... Agent: Volentine & Whitt PLLC

20080054437 - Pop package and method of fabricating the same: A package-on-package (POP) package in which semiconductor packages are stacked using lead lines rather than conventional solder balls, and a fabricating method thereof are provided. According to the POP package and the fabricating method thereof of the present invention, the POP package is prevented from being short-circuited even when an... Agent: Marger Johnson & Mccollom, P.C.

20080054436 - Semiconductor device and fabricating method thereof: A semiconductor device and a fabricating method thereof are provided. A PMD layer is formed on a semiconductor substrate, and at least one IMD layer is formed on the PMD layer. A through-electrode penetrates through the semiconductor substrate, the PMD layer, and each IMD layer, and a heat emission wiring... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080054434 - Semiconductor stack package for optimal packaging of components having interconnections: A stack package comprises a first semiconductor package having a substrate which is formed with a plurality of conductive patterns on a lower surface thereof and with an insulation layer on the lower surface thereof including the conductive patterns, the insulation layer having grooves for exposing the portions of the... Agent: Ladas & Parry LLP

20080054429 - Spacers for separating components of semiconductor device assemblies, semiconductor device assemblies and systems including spacers and methods of making spacers: Preformed dielectric spacers for separating integrated circuit components and methods of forming are disclosed. A spacer wafer may be molded from a dielectric material and subsequently singulated to form a plurality of individual spacers. The molded spacer wafer may be affixed to a die attach film and film frame, and... Agent: Trask Britt, P.C./ Micron Technology

20080054430 - Through board stacking of multiple lga-connected components: A package design is provided where a chip module is connected to a printed circuit board (PCB) via a land grid array (LGA) on the top surface of the PCB, and where a power supply is connected to the PCB via a second LGA on the bottom surface of the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080054435 - Stacked die packages: A stacked die semiconductor package that includes a substrate with a plurality of adhesive portions arranged in a manner to create at least one gap between the adhesive portions. The package also includes a first semiconductor chip having a non-active surface in contact with the adhesive portions, and an active... Agent: Sughrue Mion, PLLC

20080054439 - Power electronic package having two substrates with multiple semiconductor chips and electronic components: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which... Agent: Posz Law Group, PLC

20080054438 - Semiconductor package structure having multiple heat dissipation paths and method of manufacture: In one embodiment, a semiconductor package structure includes a conductive bridge having coupling portions on opposing ends. A lead frame includes alignment or receiving features for receiving the coupling portions of the bridge. A semiconductor device is attached to both the conductive bridge and the lead frame, and is configured... Agent: Bradley J. Botsch Semiconductor Components Industries, LLC

20080054440 - Wire bonding method, wire bonding apparatus and semiconductor device: The wire bonding method includes: a first connecting step of supplying an end of wire for electric wiring to a first electrode on an IC chip and applying vibration to the wire, thereby connecting the end of the wire to the first electrode; a wire stretching step of stretching the... Agent: Kratz, Quintos & Hanson, LLP

20080054441 - Chip package and method for fabricating the same: A method for fabricating chip package includes providing a semiconductor chip with a bonding pad, comprising an adhesion/barrier layer, connected to a pad through an opening in a passivation layer, next adhering the semiconductor chip to a substrate using a glue material, next bonding a wire to the bonding pad... Agent: Megica Corporation

20080054442 - Semiconductor module arrangement and method: A power semiconductor arrangement and method is disclosed. One embodiment provides a power semiconductor module. An insulator is arranged between the module and a cooling element, increasing clearances between the power semiconductor module and the cooling element.... Agent: Dicke, Billig & Czaja

20080054443 - Carrier board structure with semiconductor chip embedded therein: A carrier board structure with semiconductor chip embedded therein is proposed. The carrier board structure includes a carrier board having a first surface and a second surface opposed to the first surface, wherein the carrier board including at least one cavity having a chamfer. A semiconductor chip can be easily... Agent: Mr. Joseph A. Sawyer, Jr. Sawyer Law Group LLP

20080054444 - Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods: Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a semiconductor substrate having integrated circuitry and terminals electrically coupled to the integrated circuitry. The device also includes electrically conductive interconnects extending through at least a portion of the semiconductor substrate... Agent: Perkins Coie LLP Patent-sea

20080054446 - Flexible core for enhancement of package interconnect reliability: An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected... Agent: Intel/blakely

20080054445 - Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. When the substrate and dice are encased during the molding process, the rigid wave... Agent: Vierra Magen/sandisk Corporation

20080054447 - Chip package and digital camera module using same: A digital camera module (200) includes a chip package (20) and a lens module (50) mounted to the chip package. The package includes a carrier (21), a chip (23), a plurality of wires (24), a supporting member (25), an adhesive (26), and a cover (28). The carrier has a top... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20080054448 - Dual heat spreader panel assembly method for bumpless die-attach packages, packages containing same, and systems containing same: A process includes mating a first heat spreader and a second heat spreader, such that the first heat spreader at a mating surface and second heat spreader at a mating surface become parallel and adjacent. The process includes placing a first die in a first die recess of the first... Agent: Schwegman, Lundberg & Woessner, P.A.

20080054449 - Semiconductor component with cooling apparatus: Embodiments of apparatus, having a plastic structure, a semiconductor chip at least partially embedded in the structure; a heat sink at least partially embedded in the structure with a portion thereof projecting from the structure; and a bridge member, at least partially embedded in the structure and thermally coupling the... Agent: Schwegman, Lundberg & Woessner / Infineon

20080054450 - Chip package structure and heat sink for chip package: A chip package structure including a circuit substrate, a chip, a heat sink, and at least one electrical connector is provided. The circuit substrate has a carrying surface and at least one contact disposed on the carrying surface. The chip is disposed on the carrying surface and electrically connected to... Agent: J C Patents, Inc.

20080054451 - Multi-chip assembly: A chip arrangement comprises a first chip with an electrically operable structure on an active surface of the first chip. The first chip is applied on a carrier area in order to make electrical contact with the electrically operable structure via the carrier area. A second chip has a cutout... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080054452 - Microelectronic device having a plurality of stacked microelectronic dies and methods for manufacturing such microelectronic assemblies: Systems and methods for assembling microelectronic devices that have a base die and a conventional wire-bond die stacked on the base die. In one embodiment of a method in accordance with the invention, a base die is placed on a substrate and then a first stacked die is subsequently stacked... Agent: Perkins Coie LLP Patent-sea

20080054453 - Method and structure for implementing component placement suspended within grid array packages for enhanced electrical performance: A method and structure are provided for implementing component placement suspended within electrical pin grid array packages for enhanced electrical performance. A solder column grid array is coupled between a printed circuit board and a first level package. A component is connected between a predefined pair of adjacent columns in... Agent: Ibm Corporation RochesterIPLaw Dept 917

20080054454 - Semiconductor device and method for manufacturing semiconductor device: Disclosed herein is a semiconductor device including: an insulating film configured to be provided on a substrate and be porosified through decomposition and removal of a pore-forming material; a covering insulating film configured to be provided on the insulating film; and conductive layer patterns configured to be provided in the... Agent: Sonnenschein Nath & Rosenthal LLP

20080054455 - Semiconductor ball grid array package: A semiconductor package provides a ball grid array, BGA, formed on a package substrate. The apices of the solder balls of the BGA are all at the same height, even if the package substrate is non-planar. Different solder ball pad sizes are used and tailored to compensate for non-planarity of... Agent: Duane Morris LLPIPDepartment (tsmc)

20080054457 - Semiconductor chip and method for fabricating the same: A semiconductor chip includes a silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and... Agent: Megica Corporation

20080054456 - Semiconductor package including silver bump and method for fabricating the same: A semiconductor package includes a semiconductor chip operatively attached to a conductive lead of a film circuit substrate by an indium-containing solder material and a silver-containing bump electrode, where the solder material is interposed between the conductive lead and the bump electrode.... Agent: Volentine & Whitt PLLC

20080054458 - Electronic device and method of manufacturing the same: An electronic device includes bump electrodes that are formed of an elemental metal having a low melting point and electrically bond a first component and a second component and protective layers that are formed at least on sides of the bump electrodes and prevent penetration of a substance that deteriorates... Agent: Robert J. Depke Lewis T. Steadman

20080054459 - Low fabrication cost, fine pitch and high reliability solder bump: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about... Agent: Mou-shiung Lin

20080054460 - Structure of wafer level package with area bump: A package structure with an area bump has at least a chip (also known as a die), a redistribution layer, a plurality of first bumps (normal bumps) and at least a second bump (area bump). The redistribution layer may reroute and integrate the bonding pads of the chip and incorporate... Agent: Jianq Chyun Intellectual Property Office

20080054462 - Printed circuit board having reliable bump interconnection structure, method of fabricating the same, and semiconductor package using the same: Provided is a printed circuit board having a bump interconnection structure that improves reliability between interconnection layers. Also provided is a method of fabricating the printed circuit board and semiconductor package using the printed circuit board. According to one embodiment, the printed circuit board includes a plurality of bumps formed... Agent: Marger Johnson & Mccollom, P.C.

20080054463 - Semiconductor apparatus and manufacturing method of semiconductor apparatus: The semiconductor apparatus includes: a conductor section provided on a surface of a semiconductor chip so as to input and output an electric signal; and an external connection terminal provided on the surface of the conductor section so as to joint the conductor section to a package substrate, wherein the... Agent: Nixon & Vanderhye, PC

20080054461 - Reliable wafer-level chip-scale package solder bump structure in a packaged semiconductor device: A wafer level chip scale package (WLCSP) includes a packaged semiconductor device with a plurality of solder bump pads, patterned passivation regions above each of the solder bump pads, a patterned under bump metallization (UBM) region on each of the solder bump pads and the passivation regions, a polyimide region... Agent: Hiscock & Barclay, LLP

20080054467 - Method for manufacturing a semiconductor device and semiconductor device: A method for manufacturing a semiconductor device includes: the first step of forming, in an insulating film provided on a substrate, a recess that is porositized at least at inner walls; the second step of forming an alloy layer made of copper and a metal other than copper so as... Agent: Sonnenschein Nath & Rosenthal LLP

20080054466 - Semiconductor device and method of manufacturing semiconductor device: In one aspect of the invention, a method of manufacturing a semiconductor device may include providing a first dielectric layer, providing a trench in the first dielectric layer and a wiring layer which has a Cu in the trench, providing a cap layer on a top surface of the wiring... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080054468 - Semiconductor device and me