Active solid-state devices (e.g., transistors, solid-state diodes) inventions 02/08

20080048164 - Electro-resistance element, method of manufacturing the same and electro-resistance memory using the same: An electro-resistance element that develops less leakage and fewer associated short-circuits even when an electro-resistance layer is made thinner, a method of manufacturing the same and an electro-resistance memory using the same are provided. The electro-resistance element includes a first electrode, a second electrode, an electro-resistance layer stacked between the... Agent: Hamre, Schumann, Mueller & Larson P.C.

20080048165 - Variable resistance element and resistance variable type memory device: A variable resistance element includes: a first electrode; a resistance layer formed on the first electrode; and a second electrode formed on the resistance layer, wherein the resistance layer is composed of transition metal oxide having oxygen defects.... Agent: Harness, Dickey & Pierce, P.L.C

20080048168 - Semiconductor device and manufacture method thereof: A semiconductor device includes an interlayer insulating film formed on a semiconductor substrate to cover a lower electrode, a side-wall insulating film formed on a side wall of a contact hole formed through the interlayer insulating film to a depth reaching the lower electrode, a heater formed in the interior... Agent: Young & Thompson

20080048169 - Heat-shielded low power pcm-based reprogrammable efuse device: An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and... Agent: Cantor Colburn LLP-ibm Yorktown

20080048170 - Semiconductor memory device and fabrication method thereof: A semiconductor memory device comprises a heater electrode, a phase change portion, and an upper electrode. The phase change portion is connected to the heater electrode in a first direction. The upper electrode has an upper surface, a lower surface and a hole. The hole pierces the upper electrode between... Agent: Young & Thompson

20080048172 - Gallium nitride-based compound semiconductor light-emitting device: A gallium nitride compound semiconductor light-emitting device includes a crystalline substrate (10), a light-emiting layer (15) of a quantum well structure which is formed of a gallium nitride compound semiconductor barrier layer and a gallium nitride compound semiconductor well layer, which light-emitting layer is provided on a second side of... Agent: Sughrue Mion, PLLC

20080048175 - Semiconductor superjunction structure: Semiconductor structures and methods are provided for a semiconductor device (54-11, 54-12) employing a superjunction structure (81). The method comprises, forming (52-6) first spaced-apart regions (70-1, 70-2, 70-3, 70-4, etc.) of a first semiconductor material (70) of a first conductivity type, forming (52-9) second spaced-apart regions (74-1, 74-2, 74-3, etc.)... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080048176 - Semiconductor device and method for fabricating the same: A semiconductor device includes a semiconductor superlattice layer and a semiconductor multilayer. The semiconductor superlattice layer has periodic concave-convex shapes, and a plurality of semiconductor films each having bent portions in accordance with the concave-convex shapes are stacked in the semiconductor superlattice layer. The semiconductor multilayer is formed so as... Agent: Mcdermott Will & Emery LLP

20080048177 - Electronic device including a barrier layer and a process for forming the electronic device: An electronic device can include a substrate (12) having a primary surface (14), a second surface (16, 22) opposite the primary surface (14), and an electrode (50). In one embodiment, the electrode (50) can lie adjacent to the second surface (22) and include, a barrier layer (54) lying between a... Agent: Larson Newman Abel Polansky & White, LLP

20080048182 - Display with integral speaker element: A display housing a sound element and a driving circuit that may be built in on the same substrate as the display panel. Thin-film transistors PTFT constituting pixels and a sound wave generation device SPO1 having a laminated structure of a heat generation layer 700, a heat insulation layer 701... Agent: Miles & Stockbridge PC

20080048179 - Hybrid semiconductor-ferromagnet device with a junction structure of positive and negative magnetic-field regions: A hybrid semiconductor-ferromagnet device is a device which has micromagnets (Co) deposited on semiconductor (InAs) two-dimensional electrons, and which has a junction structure of positive and negative magnetic field regions using a stray field resulting from the micromagnets. The magnetoresistance measured in the hybrid semiconductor-ferromagnet device has an asymmetrical hall... Agent: Ostrolenk Faber Gerb & Soffen

20080048184 - Method of forming contact for organic active layer, method of manufacturing flat panel display, organic thin film transistor display, and organic light emitting diode display: A method for forming a contact of an organic active layer is provided. In this method, a transparent conductive oxide thin film is formed on a substrate, and a surface of the oxide thin film is activated by inducing a base —OH and an oxide —O. Then, the oxide thin... Agent: Cantor Colburn, LLP

20080048178 - Tin phosphate barrier film, method, and apparatus: A method is disclosed for inhibiting oxygen and moisture penetration of a device comprising the steps of depositing a tin phosphate low liquidus temperature (LLT) inorganic material on at least a portion of the device to create a deposited tin phosphate LLT material, and heat treating the deposited LLT material... Agent: Corning Incorporated

20080048187 - Semiconductor thin film, thin film transistor, method of manufacturing the semiconductor thin film, method of manufacturing the thin film transistor, and manufacturing device of semiconductor thin film: A semiconductor thin film according to an embodiment of the present invention includes: a polycrystallized semiconductor thin film formed by applying laser light to an amorphous semiconductor thin film; and crystal grains arranged into a lattice shape with a size that is about ½ of an oscillation wavelength of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080048188 - Electronic devices integrated on a single substrate and method for fabricating the same: Electronic devices integrated on a single substrate and a method for fabricating the same are provided. The method includes providing a substrate, and forming at least two electronic devices on the substrate, wherein the at least two electronic devices are selected from a thin film transistor, a memory, a diode,... Agent: Jianq Chyun Intellectual Property Office

20080048190 - Circuit board for electro-optical device, electro-optical device, and electronic apparatus: A circuit board includes: a plurality of data lines and a plurality of scanning lines; a transistor that has a semiconductor layer and a gate electrode. The semiconductor layer includes a first junction region that is formed between the channel region and the data-line-side source/drain region, and a second junction... Agent: Oliff & Berridge, PLC

20080048191 - Organic light emitting display device and method of fabricating the same: A display device includes a substrate having a transistor disposed thereon and including a source/drain electrode connected to the transistor, an intermediate layer disposed on the transistor, the source/drain electrode penetrating the intermediate layer, a light emitting structure disposed on the intermediate layer, the light emitting structure connected to an... Agent: Lee & Morse, P.C.

20080048192 - Led devices and associated methods: Methods for cooling semiconductor devices having a light-emitting surface and associated devices are disclosed and described. Such a device may include a light-emitting surface and a diamond layer disposed on at least a portion of the light-emitting surface. The diamond layer may be exposed to air in order to accelerate... Agent: Thorpe North & Western, LLP.

20080048193 - White light emitting diode module: A white LED module includes a circuit board, a blue LED chip disposed on the circuit board, a green light source of an LED chip or phosphor disposed on the circuit board, and a red light source of an LED chip or phosphor disposed on the circuit board. At least... Agent: Mcdermott Will & Emery LLP

20080048197 - Semiconductor device: A semiconductor is provided with: a silicon substrate 2a of a first conductivity type, including a first surface S1a and a second surface S2a; a silicon layer 4a of a second conductivity type, arranged on the first surface S1a of the silicon substrate 2a, including a third surface S3a opposite... Agent: Drinker Biddle & Reath (dc)

20080048203 - Light emitting apparatus, manufacturing method thereof, and light unit: Provided are a light emitting apparatus and a light unit. The light emitting apparatus comprises a first substrate, a second substrate, and a light emitting device. The first substrate has a plurality of lead frames, and the second substrate has an opening part on the first substrate. The light emitting... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080048199 - Light emitting device and method of making the device: A light emitting device and method of making the device uses an encapsulant to create a hollow region within a chamber of the device. The encapsulant is configured to contact at least a portion of a light source of the device and a portion of a lens of the device.... Agent: Kathy Manke Avago Technologies Limited

20080048201 - Light emitting diode package employing lead terminal with reflecting surface: Disclosed is a light emitting diode (LED) package employing a lead terminal with a reflecting surface. The package includes first and second lead terminals that are spaced apart from each other. The first lead terminal has a lower portion with an LED chip mounting area, and at least one reflecting... Agent: Marger Johnson & Mccollom, P.C.

20080048198 - Omni-directional led light source: A light emitting diode (“LED”) device that emits omni-directional light is disclosed. Such omni-directional LED device may include a LED chip capable of emitting light in all directions. In one example of one implementation, the LED chip is then assembled and sealed inside a casing, such as a glass casing... Agent: Kathy Manke Avago Technologies Limited

20080048202 - Semiconductor light emitting device, method of forming the same, and compound semiconductor device: A semiconductor device may include, but is not limited to, a substrate, a compound semiconductor epitaxial layer, and a first reflecting layer. The substrate may have a main face. The substrate may have at least one cavity that is adjacent to the main face. The compound semiconductor epitaxial layer may... Agent: Wood, Herron & Evans, LLP

20080048205 - Optical semiconductor device and method for making the same: An optical semiconductor device includes an insulating substrate provided with a first electrode and a second electrode each extending from the obverse surface onto the reverse surface of the substrate. The first electrode includes a die-bonding pad extending on the obverse surface of the substrate and a first terminal extending... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20080048204 - Semiconductor light-emitting element assembly: A semiconductor light-emitting element assembly includes: a semiconductor light-emitting element having first and second leads, a semiconductor light-emitting element chip die-bonded to the first lead and wire-bonded to the second lead, a metal body for heat dissipation fixed to the first and second leads via an insulating adhesive layer, and... Agent: Morrison & Foerster LLP

20080048167 - Chalcogenide devices exhibiting stable operation from the as-fabricated state: A chalcogenide material and chalcogenide memory device having less stringent requirements for formation, improved thermal stability and/or faster operation. The chalcogenide materials include materials comprising Ge, Sb and Te in which the Ge and/or Te content is lean relative to the commonly used Ge2Sb2Te5 chalcogenide composition. Electrical devices containing the... Agent: Ovonyx, Inc

20080048166 - Semiconductor integrated circuit device: With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080048171 - Small electrode for phase change memories: A method of manufacturing a memory cell is disclosed. In one embodiment, the method includes forming an electrode including an outer surface that is substantially circular and an exposed surface that has a sublithographic dimension in a direction parallel to the exposed surface. Further, the method may also include forming... Agent: Fletcher Yoder (micron Technology, Inc.)

20080048173 - Semiconductor device including a lateral field-effect transistor and schottky diode: A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above... Agent: Slater & Matsil, L.L.P.

20080048174 - Semiconductor device including a lateral field-effect transistor and schottky diode: A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above... Agent: Slater & Matsil, L.L.P.

20080048185 - Field effect transistor and method of manufacturing the same: s

20080048183 - Organic field-effect transistor and semiconductor device including the same: It is an object to provide an electrode for an organic field-effect transistor having a semiconductor layer formed of an organic semiconductor material (in the present invention, referred to as an organic field-effect transistor), which can reduce the energy barrier at an interface with the semiconductor layer. A composite layer... Agent: Eric Robinson

20080048181 - Organic semiconductor thin film, organic semiconductor device, organic thin film transistor and organic electronic luminescence element: An organic semiconductor thin film, comprising an organic semiconductor compound, wherein the organic semiconductor thin film is manufactured by a process of forming a film by using a solution or a dispersion at room temperature prepared by mixing the organic semiconductor compound and an organic solvent, and the half width... Agent: Cantor Colburn, LLP

20080048180 - Semiconductor device: It is an object of the present invention to provide a semiconductor device in which data can be written except when manufacturing the semiconductor device and that counterfeits can be prevented. Moreover, it is another object of the invention to provide an inexpensive semiconductor device including a memory having a... Agent: Eric Robinson

20080048186 - Design structures incorporating semiconductor device structures with self-aligned doped regions: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes semiconductor device structures with self-aligned doped regions. The semiconductor structure may include first and second doped regions of a first conductivity type defined in the semiconductor material of a... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080048189 - Semiconductor device and method of manufacturing the same: The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode being in contact with the first gate electrode and a gate... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080048196 - Component and process for manufacturing the same: An electrical and/or optical component and a process for manufacturing the component achieve especially good quality in the component and especially reliably avoid crystal dislocations in material layers of the component. In the process for producing a component, at least one trench is etched into a substrate, the trench is... Agent: Lerner Greenberg Stemer LLP

20080048195 - Gan-based light-emitting element and method for producing same: A GaN-based semiconductor light-emitting element capable of suppressing the occurrence of piezoelectric spontaneous polarization in the thickness direction of an active layer and reducing the driving voltage of a light-emitting diode is provided. The GaN-based semiconductor light-emitting element has a structure with a first GaN-based compound semiconductor layer 21 having... Agent: Bell, Boyd & Lloyd, LLP

20080048194 - Nitride semiconductor light-emitting device: A nitride semiconductor light emitting element having a laminate S made of a semiconductor crystal layer, wherein the laminate S includes an n-type layer 2, a light emitting layer 3 and a p-type layer 4. The p-type layer 4 has a p-type contact layer 42 to be in contact with... Agent: Wenderoth, Lind & Ponack, L.L.P.

20080048200 - Led with phosphor tile and overmolded phosphor in lens: Overmolded lenses and certain fabrication techniques are described for LED structures. In one embodiment, thin YAG phosphor plates are formed and affixed over blue LEDs mounted on a submount wafer. A clear lens is then molded over each LED structure during a single molding process. The LEDs are then separated... Agent: Patent Law Group LLP

20080048206 - Vertical gallium nitride-based light emitting diode and method of manufacturing the same: A method of manufacturing a vertical GaN-based LED comprises forming a light emission structure in which an n-type GaN-based semiconductor layer, an active layer, and a p-type GaN-based semiconductor layer are sequentially laminated on a substrate; etching the light emission structure such that the light emission structure is divided into... Agent: Lowe Hauptman Ham & Berner, LLP

20080048207 - Preparation method of a coating of gallium nitride: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080048208 - Electrostatic discharge protection device for an integrated circuit: An integrated circuit is made of a semiconductor material and comprises an input and/or output terminal connected to an output transistor forming a parasitic element capable of triggering itself under the effect of an electrostatic discharge applied to the terminal. The integrated circuit comprises a protection device formed so as... Agent: Seed Intellectual Property Law Group PLLC

20080048209 - Image sensor: An image sensor according to embodiments may include a first substrate having photodiode cells, a second substrate having a logic circuit, and connection electrodes that may electrically connect the photodiode cells with the logic circuit. In embodiments, more area may be available on the first substrate for photodiode cells and... Agent: Sherr & Nourse, PLLC

20080048210 - Semiconductor device and method for making the same: In a MOS-type semiconductor device in which, on a Si substrate (201), a SiGe layer (202) having a valence band edge energy value smaller than a valence band edge energy value of the first semiconductor layer and a mobility larger than a mobility of the first semiconductor layer, a Si... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080048211 - Trench isolated capacitive micromachined ultrasonic transducer arrays with a supporting frame: A one or two-dimensional capacitive micro-machined ultrasonic transducer (CMUT) array with supporting frame is provided. The CMUT array has at least three array elements deposited on a conductive substrate. The invention also has at least one CMUT cell in the array element, a conductive top layer deposited to a top... Agent: Lumen Intellectual Property Services, Inc.

20080048212 - Imaging device: An imaging device includes a first electrode for generating an electric field storing signal charges, a charge multiplication section for multiplying the stored signal charges, a second electrode for generating the electric field in the charge multiplication section, a voltage conversion portion for converting the signal charges into a voltage,... Agent: Ditthavong Mori & Steiner, P.C.

20080048213 - Self-aligned, planar phase change memory elements and devices, systems employing the same and methods of forming the same: Phase change memory elements, devices and systems using the same and methods of forming the same are disclosed. A memory element includes first and second electrodes, and a phase change material layer between the first and second electrodes. The phase change material layer has a first portion with a width... Agent: Dickstein Shapiro LLP

20080048214 - Junction field effect transistor and method of manufacturing the same: According to a junction FET of the present invention, the depth of a channel region is made shallow by selectively performing ion implantation and diffusion. Since the channel region forms a pn junction together with a p type semiconductor layer with relatively low impurity concentration, the improvement in the high... Agent: Morrison & Foerster LLP

20080048215 - Electrical stress protection apparatus and method of manufacture: In various embodiments, circuits and semiconductor devices and structures and methods to manufacture these structures and devices are disclosed. In one embodiment, a bidirectional polarity, voltage transient protection device is disclosed. The voltage transient protection device may include a bipolar PNP transistor having a turn-on voltage of VBE1, a bipolar... Agent: Hvvi Semiconductors, Inc.

20080048218 - Method and flip chip structure for power devices: A lead frame structure for supporting a semiconductor die is disclosed that includes at least two electrical leads each having a plurality of finger shaped structures unilaterally extending outward from the at least two electrical leads. The electrical leads are arranged so that the plurality of finger shaped structures forms... Agent: Perkins Coie LLP Patent-sea

20080048217 - Semiconductor device and method of fabricating the same: A semiconductor device may include a gate pattern formed on a semiconductor substrate. At least one impurity region may be formed in the semiconductor substrate such that at least a portion of the at least one impurity region is disposed under the gate pattern. An epitaxial growth layer may be... Agent: Harness, Dickey & Pierce, P.L.C

20080048216 - Apparatus and method of forming metal oxide semiconductor field-effect transistor with atomic layer deposited gate dielectric: A method for forming a metal oxide semiconductor field-effect transistor (MOSFET) includes forming a III-V compound semiconductor on a substrate with the III-V compound semiconductor being doped with a first dopant type. The method further includes doping a first and second region of the III-V compound semiconductor with a second... Agent: Barnes & Thornburg LLP

20080048219 - Semiconductor device having substrate-driven field-effect transistor and schottky diode and method of forming the same: A semiconductor device including a substrate-driven field-effect transistor with a lateral channel and a parallel-coupled Schottky diode, and a method of forming the same. In one embodiment, the substrate-driven field-effect transistor of the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom... Agent: Glenn W. Boisbrun Slater & Matsil, L.L.P.

20080048220 - Fabricating cmos image sensor: A CMOS image sensor and a fabricating method thereof are provided. The method includes forming a nitride layer over a boundary region between a device isolation region and a pixel region, forming a silicide barrier layer in the pixel region and performing a silicide process. A boundary portion of the... Agent: Sherr & Nourse, PLLC

20080048223 - cmos image sensor and method of fabricating the same: A CMOS image sensor and a fabricating method thereof improves sensitivity to blue light by forming a depletion layer by means of a PN junction in a gate of a drive transistor. The depletion layer formed on the upper portion of the gate improves the sensitivity of the CMOS image... Agent: Sherr & Nourse, PLLC

20080048222 - Bipolar junction transistor and cmos image sensor having the same: Embodiments relate to a horizontal type bipolar junction transistor element (BJT) and a CMOS image sensor having the same to form a photodiode. In embodiments, the bipolar junction transistor as well as collector current may flow uniformly in a horizontal direction, which may increase the entire amount of current. In... Agent: Sherr & Nourse, PLLC

20080048224 - Fabricating cmos image sensor: A CMOS image sensor includes at least one of: A P-type semiconductor substrate. A P-type photodiode formed in the P-type semiconductor substrate and having a higher impurity concentration than the semiconductor substrate. An N-type photodiode disposed over the P-type photodiode at a depth less than approximately 0.15 μm from the... Agent: Sherr & Nourse, PLLC

20080048221 - Image sensor and manufacturing method thereof: Embodiments relate to an image sensor and a method for manufacturing an image sensor. According to embodiments, ions of low concentration may be implanted into a photodiode region of a semiconductor substrate to form a photodiode. At least one gate insulating layer pattern may be formed on the semiconductor substrate,... Agent: Sherr & Nourse, PLLC

20080048225 - Atomic layer deposited barium strontium titanium oxide films: Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium titanium oxide layer, or a combination thereof. Embodiments of methods of fabricating such dielectric layers provide dielectric layers for use in a variety of devices. Embodiments include forming barium... Agent: Schwegman, Lundberg & Woessner, P.A.

20080048227 - Dielectric film, method of manufacturing the same, and semiconductor capacitor having the dielectric film: Provided are a dielectric film, a method of manufacturing the same, and a semiconductor capacitor having the dielectric film. The semiconductor capacitor includes a lower electrode, a ferroelectric layer disposed on the lower electrode, a paraelectric layer disposed on the ferroelectric layer, and an upper electrode disposed on the paraelectric... Agent: Ladas & Parry LLP

20080048226 - Direct cell via structures for ferroelectric random access memory devices and methods of fabricating such structures: Provided are FeRAM device constructions and fabrication methods that provide for the direct connection of metal patterns to ferroelectric capacitors. The FeRAM device constructions utilize a combination of one or more barrier layers incorporated in conductive plugs, barrier layers incorporated in primary conductive patterns or conductive patterns formed using one... Agent: Harness, Dickey & Pierce, P.L.C

20080048228 - Semiconductor device and method for manufacturing same: A semiconductor device 1 includes a region D1 for forming an electric circuit, and a seal ring 30 (guard ring) that surrounds the region D1 for forming the electric circuit. A DRAM 40 is formed in the region D1 for forming the electric circuit. Interlayer insulating films 22, 24, 26... Agent: Sughrue Mion, PLLC

20080048229 - Method for fabricating metallic bit-line contacts: A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080048230 - Semiconductor device and method for manufacturing the same: A semiconductor device including a semiconductor substrate and a recessed transistor provided on the semiconductor substrate, wherein the recessed transistor includes a recess formed in a surface of the semiconductor substrate, an insulating film provided on a surface in the recess, a gate electrode at least partly buried in the... Agent: Scully Scott Murphy & Presser, PC

20080048231 - Buried decoupling capacitors, devices and systems including same, and methods of fabrication: A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in... Agent: Schwegman, Lundberg & Woessner, P.A.

20080048232 - Trench-capacitor dram device and manufacture method thereof: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched... Agent: North America Intellectual Property Corporation

20080048233 - Methods for manufacturing a finfet using a conventional wafer and apparatus manufactured therefrom: A method is provided for producing a fin structure on a semiconductor substrate using a thin SiGe layer to produce a void between a silicon substrate and a silicon fin portion. A fin structure produced by such a method is also provided.... Agent: Joseph P. Abate Intellectual Property Law

20080048234 - Semiconductor memory device and method for fabricating same: A semiconductor memory device has a first interlayer insulating film formed on a semiconductor substrate and having a capacitor opening portion provided in the film, and a capacitance element formed over the bottom and sides of the capacitor opening portion and composed of a lower electrode, a capacitance insulating film,... Agent: Mcdermott Will & Emery LLP

20080048235 - Capacitor structure and method for preparing the same: A capacitor structure comprises a substrate having a contact plug, a conductive cylinder positioned on the substrate and an electroplating structure covering the conductive cylinder, wherein a bottom electrode of the capacitor structure comprises the conductive cylinder and the electroplating structure. The conductive cylinder can be a hollow conductive cylinder,... Agent: Oliff & Berridge, PLC

20080048236 - Parallel varactor capacitor: Provided is a parallel-varactor capacitor. The capacitor comprises a first varactor and a second varactor. The first varactor has a first capacitance which varies depending on voltages applied to a first anode and a first cathode. The second varactor has a second capacitance which varies depending on voltages applied to... Agent: Foley And Lardner LLP Suite 500

20080048238 - Nonvolatile semiconductor memory and method of fabrication thereof: There are provided a nonvolatile semiconductor memory of a structure in which electric signals from peripheral circuits are reliably transferred to control gates via word lines even if contact holes cannot be opened accurately above the word lines, and a method of fabricating the nonvolatile semiconductor memory. Plural word lines... Agent: Rabin & Berdo, PC

20080048237 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes: a source-line-side diode an anode region that is connected to a source line; a bit-line-side diode a cathode region that is connected to a bit line; and memory cell string connected between a cathode region of the source-line-side diode and an anode region of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080048241 - Nonvolatile semiconductor memory device and fabrication method therefor: Disclosed herein is a nonvolatile semiconductor memory device, including a memory transistor. The memory transistor has: a channel formation region defined between two source and drain regions formed on a semiconductor substrate; a bottom insulating film, a charge storage film and a top insulating film formed in order at least... Agent: Rader Fishman & Grauer PLLC

20080048240 - Printed non-volatile memory: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080048239 - Semiconductor memory device having dram cell mode and non-volatile memory cell mode and operation method thereof: A semiconductor memory device may have a DRAM cell mode and a non-volatile memory cell mode without a capacitor, including multiple transistors arranged in an array and having floating bodies, word lines connected to gate electrodes of the transistors, bit lines at a first side of the gate electrodes connected... Agent: Lee & Morse, P.C.

20080048242 - Semiconductor device having load resistor and method of fabricating the same: A semiconductor device includes a semiconductor substrate having a resistor region, an isolation layer disposed in the resistor region, the isolation layer defining active regions, first conductive layer patterns disposed on the active regions, a second conductive layer pattern covering the first conductive layer patterns and disposed on the isolation... Agent: Marger Johnson & Mccollom, P.C.

20080048244 - Nonvolatile memory, nonvolatile memory array and manufacturing method thereof: A nonvolatile memory includes a substrate, stacked gate structures, spacers, control gates, a composite dielectric layer and source region/drain regions. Each of stack gate structures is formed on the substrate and is consisted of a select gate dielectric layer, a select gate and a cap layer. The spacers are disposed... Agent: Jianq Chyun Intellectual Property Office

20080048243 - Nonvolatile semiconductor memory and manufacturing method thereof: A nonvolatile semiconductor memory includes a memory cell string having a plurality of memory cell transistors connected in series, a selection gate transistor connected in series with one end of the memory cell string, and having a gate electrode provided on a gate insulating film on a semiconductor substrate, and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080048245 - Semiconductor device and manufacturing methods thereof: A semiconductor device includes: a substrate having a main surface, a first main electrode formed on the main surface of the substrate, a pillar shaped semiconductor layer formed on the first main electrode and having poly crystal, a second main electrode formed on the pillar shaped semiconductor layer, an insulation... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080048246 - Multi-bit electromechanical memory devices and methods of manufacturing the same: In a memory device and a method of forming the same, in one embodiment, the memory device comprises a substrate and a bit line on the substrate extending in a first direction. A first word line structure is provided on the bit line and spaced apart from, and insulated from,... Agent: Mills & Onello LLP

20080048247 - Semiconductor device and semiconductor device fabrication method: A semiconductor device includes: source/drain regions formed in a semiconductor substrate; a trapping film for storing information by accumulating charges, the trapping film being formed in a region on the semiconductor substrate which includes a region on a channel region between the source/drain regions; and gate electrodes formed on the... Agent: Mcdermott Will & Emery LLP

20080048248 - Semiconductor memory device: Provided is a highly reliable multi-bit memory cell capable of miniaturization including: a semiconductor substrate with a channel formed therein; diffusion layers arranged at two sides of the channel, for serving as source/drain; an insulating film arranged on a part of the channel; a trap film made of an insulating... Agent: Mcginn Intellectual Property Law Group, PLLC

20080048249 - Semiconductor device and method of manufacturing the same: An interface between a bottom oxide film and a silicon nitride film in a neighborhood of a bottom part of a select gate is located at a position as high as or higher than that of an interface between a silicon substrate (p-type well) and a gate insulating film (d≧0)... Agent: Miles & Stockbridge PC

20080048250 - Mosfet with a thin gate insulating film: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the... Agent: Foley And Lardner LLP Suite 500

20080048251 - Lateral trench mosfet with direct trench polysilicon contact and method of forming the same: A lateral trench MOSFET includes a trench containing a device segment and a gate bus segment. The gate bus segment of the trench is contacted by a conductive plug formed in a dielectric layer overlying the substrate, thereby avoiding the need for the conventional surface polysilicon bridge layer. The conductive... Agent: Patentability Associates

20080048252 - Mosfet device suppressing electrical coupling between adjoining recess gates and mthod for manufacturing the same: A MOSFET device comprises a semiconductor substrate having a gate area, a storage node contact area and a bit line contact area. A first groove is defined at a first depth in the gate area and a second groove is defined at a second depth in the bit line contact... Agent: Townsend And Townsend And Crew, LLP

20080048254 - Semiconductor device and manufacturing method of the semiconductor device: A semiconductor device includes a power MOSFET including a trench formed on a surface of a semiconductor layer forming a drain; a gate electrode formed in the trench via a gate insulation film and made of poly-silicon; a channel diffusion layer formed at a surface side of the semiconductor layer... Agent: Cooper & Dunham, LLP

20080048253 - Semiconductor device having a recess channel structure and method for manufacturing the same: A semiconductor device includes a semiconductor substrate having an active region comprising a gate area, a bit line contact area and a storage node contact area. A recess is formed in the gate area and the bit line contact area. A gate is formed over the gate area and a... Agent: Townsend And Townsend And Crew, LLP

20080048255 - Insulated gate semiconductor device: Provided is an insulated gate semiconductor device. In the device, source regions are provided in the entire operation area and a first back gate region is provided below the source region between trenches. Moreover, a second back gate region connected to the first back gate region is provided outside of... Agent: Morrison & Foerster LLP

20080048256 - Semiconductor device: In an n-channel type power MISFET, a source electrode in contact with an n+-semiconductor region (source region) and a p+-semiconductor region (back gate contact region) is constituted with an Al film and an underlying barrier film comprised of MoSi2, use of the material having higher barrier height relation to n-Si... Agent: Miles & Stockbridge PC

20080048257 - Strained semiconductor power device and method: Semiconductor structures (52-9, 52-11, 52-12) and methods (100-300) are provided for a semiconductor devices employing strained (70) and relaxed (66) semiconductors, The method comprises, forming (106, 208, 308) on a substrate (54, 56, 58) first (66-1) and second (66-2) regions of a first semiconductor material (66) of a first conductivity... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080048258 - Trench power device and method: Means and methods are provided for trench TMOS devices (41-10, 11, 12), comprising, providing a first semiconductor (53, 53′) of a first composition having an upper surface (541), with a body portion (54) proximate the upper surface (541), a drift portion (46, 83) spaced apart from the upper surface (541)... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080048262 - Fin field effect transistor and method of forming the same: Provided are a fin field effect transistor (FinFET) with recess source/drain regions, and a method of forming the same. One example embodiment may provide a semiconductor device including a fin provided on a substrate and extending in a first direction, the fin including a stepped portion, and a gate electrode... Agent: Harness, Dickey & Pierce, P.L.C

20080048259 - Method for reducing defects in buried oxide layers of silicon on insulator substrates: A method and a structure for reducing defects in buried oxide layers of a silicon-on-insulator substrate. The method includes: generating a beam of infrared radiation of a selected wavelength; exposing a silicon-on-insulator substrate to the beam of infrared radiation, the substrate comprising a buried silicon dioxide layer between a lower... Agent: Schmeiser, Olsen & Watts

20080048260 - Thin film transistor array panel and method of manufacturing the same: A thin film transistor array panel includes a passivation layer formed on a plurality of end portions of a plurality of gate lines. A portion of the passivation layer has a porous structure formed between a connection portion of a flexible printed circuit substrate and a thin film transistor substrate... Agent: Cantor Colburn, LLP

20080048263 - High-voltage silicon-on-insulator transistors and methods of manufacturing the same: In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions... Agent: Ibm Corporation, Intellectual Property Law

20080048264 - Method for forming pattern of stacked film and thin film transistor: A method for forming a pattern of a stacked film, includes steps (a) to (e). The step (a) is forming sequentially a first base insulating film and a light shielding material on a transparent substrate. The step (b) is patterning the light shielding material to obtain a light shielding film... Agent: Mcginn Intellectual Property Law Group, PLLC

20080048261 - Semiconductor device and method of manufacturing the same: According to an aspect of the present invention, there is provided a semiconductor device including an insulated gate field effect transistor including a gate electrode film formed, via a gate insulating film, on a semiconductor film formed on a support substrate via an insulating film, and a source region and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080048265 - Semiconductor structures integrating damascene-body finfet's and planar devices on a common substrate and methods for forming such semiconductor structures: Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080048266 - Esd protection device and method: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were... Agent: Slater & Matsil LLP

20080048267 - Circuits and methods for improved fet matching: Various embodiments of the present invention provide circuits and methods for improved FET matching. As one example, such methods may include providing two or more transistors. Each of the transistors includes a channel that varies in cross-sectional width from the source to the drain, and the transistors are matched one... Agent: Hamilton And Desanctis

20080048268 - Semiconductor finfet structures with encapsulated gate electrodes and methods for forming such semiconductor finfet structures: Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work function of the gate electrode, is advantageously isolated... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080048269 - Method of fabricating structure for integrated circuit incorporating hybrid orientation technology and trench isolation regions: An embodiment of the present invention discloses a method of fabricating a structure for an integrated circuit incorporating hybrid orientation technology (HOT) and trench isolation regions. The structure of the integrated circuit comprising: a substrate with a first silicon layer of a first crystalline orientation and a second silicon layer,... Agent: Hoffman, Warnick & D'alessandro LLC

20080048270 - Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities: One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to... Agent: Larson Newman Abel Polansky & White, LLP

20080048271 - Structure and method to use low k stress liner to reduce parasitic capacitance: A low k stress liner, which replaces conventional stress liners in CMOS devices, is provided. In one embodiment, a compressive, low k stress liner is provided which can improve the hole mobility in pFET devices. UV exposure of this compressive, low k material results in changing the polarity of the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080048272 - Silicidation monitoring pattern for use in semiconductor manufacturing process: A silicidation monitoring pattern may electrically measure resistance of a polygate line after silicidation to measure open and/or short-circuiting of the polygate line. A silicidation monitoring pattern may minimize production costs. A silicidation monitoring pattern may quickly provide feedback based on a fabrication status.... Agent: Sherr & Nourse, PLLC

20080048273 - Method for doping a fin-based semiconductor device: A method for doping a fin-based semiconductor device is disclosed. In one aspect, the method comprises patterning at least one fin, each fin comprising a top surface and a left sidewall surface and a right sidewall surface. The method further comprises providing a first target surface being the right sidewall... Agent: Knobbe Martens Olson & Bear LLP

20080048274 - Semiconductor device including a gate electrode of lower electrical resistance and method of manufacturing the same: A semiconductor device may include a gate insulating layer on a semiconductor substrate, a polysilicon layer doped with impurities on the gate insulating layer, an interface reaction preventing layer on the polysilicon layer, a barrier layer on the interface reaction preventing layer, and a conductive metal layer on the barrier... Agent: Harness, Dickey & Pierce, P.L.C

20080048275 - Mos transistor, semiconductor device, and method of manufacturing the same: In a MOS transistor having a structure in which a source and a drain are raised on a substrate by using a selective epitaxial growth technique, a bulk resistance can be reduced while an impurity concentration of a silicon layer is reduced in the selective epitaxial growth. A metal oxide... Agent: Sughrue Mion, PLLC

20080048277 - Gate of a transistor and method of forming the same: A gate of a transistor includes a gate oxide layer formed on a semiconductor device, a first conductive layer pattern including polysilicon doped with boron and formed on the gate oxide layer, a diffusion preventing layer pattern including amorphous silicon formed by a chemical vapor deposition process using a reaction... Agent: Harness, Dickey & Pierce, P.L.C

20080048276 - Semiconductor device and method for manufacturing the same: A semiconductor device is provided including a transistor element on a substrate, a silicide on a gate and a source/drain of the transistor element; and an amorphous capping layer on the silicide.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080048278 - Method of forming pattern of inorganic material film and structure containing the pattern: A method of forming a pattern of an inorganic material film, which method is more versatile, easy, and practical. The method includes the steps of: (a) forming a sacrifice layer having a pattern on a substrate by employing a material having a different thermal expansion coefficient from that of an... Agent: Sughrue Mion, PLLC

20080048279 - Process for producing semiconductor substrate, semiconductor substrate for solar application and etching solution: Provided is: a process for producing safely at low cost a semiconductor substrate excellent in photoelectric transduction efficiency, in which a fine uneven structure suitable for a solar cell can be formed uniformly with desired size on the surface of the semiconductor substrate; a semiconductor substrate for solar application in... Agent: Marger Johnson & Mccollom, P.C.

20080048281 - Image sensor and fabricating method thereof: An image sensor according to embodiments may include a semiconductor substrate having a photo diode area formed thereon, a pre-metal dielectric (PMD) layer formed on the semiconductor substrate, at least one metal layer formed on the PMD layer, and a plurality of waveguides formed to penetrate through the metal layer... Agent: Sherr & Nourse, PLLC

20080048283 - Image sensor and fabricating method thereof: An image sensor is provided. The image sensor can include an isolation layer, a transistor region, and a photodiode region on a semiconductor substrate. A plurality of holes can be formed in the substrate of the photodiode region. The plurality of holes can be densely formed in the substrate. At... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080048284 - Image sensor and fabrication method thereof: An image sensor includes a semiconductor substrate having a pixel region and a peripheral region defined therein and having a pixel array formed in the pixel region; a PMD layer formed on the semiconductor substrate; at least one IMD layer formed over the PMD layer, wherein a region of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080048282 - Semiconductor device and fabricating method thereof: A semiconductor device for a system in a package (SiP) type device can include a semiconductor substrate; a pre-metal-dielectric (PMD) layer on the semiconductor substrate; at least one metal layer on the PMD layer; a first through-electrode extending through the semiconductor substrate and the PMD layer; and a second through-electrode... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080048280 - Light receiving device, method for fabricating same, and camera: The light receiving device of the present invention includes: a light receiving portion formed on a semiconductor substrate; and a light transmitting portion made of an organic material on an optical path reaching the light receiving portion, and the light transmitting portion contains heavy hydrogen. In the case where an... Agent: Hamre, Schumann, Mueller & Larson P.C.

20080048285 - Laminated wafer sensor system for uv dose measurement: A laminated wafer sensor structure includes a housing layer having pocket openings formed therein, a circuit layer having a sensor element and electronic components mounted for registration with the pocket openings in the housing layer, and a rigid back layer. The laminated structure is suitable for handling by conventional robotic... Agent: Stallman & Pollock LLP

20080048286 - Coplanar silicon-on-insulator (soi) regions of different crystal orientations and methods of making the same: In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI... Agent: Ibm Corporation, Intellectual Property Law

20080048287 - Isolation structures for integrated circuits and modular methods of forming the same: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall... Agent: Patentability Associates

20080048289 - Rf inductor of semiconductor device and fabrication method thereof: An RF inductor of a semiconductor device and a method of fabricating the same are provided. First and second interlayer dielectric layers are formed on an insulating layer and a lower metal interconnection. A via hole and a spiral-shaped trench are formed in the first and second interlayer dielectric layers.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080048288 - Semiconductor device: Embodiments relate to a semiconductor device and a fabrication method thereof. According to embodiments, the semiconductor device may includes a first substrate including an inductor cell, a second substrate including a RF (radio frequency) device circuit having a transistor and a wire, and a connection electrode for electrically connecting the... Agent: Sherr & Nourse, PLLC

20080048292 - Electronic device and manufacturing method thereof: In a BST thin film being a capacitor film in a capacitor element, the capacitor film is formed such that two kinds of chemical states of Sr(I) and Sr(II) exist at a portion of which depth is up to 2.5 nm from a surface thereof (surface layer portion of which... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080048290 - Semiconductor device and fabricating method: A semiconductor device and a relatively simple fabrication process which may maximize fabrication yield. A semiconductor device may include at least one of the following: A first substrate including a capacitor cell. A second substrate including a circuit unit having a transistor and a wire. A connection electrode which electrically... Agent: Sherr & Nourse, PLLC

20080048291 - Semiconductor interconnection structures and capacitors including poly-sige layers and metal contact plugs, and methods of fabricating the same: A semiconductor device includes a lower electrode of a capacitor, a dielectric layer disposed on the lower electrode, and an upper electrode of the capacitor disposed on the dielectric layer. The upper electrode includes a doped poly-Si1-xGex layer. An interlayer insulating layer is disposed on the doped poly-Si1-xGex layer and... Agent: Myers Bigel Sibley & Sajovec

20080048293 - Semiconductor device having heating structure and method of forming the same: A semiconductor device includes a lower electrode including a bottom wall portion and a sidewall portion extending upwardly from the bottom wall portion, and an insulating layer located over a top edge surface of the sidewall portion of the lower electrode. The insulating layer includes a contact window which partially... Agent: Volentine & Whitt PLLC

20080048294 - Semiconductor device with guard ring: A semiconductor device includes a semiconductor substrate; a circuit; a guard ring; a power source line; and a contact. The semiconductor substrate has a first conductive type. The circuit is formed on the semiconductor substrate. The guard ring is formed on the semiconductor substrate such that the guard ring surrounds... Agent: Young & Thompson

20080048295 - Insulated gate semiconductor device and method for manufacturing the same: There is provided a structure wherein an emitter layer 3 is provided in the region A on the first major surface side of a semiconductor substrate 1, and emitter layer 3 is not provided in the region b. There is provided a structure wherein a collector P layer 5 is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080048296 - Vertical bjt, manufacturing method thereof: A vertical BJT which has a maximal current gain for a photodiode area. According to embodiments, since the BJT can be formed together with the photodiode, and collector current flows up and down based on the double base structure, the magnitude of the current may be increased.... Agent: Sherr & Nourse, PLLC

20080048297 - Embedded interconnects, and methods for forming same: The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive interconnect structure that is embedded in the isolation region... Agent: Scully, Scott, Murphy & Presser, P.C.

20080048298 - Semiconductor devices, assemblies and constructions, and methods of forming semiconductor devices, assemblies and constructions: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the... Agent: Wells St. John P.s.

20080048299 - Electronic component with semiconductor chips, electronic assembly composed of stacked semiconductor chips, and methods for producing an electronic component and an electronic assembly: An electronic component includes a semiconductor chip with an active front face and a passive rear face, with contact connections and contact surfaces respectively being provided on the active front face and/or on the passive rear face, and with conductive connections being provided in the form of structured conductive tracks... Agent: Lerner Greenberg Stemer LLP For Infineon Technologies Ag

20080048300 - Silicon epitaxial wafer and method for manufacturing the same: This method for manufacturing a silicon epitaxial wafer includes: a step of growing an epitaxial layer having silicon on a silicon wafer having a main surface of {110}; and a cooling step of cooling the silicon wafer after growing the epitaxial layer. In a first aspect, in the cooling step,... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20080048301 - Pre-encapsulated lead frames for microelectronic device packages, and associated methods: Pre-encapsulated lead frames suitable for use in microelectronic device packages are disclosed. Individual lead frames can include a set of multiple lead fingers arranged side by side with neighboring lead fingers spaced apart from each other by a corresponding gap. An encapsulating compound at least partially encapsulates the set of... Agent: Perkins Coie LLP Patent-sea

20080048302 - Systems and methods for low profile die package: A semiconductor integrated circuit (IC) device is defined by a low-profile package without a die attach pad (DAP). In place of the DAP, an adhesive element is used to retain a die relative to a lead frame during processing. In one example, a method of manufacturing the device includes sealing... Agent: Kathy Manke Avago Technologies Limited

20080048303 - Semiconductive device having improved copper density for package-on-package applications: In one aspect, the invention provides a semiconductor device that comprises a semiconductor device packaging substrate core. A first interconnect structure is located within a mold region and on a die side of the substrate core and has a first conductive metal density associated therewith. A second interconnect structure is... Agent: Texas Instruments Incorporated

20080048304 - Heat slug for package structure: A heat slug is provided for a package structure, including a main body and a plurality of protrusions. The main body has a surface in which at least one ditch is defined. Each protrusion is connected to and extends from the main body and has a surface in which a... Agent: Madson & Austin

20080048305 - Negative thermal expansion system (ntes) device for tce compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging: A Negative Thermal Expansion system (NTEs) device for TCE compensation or CTE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging. One aspect of the present invention provides a method for fabricating micromachine devices that have negative thermal expansion coefficients that can be made into a composite for... Agent: F. Chau & Associates, LLC

20080048306 - Electro-chemical processor: A processor for making porous silicon or processing other substrates has first and second chamber assemblies. The first and second chamber assemblies include first and second seals for sealing against a wafer, and first and second electrodes, respectively. The second seal is moveable towards and away from a wafer in... Agent: Perkins Coie LLP/semitool

20080048307 - Module and mounted structure using the same: A module that can not only achieve the reduction in size and manufacturing cost but also be impervious to noise due to electromagnetic waves, and a mounted structure using the same are provided. A module (1) includes a substrate (12) and a plurality of semiconductor packages (11a, 11b), each including... Agent: Hamre, Schumann, Mueller & Larson P.C.

20080048309 - Metal core foldover package structures, systems including same and methods of fabrication: Chip scale packages and assemblies thereof and methods of fabricating such packages including Chip-On-Board, Board-On-Chip, and vertically stacked Package-On-Package modules are disclosed. The chip scale package includes a core member of a metal or alloy having a recess for at least partially receiving a die therein and includes at least... Agent: Trask Britt

20080048308 - Stackable packages for three-dimensional packaging of semiconductor dice: An apparatus and a method for packaging semiconductor devices. The apparatus includes a substrate strip component of a leadless three-dimensional stackable semiconductor package having mounting contacts on, for example, four peripheral edges. The substrate strip may either be fabricated for mounting a single electrical component (e.g., an integrated circuit die)... Agent: Schneck & Schneck

20080048310 - Carrier board structure embedded with semiconductor component and method for fabricating the carrier board structure: A carrier board structure with a semiconductor component embedded therein and a method for fabricating the same are proposed. The method provides at least one semiconductor component and a carrier having a first surface and a second surface opposed to the first surface and at least one through hole. The... Agent: Fulbright And Jaworski LLP

20080048311 - Semiconductor device, substrate for producing semiconductor device and method of producing them: A substrate B for use in production of a semiconductor device is used, which substrate includes an adhesive sheet 50 having a base layer 51 and an adhesive layer 52, and a plurality of independently provided electrically conductive portions 20. A semiconductor element having electrodes 11 formed thereon is firmly... Agent: Oliff & Berridge, PLC

20080048312 - Semiconductor package and method for manufacturing the same: A semiconductor package comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an active surface, a back surface opposite to the active surface, an optical component disposed on the active surface, and a... Agent: Reed Smith LLP

20080048313 - Wafer bonding method: One embodiment of a micro-electronic device includes a substrate including micro-electronic components thereon, and a cover including a ring of sealing material secured to the substrate and a raised ring of material positioned opposite the cover from the ring of sealing material.... Agent: Hewlett Packard Company

20080048314 - Integrated circuit cooling and insulating device and method: A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a... Agent: Schwegman, Lundberg & Woessner/micron

20080048315 - Electronic device and package used for the same: [SOLUTION A laminate ceramic electronic device of the present invention has filter chips 2, 3 for transmission and reception mounted therein. A wiring pattern 7, which connects an input terminal A of the transmission filter chip 2 with a transmission side signal terminal Tx in a first arrangement, has two... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080048316 - Packaged microdevices and methods for manufacturing packaged microdevices: Microdevices and methods for packaging microdevices. One embodiment of a packaged microdevice includes a substrate having a mounting area, contacts in the mounting area, and external connectors electrically coupled to corresponding contacts. The microdevice also includes a die located across from the mounting area and spaced apart from the substrate... Agent: Perkins Coie LLP Patent-sea

20080048318 - Semiconductor device and semiconductor package: For delivering supply power evenly into chip, a semiconductor device includes plural power supply pads 17a and grounding pads 18a, arranged in alternation in X-direction. The device also includes first upper layer power supply wire 17b, extending in X-direction and connected to first ends of the power supply pads 17,... Agent: Young & Thompson

20080048319 - Semiconductor device having pads: A semiconductor device having pads is provided. The semiconductor device includes first pads formed along a first row, and second pads formed along a second row. The first via contact portions extending from the first pads toward the second row, and second via contact portions extending from the second pads... Agent: Harness, Dickey & Pierce, P.L.C

20080048317 - Electric component with a flip-chip construction: A component includes a carrier substrate having a coefficient of thermal expansion αp and a chip mounted on the carrier substrate by a plurality of bumps. The chip has a first coefficient of thermal expansion α1 in a first direction x1 and a first expansion difference, Δα1 equal to the... Agent: Fish & Richardson PC

20080048320 - Low fabrication cost, fine pitch and high reliability solder bump: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about... Agent: Mou-shiung Lin

20080048321 - Flip chip semiconductor assembly with variable volume solder bumps: A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column... Agent: Vedder Price Kaufman & Kammholz

20080048323 - Stacked structure of chips and wafer structure for making the same: A stacked structure of chips including a first chip, a second chip, an insulation layer and a first conductive element is provided. The second chip is attached to the first chip, and the back surface of the second chip faces an active surface of the first chip. The second chip... Agent: Birch Stewart Kolasch & Birch

20080048322 - Semiconductor package including redistribution pattern and method of manufacturing the same: A semiconductor device package includes a substrate, first and second chip pads spaced apart over a surface of the substrate, and an insulating layer located over the surface of the substrate. The insulating layer includes a stepped upper surface defined by at least a lower reference potential line support surface... Agent: Volentine & Whitt PLLC

20080048324 - Fabricating semiconductor device: A method for fabricating a semiconductor device is provided. The method includes: etching an area where a plurality of modules are formed on a semiconductor substrate; forming a plurality of modules on the area; forming on insulation layer on the substrate; forming a plurality of contacts that contact a plurality... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080048326 - Semiconductor device: According to embodiments, a semiconductor device may include a PMD layer provided with a contact, and a wiring layer formed on the PMD layer and connected to the contact by stacking and forming a plurality of metal layers thereon. In embodiments, the plurality of metal layers may include a first... Agent: Sherr & Nourse, PLLC

20080048325 - Semiconductor device and fabricating method thereof: A method of effectively fabricating a semiconductor device involves separately fabricating a first substrate having a transistor layer and a second substrate having a metal wire layer, and stacking the first and second substrates. A transistor on the first substrate is electrically connected to a metal wire on the second... Agent: Sherr & Nourse, PLLC

20080048327 - Electronic circuit with embedded memory: Circuitry includes first and second circuits spaced apart by an interconnect region. The interconnect region includes a first interconnect and the second circuit includes a stack of semiconductor layers. The first interconnect extends between the first and second circuits to provide communication therebetween. The second circuit operates as a memory... Agent: Schmeiser Olsen & Watts

20080048328 - Chip structure and process for forming the same: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric... Agent: Mou-shiung Lin

20080048329 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20080048330 - Implantable microelectronic device and method of manufacture: An implantable hermetically sealed microelectronic device and method of manufacture are disclosed. The microelectronic device of the present invention is hermetically encased in a insulator, such as alumina formed by ion bean assisted deposition (“IBAD”), with a stack of biocompatible conductive layers extending from a contact pad on the device... Agent: Scott B. Dunbar Second Sight Medical Products, Inc.

20080048332 - Method for forming intermetal dielectric in semiconductor device: A method for forming an intermetal dielectric in a semiconductor device includes the steps of: forming metal wiring patterns electrically connecting circuit devices on a silicon substrate provided with the predetermined semiconductor circuit devices; forming a first silicon oxide film electrically isolating the metal wiring patterns; forming a second silicon... Agent: Sherr & Nourse, PLLC

20080048331 - Power/ground network of integrated circuits and arrangement thereof: An arrangement scheme for a power/ground (P/G) network of an integrated circuit is provided. Rows of standard cells in the integrated circuit are horizontally arranged. The P/G network has horizontal and vertical metal lines arranged in different metal layers. The horizontal metal lines have horizontal power metal lines and horizontal... Agent: Wpat, PC

20080048333 - Semiconductor device having buried word line interconnects and method of fabricating the same: A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate... Agent: Myers Bigel Sibley & Sajovec

20080048334 - Semiconductor devices and methods of fabricating the same: Embodiments include a semiconductor device comprising: a pad formed on an insulating layer and having an electric connection region with external components; and a protective insulating layer which has an aperture for exposing the electric connection region. The protective insulating layer may include a first insulating layer and a second... Agent: Konrad Raynes & Victor, LLP

20080048339 - Metal line structures and methods of forming the same: Example embodiments may provide metal line structures, and example methods may include forming the same. Example embodiment metal line structures may include a first metal line on a substrate, a first barrier metal layer on sidewalls and a lower surface of the first metal line, a first insulating layer covering... Agent: Harness, Dickey & Pierce, P.L.C

20080048335 - Semiconductor device: A semiconductor device according to embodiments may include an interposer, a plurality of devices stacked and formed on the interposer, through electrodes each formed in the plurality of devices and formed by penetrating through the respective devices, and connecting electrodes formed between the respective devices and connecting a through electrode... Agent: Sherr & Nourse, PLLC

20080048338 - Semiconductor device and fabrication method thereof: A semiconductor device and a fabricating method thereof are provided. An insulating layer pattern has a via hole exposing a lower metal layer, and a copper via is provided inside the via hole. A TiSiN layer is disposed on the insulating layer pattern and the copper via, and an interconnection... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080048336 - Semiconductor device and method for manufacturing the same: A semiconductor device and method for manufacturing the same are provided, capable of narrowing feature size by utilizing the property of oxidation of a material. In one method, a polysilicon layer can be patterned into a fine pattern up to a critical dimension using a photolithography process. Then the patterned... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080048337 - Semiconductor device including through electrode and method of manufacturing the same: The present invention provides a semiconductor device including at least one of an insulating layer and a semiconductor layer each including a hole formed therein, and a through electrode provided in the hole. In the semiconductor device, the side wall of the hole is constituted of a first region from... Agent: Young & Thompson

20080048340 - Semiconductor device having fine pattern wiring lines integrally formed with contact plug and method of manufacturing same: A semiconductor device and method are disclosed in which an interlayer insulating layer is patterned using multiple overlaying masks to define the geometry of contact plugs and corresponding wiring layers separated by fine pitches.... Agent: Volentine & Whitt PLLC

20080048341 - Chip with a vertical contact structure: A chip with a chip plane includes a functional area, a contact structure vertical with respect to the chip plane for connecting the functional area, which includes a conductive material, which has a predetermined length, and a vertical dummy-contact structure, which extends vertically into the functional area and which has... Agent: Dickstein Shapiro LLP

20080048342 - Multi-chip module: A multi-chip module that includes a conductive element connecting at least two semiconductor devices, the conductive element including enhancements for improving the mechanical coupling between the conductive element and the molded housing of the MCM.... Agent: Ostrolenk Faber Gerb & Soffen

20080048343 - Thin flip-chip method: Methods for thinning a bumped semiconductor wafer, as well as methods for producing flip-chips of very thin profiles, are disclosed. According to the methods of the present invention, a mold compound is interspersed between conductive bumps on the active face of a wafer to provide support and protection for the... Agent: Trask Britt, P.C./ Micron Technology

20080048345 - Semiconductor device and fabricating method thereof: A semiconductor device that allows an image sensor (in an upper area of a SiP semiconductor device) to exchange signals with a device in a lower area of a SiP semiconductor device. A semiconductor device includes at least one of: A semiconductor substrate having a photodiode area and a transistor... Agent: Sherr & Nourse, PLLC

20080048344 - High performance ic package and method: A novel wire-based interconnect IC package is described as well as the method of designing and the method of producing the IC package. The IC package includes one or more signal carrying wires as well as ground return wires associated with each signal carrying wire to electrically couple a chip... Agent: Hayes Soloway P.C.

20080048346 - Method of fabricating conductive lines and structure of the same: A method of forming a conductive line suitable for decreasing a sheet resistance of the conductive lines. The method comprises steps of providing a material layer having a conductive layer formed thereon and forming a patterned mask layer on the conductive layer. In addition, a portion of the conductive layer... Agent: J.c. Patents

20080048347 - Display device and manufacturing method thereof: The present invention provides a manufacturing method of a display device which can efficiently separate individual thin-thickness display devices from a large-sized mother substrate. Scribe marks for separating a plurality of display devices are preliminarily formed on back surfaces of a TFT mother substrate and a sealing mother substrate. By... Agent: Reed Smith LLP

20080042117 - Phase-change memory and fabrication method thereof: A phase-change memory and fabrication method thereof are disclosed. The phase-change memory comprises a first dielectric layer with a first opening formed on a substrate. A first electrode is filled into the first opening. A second dielectric pillar is formed on the first electrode. A first conducting layer is formed... Agent: Quintero Law Office, PC

20080042121 - Method for deposition of magnesium doped (al, in, ga, b)n layers: A method for growing an improved quality device by depositing a low temperature (LT) magnesium (Mg) doped nitride semiconductor thin film. The low temperature Mg doped nitride semiconductor thin film may have a thickness greater than 50 nm. A multi quantum well (MQW) active layer may be grown at a... Agent: Gates & Cooper LLP Howard Hughes Center

20080042123 - Methods for controlling thickness uniformity of sige regions: An integrated circuit includes a semiconductor substrate having a first region, at least one p-type region in the semiconductor substrate having SiGe regions formed therein, and at least one n-type region in the semiconductor substrate. All SiGe regions in the first region have a first combined area. All p-type regions... Agent: Slater & Matsil, L.L.P.

20080042130 - Semiconductor device, electronic device, and electronic equipment: A semiconductor device includes: an organic semiconductor layer made of an organic semiconductor material; a gate electrode for applying an electric field to the organic semiconductor layer; a first insulating layer insulating the gate electrode from the organic semiconductor layer; and a second insulating layer. The organic semiconductor layer is... Agent: Oliff & Berridge, PLC

20080042127 - Transition metal free coupling of highly fluorinated and non-fluorinated pi-electron systems: A method for making an organic conjugated monomer, oligomer, polymer or small molecule includes reacting a silyl substituted pi-system compound with a highly fluorinated pi-system compound.... Agent: King & Schickli, PLLC

20080042134 - Array substrate for liquid crystal display device and method of fabricating the same: An array substrate for a liquid crystal display device includes a gate line and a data line crossing each other on a substrate to define a pixel region, an insulating layer between the gate line and the data line, a gate electrode extending from the gate line, and a transistor... Agent: Seyfarth Shaw, LLP

20080042132 - Display panel and method for manufacturing the same: A display panel includes a substrate having a display area and a blank area. The blank area includes at least one of a non-metal line region and a metal-line region. The non-metal line region includes a plurality of insulating patterns and a first conductive pattern layer formed on the substrate.... Agent: Rabin & Berdo, PC

20080042131 - System for displaying images including thin film transistor device and method for fabricating the same: A system for displaying images. The system comprises a thin film transistor (TFT) device comprising a substrate comprising a driving circuit region and a pixel region. First and second active layers are disposed on the substrate in the driving circuit region and in the pixel region, respectively. The first active... Agent: Liu & Liu

20080042133 - Thin film transistor array substrate and method of fabricating the same: A thin film transistor (TFT) array substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion, and a method of fabricating the TFT array substrate. The TFT array substrate includes a gate interconnection line arranged on an insulating substrate, a gate... Agent: H.c. Park & Associates, PLC

20080042135 - Thin-film transistor substrate, method of manufacturing the same and display apparatus having the same: In a thin-film transistor (TFT) substrate, a gate insulating layer is disposed on a gate electrode electrically connected to a gate line. A semiconductor layer is disposed on the gate insulating layer. A source electrode is electrically connected to a data line that intersects the gate line. A drain electrode... Agent: Macpherson Kwok Chen & Heid LLP

20080042138 - Display device and method of making the same: A display device includes an insulating substrate; a semiconductor layer formed on the insulating substrate and comprising silicon and fluorine; a source electrode of which at least a portion is formed on the semiconductor layer; a drain electrode of which at least a portion is formed on the semiconductor layer... Agent: Macpherson Kwok Chen & Heid LLP

20080042137 - Electro-optical device, method for manufacturing electro-optical device, and electronic apparatus: An electro-optical device includes a substrate having a display region; TFTs each including a first electrode in the display region, a first insulating layer on the first electrode, a second electrode on the first insulating layer, and a second insulating layer on the second electrode; and terminals each including a... Agent: Lowe Hauptman Ham & Berner, LLP

20080042139 - Organic light emitting diode display and method for manufacturing the same: A method for manufacturing an organic light emitting diode display includes disposing a crystalline semiconductor layer on a substrate, disposing a gate line, a driving input electrode, and a driving output electrode on the crystalline semiconductor layer, the gate line including a switching control electrode, patterning the crystalline semiconductor layer... Agent: Cantor Colburn, LLP

20080042136 - Pixel unit structure of self-illumination display with low-reflection: A self-illumination display is provided, including a first substrate, a light-absorbing structure, a filter layer, a driving circuit unit, and a self-illumination unit. The light-absorbing structure and the filter layer are juxtaposedly disposed over the first substrate. The driving circuit unit is disposed over and shielded by the light-absorbing structure.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080042141 - Structure and method for reducing forward voltage across a silicon carbide-group iii nitride interface: A structure is disclosed that reduces the forward voltage across the interface between silicon carbide and Group III nitride layers. The structure includes a conductive silicon carbide substrate and a conductive layer of aluminum gallium nitride on the silicon carbide substrate. The aluminum gallium nitride layer has a mole fraction... Agent: Summa, Allan & Additon, P.A.

20080042145 - Diffusion barrier for light emitting diodes: A structure is disclosed for preventing reflector metals from migrating in light emitting diodes. The structure includes respective p-type and n-type semiconductor epitaxial layers for generating recombinations and photons under an applied current, a reflecting metal layer proximate at least one of the epitaxial layers for increasing the light output... Agent: Summa, Allan & Additon, P.A.

20080042147 - Led light source with integrated circuit and light guide: An elongated light source (50) comprises a subassembly (51) including a base (54), a light engine (10) positioned in mounting means (56) formed with the base; a light guide (58) positioned in spaced apart supports (57), and a cover (62) fixed to the base (54). The light engine (10) comprises... Agent: Chief Intellectual Property Counsel Osram Sylvania Inc.

20080042146 - Light-emitting device having improved ambient contrast: A light emitting device comprising one or more color-change material light-emitting elements, wherein at least one color-change material light-emitting element comprises: a light-emitting layer that emits light including a first frequency range; a light-reflecting layer or surface that reflects light including at least the first frequency range positioned relatively beneath... Agent: Patent Legal Staff Eastman Kodak Company

20080042148 - Shaped contact layer for light emitting heterostructure: An improved light emitting heterostructure and/or device is provided, which includes a contact layer having a contact shape comprising one of: a clover shape with at least a third order axis of symmetry or an H-shape. The use of these shapes can provide one or more improved operating characteristics for... Agent: Hoffman Warnick & D'alessandro, LLC

20080042149 - Vertical nitride semiconductor light emitting diode and method of manufacturing the same: A vertical nitride-based semiconductor LED comprises a structure support layer; a p-electrode formed on the structure support layer; a p-type nitride semiconductor layer formed on the p-electrode; an active layer formed on the p-type nitride semiconductor layer; an n-type nitride semiconductor layer formed on the active layer; an n-electrode formed... Agent: Lowe Hauptman Ham & Berner, LLP

20080042151 - High power light emitting diode package and method of producing the same: A high power Light Emitting Diode (LED) package and a method of producing the same. The high power LED package according to the present invention includes a plurality of light emitting diode chips, a first lead frame with the light emitting diode chips mounted thereon, and a second lead frame... Agent: Mcdermott Will & Emery LLP

20080042152 - Electronic device, display device, interface circuit and differential amplification device, which are constituted by using thin-film transistors: An integrated circuit, which is configured such that a MOS transistor and a bipolar transistor are integrated at the same time, is formed on an insulating substrate which includes a display device. An electronic device or a display includes a plurality of semiconductor devices which are formed by using a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080042154 - Light-emitting device, method of fabricating the same, and electronic apparatus: A light-emitting device is provided in which a plurality of thin films including a light-emitting layer are stacked. The light-emitting device includes a waveform structure having a directive scattering function in one interface between the thin films.... Agent: Oliff & Berridge, PLC

20080042155 - Semiconductor device, led head and image forming apparatus: A semiconductor device is manufactured using dicing of a semiconductor wafer. The semiconductor device includes a substrate, a base insulating layer formed on the substrate, a semiconductor element formed on the base insulating layer, and a separate pattern portion formed on an end portion of the substrate separately from the... Agent: Rabin & Berdo, PC

20080042157 - Surface mount light emitting diode package: A surface mount light emitting diode package (surface mount LED package) includes a leadframe, a LED chip, a plurality of conductors and an encapsulant. The LED chip is disposed over the leadframe. The LED chip has an active surface facing the leadframe and a plurality of electrodes is disposed on... Agent: Jianq Chyun Intellectual Property Office

20080042119 - Multi-layered chalcogenide and related devices having enhanced operational characteristics: A multi-layer chalcogenide, memory or switching device. The device includes an active region disposed between a first terminal and a second terminal. The active region includes a first layer and a second layer, where one of the layers is a heterogeneous layer that includes an operational component and a promoter... Agent: Energy Conversion Devices, Inc.

20080042118 - Phase-change memory device with minimized reduction in thermal efficiency and method of manufacturing the same: A phase-change memory device has a different-material contact plug having a first electrically conductive material plug made of a first electrically conductive material, and a second electrically conductive material plug made of a second electrically conductive material having a specific resistance smaller than the first electrically conductive material, the first... Agent: Sughrue Mion, PLLC

20080042120 - Integrated circuit device, manufacturing method thereof, and display device: An integrated circuit device of the present invention includes a substrate on which at least two types of nano wire element are provided. These nano wire elements have functions and materials different from each other. The nano wire elements are constituted by nano wires having sizes differing depending on types... Agent: Birch Stewart Kolasch & Birch

20080042122 - Semiconductor light emitting element, method of manufacturing the same and semiconductor light emitting device: A semiconductor light emitting element improving luminous efficiency has: a semiconductor substrate, an N-type cladding layer formed over the substrate; a barrier layer formed over the cladding layer; a quantum dot layer formed over the barrier layer, the quantum dot layer including quantum dots having a band gap smaller than... Agent: Kratz, Quintos & Hanson, LLP

20080042124 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the same are disclosed, in which an insulating layer may be formed in a strained silicon layer under source/drain regions to substantially overcome conventional problems resulting from a channel decrease in the semiconductor device. A method for manufacturing the semiconductor device may... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080042125 - High speed data channel including a cmos vcsel driver and a high performance photodetector and cmos photoreceiver: A high speed optical channel including an optical driver and a photodetector in a CMOS photoreceiver. The optical channel driver includes a FET driver circuit driving a passive element (e.g., an integrated loop inductor) and a vertical cavity surface emitting laser (VCSEL) diode. The VCSEL diode is biased by a... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20080042126 - Ballistic direct injection nrom cell on strained silicon structures: A nitride read only memory cell comprising a silicon-germanium layer with a pair of source/drain regions. A strained silicon layer is formed overlying the silicon-germanium layer such that the pair of source/drain regions is linked by a channel that is generated in the strained silicon layer during operation of the... Agent: Leffert Jay & Polglaze, P.A.

20080042129 - Organic thin film transistor and its fabrication method: An organic TFT comprising an organic thin film, a gate electrode formed on one surface of the organic thin film through a gate insulating film, source/drain electrodes formed on both sides of the gate electrode and on one surface of the organic thin film or on the other surface, and... Agent: Edwards Angell Palmer & Dodge LLP

20080042128 - Semiconductor device and manufacturing method thereof: A nonvolatile memory has a problem in that applied voltage is high. This is because a carrier needs to be injected into a floating gate through an insulating film by a tunneling effect. In addition, there is concern about deterioration of the insulating film by performing such carrier injection. An... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080042140 - Three dimensional integrated circuit and method of design: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20080042143 - Avalanche protection for wide bandgap devices: A method and device for protecting wide bandgap devices from failing during suppression of voltage transients. An improvement in avalanche capability is achieved by placing one or more diodes, or a PNP transistor, across the blocking junction of the wide bandgap device.... Agent: Hiscock & Barclay, LLP

20080042144 - Electron emitting device with projection comprising base portion and electron emission portion: The present invention relates to an electron emitting device having a structure for efficiently emitting electrons. The electron emitting device has a substrate comprised of an n-type diamond, and a pointed projection provided on the substrate. The projection comprises a base provided on the substrate side, and an electron emission... Agent: Mcdermott Will & Emery LLP

20080042142 - Highly heat-resistant synthetic polymer compound and high withstand voltage semiconductor device: The outer surface of a wide-gap semiconductor device is covered with a synthetic polymer compound. The synthetic polymer compound is formed by linking a plurality of third organosilicon polymers through covalent bonding which is formed by addition reaction, and has a three-dimensional steric structure. The third organosilicon polymers are obtained... Agent: Crowell & Moring LLP Intellectual Property Group

20080042150 - White light emitting device and method for manufacturing the same: There are provided a white light emitting device of high luminous efficiency prevented from luminance deterioration even in large electric current range, and a method for manufacturing the same with high production yield. The white light emitting device (1) is composed of a blue LED element (4) and an oxide... Agent: Rabin & Berdo, PC

20080042153 - Wavelength conversion chip for use with light emitting diodes and method for making same: A wavelength conversion chip is formed by depositing a wavelength conversion material on a substrate to form a layer, removing the resulting wavelength conversion layer from the substrate and then segmenting the wavelength conversion layer into a plurality of wavelength conversion chips. The wavelength conversion material can be annealed by... Agent: Goldeneye, Inc.

20080042156 - Semiconductor light-emitting device and light-emitting display therewith: A semiconductor light-emitting device has a semiconductor light-emitting element for emitting light with emission wavelengths of 390 to 420 nm, wherein the wavelengths of light from the semiconductor light-emitting element are converted by a fluorescent substance having a monochromatic emission peak. The emission wavelengths of 390 to 420 nm, which... Agent: Morrison & Foerster LLP

20080042158 - Liquid crystal display device: A display device having a display element is configured such that the extending directions of electrodes are made different from each other among upper, lower, left and right pixels.... Agent: Stanley P. Fisher Reed Smith LLP

20080042160 - Group iii-v nitride-based semiconductor substrate and group iii-v nitride-based light emitting device: A group III-V nitride-based semiconductor substrate is formed of a group III-V nitride-based semiconductor single crystal containing an n-type impurity. The single crystal has a periodical change in concentration of the n-type impurity in a thickness direction of the substrate. The periodical change has a minimum value in concentration of... Agent: Paul J. Esatto, Jr. Scully, Scott, Murphy & Presser

20080042161 - Nitride semiconductor light emitting diode: A nitride semiconductor light emitting diode includes: an n-type clad layer; an active layer formed on the n-type clad layer; an electron blocking layer formed on the active layer, the electron blocking layer being composed of a p-type nitride semiconductor including a transition element of group III; and a p-type... Agent: Staas & Halsey LLP

20080042159 - Transparent electrode for semiconductor light-emitting device: A transparent electrode for a gallium nitride-based compound semiconductor light-emitting device includes a p-type semiconductor layer (5), a contact metal layer (1) formed by ohmic contact on the p-type semiconductor layer, an current diffusion layer (12) formed on the contact metal layer and having a lower magnitude of resistivity on... Agent: Sughrue Mion, PLLC

20080042162 - Ultraviolet light-emitting device in which p-type semiconductor is used: An object is to provide an ultraviolet light-emitting device in which a p-type semiconductor which has high conductivity and an emission peak in ultraviolet region, and emits light efficiently is used. The p-type semiconductor is prepared by supplying a p-type impurity raw material at the same time or after starting... Agent: Birch Stewart Kolasch & Birch

20080042163 - Thermal transfer device and system and method incorporating same: A thermal transfer device having a first substrate layer, a second substrate layer and first and second electrodes disposed between the first substrate layer and the second substrate layer. The thermal transfer device also includes a release layer disposed between the first electrode and the second electrode and an actuator... Agent: General Electric Company (pcpi) C/o Fletcher Yoder

20080042165 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device includes a thyristor configured to be formed through sequential joining of a first region of a first conductivity type, a second region of a second conductivity type opposite to the first conductivity type, a third region of the first conductivity type, and a fourth region of the... Agent: Rader Fishman & Grauer PLLC

20080042164 - Power semiconductor component: A power semiconductor component is disclosed. One embodiment provides a semiconductor body, in which at least two vertical power semiconductor components are arranged. Each of the vertical power semiconductor components has a first load terminal arranged at a front side of the semiconductor body. Each of the vertical power semiconductor... Agent: Dicke, Billig & Czaja

20080042166 - Strained si mosfet on tensile-strained sige-on-insulator (sgoi): A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer... Agent: Scully, Scott, Murphy & Presser, P.C.

20080042167 - Phase change materials and associated memory devices: A memory device utilizes a phase change material as the storage medium. The phase change material includes at least one of Ge, Sb, Te, Se, As, and S, as well as a nitride compound as a dopant. The memory device can be a solid-state memory cell with electrodes in electrical... Agent: Daniel E. Johnson IBM Corporation, Almaden Research Center

20080042168 - Laminating system, ic sheet, scroll of ic sheet, and method for manufacturing ic chip: Thin film integrated circuits are peeled from a substrate and the peeled thin film integrated circuits are sealed, efficiently in order to improve manufacturing yields. The present invention provides laminating system comprising transporting means for transporting a substrate provided with a plurality of thin film integrated circuits; first peeling means... Agent: Nixon Peabody LLP

20080042169 - Doped plug for ccd gaps: A method and structure of providing a doped plug to improve the performance of CCD gaps is discussed. A highly-doped region is implemented in a semiconductor, aligned beneath a gap. The plug provides a highly-conductive region at the semiconductor surface, therefore preventing the development of a region where potential is... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20080042170 - Image sensor and method for manufacturing the same: An image sensor and fabricating method thereof are provided. A gate electrode is formed on a semiconductor substrate with a photodiode on one side and a low-concentration drain on the other side. A silicide blocking pattern covers the photodiode, the gate electrode, and part of the low-concentration drain, such that... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080042173 - Semiconductor device and method of manufacturing the same: A MOS transistor includes a substrate, source/drain regions formed at portions of the substrate, and a channel region formed between the source/drain regions. The MOS transistor further includes a gate structure having a gate insulation layer pattern and a gate electrode formed on the channel region. The gate electrode includes... Agent: Marger Johnson & Mccollom, P.C.

20080042171 - Transistor arrangement, sense-amplifier arrangement and methods of manufacturing the same via a phase shift mask: Methods of forming transistor arrangements using alternating phase shift masks are provided. The mask may include two parallel opaque lines, a first transparent section separating the opaque lines and a second transparent section in the rest. The second transparent section may shift the phase with respect to the first transparent... Agent: Edell, Shapiro & Finnan, LLC

20080042174 - Field effect transistors (fets) with inverted source/drain metallic contacts, and method of fabricating same: The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a... Agent: Scully, Scott, Murphy & Presser, P.C.

20080042172 - Semiconductor component having a space saving edge structure: A Semiconductor component having a space saving edge structure is disclosed. One embodiment provides a first side, a second side, an inner region, an edge region adjoining the inner region in a lateral direction of the semiconductor body, and a first semiconductor layer extending across the inner region and the... Agent: Dicke, Billig & Czaja

20080042176 - Method for making image sensor with reduced etching damage: A method of forming a pixel of an image sensor with reduced etching damage is disclosed. The method first includes forming a light sensitive element in a substrate. Then, a transfer gate is formed atop the substrate and adjacent to the light sensitive element. A protective layer, such as an... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080042175 - Solid state image pickup device and method of producing solid state image pickup device: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the... Agent: Robert J. Depke Lewis T. Steadman

20080042177 - Image sensor and method of fabricating the same: In one embodiment, the method includes forming a first dielectric layer over a substrate, and removing a portion of the first dielectric layer over a photoactive region of the substrate to form a concavity in the first dielectric layer. An inner lens and etch stop layer are formed over the... Agent: Harness, Dickey & Pierce, P.L.C

20080042179 - Memory arrays and methods of fabricating memory arrays: A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are... Agent: Wells St. John P.s.

20080042178 - Semiconductor constructions, and methods of forming semiconductor constructions: In some embodiments, an opening is formed through a first material, and sidewall topography of the opening is utilized to form a pair of separate anistropically etched spacers. The spacers are utilized to pattern lines in material underlying the spacers. Some embodiments include constructions having one or more openings which... Agent: Wells St. John P.s.

20080042181 - Semiconductor device: A semiconductor device in which capacitance per unit area can be enlarged without imposing any limitations upon layout has both a DRAM region and a logic region. The DRAM region and the logic region each have a plurality of cells provided with a respective capacitance element. Each capacitance element has... Agent: Young & Thompson

20080042182 - Capacitor and method of manufacturing the same: A capacitor includes a cylindrical storage electrode formed on a substrate. A ring-shaped stabilizing member encloses an upper portion of the storage electrode to structurally support the storage electrode and an adjacent storage electrode. The ring-shaped stabilizing member is substantially perpendicular to the storage electrode and extends in a direction... Agent: Marger Johnson & Mccollom, P.C.

20080042180 - Semiconductor device: The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one... Agent: Eric Robinson

20080042184 - Highly reliable nand flash memory using five side enclosed floating gate storage elements: A NAND flash memory system with an array of individual charge storage elements, such as floating gates, arranged in a NAND string, each element being capable of selectively storing data in the form of charge there-in during a program or an erase operation, and during a read operation sensing the... Agent: Mammen Thomas

20080042183 - Nonvolatile memories with shaped floating gates: In a nonvolatile memory using floating gates to store charge, individual floating gates are L-shaped. Orientations of L-shaped floating gates may alternate in the bit line direction and may also alternate in the word line direction. L-shaped floating gates are formed by etching conductive portions using etch masks of different... Agent: Winston & Strawn, LLP

20080042185 - Eeprom memory array having 5f2 cells: A non-volatile memory array featuring cells with split gate transistors and an overall area extent of 5F2, i.e. five times the minimum lithographic feature size squared. While smaller calls are known, the cells of the present invention each have a select device and a floating gate transistor with adjacent cells... Agent: Schneck & Schneck

20080042186 - Non-volatile memory device and method of manufacturing the same: A non-volatile memory device includes isolation layers, a cell trench, a floating gate, a common source region and a word line. The isolation layers define an active region of a substrate. The cell trench is formed in the active region. The cell trench extends in a first direction. The floating... Agent: F. Chau & Associates, LLC

20080042187 - Flash memory device and a method of fabricating the same: The invention relates to a flash memory device and its method of fabrication. The method includes the steps of: forming gate protection patterns over a peripheral region of a semiconductor substrate; forming a tunnel insulating film over the semiconductor substrate; forming a first conductive film over the tunnel insulating film... Agent: Marshall, Gerstein & Borun LLP

20080042188 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory includes a memory cell including, a semiconductor substrate, a first insulating layer on the semiconductor substrate, a floating gate on the first insulating layer, a second insulating layer on the floating gate, and a control gate electrode on the second insulating layer, wherein the floating gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080042189 - Split gate nonvolatile memory and manufacturing method of the same: A split gate nonvolatile memory cell is provided with a first diffusion region, a second diffusion region, and a channel region formed between the first and second diffusion regions, including a first channel region having a predetermined dopant concentration. The first channel region is positioned apart from the first and... Agent: Foley And Lardner LLP Suite 500

20080042190 - Electrically erasable programmable read-only memory cell and memory device and manufacturing method thereof: A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer... Agent: J.c. Patents

20080042191 - Non-volatile memory device and method of fabricating the same: A method of fabricating a non-volatile memory device is provided. The method includes forming a plurality of trenches in a substrate. The trenches are filled with first conducting layers to serve as buried bit lines. Thereafter, a charge storage layer is formed on the substrate to cover the surface of... Agent: J C Patents, Inc.

20080042192 - Semiconductor memory device including charge trap layer with stacked nitride layers: A semiconductor memory device includes a semiconductor substrate, a tunnel insulating layer, charge trap layer, and a blocking layer. The tunnel insulating layer is on the semiconductor substrate. The charge trap layer is on the tunnel insulating layer and includes at least one pair of a first nitride layer with... Agent: Myers Bigel Sibley & Sajovec

20080042193 - Semiconductor device: For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080042194 - Trench mosfet with terraced gate and manufacturing method thereof: A trench metal oxide semiconductor field effect transistor (MOSFET) with a terraced trench gate. An epitaxial layer with a plurality of trenches is provided and a gate oxide layer is covered the sidewalls and bottoms of the trenches. A polysilicon layer is filled in the trenches, wherein the polysilicon layer... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20080042195 - Semiconductor device including recessed-channel-array mosfet having a higher operational speed: A semiconductor device includes a recessed-channel-array MOSFET including a gate electrode having a portion received in a recess. The gate insulting film has a first portion made of silicon oxide in contact with the sidewall of the recess and a second portion made of silicon oxynitride in contact with the... Agent: Young & Thompson

20080042196 - Circuit and method of reducing body diode reverse recovery time of lateral power semiconductor devices: A lateral power semiconductor device has a substrate and an isolation layer formed over the substrate for reducing minority carrier storage in the substrate. A well region is formed over the isolation layer. A source region, drain region, and channel region are formed in the well. A first region is... Agent: Quarles & Brady LLP

20080042198 - Demos structure: Embodiments relate to a Drain Extended Metal-Oxide-Semiconductor (DEMOS) structure in which a drain region may be longer than a source region. In embodiments, the DEMOS may include a gate insulating film and a gate electrode sequentially layered over a semiconductor substrate, a spacer formed at a sidewall of a gate... Agent: Sherr & Nourse, PLLC

20080042197 - High voltage field effect transistor: A high voltage field effect transistor according to the present invention has: a p-type low concentration drain region and a low concentration source region formed on both sides of a channel formation region within a n-type region of a semiconductor substrate; a high concentration drain region formed in the low... Agent: Rabin & Berdo, PC

20080042199 - Open source/drain junction field effect transistor: The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET) with an open drain, where the open drain allows the transistors to operate at higher voltages before experiencing gate leakage current. The open drain allows the voltage... Agent: Texas Instruments Incorporated

20080042200 - Thin-film transistor and fabrication method thereof: A thin-film transistor and method for fabricating a thin-film transistor is disclosed. In the method, a controlled micro-line is formed by inkjet printing in combination with the coffee ring effect. The micro-line may be a semiconductor or an insulator. A high-current thin-film transistor utilizing the micro-line of the coffee ring... Agent: Quintero Law Office, PC

20080042204 - Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby: Methods of fabricating a semiconductor structure in which a body of monocrystalline silicon is formed on a sidewall of a sacrificial mandrel and semiconductor structures made by the methods. After the body of monocrystalline silicon is formed, the sacrificial material of the mandrel is removed selective to the monocrystalline silicon... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080042202 - Quasi self-aligned source/drain finfet process: A method of forming a semiconductor structure including a plurality of finFFET devices in which crossing masks are employed in providing a rectangular patterns to define relatively thin Fins along with a chemical oxide removal (COR) process is provided. The present method further includes a step of merging adjacent Fins... Agent: Scully, Scott, Murphy & Presser, P.C.

20080042201 - Semiconductor devices and methods of making: In one method of forming a semiconductor device, a first electrode is formed electrically coupled with a semiconductor material. After the first electrode is formed, an insulator is formed over the semiconductor material adjoining the first electrode and extending a selected distance from the first electrode. After the insulator is... Agent: Hewlett Packard Company

20080042203 - Single and double-gate pseudo-fet devices for semiconductor materials evaluation: Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior... Agent: Scully, Scott, Murphy & Presser, P.C.

20080042205 - Low-cost high-performance planar back-gate cmos: A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-gate CMOS structure that is formed utilizing the method of the present invention. The method... Agent: Scully, Scott, Murphy & Presser, P.C.

20080042206 - Integrated circuit device having input/output electrostatic discharge protection cell equipped with electrostatic discharge protection element and power clamp: There is provided an integrated circuit device having an input/output electrostatic discharge (I/O ESD) protection cell. The integrated circuit device includes an I/O ESD protection cell comprising a VDD ESD protection element connected between an I/O pad and a VDD line, a ground voltage (VSS) ESD protection element connected between... Agent: Mills & Onello LLP

20080042207 - Contact array layout for improving esd capability of cmos transistors: A transistor layout is disclosed for improving electrostatic discharge capabilities. The layout has a first gate region with a first active region and a second active region formed on two sides thereof, and a second gate region placed next to the second active region with a third active region placed... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080042208 - Trench mosfet with esd trench capacitor: An electrostatic discharging (ESD) protected metal oxide semiconductor field effect transistor (MOSFET), an epitaxial layer on substrate; a trench gate structure formed in the epitaxial layer; a source region formed in the substrate near the gate structure; a trench capacitor formed underneath gate metal pad in the epitaxial layer connected... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20080042213 - Complementary metal-oxide-semiconductor transistor and method of manufacturing the same: A CMOS transistor and a method of manufacturing the CMOS transistor are disclosed. An NMOS transistor is formed on a first region of a semiconductor substrate. A PMOS transistor is formed on a second region of a semiconductor substrate. The NMOS transistor includes a first gate conductive layer. The PMOS... Agent: Mills & Onello LLP

20080042212 - Printed dopant layers: An electronic device, including a substrate, a plurality of first semiconductor islands on the substrate, a plurality of second semiconductor islands on the substrate, a first dielectric film on the first subset of the semiconductor islands, second dielectric film on the second semiconductor islands, and a metal layer in electrical... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080042210 - Semiconductor device and method of fabricating thereof: A method of fabricating a semiconductor device is provided. A substrate is first provided, and than several IO devices and several core devices are formed on the substrate, wherein those IO devises include IO PMOS and IO NMOS, and those core devises include core PMOS and core NMOS. Thereafter, a... Agent: Jianq Chyun Intellectual Property Office

20080042209 - Semiconductor system using germanium condensation: A semiconductor system includes providing a silicon semiconductor substrate. A gate and a plurality of source/drain regions are formed on the silicon semiconductor substrate to form at least one pFET. A silicon-germanium layer is formed over the plurality of source/drain regions. The germanium is condensed from the silicon-germanium layer to... Agent: Law Offices Of Mikio Ishimaru

20080042211 - Strained semiconductor channels and methods of formation: In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain... Agent: Schwegman, Lundberg & Woessner, P.A.

20080042214 - Semiconductor device: A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region... Agent: Mcdermott Will & Emery LLP

20080042215 - Strained complementary metal oxide semiconductor (cmos) on rotated wafers and methods thereof: The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that... Agent: Scully, Scott, Murphy & Presser, P.C.

20080042216 - Formation of standard voltage threshold and low voltage threshold mosfet devices: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second... Agent: Dinsmore & Shohl LLP

20080042217 - Array substrate for a liquid crystal display device and manufacturing method of the same: An array substrate for a liquid crystal display device includes gate and data lines crossing on a substrate, common lines parallel to and between the gate lines, thin film transistors at crossing portions of the gate and data lines, and a pixel electrode. The common lines define pixel regions, which... Agent: Brinks Hofer Gilson & Lione

20080042218 - Semiconductor memory device: In the memory cell of the present invention, channel width of an access transistor is made larger than the channel width of a driver transistor about the relation of the channel width of an access transistor and a driver transistor. That is, since the access transistor can make channel area... Agent: Miles & Stockbridge PC

20080042219 - Finfet device: A finFET, a method of fabricating the finFET and a design structure of the finFET. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the... Agent: Schmeiser, Olsen & Watts

20080042220 - Gate electrode forming method for semiconductor device: A method for forming an LDD structure of a gate electrode of a MOSFET. The gate electrode may be formed by sequentially depositing a gate oxide layer and a poly silicon layer over a semiconductor substrate. A photo resist pattern may be formed over the resultant structure. A gate electrode... Agent: Sherr & Nourse, PLLC

20080042221 - High voltage transistor: According to one exemplary embodiment, a transistor includes a channel region situated adjacent to a field oxide region. The transistor further includes a gate have a first portion situated over the channel region and a second portion situated over the field oxide region. The transistor further includes at least one... Agent: Farjami & Farjami LLP

20080042222 - Trench mosfet with copper metal connections: A trench Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) with copper metal connections. A substrate is provided with a plurality of trenches. A gate oxide layer is formed on the substrate and the sidewalls and bottom of the trenches. A conductive layer is filled in the trenches to be used as a... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20080042223 - Microelectromechanical system package and method for making the same: A microelectromechanical system package includes a substrate, a microelectromechanical system transducer mounted on the substrate by a plurality of metal bumps, a non-conductive polymer ring provided around the microelectromechanical transducer for avoiding the leakage of sound pressure from the microelectromechanical transducer, an integrated circuit mounted on the substrate by a... Agent: Kamrath & Associates P.A.

20080042224 - Soi disks comprising mems structures and filled isolating trenches having a defined cross-section: Forming of filled isolation trenches, in particular the transition area in trenches and recesses free of silicon during the realisation of MEMS structures of SOI wafers. A reliable dielectic isulation of adajacent silicon regions is to be obtained. The insulation is achieved by filled isolation trenches (17). The end portions... Agent: Hunton & Williams LLP Intellectual Property Department

20080042225 - Ultrasonic transducer and manufacturing method: This invention provides a technique whereby, even if a step is produced by splitting a lower electrode into component elements, resistance increase of an upper electrode, damage to a membrane and decrease of dielectric strength between an upper electrode and the lower electrode, are reduced. In an ultrasonic transducer comprising... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080042226 - Surface-shape sensor and method of manufacturing the same: According to the present embodiment, a surface-shape sensor is provided. The surface-shape sensor includes a silicon substrate, an interlayer insulating film formed over the silicon substrate, a first moisture-barrier insulating film formed on the interlayer insulating film, a detection-electrode film formed on the first moisture-barrier insulating film, a second moisture-barrier... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080042228 - Image sensor and method for manufacturing the same: An image sensor and a fabricating method thereof are provided. The image sensor includes a plurality of pixels disposed in an active region and dummy pixels disposed in a peripheral region. An interlayer dielectric layer has a first thickness in the active region and a second thickness thinner than the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080042227 - Solid-stated image pickup device and method for manufacturing same: There are provided image pickup devices capable of significantly increasing production yield and ensuring long-term reliability and a method for manufacturing the image pickup devices. This invention is characterized in that it has a large number of light-receiving portions 2 formed at a surface portion of a wafer 1 and... Agent: Lucas & Mercanti, LLP

20080042229 - Image sensor and method for manufacturing the same: An image sensor is provided incorporating a first conductive type semiconductor substrate including an active area defined by a device isolation layer; a second conductive type first ion implant area formed as multiple regions in the active area; a second conductive type second ion implant area connecting the multiple regions... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080042230 - Image sensor and fabrication method thereof: An image sensor has a substrate, a dielectric layer positioned on the substrate, a pixel array including a plurality of pixels defined on the substrate, a shield electrode positioned between any two adjacent pixel electrodes of the pixels, a photo conductive layer positioned on the shield electrode and the pixel... Agent: North America Intellectual Property Corporation

20080042231 - Semiconductor device with a cmos image sensor and method of manufacturing such a device: According to the invention the semiconductor device comprises also precharge means by which the photodiode can be precharged by a fixed amount of charge carriers after it has been reset by the reset means. In this way the sensors has a highly linear response, in particular at low light/radiation level,... Agent: Daniel E. Fisher, Fisher Technology Law L.L.C.

20080042232 - Isolation structures for integrated circuits and modular methods of forming the same: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall... Agent: Patentability Associates

20080042233 - Semiconductor device having imprived electrical characteristics and method of manufacturing the same: A method of manufacturing a semiconductor device includes forming a pad insulating film over a silicon semiconductor substrate. The pad insulating film and the substrate may be etched to form a trench in the substrate. A thin layer including dopants may be formed over an inner wall of the trench.... Agent: Sherr & Nourse, PLLC

20080042234 - Electric fuse circuit and electronic component: An electric fuse circuit is provided which has a capacitor that forms an electric fuse; a write circuit for breaking an insulating film of the capacitor, by applying a voltage to a terminal of the capacitor in response to a write signal; and at least two transistors, including a first... Agent: Arent Fox LLP

20080042235 - Semiconductor memory device: A semiconductor memory device for reliably inducing a breakdown in the dielectric when utilizing an antifuse to write on the dielectric film even when the process scale has become more detailed. The semiconductor memory device includes an antifuse serving as the memory node, and a current regulator connected in serial... Agent: Mcginn Intellectual Property Law Group, PLLC

20080042236 - Integrated circuit system employing gate shield and/or ground shield: An integrated circuit system that includes: forming a substrate with an active region; depositing a material over the substrate to act as an etch stop and define a source and a drain; depositing a first dielectric over the substrate; processing the first dielectric to form features within the first dielectric... Agent: Law Offices Of Mikio Ishimaru

20080042238 - High performance system-on-chip using post passivation process: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting... Agent: Mou-shiung Lin Science-based Industrial Park

20080042237 - Semiconductor device and method of manufacturing the same: Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive elements are formed on the trench isolation films, respectively. Each of the trench isolation... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080042239 - High performance system-on-chip using post passivation process: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting... Agent: Mou-shiung Lin

20080042240 - Semiconductor device and method of manufacturing the same: Provided is a semiconductor device including a vertically oriented capacitor extending above the substrate surface and a method of manufacturing such devices in which cell, peripheral and boundary areas between the cell and peripheral areas are defined on a semiconductor substrate. Capacitors are formed in the cell area, a mold... Agent: Harness, Dickey & Pierce, P.L.C

20080042241 - Voltage-controlled semiconductor structure, resistor, and manufacturing processes thereof: Voltage-controlled semiconductor structures, voltage-controlled resistors, and manufacturing processes are provided. The semiconductor structure comprises a substrate, a first doped well, and a second doped well. The substrate is doped with a first type of ions. The first doped well is with a second type of ions and is formed in... Agent: Nixon Peabody LLP - Patent Group

20080042242 - High voltage sensor device: In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element.... Agent: Bradley J. Botsch Semiconductor Components Industries, LLC

20080042243 - Phase change memory devices and methods for fabricating the same: Phase change memory devices and methods for fabricating the same. An exemplary phase change memory device comprises a conductive element formed in a dielectric layer. A phase change material layer is formed in the dielectric layer. A conductive layer extends in the dielectric layer to respectively electrically connect the phase... Agent: Quintero Law Office, PC

20080042244 - Nitride compound semiconductor element and production method therefor: A nitride compound semiconductor element according to the present invention is a nitride compound semiconductor element including a substrate 1 having an upper face and a lower face and a semiconductor multilayer structure 40 supported by the upper face of the substrate 1, such that the substrate 1 and the... Agent: Mark D. Saralino (mei) Renner, Otto, Boisselle & Sklar, LLP

20080042245 - Integrated circuit package system with waferscale spacer: An integrated circuit packaging system is provided including forming a first device wafer having a first backside and a first active side; forming a waferscale spacer wafer having a waferscale spacer and a first opening; mounting the waferscale spacer wafer on the first backside; and singulating an first integrated circuit... Agent: Law Offices Of Mikio Ishimaru

20080042246 - Integrated circuit including clip: A semiconductor device is provided that includes a leadframe, a die, and a clip. The leadframe has a flag and a power pad. The die is coupled to the flag. The clip comprises a die retaining section and a pad section. The die is coupled to the die retaining section,... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080042247 - Stacked semiconductor components with through wire interconnects (twi): A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact... Agent: Stephen A. Gratton

20080042248 - Method of enabling solder deposition on a substrate and electronic package formed thereby: An electronic package includes a substrate (110, 310, 510) and a solder resist layer (120, 320, 520) over the substrate. The solder resist layer has a plurality of solder resist openings (121, 321, 521) therein. The electronic package further includes a finish layer (130, 330, 535) in the solder resist... Agent: Intel Corporation C/o Intellevate, LLC

20080042249 - Microelectronic package: A microelectronic package includes a lower unit having a lower unit substrate with conductive features and a top and bottom surface. The lower unit includes one or more lower unit chips overlying the top surface of the lower unit substrate that are electrically connected to the conductive features of the... Agent: Tessera Lerner David Et Al.

20080042251 - Stackable semiconductor package: The present invention relates to a stackable semiconductor package, comprising a top package, a bottom package, an adhesive layer, a plurality of wires and a molding compound. A part of a surface of a chip of the bottom package is exposed. The top package is inverted, and is adhered to... Agent: Volentine & Whitt PLLC

20080042250 - Stacked microelectronic assemblies and methods therefor: A stacked microelectronic assembly includes a base substrate having conductive elements projecting from a bottom surface thereof and a first microelectronic subassembly underlying a bottom surface of the base substrate. The first microelectronic subassembly includes a first dielectric substrate, a first microelectronic element connected with the first dielectric substrate and... Agent: Tessera Lerner David Et Al.

20080042253 - Stack type ball grid array package and method for manufacturing the same: A stacked BGA package and a method for manufacturing the stacked BGA package, with reduced size and/or height of a unit package, which may also reduce an electrical connection length. The stacked BGA package may include a base BGA package having at least one semiconductor chip, and a plurality of... Agent: Harness, Dickey & Pierce, P.L.C

20080042252 - Stackable ceramic fbga for high thermal applications: An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.... Agent: Trask Britt, P.C./ Micron Technology

20080042254 - Semiconductor device and manufacturing method of the same: A semiconductor device includes a semiconductor element provided over a wiring board; sealing resin configured to seal the semiconductor element; and reinforcing resin provided at least at a part of a boundary part of the sealing resin and the wiring board. In the above-mentioned semiconductor device, the reinforcing resin may... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080042256 - Chip package structure and circuit board thereof: A chip package structure including a substrate, a circuit layer, a solder mask, a chip, and an encapsulant is provided. The circuit layer is disposed on the substrate and includes two traces and a dummy trace. The dummy trace is disposed between the traces. The solder mask covers the circuit... Agent: J C Patents, Inc.

20080042255 - Chip package structure and fabrication method thereof: A chip package structure and a fabrication method thereof are disclosed herein. The fabrication method includes: providing a substrate, wherein at least a through hole penetrates through the substrate; forming a block element surrounding the through hole of the substrate; forming an adhesive element surrounding the block element; disposing a... Agent: Rosenberg, Klein & Lee

20080042257 - Die pad arrangement and bumpless chip package applying the same: A bumpless chip package including at least one chip and an interconnection structure is provided. The chip has an active surface and a non-active surface opposite the active surface, and has a die pad arrangement disposed on the active surface of the chip. The die pad arrangement includes at least... Agent: J C Patents, Inc.

20080042258 - Package for semiconductor devices: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed... Agent: Staas & Halsey LLP

20080042259 - Semiconductor device and method of manufacturing the same, circult board, and electronic instrument: A semiconductor device includes a semiconductor substrate in which an integrated circuit is formed and which includes interconnects and electrodes, the interconnects electrically connected with the semiconductor substrate, and the electrodes being formed on the interconnects; a resin layer formed on the semiconductor substrate; redistribution interconnects electrically connected with the... Agent: Oliff & Berridge, PLC

20080042260 - Micro-electromechanical systems device and manufacturing method thereof: A method of sealing and leading out an electrode for an MEMS device such as an angular velocity sensor, an acceleration sensor, or a combined sensor is provided. A fixed portion is formed within a device forming region surrounded with a base support, a beam is connected to the fixed... Agent: Miles & Stockbridge PC

20080042261 - Integrated circuit package with a heat dissipation device and a method of making the same: Integrated circuit assembly including a die stack assembly having a heat dissipation device thermally coupled to a lateral of surface the die stack assembly. The die stack assembly includes a plurality integrated circuits placed on each other. In another embodiment a heat dissipation device comprising an encapsulant is thermally coupled... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080042262 - Plastic overmolded packages with mechanically decoupled lid attach attachment: The specification describes a lidded MCM IC plastic overmolded package with chimney-type heat sink. The lid is mechanically decoupled from the chimneys by a compliant conductive polymer plug.... Agent: Law Firm Of Peter V.d. Wilde

20080042263 - Reinforced semiconductor package and stiffener thereof: A reinforced semiconductor package (500, 700) with a stiffener (400, 600) is provided. The stiffener is composed of an inner ring (410) disposed on the upper surface (512) of a substrate (510) and surrounding a semiconductor chip (520), and an outer ring (420) also disposed on the upper surface of... Agent: Madson & Austin

20080042264 - Apparatus and methods for cooling semiconductor integrated circuit package structures: Apparatus and methods are provided for thermally coupling a semiconductor chip directly to a heat conducting device (e.g., a copper heat sink) using a thermal joint that provides increased thermal conductivity between the heat conducting device and high power density regions of the semiconductor chip, while minimizing or eliminating mechanical... Agent: F. Chau & Associates, LLC

20080042265 - Chip scale module package in bga semiconductor package: A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the ball grid array (BGA) substrate, and an application die attached... Agent: Quarles & Brady LLP

20080042266 - Noncontact ic label and method and apparatus for manufacturing the same: A non-contact IC label comprising an electrically insulating first substrate; an electrically connected antenna coil and IC chip provided on one surface of said substrate; a magnetic layer provided on said one surface of said substrate so as to cover said antenna coil and said IC chip, a first adhesive... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080042267 - Integrated circuit package and system interface: A method for enhancing the performance of an IC package and media interface. Adding a fissure to a Flip-Chip type package improves the crosstalk performance of the package for both high and low frequencies. The wall of the fissure can be implemented with a heat spreader layer and can be... Agent: Pete Scott, Senior Corporate Counsel Lsi Logic Corporation

20080042268 - Void boundary structures, semiconductor devices having the void boundary structures and methods of forming the same: Void boundary structures, semiconductor devices having the void boundary structures, and methods of forming the same are provided. The structures, semiconductor devices and methods present a way for reducing parasitic capacitance between interconnections by forming a void between the interconnections. The interconnections may be formed on a semiconductor substrate. An... Agent: Harness, Dickey & Pierce, P.L.C

20080042269 - Bump structures and packaged structures thereof: A bump structure for bonding two substrates together includes a composite structure. The composite structure is formed over a first substrate. The composite structure includes at least one first polymer layer and at least one first metal-containing layer. The bump structure also includes a second metal-containing layer at least partially... Agent: Duane Morris LLPIPDepartment (tsmc)

20080042270 - System and method for reducing stress-related damage to ball grid array assembly: A ball grid array (BGA) includes straight pins at the corners and if desired along the edges of the array that are engaged with a PCB to reduce stress on the solder balls. The pins can be on the chip substrate of the BGA or on a separate frame that... Agent: Rogitz & Associates

20080042274 - Components, methods and assemblies for stacked packages: A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly employed for mounting components to a... Agent: Tessera Lerner David Et Al.

20080042273 - High performance system-on-chip using post passivation process: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting... Agent: Mou-shiung Lin

20080042272 - Semiconductor device: A semiconductor device 100 has a BGA substrate 110, a semiconductor chip 101, a bump 106 and an underfill 108 filling the periphery of the bump. An interlayer dielectric 104 in the semiconductor chip 101 contains a low dielectric constant film. The bump 106 is comprised of a lead-free solder.... Agent: Smith, Gambrell & Russell, LLP

20080042271 - Trace design to minimize electromigration damage to solder bumps: A design methodology reduces electromigration in integrated circuit joints such as flip-chip bumps by seeking to produce a more uniform current distribution at the interface between the integrated circuit pad and the joint while maintaining an interface form that coincides with standard integrated circuit designs is presented. The design methodology... Agent: Kathy Manke Avago Technologies Limited

20080042277 - Bga package with leads on chip field of the invention: A BGA package primarily includes a plurality of leads from a leadless lead frame, a chip, and a die-attaching layer. The chip is electrically connected to the leads by a plurality of bonding wires. Solder balls are disposed at the ball placing regions of the leads. Encapsulant encapsulates the chip,... Agent: Troxell Law Office PLLC

20080042279 - Mounting structure of semiconductor device having flux and under fill resin layer and method of mounting semiconductor device: A mounting structure of a semiconductor device and a method of mounting the semiconductor device are provided. The mounting structure includes a circuit substrate having a terminal pad. A device substrate is located over the circuit substrate having a ball pad facing the terminal pad of the circuit substrate. A... Agent: Marger Johnson & Mccollom, P.C.

20080042275 - Structure for bumped wafer test: A semiconductor package includes a substrate having a bond pad disposed on a top surface of the substrate. A first passivation layer is formed over the substrate and bond pad. The first passivation layer has an opening to expose the bond pad. An under bump metallurgy is formed over the... Agent: Quarles & Brady LLP

20080042278 - Substrate structure having n-smd ball pads: The present invention relates to a substrate structure having non-solder mask design (N-SMD) ball pads. The substrate structure comprises a substrate and a solder mask. The substrate has a first surface, a trace layer and at least one ball pad. The ball pad and the trace layer are disposed on... Agent: Volentine & Whitt PLLC

20080042276 - System and method for reducing stress-related damage to ball grid array assembly: A printed circuit board (PCB) for supporting a ball grid array (BGA) includes stress relief features to reduce stress on the solder balls. The stress relief features can be plural lines formed into the PCB along the edges of the BGA, and/or holes formed through the PCB near the corners... Agent: Rogitz & Associates

20080042281 - Semiconductor device and semiconductor device fabrication method: A semiconductor device includes: a semiconductor substrate; a first insulation film that is formed on the semiconductor substrate and includes grooves (including through holes); a metal film that is formed inside the grooves and includes a first metal (e.g., titanium (Ti)); a glue film formed on a side surface of... Agent: Rabin & Berdo, PC

20080042280 - Semiconductor chip structure: A semiconductor chip structure includes a semiconductor substrate, an circuit structure, a passivation layer, a first adhesion/barrier layer, a metal cap and a metal layer. The semiconductor substrate has multiple electric devices located on a surface layer of a surface of the substrate. The circuit structure had multiple circuit layers... Agent: Megica Corporation

20080042282 - Semiconductor integrated circuit device and a method of manufacturing the same: A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor substrate. Thereafter, the barrier layer and the copper film are removed from outside of the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080042283 - Treatment of plasma damaged layer for critical dimension retention, pore sealing and repair: An interconnect structure and method of fabricating the same in which the critical dimension of the conductive features are not altered by a plasma damaged layer are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modifies the density of... Agent: Scully, Scott, Murphy & Presser, P.C.

20080042287 - Integrated circuit chip utilizing oriented carbon nanotube conductive layers: A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20080042285 - Post passivation interconnection schemes on top of ic chip: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin

20080042286 - Semiconductor device: A semiconductor device comprises a substrate, a first conductive film, a first insulation film, a second insulation film, a second conductive film, and a third conductive film. The first conductive film is formed on the substrate. The first insulation film is formed on the first conductive film and has a... Agent: Rabin & Berdo, PC

20080042284 - Semiconductor integrated circuit and the method of designing the layout: The semiconductor integrated circuit of the present invention comprises: a standard cell group including a power supply wiring group or a ground wiring group, which is arranged at an interval based upon a design rule; a connection wiring that is provided in a same layer as the standard cell group... Agent: Mcdermott Will & Emery LLP

20080042288 - Method for manufacturing display device: When a conductive layer is formed, a first liquid composition containing a conductive material is applied on an outer side of a pattern that is desired to be formed (corresponding to a contour or an edge portion of a pattern), and a first conductive layer (insulating layer) having a frame-shape... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080042289 - High performance system-on-chip using post passivation process: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting... Agent: Mou-shiung Lin

20080042290 - Structures electrically connecting aluminum and copper interconnections and methods of forming the same: A structure and formation method for electrically connecting aluminum and copper interconnections stabilize a semiconductor metallization process using an inner shape electrically connecting the aluminum and copper interconnections. To this end, a copper interconnection is disposed on a semiconductor substrate. An interconnection induction layer and an interconnection insertion layer are... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080042291 - Copper contact via structure using hybrid barrier layer: Contact via structures using a hybrid barrier layer, are disclosed. One contact via structure includes: an opening through a dielectric to a silicide region; a first layer in the opening in direct contact with the silicide region, wherein the first layer is selected from the group consisting of: titanium (Ti)... Agent: Hoffman, Warnick & D'alessandro LLC

20080042292 - Bond pad for wafer and package for cmos imager: An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect... Agent: Scully, Scott, Murphy & Presser, P.C.

20080042293 - Post passivation interconnection schemes on top of ic chip: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin Science-based Industrial Park

20080042294 - Post passivation interconnection schemes on top of ic chip: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin

20080042295 - Post passivation interconnection schemes on top of ic chip: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin

20080042296 - Post passivation interconnection schemes on top of the ic chips: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: North America Intellectual Property Corporation

20080042297 - Post passivation interconnection schemes on top of the ic chips: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a... Agent: Megica Corporation

20080042298 - Semiconductor devices and methods of fabricating the same: Embodiments include a semiconductor device comprising: a pad formed on an insulating layer and having an electric connection region with external components; and a protective insulating layer which has an aperture for exposing the electric connection region. The protective insulating layer may include a first insulating layer and a second... Agent: Konrad Raynes & Victor, LLP

20080042299 - Interconnections for crosswire arrays: A system includes a first crosswire array, having first input wiring and first output wiring, and a second crosswire array, having second input wiring and second output wiring, wherein the first crosswire array and second crosswire array are provided on or above the same side of a first substrate. A... Agent: Blaise Mouttet

20080042300 - Circuit substrate and semiconductor device: A circuit substrate for improving the reliability and productivity of a semiconductor device, and that semiconductor device. In a circuit substrate to which a semiconductor element is to be flip-chip mounted, at least one island-shaped electrically conductive layer is selectively disposed together with a wiring layer at an element mounting... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080042301 - Semiconductor device package and manufacturing method: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The... Agent: Birch Stewart Kolasch & Birch

20080042302 - Plastic overmolded packages with molded lid attachments: The specification describes lidded IC plastic overmolded packages with chimney-type heat sinks. The packages have mechanical hold-down structures in the package lids that, when overmold is applied, form complementary hold-down structures in the overmold.... Agent: Law Firm Of Peter V.d. Wilde

20080035905 - Chalcogenide switch with laser recrystallized diode isolation device and use thereof in three dimensional memory arrays: A three-dimensional memory array formed of one or more two-dimensional memory arrays of one-time programmable memory elements arranged in horizontal layers and stacked vertically upon one another; and a two-dimensional memory array of reprogrammable phase change memory elements stacked on the one or more two-dimensional memory arrays as the top... Agent: Energy Conversion Devices, Inc.

20080035909 - Method for controlling color contrast of a multi-wavelength light-emitting diode: A method for controlling the color contrast of a multi-wavelength light-emitting diode (LED) made according to the present invention is disclosed. The present invention includes at least the step of increasing the junction temperature of a multi-quantum-well LED, such that holes are distributed in a deeper quantum-well layer of the... Agent: Rosenberg, Klein & Lee

20080035911 - Efficient construction of quantum computatitonal clusters: A method of creating two-dimensional quantum computational cluster states is demonstrated that is considerably more efficient than previously proposed approaches. The method uses local unitaries and type-I fusion operations. The increased efficiency of the method compared to previously proposed constructions is obtained by identifying and exploiting local equivalence properties inherent... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080035917 - Array substrate for liquid crystal display device and method of fabricating the same: An array substrate for a liquid crystal display device includes: a data line on a substrate; a source electrode contacting the data line, a drain electrode spaced apart from the source electrode and a pixel electrode connected to the drain electrode, wherein the source electrode, the drain electrode and the... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20080035912 - Field-effect transistor, method of manufacturing the same, and electronic device using the same: A field-effect transistor includes a semiconductor layer (14), a source electrode (15) and a drain electrode (16) electrically connected to the semiconductor layer (14), and a gate electrode (12) for applying an electric field to the semiconductor layer (14) between the source electrode (15) and the drain electrode (16). The... Agent: Hamre, Schumann, Mueller & Larson P.C.

20080035913 - Molecular resonant tunneling diode: Molecular resonant tunneling diode (RTD) devices that include a molecular linker or bridge between two carbon nanotube (CNT) leads. Such devices include organic material self-assembled between two leads to yield RTD device behavior without the use of metallization of the organic material. Such devices alleviate the aforementioned problems associated with... Agent: Townsend And Townsend And Crew, LLP

20080035919 - Thin film transistor array panel and method of manufacturing the same: Disclosed is a thin film transistor array panel including a substrate, a data line formed on the substrate, a gate line that intersects the data line and includes a gate electrode, a source electrode connected to the data line, and a drain electrode facing the source electrode. An organic semiconductor... Agent: Macpherson Kwok Chen & Heid LLP

20080035914 - Use of perylene diimide derivatives as air-stable n-channel organic semiconductors: The present invention relates to the use of perylene diimide derivatives as air-stable n-type organic semiconductors.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080035920 - Thin-film transistor array, method of fabricating the same, and liquid crystal display device including the same: A thin-film transistor array includes an electrically insulating substrate, a plurality of thin-film transistors arranged in a matrix on the substrate, and each including a channel, a source, and a drain each comprised of an oxide-semiconductor film, a pixel electrode integrally formed with the drain, a source signal line through... Agent: Scully Scott Murphy & Presser, PC

20080035922 - Display apparatus and enable circuit thereof: A display apparatus comprises a display array and an enable circuit. The enable circuit comprises a set of diodes and a set of transistors. The diode element comprises a first contact and a second contact. The set of transistors comprises a first contact, a second contact, and a third contact.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080035921 - Method and circuit for detecting and compensating for a degradation of a semiconductor device: A degradation detection method and circuit system for responding to degradation. The circuit system is located within a semiconductor device and comprises a process sensitive circuit, a measurement circuit, and a calculation circuit. The method comprises subjecting the semiconductor device to a first operating condition. A first value at a... Agent: Schmeiser, Olsen & Watts

20080035923 - Semiconductor device with damage detection circuit and method for producing the same: A semiconductor chip having a current source coupled between a first potential and an electrical node, a detection circuit having an input coupled to the electrical node, and a first active component coupled in series with the current source and further coupled between the electrical node and a second potential,... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20080035926 - Display device and display device manufacturing method: An active matrix type display device, wherein a pixel circuit is formed using a plurality of thin film transistors in which thin semiconductor films forming channel regions of the thin film transistors are made in different crystal states.... Agent: Sonnenschein Nath & Rosenthal LLP

20080035925 - Liquid crystal display device and manufacturing method thereof: A lower substrate for a liquid crystal display device and the method of making the same are disclosed. The method includes steps of: (a) providing a substrate; (b) forming a patterned transparent layer having plural recess on the substrate; (c) forming a first barrier layer on the surface of the... Agent: Bacon & Thomas, PLLC

20080035928 - Vertical electromechanical memory devices and methods of manufacturing the same: In a memory device and a method of forming a memory device, the device comprises a substrate, a first electrode extending in a vertical direction relative to the substrate, and a second electrode extending in a vertical direction relative to the substrate, the second electrode being spaced apart from the... Agent: Mills & Onello LLP

20080035929 - Organic light emitting display devices and methods for fabricating the same: Organic light emitting display (OLED) devices and methods for fabricating the same are disclosed. An exemplary OLED device comprises a substrate with a thin film transistor (TFT) formed over a first portion thereof. A color filter layer is formed over a second portion of the substrate. A planarization layer overlies... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080035931 - Pixel having intrinsic semiconductor as an electrode and electroluminescent displays employing such a pixel: A pixel employable by a display device, including a plurality of transistors, including a first transistor having a gate electrode, and a capacitor including a first terminal connected to the gate electrode of the first transistor and a second terminal that is an intrinsic semiconductor.... Agent: Lee & Morse, P.C.

20080035933 - Thin film transistor array substrate, manufacturing method thereof and display device: A thin film transistor array substrate includes a polysilicon layer having a predetermined pattern shape formed over a substrate, a first gate insulating film provided over the substrate and on the surface of the polysilicon layer and having a same polished surface as the surface of the polysilicon layer and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080035930 - Thin film transistor substrate, manufacturing method of thin film transistor, and display device: A thin film transistor substrate includes a first conductive layer formed on a substrate, an anti-diffusion layer deposited on the first conductive layer, a semiconductor layer formed on the anti-diffusion layer, a gate insulating layer deposited on the semiconductor layer, a second conductive layer formed on the gate insulating layer,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080035936 - Gan based led with improved light extraction efficiency and method for making the same: A light-emitting device and the method for making the same are disclosed. The device includes a substrate, a light-emitting structure and a light scattering layer. The light-emitting structure includes an active layer sandwiched between a p-type GaN layer and an n-type GaN layer, the active layer emitting light of a... Agent: The Law Offices Of Calvin B. Ward Suite 305

20080035935 - Surface mountable chip: A surface mountable device having a circuit device and a base section. The circuit device includes top and bottom layers having a top contact and a bottom contact, respectively. The base section includes a substrate having a top base surface and a bottom base surface. The top base surface includes... Agent: The Law Offices Of Calvin B. Ward

20080035939 - Method of fabricating semiconductor devices on a group iv substrate with controlled interface properties and diffusion tails: Electronic and opto-electronic devices having epitaxially-deposited III/V compounds on vicinal group IV substrates and method for making same. The devices include an AlAs nucleating layer on a Ge substrate. The group IV substrate contains a p-n junction whose change of characteristics during epitaxial growth of As-containing layers is minimized by... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080035943 - Device chip carriers, modules, and methods of forming thereof: The present invention provides novel methods of forming component carriers, component modules, and the carriers and modules formed therefrom which utilize thick film technology. In some embodiments, these methods are used to form lighting device chip carriers and modules. In further embodiments, these lighting device chip carriers and modules are... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20080035941 - Radiation-emitting thin-film semiconductor chip: A radiation-emitting thin-film semiconductor chip with an epitaxial multilayer structure (12), which contains an active, radiation-generating layer (14) and has a first main face (16) and a second main face (18)—remote from the first main face—for coupling out the radiation generated in the active, radiation-generating layer. Furthermore, the first main... Agent: Thomas Langer Cohen Pontani Lieberman & Pavane

20080035949 - Nitride semiconductor light emitting device and method of manufacturing the same: A nitride semiconductor light emitting device includes a conductive substrate, a first metal layer, a second conductivity-type semiconductor layer, an emission layer, and a first conductivity-type semiconductor layer in this order. The nitride semiconductor light emitting device additionally has an insulating layer covering at least side surfaces of the second... Agent: Morrison & Foerster LLP

20080035947 - Surface mount light emitting chip package: A surface mount light emitting package includes a chip carrier having top and bottom principal surfaces. At least one light emitting chip is attached to the top principal surface of the chip carrier. A lead frame attached to the top principal surface of the chip carrier. When surface mounted to... Agent: Fay Sharpe LLP

20080035906 - Germanium compound, semiconductor device fabricated using the same, and methods of forming the same: A germanium (Ge) compound is provided. The Ge compound has a chemical formula GeR1xR2y. “R1” is an alkyl group, and “R2” is one of hydrogen, amino group, allyl group and vinyl group. “x” is greater than zero and less than 4, and the sum of “x” and “y” is equal... Agent: Marger Johnson & Mccollom, P.C.

20080035907 - Composite chalcogenide materials and devices: An electrical device includes a composite switching material. The composite switching material includes an electrically switchable component and a non-switchable component. In one embodiment, the composite switching material includes a heterogeneous mixture of at least one chalcogenide material and at least one dielectric material. The composite switching material is disposed... Agent: Honigman Miller Schwartz & Cohn LLP

20080035908 - Group iii nitride semiconductor light-emitting device:

20080035910 - Nitride semiconductor light-emitting device: In a nitride semiconductor light-emitting device (11), an emission region (17) has a quantum well structure (19), and lies between an n-type gallium nitride semiconductor region (13) and a p-type gallium nitride semiconductor region (15). The quantum well structure (19) includes a plurality of first well layers (21) composed of... Agent: Judge Patent Associates

20080035916 - Light emitting element:

20080035918 - Organic thin-film transistor and method for manufacturing the same: An organic thin-film transistor and a method for manufacturing the same are described. The method forms a gate layer on a substrate, an insulator layer on the substrate, forming a semiconductor layer on the insulator layer, and a strip for defining a channel length on the semiconductor layer. An electrode... Agent: Rabin & Berdo, PC

20080035915 - Semiconductor film comprising discrete domains of an organic semiconductor and a method of its fabrication: According to a first aspect, the present invention provides a method for forming a semiconductor film comprising a first step of providing a solution comprising a first organic semiconductor and a second organic semiconductor on a surface of a substrate. The solution is then dried to form the semiconductor film... Agent: Oliff & Berridge, PLC

20080035924 - Esd protection structures for semiconductor components: An ESD protection structure includes a structure to be protected disposed in a semiconductor body. A region of a first conductivity type is disposed within the semiconductor body and a channel is disposed in the semiconductor body and extends through the region of the first conductivity type. A semiconductor of... Agent: Slater & Matsil LLP

20080035927 - Semiconductor device having a pixel matrix circuit that includes a pixel tft and a storage capacitor: In a CMOS circuit formed on a substrate 100, a subordinate gate wiring line (a first wiring line) 102a and main gate wiring line (a second wiring line) 113a are provided in an n-channel TFT. The LDD regions 107a and 107b overlap the first wiring line 102a and not overlap... Agent: Nixon Peabody, LLP

20080035932 - Thin film transistor and organic electroluminescence display using the same: A thin film transistor (TFT) having a lightly doped drain (LDD) structure includes a lightly doped drain (LDD) region formation pattern, an active layer formed in an uneven structure on the LDD region formation pattern, and having a source region and a drain region having an LDD region. A gate... Agent: H.c. Park & Associates, PLC

20080035934 - Passivation of wide band-gap based semiconductor devices with hydrogen-free sputtered nitrides: An improved field effect transistor formed in the Group III nitride material system includes a two part structure in which a chemical vapor deposited passivation layer of silicon nitride encapsulates a previously sputtered-deposited layer of silicon nitride. The sputtered layer provides some of the benefits of passivation and the chemical... Agent: Summa, Allan & Additon, P.A.

20080035937 - Array substrate and method of manufacturing the same: A method or manufacturing an array substrate at a low cost. Silicon patterns are formed. A first impurity is implanted at a high concentration. Gate metal patterns are formed. A second impurity is implanted. The first impurity is implanted at a low concentration. A pixel electrode is formed. The first... Agent: Frank Chau F. Chau & Associates, LLC

20080035938 - Thermally coupled light source for an image projection system: In accordance with the invention a light source for an image projection system comprises one or more LEDs packaged for high temperature operation. Advantageously, the LED die are disposed on a package comprising a ceramic coated metal base including one or more underlying thermal connection pads, and underlying electrical connection... Agent: Darby & Darby P.C.

20080035940 - Selective smile formation under transfer gate in a cmos image sensor pixel: A pixel includes a photodiode and a transfer transistor. The transfer transistor is formed between the photodiode and a floating node and selectively operative to transfer a signal from the photodiode to the floating node. The transfer transistor has a bird's beak structure formed at the interface of its transfer... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080035945 - High brightness led package: Light sources are disclosed utilizing LED dies that have a light emitting surface. A patterned low refractive index layer that can support total internal reflection within the LED die is provided in optical contact with a first portion of the emitting surface. In optical contact with a second portion of... Agent: 3m Innovative Properties Company

20080035942 - Light emitting device package and method for manufacturing the same: A light emitting device package capable of emitting uniform white light and a method for manufacturing the same are disclosed. The light emitting device package includes a package body, an electrode formed on at least one surface of the package body, a light emitting device mounted on the package body,... Agent: Mckenna Long & Aldridge LLP

20080035944 - Radiation emitting element: A radiation-emitting component (10) having a layer stack (1) which is based on a semiconductor material and which has an active layer sequence (4) for generating electromagnetic radiation, and a filter element (2) which is arranged after the active layer sequence (4) in the irradiation direction (A) and by means... Agent: Cohen Pontani Lieberman & Pavane LLP

20080035946 - Rare earth element-doped silicon oxide film electroluminescence device: A method is provided for forming a rare earth (RE) element-doped silicon (Si) oxide film with nanocrystalline (nc) Si particles. The method comprises: providing a first target of Si, embedded with a first rare earth element; providing a second target of Si; co-sputtering the first and second targets; forming a... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080035948 - Light emitting diode package: A light emitting diode package for preventing an electric short circuit among semiconductor layers and with excellent bonding strength. The light emitting diode package includes a package substrate, a light emitting diode chip bonded to an upper surface of the package substrate, and a bonding material for bonding the light... Agent: Mcdermott Will & Emery LLP

20080035951 - Selective growth method, nitride semiconductor light emitting device and manufacturing method of the same: A method for selectively growing a nitride semiconductor, in which a mask is formed, with an opening formed therein, on a nitride semiconductor layer. A nitride semiconductor crystal is selectively grown on a portion of the nitride semiconductor layer exposed through the opening in the mask, the nitride semiconductor crystal... Agent: Mcdermott Will & Emery LLP

20080035953 - Gallium nitride-based light emitting diode and method of manufacturing the same: A vertical GaN-based LED comprises an n-electrode; an n-type GaN layer formed under the n-electrode, the n-type GaN layer having an irregular-surface structure which includes a first irregular-surface structure having irregularities formed at even intervals and a second irregular-surface structure having irregularities formed at uneven intervals, the second irregular-surface structure... Agent: Mcdermott Will & Emery LLP

20080035950 - Method to make low resistance contact: Techniques for fabricating contacts on inverted configuration surfaces of GaN layers of semiconductor devices are provided. An n-doped GaN layer may be formed with a surface exposed by removing a substrate on which the n-doped GaN layer was formed. The crystal structure of such a surface may have a significantly... Agent: Patterson & Sheridan, L.L.P.

20080035952 - Photonic device: Embodiments of methods, apparatuses, devices, or systems for forming a photonic device are described.... Agent: Hewlett Packard Company

20080035954 - Semiconductor device: A semiconductor device includes a photodiode formed using a silicon substrate, a wide-bandgap semiconductor layer formed on the silicon substrate and having a bandgap larger than that of silicon, and a switching element formed using the wide-bandgap semiconductor layer. The switching element is electrically connected to the photodiode so as... Agent: Birch Stewart Kolasch & Birch

20080035955 - Semiconductor device and method for manufacturing the same: By a non-selective epitaxial growth method, an SiGe film is grown on the whole surface of a silicon oxide film so as to cover an inner wall of a base opening. Here, such film forming conditions are selected that, inside the base opening, a bottom portion is formed of single... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080035956 - Memory device with non-orthogonal word and bit lines: A semiconductor memory device such as a dynamic random access memory (DRAM) has substantially non-orthogonal word and bit lines. For a given memory cell size, such as six square lithographic features (6F2), the non-orthogonal layout allows for larger-pitch word and bit lines when compared to the orthogonal layout of the... Agent: Schwegman, Lundberg & Woessner, P.A.

20080035959 - Chip scale package for power devices and method for making the same: A chip scale package is disclosed that includes a semiconductor die further comprising an array of power buses electrically coupled to a high power integrated circuit, and a plurality of Under Bump Metallization (UBM) multi-layer power buses disposed parallel to one another and spanning substantially across the entire length of... Agent: Perkins Coie LLP Patent-sea

20080035957 - Complementary metal oxide semiconductor (cmos) image sensor: An improved complementary metal oxide semiconductor (CMOS) image sensor which may decrease the occurrence of dark current is provided. The CMOS image sensor includes a plurality of isolation regions formed in a substrate and a first impurity-doped region formed between the isolation region and separated from a side surface of... Agent: F. Chau & Associates, LLC

20080035958 - Magnetic random access memory: A magnetic random access memory includes a semiconductor substrate having a projection projecting from a substrate surface, first and second gate electrodes and a first source diffusion layer formed on first and second side surfaces and an upper surface of the projection, first and second drain diffusion layers formed in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080035960 - Electromechanical memory devices and methods of manufacturing the same: In a memory device and a method of forming the same, in one embodiment, the memory device comprises a first word line structure on a substrate, the first word line structure extending in a first direction. A bit line is provided over the first word line structure and spaced apart... Agent: Mills & Onello LLP

20080035961 - Phase-change memory and fabrication method thereof: A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are... Agent: Quintero Law Office, PC

20080035962 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a recess channel that is formed on the inner surface of a recess region, which is formed on the semiconductor substrate between the source and drain regions, and in an epitaxial semiconductor film in... Agent: F. Chau & Associates, LLC

20080035964 - Cmos image sensor: Embodiments relate to a CMOS image sensor and a fabricating method thereof. In embodiments, a linear nitride layer formed on a semiconductor substrate may protect a gate oxide layer during a process of removing a silicide barrier layer, and may improve the performance of an CMOS image sensor.... Agent: Sherr & Nourse, PLLC

20080035963 - Image sensors including multiple slope/impurity layer isolation regions, and methods of fabricating same: Image sensors include a pixel region and a logic region. Pixel isolation regions in the pixel region include pixel isolation region walls that are less sloped than logic isolation region walls in the logic region. An impurity layer also may be provided adjacent at least some of the pixel isolation... Agent: Myers Bigel Sibley & Sajovec

20080035965 - Photoelectric conversion element and solid-state image pickup device: A photoelectric conversion element comprises a photoelectric conversion section that includes: a pair of electrodes; and a photoelectric conversion layer disposed between the pair of electrodes, wherein the photoelectric conversion section further comprises between one of the pair of electrodes and the photoelectric conversion layer a first charge-blocking layer that... Agent: Sughrue-265550

20080035967 - Cmos image sensor and manufacturing method thereof: A CMOS image sensor includes isolation regions and a photo diode region formed in a substrate, gate electrodes formed on the substrate, impurity injection regions formed in the substrate respectively positioned between the gate electrodes and the isolation regions, silicide regions formed on upper surfaces of the gate electrodes and... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080035969 - Cmos image sensors and methods of forming the same: Example embodiments may provide a CMOS image sensor and example methods of forming the same. Example embodiment CMOS image sensors may include a transfer gate insulating pattern between a transfer gate and an active region. A photodiode region and/or a floating doped region may be in the active region at... Agent: Harness, Dickey & Pierce, P.L.C

20080035966 - Cmos image sensor and method of driving the same: A complementary metal-oxide semiconductor (CMOS) image sensor and a method of driving the CMOS image sensor that can reduce the number of devices required by each of a plurality of pixels and can stably drive the pixels, in which each of the pixels includes a photodiode that converts light energy... Agent: F. Chau & Associates, LLC

20080035968 - Image sensor and method of forming the same: An image sensor includes a semiconductor substrate, a photo receiving area in the semiconductor substrate, a gate electrode installed in a lateral side of the photo receiving area on the semiconductor substrate, and a patterned dielectric layer covering the gate electrode, the photo receiving area, and exposing a partial gate... Agent: North America Intellectual Property Corporation

20080035970 - Semiconductor device including ferroelectric capacitor: A semiconductor device includes a ferroelectric capacitor formed above the lower interlevel insulating film covering a MOS transistor formed on a semiconductor substrate, including lamination of a lower electrode, an oxide ferroelectric film, a first upper electrode made of conductive oxide having a stoichiometric composition AOx1 and an actual composition... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080035972 - High performance system-on-chip using post passivation process: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting... Agent: Mou-shiung Lin

20080035971 - Thin film transistor array panel for a liquid crystal display and method for manufacturing the same: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to... Agent: Cantor Colburn, LLP

20080035973 - Low-noise single-gate non-volatile memory and operation method thereof: The present invention discloses a low-noise single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the electrically-conductive gate of the transistor and the electrically-conductive gate of the capacitor structure are interconnected to form a single floating gate of... Agent: Sinorica, LLC

20080035974 - High performance system-on-chip using post passivation process: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting... Agent: Mou-shiung Lin

20080035975 - Semiconductor memory device and manufacturing method thereof: A semiconductor memory device includes: a transistor formed in a substrate; a capacitor formed above one of source/drain regions of the transistor; a bit line formed above the substrate and extending in the gate length direction of the transistor; a first conductive plug connecting one of the source/drain regions and... Agent: Mcdermott Will & Emery LLP

20080035977 - Integrated circuit (ic) with high-q on-chip discrete capacitors: A semiconductor structure that may be a discrete capacitor, a Silicon On Insulator (SOI) Integrated Circuit (IC) including circuits with discrete such capacitors and/or decoupled by such discrete capacitors and an on-chip decoupling capacitor (decap). One capacitor plate may be a well (N-well or P-well) in a silicon bulk layer... Agent: Law Office Of Charles W. Peterson, Jr. Burlington

20080035976 - Semiconductor device having box-shaped cylindrical storage nodes and fabrication method thereof: A method of forming box-shaped cylindrical storage nodes includes forming an interlayer insulating layer on a semiconductor substrate. Buried contact plugs are formed to penetrate the interlayer insulating layer. A molding layer and a photoresist layer are then sequentially formed on the substrate. Using a first phase shift mask having... Agent: Volentine & Whitt PLLC

20080035978 - Method to eliminate arsenic contamination in trench capacitors: A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as... Agent: Scully, Scott, Murphy & Presser, P.C.

20080035979 - Capacitive electrode having semiconductor layers with an interface of separated grain boundaries: The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080035980 - Mask for forming contact hole: Embodiments relate to a mask in which a mask pattern used for forming a contact hole may be designed such that any one of a horizontal-axis length and a vertical-axis length may be greater than the other in a photolithography process for forming the contact hole. In embodiments, a method... Agent: Sherr & Nourse, PLLC

20080035982 - Contactless nonvolatile memory array: An array of memory cells with non-volatile memory transistors having a compact arrangement of diagonally symmetric floating gates. The floating gates have portions extending in both X and Y directions, allowing them to be charged through a common tunnel oxide 8stripe that runs under a portion of each, for example... Agent: Schneck & Schneck

20080035981 - One time programmable memory and the manufacturing method thereof: A one time programmable memory including a first memory cell is provided. The first memory cell is disposed on a substrate having a trench disposed therein. The first memory cell includes a floating gate, a select gate, a first doped region, a second doped region and a third doped region.... Agent: Jianq Chyun Intellectual Property Office

20080035984 - Flash memory device and method of fabricating the same: One embodiment of a method of fabricating a flash memory device includes forming a trench mask pattern, which includes a gate insulation pattern and a charge storage pattern stacked in sequence, on a semiconductor substrate; etching the semiconductor substrate using the trench mask pattern as an etch mask to form... Agent: Marger Johnson & Mccollom, P.C.

20080035983 - Nanoscale floating gate and methods of formation: A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control... Agent: Brooks, Cameron & Huebsch , PLLC

20080035985 - Semiconductor device and method of manufacturing the same: Each of a plurality of convex patterns is formed on the front surface of a semiconductor substrate so that it may have a floating gate and a control gate. The insulating layer has covered the side surface and the upper surface of a plurality of convex patterns, and the bottom... Agent: Mcdermott Will & Emery LLP

20080035986 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device having a non-volatile memory cell includes forming an insulation layer as an uppermost/outermost portion of the memory cell to enhance the charge retention capability of the memory cell. The insulation layer is formed after the gate structure and integrate dielectric of the non-volatile... Agent: Volentine & Whitt PLLC

20080035989 - Fabricating process and structure of trench power semiconductor device: A process for fabricating a trench power semiconductor device is disclosed. A first dielectric layer between the pad oxide layer and the mask oxide layer is formed so as to form a gate with a height higher than the surface of the pad oxide layer after the first dielectric layer... Agent: Bacon & Thomas, PLLC

20080035987 - Inverted-trench grounded-source fet structure using conductive substrates, with highly doped substrates: This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench... Agent: Bo-in Lin

20080035990 - Semiconductor device and method of manufacturing the same: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a... Agent: Miles & Stockbridge PC

20080035988 - Trenched mosfet device with trenched contacts: A trenched semiconductor power device that includes a trenched gate disposed in an extended continuous trench surrounding a plurality of transistor cells in an active cell area and extending as trench-gate fingers to intersect with a trenched gate under the gate metal runner at a termination area. At least one... Agent: Bo-in Lin

20080035992 - Semiconductor device: A source electrode is electrically connected to the source region and a semiconductor base layer. Plural gate electrodes are formed through a gate insulation film so that a semiconductor base layer may be sandwiched by the gate electrodes. The width of the semiconductor base layer sandwiched by the gate electrodes... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080035991 - Transistor having recess channel structure and fin structure, semiconductor device employing the transistor, and method of fabricating the semiconductor device: A semiconductor device includes an upper gate trench crossing an active region of a semiconductor substrate, a lower gate trench overlapping the upper gate trench at both ends, disposed at a lower level than the upper gate trench, and having a smaller width than the upper gate trench and wherein... Agent: F. Chau & Associates, LLC

20080035993 - Termination design for deep source electrode mosfet: A power semiconductor device that includes a plurality of source trenches that extend to a depth below the gate electrodes and a termination region that includes a termination trench that is as deep as the source trenches.... Agent: Ostrolenk Faber Gerb & Soffen

20080035994 - Semiconductor device and method of manufacturing the same: A semiconductor device and a method of manufacturing the same are provided, capable of minimizing a size of the semiconductor device and inhibiting punch through. According to an embodiment, at least one conductive bar is formed in a substrate between source and drain regions. Thereby, punch through can be inhibited... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080035995 - System for displaying images including thin film transistor device and method for fabricating the same: A system for displaying images. The system comprises a thin film transistor (TFT) device comprising a substrate having a pixel region. An active layer is disposed on the substrate of the pixel region, comprising a channel region, a pair of source/drain regions separated by the channel region. The channel region... Agent: Liu & Liu

20080035997 - Fin field-effect transistor and method for fabricating a fin field-effect transistor: A fin field-effect transistor has a substrate and a fin structure above the substrate, as well as a drain region and a source region outside the fin structure above the substrate. The fin structure serves as a channel between the source region and the drain region. The source and drain... Agent: Slater & Matsil, L.L.P.

20080036000 - Planar dual-gate field effect transistors (fets): A semiconductor structure and the associated method for fabricating the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a back gate region on the semiconductor substrate, (c) a back gate dielectric region on the back gate region, (d) a semiconductor region on the back gate dielectric region comprising... Agent: Schmeiser, Olsen & Watts

20080035998 - Pseudo soi substrate and associated semiconductor devices: The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material... Agent: Williams, Morgan & Amerson

20080035996 - Semiconductor device and method of manufacturing the same: A semiconductor device having an SOI structure including a semiconductor substrate, a buried insulating layer and an SOI layer including, first and second element formation regions provided in said SOI layer, a partial isolation region including a partial insulating film provided in an upper layer portion of said SOI layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080035999 - Thin-film transistor display devices having composite electrodes: Methods of forming thin-film transistor display devices including forming a gate line and a gate electrode on a face of a substrate and forming a semiconductor layer that is insulated from the gate line. A data line and a source/drain electrode are formed on the semiconductor layer. The data line... Agent: Myers Bigel Sibley & Sajovec

20080036001 - Semiconductor devices having field effect transistors: A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity... Agent: Marger Johnson & Mccollom, P.C.

20080036002 - Semiconductor device and method of fabricating semiconductor device: Surge current, which flows-in from an exterior due to ESD or the like, is prevented from directly flowing-into a supporting substrate. A semiconductor device has: an element-isolating insulating film sectioning an SOI layer into an active region and a field region; a resistance element formed at the field region; one... Agent: Rabin & Berdo, PC

20080036003 - Backlighted membrane switch: A backlighted membrane switch includes a circuit board having a number of switch contacts, a plate spaced away from the circuit board and having a number of conductor contacts aligned with the switch contacts of the printed circuit for being selectively depressed to engage with the switch contacts of the... Agent: Charles E. Baxley, Esq.

20080036004 - Semiconductor apparatus with improved esd withstanding voltage: A semiconductor apparatus having an outer ESD protective circuit corresponding to each external connection terminal, the outer ESD protective circuit being formed in a peripheral region around the external connection terminals. The outer ESD protective circuit discharges electrostatic voltage from the external connection terminal and avoids the damaging of an... Agent: Dickstein Shapiro LLP

20080036005 - Cmos fabrication process utilizing special transistor orientation: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the <100> direction. Additionally, longitudinal tensile stress is applied to the channels.... Agent: Blakely Sokoloff Taylor & Zafman

20080036008 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes: a first gate insulating film formed on a first active region of a substrate; and a first gate electrode formed on the first gate insulating film. The second MIS transistor includes: a... Agent: Mcdermott Will & Emery LLP

20080036007 - Method of forming nitride films with high compressive stress for improved pfet device performance: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited... Agent: International Business Machines Corporation Dept. 18g

20080036006 - Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same: A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the... Agent: Volentine & Whitt PLLC

20080036009 - Jfet with built in back gate in either soi or bulk silicon: A Junction Field-Effect transistor with no surface contact for the back gate and twice as much transconductance in the channel and with a higher switching speed is achieved by intentionally shorting the channel-well PN junction with the gate region. This is achieved by intentionally etching away field oxide outside the... Agent: Ronald Craig Fish, A Law Corporation

20080036010 - Semiconductor device and manufacturing method thereof: A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and a second n-type... Agent: Mcdermott Will & Emery LLP

20080036011 - Semiconductor integrated circuit device: Latchup is prevented from occurring accompanying increasingly finer geometries of a chip. NchMOSFET N1 and PchMOSFET P1 form a CMOS circuit including: NchMOSFET N2 whose gate, drain and back gate are connected to back gate of N1 and PchMOSFET P2 whose gate, drain and back gate are connected to back... Agent: Young & Thompson

20080036013 - Semiconductor device and method for fabricating the same: The distance between a substrate contact portion and an active region in a p-type MIS transistor is greater than the distance between a substrate contact portion and an active region in an n-type MIS transistor. Alternatively, the length of a protruding part of a gate electrode of the p-type MIS... Agent: Mcdermott Will & Emery LLP

20080036012 - Strained mosfets on separated silicon layers: A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench insulation (STI) regions adjacent to the nFETs and pFETs thus can be... Agent: Hoffman, Warnick & D'alessandro LLC

20080036014 - Semiconductor device and method of fabricating the same: In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an impurity concentration peak at a position close to... Agent: Mcdermott Will & Emery LLP

20080036016 - Semiconductor device and method of manufacturing the same: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction.... Agent: Marger Johnson & Mccollom, P.C.

20080036015 - Semiconductor devices with sealed, unlined trenches and methods of forming same: A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20080036017 - Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance: A semiconductor device. The semiconductor device includes a substrate includes: a substrate having a first gate stack on a surface of the substrate, wherein the first gate stack has a top surface parallel to the surface of the substrate and sidewalls perpendicular to the surface of the substrate; an etch... Agent: Schmeiser, Olsen & Watts

20080036018 - Method of fabricating spacers and cleaning method of post-etching and semiconductor device: A method of fabricating spacers is provided. The method includes providing a substrate with a device structure formed thereon. The device structure comprises a gate structure and a pair of source/drain regions. Then, a spacer material layer is formed over the substrate to cover the substrate and the device structure.... Agent: J.c. Patents

20080036020 - Image sensor with a waveguide tube and a related fabrication method: An image sensor includes a substrate, at least an optical device, at least a dielectric layer, and at least a wave-guide tube disposed upon the optical device. The wave-guide tube has an optical barrier disposed on a sidewall thereof and a filter layer filled in the wave-guide tube. The structure... Agent: North America Intellectual Property Corporation

20080036019 - Photoelectric conversion device and manufacturing method thereof: The present invention, in a photoelectric conversion device in which a pixel including a photoelectric conversion device for converting a light into a signal charge and a peripheral circuit including a circuit for processing the signal charge outside a pixel region in which the pixel are disposed on the same... Agent: Fitzpatrick Cella Harper & Scinto

20080036022 - Image sensor and method of manufacturing the same: An image sensor and a method of manufacturing same is disclosed. The image sensor implements a reflecting film formed on a front surface of a substrate having a back-illuminated photodetector. The reflecting film operates to reflect wavelengths of light that were not received by the photodetector back to the photodetector... Agent: Volentine & Whitt PLLC

20080036023 - Image sensor having improved sensitivity and method of manufacturing the same: In an image sensor in which a vertical length from a photoelectric conversion element to an uppermost micro-lens is minimal, and a method of manufacturing the same, the image sensor includes a substrate, a plurality of photoelectric conversion elements, and first to n-level (where n is an integer greater than... Agent: Mills & Onello LLP

20080036024 - Image sensors and methods of manufacturing the same: An image sensor may include a semiconductor substrate having unit pixel regions on the semiconductor substrate; photoelectric converters formed in the unit pixel regions; interlayer insulating films covering the photoelectric converters and having opening portions formed above the photoelectric converters; a light-transmissive portion filling the opening portions; color filters formed... Agent: Harness, Dickey & Pierce, P.L.C

20080036021 - Semiconductor device having optical signal input-output mechanism: A semiconductor device has printed wiring board (11) where electric wiring (18) connected to LSI chip (17) and to planar optical element (21) is formed, and where optical waveguide (25) which transfers light inputted into planar optical element (21) and/or light outputted from planar optical element (21) is fixed. Planar... Agent: Sughrue Mion, PLLC

20080036025 - Image sensor package: An image sensor package includes a substrate having an upper surface, which is formed with a chip region and first electrodes located on the periphery of the chip region, and a lower surface. A chip is mounted on the chip region of the upper surface of the substrate. A frame... Agent: Pro-techtor International

20080036026 - Metal line of image sensor: A metal line of an image sensor and a method of fabricating a metal line of an image sensor having a transistor is disclosed, and in embodiments may include forming at least one interlayer insulating film in a semiconductor substrate having the transistor, forming a hole in the interlayer insulating... Agent: Sherr & Nourse, PLLC

20080036027 - Integrated circuit for a high-side transistor driver: The high voltage integrated circuit is disclosed. The high voltage integrated circuit comprises a low voltage control circuit, a floating circuit, a P substrate, a deep N well disposed in the substrate and a plurality of P wells disposed in the P substrate. The P wells and deep N well... Agent: J C Patents, Inc.

20080036028 - Dual trench isolation for cmos with hybrid orientations: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a... Agent: Scully, Scott, Murphy & Presser, P.C.

20080036029 - Semiconductor devices: A design structure embodied in a machine readable medium used in a design process. The design structure includes a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer, and a second sub-collector formed in an upper portion of the first... Agent: Greenblum & Bernstein, P.L.C

20080036030 - Process for manufacturing a wafer by annealing of buried channels: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.... Agent: Bryan A. Santarelli Graybeal Jackson Haley LLP

20080036031 - Fuse box for semiconductor device and method of forming same: A fuse box for a semiconductor device is disclosed and includes a first fuse group comprising a plurality of first fuses, arranged in a first direction and having a first cutting axis, each first fuse comprising a first portion having a first fuse pitch, a second portion having a second... Agent: Volentine & Whitt PLLC

20080036032 - Semiconductor device: A trimming element for trimming a redundant circuit and a high-accuracy resistance in consideration of the stability and the ease of fuse cutting, and more specifically a trimming element which is easily formed by an existing process. An SOI substrate, a heater connected to the SOI substrate, and a fuse... Agent: Miles & Stockbridge PC

20080036033 - One-time programmable memory: A one-time programmable memory. The memory has a substrate, a diffused electrode disposed on the substrate, a shallow trench isolation (STI) region formed on the substrate, a insulator formed on the STI region and the substrate, and a second electrode. The insulator separates the second electrode from the diffused electrode.... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080036034 - Lead frame with included passive devices: An semiconductor device package (10) includes a semiconductor device (die) (12) and passive devices (14) electrically connected to a common lead frame (17). The lead frame (17) is formed from a stamped and/or etched metallic structure and includes a plurality of conductive leads (16) and a plurality of interposers (20).... Agent: Wiggin And Dana LLP Attention: Patent Docketing

20080036035 - Method for manufacturing a passive integrated matching network for power amplifiers: An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second inductor coupled to the first... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080036036 - Semiconductor device and manufacturing method thereof: To easily obtain a resistance element with an adjustable resistance value, wherein the resistance value is within 1% or less of a desired design value, having a low parasitic capacitance and which permits a relatively large current to flow, in a semiconductor device wherein resistance elements are incorporated in a... Agent: Miles & Stockbridge PC

20080036037 - System and method for esd protection: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080036038 - Pulsed growth of catalyst-free growith of gan nanowires and application in group iii nitride semiconductor bulk material: Exemplary embodiments provide semiconductor devices including high-quality (i.e., defect free) group III-N nanowires and uniform group III-N nanowire arrays as well as their scalable processes for manufacturing, where the position, orientation, cross-sectional features, length and the crystallinity of each nanowire can be precisely controlled. A pulsed growth mode can be... Agent: Mh2 Technology Law Group, LLP

20080036040 - Semiconductor wafers with highly precise edge profile and method for producing them: A semiconductor wafer has a front side, a rear side and an edge which runs along the circumference of the semiconductor wafer and which connects the front side and the rear side of the edge having a defined edge profile, the edge profile being substantially constant over the entire circumference... Agent: Brooks Kushman P.C.

20080036039 - New structure for microelectronics and microsystem and manufacturing process: The invention relates to a process for making a semiconducting structure composed of a surface layer (2), at least one buried layer (4) and a support, comprising: —a first step to make a first layer (44) made of a first material on a first support, and at least one area... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080036041 - Production of semiconductor substrates with buried layers by joining (bonding) semiconductor wafers: The invention relates to a method for producing semiconductor substrates by bonding. The aim of said method is to reduce the non-usable edge region on the bonded wafer component and to improve the edge geometry of the wafer composite. This is achieved by a method for joining two semiconductor wafers... Agent: Stevens & Showalter LLP

20080036042 - Semiconductor device: A semiconductor device includes: a circuit region having a function element formed on a semiconductor substrate; a scribe region located between the circuit region and another circuit region formed spaced from the circuit region, the scribe region including a cutting region and non-cutting regions provided at both sides of the... Agent: Mcdermott Will & Emery LLP

20080036044 - Semiconductor optical device and manufacturing method therefor: To eliminate generation of a damaged layer caused by dry etching of a contact layer, occurring in a manufacturing process of a ridge waveguide type semiconductor laser, and to improve reliability and yield thereof, a method is provided involving forming a spacer layer and a damage receptor layer on the... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080036043 - Manufacture method for semiconductor device and semiconductor device: A manufacture method for semiconductor device (1, 21) including: a sealing-resin-layer forming step of forming a sealing resin layer (7) on a conductive member (13) formed at lest on one surface of a base substrate (11) formed with a plurality of wiring boards (2) therein, the conductive member spanning a... Agent: Rabin & Berdo, PC

20080036045 - Package-base structure of power semiconductor device and manufacturing process of the same: A process of manufacturing a package base of a power semiconductor device includes the following steps. Firstly, a semiconductor substrate including a first surface and a second surface is provided. Then, a portion of the semiconductor substrate is patterned and removed to form a recess on the first surface of... Agent: Kirton And Mcconkie

20080036046 - process for precision placement of integrated circuit overcoat material: The present invention provides a process for manufacturing an integrated circuit (IC) package and an integrated circuit (IC) package. The process, without limitation, includes providing an integrated circuit chip having a configuration, and forming a layer of overcoat material over the integrated circuit chip based upon the configuration.... Agent: Texas Instruments Incorporated

20080036047 - Low voltage transient voltage suppressor with reduced breakdown voltage: A semiconductor junction device includes a substrate of low resistivity semiconductor material having a preselected polarity. A tapered recess extends into the substrate and tapers inward as it extends downward from an upper surface of the substrate. A semiconductor layer is disposed within the recess and extends above the upper... Agent: Mayer & Williams PC

20080036048 - Semiconductor junction device having reduced leakage current and method of forming same: A semiconductor junction device includes a semiconductor substrate of a first conductivity type and a junction layer formed on the substrate which has a second conductivity type. A field reducing region of the first conductivity type surrounds a periphery of the junction layer and extends under a peripheral portion of... Agent: Mayer & Williams PC

20080036050 - Package with solder-filled via holes in molding layers: The present invention discloses an electronic package to contain and protect an integrated circuit (IC) chip. The electronic package further includes a leadframe, a flexible circuit or PCB type of substrate. The leadframe, flexible circuit or PCB type substrate further includes solder contacts, which are aligned with via holes in... Agent: Bo-in Lin

20080036049 - Stacked integration module and method for manufacturing the same: Disclosed is a stacked integration module having a small thickness while guaranteeing thermal and operational stabilities when operated at high frequencies. The stacked integration module includes a printed circuit board having first and second surfaces facing each other, at least one hole extending through the first and second surfaces, and... Agent: Cha & Reiter, LLC

20080036052 - Integrated circuit package system with supported stacked die: An integrated circuit package system provides a leadframe having a short lead finger, a long lead finger, and a support bar. A first die is placed in the leadframe. An adhesive is attached to the first die, the long lead finger, and the support bar. A second die is offset... Agent: Law Offices Of Mikio Ishimaru

20080036051 - Quad flat package: A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe... Agent: Quarles & Brady LLP

20080036053 - Reinforced micro-electromechanical system package structure: The present invention discloses a reinforced MEMS package structure, wherein after the wire-bonding process and before the molding process, an extra resin coating process is used to apply a protective resin onto the MEMS chip, the controller chip, the wires and a portion of the lead frame and provide an... Agent: Sinorica, LLC

20080036054 - Packaging system for semiconductor devices: A package system for integrated circuit (IC) chips and a method for making such a package system. The method uses a solder-ball flip-chip method for connecting the IC chips onto a lead frame that has pre-formed gull-wing leads only on the source/gate side of the chip. A boschman molding technique... Agent: Kenneth E. Horton Kirton & Mcconkle

20080036055 - Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant: A lead frame for making a semiconductor package is disclosed. The leadframe's leads include a lead lock provided at a free end of each inner lead that is adapted to increase a bonding force of the inner lead to a resin encapsulate, thereby effectively preventing a separation of the inner... Agent: Stetina Brunda Garred & Brucker

20080036056 - Flip chip in leaded molded package and method of manufacture thereof: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and... Agent: Townsend And Townsend And Crew, LLP

20080036057 - Semiconductor device having improved heat dissipation capabilities: A semiconductor device mountable to a substrate includes a semiconductor die and an electrically conductive lead frame having first and second end portions and a first attachment surface and a second attachment surface. The die electrically contacts the first end portion of the lead frame on the first attachment surface.... Agent: Mayer & Williams PC

20080036058 - Package substrate: A package substrate including a circuit board, a reinforcing plate and at least one conductive channel is provided. A first surface of the reinforcing plate is disposed on the circuit board for resisting the warpage of the circuit board. The reinforcing plate has an opening corresponding to a first contact... Agent: Jianq Chyun Intellectual Property Office

20080036061 - Integrated chip carrier with compliant interconnect: An electronic device includes: at least one electronic chip comprising a first coefficient of thermal expansion (CTE); and a carrier including a top side connected to the bottom side of the chip by solder bumps. The carrier further includes a second CTE that approximately matches the first CTE, and a... Agent: Michael J. Buchenhorner

20080036059 - Method for producing a module with components stacked one above another: The invention relates to a method in which components (101, 102) are provided, movement elements (104) are in each case applied to surfaces of a number of the components (101), and the components (101, 102) are stacked, so that one or a plurality of the movement elements (104) are situated... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080036062 - Multi-chip structure: A multi-chip structure at least including a first chip, a second chip and a first thermal-conductive layer is provided. The first chip has a first surface and a plurality of first pads disposed on the first surface. The second chip has a second surface facing the first surface and a... Agent: J C Patents, Inc.

20080036060 - Semiconductor chip packages and assemblies with chip carrier units: A microelectronic element package has one or more individual carrier units overlying a region or regions of the front or rear surface of the microelectronic element, leaving other regions of the microelectronic element surface uncovered. The carrier units can be made economically using only a small area of a dielectric... Agent: Tessera Lerner David Et Al.

20080036064 - Semiconductor device: A semiconductor device according to embodiments may include an interposer, a plurality of devices stacked on the interposer, a cooling device provided in at least one of the devices and including a passage for a cooling material, and a connection electrode provided between the devices, in which the connection electrode... Agent: Sherr & Nourse, PLLC

20080036063 - Semiconductor package having flexible lead connection plate for electrically connecting base and chip: A semiconductor package has a base, a chip attached to the base a flexible connection plate mounted on and electrically connecting the chip and the base, and an encapsulant encapsulating the chip and the flexible connection plate on the base. The flexible connection plate includes a film and a layer... Agent: Volentine & Whitt PLLC

20080036065 - Electronic device and method for producing a device: An electronic device or devices and method for producing a device is disclosed. One embodiment provides an integrated component, a first package body and a contact device. The contact device penetrates the package body.... Agent: Dicke, Billig & Czaja

20080036066 - Method of packaging and interconnection of integrated circuits: A method is disclosed for packaging semiconductor chips on a flexible substrate employing thin film transfer. The semiconductor chips are placed on a temporary adhesive substrate, then covered by a permanent flexible substrate with a casting layer for planarizingly embedding the chips on the permanent substrate before removing the temporary... Agent: James Sheats

20080036067 - Package structure with leadframe on offset chip-stacked structure: The present invention provides a package structure with lead-frame on stacked chips, comprising: a lead-frame, composed of a plurality of outer leads arranged in rows facing each other and a plurality of inner leads arranged in rows facing each other formed by a plurality of wires, wherein the plurality of... Agent: Reed Smith LLP

20080036068 - Stacked module systems and methods: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard associated with one or more CSPs provides a physical form that allows many of the varying package sizes found... Agent: Fish & Richardson P.C.

20080036069 - Production equipment of resin molding semiconductor device, method of manufacturing resin molding semiconductor device, and resin molding semiconductor device: A production equipment includes a substrate 2 placed inside and having a plurality of semiconductor elements 3 mounted thereon, and a resin molding mold 20 having a cavity 21. The mold 20 has resin injection ports 29a and air release ports 30a. Each of the resin injection ports 29a is... Agent: Steptoe & Johnson LLP

20080036070 - Bond wireless package: There is provided herein exemplary embodiments of a semiconductor device constructed in accordance with the present invention. The device comprises: a semiconductor chip having a lateral power transistor device formed therein. The chip has an upper surface and source, drain and gate contact terminals on the upper surface thereof. Each... Agent: Goodwin Procter LLP Patent Administrator

20080036071 - High density electronic packages: A high-density electrical package utilizing an array of high performance demountable electrical contacts such as UEC, T-Spring, F-Spring and their equivalent contained in a carrier in the form of an interposer between one or more components and a substrate. The carrier is made of a thermally conductive metal or contains... Agent: Brown & Michaels, PC 400 M & T Bank Building

20080036072 - Secmiconductor device and method for manufacturing a semiconductor device: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor die and an electrically conductive attachment region having a first attachment surface and a second attachment surface. The first attachment surface is arranged for electrical communication with the semiconductor die. An interlayer material is formed on... Agent: Mayer & Williams PC

20080036074 - Package unit: This invention relates to a package unit including a semiconductor package that houses a semiconductor chip, and a heat sink attached thereto. A peripheral wall section that surrounds a thermal junction member is provided on a stiffener. More preferably, a tip end section of the peripheral wall section is allowed... Agent: Kratz, Quintos & Hanson, LLP

20080036073 - Semiconductor device and method for manufacturing a semiconductor device having improved heat dissipation capabilities: A semiconductor device mountable to a substrate includes a semiconductor die and an electrically conductive attachment region having a first attachment surface and a second attachment surface. The first attachment surface is arranged for electrical communication with the semiconductor die. A housing at least in part encloses the semiconductor die... Agent: Mayer & Williams PC

20080036075 - Lightweight, hermetically sealed package having auxiliary, selectively contoured, low mass, pseudo wall insert for surface-mounting and dissipating heat from electronic circuit components: A hermetically sealed package for electronic circuit components includes a generally hollow, titanium body, having a reduced thickness bottom wall/floor, whose interior surface is laminated with a relatively low mass, insert, upon which electronic circuit components are mounted. The insert has a high thermal conductivity and a low coefficient of... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080036076 - Intelligent cooling method combining passive and active cooling components: A method for cooling a semiconductor including passive cooling including transferring heat via passive cooling components; active cooling including transferring heat via active cooling components; and controlling the active cooling based on temperature of the semiconductor. A cooling system for a semiconductor including: a passive component in thermal contact with... Agent: Osha Liang L.L.P./sun

20080036077 - Package structure and heat sink module thereof: A package structure and a heat sink module thereof are provided. The package structure includes a substrate, a chip and a heat sink module. The chip is disposed on the substrate. The heat sink module includes a supporting ring and a heat sink plate. The supporting ring is disposed on... Agent: Birch Stewart Kolasch & Birch

20080036078 - Wirebond-less semiconductor package: A wirebond-less packaged semiconductor device includes a plurality of I/O contacts, at least one semiconductor die, the semiconductor die having a bottom major surface and a top major surface, the top major surface having at least two electrically isolated electrodes, and a conductive clip system disposed over the top major... Agent: Duane Morris, LLPIPDepartment

20080036080 - Chip package: A chip package with an anti-creeping underfill is provided. The chip package includes a carrier, a chip and an underfill. The chip is disposed on the carrier and includes a chip body and a blocking portion. The chip body has at least one lateral surface and the blocking portion is... Agent: J C Patents, Inc.

20080036079 - Conductive connection structure formed on the surface of circuit board and manufacturing method thereof: The conductive connection structure of the present invention comprises a circuit board, a plurality of conductive pads, a solder mask layer, an electroless plating copper layer, and an electroless plating adhesive layer. The manufacturing method comprises the following steps: providing the circuit board having a plurality of conductive pads thereon;... Agent: Bacon & Thomas, PLLC

20080036082 - Multi-chip package having a stacked plurality of different sized semiconductor chips, and method of manufacturing the same: Provided is a multi-chip package in which a plurality of semiconductor chips having different sizes are stacked. A multi-chip package may include a substrate, and a plurality of semiconductor chips stacked on the substrate, each of the plurality of semiconductor chips having a different size. Each of the plurality of... Agent: Harness, Dickey & Pierce, P.L.C

20080036083 - Semiconductor device and method of manufacturing the same: A semiconductor package which has a semiconductor chip including a low dielectric constant film and a bump which consists of lead free solder, a wiring substrate by which flip chip junction of the semiconductor package was done via the bump, and under-filling resin, with which a gap between the semiconductor... Agent: Mcdermott Will & Emery LLP

20080036081 - Interconnection structure of integrated circuit chip: An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the... Agent: Marger Johnson & Mccollom, P.C.

20080036086 - Semiconductor device and method for manufacturing the same: A semiconductor device provided with a semiconductor chip wherein an electrode pad is formed on a circuit formation surface, includes a first passivation film, which serves as an adhering layer; a second passivation film formed on the first passivation film, for protecting the semiconductor chip from external physical damage; a... Agent: Nixon & Vanderhye, PC

20080036085 - Circuit board including solder ball land having hole and semiconductor package having the circuit board: A circuit board and a semiconductor package having the same are provided. The circuit board comprises a base substrate having interconnections, and solder ball lands disposed on one surface of the base substrate. The solder ball lands respectively have land holes having different sizes. The land hole disposed at the... Agent: Marger Johnson & Mccollom, P.C.

20080036084 - Laser release process for very thin si-carrier build: A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.... Agent: Connolly Bove Lodge & Hutz LLP (for IBM Yorktown)

20080036087 - Web process interconnect in electronic assemblies: Apparatuses and methods for forming displays are claimed. One embodiment of the invention relates to depositing a plurality of blocks onto a substrate and is coupled to a flexible layer having interconnect deposited thereon. Another embodiment of the invention relates to forming a display along a length of a flexible... Agent: Blakely Sokoloff Taylor & Zafman

20080036088 - Semiconductor apparatus: The present invention provides a semiconductor apparatus having the improved thermal fatigue life against temperature change by lowering the maximum temperature on a jointing member existing between a semiconductor element and an electrode terminal and reducing the range of the temperature change. The semiconductor apparatus has a jointing member placed... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080036089 - Semiconductor device having multilayer wiring structure: A semiconductor device includes a semiconductor substrate, and an interlayer wiring structure further including a lower wiring layer formed on the semiconductor substrate, a first interlayer an interlayer wiring layer including an interlayer insulating film formed on the lower wiring layer and including a first upper surface and a second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080036090 - Semiconductor device and method for producing the same: Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080036091 - Semiconductor integrated circuit device: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080036094 - Functional device-mounted module and a method for mounting functional device-mounted module: This disclosure provides a technique that prevents debonding at an interface between a functional device and a resin on reflow soldering in a functional device-mounted module requiring a hollow structure. Also disclosed is a functional device having a functional portion mounted on a substrate formed with predetermined wiring patterns, wherein... Agent: Oliff & Berridge, PLC

20080036093 - Method for embedding a component in a base: A method, in which the semiconductor components forming part of an electronic circuit, or at least some of them, are embedded in a base, such as a circuit board, during the manufacture of the base, when part of the base structure is, as it were, manufactured around the semiconductor components.... Agent: Birch Stewart Kolasch & Birch

20080036092 - Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner: The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least... Agent: Scully, Scott, Murphy & Presser, P.C.

20080036095 - Semiconductor device and method of fabricating the same: A semiconductor device includes a first interlayer insulating film formed above a semiconductor substrate, a first source line formed on the first interlayer insulating film, a second interlayer insulating film formed on the first source line, a plurality of bit lines formed on the second interlayer insulating film so as... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080036097 - Semiconductor package, method of production thereof and encapsulation resin: A flip-chip semiconductor package and method of manufacture thereof, the flip-chip semiconductor being highly reliable due to suppression of cracking. The flip-chip semiconductor package is formed by flip-chip bonding of a semiconductor chip-connecting electrode surface of a circuit board 1 and an electrode surface of a semiconductor chip 2, dispensing... Agent: Smith, Gambrell & Russell

20080036096 - Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages: A semiconductor multi-package module having stacked second and first packages, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding, and in which the first package is a flip chip ball grid array package in a die-up configuration.... Agent: Haynes Beffel & Wolfeld LLP

20080036098 - Configurable universal interconnect device: A universal interconnect device for mounting and interconnecting a semiconductor integrated circuit die in preparation for mounting to another substrate such as a printed circuit board. The device consists of a laminate substrate having a first surface upon which the integrated circuit die may be mounted. Underlying and surrounding the... Agent: Schneck & Schneck

20080036099 - Method for producing a component and device having a component: A method for producing a component and device including a component is disclosed. A basic substrate having paper as substrate material is provided, at least one integrated circuit is applied to the basic substrate, the at least one integrated circuit applied on the basic substrate is enveloped with an encapsulant,... Agent: Dicke, Billig & Czaja

20080036100 - Solder elements with columnar structures and methods of making the same: Elongated solder masses are formed by contacting the molten solder with the walls of holes in a dielectric layer overlying the front face of a chip element such as a wafer. The elongated solder masses have a relatively large aspect ratio, or ratio of height to maximum diameter, and thus... Agent: Tessera Lerner David Et Al.

20080036101 - Metal telluride nanocrystals and synthesis thereof: having a mean linear dimension of from 2 to 40 nanometers inclusive where x is between 0 and 1 inclusive and y is between 0 and 1 inclusive with the proviso that x+y is less than or equal to 1. Each of the metal telluride crystalline domains has a surface... Agent: Gifford, Krass, Sprinkle, Anderson & Citkowski, P.C.

20080029753 - Configurable circuits using phase change switches: Configurable circuits using phase change switches are described. The switches use phase change or phase transition material to create configurable connections between devices and/or interconnecting layers of an integrated circuit in order to change the behavior of the circuit after manufacturing. In at least some embodiments, the phase of the... Agent: Moore & Van Allen PLLC

20080029754 - Variable resistance non-volatile memory devices including a uniformly narrow contact layer and methods of manufacturing same: A phase changeable memory device is manufactured by forming at least one insulating layer on a substrate. A preliminary first electrode is formed on the insulating layer. The preliminary first electrode is partially etched to form a first electrode electrically connected to the substrate. After the preliminary first electrode is... Agent: Myers Bigel Sibley & Sajovec

20080029756 - Semiconductor buffer architecture for iii-v devices on silicon substrates: A composite buffer architecture for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm−2 to be formed on silicon substrates. In an embodiment of the present invention,... Agent: Intel/blakely

20080029761 - Through-hole vertical semiconductor devices or chips: The present invention discloses through-hole vertical semiconductor devices and chips. The structure of an embodiment of through-hole vertical semiconductor devices and chips having static protection diodes is the following: a semiconductor epitaxial layer is bonded to the first surface of a supporting chip with static protection diode; the first-type cladding... Agent: Hui Peng

20080029762 - Test system incorporating a field effect transistor sensor: A test system in accordance with the invention includes a field effect transistor (FET) sensor that is operable to detect an electric field present in an area located adjacent to a sensor surface of the FET sensor and generate thereby, a change in the drain-source current of the FET sensor.... Agent: Agilent Technologies Inc.

20080029764 - Capacitor, method of producing the same, semiconductor device, and liquid crystal display device: A capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially stacked. The dielectric layer has a stacked layer structure including a predetermined number of hafnium oxide sublayers and predetermined number of tantalum oxide sublayers. The number, materials, and thicknesses of the sublayers are determined... Agent: Robert J. Depke Lewis T. Steadman

20080029766 - Laminated structure, production method of the same, multilayer circuit board, active matrix substrate, and electronic display: A disclosed laminated structure includes a wettability-variable layer containing a wettability-variable material whose surface energy changes when energy is applied thereto and including at least a high-surface-energy area having high surface energy and a low-surface-energy area having low surface energy; and a conductive layer formed on the high-surface-energy area. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080029768 - Display apparatus and method of laying out pixel circuits: Herein disclosed a display apparatus including: a pixel array having a matrix of pixel circuits each including respective electrooptical elements for determining a display brightness level and respective drive circuits for driving the electrooptical elements; wherein adjacent two of the pixel circuits are paired with each other, and each of... Agent: Rader Fishman & Grauer PLLC

20080029767 - Display device and method of manufacturing the display device: A display device according to an embodiment of the present invention includes: a crystalline silicon layer formed on a substrate and including a source region, a drain region, and a channel region; a wiring layer including a signal line and formed to cover at least a predetermined portion on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080029770 - Nitride semiconductor laser element: A nitride semiconductor laser element, comprises a substrate and a nitride semiconductor layer in which a first semiconductor layer, an active layer, and a second semiconductor layer are laminated in this order on the substrate, wherein recessed and raised portions are formed in the first semiconductor layer and/or the second... Agent: GlobalIPCounselors, LLP

20080029771 - Switch having a ball member: A switch includes a housing, an emitter disposed in the housing and having an emitter head to emit a light signal, and a receiver disposed in the housing and having a receiver head to receive the light signal. A receptacle is disposed in the housing, and includes a first wall... Agent: Brooks Kushman P.C.

20080029772 - Lighting structure with light emitting diodes and method of forming same: A light module and a method of forming the module are disclosed. The light module includes a plurality of light units and a module substrate having a patterned circuit layer on a first surface of the module substrate and a plurality of openings for accommodating the light units. Each light... Agent: Snell & Wilmer L.L.P. (main)

20080029773 - Iii-nitride light-emitting devices with one or more resonance reflectors and reflective engineered growth templates for such devices, and methods: A light emitter includes a first mirror that is an epitaxially grown metal mirror, a second mirror, and an active region that is epitaxially grown such that the active region is positioned at or close to, at least, one antinode between the first mirror and the second mirror.... Agent: Song K. Jung Mckenna Long & Aldridge LLP

20080029774 - Semiconductor light source packages with broadband and angular uniformity support: Optical sources presented are comprised of a semiconductor emitter and supporting package system including a hard plastic lens cover and mounting substrate with electrical and mechanical support for the semiconductor. A cavity is formed between the lens cover and substrate which supports addition of materials which cooperate with optical propagation... Agent: Acol Technologies S.a.

20080029779 - Injection apparatus, semiconductor light emitting apparatus, manufacturing apparatus, and manufacturing method of semiconductor light emitting apparatus: A fluorescence-containing material injection apparatus of the present invention includes a fluorescence-containing material temperature control section, a fluorescence-containing material stirring section, a fluorescence-containing material remaining amount sensor, and a fluorescence-containing material injection amount adjustment section, by which disproportion in the mixture ratio of contaminates in a fluorescence-containing material M is... Agent: Morrison & Foerster LLP

20080029778 - Led module and method of manufacturing the same: Provided are a light emitting diode (LED) module and a method of manufacturing the same. The LED module may include a package housing including an inner space, a light-emitting chip in the inner space of the package housing, a phosphor layer including a fluorescent material and converting light emitted from... Agent: Harness, Dickey & Pierce, P.L.C

20080029775 - Light emitting diode package with positioning groove: A light emitting diode package structure includes a light emitting diode, a substrate structure and at least one gel. A surface of the substrate structure has a concave and at least one groove. The concave is used for containing the light emitting diode. A predetermined distance (D) is between the... Agent: Bruce H. Troxell

20080029777 - Semiconductor optical device and manufacturing method therefor: A LD (Laser Diode) includes: a laminated semiconductor structure including an active layer, a p-cladding layer, a contact layer, etc. that are sequentially on top of one another on an n-GaN substrate; a waveguide ridge including the contact layer and a portion of the p-cladding layer; a first silicon insulating... Agent: Leydig Voit & Mayer, Ltd

20080029752 - Phase change memory and manufacturing method thereof: Both a chalcogenide select device (24, 120) and a chalcogenide memory element (40, 130) are formed within vias within dielectrics (18, 22). As a result, the chalcogenides is effectively trapped within the vias and no glue or adhesion layer is needed. Moreover, delamination problems are avoided. A lance material (30)... Agent: Seed Intellectual Property Law Group PLLC

20080029755 - Structure for phase change memory and the method of forming same: A phase change device includes a first contact electrode structure a phase change material and a first insulating material between the phase change material and the first contact electrode structure and a second contact electrode in contact with the phase change material. A contact structure formed in the first insulating... Agent: Martine Penilla & Gencarella, LLP

20080029758 - Nitride semiconductor device: In the nitride semiconductor device of the present invention, an active layer 12 is sandwiched between a p-type nitride semiconductor layer 11 and an n-type nitride semiconductor layer 13. The active layer 12 has, at least, a barrier layer 2a having an n-type impurity; a well layer 1a made of... Agent: Nixon & Vanderhye, PC

20080029757 - Semiconductor device having a laterally injected active region: A semiconductor device including: a quantum well having photon emission energy level, the quantum well having at least one active layer and two barrier layers, one disposed above the active layer and one disposed below the active layer; and injection regions for injecting electrons into the quantum well, wherein the... Agent: Wilmerhale/boston

20080029759 - Optoelectronic transmitter integrated circuit and method of fabricating the same using selective growth process: Provided are an optoelectronic (OE) transmitter integrated circuit (IC) and method of fabricating the same using a selective growth process. In the OE transmitter IC, a driving circuit, which includes a double heterojunction bipolar transistor (DHBT) and amplifies received electric signals to drive an electroabsorption (EA) modulator, and the EA... Agent: Ladas & Parry LLP

20080029760 - Interfused nanocrystals and method of preparing the same: Interfused nanocrystals including two or more materials, further including an alloy layer formed of the two or more materials. In addition, a method of preparing the interfused nanocrystals. In the interfused nanocrystals, the alloy layer may be present at the interface between the two or more nanocrystals, thus increasing the... Agent: Buchanan, Ingersoll & Rooney PC

20080029763 - Transmission circuit, connecting sheet, probe sheet, probe card, semiconductor inspection system and method of manufacturing semiconductor device: A probe sheet or a connecting sheet with good transmission characteristics and flexibility comprising contact terminals capable of contacting at a plurality of points and in high density, without applying damages on an electrode pad which is a contact subject is provided. Further, a high-speed transmission circuit capable of designing... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080029765 - Electronic device: There is provided an electronic device having high reliability and high color reproducibility. A pixel structure is made such that a switching FET (201) and an electric current controlling FET (202) are formed on a single crystal semiconductor substrate (11), and an EL element (203) is electrically connected to the... Agent: Cook, Alex, Mcfarron, Manzo Cumming & Mehler, Ltd.

20080029769 - Laser mask and method of crystallization using the same: A laser mask and method of crystallization using the same that can produce a polycrystalline silicon thin film having uniform crystallization characteristics. According to the present invention, a method of crystallization using a laser mask having a reference pattern in a first block and the reverse pattern of the reference... Agent: Mckenna Long & Aldridge LLP

20080029776 - Oxynitride-based fluorescent material and method for production thereof: An oxynitride-based fluorescent material is formed of what results from substituting Eu for part of M of a general formula M3Si2N2O4, wherein M denotes one or more elements selected from among Be, Mg, Ca, Sr and Ba. The oxynitride-based fluorescent material can be produced by a method comprising mixing an... Agent: Sughrue Mion, PLLC

20080029780 - Solid state device: A solid state device has a solid state component, a power receiving/supplying portion that mounts the solid state component thereon for receiving/supplying electrical power from/to the solid state component, and a glass sealing portion that seals the solid state component. The glass sealing portion is formed of a B2O3—SiO2—Li2O—Na2O—ZnO—Nb2O5 based... Agent: Mcginn Intellectual Property Law Group, PLLC

20080029781 - One-transistor static random access memory with integrated vertical pnpn device: A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the... Agent: Hoffman, Warnick & D'alessandro LLC

20080029782 - Integrated esd protection device: An integrated electrostatic discharge (ESD) device includes a first ESD structure coupled to a pad terminal of the integrated ESD device and a second ESD structure coupled to a ground terminal of the integrated ESD device. The integrated ESD device also comprises a diffusion region that is shared by each... Agent: Texas Instruments Incorporated

20080029783 - Method of fabricating single crystal gallium nitride semiconductor substrate, nitride gallium semiconductor substrate and nitride semiconductor epitaxial substrate: A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more single crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction... Agent: Mcdermott Will & Emery LLP

20080029785 - Post passivation interconnection schemes on top of the ic chips: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Saile Ackerman LLC

20080029784 - Thin film transistor array panel for a display: A thin film transistor array panel comprising: an insulating substrate; gate lines formed on the insulating substrate; data lines defining a display region by intersecting the gate lines while being insulated; an electrostatic dispersion line intersecting the gate lines; diodes adhered to the gate lines and to the electrostatic dispersion... Agent: Macpherson Kwok Chen & Heid LLP

20080029786 - Integrated circuit with spare cells: An integrated circuit with spare cells. The integrated circuit comprises a substrate, spare cells formed on the substrate, and a plurality of metal layers and metal vias stacked over an input or output. A metal layer outermost from the substrate, among the plurality of metal layers, electrically connects to a... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080029787 - Photoelectric conversion apparatus and image pickup system using photoelectric conversion apparatus: A photoelectric conversion apparatus includes a plurality of photoelectric conversion elements configured to convert incident light to electric carriers, an amplifier MOS transistor shared by the plurality of photoelectric conversion elements, a plurality of floating diffusions connected to the gate electrode of the amplifier MOS transistor, and a plurality of... Agent: Fitzpatrick Cella Harper & Scinto

20080029788 - Imaging device: First diffusion region constituting a photodiode in each pixel stores carriers generated according to incident light. Second diffusion region is formed at a surface of the first diffusion region to cover a peripheral part of the first diffusion region. In the peripheral part of the first diffusion region, crystal defects... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080029789 - Current aperture transistors and methods of fabricating same: Transistors and/or methods of fabricating transistors that include a source contact, drain contact and gate contact are provided. In some embodiments, a channel region is provided between the source and drain contacts and at least a portion of the channel regions includes a hybrid layer comprising semiconductor material. In particular... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080029790 - Ald of silicon films on germanium: The use of atomic layer deposition (ALD) to form a semiconductor structure of a silicon film on a germanium substrate is disclosed. An embodiment includes a tantalum nitride gate electrode on a hafnium dioxide gate dielectric on the silicon film (TaN/HfO2/Si/Ge), which produces a reliable high dielectric constant (high k)... Agent: Schwegman, Lundberg & Woessner, P.A.

20080029791 - Semiconductor device and method of fabricating the same: Provided are a semiconductor device and a method of fabricating the semiconductor device. In the method, a field oxide layer can be formed in a semiconductor substrate so as to define and active electrode including a gate oxide layer and a gate poly is formed in the active region. An... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080029792 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same are disclosed, in which a dead zone and a dark current are simultaneously reduced by selective epitaxial growth. The CMOS image sensor includes a first conductive type semiconductor substrate, a second conductive type impurity ion area, a gate electrode,... Agent: Mckenna Long & Aldridge LLP

20080029793 - Photoelectric conversion device method for producing photoelectric conversion device and image pickup system: A photoelectric conversion device includes a photoelectric conversion region having a plurality of photoelectric conversion elements and a first MOS transistor configured to read a signal in response to an electric charge of each photoelectric conversion element; and a peripheral circuit region having a second MOS transistor configured to drive... Agent: Fitzpatrick Cella Harper & Scinto

20080029794 - High sensitivity and high dynamic-range cmos image sensor pixel structure with dynamic c-v characteristics: A new photogate pixel structure for high performance CMOS Image Sensors is proposed. A new photogate structure is incorporated into the photodiode active-pixel structure. The proposed pixel structure exhibits the dynamic integration capacitance characteristics, which can be controlled by varying the control-voltage at the photogate node. Since the sensitivity is... Agent: Greenblum & Bernstein, P.L.C

20080029795 - High sensitivity and high dynamic-range cmos image sensor pixel structure with dynamic c-v characteristics: A new photogate pixel structure for high performance CMOS Image Sensors is proposed. A new photogate structure is incorporated into the photodiode active-pixel structure. The proposed pixel structure exhibits the dynamic integration capacitance characteristics, which can be controlled by varying the control-voltage at the photogate node. Since the sensitivity is... Agent: Greenblum & Bernstein, P.L.C

20080029797 - Image sensor and method for manufacturing the same: An image sensor including a substrate and an interlayer dielectric layer divided into a pixel region and a logic pad region. An image sensor may include at least one of the following: a color filter, an over coating layer, and a micro lens sequentially formed over the interlayer dielectric layer... Agent: Sherr & Nourse, PLLC

20080029796 - Solid state imaging device, method for fabricating the same, and camera: A solid state imaging device includes: an imaging region formed in an upper part of a substrate made of silicon to have a photoelectric conversion portion, a charge accumulation region of the photoelectric conversion portion being of a first conductivity type; a device isolation region formed in at least a... Agent: Mcdermott Will & Emery LLP

20080029798 - Cmos image sensor and method of manufacturing the same: There is provided a CMOS image sensor comprises a LOCOS isolation film 6 formed on the surface of a semiconductor substrate 100 containing a peripheral circuit 31 and a photodiode region 15, a gate electrode 1 formed on the surface of the peripheral circuit 31, a surface-protecting film 8 deposited... Agent: Buchanan, Ingersoll & Rooney PC

20080029799 - Capacitor device with a layer structure disposed in a meander-shaped: A capacitor device includes a substrate, a first conductive structure, a second conductive structure, a dielectric layer structure, and a recess in the substrate. The first and second conductive structures are disposed on opposite sides of the dielectric layer structure, and the dielectric layer structure extends in a meander-shaped manner... Agent: Dicke, Billig & Czaja

20080029800 - Dynamic random access memory: A DRAM structure on a silicon substrate has an active area, gate conductors, deep trench capacitors, and vertical transistors. The deep trench capacitors are formed at intersections of the active area and the gate conductors, and each deep trench capacitor is coupled electrically to the corresponding vertical transistor to form... Agent: North America Intellectual Property Corporation

20080029801 - Semiconductor device and method of forming the same: A semiconductor device includes a first insulating layer, a capacitor, an adhesive layer, and an intermediate layer. The first insulating layer may include a first insulating film. The first insulating layered structure has a first hole. The capacitor is disposed in the first hole. The capacitor may include bottom and... Agent: Sughrue Mion, PLLC

20080029802 - Semiconductor device: A method of fabricating a semiconductor device is disclosed. First, a substrate is provided. The substrate includes at least a transistor area having a gate structure thereon, a capacitor area having a first electrode thereon and a resistor area having a second electrode thereon. The capacitor area and the resistor... Agent: Jianq Chyun Intellectual Property Office

20080029804 - Flash memory device and method of manufacturing the same: A flash memory device and a method of manufacturing the same, the flash memory device includes isolation layers formed in an isolation region of a semiconductor substrate, an auxiliary oxide layer formed on edge portions of an active region of the semiconductor substrate and on protruded sidewalls of the isolation... Agent: Marshall, Gerstein & Borun LLP

20080029803 - Programmable non-volatile memory cell: The present invention relates to a reprogrammable non-volatile memory cell which comprises a selection transistor and a data storage element. The invention further relates to a method of fabricating such a memory cell, as well as to a memory cell array comprising a number of such memory cells.... Agent: Dicke, Billig & Czaja

20080029805 - Semiconductor device and manufacturing method of the same: Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film... Agent: Miles & Stockbridge PC

20080029806 - Semiconductor device including nonvolatile memory and method for fabricating the same: A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080029807 - Semiconductor device: A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, a source and drain regions, a floating gate, and a control gate. Each of the source and drain... Agent: Eric Robinson

20080029808 - Non-volatile memory and method of fabricating same: In one embodiment, a semiconductor device includes a semiconductor substrate having a first junction region and a second junction region. An insulated floating gate is disposed on the substrate. The floating gate at least partially overlaps the first junction region. An insulated program gate is disposed on the floating gate.... Agent: Marger Johnson & Mccollom, P.C.

20080029809 - Semiconductor device having a vertical transistor structure: A semiconductor device includes a semiconductor substrate having a semiconductor layer on a major surface thereof. The semiconductor layer is formed to extend in the vertical direction of the major surface of the semiconductor substrate. A stress application layer is provided on either side of the semiconductor layer and applies... Agent: SprinkleIPLaw Group

20080029810 - Methods of fabricating semiconductor devices having buried gates and related semiconductor devices: Methods of fabricating semiconductor devices capable of maintaining a liner on both sidewalls of an active region overlapping a gate are provided. An isolation trench defining an active region is formed in a semiconductor substrate. A liner is formed on sidewalls of the active region. An isolation layer filling the... Agent: Myers Bigel Sibley & Sajovec

20080029811 - Vertical twin-channel transistors and methods of fabricating the same: A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between... Agent: Myers Bigel Sibley & Sajovec

20080029812 - Planar srfet using no additional masks and layout method: A semiconductor power device supported on a semiconductor substrate of a first conductivity type with a bottom layer functioning as a bottom electrode and an epitaxial layer overlying the bottom layer with a same conductivity type as the bottom layer. The semiconductor power device includes a plurality of FET cells... Agent: Bo-in Lin

20080029813 - Semiconductor device and method of manufacturing the same: In a high voltage MOS transistor, in a portion immediately below the gate electrode, peaks of concentration distribution in depth direction of a first conductivity type impurity and a second conductivity type impurity in the drain offset region are in the same depth, the second conductivity type impurity being higher... Agent: Mcginn Intellectual Property Law Group, PLLC

20080029814 - Multiple lateral resurf ldmost: A lateral DMOS transistor that includes two RESURF regions of one conductivity and two RESURF regions of another conductivity disposed between the base region and the drain region thereof.... Agent: Ostrolenk Faber Gerb & Soffen

20080029815 - Semiconductor-on-insulator (soi) strained active area transistor: A selectively strained MOS device such as selectively strained PMOS device making up an NMOS and PMOS device pair without affecting a strain in the NMOS device the method including providing a semiconductor substrate comprising a lower semiconductor region, an insulator region overlying the lower semiconductor region and an upper... Agent: Tung & Associates

20080029816 - Process for integrating on an inert substrate a device comprising at least a passive element and an active element and corresponding integrated device: A process is described for integrating, on an inert substrate, a device having at least one passive component and one active component. The process comprises: deposition of a protection dielectric layer on the inert substrate; formation of a polysilicon island on the protection dielectric layer; integration of the active component... Agent: Seed Intellectual Property Law Group PLLC

20080029817 - Process for manufacturing a semiconductor wafer having soi-insulated wells and semiconductor wafer thereby manufactured: A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor... Agent: Graybeal Jackson Haley LLP Suite 350

20080029818 - Selective silicon-on-insulator isolation structure and method: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region... Agent: Schmeiser, Olsen & Watts

20080029819 - Semiconductor device: A semiconductor device includes a transistor with a semiconductor film formed above a substrate that has at least one insulating surface; a source electrode coupled to a source region of the transistor; and a drain electrode coupled to a drain region of the transistor. The source region and the drain... Agent: Oliff & Berridge, PLC

20080029820 - Esd protection for bipolar-cmos-dmos integrated circuit devices and modular method of forming the same: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells... Agent: Patentability Associates

20080029821 - Semiconductor device and method for production thereof: The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor... Agent: Paul J Esatto Jr Scully Scott Murphy & Presser

20080029822 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080029823 - Semiconductor device having a dual stress liner and light exposure apparatus for forming the dual stress liner: In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has... Agent: Myers Bigel Sibley & Sajovec

20080029824 - Esd power clamp in triple well: A power clamp in a triple well is disclosed. A metal oxide semiconductor (MOS) varactor is used in a triggering circuit and is positioned in a first N type well. An N-channel field effect transistor is positioned in a P-type well. A P-channel field effect transistor is positioned in a... Agent: Hoffman, Warnick & D'alessandro LLC

20080029825 - Semiconductor device and method of manufacturing the same: Even if it is the semiconductor device provided with the wiring on an isolation insulating film, the sidewall formed on the side surface of this wiring, and the shared contact which connects the wiring and the impurity diffusion on an active region, the semiconductor device which can suppress the generation... Agent: Mcdermott Will & Emery LLP

20080029826 - Semicondutor memory device and method of manufacturing the same: The invention provides a semiconductor memory device which achieves memory size reduction. This memory is formed on a surface of a p-type silicon substrate, and includes an n-type impurity region serving as a cathode of a diode included in a memory cell and a word, a plurality of p-type impurity... Agent: Morrison & Foerster LLP

20080029827 - Double gate transistor, method of manufacturing same, and system containing same: A double gate transistor includes a substrate (110), a first semiconducting region (121) over the substrate, a second semiconducting region (122) adjacent to a first side of the first semiconducting region, and a third semiconducting region (123) adjacent to a second side of the first semiconducting region. The double gate... Agent: Intel Corporation C/o Intellevate, LLC

20080029828 - Fin field effect transistors including oxidation barrier layers: A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing... Agent: Myers Bigel Sibley & Sajovec

20080029829 - Void formation for semiconductor junction capacitance reduction: Semiconductor structures having a decreased semiconductor junction capacitance of a semiconductor junction within an active semiconductor layer may be fabricated using an ion implantation and thermal annealing method. The ion implantation and thermal annealing method provides for a plurality of voids located completely within the active semiconductor layer proximate to... Agent: Scully, Scott, Murphy & Presser, P.C.

20080029832 - Bonded strained semiconductor with a desired surface orientation and conductance direction: According to various method embodiments, a semiconductor layer is oriented to a substrate. The semiconductor layer has a surface orientation and is oriented to the substrate to provide a desired direction of conductance for the surface orientation. The oriented semiconductor layer is bonded to the substrate to strain the semiconductor... Agent: Schwegman, Lundberg & Woessner, P.A.

20080029831 - Cmos devices with graded silicide regions: A semiconductor device includes a semiconductor substrate, a gate stack overlying the semiconductor substrate, a spacer on a sidewall of the gate stack, a lightly doped source/drain (LDD) region adjacent the gate stack, a deep source/drain region adjoining the LDD region, and a graded silicide region on the deep source/drain... Agent: Slater & Matsil, L.L.P.

20080029830 - Forming reverse-extension mos in standard cmos flow: A reverse-extension MOS (REMOS) device and a method for forming the same are provided. The REMOS device includes a gate dielectric over a semiconductor substrate, a gate electrode on the gate dielectric, a lightly doped drain/source (LDD) region in the semiconductor substrate and having a portion extending under the gate... Agent: Slater & Matsil, L.L.P.

20080029833 - Transistor, an electronic circuit and an electronic device: A method of fabricating a TFT, including: (a) forming a gate electrode on a predetermined portion of an underlying layer, (b) covering the gate electrode with a dielectric layer so that the dielectric layer defines two indented regions and a protruding region that separate the two indented regions from each... Agent: Oliff & Berridge, PLC

20080029834 - Low-k isolation spacers for conductive regions: A multi-component low-k isolation spacer for a conductive region in a semiconductor structure is described. In one embodiment, a replacement isolation spacer process is utilized to enable the formation of a two-component low-k isolation spacer adjacent to a sidewall of a gate electrode in a MOS-FET device.... Agent: Blakely Sokoloff Taylor & Zafman

20080029835 - Method of removing refractory metal layers and of siliciding contact areas: A method of formation of contacts with cobalt silicide since is disclosed. For example, after siliciding with the SOM solution, both unreacted sections of the deposition layer including, for example, cobalt as initial layer for the siliciding and an oxidation protection layer including titanium and deposited by means of cathode... Agent: Dicke, Billig & Czaja

20080029836 - Structure and method for making high density mosfet circuits with different height contact lines: Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits comprise a contact line, a first gate layer situated proximate the contact line, and at least one subsequent gate layer situated over the first gate layer. The contact line... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080029837 - Solid-state imaging device: A solid-state imaging device is provided. The solid-state imaging device includes an imaging region having a plurality of pixels arranged in a two-dimensional array, in which the imaging region includes an effective pixel and a black reference pixel; and a shape of a floating diffusion portion in the effective pixel... Agent: Robert J. Depke Lewis T. Steadman

20080029838 - Semiconductor devices including schottky diodes with controlled breakdown and methods of fabricating same: A semiconductor device includes a semiconductor layer having a first conductivity type, a metal contact on the semiconductor layer and forming a Schottky junction with the semiconductor layer, and a semiconductor region in the semiconductor layer. The semiconductor region and the semiconductor layer form a first p-n junction in parallel... Agent: Myers Bigel Sibley & Sajovec

20080029839 - Controlling signal levels on a signal line within an integrated circuit: A signal line 12 has at a first location a first driver 14 to drive a first signal level on that signal line 12. A second driver 16 is provided at a second location, separated from the first location, and serves to drive the line signal to a different value... Agent: Nixon & Vanderhye, PC

20080029840 - Strained semiconductor, devices and systems and methods of formation: In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The device region has a channel region, and the isolation regions have volumes. The volumes of the isolation regions are adjusted to provide the channel region with... Agent: Schwegman, Lundberg & Woessner, P.A.

20080029841 - Structure and method for forming a dielectric chamber and electronic device including dielectric chamber: A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080029842 - Cbram cell and cbram array, and method of operating thereof: According to one embodiment of the present invention, a CBRAM cell includes a solid electrolyte block having at least three solid electrolyte contacting areas, electrodes electrically connected to the solid electrolyte contacting areas, wherein conductive paths are formable, erasable or detectable within the solid electrolyte block by applying voltages between... Agent: Slater & Matsil LLP

20080029843 - E-fuse and method for fabricating e-fuses integrating polysilicon resistor masks: An E-fuse and a method for fabricating an E-fuse integrating polysilicon resistor masks, and a design structure on which the subject E-fuse circuit resides are provided. The E-fuse includes a polysilicon layer defining a fuse shape including a cathode, an anode, and a fuse neck connected between the cathode and... Agent: Ibm Corporation RochesterIPLaw Dept 917

20080029844 - Anti-fuse structure optionally integrated with guard ring structure: An anti-fuse structure and a related method for fabricating the anti-fuse structure include a doped well within a semiconductor substrate. A first aperture and a second aperture that expose the doped well are located within a dielectric layer located over the semiconductor substrate and the doped well. A first conductor... Agent: Scully Scott Murphy & Presser, PC

20080029845 - On-chip magnetic components: An integrated circuit chip comprising a bond wire and a mass of magnetic material provided on the bond wire, wherein the mass of magnetic material increases the inductance of the bond wire.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080029846 - Semiconductor device: A semiconductor device having a voltage regulator is disclosed that does not have an external output condenser for phase compensation. The semiconductor device includes a semiconductor chip that includes a voltage regulator, a power supply input terminal, a ground terminal, and an output terminal for outputting a produced constant voltage;... Agent: Cooper & Dunham, LLP

20080029847 - Integrated circuit package system with filled recess: An integrated circuit package system is provided including forming a wafer having a back side and an active side, forming a recess in the wafer from the back side, forming a cover in the recess, and singulating the wafer at the recess filled with the cover.... Agent: Law Offices Of Mikio Ishimaru

20080029848 - Printed electronic device and transistor device and manufacturing method thereof: An electronic device, e.g., a printed transistor device, comprises a substrate, a first conductive layer, a second conductive layer and a semiconductor layer. The substrate has a first platform and a second platform embossing on the surface thereof, and the first and second platforms are separated by a gap whose... Agent: Wpat, PC Intellectual Property Attorneys

20080029850 - Electrical through contact: A method of fabricating an electrical contact through a through hole in a substrate, wherein the through hole is at least in part filled with a liquid conductive material and the solidified liquid conductive material provides an electrical contact through the through hole.... Agent: Dicke, Billig & Czaja

20080029849 - Method for placing material onto a target board by means of a transfer board: A method for placing material onto a target board by means of a transfer board comprising a plurality of blind holes, the method comprising the steps of immersing the transfer board in a material bath, wherein a first pressure acts on the material bath and a second pressure acts in... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080029852 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a laminated substrate formed by laminating a plurality of semiconductor substrates, a concave part formed in the laminated substrate, and a semiconductor element mounted in the concave part. A method of manufacturing a semiconductor device includes a first step of forming a laminated substrate by laminating... Agent: Drinker Biddle & Reath (dc)

20080029851 - Methods of forming conductive vias and methods of forming multichip modules including such conductive vias: A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed layer to form a plurality of laterally separated regions, and depositing metal upon the regions. Alternatively, a through-hole may be substantially filled with dielectric... Agent: Trask Britt, P.C./ Micron Technology

20080029853 - Integrated circuit system with contact film: A integrated circuit system including providing an integrated circuit device, forming an undoped insulating layer over the integrated circuit device, forming a thin insulating layer over the undoped insulating layer, forming a doped insulating layer over the thin insulating layer, and forming a contact in the undoped insulating layer, thin... Agent: Law Offices Of Mikio Ishimaru

20080029854 - Conductive shielding pattern and semiconductor structure with inductor device: The invention is directed to a conductive shielding pattern for shielding a inductor device. The conductive shielding pattern comprises a plurality of conductive layers and a plurality of diffusion regions. The conductive layers are located on a substrate. The diffusion regions are located in the substrate and the conductive layers... Agent: J C Patents, Inc.

20080029855 - Lead frame and fabrication method thereof: A lead frame and a fabrication method thereof includes a metallic plate locally fabricated in double sides to form accurately aligned and closely spaced circuits. The metallic plate is also locally fabricated in single side to form patterned trenches. A filling material is filled into the trenches to provide extra... Agent: Hdsl

20080029856 - Leadframe and non-lead package therewith: The present invention relates to a leadframe and a non-lead package therewith. The non-lead package comprises a leadframe, a die and a molding compound. The leadframe has a frame and a die pad. The frame has a plurality of conducting portions. The frame has a first recess at inner portions... Agent: North America Intellectual Property Corporation

20080029857 - Semiconductor device comprising an excess resin portion, manufacturing method thereof, and apparatus for manufacturing semiconductor device comprising a excess resin portion: A partly finished product of a semiconductor device includes a resin body encapsulating a semiconductor chip, first and second leads extended outwardly from the resin body, a dam bar connected between said first and second leads, and an excess resin portion protruding from the resin body between the first and... Agent: Young & Thompson

20080029858 - Integrated circuit package-on-package stacking system: An integrated circuit package-on-package stacking system is provided including, forming a leadframe interposer including: forming a leadframe; forming a molded base on the leadframe; and singulating the leadframe interposer from the leadframe.... Agent: Law Offices Of Mikio Ishimaru

20080029859 - Integrated circuit package system employing wafer level chip scale packaging: An integrated circuit package system that includes: providing a substrate with a protective coating; attaching a labeling film to a support member in a separate process; joining the protective coating and the labeling film; and dicing the substrate, the protective coating, and the labeling film to form the integrated circuit... Agent: Law Offices Of Mikio Ishimaru

20080029860 - Semiconductor device with internal heat sink: A single gauge lead frame for a semiconductor device includes a central die pad surrounded by lead fingers. A heat spreader is attached to a top surface of the die pad. The die pad and the lead fingers have the same thickness. A semiconductor integrated circuit is attached to the... Agent: Freescale Semiconductor, Inc. Law Department

20080029861 - Micro chip-scale-package system: A micro chip-scale-package system including providing a metal pattern on an adhesion material, attaching an integrated circuit die to the metal pattern, and molding an encapsulant over the integrated circuit die and the metal pattern.... Agent: Law Offices Of Mikio Ishimaru

20080029862 - Integrated circuit package system including die stacking: An integrated circuit package system including a leadframe with an aperture formed therein. An integrated circuit package is mounted on the leadframe over or under the aperture and a die is mounted within the aperture to the integrated circuit package.... Agent: Law Offices Of Mikio Ishimaru

20080029863 - Methods of fabrication of wafer-level vacuum packaged devices: An hermetic, gas filled or vacuum package device and method of making a vacuum package device. The device includes a device layer having one or more Micro Electro-Mechanical Systems (MEMS) devices. The device layer includes one or more electrical leads coupled to the one or more MEMS devices. The device... Agent: Honeywell International Inc. Patent Services Ab-2b

20080029864 - Package of mems device and method for fabricating the same: A package of a micro-electro-mechanical systems (MEMS) device includes a cap wafer, a plurality of bonding bumps formed over the cap wafer, a plurality of array bumps arrayed on an outer side of the bonding bumps, and an MEMS device wafer over which a plurality of first outer pads are... Agent: Morgan Lewis & Bockius LLP

20080029865 - Electronic device and method for producing the same: An electronic device is produced by providing a carrier wafer formed from at least a semiconductor material, apply a wiring structure with conductor tracks and contact pads to a top side of the carrier wafer so as to form a plurality of semiconductor device positions arranged in rows and columns... Agent: Edell , Shapiro & Finnan , LLC

20080029867 - Stackable multi-chip package system: A stackable multi-chip package system is provided including forming an external interconnect having a base and a tip, connecting a first integrated circuit die and the base, stacking a second integrated circuit die over the first integrated circuit die in an active side to active side configuration, connecting the second... Agent: Law Offices Of Mikio Ishimaru

20080029868 - Stackable multi-chip package system: A stackable multi-chip package system is provided including forming a first external interconnect having a first through hole and a second external interconnect having a second through hole, forming a first package subassembly having the first external interconnect and a first integrated circuit die, forming a second package subassembly having... Agent: Law Offices Of Mikio Ishimaru

20080029866 - Stackable multi-chip package system with support structure: A stackable multi-chip package system is provided including forming an external interconnect, having a base and a tip, and a paddle; mounting a first integrated circuit die over the paddle; stacking a second integrated circuit die over the first integrated circuit die in a active side to active side configuration;... Agent: Law Offices Of Mikio Ishimaru

20080029869 - Vertical stack type multi-chip package having improved grounding performance and lower semiconductor chip reliability: A vertical stack type multi-chip package is provided having improved reliability by increasing the grounding performance and preventing the decrease in reliability of the multi-chip package from moisture penetration into a lower semiconductor chip. The vertical stack type multi-chip package comprises an organic substrate having a printed circuit pattern on... Agent: Volentine & Whitt PLLC

20080029870 - Wafer-leveled chip packaging structure and method thereof: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first... Agent: Bacon & Thomas, PLLC

20080029873 - Integrated circuit package system with molding vents: An integrated circuit package system comprising: providing a substrate; attaching an integrated circuit die over the substrate; attaching a connector to the integrated circuit die and the substrate; and forming an encapsulant over the substrate, the integrated circuit die, and the connector and minimizing ambient gas deformation of the substrate... Agent: Law Offices Of Mikio Ishimaru

20080029871 - Interposer and semiconductor package using the same: Disclosed is an interposer including a polyhedral body having first and second surfaces facing each other, a plurality of electric terminals formed on the first surface; and a plurality of vias extending through the first and second surfaces. In addition, a semiconductor package includes a printed circuit board having a... Agent: Cha & Reiter, LLC

20080029872 - Plate structure having chip embedded therein and the manufacturing method of the same: A plate structure having a chip embedded therein, comprises an aluminum oxide plate having an upper surface, a lower surface, plural aluminum channels connected to the upper surface and the lower surface, and a cavity therein; a chip embedded in the cavity, wherein the chip has an active surface; at... Agent: Bacon & Thomas, PLLC

20080029874 - Integrated circuit component with a surface-mount housing and method for producing the same: A semiconductor component including a surface-mount housing and a method for producing the same are described herein. The semiconductor component includes lead pieces embedded into a plastic housing composition and arranged on an underside of the housing. External contact areas of the lead pieces are free of the plastic housing... Agent: Edell , Shapiro & Finnan , LLC

20080029875 - Hermetically sealed semiconductor device module: A sealed semiconductor power module that may include a rectifier, such as a silicon controlled rectifier (SCR), is provided. The module includes an AlN substrate having a bottom surface positioned on a metallic base plate and a top surface that includes a first pad and a second pad, the substrate... Agent: Ostrolenk Faber Gerb & Soffen

20080029876 - Bump pattern design for flip chip semiconductor package: A bump pattern design for flip chip semiconductor packages includes a pattern of contact pads formed on a package substrate. Each contact pad is adapted to receive a corresponding solder bump from a semiconductor chip attached thereto. The pattern includes a central portion and a peripheral portion with a transition... Agent: Duane Morris LLPIPDepartment (tsmc)

20080029877 - Method for separating package of wlp: The present invention provides a semiconductor device package singulation method. The method comprises printing a photo epoxy layer on the back surface of a substrate of a wafer for marking the scribe lines to be diced. Then etching is performed through the substrate along the marks in the photo epoxy... Agent: Kusner & Jaffe Highland Place Suite 310

20080029878 - Method and device for secure, insulated and electrically conductive assembling of treated semiconductor wafers: The invention relates to a process for and an arrangement of the connection of processed semiconductor wafers (1, 2) wherein, in addition to the firm connection, there is an electric connection (5) between the semiconductor wafers and/or the electronic structures (3) supporting them. For this purpose, low-melting structured intermediate glass... Agent: Hunton & Williams LLP Intellectual Property Department

20080029880 - Micro electrical mechanical system: This disclosure relates to lids and methods for forming and using them. One embodiment of these lids enables MEMS protected by the lids to be smaller. Another of these lids enables testing of a group of conjoined, lidded MEMS. Also, processes for forming and using these lids are also disclosed.... Agent: Hewlett Packard Company

20080029879 - Structure and method of making lidded chips: Lidded chip packages are provided in which an optoelectronic device chip has microelectronic circuits exposed at a surface of the chip with a lid mounted to overlie the optoelectronic device and the microelectronic circuits. An opaque film may be attached to the lid to overlie the microelectronic circuits while exposing... Agent: Tessera Lerner David Et Al.

20080029881 - Circuit board with cooling function: The manufacturing process of a circuit board includes forming a thermal interface layer on a first metal thin layer of a thermal plate. Joining a second metal layer of a main circuit board comprises at least one opening with the thermal interface layer. Then, reflowing the main circuit board with... Agent: Rosenberg, Klein & Lee

20080029882 - Thermal interconnect system and method of production thereof: A thermal transfer material is described herein that includes: a heat spreader component, wherein the heat spreader component comprises a top surface, a bottom surface and at least one heat spreader material, and at least one solder material, wherein the solder material is directly deposited onto the bottom surface of... Agent: Buchalter Nemer

20080029883 - Diamond composite heat spreaders having low thermal mismatch stress and associated methods: A diamond composite heat spreader having a low thermal mismatch stress can improve reliability and cost of diamond-based heat spreaders. A diamond composite heat spreader can have a diamond film and a thermally conductive base having a residual thermal mismatch stress which is less than about 75% of a residual... Agent: Thorpe North & Western, LLP.

20080029885 - Inverted pyramid multi-die package reducing wire sweep and weakening torques: An inverted pyramid multi-die package provides, for each die pad on an upper die, a rigid support underneath extending to a substrate. Such configuration reduces both the wire sweep and weakening torques. A lower die, smaller than the upper die in at least one dimension, may be positioned between the... Agent: Mark M. Friedman

20080029884 - Multichip device and method for producing a multichip device: Multichip devices and methods of making the same. In one embodiment, a chip stack is sandwiched between first and second redistribution substrates. The chip stack is electrically connected to contact structures of the first redistribution substrate and the second redistribution substrate.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080029886 - Versatile si-based packaging with integrated passive components for mmwave applications: An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and... Agent: Ibm Corporation, T.j. Watson Research Center

20080029887 - Electronic device including a conductive stud over a bonding pad region and a process for forming the electronic device: An electronic device can include an interconnect level (16) including a bonding pad region (110). An insulating layer (18) can overlie the interconnect level (16) and include an opening (112, 24) over the bonding pad region (110). In one embodiment, a conductive stud (34) can lie within the opening (112,... Agent: Larson Newman Abel Polansky & White, LLP

20080029889 - Method to create flexible connections for integrated circuits: A method of producing flexible interconnections for integrated circuits, and, in particular, the forming of flexible or compliant interconnections preferably by a laser-assisted chemical vapor deposition process in semiconductor or glass substrate-based carriers which are employed for mounting and packaging multiple integrated circuit chips and selectively, other devices in the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080029888 - Solder interconnect joints for a semiconductor package: A method and article of fabrication is described featuring a solder layer having a serpentine, interrupted, or interdigitated boundary. The non-planar design of the boundary layer increases the fatigue life of the solder joint by limiting the damage caused by micro-cracking. This irregularity of the solder boundary constrains the propagation... Agent: Bond Schoeneck & King, PLLC

20080029890 - Embedded chip package process and circuit board with embedded chip: An embedded chip package process is provided. First, a chip is connected to a first circuit layer on a carrier, and then a cover plate is pressed onto a dielectric material layer to make the chip embedded in the dielectric material layer so that a circuit board with an embedded... Agent: J C Patents, Inc.

20080029892 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device including at least one of the following steps: Forming a metal layer on and/over a semiconductor substrate. Forming a diffusion barrier film on and/over the metal layer. Forming a metal layer pattern and an diffusion barrier film pattern by etching the metal layer... Agent: Sherr & Nourse, PLLC

20080029891 - Semiconductor device and method for fabricating the same: A semiconductor device and a method of fabricating a semiconductor device is provided. The semiconductor device can include a semiconductor substrate; an interlayer dielectric layer having a damascene pattern formed on the semiconductor substrate; a diffusion barrier formed in the damascene pattern and made of a trivalent material; a seed... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080029893 - Power and ground ring layout: An integrated circuit layout on a semiconductor substrate includes a plurality of circuit modules and power rails. One of the power rails is a positive voltage supply rail, and another one is a negative voltage supply rail or a ground rail. The positive voltage supply rail is located on a... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080029895 - Carrier board structure with embedded semiconductor chip and fabrication method thereof: A circuit board structure with an embedded semiconductor chip and a fabrication method thereof are provided, including the steps of providing a semiconductor wafer having an active surface with a plurality of electrode pads, a connection metal layer formed on the electrode pads: forming a protective layer on the connection... Agent: Sawyer Law Group LLP

20080029894 - Flip-chip package substrate and a method for fabricating the same: The present invention provides a flip-chip package substrate and a method for fabricating a flip-chip package substrate comprising a circuit build-up structure, which comprises at least a dielectric layer and at least a circuit layer, wherein each dielectric layer comprises a first surface and a second surface, plural vias are... Agent: Bacon & Thomas, PLLC

20080029896 - Sip semiconductor device and method for manufacturing the same: A System In Package (SIP) semiconductor device and a method for manufacturing a SIP device. A TiSiN film may be used as a diffusion barrier film for metal wiring in a SIP semiconductor device. A TiSiN film may provide relatively good step coverage in a relatively easy formation process, which... Agent: Sherr & Nourse, PLLC

20080029897 - Side connectors for rfid chip: An RFID chip can have an RFID circuit having first and second initial bond pads and conductive paths on the RFID chip connecting the first and second bond pads to the different sides of the chip. The conductive paths including a first side connector on a first side of the... Agent: Fliesler Meyer LLP

20080029899 - Method of fabricating a semiconductor device and semiconductor device fabricated thereby: A method of fabricating a semiconductor device, including forming contact pads in a first insulating layer on a substrate, forming a second insulating layer on the first insulating layer and on the contact pads, forming bit lines on the second insulating layer, the bit lines connected to a first plurality... Agent: Lee & Morse, P.C.

20080029900 - Semiconductor device and method of manufacturing the same: A semiconductor device has a semiconductor substrate having an impurity-diffused region and a device isolation insulating film formed in the surficial portion thereof, a gate electrode formed on the semiconductor substrate, a contact formed on the gate electrode and connected to the gate electrode, and a protective film disposed between... Agent: Young & Thompson

20080029898 - Via stack structures: Via stack structures are disclosed. In one embodiment, a structure includes a via stack including: a first substantially cross-shaped line in a first dielectric layer; a second substantially cross-shaped line set in a second dielectric layer, and a via stud coupling the first substantially cross-shaped line to the second substantially... Agent: Hoffman, Warnick & D'alessandro LLC

20080029901 - Post vertical interconnects formed with silicide etch stop and method of making: A method to form a vertical interconnect advantageous for high-density semiconductor devices. A conductive etch stop layer, preferably of cobalt silicide, is formed. The etch stop layer may be in the form of patterned lines or wires. A layer of contact material is formed on and in contact with the... Agent: Patent Dept., Sandisk Corporation

20080029902 - Multi-layered complementary conductive line structure: A multi-layered complementary conductive line structure, a manufacturing method thereof and a manufacturing method of a TFT (thin film transistor) display array are provided. The process of TFT having multi-layered complementary conductive line structures does not need to increase the mask number in comparison with the currently process and is... Agent: Jianq Chyun Intellectual Property Office

20080029903 - Chip-stacked package structure: The present invention provides a chip-stacked structure, comprising: a substrate with a plurality of terminals and a chip-stacked structure formed by a plurality of stacked chips and fixedly connected to the substrate. Wherein an active surface of each chip in the chip-stacked structure is provided with a plurality of pads... Agent: Reed Smith LLP

20080029904 - Double-sided waffle pack: Double-sided waffle packs and methods of using the same are provided. In one aspect, a waffle pack is provided that includes a body that has a first side and second side opposite the first side. The first side has a first cavity for enabling a semiconductor die to be seated... Agent: Timothy M Honeycutt Attorney At Law

20080029905 - Integrated circuit package-in-package system: An integrated circuit package-in-package system is provided including forming an external interconnect having an upper portion and a lower portion; forming a packaged device; mounting an active device over the packaged device; connecting the active device to the packaged device and the upper portion; and molding the packaged device, the... Agent: Law Offices Of Mikio Ishimaru

20080029906 - Semiconductor switching module and method: The invention relates to a semiconductor switching module for on-board electrical supply systems comprising a plurality of semiconductor chips, and a method for producing the same. The semiconductor switching module has at least one half-bridge circuit comprising a first semiconductor circuit chip as LSS (low side switch) and a second... Agent: Dicke, Billig & Czaja

20080029908 - Integrated circuit utilizing down bond to define the function of the die and the implementing method thereof: The present invention provides an integrated circuit and the method of implementing the same. The integrated circuit includes a die, a base, a covering material and a plurality of pins. The die has at least a first function and a second function and includes a plurality of signal pads and... Agent: North America Intellectual Property Corporation

20080029907 - Power semiconductor devices having integrated inductor: An electronic device (100) with one or more semiconductor chips (102) has an inductor (101) assembled on or under the chips. The inductor includes a ferromagnetic body (111) and a wire (104) wrapped around the body to form at least a portion of a loop; the wire ends (104a) are... Agent: Texas Instruments Incorporated

20080029909 - Nanowire semiconductor device: Semiconductor devices are fabricated using nanowires 16. A conductive gate 22 may be used to control conduction along the nanowires 16, in which case one of the contacts is a drain 12 and the other a source 18. The nanowires 16 may be grown in a trench or through-hole 8... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080029910 - Layout of array of electrical interconnect to increase i/o density packaging: An embodiment of the present invention discloses a hexagonally structured electrical interconnect connector and a layout arrangement for a plurality of the same on a chip carrier or a multi-chip module (MCM) in a hexagonal array to increase the input output (I/O) density. The hexagonal electrical interconnect connector may take... Agent: Hoffman, Warnick & D'alessandro LLC

20080029911 - Integrated circuit package system: An integrated circuit package system is provided including forming a substrate with a device thereover, forming an encapsulation having a planar top surface to cover the device and the substrate spanning to an extraction side of the encapsulation, and forming a recess in the encapsulation from the planar top surface.... Agent: Law Offices Of Mikio Ishimaru

20080029912 - Tisin layer on semiconductor device: A method of fabricating a titanium silicide nitride (TiSiN) layer of a semiconductor device may include forming a gate electrode on a semiconductor substrate and forming spacers on sidewalls of the gate electrode, forming a source and a drain in the semiconductor substrate, and forming TiSiN layers on the gate... Agent: Sherr & Nourse, PLLC

20080029913 - Multi-layer structure for parameter measurement: Various embodiments disclosed herein include methods for measuring a parameter associated with a workpiece. Such a method may include providing a first overlay pattern on the workpiece and a second overlay pattern over the first overlay pattern. The first overlay pattern may comprise a first plurality of features spaced apart... Agent: Knobbe Martens Olson & Bear LLP