Active solid-state devices (e.g., transistors, solid-state diodes) inventions 02/08

20080048164 - Electro-resistance element, method of manufacturing the same and electro-resistance memory using the same: An electro-resistance element that develops less leakage and fewer associated short-circuits even when an electro-resistance layer is made thinner, a method of manufacturing the same and an electro-resistance memory using the same are provided. The electro-resistance element includes a first electrode, a second electrode, an electro-resistance layer stacked between the... Agent: Hamre, Schumann, Mueller & Larson P.C.

20080048165 - Variable resistance element and resistance variable type memory device: A variable resistance element includes: a first electrode; a resistance layer formed on the first electrode; and a second electrode formed on the resistance layer, wherein the resistance layer is composed of transition metal oxide having oxygen defects.... Agent: Harness, Dickey & Pierce, P.L.C

20080048168 - Semiconductor device and manufacture method thereof: A semiconductor device includes an interlayer insulating film formed on a semiconductor substrate to cover a lower electrode, a side-wall insulating film formed on a side wall of a contact hole formed through the interlayer insulating film to a depth reaching the lower electrode, a heater formed in the interior... Agent: Young & Thompson

20080048169 - Heat-shielded low power pcm-based reprogrammable efuse device: An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and... Agent: Cantor Colburn LLP-ibm Yorktown

20080048170 - Semiconductor memory device and fabrication method thereof: A semiconductor memory device comprises a heater electrode, a phase change portion, and an upper electrode. The phase change portion is connected to the heater electrode in a first direction. The upper electrode has an upper surface, a lower surface and a hole. The hole pierces the upper electrode between... Agent: Young & Thompson

20080048172 - Gallium nitride-based compound semiconductor light-emitting device: A gallium nitride compound semiconductor light-emitting device includes a crystalline substrate (10), a light-emiting layer (15) of a quantum well structure which is formed of a gallium nitride compound semiconductor barrier layer and a gallium nitride compound semiconductor well layer, which light-emitting layer is provided on a second side of... Agent: Sughrue Mion, PLLC

20080048175 - Semiconductor superjunction structure: Semiconductor structures and methods are provided for a semiconductor device (54-11, 54-12) employing a superjunction structure (81). The method comprises, forming (52-6) first spaced-apart regions (70-1, 70-2, 70-3, 70-4, etc.) of a first semiconductor material (70) of a first conductivity type, forming (52-9) second spaced-apart regions (74-1, 74-2, 74-3, etc.)... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080048176 - Semiconductor device and method for fabricating the same: A semiconductor device includes a semiconductor superlattice layer and a semiconductor multilayer. The semiconductor superlattice layer has periodic concave-convex shapes, and a plurality of semiconductor films each having bent portions in accordance with the concave-convex shapes are stacked in the semiconductor superlattice layer. The semiconductor multilayer is formed so as... Agent: Mcdermott Will & Emery LLP

20080048177 - Electronic device including a barrier layer and a process for forming the electronic device: An electronic device can include a substrate (12) having a primary surface (14), a second surface (16, 22) opposite the primary surface (14), and an electrode (50). In one embodiment, the electrode (50) can lie adjacent to the second surface (22) and include, a barrier layer (54) lying between a... Agent: Larson Newman Abel Polansky & White, LLP

20080048182 - Display with integral speaker element: A display housing a sound element and a driving circuit that may be built in on the same substrate as the display panel. Thin-film transistors PTFT constituting pixels and a sound wave generation device SPO1 having a laminated structure of a heat generation layer 700, a heat insulation layer 701... Agent: Miles & Stockbridge PC

20080048179 - Hybrid semiconductor-ferromagnet device with a junction structure of positive and negative magnetic-field regions: A hybrid semiconductor-ferromagnet device is a device which has micromagnets (Co) deposited on semiconductor (InAs) two-dimensional electrons, and which has a junction structure of positive and negative magnetic field regions using a stray field resulting from the micromagnets. The magnetoresistance measured in the hybrid semiconductor-ferromagnet device has an asymmetrical hall... Agent: Ostrolenk Faber Gerb & Soffen

20080048184 - Method of forming contact for organic active layer, method of manufacturing flat panel display, organic thin film transistor display, and organic light emitting diode display: A method for forming a contact of an organic active layer is provided. In this method, a transparent conductive oxide thin film is formed on a substrate, and a surface of the oxide thin film is activated by inducing a base —OH and an oxide —O. Then, the oxide thin... Agent: Cantor Colburn, LLP

20080048178 - Tin phosphate barrier film, method, and apparatus: A method is disclosed for inhibiting oxygen and moisture penetration of a device comprising the steps of depositing a tin phosphate low liquidus temperature (LLT) inorganic material on at least a portion of the device to create a deposited tin phosphate LLT material, and heat treating the deposited LLT material... Agent: Corning Incorporated

20080048187 - Semiconductor thin film, thin film transistor, method of manufacturing the semiconductor thin film, method of manufacturing the thin film transistor, and manufacturing device of semiconductor thin film: A semiconductor thin film according to an embodiment of the present invention includes: a polycrystallized semiconductor thin film formed by applying laser light to an amorphous semiconductor thin film; and crystal grains arranged into a lattice shape with a size that is about ½ of an oscillation wavelength of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080048188 - Electronic devices integrated on a single substrate and method for fabricating the same: Electronic devices integrated on a single substrate and a method for fabricating the same are provided. The method includes providing a substrate, and forming at least two electronic devices on the substrate, wherein the at least two electronic devices are selected from a thin film transistor, a memory, a diode,... Agent: Jianq Chyun Intellectual Property Office

20080048190 - Circuit board for electro-optical device, electro-optical device, and electronic apparatus: A circuit board includes: a plurality of data lines and a plurality of scanning lines; a transistor that has a semiconductor layer and a gate electrode. The semiconductor layer includes a first junction region that is formed between the channel region and the data-line-side source/drain region, and a second junction... Agent: Oliff & Berridge, PLC

20080048191 - Organic light emitting display device and method of fabricating the same: A display device includes a substrate having a transistor disposed thereon and including a source/drain electrode connected to the transistor, an intermediate layer disposed on the transistor, the source/drain electrode penetrating the intermediate layer, a light emitting structure disposed on the intermediate layer, the light emitting structure connected to an... Agent: Lee & Morse, P.C.

20080048192 - Led devices and associated methods: Methods for cooling semiconductor devices having a light-emitting surface and associated devices are disclosed and described. Such a device may include a light-emitting surface and a diamond layer disposed on at least a portion of the light-emitting surface. The diamond layer may be exposed to air in order to accelerate... Agent: Thorpe North & Western, LLP.

20080048193 - White light emitting diode module: A white LED module includes a circuit board, a blue LED chip disposed on the circuit board, a green light source of an LED chip or phosphor disposed on the circuit board, and a red light source of an LED chip or phosphor disposed on the circuit board. At least... Agent: Mcdermott Will & Emery LLP

20080048197 - Semiconductor device: A semiconductor is provided with: a silicon substrate 2a of a first conductivity type, including a first surface S1a and a second surface S2a; a silicon layer 4a of a second conductivity type, arranged on the first surface S1a of the silicon substrate 2a, including a third surface S3a opposite... Agent: Drinker Biddle & Reath (dc)

20080048203 - Light emitting apparatus, manufacturing method thereof, and light unit: Provided are a light emitting apparatus and a light unit. The light emitting apparatus comprises a first substrate, a second substrate, and a light emitting device. The first substrate has a plurality of lead frames, and the second substrate has an opening part on the first substrate. The light emitting... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080048199 - Light emitting device and method of making the device: A light emitting device and method of making the device uses an encapsulant to create a hollow region within a chamber of the device. The encapsulant is configured to contact at least a portion of a light source of the device and a portion of a lens of the device.... Agent: Kathy Manke Avago Technologies Limited

20080048201 - Light emitting diode package employing lead terminal with reflecting surface: Disclosed is a light emitting diode (LED) package employing a lead terminal with a reflecting surface. The package includes first and second lead terminals that are spaced apart from each other. The first lead terminal has a lower portion with an LED chip mounting area, and at least one reflecting... Agent: Marger Johnson & Mccollom, P.C.

20080048198 - Omni-directional led light source: A light emitting diode (“LED”) device that emits omni-directional light is disclosed. Such omni-directional LED device may include a LED chip capable of emitting light in all directions. In one example of one implementation, the LED chip is then assembled and sealed inside a casing, such as a glass casing... Agent: Kathy Manke Avago Technologies Limited

20080048202 - Semiconductor light emitting device, method of forming the same, and compound semiconductor device: A semiconductor device may include, but is not limited to, a substrate, a compound semiconductor epitaxial layer, and a first reflecting layer. The substrate may have a main face. The substrate may have at least one cavity that is adjacent to the main face. The compound semiconductor epitaxial layer may... Agent: Wood, Herron & Evans, LLP

20080048205 - Optical semiconductor device and method for making the same: An optical semiconductor device includes an insulating substrate provided with a first electrode and a second electrode each extending from the obverse surface onto the reverse surface of the substrate. The first electrode includes a die-bonding pad extending on the obverse surface of the substrate and a first terminal extending... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20080048204 - Semiconductor light-emitting element assembly: A semiconductor light-emitting element assembly includes: a semiconductor light-emitting element having first and second leads, a semiconductor light-emitting element chip die-bonded to the first lead and wire-bonded to the second lead, a metal body for heat dissipation fixed to the first and second leads via an insulating adhesive layer, and... Agent: Morrison & Foerster LLP

20080048167 - Chalcogenide devices exhibiting stable operation from the as-fabricated state: A chalcogenide material and chalcogenide memory device having less stringent requirements for formation, improved thermal stability and/or faster operation. The chalcogenide materials include materials comprising Ge, Sb and Te in which the Ge and/or Te content is lean relative to the commonly used Ge2Sb2Te5 chalcogenide composition. Electrical devices containing the... Agent: Ovonyx, Inc

20080048166 - Semiconductor integrated circuit device: With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080048171 - Small electrode for phase change memories: A method of manufacturing a memory cell is disclosed. In one embodiment, the method includes forming an electrode including an outer surface that is substantially circular and an exposed surface that has a sublithographic dimension in a direction parallel to the exposed surface. Further, the method may also include forming... Agent: Fletcher Yoder (micron Technology, Inc.)

20080048173 - Semiconductor device including a lateral field-effect transistor and schottky diode: A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above... Agent: Slater & Matsil, L.L.P.

20080048174 - Semiconductor device including a lateral field-effect transistor and schottky diode: A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above... Agent: Slater & Matsil, L.L.P.

20080048185 - Field effect transistor and method of manufacturing the same: s

20080048183 - Organic field-effect transistor and semiconductor device including the same: It is an object to provide an electrode for an organic field-effect transistor having a semiconductor layer formed of an organic semiconductor material (in the present invention, referred to as an organic field-effect transistor), which can reduce the energy barrier at an interface with the semiconductor layer. A composite layer... Agent: Eric Robinson

20080048181 - Organic semiconductor thin film, organic semiconductor device, organic thin film transistor and organic electronic luminescence element: An organic semiconductor thin film, comprising an organic semiconductor compound, wherein the organic semiconductor thin film is manufactured by a process of forming a film by using a solution or a dispersion at room temperature prepared by mixing the organic semiconductor compound and an organic solvent, and the half width... Agent: Cantor Colburn, LLP

20080048180 - Semiconductor device: It is an object of the present invention to provide a semiconductor device in which data can be written except when manufacturing the semiconductor device and that counterfeits can be prevented. Moreover, it is another object of the invention to provide an inexpensive semiconductor device including a memory having a... Agent: Eric Robinson

20080048186 - Design structures incorporating semiconductor device structures with self-aligned doped regions: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes semiconductor device structures with self-aligned doped regions. The semiconductor structure may include first and second doped regions of a first conductivity type defined in the semiconductor material of a... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080048189 - Semiconductor device and method of manufacturing the same: The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode being in contact with the first gate electrode and a gate... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080048196 - Component and process for manufacturing the same: An electrical and/or optical component and a process for manufacturing the component achieve especially good quality in the component and especially reliably avoid crystal dislocations in material layers of the component. In the process for producing a component, at least one trench is etched into a substrate, the trench is... Agent: Lerner Greenberg Stemer LLP

20080048195 - Gan-based light-emitting element and method for producing same: A GaN-based semiconductor light-emitting element capable of suppressing the occurrence of piezoelectric spontaneous polarization in the thickness direction of an active layer and reducing the driving voltage of a light-emitting diode is provided. The GaN-based semiconductor light-emitting element has a structure with a first GaN-based compound semiconductor layer 21 having... Agent: Bell, Boyd & Lloyd, LLP

20080048194 - Nitride semiconductor light-emitting device: A nitride semiconductor light emitting element having a laminate S made of a semiconductor crystal layer, wherein the laminate S includes an n-type layer 2, a light emitting layer 3 and a p-type layer 4. The p-type layer 4 has a p-type contact layer 42 to be in contact with... Agent: Wenderoth, Lind & Ponack, L.L.P.

20080048200 - Led with phosphor tile and overmolded phosphor in lens: Overmolded lenses and certain fabrication techniques are described for LED structures. In one embodiment, thin YAG phosphor plates are formed and affixed over blue LEDs mounted on a submount wafer. A clear lens is then molded over each LED structure during a single molding process. The LEDs are then separated... Agent: Patent Law Group LLP

20080048206 - Vertical gallium nitride-based light emitting diode and method of manufacturing the same: A method of manufacturing a vertical GaN-based LED comprises forming a light emission structure in which an n-type GaN-based semiconductor layer, an active layer, and a p-type GaN-based semiconductor layer are sequentially laminated on a substrate; etching the light emission structure such that the light emission structure is divided into... Agent: Lowe Hauptman Ham & Berner, LLP

20080048207 - Preparation method of a coating of gallium nitride: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080048208 - Electrostatic discharge protection device for an integrated circuit: An integrated circuit is made of a semiconductor material and comprises an input and/or output terminal connected to an output transistor forming a parasitic element capable of triggering itself under the effect of an electrostatic discharge applied to the terminal. The integrated circuit comprises a protection device formed so as... Agent: Seed Intellectual Property Law Group PLLC

20080048209 - Image sensor: An image sensor according to embodiments may include a first substrate having photodiode cells, a second substrate having a logic circuit, and connection electrodes that may electrically connect the photodiode cells with the logic circuit. In embodiments, more area may be available on the first substrate for photodiode cells and... Agent: Sherr & Nourse, PLLC

20080048210 - Semiconductor device and method for making the same: In a MOS-type semiconductor device in which, on a Si substrate (201), a SiGe layer (202) having a valence band edge energy value smaller than a valence band edge energy value of the first semiconductor layer and a mobility larger than a mobility of the first semiconductor layer, a Si... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080048211 - Trench isolated capacitive micromachined ultrasonic transducer arrays with a supporting frame: A one or two-dimensional capacitive micro-machined ultrasonic transducer (CMUT) array with supporting frame is provided. The CMUT array has at least three array elements deposited on a conductive substrate. The invention also has at least one CMUT cell in the array element, a conductive top layer deposited to a top... Agent: Lumen Intellectual Property Services, Inc.

20080048212 - Imaging device: An imaging device includes a first electrode for generating an electric field storing signal charges, a charge multiplication section for multiplying the stored signal charges, a second electrode for generating the electric field in the charge multiplication section, a voltage conversion portion for converting the signal charges into a voltage,... Agent: Ditthavong Mori & Steiner, P.C.

20080048213 - Self-aligned, planar phase change memory elements and devices, systems employing the same and methods of forming the same: Phase change memory elements, devices and systems using the same and methods of forming the same are disclosed. A memory element includes first and second electrodes, and a phase change material layer between the first and second electrodes. The phase change material layer has a first portion with a width... Agent: Dickstein Shapiro LLP

20080048214 - Junction field effect transistor and method of manufacturing the same: According to a junction FET of the present invention, the depth of a channel region is made shallow by selectively performing ion implantation and diffusion. Since the channel region forms a pn junction together with a p type semiconductor layer with relatively low impurity concentration, the improvement in the high... Agent: Morrison & Foerster LLP

20080048215 - Electrical stress protection apparatus and method of manufacture: In various embodiments, circuits and semiconductor devices and structures and methods to manufacture these structures and devices are disclosed. In one embodiment, a bidirectional polarity, voltage transient protection device is disclosed. The voltage transient protection device may include a bipolar PNP transistor having a turn-on voltage of VBE1, a bipolar... Agent: Hvvi Semiconductors, Inc.

20080048218 - Method and flip chip structure for power devices: A lead frame structure for supporting a semiconductor die is disclosed that includes at least two electrical leads each having a plurality of finger shaped structures unilaterally extending outward from the at least two electrical leads. The electrical leads are arranged so that the plurality of finger shaped structures forms... Agent: Perkins Coie LLP Patent-sea

20080048217 - Semiconductor device and method of fabricating the same: A semiconductor device may include a gate pattern formed on a semiconductor substrate. At least one impurity region may be formed in the semiconductor substrate such that at least a portion of the at least one impurity region is disposed under the gate pattern. An epitaxial growth layer may be... Agent: Harness, Dickey & Pierce, P.L.C

20080048216 - Apparatus and method of forming metal oxide semiconductor field-effect transistor with atomic layer deposited gate dielectric: A method for forming a metal oxide semiconductor field-effect transistor (MOSFET) includes forming a III-V compound semiconductor on a substrate with the III-V compound semiconductor being doped with a first dopant type. The method further includes doping a first and second region of the III-V compound semiconductor with a second... Agent: Barnes & Thornburg LLP

20080048219 - Semiconductor device having substrate-driven field-effect transistor and schottky diode and method of forming the same: A semiconductor device including a substrate-driven field-effect transistor with a lateral channel and a parallel-coupled Schottky diode, and a method of forming the same. In one embodiment, the substrate-driven field-effect transistor of the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom... Agent: Glenn W. Boisbrun Slater & Matsil, L.L.P.

20080048220 - Fabricating cmos image sensor: A CMOS image sensor and a fabricating method thereof are provided. The method includes forming a nitride layer over a boundary region between a device isolation region and a pixel region, forming a silicide barrier layer in the pixel region and performing a silicide process. A boundary portion of the... Agent: Sherr & Nourse, PLLC

20080048223 - cmos image sensor and method of fabricating the same: A CMOS image sensor and a fabricating method thereof improves sensitivity to blue light by forming a depletion layer by means of a PN junction in a gate of a drive transistor. The depletion layer formed on the upper portion of the gate improves the sensitivity of the CMOS image... Agent: Sherr & Nourse, PLLC

20080048222 - Bipolar junction transistor and cmos image sensor having the same: Embodiments relate to a horizontal type bipolar junction transistor element (BJT) and a CMOS image sensor having the same to form a photodiode. In embodiments, the bipolar junction transistor as well as collector current may flow uniformly in a horizontal direction, which may increase the entire amount of current. In... Agent: Sherr & Nourse, PLLC

20080048224 - Fabricating cmos image sensor: A CMOS image sensor includes at least one of: A P-type semiconductor substrate. A P-type photodiode formed in the P-type semiconductor substrate and having a higher impurity concentration than the semiconductor substrate. An N-type photodiode disposed over the P-type photodiode at a depth less than approximately 0.15 μm from the... Agent: Sherr & Nourse, PLLC

20080048221 - Image sensor and manufacturing method thereof: Embodiments relate to an image sensor and a method for manufacturing an image sensor. According to embodiments, ions of low concentration may be implanted into a photodiode region of a semiconductor substrate to form a photodiode. At least one gate insulating layer pattern may be formed on the semiconductor substrate,... Agent: Sherr & Nourse, PLLC

20080048225 - Atomic layer deposited barium strontium titanium oxide films: Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium titanium oxide layer, or a combination thereof. Embodiments of methods of fabricating such dielectric layers provide dielectric layers for use in a variety of devices. Embodiments include forming barium... Agent: Schwegman, Lundberg & Woessner, P.A.

20080048227 - Dielectric film, method of manufacturing the same, and semiconductor capacitor having the dielectric film: Provided are a dielectric film, a method of manufacturing the same, and a semiconductor capacitor having the dielectric film. The semiconductor capacitor includes a lower electrode, a ferroelectric layer disposed on the lower electrode, a paraelectric layer disposed on the ferroelectric layer, and an upper electrode disposed on the paraelectric... Agent: Ladas & Parry LLP

20080048226 - Direct cell via structures for ferroelectric random access memory devices and methods of fabricating such structures: Provided are FeRAM device constructions and fabrication methods that provide for the direct connection of metal patterns to ferroelectric capacitors. The FeRAM device constructions utilize a combination of one or more barrier layers incorporated in conductive plugs, barrier layers incorporated in primary conductive patterns or conductive patterns formed using one... Agent: Harness, Dickey & Pierce, P.L.C

20080048228 - Semiconductor device and method for manufacturing same: A semiconductor device 1 includes a region D1 for forming an electric circuit, and a seal ring 30 (guard ring) that surrounds the region D1 for forming the electric circuit. A DRAM 40 is formed in the region D1 for forming the electric circuit. Interlayer insulating films 22, 24, 26... Agent: Sughrue Mion, PLLC

20080048229 - Method for fabricating metallic bit-line contacts: A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080048230 - Semiconductor device and method for manufacturing the same: A semiconductor device including a semiconductor substrate and a recessed transistor provided on the semiconductor substrate, wherein the recessed transistor includes a recess formed in a surface of the semiconductor substrate, an insulating film provided on a surface in the recess, a gate electrode at least partly buried in the... Agent: Scully Scott Murphy & Presser, PC

20080048231 - Buried decoupling capacitors, devices and systems including same, and methods of fabrication: A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in... Agent: Schwegman, Lundberg & Woessner, P.A.

20080048232 - Trench-capacitor dram device and manufacture method thereof: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched... Agent: North America Intellectual Property Corporation

20080048233 - Methods for manufacturing a finfet using a conventional wafer and apparatus manufactured therefrom: A method is provided for producing a fin structure on a semiconductor substrate using a thin SiGe layer to produce a void between a silicon substrate and a silicon fin portion. A fin structure produced by such a method is also provided.... Agent: Joseph P. Abate Intellectual Property Law

20080048234 - Semiconductor memory device and method for fabricating same: A semiconductor memory device has a first interlayer insulating film formed on a semiconductor substrate and having a capacitor opening portion provided in the film, and a capacitance element formed over the bottom and sides of the capacitor opening portion and composed of a lower electrode, a capacitance insulating film,... Agent: Mcdermott Will & Emery LLP

20080048235 - Capacitor structure and method for preparing the same: A capacitor structure comprises a substrate having a contact plug, a conductive cylinder positioned on the substrate and an electroplating structure covering the conductive cylinder, wherein a bottom electrode of the capacitor structure comprises the conductive cylinder and the electroplating structure. The conductive cylinder can be a hollow conductive cylinder,... Agent: Oliff & Berridge, PLC

20080048236 - Parallel varactor capacitor: Provided is a parallel-varactor capacitor. The capacitor comprises a first varactor and a second varactor. The first varactor has a first capacitance which varies depending on voltages applied to a first anode and a first cathode. The second varactor has a second capacitance which varies depending on voltages applied to... Agent: Foley And Lardner LLP Suite 500

20080048238 - Nonvolatile semiconductor memory and method of fabrication thereof: There are provided a nonvolatile semiconductor memory of a structure in which electric signals from peripheral circuits are reliably transferred to control gates via word lines even if contact holes cannot be opened accurately above the word lines, and a method of fabricating the nonvolatile semiconductor memory. Plural word lines... Agent: Rabin & Berdo, PC

20080048237 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes: a source-line-side diode an anode region that is connected to a source line; a bit-line-side diode a cathode region that is connected to a bit line; and memory cell string connected between a cathode region of the source-line-side diode and an anode region of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080048241 - Nonvolatile semiconductor memory device and fabrication method therefor: Disclosed herein is a nonvolatile semiconductor memory device, including a memory transistor. The memory transistor has: a channel formation region defined between two source and drain regions formed on a semiconductor substrate; a bottom insulating film, a charge storage film and a top insulating film formed in order at least... Agent: Rader Fishman & Grauer PLLC

20080048240 - Printed non-volatile memory: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080048239 - Semiconductor memory device having dram cell mode and non-volatile memory cell mode and operation method thereof: A semiconductor memory device may have a DRAM cell mode and a non-volatile memory cell mode without a capacitor, including multiple transistors arranged in an array and having floating bodies, word lines connected to gate electrodes of the transistors, bit lines at a first side of the gate electrodes connected... Agent: Lee & Morse, P.C.

20080048242 - Semiconductor device having load resistor and method of fabricating the same: A semiconductor device includes a semiconductor substrate having a resistor region, an isolation layer disposed in the resistor region, the isolation layer defining active regions, first conductive layer patterns disposed on the active regions, a second conductive layer pattern covering the first conductive layer patterns and disposed on the isolation... Agent: Marger Johnson & Mccollom, P.C.

20080048244 - Nonvolatile memory, nonvolatile memory array and manufacturing method thereof: A nonvolatile memory includes a substrate, stacked gate structures, spacers, control gates, a composite dielectric layer and source region/drain regions. Each of stack gate structures is formed on the substrate and is consisted of a select gate dielectric layer, a select gate and a cap layer. The spacers are disposed... Agent: Jianq Chyun Intellectual Property Office

20080048243 - Nonvolatile semiconductor memory and manufacturing method thereof: A nonvolatile semiconductor memory includes a memory cell string having a plurality of memory cell transistors connected in series, a selection gate transistor connected in series with one end of the memory cell string, and having a gate electrode provided on a gate insulating film on a semiconductor substrate, and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080048245 - Semiconductor device and manufacturing methods thereof: A semiconductor device includes: a substrate having a main surface, a first main electrode formed on the main surface of the substrate, a pillar shaped semiconductor layer formed on the first main electrode and having poly crystal, a second main electrode formed on the pillar shaped semiconductor layer, an insulation... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080048246 - Multi-bit electromechanical memory devices and methods of manufacturing the same: In a memory device and a method of forming the same, in one embodiment, the memory device comprises a substrate and a bit line on the substrate extending in a first direction. A first word line structure is provided on the bit line and spaced apart from, and insulated from,... Agent: Mills & Onello LLP

20080048247 - Semiconductor device and semiconductor device fabrication method: A semiconductor device includes: source/drain regions formed in a semiconductor substrate; a trapping film for storing information by accumulating charges, the trapping film being formed in a region on the semiconductor substrate which includes a region on a channel region between the source/drain regions; and gate electrodes formed on the... Agent: Mcdermott Will & Emery LLP

20080048248 - Semiconductor memory device: Provided is a highly reliable multi-bit memory cell capable of miniaturization including: a semiconductor substrate with a channel formed therein; diffusion layers arranged at two sides of the channel, for serving as source/drain; an insulating film arranged on a part of the channel; a trap film made of an insulating... Agent: Mcginn Intellectual Property Law Group, PLLC

20080048249 - Semiconductor device and method of manufacturing the same: An interface between a bottom oxide film and a silicon nitride film in a neighborhood of a bottom part of a select gate is located at a position as high as or higher than that of an interface between a silicon substrate (p-type well) and a gate insulating film (d≧0)... Agent: Miles & Stockbridge PC

20080048250 - Mosfet with a thin gate insulating film: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the... Agent: Foley And Lardner LLP Suite 500

20080048251 - Lateral trench mosfet with direct trench polysilicon contact and method of forming the same: A lateral trench MOSFET includes a trench containing a device segment and a gate bus segment. The gate bus segment of the trench is contacted by a conductive plug formed in a dielectric layer overlying the substrate, thereby avoiding the need for the conventional surface polysilicon bridge layer. The conductive... Agent: Patentability Associates

20080048252 - Mosfet device suppressing electrical coupling between adjoining recess gates and mthod for manufacturing the same: A MOSFET device comprises a semiconductor substrate having a gate area, a storage node contact area and a bit line contact area. A first groove is defined at a first depth in the gate area and a second groove is defined at a second depth in the bit line contact... Agent: Townsend And Townsend And Crew, LLP

20080048254 - Semiconductor device and manufacturing method of the semiconductor device: A semiconductor device includes a power MOSFET including a trench formed on a surface of a semiconductor layer forming a drain; a gate electrode formed in the trench via a gate insulation film and made of poly-silicon; a channel diffusion layer formed at a surface side of the semiconductor layer... Agent: Cooper & Dunham, LLP

20080048253 - Semiconductor device having a recess channel structure and method for manufacturing the same: A semiconductor device includes a semiconductor substrate having an active region comprising a gate area, a bit line contact area and a storage node contact area. A recess is formed in the gate area and the bit line contact area. A gate is formed over the gate area and a... Agent: Townsend And Townsend And Crew, LLP

20080048255 - Insulated gate semiconductor device: Provided is an insulated gate semiconductor device. In the device, source regions are provided in the entire operation area and a first back gate region is provided below the source region between trenches. Moreover, a second back gate region connected to the first back gate region is provided outside of... Agent: Morrison & Foerster LLP

20080048256 - Semiconductor device: In an n-channel type power MISFET, a source electrode in contact with an n+-semiconductor region (source region) and a p+-semiconductor region (back gate contact region) is constituted with an Al film and an underlying barrier film comprised of MoSi2, use of the material having higher barrier height relation to n-Si... Agent: Miles & Stockbridge PC

20080048257 - Strained semiconductor power device and method: Semiconductor structures (52-9, 52-11, 52-12) and methods (100-300) are provided for a semiconductor devices employing strained (70) and relaxed (66) semiconductors, The method comprises, forming (106, 208, 308) on a substrate (54, 56, 58) first (66-1) and second (66-2) regions of a first semiconductor material (66) of a first conductivity... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080048258 - Trench power device and method: Means and methods are provided for trench TMOS devices (41-10, 11, 12), comprising, providing a first semiconductor (53, 53′) of a first composition having an upper surface (541), with a body portion (54) proximate the upper surface (541), a drift portion (46, 83) spaced apart from the upper surface (541)... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080048262 - Fin field effect transistor and method of forming the same: Provided are a fin field effect transistor (FinFET) with recess source/drain regions, and a method of forming the same. One example embodiment may provide a semiconductor device including a fin provided on a substrate and extending in a first direction, the fin including a stepped portion, and a gate electrode... Agent: Harness, Dickey & Pierce, P.L.C

20080048259 - Method for reducing defects in buried oxide layers of silicon on insulator substrates: A method and a structure for reducing defects in buried oxide layers of a silicon-on-insulator substrate. The method includes: generating a beam of infrared radiation of a selected wavelength; exposing a silicon-on-insulator substrate to the beam of infrared radiation, the substrate comprising a buried silicon dioxide layer between a lower... Agent: Schmeiser, Olsen & Watts

20080048260 - Thin film transistor array panel and method of manufacturing the same: A thin film transistor array panel includes a passivation layer formed on a plurality of end portions of a plurality of gate lines. A portion of the passivation layer has a porous structure formed between a connection portion of a flexible printed circuit substrate and a thin film transistor substrate... Agent: Cantor Colburn, LLP

20080048263 - High-voltage silicon-on-insulator transistors and methods of manufacturing the same: In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions... Agent: Ibm Corporation, Intellectual Property Law

20080048264 - Method for forming pattern of stacked film and thin film transistor: A method for forming a pattern of a stacked film, includes steps (a) to (e). The step (a) is forming sequentially a first base insulating film and a light shielding material on a transparent substrate. The step (b) is patterning the light shielding material to obtain a light shielding film... Agent: Mcginn Intellectual Property Law Group, PLLC

20080048261 - Semiconductor device and method of manufacturing the same: According to an aspect of the present invention, there is provided a semiconductor device including an insulated gate field effect transistor including a gate electrode film formed, via a gate insulating film, on a semiconductor film formed on a support substrate via an insulating film, and a source region and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080048265 - Semiconductor structures integrating damascene-body finfet's and planar devices on a common substrate and methods for forming such semiconductor structures: Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080048266 - Esd protection device and method: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were... Agent: Slater & Matsil LLP

20080048267 - Circuits and methods for improved fet matching: Various embodiments of the present invention provide circuits and methods for improved FET matching. As one example, such methods may include providing two or more transistors. Each of the transistors includes a channel that varies in cross-sectional width from the source to the drain, and the transistors are matched one... Agent: Hamilton And Desanctis

20080048268 - Semiconductor finfet structures with encapsulated gate electrodes and methods for forming such semiconductor finfet structures: Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work function of the gate electrode, is advantageously isolated... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080048269 - Method of fabricating structure for integrated circuit incorporating hybrid orientation technology and trench isolation regions: An embodiment of the present invention discloses a method of fabricating a structure for an integrated circuit incorporating hybrid orientation technology (HOT) and trench isolation regions. The structure of the integrated circuit comprising: a substrate with a first silicon layer of a first crystalline orientation and a second silicon layer,... Agent: Hoffman, Warnick & D'alessandro LLC

20080048270 - Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities: One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to... Agent: Larson Newman Abel Polansky & White, LLP

20080048271 - Structure and method to use low k stress liner to reduce parasitic capacitance: A low k stress liner, which replaces conventional stress liners in CMOS devices, is provided. In one embodiment, a compressive, low k stress liner is provided which can improve the hole mobility in pFET devices. UV exposure of this compressive, low k material results in changing the polarity of the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080048272 - Silicidation monitoring pattern for use in semiconductor manufacturing process: A silicidation monitoring pattern may electrically measure resistance of a polygate line after silicidation to measure open and/or short-circuiting of the polygate line. A silicidation monitoring pattern may minimize production costs. A silicidation monitoring pattern may quickly provide feedback based on a fabrication status.... Agent: Sherr & Nourse, PLLC

20080048273 - Method for doping a fin-based semiconductor device: A method for doping a fin-based semiconductor device is disclosed. In one aspect, the method comprises patterning at least one fin, each fin comprising a top surface and a left sidewall surface and a right sidewall surface. The method further comprises providing a first target surface being the right sidewall... Agent: Knobbe Martens Olson & Bear LLP

20080048274 - Semiconductor device including a gate electrode of lower electrical resistance and method of manufacturing the same: A semiconductor device may include a gate insulating layer on a semiconductor substrate, a polysilicon layer doped with impurities on the gate insulating layer, an interface reaction preventing layer on the polysilicon layer, a barrier layer on the interface reaction preventing layer, and a conductive metal layer on the barrier... Agent: Harness, Dickey & Pierce, P.L.C

20080048275 - Mos transistor, semiconductor device, and method of manufacturing the same: In a MOS transistor having a structure in which a source and a drain are raised on a substrate by using a selective epitaxial growth technique, a bulk resistance can be reduced while an impurity concentration of a silicon layer is reduced in the selective epitaxial growth. A metal oxide... Agent: Sughrue Mion, PLLC

20080048277 - Gate of a transistor and method of forming the same: A gate of a transistor includes a gate oxide layer formed on a semiconductor device, a first conductive layer pattern including polysilicon doped with boron and formed on the gate oxide layer, a diffusion preventing layer pattern including amorphous silicon formed by a chemical vapor deposition process using a reaction... Agent: Harness, Dickey & Pierce, P.L.C

20080048276 - Semiconductor device and method for manufacturing the same: A semiconductor device is provided including a transistor element on a substrate, a silicide on a gate and a source/drain of the transistor element; and an amorphous capping layer on the silicide.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080048278 - Method of forming pattern of inorganic material film and structure containing the pattern: A method of forming a pattern of an inorganic material film, which method is more versatile, easy, and practical. The method includes the steps of: (a) forming a sacrifice layer having a pattern on a substrate by employing a material having a different thermal expansion coefficient from that of an... Agent: Sughrue Mion, PLLC

20080048279 - Process for producing semiconductor substrate, semiconductor substrate for solar application and etching solution: Provided is: a process for producing safely at low cost a semiconductor substrate excellent in photoelectric transduction efficiency, in which a fine uneven structure suitable for a solar cell can be formed uniformly with desired size on the surface of the semiconductor substrate; a semiconductor substrate for solar application in... Agent: Marger Johnson & Mccollom, P.C.

20080048281 - Image sensor and fabricating method thereof: An image sensor according to embodiments may include a semiconductor substrate having a photo diode area formed thereon, a pre-metal dielectric (PMD) layer formed on the semiconductor substrate, at least one metal layer formed on the PMD layer, and a plurality of waveguides formed to penetrate through the metal layer... Agent: Sherr & Nourse, PLLC

20080048283 - Image sensor and fabricating method thereof: An image sensor is provided. The image sensor can include an isolation layer, a transistor region, and a photodiode region on a semiconductor substrate. A plurality of holes can be formed in the substrate of the photodiode region. The plurality of holes can be densely formed in the substrate. At... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080048284 - Image sensor and fabrication method thereof: An image sensor includes a semiconductor substrate having a pixel region and a peripheral region defined therein and having a pixel array formed in the pixel region; a PMD layer formed on the semiconductor substrate; at least one IMD layer formed over the PMD layer, wherein a region of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080048282 - Semiconductor device and fabricating method thereof: A semiconductor device for a system in a package (SiP) type device can include a semiconductor substrate; a pre-metal-dielectric (PMD) layer on the semiconductor substrate; at least one metal layer on the PMD layer; a first through-electrode extending through the semiconductor substrate and the PMD layer; and a second through-electrode... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080048280 - Light receiving device, method for fabricating same, and camera: The light receiving device of the present invention includes: a light receiving portion formed on a semiconductor substrate; and a light transmitting portion made of an organic material on an optical path reaching the light receiving portion, and the light transmitting portion contains heavy hydrogen. In the case where an... Agent: Hamre, Schumann, Mueller & Larson P.C.

20080048285 - Laminated wafer sensor system for uv dose measurement: A laminated wafer sensor structure includes a housing layer having pocket openings formed therein, a circuit layer having a sensor element and electronic components mounted for registration with the pocket openings in the housing layer, and a rigid back layer. The laminated structure is suitable for handling by conventional robotic... Agent: Stallman & Pollock LLP

20080048286 - Coplanar silicon-on-insulator (soi) regions of different crystal orientations and methods of making the same: In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI... Agent: Ibm Corporation, Intellectual Property Law

20080048287 - Isolation structures for integrated circuits and modular methods of forming the same: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall... Agent: Patentability Associates

20080048289 - Rf inductor of semiconductor device and fabrication method thereof: An RF inductor of a semiconductor device and a method of fabricating the same are provided. First and second interlayer dielectric layers are formed on an insulating layer and a lower metal interconnection. A via hole and a spiral-shaped trench are formed in the first and second interlayer dielectric layers.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080048288 - Semiconductor device: Embodiments relate to a semiconductor device and a fabrication method thereof. According to embodiments, the semiconductor device may includes a first substrate including an inductor cell, a second substrate including a RF (radio frequency) device circuit having a transistor and a wire, and a connection electrode for electrically connecting the... Agent: Sherr & Nourse, PLLC

20080048292 - Electronic device and manufacturing method thereof: In a BST thin film being a capacitor film in a capacitor element, the capacitor film is formed such that two kinds of chemical states of Sr(I) and Sr(II) exist at a portion of which depth is up to 2.5 nm from a surface thereof (surface layer portion of which... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080048290 - Semiconductor device and fabricating method: A semiconductor device and a relatively simple fabrication process which may maximize fabrication yield. A semiconductor device may include at least one of the following: A first substrate including a capacitor cell. A second substrate including a circuit unit having a transistor and a wire. A connection electrode which electrically... Agent: Sherr & Nourse, PLLC

20080048291 - Semiconductor interconnection structures and capacitors including poly-sige layers and metal contact plugs, and methods of fabricating the same: A semiconductor device includes a lower electrode of a capacitor, a dielectric layer disposed on the lower electrode, and an upper electrode of the capacitor disposed on the dielectric layer. The upper electrode includes a doped poly-Si1-xGex layer. An interlayer insulating layer is disposed on the doped poly-Si1-xGex layer and... Agent: Myers Bigel Sibley & Sajovec

20080048293 - Semiconductor device having heating structure and method of forming the same: A semiconductor device includes a lower electrode including a bottom wall portion and a sidewall portion extending upwardly from the bottom wall portion, and an insulating layer located over a top edge surface of the sidewall portion of the lower electrode. The insulating layer includes a contact window which partially... Agent: Volentine & Whitt PLLC

20080048294 - Semiconductor device with guard ring: A semiconductor device includes a semiconductor substrate; a circuit; a guard ring; a power source line; and a contact. The semiconductor substrate has a first conductive type. The circuit is formed on the semiconductor substrate. The guard ring is formed on the semiconductor substrate such that the guard ring surrounds... Agent: Young & Thompson

20080048295 - Insulated gate semiconductor device and method for manufacturing the same: There is provided a structure wherein an emitter layer 3 is provided in the region A on the first major surface side of a semiconductor substrate 1, and emitter layer 3 is not provided in the region b. There is provided a structure wherein a collector P layer 5 is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080048296 - Vertical bjt, manufacturing method thereof: A vertical BJT which has a maximal current gain for a photodiode area. According to embodiments, since the BJT can be formed together with the photodiode, and collector current flows up and down based on the double base structure, the magnitude of the current may be increased.... Agent: Sherr & Nourse, PLLC

20080048297 - Embedded interconnects, and methods for forming same: The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive interconnect structure that is embedded in the isolation region... Agent: Scully, Scott, Murphy & Presser, P.C.

20080048298 - Semiconductor devices, assemblies and constructions, and methods of forming semiconductor devices, assemblies and constructions: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the... Agent: Wells St. John P.s.

20080048299 - Electronic component with semiconductor chips, electronic assembly composed of stacked semiconductor chips, and methods for producing an electronic component and an electronic assembly: An electronic component includes a semiconductor chip with an active front face and a passive rear face, with contact connections and contact surfaces respectively being provided on the active front face and/or on the passive rear face, and with conductive connections being provided in the form of structured conductive tracks... Agent: Lerner Greenberg Stemer LLP For Infineon Technologies Ag

20080048300 - Silicon epitaxial wafer and method for manufacturing the same: This method for manufacturing a silicon epitaxial wafer includes: a step of growing an epitaxial layer having silicon on a silicon wafer having a main surface of {110}; and a cooling step of cooling the silicon wafer after growing the epitaxial layer. In a first aspect, in the cooling step,... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20080048301 - Pre-encapsulated lead frames for microelectronic device packages, and associated methods: Pre-encapsulated lead frames suitable for use in microelectronic device packages are disclosed. Individual lead frames can include a set of multiple lead fingers arranged side by side with neighboring lead fingers spaced apart from each other by a corresponding gap. An encapsulating compound at least partially encapsulates the set of... Agent: Perkins Coie LLP Patent-sea

20080048302 - Systems and methods for low profile die package: A semiconductor integrated circuit (IC) device is defined by a low-profile package without a die attach pad (DAP). In place of the DAP, an adhesive element is used to retain a die relative to a lead frame during processing. In one example, a method of manufacturing the device includes sealing... Agent: Kathy Manke Avago Technologies Limited

20080048303 - Semiconductive device having improved copper density for package-on-package applications: In one aspect, the invention provides a semiconductor device that comprises a semiconductor device packaging substrate core. A first interconnect structure is located within a mold region and on a die side of the substrate core and has a first conductive metal density associated therewith. A second interconnect structure is... Agent: Texas Instruments Incorporated

20080048304 - Heat slug for package structure: A heat slug is provided for a package structure, including a main body and a plurality of protrusions. The main body has a surface in which at least one ditch is defined. Each protrusion is connected to and extends from the main body and has a surface in which a... Agent: Madson & Austin

20080048305 - Negative thermal expansion system (ntes) device for tce compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging: A Negative Thermal Expansion system (NTEs) device for TCE compensation or CTE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging. One aspect of the present invention provides a method for fabricating micromachine devices that have negative thermal expansion coefficients that can be made into a composite for... Agent: F. Chau & Associates, LLC

20080048306 - Electro-chemical processor: A processor for making porous silicon or processing other substrates has first and second chamber assemblies. The first and second chamber assemblies include first and second seals for sealing against a wafer, and first and second electrodes, respectively. The second seal is moveable towards and away from a wafer in... Agent: Perkins Coie LLP/semitool

20080048307 - Module and mounted structure using the same: A module that can not only achieve the reduction in size and manufacturing cost but also be impervious to noise due to electromagnetic waves, and a mounted structure using the same are provided. A module (1) includes a substrate (12) and a plurality of semiconductor packages (11a, 11b), each including... Agent: Hamre, Schumann, Mueller & Larson P.C.

20080048309 - Metal core foldover package structures, systems including same and methods of fabrication: Chip scale packages and assemblies thereof and methods of fabricating such packages including Chip-On-Board, Board-On-Chip, and vertically stacked Package-On-Package modules are disclosed. The chip scale package includes a core member of a metal or alloy having a recess for at least partially receiving a die therein and includes at least... Agent: Trask Britt

20080048308 - Stackable packages for three-dimensional packaging of semiconductor dice: An apparatus and a method for packaging semiconductor devices. The apparatus includes a substrate strip component of a leadless three-dimensional stackable semiconductor package having mounting contacts on, for example, four peripheral edges. The substrate strip may either be fabricated for mounting a single electrical component (e.g., an integrated circuit die)... Agent: Schneck & Schneck

20080048310 - Carrier board structure embedded with semiconductor component and method for fabricating the carrier board structure: A carrier board structure with a semiconductor component embedded therein and a method for fabricating the same are proposed. The method provides at least one semiconductor component and a carrier having a first surface and a second surface opposed to the first surface and at least one through hole. The... Agent: Fulbright And Jaworski LLP

20080048311 - Semiconductor device, substrate for producing semiconductor device and method of producing them: A substrate B for use in production of a semiconductor device is used, which substrate includes an adhesive sheet 50 having a base layer 51 and an adhesive layer 52, and a plurality of independently provided electrically conductive portions 20. A semiconductor element having electrodes 11 formed thereon is firmly... Agent: Oliff & Berridge, PLC

20080048312 - Semiconductor package and method for manufacturing the same: A semiconductor package comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an active surface, a back surface opposite to the active surface, an optical component disposed on the active surface, and a... Agent: Reed Smith LLP

20080048313 - Wafer bonding method: One embodiment of a micro-electronic device includes a substrate including micro-electronic components thereon, and a cover including a ring of sealing material secured to the substrate and a raised ring of material positioned opposite the cover from the ring of sealing material.... Agent: Hewlett Packard Company

20080048314 - Integrated circuit cooling and insulating device and method: A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a... Agent: Schwegman, Lundberg & Woessner/micron

20080048315 - Electronic device and package used for the same: [SOLUTION A laminate ceramic electronic device of the present invention has filter chips 2, 3 for transmission and reception mounted therein. A wiring pattern 7, which connects an input terminal A of the transmission filter chip 2 with a transmission side signal terminal Tx in a first arrangement, has two... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080048316 - Packaged microdevices and methods for manufacturing packaged microdevices: Microdevices and methods for packaging microdevices. One embodiment of a packaged microdevice includes a substrate having a mounting area, contacts in the mounting area, and external connectors electrically coupled to corresponding contacts. The microdevice also includes a die located across from the mounting area and spaced apart from the substrate... Agent: Perkins Coie LLP Patent-sea

20080048318 - Semiconductor device and semiconductor package: For delivering supply power evenly into chip, a semiconductor device includes plural power supply pads 17a and grounding pads 18a, arranged in alternation in X-direction. The device also includes first upper layer power supply wire 17b, extending in X-direction and connected to first ends of the power supply pads 17,... Agent: Young & Thompson

20080048319 - Semiconductor device having pads: A semiconductor device having pads is provided. The semiconductor device includes first pads formed along a first row, and second pads formed along a second row. The first via contact portions extending from the first pads toward the second row, and second via contact portions extending from the second pads... Agent: Harness, Dickey & Pierce, P.L.C

20080048317 - Electric component with a flip-chip construction: A component includes a carrier substrate having a coefficient of thermal expansion αp and a chip mounted on the carrier substrate by a plurality of bumps. The chip has a first coefficient of thermal expansion α1 in a first direction x1 and a first expansion difference, Δα1 equal to the... Agent: Fish & Richardson PC

20080048320 - Low fabrication cost, fine pitch and high reliability solder bump: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about... Agent: Mou-shiung Lin

20080048321 - Flip chip semiconductor assembly with variable volume solder bumps: A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column... Agent: Vedder Price Kaufman & Kammholz

20080048323 - Stacked structure of chips and wafer structure for making the same: A stacked structure of chips including a first chip, a second chip, an insulation layer and a first conductive element is provided. The second chip is attached to the first chip, and the back surface of the second chip faces an active surface of the first chip. The second chip... Agent: Birch Stewart Kolasch & Birch

20080048322 - Semiconductor package including redistribution pattern and method of manufacturing the same: A semiconductor device package includes a substrate, first and second chip pads spaced apart over a surface of the substrate, and an insulating layer located over the surface of the substrate. The insulating layer includes a stepped upper surface defined by at least a lower reference potential line support surface... Agent: Volentine & Whitt PLLC

20080048324 - Fabricating semiconductor device: A method for fabricating a semiconductor device is provided. The method includes: etching an area where a plurality of modules are formed on a semiconductor substrate; forming a plurality of modules on the area; forming on insulation layer on the substrate; forming a plurality of contacts that contact a plurality... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080048326 - Semiconductor device: According to embodiments, a semiconductor device may include a PMD layer provided with a contact, and a wiring layer formed on the PMD layer and connected to the contact by stacking and forming a plurality of metal layers thereon. In embodiments, the plurality of metal layers may include a first... Agent: Sherr & Nourse, PLLC

20080048325 - Semiconductor device and fabricating method thereof: A method of effectively fabricating a semiconductor device involves separately fabricating a first substrate having a transistor layer and a second substrate having a metal wire layer, and stacking the first and second substrates. A transistor on the first substrate is electrically connected to a metal wire on the second... Agent: Sherr & Nourse, PLLC

20080048327 - Electronic circuit with embedded memory: Circuitry includes first and second circuits spaced apart by an interconnect region. The interconnect region includes a first interconnect and the second circuit includes a stack of semiconductor layers. The first interconnect extends between the first and second circuits to provide communication therebetween. The second circuit operates as a memory... Agent: Schmeiser Olsen & Watts

20080048328 - Chip structure and process for forming the same: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric... Agent: Mou-shiung Lin

20080048329 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20080048330 - Implantable microelectronic device and method of manufacture: An implantable hermetically sealed microelectronic device and method of manufacture are disclosed. The microelectronic device of the present invention is hermetically encased in a insulator, such as alumina formed by ion bean assisted deposition (“IBAD”), with a stack of biocompatible conductive layers extending from a contact pad on the device... Agent: Scott B. Dunbar Second Sight Medical Products, Inc.

20080048332 - Method for forming intermetal dielectric in semiconductor device: A method for forming an intermetal dielectric in a semiconductor device includes the steps of: forming metal wiring patterns electrically connecting circuit devices on a silicon substrate provided with the predetermined semiconductor circuit devices; forming a first silicon oxide film electrically isolating the metal wiring patterns; forming a second silicon... Agent: Sherr & Nourse, PLLC

20080048331 - Power/ground network of integrated circuits and arrangement thereof: An arrangement scheme for a power/ground (P/G) network of an integrated circuit is provided. Rows of standard cells in the integrated circuit are horizontally arranged. The P/G network has horizontal and vertical metal lines arranged in different metal layers. The horizontal metal lines have horizontal power metal lines and horizontal... Agent: Wpat, PC

20080048333 - Semiconductor device having buried word line interconnects and method of fabricating the same: A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate... Agent: Myers Bigel Sibley & Sajovec

20080048334 - Semiconductor devices and methods of fabricating the same: Embodiments include a semiconductor device comprising: a pad formed on an insulating layer and having an electric connection region with external components; and a protective insulating layer which has an aperture for exposing the electric connection region. The protective insulating layer may include a first insulating layer and a second... Agent: Konrad Raynes & Victor, LLP

20080048339 - Metal line structures and methods of forming the same: Example embodiments may provide metal line structures, and example methods may include forming the same. Example embodiment metal line structures may include a first metal line on a substrate, a first barrier metal layer on sidewalls and a lower surface of the first metal line, a first insulating layer covering... Agent: Harness, Dickey & Pierce, P.L.C

20080048335 - Semiconductor device: A semiconductor device according to embodiments may include an interposer, a plurality of devices stacked and formed on the interposer, through electrodes each formed in the plurality of devices and formed by penetrating through the respective devices, and connecting electrodes formed between the respective devices and connecting a through electrode... Agent: Sherr & Nourse, PLLC

20080048338 - Semiconductor device and fabrication method thereof: A semiconductor device and a fabricating method thereof are provided. An insulating layer pattern has a via hole exposing a lower metal layer, and a copper via is provided inside the via hole. A TiSiN layer is disposed on the insulating layer pattern and the copper via, and an interconnection... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080048336 - Semiconductor device and method for manufacturing the same: A semiconductor device and method for manufacturing the same are provided, capable of narrowing feature size by utilizing the property of oxidation of a material. In one method, a polysilicon layer can be patterned into a fine pattern up to a critical dimension using a photolithography process. Then the patterned... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080048337 - Semiconductor device including through electrode and method of manufacturing the same: The present invention provides a semiconductor device including at least one of an insulating layer and a semiconductor layer each including a hole formed therein, and a through electrode provided in the hole. In the semiconductor device, the side wall of the hole is constituted of a first region from... Agent: Young & Thompson

20080048340 - Semiconductor device having fine pattern wiring lines integrally formed with contact plug and method of manufacturing same: A semiconductor device and method are disclosed in which an interlayer insulating layer is patterned using multiple overlaying masks to define the geometry of contact plugs and corresponding wiring layers separated by fine pitches.... Agent: Volentine & Whitt PLLC

20080048341 - Chip with a vertical contact structure: A chip with a chip plane includes a functional area, a contact structure vertical with respect to the chip plane for connecting the functional area, which includes a conductive material, which has a predetermined length, and a vertical dummy-contact structure, which extends vertically into the functional area and which has... Agent: Dickstein Shapiro LLP

20080048342 - Multi-chip module: A multi-chip module that includes a conductive element connecting at least two semiconductor devices, the conductive element including enhancements for improving the mechanical coupling between the conductive element and the molded housing of the MCM.... Agent: Ostrolenk Faber Gerb & Soffen

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