Active solid-state devices (e.g., transistors, solid-state diodes) inventions 12/07

20070295948 - Nonvolatile memory cell with concentric phase change material formed around a pillar arrangement: A memory cell comprises a first feature and a second feature. The second feature comprises a dielectric material and defines an opening at least partially overlying the first feature. A third feature is formed on the first feature and partially fills the opening in the second feature. What is more,... Agent: Ryan, Mason & Lewis, LLP

20070295949 - Phase change memory device and fabrication method thereof: A phase change memory device comprising an electrode, a phase change layer crossing and contacting the electrode at a cross region thereof, and a transistor comprising a source and a drain, wherein the drain of the transistor electrically connects the electrode or the phase change layer is disclosed.... Agent: Quintero Law Office, PC

20070295950 - Variable resistance random access memory device and a method of fabricating the same: Provided is a variable resistance random access memory device having an n+ interfacial layer and a method of fabricating the same. The variable resistance random access memory device may include a lower electrode, an n+ interfacial layer on the lower electrode, a buffer layer on the n+ interfacial layer, an... Agent: Harness, Dickey & Pierce, P.L.C

20070295951 - Light-emitting diode incorporating an array of light extracting spots: A light-emitting diode includes an optical layer formed in an array of substantially equidistant light extracting spots integrated to its multi-layer structure. The array of light extracting spots includes a distribution of juxtaposed hexagon patterns. The layer thickness of the light extracting spots is less than 800 Å, and preferably... Agent: David I. Roche Baker & Mckenzie LLP

20070295952 - Light emitting diode having vertical topology and method of making the same: An LED having vertical topology and a method of making the same is capable of improving a luminous efficiency and reliability, and is also capable of achieving mass productivity. The method includes forming a semiconductor layer on a substrate; forming a first electrode on the semiconductor layer; forming a supporting... Agent: Mckenna Long & Aldridge LLP

20070295957 - Dispersant compound and method for preparing the same: Disclosed herein are a novel oligomeric compound with improved dispersion performance and a method for preparing the same. The oligomeric compound comprises a tail structure consisting of hydrophilic and hydrophobic blocks and an amine or imidazole head structure. The dye containing the compound can be used to prepare a paste... Agent: Cantor Colburn, LLP

20070295956 - Optoelectronic device: The present invention provides an optoelectronic device comprising a light emitting semiconductor and an encapsulant. The encapsulant is made from an encapsulant formulation comprising an epoxy hydantoin, an epoxy isocyanurate, and a curing agent. The present invention also provides a method of preparing such optoelectronic device.... Agent: Fay Sharpe LLP

20070295961 - Organic light emitting display: An organic light emitting display is disclosed. One embodiment of the organic light emitting display includes a substrate member and a plurality of pixels that are formed on the substrate member. At least one of the pixels includes a thin film transistor, a light emitting element that is electrically connected... Agent: Knobbe Martens Olson & Bear LLP

20070295959 - Organic light-emitting display device: An organic light-emitting display device wherein an IR drop across a first electrode can be prevented. The organic light-emitting display device includes a substrate; a plurality of stripe-shaped first electrodes disposed on the substrate and extending in a first direction; a plurality of stripe-shaped first insulators extending in a second... Agent: Stein, Mcewen & Bui, LLP

20070295960 - Semiconductor device, electro-optical device, electronic apparatus, and method of producing semiconductor device: A semiconductor device includes an organic semiconductor transistor provided on a substrate; a data line connected to a source electrode or a drain electrode of the organic semiconductor transistor; and a gate line that is disposed so as to intersect the data line and that is connected to a gate... Agent: Harness, Dickey & Pierce, P.L.C

20070295958 - Semiconductor structure having a low hot-carrier effect characteristic: The present invention relates to a semiconductor structure having a low hot-carrier effect characteristic, and, more particularly, to a semiconductor structure capable of reducing the detrimental influence of the happening of the hot-carrier effect on the performance of the transistor having the semiconductor structure, even after the transistor has been... Agent: Bacon & Thomas, PLLC

20070295962 - Organic light emitting diode display and method for manufacturing the same: An organic light emitting diode (“OLED”) display includes a substrate, a gate line, a data line, a driving voltage line, a light blocking member, a switching thin film transistor (“TFT”), a driving TFT, and an OLED, wherein the driving voltage line includes a portion parallel to at least one of... Agent: Cantor Colburn, LLP

20070295963 - Tft array substrate and method of manufacturing the same: A TFT array substrate includes a TFT having an ohmic contact film and a source electrode and a drain electrode formed on the ohmic contact film. It also includes a pixel electrode electrically connected with the drain electrode. The source electrode and the drain electrode are made of an Al... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070295965 - Thin film transistor, method of fabricating the same, and method of fabricating liquid crystal display device having the same: A thin film transistor includes a gate electrode, a gate insulation layer on the gate electrode, source and drain electrodes formed on the gate insulation layer, a polysilicon channel layer overlapping the ohmic contact layers and on the gate insulation layer between the source and drain electrodes, ohmic contact regions... Agent: Seyfarth Shaw, LLP

20070295966 - Conversion apparatus and imaging system: A conversion apparatus comprises a pixel region, on a substrate, including a plurality of pixels arranged in a matrix, each pixel having a conversion element that converts radiation into electric signals and a switching element, wherein the switching element has a structure comprising a gate electrode, a first insulating layer,... Agent: Fitzpatrick Cella Harper & Scinto

20070295970 - Base apparatus of a light emitting diode and method for manufacturing the light emitting diode: A base apparatus includes a base and two finger devices. The base has a first surface and two opposite sides. The finger devices are respectively mounted on the sides of the base, are made of conductive material, and each of the finger devices has multiple fingers. The fingers are extended... Agent: Rabin & Berdo, PC

20070295968 - Electroluminescent device with high refractive index and uv-resistant encapsulant: An encapsulant containing nanoparticles that improve the heat and UV resistance properties of electroluminescent devices. The nanoparticles that are suspended in the encapsulant may be either oxides or non-oxides and may include SiO2, TiO2, Al2O3, ZrO2, Ti, TiB2, TiC, and TiN. The nanoparticles may range in size from 5 to... Agent: Kathy Manke Avago Technologies Limited

20070295969 - Led device having a top surface heat dissipator: An LED Device Having a Top Surface Heat Dissipator is provided. The LED Device Having a Top Surface Heat Dissipator includes a substrate body, and a light emitting diode over the substrate body. The LED Device Having a Top Surface Heat Dissipator also has an electrically and thermally conductive heat... Agent: Kathy Manke Avago Technologies Limited

20070295971 - Light emitting device and method for fabricating the same: Disclosed are a light emitting device and a method for fabricating the same. The light emitting device can include a substrate, a buffer layer having a pattern on the substrate, a first conductive-type semiconductor layer on the buffer layer, an active layer on the first conductive-type semiconductor layer, and a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070295972 - Light emitting diode module: A light emitting diode module is disclosed. The light emitting diode module includes a substrate, a plurality of light emitting diodes, and a plurality of lenses. The light emitting diodes are disposed on the substrate, and the lenses are disposed on the substrate and covering the light emitting diodes, in... Agent: North America Intellectual Property Corporation

20070295979 - Led device having reduced spectrum: A structure of light emitting diode (LED) effectively reduces its spectral width. The LED structure is applied in a three color mixing of a backlight module to broaden a color space and to improve a saturation of a color display. A grating structure is used as a waveguide layer to... Agent: Troxell Law Office PLLC

20070295978 - Light emitting diode with direct view optic: An LED and light guide assembly has an LED with an output surface; a first power input lead electrically coupled to a first pole and having a first surface and a second surface; and a second power input lead electrically coupled to a second pole and having a first surface... Agent: William E. Meyer Osram Sylvania Inc.

20070295982 - Micro universal serial bus memory package and manufacturing method the same: In order to accomplish the object of the present invention, there is disclosed a micro USB memory package, which comprises a substrate with a plurality of circuit patterns formed on the top surface thereof, at least one of passive elements connected with the circuit patterns of the substrate, at least... Agent: St. Onge Steward Johnston & Reens, LLC

20070295953 - Germanium phototransistor with floating body: A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070295954 - Method and structure to isolate a qubit from the environment: A method (and structure) of coupling a qubit includes locating the qubit near a transmission line approximately at a location corresponding to a node at a predetermined frequency.... Agent: Mcginn Intellectual Property Law Group, PLLC

20070295955 - N-channel transistor: An n-channel or ambipolar field-effect transistor including an organic semiconductive layer having an electron affinity EAsemicond; and an organic gate dielectric layer forming an interface with the semiconductive layer; characterised in that the bulk concentration of trapping groups in the gate dielectric layer is less than 1018cm−3, where a trapping... Agent: Sughrue Mion, PLLC

20070295964 - Semiconductor device and method for preparing the same: A semiconductor device and a method for preparing the same that can solve crack of a semiconductor film, capacitance electrodes and the like due to stress when forming a source electrode and a drain electrode in a semiconductor device having a thin film transistor and a holding capacitance with three... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070295967 - Active matrix tft array substrate and method of manufacturing the same: An active matrix TFT array substrate includes a gate electrode and a gate line formed from a first metal film over a transparent insulating substrate, a gate insulating film to cover the gate electrode and gate line, a semiconductor layer formed over the gate insulating film, a source electrode and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070295974 - Incoherent combination of laser beams: A method of combining beams from a plurality of laser resonators includes frequency modulating the output of each of the lasers with one or more of the lasers frequency modulated out-of-phase with the others. The frequency modulated beams are directed along parallel spaced-apart paths and overlap in a plane along... Agent: Stallman & Pollock LLP

20070295973 - Method for manufacturing semiconductor device: The present invention provides a manufacturing technique of a semiconductor device and a display device using a peeling process, in which a transfer process can be conducted with a good state in which a shape and property of an element before peeling are kept. Further, the present invention provides a... Agent: Eric Robinson

20070295975 - Light-emitting device: A light-emitting device (1) is composed by integrating light-emitting diodes (2R, 2G, 2B) and a drive IC (3) for driving these light-emitting diodes (2R, 2G, 2B). The light-emitting device (1) is characterized in that the drive IC (3) has a built-in circuit for controlling the current value of each light-emitting... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070295976 - Semiconductor device and production method thereof: The semiconductor device of the present invention is a semiconductor device including P-type and N-type thin film transistors, at least one of the N-type thin film transistors having an off-set gate structure, at least one of the P-type thin film transistors having a LDD structure, wherein a P-type high concentration... Agent: Nixon & Vanderhye, PC

20070295977 - Optical semiconductor device and method of manufacturing the same: Provided is an optical semiconductor device, which includes a GaAs substrate (or a semiconductor substrate) 20; an n-type contact layer (or a doping layer) 21 formed on one surface 20a of the GaAs substrate 20; an active layer 25 formed on top of the n-type contact layer 21 and including... Agent: Kratz, Quintos & Hanson, LLP

20070295981 - Patterned light-emitting devices: Light-emitting devices (e.g., LEDs) and methods associated with such devices are provided. The devices may include a first pattern and a second pattern which are formed at one or more interfaces of the device (e.g., the emission surface). The patterns may be positioned such that light generated by the device... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.C.

20070295980 - Semiconductor light emitting device, illuminating device, mobile communication device, camera, and manufacturing method therefor: A semiconductor light emitting device 100 comprises: a mount member 130 and a semiconductor light emitting element 110 arranged on the mount member 130, the mount member 130 including: a substrate 131; an electrode assembly (a positive electrode 134, a negative electrode 135, and bumps 140 to 144) that is... Agent: Wenderoth, Lind & Ponack L.L.P.

20070295983 - Optoelectronic device: The present invention provides an optoelectronic device comprising a light emitting semiconductor and an encapsulant. The encapsulant is made from an encapsulant formulation comprising an epoxy isocyanurate such as formula (I-1) compound, and a curing agent. The present invention also provides a method of preparing such optoelectronic device.... Agent: Fay Sharpe LLP

20070295985 - Gallium nitride material devices and methods of forming the same: The invention provides gallium nitride material devices, structures and methods of forming the same. The devices include a gallium nitride material formed over a substrate, such as silicon. Exemplary devices include light emitting devices (e.g., LED's, lasers), light detecting devices (such as detectors and sensors), power rectifier diodes and FETs... Agent: Wolf Greenfield & Sacks, P.C.

20070295984 - Gan based luminescent device on a metal substrate: e

20070295986 - Method of fabricating vertical structure leds: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate,... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070295987 - Semiconductor device and method of driving the same: A semiconductor device includes: a bulk semiconductor substrate; a thyristor formed in the bulk semiconductor substrate; a gate electrode formed at the third region; and a well region. The thyristor included a first region of a first conduction type, a second region of a second conduction type opposite to the... Agent: Rader Fishman & Grauer PLLC

20070295988 - Dual-gate sensor: A sensor includes a first gate electrode, a second gate electrode, a semiconductor layer, a gate-insulating layer, a source electrode, a drain electrode, and a sensing portion including an accommodating part and a receiving layer. The first and second gate electrodes are opposed to each other with the sensing portion,... Agent: Fitzpatrick Cella Harper & Scinto

20070295992 - Hetero junction field effect transistor and method of fabricating the same: There is provided a hetero junction field effect transistor including: a first layer of a nitride based, group III-V compound semiconductor; a second layer of a nitride based, group III-V compound semiconductor containing a rare earth element, overlying the first layer; a pair of third layers of a nitride based,... Agent: Birch Stewart Kolasch & Birch

20070295991 - Semiconductor device and manufacturing method of the same: A semiconductor device according to the present invention includes: a semiconductor substrate; a channel layer formed on the semiconductor substrate; a donor layer formed on the channel layer; a first Schottky layer formed on the donor layer; a second Schottky layer formed on the first Schottky layer; a first gate... Agent: Greenblum & Bernstein, P.L.C

20070295989 - Strained semiconductor device and method of making same: A semiconductor body is formed from a first semiconductor material, e.g., silicon. A compound semiconductor region, e.g., silicon germanium, is embedded in the semiconductor body. The compound semiconductor region includes the first semiconductor material and a second semiconductor material. The compound semiconductor region has a concentration of the second semiconductor... Agent: Slater & Matsil LLP

20070295990 - Gan-based field effect transistor and production method therefor: A GaN-based heterostructure field effect transistor capable of accomplishing higher output, higher breakdown voltage, higher speed, higher frequency, and the like. A heterostructure field effect transistor including a channel layer (4) of GaN and a barrier layer (6) of AlGaN, wherein the surface of a transistor element has an insulating... Agent: Osha Liang L.L.P.

20070295993 - Low density drain hemts: Methods and devices for fabricating AlGaN/GaN normally-off high electron mobility transistors (HEMTs). A fluorine-based (electronegative ions-based) plasma treatment or low-energy ion implantation is used to modify the drain-side surface field distribution without the use of a field plate electrode. The off-state breakdown voltage can be improved and current collapse can... Agent: Groover & Holmes

20070295994 - Hetero junction bipolar transistor: A hetero-junction bipolar transistor is provided including emitter contact region, an emitter region made of a first semiconductor material, a base region made of a second semiconductor material having a smaller energy band gap than the first semiconductor material, a collector region made of the first semiconductor material, and a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070295995 - Methods of forming a semiconductor device including buried bit lines: A method of forming a buried interconnection includes removing a semiconductor substrate to form a groove in the semiconductor substrate. A metal layer is formed on inner walls of the groove using an electroless deposition technique. A silicidation process is applied to the substrate having the metal layer, thereby forming... Agent: Marger Johnson & Mccollom, P.C.

20070295996 - Closed cell configuration to increase channel density for sub-micron planar semiconductor power device: A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the... Agent: Bo-in Lin

20070295998 - Forward body bias-controlled semiconductor integrated circuit: In a first functional block, a source voltage input terminal of a PMOS transistor and a substrate voltage input terminal of an NMOS transistor are connected to their voltage supply terminals, respectively. The substrate voltage input terminal of the PMOS transistor in the ith (1≦i≦n−1) functional block and the source... Agent: Mcdermott Will & Emery LLP

20070295997 - Integrated circuit anti-interference outline structure: ABSTRACT The invention discloses an integrated circuit anti-interference outline structure for applications of integrated circuits capable of shielding the integrated circuit from invasions of external electromagnetic waves and leaks of internal electromagnetic waves, wherein the integrated circuit anti-interference outline structure surrounds a periphery of a partial circuit within the integrated... Agent: Alcor Micro, Corp.

20070295999 - Semiconductor memory device and method of forming the same: Example embodiments provide a semiconductor memory device and method of forming a semiconductor memory device that may equalize load due to a coupling capacitance between a line and a component signal when the line intersects the component signal in a memory cell array. A line may intersect a memory cell... Agent: Harness, Dickey & Pierce, P.L.C

20070296000 - Method for manufacturing a semiconductor device: A method for manufacturing a semiconductor device, includes: partially forming an epitaxial growth stopper film on a single crystal semiconductor substrate; sequentially depositing a first semiconductor layer and a second semiconductor layer on the semiconductor substrate by an epitaxial growth process; forming a first groove penetrating through the second semiconductor... Agent: Advantedge Law Group, LLC

20070296001 - Multiple conduction state devices having differently stressed liners: A field effect transistor (“FET”) is provided which includes an active semiconductor region including a channel region, a first source-drain region and a second source-drain region. A major surface of the active semiconductor region is divided into a mutually exclusive first portion and a second portion. A first liner applies... Agent: International Business Machines Corporation Dept. 18g

20070296002 - Backside contacts for mos devices: A semiconductor structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a gate dielectric over the first surface of the semiconductor substrate, a gate electrode over the gate dielectric, a source/drain region having at least a portion in the semiconductor substrate, a... Agent: Slater & Matsil, L.L.P.

20070296003 - Thin film transistor substrate and method for manufacturing the same: A thin-film transistor (TFT) substrate includes a base substrate, a semiconductor layer, a gate insulating layer, a first gate electrode and a second gate electrode. The semiconductor layer is formed on the base substrate and includes source, drain, channel and low concentration doped regions. The channel region is formed between... Agent: F. Chau & Associates, LLC

20070296004 - Suppression of dark current in a photosensor for imaging: A pixel cell having a halogen-rich region localized between an oxide isolation region and a photosensor. The halogen-rich region prevents leakage from the isolation region into the photosensor, thereby suppressing dark current in imagers.... Agent: Dickstein Shapiro LLP

20070296005 - Edge illuminated photodiodes: This invention comprises plurality of edge illuminated photodiodes. More specifically, the photodiodes of the present invention comprise novel structures designed to minimize reductions in responsivity due to edge surface recombination and improve quantum efficiency. The novel structures include, but are not limited to, angled facets, textured surface regions, and appropriately... Agent: Patentmetrix

20070296006 - Structure for pixel sensor cell that collects electrons and holes: The present invention relates to a design structure for a pixel sensor cell. The pixel sensor cell approximately doubles the available signal for a given quanta of light. A design structure for a pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of... Agent: Ibm Microelectronics Intellectual Property Law

20070296008 - Semiconductor device: A semiconductor device includes: a semiconductor substrate; a transistor formed on the semiconductor substrate; an interlayer dielectric layer that covers the transistor; a ferroelectric capacitor formed above the interlayer dielectric layer and having a first electrode, a ferroelectric layer and a second electrode; another interlayer dielectric layer that covers the... Agent: Harness, Dickey & Pierce, P.L.C

20070296007 - Shared ground contact isolation structure for high-density magneto-resistive ram: A buried ground contact that connects the ground electrodes of transistors in adjacent memory cells that are separated by an isolation region is described. In some embodiments, the buried ground contact passes beneath the isolation region that separates cells to electrically connect the drain regions of transistors in adjacent cells.... Agent: Slater & Matsil LLP

20070296009 - Semiconductor device including a capacitance: It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070296010 - Pick-up structure for dram capacitors and dram process: A pick-up structure for DRAM capacitors and a DRAM process are described. A substrate with trenches therein is provided, wherein the trenches include a first trench and the sidewall of each of the trenches is formed with a dielectric layer thereon. A conductive layer is formed on the surfaces of... Agent: Jianq Chyun Intellectual Property Office

20070296011 - Structure and method for accurate deep trench resistance measurement: A test structure for implementing resistance measurement of a deep trench formed in a semiconductor device includes a pair of deep trenches formed within a semiconductor substrate. The pair of deep trenches has a dielectric material formed on side and bottom surfaces thereof, and includes a conductive fill material therein.... Agent: Cantor Colburn LLP - IBM Fishkill

20070296012 - Structure and method for accurate deep trench resistance measurement: A test structure for implementing resistance measurement of a deep trench formed in a semiconductor device includes a deep trench formed within a semiconductor substrate. The deep trench has a dielectric material formed on upper portions of sidewall surfaces thereof, and includes a conductive fill material therein. A doped buried... Agent: Cantor Colburn LLP - IBM Fishkill

20070296013 - Semiconductor device structure for reducing mismatch effects: An integrated circuit chip includes a first electronic device, a second electronic device, and a common electrode feature. The first electronic device includes a first feature. The first electronic device has a first footprint area in a given layer. The second electronic device includes a second feature. The second electronic... Agent: Slater & Matsil, L.L.P.

20070296014 - Semiconductor memory device and manufacturing method therefor: This disclosure concerns a semiconductor memory comprising Fin-type semiconductor layers (Fins) provided on the insulation layer provided on a substrate; first gate insulation films provided on first side surfaces of the Fins; second gate insulation films provided on second side surfaces of the Fins, the second side surfaces being opposite... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070296015 - Memory devices having reduced interference between floating gates and methods of fabricating such devices: A floating gate memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another and methods of fabricating the same. Floating gate transistors are formed such that each of the floating gate transistors in the array has a floating gate, a control gate and an inter-gate dielectric... Agent: Fletcher Yoder (micron Technology, Inc.)

20070296017 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory in which the area of each memory cell is small and which can perform high-speed operation with accuracy. A pair of honeycomb-like diffusion layers which are deviated from each other by a quarter-pitch are formed. Memory transistors (MemoryTr) and select transistors (SelectTr) are formed at portions... Agent: Arent Fox LLP

20070296016 - Semiconductor device and method of manufacturing the same: A semiconductor device including a semiconductor substrate; an element isolation region having a trench filled with an insulating film defined or the semiconductor substrate; a memory cell transistor formed in an element forming region isolated by the element isolating regions of the semiconductor substrate; and the memory cell transistor includes... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070296018 - Nonvolatile single-poly memory device: A non-volatile single-poly memory device is disclosed. The non-volatile single-poly memory device includes two mirror symmetric unit cells, which is capable of providing improved data correctness. Further, the non-volatile single-poly memory device is operated at low voltages and is fully compatible with logic processes.... Agent: North America Intellectual Property Corporation

20070296020 - Semiconductor device: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of... Agent: Miles & Stockbridge PC

20070296019 - Non-volatile electromechanical field effect devices and circuits using same and methods of forming same: Under one aspect, a field effect device includes a gate, a source, and a drain, with a conductive channel between the source and the drain; and a nanotube switch having a corresponding control terminal, said nanotube switch being positioned to control electrical conduction through said conductive channel. Under another aspect,... Agent: Wilmerhale/boston

20070296021 - Nonvolatile semiconductor memory with backing wirings and manufacturing method thereof: A manufacturing method of a nonvolatile semiconductor memory includes steps (a) to (d). The (a) is a step of laminating a 2nd insulating film, a gate film and a hard mask film which cover a 1st gate electrode of a 1st memory cell transistor formed on a 1st region of... Agent: Foley And Lardner LLP Suite 500

20070296022 - Flash memory process with high voltage ldmos embedded: A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A... Agent: Slater & Matsil, L.L.P.

20070296023 - Charge monitoring devices and methods for semiconductor manufacturing: A charge monitoring device is described for monitoring charging effect during semiconductor manufacturing. In a first aspect of the invention, a charge storage MOS memory structure comprises a substrate body, an oxide-nitride-oxide structure that overlays a top surface of the substrate and extends above the edges between a source region... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070296024 - Memory device and manufacturing method and operating method thereof: A memory device including a substrate, a plurality of conductive layers, a composite dielectric layer and a plurality of gates are provided. Wherein, the conductive layers are disposed on the substrate. The composite dielectric layer is disposed on the substrate and covers the conductive layers. The composite dielectric layer includes... Agent: J.c. Patents, Inc.

20070296025 - Random number generating device: A random number generating device includes a semiconductor device including a source region, a drain region, a channel region provided between the source region and the drain region, and an insulating portion provided on the channel region, the insulating portion including a trap insulating film having traps based on dangling... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070296026 - Sonos memory device: A SONOS memory device, and a method of manufacturing the same, includes a substrate and a multifunctional device formed on the substrate. The multifunctional device performs both switching and data storing functions. The multifunctional device includes first and second impurities areas, a channel formed between the first and second impurities... Agent: Lee & Morse, P.C.

20070296027 - Cmos devices comprising a continuous stressor layer with regions of opposite stresses, and methods of fabricating the same: The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having a continuous dielectric stressor layer containing regions of opposite stresses. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A continuous dielectric stressor... Agent: Scully Scott Murphy & Presser, PC

20070296028 - Vertical field-effect transistor and method of forming the same: A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes... Agent: Slater & Matsil, L.L.P.

20070296029 - Integratred circuit including a trench transistor having two control electrodes: An integrated circuit including a field effect controllable trench transistor having two-control electrodes is disclosed. One embodiment provides a trench having a first control electrode and a second control electrode. A first electrical line is provided in an edge structure for electrically contact-connecting second control electrode.... Agent: Dicke, Billig & Czaja

20070296030 - Semiconductor integrated circuit device having deposited layer for gate insulation: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070296031 - Semiconductor device and manufacture method thereof: The present invention provides a trench gate Tr having a first gate electrode and a second gate electrode in the inside of a groove. The first gate electrode is provided in a groove lower part defining a channel of the Tr with a gate oxide film interposed between the first... Agent: Foley And Lardner LLP Suite 500

20070296035 - Apparatus and method for semiconductor bonding: An apparatus for bonding semiconductor structures includes equipment for positioning a first surface of a first semiconductor structure directly opposite and in contact with a first surface of a second semiconductor structure and equipment for forming a bond interface area between the first surfaces of the first and second semiconductor... Agent: Akc Patents

20070296033 - Non-volatile memory device having four storage node films and methods of operating and manufacturing the same: A nonvolatile memory device that may operate in a multi-bit mode and a method of operating and manufacturing the nonvolatile memory device are provided. The nonvolatile memory device may include a first source region and a first drain region that are respectively in first fin portions on both sides of... Agent: Harness, Dickey & Pierce, P.L.C

20070296034 - Silicon-on-insulator (soi) memory device: A single-poly SOI memory cell includes a PMOS select transistor serially connected with a floating-gate PMOS transistor on an SOI substrate. The PMOS select transistor includes a select gate, a P+ source region and a P+ drain/source region. The floating-gate PMOS transistor includes a floating gate, a P+ drain region... Agent: North America Intellectual Property Corporation

20070296036 - Soi device with contact trenches formed during epitaxial growing: A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070296032 - Artificial dielectrics using nanostructures: Artificial dielectrics using nanostructures, such as nanowires, are disclosed. In embodiments, artificial dielectrics using other nanostructures, such as nanorods, nanotubes or nanoribbons and the like are disclosed. The artificial dielectric includes a dielectric material with a plurality of nanowires (or other nanostructures) embedded within the dielectric material. Very high dielectric... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070296038 - High performance stress-enhanced mosfets using si:c and sige epitaxial source/drain and method of manufacture: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of... Agent: Greenblum & Bernstein, P.L.C

20070296037 - Semiconductor device and manufacturing method of semiconductor device: The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection.... Agent: Eric Robinson

20070296039 - Semiconductor device structures incorporating voids and methods of fabricating such structures: Semiconductor device structures and fabrication methods for field effect transistors in which a gate electrode is provided with an air gap or void disposed adjacent to a sidewall of the gate electrode. The void may be bounded by a dielectric spacer proximate to the sidewall of the gate electrode and... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20070296040 - Semiconductor device, and life prediction circuit and life prediction method for semiconductor device: A life prediction wire 14 is connected to an emitter-wire bonding pad 2 of a semiconductor device 1. Wire deterioration is detected by checking whether or not an electric current flows from the life prediction wire 14 to the emitter-wire bonding pad 2. Thus, by directly checking a deterioration state... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070296041 - Semiconductor device and method of manufacturing the same: A semiconductor device including a semiconductor substrate, a memory cell transistor formed in a memory cell region of the semiconductor substrate; a transistor formed in a peripheral circuit region of the semiconductor substrate and having an LDD (Lightly Doped Drain) structure; and the memory cell transistor has a same film... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070296042 - Field-effect transistor structures with gate electrodes with a metal layer: Provided is an integrated circuit including a transistor with a gate electrode. The gate electrode includes a polysilicon layer in contact with a gate dielectric layer separating the gate electrode and a semiconductor substrate that comprises an active region of the transistor. The gate electrode includes sidewall structures extending along... Agent: Dicke, Billig & Czaja

20070296043 - Semiconductor device: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070296044 - Device having dual etch stop liner and reformed silicide layer and related methods: The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a silicide layer not exposed to the formation of the dual... Agent: Hoffman, Warnick & D'alessandro LLC

20070296045 - Semiconductor device and method for manufacturing the same: A semiconductor device is provided with a semiconductor substrate, a plurality of active regions separated from each other by element isolation regions formed on the semiconductor substrate; gate oxide films formed on the active regions; gate electrodes formed on the gate oxide films; side wall insulation films formed on side... Agent: Young & Thompson

20070296046 - Semiconductor device and method of manufacture thereof: In a high withstand voltage transistor of a LOCOS offset drain type having a buried layer, a plurality of stripe-shaped diffusion layers are formed below a diffusion layer ranging from an offset layer to a drain layer and a portion between the drain region and the buried layer is depleted... Agent: Steptoe & Johnson LLP

20070296047 - Thin film transistors with poly(arylene ether) polymers as gate dielectrics and passivation layers:

20070296048 - Double gate transistor, method of manufacturing same, and system containing same: A double gate transistor comprises a substrate (105, 905) and first and second electrically insulating layers (110, 910), (120, 920). The first and second electrically insulating layers form a fin (130, 930). A first gate dielectric (140,940) is at a first side (131, 931) of the fin and a second... Agent: Intel Corporation C/o Intellevate, LLC

20070296050 - Electro-optical device and electronic apparatus: An electro-optical device includes peripheral circuit wiring arranged in the peripheral area on the element substrate, and which has overlapping portions that overlap vertical conduction terminals on the element substrate in plan view. The overlapping portions are arranged on a lower layer side relative to the vertical conduction terminals.... Agent: Advantedge Law Group, LLC

20070296049 - Moveable barriers with obstruction detection: A system includes a photo beam detector. The photobeam detector senses a presence of an obstruction. The system also includes an apparatus to attach the photo beam detector to the moveable barrier. At least a portion of the photo beam detector is positioned at the moveable barrier such that a... Agent: Fitch Even Tabin And Flannery

20070296051 - Full frame ito pixel with improved optical symmetry: A charge-coupled device includes a photosensitive region for collecting charge in response to incident light; a first and third gate electrode made of a transmissive material spanning at least a portion of the photosensitive region; and a second gate electrode made of a transmissive material that is less transmissive than... Agent: Pamela R. Crocker Eastman Kodak Company

20070296052 - Methods of forming silicide regions and resulting mos devices: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on... Agent: Slater & Matsil, L.L.P.

20070296053 - Semiconductor device and method of forming the same: A method of forming a semiconductor device is provided. A device isolation region is formed in a semiconductor substrate, thereby defining a device region in the semiconductor substrate. The device region has a flat main surface. The flat main surface is deformed into a round surface, thereby forming a surface-rounded... Agent: Sughrue Mion, PLLC

20070296054 - Fuse with silicon nitride removed from fuse surface in cutting region: A fuse is formed by a borderless contact process that removes the silicon nitride layer above the cutting region of the fuse. The fuse is formed on a semiconductor substrate, and comprises an insulation layer such as an oxide layer formed on the substrate, a fuse layer formed on the... Agent: Fenwick & West LLP

20070296056 - Integrated circuits having controlled inductances: An electronic device has a semiconductor chip (101) with a surface and an electric circuit including terminals on the surface. The circuit has a first (103) and a second terminal (104) with a metallurgical composition for wire bonding. The chip has a conductive wire (120) above the chip surface, which... Agent: Texas Instruments Incorporated

20070296057 - Integrated low inductance interconnect for rf integrated circuits: An interconnect path configured for use in RFICs and configured to reduce inductance at the input of an array of cells, and also at the output of the array of cells. According to one preferred embodiment of the present invention, a multi-layered interconnect formed by at least two metal layers... Agent: Jackson Walker LLP

20070296055 - Rf integrated circuit with esd protection and esd protection apparatus thereof: A radio frequency (RF) integrated circuit with electrostatic discharge (ESD) protection and an ESD protection apparatus thereof are provided. The ESD protection apparatus includes a substrate, an RF bonding pad, and an ESD protection unit. The RF bonding pad for transmitting RF signal is disposed upon the substrate. The ESD... Agent: Jianq Chyun Intellectual Property Office

20070296058 - Semiconductor structure of a high side driver and method for manufacturing the same: A semiconductor structure of a high side driver and method for manufacturing the same is disclosed. The semiconductor of a high side driver includes an ion-doped junction and an isolation layer formed on the ion-doped junction. The ion-doped junction has a number of ion-doped deep wells, and the ion-doped deep... Agent: Bacon & Thomas, PLLC

20070296059 - Semiconductor device: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070296060 - Method for forming p-type semiconductor region, and semiconductor element: A substrate 103 is set in a film-forming apparatus, such as a metal organic vapor phase epitaxy system 101, and a GaN buffer film 105, an undoped GaN film 107, and a GaN film 109 containing a p-type dopant are successively grown on the substrate 103 to form an epitaxial... Agent: Fish & Richardson P.C.

20070296061 - Group iii-nitride crystal substrate and manufacturing method thereof, and group iii-nitride semiconductor device: A method of manufacturing a group III-nitride crystal substrate including the steps of introducing an alkali-metal-element-containing substance, a group III-element-containing substance and a nitrogen-element-containing substance into a reactor, forming a melt containing at least the alkali metal element, the group III-element and the nitrogen element in the reactor, and growing... Agent: Mcdermott Will & Emery LLP

20070296062 - Substrate strip and substrate structure and method for manufacturing the same: A substrate structure is disclosed. The substrate structure includes a core substrate, an interconnection portion and a solder mask. The core substrate includes a top surface and a bottom surface opposite the top surface. A circuit pattern is disposed on the top surface. The interconnection portion is disposed on the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070296063 - Spin coating apparatus and coating method of composition for antireflection layer: A spin coating apparatus includes a cleaning liquid ejection device that supplies a cleaning liquid primarily containing water to a surface of a lens base material, an antireflection-layer composition ejection device that supplies a composition for an antireflection layer to form an antireflection layer on the surface of the lens... Agent: Sughrue Mion, PLLC

20070296064 - Electronic structures utilizing etch resistant boron and phosphorus materials and methods to form same: A dense boron-based or phosphorus-based dielectric material is provided. Specifically, the present invention provides a dense boron-based dielectric material comprised of boron and at least one of carbon, nitrogen, and hydrogen or a dense phosphorus-based dielectric comprised of phosphorus and nitrogen. The present invention also provides electronic structures containing the... Agent: Scully Scott Murphy & Presser, PC

20070296065 - 3d electronic packaging structure having a conductive support substrate: The present invention provides a 3D electronic packaging unit having a conductive supporting substrate that can achieve multi-chip stacking through the signal contacts on the both sides of the unit. The packaging unit can be batched manufactured on wafers or substrates, and thus reduce the manufacturing cost of each individual... Agent: Bacon & Thomas, PLLC

20070296067 - Bga semiconductor package and method of fabricating the same: A semiconductor package and a method of fabricating the same are provided. The semiconductor package includes a semiconductor chip and a circuit board. The semiconductor chip has a bond pad. The circuit board has a base substrate with a throughole, and a conductive film pattern placed on a sidewall of... Agent: Marger Johnson & Mccollom, P.C.

20070296066 - Electrical connector with elongated ground contacts: In an electrical connector, cross talk between signal contacts in adjacent linear columns and rows may be reduced by changing the size of the lead portions of the contacts extending within a leadframe housing. For example, the height of the ground contact lead portions may be increased to further isolate... Agent: Woodcock Washburn, LLP

20070296068 - In-situ monitoring and method to determine accumulated printed wiring board thermal and/or vibration stress fatigue using a mirrored monitor chip and continuity circuit: A monitoring system includes a monitor chip or chips soldered to a printed wiring board. By mirroring a function IC chip interface with the monitor chip, the consumed and remaining thermal/and or vibration-fatigue life of the function IC chip based on the life-environment actually experienced through monitoring of the monitor... Agent: Carlson, Gaskey & Olds, P.C.

20070296069 - Semiconductor apparatus with decoupling capacitor: A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair... Agent: Rabin & Berdo, PC

20070296070 - Semiconductor package having functional and auxiliary leads, and process for fabricating it: A semiconductor package and a process for fabricating such a package are presented. The package has a substantially parallelepipedal block, made of an encapsulation material. Embedded within the block is at least one integrated-circuit chip and a leadframe having functional leads for electrical connection to said chip. These functional leads... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20070296072 - Compliant integrated circuit package substrate: An integrated circuit package may include a plurality of interconnects, and an integrated package substrate coupled to the plurality of interconnects and comprising an integrated circuit package substrate core. A first surface of the integrated circuit package substrate core may define a depression.... Agent: Buckley, Maschoff & Talwalkar LLC Attorneys For Intel Corporation

20070296071 - Microelectronic package including temperature sensor connected to the package substrate and method of forming same: A microelectronic package, a method of forming the package and a system incorporating the package. The package includes a substrate; a die bonded to the substrate; and a thermal sensor connected to the substrate.... Agent: Intel Corporation C/o Intellevate, LLC

20070296073 - Three dimensional integrated circuit and method of making the same: A three dimensional integrated circuit structure includes at least first and second devices, each device comprising a substrate and a device layer formed over the substrate, the first and second devices being bonded together in a stack, wherein the bond between the first and second devices comprises a metal-to-metal bond... Agent: Duane Morris LLPIPDepartment (tsmc)

20070296074 - Embedded metal heat sink for semiconductor device and method for manufacturing the same: An embedded metal heat sink for a semiconductor device and a method for manufacturing the same are described. The embedded metal heat sink for a semiconductor device comprises a metal thin layer, a metal heat sink and two bonding pads. The metal thin layer including a first surface and a... Agent: Lowe Hauptman Ham & Berner, LLP

20070296075 - Package using selectively anodized metal and manufacturing method thereof: A package using selectively anodized metal and a manufacturing method thereof are provided. The method includes a patterning step, an anodized metal film forming step, a via hole forming step, and a bump forming step. The pattering step is performed by attaching a masking material to a surface of a... Agent: Gwips Peter T. Kwon

20070296076 - Semiconductor device and apparatus and method for manufacturing the same: The present invention provides a semiconductor device including: a semiconductor chip mounted on a substrate; a heat spreader provided above the semiconductor chip; and a sealing resin interposed between the semiconductor chip and the heat spreader and covering the semiconductor chip. The heat spreader is not in contact with any... Agent: Young & Thompson

20070296077 - Semiconductor component and method of manufacture: In various embodiments, semiconductor components and methods to manufacture semiconductor components are disclosed. In one embodiment, a method to manufacture semiconductor components includes attaching multiple heat spreaders to a semiconductor wafer. Other embodiments are described and claimed.... Agent: Hvvi Semiconductors, Inc.

20070296079 - Heat dissipating structure and method for fabricating the same: A heat sink package structure and a method for fabricating the same are disclosed. The method includes mounting and electrically connecting a semiconductor chip to a chip carrier, forming an interface layer or a second heat dissipating element having the interface layer on the semiconductor chip and installing a first... Agent: Edwards Angell Palmer & Dodge LLP

20070296078 - Semiconductor module having low thermal load: At least one bearing body in a power semiconductor module has a surface section on which a first semiconductor component and at least one additional semiconductor component are arranged adjacent to each other. The semiconductor components have contact surfaces, oriented away from the surface section of the bearing body, that... Agent: Staas & Halsey LLP

20070296080 - Semiconductor devices and method of manufacturing them: A semiconductor device is provided with a silicon substrate, with a surface for soldering the silicon substrate to a ceramic substrate, and an electrode making contact with the surface of the silicon substrate. The electrode comprises a first conductor layer, a second conductor layer, and a third conductor layer. The... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070296082 - Semiconductor device having conductive adhesive layer and method of fabricating the same: In a semiconductor device, a semiconductor substrate may include a plurality of first conductive pads. An insulating isolation layer may be on the semiconductor substrate so as to separate the first conductive pads. A package substrate may include a plurality of second conductive pads. A conductive adhesive layer may connect... Agent: Harness, Dickey & Pierce, P.L.C

20070296081 - Semiconductor package and method of manufacturing the same: Disclosed is a semiconductor package and a method of manufacturing the same. The semiconductor package includes a semiconductor chip that includes metal pads provided on a predetermined area of an upper side of a semiconductor substrate, where element structures used to manufacture a semiconductor element are formed, and bump electrodes... Agent: HorizonIPPte Ltd

20070296083 - Low dielectric constant integrated circuit insulators and methods: A system for low dielectric constant insulators is provided. One aspect of this disclosure relates to a method for forming an insulator. According to an embodiment of the method, a first structural material is applied as one or more layers of insulation to an integrated circuit surface, a damascene pattern... Agent: Schwegman, Lundberg & Woessner, P.A.

20070296084 - Small grain size, conformal aluminum interconnects and method for their formation: A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mixed grain... Agent: Schwegman, Lundberg & Woessner, P.A.

20070296085 - Mim capacitor and method of making same: A MIM capacitor device and method of making the device. The device includes an upper plate comprising one or more electrically conductive layers, the upper plate having a top surface, a bottom surface and sidewalls; a spreader plate comprising one or more electrically conductive layers, the spreader plate having a... Agent: Schmeiser, Olsen & Watts

20070296086 - Integrated circuit package system with offset stack: An integrated circuit package system is provided including mounting a first integrated circuit device over a carrier, mounting a second integrated circuit device having an adhesive spacer over the first integrated circuit device in an offset configuration, connecting a first internal interconnect between the carrier and the first integrated circuit... Agent: Ishimaru & Zahrt LLP

20070296087 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device includes a first semiconductor chip face-down mounted on a substrate, a second semiconductor chip face-up mounted on the first semiconductor chip, and an electromagnetic shielding plate interposed between the first semiconductor chip and the second semiconductor chip.... Agent: Harness, Dickey & Pierce, P.L.C

20070296088 - Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument: A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of the electrodes; a conductive foil provided at a given spacing from the surface on which the passivation film is... Agent: Oliff & Berridge, PLC

20070296089 - Use of a die-attach composition for high power semiconductors, method for attaching same to a printed circuit board and semiconductor device manufactured thereby: The Directive 2002/95/EC of the European Parliament and of the Council promulgated that from 1 Jul. 2006 new electrical and electronic equipment must no longer contain lead. Accordingly, lead-free solder alloys for various electrical and electronic applications have been developed. But at present, lead in high melting temperature type solders,... Agent: Kalow & Springut LLP

20070296090 - Die package and probe card structures and fabrication methods: A semiconductor die has conductors encapsulated in a dielectric material disposed on the active surface extending across the active surface from bond pads to one or more peripheral edges where the conductor ends are disposed at a side surface of the dielectric material. Stacks of such semiconductor dice, wherein one... Agent: Trask Britt, P.C./ Micron Technology

20070296091 - Semiconductor device having symbol pattern utilized as indentification sign and its manufacture method: A plurality of device patterns constituting part of an electronic circuit are formed over the surface of a substrate. A symbol pattern to be used for an identification sign is formed in the same layer as the device patterns. A width of the device pattern is within a pattern width... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070296092 - Pixel circuit: A pixel circuit includes a LED, first switch, second switch, first transistor, second transistor and capacitor. The LED has a first end receiving a first supply voltage. The first switch has a first terminal receiving a data signal and a control terminal receiving a scan signal. The second switch has... Agent: Rabin & Berdo, PC

20070290185 - Phase change memory cells and methods for fabricating the same: Phase change memory cells and methods for fabricating the same are provided. In an exemplary embodiment, a phase change memory cell comprises a first electrode disposed over a substrate along a first direction. A first dielectric layer is formed over the first electrode. A conductive contact is formed in the... Agent: Quintero Law Office, PC

20070290187 - Repair structure and active device array substrate: A repair structure including a substrate, at least one first conducting line, a first insulating layer, at least one second conducting line and a repair connecting layer is provided. The at least one first conducting line is disposed on the substrate. The first insulating layer is disposed over the substrate... Agent: Jianq Chyun Intellectual Property Office

20070290189 - Light emitting device and method of manufacturing the same: The invention discloses a light emitting device including a substrate, a first metal layer, and an infrared light emitter. The substrate has a first surface, and the first metal layer is formed on the first surface of the substrate. The infrared light emitter is formed on the first metal layer... Agent: Birch Stewart Kolasch & Birch

20070290188 - Semiconductor light emitting device substrate and method of fabricating the same: A substrate for semiconductor light emitting devices is provided. The substrate is characterized in that the substrate is a single crystal material and has a nanocrystal structure capable of diffracting an electromagnetic wave. The nanocrystal structure is disposed on a surface portion of the substrate and includes an etched region... Agent: Jianq Chyun Intellectual Property Office

20070290191 - Resonant cavity optoelectronic device with suppressed parasitic modes: In other embodiments a double periodicity is selected to ensure a high reflectivity of light in a direction tilted with respect to the vertical direction. An optoelectronic device having a multilayer interference reflector with two periodicities can operate as a light-emitting diode, a superluminescence light-emitting diode, a laser diode, a... Agent: Vitaly Shchukin

20070290192 - Method to prevent defects on sram cells that incorporate selective epitaxial regions: An SRAM device and method of forming MOS transistors of the device having reduced defects associated with selective epitaxial growth in moat tip regions is discussed. The SRAM device comprises a core region and a logic region, logic transistors within the logic region of the SRAM, and selective epitaxial regions... Agent: Texas Instruments Incorporated

20070290202 - Organosilicon compound: wherein, R1 represents a hydrogen atom, or an unsubstituted or substituted monovalent hydrocarbon group, R2 to R4 represent identical or different unsubstituted or substituted monovalent hydrocarbon groups, each R5 represents, independently, a hydrogen atom, or an unsubstituted or substituted monovalent hydrocarbon group, each R6 represents, independently, an identical or different... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070290204 - Semiconductor structure and method for manufacturing thereof: The invention is directed to a semiconductor structure located on a substrate in a scribe line region of a wafer. The semiconductor structure comprises a first dielectric layer, a first test pad and a passivation layer. The first dielectric layer is disposed on the substrate and the first test pad... Agent: Jianq Chyun Intellectual Property Office

20070290205 - Dual-channel thin film transistor: A dual-channel thin film transistor is applied to a thin film transistor liquid crystal display. It includes a substrate, a gate electrode, a source, and a drain. The drain further includes two drain electrodes. The two drain electrodes form the dual-channel with the source. A channel layer is between the... Agent: North America Intellectual Property Corporation

20070290206 - Thin film transistor and organic electro-luminescence display device using the same: A thin film transistor includes a semiconductor pattern on a substrate, a gate insulating film to cover the semiconductor pattern, a gate electrode partially overlapping the semiconductor pattern with the gate insulating film therebetween, a hole in the gate electrode to expose the gate insulating film, an interlayer insulating film... Agent: Seyfarth Shaw, LLP

20070290212 - Silicon carbide and related wide-bandgap transistors on semi insulating epitaxy: A method of making a semi-insulating epitaxial layer includes implanting a substrate or a first epitaxial layer formed on the substrate with boron ions to form a boron implanted region on a surface of the substrate or on a surface of the first epitaxial layer, and growing a second epitaxial... Agent: Dla Piper US LLP Attn: Patent Group

20070290214 - Light emitting diode structure: A LED (Light Emitting Diode) structure with a contact layer of a multiple structure includes a nucleation layer disposed on a substrate; a conductive buffer layer disposed on the nucleation layer; an active layer disposed between an upper and a lower confinement layer, wherein the structure of active layer includes... Agent: Rosenberg, Klein & Lee

20070290213 - Light-emitting device, image forming apparatus, display device, and electronic apparatus: A light-emitting device includes: a substrate; a light reflection layer that is formed on the substrate and reflects light; a first electrode that is formed on the light reflection layer and transmits light; a light-emitting layer that is formed on the first electrode and emits light; a second electrode that... Agent: Oliff & Berridge, PLC

20070290215 - Light-emitting semiconductor device protected against reflector metal migration, and method of fabrication: An LED has a light-generating semiconductor region formed on a baseplate via a metal-made reflector layer. The light-generating semiconductor region has an active layer sandwiched between a pair of claddings of opposite conductivity types. An annular marginal space is left around the reflector layer between the light-generating semiconductor region and... Agent: Woodcock Washburn LLP

20070290216 - Semiconductor light emitting element, manufacturing method therefor, and compound semiconductor light emitting diode: A semiconductor light emitting element is provided with a transparent substrate for improving the optical extraction efficiency by using a transparent substrate. The semiconductor light emitting element includes a main body constructed of an n-Al0.6Ga0.4As current diffusion layer, an n-Al0.5In0.5P cladding layer, an AlGaInP active layer, a p-Al0.5In0.5P cladding layer,... Agent: Morrison & Foerster LLP

20070290217 - Solid state light sheet and bare die semiconductor circuits with series connected bare die circuit elements: An electronically active sheet includes a bottom substrate having a bottom electrically conductive surface. A top substrate having a top electrically conductive surface is disposed facing the bottom electrically conductive surface. An electrical insulator separates the bottom electrically conductive surface from the top electrically conductive surface. At least one bare... Agent: Michaud-duffy Group LLP

20070290221 - Light emitting diode and manufacturing method of the same: A light emitting diode includes a permanent substrate having a first portion and a second portion, and a chip attached on the first portion of the permanent substrate by a chip bonding technology. The chip includes at least one first electrode and a light emitting region. The manufacturing method comprises... Agent: Wpat, PC

20070290220 - Package for a light emitting diode and a process for fabricating the same: A package for an LED, comprises a metal substrate, at least one LED chip, and an insulative housing, wherein the metal substrate has a first terminal and a second terminal, and the first terminal is formed with a recess. The at least one LED chip is arranged in the recess... Agent: Rosenberg, Klein & Lee

20070290222 - Semiconductor light emitting device and method of fabricating the same: The present invention provides a flip chip semiconductor light-emitting device which includes a substrate and a semiconductor multi-layer structure. The semiconductor multi-layer structure has a first surface and a second surface in opposition to the first surface. The semiconductor multi-layer structure is bonded to the substrate by the first surface.... Agent: Birch Stewart Kolasch & Birch

20070290184 - Method for programming a multilevel phase change memory device: A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at... Agent: Martine Penilla & Gencarella, LLP

20070290186 - Non-volatile variable resistance memory device and method of fabricating the same: A non-volatile variable resistance memory device and a method of fabricating the same are provided. The non-volatile variable resistance memory device may include a lower electrode, a buffer layer on the lower electrode, an oxide layer on the buffer layer and an upper electrode on the oxide layer. The buffer... Agent: Harness, Dickey & Pierce, P.L.C

20070290190 - Adapted led device with re-emitting semiconductor construction: An article includes an LED that has an emitting surface. A reemitting semiconductor structure has an emitting surface and converts light emitted by the LED to light of a different wavelength. At least one of the emitting surfaces frustrates total internal reflection.... Agent: 3m Innovative Properties Company

20070290193 - Field effect transistor devices and methods: A field-effect transistor device is provided, including: a substrate; a vertically stacked layered semiconductor structure on the substrate including the following layers: a first quantum well layer having laterally spaced-apart drain and source regions that are each delta-doped with a dopant of a first conductivity type, the drain and source... Agent: Martin Novack

20070290201 - Encapsulation for organic device: The present invention concerns a thin-film encapsulation structure for electronic devices with organic substances, especially OLEDs or other organic optoelectronic devices as well as corresponding components and a process for the production with a primary, inorganic barrier layer (5), which is directly arranged on the device or the surface to... Agent: Townsend And Townsend And Crew, LLP

20070290195 - Increased open-circuit-voltage organic photosensitive devices: A photosensitive device includes a first organic material and a second organic material forming a donor-acceptor heterojunction electrically connected between an anode and a cathode, where the first organic material and second organic material each have a Franck-Condon Shift of less than 0.5 eV. Preferably, one or both of the... Agent: Kenyon & Kenyon LLP

20070290194 - Method for cross-linking an organic semi-conductor: The present invention describes a novel method for crosslinking organic semiconductors and conductors by initiating this crosslinking in an autophotosensitised manner. It furthermore describes the production of organic electronic devices through the use of this crosslinking method. The properties of the electronic devices are thereby improved.... Agent: Connolly Bove Lodge & Hutz, LLP

20070290199 - Multi-functional copolymers comprising rare earth metal complexes and devices thereof: wherein [Ax-[B(C)]y-Dz] denotes a single unit of the copolymer complex that is repeated n times, wherein n is an integer greater than one, and wherein the single unit comprises a conjugated backbone coordinated to a complex (C) comprising rare earth metal(s); x, y and z are numbers greater than zero... Agent: James Remenick Novak Druce & Quigg, LLP

20070290196 - Organic light emitting display device and method for manufacturing the organic light emitting display device: An organic light emitting display device has thin film transistors. An organic thin film transistor (OTFT) is manufactured in one substrate and an organic light emitting diode (OLED) is manufactured on the other substrate, and the first substrate and second substrate are then positioned to face each other. The first... Agent: H.c. Park & Associates, PLC

20070290198 - P-alkoxyphenylen-thiophene oligomers as organic semiconductors for use in electronic devices: This invention provides phenylene-thiophene compounds that exhibit useful electronic properties such as high mobility and high on/off ratio. The invention also provides electronic devices incorporating these compounds. These devices include field effect transistors (FETs), thin film transistors (TFTs), display devices, light-emitting diodes, photovoltaic cells, photo-detectors, and memory cells. Further, the... Agent: E I Dupot De Nemours And Company Legal Patent Records Center

20070290197 - Photoactive nanocomposite and method for the production thereof: The invention concerns a photoactive nanocomposite (3) comprising at least one donor-acceptor couple of semiconductor elements. One of the elements is made of doped nanowires (7) with sp3 structure, and the other of the elements is an organic compound (8). The elements are supported by a device substrate (1). The... Agent: Young & Thompson

20070290200 - Thin film semiconductor device, method of manufacturing the same and display: A method of manufacturing a thin film semiconductor device is disclosed. The method includes the steps of: forming a light reflection and absorption layer for reflecting and absorbing light on a substrate; patterning the light reflection and absorption layer in a prescribed shape; forming an insulating film covering the patterned... Agent: Sonnenschein Nath & Rosenthal LLP

20070290203 - Semiconductor element and method of manufacturing the same: In one aspect, a semiconductor element may include a first substrate made of a N-type ZnO substrate, a P-type semiconductor layer provided on the first substrate, the P-type semiconductor layer having a nitride-based semiconductor, a lamination member provided on the P-type semiconductor layer, lamination member having a nitride-based semiconductor, and... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20070290208 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a substrate having a first area and a second area adjacent to the first area, a first silicon layer provided on the substrate in the first area, a relaxed layer which is provided on the substrate in the second area and which has a lattice constant... Agent: Foley And Lardner LLP Suite 500

20070290207 - Semiconductor device and method for manufacturing semiconductor device: In a semiconductor device including a digital circuit portion and an analog circuit portion having a capacitor portion provided over a substrate, the capacitor portion is provided with a first wiring, a second wiring and a plurality of blocks each having a plurality of capacitor elements. Further, each the plurality... Agent: Eric Robinson

20070290209 - Display device: A display including a driving substrate is provided. Arrayed on the driving substrate is a plurality of pixel electrodes and thin film transistors for driving the pixel electrodes. Each thin film transistor includes a semiconductor thin film having an active region made to be polycrystalline by irradiation with an energy... Agent: Bell, Boyd & Lloyd, LLP

20070290210 - Semiconductor device and method of fabricating a ltps film: A semiconductor device and a method of fabricating a low-temperature polysilicon film are provided. An amorphous silicon film is formed over a substrate. An insulating layer and a laser absorption layer are formed over the amorphous silicon film. A photolithographic and etching process is performed to remove portions of the... Agent: North America Intellectual Property Corporation

20070290211 - Bipolar semiconductor device and process for producing the same: A process for manufacturing a bipolar type semiconductor device in which at least a part of a region where an electron and a hole are recombined during current flowing is formed with a silicon carbide epitaxial layer that has been grown from the surface of a silicon carbide substrate, is... Agent: The Webb Law Firm, P.C.

20070290219 - Light emitting device and method of manufacturing the same: A high-quality light emitting device is provided which has a long-lasting light emitting element free from the problems of conventional ones because of a structure that allows less degradation, and a method of manufacturing the light emitting device is provided. After a bank is formed, an exposed anode surface is... Agent: Nixon Peabody, LLP

20070290218 - Packaged light emitting devices: Packaged semiconductor light emitting device are provided including a reflector having a lower sidewall portion defining a reflective cavity. A light emitting device is positioned in the reflective cavity. A first quantity of cured encapsulant material having a first index of refraction is provided in the reflective cavity including the... Agent: Myers Bigel Sibley & Sajovec, P.A.

20070290224 - Method of manufacturing nitride semiconductor light-emitting element and nitride semiconductor light-emitting element: There are provided a method of manufacturing a nitride semiconductor light-emitting element in which a nitride semiconductor layer of a first conductivity type, an active layer, and a nitride semiconductor layer of a second conductivity type are stacked in this order, including the steps of forming unevenness at a surface... Agent: Morrison & Foerster LLP

20070290225 - Method of manufacturing a vertically-structured gan-based light emitting diode: The present invention relates to a method of manufacturing a vertically-structured GaN-based light emitting diode. The method of manufacturing a vertically-structured GaN-based light emitting diode includes forming a GaN layer on a substrate; patterning the compound layer in a predetermined shape; forming an n-type GaN layer on the patterned compound... Agent: Mcdermott Will & Emery LLP

20070290223 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device includes an insulating film formed on a semiconductor substrate, a fin-shaped semiconductor layer formed on the insulating film, and having first and second side surfaces opposing each other, a gate electrode formed across the first side surface and second side surface of the semiconductor layer, a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070290226 - Method for producing a semiconductor arrangement, semiconductor arrangement and its application: A semiconductor arrangement for an integrated circuit is provided that includes a first region in which a number of components are formed, a second region, a buried insulating layer for vertically insulating the first region, an insulating structure, which is formed between the first region and the second region for... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20070290227 - Dual-gate transistor and pixel structure using the same: A dual-gate transistor includes a first gate formed on a substrate, a first dielectric layer covering the first gate and the substrate, a semiconductor layer formed on the first dielectric layer, first and second electrodes formed on the semiconductor layer and spaced with an interval in order to separate each... Agent: Birch Stewart Kolasch & Birch

20070290228 - Nitride semiconductor free-standing substrate: A nitride semiconductor free-standing substrate formed of a free-standing nitride-based compound semiconductor crystal that has a variation in lattice constant of ±12 ppm or less.... Agent: Foley And Lardner LLP Suite 500

20070290229 - Array substrate for liquid crystal display device and method of fabricating the same: An array substrate for a liquid crystal display device includes a first source electrode and a first drain electrode on a substrate, wherein the first source electrode and the first drain electrode are separated from each other and formed of a metallic material, a second source electrode and a second... Agent: Seyfarth Shaw, LLP

20070290230 - Nitride semiconductor device and production method thereof: A nitride semiconductor device according to the present invention includes a p-type nitride semiconductor layer, an n-type nitride semiconductor layer, and an active layer interposed between the p-type nitride semiconductor layer and the n-type nitride semiconductor layer. The p-type nitride semiconductor layer includes: a first p-type nitride semiconductor layer containing... Agent: Mark D. Saralino (mei) Renner, Otto, Boisselle & Sklar, LLP

20070290231 - Method of manufacturing a bipolar transistor and bipolar transistor thereof: A bipolar transistor (100) is manufactured using the following processes: (a) forming a base electrode layer (129) as a portion of a base electrode over a semiconductor substrate (110); (b) forming a first portion of an emitter electrode (154) over the base electrode layer; (c) forming a mask layer (280)... Agent: Walter P. Opaska Bryan Cave LLP

20070290232 - Semiconductor device and a manufacturing method thereof: A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070290233 - Reprogrammable fuse structure and method: A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed... Agent: Paul D. Greeley Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20070290234 - High switching speed two mask schottky diode with high field breakdown: A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device includes a LOCOS structure grown on the bottom of the trenches by using nitride spacer on the sidewall of the trenches as a thermal oxidation mask. A polycrystalline silicon layer is then filled... Agent: Birch Stewart Kolasch & Birch

20070290235 - Electric component: An electric component comprising a sensor and/or actuator chip with a substrate on which a passivating layer and a sensor and/or actuator structure consisting of an active surface area is arranged. The chip is surrounded by an encapsulation having an opening which forms an access to the at least one... Agent: The Webb Law Firm, P.C.

20070290236 - Semiconductor device and method of fabricating the same: A semiconductor device and a method of fabricating the semiconductor device are described. There is provided the semiconductor device including, a semi-conductor substrate, a gate insulating layer on the semiconductor substrate, a two-step gate electrode formed on the gate insulating layer, the two-step gate electrode having a first gate electrode... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070290237 - Insulated gate bipolar transistor and method for manufacturing same: An insulated gate bipolar transistor has a p-type emitter layer; an n-type buffer layer provided on the p-type emitter layer; an n-type base layer provided on the n-type buffer layer and having a higher resistivity than the n-type buffer layer; a p-type base layer provided in part of an upper... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070290238 - Field effect transistor and solid state image pickup device: A solid-state image pickup device improves the linearity of signal S1 and increases the saturation level in a solid-state image pickup device with an expanded dynamic range, and a field effect transistor used in the solid-state image pickup device. For the field effect transistor, gate electrode 60 is formed via... Agent: Texas Instruments Incorporated

20070290239 - Method of fabricating semiconductor device: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070290240 - Semiconductor device and method of manufacturing the semiconductor device: A semiconductor device comprises: an MOS transistor including: a semiconductor substrate; a source region, formed in the semiconductor substrate, that comprises an impurity of a first conductive type; a drain region, formed in the semiconductor substrate, that comprises an impurity of the first conductive type; and a gate electrode, formed... Agent: Birch Stewart Kolasch & Birch

20070290241 - Solid state image pickup device and manufacturing method thereof: A solid-state image pickup device that can suppress the dark current with respect to the photo-electrons overflowing from the photodiode, as well as its manufacturing method. Each pixel has the following parts: photodiode, transfer transistor, floating diffusion, accumulating capacitive element, and accumulating transistor. At least one of said source/drain regions... Agent: Texas Instruments Incorporated

20070290242 - Solid-state imaging device having transmission gates which pass over part of photo diodes when seen from the thickness direction of the semiconductor substrate: A solid-imaging device having a plurality of image pixels arranged along a main surface of a semiconductor substrate, wherein each of the plurality of image pixels includes a photodiode that converts incident light into an electric charge and a transmission gate that is formed so as to have a crossing... Agent: Mcdermott Will & Emery LLP

20070290243 - Ultrashallow photodiode using indium: The invention provides an imager having a p-n-p photodiode with an ultrashallow junction depth. A p+ junction layer of the photodiode is doped with indium to decrease transient enhanced diffusion effects, minimize fixed pattern noise and fill factor loss.... Agent: Dickstein Shapiro LLP

20070290246 - Image sensor and image sensor integrated type active matrix type display device: To fabricate an active matrix type display device integrated with an image sensor at a low cost and without complicating process, an image sensor laminated with TFT and a light receiving unit is formed on a light receiving matrix, a display matrix is arranged with TFT and pixel electrodes on... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070290244 - Method for processing a scratched surface, particularly a glass plate of a semiconductor wafer: A method for processing a scratched surface of a material that is transparent to electromagnetic radiation includes a step of depositing onto the scratched surface at least one layer of a polymer material having substantially the same optical index as the material having the scratched surface, so as to fill... Agent: Seed Intellectual Property Law Group PLLC

20070290245 - Solid-state imaging device: A pixel area, which is composed of a plurality of unit pixels each including a photoelectric conversion unit and a signal scanning circuit, is formed on a semiconductor substrate. An optical black pixel region, in which a plurality of optical black pixels for setting a dark-time level are formed, is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070290247 - Method of forming gate insulating film, semiconductor device and computer recording medium: In the present invention, when a gate insulation film in a DRAM is formed, an oxide film constituting a base of the gate insulation film is plasma-nitrided. The plasma nitridation is performed with microwave plasma generated by using a plane antenna having a large number of through holes. Nitrogen concentration... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070290248 - Manufacturing method for an integrated semiconductor structure and corresponding semiconductor structure: The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding semiconductor structure. The method comprises the steps of: providing a semiconductor substrate having a plurality of trench capacitors which are arranged in rows and columns in a checkerboard layout; forming connection straps for electrically connecting... Agent: Eschweiler & Associates LLC

20070290249 - Integrated circuit including a memory cell array: An integrated circuit includes a memory cell array comprising memory cells with a transistor. The transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction.... Agent: Edell, Shapiro & Finnan, LLC

20070290250 - Multiple dielectric finfet structure and method: Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics... Agent: Frederick W. Gibb, Iii Mcginn & Gibb, PLLC

20070290251 - A nand memory device with inversion bit lines and methods for making the same: A NAND based memory device uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities in smaller packaging. In another aspect, a method for fabricating a NAND based memory device that uses... Agent: Baker & Mckenzie LLP Patent Department

20070290254 - Exposure system, semiconductor device, and method for fabricating the semiconductor device: In order to link a defect inspection process before forming contact holes with an exposure process for forming the contact holes, a position (physical coordinates) of a defect on a wafer is stored, the defect having been detected in the defect inspection process before forming the contact holes, an exposure... Agent: Paul J. Winters

20070290253 - Nonvolatile semiconductor memory device and manufacturing method thereof: A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070290252 - Programmable memory device, integrated circuit including the programmable memory device, and method of fabricating same: An integrated circuit comprises a memory device including an isolation layer for defining an active area of a substrate, a tunnel oxide layer formed on the active area, a floating gate formed over the active area and the isolation layer, an inter-gate dielectric layer formed on the floating gate, and... Agent: F. Chau & Associates, LLC

20070290255 - Source lines for nand memory devices: A NAND memory device has a source line connected to two or more columns of serially-connected floating-gate transistors. The source line includes a first conductive layer formed on a substrate and coupled to source select gates associated with the two or more columns of serially-connected floating-gate transistors. The source line... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20070290256 - A 2-bit assisted charge memory device and method for making the same: An Assisted Charge (AC) Memory cell comprises a transistor that includes, for example, a p-type substrate with an n+ source region and an n+ drain region implanted on the p-type substrate. A gate electrode can be formed over the substrate and portions of the source and drain regions. The gate... Agent: Baker & Mckenzie LLP Patent Department

20070290258 - Field effect transistors including source/drain regions extending beneath pillars: Field effect transistors include a substrate and a pillar that extends away from the substrate. The pillar includes a base adjacent the substrate, a top remote from the substrate, and a sidewall that extends between the base and the top. An insulated gate is provided on the sidewall. A first... Agent: Myers Bigel Sibley & Sajovec

20070290259 - Method for manufacturing a semiconductor device including an impurity-doped silicon film: A process for manufacturing a semiconductor device consecutively includes forming a recess in the surface region of a silicon substrate, forming a gate insulation film on the surface of the recess, depositing a silicon electrode film including an oxygen-mixed layer extending parallel to the surface of the recess, injecting impurities... Agent: Scully Scott Murphy & Presser, PC

20070290257 - Structure and method for forming a shielded gate trench fet with the shield and gate electrodes being connected together: A field effect transistor (FET) includes a plurality of trenches extending into a semiconductor region. Each trench includes a gate electrode and a shield electrode with an inter-electrode dielectric therebetween, wherein the shield electrode and the gate electrode are electrically connected together.... Agent: Townsend And Townsend And Crew, LLP

20070290260 - Trench type mosfet and method of fabricating the same: A Trench MOSFET of an embodiment of the present invention includes: a semiconductor substrate including a substrate, an epitaxial layer, a body region, and a highly doped source region. The substrate, the epitaxial layer, the body region, and the highly doped source region are adjacently formed in this order. A... Agent: Harness, Dickey & Pierce, P.L.C

20070290261 - Self-driven ldmos transistor: The present invention provides a self-driven LDMOS, which utilizes a parasitic resistor between a drain terminal and an auxiliary region. The parasitic resistor is formed between two depletion boundaries in a quasi-linked deep N-type well. When the two depletion boundaries pinch off, a gate-voltage potential at a gate terminal will... Agent: Jianq Chyun Intellectual Property Office

20070290262 - High voltage ldmos: A semiconductor device, such as a LDMOS device, comprising: a semiconductor substrate; a drain region in the semiconductor substrate; a source region in the semiconductor substrate laterally spaced from the drain region; and a drift region in the semiconductor substrate between the drain region and the source region. A gate... Agent: Hiscock & Barclay, LLP

20070290263 - Semiconductor device and method for manufacturing the same: It is made possible to obtain epitaxially grown layers with excellent crystallinity. A semiconductor device includes: a semiconductor layer having crystallinity; a first insulating film formed on the semiconductor layer and having a first opening to reach the semiconductor layer; a first epitaxially grown layer formed on the first insulating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070290264 - Semiconductor device and a method of manufacturing the same: The invention aims at increasing an effect of a strain applying technique for enhancing transistor performance in a fully depleted silicon-on-insulator (FDSOI) type transistor having a thin buried oxide (BOX) film. In an FDSOI type transistor having a very thin SOI structure (6), a stress generating region is formed on... Agent: Miles & Stockbridge PC

20070290265 - Method of fabricating heterojunction photodiodes with cmos: An epitaxial device module monolithically integrated with a CMOS structure in a bulk or thick-film SOI substrate, comprising an active area on which epitaxial layers are formed by selective or non-selective epitaxial growth and a separate active area in which the CMOS structure is formed. A hard mask for epitaxy... Agent: Sturm & Fix LLP

20070290266 - Turn-on-efficient bipolar structures for on-chip esd protection: A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the... Agent: Berkeley Law & Technology Group, LLP

20070290268 - Method of fabricating semiconductor device: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070290267 - Semiconductor device and method of manufacturing the same: A semiconductor device is disclosed which improves the breakdown voltage of a planar-type junction edge terminating structure. The device includes an n-type semiconductor substrate layer common to an active section and an edge terminating section. An n-type drift region is formed selectively on the n-type semiconductor substrate layer in the... Agent: Rossi, Kimms & Mcdowell LLP.

20070290269 - Device with gates configured in loop structures: A device includes a substrate, a first gate, a second gate, and a third gate. The substrate has a first active region and a second active region. The first gate is configured in a first loop structure around the first active region. The second gate is configured in a second... Agent: Hewlett-packard Company Intellectual Property Administration

20070290270 - Performance and area scalable cell architecture technology: An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at... Agent: Texas Instruments Incorporated

20070290271 - Semiconductor device and method of manufacturing the same: A resist layer is formed so that the silicon nitride film and filling insulating film in region A may be covered. Then, in order to adjust the height position of the upper surface of a filling insulating film, a plasma etch back or fluoric acid is performed. Thereby, the filling... Agent: Mcdermott Will & Emery LLP

20070290272 - Integrated thin-film resistor with direct contact: A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness... Agent: Intellectual Property Law IBM Corporation

20070290273 - Operating method of non-volatile memory device: An operating method of non-volatile memory device is provided. The device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the substrate and separated by a channel region. The stack layer includes an insulating layer disposed on the channel... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070290274 - Nonvolatile semiconductor memory device including memory cells formed to have double-layered gate electrodes: A nonvolatile semiconductor memory device includes a plurality of floating gate electrodes respectively formed above a semiconductor substrate with first insulating films disposed therebetween, and a control gate electrode formed above the plurality of floating gate electrodes with a second insulating film disposed therebetween. In each of the plurality of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070290275 - Semiconductor integrated circuit device having deposited layer for gate insulation: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070290276 - Voltage-clipping device with high breakdown voltage: The present invention proposes a voltage-clipping device utilizing a pinch-off mechanism formed by two depletion boundaries. A clipping voltage of the voltage-clipping device can be adjusted in response to a gate voltage; a gap of a quasi-linked well; and a doping concentration and a depth of the quasi-linked well and... Agent: Jianq Chyun Intellectual Property Office

20070290277 - Process for fabricating a strained channel mosfet device: A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used... Agent: Slater & Matsil, L.L.P.

20070290278 - Semiconductor device and process for reducing damaging breakdown in gate dielectrics: The present invention, in one aspect, provides an integrated circuit that comprises a first region of transistors having gate structures with a low dopant concentration, and a second region of transistors having gate structures with a dopant concentration substantially higher than the gate structures of the first region, and wherein... Agent: Hitt Gaines, PC Lsi Corporation

20070290279 - Semiconductor device including groove pattern around effective chip and method for fabricating the same: A semiconductor device includes an interlayer insulating film, a first interconnect material, and a second interconnect material. The interlayer insulating film is formed on a semiconductor substrate including an effective chip. The first interconnect material is formed in an interconnect pattern in the interlayer insulating film. The interconnect pattern is... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070290280 - Semiconductor device having silicide thin film and method of forming the same: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed... Agent: Marger Johnson & Mccollom, P.C.

20070290281 - Activation device: Disclosed is an activation device for use in initiating an event. This activation device includes an activation member with a body having a front surface and a rear surface. The illumination member is positioned substantially adjacent, spaced from or near to the rear surface of the body of the activation... Agent: The Webb Law Firm, P.C.

20070290282 - Bonded chip assembly with a micro-mover for microelectromechanical systems: An embodiment of a micro-mover in accordance with the present invention can include a movable plate hermetically sealed between a top cap wafer and a bottom cap wafer. A magnet disposed on one or both of the cap wafers. The movable plate can include current paths disposed within a magnetic... Agent: Fliesler Meyer LLP

20070290283 - Solar cell and manufacturing method thereof: A solar cell and a manufacturing method thereof. A method of manufacturing a solar cell includes: forming an emitter layer on a first surface of a semiconductor substrate; forming an insulation layer on the emitter layer; applying a chemical compound including a dopant having a conductive type of the emitter... Agent: Christie, Parker & Hale, LLP

20070290284 - Incident light angle detector for light sensitive integrated circuit: A detector configuration determines the direction of illumination incident on a photosensitive device. Multiple mask layers include holes which form an interlayer optical path through which radiation reaches a photodetector. The interlayer optical path provides a selected nominal maximum signal angle and the detector senses when radiation is received at... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20070290285 - Semiconductor device, solid state image pickup device and manufacturing method thereof: A semiconductor device that contains photodiodes whose sensitivity and storage capacity can be increased, and a solid-state image pickup device formed by arranging the photodiodes in an array and its manufacturing method. A first semiconductor region 11 of a second conductivity type is formed on the principal surface of a... Agent: Texas Instruments Incorporated

20070290286 - Solid-state imaging device: A solid-state imaging device including: a plurality of photosensitive cells, each having a photodiode, arranged on a semiconductor substrate (1) in a matrix; and a peripheral driving circuit that has a plurality of transistors for driving the plurality of photosensitive cells. The plurality of transistors includes a first transistor and... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070290287 - Thin film photodetector, method and system: A photodetector, comprises a first section comprising at least one p-n junction that converts photon energy into a separate charge carrier and hole carrier; and another section of semiconductors of opposing conductivity type connected electrically in series and thermally in parallel in a heat dissipating and electric generating relationship to... Agent: Philip D Freedman PC Philip D Freedman

20070290288 - Floating body germanium phototransistor having a photo absorption threshold bias region: A floating body germanium (Ge) phototransistor with a photo absorption threshold bias region, and an associated fabrication process are presented. The method includes: providing a p-doped Silicon (Si) substrate; selectively forming an insulator layer overlying a first surface of the Si substrate; forming an epitaxial Ge layer overlying the insulator... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070290289 - Diode structure to suppress parasitic current: A diode conducts current between an anode terminal and a cathode terminal. The diode includes a parasitic transistor formed between one of the terminals and the substrate. The diode also includes a second transistor that competes with the parasitic transistor to direct current flow between the anode terminal and the... Agent: Kinney & Lange, P.A.

20070290290 - Esd device layout for effectively reducing internal circuit area and avoiding esd and breakdown damage and effectively protecting high voltage ic: An improved layout pattern for electrostatic discharge protection is disclosed. A first heavily doped region of a first type is formed in a well of said first type. A second heavily doped region of a second type is formed in a well of said second type. A battlement layout pattern... Agent: Baker & Mckenzie LLP Patent Department

20070290291 - High voltage devices: High voltage devices capable of preventing leakage current caused by inversion layer. In the high voltage device, a substrate comprises an active area formed therein, a source region and a drain region formed in the substrate, and a gate structure is formed on the active area to define a channel... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20070290293 - Liner for shallow trench isolation: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the... Agent: Knobbe Martens Olson & Bear LLP

20070290292 - Use of teos oxides in integrated circuit fabrication processes: A method for manufacturing a low temperature removable silicon dioxide hard mask for patterning and etching is provided, wherein tetra-ethyl-ortho-silane (TEOS) is used to deposit a silicon dioxide hard mask.... Agent: Macpherson Kwok Chen & Heid LLP

20070290294 - Trench insulation structures and methods: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited... Agent: Knobbe Martens Olson & Bear LLP

20070290296 - Fuse structures and methods of forming the same: A fuse structure includes an insulating structure, a fuse pattern, an insulating pattern and an insulating layer. The insulating structure has a fuse region and a wire region proximate the fuse region. The fuse pattern is on the fuse region. The insulating pattern has a first portion and a second... Agent: Myers Bigel Sibley & Sajovec

20070290295 - Integrated circuit fuse structures including spatter shields and methods of forming the same: At least one fuse pattern extending in a first direction is formed on a fuse region of a substrate. A preliminary first insulating pattern is formed on the fuse region to cover the fuse pattern. A conductive layer is formed on the preliminary first insulating pattern. The conductive layer and... Agent: Myers Bigel Sibley & Sajovec

20070290297 - Filter having integrated floating capacitor and transient voltage suppression structure and method of manufacture: In one embodiment, a well region of one conductivity type is formed in semiconductor substrate of an opposite conductivity type. The well region forms one plate of a floating capacitor and an electrode of a transient voltage suppression device.... Agent: Bradley J. Botsch Semiconductor Components Industries, LLC

20070290298 - Semiconductor filter structure and method of manufacture: In one embodiment, a split well region of one conductivity type is formed in semiconductor substrate of an opposite conductivity type. The split well region forms one plate of a floating capacitor and an electrode of a transient voltage suppression device.... Agent: Bradley J. Botsch Semiconductor Components Industries, LLC

20070290299 - Laser processing method and semiconductor chip: This laser processing method irradiates a substrate 4 with laser light L while using a rear face 21 as a laser light entrance surface and locating a light-converging point P within the substrate 4, so as to form modified regions 71, 72, 73 within the substrate 4. Here, the quality... Agent: Drinker Biddle & Reath (dc)

20070290300 - Semiconductor device and method for manufacturing same: Herein disclosed a semiconductor device in which a semiconductor chip is mounted over a substrate, the device including a plurality of through-interconnects configured to be formed inside each of through-holes that penetrate the substrate and be led from the semiconductor chip to a face of the substrate on an opposite... Agent: Robert J. Depke Lewis T. Steadman

20070290301 - Multi-chip stacked package with reduced thickness: A multi-chip stacked package is revealed, primarily comprising a spacer pad and a plurality of leads of a lead frame, a first chip, a second chip, and an encapsulant. A plurality of first electrodes are formed on the active surface of the first chip below the spacer pad and are... Agent: Troxell Law Office PLLC Suite 1404

20070290302 - Ic chip package, and image display apparatus using same: In a liquid crystal driver package (1a) of one embodiment of the present invention, a film base member (2) is connected to a liquid crystal driver (3) through an interposer substrate (4a). Film base member connecting terminals (13) of the interposer substrate (4a) are connected to terminals of on-film wires... Agent: Harness, Dickey & Pierce, P.L.C

20070290303 - Dual leadframe semiconductor device package: A semiconductor device (10) comprises a die (11) provided between a first leadframe (12) and a second leadframe (13), such that a first surface of the die (11) is connected to the first leadframe (12) and a second surface of the die (11) is connected to a second leadframe (13).... Agent: Texas Instruments Incorporated

20070290304 - High power shunt switch with high isolation and ease of assembly: A high power shunt switch comprises a leadframe including a paddle for supporting a shunt element, and a plurality of bond pads located around a periphery of the paddle, wherein at least a first subset of the bond pads are aligned in a substantially straight-line configuration. A shunt element is... Agent: Tyco Technology Resources

20070290307 - Light emitting diode module: A light emitting diode (LED) module includes a circuit substrate and a plurality of LED dies. The circuit substrate sequentially includes a metal layer, a first dielectric layer and an interconnection layer. The first dielectric layer has a plurality of openings. The LED dies are respectively disposed in the openings... Agent: Birch Stewart Kolasch & Birch

20070290308 - Package of mems device and method for fabricating the same: A package of a micro-electro-mechanical systems (MEMS) device includes a cap wafer, a plurality of bonding bumps formed over the cap wafer, a plurality of array pads arrayed on an outer side of the bonding bumps, and an MEMS device wafer bonded to an upper portion of the cap wafer... Agent: Morgan Lewis & Bockius LLP

20070290305 - Power semiconductor module and fabrication method thereof: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress may be escaped. On the other hand, the wires on which a high voltage is applied are... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070290306 - Wiring substrate and manufacturing method thereof, and semiconductor apparatus: In a semiconductor apparatus, a semiconductor element is mounted on a wiring substrate. Wiring patterns and protrusions are formed on a surface of a substrate with the wiring patterns extending on tops of the protrusions. The surface of the substrate on which the wiring patterns are formed are covered with... Agent: Rankin, Hill, Porter & Clark LLP

20070290309 - System and method for hermetically sealing a package: A method for hermetically sealing a package includes applying a light or energy active resist to a fill port to act as a temporary hermetic seal, patterning the resist, and applying a solder to the fill port, wherein the solder is configured to serve as a hermetic seal.... Agent: Hewlett Packard Company

20070290310 - Semiconductor device and method for manufacturing the same: The heat dissipation characteristics of a semiconductor device having a flip-chip mounted semiconductor chip are improved at low costs. The semiconductor device includes: a substrate; the semiconductor chip which is flip-chip mounted on the substrate with the front surface of the chip facing downward; a sealing resin layer which is... Agent: Katten Muchin Rosenman LLP

20070290311 - Bond wireless power module wiht double-sided single device cooling and immersion bath cooling: A wire bond free power module assembly consists of a plurality of individual thin packages each consisting of two DBC wafers which sandwich one or more semiconductor die. The die electrodes and terminals extend through one insulation covered end of the wafer sandwich and the outer sides of the sandwiches... Agent: Ostrolenk Faber Gerb & Soffen

20070290312 - Carrier structure stacking system and method: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC and the upper shoulder of leads of a lower IC while conductive transits that implement stacking-related intra-stack connections between the constituent... Agent: Fish & Richardson P.C.

20070290315 - Chip system architecture for performance enhancement, power reduction and cost reduction: A computer chip is structured to have at least one single-layered chip, at least one multi-layered chip stack, and a carrier package characterized by electrical interconnections of less than 100 microns diameter, wherein the single-layered chip and the multi-layered chip stack are each electrically coupled to the electrical interconnections of... Agent: Fleit, Kain, Gibbons, Gutman, Bongini & Bianco Pl

20070290314 - Contrast interposer stacking system and method: The present description provides increased contrast between interposer and leads in a stack embodiment that employs an interposer that extends beyond a boundary or perimeter established by the leads of the constituent IC devices.... Agent: Fish & Richardson P.C.

20070290313 - Interposer stacking system and method: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC element and the upper shoulder of leads of a lower IC element while traces that implement stacking-related intra-stack connections between the... Agent: Fish & Richardson P.C.

20070290320 - Carrier for stacked type semiconductor device and method of fabricating the same: A carrier for a stacked type semiconductor device includes a lower carrier having a first accommodating portion that accommodates a first semiconductor device, and an upper carrier having a second accommodating portion that accommodates a second semiconductor device stacked on the first semiconductor device so as to be placed in... Agent: Paul J. Winters

20070290318 - Multi-chip package structure: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate.... Agent: Volentine & Whitt PLLC

20070290319 - Nested integrated circuit package on package system: A package on package system is provided including providing a first substrate having a first integrated circuit thereon and a second substrate having a second integrated circuit thereon, the second substrate having a recess provided therein. The first and second substrates are mounted having the first integrated circuit at least... Agent: Ishimaru & Zahrt LLP

20070290317 - Semiconductor device having a multi-layered semiconductor substrate: A semiconductor device includes an interface chip and a plurality of DRAM chips consecutively layered on the interface chip. A plurality of source electrodes, a plurality of ground electrodes, and a plurality of signal electrodes penetrate DRAM chips and interconnect the DRAM chips to the interface chip, which is connected... Agent: Young & Thompson

20070290316 - Stacked packages and systems incorporating the same: A microelectronic assembly includes units superposed on one another to form at least one stack having a vertical direction. Each unit includes one or more microelectronic devices and has top and bottom surfaces. Top unit terminals are exposed at the top surfaces and bottom unit terminals are exposed at the... Agent: Tessera Lerner David Et Al.

20070290321 - Die stack capacitors, assemblies and methods: Chip and wire and flip chip compatible die stack capacitors (“stack caps”), die stack assemblies and die stack assembly methods are disclosed. Each stack cap includes a plurality of multilayer sections. Each multilayer section is fabricated separately, and the sections are then bonded or integrated together. As illustrative examples, stack... Agent: Honeywell International Inc.

20070290322 - Thermal improvement for hotspots on dies in integrated circuit packages: Methods and apparatuses for improved integrated circuit (IC) packages are described herein. In an aspect, an IC device package includes an IC die having a contact pad, where the contact pad is located on a hotspot of the IC die. The hotspot is thermally coupled to a thermal interconnect member.... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070290323 - On-die termination method for multi-chip packages: An on-die termination method to support a multi-chip package routing topology is described. The on die termination method may increase the surface area on the substrate such that larger size die or more memory may be mounted thereto. The on-die termination method may include a semiconductor package that features on... Agent: Intel Corporation C/o Intellevate, LLC

20070290324 - Printed circuit board and circuit structure for power supply: In a printed circuit board, a semiconductor including plural power supply terminals and a semiconductor chip is mounted onto a mounting surface of a printed wiring board, and a bypass capacitor for reducting a power ground noise is provided. Another bypass capacitor, which is connected to the bypass capacitor only... Agent: Fitzpatrick Cella Harper & Scinto

20070290325 - Surface mounting structure and packaging method thereof: A surface mounting structure and a packaging method thereof comprises a chip, a first conducting wire and a second conducting wire. The two conducting wires instead of lead frame architecture of the prior art is that the lead frame and a bridge jumper connected with N junction and P junction... Agent: Rosenberg, Klein & Lee

20070290326 - Multi-dimensional wafer-level integrated antenna sensor micro packaging: An integrated packaging assembly for an MMIC that uses the semiconductor wafers on which circuit elements are fabricated as the package. The packaging assembly includes a plurality of semiconductor layers that have been diced from the semiconductor wafers, where the semiconductor layers can be made of different semiconductor material. The... Agent: MillerIPGroup, PLC Northrop Grumman Corporation

20070290327 - Circuit board and method for manufacturing semiconductor modules and circuit boards: The deterioration of dielectric breakdown strength arising from an opening of a metal plate is prevented and the reliability as a circuit board is enhanced. A circuit board is provided with a metal plate, having openings, as core material. The opening is provided in a manner that the size of... Agent: Fish & Richardson P.C.

20070290328 - Light emitting diode module: A light emitting diode (LED) module includes a metal circuit substrate and a plurality of LED dies. The metal circuit substrate sequentially includes a metal board, a first dielectric layer and an interconnection layer. The first dielectric layer has a plurality of openings. The LED dies are respectively disposed in... Agent: Birch Stewart Kolasch & Birch

20070290329 - Semiconductor device and method of manufacturing semiconductor device: In a semiconductor device 100, a light emitting element 120 has been mounted on an upper plane of a semiconductor substrate 102. In an impurity diffusion region of the semiconductor substrate 102, a P conducting type of a layer 104, and an N layer 106 have been formed, while an... Agent: Drinker Biddle & Reath (dc)

20070290330 - Integrated heat sink: An integrated heat sink comprises a plurality of heat sink portions. The integrated heat sink provides efficient transfer of heat from a non-planar surface. In an example configuration two heat sinks are integrated to provide a thermal solution for dual bare die silicon circuits on a common substrate. One of... Agent: Woodcock Washburn LLP (microsoft Corporation)

20070290331 - Thermally efficient ccd camera housing: A system and method of cooling a CCD camera may employ a composite material housing design that allows the cold side of a TEC to be mounted relatively close to the CCD and the hot side of the TEC to be isolated from the housing cavity in which the CCD... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070290333 - Chip stack with a higher power chip on the outside of the stack: In some embodiments, a system includes a circuit board, a first chip, and a second chip stacked on the first chip. The first chip is coupled between the circuit board and the second chip, and the first chip includes circuitry to repeats commands the first chip receives to the second... Agent: Blakely Sokoloff Taylor & Zafman

20070290332 - Stacking structure of chip package: A stacking structure of chip package disclosed herein includes a lead frame having a plurality of supporting fingers and a plurality of leads; a first chip arranged on one side of the lead frame by utilizing a first connecting element so as to partially cover these supporting fingers, wherein the... Agent: Birch Stewart Kolasch & Birch

20070290334 - High frequency semiconductor device: A semiconductor device has a mounting substrate and a semiconductor package mounted on the mounting substrate. The mounting substrate has a substrate body, input/output line conductors on the upper surface of the substrate body, a front-face grounding conductor on the upper surface of the substrate body, spaced from the input/output... Agent: Leydig Voit & Mayer, Ltd

20070290335 - High-frequency semiconductor device: An example of a high-frequency semiconductor device includes two unit semiconductor devices. Each of the two unit semiconductor devices has a ground substrate, a high-frequency semiconductor element, an input-side matching circuit, an output-side matching circuit, a side wall member, an input terminal, and an output terminal. The ground substrate has... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070290336 - Semiconductor package having dimpled plate interconnections: A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area, a patterned source connection having a plurality of dimples formed thereon coupling... Agent: Fortune Law Group LLP

20070290339 - Bulk metallic glass solders, foamed bulk metallic glass solders, foamed-solder bond pads in chip packages, methods of assembling same, and systems containing same: A foamed bulk metallic glass electrical connection is formed on a substrate of an integrated circuit package. The foamed bulk metallic glass electrical connection exhibits a low modulus that resists cracking during shock and dynamic loading. The foamed bulk metallic glass electrical connection is used as a solder bump for... Agent: Schwegman, Lundberg & Woessner, P.A.

20070290340 - Chip structure: A chip structure including a chip, at least an arrangement of side pads and multiple bumps is provided. The chip has an active surface, and the arrangement of side pads is disposed on the active surface and close to a side of the active surface. The arrangement of side pads... Agent: Jianq Chyun Intellectual Property Office

20070290337 - Electrically conductive connection, electronic component and method for their production: A connection structure includes a semiconductor die having a first major surface and an electrically conductive substrate having a second major surface. At least part of the second major surface is positioned facing towards and spaced at a distance from the first major surface. A galvanically deposited metallic layer extends... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20070290343 - Electronic component, semiconductor device employing same, and method for manufacturing electronic component: Herein disclosed an electronic component having a passivation layer in which an opening that exposes a part of a pad electrode is formed, an underlying metal layer formed on the pad electrode and the passivation layer, and a barrier metal layer formed on the underlying metal layer for an external... Agent: Robert J. Depke Lewis T. Steadman

20070290338 - Method and apparatus for carbon dioxide gettering for a chip module assembly: A chip module assembly includes a CO2 getter exposed through a gas-permeable membrane to a chip cavity of a chip module. One or more chips is/are enclosed within the cavity. The CO2 getter comprises a liquid composition including 1,8-diaza-bicyclo-[5,4,0]-undec-7-ene (DBU) in a solvent that includes an alcohol, preferably, 1-hexanol. In... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070290341 - Semiconductor package and method of mounting the same: A semiconductor package having a good joint to an external board, providing easy measurement control of the electrical characteristics of a semiconductor chip, and ensuring a sufficient number of input and output terminals, and a method of mounting the same are provided. The semiconductor package comprises a plurality of connection... Agent: Marger Johnson & Mccollom, P.C.

20070290342 - Semiconductor device: The first external electrode has a main body portion a part of which is buried in a side wall of a case and joining portions protruding from an end of the main body portion toward the inside of the case. Each joining portion of the first external electrode is formed... Agent: Woodcock Washburn LLP

20070290344 - Printed circuit board for package of electronic components and manufacturing method thereof: The present invention relates to a printed circuit board, and in particular, to a printed circuit board for a package of electronic components and manufacturing method thereof. One aspect of present invention provides a manufacturing method of a printed circuit board for an electronic component package, which includes: forming a... Agent: Staas & Halsey LLP

20070290345 - Structure and method for producing multiple size interconnections: An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically... Agent: Schmeiser, Olsen & Watts

20070290346 - Method for manufacturing an electronic component and corresponding electronic component: The invention pertains to a method for manufacturing an electronic component with a semiconductor element (1) that is contacted and fixed on a substrate surface (2). The method is characterized in that the rear side of the semiconductor element and/or the substrate surface is coated with an adhesive structure consisting... Agent: Dicke, Billig & Czaja

20070290347 - Semiconductive device having resist poison aluminum oxide barrier and method of manufacture: The invention provides a semiconductive device that comprises interlevel dielectric layers that are located over devices. The interlevel dielectric layers have a dielectric constant (k) less than about 4.0. Interconnects are formed within or over the interlevel dielectric layers. The semiconductive device further comprises an aluminum oxide barrier located between... Agent: Texas Instruments Incorporated

20070290348 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070290349 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070290350 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070290351 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070290352 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070290353 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070290354 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070290355 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070290356 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070290357 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070290358 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070290359 - Inexpensive method of fabricating a higher performance capacitance density mimcap integrable into a copper interconnect scheme: A method to integrate MIM capacitors into conductive interconnect levels, with low cost impact, and high yield, reliability and performance than existing integration methods is provided. This is accomplished by recessing a prior level dielectric for MIM capacitor level alignment followed by deposition and patterning of the MIM capacitor films.... Agent: Scully, Scott, Murphy & Presser, P.C.

20070290361 - Via layout with via groups placed in interlocked arrangement: Via layout with via groups placed in an interlocked arrangement for suppressing the crack propagation along the domain boundary between the via groups. A structure has a metal via pattern located in a dielectric layer and having a first via group and a second via group adjacent to each other.... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070290360 - Electrode pad on conductive semiconductor substrate: An electrode pad on a semiconductor substrate having a reduced capacitance of an electrode pad portion and allowing control of a characteristic impedance for a practical electrode pad size is provided. A mesa-stripe type optical waveguide formed by stacking an n-InP clad layer 2, an i layer 3 and a... Agent: Workman Nydegger

20070290362 - Integrated inductors and compliant interconnects for semiconductor packaging: Some embodiments of the present invention include integrated inductors and compliant interconnects for semiconductor packaging.... Agent: Intel/blakely

20070290363 - Semiconductor device having interface chip including penetrating electrode: A semiconductor device includes a memory chip having a memory cell array including a plurality of memory blocks, wherein the memory chip includes a plurality of test pads for testing operations of the memory blocks, and an interface chip including a penetrating electrode and a plurality of interface circuit blocks,... Agent: F. Chau & Associates, LLC

20070290364 - Stacked die package for mems resonator system: A stacked die package for an electromechanical resonator system includes a chip that contains an electromechanical resonator bonded onto the control chip for the electromechanical resonator by a thermally and/or electrically conductive epoxy. In various embodiments, the electromechanical resonator can be a micro-electromechanical system (MEMS) resonator or a nano-electromechanical system... Agent: Patterson & Sheridan, L.L.P.

20070290365 - Electronic device including a component stack and connecting elements, and connecting elements, and method for producing the electronic device: An electronic device includes a stack of electronic components and connecting elements. The component stack includes two components stacked one on top of another by their top sides. Contact areas are arranged on the top sides of the components, and the contact areas include external contact structures as connecting elements.... Agent: Edell, Shapiro & Finnan, LLC

20070290366 - Embedded chip package structure and fabricating method thereof: An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer... Agent: Jianq Chyun Intellectual Property Office

20070290367 - Mold for forming conductive bump, method of fabricating the mold, and method of forming bump on wafer using the mold: A mold for forming a conductive bump, a method of fabricating the mold, and a method of forming a bump on a wafer using the mold are provided. The bump can be formed by employing various materials, the mold can be repeatedly used several times because the mold is not... Agent: Marger Johnson & Mccollom, P.C.

20070290368 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070290369 - Resin paste for die bonding and its use: Disclosed is a resin paste for die bonding comprising a butadiene homopolymer or copolymer (A) having a carboxylic acid terminal group, a thermosetting resin (B), a filler (C), and a printing solvent (D), wherein the elastic modulus of the resin paste following drying and curing is within a range from... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070290370 - Device configured to have a nanowire formed laterally between two electrodes and methods for forming the same: A device configured to have a nanowire formed laterally between two electrodes includes a substrate and an insulator layer established on at least a portion of the substrate. An electrode of a first conductivity type and an electrode of a second conductivity type different than the first conductivity type are... Agent: Hewlett Packard Company

20070290371 - Pad structure and method of testing: An interconnect structure includes: a plurality of dielectric layers having aligned process control monitor (PCM) pads, and a conductive structure above a topmost one of the PCM pads. The conductive structure electrically connects the topmost PCM pad to a device under test above a level of the topmost PCM pad.... Agent: Duane Morris LLPIPDepartment (tsmc)

20070290372 - Semiconductor device having wire loop and method and apparatus for manufacturing the semiconductor device: A semiconductor device having a wire loop and a method and apparatus for manufacturing the semiconductor device are provided. The semiconductor device includes a wiring board having an electrode pad, a semiconductor chip having a bonding pad and attached on a top surface of the wiring board while exposing the... Agent: Marger Johnson & Mccollom, P.C.

20070290373 - Multilayer bonding ribbon: A bonding wire takes the form of a ribbon, and a bond includes such a bonding wire. The bonding wire includes at least two layers having different current carrying capacity.... Agent: Kenyon & Kenyon LLP

20070290374 - Component with encapsulation suitable for wlp and production method: An electrical component includes a substrate that includes one or more terminal contacts for one or more electrical component structures on a surface of the substrate. The electrical component also includes a cover having a first surface and a second surface. The cover includes one or more terminal pads on... Agent: Fish & Richardson PC

20070290375 - Active device array mother substrate: An active device array mother substrate suitable for being divided into a plurality of active device array substrates is provided. The active device array mother substrate includes a substrate, multiple sets of active device arrays, and a plurality of outer circuit pads. The substrate has a plurality of predetermined regions... Agent: Jianq Chyun Intellectual Property Office

20070290376 - Integrated circuit (ic) package stacking and ic packages formed by same: Methods, systems, and apparatuses for integrated circuit (IC) package vertical interconnection are described herein. In an aspect of the invention, an IC package includes an IC die with contact pads. The IC package also includes interconnect members which are coupled to the die at the contact pads. An encapsulating material... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070290377 - Three dimensional six surface conformal die coating: Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the... Agent: Haynes Beffel & Wolfeld LLP

20070290378 - Novel reworkable underfills for ceramic mcm c4 protection: The present invention provides chip containing electronic devices such as Multichip Ceramic Modules (MCM's) containing a plurality of chips on a substrate which chips are underfilled with a reworkable composition which allows one or more chips to be removed from the device and replaced. The reworkable compositions contain a base... Agent: Law Office Of Delio & Peterson, LLC.

20070290379 - Hydrophobic compositions for electronic applications: Disclosed area compositions comprising: a polyimide resin with a water absorption of 2% or less and, optionally, one or more of an electrically insulated filler, a defoamer and a colorant and one or more organic solvents. The compositions are useful as encapsulants and have a consolidation temperature of 190° C.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070284566 - Composite semiconductor device and method of manufacturing the same: The disclosed subject matter provides a composite semiconductor device which can include a common substrate, a first semiconductor light emitting structure, and a second semiconductor light emitting structure. The first semiconductor light emitting structure can include an epitaxial grown layer containing a light emitting layer formed on part of the... Agent: Cermak Kenealy & Vaidya, LLP

20070284565 - Led device with re-emitting semiconductor construction and optical element: A light source includes an LED component having an emitting surface, and an optical element having an input surface in optical contact with the emitting surface. The LED component may be or include an LED such as an LED die capable of emitting light at a first wavelength, in combination... Agent: 3m Innovative Properties Company

20070284568 - Field effect transistor and method for manufacturing same: A problem is arisen in conventional J-FETs that a shifting in a threshold voltage (VT) is generated before or after an energization with a gate current. A junction gate field effect transistor (J-FET) according to the present invention includes an undoped InGaAs channel layer 5, which is capable of accumulating... Agent: Sughrue Mion, PLLC

20070284570 - Organic semiconductor compositions with nanoparticles: A composition, comprising a medium of organic molecules, a plurality of nanoparticles dispersed in the medium, and a coating chemically bonded to a surface of the nanoparticles, wherein the composition is a semiconducting solid.... Agent: Hitt Gaines, PC Alcatel-lucent

20070284571 - Organic thin-film transistor, method of manufacturing same and equipment for manufacturing same: An organic thin-film transistor (TFT) with a large carrier mobility includes a drain electrode, a source electrode, which are made of different materials, and a semiconductor layer formed on upper surface of a substrate. Equipment for manufacturing the organic TFT comprises a substrate mounting unit, a painting unit, a light... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070284573 - Gate controlled field emission triode and process for fabricating the same: This invention relates to a process for fabricating ZnO nanowires with high aspect ratio at low temperature, which is associated with semiconductor manufacturing process and a gate controlled field emission triode is obtained. The process comprises providing a semiconductor substrate, depositing a dielectric layer and a conducting layer, respectively, on... Agent: Bucknam And Archer

20070284577 - Semiconductor device including fuses and method of cutting the fuses: A semiconductor device may include multiple fuses spaced at a same pitch from each other and a check pattern spaced a predetermined distance from one side of the fuses, where the check pattern has the same width, height, and pitch as the fuses, and the fuses may be formed of... Agent: Lee & Morse, P.C.

20070284580 - Bottom gate thin film transistor and method of manufacturing the same: A method of manufacturing a bottom gate thin film transistor (“TFT”) in which a polycrystalline channel region having a large grain size is formed relatively simply and easily. The method of manufacturing a bottom gate thin film transistor includes forming a bottom gate electrode on a substrate, forming a gate... Agent: Cantor Colburn, LLP

20070284581 - Method of fabricating pmos thin film transistor: A method of fabricating a p-type thin film transistor (TFT) includes: performing a first annealing process on a substrate to diffuse a metal catalyst through a capping layer into a surface of an amorphous silicon layer, and to crystallize the amorphous silicon layer to a polycrystalline silicon layer due to... Agent: Stein, Mcewen & Bui, LLP

20070284582 - Semiconductor device and manufacturing method of the same: A semiconductor device and manufacturing method of the same is provided in which the driving current of a PMOSFET is increased, through a scheme formed easily using an existing silicon process. A PMOSFET is formed with a channel in a <100> direction on a (100) silicon substrate. A compressive stress... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070284584 - System for displaying images including electroluminescent device and method for fabricating the same: The invention discloses a system for displaying images comprising an organic electroluminescent device. The organic electroluminescent device comprises a pixel area including a plurality of sub-pixels, a switching TFT having a first silicon layer with a first thickness and a driving TFT having a second silicon layer with a second... Agent: Liu & Liu

20070284585 - Thin film transistor array panel and method of manufacturing the same: A thin film transistor array panel and a method of manufacturing the same include: a substrate; a data line formed on the substrate; a gate line intersecting the data line and including a gate electrode; a source electrode connected to the data line; a drain electrode opposite the source electrode;... Agent: Cantor Colburn, LLP

20070284586 - Thin film transistor array substrate and method for fabricating the same: A TFT array substrate includes a gate line, a gate electrode, and a gate pad on a substrate, each of which including stacked layers of a first metal and a transparent conductive material, respectively, a pixel electrode formed of the transparent conductive material, a gate insulation layer on the substrate... Agent: Seyfarth Shaw, LLP

20070284592 - Led device with re-emitting semiconductor construction and reflector: Briefly, the present disclosure provides a device comprising: a) an LED capable of emitting light at a first wavelength; b) a re-emitting semiconductor construction which comprises a potential well not located within a pn junction; and c) a reflector positioned to reflect light emitted from the LED onto the re-emitting... Agent: 3m Innovative Properties Company

20070284589 - Light emitting device having increased light output: The light intensity emitted from a package is increased by adjusting a portion of the package encapsulant so that light impacting the side walls of the adjusted encapsulant portion will encounter total internal reflection (TIR) with the reflected light directed toward the top surface of the package. The adjusted portion... Agent: Kathy Manke Avago Technologies Limited

20070284596 - Display apparatus: Provided is a novel structure of an active matrix TFT backplane. In order to form an auxiliary capacitor by a pixel electrode or a drain electrode of a TFT connected therewith, a base metal layer is formed on a glass substrate and a substrate insulating layer is formed on an... Agent: Fitzpatrick Cella Harper & Scinto

20070284595 - Organic light emitting device and method for fabricating the same: An organic light emitting device includes a first electrode disposed on a first substrate and comprising an emission area and an non-emission area, a plurality of barrier ribs located on a portion of the non-emission area of the first electrode, each barrier rib having an overhang structure, auxiliary electrodes disposed... Agent: Brinks Hofer Gilson & Lione

20070284599 - Process for producing group iii nitride semiconductor stacked structure: In the inventive method of producing a Group III nitride semiconductor stacked structure, the stacked structure has an n-type underlying layer, an active layer, a p-type cladding layer and a p-type contact layer, each comprising a Group III nitride semiconductor, in this order on a substrate, wherein the p-type contact... Agent: Sughrue Mion, PLLC

20070284603 - Led device with re-emitting semiconductor construction and converging optical element: A light source is provided comprising an LED component having an emitting surface, which may comprise: i) an LED capable of emitting light at a first wavelength; and ii) a re-emitting semiconductor construction which comprises a second potential well not located within a pn junction having an emitting surface; or... Agent: 3m Innovative Properties Company

20070284601 - Light emitting device having improved light extraction efficiency and method of making same: A light emitting device including a multi-layer stack and an encapsulant layer having a patterned encapsulant region in optical proximity to a luminous stack surface of the multi-layer stack is disclosed. A method of making that encapsulant layer and of affixing that encapsulant layer to a luminous stack surface is... Agent: Rohm And Haas Company Patent Department

20070284600 - Low profile side emitting led: Low profile, side-emitting LEDs are described, where all light is efficiently emitted within a relatively narrow angle generally parallel to the surface of the light-generating active layer. The LEDs enable the creation of very thin backlights for backlighting an LCD. In one embodiment, the LED is a flip chip with... Agent: Patent Law Group LLP

20070284605 - Casting for an led module: A casting adapted to carry a light emitting diode die and an anti-static die is disclosed. The casting comprises two electrodes for opposite electrodes and a wall. The light emitting diode die is mounted one of electrodes and the anti-static die is mounted on the other electrode. The wall is... Agent: Rosenberg, Klein & Lee

20070284564 - Gan-based semiconductor light-emitting device, light illuminator, image display planar light source device, and liquid crystal display assembly: A GaN-based semiconductor light-emitting device includes (A) a first GaN-based compound semiconductor layer 13 having n-type conductivity, (B) an active layer 15 having a multi-quantum well structure including well layers and barrier layers for separating between the well layers, and (C) a second GaN-based compound semiconductor layer 17 having p-type... Agent: Bell, Boyd & Lloyd, LLP

20070284563 - Light emitting device including rgb light emitting diodes and phosphor: Disclosed herein is a light emitting device including at least three light emitting diodes having different peak emission wavelengths to primarily emit light in a blue, green or red wavelength range, and a wavelength-conversion means to convert primary light into secondary light in a visible light wavelength range, The light... Agent: Marger Johnson & Mccollom, P.C.

20070284567 - Polarization recycling devices and methods: Light-emitting devices and/or systems are described. In some embodiments, light-emitting devices and/or systems can recycle at least some light generated by a light-generating region of the light-emitting device. In one embodiment, a light-emitting device comprises a semiconductor light-emitting material stack including a light-generating region and a light emission surface, wherein... Agent: Wolf Greenfield & Sacks, P.C.

20070284569 - Charge coupled device: A charge coupled device (CCD) is disclosed which has a semiconductor body (20) comprising polymer or oligomer semiconductor material in place of the conventional silicon. A back electrode (22) of the device is electrically coupled to the semi-conductor body through a Schottky junction, reducing the availability of holes in the... Agent: Blakely, Sokoloff, Taylor & Zafman

20070284572 - Polythiophenes and devices thereof: wherein R represents a side chain, m represents the number of R substituents; A is a divalent linkage; x, y and z represent, respectively, the number of Rm substituted thienylenes, unsubstituted thienylenes, and divalent linkages A, respectively, in the monomer segment subject to z being 0 or 1, and n... Agent: Fay Sharpe / Xerox - Rochester

20070284575 - Metal/semiconductor/metal current limiter: A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method comprises: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070284574 - Method of forming a transistor having a dual layer dielectric: Embodiments of methods, apparatuses, components, and/or systems for forming transistor having a dual layer dielectric are described.... Agent: Hewlett Packard Company

20070284578 - Array substrate for liquid crystal display and method of testing: An array substrate including a signal line, a test line to inspect the open of the signal line and fault of the pixels, and a fuse electrically connecting the signal line with the test line. The fuse is opened when a current higher than a reference current is applied thereto.... Agent: Macpherson Kwok Chen & Heid LLP

20070284576 - Semiconductor circuit arrangement and associated method for temperature detection: A semiconductor circuit arrangement and a method for temperature detection is disclosed. One embodiment includes a semiconductor substrate, on which is formed a first insulating layer and thereon a thin active semiconductor region, which is laterally delimited by a second insulating layer. In the active semiconductor region, a first and... Agent: Dicke, Billig & Czaja

20070284579 - Strained si formed by anneal: A semiconductor structure includes a silicon substrate layer, a relaxed silicon-germanium layer on the silicon substrate layer and a strained single crystal silicon layer on the silicon-germanium layer. The silicon-germanium layer may include a thickness of 500 angstroms or less. The method for forming the semiconductor structure includes epitaxially forming... Agent: Mark J. Marcelli Duane Morris LLP

20070284583 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device, including forming a gate electrode or dummy gate on a fin-type silicon layer, introducing an impurity into the fin-type silicon layer with the gate electrode or dummy gate used as mask so as to form first impurity regions, etching the gate electrode or... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070284587 - Flexible electronic device and production method of the same: A flexible electronic device excellent in heat liberation characteristics and toughness and a production method for actualizing thereof in low cost and with satisfactory reproducibility are provided. A protection film is adhered onto the surface of a substrate on which surface a thin film device is formed. Successively, the substrate... Agent: Sughrue Mion, PLLC

20070284588 - Follicle stimulating hormone supreagonists: A plurality of semiconductor layers including a light-emitting layer (14) are formed on the main surface of a substrate (10) which is composed of a group III-V nitride semiconductor. A first n-type semiconductor layer (12) containing indium is formed between the light-emitting layer (14) and the substrate (10), thereby reducing... Agent: Mcdermott Will & Emery LLP

20070284590 - Light emitting element and manufacturing method thereof: A light emitting device having little variation in the intensity of light emitted from the light emitting surface is provided. The light emitting device of exemplary embodiments of the present invention 2 includes a laminated body with a first conductivity type layer and a second conductivity type layer, with a... Agent: Sughrue Mion, PLLC

20070284593 - Nitride-based semiconductor light emitting diode: A nitride-based semiconductor LED comprises a substrate; an n-type nitride semiconductor layer formed on the substrate; an active layer formed on a predetermined region of the n-type nitride semiconductor layer; a p-type nitride semiconductor layer formed on the active layer; a p-electrode formed on the p-type nitride semiconductor layer, the... Agent: Mcdermott Will & Emery LLP

20070284594 - Light emitting diode chip: A light emitting diode (LED) chip including: a substrate; and a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, sequentially deposited on the substrate, in which when a length of the substrate is L and a width of the substrate... Agent: Mcdermott Will & Emery LLP

20070284597 - Light emitting device and lcd backlighting device: A light emitting device has a mount with a protruding portion that has an element mounting surface on which a light emitting element is mounted and a first lead and a second lead are exposed. The light emitting element has a first electrode and a second electrode that are electrically... Agent: Mcginn Intellectual Property Law Group, PLLC

20070284598 - Semiconductor light emitting device: There is provided a highly reliable semiconductor light emitting device in which disconnection of wires does not occur in case that a semiconductor light emitting device capable of being used in place of incandescent lamps or fluorescent lamps is formed in a monolithic type by forming a plurality of light... Agent: Rabin & Berdo, PC

20070284602 - Dielectric wafer level bonding with conductive feed-throughs for electrical connection and thermal management: A method for fabricating semiconductor and electronic devices at the wafer level is described. In this method, dielectric material is used to wafer bond a device wafer to a submount wafer, after which vias can be structured into the submount wafer and dielectric bonding material to access contact pads on... Agent: Koppel, Patrick & Heybl

20070284604 - Light emitting diodes including transparent oxide layers: Light emitting diodes include a substrate having first and second opposing faces and that is transparent to optical radiation in a predetermined wavelength range and that is patterned to define, in cross-section, a plurality of pedestals that extend into the substrate from the first face towards the second face. A... Agent: Myers Bigel Sibley & Sajovec, P.A.

20070284606 - High-efficiency, overvoltage-protected, light-emitting semiconductor device: An LED comprises a multilayered light-generating semiconductor region grown on one of a pair of opposite major surfaces of a semiconducting silicon substrate, a bonding pad overlying the light-generating semiconductor region and received in part in a cavity formed centrally therein, and a substrate electrode on the other major surface... Agent: Woodcock Washburn LLP

20070284607 - Semiconductor light emitting device including porous layer: A light emitting device includes a semiconductor structure having a light emitting layer disposed between an n-type region and a p-type region. A porous region is disposed between the light emitting layer and a contact electrically connected to one of the n-type region and the p-type region. The porous region... Agent: Patent Law Group LLP

20070284608 - Reduction of dopant loss in a gate structure: A semiconductor device includes offset spacers that contact opposing side surfaces of a gate of a gate structure. The offset spacers can be formed by selectively depositing an oxide layer over the gate and the semiconductor substrate so that the opposing side surfaces of the gate e are substantially free... Agent: Texas Instruments Incorporated

20070284609 - Method and apparatus for drain pump power conservation: A method and apparatus are provided for improved power conservation in a semiconductor device (100) which includes a high voltage generating circuit (200) such as a drain pump. The operation frequency of the drain pump (200) is controlled in response to the high voltage level detected at the output thereof.... Agent: Ingrassia Fisher & Lorenz, P.C.

20070284610 - Switching device, drive and manufacturing method for the same, integrated circuit device and memory device: Provided is a switching device including ion conducting part 4 having an ion conductor, first electrode 1 formed at a first gap away from ion conducting part 4, second electrode 2 formed to be in contact with ion conducting part 4 and third electrode 3 formed at a second gap... Agent: Sughrue Mion, PLLC

20070284611 - Structure of strained silicon on insulator and method of manufacturing the same: Provided is a strained SOI structure and a method of manufacturing the strained SOI structure. The strained SOI structure includes an insulating substrate, a SiO2 layer formed on the insulating substrate, and a strained silicon layer formed on the SiO2 layer.... Agent: Buchanan, Ingersoll & Rooney PC

20070284612 - Semiconductor devices with one-sided buried straps: Structures and methods for forming the same. A semiconductor fabrication method comprises a step of providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate and a capacitor electrode on the semiconductor substrate. The capacitor electrode comprises dopants, and is electrically insulated from the semiconductor substrate by a capacitor... Agent: Schmeiser, Olsen & Watts

20070284613 - Strain-inducing semiconductor regions: A method to form a strain-inducing semiconductor region comprising three or more species of charge-neutral lattice-forming atoms is described. In one embodiment, formation of a strain-inducing semiconductor region, comprising three or more species of charge-neutral lattice-forming atoms, laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to... Agent: Intel/blakely

20070284614 - Ohmic contacts for semiconductor devices: A method for making a high electron mobility field-effect transistor device, including the following steps: providing a layered semiconductor structure that includes an InGaAs channel layer and at least two layers over the channel layer, the at least two layers including a layer of InAlAs, a portion of which has... Agent: Martin Novack

20070284615 - Ultra-shallow and highly activated source/drain extension formation using phosphorus: A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the... Agent: Slater & Matsil, L.L.P.

20070284616 - Light emitting transistor: A light emitting transistor comprises a first conductivity-type collector layer formed on a substrate; a second conductivity-type base layer formed on a predetermine region of the collector layer; a collector electrode formed on the collector layer where the base layer is not formed; a first conductivity-type emitter layer formed on... Agent: Mcdermott Will & Emery LLP

20070284617 - High performance cmos devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same: The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A tensilely stressed dielectric layer overlays the... Agent: Scully Scott Murphy & Presser, PC

20070284618 - Transistor layout for standard cell with optimized mechanical stress effect: A layout for a transistor in a standard cell is disclosed. The layout for a transistor comprises an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20070284619 - Semiconductor integrated circuit device: In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell.... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070284621 - Dual-gate semiconductor devices with enhanced scalability: A scalable semiconductor device is formed using control gates formed on opposite sides of a semiconductor layer. A first control gate is formed electrically isolated from a first surface of the semiconductor layer by a first dielectric layer, such that, when a first voltage is applied on the first control... Agent: Macpherson Kwok Chen & Heid LLP

20070284624 - Optical semiconductor device with sensitivity improved: An optical semiconductor device containing a photodiode, includes a first semiconductor layer of a first conductive type; and a channel layer of a second conductive type formed from a surface portion of the first semiconductor layer in a light receiving region. The channel layer and the first semiconductor layer in... Agent: Young & Thompson

20070284623 - Semiconductor device having vertical channel transistor: A semiconductor device includes a substrate, and a plurality of active pillars arranged in a pattern of alternating even and odd rows and alternating even and odd columns, each active pillar extending from the substrate and including a channel portion, wherein the odd columns include active pillars spaced at a... Agent: Lee & Morse, P.C.

20070284620 - Structure and method of sub-gate and architectures employing bandgap engineered sonos devices: A bandgap engineered SONOS device structure for design with various AND architectures to perform a source side injection programming method. The BE-SONOS device structure comprises a spacer oxide disposed between a control gate overlaying an oxide-nitride-oxide-nitride-oxide stack and a sub-gate overlaying a gate oxide. In a first embodiment, a BE-SONOS... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070284622 - Phase-change memory device: Disclosed is a phase-change memory device including a phase-change material pattern, a diffusion barrier layer, a bottom electrode and a top electrode. The phase-change material pattern is placed on the bottom electrode, and the diffusion barrier layer containing tellurium is placed on the phase-change material pattern. The top electrode containing... Agent: Volentine & Whitt PLLC

20070284625 - Method for producing si1-ygey based zones with different contents in ge on a same substrate by condensation of germanium: s

20070284626 - Scalable process and structure for jfet for small and decreasing line widths: A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms or less on... Agent: Ronald Craig Fish, A Law Corporation

20070284627 - Liquid crystal display device and semiconductor device: By increasing an interval between electrodes which drives liquid crystals, a gradient of an electric field applied between the electrodes can be controlled and an optimal electric field can be applied between the electrodes. The invention includes a first electrode formed over a substrate, an insulating film formed over the... Agent: Fish & Richardson P.C.

20070284628 - Self aligned gate jfet structure and method: A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or silicide) and a self-aligned gate contact made of second polysilicon which has been polished back... Agent: Ronald Craig Fish, A Law Corporation

20070284629 - High-performance field effect transistors with self-assembled nanodielectrics: Field effect transistor devices comprising III-V semiconductors and organic gate dielectric materials, such dielectric materials as can afford flexibility in device design and fabrication.... Agent: Reinhart Boerner Van Deuren S.c. Attn: Linda Kasulke, Docket Coordinator

20070284631 - Integrally gated carbon nanotube field ionizer device and method of manufacture therefor: A field ionization device can include a first insulator layer on a first side of a substrate, a conductive gate layer on the first insulator layer, a cavity in the substrate, a portion of first insulator over the cavity, an aperture in the portion of the first insulator layer and... Agent: Naval Research Laboratory Associate Counsel (patents)

20070284632 - Non-volatile memory device and a method of fabricating the same: A non-volatile memory device and a method of fabricating the same are provided. A non-volatile memory device may include a semiconductor substrate including a body and at least one pair of fins vertically protruding from the body and spaced apart from each other, and at least one control gate electrode... Agent: Harness, Dickey & Pierce, P.L.C

20070284634 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a convex portion of a first conductive type protruding from a semiconductor substrate between insulating films formed on the semiconductor substrate in an upper direction than the insulating films. A gate insulating film contains nitrogen and is formed on at least a portion of the convex... Agent: Foley And Lardner LLP Suite 500

20070284633 - Curled semiconductor transistor: A curled transistor comprises a coiled semiconductor substrate having a plurality of concentrically curled layers. Source and drain regions are configured on a portion of the coiled semiconductor substrate, and a gate dielectric is positioned between the source and drain regions. A first set of metallic contacts electrically couple to... Agent: Andrews Kurth LLP Intellectual Property Department

20070284630 - Field effect transistor for measuring biocomponents: The invention relates to a device for measuring living cells or similar biocomponents comprising a field effect transistor which is provided with a source, a drain and a channel area placed on a substrate. Said channel area connects said source and drain and is provided with a gate-electrode mounted thereon.... Agent: The Webb Law Firm, P.C.

20070284635 - Nitrogenated carbon electrode for chalcogenide device and method of making same: A nitrogenated carbon electrode suitable for use in a chalcogenide device and method of making the same are described. The electrode comprises nitrogenated carbon and is in electrical communication with a chalcogenide material. The nitrogenated carbon material may be produced by combining nitrogen and vaporized carbon in a physical vapor... Agent: Honigman Miller Schwartz & Cohn LLP

20070284636 - Semiconductor memory device and method for fabricating the same: A semiconductor memory device includes: a first conductive layer; a second conductive layer; a first insulating film; a first plug; a second plug; a second insulating film having a first opening and a second opening; a first metal film; a second metal film; a first capacitor insulating film formed on... Agent: Mcdermott Will & Emery LLP

20070284637 - Ferroelectric memory and its manufacturing method: To securely prevent hydrogen from entering a ferroelectric layer of a ferroelectric memory. A first hydrogen barrier layer 5 is formed on the lower side of ferroelectric capacitors 7. Upper surfaces and side surfaces of the ferroelectric capacitors 7 are covered by a second hydrogen barrier layer. All upper electrodes... Agent: Oliff & Berridge, PLC

20070284638 - Conductive container structures having a dielectric cap: Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures... Agent: Schwegman, Lundberg & Woessner, P.A.

20070284639 - Transistor and method for manufacturing the same: A transistor including a semiconductor substrate defined with an active region and a device isolation region, a gate formed on the semiconductor substrate, an insulating spacers formed on respective side walls of the gate, and source/drain junctions formed in the semiconductor substrate at opposite sides of the gate, the source/drain... Agent: Marshall, Gerstein & Borun LLP

20070284640 - Semiconductor capacitors in hot (hybrid orientation technology) substrates: A semiconductor structure and a method for forming the same. The semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an electrically insulating region on top of the semiconductor substrate. The semiconductor structure further includes a first semiconductor region on top of and in direct physical contact with... Agent: Schmeiser, Olsen & Watts

20070284642 - Dielectric memory and manufacturing method thereof: As an oxygen diffusion prevention layer, a multilayer film formed by a metal nitride and a noble metal element. As an interlayer insulation film on the oxygen diffusion prevention layer, a plasma CVD oxide film is used. Moreover, as an interlayer insulation film on a capacitor, an ozone TEOS film... Agent: Mcdermott Will & Emery LLP

20070284641 - Metal-insulator-metal-structured capacitor formed with polysilicon: A METAL-INSULATOR-METAL structured capacitor is formed with polysilicon instead of an oxide film as a sacrificial layer material that defines a storage electrode region. A MPS (Meta-stable Poly Silicon) process is performed to increase the surface area of the sacrificial layer that defines the storage electrode region and also increase... Agent: Townsend And Townsend And Crew, LLP

20070284643 - Capacitor structure of semiconductor memory and method for preparing the same: A capacitor structure comprises a plurality of cylinders and a supporting ring positioned among the plurality of cylinders and connecting a portion of the sidewall of each cylinder. The cylinders can be hollow circular cylinders, and the supporting ring can be positioned on a top portion of the cylinders. The... Agent: Oliff & Berridge, PLC

20070284644 - An apparatus and associated method for making a floating gate cell in a virtual ground array: A method for fabricating a floating gate memory device comprises using thin buried diffusion regions with increased encroachment by a buried diffusion oxide layer into the buried diffusion layer and underneath the tunnel oxide under the floating gate. Further, the floating gate polysilicon layer has a eight than the buried... Agent: Baker & Mckenzie LLP Patent Department

20070284645 - Non-volatile memory devices having a multi-layered charge storage layer and methods of forming the same: A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap... Agent: Myers Bigel Sibley & Sajovec

20070284647 - Semiconductor device and method of fabricating the same: A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active... Agent: Harness, Dickey & Pierce, P.L.C

20070284646 - Nonvolatile semiconductor memory device: According to an aspect of the invention, a nonvolatile semiconductor memory device includes: a semiconductor layer comprising an n-type semiconductor region; p-type source-drain regions separated from each other within the n-type semiconductor region; a charge storage layer provided on the semiconductor layer and between the p-type source-drain regions, the charge... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070284648 - Non-volatile memory device and method of manufacturing the same: The non-volatile memory device may include a semiconductor substrate having a body and a pair of fins. A bridge insulating layer may non-electrically connect upper portions of the pair of fins to define a void between the pair of fins. Outer surfaces of the pair of fins are the surfaces... Agent: Harness, Dickey & Pierce, P.L.C

20070284649 - Semiconductor device and method of manufacturing same: A semiconductor device includes a deposited-type insulating film disposed on a substrate; a coating-type insulating film disposed on a surface of the deposited-type insulating film and having a film density which is lower than a film density of the deposited-type insulating film; and an intermediate insulating film disposed between the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070284651 - Charge-trap type non-volatile memory devices and related methods: Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so... Agent: Myers Bigel Sibley & Sajovec

20070284650 - Memory device and a method of forming a memory device: A memory device includes active regions extending in a first direction, the active regions being formed in a semiconductor substrate. Transistors are formed in the active regions, including a first and a second source/drain region, a channel formed between the first and the second source/drain region, a gate electrode, and... Agent: Edell, Shapiro & Finnan, LLC

20070284653 - Semiconductor device: A semiconductor device includes a first group III-V nitride semiconductor layer, a second group III-V nitride semiconductor layer having a larger band gap than the first group Ill-V nitride semiconductor layer and at least one ohmic electrode successively formed on a substrate. The ohmic electrode is formed so as to... Agent: Mcdermott Will & Emery LLP

20070284652 - Semiconductor memory device: A semiconductor memory device capable of suppressing detrapping of stored charges from a charge storage dielectric is disclosed. According to one aspect of the present invention, there is provided a semiconductor memory device comprising a semiconductor substrate, a blocking dielectric disposed on the semiconductor substrate a charge storage dielectric disposed... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070284654 - Metal alloy layer over conductive region of transistor device of different conductive material than conductive region: A transistor device and method are disclosed for reducing parasitic resistance and enhancing channel mobility using a metal alloy layer over a conductive region. A transistor device may include a conductive region such as a source, drain and/or gate including at least one first conductive material, and a metal alloy... Agent: Hoffman, Warnick & D'alessandro LLC

20070284655 - Semiconductor device and method for fabricating the same: A semiconductor device includes a device isolation structure formed on a semiconductor substrate to define an active region. A first Si-based epitaxial pattern is formed over the active region corresponding to a bit line contact region and a portion of a gate region at both sides adjacent to the bit... Agent: Townsend And Townsend And Crew, LLP

20070284656 - Conductive hard mask to protect patterned features during trench etch: A method is provided for forming patterned features using a conductive hard mask, where the conductive hard mask protects those features during a subsequent trench etch to form Damascene conductors providing electrical connection to those features from above. The thickness of the hard mask provides a margin to avoid overetch... Agent: Patent Dept., Sandisk Corporation

20070284657 - Semiconductor device having trench-type gate and its manufacturing method capable of simplifying manufacturing steps: In a semiconductor device, a gate silicon dioxide layer is formed within a trench of a semiconductor wafer. A first gate electrode is formed on a sidewall of the trench of the semiconductor wafer via the gate silicon dioxide layer. An insulating layer is formed on a bottom of the... Agent: Mcginn Intellectual Property Law Group, PLLC

20070284658 - Laterally diffused metal oxide semiconductor device and method of forming the same: A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region... Agent: Glenn W. Boisbrun Slater & Matsil, L.L.P.

20070284659 - Method of forming high voltage n-ldmos transistors having shallow trench isolation region with drain extensions: A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070284660 - Method for fabricating a semiconductor on insulator wafer: A method for fabricating semiconductor on insulator wafers by providing a semiconductor substrate or a substrate that includes an epitaxial semiconductor layer as a source substrate, attaching the source substrate to a handle substrate to form a source handle assembly and detaching the source substrate at a predetermined splitting area... Agent: Winston & Strawn LLP Patent Department

20070284661 - Semiconductor memory device and method of manufacturing the same: This disclosure concerns a semiconductor memory device comprising a semiconductor substrate; a first dielectric film provided on the semiconductor substrate; two Fins provided on the first dielectric film and made of a semiconductor material; a second dielectric film provided on facing inner side surfaces among side surfaces of the two... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070284662 - Microelectronic structure including high current density resistor: A microelectronic structure and a method for fabricating the microelectronic structure include a resistor located and formed over a substrate. A conductor contact layer contacts the resistor. A maximum length of the conductor contact layer is determined using a Blech constant to avoid electromigration of a conductor material that comprises... Agent: Scully, Scott, Murphy & Presser, P.C.

20070284664 - Semiconductor power converter apparatus: Even when one of IGBTs fails in a semiconductor power converter apparatus in which a plurality of semiconductor elements are connected in parallel, the remaining IGBT(s) is prevented from failing with a simple circuit configuration. The semiconductor power converter apparatus includes: a semiconductor power conversion circuit in which a first... Agent: Sughrue Mion, PLLC

20070284663 - System and method for i/o esd protection with polysilicon regions fabricated by processes for making core transistors: A system and method for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is... Agent: Townsend And Townsend And Crew, LLP

20070284665 - Electrostatic discharge protection device: According to an embodiment of the present invention, an electrostatic discharge protection circuit used for a semiconductor device including a first power supply terminal, a second power supply terminal, and an input/output terminal, includes: a thyristor passing a surge current from the input/output terminal to the second power supply terminal;... Agent: Mcginn Intellectual Property Law Group, PLLC

20070284666 - Local esd protection for low-capicitance applications: A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad (301) against ESD events, when the I/O pad is located between a power pad (303) and a ground potential pad (305a). A first diode (311) and a second diode (312) are connected in series, the anode (311b) of... Agent: Texas Instruments Incorporated

20070284667 - Electrostatic discharge protection method and device for semiconductor device: According to an embodiment of the present invention, an electrostatic breakdown protection method protects a semiconductor device from a surge current impressed between a first terminal and a second terminal, the semiconductor device including: a diode impressing a forward-bias current from the first terminal to the second terminal; and a... Agent: Mcginn Intellectual Property Law Group, PLLC

20070284668 - Cmos s/d sige device made with alternative integration process: A semiconductor device includes a substrate having regions filled with an additive that forms a source/drain for a MOS device, a gate dielectric layer deposited over the substrate, the gate dielectric layer electrically isolates the substrate from subsequently deposited layers, a gate electrode deposited over the gate dielectric layer, an... Agent: Townsend And Townsend And Crew LLP / Amat

20070284669 - Method and structure to process thick and thin fins and variable fin to fin spacing: Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070284670 - Semiconductor device and fabrication method therefor: A semiconductor device has a transistor of a first conductivity type formed on a semiconductor substrate and having a first gate insulating film and a first gate electrode and a transistor of a second conductivity type having a second gate insulating film and a second gate electrode. The first gate... Agent: Mcdermott Will & Emery LLP

20070284671 - Semiconductor device including cmis transistor: Gate electrodes made of polysilicon film are isolated and face each other by way of a side wall spacer portion that fills a gap formed above an isolation insulating film at the boundary of NMIS region and PMIS region. A first metal film is formed on one of the gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070284672 - Current limiting mosfet structure for solid state relays: A current-limiting circuit for limiting rising of a current above a predetermined level. The circuit including forward- and reverse-conducting devices, each device including a MOS and a bipolar transistor, wherein ON-resistance of one of the devices is used instead of a current-sensing resistance for another of the devices; and a... Agent: Ostrolenk Faber Gerb & Soffen

20070284673 - High frequency mos device and manufacturing process thereof: MOS device formed in a semiconductor body having a first conductivity type and a surface and housing a first current-conduction region and a second current-conduction region, of a second conductivity type. The first and second current-conduction regions define between them a channel, arranged below a gate region, formed on top... Agent: Bryan A. Santarelli Graybeal Jackson Haley LLP

20070284674 - Porous silicon for isolation region formation and related structure: A method of forming an isolation region using porous silicon and a related structure are disclosed. One embodiment of the method may include forming a collector region; forming a porous silicon region in the collector region; forming a crystalline silicon intrinsic base layer over the collector region, the intrinsic base... Agent: Hoffman, Warnick & D'alessandro LLC

20070284675 - Semiconductor device and method for manufacturing same: The semiconductor device includes a silicon substrate, an SiO2 film provided so as to be in contact with the upper portion of the silicon substrate, and a p-type MOSFET including a polycrystalline silicon film, which is provided so as to be in contact with the upper portion of the SiO2... Agent: Sughrue Mion, PLLC

20070284677 - Metal oxynitride gate: A metal-oxide-semiconductor (MOS) transistor having a gate electrode comprising a metal oxynitride and a method of forming the same are provided. The metal oxynitride preferably comprises molybdenum oxynitride and/or iridium oxynitride. The gate electrode may further comprise carbon and/or silicon. The gate electrode is preferably formed in a chamber containing... Agent: Slater & Matsil, L.L.P.

20070284678 - Methods of manufacturing metal-silicide features: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening by a metal deposition process employing a target which... Agent: Haynes And Boone, LLP

20070284676 - Semiconductor device having multiple work functions and method of manufacture therefor: The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a metal gate electrode (135)... Agent: Texas Instruments Incorporated

20070284679 - Mos solid-state image pickup device and manufacturing method thereof: An N-type epitaxial layer 115, which is formed above an N-type semiconductor substrate 114 in each of a pixel region and a peripheral circuit region; a first P-type well 1 formed above the N-type epitaxial layer 115 in the pixel region; and light receiving regions 117, which are formed within... Agent: Mcdermott Will & Emery LLP

20070284681 - Apparatus and method for protective covering of microelectromechanical system (mems) devices: A microelectromechanical system (MEMS) assembly includes a MEMS substrate having a plurality of MEMS devices, a plurality of bond pads, and a wafer cap. The wafer cap includes a unitary structure having a plurality of pockets and a plurality of apertures. The wafer cap is fixed to the MEMS substrate... Agent: Seed Intellectual Property Law Group PLLC

20070284680 - Method for manufacturing semiconductor device and semiconductor device using the same: A method for manufacturing a semiconductor device, includes: forming a protrusive portion on a surface of a semiconductor substrate, forming a thin film on the surfaces of the semiconductor substrate and the protrusive portion, applying a resist on a surface of the thin film so that at least an apex... Agent: Pearne & Gordon LLP

20070284682 - Mems process and device: A MEMS device, for example a capacitive microphone, comprises a flexible membrane 11 that is free to move in response to pressure differences generated by sound waves. A first electrode 13 is mechanically coupled to the flexible membrane 11, and together form a first capacitive plate of the capacitive microphone... Agent: Dickstein Shapiro LLP

20070284683 - Enhanced permeability device structures and method: Low power magnetoelectronic device structures and methods therefore are provided. The magnetoelectronic device structure (100, 150, 450, 451) comprises a programming line (104, 154, 156, 454, 456), a magnetoelectronic device (102, 152, 452) magnetically coupled to the programming line (104, 154, 156, 454, 456), and an enhanced permeability dielectric (EPD)... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070284684 - Semiconductor device, magnetic sensor, and magnetic sensor unit: A semiconductor device, comprising a semiconductor chip; a pad electrode; an electrode portion; a wiring portion. An insulating portion is formed from electrically insulating material, covering the surface of the semiconductor chip and sealing the sensor element, wiring portion and electrode portion, in a state which exposes at least the... Agent: Dickstein Shapiro LLP

20070284686 - Method of forming elevated photosensor and resulting structure: Elevated crystal silicon photosensors for imagers pixels, each photosensor formed of crystal silicon above the surface of a substrate that has pixel circuitry formed thereon. The imager has a high fill factor and good imaging properties due to the crystal silicon photosensor.... Agent: Dickstein Shapiro LLP

20070284687 - Semiconductor optoelectronics devices: A semiconductor device comprising a semiconductor substrate with a plurality of photo-diodes arranged in the semiconductor substrate with interconnect layers defining apertures at the photo-diodes and a first polymer which fills the gaps such as to cover the photo-diode. Further, layers of color filters are arranged on top the gap... Agent: Kubovcik & Kubovcik

20070284685 - Semiconductor photodetector and method of manufacturing the same: The present invention relates to a semiconductor photodetector and the like that can be made adequately compact while maintaining mechanical strength. The semiconductor photodetector includes a structural body of layers and a glass substrate. The structural body of layers is arranged from an antireflection film, a high-concentration carrier layer of... Agent: Drinker Biddle & Reath (dc)

20070284688 - Pin diodes for photodetection and high-speed, high-resolution image sensing: The present invention provides high-speed, high-efficiency PIN diodes for use in photodetector and CMOS imagers. The PIN diodes include a layer of intrinsic semiconducting material, such as intrinsic Ge or intrinsic GeSi, disposed between two tunneling barrier layers of silicon oxide. The two tunneling barrier layers are themselves disposed between... Agent: Foley & Lardner LLP

20070284689 - Drive circuit: A drive circuit has a level shift circuit which outputs level-shifted on and off signals each for controlling a power semiconductor element in an on or off state, a first RS flip flop which is supplied with the on signal through a setting input terminal and supplied with the off... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070284690 - Etch features with reduced line edge roughness: A method for forming a feature in a layer with reduced line edge roughening is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A sidewall layer with a thickness less than 100 nm is formed over the... Agent: Beyer Weaver LLP

20070284691 - Semiconductor device with omega gate and method for fabricating a semiconductor device: A substrate has an active region divided into storage node contact junction regions, channel regions and a bit line contact junction region. Device isolation layers are formed in the substrate isolating the active region from a neighboring active region Recess patterns are formed each in a trench structure and extending... Agent: Blakely Sokoloff Taylor & Zafman

20070284692 - Device isolation structure incorporated in semiconductor device and method of forming the same: The structure of the present invention comprises a semiconductor substrate and a trench region formed on the semiconductor substrate. The trench region includes an extended funnel portion in the vicinity of the semiconductor substrate surface. A device isolation layer is formed at the trench region. The device isolation layer includes... Agent: Marger Johnson & Mccollom, P.C.

20070284693 - Electrically programmable fuse with asymmetric structure: An electrically programmable fuse is provided which includes a cathode, an anode, and a fuse link conductively connecting the cathode to the anode. The cathode, the anode and the fuse link each have a length in a direction of current between the anode and cathode. Each of the cathode, the... Agent: International Business Machines Corporation Dept. 18g

20070284694 - Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structure: A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method includes forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such that an average resultant grain size... Agent: Schmeiser, Olsen & Watts

20070284695 - Apparatus and method for controlled particle beam manufacturing: A chamber for exposing a workpiece to charged particles includes a charged particle source for generating a stream of charged particles, a collimator configured to collimate and direct the stream of charged particles from the charged particle source along an axis, a beam digitizer downstream of the collimator configured to... Agent: Knobbe Martens Olson & Bear LLP

20070284696 - Nitride semiconductor substrate: In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, warp will be a large ±40 μm to ±100 μm. Since with that warp device... Agent: Judge & MurakamiIPAssociates

20070284697 - Marker for alignment of non-transparent gate layer, method for manufacturing such a marker, and use of such a marker in a lithographic apparatus: A method for manufacturing a marker structure including line elements and trench elements arranged in a repetitive order includes filling the trench elements with silicon dioxide and leveling the marker structure. A sacrificial oxide layer is grown on the semiconductor surface, and a first subset of the line elements is... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070284698 - Duv laser annealing and stabilization of sicoh films: A method of fabricating a dielectric film comprising atoms of Si, C, O and H (hereinafter SiCOH) that has improved insulating properties as compared with prior art dielectric films, including prior art SiCOH dielectric films that are not subjected to the inventive deep ultra-violet (DUV) is disclosed. The improved properties... Agent: Scully, Scott, Murphy & Presser, P.C.

20070284699 - Microfabricated devices and method for fabricating microfabricated devices: Microfabricated devices for operation in a fluid that include a substrate that has a first and second surface and a first electrode material layer located over the first surface of the substrate. The devices have a piezoelectric material layer located over the first electrode material layer and a second electrode... Agent: Proskauer Rose LLP

20070284700 - Coatings and methods for inhibiting tin whisker growth: An electrical component includes a conductive substrate, a tin layer formed on the substrate, and a conformal coating formed on the tin layer to impede tin whisker growth. The conformal coating comprises a polymer matrix having gas-filled voids dispersed therethrough. In a method for impeding tin whisker growth from a... Agent: Honeywell International Inc.

20070284701 - Method of forming a component having dielectric sub-layers: Embodiments of methods, apparatuses, devices, and/or systems for forming a component having dielectric sub-layers are described.... Agent: Hewlett Packard Company

20070284702 - Semiconductor device having a bonding pad and fuse and method for forming the same: A semiconductor device, including an interlayer dielectric layer having a bonding pad and a fuse on a semiconductor substrate, the interlayer dielectric layer having a pad opening and a fuse opening exposing the bonding pad and the fuse, an organic passivation layer on the interlayer dielectric layer, and a fuse... Agent: Lee & Morse, P.C.

20070284704 - Methods and apparatus for a semiconductor device package with improved thermal performance: A package assembly 200 includes a semiconductor die (e.g., an RF power amplifier) 208 fixed within the cavity of a conductive leadframe 204 using a thermally and electrically-conductive adhesive material 209. The semiconductor die 209 has a first side and a second side, wherein the first side includes at least... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070284705 - Package structure and lead frame using the same: A package structure and a lead frame using the same are provided. The package structure includes a lead frame, a chip and an adhesive. The lead frame has a first surface and a second surface opposite to the first surface. The first surface has a chip adherent area. The lead... Agent: Birch Stewart Kolasch & Birch

20070284703 - Semiconductor package structure: A semiconductor package structure includes a substrate, a chip module, a lead frame, and a bridging element. The chip module is electrically connected to the substrate. The lead frame is disposed beside one side of the substrate, and the lead frame has a projecting block unit. The bridging element has... Agent: Rosenberg, Klein & Lee

20070284706 - No-wick(tm) 2 interconnections: The present invention relates generally to permanent interconnections between electronic devices, such as integrated circuit packages, chips, wafers and printed circuit boards or substrates, or similar electronic devices. More particularly it relates to high-density electronic devices. The invention describes means and methods that can be used to counteract the undesirable... Agent: Gabe Cherian

20070284707 - Semiconductor device: A semiconductor device includes a semiconductor chip, an insulating base film and first projecting electrodes. The first projecting electrodes are formed in a single row on one face of the semiconductor chip along the edge of the semiconductor chip. This face of the semiconductor chip faces a semiconductor chip mounting... Agent: Rabin & Berdo, PC

20070284709 - Semiconductor device with improved high current performance: A semiconductor device comprises a die having a first surface and a second surface, a first leadframe connected to the first surface and the second surface, and a second leadframe connected to the first surface.... Agent: Texas Instruments Incorporated

20070284708 - Semiconductor optical device: The disclosed subject matter includes a semiconductor optical device with a stable optical characteristic, an excellent radiant efficiency, and a high mounting reliability. A casing can be configured with a concaved-shaped cavity that includes an opening and a bottom portion. Each of one end portions of first/second lead frame electrodes... Agent: Cermak Kenealy & Vaidya, LLP

20070284710 - Method for fabricating flip-chip semiconductor package with lead frame as chip carrier: A flip-ship semiconductor package with a lead frame as a chip carrier is provided, wherein a plurality of leads of the lead frame are each formed with at least a dam member thereon. When a chip is mounted on the lead frame by means of solder bumps, each of the... Agent: Edwards Angell Palmer & Dodge LLP

20070284711 - Methods and apparatus for thermal management in a multi-layer embedded chip structure: A multi-layer structure (102) includes a first build-up layer structure (202) configured to connect to a heat-generating module (120), a second build-up layer structure (206) configured to connect to a substrate, and a middle layer (204) provided between the first build-up layer structure and the second build-up layer structure, the... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070284712 - Semiconductor integrated circuit device, and method of designing and manufacturing the same: Disclosed are a semiconductor integrated circuit device, and a design and manufacturing method of the device, in which various semiconductor integrated circuit devices can be effectively designed and manufactured at low cost using a master slice method. A fixed layer used in common between Wire-Bonding (WB) chips and Flip-Chip (FC)... Agent: Staas & Halsey LLP

20070284713 - Sensor device: A sensor device includes a board, a sensor element and a resin member made of resin. The sensor element has a displace part to be displaced in a predetermined detection direction, and detects a displace amount of the displace part in the detection direction. The sensor element is mounted and... Agent: Posz Law Group, PLC

20070284714 - Electronic part and method of producing the same: An electronic component is provided with a base member 1 having a through hole 41 (43) extending from a bottom surface of a recess 15 to a back surface 11back, an electronic element 4 mounted in the recess 15, a lid member 2 closing an aperture of the recess 15,... Agent: Drinker Biddle & Reath (dc)

20070284717 - Device embedded with semiconductor chip and stack structure of the same: A circuit board stack structure embedded with semiconductor components includes two circuit boards, each of which having an opening; circuit layers formed on top and bottom surfaces of the circuit boards, each of the circuit layers having a plurality of conductive structures and electrical connecting pads; two semiconductor components embedded... Agent: Sawyer Law Group LLP

20070284715 - System-in-package device: A system-in-package (SIP) device includes a substrate, a first chip and a chip package. The first chip is mounted and electrically connected to the substrate. The chip package is disposed above the first chip, and includes a leadframe, a second chip and a first encapsulant. The leadframe includes a die... Agent: Reed Smith LLP Suite 1400

20070284716 - Assembly having stacked die mounted on substrate: The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon... Agent: Haynes Beffel & Wolfeld LLP

20070284718 - Stacked die package system: A stacked die package system including forming a bottom package including a bottom substrate and a bottom die mounted and electrically connected under the bottom substrate and forming a top package including a top substrate and a top die mounted and electrically connected over the top substrate. Mounting the top... Agent: Ishimaru & Zahrt LLP

20070284719 - Semiconductor device: A semiconductor device includes an insulator substrate mounted on a base plate, the insulator substrate having an upper electrode, semiconductor chips mounted on the insulator substrate, external terminals for establishing external electrical connections of the semiconductor device, wires for establishing electrical connections among the external terminals, the upper electrode and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070284721 - Semiconductor device and method for producing the semiconductor device: A semiconductor device of the present invention is includes a semiconductor device comprising: a semiconductor chip having a passivation film on an electrode forming surface thereof on which a plurality of electrodes are formed; a protective film which is provided on an upper surface of the passivation film and patterned... Agent: Rabin & Berdo, PC

20070284720 - Power semiconductor device and method for its production: A power semiconductor device and a method for its production. The power semiconductor device has at least one power semiconductor chip, which has on its top side and on its back side large-area electrodes. The electrodes are electrically in connection with external contacts by means of connecting elements, the power... Agent: Edell, Shapiro & Finnan, LLC

20070284722 - Semiconductor device package utilizing proud interconnect material: A semiconductor package which includes a conductive can, a semiconductor die received in the interior of the can and connected to an interior portion thereof at one of its sides, at least one interconnect structure formed on the other side of the semiconductor die, and a passivation layer disposed on... Agent: Ostrolenk Faber Gerb & Soffen

20070284724 - Mounting integrated circuit dies for high frequency signal isolation: A method of connecting signal lines between an integrated circuit (IC) die and a carrier or external circuit, and corresponding apparatus. Techniques for adjusting magnetic coupling between terminated signal lines include splitting a return path for termination current and disposing one nearby on either side of the terminated signal line,... Agent: Martin J. Jaquez, Esq. Jaquez & Associates

20070284723 - Packaged integrated circuit device: A packaged integrated circuit device is disclosed, in which there are provided at least one pad formed at an active surface and a conductive line which is connected with a non-active surface along a lateral surface, so that a connection between the pad and the non-active surface is performed through... Agent: Ipla P.A.

20070284725 - Integrated circuit (ic) carrier assembly incorporating serpentine suspension: An integrated circuit (IC) carrier assembly includes a printed circuit board (PCB). A carrier is soldered to the PCB. The carrier includes a grid of electrical contact islands surrounding a receiving zone for receiving an IC. Pairs of adjacent islands are interconnected by respective resilient suspension means. Each resilient suspension... Agent: Silverbrook Research Pty Ltd

20070284726 - Integrated circuit package system with post-passivation interconnection and integration: An integrated circuit package system including: providing an integrated circuit die, forming a first layer over the integrated circuit die, forming a bridge on and in the first layer, forming a second layer on the first layer, and forming bump pads on and in the second layer, the bump pads... Agent: Ishimaru & Zahrt LLP

20070284728 - Flip-chip bonding structure using multi chip module-deposited substrate: An MCM-D substrate in accordance with the present invention includes a silicon substrate provided with a Si-bump and a ground bump formed thereon, an insulating layer formed on the silicon substrate, a metal layer patterned on the insulating layer, a dielectric layer, a transmission line, a flip-chip bonding bump and... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070284727 - Printed circuit board with coextensive electrical connectors and contact pad areas: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.... Agent: Vierra Magen/sandisk Corporation

20070284729 - Semiconductor structure and method for forming the same: Example embodiments are directed to a method of forming a semiconductor structure and a semiconductor structure including a semiconductor unit including a protrusion on a front side of the semiconductor unit and a recess on a backside of the semiconductor unit.... Agent: Harness, Dickey & Pierce, P.L.C

20070284730 - Method, apparatus, and system for thin die thin thermal interface material in integrated circuit packages: Some embodiments of the invention include a thermal interface between a heat spreader and a die. The thermal interface may include a main layer of a single material or a combination of multiple materials. The thermal interface may include one or more additional layers covering one or more surfaces of... Agent: Schwegman, Lundberg & Woessner, P.A.

20070284731 - Power module: The mounting structure of a power device is simplified so as to reduce cost while achieving improvements in heat dissipation and reliability. A power module 100 is comprised of a metal wiring board 13, a power device 11 disposed on an upper surface of the metal wiring board 13 via... Agent: Oliff & Berridge, PLC

20070284733 - Method of making thermally enhanced substrate-base package: An array-type package encasing one or more semiconductor devices. The package includes a dielectric substrate having opposing first and second sides with a plurality of electrically conductive vias and a centrally disposed aperture extending from the first side to the second side. A heat slug has a mid portion extending... Agent: Wiggin And Dana LLP Attention: Patent Docketing

20070284732 - Semiconductor device, heat dissipating unit, and method for making a heat dissipating unit: A heat dissipating unit includes a hat-shaped body of a metal layered structure having: a copper alloy layer having upper and lower surfaces; a nickel layer formed on the upper surface of the copper alloy layer; a chrome layer formed on the nickel layer; and a metal oxide layer formed... Agent: Townsend And Townsend And Crew, LLP

20070284734 - Integrated circuit interconnect: An embodiment of an integrated circuit comprises active components in more than one active layer. A first conductor in one active layer is operative to produce a static electric field that controls a first active element in an adjacent active layer.... Agent: Hewlett Packard Company

20070284735 - Semiconductor device: A semiconductor device (1, 1A, 21, 31, 41, 51) provided with a first semiconductor chip (3) having a first functional surface (3F) formed with a first functional element (3a), a protective resin layer (12) provided on the first functional surface, and an external connection terminal (10, 19, 52) provided on... Agent: Rabin & Berdo, PC

20070284736 - Enhanced mechanical strength via contacts: The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of... Agent: International Business Machines Corporation Dept. 18g

20070284737 - Void reduction in indium thermal interface material: Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium... Agent: Timothy M Honeycutt Attorney At Law

20070284738 - Wiring board method for manufacturing the same, and semiconductor device: A wiring board includes an insulating base; an adhesive layer formed on the surface of the insulating base; a conductor wiring formed on the surface of the adhesive layer; and a bump formed crossing the longitudinal direction of the conductor wiring over regions on the adhesive layer on both sides... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070284739 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: North America Intellectual Property Corporation

20070284741 - Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same: A ball-limiting metallurgy (BLM) stack is provided for an electrical device. The BLM stack resists tin migration toward the metallization of the device. A solder system is also provided that includes a eutectic-Pb solder on a substrate that is mated to a high-Pb solder, and that withstands higher temperature reflows... Agent: Schwegman, Lundberg & Woessner, P.A.

20070284740 - Semiconductor device with improved contacts: A device with a solder joint made of a copper contact pad (210) of certain area (202) and an alloy layer (301) metallurgically attached to the copper pad across the pad area. The alloy layer contains copper/tin alloys, which include Cu6Sn5 intermetallic compound, and nickel/copper/tin alloys, which include (Ni,Cu)6Sn5 intermetallic... Agent: Texas Instruments Incorporated

20070284742 - Semiconductor device and active matrix display device: A semiconductor device includes a semiconductor layer, an Al alloy film electrically connected to the semiconductor layer, and a transparent electrode layer directly contacting with the Al alloy film at least over an insulating substrate. The Al alloy film includes one or more kinds of elements selected from Fe, Co... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070284744 - Apparatus for an improved air gap interconnect structure: In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one... Agent: Intel/blakely

20070284743 - Fabricating memory devices using sacrificial layers and memory devices fabricated by same: A protection layer is formed on a semiconductor substrate having a cell array region and an alignment key region. A plurality of data storage elements are formed on the protection layer in the cell array region. An insulating layer is formed on the data storage elements, a barrier layer is... Agent: Myers Bigel Sibley & Sajovec

20070284745 - Semiconductor device having a resistance for equalizing the current distribution: A first insulating substrate is formed on a heat sink, and a semiconductor element is formed thereon. An insulating resin casing is formed so as to cover the first insulating substrate and the semiconductor element. A second insulating substrate is mounted inside the insulating resin casing apart from the first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070284746 - Nano-electrode-array for integrated circuit interconnects: An integrated circuit is provided including an integrated circuit having a trench and via provided in a dielectric layer. A nano-electrode-array is over the dielectric layer in the trench and via, and a conductor is over the nano-electrode-array. The conductor and the nano-electrode-array are coplanar with a surface of the... Agent: Ishimaru & Zahrt LLP

20070284748 - Copper interconnects with improved electromigration lifetime: The peeling stress between a Cu line and a capping layer thereon, after via patterning, is reduced by varying the shape of the via and positioning the via to increase the space between the via and the line edge, thereby increasing electromigration lifetime. Embodiments include varying the shape of the... Agent: Mcdermott Will & Emery LLP

20070284747 - Integrated circuit having improved interconnect structure: An improved integrated circuit structure and method of making the same is provided. The integrated circuit structure comprises a substrate, the substrate having a top surface and a bottom surface. The top surface has a circuit device formed thereon. The structure includes a plurality of metallization layers, a bonding structure... Agent: Duane Morris LLPIPDepartment (tsmc)

20070284749 - Semiconductor device having no cracks in one or more layers underlying a metal line layer and method of manufacturing the same: A semiconductor device and a method of manufacturing the same which yields high reliability and a high manufacturing yield. The semiconductor device includes a metal line layer having a plurality of metal line patterns spaced apart from each other, and at least one underlying layer under the metal line layer,... Agent: Lee & Morse, P.C.

20070284750 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: North America Intellectual Property Corporation

20070284751 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: North America Intellectual Property Corporation

20070284752 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: North America Intellectual Property Corporation

20070284753 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: North America Intellectual Property Corporation

20070284754 - Power mosfet contact metallization: A structure includes a semiconductor device formed in a substrate; an insulator adjacent to the semiconductor device; an electrical contact electrically coupled to the semiconductor device, wherein the electrical contact includes tungsten; and an electrical connector coupled to the electrical contact, wherein the electrical connector includes aluminum. A surface of... Agent: Murabito Hao & Barnes LLP

20070284755 - Semiconductor device, manufacturing method of the semiconductor device, and mounting method of the semiconductor device: A semiconductor device, including a semiconductor substrate where a plurality of functional elements is formed; and a multilayer interconnection layer provided over the semiconductor substrate, the multilayer interconnection layer including a wiring layer mutually connecting the plural functional elements and including an interlayer insulation layer, wherein a region where the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070284756 - Stacked chip package: A stacked chip package is provided. The metal bumps disposed on the lower chip are encapsulated by a layer of non-conductive adhesive and the area around by the layer of non-conductive adhesive material is filled with another adhesive. Under such a configuration, it can prevent the upper chip from contacting... Agent: Lowe Hauptman Ham & Berner, LLP

20070284757 - Electronic circuit arrangement and method for producing it: Electronic circuit arrangement, includes a chip and a chip carrier having a substrate and a chip contact location. At least the chip contact location is provided with a soldering layer. The chip includes a bonding layer. A silver layer for eutectic bonding with the bonding layer is provided on the... Agent: Slater & Matsil LLP

20070284758 - Electronics package and associated method: An electronics package is provided. The electronics package may include an underfill layer having a surface that defines an opening. The electronics package may include a polymer bump structure disposed within the opening. A laminate for use as an underfill layer is provided. Associated methods are provided.... Agent: General Electric Company Global Research

20070284759 - Method for producing sheet with ic tags, apparatus for producing sheet with ic tags, sheet with ic tags, method for fixing ic chips, apparatus for fixing ic chips, and ic tag: A method of producing a sheet 1 with IC tags comprises the steps of: preparing and feeding a sheet 21a with electrical conductors formed thereon; providing an adhesive 18 on the sheet 21a with electrical conductors; preparing multiple IC chips 20 and successively feeding the IC chips 20; successively arranging... Agent: Oliff & Berridge, PLC

20070284760 - Chip and flat panel display apparatus comprising the same: A chip electrically connected to wires on a substrate without errors and a flat panel display apparatus including the chip is provided. The chip includes a plurality of bumps that protrude from the chip and have different heights. The flat panel display apparatus may include pads with variable heights on... Agent: Knobbe Martens Olson & Bear LLP

20070284761 - Functional device: A functional device includes plural substrates, an encapsulant arranged between the plurality of substrates, and a functional material arranged between the plural of substrates and encapsulated with the encapsulant. The functional device further includes an insulating spacer arranged in an entire region where the encapsulant lies, and the insulating spacer... Agent: Wolf Greenfield & Sacks, P.C.

20070284763 - Driving circuit and liquid crystal display device including the same: A tape carrier package (TCP) includes a film, a plurality of output leads and a plurality of input leads on the film, the plurality of output leads and the plurality of input leads being disposed on different sides, first and second TCP alignment marks arranged on opposing sides of the... Agent: Morgan Lewis & Bockius LLP

20070284764 - Driving circuit and liquid crystal display device including the same: A sensing mechanism for crystal orientation indication mark of semiconductor wafer is provided. The semiconductor wafer includes: a device region formed on a surface of the semiconductor wafer, plural devices are formed or are to be formed on the surface; a circular peripheral extra region formed around the device region;... Agent: Brinks Hofer Gilson & Lione

20070284762 - Semiconductor seal ring: An improved semiconductor seal ring and method therefore is described. The seal ring comprises a thick layer wherein at least a portion of the thick layer is removed from a singulation street prior to singulation, thereby avoiding damage to the thick layer during the singulation process. A thin moisture-proof barrier... Agent: Farjami & Farjami LLP

20070278469 - Component containing a baw filter: A monolithic assembly of electronic components including a semiconductor substrate, at a first level above the substrate, at least one bulk acoustic wave resonator, at a second level above the resonator, a single-crystal semiconductor layer in which are formed semiconductor components, and recesses under the semiconductor layer portions arranged above... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070278471 - Novel chalcogenide material, switching device and array of non-volatile memory cells: A novel chalcogenide material has a bulk composition which has a first material selected from the group of Si and Sn, a second material selected from the group of Sb, and a third material selected from the group of Te. The first material, second material, and third material are in... Agent: Dla Piper US LLP

20070278473 - Light emitting device and method of manufacturing the same: A light emitting device comprises an anode electrode layer disposed in a first direction, a cathode electrode layer disposed in a second direction different from the first direction, an emitting area with a pixel forming on an area crossed by the anode electrode layer and the cathode electrode layer and... Agent: Ked & Associates, LLP

20070278475 - Semiconductor light-emitting device: A semiconductor light-emitting device includes: a semiconductor light-emitting element including a first conductive type semiconductor layer, an active layer including a light-emitting region, and a second conductive type semiconductor layer in this order; a filter having a transmission characteristic in which the transmittance in a direction parallel to the optical... Agent: Rader Fishman & Grauer PLLC

20070278481 - Organic electronic device: Disclosed is an organic electronic device, in which a semiconductor layer and source/drain electrodes may be formed from materials of the same type, suitable for a room-temperature wet process, and thus have surface properties similar to each other, thereby decreasing contact resistance between the semiconductor layer and the source/drain electrodes.... Agent: Harness, Dickey & Pierce, P.L.C

20070278480 - Organic light emitting display and method of manufacturing the same: In an organic light emitting display, the process of forming a storage capacitor is simplified, and deterioration of the properties and the reliability of the TFT is prevented. The organic light emitting display includes a substrate, a thin film transistor formed on one portion of the substrate, the thin film... Agent: Robert E. Bushnell

20070278482 - Organic memory devices including organic material and fullerene layers and related methods: An organic memory device may include a stack of an organic material layer and a fullerene layer to provide a data storage element between first and second electrodes. The data storage element may include an organic material layer formed on the first electrode, and a fullerene layer between the organic... Agent: Myers Bigel Sibley & Sajovec

20070278484 - Method and test structure for estimating electromigration effects caused by porous barrier materials: By providing a test structure for electromigration tests in semiconductor devices, which may indicate the status of a barrier layer at the bottom of a test via in the structure, a significantly increased reliability of respective electromigration tests may be obtained. Furthermore, the degree of porosity of the barrier layer... Agent: J. Mike Amerson, Williams, Morgan & Amerson P.C.

20070278485 - Substrate, substrate inspecting method and methods of manufacturing an element and a substrate: A substrate inspection method allowing inspection of all a plurality of substrates each provided at its surface with a plurality of layers by determining quality of the plurality of layers as well as methods of manufacturing the substrate and an element using the substrate inspection method are provided. The substrate... Agent: Mcdermott Will & Emery LLP

20070278488 - Electro-optical device and electronic apparatus: An electro-optical device includes pixel regions arranged at intersections of a plurality of data lines and a plurality of scanning lines on an element substrate. A sensor element, a sensor signal line for outputting a signal from the sensor element, and a common wiring line are disposed at an end... Agent: Oliff & Berridge, PLC

20070278487 - Thin film transistor substrate and method of manufacturing thereof: A thin film transistor substrate and a method of manufacturing the thin film transistor substrate comprises forming a gate line and a data line intersecting each other with a gate insulating layer interposed and defining a pixel area on the substrate, a thin film transistor electrically connected to the gate... Agent: Macpherson Kwok Chen & Heid LLP

20070278493 - Light-emitting element and display device: An object is to provide a light-emitting element having high light extraction efficiency. Further, an object is to provide a light-emitting element and a display device having high luminance and low power consumption. A light-emitting element of the present invention includes a light-emitting layer interposed between a first and second... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070278491 - Spacing architecture for liquid crystal display and spacing method thereof: A liquid crystal display is provided. A liquid crystal display includes a first substrate having color filters therewith; a second substrate having plural first signal lines and plural second signal lines thereon; plural first openings located at intersections of said first signal lines and plural of second signal lines; and... Agent: Volpe And Koenig, P.C.

20070278492 - Thin film transistor array panel and method of manufacturing the same: A thin film transistor array panel including a substrate, a plurality of data lines disposed on the substrate, an interlayer insulating layer disposed on the data lines and including contact holes through which the data lines are exposed, a plurality of source electrodes, each of the source electrodes disposed on... Agent: Cantor Colburn, LLP

20070278498 - Light emitting device, electronic apparatus, and manufacturing method of light emitting device: A light emitting device including a thin film transistor and an inorganic EL element, and a manufacturing method thereof. The present invention provides a manufacturing method of a light emitting device, including a step of forming a light emitting layer including at least a layer made from an inorganic fluorescent... Agent: Fish & Richardson P.C.

20070278496 - Light emitting diode: A light emitting diode is disclosed. The light emitting diode includes a substrate, a thermal spreading layer disposed on the bottom of the substrate, a soldering layer disposed on the bottom of the thermal spreading layer, a barrier layer disposed between the thermal spreading layer and the soldering layer, and... Agent: North America Intellectual Property Corporation

20070278499 - Nitride-based semiconductor light emitting diode: A nitride-based semiconductor LED comprises an anode; a first p-type clad layer having a second n-type clad layer coming in contact with the anode, the first p-type clad layer being formed under the anode such that a portion of the first p-type clad layer comes in contact with the anode;... Agent: Staas & Halsey LLP

20070278497 - Thin film transistor substrate and display device: Disclosed are a thin film transistor substrate where barrier metal can be omitted to be formed between a semiconductor layer of a thin film transistor and source and drain electrodes (barrier metal need not be formed between the semiconductor layer of the thin film transistor and the source and drain... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070278500 - Package module of light emitting diode: A package module of a light emitting diode includes a substrate, a first light emitting diode and a transistor. The first light emitting diode is disposed on the substrate, and the transistor is electrically connected with the first light emitting diode. The transistor is disposed on the substrate and turns... Agent: Birch Stewart Kolasch & Birch

20070278507 - Field effect transistor and method for fabricating the same: A field effect transistor includes a nitride semiconductor layered structure that is formed on a substrate and includes a capping layer made of a compound represented by a general formula of InxAlyGa1-yN (wherein 0<x≦1, 0≦y <1 and 0<x+y≦1). A non-alloy source electrode and a non-alloy drain electrode are formed on... Agent: Mcdermott Will & Emery LLP

20070278512 - Packaged light emitting devices including multiple index lenses and methods of fabricating the same: A packaged light emitting device includes a substrate, a solid state light emitting device on the substrate, a first generally toroidal lens on the substrate and defining a cavity relative to the solid state light emitting device and having a first index of refraction, and a second lens at least... Agent: Myers Bigel Sibley & Sajovec

20070278470 - Phase-change memory device and manufacturing process thereof: A phase-change memory cell is formed by a phase-change memory element and by a selection element, which is formed in a semiconductor material body and is connected to the phase-change memory element. The phase-change memory element is made up of a calcogenic material layer and a heater. The selection element... Agent: Seed Intellectual Property Law Group PLLC

20070278472 - Soft switching semiconductor component with high robustness and low switching losses: A semiconductor component includes a semiconductor body and a second semiconductor zone of a first conductivity type that serves as a rear side emitter. The second semiconductor zone is preceded by a plurality of third semiconductor zones of a second conductivity type that is opposite to the first conductivity type.... Agent: Edell, Shapiro & Finnan, LLC

20070278474 - Semiconductor light emitting element: A semiconductor light emitting element includes an active layer of a quantum well structure, and an n-type semiconductor layer and a p-type semiconductor layer, formed to hold the active layer therebetween. The active layer includes at least a well layer containing InGaN, and at least two barrier layers formed to... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20070278476 - Optoelectronic devices utilizing materials having enhanced electronic transitions: An optoelectronic device that includes a material having enhanced electronic transitions. The electronic transitions are enhanced by mixing electronic states at an interface. The interface may be formed by a nano-well, a nano-dot, or a nano-wire.... Agent: Los Alamos National Security, LLC

20070278478 - Ambipolar, light-emitting field-effect transistors: An ambipolar, light-emitting transistor comprising an organic semiconductive layer in contact with an electron injecting electrode and a hole injecting electrode separated by a distance L defining the channel length of the transistor, in which the zone of the organic semiconductive layer from which the light is emitted is located... Agent: Sughrue Mion, PLLC

20070278483 - Light emitting device and method of manufacturing the same: A light emitting device of the present invention includes a first conductive film, a second conductive film, a half-etching hole, a light emitting element, through-hole electrodes, conductive metal layers, metallic wires and a transparent protective resin. The first conductive film is thick, and is provided on one main surface of... Agent: Morrison & Foerster LLP

20070278479 - N-doping of organic semiconductors: The invention relates to a process for producing doped organic semiconductor materials with an elevated charge carrier density and effective charge carrier mobility by doping, in which the doping agent is substantially produced by electrocrystallization in a first step, the doping agent is selected from a group of organic compounds... Agent: Sutherland Asbill & Brennan LLP

20070278477 - Organic semiconductor light-emitting device: A light-emitting device having an organic semiconductor layer and a control electrode electrically coupled to the semiconductor layer, the organic semiconductor layer being provided between a first electrode and an emission layer and having an absorption band within an emission wavelength band of the emission layer.... Agent: Drinker Biddle & Reath (dc)

20070278486 - Scanning head for optical position-measuring systems: A scanning head for an optical position-measuring system includes a receiver grating, formed of photosensitive areas, for the scanning of locally intensity-modulated light of differing wavelengths. The receiver grating is formed from a semiconductor layer stack of a doped p-layer, an intrinsic i-layer and a doped n-layer. The individual photosensitive... Agent: Kenyon & Kenyon LLP

20070278489 - Display device: A structure for preventing deteriorations of a light-emitting device and retaining sufficient capacitor elements (condenser) required by each pixel is provided. A first passivation film, a second metal layer, a flattening film, a barrier film, and a third metal layer are stacked in this order over a transistor. A side... Agent: Nixon Peabody, LLP

20070278490 - Semiconductor device including active layer of zinc oxide with controlled crystal lattice spacing and manufacturing method thereof: A semiconductor device includes an oxide semiconductor thin film layer of zinc oxide. The (002) lattice planes of at least a part of the oxide semiconductor thin film layer have a preferred orientation along a direction perpendicular to a substrate of the semiconductor device and a lattice spacing d002 of... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070278494 - Single-crystal layer on a dielectric layer: The process relates to the production of a layer of a single-crystal first material on a second material. The second material has at least one aperture exposing a surface portion of a single-crystal third material. The process generally includes forming an at least partially crystalline first layer of said first... Agent: Docket Clerk

20070278495 - Thin film transistor formed on flexible substrate and method of manufacturing the same: A thin film transistor (“TFT”) includes a poly silicon layer formed on a flexible substrate and including a source region, a drain region, and a channel region, and a gate stack formed on the channel region of the poly silicon layer, wherein the gate stack includes first and second gate... Agent: Cantor Colburn, LLP

20070278501 - Electronic device including a guest material within a layer and a process for forming the same: An electronic device made by a process that includes forming a first layer over a substrate and placing a first liquid composition over a first portion of the first layer. The first liquid composition includes at least a first guest material and a first liquid medium. The first liquid composition... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070278503 - Lighting device and lighting method: A lighting device, comprising a first group of solid state light emitters and a first group of lumiphors, wherein at least some of the first group of solid state light emitters are contained in a first group of packages, each of which also comprises at least one of the first... Agent: Burr & Brown

20070278502 - Semiconductor light emitting device: There is provided a semiconductor light emitting device which can prevent flickering in illumination due to an alternative current drive, and sensing incongruity at a time of turning off a switch, by providing anti-flickering means in itself, when it is assembled in an illumination device without any extra parts therein.... Agent: Rabin & Berdo, PC

20070278504 - Methods and systems relating to solid state light sources for use in industrial processes: Methods and systems relating to solid state light sources for use in industrial processes.... Agent: Ganz Law, P.C.

20070278505 - Light-emitting diode array, light-emitting diode, and printer head: A light emitting diode array in which, when viewed from the above, the shape of an almost square light emitting diode is square-chamfered or round-chamfered at the corners thereof in order to minimize light leakage at a reverse mesa surface to allow an electrode layer to surround the three directions... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070278506 - Vertical light emitting diode device structure: A vertical light-emitting diode (VLED) structure that may impart increased luminous efficiency over conventional LEDs and VLEDs is described. As additional benefits, some embodiments may have less susceptibility to electrostatic discharge (ESD) and higher manufacturing yields than conventional devices. To accomplish these benefits, embodiment of the invention may utilize a... Agent: Patterson & Sheridan, L.L.P.

20070278508 - Thin film led comprising a current-dispersing structure: A thin-film LED comprising an active layer (7) made of a nitride compound semiconductor, which emits electromagnetic radiation (19) in a main radiation direction (15). A current expansion layer (9) is disposed downstream of the active layer (7) in the main radiation direction (15) and is made of a first... Agent: Cohen, Pontani, Lieberman & Pavane

20070278509 - Group iii nitride semiconductor light-emitting device and method of producing the same: A Group III nitride semiconductor light-emitting device includes a stacked structure 11 formed on a crystal substrate (100) to be removed from it and including two Group III nitride semiconductor layers 104 and 106 having different electric conductive types and a light-emitting layer 105 which is stacked between the two... Agent: Sughrue Mion, PLLC

20070278510 - Light emitting device and a lighting apparatus: The present invention provides in one embodiment a light emitting device that has a high efficacy even in a range of low color temperatures, a long-term reliability, and an improved color rendering property. In addition, the present invention provides in another embodiment a lighting apparatus using such a light emitting... Agent: Sughrue Mion, PLLC

20070278511 - Light-emitting device manufacturing method and light-emitting device: A method for producing a light-emitting device comprising: a step of electrically connecting a first electrode provided on one main surface of a semiconductor substrate (element substrate) through a light-emitting layer, and a first lead of a lead frame, so as to oppose each other; a step of electrically connecting... Agent: Reed Smith LLP

20070278513 - Semiconductor light emitting device and method of fabricating the same: There is provided a method that allows fabrication, through a simple process, of a good quality semiconductor light emitting device having a semiconductor light emitting element surrounded and thus covered with a fluorescent layer formed of resin uniform in thickness. At least two semiconductor light emitting elements are bonded to... Agent: Morrison & Foerster LLP

20070278515 - Silicon controlled rectifier protection circuit: In one embodiment, the present invention includes an apparatus having a protection circuit to provide protection from transient surges. The protection circuit may include a silicon controlled rectifier (SCR) that is formed on a substrate via a planar process, along with one or more circuits to be protected by the... Agent: Trop Pruner & Hu, PC

20070278514 - Semiconductor component comprising a temporary field stopping area, and method for the production thereof: The invention relates to a semiconductor component comprising a buried temporarily n-doped area (9), which is effective only in the event of turn-off from the conducting to the blocking state of the semiconductor component and prevents chopping of the tail current in order thus to improve the turn-off softness. Said... Agent: Maginot, Moor & Beck

20070278516 - Semiconductor device and power source unit using the same: The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the... Agent: Townsend And Townsend And Crew, LLP

20070278517 - Hetero-integrated strained silicon n- and p- mosfets: The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions... Agent: Scully, Scott, Murphy & Presser, P.C.

20070278522 - Semiconductor device: In relation to the conventional semiconductor device provided with a plurality of FETS, there is room for improving the pair accuracy of the FET-pair. A semiconductor device includes a first FET, a second FET, a third FET and a fourth FET. The four FETs are provided in an active region... Agent: Mcginn Intellectual Property Law Group, PLLC

20070278521 - Transistor: There is provided a normally-off type transistor made of a nitride semiconductor. The transistor includes: an undoped GaN layer which forms a channel region; an undoped Al0.2Ga0.8N layer which is formed on the undoped GaN layer and has a band gap larger than that of the undoped GaN layer; a... Agent: Greenblum & Bernstein, P.L.C

20070278519 - Enhancement depletion field effect transistor structure and method of manufacture: The invention relates to a transistor structure with both enhancement and depletion mode transistors. In order to allow good control over the manufacture of both transistors, a first Schottky layer (10) and a second Schottky layer (12) are used made of first and second semiconductor materials respectively. The first and... Agent: Philips Intellectual Property & Standards

20070278518 - Enhancement-mode iii-n devices, circuits, and methods: A method of fabricating AlGaN/GaN enhancement-mode heterostructure field-effect transistors (HFET) using fluorine-based plasma immersion or ion implantation. The method includes: 1) generating gate patterns; 2) exposing the AlGaN/GaN heterostructure in the gate region to fluorine-based plasma treatment with photoresist as the treatment mask in a self-aligned manner; 3) depositing the... Agent: Groover & Holmes

20070278520 - Field effect transistor having multiple pinch off voltages: A compound field effect transistor having multiple pinch-off voltages comprising: first and second field effect transistors, each field effect transistor comprising a semiconductor layer, the semiconductor layer having an electrically conducting layer therein; an ohmic contact layer on the semiconductor layer; a source and a drain on the ohmic contact... Agent: Howard & Howard Attorneys, P.C.

20070278523 - Structure and a method for monolithic integration of hbt, depletion-mode hemt and enhancement-mode hemt on the same substrate: An epitaxial layers structure and a method for fabricating HBTs and HEMTs on a common substrate are disclosed. The epitaxial layers comprise generally a set of HBT layers on the top of a set of HEMT layers. The method can be used to fabricate HBT, E-mode HEMT and D-mode HEMT... Agent: Bacon & Thomas, PLLC

20070278524 - Recessed drain extensions in transistor device: A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms... Agent: Texas Instruments Incorporated

20070278525 - High-efficiency filler cell with switchable, integrated buffer capacitance for high frequency applications: A cell based integrated circuit chip includes a top voltage supply rail and a bottom voltage supply rail and a plurality of metal layers defining at least one filler cell. The filler cell is formed by a first field effect transistor of a first type conductivity, typically an n-channel MOSFET.... Agent: Brinks Hofer Gilson & Lione Infineon

20070278526 - Methods of making semiconductor-based electronic devices on a wire and articles that can be made using such devices: Strands of active electronic devices (AEDs), such as FETs, are made by first completely or partially forming a plurality of the AEDs on a precursor substrate. Then, one or more elongate conductors (e.g., wires) are secured to ones of the AEDs so as to electrically connected the AEDs together. After... Agent: Downs Rachlin Martin PLLC

20070278527 - Complementary misfet and integrated circuit: Integrated circuits such as semiconductor memories, image sensors, PLA's, and the like have been formed on rigid, planar substrates such as silicon substrates. This has resulted in shapes without flexibility and limited applicabilities. Further, since multiple circuit elements are continuously formed on a flat surface, it has been impossible to... Agent: Young & Thompson

20070278528 - Semiconductor device: A semiconductor device of the present invention comprises a logic circuit to which a power supply voltage, a sub-power supply voltage, a ground voltage and a sub-ground voltage are supplied; a driver for generating the sub-power supply voltage and the sub-ground voltage based on the power supply voltage and the... Agent: Mcginn Intellectual Property Law Group, PLLC

20070278529 - Resistor random access memory cell with l-shaped electrode: A phase change random access memory PCRAM device is described suitable for use in large-scale integrated circuits. An exemplary memory device has a pipe-shaped first electrode formed from a first electrode layer on a sidewall of a sidewall support structure. A sidewall spacer insulating member is formed from a first... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070278530 - Memory device, in particular phase change random access memory device with transistor, and method for fabricating a memory device: A memory device, in particular to a resistively switching memory device such as a Phase Change Random Access Memory (“PCRAM”), with a transistor is disclosed. Further, the invention relates to a method for fabricating a memory device. According one embodiment of the invention, a memory device is provided, having at... Agent: Dicke, Billig & Czaja

20070278531 - Semiconductor flash memory device and method of fabricating the same: A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070278532 - Field-effect transistor, semiconductor device, a method for manufacturing them, and a method of semiconductor crystal growth: A field-effect transistor which comprises a buffer layer and a barrier layer each of which is made of a Group III nitride compound semiconductor and has a channel at the interface inside of the buffer layer to the barrier layer, wherein the barrier layer has multiple-layer structure comprising an abruct... Agent: Mcginn Intellectual Property Law Group, PLLC

20070278533 - Mos type solid-state image pickup device and driving method comprised of a photodiode, a detection portion, and a tranfer transistor: An MOS type solid-state image pickup device including pixels each of which comprises a photodiode PD, a detection portion N and a transfer transistor QT for transferring the charges accumulated in the photodiode PD to the detection portion N, wherein the gate voltage of the transfer transistor QT when the... Agent: Sonnenschein Nath & Rosenthal LLP

20070278534 - Low crosstalk, front-side illuminated, back-side contact photodiode array: The present invention is directed to novel front side illuminated, back side contact photodiodes and arrays thereof In one embodiment, the photodiode has a substrate with at least a first and a second side and a plurality of electrical contacts physically confined to the second side. The electrical contacts are... Agent: Patentmetrix

20070278535 - Solid-state imaging device and imaging apparatus: A CCD type solid-state imaging device includes: a photoelectric conversion element (n layer 2, p layer 3) formed in a semiconductor substrate 1; a charge transfer channel 5 that transfers electric charges generated in the photoelectric conversion element; a charge read region 6 that reads out the electric charges accumulated... Agent: Birch Stewart Kolasch & Birch

20070278537 - Image sensor having reset transistor: An image sensor includes a reset transistor, reset gate electrodes and a potential shift circuit. The reset transistor includes a reset gate and a reset drain, and resets charges detected by a charge detection device. The reset gate electrodes control a potential of the reset gate. The potential shift circuit... Agent: Young & Thompson

20070278536 - Solid state image pickup device and operating method thereof: This invention provides a type of solid-state image pickup device characterized by the fact that for a solid-state image pickup device with a broad dynamic range, it is possible to suppress the dark current than photoelectrons overflowing from the photodiode, as well as its driving method. Plural pixels are integrated... Agent: Texas Instruments Incorporated

20070278538 - Phase change memory cell: A phase change memory cell is disclosed, including a first electrode and a second electrode, and a plurality of recording layers disposed between the first and second electrodes. The phase of an active region of each of the recording layers can be changed to a crystalline state or an amorphous... Agent: Quintero Law Office, PC

20070278539 - Junction field effect transistor and method for manufacture: A semiconductor device is described that operates as an improved junction field effect transistor (JFET). A bipolar transistor with a collector region, a base region, an emitter region, a first base contact, and a second base contact insulated from the first base contact, has the base region lightly doped to... Agent: Priest & Goldstein, PLLC

20070278540 - Vertical junction field effect transistors, and methods of producing the vertical junction field effect transistors: A vertical JFET 1a according to the present invention has an n+ type drain semiconductor portion 2, an n-type drift semiconductor portion 3, a p+ type gate semiconductor portion 4, an n-type channel semiconductor portion 5, an n+ type source semiconductor portion 7, and a p+ type gate semiconductor portion... Agent: Fish & Richardson, PC

20070278542 - Semiconductor device and fabricating method thereof: There is provided a semiconductor device including: a semiconductor substrate including a supporting substrate, a first insulating film formed on the supporting substrate, and a silicon film having a first region and a second region formed on the first insulating film, and a third region at least a portion of... Agent: Rabin & Berdo, PC

20070278541 - Spacer engineering on cmos devices: A MOS device having a reduced LDD dopant diffusion length and a method for forming the same are provided. The MOS device includes a gate stack over a semiconductor substrate, a spacer liner on a sidewall of the gate stack and having a portion over the semiconductor substrate, and a... Agent: Slater & Matsil, L.L.P.

20070278543 - Solid state imaging device: A solid-state imaging device includes a semiconductor substrate, photodetector elements, and blocking layers. The solid-state imaging device receives light on the back surface, and photoelectrically converts light incident upon the back surface of the semiconductor substrate, thereby acquiring an image of an object to be imaged. The photodetector elements receive... Agent: Young & Thompson

20070278544 - Solid state image pickup device inducing an amplifying mos transistor having particular conductivity type semiconductor layers, and camera using the same device: To provide an amplification type solid state image pickup device enabling lower noise, higher gain, and higher sensitivity than any conventional amplification type solid state image pickup device. A solid state image pickup device according to the present invention includes an arrangement of a plurality of unit pixels each of... Agent: Fitzpatrick Cella Harper & Scinto

20070278545 - Ferroelectric capacitor, method of manufacturing ferroelectric capacitor, and ferroelectric memory: A ferroelectric capacitor including: a substrate; a first electrode formed above the substrate; a first ferroelectric layer formed above the first electrode and including a complex oxide shown by Pb(Zr,Ti)O3; a second ferroelectric layer formed above the first ferroelectric layer and including a complex oxide shown by Pb(Zr,Ti)1-xNbxO3; and a... Agent: Harness, Dickey & Pierce, P.L.C

20070278546 - Memory cell array and method of forming a memory cell array: A memory cell array includes a plurality of first conductive lines running in a first direction, where the first conductive lines have a pitch Bp, a plurality of second conductive lines, and a plurality of memory cells. Each of the memory cells are at least partially formed in a semiconductor... Agent: Edell, Shapiro & Finnan, LLC

20070278547 - Mram synthetic anitferomagnet structure: An MRAM bit (10) includes a free magnetic region (15), a fixed magnetic region (17) comprising an antiferromagnetic material, and a tunneling barrier (16) comprising a dielectric layer positioned between the free magnetic region (15) and the fixed magnetic region (17). The MRAM bit (10) avoids a pinning layer by... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070278548 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and... Agent: F. Chau & Associates, LLC

20070278549 - Integrated circuit with a transistor structure element: An integrated semiconductor memory includes at least one memory cell having at least one transistor which forms an inversion channel in the switched-on state. The transistor comprises a structure element having a first source/drain region, a second source/drain region, and a region arranged between the first and the second source/drain... Agent: Edell, Shapiro & Finnan, LLC

20070278550 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a semiconductor element having first and second surfaces, wherein the semiconductor element includes at least one electrode, which is disposed on one of the first and second surfaces; and first and second metallic layers, wherein the first metallic layer is disposed on the first surface of... Agent: Posz Law Group, PLC

20070278551 - Metal-insulator-metal capacitors: An interdigitated Metal-Insulator-Metal (MIM) capacitor provides self-shielding and accurate capacitance ratios with small capacitance values. The MIM capacitor includes two terminals that extend to a plurality of interdigitated fingers separated by an insulator. Metal plates occupy layers above and below the fingers and connect to fingers of one terminal. As... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20070278552 - Spacer patterned, high dielectric constant capacitor: A method for fabricating a contact of a semiconductor device structure includes forming a barrier layer that is entirely recessed within a contact aperture. A central region of the barrier layer may be recessed relative to at least a portion of an outer periphery of the barrier layer. Semiconductor device... Agent: Trask Britt, P.C./ Micron Technology

20070278553 - Semiconductor device and fabrication thereof: A memory device is disclosed. A floating gate is disposed overlying a substrate. A tunneling dielectric layer is interposed between the floating gate and the substrate. An inter poly dielectric layer is disposed overlying the floating gate and the substrate. A word line is disposed overlying the floating gate, extending... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070278554 - Semiconductor memory device and method of forming the same: Example embodiments are directed to a semiconductor memory device that may include a plurality of memory cells, each having a transistor of a first conductivity type with a first shape, a sub-word line driver including a transistor of the first conductivity type with a second shape and a transistor of... Agent: Harness, Dickey & Pierce, P.L.C

20070278555 - Non volatile semiconductor memory device: A non volatile semiconductor memory device wherein it is possible to transfer Vpp without a drop in voltage of the transfer transistor Vth (threshold voltage) in a transfer circuit or decoder circuit for selectively transferring Vpp by using a usual LVP (low voltage P type transistor) to reduce step(s) of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070278560 - Nonvolatile semiconductor storage device having silicide in control gate electrode: A nonvolatile semiconductor storage device includes a semiconductor substrate, and at least one memory cell formed on the semiconductor substrate, the at least one memory cell having a gate electrode unit in which a floating gate electrode and a control gate electrode are stacked, at least part of the control... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070278557 - Novel method to form memory cells to improve programming performance of embedded memory technology: An embedded memory device and method of forming MOS transistors having reduced masking requirements and defects using a single drain sided halo implant in the NMOS FLASH or EEPROM memory regions is discussed. The memory device comprises a memory region and a logic region. Logic transistors within the logic region... Agent: Texas Instruments Incorporated

20070278558 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a p-channel MIS transistor. A p-channel MIS transistor includes; an n-type semiconductor layer formed on the substrate; first source/drain regions being formed in the n-type semiconductor layer and being separated from each other; a first gate insulating film being formed on the n-type semiconductor layer between... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070278559 - Semiconductor memory device: A semiconductor memory device according to the present invention includes a first wiring region and a second wiring region located adjacent to the first wiring region. First lines located in the first wiring region include a first portion, a first lead portion and first inclined portion. Second lines located in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070278556 - Two bits non volatile memory cells and method of operating the same: A twin non-volatile memory cell on unit device and method of operating the same are disclosed. The device is formed in the n-well and compatible with CMOS processes comprising a selecting gate, two ONO spacers, a p+ source/drain, and n extended source/drain. To program the cells, two strategies can be... Agent: Jianq Chyun Intellectual Property Office

20070278561 - Flash memory device and method of manufacturing the same: A non-volatile memory device has a gate dielectric film formed between a floating gate and a control gate. The gate dielectric film is formed by forming an oxide film and a ZrO2/Al2O3/ZrO2 (ZAZ) film. Accordingly, the reliability of non-volatile memory devices can be improved while securing a high coupling ratio.... Agent: Townsend And Townsend And Crew, LLP

20070278562 - Nonvolatile semiconductor memory device and its manufacturing method: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate area floating gate via a first gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070278563 - Nonvolatile semiconductor memory device: An object is to provide a nonvolatile semiconductor memory device which is excellent in a writing property and a charge retention property. In addition, another object is to provide a nonvolatile semiconductor memory device capable of reducing writing voltage. A nonvolatile semiconductor memory device includes a semiconductor layer or a... Agent: Eric Robinson

20070278564 - Semiconductor device: This invention is to improve data retention properties of a nonvolatile memory cell having an ONO film. A first cavity is disposed, in a position between the nitride film serving as a charge storage film and a memory gate and below an end portion of the memory gate, adjacent to... Agent: Miles & Stockbridge PC

20070278565 - Semiconductor device having sub-surface trench charge compensation regions and method: In one embodiment, a semiconductor device is formed having sub-surface charge compensation regions in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two... Agent: Bradley J. Botsch Semiconductor Components Industries, LLC

20070278566 - Semiconductor device: A semiconductor device includes a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a trench formed from the surface of the barrier layer to such a depth as to reach a region in the vicinity of an interface... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070278567 - Method of fabricating semiconductor device: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070278568 - High-voltage bipolar-cmos-dmos integrated circuit devices and modular methods of forming the same: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and... Agent: Patentability Associates

20070278569 - Lateral dmos structure: A lateral DMOS structure includes a light doped p-type region beneath and near the gate at the drain side. The electric field on the surface near the gate is reduced. Thus the electric field near the gate decreases, and the SOA (safe operating area) of the lateral DMOS device increases... Agent: Birch Stewart Kolasch & Birch

20070278570 - High-voltage nmos-transistor and associated production method: An n-conductively doped source region (2) in a deep p-conducting well (DP), a channel region (13), a drift region (14) formed by a counterdoping region (12), preferably below a gate field plate (6) insulated by a gate field oxide (8), and an n-conductively doped drain region (3) arranged in a... Agent: Cohen, Pontani, Lieberman & Pavane

20070278572 - Asymmetric channel doping for improved memory operation for floating body cell (fbc) memory: An improved dynamic memory cell using a semiconductor fin or body is described. Asymmetrical doping is used in the channel region, with more dopant under the back gate to improve retention without significantly increasing read voltage.... Agent: Blakely Sokoloff Taylor & Zafman

20070278571 - Planar split-gate high-performance mosfet structure and manufacturing method: This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting... Agent: Bo-in Lin

20070278573 - High-voltage pmos transistor: In a high-voltage PMOS transistor having an insulated gate electrode (18), a p-conductive source (15) in an n-conductive well (11), a p-conductive drain (14) in a p-conductive well (12) which is arranged in the n-conductive well, and having a field oxide area (13) between the gate electrode and drain, the... Agent: Thomas Langer Cohen, Pontani, Lieberman & Pavane

20070278574 - Compound semiconductor-on-silicon wafer with a thermally soft insulator: A method is provided for forming a compound semiconductor-on-silicon (Si) wafer with a thermally soft insulator. The method forms a Si substrate, with a thermally soft insulator layer overlying the Si substrate. A silicon oxide layer is formed immediately overlying the thermally soft insulator layer, a top Si layer overlies... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070278576 - Fin field effect transistor and method for forming the same: Example embodiments are directed to a method of forming a field effect transistor (FET) and a field effect transistor (FET) including a source/drain pair that is elevated with respect to the corresponding gate structure.... Agent: Harness, Dickey & Pierce, P.L.C

20070278578 - Memory cell array, method of producing the same, and semiconductor memory device using the same: A memory cell array includes isolated semiconductor regions formed on a supporting insulating substrate, memory cells formed in the respective semiconductor regions, and insulating regions formed so as to insulate the memory cells. Each memory cell formed in a semiconductor region includes a source region, a drain region, a front... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070278577 - Semiconductor device and manufacturing method of the same: To reduce the adverse affect that characteristics of end portions of a channel forming region of a semiconductor film have on characteristics of a transistor. A gate electrode is formed over a channel forming region of a semiconductor film over a substrate, with a gate insulating film interposed therebetween. The... Agent: Nixon Peabody, LLP

20070278575 - Transistor and fabrication process: Process for fabricating a transistor, in which an electron-sensitive resist layer lying between at least two semiconductor fingers is formed and said resist lying between at least two wires is converted into a dielectric. For example, in one embodiment of the present disclosure an integrated circuit includes a transistor having... Agent: Docket Clerk

20070278579 - Protective assembly: A protective device for use with a metal stud features a body region, a reduced region, and a passageway disposed therethrough. The reduced region has an outer cross-section that is smaller than the outer cross-section of the body region and is sized and shaped to fit within an aperture disposed... Agent: Bourque & Associates Intellectual Property Attorneys, P.A.

20070278580 - Semiconductor integrated circuit device: A semiconductor integrated circuit device according to an embodiment of the present invention includes: a semiconductor substrate; an internal circuit formed on the semiconductor substrate, a first potential and a second potential being supplied to the internal circuit, thereby applying an operating voltage to the internal circuit; a fuse disposed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070278581 - Semiconductor dual guardring arrangement: A semiconductor dual guardring arrangement is provided which is useful during electrostatic discharge (ESD) events as well as during normal operating conditions. In particular, an inner guard that is located closer to an active area provides desirable performance during normal operating conditions, while an outer guardring located further from the... Agent: Texas Instruments Incorporated

20070278582 - Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devices: A voltage divider device includes a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region. An input voltage is coupled between the first and second gates, and an output voltage is taken from at least one of... Agent: Cantor Colburn LLP-ibm Burlington

20070278583 - Gate stress engineering for mosfet: Methods of stressing a channel of a transistor as a result of a material volume change in a gate structure and a related structure are disclosed. In one embodiment, a method includes forming a gate over the channel, wherein the gate includes several materials, such as layers of silicon materials... Agent: Hoffman, Warnick & D'alessandro LLC

20070278585 - Cmos devices with hybrid channel orientations, and methods for fabricating the same using faceted epitaxy: The present invention relates to a semiconductor substrate comprising at least first and second device regions. The first device region has a substantially planar surface oriented along one of a first set of equivalent crystal planes, and the second device region contains a protruding semiconductor structure having multiple intercepting surfaces... Agent: Scully Scott Murphy & Presser, PC

20070278584 - Semiconductor device fabricated using a metal microstructure control process: The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen... Agent: Texas Instruments Incorporated

20070278586 - Cmos structure and method for fabrication thereof using multiple crystallographic orientations and gate materials: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon... Agent: Scully Scott Murphy & Presser, PC

20070278587 - Semiconductor device and manufacturing method thereof: This disclosure concerns a semiconductor device comprising a semiconductor substrate; a gate dielectric film provided on the semiconductor substrate and containing Hf, Si, and O or containing Zr, Si and O; a gate electrode of an n-channel FET provided on the gate dielectric film, the gate electrode being made of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070278588 - Semiconductor device and method for manufacturing the same: A semiconductor device manufacturing method has forming a gate insulation film on a silicon substrate having an nMOS transistor region and a pMOS transistor region, forming a first metal film on the gate insulation film and thereby forming a gate electrode of the nMOS transistor, removing the first metal film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070278589 - Semiconductor device and fabrication method thereof: A semiconductor device includes: an NMIS transistor on an NMIS region of a semiconductor substrate; a PMIS transistor on a PMIS region of the semiconductor substrate; and a stress dielectric film continuously provided on the semiconductor substrate to cover the NMIS transistor and PMIS transistor, the stress dielectric film having... Agent: Mcdermott Will & Emery LLP

20070278593 - Semiconductor device and manufacturing method thereof: A semiconductor device includes: a P-type semiconductor layer formed in a surface region of a semiconductor substrate; a first gate insulating film formed on the P-type semiconductor layer; a first gate electrode; and a first source region and a first drain region formed in the P-type semiconductor layer to interpose... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070278592 - Semiconductor device having trench charge compensation regions and method: In one embodiment, a semiconductor device is formed having charge compensation trenches in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite... Agent: Bradley J. Botsch Semiconductor Components Industries, LLC

20070278590 - Cmos with dual metal gate: Embodiments herein present a structure and method to make a CMOS with dual metal gates. Specifically, the CMOS comprises a first gate comprising a first metal and a second gate comprising a second metal. The first gate comprises a portion of a first transistor that is complementary to a second... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070278591 - Method and structure to form self-aligned selective-soi: Methods of forming a self-aligned, selective semiconductor on insulator (SOI) structure and a related structure are disclosed. In one embodiment, a method includes providing a substrate; forming a gate structure over a channel within the substrate; recessing a portion of the substrate adjacent the channel; forming an insulating layer on... Agent: Hoffman, Warnick & D'alessandro LLC

20070278594 - Semiconductor device: The invention is directed to providing a resistor with high reliability. The invention is also directed to miniaturizing a semiconductor device having a MOS transistor and a resistor element on the same semiconductor substrate. An N-type well region is formed in a front surface of a P-type semiconductor substrate, and... Agent: Morrison & Foerster LLP

20070278596 - Method of increasing transistor drive current by recessing an isolation trench: By recessing the isolation structure of a transistor prior to silicidation, the series resistance may be reduced due to the increased amount of metal silicide formed in the vicinity of the isolation structure. By recessing the isolation structure prior to the formation of the gate electrode, an increased degree of... Agent: J. Mike Amerson, Williams, Morgan & Amerson, P.C.

20070278595 - Multi-fin field effect transistor and fabricating method thereof: A multi-fin field effect transistor includes a substrate, an oxide layer, a conductive layer, a gate oxide layer, and a doped region is provided. The substrate is surrounded by a trench, and there are at least two fin-type silicon layers formed in the substrate in a region prepared to form... Agent: Jianq Chyun Intellectual Property Office

20070278597 - Monolithic power semiconductor structures: Provided herein are exemplary embodiments of monolithic semiconductor structures having at least two lateral constructed semiconductor devices combined on a single semiconductor substrate.... Agent: Goodwin Procter LLP Patent Administrator

20070278598 - Transistor, a transistor arrangement and method thereof: A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor and a device isolation layer of the transistor based on the adjusted gate... Agent: Harness, Dickey & Pierce, P.L.C

20070278599 - Semiconductor device and methods thereof: A semiconductor device and method of forming the same are provided. The example semiconductor device may include a gate pattern including a gate electrode and a capping layer pattern on a semiconductor substrate, a spacer covering first and second sidewalls of the gate pattern, an impurity injection region formed in... Agent: Harness, Dickey & Pierce, P.L.C

20070278600 - Piezo-diode cantilever mems: A piezo thin-film diode (piezo-diode) cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method deposits thin-films overlying a substrate. The substrate can be made of glass, polymer, quartz, metal foil, Si, sapphire, ceramic, or compound semiconductor materials. Amorphous silicon (a-Si), polycrystalline Si (poly-Si), oxides, a-SiGe, poly-SiGe, metals,... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070278601 - Mems device and method of fabricating the same: A MEMS device includes a chip carrier having an acoustic port extending from a first surface to a second surface of the chip carrier, a MEMS die disposed on the chip carrier to cover the acoustic port at the first surface of the chip carrier, and an enclosure bonded to... Agent: Morgan Lewis & Bockius LLP

20070278603 - Magnetic memory device and method for fabricating the same: The magnetic memory device comprises a recording layer 70 formed linearly over a substrate 10 and having a plurality of pinning sites 52 for restricting the motion of domain walls 50 formed at a prescribed pitch and having the regions between the plural pinning sites 52 as recording bits 72.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070278602 - Mram structure using sacrificial layer for anti-ferromagnet and method of manufacture: A magnetic random access memory structure comprising an anti-ferromagnetic layer structure, a crystalline ferromagnetic structure physically coupled to the anti-ferromagnetic layer structure and a ferromagnetic free layer structure physically coupled to the crystalline ferromagnetic structure.... Agent: Slater & Matsil LLP

20070278605 - Infrared sensor and method of producing the same: A through hole P of this infrared sensor is formed in a position opposed to an adhesive layer AD. The through hole P, the bottom part thereof and an insulating film Pi formed therein is restrained from being deteriorated and damaged, in order to improve the characteristics of the infrared... Agent: Drinker Biddle & Reath (dc)

20070278604 - Optoelectronic component which can detect radiation: In a radiation-detecting optoelectronic component with a semiconductor chip (2) which chip has one or more radiation-sensitive zones (7, 8, 9) for detection of electromagnetic radiation (17), focusing of the electromagnetic radiation (17) occurs in the radiation-sensitive zones (7, 8, 9) by means of a diffractive element (1) which element... Agent: Fish & Richardson PC

20070278606 - Photoelectric conversion element and manufacturing method of photoelectric conversion element: An object is to provide a photoelectric conversion element having a side surface with different taper angles by conducting etching of a photoelectric conversion layer step-by-step. A pin photodiode has a high response speed compared with a pn photodiode but has a disadvantage of large dark current. One cause of... Agent: Fish & Richardson P.C.

20070278607 - Shallow semiconductor sensor with fluorescent molecule layer that eliminates optical and electronic crosstalk: A shallow semiconductor sensor with a fluorescent molecule layer that eliminates optical and electronic crosstalk.... Agent: Ratnerprestia

20070278608 - Schottky diode having low breakdown voltage and method for fabricating the same: Provided are a schottky diode having an appropriate low breakdown voltage to be used in a radio frequency identification (RFID) tag and a method for fabricating the same. The schottky diode includes a silicon substrate having a structure in which an N-type well is formed on a P-type substrate, an... Agent: Sughrue Mion, PLLC

20070278609 - Semiconductor device: A semiconductor device of unipolar type has Schottky-contacts (6) laterally separated by regions in the form of additional layers (7, 7″) of semiconductor material on top of a drift layer (3). Said additional layers being doped according to a conductivity type being opposite to the one of the drift layer.... Agent: Dilworth & Barrese, LLP

20070278610 - Semiconductor device with seg film active region: A semiconductor device and a method for manufacturing the same are provided. A barrier film is formed in a device separating structure, and the device separating structure is etched at a predetermined thickness to expose a semiconductor substrate. Then, a SEG film is grown to form an active region whose... Agent: Townsend And Townsend And Crew, LLP

20070278611 - Modified facet etch to prevent blown gate oxide and increase etch chamber life: A modified facet etch is disclosed to prevent blown gate oxide and increase etch chamber life. The modified facet etch is a two-stage process. The first stage is a plasma sputter etch to form a facet profile. The first stage etch is terminated prior to reaching the target depth for... Agent: Whyte Hirschboeck Dudek S.c.

20070278612 - Isolation structures for integrated circuits and modular methods of forming the same: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall... Agent: Patentability Associates

20070278613 - Semiconductor device: A semiconductor device includes: a semiconductor substrate; a device active portion formed in the semiconductor substrate; a device isolation portion formed in the semiconductor substrate so as to surround the periphery of the device active portion; an insulating film stacked on the device active portion; and a gate electrode stacked... Agent: Mcdermott Will & Emery LLP

20070278614 - Lateral passive device having dual annular electrodes: A lateral passive device is disclosed including a dual annular electrode. The annular electrodes form an anode and a cathode. The annular electrodes allow anode and cathode series resistances to be optimized to the lowest values at a fixed device area. In addition, the parasitic capacitance to a bottom plate... Agent: Hoffman, Warnick & D'alessandro LLC

20070278617 - Semiconductor device and method for determining fuse state: A semiconductor device includes a semiconductor substrate, a fuse which comprises a conductive material and is formed on a semiconductor substrate, a contacting target conductor region which is placed around the fuse on the semiconductor substrate and formed so as to make electrical contact with the fuse through the conductive... Agent: Young & Thompson

20070278616 - Semiconductor device, method of cutting electrical fuse, and method of determining electrical fuse state: A semiconductor device includes a semiconductor substrate and an electrical fuse formed on the semiconductor substrate, and including a first conductor and a second conductor electrically separated from the first conductor. In a state of the electrical fuse after a cutting processing, the first conductor is cut and separated into... Agent: Young & Thompson

20070278615 - Resistance-change-type fuse circuit: A resistance-change-type fuse circuit has a plurality of polysilicon fuses which are made of polysilicon and causes irreversible change in resistance by flowing a current; a plurality of programming transistors which are provided corresponding to the plurality of fuses, each programming transistor switching whether to flow the current through the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070278618 - Method and structure for symmetric capacitor formation: A structure and associated method for forming a structure. The structure comprises a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped... Agent: Schmeiser, Olsen & Watts

20070278620 - Semiconductor device incorporating a capacitor and method of fabricating the same: A semiconductor device incorporating a capacitor and a method of fabricating the same include a first inter-layer dielectric film formed on a semiconductor substrate, a first electrode pattern formed on the first inter-layer dielectric film, and a capacitor region self-aligned to the first electrode pattern and in which the first... Agent: Mills & Onello LLP

20070278619 - Semiconductor integrated circuit devices having high-q wafer back-side capacitors: Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a... Agent: F. Chau & Associates, LLC

20070278621 - Bipolar transistor with raised base connection region and process for the production thereof: A bipolar transistor has a base with an epitaxial base layer and a raised base connection region which in a lateral direction in parallel relationship with the substrate surface encloses the emitter which is surrounded by a spacer of insulating material. The epitaxial base layer is raised in a heightwise... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20070278622 - Gallium nitride device substrate contaning a lattice parameter altering element: A gallium nitride device substrate comprises a layer of gallium nitride containing an additional lattice parameter altering element located over a substitute substrate.... Agent: Kathy Manke Avago Technologies Limited

20070278623 - Electric circuit device and related manufacturing method: An electric circuit device and related manufacturing method are disclosed as having a case incorporating therein a substrate on which electric circuit elements are mounted. A sealant is filled in the case to cover the electric circuit elements and the substrate and is composed of a lower layer gel and... Agent: Nixon & Vanderhye, PC

20070278624 - Damascene filament wire structure: A structure. The structure includes a substrate. A first dielectric layer is on and in direct mechanical contact with the substrate. A first hard mask is on the first dielectric layer. A first and second trench is within the first dielectric layer and the first hard mask. The second trench... Agent: Schmeiser, Olsen & Watts

20070278625 - Semiconductor device, method for manufacturing the semiconductor device and portable electronic device provided with the semiconductor device: A semiconductor device, which is characterized by that two or more island-shaped semiconductor layers including first and second island-shaped semiconductor layers are formed on the same substrate, at least the first island-shaped semiconductor layer has steps in its side wall so that sectional area of a cross section parallel to... Agent: Morrison & Foerster LLP

20070278626 - Semiconductor element with a passivation layer and method for production thereof: Semiconductor component that contains AlxGayIn1−x−yAszSb1−z, whereby the parameters x, y, and z are selected such that a bandgap of less than 350 meV is achieved, whereby it features a mesa-structuring and a passivation layer containing AlnGa1−nAsmSb1−m is applied at least partially on at least one lateral surface of the structuring,... Agent: Greenblum & Bernstein, P.L.C

20070278627 - Dielectric device: A dielectric device comprises a dielectric layer and first to nth metal layers (where n is an integer of 2 or greater) in contact with the dielectric layer. At least one of the first to nth metal layers contains a base metal. Interfaces between the first to nth metal layers... Agent: Oliff & Berridge, PLC

20070278628 - Multilayer structures for magnetic shielding: A magnetic shield is presented. The shield may be used to protect a microelectronic device from stray magnetic fields. The shield includes at least two layers. A first layer includes a magnetic material that may be used to block DC magnetic fields. A second layer includes a conductive material that... Agent: Honeywell International Inc.

20070278629 - Method and structure for improving the reliability of leadframe integrated circuit packages: A method and structure for forming a reliable metallurgical bond during the implementation of a wire bonding process on leadframe-based integrated arrangement, which improves the stress-resistance of a metallurgical bond during and subsequent to a wire bonding process wherein the leadframes of integrated circuit packages utilize a metal plating on... Agent: Steven Fischman, Esq. Scully, Scott, Murphy & Presser

20070278630 - Heat sink dissipating device for electrical connector: A heat sink dissipating device (1) includes a heat sink assembly (20), a first attachment frame (100) and a second attachment frame (110). The first attachment frame defines a region (113) for the heat sink assembly to be retained thereon. The second attachment frame includes a plurality frame pieces (101)... Agent: Wei Te Chung Foxconn International, Inc.

20070278633 - Lead frame and method of manufacturing the same and semiconductor device: In the lead frame of the present invention, a common wiring portion (ground ring) is arranged around a die pad at a predetermined interval to be connected partially to the die pad, projection portions projected toward the die pad side are provided to side portions of the common wiring portion,... Agent: Kratz, Quintos & Hanson, LLP

20070278632 - Leadframe ic packages having top and bottom integrated heat spreaders: Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages is described. A die-up or die-down package includes first and second caps defining a cavity, an IC die, and a leadframe. The leadframe includes a centrally located die attach pad, a plurality of... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070278631 - Self-aligned wafer level integration system: A polymer-based, self-aligned wafer-level heterogeneous integration system, SA WLIT, for integrating semiconductor integrated circuit (IC) chips to a substrate is presented. The system includes a method including preparing a substrate, flipping the substrate onto a polymer-based flat surface and securing the substrate to the flat surface, mounting semiconductor chips into... Agent: Brinks Hofer Gilson & Lione

20070278634 - Au-ag based alloy wire for semiconductor package: A gold-silver based wire for a semiconductor package has high humidity reliability as well as high dry reliability. The wire includes a first additive ingredient that contains 5˜15 wt % of at least one kind of elements from among first group elements composed of palladium (Pd) and platinum (Pt) added... Agent: Volpe And Koenig, P.C.

20070278635 - Microelectronic package having solder-filled through-vias: An apparatus, a method, and a system associated with microelectronic packaging are disclosed herein. In various embodiments, a microelectronic package may include a die having one or more through-vias, each filled with a solder material; a substrate; and one or more solder bumps disposed between and electrically connecting the substrate... Agent: Schwabe, Williamson & Wyatt, P.C.

20070278637 - Circuit arrangement, system carrier and methods for producing same: A circuit arrangement includes a component or an integrated circuit firmly attached on a wiring carrier via an adhesive layer. Furthermore, a pyrolytically deposited adhesion promoter layer with high surface energy and/or high porosity in the nanometer range is selectively provided on a metallic adherend location of the wiring carrier.... Agent: Edell, Shapiro & Finnan, LLC

20070278636 - Matching circuits on optoelectronic devices: The present invention alters the frequency response of an optoelectronic device to match a driver circuit that drives the optoelectronic device. The optoelectronic device is formed on a first substrate. A matching circuit is also formed on the first substrate and coupled to the optoelectronic device to change its frequency... Agent: Kathy Manke Avago Technologies Limited

20070278642 - Semiconductor device: A semiconductor device includes a first semiconductor module having a semiconductor part on a board and conductive parts for making connection with another board on an upper surface of the board, a second semiconductor module having a semiconductor part on a board and conductive parts for making connection with another... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070278638 - Semiconductor package structure: A semiconductor package structure includes a substrate, a chip module, a lead frame, and a bridging element. The chip module is electrically connected to the substrate. The lead frame is disposed beside one side of the substrate, wherein the lead frame has a receiving unit. The bridging element has one... Agent: Rosenberg, Klein & Lee

20070278644 - Stack structure of circuit board with semiconductor component embedded therein: A stack structure of circuit boards embedded with semiconductor components therein is proposed, which includes at least two semiconductor components embedded circuit boards, a plurality of conductive bumps, and at least one adhesive layer. The circuit boards are each formed with a circuit layer having a plurality of electrical connection... Agent: Sawyer Law Group LLP

20070278643 - Stackable multi-chip package system: A stackable multi-chip package system is provided including forming an inter-chip structure adjacent to an external interconnect having both a base and a tip; connecting a first integrated circuit die and an outer portion of the base with the first integrated circuit die mounted over the inter-chip structure, connecting a... Agent: Ishimaru & Zahrt LLP

20070278640 - Stackable semiconductor package: The present invention relates to a stackable semiconductor package comprising a first substrate, a semiconductor device, a second substrate, a plurality of first wires, a supporting element, and a first molding compound. The semiconductor device is disposed on the first substrate. The second substrate is disposed above the semiconductor device,... Agent: Volentine & Whitt PLLC

20070278648 - Multiple die stack apparatus employing t-shaped interposer elements: Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction or heat removal for semiconductor devices and the methods for the stacking thereof are disclosed.... Agent: Trask Britt, P.C./ Micron Technology

20070278647 - Package mounted module and package board module: A package board module wherein a semiconductor chip such as an LSI is mounted on the topside surface of a package board, and a package mounted module wherein the package board is mounted on the motherboard of a large-sized computer or the like. A stiffener for supporting the package board... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070278646 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device includes: a first semiconductor chip face-down mounted on a substrate; a second semiconductor chip face-up mounted on the first semiconductor chip; an electromagnetic shielding plate inserted between the first semiconductor chip and the second semiconductor chip; and a bonding wire bonded on the substrate so as to... Agent: Harness, Dickey & Pierce, P.L.C

20070278639 - Semiconductor device stack and method for its production: A semiconductor stack and a semiconductor base device with a wiring substrate and an intermediate wiring board for a semiconductor device stack is disclosed. In one embodiment, a semiconductor chip is arranged between the intermediate wiring board and the wiring substrate which is electrically connected by way of the wiring... Agent: Dicke, Billig & Czaja

20070278641 - Side stacking apparatus and method: A module has at least two ICs connected to each other such that they lie in different planes and are arranged as a first stack of ICs, a third IC is connected to at least one of the at least two ICs, wherein the third IC is off plane from... Agent: Morgan & Finnegan, L.L.P.

20070278645 - Stacked package electronic device: An electrical component includes a substrate, a first integrated circuit attached to the substrate, a metal portion coupled to the first integrated circuit, and a second integrated circuit attached to the first integrated circuit. The metal portion is sandwiched between the first integrated circuit and the second integrated circuit.... Agent: Schwegman, Lundberg & Woessner, P.A.

20070278649 - Semiconductor package, method of producing the same and semiconductor package assembly: A semiconductor package, includes: element substrate having first surface, including: functional element on first surface, and extracting electrode on first surface and configured to output a signal of functional element, extracting electrode being disposed around functional element; rim substrate shaped into a frame, and configured to have first junction with... Agent: Foley And Lardner LLP Suite 500

20070278651 - Electronic component package and manufacturing method thereof: An electronic component package and a manufacturing method thereof are disclosed. A method of manufacturing an electronic component package, which includes: forming a protrusion part on a first carrier board; stacking an insulation layer on the first carrier board and forming a circuit pattern, which includes a bonding pad and... Agent: Staas & Halsey LLP

20070278652 - Semiconductor integrated circuit device: Disclosed is a semiconductor IC device capable of suppressing the interference of noise generated in one functional block with other functional blocks therein while protecting against electrostatic breakdown. A plurality of isolated pads are connected to a first terminal through respective wires, and further connected to a plurality of isolated... Agent: Ratnerprestia

20070278655 - Electronic assemblies and systems with filled no-flow underfill: High yield, high reliability, flip-chip integrated circuit (IC) packages are achieved utilizing a combination of heat and pressure to bond flip-chip die and to cure no-flow underfill material. The underfill comprises a filler or low coefficient of thermal expansion (CTE) material to decrease CTE of the cured underfill. The filler... Agent: Schwegman, Lundberg & Woessner, P.A.

20070278654 - Method of making an electronic package: An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at... Agent: John A. Jordan, Esq.

20070278656 - Modular bonding pad structure and method: A semiconductor die includes a plurality of drivers and a plurality of bonding pads. Each driver is formed by a plurality of interconnected modules and has an associated bonding pad to which at least one of the modules of the driver is electrically connected. The modules of some of the... Agent: Agilent Technologies Inc.

20070278653 - Producing thin integrated semiconductor devices: Thin integrated semiconductor devices are produced by being embedded in a molding compound matrix in such a way that a composite is formed. The semiconductor devices are first embedded in the matrix and then thinned after being embedded. The thin integrated semiconductor devices are singulated by forming separating cuts into... Agent: Edell, Shapiro & Finnan, LLC

20070278650 - Semiconductor device: In a semiconductor device a substrate is formed in a rectangular shape having four edges along dicing lines, and a jetty portion is formed so as to surround an actuator element and an electrode pad for signal input and output. The jetty portion is a rectangular shape having four sides... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070278657 - Chip stack, method of fabrication thereof, and semiconductor package having the same: A chip stack may include a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. Each semiconductor chip may have an active surface, a back surface opposite to the active surface, and a plurality of connection pads arranged in the center of the active surface.... Agent: Harness, Dickey & Pierce, P.L.C

20070278658 - Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package: A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package... Agent: Haynes Beffel & Wolfeld LLP

20070278659 - Semiconductor package substrate and semiconductor package having the same: A semiconductor package substrate includes a substrate body and at least one intermediate bonding portion disposed on the substrate body. The substrate body includes at least one chip mounting area for mounting a chip thereon, and a plurality of electrical pads formed around the chip mounting area and for being... Agent: Edwards Angell Palmer & Dodge LLP

20070278660 - Integrated circuit package system with edge connection system: An integrated circuit package system including a plurality of substrates and a plurality of semiconductor devices formed on each of the substrates. An edge connection system is provided and an electrical edge connector on each of the substrates is for attachment to the edge connection system. A vertically stacked configuration... Agent: Ishimaru & Zahrt LLP

20070278661 - Circuit board and manufacturing method thereof: A circuit board and a manufacturing method thereof are provided. First, the circuit board has a coaxial signal trace that comprises a conductive line and conductive wall. The conductive wall surrounds part or all of the conductive line. Additionally, the circuit board has a plurality of circuit layers where the... Agent: J C Patents, Inc.

20070278662 - Inspection apparatus and method for semiconductor ic: The connection between a PTC element 22a corresponding to each semiconductor IC 11a and a power-supply line 25a is performed via a relay, a high voltage is supplied to the power-supply line 25a by sequentially turning on the relays, and a high voltage is supplied to each PTC element 22a... Agent: Steptoe & Johnson LLP

20070278663 - Integrated circuit cooling device: A pump having: a cavity formed inside an insulating substrate, the upper part of the substrate being situated near the cavity having an edge; a conductive layer covering the inside of the cavity up to the edge and optionally covering the edge itself; a flexible membrane made of a conductive... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070278664 - Semiconductor package structure having enhanced thermal dissipation characteristics: In one embodiment, a packaged semiconductor device having enhanced thermal dissipation characteristics includes a lead frame structure and a semiconductor chip having a major current carrying or heat generating electrode. The semiconductor chip is oriented so that the major current carrying electrode faces the top of the package or away... Agent: Bradley J. Botsch Semiconductor Components Industries, LLC

20070278665 - Thermally enhanced three-dimensional package and method for manufacturing the same: A thermally enhanced three-dimensional (3D) package is disclosed. The package includes a heat sink having an opening and a stiffener ring inside the opening. The stiffener ring has a first surface and a second surface. A first substrate of a first package is disposed inside the opening and secured to... Agent: North America Intellectual Property Corporation

20070278666 - Method for production of electronic and optoelectronic circuits: According to the invention, in an assembly comprising an electronic component (108), said component is connected by microbeads (107) to at least one heat sink (106, 109), said beads being connected to electrically-conductive lines on said electronic component and to electrically-conductive lines on at least one heat sink, said beads... Agent: Young & Thompson

20070278667 - Semiconductor device having high cooling efficiency and method for manufacturing the same: A semiconductor device includes a substrate, a semiconductor chip flip-chip mounted on the substrate, a sealing resin layer sealing the surroundings of the semiconductor chip, and a heat sink bonded to the sealing resin layer through a TIM layer. In addition, a cooling medium is encapsulated in an enclosed space... Agent: Katten Muchin Rosenman LLP

20070278668 - Packaged electroosmotic pumps using porous frits for cooling integrated circuits: An integrated electroosmotic pump may be incorporated in the same integrated circuit package with a re-combiner, and an integrated circuit chip to be cooled by fluid pumped by the electroosmotic pump.... Agent: Trop Pruner & Hu, PC

20070278669 - Semiconductor circuit arrangement: A semiconductor circuit arrangement is disclosed. In one embodiment, a semiconductor module is attached to a board using a screw, with a mechanical and electrical contact being made between module contacts on the semiconductor module and associated board contacts on the board at the same time by attachment using the... Agent: Dicke, Billig & Czaja

20070278670 - Multilayer electronic component, electronic device, and method for producing multilayer electronic component: A multilayer electronic component including a resin layer disposed on a mounting board side is mounted on a mounting board, and has a structure such that, even when deformation, such as deflection and strain, occurs, a stress on the multilayer electronic component is relieved. In the multilayer electronic component, ends... Agent: Murata Manufacturing Company, Ltd. C/o Keating & Bennett, LLP

20070278671 - Ball grind array package structure: An IC package structure of die face up or die face down is provided with adding the occupied area of die-attaching material. The die-attaching layer is distributed the surface of the substrate exposed by a die and configured for absorbing the thermal stress induced from thermal expansion mismatch of materials... Agent: Birch Stewart Kolasch & Birch

20070278672 - Semiconductor device having an improved structure for high withstand voltage: Second diffusion layers to be guard rings of a second conductivity type are formed on the major surface of a semiconductor substrate of a first conductivity type in a guard ring region. An insulating film is formed on these second diffusion layers. The semiconductor device has a structure wherein a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070278673 - Repaired structure of circuit board having pre-soldering bump and methods for repairing the same: A repaired structure of a circuit board having pre-soldering bumps and a method for repairing the same are proposed. Firstly, a circuit board having a plurality of pre-soldering bumps on a surface thereof is provided, wherein at least one of the pre-soldering bumps has a defect. Then, a micro-electroplating process... Agent: Sawyer Law Group LLP

20070278674 - Power semiconductor arrangement with soldered clip connection and method: A power semiconductor arrangement with soldered clip connection and a method for producing such an arrangement is disclosed. One embodiment provides a semiconductor chip with soldered clip connection. A solderable front-side power metallization layer is provided. A gate finger structure is provided. A structured passivation layer is provided for the... Agent: Dicke, Billig & Czaja

20070278676 - Process for reforming a plastic packaged integrated circuit die and a reformed plastic packaged integrated circuit die: A process for reforming a plastic packaged integrated circuit die (100) includes grinding away (305) a bottom side (210) of a plastic package (205) and portions of a set of leads (110) that are in the plane of the grinding until a bottom surface (240) of an inner portion (230)... Agent: Motorola, Inc.

20070278678 - Semiconductor device and method for fabricating the same: A semiconductor device according to the present invention includes a semiconductor substrate, which comprises a first surface on which an electrode pad is formed, and a second surface arranged at an opposite side of the first surface; an external terminal formed on the first surface of the semiconductor substrate and... Agent: Rabin & Berdo, PC

20070278677 - Semiconductor module featuring solder balls having lower melting point than that of solder electrode terminals of passive element device: In a semiconductor module including a wiring board having a top surface and a bottom surface, a passive element device Is soldered on the top surface of the wiring board by a first solder material, and an external solder electrode terminal is adhered on the bottom surface of the wiring... Agent: Mcginn Intellectual Property Law Group, PLLC

20070278675 - System and method to reduce metal series resistance of bumped chip: Provided herein, in accordance with one aspect of the present invention, are exemplary embodiments of semiconductor chips having low metallization series resistance. In one embodiment, the semiconductor chip comprises a semiconductor substrate and a metallization structure formed on the semiconductor substrate; an under bump metallurgy (“UBM”) structure layer formed over... Agent: Goodwin Procter LLP Patent Administrator

20070278679 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070278680 - Method and device for concentrating light in optoelectronic devices using resonant cavity modes: A grating structure for channeling and concentrating incident radiation includes a regular pattern of elements each with a metallic shell partially surrounding at least one subcavity. The subcavity is filled with a dielectric or semiconductor. Light of one or more predetermined wavelength ranges can be concentrated in the subcavity(s) and... Agent: Hoffmann & Baron, LLP

20070278681 - Interconnection structure design for low rc delay and leakage: An interconnection structure for integrated circuits having reduced RC delay and leakage is provided. The interconnection structure includes a first conductive line in a first dielectric layer, a second dielectric layer over the first dielectric layer and the first conductive line, and a dual damascene structure in the second dielectric... Agent: Slater & Matsil, L.L.P.

20070278682 - Self-assembled mono-layer liner for cu/porous low-k interconnections: An interconnect structure of an integrated circuit includes a low-k dielectric layer over a semiconductor substrate, a conductor in the low-k dielectric layer, and a dielectric transition layer between the low-k dielectric layer and the conductor, wherein the dielectric transition layer has a thickness of less than about 50 Å.... Agent: Slater & Matsil, L.L.P.

20070278683 - Interlayer dielectric and pre-applied die attach adhesive materials: The present invention relates to interlayer dielectric materials and pre-applied die attach adhesives, more specifically pre-applied die attach adhesives (such as wafer and other substrate-applied die attach adhesives), methods of applying the interlayer dielectric materials onto substrates to prepare low K dielectric semiconductor chips, methods of applying the pre-applied die... Agent: Loctite Corporation

20070278684 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070278685 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070278686 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070278687 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070278688 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070278689 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070278690 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070278691 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070278693 - Metallization layer of a semiconductor device having differently thick metal lines and a method of forming the same: A semiconductor device comprises metal lines in a specific metallization layer which have a different thickness and thus a different resistivity in different device regions. In this way, in high density areas of the device, metal lines of reduced thickness may be provided in order to comply with process requirements... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20070278694 - Semiconductor device and manufacturing method thereof: Two interconnect layers are electrically connected while reducing the number of manufacturing steps. A contact plug 9c which is formed into a beaded shape in a layer underlying two interconnects 11C and 11D and which also electrically connects the two interconnects 11C and 11D is included. The two interconnects 11C... Agent: Mcginn Intellectual Property Law Group, PLLC

20070278692 - Structure of semiconductor substrate and molding method: A chip molded onto a substrate with a slot forms a molded semiconductor structure, wherein the chip covers one end of the slot and the other open. This special design leads the mold flow and enhances the semiconductor by a transverse pressure induced by the molding flow as the semiconductor... Agent: Birch Stewart Kolasch & Birch

20070278695 - Interconnect structures: The present invention relates to metallic interconnect having an interlayer dielectric thereover, the metallic interconnect having an upper surface substantially free from oxidation. The metallic interconnect may have an exposed upper surface thereon that is passivated by a nitrogen containing compound.... Agent: Trask Britt, P.C./ Micron Technology

20070278697 - Semiconductor device: A first semiconductor chip, a spacer of plane shape, and a second semiconductor chip are put on a module substrate, sequentially. These semiconductor chips have a relation that every side of the first semiconductor chip is shorter than the first side and the second side of the second semiconductor chip,... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070278696 - Stackable semiconductor package: The present invention relates to a stackable semiconductor package including a first substrate, a chip, a low modules film, a second substrate, a plurality of first wires, and a first molding compound. The chip is disposed on the first substrate. The low modules film is disposed on the chip. The... Agent: Volentine & Whitt PLLC

20070278698 - Semiconductor device and semiconductor wafer and a method for manufacturing the same: The semiconductor device 1 has a semiconductor chip 10 (first semiconductor chip) and a semiconductor chip 20 (second semiconductor chip). The semiconductor chip 20 is formed on the semiconductor chip 10. The semiconductor chip 20 is constituted by comprising a semiconductor substrate 22. The semiconductor substrate 22, which is an... Agent: Sughrue Mion, PLLC

20070278699 - Microelectronic element chips: Apparatus including a chip substrate having a first chip surface facing away from a second chip surface; an array of microelectronic elements on the first chip surface; and an array of conductors each in communication with one of the microelectronic elements, the conductors passing through the chip substrate and fully... Agent: The Eclipse Group

20070278700 - Method for forming an encapsulated device and structure: In one embodiment, an electronic device package (1) includes a leadframe (2) with a flag (3). An electronic chip (8) is attached to the flag (3) with a die attach layer (9). A trench (16) having curved sidewalls is formed in the flag (3) in proximity to the electronic chip... Agent: James J. Stipanuk Semiconductor Components Industries, L.L.C.

20070278701 - Semiconductor package and method for fabricating the same: A semiconductor package and a method for fabricating the same are disclosed. The method includes installing a plurality of conductive components on a plurality of chip carriers of a chip carrier module, connecting electrically the conductive components to electrical connection points of the adjacent chip carriers, mounting and electrically connecting... Agent: Edwards Angell Palmer & Dodge LLP