Active solid-state devices (e.g., transistors, solid-state diodes) inventions 11/07

20070272914 - Group-iii nitride vertical-rods substrate: The invention is directed to a group-III nitride vertical-rods substrate. The group-III vertical-rods substrate comprises a substrate, a buffer layer and a vertical rod layer. The buffer layer is located over the substrate. The vertical rod layer is located on the buffer layer and the vertical rod layer is comprised... Agent: Jianq Chyun Intellectual Property Office

20070272916 - Flash memory with deep quantum well and high-k dielectric: A flash memory cell includes a substrate and a gate structure formed on the substrate. The gate structure includes a tunneling layer over the substrate, a storage layer over the tunneling layer, a blocking layer over the storage layer, and a gate electrode over the dielectric. The storage layer preferably... Agent: Slater & Matsil, L.L.P.

20070272921 - Multicolor organic light-emitting device: Provided is a multicolor organic EL display having plural organic EL devices arranged on a substrate. The multicolor organic light-emitting device includes a substrate; plural organic light-emitting elements provided on the substrate, including a first organic light-emitting element of first emission color and a second organic light-emitting element of second... Agent: Fitzpatrick Cella Harper & Scinto

20070272919 - Stressed organic semiconductor devices: An organic semiconductor device including: a substrate having a first thermal expansion coefficient; and an organic semiconductor material coupled to the substrate at an interface therebetween. The organic semiconductor material includes a polymer organic semiconductor material and/or an oligomer organic semiconductor material. The organic semiconductor material also has a second... Agent: Ratnerprestia

20070272922 - Zno thin film transistor and method of forming the same: A zinc oxide (ZnO) thin film transistor (TFT) and method of forming the same are provided. The ZnO may include a ZnO semiconductor channel, a conductive ZnO gate forming an electric field around the ZnO semiconductor channel, an ZnO gate insulator interposed between the conductive ZnO gate and the ZnO... Agent: Harness, Dickey & Pierce, P.L.C

20070272923 - Charge pump with reduced turn-off time and phase locked loop including the same: A charge pump includes a current source/sink unit that charges/discharges an output node in response to an UP/DOWN signal generated by a PFD (phase frequency detector). The charge pump also includes a pull-down/pull-up unit configured to discharge/charge a cascode node within the current source/sink unit for a limited time period... Agent: Law Office Of Monica H Choi

20070272924 - Integrated circuit (ic) testing device with conduction interface: An IC testing device with conduction interface comprising an electrical circuit board having a test circuit; an insulation pad set on the circuit board; and a pressing block provided on the insulation pad for depressing the pins of the IC. While the conduction interface comprises a plurality of contactors provided... Agent: Lowe Hauptman Ham & Berner, LLP

20070272926 - Tft lcd array substrate and manufacturing method thereof: A TFT LCD array substrate and a manufacturing method thereof. The TFT LCD array substrate includes a substrate and a pixel array on the substrate. Each pixel has: a gate line and a gate electrode formed on the substrate; a gate insulating layer formed on the gate line and the... Agent: Hasse & Nesbitt LLC

20070272928 - Thin film transistor, array substrate having the thin film transistor and method of manufacturing the array substrate: A thin film transistor includes a semiconductor layer a source electrodes a drain electrode and a gate electrode. The semiconductor layer includes a plurality of grain boundaries disposed along a first direction. An acute angle between a gate electrode and a grain boundary prevents grain to boundaries from being formed... Agent: F. Chau & Associates, LLC

20070272933 - Light-emitting diode chip for backlight unit, manufacturing method thereof, and liquid crystal display device including the same: A light-emitting diode includes a substrate, a buffer layer on the substrate, a first semiconductor layer on the buffer layer, a light-emitting layer on the first semiconductor layer, a second semiconductor layer on the light-emitting layer, wherein the first semiconductor layer is partially exposed through the second semiconductor layer and... Agent: Mckenna Long & Aldridge LLP

20070272934 - Led device with improved life performance: A light-emitting diode with an improved service life is provided. The diode is formed from a transparent outer shell that contains a heat-resistant encapsulant at least partially surrounding a light-emitting diode clip. The first encapsulant is compressed between the outer shell and a second encapsulant when it is sealed into... Agent: Kathy Manke Avago Technologies Limited

20070272935 - Semiconductor device and manufacturing method therefor: A laser diode includes a first n-cladding layer disposed on and lattice-matched to an n-semiconductor substrate, wherein the first n-cladding layer is n-AlGaInP or n-GaInP; a second n-cladding layer of n-AlGaAs supported by the first n-cladding layer; and an inserted layer disposed between the first n-cladding layer and the second... Agent: Leydig Voit & Mayer, Ltd

20070272936 - Nitride based light emitting device: A nitride based light emitting device is disclosed. More particularly, a nitride based light emitting device capable of improving light emitting efficiency and reliability thereof is disclosed. The nitride based light emitting device includes a first conductive semiconductor layer connected to a first electrode, a second conductive semiconductor layer connected... Agent: Mckenna Long & Aldridge LLP

20070272937 - Nitride semiconductor light emitting device: where X is the distance between ends of the p-side pad electrode and the n-side pad electrode, Y is the distance between the end of the p-side pad electrode and the periphery of the translucent electrode, L is the length of the translucent electrode on the line connecting the centroids... Agent: Birch Stewart Kolasch & Birch

20070272939 - Tunnel vertical semiconductor devices or chips: The present invention discloses tunnel vertical semiconductor devices and chips comprising tunnel vertical GaN based, GaP based and ZnO based LEDs and manufacturing method. The structure of an embodiment of tunnel vertical semiconductor devices and chips is the following: first and second electrodes formed on first surface of a supporting... Agent: Hui Peng

20070272912 - Conductive paste and method of manufacturing electronic component using the same: Exemplary embodiments provided a conductive paste including an organic gold compound and a glass component in a solvent. When electrodes are formed on both surfaces of piezoelectric members using the conductive paste according to the invention, it is possible to improve the close adhesion property between the electrodes and the... Agent: Hunton & Williams LLP Intellectual Property Department

20070272913 - Forming nonvolatile phase change memory cell having a reduced thermal contact area: The invention provides for a nonvolatile memory cell comprising a heater layer in series with a phase change material, such as a chalcogenide. Phase change is achieved in chalcogenide memories by thermal means. Concentrating thermal energy in a relatively small volume assists this phase change. In the present invention, a... Agent: Vierra Magen/sandisk Corporation

20070272915 - Nitride semiconductor with active layer of quantum well structure with indium-containing nitride semiconductor: A nitride semiconductor device has a nitride semiconductor layer structure. The structure includes an active layer of a quantum well structure containing an indium-containing nitride semiconductor. A first nitride semiconductor layer having a band gap energy larger than that of the active layer is provided in contact with the active... Agent: Nixon & Vanderhye, PC

20070272920 - Electroluminescent materials and devices: Novel ruthenium, rhodium, palladium, osmium, iridium or platinum complexes of thianthrene ligands are electroluminescent compounds. According to the invention there is provided complexes of Formula (I).... Agent: David Silverstein Andover-ip-law

20070272918 - Organic photosensitive devices using subphthalocyanine compounds: An organic photosensitive optoelectronic device, having a donor-acceptor heterojunction of a donor-like material and an acceptor-like material and methods of making such devices is provided. At least one of the donor-like material and the acceptor-like material includes a subphthalocyanine, a subporphyrin, and/or a subporphyrazine compound; and/or the device optionally has... Agent: Kenyon & Kenyon LLP

20070272917 - Process for improved cross-linking of an organic semiconductor layer by using a plastiser containing oxetane groups: Semiconducting films are formed on a substrate by coating the substrate with a mixture of a semiconducting material and a substance which results in a Tg of the resulting mixture which is lower than that of the said material, and cross-linking the said material. Multilayer electronic devices may be produced... Agent: Millen, White, Zelano & Branigan, PC

20070272925 - Semiconductor device having multi-gate structure and method of manufacturing the same: Provided are a semiconductor device having a mesa-type active region including a plurality of slabs and a method of manufacturing the semiconductor device. The semiconductor device includes a first active region and a second active region. The first active region is formed in a line-and-space pattern on a substrate and... Agent: F. Chau & Associates, LLC

20070272927 - Thin film transistor, method of manufacturing the thin film transistor, active matrix type display device, and method of manufacturing the active matrix type display device: A TFT according to an embodiment of the present invention includes an insulative base film formed on a TFT array substrate, and a semiconductor film including a channel region formed on the base film, in which an impurity concentration of a channel region in the semiconductor film becomes substantially uniform... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070272929 - Diamond n-type semiconductor, method of manufacturing the same, semiconductor device, and electron emitting device: The present invention relates to a diamond n-type semiconductor in which the amount of change in carrier concentration is fully reduced in a wide temperature range. The diamond n-type semiconductor comprises a diamond substrate, and a diamond semiconductor formed on a main surface thereof and turned out to be n-type.... Agent: Mcdermott Will & Emery LLP

20070272930 - Light-emitting diode package: A light-emitting diode package (LED package) includes a LED and a carrier. The LED includes a substrate, a semiconductor layer, a first electrode and a second electrode. The semiconductor layer is located on a surface of the substrate and has a rough surface. The semiconductor layer includes a first-type doped... Agent: Jianq Chyun Intellectual Property Office

20070272932 - Light-emitting diode with improved ultraviolet light protection: The present application relates to a semiconductor device comprising one or more protective layers, and more specifically to a light-emitting diode comprising one or more ultraviolet protective layers. The use of said UV protective layers prevents the degradation of a LED by UV light. This results in a LED with... Agent: Kathy Manke Avago Technologies Limited

20070272931 - Methods, devices and systems producing illumination and effects: A device has a plurality of ultra-small resonant structures, each of said structures constructed and adapted to emit light at a particular wavelength when a beam of charged particles is passed nearby, wherein at least one of the light emitters emits light in a first range of wavelengths and wherein... Agent: Davidson Berquist Jackson & Gowdey LLP

20070272938 - Package for storing light emitting element and method for producing package for storing light emitting element: A light-emitting element storing package which ensures the efficient reflection of light emitted by a light-emitting element by a reflector frame and thereby improves the brightness of the emitted light, and a method of manufacturing the same are provided. The light-emitting element storing package includes: an insulating substrate consisting of... Agent: The Webb Law Firm, P.C.

20070272940 - Semiconductor device with a light emitting semiconductor die: A semiconductor device includes a light emitting semiconductor die mounted on at least one of first and second electrically conductive bonding pads, which are located on a first major surface of a substrate of the device. The light emitting semiconductor die has an anode and a cathode, which are electrically... Agent: Kathy Manke Avago Technologies Limited

20070272941 - Method for producing iii group element nitride crystal, production apparatus for use therein, and semiconductor element produced thereby: A method for producing Group-III-element nitride crystals by which an improved growth rate is obtained and large high-quality crystals can be grown in a short time, a producing apparatus used therein, and a semiconductor element obtained using the method and the apparatus are provided. The method is a method for... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070272942 - Semiconductor device and method of manufacturing the same: In a semiconductor device of the present invention, an N type epitaxial layer is divided into a plurality of element formation regions by an isolation region. In one of the element formation regions, a resistance is formed. Around the resistance, a protection element having a PN junction region is formed.... Agent: Fish & Richardson P.C.

20070272944 - Semiconductor member, manufacturing method thereof, and semiconductor device: An SiGe layer is grown on a silicon substrate. The SiGe layer or the silicon substrate and SiGe layer are porosified by anodizing the SiGe layer to form a strain inducing porous layer or a porous silicon layer and strain inducing porous layer. An SiGe layer and strained silicon layer... Agent: Fitzpatrick Cella Harper & Scinto

20070272943 - Structure and manufacturing method for epitaxial layers of gallium nitride-based compound semiconductors: The present invention relates to a structure and a manufacturing method of epitaxial layers of gallium nitride-based compound semiconductors with less dislocation densities. Surface treatment is carried out first on the surface of a substrate using reaction precursors Cp2Mg and NH3. Then a gallium nitride-based buffer layer is formed on... Agent: Rosenberg, Klein & Lee

20070272945 - Field-effect transistor: A field-effect transistor has a so-called double heterostructure which is formed such that a channel layer through which electrons travel is provided between an electron supply layer and a liner layer, wherein a forbidden band width of the liner layer and a forbidden band width of the electron supply layer... Agent: Mcdermott Will & Emery LLP

20070272946 - Silicon germanium emitter: Disclosed are an improved hetero-junction bipolar transistor (HBT) structure and a method of forming the structure that incorporates a silicon-germanium emitter layer with a graded germanium profile. The graded germanium concentration creates a quasi-drift field in the neutral region of the emitter layer. This quasi-drift field induces valence bandgap grading... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070272947 - Low power consuming semiconductor device: A low power consuming semiconductor device comprises a p substrate, a first semiconductor cell formed over the p substrate, a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell, and a tap cell for coupling a power pin to n-well structures of the first semiconductor... Agent: North America Intellectual Property Corporation

20070272948 - Inverter with dual-gate organic thin-film transistor: Provided is an inverter having a new structure capable of easily controlling a threshold voltage according to position in fabricating an inverter circuit on a plastic substrate using an organic semiconductor. A driver transistor is formed with a dual-gate structure and a positive bias voltage is applied to the top... Agent: Ladas & Parry LLP

20070272949 - Semiconductor integrated circuit, and method and apparatus for designing wiring pattern of semiconductor integrated circuit: It is an object to provide a semiconductor integrated circuit which can easily be designed and has a low wiring resistance, and a method and apparatus for designing the semiconductor integrated circuit. In a semiconductor integrated circuit apparatus according to the invention, a first wiring layer is provided with a... Agent: Mcdermott Will & Emery LLP

20070272951 - Nanoscopic wire-based devices and arrays: Electrical devices comprised of nanoscopic wires are described, along with methods of their manufacture and use. The nanoscopic wires can be nanotubes, preferably single-walled carbon nanotubes. They can be arranged in crossbar arrays using chemically patterned surfaces for direction, via chemical vapor deposition. Chemical vapor deposition also can be used... Agent: Wolf Greenfield & Sacks, P.C.

20070272950 - Semiconductor memory devices and methods of fabricating the same: A method of fabricating a semiconductor memory device includes forming a first insulating layer and a sacrificial layer on a substrate. The first insulating layer and the sacrificial layer have an opening therein. A first conductive layer is formed in the opening and on the sacrificial layer. A second insulating... Agent: Marger Johnson & Mccollom, P.C.

20070272952 - Electronic devices including a semiconductor layer: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the... Agent: Larson Newman Abel Polansky & White, LLP

20070272953 - Power semiconductor component with charge compensation structure and method for producing the same: A power semiconductor device with charge compensation structure and a method for producing the same is disclosed. In one embodiment, the power semiconductor device has in a semiconductor body a drift path between a body zone and a substrate region. The drift path is divided into drift zones of a... Agent: Dicke, Billig & Czaja

20070272954 - Fin-fet device structure formed employing bulk semiconductor substrate: A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A... Agent: Tung & Associates

20070272956 - Nonvolatile semiconductor memory: A control electrode is provided via an insulating film on one main surface of a semiconductor substrate having a first conductivity type. A pair of dopant diffusion regions are formed, with the control electrode therebetween, in a surface layer region of the semiconductor substrate. Resistance variation sections are formed in... Agent: Rabin & Berdo, PC

20070272955 - Reliable contacts: A nickel-based germanide contact includes a processing material that inhibits agglomeration of nickel-based germanide during processing to form the contact as well as during post-germanidation processes. The processing material is either in the form of a capping layer over the nickel layer or integrated into the nickel layer used to... Agent: HorizonIPPte Ltd

20070272957 - Gallium nitride material devices and associated methods: Gallium nitride material devices and methods associated with the same. In some embodiments, the devices may be transistors which include a conductive structure connected to a source electrode. The conductive structure may form a source field plate which can be formed over a dielectric material and can extend in the... Agent: Wolf Greenfield & Sacks, P.C.

20070272958 - Solid-state image sensing device and manufacturing method thereof: Pixel portions each of which has a charge storage portion formed in a semiconductor substrate 11 and a transfer gate for transferring charges stored in the charge storage portion are isolated from each other by a device isolation region in the semiconductor substrate. A buried gate electrically connected to the... Agent: Mcdermott Will & Emery LLP

20070272959 - Ferroelectric memory cell and manufacturing method thereof: A method of manufacturing a ferroelectric memory cell includes: forming device isolation regions; and source/drain regions; forming a gate insulating film on the semiconductor substrate; forming a gate electrode on the gate insulating film; forming; forming a contact plug to be connected to one of the source/drain regions. The method... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070272960 - Ferroelectric memory transistor with conductive oxide gate structure: The present invention discloses a ferroelectric transistor having a conductive oxide in the place of the gate dielectric. The conductive oxide gate ferroelectric transistor can have a three-layer metal/ferroelectric/metal or a two-layer metal/ferroelectric on top of the conductive oxide gate. By replacing the gate dielectric with a conductive oxide, the... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070272961 - Capacitor below the buried oxide of soi cmos technologies for protection against soft errors: Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070272962 - Semiconductor device with l-shaped spacer and method of manufacturing the same: A semiconductor device with an L-shape spacer and the method for manufacturing the same are provided. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer. The substrate comprises a shallow trench isolation structure and a neighboring active area. The composite spacer is formed on the... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC

20070272963 - Semiconductor device and method for fabricating the same: A semiconductor device having in a deep hole formed in a first interlayer insulating film a memory cell region that comprises a plurality of capacitors having a lower electrode 229 composed of a crown structure having an outside face and inner face, a first upper electrode 231 facing the outside... Agent: Paul J. Esatto, Jr. Scully, Scott, Murphy & Presser, P.C.

20070272964 - Semiconductor device and method of manufacturing the same: Provided is a semiconductor device including: a silicon substrate; at least two trenches spaced apart from each other, being in parallel with each other, and being formed by vertically etching the silicon substrate from a surface thereof; an electrically insulating film for burying therein at least bottom surfaces of the... Agent: Bruce L. Adams, Esq.

20070272965 - Method for producing a dielectric interlayer and storage capacitor with such a dielectric interlayer: A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.... Agent: Morrison & Foerster LLP

20070272966 - Nonvolatile semiconductor memory device and method of fabricating the same: A method of fabricating a nonvolatile semiconductor memory device includes forming a first dielectric layer on a major surface of a semiconductor substrate, forming a floating gate electrode layer on the first dielectric layer, and forming a second dielectric layer, which includes a metal oxide film or a stacked film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070272969 - Field-effect transistor: A field-effect transistor is provided which includes: a first nitride semiconductor layer having a lattice constant a1 and a bandgap Eg1; a second nitride semiconductor layer stacked on the first nitride semiconductor layer and having a lattice constant a2 and a bandgap Eg2; a source electrode and a drain electrode... Agent: Birch Stewart Kolasch & Birch

20070272968 - Semiconductor device and a method of manufacturing the same: Separate first and second floating gates for attracting carriers transferring in a transistor structure having a channel region and first and second main electrode regions into charge storage films therebelow are formed so as to largely face a control gate. The control gate between the separate first and second floating... Agent: Rabin & Berdo, PC

20070272967 - Method for modulating the effective work function: A new MOSFET device is described comprising a metal gate electrode, a gate dielectric and an interfacial layer. The electrostatic potential at an interface between the gate electrode and the gate dielectric of a MOSFET device can be controlled by introducing one or more interfacial layer(s) of a dielectric material,... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20070272970 - Non-volatile memory: A non-volatile memory and a method of fabricating the same are described. First, a substrate is provided. Then, a plurality of stack structures is formed on the substrate. Each stack structure comprises, from bottom to top, a bottom dielectric layer, a charge trapping layer, a top dielectric layer, a control... Agent: Jianq Chyun Intellectual Property Office

20070272971 - Non-volatile memory device and method of fabricating the same: In the non-volatile memory device, a first isolation layer is formed to have a plurality of depressions each having a predetermined depth from an upper surface of the semiconductor substrate. A fin type first active region is defined by the first isolation layer and has one or more inflected portions... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070272972 - Semiconductor memory device and manufacturing method thereof: A semiconductor device, in which both a reduction in a resistivity of a gate electrode and stabilization of transistor characteristics is achieved, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a semiconductor substrate, a plurality of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070272973 - Semiconductor memory devices including recess-type control gate electrodes and methods of fabricating the semiconductor memory devices: A semiconductor memory device includes a semiconductor substrate, a control gate electrode recessed in the semiconductor substrate, a storage node layer interposed between a sidewall of the control gate electrode and the semiconductor substrate, a tunneling insulation layer interposed between the storage node layer and the semiconductor substrate, a blocking... Agent: Harness, Dickey & Pierce, P.L.C

20070272974 - Twin-gate non-volatile memory cell and method of operating the same: A non-volatile memory cell with twin gates formed on an N-well is provided. The non-volatile memory cell includes at least a first gate, a second gate, a pair of NO (Nitride/Oxide) spacer layers, a pair of ONO (Oxide/Nitride/Oxide) spacers, a source, a drain, an extension source and an extension drain.... Agent: Jianq Chyun Intellectual Property Office

20070272975 - Method of forming a semiconductor device having an interlayer and structure therefor: A stack located over a substrate. The stack includes a layer between a dielectric layer and a metal layer. The layer includes a halogen and a metal. In one embodiment, the halogen is fluorine. In one embodiment, the stack is a control electrode stack for a transistor. In one example... Agent: Freescale Semiconductor, Inc. Law Department

20070272976 - Power semiconductor module: A power semiconductor module having an electrically insulating substrate, to be arranged with a circuit board. The circuit board is spaced apart from the substrate by a housing. First conductor tracks are disposed inside the substrate, facing the circuit board, for receiving power semiconductor devices which can be driven by... Agent: Cohen, Pontani, Lieberman & Pavane

20070272977 - Power semiconductor device: A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070272978 - Semiconductor device including a vertical gate zone, and method for producing the same: A semiconductor device includes a semiconductor body defining a trench structure having walls. A plurality of vertical gate zones each have a gate electrode and a gate oxide that covers the walls of the trench structure. A body zone of a first conduction type is arranged between two of the... Agent: Dicke, Billig & Czaja

20070272979 - Semiconductor device: A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070272980 - Semiconductor device with vertical current flow and low substrate resistance and manufacturing process thereof: A semiconductor device with vertical current flow includes a body having a substrate made of semiconductor material. At least one electrical contact on a first face of the body. A metallization structure is formed on a second face of the body, opposite to the first face. The metallization structure is... Agent: Graybeal, Jackson, Haley LLP

20070272981 - Cmos image sensor and method for fabricating the same: A complementary metal-oxide semiconductor (CMOS) image sensor includes a photodiode formed in a substrate structure, first to fourth gate electrodes formed over the substrate structure, spacers formed on both sidewalls of the first to fourth gate electrodes and filled between the third and fourth gate electrodes, a first ion implantation... Agent: Morgan Lewis & Bockius LLP

20070272982 - Electro-optical apparatus, electronic apparatus, and method of manufacturing electro-optical apparatus: Provided is an electro-optical apparatus including a first thin-film transistor having a first gate electrode, a first gate insulating layer and a first active layer, which are respectively formed of a conductive film, an insulating film and a semiconductor film, in a pixel region of a device substrate, the apparatus... Agent: Oliff & Berridge, PLC

20070272983 - Active device array substrate: An active device array substrate, including a substrate, a plurality of pixel units, a plurality of first lead wires, an insulating layer, a plurality of second lead wires and a passivation layer, is provided. The active device array substrate has a display area and a peripheral area. The pixel units... Agent: Jianq Chyun Intellectual Property Office

20070272984 - Semiconductor device manufacturing method and semiconductor device: Provided is a semiconductor device manufacturing method including a field oxide insulation film forming step including forming a field oxide insulation film (12) so that, in an active region (13), a portion (13a), which corresponds to a side surface portion of the active region (13) opposing a rotation center (O)... Agent: Bruce L. Adams, Esq.

20070272985 - Stagger memory cell array: A memory device includes a first memory cell area having a first latch area where one or more electronic components are constructed for storing a value, and a first peripheral area surrounding the first latch area; and a second memory cell area being disposed adjacent to a first side of... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20070272986 - Modular bipolar-cmos-dmos analog integrated circuit and power transistor technology: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of... Agent: Patentability Associates

20070272987 - Non-volatile electrical phase change memory device comprising interfacial control layer and method for the preparation thereof: wherein an interfacial control layer is formed at the interface of the contact hole between the phase change layer and the bottom electrode layer, said interfacial control layer having strong chemical bonds with the phase change material as well as electrical resistivity and thermal conductivity values lower than those of... Agent: Anderson, Kill & Olick, P.C.

20070272988 - Voltage regulating apparatus: There is disclosed a voltage regulating apparatus with a short settling time and a small current consumption. The voltage regulating apparatus comprises a reference voltage generator including an MOSFET array comprising a plurality of MOSFETs with a structure in which a drain and a source are connected in series with... Agent: Lowe Hauptman Ham & Berner, LLP

20070272989 - Semiconductor device and method for manufacturing the same: In the fabrication of semiconductor devices such as active matrix displays, the need to pattern resist masks in photolithography increases the number of steps in the fabrication process and the time required to complete them and consequently represents a substantial cost. This invention provides a method for forming an impurity... Agent: Fish & Richardson P.C.

20070272990 - Diffusion tube, dopant source for a diffusion process and diffusion method using the diffusion tube and the dopant source: According to an exemplary embodiment of the present invention, a diffusion tube includes a diffusion housing which includes a first cavity within a first end which receives a diffusion target, a second cavity within a second end which receives a dopant source for diffusion, and a diffusion port disposed between... Agent: Cantor Colburn, LLP

20070272991 - Method and device for alternately contacting two wafers: A method and device for alternately contacting two wafer-like component composite arrangements (12, 14) consisting of a plurality of cohesively designed similar components, in particular of a semiconductor wafer with a function component wafer for manufacturing electronic modules on a wafer level, in which the two component composite arrangements, each... Agent: Blakely Sokoloff Taylor & Zafman

20070272992 - Method for fabricating condenser microphone and condenser microphone: A first semiconductor chip includes a fixed electrode formed on a first semiconductor substrate and a plurality of first metal spacers formed on a first interlayer dielectric. A second semiconductor chip includes a vibrating electrode formed on a second semiconductor substrate and a plurality of second metal spacers formed on... Agent: Mcdermott Will & Emery LLP

20070272993 - Optical sensor assemblage and corresponding manufacturing method: The present invention creates an optical sensor assemblage, in particular a thermopile sensor assemblage, comprising a sensor chip assemblage (10; 10′) having an optically transparent irradiation region (OB; OB′), a mounting region (RB; RB′) surrounding the latter, and a wire-bond region (BB); an optically isolating mounting frame (MLF; MLF′) having... Agent: Kenyon & Kenyon LLP

20070272994 - Sensor semiconductor device: A sensor semiconductor device is proposed. A plurality of metal bumps and a sensor chip are mounted on a substrate. A dielectric layer and a circuit layer are formed on the substrate, wherein the circuit layer is electrically connected to the metal bumps and the sensor chip. Thus, the sensor... Agent: Ishimaru & Zahrt LLP

20070272995 - Photosensitive device: A photosensitive device is provided. The photosensitive device can be an image sensor or a solar cell. The photosensitive device includes a driving circuit such as photo sensor circuit or solar cell circuit, and a nano-crystal layer. The nano-crystal layer is located above the driving circuit and includes a silicon... Agent: Birch Stewart Kolasch & Birch

20070272996 - Self-aligned implanted waveguide detector: A method of fabricating a detector, the method including forming an island of detector core material on a substrate, the island having a horizontally oriented top end, a vertically oriented first sidewall, and a vertically oriented second sidewall that is opposite said first sidewall; implanting a first dopant into the... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070272998 - Semiconductor device: With this semiconductor device, the distortion and cracking of a thinned portion of a semiconductor substrate are prevented to enable high precision focusing with respect to a photodetecting unit and uniformity and stability of high sensitivity of the photodetecting unit to be maintained. A semiconductor device 1 has a semiconductor... Agent: Drinker Biddle & Reath (dc)

20070272997 - Semiconductor device and method for manufacturing the same: With this semiconductor device, the distortion and cracking of a thinned portion of a semiconductor substrate are prevented to enable high precision focusing with respect to a photodetecting unit and uniformity and stability of high sensitivity of the photodetecting unit to be maintained. A semiconductor device 1 has a semiconductor... Agent: Drinker Biddle & Reath (dc)

20070272999 - Voltage sustaining layer with opposite-doped islands for semiconductor power devices: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070273000 - Trench widening without merging: A semiconductor fabrication method comprises steps of providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench comprises a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on... Agent: Schmeiser, Olsen & Watts

20070273001 - System on chip and method for manufacturing the same: A system-on-chip semiconductor structure. The system-on-chip semiconductor structure comprises a substrate, a low voltage device, a middle voltage device, at least one high voltage device and a plurality of isolation structures. The substrate has a low voltage circuit region and a high voltage circuit region. The low voltage device is... Agent: Jianq Chyun Intellectual Property Office

20070273002 - Semiconductor memory devices having fuses and methods of fabricating the same: An integrated circuit device is provided with a plurality of normally open fuse elements. A fuse element includes a fuse insulation film lining a sidewall and a bottom of a recess in a semiconductor substrate. A semiconductor fuse region of first conductivity type (e.g., N-type) is provided in the semiconductor... Agent: Myers Bigel Sibley & Sajovec

20070273003 - Semiconductor device and manufacturing method thereof: A semiconductor device and a method of manufacturing the semiconductor device is provided. The method includes the steps of forming a first insulating layer on a top surface of a semiconductor substrate having a plurality of patterns, immediately before gaps between the patterns are completely closed; forming a lower insulating... Agent: Lowe Hauptman Ham & Berner, LLP

20070273004 - Like integrated circuit devices with different depth: The invention forms integrated circuit devices of similar structure and dissimilar depth, such as interconnects and inductors, simultaneously. The invention deposits a conformal polymer over an area on a substrate with vias and an area without vias. Simultaneously, cavities are formed in the areas with and without vias. The depth... Agent: International Business Machines Corporation Dept. 18g

20070273005 - Mim type capacitor: A method of fabricating an MIM type capacitor includes at least one of: Forming a first trench within an insulating interlayer formed on a semiconductor substrate. Forming a lower electrode layer of a metal nitride layer substance to fill an inside of the first trench. Forming a second trench on... Agent: Sherr & Nourse, PLLC

20070273006 - Bipolar method and structure having improved bvceo/rcs trade-off made with depletable collector columns: In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in... Agent: Mh2 Technology Law Group

20070273007 - Bipolar-transistor and method for the production of a bipolar-transistor: The invention relates to NPN and PNP bipolar transistors and to a method for the production thereof, said transistors being characterised by a particularly high collector-emitter and collector-base blocking voltage. The blocking voltage is increased by a particular doping profile. An NPN bipolar transistor comprises a p-doped substrate (1), a... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20070273008 - Multilayer dielectric substrate and semiconductor package: A multilayer dielectric substrate that mounts a semiconductor device in a cavity formed on a substrate. The multilayer dielectric substrate includes an opening formed in a surface-layer grounding conductor on the substrate in the cavity, and an impedance transformer, with a length of about ¼ of an in-substrate effective wavelength... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070273010 - Design and method for attaching a die to a leadframe in a semiconductor device: The semiconductor device whose structure is formed from a die attached to a leadframe comprises a die having an attachment member, and a leadframe having a recess configured to receive a corresponding attachment member so as to establish a connection between the die and the leadframe.... Agent: Texas Instruments Incorporated

20070273009 - Highly efficient both-side-cooled discrete power package, especially basic element for innovative power modules: Two DBC wafers have patterned first conductive surfaces which receive a semiconductor die in sandwich fashion. Lead frame terminally extending into the package interior and are connected to the die terminals. The outer conductive surfaces of each of the wafers are available for two-sided cooling of the semiconductor.... Agent: Ostrolenk Faber Gerb & Soffen

20070273011 - Method for fabricating a module having an electrical contact-connection: A method for fabricating a module having an electrical contact-connection is disclosed. One embodiment provides a chip having a contact area, applying a contact elevation to the contact area and applying a solder material to the contact elevation. The contact elevation may be applied to the contact area by using... Agent: Dicke, Billig & Czaja

20070273012 - Semiconductor device: A semiconductor device comprising, a layer on which a semiconductor element is arranged, an insulation layer on which a wiring connected to the semiconductor element is arranged, dummy metal plates arranged in the insulation layer, wherein the dummy metal plates have an aspect ratio larger than 1, and are arranged... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070273013 - Packaging for micro electro-mechanical systems and methods of fabricating thereof: Embodiments of the present disclosure provide systems and methods for producing micro electro-mechanical device packages. Briefly described, in architecture, one embodiment of the system, among others, includes a micro electro-mechanical device formed on a substrate layer; and a thermally decomposable sacrificial structure protecting at least a portion of the micro... Agent: Christopher B Linder Thomas Kayden Horstemeyer & Risley

20070273015 - Semiconductor device: A semiconductor device 1 includes a semiconductor chip 10. Each of the semiconductor chips 10 includes a semiconductor substrate 12, a semiconductor layer 14 and an interconnect layer 16. The semiconductor substrate 12 has a specific resistance ρ1 (first specific resistance). A semiconductor layer 14 is provided on the semiconductor... Agent: Young & Thompson

20070273014 - System in package module: A System in Package (SIP) module. The module includes a printed circuit board with at least one cavity formed therein. The module also includes at least one first device mounted in the cavity and a circuit pattern formed on an undersurface of the cavity and electrically connected to the first... Agent: Lowe Hauptman Ham & Berner, LLP

20070273016 - Double sided semiconduction device with edge contact and package therefor: A semiconductor die has devices such as MOSgated devices, diodes and the like formed into the top and bottom surfaces of the die. One terminal of each of the devices terminal in the interior center of the die and a common contact is made to the interior center of the... Agent: Ostrolenk Faber Gerb & Soffen

20070273017 - Quad flat no-lead chip carrier with stand-off: A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed... Agent: John A. Jordan, Esq.

20070273018 - Semiconductor apparatus and method for manufacturing the same: It is made possible to provide a highly integrated, thin apparatus can be obtained, even if the apparatus contains MEMS devices and semiconductor devices. A semiconductor apparatus includes: a first chip comprising a MEMS device formed therein; a second chip comprising a semiconductor device formed therein; and an adhesive layer... Agent: Amin, Turocy & Calvin, LLP

20070273019 - Semiconductor package, chip carrier structure thereof, and method for fabricating the chip carrier: A semiconductor package, a chip carrier structure thereof, and a method for fabricating the chip carrier structure are provided. A substrate having a mounting region and a covering region is disposed in an opening of a carrier. A molding process is performed to form an encapsulant on the covering region... Agent: Edwards Angell Palmer & Dodge LLP

20070273020 - Semiconductor device: The present invention provides a method of manufacturing semiconductor device. The method includes providing a semiconductor wafer having a main surface; defining a chip forming region which includes chip regions defined by scribe lines, and a peripheral region which surrounds the chip forming region, on the main surface; forming circuit... Agent: Rabin & Berdo, PC

20070273021 - Semiconductor package: A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second... Agent: Foley And Lardner LLP Suite 500

20070273022 - Semiconductor device: In a semiconductor device comprising a ceramic substrate, a surface mount component, and sealing resin and obtained by division into pieces, the ceramic substrate is composed of a multiple piece substrate provided with dividing grooves for the division into pieces on both front and rear surfaces in advance, a plurality... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070273023 - Integrated circuit package having exposed thermally conducting body: An apparatus and method for a wire-bond die-up area array package is described. The package includes an integrated circuit (IC) die, a substrate, and a thermally conducting body. A bottom surface of the IC die is exposed through an opening in a central region of the substrate. The die is... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070273024 - Cooling system with a bubble pump: The present invention relates to a closed system for cooling without moving mechanical parts and at a low noise level, one or more heat-emitting elements. The system comprises a first heat-receiving part that is adapted to receive heat from the at least one heat-emitting element, a cooling fluid for absorption... Agent: Volentine & Whitt PLLC

20070273025 - Device comprising circuit elements connected by bonding bump structure: A bonding-bump (1) of small dimensions comprises a gold pedestal portion (2) formed on a circuit element (10), a nickel barrier layer (3) formed on the pedestal portion (2), and a soldering portion (5) formed on the barrier layer (3). The soldering portion (5) comprises first (6) and second (8)... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070273026 - Semiconductor package substrate: A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one... Agent: Edwards Angell Palmer & Dodge LLP

20070273027 - Method of forming dual damascene pattern: A method of forming a dual damascene pattern for a metal interconnection by a relatively simple process. Only a portion of an interlayer insulating film is initially etched when forming a via hole. When the interlayer insulating is etched to form a trench, the remaining portion of the via hole... Agent: Sherr & Nourse, PLLC

20070273028 - Semiconductor integrated circuit device comprising different level interconnection layers connected by conductor layers including conductor layer for redundancy: A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for... Agent: Amin, Turocy & Calvin, LLP

20070273029 - Photo mask set for forming multi-layered interconnection lines and semiconductor device fabricated using the same: A photo mask set for forming multi-layered interconnection lines and a semiconductor device fabricated using the same includes a first photo mask for forming lower interconnection lines and a second photo mask for forming upper interconnection lines. The first and second photo masks have lower opaque patterns parallel with each... Agent: Marger Johnson & Mccollom, P.C.

20070273030 - Semiconductor device having metal lines with slits: A semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, and a plurality of metal line patterns on the insulation layer. First and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from... Agent: Lee & Morse, P.C.

20070273031 - Method of wire bonding over active area of a semiconductor circuit: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over... Agent: Saile Ackerman LLC

20070273032 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273033 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273034 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273035 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273036 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273037 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273038 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273039 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273040 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273041 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273042 - Copper-filled trench contact for transistor performance improvement: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length... Agent: Blakely Sokoloff Taylor & Zafman

20070273043 - Wire bonding structure and method that eliminates special wire bondable finish and reduces bonding pitch on substrates: A semiconductor package has a semiconductor die disposed on a substrate. A bond wire is connected between a first bonding site on the semiconductor die and a second bonding site on the substrate. The first bonding site is a die bond pad; the second bonding site is a stitch bond.... Agent: Quarles & Brady LLP

20070273044 - Adhesion enhancement for metal/dielectric interface: An interconnect structure and method of fabricating the same in which the adhesion between a chemically etched dielectric material and a noble metal liner is improved are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modified the chemical nature... Agent: Scully Scott Murphy & Presser, PC

20070273045 - Printed wiring board, method for forming the printed wiring board, and board interconnection structure: A board interconnection structure having a first printed wiring board in which a first conductive circuit is arranged on a first insulating layer, the first conductive circuit having, on an end portion thereof, a first connection terminal in which an upper surface width is narrower than a bottom surface width;... Agent: Sughrue Mion, PLLC

20070273046 - Semiconductor component with connecting elements and method for producing the same: A semiconductor component with connecting elements between a semiconductor chip made from a semiconductor wafer with discrete semiconductor components and a superordinate circuit carrier is disclosed. The semiconductor component has a coplanar area having top sides of the connecting elements and a plastic housing composition. The connecting element has a... Agent: Dicke, Billig & Czaja

20070273047 - Printed wiring board and manufacturing method thereof: A printed wiring board having an interlayer insulation layer and conductive circuits formed on the interlayer insulation layer. The conductive circuits include a first conductive circuit and a second conductive circuit positioned adjacent to each other, and the first and second conductive circuits satisfy a formula, 0.10 T≦|W1−W2|≦0.73 T, where... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070273048 - Shapes-based migration of aluminum designs to copper damascene: An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.... Agent: Schmeiser, Olsen & Watts

20070273049 - Interconnect structure and formation for package stacking of molded plastic area array package: Apparatuses, methods, and systems for improved integrated circuit packages are described. An integrated circuit (IC) package includes a substrate having opposing first and second surfaces, an IC die, a plurality of conductive elements, and an encapsulating material. The substrate has a plurality of contact pads on the first surface that... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070273050 - Semiconductor device and method of manufacturing thereof: A method of manufacturing a semiconductor device sealed in a cured silicone body by placing an unsealed semiconductor device into a mold and subjecting a curable liquid silicone composition that fills the spaces between the mold and the unsealed semiconductor device to compression molding under a predetermined molding temperature, wherein... Agent: Howard & Howard Attorneys, P.C.

20070273051 - Curable organopolysiloxane composition, use of the cured product of the composition, and semiconductor device: A curable organopolysiloxane composition capable of forming cured products of superior optical transmittance exhibiting little heat-induced yellowing over time. A semiconductor device having semiconductor elements encapsulated in a cured product of the composition. The composition includes (A) an organopolysiloxane having at least two silicon-bonded alkenyl groups per molecule and bearing... Agent: Howard & Howard Attorneys, P.C.

20070267618 - Memory device: A phase change memory cell includes a first spacer electrically coupled to a first electrode and to a second spacer. The first spacer includes a planar base contacting the first electrode and a wall extending from the planar base. The second spacer is electrically coupled between a second electrode and... Agent: Dicke, Billig & Czaja

20070267619 - Memory using tunneling field effect transistors: A memory includes a first tunneling field effect transistor including a first drain and a first source, the first drain coupled to a first resistive memory element. The memory includes a second tunneling field effect transistor including a second drain and sharing the first source, the second drain coupled to... Agent: Dicke, Billig & Czaja

20070267620 - Memory cell including doped phase change material: A phase change memory cell includes a phase change material doped with a first material having a resistivity that decreases less than one decade per 20 degrees Celsius when transitioning from an amorphous state to a crystalline state.... Agent: Dicke, Billig & Czaja

20070267622 - Multi-functional chalcogenide electronic devices having gain: Multi-functional electronic switching and current control device comprising a chalcogenide material. The devices include a load terminal, a reference terminal and a control terminal. Application of a control signal to the control terminal permits the device to function in one or more of the following modes reversibly: (1) a gain... Agent: Energy Conversion Devices, Inc.

20070267621 - Resistive memory device: A programmable resistive memory cell comprising a lower electrode, a programmable resistance layer, and an upper electrode, wherein the programmable resistance layer comprises a first transition metal oxide and a second transition metal oxide.... Agent: Dicke, Billig & Czaja

20070267623 - Multi-functional electronic devices: Multi-functional electronic switching and current control devices comprising a material capable of supporting a space-charge. The devices include a load terminal, a reference terminal and a control terminal in contact with the space-charge material and a space-charge region is present at each of the multiple terminals, where each space-charge region... Agent: Energy Conversion Devices, Inc.

20070267624 - Multi-functional chalcogenide electronic devices having gain: Multi-functional electronic switching and current control device comprising a chalcogenide material. The devices include a load terminal, a reference terminal and a control terminal. Application of a control signal to the control terminal permits the device to function in one or more of the following modes reversibly: (1) a gain... Agent: Energy Conversion Devices, Inc.

20070267629 - Laser irradiation device and method of fabricating oled using the same: A laser irradiation device and a method of fabricating an OLED having an increased laser efficiency. The laser irradiation device includes: a light source to produce a laser beam; a collimation lens disposed adjacent to the light source; and an asymmetrical micro lens array disposed adjacent to the collimation lens.... Agent: Stein, Mcewen & Bui, LLP

20070267628 - Method for forming electrodes of organic electronic devices, organic thin film transistors comprising such electrodes, and display devices comprising such transistors: Disclosed are methods for forming electrodes for organic electronic devices which allow for the use of an improved range of conductive materials for forming source/drain electrodes. The disclosed methods also allow for the use of different conductive materials for forming data lines and source/drain electrodes during the fabrication of organic... Agent: Harness, Dickey & Pierce, P.L.C

20070267630 - Method of manufacturing organic thin film transistor and organic thin film transistor: A method of manufacturing an organic thin film transistor characterized by low costs and high performances, the method in which the self-assemble monolayer is formed in a short period of time, and the organic thin film transistor are provided. A method of manufacturing an organic thin film a transistor having... Agent: Brinks Hofer Gilson & Lione

20070267627 - Organic memory device and fabrication method thereof: An organic memory device and a method for fabricating the memory device are provided. The organic memory device may include a first electrode, a second electrode, and an ion transfer layer between the first electrode and the second electrode. The organic memory device may have lower operating voltage and current,... Agent: Harness, Dickey & Pierce, P.L.C

20070267631 - System and method for increasing productivity of combinatorial screening: The present invention provides systems and methods for simultaneous, parallel and/or rapid serial testing of material parameters or other parameters of the result of a process. The testing is typically used for screening different methods or materials to select those methods or materials with desired properties. A reactor structure used... Agent: Patent Law Group LLP

20070267633 - Flat panel display device and method for fabricating same: Provided is a flat panel display device and a method for fabricating the same. The flat panel display device comprises a first substrate, a light emitting unit, a second substrate, and insulating films. The light emitting unit comprises thin film transistors positioned on the first substrate, a first electrode electrically... Agent: Brinks Hofer Gilson & Lione

20070267634 - Hybrid strained orientated substrates and devices: A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor material and a second semiconductor material, which is different from... Agent: Schmeiser, Olsen & Watts

20070267635 - Thin film transistor: A thin film transistor is disclosed, comprising a substrate, a polysilicon layer overlying the substrate, a gate insulating layer overlying the polysilicon layer, a gate electrode, a dielectric interlayer overlying the gate electrode and gate insulating layer, and a source/drain electrode overlying the dielectric interlayer. Specifically, the gate electrode comprises... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070267637 - Light emitting package and light emitting package array: Example embodiments may include a light emitting device package. The light emitting device package may include a light emitting device, a package body including a cavity having a bottom surface on which the light emitting device is mounted and a side surface for reflecting light emitted from the light emitting... Agent: Harness, Dickey & Pierce, P.L.C

20070267638 - Light emission device and electron emission display: A light emission device includes: first and second substrates facing each other and spaced apart from each other; an electron emission region on an inner surface of the first substrate; a driving electrode on the inner surface of the first substrate to control an electron emission of the electron emission... Agent: Christie, Parker & Hale, LLP

20070267639 - Light emission device, method of manufacturing electron emission unit for the light emission device, and display device having the light emission device: l

20070267641 - Light emitting device and method of manufacturing the same: A light emitting device and a method of manufacturing the same are provided. The light emitting device comprises a substrate, a gate electrode positioned on the substrate, a first insulating layer positioned on the substrate comprising the gate electrode, an amorphous silicon layer positioned on the first insulating layer so... Agent: Brinks Hofer Gilson & Lione

20070267640 - Semiconductor light emitting diode and method of manufacturing the same: The present invention relates to a semiconductor light emitting diode. The semiconductor light emitting diode includes a substrate; an n-type nitride semiconductor layer that is formed on the substrate; an active layer that is formed on the n-type nitride semiconductor layer; a p-type nitride semiconductor layer that is formed on... Agent: Mcdermott Will & Emery LLP

20070267642 - Light-emitting devices and methods for manufacturing the same: Light-emitting device assemblies are described. The assemblies can include a light-emitting device, an optional package supporting the light-emitting device, and a base supporting the light-emitting device or the optional package. The base may include a protrusion extending in the direction of the light-emitting device. The thermally conductive pathway can extend... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.C.

20070267643 - Semiconductor light emitting device and method for manufacturing the same: A reliable semiconductor light-emitting device and a method for manufacturing the same can be provided in which peeling can be prevented in a phase boundary, and optical axis positional errors between the optical lens and a semiconductor light-emitting chip can be reduced or prevented. The semiconductor light-emitting device can include... Agent: Cermak Kenealy & Vaidya, LLP

20070267645 - Ultraviolet ray emitting element package: An ultraviolet ray emitting element package comprises a condenser lens, and an ultraviolet ray emitting element which is arranged approximately at a center and in a bottom side of the condenser lens and which is apart from a bottom of the condenser lens, wherein a refractive index difference reduction substance... Agent: Rader Fishman & Grauer PLLC

20070267648 - Light emitting device and method for fabricating the same: A light emitting device includes a first substrate and a second substrate. Each substrate may be subdivided into a contact region and a pixel region. Conductive elements positioned in each of the contact region and pixel region of the first substrate may be of substantially the same height.... Agent: Brinks Hofer Gilson & Lione

20070267650 - Light-emitting device: A light-emitting device comprises a carrier, an insulated transparent adhesive layer, and a multi-layer epitaxial light-emitting structure located on the upper side of the insulated transparent adhesive layer. The top surface of the carrier comprises a first contact pad and a second contact pad. The insulated transparent adhesive layer is... Agent: Bacon & Thomas, PLLC

20070267649 - Semiconductor laser device: In one aspect, a semiconductor laser device may include a supporting member, a semiconductor laser element provided over the supporting member, and configured to emit a laser from a front surface and monitoring laser from a rear surface, and a photo receiving element provided over the supporting member, and configured... Agent: Amin, Turocy & Calvin, LLP

20070267625 - Utilizing nanowire for different applications: One embodiment in accordance with the invention is an apparatus that can include a non-single crystal substrate and a nanowire grown from a surface of the non-single crystal substrate. Furthermore, the apparatus can also include an electrode coupled to the nanowire. It is noted that the nanowire can be electrically... Agent: Hewlett Packard Company

20070267626 - Semiconductor structure: The invention concerns a semiconductor structure comprising at least one first material region and a second material region, whereby the second material region epitaxially surrounds the first material region and forms a boundary surface. The structure is characterized in that Fermi level pinning is present on the non-epitaxial boundary surface... Agent: K.f. Ross P.C.

20070267632 - Apparatus and method for test structure inspection: Herein are described layouts of test structures and scanning methodologies that allow large probe currents to be used so as to allow the detection of resistive defects with a resistance lower than 1 MΩ while at the same time allowing a sufficient degree of localization to be obtained for root... Agent: Applied Materials, Inc. C/o Sonnenschein Nath & Rosenthal LLP

20070267636 - Gallium-nitride based light-emitting diode structure with high reverse withstanding voltage and anti-esd capability: An epitaxial structure for GaN-based LEDs to achieve better reverse withstanding voltage and anti-ESD capability is provided herein. The epitaxial structure has an additional anti-ESD thin layer as the topmost layer, which is made of undoped indium-gallium-nitrides (InGaN) or low-band-gap (Eg<3.4 eV), undoped aluminum-indium-gallium-nitrides (AlInGaN). The anti-ESD thin layer could... Agent: Lin & Associates Intellectual Property

20070267646 - Light emitting device including a photonic crystal and a luminescent ceramic: A semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region and a photonic crystal formed within or on a surface of the semiconductor structure is combined with a ceramic layer which is disposed in a path of light emitted by the light emitting... Agent: Patent Law Group LLP

20070267644 - Light emitting diode: A light emitting diode is disclosed, wherein the light extraction efficiency of a device can be enhanced by forming patterns on a substrate, a light emitting structure is formed on the substrate formed with the patterns, the substrate is removed from the light emitting structure, and patterns corresponding to those... Agent: Mckenna Long & Aldridge LLP

20070267647 - Optoelectronic device chip having a composite spacer structure and method making same: An optoelectronic device chip, and a method for making the chip, are disclosed. The chip comprises a device substrate, an optically transparent upper substrate, and a composite spacer layer which includes an adhesive material and a plurality of particles dispersed in said adhesive material. The distance between the device substrate... Agent: Tung & Associates Suite 120

20070267651 - Semiconductor device having a fuse and method of forming thereof: A fuse (43) is formed overlying a passivation layer (35) and under a packaging material (55, 70). In one embodiment, a fuse (43) is blown before the packaging material (55, 70) is formed. In some embodiments, the fuse (43) may be formed of metal (47), a metal nitride (42) or... Agent: Freescale Semiconductor, Inc. Law Department

20070267652 - Field-effect transistor: A field-effect transistor includes a channel layer formed of a III-V compound semiconductor excluding aluminum; a gate contact layer formed of a III-V compound semiconductor and provided on the channel layer, the III-V compound semiconductor having a dopant concentration equal to or less than 1×1016 cm−3, containing aluminum, and having... Agent: Leydig Voit & Mayer, Ltd

20070267653 - Semiconductor light-receiving device: f

20070267654 - In-situ defect reduction techniques for nonpolar and semipolar (al,ga, in)n: A method for growing reduced defect density planar gallium nitride (GaN) films is disclosed. The method includes the steps of (a) growing at least one silicon nitride (SiNx) nanomask layer over a GaN template, and (b) growing a thickness of a GaN film on top of the SiNx nanomask layer.... Agent: Gates & Cooper LLP Howard Hughes Center

20070267655 - Semiconductor device having mis structure and its manufacture method: A channel layer (11) made of compound semiconductor and a barrier layer (12) made of compound semiconductor having a band gap wider than the channel layer are formed over a substrate. A gate insulating film (13) made of first insulating material is formed on the barrier layer over the channel... Agent: Kratz, Quintos & Hanson, LLP

20070267656 - Bipolar transistors with depleted emitter: This invention disclosed a novel method of fully depleted emitter so that the built-in potential between emitter and the base becomes lower and the charge storage between the emitter and base becomes small. This concept also applies to the diodes or rectifiers. With depleted junction, this result in very fast... Agent: Ho-yuan Yu

20070267657 - Flat panel image display device: A flat panel image display device comprises: a rear plate including plural electron emission elements; a face plate disposed opposed to the rear plate, fluorescent members being disposed on a surface of the face plate opposed to the rear plate, and the fluorescent members being covered with a metal back... Agent: Fitzpatrick Cella Harper & Scinto