Active solid-state devices (e.g., transistors, solid-state diodes) inventions 11/07

20070272914 - Group-iii nitride vertical-rods substrate: The invention is directed to a group-III nitride vertical-rods substrate. The group-III vertical-rods substrate comprises a substrate, a buffer layer and a vertical rod layer. The buffer layer is located over the substrate. The vertical rod layer is located on the buffer layer and the vertical rod layer is comprised... Agent: Jianq Chyun Intellectual Property Office

20070272916 - Flash memory with deep quantum well and high-k dielectric: A flash memory cell includes a substrate and a gate structure formed on the substrate. The gate structure includes a tunneling layer over the substrate, a storage layer over the tunneling layer, a blocking layer over the storage layer, and a gate electrode over the dielectric. The storage layer preferably... Agent: Slater & Matsil, L.L.P.

20070272921 - Multicolor organic light-emitting device: Provided is a multicolor organic EL display having plural organic EL devices arranged on a substrate. The multicolor organic light-emitting device includes a substrate; plural organic light-emitting elements provided on the substrate, including a first organic light-emitting element of first emission color and a second organic light-emitting element of second... Agent: Fitzpatrick Cella Harper & Scinto

20070272919 - Stressed organic semiconductor devices: An organic semiconductor device including: a substrate having a first thermal expansion coefficient; and an organic semiconductor material coupled to the substrate at an interface therebetween. The organic semiconductor material includes a polymer organic semiconductor material and/or an oligomer organic semiconductor material. The organic semiconductor material also has a second... Agent: Ratnerprestia

20070272922 - Zno thin film transistor and method of forming the same: A zinc oxide (ZnO) thin film transistor (TFT) and method of forming the same are provided. The ZnO may include a ZnO semiconductor channel, a conductive ZnO gate forming an electric field around the ZnO semiconductor channel, an ZnO gate insulator interposed between the conductive ZnO gate and the ZnO... Agent: Harness, Dickey & Pierce, P.L.C

20070272923 - Charge pump with reduced turn-off time and phase locked loop including the same: A charge pump includes a current source/sink unit that charges/discharges an output node in response to an UP/DOWN signal generated by a PFD (phase frequency detector). The charge pump also includes a pull-down/pull-up unit configured to discharge/charge a cascode node within the current source/sink unit for a limited time period... Agent: Law Office Of Monica H Choi

20070272924 - Integrated circuit (ic) testing device with conduction interface: An IC testing device with conduction interface comprising an electrical circuit board having a test circuit; an insulation pad set on the circuit board; and a pressing block provided on the insulation pad for depressing the pins of the IC. While the conduction interface comprises a plurality of contactors provided... Agent: Lowe Hauptman Ham & Berner, LLP

20070272926 - Tft lcd array substrate and manufacturing method thereof: A TFT LCD array substrate and a manufacturing method thereof. The TFT LCD array substrate includes a substrate and a pixel array on the substrate. Each pixel has: a gate line and a gate electrode formed on the substrate; a gate insulating layer formed on the gate line and the... Agent: Hasse & Nesbitt LLC

20070272928 - Thin film transistor, array substrate having the thin film transistor and method of manufacturing the array substrate: A thin film transistor includes a semiconductor layer a source electrodes a drain electrode and a gate electrode. The semiconductor layer includes a plurality of grain boundaries disposed along a first direction. An acute angle between a gate electrode and a grain boundary prevents grain to boundaries from being formed... Agent: F. Chau & Associates, LLC

20070272933 - Light-emitting diode chip for backlight unit, manufacturing method thereof, and liquid crystal display device including the same: A light-emitting diode includes a substrate, a buffer layer on the substrate, a first semiconductor layer on the buffer layer, a light-emitting layer on the first semiconductor layer, a second semiconductor layer on the light-emitting layer, wherein the first semiconductor layer is partially exposed through the second semiconductor layer and... Agent: Mckenna Long & Aldridge LLP

20070272934 - Led device with improved life performance: A light-emitting diode with an improved service life is provided. The diode is formed from a transparent outer shell that contains a heat-resistant encapsulant at least partially surrounding a light-emitting diode clip. The first encapsulant is compressed between the outer shell and a second encapsulant when it is sealed into... Agent: Kathy Manke Avago Technologies Limited

20070272935 - Semiconductor device and manufacturing method therefor: A laser diode includes a first n-cladding layer disposed on and lattice-matched to an n-semiconductor substrate, wherein the first n-cladding layer is n-AlGaInP or n-GaInP; a second n-cladding layer of n-AlGaAs supported by the first n-cladding layer; and an inserted layer disposed between the first n-cladding layer and the second... Agent: Leydig Voit & Mayer, Ltd

20070272936 - Nitride based light emitting device: A nitride based light emitting device is disclosed. More particularly, a nitride based light emitting device capable of improving light emitting efficiency and reliability thereof is disclosed. The nitride based light emitting device includes a first conductive semiconductor layer connected to a first electrode, a second conductive semiconductor layer connected... Agent: Mckenna Long & Aldridge LLP

20070272937 - Nitride semiconductor light emitting device: where X is the distance between ends of the p-side pad electrode and the n-side pad electrode, Y is the distance between the end of the p-side pad electrode and the periphery of the translucent electrode, L is the length of the translucent electrode on the line connecting the centroids... Agent: Birch Stewart Kolasch & Birch

20070272939 - Tunnel vertical semiconductor devices or chips: The present invention discloses tunnel vertical semiconductor devices and chips comprising tunnel vertical GaN based, GaP based and ZnO based LEDs and manufacturing method. The structure of an embodiment of tunnel vertical semiconductor devices and chips is the following: first and second electrodes formed on first surface of a supporting... Agent: Hui Peng

20070272912 - Conductive paste and method of manufacturing electronic component using the same: Exemplary embodiments provided a conductive paste including an organic gold compound and a glass component in a solvent. When electrodes are formed on both surfaces of piezoelectric members using the conductive paste according to the invention, it is possible to improve the close adhesion property between the electrodes and the... Agent: Hunton & Williams LLP Intellectual Property Department

20070272913 - Forming nonvolatile phase change memory cell having a reduced thermal contact area: The invention provides for a nonvolatile memory cell comprising a heater layer in series with a phase change material, such as a chalcogenide. Phase change is achieved in chalcogenide memories by thermal means. Concentrating thermal energy in a relatively small volume assists this phase change. In the present invention, a... Agent: Vierra Magen/sandisk Corporation

20070272915 - Nitride semiconductor with active layer of quantum well structure with indium-containing nitride semiconductor: A nitride semiconductor device has a nitride semiconductor layer structure. The structure includes an active layer of a quantum well structure containing an indium-containing nitride semiconductor. A first nitride semiconductor layer having a band gap energy larger than that of the active layer is provided in contact with the active... Agent: Nixon & Vanderhye, PC

20070272920 - Electroluminescent materials and devices: Novel ruthenium, rhodium, palladium, osmium, iridium or platinum complexes of thianthrene ligands are electroluminescent compounds. According to the invention there is provided complexes of Formula (I).... Agent: David Silverstein Andover-ip-law

20070272918 - Organic photosensitive devices using subphthalocyanine compounds: An organic photosensitive optoelectronic device, having a donor-acceptor heterojunction of a donor-like material and an acceptor-like material and methods of making such devices is provided. At least one of the donor-like material and the acceptor-like material includes a subphthalocyanine, a subporphyrin, and/or a subporphyrazine compound; and/or the device optionally has... Agent: Kenyon & Kenyon LLP

20070272917 - Process for improved cross-linking of an organic semiconductor layer by using a plastiser containing oxetane groups: Semiconducting films are formed on a substrate by coating the substrate with a mixture of a semiconducting material and a substance which results in a Tg of the resulting mixture which is lower than that of the said material, and cross-linking the said material. Multilayer electronic devices may be produced... Agent: Millen, White, Zelano & Branigan, PC

20070272925 - Semiconductor device having multi-gate structure and method of manufacturing the same: Provided are a semiconductor device having a mesa-type active region including a plurality of slabs and a method of manufacturing the semiconductor device. The semiconductor device includes a first active region and a second active region. The first active region is formed in a line-and-space pattern on a substrate and... Agent: F. Chau & Associates, LLC

20070272927 - Thin film transistor, method of manufacturing the thin film transistor, active matrix type display device, and method of manufacturing the active matrix type display device: A TFT according to an embodiment of the present invention includes an insulative base film formed on a TFT array substrate, and a semiconductor film including a channel region formed on the base film, in which an impurity concentration of a channel region in the semiconductor film becomes substantially uniform... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070272929 - Diamond n-type semiconductor, method of manufacturing the same, semiconductor device, and electron emitting device: The present invention relates to a diamond n-type semiconductor in which the amount of change in carrier concentration is fully reduced in a wide temperature range. The diamond n-type semiconductor comprises a diamond substrate, and a diamond semiconductor formed on a main surface thereof and turned out to be n-type.... Agent: Mcdermott Will & Emery LLP

20070272930 - Light-emitting diode package: A light-emitting diode package (LED package) includes a LED and a carrier. The LED includes a substrate, a semiconductor layer, a first electrode and a second electrode. The semiconductor layer is located on a surface of the substrate and has a rough surface. The semiconductor layer includes a first-type doped... Agent: Jianq Chyun Intellectual Property Office

20070272932 - Light-emitting diode with improved ultraviolet light protection: The present application relates to a semiconductor device comprising one or more protective layers, and more specifically to a light-emitting diode comprising one or more ultraviolet protective layers. The use of said UV protective layers prevents the degradation of a LED by UV light. This results in a LED with... Agent: Kathy Manke Avago Technologies Limited

20070272931 - Methods, devices and systems producing illumination and effects: A device has a plurality of ultra-small resonant structures, each of said structures constructed and adapted to emit light at a particular wavelength when a beam of charged particles is passed nearby, wherein at least one of the light emitters emits light in a first range of wavelengths and wherein... Agent: Davidson Berquist Jackson & Gowdey LLP

20070272938 - Package for storing light emitting element and method for producing package for storing light emitting element: A light-emitting element storing package which ensures the efficient reflection of light emitted by a light-emitting element by a reflector frame and thereby improves the brightness of the emitted light, and a method of manufacturing the same are provided. The light-emitting element storing package includes: an insulating substrate consisting of... Agent: The Webb Law Firm, P.C.

20070272940 - Semiconductor device with a light emitting semiconductor die: A semiconductor device includes a light emitting semiconductor die mounted on at least one of first and second electrically conductive bonding pads, which are located on a first major surface of a substrate of the device. The light emitting semiconductor die has an anode and a cathode, which are electrically... Agent: Kathy Manke Avago Technologies Limited

20070272941 - Method for producing iii group element nitride crystal, production apparatus for use therein, and semiconductor element produced thereby: A method for producing Group-III-element nitride crystals by which an improved growth rate is obtained and large high-quality crystals can be grown in a short time, a producing apparatus used therein, and a semiconductor element obtained using the method and the apparatus are provided. The method is a method for... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070272942 - Semiconductor device and method of manufacturing the same: In a semiconductor device of the present invention, an N type epitaxial layer is divided into a plurality of element formation regions by an isolation region. In one of the element formation regions, a resistance is formed. Around the resistance, a protection element having a PN junction region is formed.... Agent: Fish & Richardson P.C.

20070272944 - Semiconductor member, manufacturing method thereof, and semiconductor device: An SiGe layer is grown on a silicon substrate. The SiGe layer or the silicon substrate and SiGe layer are porosified by anodizing the SiGe layer to form a strain inducing porous layer or a porous silicon layer and strain inducing porous layer. An SiGe layer and strained silicon layer... Agent: Fitzpatrick Cella Harper & Scinto

20070272943 - Structure and manufacturing method for epitaxial layers of gallium nitride-based compound semiconductors: The present invention relates to a structure and a manufacturing method of epitaxial layers of gallium nitride-based compound semiconductors with less dislocation densities. Surface treatment is carried out first on the surface of a substrate using reaction precursors Cp2Mg and NH3. Then a gallium nitride-based buffer layer is formed on... Agent: Rosenberg, Klein & Lee

20070272945 - Field-effect transistor: A field-effect transistor has a so-called double heterostructure which is formed such that a channel layer through which electrons travel is provided between an electron supply layer and a liner layer, wherein a forbidden band width of the liner layer and a forbidden band width of the electron supply layer... Agent: Mcdermott Will & Emery LLP

20070272946 - Silicon germanium emitter: Disclosed are an improved hetero-junction bipolar transistor (HBT) structure and a method of forming the structure that incorporates a silicon-germanium emitter layer with a graded germanium profile. The graded germanium concentration creates a quasi-drift field in the neutral region of the emitter layer. This quasi-drift field induces valence bandgap grading... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070272947 - Low power consuming semiconductor device: A low power consuming semiconductor device comprises a p substrate, a first semiconductor cell formed over the p substrate, a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell, and a tap cell for coupling a power pin to n-well structures of the first semiconductor... Agent: North America Intellectual Property Corporation

20070272948 - Inverter with dual-gate organic thin-film transistor: Provided is an inverter having a new structure capable of easily controlling a threshold voltage according to position in fabricating an inverter circuit on a plastic substrate using an organic semiconductor. A driver transistor is formed with a dual-gate structure and a positive bias voltage is applied to the top... Agent: Ladas & Parry LLP

20070272949 - Semiconductor integrated circuit, and method and apparatus for designing wiring pattern of semiconductor integrated circuit: It is an object to provide a semiconductor integrated circuit which can easily be designed and has a low wiring resistance, and a method and apparatus for designing the semiconductor integrated circuit. In a semiconductor integrated circuit apparatus according to the invention, a first wiring layer is provided with a... Agent: Mcdermott Will & Emery LLP

20070272951 - Nanoscopic wire-based devices and arrays: Electrical devices comprised of nanoscopic wires are described, along with methods of their manufacture and use. The nanoscopic wires can be nanotubes, preferably single-walled carbon nanotubes. They can be arranged in crossbar arrays using chemically patterned surfaces for direction, via chemical vapor deposition. Chemical vapor deposition also can be used... Agent: Wolf Greenfield & Sacks, P.C.

20070272950 - Semiconductor memory devices and methods of fabricating the same: A method of fabricating a semiconductor memory device includes forming a first insulating layer and a sacrificial layer on a substrate. The first insulating layer and the sacrificial layer have an opening therein. A first conductive layer is formed in the opening and on the sacrificial layer. A second insulating... Agent: Marger Johnson & Mccollom, P.C.

20070272952 - Electronic devices including a semiconductor layer: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the... Agent: Larson Newman Abel Polansky & White, LLP

20070272953 - Power semiconductor component with charge compensation structure and method for producing the same: A power semiconductor device with charge compensation structure and a method for producing the same is disclosed. In one embodiment, the power semiconductor device has in a semiconductor body a drift path between a body zone and a substrate region. The drift path is divided into drift zones of a... Agent: Dicke, Billig & Czaja

20070272954 - Fin-fet device structure formed employing bulk semiconductor substrate: A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A... Agent: Tung & Associates

20070272956 - Nonvolatile semiconductor memory: A control electrode is provided via an insulating film on one main surface of a semiconductor substrate having a first conductivity type. A pair of dopant diffusion regions are formed, with the control electrode therebetween, in a surface layer region of the semiconductor substrate. Resistance variation sections are formed in... Agent: Rabin & Berdo, PC

20070272955 - Reliable contacts: A nickel-based germanide contact includes a processing material that inhibits agglomeration of nickel-based germanide during processing to form the contact as well as during post-germanidation processes. The processing material is either in the form of a capping layer over the nickel layer or integrated into the nickel layer used to... Agent: HorizonIPPte Ltd

20070272957 - Gallium nitride material devices and associated methods: Gallium nitride material devices and methods associated with the same. In some embodiments, the devices may be transistors which include a conductive structure connected to a source electrode. The conductive structure may form a source field plate which can be formed over a dielectric material and can extend in the... Agent: Wolf Greenfield & Sacks, P.C.

20070272958 - Solid-state image sensing device and manufacturing method thereof: Pixel portions each of which has a charge storage portion formed in a semiconductor substrate 11 and a transfer gate for transferring charges stored in the charge storage portion are isolated from each other by a device isolation region in the semiconductor substrate. A buried gate electrically connected to the... Agent: Mcdermott Will & Emery LLP

20070272959 - Ferroelectric memory cell and manufacturing method thereof: A method of manufacturing a ferroelectric memory cell includes: forming device isolation regions; and source/drain regions; forming a gate insulating film on the semiconductor substrate; forming a gate electrode on the gate insulating film; forming; forming a contact plug to be connected to one of the source/drain regions. The method... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070272960 - Ferroelectric memory transistor with conductive oxide gate structure: The present invention discloses a ferroelectric transistor having a conductive oxide in the place of the gate dielectric. The conductive oxide gate ferroelectric transistor can have a three-layer metal/ferroelectric/metal or a two-layer metal/ferroelectric on top of the conductive oxide gate. By replacing the gate dielectric with a conductive oxide, the... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070272961 - Capacitor below the buried oxide of soi cmos technologies for protection against soft errors: Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070272962 - Semiconductor device with l-shaped spacer and method of manufacturing the same: A semiconductor device with an L-shape spacer and the method for manufacturing the same are provided. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer. The substrate comprises a shallow trench isolation structure and a neighboring active area. The composite spacer is formed on the... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC

20070272963 - Semiconductor device and method for fabricating the same: A semiconductor device having in a deep hole formed in a first interlayer insulating film a memory cell region that comprises a plurality of capacitors having a lower electrode 229 composed of a crown structure having an outside face and inner face, a first upper electrode 231 facing the outside... Agent: Paul J. Esatto, Jr. Scully, Scott, Murphy & Presser, P.C.

20070272964 - Semiconductor device and method of manufacturing the same: Provided is a semiconductor device including: a silicon substrate; at least two trenches spaced apart from each other, being in parallel with each other, and being formed by vertically etching the silicon substrate from a surface thereof; an electrically insulating film for burying therein at least bottom surfaces of the... Agent: Bruce L. Adams, Esq.

20070272965 - Method for producing a dielectric interlayer and storage capacitor with such a dielectric interlayer: A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.... Agent: Morrison & Foerster LLP

20070272966 - Nonvolatile semiconductor memory device and method of fabricating the same: A method of fabricating a nonvolatile semiconductor memory device includes forming a first dielectric layer on a major surface of a semiconductor substrate, forming a floating gate electrode layer on the first dielectric layer, and forming a second dielectric layer, which includes a metal oxide film or a stacked film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070272969 - Field-effect transistor: A field-effect transistor is provided which includes: a first nitride semiconductor layer having a lattice constant a1 and a bandgap Eg1; a second nitride semiconductor layer stacked on the first nitride semiconductor layer and having a lattice constant a2 and a bandgap Eg2; a source electrode and a drain electrode... Agent: Birch Stewart Kolasch & Birch

20070272968 - Semiconductor device and a method of manufacturing the same: Separate first and second floating gates for attracting carriers transferring in a transistor structure having a channel region and first and second main electrode regions into charge storage films therebelow are formed so as to largely face a control gate. The control gate between the separate first and second floating... Agent: Rabin & Berdo, PC

20070272967 - Method for modulating the effective work function: A new MOSFET device is described comprising a metal gate electrode, a gate dielectric and an interfacial layer. The electrostatic potential at an interface between the gate electrode and the gate dielectric of a MOSFET device can be controlled by introducing one or more interfacial layer(s) of a dielectric material,... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20070272970 - Non-volatile memory: A non-volatile memory and a method of fabricating the same are described. First, a substrate is provided. Then, a plurality of stack structures is formed on the substrate. Each stack structure comprises, from bottom to top, a bottom dielectric layer, a charge trapping layer, a top dielectric layer, a control... Agent: Jianq Chyun Intellectual Property Office

20070272971 - Non-volatile memory device and method of fabricating the same: In the non-volatile memory device, a first isolation layer is formed to have a plurality of depressions each having a predetermined depth from an upper surface of the semiconductor substrate. A fin type first active region is defined by the first isolation layer and has one or more inflected portions... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070272972 - Semiconductor memory device and manufacturing method thereof: A semiconductor device, in which both a reduction in a resistivity of a gate electrode and stabilization of transistor characteristics is achieved, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a semiconductor substrate, a plurality of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070272973 - Semiconductor memory devices including recess-type control gate electrodes and methods of fabricating the semiconductor memory devices: A semiconductor memory device includes a semiconductor substrate, a control gate electrode recessed in the semiconductor substrate, a storage node layer interposed between a sidewall of the control gate electrode and the semiconductor substrate, a tunneling insulation layer interposed between the storage node layer and the semiconductor substrate, a blocking... Agent: Harness, Dickey & Pierce, P.L.C

20070272974 - Twin-gate non-volatile memory cell and method of operating the same: A non-volatile memory cell with twin gates formed on an N-well is provided. The non-volatile memory cell includes at least a first gate, a second gate, a pair of NO (Nitride/Oxide) spacer layers, a pair of ONO (Oxide/Nitride/Oxide) spacers, a source, a drain, an extension source and an extension drain.... Agent: Jianq Chyun Intellectual Property Office

20070272975 - Method of forming a semiconductor device having an interlayer and structure therefor: A stack located over a substrate. The stack includes a layer between a dielectric layer and a metal layer. The layer includes a halogen and a metal. In one embodiment, the halogen is fluorine. In one embodiment, the stack is a control electrode stack for a transistor. In one example... Agent: Freescale Semiconductor, Inc. Law Department

20070272976 - Power semiconductor module: A power semiconductor module having an electrically insulating substrate, to be arranged with a circuit board. The circuit board is spaced apart from the substrate by a housing. First conductor tracks are disposed inside the substrate, facing the circuit board, for receiving power semiconductor devices which can be driven by... Agent: Cohen, Pontani, Lieberman & Pavane

20070272977 - Power semiconductor device: A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070272978 - Semiconductor device including a vertical gate zone, and method for producing the same: A semiconductor device includes a semiconductor body defining a trench structure having walls. A plurality of vertical gate zones each have a gate electrode and a gate oxide that covers the walls of the trench structure. A body zone of a first conduction type is arranged between two of the... Agent: Dicke, Billig & Czaja

20070272979 - Semiconductor device: A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070272980 - Semiconductor device with vertical current flow and low substrate resistance and manufacturing process thereof: A semiconductor device with vertical current flow includes a body having a substrate made of semiconductor material. At least one electrical contact on a first face of the body. A metallization structure is formed on a second face of the body, opposite to the first face. The metallization structure is... Agent: Graybeal, Jackson, Haley LLP

20070272981 - Cmos image sensor and method for fabricating the same: A complementary metal-oxide semiconductor (CMOS) image sensor includes a photodiode formed in a substrate structure, first to fourth gate electrodes formed over the substrate structure, spacers formed on both sidewalls of the first to fourth gate electrodes and filled between the third and fourth gate electrodes, a first ion implantation... Agent: Morgan Lewis & Bockius LLP

20070272982 - Electro-optical apparatus, electronic apparatus, and method of manufacturing electro-optical apparatus: Provided is an electro-optical apparatus including a first thin-film transistor having a first gate electrode, a first gate insulating layer and a first active layer, which are respectively formed of a conductive film, an insulating film and a semiconductor film, in a pixel region of a device substrate, the apparatus... Agent: Oliff & Berridge, PLC

20070272983 - Active device array substrate: An active device array substrate, including a substrate, a plurality of pixel units, a plurality of first lead wires, an insulating layer, a plurality of second lead wires and a passivation layer, is provided. The active device array substrate has a display area and a peripheral area. The pixel units... Agent: Jianq Chyun Intellectual Property Office

20070272984 - Semiconductor device manufacturing method and semiconductor device: Provided is a semiconductor device manufacturing method including a field oxide insulation film forming step including forming a field oxide insulation film (12) so that, in an active region (13), a portion (13a), which corresponds to a side surface portion of the active region (13) opposing a rotation center (O)... Agent: Bruce L. Adams, Esq.

20070272985 - Stagger memory cell array: A memory device includes a first memory cell area having a first latch area where one or more electronic components are constructed for storing a value, and a first peripheral area surrounding the first latch area; and a second memory cell area being disposed adjacent to a first side of... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20070272986 - Modular bipolar-cmos-dmos analog integrated circuit and power transistor technology: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of... Agent: Patentability Associates

20070272987 - Non-volatile electrical phase change memory device comprising interfacial control layer and method for the preparation thereof: wherein an interfacial control layer is formed at the interface of the contact hole between the phase change layer and the bottom electrode layer, said interfacial control layer having strong chemical bonds with the phase change material as well as electrical resistivity and thermal conductivity values lower than those of... Agent: Anderson, Kill & Olick, P.C.

20070272988 - Voltage regulating apparatus: There is disclosed a voltage regulating apparatus with a short settling time and a small current consumption. The voltage regulating apparatus comprises a reference voltage generator including an MOSFET array comprising a plurality of MOSFETs with a structure in which a drain and a source are connected in series with... Agent: Lowe Hauptman Ham & Berner, LLP

20070272989 - Semiconductor device and method for manufacturing the same: In the fabrication of semiconductor devices such as active matrix displays, the need to pattern resist masks in photolithography increases the number of steps in the fabrication process and the time required to complete them and consequently represents a substantial cost. This invention provides a method for forming an impurity... Agent: Fish & Richardson P.C.

20070272990 - Diffusion tube, dopant source for a diffusion process and diffusion method using the diffusion tube and the dopant source: According to an exemplary embodiment of the present invention, a diffusion tube includes a diffusion housing which includes a first cavity within a first end which receives a diffusion target, a second cavity within a second end which receives a dopant source for diffusion, and a diffusion port disposed between... Agent: Cantor Colburn, LLP

20070272991 - Method and device for alternately contacting two wafers: A method and device for alternately contacting two wafer-like component composite arrangements (12, 14) consisting of a plurality of cohesively designed similar components, in particular of a semiconductor wafer with a function component wafer for manufacturing electronic modules on a wafer level, in which the two component composite arrangements, each... Agent: Blakely Sokoloff Taylor & Zafman

20070272992 - Method for fabricating condenser microphone and condenser microphone: A first semiconductor chip includes a fixed electrode formed on a first semiconductor substrate and a plurality of first metal spacers formed on a first interlayer dielectric. A second semiconductor chip includes a vibrating electrode formed on a second semiconductor substrate and a plurality of second metal spacers formed on... Agent: Mcdermott Will & Emery LLP

20070272993 - Optical sensor assemblage and corresponding manufacturing method: The present invention creates an optical sensor assemblage, in particular a thermopile sensor assemblage, comprising a sensor chip assemblage (10; 10′) having an optically transparent irradiation region (OB; OB′), a mounting region (RB; RB′) surrounding the latter, and a wire-bond region (BB); an optically isolating mounting frame (MLF; MLF′) having... Agent: Kenyon & Kenyon LLP

20070272994 - Sensor semiconductor device: A sensor semiconductor device is proposed. A plurality of metal bumps and a sensor chip are mounted on a substrate. A dielectric layer and a circuit layer are formed on the substrate, wherein the circuit layer is electrically connected to the metal bumps and the sensor chip. Thus, the sensor... Agent: Ishimaru & Zahrt LLP

20070272995 - Photosensitive device: A photosensitive device is provided. The photosensitive device can be an image sensor or a solar cell. The photosensitive device includes a driving circuit such as photo sensor circuit or solar cell circuit, and a nano-crystal layer. The nano-crystal layer is located above the driving circuit and includes a silicon... Agent: Birch Stewart Kolasch & Birch

20070272996 - Self-aligned implanted waveguide detector: A method of fabricating a detector, the method including forming an island of detector core material on a substrate, the island having a horizontally oriented top end, a vertically oriented first sidewall, and a vertically oriented second sidewall that is opposite said first sidewall; implanting a first dopant into the... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070272998 - Semiconductor device: With this semiconductor device, the distortion and cracking of a thinned portion of a semiconductor substrate are prevented to enable high precision focusing with respect to a photodetecting unit and uniformity and stability of high sensitivity of the photodetecting unit to be maintained. A semiconductor device 1 has a semiconductor... Agent: Drinker Biddle & Reath (dc)

20070272997 - Semiconductor device and method for manufacturing the same: With this semiconductor device, the distortion and cracking of a thinned portion of a semiconductor substrate are prevented to enable high precision focusing with respect to a photodetecting unit and uniformity and stability of high sensitivity of the photodetecting unit to be maintained. A semiconductor device 1 has a semiconductor... Agent: Drinker Biddle & Reath (dc)

20070272999 - Voltage sustaining layer with opposite-doped islands for semiconductor power devices: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070273000 - Trench widening without merging: A semiconductor fabrication method comprises steps of providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench comprises a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on... Agent: Schmeiser, Olsen & Watts

20070273001 - System on chip and method for manufacturing the same: A system-on-chip semiconductor structure. The system-on-chip semiconductor structure comprises a substrate, a low voltage device, a middle voltage device, at least one high voltage device and a plurality of isolation structures. The substrate has a low voltage circuit region and a high voltage circuit region. The low voltage device is... Agent: Jianq Chyun Intellectual Property Office

20070273002 - Semiconductor memory devices having fuses and methods of fabricating the same: An integrated circuit device is provided with a plurality of normally open fuse elements. A fuse element includes a fuse insulation film lining a sidewall and a bottom of a recess in a semiconductor substrate. A semiconductor fuse region of first conductivity type (e.g., N-type) is provided in the semiconductor... Agent: Myers Bigel Sibley & Sajovec

20070273003 - Semiconductor device and manufacturing method thereof: A semiconductor device and a method of manufacturing the semiconductor device is provided. The method includes the steps of forming a first insulating layer on a top surface of a semiconductor substrate having a plurality of patterns, immediately before gaps between the patterns are completely closed; forming a lower insulating... Agent: Lowe Hauptman Ham & Berner, LLP

20070273004 - Like integrated circuit devices with different depth: The invention forms integrated circuit devices of similar structure and dissimilar depth, such as interconnects and inductors, simultaneously. The invention deposits a conformal polymer over an area on a substrate with vias and an area without vias. Simultaneously, cavities are formed in the areas with and without vias. The depth... Agent: International Business Machines Corporation Dept. 18g

20070273005 - Mim type capacitor: A method of fabricating an MIM type capacitor includes at least one of: Forming a first trench within an insulating interlayer formed on a semiconductor substrate. Forming a lower electrode layer of a metal nitride layer substance to fill an inside of the first trench. Forming a second trench on... Agent: Sherr & Nourse, PLLC

20070273006 - Bipolar method and structure having improved bvceo/rcs trade-off made with depletable collector columns: In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in... Agent: Mh2 Technology Law Group

20070273007 - Bipolar-transistor and method for the production of a bipolar-transistor: The invention relates to NPN and PNP bipolar transistors and to a method for the production thereof, said transistors being characterised by a particularly high collector-emitter and collector-base blocking voltage. The blocking voltage is increased by a particular doping profile. An NPN bipolar transistor comprises a p-doped substrate (1), a... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20070273008 - Multilayer dielectric substrate and semiconductor package: A multilayer dielectric substrate that mounts a semiconductor device in a cavity formed on a substrate. The multilayer dielectric substrate includes an opening formed in a surface-layer grounding conductor on the substrate in the cavity, and an impedance transformer, with a length of about ¼ of an in-substrate effective wavelength... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070273010 - Design and method for attaching a die to a leadframe in a semiconductor device: The semiconductor device whose structure is formed from a die attached to a leadframe comprises a die having an attachment member, and a leadframe having a recess configured to receive a corresponding attachment member so as to establish a connection between the die and the leadframe.... Agent: Texas Instruments Incorporated

20070273009 - Highly efficient both-side-cooled discrete power package, especially basic element for innovative power modules: Two DBC wafers have patterned first conductive surfaces which receive a semiconductor die in sandwich fashion. Lead frame terminally extending into the package interior and are connected to the die terminals. The outer conductive surfaces of each of the wafers are available for two-sided cooling of the semiconductor.... Agent: Ostrolenk Faber Gerb & Soffen

20070273011 - Method for fabricating a module having an electrical contact-connection: A method for fabricating a module having an electrical contact-connection is disclosed. One embodiment provides a chip having a contact area, applying a contact elevation to the contact area and applying a solder material to the contact elevation. The contact elevation may be applied to the contact area by using... Agent: Dicke, Billig & Czaja

20070273012 - Semiconductor device: A semiconductor device comprising, a layer on which a semiconductor element is arranged, an insulation layer on which a wiring connected to the semiconductor element is arranged, dummy metal plates arranged in the insulation layer, wherein the dummy metal plates have an aspect ratio larger than 1, and are arranged... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070273013 - Packaging for micro electro-mechanical systems and methods of fabricating thereof: Embodiments of the present disclosure provide systems and methods for producing micro electro-mechanical device packages. Briefly described, in architecture, one embodiment of the system, among others, includes a micro electro-mechanical device formed on a substrate layer; and a thermally decomposable sacrificial structure protecting at least a portion of the micro... Agent: Christopher B Linder Thomas Kayden Horstemeyer & Risley

20070273015 - Semiconductor device: A semiconductor device 1 includes a semiconductor chip 10. Each of the semiconductor chips 10 includes a semiconductor substrate 12, a semiconductor layer 14 and an interconnect layer 16. The semiconductor substrate 12 has a specific resistance ρ1 (first specific resistance). A semiconductor layer 14 is provided on the semiconductor... Agent: Young & Thompson

20070273014 - System in package module: A System in Package (SIP) module. The module includes a printed circuit board with at least one cavity formed therein. The module also includes at least one first device mounted in the cavity and a circuit pattern formed on an undersurface of the cavity and electrically connected to the first... Agent: Lowe Hauptman Ham & Berner, LLP

20070273016 - Double sided semiconduction device with edge contact and package therefor: A semiconductor die has devices such as MOSgated devices, diodes and the like formed into the top and bottom surfaces of the die. One terminal of each of the devices terminal in the interior center of the die and a common contact is made to the interior center of the... Agent: Ostrolenk Faber Gerb & Soffen

20070273017 - Quad flat no-lead chip carrier with stand-off: A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed... Agent: John A. Jordan, Esq.

20070273018 - Semiconductor apparatus and method for manufacturing the same: It is made possible to provide a highly integrated, thin apparatus can be obtained, even if the apparatus contains MEMS devices and semiconductor devices. A semiconductor apparatus includes: a first chip comprising a MEMS device formed therein; a second chip comprising a semiconductor device formed therein; and an adhesive layer... Agent: Amin, Turocy & Calvin, LLP

20070273019 - Semiconductor package, chip carrier structure thereof, and method for fabricating the chip carrier: A semiconductor package, a chip carrier structure thereof, and a method for fabricating the chip carrier structure are provided. A substrate having a mounting region and a covering region is disposed in an opening of a carrier. A molding process is performed to form an encapsulant on the covering region... Agent: Edwards Angell Palmer & Dodge LLP

20070273020 - Semiconductor device: The present invention provides a method of manufacturing semiconductor device. The method includes providing a semiconductor wafer having a main surface; defining a chip forming region which includes chip regions defined by scribe lines, and a peripheral region which surrounds the chip forming region, on the main surface; forming circuit... Agent: Rabin & Berdo, PC

20070273021 - Semiconductor package: A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second... Agent: Foley And Lardner LLP Suite 500

20070273022 - Semiconductor device: In a semiconductor device comprising a ceramic substrate, a surface mount component, and sealing resin and obtained by division into pieces, the ceramic substrate is composed of a multiple piece substrate provided with dividing grooves for the division into pieces on both front and rear surfaces in advance, a plurality... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070273023 - Integrated circuit package having exposed thermally conducting body: An apparatus and method for a wire-bond die-up area array package is described. The package includes an integrated circuit (IC) die, a substrate, and a thermally conducting body. A bottom surface of the IC die is exposed through an opening in a central region of the substrate. The die is... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070273024 - Cooling system with a bubble pump: The present invention relates to a closed system for cooling without moving mechanical parts and at a low noise level, one or more heat-emitting elements. The system comprises a first heat-receiving part that is adapted to receive heat from the at least one heat-emitting element, a cooling fluid for absorption... Agent: Volentine & Whitt PLLC

20070273025 - Device comprising circuit elements connected by bonding bump structure: A bonding-bump (1) of small dimensions comprises a gold pedestal portion (2) formed on a circuit element (10), a nickel barrier layer (3) formed on the pedestal portion (2), and a soldering portion (5) formed on the barrier layer (3). The soldering portion (5) comprises first (6) and second (8)... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070273026 - Semiconductor package substrate: A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one... Agent: Edwards Angell Palmer & Dodge LLP

20070273027 - Method of forming dual damascene pattern: A method of forming a dual damascene pattern for a metal interconnection by a relatively simple process. Only a portion of an interlayer insulating film is initially etched when forming a via hole. When the interlayer insulating is etched to form a trench, the remaining portion of the via hole... Agent: Sherr & Nourse, PLLC

20070273028 - Semiconductor integrated circuit device comprising different level interconnection layers connected by conductor layers including conductor layer for redundancy: A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for... Agent: Amin, Turocy & Calvin, LLP

20070273029 - Photo mask set for forming multi-layered interconnection lines and semiconductor device fabricated using the same: A photo mask set for forming multi-layered interconnection lines and a semiconductor device fabricated using the same includes a first photo mask for forming lower interconnection lines and a second photo mask for forming upper interconnection lines. The first and second photo masks have lower opaque patterns parallel with each... Agent: Marger Johnson & Mccollom, P.C.

20070273030 - Semiconductor device having metal lines with slits: A semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, and a plurality of metal line patterns on the insulation layer. First and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from... Agent: Lee & Morse, P.C.

20070273031 - Method of wire bonding over active area of a semiconductor circuit: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over... Agent: Saile Ackerman LLC

20070273032 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273033 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273034 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273035 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273036 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273037 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273038 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273039 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273040 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273041 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070273042 - Copper-filled trench contact for transistor performance improvement: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length... Agent: Blakely Sokoloff Taylor & Zafman

20070273043 - Wire bonding structure and method that eliminates special wire bondable finish and reduces bonding pitch on substrates: A semiconductor package has a semiconductor die disposed on a substrate. A bond wire is connected between a first bonding site on the semiconductor die and a second bonding site on the substrate. The first bonding site is a die bond pad; the second bonding site is a stitch bond.... Agent: Quarles & Brady LLP

20070273044 - Adhesion enhancement for metal/dielectric interface: An interconnect structure and method of fabricating the same in which the adhesion between a chemically etched dielectric material and a noble metal liner is improved are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modified the chemical nature... Agent: Scully Scott Murphy & Presser, PC

20070273045 - Printed wiring board, method for forming the printed wiring board, and board interconnection structure: A board interconnection structure having a first printed wiring board in which a first conductive circuit is arranged on a first insulating layer, the first conductive circuit having, on an end portion thereof, a first connection terminal in which an upper surface width is narrower than a bottom surface width;... Agent: Sughrue Mion, PLLC

20070273046 - Semiconductor component with connecting elements and method for producing the same: A semiconductor component with connecting elements between a semiconductor chip made from a semiconductor wafer with discrete semiconductor components and a superordinate circuit carrier is disclosed. The semiconductor component has a coplanar area having top sides of the connecting elements and a plastic housing composition. The connecting element has a... Agent: Dicke, Billig & Czaja

20070273047 - Printed wiring board and manufacturing method thereof: A printed wiring board having an interlayer insulation layer and conductive circuits formed on the interlayer insulation layer. The conductive circuits include a first conductive circuit and a second conductive circuit positioned adjacent to each other, and the first and second conductive circuits satisfy a formula, 0.10 T≦|W1−W2|≦0.73 T, where... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070273048 - Shapes-based migration of aluminum designs to copper damascene: An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.... Agent: Schmeiser, Olsen & Watts

20070273049 - Interconnect structure and formation for package stacking of molded plastic area array package: Apparatuses, methods, and systems for improved integrated circuit packages are described. An integrated circuit (IC) package includes a substrate having opposing first and second surfaces, an IC die, a plurality of conductive elements, and an encapsulating material. The substrate has a plurality of contact pads on the first surface that... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070273050 - Semiconductor device and method of manufacturing thereof: A method of manufacturing a semiconductor device sealed in a cured silicone body by placing an unsealed semiconductor device into a mold and subjecting a curable liquid silicone composition that fills the spaces between the mold and the unsealed semiconductor device to compression molding under a predetermined molding temperature, wherein... Agent: Howard & Howard Attorneys, P.C.

20070273051 - Curable organopolysiloxane composition, use of the cured product of the composition, and semiconductor device: A curable organopolysiloxane composition capable of forming cured products of superior optical transmittance exhibiting little heat-induced yellowing over time. A semiconductor device having semiconductor elements encapsulated in a cured product of the composition. The composition includes (A) an organopolysiloxane having at least two silicon-bonded alkenyl groups per molecule and bearing... Agent: Howard & Howard Attorneys, P.C.

20070267618 - Memory device: A phase change memory cell includes a first spacer electrically coupled to a first electrode and to a second spacer. The first spacer includes a planar base contacting the first electrode and a wall extending from the planar base. The second spacer is electrically coupled between a second electrode and... Agent: Dicke, Billig & Czaja

20070267619 - Memory using tunneling field effect transistors: A memory includes a first tunneling field effect transistor including a first drain and a first source, the first drain coupled to a first resistive memory element. The memory includes a second tunneling field effect transistor including a second drain and sharing the first source, the second drain coupled to... Agent: Dicke, Billig & Czaja

20070267620 - Memory cell including doped phase change material: A phase change memory cell includes a phase change material doped with a first material having a resistivity that decreases less than one decade per 20 degrees Celsius when transitioning from an amorphous state to a crystalline state.... Agent: Dicke, Billig & Czaja

20070267622 - Multi-functional chalcogenide electronic devices having gain: Multi-functional electronic switching and current control device comprising a chalcogenide material. The devices include a load terminal, a reference terminal and a control terminal. Application of a control signal to the control terminal permits the device to function in one or more of the following modes reversibly: (1) a gain... Agent: Energy Conversion Devices, Inc.

20070267621 - Resistive memory device: A programmable resistive memory cell comprising a lower electrode, a programmable resistance layer, and an upper electrode, wherein the programmable resistance layer comprises a first transition metal oxide and a second transition metal oxide.... Agent: Dicke, Billig & Czaja

20070267623 - Multi-functional electronic devices: Multi-functional electronic switching and current control devices comprising a material capable of supporting a space-charge. The devices include a load terminal, a reference terminal and a control terminal in contact with the space-charge material and a space-charge region is present at each of the multiple terminals, where each space-charge region... Agent: Energy Conversion Devices, Inc.

20070267624 - Multi-functional chalcogenide electronic devices having gain: Multi-functional electronic switching and current control device comprising a chalcogenide material. The devices include a load terminal, a reference terminal and a control terminal. Application of a control signal to the control terminal permits the device to function in one or more of the following modes reversibly: (1) a gain... Agent: Energy Conversion Devices, Inc.

20070267629 - Laser irradiation device and method of fabricating oled using the same: A laser irradiation device and a method of fabricating an OLED having an increased laser efficiency. The laser irradiation device includes: a light source to produce a laser beam; a collimation lens disposed adjacent to the light source; and an asymmetrical micro lens array disposed adjacent to the collimation lens.... Agent: Stein, Mcewen & Bui, LLP

20070267628 - Method for forming electrodes of organic electronic devices, organic thin film transistors comprising such electrodes, and display devices comprising such transistors: Disclosed are methods for forming electrodes for organic electronic devices which allow for the use of an improved range of conductive materials for forming source/drain electrodes. The disclosed methods also allow for the use of different conductive materials for forming data lines and source/drain electrodes during the fabrication of organic... Agent: Harness, Dickey & Pierce, P.L.C

20070267630 - Method of manufacturing organic thin film transistor and organic thin film transistor: A method of manufacturing an organic thin film transistor characterized by low costs and high performances, the method in which the self-assemble monolayer is formed in a short period of time, and the organic thin film transistor are provided. A method of manufacturing an organic thin film a transistor having... Agent: Brinks Hofer Gilson & Lione

20070267627 - Organic memory device and fabrication method thereof: An organic memory device and a method for fabricating the memory device are provided. The organic memory device may include a first electrode, a second electrode, and an ion transfer layer between the first electrode and the second electrode. The organic memory device may have lower operating voltage and current,... Agent: Harness, Dickey & Pierce, P.L.C

20070267631 - System and method for increasing productivity of combinatorial screening: The present invention provides systems and methods for simultaneous, parallel and/or rapid serial testing of material parameters or other parameters of the result of a process. The testing is typically used for screening different methods or materials to select those methods or materials with desired properties. A reactor structure used... Agent: Patent Law Group LLP

20070267633 - Flat panel display device and method for fabricating same: Provided is a flat panel display device and a method for fabricating the same. The flat panel display device comprises a first substrate, a light emitting unit, a second substrate, and insulating films. The light emitting unit comprises thin film transistors positioned on the first substrate, a first electrode electrically... Agent: Brinks Hofer Gilson & Lione

20070267634 - Hybrid strained orientated substrates and devices: A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor material and a second semiconductor material, which is different from... Agent: Schmeiser, Olsen & Watts

20070267635 - Thin film transistor: A thin film transistor is disclosed, comprising a substrate, a polysilicon layer overlying the substrate, a gate insulating layer overlying the polysilicon layer, a gate electrode, a dielectric interlayer overlying the gate electrode and gate insulating layer, and a source/drain electrode overlying the dielectric interlayer. Specifically, the gate electrode comprises... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070267637 - Light emitting package and light emitting package array: Example embodiments may include a light emitting device package. The light emitting device package may include a light emitting device, a package body including a cavity having a bottom surface on which the light emitting device is mounted and a side surface for reflecting light emitted from the light emitting... Agent: Harness, Dickey & Pierce, P.L.C

20070267638 - Light emission device and electron emission display: A light emission device includes: first and second substrates facing each other and spaced apart from each other; an electron emission region on an inner surface of the first substrate; a driving electrode on the inner surface of the first substrate to control an electron emission of the electron emission... Agent: Christie, Parker & Hale, LLP

20070267639 - Light emission device, method of manufacturing electron emission unit for the light emission device, and display device having the light emission device: l

20070267641 - Light emitting device and method of manufacturing the same: A light emitting device and a method of manufacturing the same are provided. The light emitting device comprises a substrate, a gate electrode positioned on the substrate, a first insulating layer positioned on the substrate comprising the gate electrode, an amorphous silicon layer positioned on the first insulating layer so... Agent: Brinks Hofer Gilson & Lione

20070267640 - Semiconductor light emitting diode and method of manufacturing the same: The present invention relates to a semiconductor light emitting diode. The semiconductor light emitting diode includes a substrate; an n-type nitride semiconductor layer that is formed on the substrate; an active layer that is formed on the n-type nitride semiconductor layer; a p-type nitride semiconductor layer that is formed on... Agent: Mcdermott Will & Emery LLP

20070267642 - Light-emitting devices and methods for manufacturing the same: Light-emitting device assemblies are described. The assemblies can include a light-emitting device, an optional package supporting the light-emitting device, and a base supporting the light-emitting device or the optional package. The base may include a protrusion extending in the direction of the light-emitting device. The thermally conductive pathway can extend... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.C.

20070267643 - Semiconductor light emitting device and method for manufacturing the same: A reliable semiconductor light-emitting device and a method for manufacturing the same can be provided in which peeling can be prevented in a phase boundary, and optical axis positional errors between the optical lens and a semiconductor light-emitting chip can be reduced or prevented. The semiconductor light-emitting device can include... Agent: Cermak Kenealy & Vaidya, LLP

20070267645 - Ultraviolet ray emitting element package: An ultraviolet ray emitting element package comprises a condenser lens, and an ultraviolet ray emitting element which is arranged approximately at a center and in a bottom side of the condenser lens and which is apart from a bottom of the condenser lens, wherein a refractive index difference reduction substance... Agent: Rader Fishman & Grauer PLLC

20070267648 - Light emitting device and method for fabricating the same: A light emitting device includes a first substrate and a second substrate. Each substrate may be subdivided into a contact region and a pixel region. Conductive elements positioned in each of the contact region and pixel region of the first substrate may be of substantially the same height.... Agent: Brinks Hofer Gilson & Lione

20070267650 - Light-emitting device: A light-emitting device comprises a carrier, an insulated transparent adhesive layer, and a multi-layer epitaxial light-emitting structure located on the upper side of the insulated transparent adhesive layer. The top surface of the carrier comprises a first contact pad and a second contact pad. The insulated transparent adhesive layer is... Agent: Bacon & Thomas, PLLC

20070267649 - Semiconductor laser device: In one aspect, a semiconductor laser device may include a supporting member, a semiconductor laser element provided over the supporting member, and configured to emit a laser from a front surface and monitoring laser from a rear surface, and a photo receiving element provided over the supporting member, and configured... Agent: Amin, Turocy & Calvin, LLP

20070267625 - Utilizing nanowire for different applications: One embodiment in accordance with the invention is an apparatus that can include a non-single crystal substrate and a nanowire grown from a surface of the non-single crystal substrate. Furthermore, the apparatus can also include an electrode coupled to the nanowire. It is noted that the nanowire can be electrically... Agent: Hewlett Packard Company

20070267626 - Semiconductor structure: The invention concerns a semiconductor structure comprising at least one first material region and a second material region, whereby the second material region epitaxially surrounds the first material region and forms a boundary surface. The structure is characterized in that Fermi level pinning is present on the non-epitaxial boundary surface... Agent: K.f. Ross P.C.

20070267632 - Apparatus and method for test structure inspection: Herein are described layouts of test structures and scanning methodologies that allow large probe currents to be used so as to allow the detection of resistive defects with a resistance lower than 1 MΩ while at the same time allowing a sufficient degree of localization to be obtained for root... Agent: Applied Materials, Inc. C/o Sonnenschein Nath & Rosenthal LLP

20070267636 - Gallium-nitride based light-emitting diode structure with high reverse withstanding voltage and anti-esd capability: An epitaxial structure for GaN-based LEDs to achieve better reverse withstanding voltage and anti-ESD capability is provided herein. The epitaxial structure has an additional anti-ESD thin layer as the topmost layer, which is made of undoped indium-gallium-nitrides (InGaN) or low-band-gap (Eg<3.4 eV), undoped aluminum-indium-gallium-nitrides (AlInGaN). The anti-ESD thin layer could... Agent: Lin & Associates Intellectual Property

20070267646 - Light emitting device including a photonic crystal and a luminescent ceramic: A semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region and a photonic crystal formed within or on a surface of the semiconductor structure is combined with a ceramic layer which is disposed in a path of light emitted by the light emitting... Agent: Patent Law Group LLP

20070267644 - Light emitting diode: A light emitting diode is disclosed, wherein the light extraction efficiency of a device can be enhanced by forming patterns on a substrate, a light emitting structure is formed on the substrate formed with the patterns, the substrate is removed from the light emitting structure, and patterns corresponding to those... Agent: Mckenna Long & Aldridge LLP

20070267647 - Optoelectronic device chip having a composite spacer structure and method making same: An optoelectronic device chip, and a method for making the chip, are disclosed. The chip comprises a device substrate, an optically transparent upper substrate, and a composite spacer layer which includes an adhesive material and a plurality of particles dispersed in said adhesive material. The distance between the device substrate... Agent: Tung & Associates Suite 120

20070267651 - Semiconductor device having a fuse and method of forming thereof: A fuse (43) is formed overlying a passivation layer (35) and under a packaging material (55, 70). In one embodiment, a fuse (43) is blown before the packaging material (55, 70) is formed. In some embodiments, the fuse (43) may be formed of metal (47), a metal nitride (42) or... Agent: Freescale Semiconductor, Inc. Law Department

20070267652 - Field-effect transistor: A field-effect transistor includes a channel layer formed of a III-V compound semiconductor excluding aluminum; a gate contact layer formed of a III-V compound semiconductor and provided on the channel layer, the III-V compound semiconductor having a dopant concentration equal to or less than 1×1016 cm−3, containing aluminum, and having... Agent: Leydig Voit & Mayer, Ltd

20070267653 - Semiconductor light-receiving device: f

20070267654 - In-situ defect reduction techniques for nonpolar and semipolar (al,ga, in)n: A method for growing reduced defect density planar gallium nitride (GaN) films is disclosed. The method includes the steps of (a) growing at least one silicon nitride (SiNx) nanomask layer over a GaN template, and (b) growing a thickness of a GaN film on top of the SiNx nanomask layer.... Agent: Gates & Cooper LLP Howard Hughes Center

20070267655 - Semiconductor device having mis structure and its manufacture method: A channel layer (11) made of compound semiconductor and a barrier layer (12) made of compound semiconductor having a band gap wider than the channel layer are formed over a substrate. A gate insulating film (13) made of first insulating material is formed on the barrier layer over the channel... Agent: Kratz, Quintos & Hanson, LLP

20070267656 - Bipolar transistors with depleted emitter: This invention disclosed a novel method of fully depleted emitter so that the built-in potential between emitter and the base becomes lower and the charge storage between the emitter and base becomes small. This concept also applies to the diodes or rectifiers. With depleted junction, this result in very fast... Agent: Ho-yuan Yu

20070267657 - Flat panel image display device: A flat panel image display device comprises: a rear plate including plural electron emission elements; a face plate disposed opposed to the rear plate, fluorescent members being disposed on a surface of the face plate opposed to the rear plate, and the fluorescent members being covered with a metal back... Agent: Fitzpatrick Cella Harper & Scinto

20070267659 - Chip-type electronic component including thin-film circuit elements: A chip-type electronic component includes a substrate, a common potential layer formed on an upper side of the substrate, an insulating film formed on the common potential layer, and provided to expose at least part of the common potential layer. At least one common potential electrode is provided on the... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070267658 - Image sensor and methods of fabricating the same: An image sensor and methods of fabricating the same are provided. An example method may include forming at least one gate on a substrate, forming first, second and third layers on the at least one gate, first etching the third layer with a first etching process, the second layer configured... Agent: Harness, Dickey & Pierce, P.L.C

20070267660 - Method and apparatus for forming a semiconductor substrate with a layer structure of activated dopants: Methods of forming semiconductor devices with a layered structure of thin and well defined layer of activated dopants, are disclosed. In a preferred method, a region in a semiconductor substrate is amorphized, after which the region is implanted with a first dopant at a first doping concentration. Then a solid... Agent: Knobbe Martens Olson & Bear LLP

20070267661 - Solid-state imaging apparatus: A solid-state imaging apparatus is provided. The solid-state imaging apparatus includes a solid-state imaging device, an α-ray shielding layer formed so as to cover at least an imaging area of the solid-state imaging device and a cover glass provided above the α-ray shielding layer.... Agent: Bell, Boyd & Lloyd, LLP

20070267662 - N-channel tft and oled display apparatus and electronic device using the same: An N-channel TFT and OLED display apparatus and electronic device using the same are disclosed. The N-channel TFT comprises a a substrate; an active layer on the substrate, wherein the active layer comprises an N type source region and an N type drain region; a gate dielectric layer on the... Agent: Liu & Liu

20070267664 - Semiconductor device and method of manufacturing the same: A semiconductor device according to the present invention comprises a first semiconductor layer of the first conductivity type. A pillar layer includes first semiconductor pillars of the first conductivity type and second semiconductor pillars of the second conductivity type arranged periodically and alternately on the first semiconductor layer. The first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070267663 - Semiconductor device having improved insulated gate bipolar transistor and method for manufacturing the same: An n-type first base layer is formed on a semiconductor substrate 1 having a first major surface and a second major surface, and a p-type second base layer is formed thereon. Between the first base layer and the second base layer, a carrier stored layer is formed. The carrier stored... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070267665 - Optical sensor device and electronic apparatus: In an optical sensor device employing an amorphous silicon photodiode, an external amplifier IC and the like are required due to low current capacity of the sensor element in order to improve the load driving capacity. It leads to increase in cost and mounting space of the optical sensor device.... Agent: Fish & Richardson P.C.

20070267666 - Methods of fabricating image sensors and image sensors fabricated thereby: A method of fabricating an image sensor may include providing a substrate including light-receiving and non-light-receiving regions; forming a plurality of gates on the non-light-receiving region; ion-implanting a first-conductivity-type dopant into the light-receiving region to form a first dopant region of a pinned photodiode; primarily ion-implanting a second-conductivity-type dopant, different... Agent: Harness, Dickey & Pierce, P.L.C

20070267667 - Programmable resistive memory cell with a programmable resistance layer: A programmable resistive memory cell comprising a lower electrode, a programmable resistance layer, and an upper electrode, wherein a lower mask is arranged between the lower electrode and the programmable resistance layer and an upper mask is arranged between the programmable resistance layer and the upper electrode, and wherein the... Agent: Klaus Dieter Ufert

20070267669 - Phase-changeable memory device and method of manufacturing the same: A phase-changeable memory device may include a substrate including a peripheral region and a cell region, a first pad on the peripheral region, a second pad on the cell region, a lower electrode on the second pad, an insulation layer pattern on the substrate, the insulation layer pattern including a... Agent: Lee & Morse, P.C.

20070267668 - Semiconductor constructions, dram arrays, and methods of forming semiconductor constructions: The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. The invention also includes DRAM arrays having low rates of refresh. Additionally, the invention includes semiconductor constructions... Agent: Wells St. John P.s.

20070267670 - Integrated circuit with a trench capacitor structure and method of manufacture: An integrated circuit device having a capacitor structure. In one form of the invention, an integrated circuit device includes a capacitor structure formed along a surface of a semiconductor layer. The capacitor structure includes a trench region formed in the semiconductor surface, a layer of dielectric material formed along a... Agent: Beusse Brownlee Wolter Mora & Maire, P.A.

20070267672 - Semiconductor device and method for manufacturing same: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a plurality of first trenches passing through the second semiconductor layer and reaching the first semiconductor layer; a gate insulating film provided... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070267671 - Trench capacitor having lateral extensions in only one direction and related methods: A trench capacitor and related methods are disclosed including a trench having lateral extensions extending in only one direction from the trench filled with a capacitor material. In one embodiment, the trench capacitor includes a trench within a substrate, and at least one lateral extension extending from the trench in... Agent: Hoffman, Warnick & D'alessandro LLC

20070267673 - Adjustable on-chip sub-capacitor design: One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about... Agent: Driggs, Hogg & Fry Co. L.p.a.

20070267674 - 1t mim memory for embedded ram application in soc: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer,... Agent: Birch Stewart Kolasch & Birch

20070267675 - Nonvolatile memory devices including oxygen-deficient metal oxide layers and methods of manufacturing the same: A nonvolatile memory device includes at least one switching device and at least one storage node electrically connected to the at least one switching device. The at least one storage node includes a lower electrode, one or more oxygen-deficient metal oxide layers, one or more data storage layers, and an... Agent: Harness, Dickey & Pierce, P.L.C

20070267676 - Fin field effect transistor and method for forming the same: Example embodiments are directed to a method of forming a field effect transistor (FET) and a field effect transistor (FET) including at least one buried gate structure, buried entirely below an upper surface of an active fin and an upper surface of the isolation region.... Agent: Harness, Dickey & Pierce, P.L.C

20070267678 - Mos devices with corner spacers: A MOS device having corner spacers and a method for forming the same are provided. The method includes forming a gate structure overlying a substrate, forming a first dielectric layer over the gate structure and the substrate, forming a second dielectric layer on the first dielectric layer, forming a third... Agent: Slater & Matsil, L.L.P.

20070267677 - Single poly non-volatile memory device with inversion diffusion regions and methods for operating the same: A non-volatile memory device comprises a substrate with the dielectric layer formed thereon. A control gate and a floating gate are then formed on top of the dielectric layer. Accordingly, a non-volatile memory device can be constructed using a single poly process that is compatible with conventional CMOS processes. In... Agent: Baker & Mckenzie LLP Patent Department

20070267684 - Non-volatile memory integrated circuit device and method of fabricating the same: A non-volatile memory integrated circuit device and a method fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, word and select lines, and a floating junction region, a bit line junction region and a common source region. The semiconductor substrate has a plurality of... Agent: Mills & Onello LLP

20070267679 - Nonvolatile memory devices including floating gates formed of silicon nano-crystals and methods of manufacturing the same: A memory device includes a gate stack on a substrate. The gate stack is disposed between a source and a drain. The gate stack includes a tunneling film, storage node, and control oxide film. A thickness of the control oxide film is greater than or equal to about 5 nm... Agent: Harness, Dickey & Pierce, P.L.C

20070267682 - Semiconductor device and method of manufacturing same: According to an aspect of the invention, there is provided a semiconductor device comprising a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a first conductive layer formed as a floating gate on the first insulating layer, a second insulating layer formed as an interelectrode insulating film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070267681 - Semiconductor device and method of manufacturing the same: Example embodiments are directed to a method of manufacturing a semiconductor device and a semiconductor device including a substrate including a plurality of active regions and a plurality of isolation regions between adjacent active regions, each active region including a groove, a bottom surface of the groove being below an... Agent: Harness, Dickey & Pierce, P.L.C

20070267680 - Semiconductor integrated circuit device: A semiconductor integrated circuit device contains a CMOS circuit that includes a plurality of N-channel transistors and a plurality of P-channel transistors. The plurality of N-channel transistors is provided with device isolation by one of a gate isolation structure and a shallow trench isolation structure. The plurality of P-channel transistors... Agent: Amin, Turocy & Calvin, LLP

20070267683 - Nonvolatile memory cell of a circuit integrated in a semiconductor chip, method for producing the same, and application of a nonvolatile memory cell: A method for producing a nonvolatile memory cell in a semiconductor chip is provided, wherein a gate electrode is produced, a read region is produced, which together with the gate electrode forms a transistor arrangement, a first programming region is produced, which together with the gate electrode forms a first... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20070267685 - Nonvolatile semiconductor memory and method of manufacturing the same: A nonvolatile semiconductor memory includes memory cell transistors and resistors. Each memory cell transistor has source/drain diffusion layers provided in a semiconductor substrate, a first gate insulating film located between the source/drain diffusion layers, a floating gate electrode layer located on the first gate insulating film, a first inter-gate insulating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070267687 - Bandgap engineered split gate memory: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height;... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070267688 - Sonos memory device having nano-sized trap elements: A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the... Agent: Lee & Morse, P.C.

20070267686 - System and method for reducing process-induced charging: A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.... Agent: Harrity & Snyder, L.L.P.

20070267689 - One-transistor composite-gate memory: One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20070267690 - Dmosfet with current injection: This invention disclosed a novel method for the reduction the resistance of the drift region by using the minority carrier current injector near the drift region. This current injector is a p-n junction or a p-n junction in connection with a resistor to the gate or the p-n junction in... Agent: Ho-yuan Yu

20070267691 - Metal oxide semiconductor transistor and fabrication method thereof: A manufacturing method of metal oxide semiconductor transistor is provided. A substrate is provided. A source/drain extension region is formed in the substrate. A pad material layer with low dielectric constant is formed on the substrate. A trench is formed in the substrate and the pad material layer. A gate... Agent: Jianq Chyun Intellectual Property Office

20070267692 - Semiconductor device and method of manufacturing the same: Example embodiments are directed to a method of manufacturing a semiconductor device and a semiconductor device including a substrate including a plurality of active regions and a plurality of isolation regions between adjacent active regions, each active region including a groove, a bottom surface of the groove being below an... Agent: Harness, Dickey & Pierce, P.L.C

20070267693 - Suppression of hot-carrier effects using double well for thin gate oxide ldmos embedded in hv process: A semiconductor device includes a first high-voltage well having a first dopant disposed in a semiconductor substrate; a second high-voltage well having a second dopant disposed in the semiconductor substrate, laterally adjacent to the first high-voltage well; a low-voltage well having the second dopant disposed overlying the second high-voltage well;... Agent: Haynes And Boone, LLP

20070267694 - Transistors with stressed channels and methods of manufacture: A MOS device having optimized stress in the channel region and a method for forming the same are provided. The MOS device includes a gate over a substrate, a gate spacer on a sidewall of the gate wherein a non-silicide region exists under the gate spacer, a source/drain region comprising... Agent: Slater & Matsil, L.L.P.

20070267695 - Silicon-on-insulator structures and methods of forming same: Methods which include providing a single crystal silicon substrate having a device pattern formed on a portion of the substrate where the device pattern has a protrusion, forming a protection layer on a portion of the protrusion, and forming an oxide insulation layer between the protrusion and the substrate using... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070267697 - Structure of semiconductor device and method of fabricating the same: A structure of semiconductor device including an insulation substrate is provided. A channel layer is disposed on the insulation substrate. A plurality of doped layers is disposed on the insulation substrate, and protrudes from the channel layer. The doped layers form at least two source/drain electrode (S/D electrode) pairs, and... Agent: Jianq Chyun Intellectual Property Office

20070267698 - Dual wired integrated circuit chips: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side... Agent: Schmeiser, Olsen & Watts

20070267696 - Mobile transforming plug: A mobile transforming plug includes an insulating main body, a shell cover, a linking element and a linker. At the front side of the insulating main body, a connecting part is formed. A carrying part is formed at the rear side of the insulating main body. There is a connection... Agent: Rosenberg, Klein & Lee

20070267699 - Transistor including a deposited channel region having a doped portion: A transistor having a gate electrode, a source electrode, a drain electrode, a dielectric material and a channel region disposed between the source electrode and drain electrode. The channel region includes a portion doped with an impurity to change the fixed charge density within the portion relative to a remainder... Agent: Hewlett Packard Company

20070267700 - Esd protection element: According to one embodiment of the present invention, an ESD protection element for use in an electrical circuit is provided, including a plurality of diodes which are connected in series with one another and which are formed in a contiguous active area, wherein the ESD protection element has a fin... Agent: Dickstein Shapiro LLP

20070267701 - Electrostatic discharge circuit and method for reducing input capacitance of semiconductor chip including same: A multi-mode electrostatic discharge (ESD) circuit for a semiconductor chip comprises first and second ESD diodes. In a first mode, a body voltage greater than a power source voltage of the semiconductor chip is applied to the first ESD diode and a body voltage less than a ground voltage of... Agent: Volentine & Whitt PLLC

20070267702 - Dynamic threshold p-channel mosfet for ultra-low voltage ultra-low power applications: A dynamic threshold voltage p-channel MOSFET (PMOS) for ultra-low power ultra-low voltage applications is disclosed. These applications are of low-to-moderate performance requirements; hence ultra-low voltage subthreshold operation, where the supply voltage is less than the transistors threshold voltage, is suitable. By tying the PMOS body to the output node of... Agent: Kean, Miller, Hawthorne, D'armond, Mccowan & Jarman, L.L.P.

20070267703 - Strained channel transistor and method of fabrication thereof: The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain... Agent: Ishimaru & Zahrt LLP

20070267704 - Method of fabricating thin film transistor: A method of fabricating a CMOS thin film transistor includes: providing a substrate; forming an amorphous silicon layer on the substrate; performing a first annealing process on the substrate and crystallizing the amorphous silicon layer into a polysilicon layer; patterning the polysilicon layer to form first and second semiconductor layers;... Agent: Stein, Mcewen & Bui, LLP

20070267705 - Semiconductor integrated circuit device having mim capacitor and method of fabricating the same: In a semiconductor integrated circuit device and a method of formation thereof, a semiconductor device comprises: a semiconductor substrate; an insulator at a top portion of the substrate, defining an insulator region; a conductive layer pattern on the substrate, the conductive layer pattern being patterned from a common conductive layer,... Agent: Mills & Onello LLP

20070267706 - Formation of low leakage thermally assisted radical nitrided dielectrics: One or more aspects of the present invention relate to forming a dielectric suitable for use as a gate dielectric in a transistor. The gate dielectric is formed by a nitridation process that adds nitrogen to a semiconductor substrate.... Agent: Texas Instruments Incorporated

20070267707 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a first active region surrounded with an isolation region of a semiconductor substrate; a first gate electrode formed over the first active region and having a protrusion protruding on the isolation region; a first side-wall insulating film; an auxiliary pattern formed to be spaced apart in... Agent: Mcdermott Will & Emery LLP

20070267708 - Methods and apparatus having an integrated circuit attached to fused silica: Disclosed are methods for attaching an integrated circuit to a substrate, and in particular, a fused silica substrate, along with apparatus fabricated using the methods. Exemplary apparatus comprises a glass substrate, a metallic layer disposed on the substrate, and an integrated circuit eutectically bonded to the glass substrate via the... Agent: Law Offices Of Kenneth W. Float

20070267709 - Magnetic sensor having vertical hall device: A vertical Hall device includes: a substrate; a semiconductor region having a first conductive type and disposed in the substrate; and a magnetic field detection portion disposed in the semiconductor region. The magnetic field detection portion is capable of detecting a magnetic field parallel to a surface of the substrate... Agent: Posz Law Group, PLC

20070267710 - High performance photosensor: A photosensor includes a photovoltage generator for generating a photovoltage, and a comparator for determining a number of integer multiples of a threshold voltage associated with the photosensor. A primary counter is incremented by the determined number of integer multiples. A voltage injector adds at least one unit of voltage... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070267711 - Optical receiving device: An optical receiving device has a photoelectric conversion layer including a matrix semiconductor containing silicon atoms as a main component, an n-type dopant D substituted for the silicon atom in a lattice site, and a heteroatom Z inserted into an interstitial site positioned closest to the n-type dopant D, in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070267712 - Solid state imaging device, semiconductor wafer, optical device module, method of solid state imaging device fabrication, and method of optical device module fabrication: With the reduced size of a solid state imaging device, the invention provides: a solid state imaging device of a chip size and having good environmental durability; a semiconductor wafer used for fabricating a solid state imaging device; an optical device module incorporating a solid state imaging device; a method... Agent: Edwards Angell Palmer & Dodge LLP

20070267713 - Communication device for two-dimensional diffusive signal transmission: A communication device capable of transmitting a signal by two-dimensional diffusive signal transmission technology includes: a signal layer in which the signal is transmitted; a plurality of communication chips which are connected to the signal layer to transmit the signal by the two-dimensional diffusive signal transmission technology; a power supply... Agent: Greenblum & Bernstein, P.L.C

20070267714 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070267715 - Shallow trench isolation (sti) with trench liner of increased thickness: Improved shallow trench isolation (STI) techniques are provided for semiconductor devices. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a substrate, a first trench in the substrate, and a second trench in the substrate. A first silicon dioxide liner substantially lines the first... Agent: Macpherson Kwok Chen & Heid LLP

20070267716 - Current amplifying integrated circuit: Present invention proposes a dramatic improvement of CMOS IC technology by providing high speed bipolar current amplifiers compatible with CMOS technological process while retaining the footprint compatible to one of standard CMOS devices. This invention promises further increase of speed of ICs as well as a reduction of power dissipation.... Agent: Sergey Antonov

20070267717 - Coaxial rf device thermally conductive polymer insulator and method of manufacture: An insulator supporting an inner conductor within the outer conductor of a coaxial device formed from a portion of thermally conductive polymer composition with a thermal conductivity of at least 4 W/m-K. The portion is dimensioned with an outer diameter in contact with the outer conductor and a coaxial central... Agent: Babcock Ip, PLLC

20070267718 - Multilayer winding inductor: A multilayer winding inductor. The inductor at least includes multi-level interconnect and single-level interconnect structures. The multi-level interconnect structure includes a plurality of conductive plugs and a plurality of looped conductive traces overlapping and separated from each other. Each looped conductive trace has a gap to define first and second... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070267720 - Semiconductor device including capacitor connected between two conductive strip groups: A semiconductor device includes an upper conductive strip group and a lower conductive strip group crossing under the upper conductive strip group. Adjacent first and second conductive strips of the upper conductive strip group are adapted to receive a first voltage, a third conductive strip of the lower conductive strip... Agent: Mcginn Intellectual Property Law Group, PLLC

20070267719 - Structure and manufacturing method of high precision chip capacitor fabricated on silicon substrate: The present invention provides a structure and the manufacturing method of high precision chip capacitor fabricated on silicon substrate. The structure of the chip capacitor consists of a dielectric layer formed on the surface of a heavily doped silicon substrate with an inner primary portion of thin oxide and an... Agent: Perkins Coie LLP

20070267721 - Phase change memory cell employing a gebite layer as a phase change material layer, phase change memory device including the same, electronic system including the same and method of fabricating the same: A phase change memory cell includes an interlayer insulating layer formed on a semiconductor substrate, and a first electrode and a second electrode disposed in the interlayer insulating layer. A phase change material layer is disposed between the first and second electrodes. The phase change material layer may be an... Agent: Myers Bigel Sibley & Sajovec

20070267722 - Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.... Agent: Goodwin Procter LLP Patent Administrator

20070267723 - Double-sided integrated circuit chips: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and... Agent: Schmeiser, Olsen & Watts

20070267724 - Integrated circuit having stress tuning layer and methods of manufacturing same: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of... Agent: Slater & Matsil, L.L.P.

20070267725 - Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package: In a semiconductor chip, a body has a top surface where a pattern is formed, an underside surface opposing the top surface and a plurality of side surfaces. A plurality of electrode pads are formed on the top surface of the body to connect to an external terminal. A shielding... Agent: Mcdermott Will & Emery LLP

20070267726 - Dual side cooling integrated power device module and methods of manufacture: An integrated power device module including a lead frame having first and second spaced pads, one or more common source-drain leads located between the first and second pads, and one or more drain leads located on the outside of the second pad. First and second transistors are flip chip attached... Agent: Hiscock & Barclay, LLP

20070267727 - Copper straps: A copper strap for a semiconductor device package having a contact electrically connected to a die electrode, a leg portion electrically connected to a lead frame, a web portion positioned between the contact and the leg portion and connected to the leg portion and a connection region connecting the web... Agent: Ostrolenk Faber Gerb & Soffen

20070267728 - Flip chip mlp with folded heat sink: A semiconductor package assembly including a molded leadless package (MLP) having an exposed top emitter pad and an exposed bottom source pad. A folded heat sink is attached to the exposed top emitter pad of the MLP by a soft solder attach process. The folded heat sink has a planar... Agent: Hiscock & Barclay, LLP

20070267729 - Electronic component having a semiconductor power device: An electronic component adapted to be mounted on a substrate with landing pads having a landing pad layout has a power semiconductor device and outer contact surfaces with a component pad layout. The outer contact surfaces have an arrangement so that, in a first orientation, the component pad layout matches... Agent: Baker Botts, L.L.P.

20070267731 - Integrated circuit package system with different mold locking features: An integrated circuit package system is provided including forming a first inner lead having a first inner bottom side and a first outer lead, forming a first side lock of the first inner lead above the first inner bottom side, connecting an integrated circuit die with the first inner lead... Agent: Ishimaru & Zahrt LLP

20070267730 - Wafer level semiconductor chip packages and methods of making the same: A wafer having a front surface and contacts exposed at the front surface is treated by forming electrically conductive risers projecting upwardly from the contacts as, for example, by electroless plating, and then applying a flowable material over the front surface of the device, around the risers, to form a... Agent: Tessera Lerner David Et Al.

20070267732 - Circuit card module and method for fabricating the same: A circuit card module and a method for fabricating the same are disclosed. The present invention includes the steps of providing a carrier having at least a first carrying region and a second carrying region that are co-planar; respectively mounting a substrate electrically connected to a first chip on the... Agent: Edwards Angell Palmer & Dodge LLP

20070267733 - Symmetrical mimcap capacitor design: Semiconductor chip capacitance circuits and methods are provided comprising at least two capacitors mounted close to a substrate, wherein each capacitor has a lateral lower conductive plate mounted near enough to the substrate to have extrinsic capacitance greater than an upper plate extrinsic capacitance. One half of lower plates and... Agent: Driggs, Hogg & Fry Co. L.p.a.

20070267734 - No-lead ic packages having integrated heat spreader for electromagnetic interference (emi) shielding and thermal enhancement: Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages are described. A die-up or die-down package includes an IC die, a die attach pad, a heat spreader cap coupled to the die attach pad defining a cavity, and one or more peripheral... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070267736 - Semiconductor device and method of manufacturing the same: A semiconductor device manufacturing method capable of improving the semiconductor device manufacturing yield is disclosed. Semiconductor chips are mounted respectively over semiconductor device regions of a matrix wiring substrate having plural semiconductor device regions, followed by wire bonding, and thereafter sealing resin is formed at a time onto the semiconductor... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070267735 - Semiconductor device with semiconductor chips mounted on mounting board: A plurality of conductive pads (2) are formed on a mounting surface of a mounting board. Conductive pads (11) are formed on a principal surface of a semiconductor chip (10) at positions corresponding to the conductive pads of the mounting board, when the principal surface faces toward the mounting board.... Agent: Kratz, Quintos & Hanson, LLP

20070267737 - Packaged devices and methods for forming packaged devices: Packaged devices and methods of forming packaged devices are provided. At least one device is disposed on a substrate. The material layer encapsulates the device and covers at least a portion of the substrate, wherein the material layer comprises at least a first portion adjacent to the device and a... Agent: Duane Morris LLPIPDepartment (tsmc)

20070267738 - Stack-type semiconductor device having cooling path on its bottom surface: Provided is a semiconductor device having a cooling path on its bottom surface. The stack-type semiconductor device having a cooling path comprises a stack-type semiconductor chip comprising a first semiconductor chip and a second semiconductor chip. The first semiconductor chip comprises a first surface in which a circuit unit is... Agent: Marger Johnson & Mccollom, P.C.

20070267739 - Power semiconductor module: A power semiconductor module and an inverter apparatus in which a device or a joining part is not mechanically damaged even when the temperature in use becomes a high temperature in the range of 175 to 250° C., resulting in excellent reliability at high temperature retaining test and thermal cycling... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070267740 - Method and apparatus for cooling semiconductor device hot blocks and large scale integrated circuit (ic) using integrated interposer for ic packages: A method, system, and apparatus for improved IC device packaging is described. In an aspect, an (IC) device package includes an IC die having at one or more contact pads, each contact pad located at a corresponding hotspot on a surface of the IC die. The package also includes a... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070267741 - Liquid submersion cooling system: A portable, self-contained liquid submersion cooling system that is suitable for cooling a number of electronic devices, including cooling heat-generating components in computer systems and other systems that use electronic, heat-generating components. The electronic device includes a housing having an interior space, a dielectric cooling liquid in the interior space,... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20070267742 - Dual mosfet package: A semiconductor device package comprises a first semiconductor die having a first source region, a first gate region, and a first drain region attached on a first leadframe, a second semiconductor die having a second source region, a second gate region, and a second drain region attached on a second... Agent: Rosenberg, Klein & Lee

20070267743 - Semiconductor device having low dielectric insulating film and manufacturing method of the same: A semiconductor device includes a semiconductor substrate and low dielectric film wiring line laminated structure portions which are provided in regions on the semiconductor substrate except a peripheral portion thereof. Each of the laminated structure portions has a laminated structure of low dielectric films and a plurality of wiring lines.... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070267744 - Manufacturing a bump electrode with roughened face: A semiconductor device and a method for making the same, wherein bumps of a semiconductor chip and inner leads of a film tape carrier can be securely bonded to each other by thermal welding using a heating unit.... Agent: Oliff & Berridge, PLC

20070267745 - Semiconductor device including electrically conductive bump and method of manufacturing the same: A semiconductor device and method of manufacturing are provided that include forming an electrically conductive bump on a substrate and forming at least one passivation layer on the bump to reduce solder joint failures.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070267746 - Dual-sided chip attached modules: An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads... Agent: Schmeiser, Olsen & Watts

20070267747 - Dispersions of intrinsically conductive polymers, and methods for the production thereof: The invention relates to a dispersion which contains particles of at least one intrinsically conductive polymer, wherein the particle size is on average (weight) less than 1 μm, and which is characterized in that the dispersant is a liquid at room temperature, and a layer, film or sheet formed from... Agent: Swanson & Bratschun, L.L.C.

20070267748 - Integrated circuit having pads and input/output (i/o) cells: A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a... Agent: Freescale Semiconductor, Inc. Law Department

20070267749 - Metallization layer for a power semiconductor device: A power semiconductor IC device is disclosed. In one embodiment, the device includes a substrate, and a layer structure formed on the substrate. The layer structure includes a metallization layer including copper, wherein the metallization layer is formed as a stack structure including at least two copper layers and a... Agent: Dicke, Billig & Czaja

20070267750 - Semiconductor device including interconnect layer made of copper: A semiconductor device includes an interlayer insulating film, a barrier metal layer, a conductive layer and a first insulating film. The barrier metal layer is formed on a bottom surface and a side face of a trench made in the interlayer insulating film. The conductive layer is formed on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070267751 - Structure and method for creating reliable via contacts for interconnect applications: A reliable and mechanical strong interconnect structure is provided that does not include gouging features in the bottom of the an opening, particularly at a via bottom. Instead, the interconnect structures of the present invention utilize a Co-containing buffer layer that is selectively deposited on exposed surfaces of the conductive... Agent: Scully Scott Murphy & Presser, PC

20070267752 - Semiconductor device having pad structure for preventing and buffering stress of silicon nitride film: A semiconductor device having a pad structure for preventing a stress of a silicon nitride film. The semiconductor device includes a semiconductor substrate, a lower structure formed on the semiconductor substrate, a first insulation film formed on the lower structure, a first metal layer coupled to the lower structure through... Agent: Marshall, Gerstein & Borun LLP

20070267753 - Substantially l-shaped silicide for contact and related method: A structure, semiconductor device and method having a substantially L-shaped silicide element for a contact are disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the structure includes a substantially L-shaped silicide element including a base member... Agent: Hoffman, Warnick & D'alessandro LLC

20070267754 - Microfeature workpieces and methods for forming interconnects in microfeature workpieces: Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a method of forming an interconnect in a microfeature workpiece includes forming a hole extending through a terminal and a dielectric layer to at least an intermediate depth in a substrate... Agent: Perkins Coie LLP Patent-sea

20070267755 - Integrated circuit having pads and input/output (i/o) cells: A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a... Agent: Freescale Semiconductor, Inc. Law Department

20070267756 - Integrated circuit package and multi-layer lead frame utilized: An IC package with a defined wire-bonding region primarily comprises a multi-layer lead frame with a plurality of leads, a chip, a plurality of bonding wires within the wire-bonding region, and at least an electrical transition component outside the wire-bonding region. At least a transition finger is carried on one... Agent: Troxell Law Office PLLC

20070267757 - Semiconductor device: A semiconductor device of the present invention includes a semiconductor chip provided with a plurality of electrodes on one surface thereof in the thickness direction and a resin layer provided so as to overlap the one surface of the semiconductor chip. In the semiconductor device, a surface of the resin... Agent: Rabin & Berdo, PC

20070267758 - Semiconductor package: A semiconductor package comprises a first chip, a substrate, a middle layer, a second chip, and an encapsulant. The first chip has an active surface and a high-frequency element defining a high-frequency area on the active surface. The substrate supports the first chip and is electrically connected to the first... Agent: Lowe Hauptman Ham & Berner, LLP

20070267759 - Semiconductor device with a distributed plating pattern: A substrate, and a semiconductor die package formed therefrom, are disclosed which include a distributed plating pattern for reducing mechanical stress on the semiconductor die. The substrate according to embodiments of the invention may include traces and contact pads plated in a double image plating process. Additionally, the substrate may... Agent: Vierra Magen/sandisk Corporation

20070267760 - Semiconductor apparatus: A semiconductor apparatus includes an internal layer where a first power supply line to provide a first power supply to transistors in a layout cell and an internal cell line to connect transistors in the layout cell are placed, an input/output line connected with an input/output terminal of the layout... Agent: Mcginn Intellectual Property Law Group, PLLC

20070267761 - Semiconductor device and method of designing the semiconductor device: A semiconductor device according to an embodiment of the present invention includes: a first region having patterns formed based on grid points as intersections of grid lines; and a second region including a plurality of layout cells an outer edge of which is defined by the grid points, the layout... Agent: Mcginn Intellectual Property Law Group, PLLC

20070267762 - Semiconductor devices: A semiconductor device is disclosed. The device has a first and second electrode formed in a semiconductor substrate. The first and second electrode are separated from each other by a semiconductor region. and the device also includes a third electrode for controlling conductivity of the semiconductor region. At least one... Agent: Knobbe Martens Olson & Bear LLP

20070262292 - Photodetecting device and method of manufacturing the same: A photodetecting device which is capable of performing photodetection with a high sensitivity in a wide temperature range. A quantum dot structure including an embedding layer and quantum dots embedded by the embedding layer is formed. A quantum well structure including embedding layers and a quantum well layer whose band... Agent: Kratz, Quintos & Hanson, LLP

20070262293 - Nitride semiconductor light emitting element: A n-type layer, a multiquantum well active layer comprising a plurality of pairs of an InGaN well layer/InGaN barrier layer, and a p-type layer are laminated on a substrate to provide a nitride semiconductor light emitting element. A composition of the InGaN barrier included in the multiquantum well active layer... Agent: Mcginn Intellectual Property Law Group, PLLC

20070262300 - Method of forming fine pattern using azobenzene-functionalized polymer and method of manufacturing nitride-based semiconductor light emitting device using the method of forming fine pattern: Provided is a method of forming a fine pattern having a pattern dimension of 1 μm or less, repeatedly with reproducibility. The method of forming the fine pattern includes: forming an azobenzene-functionalized polymer film on an etched layer; irradiating the azobenzene-functionalized polymer film using an interference laser beam to form... Agent: Cantor Colburn, LLP

20070262303 - Organic semiconductor crystalline film, method for preparing the same, organic transistor, and organic phototransistor: An organic semiconductor crystalline film and weak oriented epitaxy growth preparation method thereof. The organic semiconductor crystalline film is a n-type semiconductor or a p-type semiconductor, and organic semiconductor crystal molecules in the organic semiconductor crystalline film are oriented in a stand-up manner on the ordered substrate, and have an... Agent: Leonard Tachner, A Professional Law Corporation

20070262298 - Photosensing soluble organic semiconductor material: A photosensing soluble organic semiconductor material is disclosed, which includes a Diels-Alder adduct which is a polycyclic aromatic compound with a dienophile. The polycyclic aromatic compound is selected from the group consisting of oligothiophene, perylene, benzo[ghi]perylene, coronene and polyacene. And the dienophile is represented by the formula of O═S═N—R1, wherein... Agent: Jianq Chyun Intellectual Property Office

20070262304 - Fast recovery rectifier: A fast recovery rectifier structure with the combination of Schottky structure to relief the minority carriers during the forward bias condition for the further reduction of the reverse recovery time during switching in addition to the lifetime killer such as Pt, Au, and/or irradiation. This fast recovery rectifier uses unpolished... Agent: Charles T. Cheng

20070262309 - Liquid crystal display device: A liquid crystal display device includes a first substrate and a second substrate facing each other having a pixel region; a color filter layer on the first substrate corresponding to the pixel region; a planarization layer on the color filter layer having a groove; a common electrode on the planarization... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070262310 - Liquid crystal display device and driving method thereof: A liquid crystal display device includes: a liquid crystal panel; a horizontal sync signal having a horizontal period; a gate driver that supplies a plurality of gate signals sequentially to a plurality of gate lines, wherein a first gate line provides a gate signal with a gate pulsewidth equal to... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070262308 - Thin film transistor array panel and manufacturing method thereof: A thin film transistor array panel includes a substrate with a plurality of gate lines and data lines crossing each other, wherein the gate lines and the data lines define pixel groups each including a plurality of pixels, and a plurality of thin film transistors are connected to the gate... Agent: Cantor Colburn, LLP

20070262316 - Liquid crystal display device and method of fabricating the same: A liquid crystal display device includes a gate line and a data line crossing each other to define a pixel region on a substrate, a gate electrode connected to the gate line, a gate insulating layer on the gate electrode, an active layer on the gate insulating layer, source and... Agent: Seyfarth Shaw, LLP

20070262317 - Poly-silicon thin film transistor array substrate and method for fabricating the same: A poly-silicon thin film transistor array substrate includes a gate line and a gate electrode over a substrate, a semiconductor layer having source/drain regions doped with impurity ions, a data line crossing the gate line, and source/drain electrodes connected to the source/drain regions, and a pixel electrode connected to the... Agent: Seyfarth Shaw, LLP

20070262312 - Thin film transistor array substrate structures and fabrication method thereof: A thin film transistor array substrate structure. The array substrate structure includes a thin film transistor array substrate, an organic material layer formed thereon, and a plurality of black matrices and color filter patterns disposed on the organic material layer. The invention also provides a method of fabricating the thin... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070262315 - Thin film transistor substrate, liquid crystal display panel including the same, and method of manufacturing liquid crystal display panel: A liquid crystal display panel capable of preventing flicker and improving reflectance include a thin film transistor substrate having a gate line, a data line, a thin film transistor connected to the gage and data lines, and a reflective electrode connected to the thin film transistor and covering at least... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070262313 - Thin film transistor, method of manufacturing the thin film transistor, and display substrate having the thin film transistor: A thin film transistor includes a semiconductor pattern disposed on a substrate and a semiconductor pattern portion with a conductive or nonconductive characteristic, and a anti-diffusion portion on a side of the semiconductor pattern portion to prevent metal ions from being diffused along the semiconductor pattern portion. A first insulating... Agent: Brinks Hofer Gilson & Lione

20070262323 - Semiconductor light emitting element array illuminator using the same: A semiconductor light emitting element array includes a substrate made of SiC and having a first surface and a second surface opposite to the first surface. The array also includes a plurality of semiconductor light emitting elements supported by the first surface of the substrate. Each of the light emitting... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20070262330 - Light emitting device having multi-pattern structure and method of manufacturing same: A semiconductor light emitting device having a multiple pattern structure greatly increases light extraction efficiency. The semiconductor light emitting device includes a substrate and a semiconductor layer, an active layer, and an electrode layer formed on the substrate, a first pattern defining a first corrugated structure between the substrate and... Agent: Cantor Colburn, LLP

20070262329 - Semiconductor device and method for manufacturing the same: A semiconductor device manufacturing method can produce semiconductor light emitting/detecting devices that have high connective strength and high luminous energy by increasing contact areas of electrodes thereof and decreasing enclosed areas of electrodes thereof. A wafer is provided with a semiconductor substrate and a semiconductor epitaxial layer. A plurality of... Agent: Cermak Kenealy & Vaidya, LLP

20070262331 - Semiconductor device, led printhead, and image forming apparatus: An inclined surface having an inclination angle θ is formed in an edge portion which forms an opening portion of an inter-layer insulating film, thereby reducing a stress by the inclined surface.... Agent: Rabin & Berdo, PC

20070262328 - Semiconductor light emitting device and a method for producing the same: Both ends of the lead arrangement project outward from side surfaces of a package to form outer lead regions. Each of the outer lead regions includes a pair of outer lead projections and lead terminal smaller projections that are located between the outer lead projections. The outer lead projections and... Agent: Ditthavong Mori & Steiner, P.C.

20070262332 - Light emitting device and method for fabricating the same: Embodiments of a light emitting device and a method for fabricating the same are provided. The light emitting device comprises a cavity and one or more light emitting elements. The cavity is formed to a depth of 450 μm or less, and the light emitting elements are installed in the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070262334 - Full color led display: A full color LED display, comprised a plurality of full color luminant units, is characteristic of: each of the full color luminant units comprises four LEDs distributed in a cross type; each of the LEDs has a polygon top; each space between any two adjacent LEDs of the LEDs is... Agent: Kamrath & Associates P.A.

20070262336 - Light emitting device: A light emitting device includes a package having a recessed portion defined by a bottom surface and a side surface and a light emitting element mounted on the bottom surface of the recessed portion, in which the package has fibrous fillers, and at least some of the fillers are projected... Agent: Perkins Coie LLP

20070262335 - Light emitting device with porous alumina reflector and its manufacture: A light emitting device is provided which has a reflector having a reflection surface made of porous alumina having an apparent density of 2.5 to 3.3 g/cm3, and an LED disposed on the reflection surface or near the reflection surface. There are provided: a light emitting device equipped with an... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070262294 - Light source including quantum dot material and apparatus including same: A light source comprising a light emitting device and quantum dot material is disclosed. According to various embodiments, the quantum dot material is positioned relative to the light emitting device such that the quantum dot material absorbs light emitted from the light emitting device and converts the wavelengths of photons... Agent: Mccarter & English , LLP Stamford Office

20070262295 - A method for manipulation of oxygen within semiconductor materials: Methods and electronic devices fabricated by those methods are disclosed where the method allows controlled movement of oxygen during fabrication of electronic and photonic devices, facilitated by a technique of oxygen updiffusion (OUD). The method includes fabrication of a compound semiconductor film, doped with either carbon or boron, over a... Agent: Schneck & Schneck

20070262296 - Photodetectors employing germanium layers: A germanium-based photodetector comprises a p- (or n-type) germanium layer, an intrinsic single crystal germanium layer formed on the p- (or n-) type germanium layer, and an n- (or p-type) germanium layer formed on the intrinsic single crystal germanium layer. An electrically conductive contact extends vertically from an upper surface... Agent: Knobbe, Martens, Olsen & Bear LLP

20070262301 - Data storage device and method: A serial magnetic mass storage device and associated data storage method of the kind in which data is encoded in single magnetic domains in nanowires. In the invention, the nanowires are provided with a large number of notches along their length to form domain wall pinning sites. Moreover, the notches... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20070262302 - Light emitting devices and compositions: A light emitting composition includes a light-emitting lumophore-functionalized nanoparticle, such as an organic-inorganic light-emitting lumophore-functionalized nanoparticle. A light emitting device includes an anode, a cathode, and a layer containing such a light-emitting composition. In an embodiment, the light emitting device can emit white light.... Agent: Knobbe Martens Olson & Bear LLP

20070262299 - Organic light emitting device and method of fabricating the same: An organic light emitting device which has an anode, i.e. a lower electrode, made of a single metal layer in a top emission structure, and a method of fabricating the same are provided. The organic light emitting device is constructed with a substrate, an anode disposed on the substrate and... Agent: Robert E. Bushnell Suite 300

20070262297 - Organic thin-film transistor device and corresponding manufacturing method: An organic thin-film transistor device integrated on a substrate and comprising at least an organic active layer and metallic contact regions realized on an insulating layer. Advantageously the organic thin-film transistor device further comprises a thin buffer layer of polymethylmetacrylate or PMMA realized between the metallic contact regions and the... Agent: Graybeal, Jackson, Haley LLP

20070262305 - Integrated circuit protection from esd damage during fabrication: A semiconductor integrated circuit wafer containing a plurality of integrated circuit chips and having a common substrate, each chip formed with an internal region in the interior of the chip and a removable external region on the perimeter of the internal region and circuitry disposed preferably in the external region... Agent: Edward W. Brown

20070262306 - Semiconductor device having microstructure and method of manufacturing microstructure: A semiconductor device having a microstructure and a method of manufacturing a microstructure are provided, suppressing any change of characteristics in a wafer state caused in an assembly step. Specifically, a wafer where a plurality of microstructure chips are formed and a dummy wafer are attached to each other using... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070262307 - Method of forming an oxygen- or nitrogen-terminated silicon nanocrystalline structure and an oxygen- or nitrogen-terminated silicon nanocrystalline structure formed by the method: A substrate is set at a predetermined temperature in a plasma treatment chamber, then the inside of the plasma treatment chamber is regulated at a reduced pressure containing at least a silicon hydride gas and a hydrogen gas, a high-frequency electric field is applied to form a silicon film of... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070262311 - Flat panel display and fabrication method and thereof: The method for fabricating a flat panel display includes performing a first crystallization process to re-crystallize an amorphous silicon layer on a glass substrate to make the amorphous silicon layer become a polysilicon layer, forming a patterned absorbing layer to cover an active area pattern of a driving TFT and... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070262319 - Lcd with first and second circuit regions each with separately optimized transistor properties: A large number of pixels PXL are arranged in a matrix fashion in a display region DSP on an insulating substrate. Disposed around the display region DSP are a drain-side pixel-driving circuit including a drain shift register DSR, a digital-to-analog converter circuit DAC, a drain level shifter DLS, a buffer... Agent: Stanley P. Fisher Reed Smith LLP

20070262318 - Method for manufacturing display device: The present invention provides a method for manufacturing a display device having a TFT that can be operated at high speed while using a small number of photomasks and improving the utilization efficiency of materials, where the threshold value is difficult to be varied. In the invention, a catalytic element... Agent: Nixon Peabody, LLP

20070262314 - Transistor, method of fabricating the same and organic light emitting display including the transistor: A transistor includes; at least two polycrystalline silicon layers disposed substantially parallel to each other, each polycrystalline silicon layer including a channel region and at least two high conductivity regions disposed at opposing sides of the channel region; a gate which corresponds to the channel region of the two polycrystalline... Agent: Cantor Colburn, LLP

20070262320 - Electron emitter and the method of manufacturing the same apparatus: An electron emitter according to the present invention includes: an area in which a surface of the substrate is exposed or an area in which the inner surface of the substrate is exposed; the SiC substrate with the (0001) surface as a principal surface; the electron emission layer has carbon... Agent: Greenblum & Bernstein, P.L.C

20070262321 - Lateral field effect transistor and its fabrication comprising a spacer layer above and below the channel layer: A lateral field effect transistor for high switching frequencies having a source region layer (4) and a drain region layer (5) laterally spaced and of highly doped first conductivity type, a first-conductivity-type channel layer (6) of lower doping concentration extending laterally and interconnecting the source region layer (4) and the... Agent: Dilworth & Barrese, LLP

20070262322 - Monocrystalline silicon carbide ingot, monocrystalline silicon carbide wafer and method of manufacturing the same: Provided is a monocrystalline silicon carbide ingot containing a dopant element, wherein a maximum concentration of the dopant element is less than 5×1017 atoms/cm3 and the maximum concentration is 50 times or less than that of a minimum concentration of the dopant element. Also provided is a monocrystalline silicon carbide... Agent: Birch Stewart Kolasch & Birch

20070262324 - Silicon carbide semiconductor device: A silicon carbide semiconductor device is provided with a semiconductor substrate (20) of silicon carbide of a first conductivity type, a hetero semiconductor region (60) forming a hetero-junction with the semiconductor substrate (20), an insulated gate including a gate electrode (40) and a gate insulator layer (30) formed on the... Agent: Mcdermott Will & Emery LLP

20070262326 - Led multi-layer metals primary electrodes manufacturing process & installation: Primary electrodes process and installation for manufacturing of LED multi-layer metals comprised of having epitaxial wafer cleaned up and placed in the manufacturing installation to undergo multi-metal electrodes process; installation include a loader, a magnetic device, a carrier, a magnetic mask, and multiple-layer metal sources for epitaxial wafer loaded by... Agent: Troxell Law Office PLLC

20070262325 - Light emitting diode and wavelength converting material: A wavelength converting material including a wavelength converting activator and a scatter is provided. The wavelength converting activator is suitable for being activated by a light with a wavelength λ1, so as to emit a light with a wavelength λ2. The scatter is disposed on the wavelength converting activator. The... Agent: Jianq Chyun Intellectual Property Office

20070262327 - Semiconductor device using buried oxide layer as optical wave guides: A semiconductor optical wave guide device is described in which a buried oxide layer (BOX) is capable of guiding light. Optical signals may be transmitted from one part of the semiconductor device to another, or with a point external to the semiconductor device, via the wave guide. In one example,... Agent: Banner & Witcoff, Ltd.

20070262333 - Light-emitting element array and image forming apparatus: A light-emitting element array can be manufactured without the separation of a metal reflection layer. The light-emitting element array includes a plurality of light-emitting element portions provided on a substrate, at least one space of the spaces between adjacent light-emitting element portions being electrically separated from each other, wherein the... Agent: Fitzpatrick Cella Harper & Scinto

20070262337 - Multiple thermal path packaging for solid state light emitting apparatus and associated assembling methods: A mounting substrate includes a peripheral portion and a central portion. Solid state light emitting elements are provided on the mounting substrate. A housing is configured to thermally couple to the peripheral portion of the mounting substrate, so as to provide a first thermal conduction path for at least some... Agent: Myers Bigel Sibley & Sajovec

20070262338 - Semiconductor light-emitting element, manufacturing method and mounting method of the same and light-emitting device: An LED chip of the present invention has a structure in which an n-type semiconductor layer and a p-type semiconductor layer are successively formed on the lower face of an element substrate, with the p-type semiconductor layer being formed on an area except for an area for an n-electrode. A... Agent: Wenderoth, Lind & Ponack L.L.P.

20070262339 - Side-view surface mount white led: A light emitting diode is disclosed. The diode includes a package support and a semiconductor chip on the package support, with the chip including an active region that emits light in the visible portion of the spectrum. Metal contacts are in electrical communication with the chip on the package. A... Agent: Summa, Allan & Additon, P.A.

20070262340 - Light emitting semiconductor apparatus: The disclosed subject matter relates to a light emitting semiconductor apparatus with reduced color unevenness and suppressed topical deterioration over time with regard to an amount and chromaticity of the illuminating light. The light emitting semiconductor apparatus of the disclosed subject matter can include three separate bonding pads. Among those,... Agent: Cermak Kenealy & Vaidya, LLP

20070262342 - P-type layer for a iii-nitride light emitting device: A semiconductor structure includes a light emitting region, a p-type region disposed on a first side of the light emitting region, and an n-type region disposed on a second side of the light emitting region. At least 10% of a thickness of the semiconductor structure on the first side of... Agent: Patent Law Group LLP

20070262341 - Vertical led with eutectic layer: A vertical light-emitting diode (VLED) structure with a eutectic layer is described. The eutectic layer improves the heat conductivity of the device, thereby leading to increased brightness and higher luminous efficiency. The eutectic bonds of this layer also improve the reliability of the VLED structure since they have a lower... Agent: Patterson & Sheridan, L.L.P.

20070262343 - Semiconductor apparatus: A semiconductor apparatus includes an electrostatic protective device having PN junction with N-type Si and P-type SiGe. The electrostatic protective device is directly connected with a terminal to receive static electricity and with a terminal to discharge static electricity.... Agent: Sughrue Mion, PLLC

20070262344 - Insulated gate silicon nanowire transistor and method of manufacture: An insulated gate silicon nanowire transistor amplifier structure is provided and includes a substrate formed of dielectric material. A patterned silicon material may be disposed on the substrate and includes at least first, second and third electrodes uniformly spaced on the substrate by first and second trenches. A first nanowire... Agent: Department Of The Air Force

20070262345 - Electrostatic discharge protection device and method of fabricating same: A silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried... Agent: Schmeiser, Olsen & Watts

20070262346 - Electronic component and a method for its production: An electronic component includes a vertical semiconductor power transistor and a further semiconductor device arranged on the transistor to form a stack. The first vertical semiconductor power transistor has a semiconductor body having a first side and a second side and device structures, at least one first electrode positioned on... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20070262347 - Display substrate, method for manufacturing the same and display apparatus having the same: A display substrate having a high aperture ratio includes gate and source metallic patterns, first and second gate insulating layers, and a pixel electrode. The gate metallic pattern includes a gate line, a gate electrode and a first storage electrode. The first gate insulating layer covers at least one of... Agent: Macpherson Kwok Chen & Heid LLP

20070262348 - High-temperature stable gate structure with metallic electrode: The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has... Agent: Scully, Scott, Murphy & Presser, P.C.

20070262350 - Semiconductor integrated circuit device: Semiconductor integrated circuit device wherein action for averting antenna effect has been taken, and method for producing a semiconductor integrated circuit device in which action for averting the antenna effect can be taken with ease. The method for producing a semiconductor integrated circuit device includes forming step of forming a... Agent: Paul J. Esatto, Jr. Scully, Scott, Murphy & Presser, P.C.

20070262349 - Common pass gate layout of a d flip flop: A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of... Agent: North America Intellectual Property Corporation

20070262351 - Rescue structure and method for laser welding: A rescue structure to repair an open wire includes a first metal layer having at least a rescue line, an isolation layer formed on the first metal layer, and a second metal layer formed on the isolation layer. The second metal layer has at least a signal line crossing the... Agent: Birch Stewart Kolasch & Birch

20070262352 - Electro-optical device and electronic apparatus: An electro-optical device includes an element substrate having a plurality of pixel regions; thin-film transistors, arranged in the pixel regions, including gate electrodes, portions of a gate insulating layer, and semiconductor layers; pixel electrodes electrically connected to drain regions of the thin-film transistors; and storage capacitors including lower electrodes and... Agent: Oliff & Berridge, PLC

20070262353 - Semiconductor device and method of fabricating the same: A semiconductor device according to an embodiment of the present invention includes: a square pole-shaped channel portion made from a first semiconductor layer formed on a substrate, and surrounded with four side faces; a gate electrode formed on a first side face of the channel portion, and a second side... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070262354 - Spectrally efficient photodiode for backside illuminated sensor: A backside illuminated sensor includes a semiconductor substrate having a front surface and a back surface and a plurality of pixels formed on the front surface of the semiconductor substrate. A dielectric layer is disposed above the front surface of the semiconductor substrate. The sensor further includes a plurality of... Agent: Haynes And Boone, LLP

20070262355 - Pixel with asymmetric transfer gate channel doping: A pixel including a substrate of a first conductivity type and having a surface, a photodetector of a second conductivity type that is opposite the first conductivity type, a floating diffusion region of the second conductivity type, a transfer region between the photodetector and the floating diffusion, a gate positioned... Agent: Kathy Manke Avago Technologies Limited

20070262356 - Semiconductor device manufacturing method and semiconductor integrated circuit device: A semiconductor device manufacturing method includes forming a first insulating film on a semiconductor substrate, forming a first conductor film on the first insulating film, forming a second insulating film on the first conductor film, forming a first line-and-space pattern by etching the second insulating film and the first conductor... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070262357 - Semiconductor device and method for cutting electric fuse: An electric fuse includes: a first interconnect and a second interconnect, formed on a semiconductor substrate; a fuse link, formed on the semiconductor substrate and provided so that an end thereof is coupled to the first interconnect, the fuse link being capable of electrically cutting the second interconnect from the... Agent: Young & Thompson

20070262359 - Self heating monitor for sige and soi cmos devices: A structure, apparatus and method for deterring the temperature of an active region in semiconductor, particularly a FET is provided. A pair FETs are arranged on a silicon island a prescribed distance from one another where the silicon island is surrounded by a thermal insulator. One FET is heated by... Agent: Greenblum & Bernstein, P.L.C

20070262358 - Sensor and method for the production thereof: The invention concerns a sensor with silicon-containing components from whose sensitive detection element electrical signals relevant to a present analyte can be read out by means of a silicon semiconductor system. The invention is characterized in that the silicon-containing components are covered with a layer made of hydrophobic material in... Agent: O'shea, Getz & Kosakowski, P.C.

20070262360 - High mobility power metal-oxide semiconductor field-effect transistors: High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, or equivalents, and the current flow is in the [110]... Agent: Wagner, Murabito & Hao LLP

20070262361 - Structure and method for manufacturing strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels: The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact... Agent: Scully, Scott, Murphy & Presser, P.C.

20070262362 - Semiconductor device and manufacturing method thereof: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity... Agent: Rossi, Kimms & Mcdowell LLP.

20070262363 - Low temperature fabrication of discrete silicon-containing substrates and devices: Fabrication methods and processes are described, the methods and processes occurring at a low-temperature and involving passivation. The methods and processes easily incorporate annealing, deposition, patterning, lithography, etching, oxidation, epitaxy and chemical mechanical polishing for forming suitable devices, such as diodes and MOSFETs. Such fabrication is a suitable and more... Agent: Monique A. Vander Molen Gardere Wynne Sewell LLP

20070262364 - Method of making wafer structure for backside illuminated color image sensor: A backside illuminated sensor includes a semiconductor substrate having a front surface and a back surface, and a plurality of pixels formed on the front surface of the semiconductor substrate. The sensor further includes a plurality of absorption depths formed within the back surface of the semiconductor substrate. Each of... Agent: Haynes And Boone, LLP

20070262365 - Solid-state imaging device and method of driving the same: A charge transfer section includes first transfer electrodes for effecting the reading and transfer of electric charges and the transfer of signal charges and second transfer electrodes each provided between adjacent ones of the first transfer electrodes to effect the transfer of the signal charges along the charge transfer section.... Agent: Birch Stewart Kolasch & Birch

20070262366 - Cmos image sensor and method of manufacturing same: Disclosed are a complementary metal oxide semiconductor (CMOS) image sensor and a method of forming the same. The CMOS image sensor comprises a semiconductor substrate having a photodiode region and a transistor region. An optical path is formed between a micro lens on the photodiode region and a photodiode formed... Agent: Volentine & Whitt PLLC

20070262367 - Image pickup device and camera: An object is to provide a solid state image pickup device and a camera which do not worsen a sensor performance in terms of an optical property, a saturated charge amount and the like. A solid state image sensor including a pixel region having a plurality of pixels includes at... Agent: Fitzpatrick Cella Harper & Scinto

20070262368 - Non-volatile memory and manufacturing method thereof: A non-volatile memory is provided, including a substrate, a control gate, a floating gate, and a select gate. A source region and a drain region are disposed in the substrate. The control gate is disposed on the substrate between the source region and the drain region. The floating gate is... Agent: Jianq Chyun Intellectual Property Office

20070262370 - Semiconductor device: n

20070262371 - Semiconductor device and manufacturing method thereof: A semiconductor device includes first and second memory cells lying adjacently each other, the first cell comprising first island region and first conductive spacer, the first region including first island semiconductor portion, first insulating film and first FG, the first spacer provided on upper side portion of first FG, the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070262369 - Semiconductor device, method of fabricating the same, and patterning mask utilizied by the method: A semiconductor device. The device comprises an active region isolated by an isolation structure on a substrate. The device further comprises a gate electrode extending across the active area and overlying the substrate, a pair of source region and drain region, disposed on either side of the gate electrode on... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070262373 - Non-volatile memory integrated circuit device and method of fabricating the same: A non-volatile memory integrated circuit device and a method of fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, a tunneling dielectric layer, a memory gate and a select gate, a floating junction region, a bit line junction region and a common source region,... Agent: Mills & Onello LLP

20070262372 - Semiconductor device and method for manufacturing the same: A semiconductor device including a gate dielectric film provided on at least one site on a surface of a semiconductor substrate, at least one first gate electrode provided on the gate dielectric film, an inter-electrode dielectric film provided while covering a surface of the first gate electrode, at least partial... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070262374 - Semiconductor memory device and manufacturing method thereof: After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11)... Agent: Kratz, Quintos & Hanson, LLP

20070262375 - Non-planar transistor and techniques for fabricating the same: A non-planar transistor and methods for fabricating the same. In certain embodiments, the transistor includes an active gate and a passive gate. The active gate may be switchably coupled to a first voltage that is configured to turn on the transistor, and the passive gate may be fixedly coupled to... Agent: Michael G. Fletcher Fletcher Yoder

20070262376 - High-voltage field-effect transistor and method for manufacturing a high-voltage field-effect transistor: High-voltage field-effect transistor is provided that includes a drain terminal, a source terminal, a body terminal, and a gate terminal. A gate oxide and a gate electrode, adjacent to the gate oxide, is connected to the gate terminal. A drain semiconductor region of a first conductivity type is connected to... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20070262377 - Transistor structure and method of manufacturing thereof: Method of manufacturing and a transistor structure thereof comprising: a pair of spaced apart regions forming a source region and a drain region and defining at least part of a channel region there between, the source region and the drain region comprising a semiconductor heavily doped with n-type impurity element... Agent: Nath & Associates

20070262380 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device comprises: a semiconductor substrate including a SOI region and a bulk region; a first element formed in the SOI region; a second element formed in the bulk region; a first element isolation layer including a trench structure; and a second element isolation layer including a LOCOS structure.... Agent: Advantedge Law Group, LLC

20070262381 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor chip having at least an electrode pad and a device formed on a semiconductor layer on its surface, a seal cap having a recess portion facing the device which is adhered to the surface of the semiconductor chip, and a cavity as an airspace... Agent: Thomas Spinelli Scully, Scott, Murphy & Presser

20070262379 - Metal structure of glass substrate and formation thereof: Aluminum gate electrode parasitic resistance and capacitance delay suffers performance, and even makes the signal loss to high-resolution and small-size requests for thin film transistor liquid crystal display. An important technology employed in manufacturing thin film transistor is to convert surface of glass substrate into a silicon nitride layer, and... Agent: Jianq Chyun Intellectual Property Office

20070262378 - Technique for stable processing of thin/fragile substrates: A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070262382 - Semiconductor device and a method of manufacturing the same: In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is... Agent: Miles & Stockbridge PC

20070262384 - Semiconductor device and method of manufacturing the same: A semiconductor device comprising a high breakdown voltage transistor and a low breakdown voltage transistor. The semiconductor device comprises a support substrate, an insulating layer formed on the support substrate, a high breakdown voltage transistor, a low breakdown voltage transistor, wherein the high breakdown voltage transistor is adjacent to a... Agent: Edwards Angell Palmer & Dodge LLP

20070262383 - Soi substrate and semiconductor integrated ciruit device: A semiconductor IC device includes a base substrate comprising P−-type silicon, a first P+-type silicon layer is provided on the base substrate, and an N+-type silicon layer and a second P+-type silicon layer are provided in the same layer thereon. The impurity concentration of the first P+-type silicon layer and... Agent: Sughrue Mion, PLLC

20070262385 - Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit: An integrated circuit includes NMOS and PMOS transistors. The NMOS has a strained channel having first and second stress values along first and second axes respectively. The PMOS has a strained channel having third and fourth stress values along the first and second axes. The first value stress differs from... Agent: Freescale Semiconductor, Inc.

20070262386 - Esd protection element and esd protection device for use in an electrical circuit: An ESD protection element for use in an electrical circuit having a fin structure or a fully depleted silicon-on-insulator structure. The fin structure or the fully depleted silicon-on-insulator structure contains a first connection region having a first conductivity type; a second connection region having a second conductivity type, which is... Agent: Brinks Hofer Gilson & Lione Infineon

20070262387 - Power semiconductor module: A power semiconductor module having an integral circuit board with a metal substrate electrode, an insulation substrate and a heat sink joined is disclosed. A SiC semiconductor power device is joined to a top of the metal substrate electrode of the circuit board. A difference in average coefficients of thermal... Agent: Birch Stewart Kolasch & Birch

20070262388 - Bridge resistance random access memory device and method with a singular contact structure: A resistance random access memory in a bridge structure is disclosed that comprises a contact structure where first and second electrodes are located within the contact structure. The first electrode has a circumferential extending shape, such as an annular shape, surrounding an inner wall of the contact structure. The second... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070262389 - Tri-gate transistors and methods to fabricate same: Embodiments of the invention provide a method for effecting uniform silicon body height for silicon-on-insulator transistor fabrication. For one embodiment, a sacrificial oxide layer is disposed upon a semiconductor substrate. The oxide layer is etched to form a trench. The trench is then filled with a semiconductor material. The semiconductor... Agent: Intel/blakely

20070262390 - Insulated gate semiconductor device: Channel regions and gate electrodes are also disposed continuously with transistor cells below a gate pad electrode. The transistor cells are formed in a stripe pattern and allowed to contact a source electrode. In this way, the channel regions and the gate electrodes, which are positioned below the gate pad... Agent: Morrison & Foerster LLP

20070262391 - Semiconductor device that is advantageous in complex stress engineering and method of manufacturing the same: A semiconductor device according to an embodiment includes an insulated-gate field-effect transistor including a gate insulation film provided on a major surface of a semiconductor substrate, a gate electrode provided on the gate insulation film, and a source and a drain provided spaced apart in the semiconductor substrate such that... Agent: Foley And Lardner LLP Suite 500

20070262392 - Locos on soi and hot semiconductor device and method for manufacturing: One or more local oxidation of silicon (LOCOS) regions may be formed that apply compressive strain to a channel of a field-effect transistor such as a P-type field-effect transistor (PFET) or other circuit element of a semiconductor device. For instance, a pair of LOCOS regions may be formed on opposite... Agent: Banner & Witcoff, Ltd.

20070262393 - Semiconductor devices and methods of forming the same: Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling... Agent: Harness, Dickey & Pierce, P.L.C

20070262394 - Semiconductor device with sti structure: A semiconductor device such as a flash memory includes a semiconductor substrate having a surface, and a plurality of trenches formed in the substrate so as to be open at the surface of the substrate, the trenches having opening widths different from each other. The trench with a smaller opening... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070262395 - Memory cell access devices and methods of making the same: Planar access transistor devices and recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are electrically isolated from each other and supplied with two or more voltage supplies, or materials that create a diode junction within the gate electrode.... Agent: Trask Britt, P.C./ Micron Technology

20070262397 - Nanoscale fet: A transistor device is formed of a continuous linear nanostructure having a source region, a drain region and a channel region between the source and drain regions. The source (20) and drain (26) regions are formed of nanowire ania the channel region (24) is in the form of a nanotube.... Agent: Nxp, B.v. Nxp Intellectual Property Department

20070262396 - Transistors having v-shape source/drain metal contacts: A semiconductor structure and a method for forming the same. The semiconductor structure includes (a) a semiconductor layer, (b) a gate dielectric region, and (c) a gate electrode region. The gate electrode region is electrically insulated from the semiconductor layer. The semiconductor layer comprises a channel region, a first and... Agent: Schmeiser, Olsen & Watts

20070262398 - High voltage semiconductor device with lateral series capacitive structure: According to the present invention, semiconductor device breakdown voltage can be increased by embedding field shaping regions within a drift region of the semiconductor device. A controllable current path extends between two device terminals on the top surface of a planar substrate, and the controllable current path includes the drift... Agent: Lumen Intellectual Property Services, Inc.

20070262399 - Sealing spacer to reduce or eliminate lateral oxidation of a high-k gate dielectric: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced or eliminated oxide layer beneath the high-k gate dielectric layer. A spacer adjacent a gate stack may act as an oxygen barrier to prevent the oxide from forming.... Agent: Intel Corporation C/o Intellevate, LLC

20070262400 - Mems device using an actuator: A MEMS includes a first fixed end, a second fixed end, a first electrode, and an actuator element. The first electrode interposes between the first fixed end and the second fixed end. The first electrode is movable by the actuator element. A shape from the first electrode to the first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070262401 - Semiconductor device embedded with pressure sensor and manufacturing method thereof: The method for promoting the size reduction, the performance improvement and the reliability improvement of a semiconductor device embedded with pressure sensor is provided. In a semiconductor device embedded with pressure sensor, a part of an uppermost wiring is used as a lower electrode of a pressure detecting unit. A... Agent: Stanley P. Fisher Reed Smith LLP

20070262402 - Integrated inductor with higher moment magnetic via: Embodiments of the invention provide an inductor integrated on a microelectronic die. The inductor may include upper and lower layers of magnetic material above and below an electrically conductive coil. There may be a magnetic via between the upper and lower layers of magnetic material. The magnetic via may comprise... Agent: Intel Corporation C/o Intellevate, LLC

20070262403 - Semiconductor device and method for manufacturing the same: An object of the prevent invention is to provide a semiconductor device having a conductive film, which sufficiently serves as an antenna, and a method for manufacturing thereof. The semiconductor device has an element formation layer including a transistor, which is provided over a substrate, an insulating film provided on... Agent: Eric Robinson

20070262404 - Direct electron detector: An electron detector (30) for detection of electrons comprises a semiconductor wafer (11) having a central portion (12) with a thickness of at most 150 μm, preferably at most 100 μm, formed by etching an area of a thicker wafer. On opposite sides of the central portion (12) there are... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070262406 - Method of manufacturing semiconductor device and semiconductor device: A method of manufacturing a semiconductor device, the semiconductor device comprising: a semiconductor substrate; a pixel portion including an in-layer lens; and a peripheral circuit portion including a metal wiring portion, the pixel portion and the peripheral circuit portion being on the semiconductor substrate, the method comprising: forming an insulating... Agent: Birch Stewart Kolasch & Birch

20070262407 - Optically blocked reference pixels for focal plane arrays: Methods for making optically blind reference pixels and systems employing the same. The reference pixels may be configured to be identical to, or substantially identical to, the active detector elements of a focal plane array assembly. The reference pixels may be configured to use the same relatively longer thermal isolation... Agent: William W. Enders O'keefe, Egan, Peterman & Enders, LLP

20070262405 - Photo detector and optically interconnected lsi: A photo detector having an electrically conductive thin film and a light-receiving unit. A coupling periodic structure is provided on a surface of the film and converts incidence light to surface plasmon. The coupling periodic structure has an opening that penetrates the obverse and reverse surfaces of the thin film.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070262408 - Thermistor device: A thermistor device having a high-speed response to temperature and a large ON/OFF ratio at the operating temperature. The thermistor device comprises a first layer of a first material having a positive temperature coefficient of resistance and a second layer of a second material having a semiconductivity and formed directly... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20070262409 - Lead frame and semiconductor device using the same: A lead frame includes: a die pad for holding a semiconductor chip; a radiator plate extending outward from one side face of the die pad and another side face thereof opposite the one side; a plurality of inner leads arranged opposite respective sides of the die pad other than the... Agent: Mcdermott Will & Emery LLP

20070262410 - Semiconductor device and method for manufacturing: A semiconductor device includes: a semiconductor layer of a first conductivity type, a plurality of trenches provided on a major surface side of the semiconductor layer, an insulating film provided on an inner wall surface and on top of the trench, a conductive material surrounded by the insulating film and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070262411 - Semiconductor device having a frontside contact and vertical trench isolation and method of fabricating same: There is a method of forming a contact post and surrounding isolation trench in a semiconductor-on-insulator (SOI) substrate. The method comprises etching a contact hole and surrounding isolation trench from an active layer of the substrate to the insulating layer, masking the trench and further etching the contact hole to... Agent: Nxp, B.v. Nxp Intellectual Property Department

20070262412 - Avoiding field oxide gouging in shallow trench isolation (sti) regions: A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI region and extend beyond the boundaries of... Agent: Winstead PC

20070262414 - Semiconductor device and method for cutting electric fuse: A semiconductor device includes an electric fuse formed on a semiconductor substrate and composed of an electric conductor. The electric fuse includes an upper layer interconnect, a via coupled to the upper interconnect and a lower layer interconnect coupled to the via, which are formed in different layers, respectively, in... Agent: Young & Thompson

20070262413 - E-fuse and method for fabricating e-fuses integrating polysilicon resistor masks: An E-fuse and a method for fabricating an E-fuse are provided integrating polysilicon resistor masks. The E-fuse includes a polysilicon layer defining a fuse shape including a cathode, an anode, and a fuse neck connected between the cathode and the anode silicide formation. A silicide formation is formed on the... Agent: Ibm Corporation RochesterIPLaw Dept 917

20070262415 - Recessed antifuse structures and methods of making the same: Antifuses having two or more materials with differing work function values may be fabricated as recessed access devices and spherical recessed access devices for use with integrated circuit devices and semiconductor devices. The use of materials having different work function values in the fabrication of recessed access device antifuses allows... Agent: Trask Britt, P.C./ Micron Technology

20070262417 - Semiconductor device capable of reducing interelectrode leak current and manufacturing method thereof: A semiconductor device has a capacitive structure formed by sequentially layering, on a wiring or conductive plug, a lower electrode, a capacitive insulation film, and an upper electrode. The semiconductor device has, as the capacitive structure, a thin-film capacitor having a lower electrode structure composed of an amorphous or microcrystalline... Agent: Sughrue Mion, PLLC

20070262416 - Method and structure for creation of a metal insulator metal capacitor: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator... Agent: International Business Machines Corporation Dept. 18g

20070262418 - Integrated passive devices: The specification describes an integrated passive device (IPD) that is formed on a polysilicon substrate. A method for making the IPD is disclosed wherein the polysilicon substrate is produced starting with a single crystal handle wafer, depositing a thick substrate layer of polysilicon on one or both sides of the... Agent: Law Office Of Peter V.d. Wilde

20070262419 - Semiconductor device: A semiconductor device including a multiplicity of large current power elements with each power element divided into a multiplicity of divisional elements and arranged such that the power elements belonging to different power elements are arranged in a repetitive sequential order. The IC chip of the semiconductor device is formed... Agent: Hogan & Hartson L.L.P.

20070262420 - Manufacturing method for semiconductor chips, and semiconductor chip: By performing plasma etching on the second surface of a semiconductor wafer on the first surface of which an insulating film is placed in dividing regions and on the second surface of which a mask for defining the dividing regions are placed, the second surface being located opposite from the... Agent: Wenderoth, Lind & Ponack L.L.P.

20070262421 - Thermoset polyimides for microelectronic applications: Dendrimer/hyperbranched materials are combined with polyimide to form a low CTE material for use as a dielectric substrate layer or an underfill. In the alternative, ruthenium carbene complexes are used to catalyze ROMP cross-linking reactions in polyimides to produce a class of cross-linkable, thermal and mechanical stable material for use... Agent: Stephen M. De Klerk Blakely, Sokoloff, Taylor & Zafman LLP

20070262422 - Shielding device: One aspect of the invention relates to a shielding device for shielding from electromagnetic radiation, including a shielding base element, a shielding cover element and a shielding lateral element for electrically connecting the base element to the cover element in such that a circuit part to be shielded is arranged... Agent: Dicke, Billig & Czaja

20070262423 - Integrated circuit encapsulation system with vent: An integrated circuit encapsulation system with vent is provided including providing a sheet material, forming a leadframe array on the sheet material, forming a leadframe air vent on the leadframe array, attaching an integrated circuit to the leadframe array, mounting the leadframe array in a mold and encapsulating the integrated... Agent: Ishimaru & Zahrt LLP

20070262424 - Methods for forming through-wafer interconnects and devices and systems having at least one dam structure: A method for forming through-wafer interconnects (TWI) in a substrate. Blind holes are formed from a surface, sidewalls thereof passivated and coated with a conductive material. A vent hole is then formed from the opposite surface to intersect the blind hole. The blind hole is solder filled, followed by back... Agent: Trask Britt, P.C./ Micron Technology

20070262425 - Tape carrier, semiconductor apparatus, and semiconductor module apparatus: A tape carrier of the present invention includes an insulating tape and a wiring pattern formed on the insulating tape. The wiring pattern includes a connecting section via which the wiring pattern is connected to a bump electrode. The connecting section is provided at a part of an overlap part... Agent: Harness, Dickey & Pierce, P.L.C

20070262426 - Semiconductor housings having coupling coatings: A semiconductor housing having a coupling coating is disclosed. In one embodiment, the semiconductor housing includes a leadframe for equipping with a semiconductor chip and for enveloping with a polymer material, to which a polymer layer has been applied. The polymer layer has end groups which possess particularly good adhesion... Agent: Steven E Dicke Dicke Billig & Czaja

20070262427 - Semiconductor device: A semiconductor device includes a semiconductor element; a board where the semiconductor element is mounted; a heat radiation member thermally connected to the semiconductor element and fixed to the board; and a plurality of outside connection terminals provided on a surface opposite to a surface where the heat radiation member... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070262430 - Electric component, method of producing the same, substrate with built-in electric component, and method of producing the same: An electric component includes a substrate having a first surface and a second surface opposite to the first surface; a first conductive layer formed on the first surface; a second conductive layer formed on the second surface; an electrode formed on the first conductive layer; a resin portion formed on... Agent: Takeuchi & Kubotera, LLP

20070262431 - Semiconductor device: The first semiconductor chip and the second semiconductor chip which did the stack are mounted on the module substrate concerned deflecting a centre position mutually between module substrates to right and left. In the side where the distance from the edge of the deflected semiconductor chip to the edge of... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070262432 - Semiconductor device comprising semiconductor device components embedded in plastic housing composition: The invention relates to a semiconductor device comprising semiconductor device components embedded in plastic housing composition. The semiconductor device components partly contain copper or have copper-containing coatings and/or coating structures. The copper-containing regions of the semiconductor device components have an adhesion promoting layer with copper(II)oxide whiskers on the surfaces that... Agent: Dicke, Billig & Czaja

20070262428 - Indented structure for encapsulated devices and method of manufacture: A method for providing improved gettering in a vacuum encapsulated device is described The method includes forming a plurality of small indentation features in a device cavity formed in a lid wafer. The gettering material is then deposited over the indentation features. The indentation features increase the surface area of... Agent: Jaquelin K. Spong

20070262429 - Perimeter stacking system and method: A stacked module employs flexible circuitry to connect CSP integrated circuits. A flexible circuit with obverse and reverse sides is disposed between two CSPs oriented face-to-face with the flex circuit between to form a precursor assembly. One or more flaps or extension parts of the flex circuitry extend from the... Agent: Fish & Richardson P.C.

20070262433 - Semiconductor component with surface mountable devices and method for producing the same: A semiconductor component including: a substrate, at least one semiconductor chip arranged on the substrate and at least one passive device likewise arranged on the substrate. The passive device is mounted with its underside on the substrate. The semiconductor component further includes an interspace disposed between the underside of the... Agent: Edell, Shapiro & Finnan, LLC

20070262434 - Interconnected ic packages with vertical smt pads: An electronic component is disclosed including a plurality of semiconductor packages soldered together in a side-by-side configuration. The packages are batch processed on a substrate panel. The panel includes a plurality of through-holes drilled through the panel and subsequently filled with metal such as copper or gold. These filled through-holes... Agent: Vierra Magen/sandisk Corporation

20070262437 - Semiconductor device with temperature cycle life improved: The semiconductor device of the invention has a motherboard 3, a lower package 2 mounted on the motherboard 3, and an upper package 1 mounted on the lower package 2 via intermediate terminals 11. Edge portions, in a marginal area of the lower package 2, with which the intermediate terminals... Agent: Paul J. Esatto, Jr. Scully, Scott, Murphy & Presser

20070262436 - Microelectronic devices and methods for manufacturing microelectronic devices: Microelectronic devices and methods for manufacturing microelectronic devices are described herein. An embodiment of one such method includes attaching a plurality of singulated microelectronic dies to a removable support member with an active side of the individual dies facing toward the support member, depositing a flowable material onto the dies... Agent: Perkins Coie LLP Patent-sea

20070262435 - Three-dimensional packaging scheme for package types utilizing a sacrificial metal base: An apparatus and a method for packaging semiconductor devices. The apparatus is applicable to many types of contemporary packaging schemes that utilize a sacrificial metal base strip. Tunnels formed through an encapsulation area surrounding the device and associated bond wires are filled with a metallic conductor by, for example, electroplating,... Agent: Schneck & Schneck

20070262438 - System and method of silicon switched power delivery using a package: In one particular embodiment, an integrated circuit includes a package and a substrate electrically and physically coupled to the package. The package includes a first pin, a second pin, and metallization coupling the first pin to the second pin. The substrate is coupled to the package via the first pin... Agent: Qualcomm Incorporated

20070262439 - Cob type ic package to enhanced bondibility of bumps embedded in substrate and method for fabricating the same: An IC package to enhance the bondibility of embedded bumps, primarily includes a substrate having a plurality of bump-accommodating holes, a bumped chip, an encapsulant, and a plurality of external terminals. The substrate further has a plurality of inner pads at one ends of the bump-accommodating holes respectively. The inner... Agent: Troxell Law Office PLLC

20070262440 - Sealing structure and method of manufacturing the sealing structure: A sealing structure having a sealing space provided by bonding a substrate and an intermediate member with a first bonding part and by bonding the intermediate member and a cap with a second bonding part. The intermediate member has a higher thermal conductivity than the substrate and the cap.... Agent: Scully, Scott, Murphy & Presser

20070262442 - Packaged electronic component: A packaged electronic component includes a body, a plurality of magnetic elements and a silicon material, wherein the magnetic elements are disposed in the body, and the silicon material covers the surfaces of the magnetic elements. At least one side of the body has a hole to dissipate heat, and... Agent: Birch Stewart Kolasch & Birch

20070262443 - Electronic device with integrated heat distributor: The present invention relates to an electronic device incorporating a heat distributor. It applies more particularly to devices of the plastic package type, with one or more levels of components. According to the invention, the electronic device, for example of the package type, is provided for its external connection with... Agent: Lowe Hauptman & Berner, LLP

20070262441 - Heat sink structure for embedded chips and method for fabricating the same: A heat sink structure for embedding chips and a method for fabricating the same are proposed. An external metal layer is formed on the surface of a chip with pads and a wafer backside heat conductive layer is formed on the inactive surface of the chip. At least one chip... Agent: Sawyer Law Group LLP

20070262444 - Semiconductor device and chip structure thereof: A semiconductor device, a chip structure thereof, and a method for fabricating the same are proposed. The method involves cutting a wafer with an array of chips twice so as to separate the chips and to form a chip structure. The first cutting is wider than the second cutting, and... Agent: Edwards Angell Palmer & Dodge LLP

20070262445 - Stack mcp and manufacturing method thereof: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070262446 - Stacked bump structure and manufacturing method thereof: A method for manufacturing a stacked bump structure including the following steps is provided. First, a substrate having multiple bonding pads disposed on a surface thereof is provided. Next, a first bump and a second bump are respectively formed on any two adjacent bonding pads of the substrate. Then, a... Agent: Jianq Chyun Intellectual Property Office

20070262447 - Circuit board, method for manufacturing the same, and semiconductor device: A circuit board 1 having a base material 10 and an electrode 11 formed on at least one main surface of the base material 10 includes an easy peeling portion 12 formed in at least one of an inner portion and a side portion of the electrode 11, with the... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070262448 - Semiconductor device, power supply apparatus using same, and electronic device: A semiconductor device capable of suppressing diffusion of noise signals is provided. The semiconductor device has a BGA (Ball Grid Array) structure in which a plurality of electrode terminals to do input and/or output of signals from and to the outside is arranged in a matrix form. The semiconductor device... Agent: Cantor Colburn, LLP

20070262449 - Coating method and solutions for enhanced electromigration resistance: a first solution containing an aryl diazonium salt and successively a second solution containing a compound bearing at least one functional group and bearing at least one functional group capable of reacting with the aryl radical grafted on the surface of the composite material thanks to the aryl diazonium salt;... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20070262452 - Electronic component built-in substrate and method of manufacturing the same: In an electronic component built-in substrate of the present invention, an electronic component is mounted on a mounted body having a first wiring layer, the electronic component is embedded in an insulating layer, a conductive ball is arranged to pass through the insulating layer and connected electrically to the first... Agent: Kratz, Quintos & Hanson, LLP

20070262453 - Semiconductor device including triple-stacked structures having the same structure: In a semiconductor device, a plurality of triple-stacked structures all having the same structure are provided. Each of the triple-stacked structures includes one lower electrode layer, at least one upper electrode layer and one dielectric layer sandwiched by the lower electrode layer and the upper electrode layer.... Agent: Mcginn Intellectual Property Law Group, PLLC

20070262450 - Electric fuses using cnts (carbon nanotubes): A fuse structure and a method for operating the same. The fuse structure operating method includes providing a structure. The structure includes (a) an electrically conductive layer and (b) N electrically conductive regions hanging over without touching the electrically conductive layer. N is a positive integer and N is greater... Agent: Schmeiser, Olsen & Watts

20070262451 - Recessed workfunction metal in cmos transistor gates: A transistor gate comprises a substrate having a pair of spacers disposed on a surface, a high-k dielectric conformally deposited on the substrate between the spacers, a recessed workfunction metal conformally deposited on the high-k dielectric and along a portion of the spacer sidewalls, a second workfunction metal conformally deposited... Agent: Intel Corporation C/o Intellevate, LLC

20070262454 - Semiconductor device and wiring auxiliary pattern generating method: An area with a low via pattern density is extracted from a semiconductor integrated circuit that includes the first wirings and the second wirings disposed on the upper layer of the first wirings, based on wiring layout information. Then, dummy via patterns connected either to the first wirings or the... Agent: Mcdermott Will & Emery LLP

20070262455 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070262456 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070262457 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070262458 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070262459 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070262460 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070262462 - Manufacturing method of resin-molding type semiconductor device, and wiring board therefor: A wiring board used for manufacturing a resin-molding type semiconductor device includes a plurality of element regions each having a mount region on which a semiconductor element is mounted and an electrode wire, and a peripheral region surrounding the plurality of element regions and having engagement parts such as through... Agent: Steptoe & Johnson LLP

20070262461 - Semiconductor device and method of producing the same: A semiconductor device includes a substrate; a wiring formed on the substrate; a base portion disposed at an end portion of the wiring; and an electrode formed on the base portion. The base portion has a size smaller than that of the electrode, so that the base portion is not... Agent: Takeuchi & Kubotera, LLP

20070262464 - Method of forming vias in semiconductor substrates and resulting structures: Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from the active surface through a conductive element thereon and a portion of the substrate underlying the conductive element. The through via... Agent: Trask Britt, P.C./ Micron Technology

20070262463 - Semiconductor substrate-based interconnection assembly for semiconductor device bearing external elements: The present invention relates to a method of forming interconnections for a temporary package, wherein the interconnections are capable of receiving solder balls on a die, partial wafer or wafer under test for testing and burn-in. The interconnections are formed in recesses sized and shaped to receive and contain approximately... Agent: Trask Britt, P.C./ Micron Technology

20070262466 - Semiconductor device: A semiconductor device of the present invention includes a first semiconductor chip, a second semiconductor chip, and an adhesive layer, sandwiched between the first and second semiconductor chips, which adheres to the first semiconductor chip 2, the first and second semiconductor chips being laminated so that part of the second... Agent: Nixon & Vanderhye, PC

20070262465 - Semiconductor device and method of fabricating the same: An MCM-type semiconductor device allowing high-speed operation and reduction in power consumption, and is also capable of preventing reliability and yield rate of MCM from degrading. The reduction in power consumption and increase in operation speed are attained by connecting signal lines between in-chip circuits (30), (32) in an electrically... Agent: Rader Fishman & Grauer PLLC

20070262468 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a first semiconductor chip having a first pad, a bonding member having a second pad facing the first pad, and a refractory metal layer which is formed by electroless plating in direct contact with the first pad and the second pad.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070262467 - Semiconductor device having a chip stack on a rewiring plate: A semiconductor device having a semiconductor chip stack on a rewiring plate is disclosed. In one embodiment, the device includes an external contact area having a plurality of external contact area regions which are physically separate from one another is arranged on the underside. The individual external contact area regions... Agent: Dicke, Billig & Czaja

20070262469 - Method for fabricating semiconductor package with multi-layer die contact and external contact: A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package also includes an array of external contacts formed as multi layered metal bumps that include a base layer, a bump layer, and a non-oxidizing... Agent: Stephen A. Gratton

20070262470 - Module with built-in semiconductor and method for manufacturing the module: The present invention provides a module with a built-in semiconductor that can suppress a reduction in yield caused by a crack or failure of a semiconductor device in the process of mounting a thin semiconductor device on a wiring board and a method for manufacturing the module. In the module... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070262471 - Plated antenna for high frequency devices: A method of making a double-sided antenna for high frequency devices is discussed. The method includes forming metal patterns on both sides of a substrate having pre-formed connection holes. Preferably, the metal patterns are formed using a printing ink having a precursor and a solvent. In one embodiment, the metal... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070262473 - Integrated circuit package system with contoured encapsulation: An integrated circuit package system is provided including providing a carrier, mounting an integrated circuit die on the carrier, connecting the integrated circuit die with the carrier, and forming an encapsulation having a multi-sloped side over the integrated circuit die for reducing ejection stress.... Agent: Ishimaru & Zahrt LLP

20070262472 - High withstand voltage semiconductor device covered with resin and manufacturing method therefor: A high withstand voltage semiconductor chip mounted on a package or a board is covered with a sealing resin, and the resin is cured while a high voltage is applied between at least one of electrode terminals connected from a chip electrode or the chip via wiring of wires or... Agent: Nixon & Vanderhye, PC

20070262474 - Semiconductor device and method of manufacturing same: A semiconductor device is provided which is capable of suppressing decreased yields and increased costs, maintaining excellent optical characteristics, reducing secular changes in characteristics to ensure high erliability. After implanting a dopant into a polycrystalline silicon film and activating the implanted dopant and forming a source region, drain region, and... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20070262475 - Polysilicon hard mask for enhanced alignment signal: A method is provided for forming a polysilicon layer on a substrate and aligning an exposure system with an alignment feature of the substrate through the polysilicon layer. In such method, a polysilicon layer is deposited over the substrate having the alignment feature such that the polysilicon layer reaches a... Agent: International Business Machines Corporation Dept. 18g

20070262476 - Method for providing sti structures with high coupling ratio in integrated circuit manufacturing: A process for manufacturing an integrated circuit using shallow trench isolation (STI) includes a 2-step nitride removal process which, when combined with a nitride pull-back step provides, in a floating gate memory integrated circuit, a high coupling ratio and a reduction in thinning of the tunnel oxide layer in a... Agent: Macpherson Kwok Chen & Heid LLP

20070257247 - Information reproducing system using information storage medium: According to one embodiment, there is provided an information reproducing method. The method includes, from an information storage medium storing stream data having a plurality of advanced packs each including a resource file and an advanced ID to identify the resource file, acquiring respective advanced IDs, identifying respective resource files... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070257252 - Circuit structure with a double-gate organic thin film transistor device and application thereof: This invention provides a circuit structure with a double-gate organic thin film transistor device and application thereof. A protection layer covered on an organic thin film transistor structure having a bottom gate is used as another gate insulating layer. A metal layer is formed on this gate insulating layer to... Agent: Venable LLP Raymond J. Ho

20070257254 - Organic light emitting display device: An organic light-emitting display device, includes a substrate, a thin film transistor on the substrate, a passivation layer on the thin film transistor, an organic light-emitting diode on the passivation layer and electrically connected to the thin film transistor, a photo sensor between the substrate and the organic light-emitting diode,... Agent: Lee & Morse, P.C.

20070257256 - Photosensing thin film transistor: A thin film transistor (TFT) photosensitive to illumination with light, which may enhance the transistor's characteristics and the controlling parameters of the transistor state. The transistor comprises an insulating substrate; a source electrode; a drain electrode; a semiconductor layer of a first semiconductor material, which forms a channel of the... Agent: Oliff & Berridge, PLC

20070257255 - Thin film solar cells by selenization sulfurization using diethyl selenium as a selenium precursor: A method of forming a CIGSS absorber layer includes the steps of providing a metal precursor, and selenizing the metal precursor using diethyl selenium to form a selenized metal precursor layer (CIGSS absorber layer). A high efficiency solar cell includes a CIGSS absorber layer formed by a process including selenizing... Agent: Akerman Senterfitt

20070257258 - Semiconductor evaluation device and evaluation method using the same: A semiconductor evaluation device evaluates an amount of mask misalignment in an optical exposure step during the fabrication of a semiconductor device. The semiconductor evaluation device has a first semiconductor region selectively formed in a semiconductor substrate, a first gate electrode having a cross-shaped plan configuration, formed on the first... Agent: Mcdermott Will & Emery LLP

20070257261 - Method for forming metal wiring, method for manufacturing active matrix substrate, device, electro-optical device, and electronic appratus: A device includes a substrate; a bank provided on the substrate; and a metal wiring in a wiring forming region of the substrate that is sectioned by the bank with a liquid phase method. The metal wiring includes a first film formed along a bottom of the wiring forming region... Agent: Harness, Dickey & Pierce, P.L.C

20070257260 - Multi-channel thin film transistor structure: A multi-channel thin film transistor structure including a first conducting layer, an insulating layer, a semiconductor layer and a second conducting layer is provided. The first conducting layer formed on a substrate includes a gate electrode. The insulating layer covers the first conducting layer. The semiconductor layer formed on the... Agent: Lowe Hauptman Ham & Berner, LLP

20070257263 - Display device: A display device includes a first substrate; a first electrode and a second electrode placed on the first substrate; a second substrate separately placed from and facing with the first substrate; a third electrode placed on the second substrate; a first layer placed between the first and second substrates, being... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070257246 - Electric device with nanowires comprising a phase change material: The method according to the invention is directed to manufacturing an electric device (100) according to the invention, having a body (102) with a resistor comprising a phase change material being changeable between a first phase and a second phase, the resistor having a first electrical resistance when the phase... Agent: Philips Intellectual Property & Standards

20070257248 - Semiconductor device and electronic appliance using the same: An object is to provide a photoelectric conversion device capable of detecting a wider range of illuminance without expansion of a range of an output voltage or output current. The photoelectric conversion device has a photoelectric conversion device including a photoelectric conversion element and an amplifier circuit electrically connected to... Agent: Eric Robinson

20070257249 - Silicon/silcion germaninum/silicon body device with embedded carbon dopant: A semiconductor structure and method of manufacturing a semiconductor device, and more particularly, an NFET device. The devices includes a stress receiving layer provided over a stress inducing layer with a material at an interface there between which reduces the occurrence and propagation of misfit dislocations in the structure. The... Agent: Greenblum & Bernstein, P.L.C

20070257251 - Acene compositions and an apparatus having such compositions: An apparatus comprising a substrate and an organic semiconductor matrix being located over the substrate. The organic semiconductor matrix includes one of a polymer co-polymer or a stabilized pentacene. The polymer includes monomers of pentacene or a substituted pentacene. The stabilized pentacene is a substituted pentacene having a lower oxidation... Agent: Hitt Gaines, PC Alcatel-lucent

20070257250 - Organic electroluminescent device and fabrication methods thereof: The invention discloses an organic electroluminescent device comprising a pixel element. The pixel element comprises a substrate comprising a control area and a sensitive area, a switch device and a driving device overlying the control area, a photo diode serving as a photo sensor overlying the sensitive area, an OLED... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070257253 - Organic light emitting display device and method of fabricating the same: An organic light emitting display device and a method of fabricating the same are provided. A trench is formed in a planarization layer, and then a first electrode is formed to have opposite ends in the trench, thereby reducing a height difference between the planarization layer and the first electrode.... Agent: Christie, Parker & Hale, LLP

20070257257 - Nonvolatile memory device including amorphous alloy metal oxide layer and method of manufacturing the same: A nonvolatile memory device may include a lower electrode, an oxide layer including an amorphous alloy metal oxide disposed on the lower electrode, and a diode structure disposed on the oxide layer.... Agent: Harness, Dickey & Pierce, P.L.C

20070257259 - Input display with embedded photo sensor: A readout pixel of an input display is provided. The readout pixel includes the fundamental elements as the normal pixel, and further includes a photo sensing element with a second switching element and a third switching element for generating a photo signal. The second switching element includes a second gate... Agent: Volpe And Koenig, P.C.

20070257262 - Thin film transistor substrate and method for fabricating the same: A stagger type TFT substrate and a fabrication method therefor in which the number of exposure processes is reduced. A resist pattern is formed in an area on the TFT substrate where a drain bus-line (DB) is to be formed and an area on the TFT substrate where a TFT... Agent: Greer, Burns & Crain

20070257264 - Catalyst-free growth of gan nanoscale needles and application in ingan/gan visible leds: Exemplary embodiments provide a scalable process for the growth of large scale and uniform III-N nanoneedle arrays with precise control of the position, cross sectional shape and/or dimensions for each nanoneedle. In an exemplary process, a plurality of nanoneedle array can be formed by growing one or more semiconductor material... Agent: Mh2 Technology Law Group

20070257265 - Use of tungsten interlayer to enhance the initial nucleation and conformality of ultrananocrystalline diamond (uncd) thin films: Extremely smooth (6 nm roughness) and continuous ultrananocrystalline diamond (UNCD) thin films were achieved by microwave plasma chemical vapor deposition using a thin 10 nm tungsten (W) interlayer between the silicon (Si) substrate and the diamond film. The W interlayer significantly increased the initial UNCD nucleation density to >1012 sites/cm2,... Agent: Harry M. Levy, Esq. Emrich & Dithmar

20070257267 - Led extractor composed of high index glass: An LED extractor has an input surface adapted to optically couple to an emitting surface of an LED die, and is composed of a glass (including a glass-ceramic) material whose refractive index is at least 2, or at least 2.2.... Agent: 3m Innovative Properties Company

20070257266 - Led package with converging optical element: The present application discloses a light source comprising an LED die having an emitting surface and an optical element including a base, an apex smaller than the base, and a converging side extending between the base and the apex, wherein the base is optically coupled to and is no greater... Agent: 3m Innovative Properties Company

20070257268 - Semiconductor light emitting device: There is provided a highly reliable semiconductor light emitting device even in using for street lamps or traffic signals, which can be used in place of electric lamps or fluorescent lamps by protecting from surges such as static electricity or the like. A plurality of light emitting units (1) are... Agent: Rabin & Berdo, PC

20070257269 - Light emitting device and method for manufacturing the same: A nitride-based light emitting device capable of achieving an enhancement in emission efficiency and an enhancement in reliability is disclosed. The light emitting device includes a semiconductor layer, and a light extracting layer arranged on the semiconductor layer and made of a material having a refractive index equal to or... Agent: Birch Stewart Kolasch & Birch

20070257271 - Led package with encapsulated converging optical element: The present application discloses a light source comprising an LED die having an emitting surface, a first optical element including a base, an apex, and a converging side joining the base and the apex, wherein the base is optically coupled to the emitting surface and a second optical element encapsulating... Agent: 3m Innovative Properties Company

20070257270 - Led package with wedge-shaped optical element: In one aspect, the present application discloses a light source comprising an LED die having an emitting surface and an optical element having a base, two converging sides, and two diverging sides, wherein the base is optically coupled to the emitting surface. In another aspect, the present application discloses a... Agent: 3m Innovative Properties Company

20070257272 - Multi-element led lamp package: In one embodiment, a single light emitting diode lamp package includes at least two light emitting devices that can be switched independently of one another and thus may be useful in vehicular lighting applications, for example low and high beam headlights. In another embodiment, a LED device includes a first... Agent: Intellectual Property / Technology Law

20070257273 - Novel optical cover for optical chip: A cover for use together with a transmitter of an encoded light or EMR beam for intercepting and re-directing the beam away from the transmitter toward a receiver, an optical device or another solid state device whereby data encoded on the encoded light or EMR beam can be transmitted out... Agent: Davidson Berquist Jackson & Gowdey LLP

20070257274 - Lighting device and method: A lighting device having a light emitting diode (LED). The device includes a metal substrate having a surface. A dielectric coating layer is superimposed on the surface of the metal substrate. A light emitting diode (LED) is supported on the dielectric coating layer. The metal substrate serves as a heat... Agent: Rankin, Hill, Porter & Clark, LLP

20070257275 - Imaging method utilizing thyristor-based pixel elements: An improved imaging array (and corresponding method of operation) includes a plurality of heterojunction thyristor-based pixel elements disposed within resonant cavities formed on a substrate. Each thyristor-based pixel element includes complementary n-type and p-type modulation doped quantum well interfaces that are spaced apart from one another. Incident radiation within a... Agent: Gordon & Jacobson, P.C.

20070257276 - Donor substrate for a flat panel display and method of fabricating an organic light emitting diode (oled) display using the same: A donor substrate for a flat panel display includes a base film, a light-to-heat conversion layer on the base film, a first buffer layer on the light-to-heat conversion layer, the first buffer layer including an emission host material, a transfer layer on the first buffer layer, and a second buffer... Agent: Lee & Morse, P.C.

20070257277 - Semiconductor device and method for manufacturing the same: A semiconductor device having SRAM cell units each comprising a pair of driving transistors, a pair of load transistors and a pair of access transistors, in which each of the transistors has a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the... Agent: Sughrue Mion, PLLC

20070257278 - Low resistance integrated mos structure: The present invention is related to a metal-oxide semiconductor field-effect transistor (MOSFET) having a symmetrical layout such that the resistance between drains and sources is reduced, thereby reducing power dissipation. Drain pads, source pads, and gates are placed on the MOSFET such that the distances between drains, sources, and gates... Agent: Volpe And Koenig, P.C.

20070257279 - Electro-optical device and electronic equipment: An electro-optical device includes: a pair of substrates facing one another across an electro-optical substance layer; and a layered structure formed on one of the substrates, including scanning lines formed in a first direction, data lines formed in a second direction intersecting the first direction, pixel electrodes formed corresponding to... Agent: Sonnenschein Nath & Rosenthal LLP

20070257280 - Complementary metal oxide semiconductor (cmos) image sensor with extended pixel dynamic range incorporating transfer gate with potential well: A charge transfer transistor includes: a first diffusion region and a second diffusion region; a gate for controlling a charge transfer from the first diffusion region to the second diffusion region by a control signal; and a potential well incorporated under the gate, wherein the first diffusion region is a... Agent: Morgan Lewis & Bockius LLP

20070257281 - Solid state image pickup device and manufacturing method therefor: MOS-type solid-state image pickup device includes a photoelectric conversion unit having a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type forming a pn-junction with the first semiconductor region, a third semiconductor region of the first conductivity type disposed at a light... Agent: Fitzpatrick Cella Harper & Scinto

20070257282 - Image sensor applying power voltage to backside of semiconductor substrate and method of manufacturing image sensor: An image sensor applying a power voltage to a backside of a semiconductor substrate includes a first type semiconductor substrate, a first type semiconductor layer formed on the first type semiconductor substrate, a second type semiconductor layer formed on the first type semiconductor layer, and a power voltage receiver formed... Agent: F. Chau & Associates, LLC

20070257283 - Color filter-embedded msm image sensor: An image sensor device includes a semiconductor substrate having a light-sensing region, and a first and second electrode embedded within the substrate. The first and second electrode forms an array of slits, the array of slits is configured to allow a wavelength of light to pass through to the light-sensing... Agent: Haynes And Boone, LLP

20070257284 - An ultra-small cmos image sensor pixel using a photodiode potential technique: An image sensor includes a photosensitive region that accumulates charge corresponding to received incident light; a transfer gate for transferring all or a portion of the charge from the photosensitive region; a voltage supply having an increasing voltage over time that is applied to the transfer gate; a floating diffusion... Agent: Pamela R. Crocker Patent Legal Staff

20070257286 - Cmos image sensor with improved performance incorporating pixels with burst reset operation: A reset transistor includes a floating diffusion region for detecting a charge, a junction region for draining the charge, a gate for controlling a transfer of the charge from the floating diffusion region to the junction region upon receipt of a reset signal, and a potential well incorporated underneath the... Agent: Morgan Lewis & Bockius LLP

20070257285 - Silicon-rich-oxide white light photodiode: A white light photodiode has a film layer and an ultraviolet (UV) photodiode. The film layer is made of an oxide rich in silicon; and is formed through a chemical vapor deposition. A white light can be generated by exciting the film layer with a UV light from the UV... Agent: Troxell Law Office PLLC

20070257288 - Alignment mark for semiconductor device, and semiconductor device: An alignment mark for a semiconductor device is provided. The alignment mark defines a plane pattern and includes a conductive layer embedded in a recessed section provided in an insulation layer, and an oxidation barrier layer provided on the conductive layer, wherein an area occupancy ratio of the recessed section... Agent: Harness, Dickey & Pierce, P.L.C

20070257287 - Assemblies comprising magnetic elements and magnetic barrier or shielding at least partially around the magnetic elements: The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First and second layers are formed over the block, and over a region of the substrate proximate the block. The first and second layers are removed from... Agent: Wells St. John P.s.

20070257289 - Liquid crystal display device and fabricating method thereof: A liquid crystal display device may comprise a semiconductor layer on a substrate and including a channel portion and ohmic contact portions at both sides of the channel portion, wherein an edge portion of the semiconductor layer has a side surface of a substantially tapered shape; a gate insulating layer... Agent: Mckenna Long & Aldridge LLP

20070257291 - Semiconductor memory cell and array using punch-through to program and read same: An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part,... Agent: Neil Steinberg

20070257290 - Memory structure and memory device: A memory structure, a memory device and a manufacturing method thereof are provided. First, a substrate is provided and a dielectric layer is formed over the substrate. Then, a pattern is formed in the dielectric layer. An amorphous silicon layer is formed in the pattern and over the dielectric layer.... Agent: Jianq Chyun Intellectual Property Office

20070257292 - Wireless chip: An ID tag capable of communicating data wirelessly, the size of which is reduced, and where the size of an IC chip is reduced, a limited area of the chip is effectively used, current consumption is reduced, and communication distance is prevented from decreasing. The ID tag of the invention... Agent: Eric Robinson

20070257293 - Semiconductor memory device and method for production of the semiconductor memory device: The semiconductor memory device has a substrate with a main surface, on which parallel trenches are arranged. A memory layer is disposed at the sidewalls of the trenches, and gate electrodes are disposed in the trenches. Buried bitlines are formed as doped regions between neighboring trenches. The buried bitlines abut... Agent: Slater & Matsil LLP

20070257294 - Dram (dynamic random access memory) cells: A DRAM cell with a self-aligned gradient P-well and a method for forming the same. The DRAM cell includes (a) a semiconductor substrate; (b) an electrically conducting region including a first portion, a second portion, and a third portion; (c) a first doped semiconductor region wrapping around the first portion,... Agent: Schmeiser, Olsen & Watts

20070257295 - Semiconductor memory device: Hafnium oxide is not replaced with the other materials, but the dielectric constant of hafnium oxide is improved to increase the capacitance. An element having a large ion radius such as yttrium is added in a small amount to increase the dielectric constant of hafnium while an amorphous state is... Agent: Miles & Stockbridge PC

20070257296 - Semiconductor device and method for manufacturing the same: This disclosure concerns a semiconductor device comprising a convex-shaped semiconductor layer formed on a semiconductor substrate; an insulation film formed on the semiconductor substrate, the insulation film having a film thickness to the extent that a lower part of the semiconductor layer is buried; a gate electrode formed on a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070257298 - Memory cell with reduced size and standby current: A present invention is a method, and resulting device, for fabricating memory cells with an extremely small area and reduced standby current. The small area is accomplished by a judicious use of spacers which allows a tunnel window of a storage device to be fabricated in close proximity to an... Agent: Schneck & Schneck

20070257297 - Memory device having nanocrystals and methods of manufacturing the same: The memory device includes a source region and a drain region in a substrate and spaced apart from each other; a memory cell formed on a surface of the substrate, wherein the memory cell connects the source region and the drain region and includes a plurality of nanocrystals; a control... Agent: Harness, Dickey & Pierce, P.L.C

20070257302 - Semiconductor device having a gate contact structure capable of reducing interfacial resistance and method of forming the same: A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer... Agent: Lee & Morse, P.C.

20070257303 - Transistor and method for forming the same: A deep source/drain region and a source/drain extension region may be formed in a semiconductor substrate adjacent to a gate electrode. A first silicide layer may be formed on the source/drain extension region. A gate spacer may be formed on a sidewall of the gate electrode to cover the first... Agent: Harness, Dickey & Pierce, P.L.C

20070257301 - Multi-gate fet with multi-layer channel: The invention concerns a field-effect transistor with a drain, a source, a channel in electrical contact with the source and the drain, and at least one gate, so as to apply an electric field to the channel when each gate is polarised, where the channel has a multi-layer structure with... Agent: Winston & Strawn LLP Patent Department

20070257299 - Nor flash memory and fabrication process: Semiconductor memory array and process of fabrication in which a plurality of bit line diffusions are formed in a substrate, and memory cells formed in pairs between the bit line diffusions, with each of the pairs of cells having first and second conductors adjacent to the bit line diffusions, floating... Agent: Edward S. Wright

20070257304 - Semiconductor device and method of manufacturing the same: An insulating film provided below a floating gate electrode includes a first insulating film located at both end portions below the floating gate electrode, and a second insulating film sandwiched between the first insulating films and located in a middle portion below the floating gate electrode. The first insulating film... Agent: Mcdermott Will & Emery LLP

20070257300 - Structures and methods of a bistable resistive random access memory: Structures and methods to form a bistable resistive random access memory for reducing the amount of heat dissipation from electrodes by confining a heating region in the memory cell device are described. The heating region is confined in a kernel comprising a programmable resistive memory material that is in contact... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070257305 - Nonvolatile semiconductor memory device and manufacturing method thereof: By decreasing the threshold voltage shift due to the potential change of the cells adjacent in a word line direction, the reliability of a flash memory can be enhanced. Memory cells of a flash memory are formed in p-type wells of a semiconductor substrate and include gate insulator films, floating... Agent: Miles & Stockbridge PC

20070257306 - Semiconductor memory device and method for producing the same: Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a... Agent: Reed Smith LLP

20070257307 - Nand non-volatile two-bit memory and fabrication method: A NAND non-volatile two-bit memory cell comprises a cell stack and two select stacks disposed on an active area of a substrate. Each select stack is respectively disposed on a side of the cell stack with a sidewall between the cell stack and a respective select stack. The cell stack... Agent: Hogan & Hartson L.L.P.

20070257308 - Modifying work function in pmos devices by counter-doping: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the... Agent: Slater & Matsil, L.L.P.

20070257309 - Pmos transistor of semiconductor device, semiconductor device comprising the same, and method for manufacturing the same: A PMOS transistor of a semiconductor device exhibiting improved characteristics, a semiconductor device incorporating the same, and a method for manufacturing the semiconductor device. The PMOS transistor incorporates a first gate insulation film formed in a predetermined region on a semiconductor substrate and comprising a hafnium-based oxide, a second gate... Agent: Marshall, Gerstein & Borun LLP

20070257310 - Body-tied mosfet device with strained active area: A body-tied MOSFET device and method of fabrication are presented. In the method of fabrication, oxygen diffuses and reacts down a first axis of a pFET or nFET. This results in a partial oxidation of a buried-oxide/silicon island interface. The partial oxidation produces a thickness variation in the silicon island... Agent: Honeywell International Inc.

20070257311 - Semiconductor device and method for manufacturing the same: The present invention provides a method for manufacturing massively and efficiently a minute device which can receive or send data in contact, preferably, out of contact by forming an integrated circuit which is formed by a thin film over a large glass substrate and by peeling the integrated circuit from... Agent: Eric Robinson

20070257313 - Semiconductor memory device including an soi substrate: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain... Agent: Mcdermott Will & Emery LLP

20070257312 - Semiconductor-on-insulator (soi) substrates and semiconductor devices using void spaces: An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate,... Agent: Myers Bigel Sibley & Sajovec

20070257314 - Integrated circuit chip with fets having mixed body thicknesses and method of manufacture thereof: An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20070257315 - Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors: This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for... Agent: Robert M. Trepp IBM Corporation

20070257316 - Semiconductor device: A terminating resistance element of an LSI chip has an N− type impurity diffusion region formed at the surface of a P type well at the surface of a semiconductor substrate, an N+ type impurity diffusion layer formed at the surface of the N− type impurity diffusion region, and a... Agent: Mcdermott Will & Emery LLP

20070257317 - Method of forming a body-tie: A method of forming a body-tie. The method includes forming the body-tie during an STI scheme of an SOI process. During the STI scheme, a first trench is formed. The first trench stops before a buried oxide layer of the SOI substrate. The first trench may determine a height of... Agent: Honeywell International Inc.

20070257319 - Integrating high performance and low power multi-gate devices: A semiconductor device comprising a first multi-gate device and a second multi-gate device on a semiconductor substrate. The first multi-gate device comprising a first gate structure and the second multi-gate device comprises a second gate structure. An effective width of the first gate structure is greater than an effective width... Agent: Texas Instruments Incorporated

20070257318 - Method of manufacturing semiconductor integrated circuit device, and semiconductor integrated circuit device manufactured by the method: Provided are a more stable semiconductor integrated circuit device and a method of manufacturing the same. The method includes providing a semiconductor substrate comprising a first transistor region having a stacked structure of a first gate insulating layer and a first gate and a second transistor region having a stacked... Agent: Myers Bigel Sibley & Sajovec

20070257320 - Semiconductor device and manufacturing method thereof: A semiconductor device is provided with a first MISFET including a first gate insulating film including a HfAlO film formed over a semiconductor substrate and a first gate electrode, including a nickel silicide film, formed over the first gate insulating film. An aluminum concentration of the HfAlO film on a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070257321 - Semiconductor structure and fabrication thereof: A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in the substrate beside the spacer, and... Agent: J.c. Patents

20070257322 - Hybrid transistor structure and a method for making the same: A topography (40) is provided which includes a device having a transistor formed from a stack of semiconductor layers (42/46). The different semiconductor layers are spaced apart by a gate (60) and by support structures (48) comprising a material having different etch characteristics than the materials of the spaced apart... Agent: Larson Newman Abel Polansky & White, LLP

20070257323 - Stacked contact structure and method of fabricating the same: A stacked contact structure includes a first contact plug of a first conductive material filling a first contact hole in a first dielectric layer, and a second contact plug of a second conductive material filling a second contact hole in a second dielectric layer. The second conductive material is different... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070257324 - Semiconductor devices having gate structures and contact pads that are lower than the gate structures: Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. Second spacers are disposed on sidewalls of the first spacers and... Agent: Myers Bigel Sibley & Sajovec

20070257325 - Tri-gate device with conformal pvd workfunction metal on its three-dimensional body and fabrication method thereof: A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conformal physical vapor deposition workfunction metal on its three-dimensional... Agent: Intel Corporation C/o Intellevate, LLC

20070257326 - Integrated circuit structure and method of manufacturing a memory cell: An integrated circuit structure is formed on a substrate. The integrated circuit structure includes a logic area and a memory cell area. The memory cell area includes a charge storage area and a non-charge storage area. A dielectric layer is formed on the substrate in the charge storage area. A... Agent: North America Intellectual Property Corporation

20070257327 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment includes providing a workpiece having a first orientation and at least one second orientation. The semiconductor device is implanted with a dopant species using a first implantation process in the first orientation of the workpiece. The semiconductor device... Agent: Slater & Matsil LLP

20070257328 - Detecting plasmons using a metallurgical junction: A sensor device includes a substrate having first and second regions of first and second conductivity types, respectively. A junction having a band-gap is formed between the first and second regions. A plasmon source generates plasmons having fields. At least a portion of the plasmon source is formed near the... Agent: Davidson Berquist Jackson & Gowdey LLP

20070257329 - Photodiode with controlled current leakage: The present invention is directed towards radiation detectors and methods of detecting incident radiation. In particular the present invention is directed towards photodiodes with controlled current leakage detector structures and a method of manufacturing photodiodes with controlled current leakage detector structures. The photodiodes of the present invention are advantageous in... Agent: Patentmetrix

20070257330 - Semiconductor device: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below... Agent: Mcdermott Will & Emery LLP

20070257331 - Anti-fuse memory cell: An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide has a thick gate oxide portion and a thin gate oxide portion, where the thing gate oxide portion has at least one dimension less than a minimum feature size of a process technology. The thin... Agent: Borden Ladner Gervais LLP Anne Kinsman

20070257332 - Bipolar transistor and a method of manufacturing the same: A bipolar transistor having the enhanced characteristics is fabricated by etching a base mesa, which is formed below an emitter mesa (upper emitter layer) and a base electrode, to have jut regions on the edges of its generally rectangular region. A mask film, e.g., insulating film, is formed to cover... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070257333 - Seeded growth process for preparing aluminum nitride single crystals: A method of growing bulk single crystals of an AlN on a single crystal seed is provided, wherein an AlN source material is placed within a crucible chamber in spacial relationship to a seed fused to the cap of the crucible. The crucible is heated in a manner sufficient to... Agent: Alston & Bird LLP

20070257334 - Process for producing a iii-n bulk crystal and a free-standing iii-n substrate, and iii-n bulk crystal and free-standing iii-n substrate: Embodiments of the invention relate to a process for producing a III-N bulk crystal, wherein III denotes at least one element selected from group III of the periodic system, selected from Al, Ga and In, wherein the III-N bulk crystal is grown by vapor phase epitaxy on a substrate, and... Agent: Foley And Lardner LLP Suite 500

20070257335 - Illuminator and manufacturing method: An illuminator (1) is manufactured by embossing an aluminium preform to provide a structured substrate base (21) with cavities (25) for LEDs and recesses (26) for tracks. The substrate is anodised to provide an aluminium oxide insulating layer (30) over the structured surface. A metal layer (35) is then applied... Agent: Jacobson Holman PLLC

20070257336 - Mosfet having a channel region with enhanced stress and method of forming same: A semiconductor device is provided that includes a semiconductor substrate, an n-channel MOSFET formed on the substrate and a p-channel MOSFET formed on the substrate. A first layer is formed to cover the n-channel MOSFET, wherein the first layer has a first flexure-induced stress. A second layer is formed to... Agent: Mayer & Williams PC

20070257337 - Shield substrate, semiconductor package, and semiconductor device: To provide a shield substrate, semiconductor package and semiconductor device which can give improved resistance to thermal stress. The shield substrate according to this invention is provided with a conductive film on which slits each having a shape through which electromagnetic wave noise does not leak are formed. These slits... Agent: Mcdermott Will & Emery LLP

20070257338 - Method of manufacturing a coaxial trace in a surrounding material, coaxial trace formed thereby, and semiconducting material containing same: A method of manufacturing a coaxial trace (100) within a surrounding material (190) includes: providing a first substrate (191, 410) and a second substrate (192, 1010) composed of the surrounding material; forming a first portion (101, 601) of the coaxial trace in the first substrate; forming a second portion (102,... Agent: Intel Corporation C/o Intellevate, LLC

20070257339 - Shield structures: Shield structures are provided. A first and second shield lines are formed over a substrate and coupled with a first voltage. A conductive line is formed between the first and the second shield lines, and coupled with a second voltage. The first shield layer is formed over the substrate and... Agent: Duane Morris LLPIPDepartment (tsmc)

20070257342 - Method of manufacturing photo couplers: A method of manufacturing photo couplers is provided. At first, a receiver lead-frame array is cut from a lead-frame matrix having a transmitter lead-frame array and the receiver lead-frame array. Then, the receiver lead-frame array is overturned and placed on the lead-frame matrix to allow light-receiver elements on the receiver... Agent: Birch Stewart Kolasch & Birch

20070257341 - Structure of a lead-frame matrix of photoelectron devices: A structure of a lead-frame matrix of photoelectron devices is provided. The lead-frame matrix is used to fabricate a first lead-frame array and a second lead-frame array. In the structure of the lead-frame matrix of the photoelectron devices, pins of the first lead-frame array and pins of the second lead-frame... Agent: Birch Stewart Kolasch & Birch

20070257340 - System and method for routing signals between side-by-side die in lead frame type system in a package (sip) devices: An integrated circuit includes a first and a second die positioned on a lead frame of a package. The lead frame includes a plurality of bond fingers. The integrated circuit includes a first bond pad on the first die that is electrically interconnected to a corresponding second bond pad on... Agent: Kathy Manke Avago Technologies Limited

20070257343 - Die-on-leadframe (dol) with high voltage isolation: A high voltage semiconductor module has a leadframe with spaced pads which is connected to a heat sink plate by a curable insulation layer on the top of the plate. Semiconductor die may be soldered to the leadframe pads before or after assembly to the plate. The insulation layer may... Agent: Ostrolenk Faber Gerb & Soffen

20070257344 - Flip chip type led lighting device manufacturing method: A flip chip type LED lighting device manufacturing method includes the step of providing a strip, the step of providing a submount, the step of forming a metal bonding layer on the strip or submount, the step of bonding the submount to the strip, and the step of cutting the... Agent: Rosenberg, Klein & Lee

20070257345 - Package structure to reduce warpage: A package structure includes: a substrate having a chip-bearing area arranged thereon; an window type assistant element arranged on the substrate and surrounding the edge of the chip-bearing area; a plurality of chips arranged within the chip-bearing area; and a package encapsulation covering chips within the chip-bearing area. It can... Agent: Birch Stewart Kolasch & Birch

20070257346 - Semiconductor device and method for manufacturing same: A process yield of a semiconductor device is enhanced. To that end, there is provided a semiconductor device comprising a substrate having a component mount face with semiconductor chips mounted thereon, the substrate being provided with a plurality of connection leads, and a cap made of resin, placed over the... Agent: Miles & Stockbridge PC

20070257347 - Chip structure and fabricating process thereof: A chip structure comprising a substrate, a conductive layer, a plurality of bumps and a trap layer is provided. The substrate has a plurality of pads and the conductive layer is disposed on the pads. The bumps are disposed on the conductive layer above the pads and the trap layer... Agent: Jianq Chyun Intellectual Property Office

20070257349 - Leaded package integrated circuit stacking: There is provided a stacked IC module including first and second leaded packages in stacked disposition, each of the first and second leaded packages having plural leads emergent along at least one side of each of the respective leaded packages, and a flexible circuit disposed in part between the first... Agent: Fish & Richardson P.C.

20070257348 - Multiple chip package module and method of fabricating the same: A multiple chip package module comprises a first substrate, a first chip, an inverted first semiconductor unit, a first encapsulant, and a second semiconductor unit. The first chip is disposed on the first substrate. The inverted first semiconductor unit is stacked over the first chip. The first encapsulant covers the... Agent: Bacon & Thomas, PLLC

20070257350 - Wafer level stack structure for system-in-package and method thereof: A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller... Agent: Harness, Dickey & Pierce, P.L.C

20070257351 - Power module for low thermal resistance and method of fabricating the same: A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a... Agent: Hiscock & Barclay, LLP

20070257353 - Semiconductor chip having a crack test circuit and method of testing a crack of a semiconductor chip using the same: A semiconductor chip includes a line structure arranged along a peripheral region of the semiconductor chip region in order to inspect a crack, a first pad and second pad arranged on different end portions of the line structure, a second pad arranged on another end portion of the line structure,... Agent: Harness, Dickey & Pierce, P.L.C

20070257352 - Test pads on flash memory cards: A semiconductor package is disclosed including test pads formed of solder bumps affixed to the semiconductor package during fabrication. When the package is encapsulated, due to the pressure exerted on the package during the encapsulation process, portions of the solder bumps get flattened out to be generally flush with and... Agent: Vierra Magen/sandisk Corporation

20070257354 - Code installation decisions for improving aggregate functionality: A method and system are described for obtaining a first code role indicator, an association between the first code role indicator and a first code module, and a second code role indicator and circuitry for deciding whether to install a second code module in a first node, responsive to a... Agent: Searete LLC Clarence T. Tegreene

20070257355 - Soldering structure of through hole: In the vicinity of soldering through holes of lands for soldering a lead terminal in a multilayer printed board, electrically isolated lands are provided to form a thermal through hole. In the soldering, by the radiation and supply of heat of a lead-free solder filled in the thermal through hole,... Agent: Morgan Lewis & Bockius LLP

20070257356 - Semiconductor device having multilayer printed wiring board and manufacturing method of the same: A semiconductor device includes a support body, a first substrate provided on a surface at one side of the support body, a second substrate provided on a surface at the other side of the support body, and a semiconductor chip provided on the first substrate exposed to an opening part... Agent: Kratz, Quintos & Hanson, LLP

20070257357 - Forcing gas trapped between two components into cavities: An apparatus includes a first component and a second component. The apparatus includes one or more cavities within one or more of the first and the second components. The apparatus includes one or more channels within one or more of the first and the second components. The channels are fluidically... Agent: Hewlett Packard Company

20070257358 - Heat sink and method for fabricating the same: A heat sink and method for fabricating the same are disclosed. The heat sink includes a lower substrate having a concave portion, a supporting column formed on the concave portion of the lower substrate, and an upper substrate opposed to the lower substrate and tightly fixed to the lower substrate... Agent: Ishimaru & Zahrt LLP

20070257360 - Apparatus and method for precise alignment of packaging caps on a substrate: The specification discloses an apparatus comprising an alignment plate having a plurality of depressions therein, each depression being sized to receive a packaging cap therein and to prevent its movement, and a force applicator to apply a force to press the packaging caps and a substrate firmly together. Also disclosed... Agent: Blakely Sokoloff Taylor & Zafman

20070257359 - Thermal management device for a memory module: A memory module which includes a memory board having two major surfaces, one of the major surfaces with a plurality of chips thereon, wherein at least one of the chips operates at a higher power than at least one other of the chips; and a thermal management system in thermal... Agent: Waddey & Patterson, P.C.

20070257361 - Chip package: A chip package includes a first wiring layer, chips, a second wiring layer, dielectric layers, first conductive vias, and second conductive vias. The first wiring layer has contacts near a side of the first wiring layer. The chips are stacked over the first wiring layer. The second wiring layer is... Agent: Jianq Chyun Intellectual Property Office

20070257363 - Semiconductor device: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer... Agent: Oliff & Berridge, PLC

20070257364 - Methods of reactive composite joining with minimal escape of joining material: The present inventors have observed that in some applications of reactive composite joining there is escape of a portion of the molten joining material through the edges of the joining regions. Such escape is not only a waste of expensive material (e.g. gold or indium) but also a reduction from... Agent: Polster, Lieder, Woodruff & Lucchesi

20070257365 - Packaged semiconductor chip comprising an integrated circuit chip ablated with laser and cut with saw blade from wafer: A packaged semiconductor chip comprising an integrated circuit chip including a low-k dielectric layer and a chip substrate, wherein an edge of the integrated circuit chip has a first edge portion and a second edge portion. At least part of the first edge portion being across a same level as... Agent: Steven H. Slater Slater & Matsil, L.L.P.

20070257362 - Process for forming bumps and solder bump: There is provided a process for forming bumps wherein a plurality of fine bumps are uniformly formed with high productivity. In this process, a resin (13) comprising solder powder and a convection additive (12) is supplied onto a substrate (10) having a plurality of electrodes (11) thereon. And subsequently the... Agent: Wenderoth, Lind & Ponack L.L.P.

20070257366 - Barrier layer for semiconductor interconnect structure: A method for producing a semiconductor-device having an electrical interconnect. The method produces having an improved barrier layer between the interconnect conductor and the dielectric material in which the interconnect recess is formed. A dielectric layer is formed on top of a wafer substrate having at least one contact region.... Agent: Slater & Matsil, L.L.P.

20070257370 - Multilayer electrode structures including capacitor structures having aluminum oxide diffusion barriers and methods of forming the same: A multilayer electrode structure has a conductive layer including aluminum, an oxide layer formed on the conductive layer, and an oxygen diffusion barrier layer. The oxide layer includes zirconium oxide and/or titanium oxide. The oxygen diffusion barrier layer is formed at an interface between the conductive layer and the oxide... Agent: Myers Bigel Sibley & Sajovec

20070257368 - Dielectric spacers for metal interconnects and method to form the same: A plurality of metal interconnects incorporating dielectric spacers and a method to form such dielectric spacers are described. In one embodiment, the dielectric spacers adjacent to neighboring metal interconnects are discontiguous from one another. In another embodiment, the dielectric spacers may provide a region upon which un-landed vias may effectively... Agent: Blakely Sokoloff Taylor & Zafman

20070257367 - Dielectric trenches, nickel/tantalum oxide structures,and chemical mechanical polishing techniques: A portion of a conductive layer (310, 910) provides a capacitor electrode (310.0, 910.0). Dielectric trenches (410, 414, 510) are formed in the conductive layer to insulate the capacitor electrode from those portions of the conductive layer which are used for conductive paths passing through the electrode but insulated from... Agent: Macpherson Kwok Chen & Heid LLP

20070257369 - Reducing resistivity in interconnect structures of integrated circuits: An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening.... Agent: Slater & Matsil, L.L.P.

20070257371 - Semiconductor device having a guard ring: A multilayer interconnection structure of a semiconductor device includes a first guard ring extending continuously along a periphery of a substrate and a second guard ring extending continuously in the multilayer interconnection structure along the periphery so as to be encircled by the first guard ring and so as to... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070257372 - Method for forming ti film and tin film, contact structure, computer readable storing medium and computer program: A cleaning process is performed on the surface of a nickel silicide film serving as an underlayer. Then, a Ti film is formed to have a film thickness of not less than 2 nm but less than 10 nm by CVD using a Ti compound gas. Then, the Ti film... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070257373 - Methods of forming blind wafer interconnects, and related structures and assemblies: Methods for forming blind wafer interconnects (BWIs) from the back side surface of a substrate structure to the underside of a bond pad on the opposing surface includes the formation of a blind hole from the back side surface, forming a passivating layer therein, removing passivation material from the blind... Agent: Trask Britt, P.C./ Micron Technology

20070257374 - Semiconductor chip and semiconductor device: To prevent short-circuit due to contact of bonding wires each other and to make a semiconductor device compact. A semiconductor chip with a rectangular main surface may comprise: a first side composing the main surface; a second side opposed to the first side; a main electrode pad group composed of... Agent: Nixon Peabody, LLP

20070257375 - Increased interconnect density electronic package and method of fabrication: An electronic package. The electronic package includes an electronic component having a heat producing device, an attachment piece, and at least two attachment units. Each unit includes an attachment pillar having a mating surface, a solder layer formed on the mating surface, and an attachment pad located on the attachment... Agent: Kathy Manke Avago Technologies Limited

20070257376 - Semiconductor module: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070257377 - Package structure: A package structure including a first carrier, a second carrier, at least a first electronic component and at least a second electronic component is provided. The second carrier is electrically connected to the first carrier. The first electronic component is disposed on the first carrier and electrically connected to the... Agent: J.c. Patents, Inc.

20070252129 - Semiconductor film and manufacturing method thereof, light receiving element using semiconductor film, electrophotographic photoreceptor, process cartridge, and image forming device: There is provided: a semiconductor film formed on a base material, containing a group 13 element, nitrogen, and oxygen in an amount of about 15 atomic % or more; a manufacturing method thereof; a light receiving element using the semiconductor film; an electrophotographic photoreceptor; a process cartridge; and an image... Agent: Oliff & Berridge, PLC

20070252133 - Light emitting apparatus: A light emitting apparatus includes a substrate, a first metal layer, at least one light emitting device and a protective layer for covering the light emitting device. The first metal layer is disposed on the substrate and includes a structure for increasing the light emitting efficiency. The light emitting device... Agent: Birch Stewart Kolasch & Birch

20070252141 - Organic compound and organic light-emitting element: A fluoranthene compound has 6 fused rings. An organic light-emitting element uses the fluoranthene compound.... Agent: Fitzpatrick Cella Harper & Scinto

20070252142 - Thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor (“TFT”) array panel includes forming a first conductive layer, gate insulating layer, and first insulating layer on a substrate, patterning the first insulating layer to form a first insulating pattern including an opening, etching the gate insulating layer and first conductive layer... Agent: Cantor Colburn, LLP

20070252144 - Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility: By appropriately orienting the channel length direction with respect to the crystallographic characteristics of the silicon layer, the stress-inducing effects of strained silicon/carbon material may be significantly enhanced compared to conventional techniques. In one illustrative embodiment, the channel may be oriented along the <100> direction for a (100) surface orientation,... Agent: Williams, Morgan & Amerson

20070252145 - Image display device and manufacturing method thereof: An image display device of reduced cost is provided. A plurality of gate lines, a plurality of signal lines formed to cross the gate lines in a matrix fashion, and a plurality of thin-film transistors are formed on an insulating substrate, and the plurality of gate lines are laminated electrodes.... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070252148 - Thin film transistor substrate and method for manufacturing same: An exemplary TFT substrate (300) includes a substrate (310), a silicon layer (320), a insulating layer (330, 340), and a metal layer (350), the metal layer, the insulating layer, the silicon layer being formed on the substrate in that order from top to bottom. The insulating layer comprises a first... Agent: Wei Te Chung Foxconn International, Inc.

20070252152 - Electro-optical device, electronic apparatus, and method of manufacturing electro-optical device: An electro-optical device includes a thin-film transistor in each of a plurality of pixel regions on an element substrate, the thin film transistor including a gate electrode, a gate insulating layer disposed above the gate electrode, and a semiconductor layer disposed above the gate insulating layer, a pixel electrode that... Agent: Oliff & Berridge, PLC

20070252156 - Composite semiconductor device, led head that employs the composite semiconductor device, and image forming apparatus that employs the led head: A composite semiconductor device includes a semiconductor thin film, a substrate, connection pads, and a light blocking layer. The semiconductor thin film includes light emitting elements. The driver circuits are formed on the substrate and the semiconductor thin film is fixed on the substrate, the driver circuit driving the light... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070252157 - Light emitting apparatus: A light emitting apparatus includes a substrate, a first metal layer, an insulating layer and at least one light emitting device. The first metal layer is disposed on the substrate. The insulating layer is disposed on the first metal layer. The light emitting device is disposed on the insulating layer.... Agent: Birch Stewart Kolasch & Birch

20070252159 - Light emitting apparatus: A light emitting apparatus includes a substrate, an insulating layer and at least one light emitting device. The insulating layer is disposed over the substrate and has a patterned area exposing at least a portion of the substrate. The light emitting device is disposed over the substrate and is located... Agent: Birch Stewart Kolasch & Birch

20070252158 - Semiconductor light-emitting device and method of manufacturing the same: A semiconductor light-emitting device has a first conductivity type semiconductor layer, a luminous layer formed on the first conductivity type semiconductor layer, a second conductivity type semiconductor layer formed on the luminous layer, and a transmissive semiconductor layer formed on the second conductivity type semiconductor layer. The transmissive semiconductor layer... Agent: Morrison & Foerster LLP

20070252160 - Light emitting device and method of driving the same: The present invention relates to a light emitting device for preventing a cross-talk phenomenon and a pectinated pattern. The light emitting device includes data lines, scan lines, pixels and a discharging circuit. The data lines are disposed in a first direction, and the scan lines are disposed in a second... Agent: Ked & Associates, LLP

20070252166 - Light emitting apparatus: A light emitting apparatus includes a substrate, at least one light emitting device and a protective layer. The substrate has a surface formed with a structure for increasing light emitting efficiency. The light emitting device is disposed on a predetermined position of the substrate. The light emitting device emits lights... Agent: Birch Stewart Kolasch & Birch

20070252167 - Surface mounting optoelectronic device: A surface mounting optoelectronic device is provided. The surface mounting optoelectronic device comprises a circuit board, a conductive layer, an auto-focus LED chip, a flash LED chip, a reflector and an encapsulant. The auto-focus LED chip and the flash LED chip are located on the conductive layer. The reflector is... Agent: Birch Stewart Kolasch & Birch

20070252126 - Driver and drive method for organic bistable electrical device and organic led display: An electroluminescent device based on bistability, and method for its use. The device alternates between a low resistance state and a high resistance state by application of an electrical voltage. A bistable electrical device has two electrodes sandwiching an organic material that produces bistable action. An organic light emitting diode... Agent: Rabin & Berdo, PC

20070252127 - Phase change memory element with a peripheral connection to a thin film electrode and method of manufacture thereof: A PCM cell structure comprises a first electrode, a phase change element, and a second electrode, wherein the phase change element is inserted in between the first electrode and the second electrode and only the peripheral edge of one of the first and second electrodes contacts the phase change element... Agent: Graham S. Jones, Ii

20070252128 - Switching device and methods for controlling electron tunneling therein: A switching device includes at least one bottom electrode and at least one top electrode. The top electrode crosses the bottom electrode at a non-zero angle, thereby forming a junction. A metal oxide layer is established on at least one of the bottom electrode or the top electrode. A molecular... Agent: Hewlett Packard Company

20070252131 - Method of interconnect formation using focused beams: A method of forming an electrical interconnect, which includes a first electrode, an interlayer of a programmable material disposed over at least a portion of the first electrode, and a second electrode disposed over the programmable material at a non-zero angle relative to the first electrode. The interlayer includes a... Agent: Hewlett Packard Company

20070252130 - Transistor with tunneling dust electrode: A transistor-like electronic device operates somewhat as a triode vacuum tube. Two electrodes (source and drain) sandwich an intermediate layer of organic semiconductor material in which fine metallic particles are dispersed. Due to the fineness and number of the particles, they are close enough to each other that electrons can... Agent: Rabin & Berdo, PC

20070252132 - Nanowire devices and systems, light-emitting nanowires, and methods of precisely positioning nanoparticles: A radiation-emitting device includes a nanowire that is structurally and electrically coupled to a first electrode and a second electrode. The nanowire includes a double-heterostructure semiconductor device configured to emit electromagnetic radiation when a voltage is applied between the electrodes. A device includes a nanowire having an active longitudinal segment... Agent: Hewlett Packard Company

20070252134 - Detector with tunable spectral response: A semiconductor detector has a tunable spectral response. These detectors may be used with processing techniques that permit the creation of “synthetic” sensors that have spectral responses that are beyond the spectral responses attainable by the underlying detectors. For example, the processing techniques may permit continuous and independent tuning of... Agent: Mh2 Technology Law Group

20070252135 - Nitride semiconductor light emitting device and fabrication method thereof: A nitride semiconductor light-emitting device according to the present invention comprises a first nitride semiconductor layer; an active layer formed on the first nitride semiconductor layer; a second nitride semiconductor layer formed on the active layer; and a third nitride semiconductor layer having AlIn, which is formed on the second... Agent: Birch Stewart Kolasch & Birch

20070252136 - Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors and fabricating such devices: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest... Agent: Wolf Greenfield & Sacks, P.C.

20070252140 - Heterocyclic radical or diradical, the dimers, oligomers, polymers, dispiro compounds and polycycles thereof, the use thereof, organic semiconductive material and electronic or optoelectronic component: The present invention relates to heterocyclic radicals or diradicals, the dimers, oligomers, polymers, dispiro compounds and polycycles thereof, to the use thereof to organic semiconductive materials and to electronic and optoelectronic components.... Agent: Sutherland Asbill & Brennan LLP

20070252137 - Non-volatile ferroelectric thin film device using an organic ambipolar semiconductor and method for processing such a device: A non-volatile ferroelectric memory device is proposed which comprises a combination of an organic ferroelectric polymer with an organic ambipolar semiconductor. The devices of the present invention are compatible with—and fully exploit the benefits of polymers, i.e. solution processing, low-cost, low temperature layer deposition and compatibility with flexible substrates.... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070252138 - Polyacenes and electronic devices generated therefrom: wherein R is a suitable hydrocarbon, a halogen, or a heteroatom containing group; each R′ and R″ are independently a suitable hydrocarbon, a heteroatom containing group, or a halogen; x and y each represent the number of groups; a and b each independently represent the number of groups; and n... Agent: Fay Sharpe / Xerox - Rochester

20070252139 - Polymers for use in organic electroluminescent devices: A polymer comprising an optionally substituted first repeal unit off formula (1): wherein F is a divalent residue; each Gin each occurrence is independently a divalent residue; r is at least 1; each p is independently 0 or 1 and each corresponding q is the other of 0 or 1:... Agent: Connolly Bove Lodge & Hutz, LLP

20070252143 - Semiconductor memory element and lifetime operation starting apparatus therefor: An example memory includes an address control portion, a protection film, a property deterioration material layer, data storage areas, and bonding pads. The protection film protects an organic semiconductor layer of a semiconductor circuit and prevents intrusion of moisture or chemical molecules in the air, light, or the like, into... Agent: Nixon & Vanderhye, PC

20070252146 - Liquid crystal display and defect repairing method for same: The present invention provides a liquid crystal display having a plurality of gate lines, a plurality of source lines, a plurality of pixel electrodes provided in a matrix form, first TFTs having a first gate electrode connected to a gate line, a first source electrode connected to a source line... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070252149 - Semiconductor device and method for forming the same: A semiconductor device and a method for forming the same are disclosed. The semiconductor device comprising an insulated gate field effect transistor provided with a region having added thereto an element at least one selected from the group consisting of carbon, nitrogen, and oxygen, said region having established at either... Agent: Eric Robinson

20070252147 - Semiconductor device and method of manufacturing the same: s

20070252150 - Light emitting device: A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line.... Agent: Fish & Richardson P.C.

20070252151 - Polysilicon thin film transistor device and method of fabricating the same: A polysilicon thin film transistor device includes a gate metal pattern including a gate electrode and a gate line formed on a substrate, the gate metal pattern having a stepped portion, a gate insulating film formed on the gate metal pattern, a polysilicon semiconductor layer formed on the gate insulating... Agent: Morgan Lewis & Bockius LLP

20070252153 - Semiconductor device: In a conventional analog buffer circuit composed of polycrystalline semiconductor TFTs, a variation in the output is large. Thus, a measure such as to provide a correction circuit has been taken. However, there has been such a problem that a circuit and driver operation are complicated. Therefore, a gate length... Agent: Nixon Peabody, LLP

20070252154 - Semiconductor chip manufacturing method, semiconductor chip, semiconductor thin film chip, electron tube and photo-detecting device: The present invention relates to a semiconductor chip manufacturing method in which a semiconductor thin film can be cut in a relatively short time and the cut surface can be relatively smoothly formed. When an Si substrate having a diamond thin film formed on the surface thereof is cut in... Agent: Drinker Biddle & Reath (dc)

20070252155 - Composite electrode for light-emitting device: A multi-layer composite electrode for a light-emitting device, comprising: a transparent, conductive layer; a reflective, conductive layer in electrical contact with the transparent, conductive layer; and a light-scattering layer formed between the transparent, conductive layer and the reflective, conductive layer over only a first portion of the transparent, conductive layer,... Agent: Paul A. Leipold Patent Legal Staff

20070252161 - Led mounting structures: An LED assembly may include a substrate, an elongate mounting structure that is formed in or on the substrate, and an LED that is mechanically secured to the elongate mounting structure. A light producing apparatus may include a substrate, an elongate mounting structure that may be formed in or on... Agent: 3m Innovative Properties Company

20070252162 - Light-emitting device and manufacturing method thereof: To provide a light-emitting device using a nitride semiconductor which can attain high-power light emission by highly efficient light emission and a manufacturing method thereof, the light-emitting device includes a GaN substrate and a light-emitting layer including an InAlGaN quaternary alloy on a side of a first main surface of... Agent: Fasse Patent Attorneys, P.A.

20070252163 - Led light source with better color mixing: A light source that has improved light mixing. The light source uses a nanolens layer in conjunction with an LED light source to enhance the mixing of the colored light emitting from the LED light source.... Agent: Kathy Manke Avago Technologies Limited

20070252165 - Light emitting device having vertical structure and method for manufacturing the same: A light emitting device having a vertical structure, which includes a semiconductor layer having a first surface and a second surface, a first electrode arranged on the first surface of the semiconductor layer, a transparent conductive oxide (TCO) layer arranged on the second surface of the semiconductor layer and a... Agent: Birch Stewart Kolasch & Birch

20070252164 - Method for growth of semipolar (al,in,ga,b)n optoelectronic devices: A method of fabricating an optoelectronic device, comprising growing an active layer of the device on an oblique surface of a suitable material, wherein the oblique surface comprises a facetted surface. The present invention also discloses a method of fabricating the facetted surfaces. One fabrication process comprises growing an epitaxial... Agent: Gates & Cooper LLP Howard Hughes Center

20070252168 - Semiconductor device and manufacturing method thereof: An electrostatic discharge protection element and a protection resistor, which are formed on an N-drain region with a field oxide film interposed therebetween for the purpose of preventing electrical breakdown of a field effect transistor, are composed as a stacked bidirectional Zener diode of one or a plurality of N+... Agent: Foley And Lardner LLP Suite 500

20070252169 - Electric circuit device, electric circuit module, and power converter: The above object can be attained by constructing multiple plate-like conductors so that each of these conductors electrically connected to multiple semiconductor chips is also thermally connected to both chip surfaces of each such semiconductor chip to release heat from the chip surfaces of each semiconductor chip, and so that... Agent: Crowell & Moring LLP Intellectual Property Group

20070252170 - Electrostatic discharge protection device for optical drive: An electrostatic discharge protection device for an optical drive is a circuit on a printed circuit board, which is disposed between a tray and a panel of the optical drive and attached to a front end surface of the tray. The panel has a button, an indicator hole and an... Agent: Bacon & Thomas, PLLC

20070252171 - Semiconductor device and manufacturing method thereof: As semiconductor regions in contact with a first main surface of a semiconductor base composed by forming an N− silicon carbide epitaxial layer on an N+ silicon carbide substrate connected to a cathode electrode, there are provided both of an N+ polycrystalline silicon layer of a same conduction type as... Agent: Foley And Lardner LLP Suite 500

20070252172 - Semiconductor device: A semiconductor device, includes: 1) a semiconductor base having a first face; 2) a hetero semiconductor region configured to contact the first face of the semiconductor base and different from the semiconductor base in band gap, the semiconductor base and the hetero semiconductor region defining therebetween a junction part in... Agent: Foley And Lardner LLP Suite 500

20070252173 - Semiconductor device and manufacturing method thereof: A semiconductor device is provided with: a semiconductor substrate of a predetermined electroconduction type; a hetero semiconductor region contacted with a first main surface of the semiconductor substrate and comprising a semiconductor material having a bandgap different from that of the semiconductor substrate; a gate electrode formed through a gate... Agent: Foley And Lardner LLP Suite 500

20070252174 - Method of manufacturing semiconductor device and semiconductor device: After a polycrystalline silicon as a hetero-semiconductor region forming a heterojunction with a semiconductor base is formed on an epitaxial layer configuring the semiconductor base, the unevenness on the surface of the polycrystalline silicon is planarized before a gate insulating film is formed. Alternatively, as the hetero-semiconductor region, amorphous or... Agent: Foley And Lardner LLP Suite 500

20070252176 - Field effect transistor for detecting ionic material and method of detecting ionic material using the same: A field effect transistor for detecting ionic material and a method of detecting ionic material using the field effect transistor. The field effect transistor for detecting ionic material includes a substrate formed of a semiconductor material, a source region and a drain region spaced apart from each other in the... Agent: Cantor Colburn, LLP

20070252175 - Floating body transistor constructions, semiconductor constructions, and methods of forming semiconductor constructions: The invention includes floating body transistor constructions containing U-shaped semiconductor material slices. The U-shapes have a pair of prongs joined to a central portion. Each of the prongs contains a source/drain region of a pair of gatedly-coupled source/drain regions, and the floating bodies of the transistors are within the central... Agent: Wells St. John P.s.

20070252177 - Silicon integrated circuit operating at microwave frequencies and fabrication process: The invention relates to integrated circuits for microwave applications in the millimeter wavelength range (frequencies of around 50 GHz). To improve the performance of the microwave transmission lines in the circuit, a structure of conducting vias between a transmission line and a conducting zone is proposed. The vias are formed... Agent: Lowe Hauptman & Berner, LLP

20070252178 - Semiconductor device: The junction FET includes: an n+ SiC substrate 10 as a drain layer; an n− SiC layer 11 contiguous to the drain layer as a drift layer; an n+ SiC layer 12 formed on the drift layer as a source layer; trench grooves formed ranging from the source layer to... Agent: Miles & Stockbridge PC

20070252179 - Semiconductor device and method for manufacturing the same: A manufacturing method of a semiconductor device of the present invention includes the steps of forming a stacked body in which a semiconductor film, a gate insulating film, and a first conductive film are sequentially stacked over a substrate; selectively removing the stacked body to form a plurality of island-shaped... Agent: Eric Robinson

20070252181 - Semiconductor device, method for manufacturing semiconductor device, and electronic appliance having the semiconductor device: In order to connect a semiconductor device including an integrated circuit to an external circuit typified by an antenna, the shape of the contact electrode to be formed in the semiconductor device is devised, so that bad connection between the external circuit and the contact electrode is not easily caused... Agent: Eric Robinson

20070252180 - Semiconductor element, semiconductor device, and method for manufacturing the same: A semiconductor element includes: a semiconductor region formed in a semiconductor substrate and containing an impurity of a predetermined conductivity type; source and drain regions formed to face each other in the semiconductor region, and containing a metal or a compound of a metal and a semiconductor forming the semiconductor... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070252182 - Buried-gated photodiode device and method for configuring and operating same: A 3-T buried-gated photodiode device that is suitable for use in a windowed array. The 3-T buried-gated photodiode device is configured such that the floating diffusion (FD) node of the device is held low when the device is not being specifically addressed, which ensures that the device cannot drive the... Agent: Ratnerprestia

20070252183 - Ccd type solid-state imaging device and method for manufacturing the same: A CCD type solid-state imaging device is provided and includes: photodiodes (PD) in a light receiving area of a semiconductor substrate; vertical charge transfer paths; a horizontal charge transfer path; channel stops including linear high density impurity regions for separating mutually adjoining sets from each other, each set including a... Agent: Birch Stewart Kolasch & Birch

20070252184 - Imaging device and manufacturing method thereof: Disclosed is an imaging device including a photodiode and floating diffusion region formed to be spaced from each other on a surface layer of a pixel region of a silicon (semiconductor) substrate, and a transfer gate having one of a concave and convex portions toward the floating diffusion region, the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070252185 - Integrated circuit and manufacturing method thereof: An integrated circuit and a manufacturing method thereof are provided. A chip size can be reduced by forming a memory device in which a ferroelectric capacitor region is laminated on a DRAM. The integrated circuit includes a cell array region having a capacitor, a peripheral circuit region, and a ferroelectric... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070252186 - Mtj read head with sidewall spacers: Following CMP, a magnetic tunnel junction stack may protrude through the oxide that surrounds it, making it susceptible to possible shorting to its sidewalls. The present invention overcomes this problem by depositing silicon nitride spacers on these sidewalls prior to oxide deposition and CMP. So, even though the stack may... Agent: Saile Ackerman LLC

20070252187 - Top electrode barrier for on-chip die de-coupling capacitor and method of making same: An improvement in the method of fabricating on chip decoupling capacitors which help prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. The inclusion of a hybrid metal/metal nitride top electrode/barrier provides for a low cost and higher performance option to strapping decoupling... Agent: Intel/blakely

20070252188 - Semiconductor device and manufacturing method of same: A semiconductor device in which a channel region of MOS transistor is provided not to include a non-flat active region end portion and a manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor device comprising a semiconductor substrate, a device isolation separating active region, wherein... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070252189 - Flash memory cell and method for manufacturing the same: An active region and a trench region are formed on a semiconductor substrate. The trench region is filled with a dielectric material to form an isolation layer. Oxide and polysilicon layers are formed on the semiconductor substrate. A second polysilicon layer, a second oxide layer, and a first polysilicon layer... Agent: Mckenna Long & Aldridge LLP

20070252193 - Non-volatile memory devices including variable resistance material: A non-volatile memory device comprises a first oxide layer, a second oxide layer and a buffer layer formed on a lower electrode. An upper electrode is formed on the buffer layer. In one example, the lower electrode is composed of at least one of Pt, Ru, Ir, IrOx and an... Agent: Harness, Dickey & Pierce, P.L.C

20070252191 - Method of manufacturing a semiconductor device: In a method of manufacturing a semiconductor device, an isolation pattern is formed on a substrate. The isolation pattern includes an opening that exposes a portion of the substrate. A preliminary polysilicon layer is formed on the substrate and the isolation pattern to partially fill up the opening. A sacrificial... Agent: Marger Johnson & Mccollom, P.C.

20070252190 - Nonvolatile memory device and method for manufacturing the same: Provided are a nonvolatile memory device and a method for manufacturing the same. The nonvolatile memory device may include a semiconductor substrate, a floating gate, a second insulation layer, a third insulation layer, a control gate, and a common source line. The semiconductor substrate may have an active region limited... Agent: Harness, Dickey & Pierce, P.L.C

20070252192 - Pillar cell flash memory technology: An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon floating gate layer (819), ONO or oxide layer (822), polysilicon... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20070252194 - Memory device and fabrication method thereof: A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive... Agent: Harness, Dickey & Pierce, P.L.C

20070252195 - Vertical and trench type insulated gate mos semiconductor device: A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively... Agent: Rossi, Kimms & Mcdowell LLP.

20070252196 - Vertical channel transistors and memory devices including vertical channel transistors: A semiconductor device is provided which includes an NMOS vertical channel transistor located on a substrate and including a p+ polysilicon gate electrode surrounding a vertical p-channel region, and a PMOS vertical channel transistor located on the substrate and including an n+ polysilicon gate electrode surrounding a vertical n-channel region.... Agent: Volentine & Whitt PLLC

20070252198 - Semiconductor device having a fin channel transistor: The semiconductor device includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof. The semiconductor device additionally has a fin channel region protruded over the device isolation structure in a longitudinal direction of a... Agent: Townsend And Townsend And Crew, LLP

20070252199 - Semiconductor device having a recess channel transistor: The semiconductor device having a recess channel transistor includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof and a recess channel region formed in the semiconductor substrate under the active region. A method... Agent: Heller Ehrman LLP

20070252200 - High voltage transistor and method for fabricating the same: A high voltage transistor operating through a high voltage and a method for fabricating the same are provided. The high voltage transistor includes: an insulation layer on a substrate; an N+-type drain junction region on the insulation layer; an N−-type drain junction region on the N+-type drain junction region; a... Agent: Blakely Sokoloff Taylor & Zafman

20070252197 - Polysilicon control etch-back indicator: This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining... Agent: Bo-in Lin

20070252201 - Nonvolatile semiconductor memory device and manufacturing method thereof: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070252202 - Sliding-tilt unit and mobile device using the same: A mobile device including a first body and a second body slidably and tiltably coupled. The second body can be arranged to a first location, at which the second body overlaps the first body, and a second location, at which the second body is tilted with respect to the first... Agent: Stein, Mcewen & Bui, LLP

20070252203 - Structure and method for manufacturing mosfet with super-steep retrograded island: The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure... Agent: Scully, Scott, Murphy & Presser, P.C.

20070252208 - Semiconductor device and position detecting method using the semiconductor device: An object of the present invention is to solve a problem of a conventional semiconductor device in that although information such as whether the semiconductor device exists in a predetermined space and information on an ID and the like included in the semiconductor device can be obtained, a position where... Agent: Eric Robinson

20070252209 - Semiconductor device, and manufacturing method of semiconductor device: In order to form a plurality of semiconductor elements over an insulating surface, in one continuous semiconductor layer, an element region serving as a semiconductor element and an element isolation region having a function to electrically isolate element regions from each other by repetition of PN junctions. The element isolation... Agent: Eric Robinson

20070252205 - Soi transistor having a reduced body potential and a method of forming the same: By introducing a atomic species, such as carbon, fluorine and the like, into the drain and source regions, as well as in the body region, the junction leakage of SOI transistors may be significantly increased, thereby providing an enhanced leakage path for accumulated minority charge carriers. Consequently, fluctuations of the... Agent: Williams, Morgan & Amerson

20070252204 - Soi transistor having an embedded strain layer and a reduced floating body effect and a method for forming the same: By forming a portion of a PN junction within strained silicon/germanium material in SOI transistors with a floating body architecture, the junction leakage may be significantly increased, thereby reducing floating body effects. The positioning of a portion of the PN junction within the strained silicon/germanium material may be accomplished on... Agent: Williams, Morgan & Amerson

20070252207 - Thin film transistor and method of fabricating the same: A thin film transistor (TFT) and a method of fabricating the TFT may be provided. The TFT may include a substrate; a channel formed on the substrate; source and drain layers formed on both ends of the channel; a gate insulator covering the source and drain layers and the channel;... Agent: Harness, Dickey & Pierce, P.L.C

20070252210 - Semiconductor element, semiconductor device and methods for manufacturing thereof: The present invention provides a method of manufacturing a semiconductor element having a miniaturized structure and a semiconductor device in which the semiconductor element having a miniaturized structure is integrated highly, by overcoming reduction of the yield caused by alignment accuracy, accuracy of a processing technique by reduced projection exposure,... Agent: Nixon Peabody, LLP

20070252206 - Semiconductor thin film and method of manufacturing the same and semiconductor device and method of manufacturing the same: A thin film semiconductor transistor structure has a substrate with a dielectric surface, and an active layer made of a semiconductor thin film exhibiting a crystallinity as equivalent to the single-crystalline. To fabricate the transistor, the semiconductor thin film is formed on the substrate, which film includes a mixture of... Agent: Fish & Richardson P.C.

20070252211 - Semiconductor device and manufacturing method for semiconductor device: A semiconductor device that has a pMOS double-gate structure, has a substrate, the crystal orientation of the top surface of which is (100), a semiconductor layer that is made of silicon or germanium, formed on the substrate such that currents flow in a direction of a first <110> crystal orientation,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070252212 - Improved cmos diodes with dual gate conductors, and methods for forming the same: The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of... Agent: Scully Scott Murphy & Presser, PC

20070252213 - Semiconductor device: In a semiconductor device, where, with respect to a parasitic resistor in a current mirror circuit, a compensation resistor for compensating the parasitic resistor is provided in the current mirror circuit, the current mirror circuit includes at least two thin film transistors. The thin film transistors each have an island-shaped... Agent: Eric Robinson

20070252217 - Semiconductor device: A semiconductor device comprises a decoupling capacitance in which a P-type MOS capacitor C1 is connected in series with an N-type MOS capacitor C2 between VDD and GND. The source and drain 2b of the P-type MOS capacitor C1 are connected to VDD. The source and drain 2a of the... Agent: Sughrue Mion, PLLC

20070252214 - Cmos structures and methods using self-aligned dual stressed layers: A CMOS structure and methods for fabricating the CMOS structure provide that a first stressed layer located over a first transistor and a second stressed layer located over a second transistor abut but do not overlap. Such an abutment absent overlap provides for enhanced manufacturing flexibility when forming a contact... Agent: Scully Scott Murphy & Presser, PC

20070252215 - Hybrid orientation soi substrates, and method for forming the same: The present invention relates to a hybrid orientation semiconductor-on-insulator (SOI) substrate structure that contains a base semiconductor substrate with one or more first device regions and one or more second device regions located over the base semiconductor substrate. The one or more first device regions include an insulator layer with... Agent: Scully Scott Murphy & Presser, PC

20070252218 - Semiconductor device: A semiconductor device is provided herein, which includes a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The semiconductor device further includes a first stress layer and a second stress layer. The first stress layer is disposed on... Agent: Jianq Chyun Intellectual Property Office

20070252216 - Semiconductor device and a method of manufacturing such a semiconductor device: A semiconductor device, specifically a Complementary Metal Oxide Semiconductor (CMOS) device, has a substrate on which are formed first and second field effect transistors. Each of the field effect transistors comprises a source-drain region, a channel of either an n-type or a p-type conductivity semiconductor material formed on the substrate,... Agent: Morrison & Foerster LLP

20070252219 - Memory cell array with low resistance common source and high current drivability: In the present resistive memory array, included are a substrate, a plurality of source regions in the substrate, and a conductor connecting the plurality of source regions, the conductor being positioned adjacent to the substrate to form, with the plurality of source regions, a common source. In one embodiment, the... Agent: Paul J. Winters

20070252220 - Integrated circuit with metal silicide regions: A method for forming a metal silicide region in a silicon region of a semiconductor substrate. The method comprises forming a metal layer over the silicon region, then in succession forming a titanium and a titanium nitride layer thereover. As the substrate is heated to form the silicide, the titanium... Agent: Agere Lerner, David Et Al.

20070252222 - Method for manufacturig a semiconductor device including a shallow trench isolation: A method of manufacturing a semiconductor device having a semiconductor substrate that includes an active region for forming transistor elements, which includes a gate, and an element isolation region for isolating the transistor elements separately each other, which has a STI structure, the method comprises; first—ion implanting first ions onto... Agent: Harness, Dickey & Pierce, P.L.C

20070252221 - Semiconductor device and method for fabricating the same: The semiconductor device comprises gate electrodes 50 formed on a silicon substrate 32 with a gate insulation film 48 formed therebetween, source/drain diffused layers 66n, 66p formed in the silicon substrate 32 on both sides of the gate electrodes 50, a skirt-like insulation film 58 formed on a lower part... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070252223 - Insulated gate devices and method of making same: Structures and devices, and methods of making such structures and devices, including a gate dielectric layer are provided. A semiconductor structure can include a semiconductor channel layer including a nitride-free semiconductor layer and a gate dielectric layer including a group III-nitride layer, wherein the gate dielectric layer is disposed over... Agent: Wolf Greenfield & Sacks, P.C.

20070252224 - Integrated chemical microreactor with large area channels and manufacturing process thereof: The microreactor has a body of semiconductor material; a large area buried channel extending in the body and having walls; a coating layer of insulating material coating the walls of the channel; a diaphragm extending on top of the body and upwardly closing the channel. The diaphragm is formed by... Agent: Tamsen Valoir, Ph.d. Baker & Mckenzie LLP

20070252226 - Image display device: An image display device includes a vacuum structure having a first substrate, a second substrate placed at the front side of the first substrate to form a first region together with the first substrate, and a reinforcing panel placed at the rear of the first substrate to form a second... Agent: Christie, Parker & Hale, LLP

20070252225 - Image sensor and manufacturing method thereof: An image sensor includes: a light source that irradiates a light on an object; a lens body that converges a reflection of the light from the object; a plurality of IC chips that receive the reflection passed through the lens body; and a transparent member provided between the IC chips... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070252227 - Optical apparatus and optical module using the same: An optical apparatus includes an optical device (LED device or semiconductor imaging device) having a photoreceptor/light-emitting region, a peripheral circuit region and an electrode region, a transparent member having a larger light passing through region than the optical device and including, on one surface thereof, protruding electrodes for connection to... Agent: Mcdermott Will & Emery LLP

20070252228 - Integrated circuit structure and manufacturing method thereof: An integrated circuit structure is described, and includes a substrate, a contact window, and a Schottky contact metal layer. A heavily doped region and a lightly doped region are formed in the substrate. The contact window is disposed above the heavily doped region, and the Schottky contact metal layer is... Agent: J.c. Patents, Inc.

20070252229 - Field effect transistor and manufacturing method thereof: A manufacturing method of a field effect transistor in which, a patterned gate electrode is provided on a substrate, and a gate insulator is provided on the substrate and the gate electrode, a source electrode and a drain electrode are spaced apart from each other on the gate insulator, a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070252230 - Cmos structures and methods for improving yield: A simple, effective and economical method to improved the yield of CMOS devices using contact etching stopper liner, including, single neutral stressed liner, single stressed liner and dual stress liner (DSL), technology is provided. In order to improve the chip yield, the present invention provides a method in which a... Agent: Scully, Scott, Murphy & Presser, P.C.

20070252231 - Semiconductor integrated circuit and system lsi including the same: A semiconductor integrated circuit having a diode element includes a diffusion layer which constitutes the anode and two diffusion layers which are provided on the left and right sides of the anode and which constitute the cathode, such that the anode and the cathode constitute the diode. A well contact... Agent: Mcdermott Will & Emery LLP

20070252232 - Semiconductor device and method for manufacturing the same: It is made possible to provide a semiconductor device and a method for manufacturing the semiconductor device that have the highest possible permittivity and can be produced at low production costs. A method for manufacturing a semiconductor device, includes: forming an amorphous film containing (HfzZr1-z)xSi1-xO2-y (0.81≦x≦0.99, 0.04≦y≦0.25, 0≦z≦1) on a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070252233 - Semiconductor device and method for manufacturing the semiconductor device: A semiconductor device is provided, which comprises a semiconductor layer over an insulating surface, and an insulating layer over the semiconductor layer. The semiconductor layer includes at least two element regions, and an element separation region. The element separation region is disposed between the two element regions. The element separation... Agent: Eric Robinson

20070252234 - Semiconductor device and method for manufacturing the same: To provide a highly reliable semiconductor device and a method for manufacturing the semiconductor device, where defects such as a short between a gate electrode layer and a semiconductor layer and a leakage current, which would otherwise be caused due to a coverage defect of the semiconductor layer with an... Agent: Eric Robinson

20070252235 - Semiconductor device having a circular-arc profile on a silicon surface: A semiconductor device includes a shallow isolation trench (STI) structure on a silicon substrate for isolating element-forming regions from one another. The surface region of the silicon substrate in the element-forming regions, as viewed in the extending direction of the gate electrode lines, once falls and thereafter rises monotonically from... Agent: Mcginn Intellectual Property Law Group, PLLC

20070252236 - Semiconductor device having isolation region and method of manufacturing the same: A trench isolation region is formed in a surface region of a semiconductor substrate to form a MOS type element region. A mask layer having an opening portion is formed on the semiconductor layer, the opening portion continuously ranging on the entire surface of the MOS type element region and... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070252238 - Tungstein plug as fuse for ic device: The present invention provides a fuse circuit in a dielectric layer for trimming an Integrated Circuit. The fuse circuit has a first conductive layer, a second conductive layer and a third conductive layer. A first metal plug is coupled between the first conductive layer and the second conductive layer. At... Agent: Murabito, Hao & Barnes, LLP

20070252237 - Devices and methods for constructing electrically programmable integrated fuses for low power applications: Electrically programmable integrated fuses are provided for low power applications. Integrated fuse devices have stacked structures with a polysilicon layer and a conductive layer formed on the polysilicon layer. The integrated fuses have structural features that enable the fuses to be reliably and efficiently programmed using low programming currents/voltages, while... Agent: F. Chau & Associates, LLC

20070252240 - Implanted counted dopant ions: This invention concerns semiconductor devices of the general type comprising a counted number of dopant atoms (142) implanted in regions of a substrate (158) that are substantially intrinsic semiconductor. One or more doped surface regions (152) of the substrate (158) are metallised to form electrodes (150) and a counted number... Agent: Wood, Phillips, Katz, Clark & Mortimer

20070252239 - Silicon semiconductor substrate heat-treatment method and silicon semiconductor substrate treated by the method: A method is provided capable of universally controlling the proximity gettering structure, the need for which can vary from manufacturer to manufacturer, by arbitrarily controlling an M-shaped distribution in a depth direction of a wafer BMD density after RTA in a nitrogen-containing atmosphere. The heat-treatment method is provided for forming... Agent: Fish & Richardson PC

20070252241 - Low-capacitance contact for long gate-length devices with small contacted pitch: Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070252242 - Semiconductor device: An uppermost one of multilayered electrode pads, on which a bump and a plating coat will be formed, is made of metal having high ionization tendency, particularly, Al. On the other hand, an uppermost one of multilayered electrode pads, on which none of the bump and the plating coat will... Agent: Steptoe & Johnson LLP

20070252243 - Semiconductor device and manufacturing method thereof: As a substrate for a semiconductor device, a metal substrate is used, and the metal substrate is composed of a metal base body made of a first metal and a connecting metal layer made of a second metal for covering the metal base body. The substrate has a structure wherein... Agent: Foley And Lardner LLP Suite 500

20070252244 - Methods of forming material over substrates: The invention includes ALD-type methods in which two or more different precursors are utilized with one or more reactants to form a material. In particular aspects, the precursors are hafnium and aluminum, the only reactant is ozone, and the material is hafnium oxide predominantly in a tetragonal crystalline phase.... Agent: Wells St. John P.s.

20070252247 - Leadframe structures for semiconductor packages: A semiconductor package includes a lead structure upon which a semiconductor die is mounted with at least some portion of at least some of the leads extending to, at, or across an axis or axis of the package to militate against thermally induced growth of the package and the reduce... Agent: Wallace G. Walter

20070252249 - Circuit apparatus and method of fabricating the apparatus: The likelihood of exfoliation of a sealing resin layer at a pad electrode part is reduced so that the reliability of a circuit apparatus is improved. A circuit apparatus includes a wiring layer, a gold plating layer, an insulating resin layer, a circuit element, a conductive member and sealing resin... Agent: Fish & Richardson P.C.

20070252246 - Light emitting diode package with direct leadframe heat dissipation: A packaged circuit and method for packaging an integrated circuit are disclosed. The packaged circuit has a lead frame, an integrated circuit chip, and an encapsulating layer. The lead frame has first and second sections, the first section including a lateral portion, a chip mounting area and a first extension.... Agent: Kathy Manke Avago Technologies Limited

20070252248 - Packaging of intergrated circuits to lead frames: A lead frame (200) for housing an integrated circuit is disclosed comprising a main member (220) and an engagement portion (230) for receiving an integrated circuit (210). The integrated circuit (210) is located at the engagement portion (230) and engaged with the lead frame through resilient engagement with the first... Agent: Slater & Matsil LLP

20070252245 - System and method for providing a power bus in a wirebond leadframe package: An integrated circuit (IC) package, such as a Quad Flat Pack (QFP), has at least one lead with a tip that extends substantially perpendicular to the ends of two or more bondwires, so that there is room for more than one bondwire to be attached to it along its length.... Agent: Kathy Manke Avago Technologies Limited

20070252250 - Apparatus and method for use in mounting electronic elements: Some embodiments provide surface mount devices that include a first electrode comprising a chip carrier part, a second electrode disposed proximate to the chip carrier part, and a casing encasing a portion of the first and second electrodes. The first electrode can extend from the chip carrier part toward a... Agent: Sinsheimer Juhnke Lebens & Mcivor, LLP

20070252251 - Flip chip mounted semiconductor device package having a dimpled leadframe: A wafer level bumpless method of making flip chip mounted semiconductor device packages is disclosed. The method includes the steps of solder mask coating a semiconductor die wafer frontside, processing the solder mask coating to reveal a plurality of gate contact and a plurality of source contacts, patterning a lead... Agent: Fortune Law Group LLP

20070252255 - Multi-component package with both top and bottom side connection pads for three-dimensional packaging: An apparatus and a method for packaging semiconductor devices. The apparatus is a three-dimensional electronic package comprising one or more electronic components, a plurality of electrical contact pads, and a plurality of electrically conductive three-dimensional plugs formed through an encapsulant. Specific ones of the plurality of electrical contact pads are... Agent: Schneck & Schneck

20070252258 - Semiconductor device and semiconductor device layout designing method: In each wiring layer in which wirings connected to a gate is formed, wirings are routed so as not to cover the active region of an antenna protection element. A wiring formed in an upper wiring layer is routed so as to cover at least a part of the active... Agent: Mcdermott Will & Emery LLP

20070252257 - Semiconductor package structures having heat dissipative element directly connected to internal circuit and methods of fabricating the same: In one embodiment, a semiconductor package structure includes a heat dissipative element connected to an internal circuit. The semiconductor package includes a semiconductor chip, an interconnection substrate, and a heat dissipative element. The semiconductor chip includes an internal circuit and inner pads that connect the internal circuit. The interconnection substrate... Agent: Marger Johnson & Mccollom, P.C.

20070252253 - Cooling mechanism for stacked die package, and method of manufacturing stacked die package containing same: A stacked die package includes a substrate (210, 310), a first die (220, 320) above the substrate, a spacer (230, 330) above the first die, a second die (240, 340) above the spacer, and a mold compound (250, 370) disposed around at least a portion of the first die, the... Agent: Intel Corporation C/o Intellevate, LLC

20070252254 - Molded sip package with reinforced solder columns: An integrated circuit, and a semiconductor die package formed therefrom, are disclosed including solder columns for adding structural support to the package during the fabrication process.... Agent: Vierra Magen/sandisk Corporation

20070252256 - Package-on-package structures: A POP (package-on-package) structure includes a first and a second semiconductor chip and a connecting structure. The first semiconductor chip is disposed on a first substrate that includes a plurality of first internal terminals and a plurality of first external terminals. The second semiconductor chip is disposed on a second... Agent: F. Chau & Associates, LLC

20070252252 - Structure of electronic package and printed circuit board thereof: A PCB for mounting IC package is designed with dummy solder pads. Dummy solder pastes will spread on the dummy solder pads after screen printing process of solder paste. A substrate for a package of IC is designed with or without dummy solder pads. After mounting the package of IC... Agent: Birch Stewart Kolasch & Birch

20070252259 - Multi-standards compliant card body: A card body comprises a module-receiving part (3) having a cavity for receiving an electronic module ML. The card body comprises a first side part (4) coupled to the module-receiving part (3), the first side part being separated from the module-receiving part by a first separation line (6), and a... Agent: Osha Liang L.L.P.

20070252261 - Semiconductor device package: The present invention relates to a semiconductor device package, comprising a carrier, a first semiconductor device, a second semiconductor device, a plurality of conductive elements, a pre-mold and a lid. The first semiconductor device is electrically connected to the carrier. The second semiconductor device is disposed above the first semiconductor... Agent: North America Intellectual Property Corporation

20070252262 - Die assembly having electrical interconnect: The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon... Agent: Haynes Beffel & Wolfeld LLP

20070252260 - Stacked die packages: The invention includes stacked die packages. In one implementation, a stacked die package includes a base substrate and at least two pairs of flip chip stacks. Each pair comprises a flip chip in die up orientation, a flip chip in die down orientation and an interposer substrate to which the... Agent: Wells St. John P.s.

20070252263 - Memory package structure: A memory package structure includes: a substrate having a first surface and a second surface, a first memory chip arranged on a chip-bearing area of the first surface and electrically connected with the substrate, an opening formed within a chip-bearing area of the substrate, a control chip arranged on the... Agent: Bacon & Thomas, PLLC

20070252264 - Hybrid integrated circuit device, and method for fabricating the same, and electronic device: A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate,... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070252265 - Power semiconductor module as h - bridge circuit and method for producing the same: A power semiconductor module (41) as H-bridge circuit (42) has four power semiconductor chips (N1, N2, P1, P2) and a semiconductor control chip (IC). The semiconductor chips (N1, N2, P1, P2, IC) are arranged on three mutually separate large-area lead chip contact areas (43 to 45) of a lead plane... Agent: Coats & Bennett/infineon Technologies

20070252266 - Flat panel display with black matrix and method of fabricating the same: A flat panel display with a black matrix and a fabrication method of the same. The flat panel display has an insulating substrate at the upper part of which a pixel electrode is equipped; an opaque conductive film formed on the front surface of the insulating substrate except at the... Agent: Stein, Mcewen & Bui, LLP

20070252267 - Heat sink substrate and production method for the same: A heat sink substrate has a composite structure including a three-dimensional network structure of SiC ceramic having pores infiltrated with Si, and has a thermal conductivity of not less than 150 W/m·K and an oxygen content of not greater than 7 ppm. The heat sink substrate is easily allowed to... Agent: Rabin & Berdo, PC

20070252268 - Thermally controllable substrate: A thermally controllable substrate is disclosed. The substrate supports a heat generating source. One of more microchannels are embedded within the substrate and preferably circulate a cooling fluid to dissipate heat being generated by the source. The flow of the cooling fluid serves to remove heat entering the substrate proximate... Agent: Kathy Manke Avago Technologies Limited

20070252269 - Substrate structure for semiconductor package and package method thereof: A substrate structure for a semiconductor a package and a package method thereof are disclosed. A plurality of independent module substrates are arranged on a metal or heat-resistant frame that has a hollow portion and those module substrates are suspended and connected with the frame by a plurality of connecting... Agent: Bacon & Thomas, PLLC

20070252270 - Circuit apparatus: Heat from a circuit element is effectively conducted to a metal substrate so that reliability of a circuit apparatus is improved. A circuit element is configured such that a wiring layer is formed on a metal substrate. Power devices are mounted on the wiring layer in addition to a circuit... Agent: Fish & Richardson P.C.

20070252271 - Semiconductor memory module having an oblique memory chip: Provided is a semiconductor memory module allowing a filling member formed between a module substrate and memory chips mounted on the module substrate to completely fill the space between the module substrate and the memory chips. According to embodiments of the present invention, the semiconductor memory module includes a module... Agent: Marger Johnson & Mccollom, P.C.

20070252272 - Bump structure, method of forming bump structure, and semiconductor apparatus using the same: A bump structure includes a squashed ball provided on an electrode pad, and a wire provided on the squashed ball. The wire is a wire loop that is loop-shaped and is formed so as to protrude from an end part of the squashed ball. This provides high bonding reliability between... Agent: Nixon & Vanderhye, PC

20070252273 - Semiconductor device having a smaller electrostatic capacitance electrode: A semiconductor package includes a uniform thin insulating film covering the internal circuit formed on a silicon substrate. A plurality of thick island insulating films are formed underlying respective pad electrodes, which connect the internal circuit to an external circuit. The silicon substrate is polished from the bottom to have... Agent: Sughrue Mion, PLLC

20070252275 - Chip packaging structure: A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. The redistribution layer... Agent: Jianq Chyun Intellectual Property Office

20070252274 - Method for forming c4 connections on integrated circuit chips and the resulting devices: A method for forming preferably Pb-lead C4 connections or capture pads with ball limiting metallization on an integrated circuit chip by using a damascene process and preferably Cu metallization in the chip and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad is formed in... Agent: Edward W. Brown

20070252276 - Thin film for vertical form fill and seal packaging of flowable materials: A multi-layer film for vertical form, film and seal systems for liquid, powder, granules and/or other flowables packaging, said multi-layer comprising: an inner layer made of polyethylene, a blend of polyethylenes or ethylene copolymers; a core, comprising one or more than one layer, made from a blend of polypropylene, linear... Agent: Ogilvy Renault LLP

20070252278 - Process of forming a composite diffusion barrier in copper/organic low-k damascene technology: A semiconductor device, having a composite barrier layer, comprising the following. A substrate has a dielectric layer formed thereover and having an opening within the dielectric layer. The opening exposes a first portion of the substrate. A composite barrier layer lines the opening. The composite barrier layer comprises: a dielectric... Agent: Saile Ackerman LLC

20070252277 - Semiconductor devices and fabrication method thereof: A semiconductor device. The semiconductor device includes a substrate, a dielectric layer formed thereon, an opening formed in the dielectric layer, a first barrier layer overlying the sidewall of the opening, a second barrier layer overlying the first barrier layer and the bottom of the opening, and a conductive layer... Agent: Daniel R. Mcclure Thomas, Kayden, Horstemeyer & Risley, LLP

20070252279 - Method of manufacturing a semiconductor device having a silicidation blocking layer: A silicidation blocking layer (SBL) pattern is formed on a substrate including an active region and a field region. The SBL pattern covers the field region and exposes the active region. A silicide layer is formed on the active region by reacting metal with silicon existing in the active region.... Agent: Marger Johnson & Mccollom, P.C.

20070252280 - Semiconductor device using metal nitride as insulating film: A first insulating film is formed on a semiconductor substrate. A second insulating film made of insulating metal nitride is formed on the first insulating film. A recess is formed through the second insulating film and reaches a position deeper than an upper surface of the first insulating film. A... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070252281 - Wirebond pad for semiconductor chip or wafer: In the present invention, copper interconnection with metal caps is extended to the post-passivation interconnection process. Metal caps may be aluminum. A gold pad may be formed on the metal caps to allow wire bonding and testing applications. Various post-passivation passive components may be formed on the integrated circuit and... Agent: Megica Corporation

20070252282 - Air-gap insulated interconnections: Air-gap insulated interconnection structures and methods of fabricating the structures, the methods including: forming a dielectric layer on a substrate; forming a capping layer on a top surface of the dielectric layer; forming a trench through the capping layer, the trench extending toward said substrate and into but not through,... Agent: Schmeiser, Olsen & Watts

20070252284 - Stackable semiconductor package: The present invention relates to a stackable semiconductor package. The stackable semiconductor package includes a first substrate, a chip, a first molding compound, a second substrate, a plurality of first wires, and a second molding compound. The chip is disposed on the first substrate. The second substrate is disposed on... Agent: Volentine & Whitt PLLC

20070252283 - High speed, high density board to board interconnect: A high speed, high density board to board interconnect structure uses a spacer board and BGA techniques to connect two circuit boards. The spacer board is a standard double-sided FR-4 printed circuit board and are connected to each of the circuit boards by a BGA. This interconnect structure allows high... Agent: Ying Chen Chen Yoshimura LLP

20070252285 - Semiconductor device, electronic device, electronic apparatus, and method of manufacturing semiconductor device: A method is provided to suppress detachment between semiconductor packages while preventing dislocation at the time of mounting a stacked semiconductor package on a motherboard. Semiconductor packages PK1 and PK2 are bonded to each other through protruding electrodes and resin is provided between the semiconductor packages PK1 and PK2. The... Agent: Harness, Dickey & Pierce, P.L.C

20070252286 - Mounting substrate: There is provided a mounting substrate on which a semiconductor chip is mounted using a flip chip bonding, having a plurality of connection pads which are connected to the semiconductor chip, and an insulation layer formed in such a manner as to cover the connection pads partially, wherein the insulation... Agent: Rankin, Hill, Porter & Clark LLP

20070252287 - Integrated electronic chip and interconnect device and process for making the same: A method is described for forming an integrated structure, including a semiconductor device and connectors for connecting to a motherboard. A first layer is formed on a plate transparent to ablating radiation, and a second layer on the semiconductor device. The first layer has a first set of conductors connecting... Agent: International Business Machines Corporation Dept. 18g

20070252288 - Semiconductor module and method for forming the same: Under the present invention, a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure. The interposer structure comprises an elastomeric, compliant material that includes metallurgic through connections having a predetermined shape. In a typical embodiment, the metallurgical through connections electrically connect an under... Agent: Hoffman Warnick & D'alessandro, LLC

20070252289 - Oriented self-location of microstructures with alignment structures: An electronic apparatus comprising one or more microstructures on a substrate and a method for fabricating the electronic apparatus. The microstructures have alignment structures that allow the microstructures to be oriented in receptacles having shapes that are complementary to the shapes of the alignment structures. The alignment structures are shapes... Agent: Ladas & Parry