SEARCH:      Monitor Keywords |  Custom RSS

Active solid-state devices (e.g., transistors, solid-state diodes) October listing of patent apps 10/07

20070246700 - Light emitting device and method of manufacturing the same: Provided are embodiments of a light emitting device and a method of manufacturing the same. The light emitting device can include a substrate having a nano-sized structure and a semiconductor light emitting structure on the substrate. The method of manufacturing the light emitting device can include forming a nano-sized structure... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070246707 - Thin film transistor liquid crystal display array substrate and manufacturing method thereof: A TFT LCD array substrate and a manufacturing method thereof. The manufacturing method includes the steps of: forming a thin film transistor on a substrate to form a gate line and a gate electrode connected with the gate line on the substrate; forming a gate insulating layer and a semiconductor... Agent: Hasse & Nesbitt LLC

20070246708 - Semiconductor device: A semiconductor device comprising a high-dielectric film in a part of a gate insulation film is provided by a more simplified method. In a semiconductor device having a first region and a second region, a first gate electrode, a second gate electrode and a high-dielectric gate insulation film are formed... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070246714 - Led package: An LED package improved in efficiency and brightness. In the package, a body has a mounting part thereon. A plurality of light emitting diode chips are mounted on the mounting part. The mounting part has a cross-section upwardly convexed with a non-planar top portion so that at least two adjacent... Agent: Mcdermott Will & Emery LLP

20070246712 - Light emitting diode module: A long life light-emitting diode (LED) module is provided. The LED module includes: a light-emitting chip; a phosphor layer formed of phosphor materials that transform light emitted from the light-emitting chip into light having a longer wavelength than the light emitted from the light-emitting chip; a capping layer that is... Agent: Buchanan, Ingersoll & Rooney PC

20070246715 - Light emitting diode package having multi-stepped reflecting surface structure and fabrication method thereof: A high luminance and high output LED package using an LED as a light source and a fabrication method thereof. The LED package includes an Al substrate with a recessed multi-stepped reflecting surface formed therein and a light source composed of LEDs mounted on the reflecting surface and electrically connected... Agent: Mcdermott Will & Emery LLP

20070246718 - Composite semiconductor device, led print head that employs the composite semiconductor device, and image forming apparatus that employs the led print head: A composite semiconductor device includes a plurality of semiconductor thin films and a substrate on which the semiconductor thin films are attached. Each semiconductor thin film includes a plurality of semiconductor elements. Each semiconductor element includes a first contact region and a second contact region. The first contact region is... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070246720 - Nitride semiconductor light-emitting device and method of manufacturing nitride semiconductor light-emitting device: A nitride semiconductor light-emitting device including a coating film and a reflectance control film successively formed on a light-emitting portion, in which the light-emitting portion is formed of a nitride semiconductor, the coating film is formed of an aluminum oxynitride film or an aluminum nitride film, and the reflectance control... Agent: Harness, Dickey & Pierce, P.L.C

20070246723 - Method for forming film pattern, method for manufacturing active matrix substrate, device, electro-optical device and electronic apparatus: A method for forming a film pattern by disposing a functional liquid in a pattern forming region partitioned by a bank includes: disposing a first bank forming material to a substrate so as to form a first bank layer; and forming a second bank layer on the first bank layer,... Agent: Harness, Dickey & Pierce, P.L.C

20070246724 - Package base structure and associated manufacturing method: A package base structure of a light emitting device and associated manufacturing method is provided. The method includes steps of forming a first mask layer and a second mask layer on a first surface and a second surface of a substrate; defining a first opening and a second opening on... Agent: Madson & Austin Gateway Tower West

20070246727 - Chip seat structuer for light-emitting crystal and a packaging structure thereof: A chip seat structure for light-emitting crystal and a packaging structure thereof. The chip seat structure includes: a model body made of a thermoconductive nonelectroconductive material, the model body having an integrated thermoconductive section; at least one cup seat disposed on a top face of the model body for mounting... Agent: Kamrath & Associates P.A.

20070246729 - High efficiency led package: A light emitting diode (LED) package is disclosed. In one embodiment, the LED package includes an LED, which emits light corresponding to an electric signal and a substrate, which is mounted to electrically couple to the LED and has an anode lead frame and a cathode lead frame. The package... Agent: Knobbe Martens Olson & Bear LLP

20070246726 - Package structure of light emitting device: The present invention relates to a package structure of light emitting device, comprising a light emitting diode disposed on a submount, wherein the light emitting diode comprises a first contact and a second contact respectively connected with a first conductive lead and a second conductive lead of the submount. The... Agent: Rosenberg, Klein & Lee

20070246728 - Surface mounting device-type light emitting diode: A surface mounting device-type light emitting diode (SMD-type LED) comprises a lead frame composed of a pair of lead terminals; a package housing a portion of the lead frame therein, the package having an emission window which is opened so that light is emitted through the emission window; an LED... Agent: Lowe Hauptman Ham & Berner, LLP

20070246699 - Phase change memory cell with vacuum spacer: A memory device. The device includes first and second electrode members, in spaced relation on a substrate. A phase change element lies in electrical contact with the first and second electrode elements and spans the space separating them. The phase change element includes two segments, each in contact with one... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070246701 - Generating multiple bandgaps using multiple epitaxial layers: A quantum well intermixing (QWI) technique for modifying an energy bandgap during the formation of optical semi-conductor devices enables spatial control of the QWI process so as to achieve differing bandgap shifts across a wafer, device or substrate surface. The method includes: forming a substrate comprising one or more core... Agent: Momkus Mccluskey Monroe Marsh & Spyratos, LLC

20070246702 - Fabrication of active areas of different natures directly onto an insulator: application to the single or double gate mos transistor: The invention concerns a micro-electronic device comprising a substrate, a first insulating zone and a second insulating zone laying on said substrate, a first active zone comprising at least one layer made of a first semi-conductor crystalline material, resting on said first insulating zone which insulates it from the substrate,... Agent: Mckenna Long & Aldridge LLP

20070246705 - High performance light-emitting devices: An organic light emitting device consists of a layered structure including a top multilayer stack, a bottom multilayer stack, a cavity layer between the top multilayer stack and the bottom multilayer stack, and an organic light emitting region within the cavity layer. The layered structure is constructed such that the... Agent: Marks & Clerk

20070246703 - Nanoparticle positioning technique: Embodiments of the present invention are generally directed to a method for disposing nanoparticles on a substrate. In one embodiment, a substrate having a plurality of recesses is provided. In this embodiment, a plurality of nanoparticles is also provided. The nanoparticles include a catalyst material coupled to one or more... Agent: Fletcher Yoder (micron Technology, Inc.)

20070246704 - Polymerisable thieno[3,2-b]thiophenes: The invention relates to novel polymerisable thieno[3,2-b]thiophenes, to their use as semiconductors or charge transport materials, in optical, electro-optical or electronic devices like for example liquid, crystal displays, optical films, organic field effect transistors (FET or OFET) for thin film transistor liquid crystal displays and integrated circuit devices such as... Agent: Millen, White, Zelano & Branigan, P.C.

20070246706 - Electronic circuit with repetitive patterns formed by shadow mask vapor deposition and a method of manufacturing an electronic circuit element: An electronic circuit with repetitive patterns formed by shadow mask vapor deposition includes a repetitive pattern of electronic circuit elements formed on a substrate. Each electronic circuit element includes the following elements in the desired order of deposition: a first semiconductor segment, a second semiconductor segment, a first metal segment,... Agent: The Webb Law Firm, P.C.

20070246709 - Thin film semiconductor device: A thin film semiconductor device is provided which includes an insulating substrate, a Si thin film formed over the insulating substrate, and a transistor with the Si thin film as a channel thereof. The Si thin film includes a polycrystal where a plurality of narrow, rectangular crystal grains are arranged.... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070246710 - Semiconductor device and method of manufacturing same: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not... Agent: Fish & Richardson P.C.

20070246713 - Light source and method for producing a light source: The invention relates to a light source comprising at least one p-n-junction which is formed by the arrangement of two suitable semi-conductor materials for the induced emission of light. Said light source is embodied and improved in such a manner that at least one of the semi-conductor materials is in... Agent: Alston & Bird LLP

20070246711 - Multi-directional light scattering led and manufacturing method thereof: A multidirectional light scattering LED and a manufacturing method thereof are disclosed. A metal oxide is irregular disposed over a second semiconductor layer and then is removed by etching. Part of the second semiconductor layer, part of a light-emitting layer or part of the first semiconductor layer is also removed... Agent: Rosenberg, Klein & Lee

20070246717 - Light source having both thermal and space efficiency: A light source that is both thermally and spatially efficient can be achieved by attaching a light source, such as an LED chip, to a flexible circuit and positioning a light conductive material around the light source. For one embodiment, a cavity is created around the light source such that... Agent: Kathy Manke Avago Technologies Limited

20070246716 - Semiconductor light emitting device with integrated electronic components: One or more circuit elements such as silicon diodes, resistors, capacitors, and inductors are disposed between the semiconductor structure of a semiconductor light emitting device and the connection layers used to connect the device to an external structure. In some embodiments, the n-contacts to the semiconductor structure are distributed across... Agent: Patent Law Group LLP

20070246719 - P-n junction-type compound semiconductor light-emitting diode: In a p-n junction-type compound semiconductor light-emitting diode provided on a crystal substrate with at least an n-type active layer formed of a Group m nitride semiconductor as a light emitting layer, and with a Group m nitride semiconductor layer containing a p-type impurity on the n-type active layer, the... Agent: Sughrue Mion, PLLC

20070246722 - Sealed led having improved optical transmissibility: A light emitting diode (LED) having enhanced integrity. The light emitting source of the LED is preferably an LED chip encapsulated by a compliant material, preferably silicone. The LED chip is supported within an optical shell so that a gap exists between the compliant material and the interior surface of... Agent: Kathy Manke Avago Technologies Limited

20070246721 - Semiconductor component having a curved mirror and method for producing a semiconductor component having a curved semiconductor body: A semiconductor component having a semiconductor body, the semiconductor body comprising a curved mirror (3), which is monolithically integrated in the semiconductor body. A method for curving a semiconductor body is also disclosed.... Agent: Cohen, Pontani, Lieberman & Pavane

20070246725 - Semiconductor display device: It is an object of the present invention to provide a semiconductor display device using a protective circuit in which dielectric breakdown is prevented more effectively. In the invention, in the cases that a first interlayer insulating film is formed covering a TFT used for a protective circuit and a... Agent: Eric Robinson

20070246730 - Light emitting diode and light emitting diode device including the light emitting diode element and method for manufacturing the light emitting diode: A light emitting element has a base made of heat conductive material, a wire plate made of an insulation material and secured to an upper surface of the base. Conductive patterns are secured to the wire plate, and a light emitting chip is secured to the base at an exposed... Agent: Dennison, Schultz & Macdonald

20070246731 - Semiconductor device using semiconductor chip: A semiconductor device includes an insulating substrate 2 having an obverse surface formed with a die pad 3, a rectangular semiconductor chip 7 such as an LED chip bonded to the die pad with a die bonding material 10, and a molded portion 9 made of a synthetic resin for... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20070246734 - Multilayered white light emitting diode using quantum dots and method of fabricating the same: A multilayered white light emitting diode and a method of fabricating the same include forming a phosphor mixture layer including a green phosphor and a blue phosphor on a UV light emitting diode and forming a red quantum dot layer on the phosphor mixture layer. In the white light emitting... Agent: Cantor Colburn, LLP

20070246733 - Nitride-based semiconductor substrate, method of making the same and epitaxial substrate for nitride-based semiconductor light emitting device: A nitride-based semiconductor substrate has a substrate formed of a nitride-based semiconductor crystal having a mixed crystal composition with three elements or more. The substrate has a diameter of not less than 25 mm, and a thermal resistivity in a range of 0.02 Kcm2/W to 0.5 Kcm2/W in its thickness... Agent: Foley And Lardner LLP Suite 500

20070246736 - Light emitting element and communication device using same: A light emitting element has a well layer formed of a GaN-based semiconductor, a barrier layer next to the well layer, the barrier layer being formed of a GaN-based semiconductor, and a GaN-based semiconductor layer formed between the well layer and the barrier layer. The GaN-based semiconductor layer has a... Agent: Mcginn Intellectual Property Law Group, PLLC

20070246732 - Oxynitride phosphor and a light emitting device: One preferred embodiment according to the present invention, there is provided an oxynitride phosphor and a light emitting device using the same that is able to reduce production costs and chromaticity shifts. The phosphor is represented by a general formula of (Ca1−zYz)x(Si, Al)12(O, N)16:Eu2+y, and has a main phase of... Agent: Sughrue Mion, PLLC

20070246735 - Semiconductor light emitting element: A semiconductor light emitting element has an electrode formed on a semiconductor layer, a passivation film covering a part of a top surface of the electrode, and a multilayer film formed on the electrode. The multilayer film has at least one pair of a Ti layer and a Ni layer,... Agent: Mcginn Intellectual Property Law Group, PLLC

20070246737 - Electrostatic discharge protection apparatus for integrated circuits: An electrostatic discharge (ESD) protection apparatus for integrated circuits is provided. The ESD protection apparatus includes an ESD protection device. The ESD protection device is disposed in a guard ring and includes a special ESD protection unit and an ESD protection unit. The special ESD protection unit is parallel to... Agent: J.c. Patents, Inc.

20070246738 - Semiconductor device and method of manufacturing the same: In a semiconductor device of the present invention, an N type epitaxial layer is divided into a plurality of element formation regions by an isolation region. In one of the element formation regions, a MOS transistor is formed. Around the MOS transistor, a protection element having a PN junction region... Agent: Fish & Richardson P.C.

20070246739 - Semiconductor device and method of manufacturing the same: In a semiconductor device of the present invention, an N type epitaxial layer is divided into a plurality of element formation regions by an isolation region. In one of the element formation regions, an NPN transistor is formed. Around the NPN transistor, a protection element having a PN junction region... Agent: Fish & Richardson P.C.

20070246740 - Transistor with increased esd robustness and related layout method thereof: The invention relates to a layout method for a transistor with improved ESD robustness. The layout method includes defining a ring region from a first conductive type; defining a first and a second rectangular diffusion regions from a second conductive type, wherein the first and second rectangular diffusion regions are... Agent: North America Intellectual Property Corporation

20070246741 - Stress relaxation for top of transistor gate: An improved way to apply tensile or compressive stress to one or more transistors on a semiconductor device is described. A portion of the tensile or compressive stress liner may be removed or modified such that a reduced amount of stress, or even no stress, is applied above the transistor... Agent: Banner & Witcoff, Ltd.

20070246742 - Method of manufacturing a strained semiconductor layer, method of manufacturing a semiconductor device and semiconductor substrate suitable for use in such a method: The invention relates to a method of manufacturing a semiconductor strained layer and to a method of manufacturing a semiconductor device (10) in which a semiconductor body (11) of silicon is provided, at a surface thereof, with a first semiconductor layer (1) having a lattice of a mixed crystal of... Agent: Nxp, B.v. Nxp Intellectual Property Department

20070246743 - Method of forming a phase change material layer, method of forming a phase change memory device using the same, and a phase change memory device so formed: A method of forming a phase change material layer includes preparing a substrate having an insulator and a conductor, loading the substrate into a process housing, injecting a deposition gas into the process housing to selectively form a phase change material layer on an exposed surface of the conductor, and... Agent: Lee & Morse, P.C.

20070246744 - Method of manufacturing a coreless package substrate and conductive structure of the substrate: A method of manufacturing a coreless package substrate together with a conductive structure of the substrate is disclosed. The method can produce a coreless package substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed... Agent: Bacon & Thomas, PLLC

20070246745 - Complementary metal oxide semiconductor image sensor and method for fabricating the same: A complementary metal oxide semiconductor image sensor and a method for fabricating the same are disclosed, wherein a width of a depletion area of a photodiode is varied by variably applying a back bias voltage to a semiconductor substrate without using any color filter, thereby preventing a back bias voltage... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070246746 - Solid-state image pickup device: A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion... Agent: Robert J. Depke Lewis T. Steadman

20070246747 - Image display apparatus: An image display apparatus includes a front substrate, and a rear substrate opposed to the front substrate. The front substrate has phosphor layers, resistor layers provided between the phosphor layers, a metal-back layer divided into metal-back segments covering the phosphor layers and resistor layers at least in part, and spaced... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070246748 - Phase change memory cell with limited switchable volume: A memory cell comprises a dielectric layer and a phase change material. The dielectric layer defines a trench having both a wide portion and a narrow portion. The narrow portion is substantially narrower than the wide portion. The phase change material, in turn, at least partially fills the wide and... Agent: Ryan, Mason & Lewis, LLP

20070246749 - Solution of power consumption reduction for inverter covered by metal case: For improving efficiency of a power device having an exposed surface capable of radiating energy, a shielding layer is disposed in between the exposed surface and a conductive layer. The shielding layer causes at least a portion of the energy to be directed back into the power device, thereby substantially... Agent: Haynes And Boone, LLP

20070246750 - Control of body potential of partially-depleted field-effect transistors: A partially-depleted silicon-on-insulator (SOI) field-effect transistor (FET) with a reduced off-current is described, as well as methods for manufacturing. This may be accomplished by providing an SOI FET having a lower body potential than in previous SOI FETs. To lower the body potential, carrier traps may be formed mainly in... Agent: Banner & Witcoff, Ltd.

20070246755 - Method for fabricating recessed gate mos transistor device: A method of fabricating self-aligned gate trench utilizing TTO poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has... Agent: North America Intellectual Property Corporation

20070246753 - Metal gated ultra short mosfet devices: MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer... Agent: Innovation Interface, LLC

20070246754 - Semiconductor device and method for manufacture: A semiconductor device is formed with a lower field plate (32) and optional lateral field plates (34) around semiconductor (20) in which devices are formed, for example power FETs or other transistor or diode types. The semiconductor device is manufactured by forming trenches with insulated sidewalls, etching cavities (26) at... Agent: Nxp, B.v. Nxp Intellectual Property Department

20070246752 - Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering and methods for fabricating such device structures and for fabricating a semiconductor-on-insulator substrate: Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering, methods for fabricating such device structures, and methods for forming a semiconductor-on-insulator substrate. The semiconductor structure comprises a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20070246751 - Spacer structure and fabrication method thereof: A spacer structure contains a carbon-containing oxynitride film positioned on a gate sidewall and a nitride film covering the carbon-containing oxide film. The carbon-containing oxynitride film has low etch rate so that the spacer structure can have a good profile during etching the carbon-containing oxynitride film.... Agent: North America Intellectual Property Corporation

20070246757 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same is disclosed, to improve reliability of a driving part transistor and to improve an output voltage of a photodiode, which includes a semiconductor substrate defined as a photodiode transistor region and a driving part transistor region; a first gate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070246756 - Image sensor with soi substrate: An imager pixel utilizing a silicon-on-insulator substrate, a photodiode in said substrate below the buried oxide, and a dual contact to said photodiode and methods of forming said imager pixel. The photodiode has an increased fill factor due to its increased size relative to the pixel.... Agent: Dickstein Shapiro LLP

20070246758 - Semiconductor device: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element... Agent: Harness, Dickey & Pierce, P.L.C

20070246759 - Semiconductor device: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element... Agent: Harness, Dickey & Pierce, P.L.C

20070246760 - Semiconductor device: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element... Agent: Harness, Dickey & Pierce, P.L.C

20070246761 - Electrical lapping guides made from tunneling magnetoresistive (tmr) material: Tunneling magnetoresistive (TMR) electrical lapping guides (ELG) are disclosed for use in wafer fabrication of magnetic sensing devices, such as magnetic recording heads using TMR read elements. A TMR ELG includes a TMR stack comprising a first conductive layer, a barrier layer, and a second conductive layer of TMR material.... Agent: Duft Bornsen & Fishman, LLP

20070246762 - Semiconductor device including a tcam having a storage element formed: In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact... Agent: Mcdermott Will & Emery LLP

20070246763 - Trench step channel cell transistor and manufacture method thereof: A trench step channel cell transistor and a manufacture method thereof are disclosed. The transistor could be applied to increase the channel length thereof. The transistor comprises a step silicon layer formed by a selective growth, while the step silicon layer is located above the active area of the transistor.... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC

20070246764 - Low-temperature metal-induced crystallization of silicon-germanium films: The present invention provides for a low-temperature method to crystallize a silicon-germanium film. Metal-induced crystallization of a deposited silicon film can serve to reduce the temperature required to crystallize the film. Increasing germanium content in a silicon-germanium alloy further decreases crystallization temperature. By using metal-induced crystallization to crystallize a deposited... Agent: Patent Dept., Sandisk Corporation

20070246766 - Phase change memory elements using self-aligned phase change material layers and methods of making and using same: A phase change memory element and method of forming the same. The memory element includes a substrate supporting a first electrode. An insulating material element is positioned over the first electrode, and a phase change material layer is formed over the first electrode and surrounding the insulating material element such... Agent: Dickstein Shapiro LLP

20070246767 - Semiconductor device formed on a soi substrate: Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070246765 - Semiconductor memory device and method for production: Parallel fins or ridges are arranged on a main surface of a semiconductor substrate. Source/drain regions are provided at top and bottom portions of said fins, and wordlines comprising gate electrodes are arranged in interspaces between neighboring fins. The channels of individual memory cells are directed vertically with respect to... Agent: Slater & Matsil LLP

20070246769 - Semiconductor device including adjacent two interconnection lines having different distances therebetween: A semiconductor device includes an interconnection layer including adjacent two interconnection lines extending adjacent to each other. A plurality of contact plugs pass through the space between the adjacent two interconnection lines. The adjacent two interconnection lines have different distances therebetween due to a concave-and-convex surface of the sidewall of... Agent: Sughrue Mion, PLLC

20070246768 - Nonvolatile memory device and method of fabricating the same: A nonvolatile memory device and a method of fabricating the same are disclosed. The method includes forming a tunnel oxide film and a conductive film for a floating gate on a semiconductor substrate; nitriding the top surface of the conductive film for a floating gate; oxidizing the nitrided top surface... Agent: Mills & Onello LLP

20070246770 - Semiconductor device and method of manufacturing the same: A semiconductor device, including a semiconductor region of the first conduction type which is formed on a semiconductor substrate; a gate electrode at least part of which is present within a trench which is selectively formed in part of the semiconductor region, and an extended top end portion of which... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070246771 - Lateral double-diffused metal oxide semiconductor (ldmos) device with an enhanced drift region that has an improved ron area product: A lateral double-diffused metal oxide semiconductor (LDMOS) device is disclosed. The LDMOS device comprises a gate region and a body region under the gate region. The LDMOS device includes an enhanced drift region under the gate region. The enhanced drift region touches the body region. By designing the device such... Agent: Sawyer Law Group LLP

20070246772 - Mosfet power package: A power MOSFET package is disclosed. The power MOSFET package includes a leadframe having first and second die pads insulated one from the other, the first die pad being coupled to a first drain lead and the second die pad being coupled to a second drain lead. A first MOSFET... Agent: Fortune Law Group LLP

20070246773 - Drive circuit and drain extended transistor for use therein: A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconductor region that differs from the first semiconductor region. An interface exists between... Agent: Texas Instruments Incorporated

20070246775 - Soi substrate and method for forming the same: Provided are an SOI substrate, memory devices using the SOI substrate, and a method of manufacturing the same. The SOI substrate includes a thermal oxide layer pattern which minimizes leakage current but allows back biasing and heat dissipation through the substrate. The SOI substrate also includes a metal-gettering site to... Agent: Marger Johnson & Mccollom, P.C.

20070246774 - Semiconductor device with substantial driving current and decreased junction leakage current: The semiconductor device includes an active region, a stepped recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The stepped recess channel region is formed in the active region.... Agent: Heller Ehrman LLP

20070246776 - Stress engineering for cap layer induced stress: Improved layouts take better advantage of desirable cap-layer induced transverse and vertical stress. In one aspect, roughly described, a tensile strained cap material overlies the transistor channels in the N-channel diffusion regions but not the P-channel diffusion regions. The material terminates at an edge that is located as far as... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20070246777 - Electronic appliance including transistor having ldd region: A high reliability semiconductor display device is provided. A semiconductor layer in the semiconductor display device has a channel forming region, an LDD region, a source region, and a drain region, and the LDD region overlaps a first gate electrode, sandwiching a gate insulating film.... Agent: Fish & Richardson P.C.

20070246778 - Electrostatic discharge panel protection structure: An electrostatic discharge protection structure disposed in a peripheral area of a display panel is electrical connected to a wire of a display area of the display panel and a short ring of the peripheral area. The electrostatic discharge protection structure comprises a first path having a first resistance, and... Agent: North America Intellectual Property Corporation

20070246779 - Dual gate oxide structure in semiconductor device and method thereof: In the method of manufacturing a dual gate oxide layer of a semiconductor device, which has first and second active regions operating at mutually different voltages on a semiconductor substrate, the first and second active regions having a device isolation layer of STI (Shallow Trench Isolation) structure; the method of... Agent: Marger Johnson & Mccollom, P.C.

20070246780 - Semiconductor device and a method of manufacturing the same: A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide... Agent: Miles & Stockbridge PC

20070246781 - Mos semiconductor device and method of fabricating the same: A MOS semiconductor device includes a substrate having a first region with a Si(110) surface and a second region with a Si(100) surface, a p-channel MOSFET formed in the first region, and an n-channel MOSFET formed in the second region. The p-channel MOSFET including a first silicide layer formed on... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070246782 - Memory cell having sidewall spacer for improved homogeneity: A memory cell includes a first electrode, a second electrode, a layer of phase change material extending from a first contact with the first electrode to a second contact with the second electrode, and a sidewall spacer contacting the second electrode and a sidewall of the layer of phase change... Agent: Dicke, Billig & Czaja

20070246783 - Methods of manufacturing semiconductor devices and semiconductor devices manufactured using such a method: A method of manufacturing a semiconductor device includes forming a pillar-shaped active region by etching a portion of a semiconductor substrate, forming a blocking film selectively exposing a sidewall of a lower portion of the pillar-shaped active region, and forming a bit-line selectively on the exposed sidewall of the lower... Agent: Lee & Morse, P.C.

20070246784 - Unipolar nanotube transistor using a carrier-trapping material: An ambipolar nanotube field effect transistor is converted to a unipolar nanotube field effect transistor by providing a carrier-trapping material such as oxygen molecules for the nanotube such as by adsorption or by providing a layer of material containing the carrier-trapping material adjacent to the nanotube.... Agent: Buchanan, Ingersoll & Rooney PC

20070246785 - Locking device, adjustment mechanism and lithographic apparatus: A locking device to lock a six degree of freedom positioned body is disclosed. The device has a clamping bushing to clamp against a surface of a bore extending through the body, a clamping ring to expand when subject to a compression force, and a lock actuator configured to cause... Agent: Pillsbury Winthrop Shaw Pittman, LLP Eric S. Cherry - Docketing Supervisor

20070246786 - Doping of sic structures and methods associated with same: Doped silicon carbide structures, as well as methods associated with the same, are provided. The structures, for example, are components (e.g., layer, patterned structure) in MEMS structures. The doped silicon carbide structures may be highly conductive, thus, providing low resistance to electrical current. An in-situ doping process may be used... Agent: Demont & Breyer, LLC

20070246787 - On-plug magnetic tunnel junction devices based on spin torque transfer switching: Techniques and device designs associated with devices having magnetic or magnetoresistive tunnel junctions (MTJs) configured to operate based on spin torque transfer switching. On-plug MTJ designs and fabrication techniques are described.... Agent: Fish & Richardson, PC

20070246788 - N-well barrier pixels for improved protection of dark reference columns and rows from blooming and crosstalk: The barrier region for isolating one or more dark regions of the pixel array of an image sensor from the active array or from the peripheral circuitry includes N-well pixel isolation region. The N-well pixel isolation region includes at least one N-well implant or at least one N-well stripe. The... Agent: Dickstein Shapiro LLP

20070246789 - Thermionic flat electron emitter: A thermionic flat electron emitter has an emitter arrangement with an emitter plate having slits therein that produce serpentine current paths. The emitter arrangement has a structure that, in operation, causes the electron density of the emitted electrons to be lower in the central region of the emitter plate than... Agent: Schiff Hardin, LLP Patent Department

20070246790 - Transistor process using a double-epitaxial layer for reduced capacitance: In a method to form a DMOS or bipolar transistor, two epitaxial silicon layers are grown over a silicon substrate instead of the typical one low-resistivity epitaxial layer. The bottom epitaxial layer has a relatively high resistivity of, for example 10 ohms-cm, while the upper epitaxial layer, acting as a... Agent: Patent Law Group LLP

20070246791 - Power semiconductor device: A The semiconductor device has a heavily doped substrate and an upper layer with doped silicon of a first conductivity type disposed on the substrate, the upper layer having an upper surface and including an active region that comprises a well region of a second, opposite conductivity type. An edge... Agent: Baker Botts, L.L.P.

20070246793 - Electronic device including a semiconductor layer and another layer adjacent to an opening within the semiconductor layer and a process of forming the same: A process of forming an electronic device can include patterning a semiconductor layer to define an opening. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface is spaced apart from the bottom of the opening.... Agent: Larson Newman Abel Polansky & White, LLP

20070246792 - Method for fabricating back end of the line structures with liner and seed materials: A sputter-etching method employed to achieve a thinned down noble metal liner layer deposited on the surface or field of an intermediate back end of the line (BEOL) interconnect structure. The noble metal liner layer is substantially thinned down to a point where the effect of the noble metal has... Agent: Hoffman, Warnick & D'alessandro LLC

20070246794 - Integrated circuit including power diode: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor... Agent: Courtney Staniford & Gregory LLP

20070246795 - Dual depth shallow trench isolation and methods to form same: Trench isolation structures and methods to form same for use in the manufacture of semiconductor devices are described. The trench isolation structures are formed using several processing schemes that utilize disclosed dry etching processes to form a significant depth A between an array trench depth and a periphery trench depth.... Agent: David J. Paul Micron Technology, Inc.

20070246797 - Fuse corner pad for an integrated circuit: A fuse corner pad is part of an integrated circuit that includes a built-in fuse contact and a plurality of auxiliary pads. The fuse contact is a conductive metallic or metalloid structure that is connected to a fuse element. The fuse contact and fuse element are used inside of the... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070246796 - Semiconductor device with improved contact fuse: One aspect of the invention provides an integrated circuit (IC). The IC comprises transistors and contact fuses. The contact fuses each comprise a conducting layer, a frustum-shaped contact has a narrower end that contacts the conducting layer and a first metal layer that is located over the conducting layer. A... Agent: Texas Instruments Incorporated

20070246798 - Inductor energy loss reduction techniques: An inductive device including an inductor coil located over a substrate, at least one electrically insulating layer interposing the inductor coil and the substrate, and a plurality of current interrupters each extending into the substrate, wherein a first aggregate outer boundary of the plurality of current interrupters substantially encompasses a... Agent: Haynes And Boone, LLP

20070246799 - Semiconductor device: A first opening portion for via hole opening is formed above an electrode groove and a second opening portion for via hole opening for connecting with wiring layer is formed on interlayer insulation film at a position corresponding to the top portion of wiring layer provided out of a capacitor... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070246800 - Transistor apparatus: A transistor apparatus includes a silicon substrate and a barrier structure extending substantially from generally adjacent the silicon substrate to a locus displaced from the silicon substrate. The barrier structure generally surrounds a volume containing connection loci for the transistor apparatus and a buried layer in a silicon medium. The... Agent: Texas Instruments Incorporated

20070246801 - Varactor: A varactor on a substrate is provided. The varactor comprises a bottom electrode, an upper electrode, a first dielectric layer and a conductive layer. The bottom electrode has several doped regions arranged in the substrate as an array with several rows and several columns, wherein the doped regions in adjacent... Agent: J.c. Patents, Inc.

20070246802 - Semiconductor device and methods thereof: A semiconductor device and method thereof. The example method may include forming a semiconductor device, including forming a first layer on a substrate, the first layer including aluminum nitride (AlN), forming a second layer by oxidizing a surface of the first layer and forming a third layer on the second... Agent: Harness, Dickey & Pierce, P.L.C

20070246803 - Semiconductor constructions, and methods of forming semiconductor constructions: The invention includes a method in which a semiconductor substrate is provided to have a memory array region, and a peripheral region outward of the memory array region. Paired transistors are formed within the memory array region, with such paired transistors sharing a source/drain region corresponding to a bitline contact... Agent: Wells St. John P.s.

20070246804 - Organic insulating film, manufacturing method thereof, semiconductor device using such organic insulating film and manufacturing method thereof: The dielectric constants of SiC and SiCN that are currently the subjects of much investigation are both 4.5 to 5 or so and that of SiOC, 2.8 to 3.0 or so. With further miniaturization of the interconnection size and the spacing of interconnections brought about by the reduction in device... Agent: Hayes Soloway P.C.

20070246805 - Multi-die inductor: A technique for improving the quality factor of an inductor includes increasing a cross-sectional area of the inductor by increasing a vertical dimension associated with the inductor. An apparatus includes an inductor formed partially in a first integrated circuit die and formed partially in at least a second integrated circuit... Agent: Zagorin O'brien Graham LLP

20070246806 - Embedded integrated circuit package system: An embedded integrated circuit package system is provided forming a first conductive pattern on a first structure, connecting a first integrated circuit die on the first conductive pattern, forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern, forming a channel in the... Agent: Ishimaru & Zahrt LLP

20070246807 - Semiconductor device having charge accumulation layers and control gates and memory circuit system: A semiconductor device includes a plurality of semiconductor chips and a memory device. The semiconductor chips are provided in a package. Each of the semiconductor chips includes a memory cell array having memory cells which stores data, an output buffer which outputs data read from the memory cell array to... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070246808 - Power semiconductor module having surface-mountable flat external contacts and method for producing the same: The invention relates to a power semiconductor module (1) comprising surface-mountable flat external contact areas (3) and a method for producing the same. The top sides (10) of the external contacts (3) form an inner housing plane (11), on which at least one power semiconductor chip (6) is fixed by... Agent: Dicke, Billig & Czaja

20070246809 - Package for optical device and method of manufacturing the same: A package for an optical device includes a plurality of ceramic layers 101, 102 and 103 stacked on a base 2 and a recessed portion 18 formed to mount an optical element at the center. Reversely rounded portions 11 are formed on the corners of the ceramic layers 100, 101... Agent: Steptoe & Johnson LLP

20070246811 - Stack structure of semiconductor packages and method for fabricating the stack structure: A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower... Agent: Edwards Angell Palmer & Dodge LLP

20070246812 - High reliability power module: A high reliability power module which includes a plurality of hermetically sealed packages each having electrical terminals formed from an alloy of tungsten copper and brazed onto a surface of a ceramic substrate.... Agent: Ostrolenk Faber Gerb & Soffen

20070246810 - Leadframe enhancement and method of producing a multi-row semiconductor package: A semiconductor package includes a plurality of first leads, each with a top outer portion removed from the lead and an outer end, and a plurality of second leads, each with a bottom outer portion removed from the lead and an outer end. The first and second leads alternate with... Agent: Sughrue Mion, PLLC

20070246814 - Ball grid array package structure: A ball grid array structure includes a substrate, wherein a plurality of electric contacts are arranged on its lower surface; a chip arranged on the upper surface of the substrate and electrically connecting with those electric-connecting points; at least a through hole on the substrate and arranged around the edge... Agent: Birch Stewart Kolasch & Birch

20070246816 - Semiconductor integrated circuit device and method for fabricating the same: A semiconductor integrated circuit device is made by stacking a plurality of semiconductor chips. The semiconductor integrated circuit device includes: a penetrating electrode formed to penetrate the plurality of semiconductor chips; a plurality of electrodes formed in respective layers constituting each of the plurality of semiconductor chips and having respective... Agent: Mcdermott Will & Emery LLP

20070246815 - Stackable semiconductor package: The present invention relates to a stackable semiconductor package, comprising a first substrate, a chip, a second substrate, a plurality of second wires, a plurality of supporting elements and a molding compound. The chip is disposed on and electrically connected to the first substrate. The second substrate is disposed above... Agent: North America Intellectual Property Corporation

20070246813 - Embedded integrated circuit package-on-package system: An embedded integrated circuit package-on-package system is provided forming a first integrated circuit package system, forming a second integrated circuit package system, and mounting the second integrated circuit package system over the first integrated circuit package system with the first integrated circuit package system, the second integrated circuit package system,... Agent: Ishimaru & Zahrt LLP

20070246817 - Solder ball assembly for a semiconductor device and method of fabricating same: Solder ball assembly for a semiconductor device and method of fabricating the same is described. In one example, a solder mask is formed on a substrate having an aperture exposing at least a portion of a conductive pad of the substrate. A solder pillar is formed in the aperture and... Agent: Xilinx, Inc Attn: Legal Department

20070246818 - Semiconductor module featuring solder balls having lower melting point than that of solder electrode terminals of electronic device containing additional metal powder component: A semiconductor module includes a wiring board having a bottom surface and a top surface. A first solder electrode terminal has a given melting point, and is provided on the bottom surface of the wiring board. An electrode pad is provided on or above the top surface of the wiring... Agent: Mcginn Intellectual Property Law Group, PLLC

20070246819 - Semiconductor components and systems having encapsulated through wire interconnects (twi) and wafer level methods of fabrication: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact. The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate. The through wire interconnect (TWI) includes a... Agent: Stephen A Gratton The Law Office Of Steve Gratton

20070246820 - Die protection process: A method of protecting a microelectronic chip contained in a microelectronic assembly, including the steps of depositing a protective coating across the exposed faces of the chip. The coating, having a low modulus of elasticity, is applied across the chip so as to reduce the overall height of the assembly... Agent: Tessera Lerner David Et Al.

20070246821 - Utra-thin substrate package technology: A semiconductor package assembly having reduced stresses and a method for forming the same are provided. The method includes providing a package substrate comprising a base material, forming an interconnect structure overlying the package substrate, attaching at least one chip to a first surface of the package substrate, thinning the... Agent: Slater & Matsil, L.L.P.

20070246822 - Hard disk drive preamp heat dissipation methods: A heatsink architecture employing a combination of stiffeners and flex substrate to improve the sinking of heat from the integrated circuit. The stiffener may be employed in numerous locations, including above the integrated circuit, or interposed between the integrated circuit and an e-block. The flex substrate may be interposed between... Agent: Texas Instruments Incorporated

20070246823 - Thermally enhanced bga package with ground ring: The invention provides thermally enhanced BGAs and methods for their fabrication with a ground ring suitable for operably coupling to either the frontside or backside, or both, of an IC chip mounted on a substrate. The methods and devices of the invention disclosed include the fabrication of a ground ring... Agent: Texas Instruments Incorporated

20070246824 - Heat sink design using clad metal: According to some embodiments, an outer metal is cladded to a core metal to create a cladded heat sink fin, the cladded heat sink fin is inserted in a groove of a heat sink base, and the outer metal is heated to a reflow temperature of the outer metal. Embodiments... Agent: Buckley, Maschoff & Talwalkar LLC

20070246825 - High frequency module using metal-wall and method of manufacturing the same: A high frequency module and a manufacturing method thereof In the module, a substrate has a ground. A plurality of surface mounted devices are mounted on the substrate. A metal wall is connected to the ground of the substrate. A resin molding hermetically seals the surface mounted devices and the... Agent: Lowe Hauptman Ham & Berner, LLP

20070246826 - Wafer level semiconductor module and method for manufacturing the same: A wafer level semiconductor module may include a module board and an IC chip set mounted on the module board. The IC chip set may include a plurality of IC chips having scribe lines areas between the adjacent IC chips. Each IC chip may have a semiconductor substrate having an... Agent: Harness, Dickey & Pierce, P.L.C

20070246827 - Semiconductor integrated circuit and method of designing semiconductor integrated circuit: A semiconductor integrated circuit has: a power pad placed on a chip; and a circuit group connected to the power pad through a power wiring structure. The power wiring structure includes: a plurality of first power wirings and a plurality of second power wirings that are formed in different wiring... Agent: Mcginn Intellectual Property Law Group, PLLC

20070246828 - Semiconductor device and method of manufacturing the same: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bonding pad formed on a surface of the electrode pad... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20070246829 - Semiconductor device and method for producing the same: A method for producing a semiconductor device of the present invention includes forming a surface electrode on a semiconductor element, forming a solder layer by plating on one principal surface of the surface electrode, mounting the semiconductor element on the sub-mount so that the solder layer contacts a principal surface... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070246830 - Long-lifetime interconnect structure and method for making: An interconnect structure and method for manufacturing are described wherein an insulating material adjacent to or at least partially surrounding a conductive interconnect has a coefficient of thermal expansion (CTE) equal to or larger than the CTE of the interconnect. For example, a copper-based damascene interconnect layer may be provided,... Agent: Banner & Witcoff, Ltd.

20070246831 - Method for manufacturing a layer arrangement and layer arrangement: In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures.... Agent: Slater & Matsil LLP

20070246832 - Electro-resistance element and electro-resistance memory using the same: An electro-resistance element that has a different configuration from conventional elements and is excellent in both affinity with semiconductor manufacturing processes and heat treatment stability under a hydrogen-containing atmosphere is provided. An electro-resistance element includes an electro-resistance layer that has two or more states in which electric resistance values are... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070246833 - Semiconductor power module: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070246834 - Post passivation interconnection schemes on top of the ic chips: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a... Agent: Saile Ackerman LLC

20070246835 - Semiconductor device: In the case where a first semiconductor chip and a second semiconductor chip are stacked, both the semiconductor chips are connected using micro bumps, such that a circuit block in the first semiconductor chip and a circuit block in the second semiconductor chip are connected by the micro bumps, and... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070246837 - Ic chip package with minimized packaged-volume: An IC chip package, including a single chip package, two stacked chips package or a System-In-Package (SIP), is created to minimize the assembled volume, which basic structure comprises a chip, a circuited substrate provided for the chip electrically mounted thereon and an encapsulated means for covering the chip to constitute... Agent: Bacon & Thomas, PLLC

20070246836 - Electric terminal device and method of connecting the same: An electric terminal device is provided with glass substrate 11, glass-substrate-side electric terminals 15 formed on glass substrate 11, tape carrier packages 16a and 16b which are larger in thermal expansion rate than glass substrate 11, and tape-side electric terminals 21 provided to correspond to glass-substrate-side electric terminals 15. Tape-side... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070246838 - Power semiconductor component, power semiconductor device as well as methods for their production: A power semiconductor component (2) has a semiconductor body with a front face (7) and a rear face (9). The front face (7) has a front-face metallization (8), which provides at least one first contact pad (11). A structured metal seed layer (14) is provided as the front-face metallization (8),... Agent: Baker Botts, L.L.P.

20070246840 - Integrated circuit devices with stacked package interposers: An IC device includes a die and a first package interposer stacked over a second package interposer. The IC device includes a first conductive connection from a first bond pad of the die directly to a bond pad of the first interposer and a second conductive connection from a second... Agent: Wells St. John P.s.

20070246839 - Method of proximity pin manufacture: A method and apparatus related to a substrate support structure are provided. In accordance with one embodiment of the present invention, a method for manufacturing a substrate support structure including proximity pins and apparatus for supporting a substrate inside a semiconductor processing equipment are provided. The method includes providing a... Agent: Townsend And Townsend And Crew, LLP

20070246841 - Semiconductor device: The semiconductor device of the present invention comprises a semiconductor element 28 having a pair of electrodes, a housing 12 having the recess 14 for accommodating the semiconductor element 28, a first lead electrode 18 and the second lead electrode 20 which are exposed on the bottom of the recess... Agent: Birch Stewart Kolasch & Birch

20070246842 - Semiconductor device, electronic apparatus and semiconductor device fabricating method: There is provided a semiconductor device which includes a primary semiconductor chip 11, a secondary semiconductor chip 12 stacked on the primary semiconductor chip 11, primary external connecting terminals 16 which are electrically connected with the primary semiconductor chip 11 via wires 21, secondary external connecting terminals 17 which are... Agent: Rankin, Hill, Porter & Clark LLP

20070246844 - Multi-layer registration and dimensional test mark for scatterometrical measurement: A layered test pattern for measuring registration and critical dimension (CD) for multi-layer semiconductor integrated circuits is disclosed. A first layer includes a first pattern having vertical and horizontal portions. A second layer is formed over the first layer and includes a second pattern having vertical and horizontal portions having... Agent: Intellectual Property Law Department Lsi Logic Corporation

20070246843 - Pattern registration mark designs for use in photolithography and methods of using the same: Pattern registration marks which include: a substrate and an upper material layer disposed above the substrate; an outer trench formed in the upper material layer, the outer trench having an outer trench width; an inner trench formed in the upper material layer, the inner trench having an inner trench width;... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070246845 - Method of forming a metal line and method of manufacturing a display substrate by using the same: In a method of forming a metal line and a method of manufacturing a display substrate, a channel layer and a metal layer are successively formed on a base substrate. A photoresist pattern is formed in a wiring area. The metal layer is etched by using the photoresist pattern to... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070241319 - Phase change memory device having carbon nano tube lower electrode material and method of manufacturing the same: Disclosed is a phase change memory device including: a semiconductor substrate formed with a first insulating interlayer having a first contact hole; a contact plug formed in such a manner so as to be recessed within the first contact hole; a catalyst layer formed on the contact plug in such... Agent: Ladas & Parry LLP

20070241320 - Thin film electron source: A thin film electron source comprising a substrate, a lower electrode formed on one main face of said substrate, an insulation layer formed in contact with said lower electrode and an upper electrode formed in contact with said insulation layer. The upper electrode comprises a first under-layer, a second under-layer,... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070241321 - Light-emitting diode structure: A light-emitting diode (LED) structure including a substrate, a first type doped semiconductor layer, an active layer, a second type doped semiconductor layer and a transparent conductive layer is provided. The first type doped semiconductor layer is located on the substrate. The active layer is located on the first type... Agent: Jianq Chyun Intellectual Property Office

20070241326 - Organic light emitting diode display and manufacturing method thereof: An organic light emitting device and manufacturing method thereof includes a substrate; a first electrode formed on the substrate; a second electrode formed on the first electrode; an light emitting member interposed between the first electrode and the second electrode; and a photonic crystal member disposed in proximity to the... Agent: Cantor Colburn, LLP

20070241327 - Fabrication methods of a zno thin film structure and a zno thin film transistor, and a zno thin film structure and a zno thin film transistor: Provided is a method of fabricating a ZnO thin film structure and a ZnO thin film transistor (TFT), and a ZnO thin film structure and a ZnO thin film transistor. The method of fabricating a ZnO thin film structure may include forming a ZnO thin film on a substrate in... Agent: Harness, Dickey & Pierce, P.L.C

20070241329 - Semiconductor integrated circuit and method for manufacturing same, and mask: A semiconductor integrated circuit includes a first conductor provided in a first region on a substrate and a second conductor provided in a second region on the substrate. The second region is a region enclosing the first region. A minimum design dimension in linewidth of the first conductor is smaller... Agent: Young & Thompson

20070241331 - Electroluminescent device and methods for fabricating the same: Electroluminescent devices and methods for fabricating the same are provided. An exemplary embodiment of an electroluminescent device comprises a substrate. A thin film transistor (TFT) is formed on the substrate. An insulating layer is formed to overlie the TFT and the substrate. An opening is formed in the insulating layer,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070241332 - Liquid crystal display device: A liquid crystal display device having a liquid crystal display panel includes a first substrate, a second substrate, and liquid crystal interposed between the first and second substrates. The first substrate includes an active element, a first insulating film formed on the active element, a plurality of first electrodes disposed... Agent: Reed Smith LLP

20070241333 - Amorphous silicon thin film transistor, organic light-emitting display device including the same and method thereof: An amorphous silicon thin film transistor, an organic light-emitting display (OLED) device including the same and method thereof are provided. The example amorphous silicon thin film transistor may include an amorphous silicon thin film transistor portion including a gate electrode, a gate insulating layer, an amorphous silicon layer, and source/drain... Agent: Harness, Dickey & Pierce, P.L.C

20070241334 - Thin film transistor, method of manufacturing the thin film transistor, and display device: A thin film transistor according to an embodiment of the present invention includes: a semiconductor layer formed on a substrate and having a first diffusion region, a channel region, and a second diffusion region; a gate electrode opposite to the semiconductor layer across a gate insulating film formed on the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070241336 - Thin film transistor: In first and second gate electrodes constituting a gate electrode, the gate length of the second gate electrode is set shorter than the gate length of the first gate electrode and short enough to produce the short channel effect. The threshold voltage of a second transistor corresponding to the second... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070241341 - Light reflecting device with stray light extinction capability: A light reflecting device includes: a substrate having front and back surfaces; a light absorbing layer formed on a selected one of the front and back surfaces of the substrate; a buffer layer formed on the light absorbing layer when the light absorbing layer is formed on the front surface... Agent: Mcnees Wallace & Nurick LLC

20070241345 - Semiconductor light-emitting device and method of fabricating the same: The present invention provides a semiconductor light emitting device which includes a multi-layer structure. Additionally, an electrode is disposed on a first surface of the multi-layer structure. Furthermore, the electrode includes a plurality of bonding pads.... Agent: Birch Stewart Kolasch & Birch

20070241346 - Light emitting device and method for producing light emitting device: A light emitting device of the present invention includes: a substrate including wire patterns separated from each other on a basic material and a runner section to which sealing resin is poured, which runner section is a space between the wire patterns; a light emitting element die-bonded on the substrate;... Agent: Morrison & Foerster LLP

20070241347 - Reflection type liquid crystal display apparatus and liquid crystal projector system: In order to suppress the effect due to electrons (holes) generated by incident light that cannot be prevented from entering only by means of light shielding, rather than the drain region 34 of a transistor, with respect to a majority carrier, a region 36 whose voltage is set to a... Agent: Fitzpatrick Cella Harper & Scinto

20070241349 - Semiconductor device with a driver circuit for light emitting diodes: A novel semiconductor device includes a plurality of light emitting diodes, a plurality of transistors, a source pad, and a plurality of wires. The plurality of transistors drive the plurality of light emitting diodes. The source pad is connected to sources of the plurality of transistors and supplies an electric... Agent: Cooper & Dunham, LLP

20070241348 - Semiconductor light emitting device: An excellent light emitting element capable of improving problems caused by a material having high light-reflectivity and susceptible to electromigration, especially Al used for the electrode. FIG. 2A depicts semiconductor light emitting element having a first and second electrodes 20 and 30 disposed at a same surface side respectively on... Agent: Birch Stewart Kolasch & Birch

20070241350 - Light emitting device and fabrication method thereof: Provided are embodiments of a light emitting device and fabrication methods thereof. The light emitting device can include a buffer layer provided between a substrate and a semiconductor layer incorporating a high fusion point metal. In a fabrication method of the light emitting device, the buffer layer incorporating a high... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070241356 - Semiconductor light emitting device: This invention relates to a semiconductor light-emitting device including a semiconductor light-emitting chip and a transparent carrier. The semiconductor light-emitting chip includes an active layer and transparent substrate. The active layer emits light under a bias. At least a portion of the light emitted from the active layer enters into... Agent: Bacon & Thomas, PLLC

20070241322 - Long wavelength induim arsenide phosphide (inasp) quantum well active region and method for producing same: An InAsP active region for a long wavelength light emitting device and a method for growing the same are disclosed. In one embodiment, the method comprises placing a substrate in an organometallic vapor phase epitaxy (OMVPE) reactor, the substrate for supporting growth of an indium arsenide phosphide (InAsP) film, forming... Agent: Avago Technologies, Ltd.

20070241323 - Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates: Edge-angle-optimized solid phase epitaxy is described as a method for forming hybrid orientation substrates comprising changed-orientation Si device regions free of the trench-edge defects typically seen when trench-isolated regions of Si are recrystallized to the orientation of an underlying single-crystal Si template after an amorphization step. For the case of... Agent: Ibm Corporation, T.j. Watson Research Center

20070241324 - Functional molecular element and functional molecular device: A functional molecular element exhibiting its function under the operation of an electrical field is provided. A compound is used in which a pendant molecule, formed by 4-pentyl-4′-cyanobiphenyl, exhibiting positive dielectric constant anisotropy or a dipole moment along the direction of the long axis of the molecule, is covalently bonded... Agent: Bell, Boyd & Lloyd, LLP

20070241325 - Schottky gate organic field effect transistor and fabrication method of the same: A Schottky gate field effect transistor with high speed and simple structure is provided. The Schottky gate field effect transistor includes: a source, a channel and a drain formed by one organic conductive material, in which the source, channel and drain are formed in a continuous structure within an organic... Agent: Birch Stewart Kolasch & Birch

20070241328 - Process for producing power semiconductor components using a marker: A power semiconductor component and process for producing power semiconductor components is disclosed. In one embodiment, a power semiconductor component is produced, including applying a semiconductor ship to a substrate using a fluorescent marker substance.... Agent: Dicke, Billig & Czaja

20070241330 - Semiconductor integrated circuit device and manufacture thereof: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070241335 - Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques and semiconductor integrated circuits fabricated thereby: Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with... Agent: Marger Johnson & Mccollom, P.C.

20070241337 - Nitride semiconductor device: In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an undoped or n-type aluminum gallium nitride (AlGaN)... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070241338 - Sic semiconductor device and method for manufacturing the same: A SiC semiconductor device includes: a SiC substrate having a drain layer, a drift layer and a source layer stacked in this order; multiple trenches penetrating the source layer and reaching the drift layer; a gate layer on a sidewall of each trench; an insulation film on the sidewall of... Agent: Posz Law Group, PLC

20070241339 - Light-emitting diode with low thermal resistance: A light-emitting diode (LED) structure providing an improved heat transfer path with a lower thermal resistance than conventional LEDs without significantly deviating from the conventional dimensions is described. For some embodiments, a light-emitting diode structure is illustrated that includes a lead frame that is substantially exposed for low thermal resistance... Agent: Patterson & Sheridan, L.L.P.

20070241340 - Micro-mirror based display device having an improved light source: A display device includes one or more light emitting diodes (LEDs) configured to emit light and a spatial light modulator comprising one or more tiltable micro mirrors each configured to receive the light emitted from the one or more LEDs and reflect the emitted light in two or more directions.... Agent: Fish & Richardson P.C.

20070241343 - Photo coupler: A photo coupler includes a semiconductor laser, a semiconductor light-receiver, a resin protector, a reflective film, a light pipe, and electrodes. The light pipe is made of resin, has a rectangular parallelepiped shape, and is provided so as to surround an outer circumferential portion of the semiconductor light-receiver. On a... Agent: Mcdermott Will & Emery LLP

20070241342 - Semiconductor light emitting device: In at least one aspect, a semiconductor light emitting device may include a first lead, a second lead provided being apart from the first lead, a semiconductor light emitting element provided on the first lead, a wiring electrically connecting the semiconductor light emitting element and the second lead, a first... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20070241344 - Semiconductor light emitting device: For a semiconductor light emitting device using GaInNAs as an active layer, since GaInNAs includes N, the critical thickness is reduced and it is difficult to lengthen the wavelength of a laser beam. A semiconductor light emitting device is prepared, which has an active layer comprising a quantum well layer... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070241351 - Double-sided nitride structures: A compound nitride semiconductor substrate includes a substrate having a first side and a second side. A first layer overlies the first side of the substrate and a second layer overlies the second side of the substrate. The first layer includes a first group-III element and nitrogen. The second layer... Agent: Townsend And Townsend And Crew LLP / Amat

20070241353 - Group iii intride semiconductor light emitting element: A group III nitride semiconductor light emitting element, comprising having a light emitting layer with a multiquantum well structure formed of a group III nitride semiconductor. The light emitting layer has plural well layers, and the plural well layers are formed to coincide in emission wavelength with each other.... Agent: Mcginn Intellectual Property Law Group, PLLC

20070241352 - Group iii nitride semiconductor light emitting device: It is an object of the present invention to provide a simple and reliable method for forming a rough structure having inclined side surfaces in a light emitting device, and to provide a group III nitride semiconductor light emitting device that is obtained by the method and is excellent in... Agent: Sughrue Mion, PLLC

20070241358 - Led package and method for producing the same: An LED package and method for producing the same are described. The LED package has an LED die with a conductive region-forming surface and a plurality of conductive regions disposed on the conductive region-forming surface. An insulation layer is formed on the conductive region-forming surface of the LED die, and... Agent: Rosenberg, Klein & Lee

20070241359 - Led package and method for producing the same: An LED package and method for producing the same are described. The LED package has an LED die with a conductive region-forming surface and a plurality of conductive regions disposed on the conductive region-forming surface. An insulation layer is formed on the conductive region-forming surface of the LED die, and... Agent: Rosenberg, Klein & Lee

20070241357 - Led packages with mushroom shaped lenses and methods of manufacturing led light-emitting devices: Methods of fabricating a light-emitting device are provided. A light-emitting device can be formed from bonding a lens including a plug and a cap to an LED package including a socket configured to receive the plug. The lens can be fabricated using an injection mold formed from a well secured... Agent: Carr & Ferrell LLP

20070241354 - Semiconductor light-emitting device and its manufacturing method: A semiconductor light-emitting device comprises a multilayer structure and a glass substrate. The multilayer structure includes a plurality of laminated compound semiconductor layers and generates light. The multilayer structure has a light exit face for emitting the generated light, whereas the glass substrate optically transparent to the light is bonded... Agent: Drinker Biddle & Reath (dc)

20070241355 - System and method for enhancing light emissions from light packages by adjusting the index of refraction at the surface of the encapsulation material: Light emission from a light package, such as from an LED light package, is enhanced by a system and method for adjusting the refractive index at the surface of the encapsulating material surrounding the light source. The surface refractive index is changed to better match the index within the encapsulating... Agent: Kathy Manke Avago Technologies Limited

20070241360 - Light emitting devices suitable for flip-chip bonding: Light emitting device die having a mesa configuration on a substrate and an electrode on the mesa are attached to a submount in a flip-chip configuration by forming predefined pattern of conductive die attach material on at least one of the electrode and the submount and mounting the light emitting... Agent: Myers Bigel Sibley & Sajovec, P.A.

20070241361 - Light emitting diode and light emitting diode device including the light emitting diode element and method for manufacturing the light emitting diode: A light emitting diode has a base made of heat conductive material, a wire plate made of an insulation material and secured to an upper surface of the base. Conductive patterns are secured to the wire plate, and a light emitting diode element is secured to the base at an... Agent: Dennison, Schultz & Macdonald

20070241362 - Light emitting diode package and fabrication method thereof: An LED package and a fabrication method therefor. The LED package includes first and second lead frames made of heat and electric conductors, each of the lead frames comprising a planar base and extensions extending in opposed directions and upward directions from the base. The package also includes a package... Agent: Mcdermott Will & Emery LLP

20070241363 - Light-emitting diode lamp with low thermal resistance: A light-emitting diode (LED) structure with an improved heat transfer path with a lower thermal resistance than conventional LED lamps is provided. For some embodiments, a surface-mountable light-emitting diode structure is provided having an active layer deposited on a metal substrate directly bonded to a metal plate that is substantially... Agent: Patterson & Sheridan, L.L.P.

20070241364 - Substrate with transparent conductive film and patterning method therefor: A substrate with transparent conductive film which is suitable for laser patterning and can be produced with high productivity, is provided. A substrate with transparent conductive film, which comprises a glass substrate and a transparent conductive film composed mainly of indium oxide, formed thereon, wherein the average domain diameter at... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070241365 - Semiconductor integrated circuit device: A finger length a1 of a transistor P11 is longer than a finger length A1 of a transistor P1, and a finger length b1 of a transistor N11 is longer than a finger length B1 of a transistor N1. The finger length b1 of the transistor N11 is shorter than... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070241366 - Field effect transistor with shifted gate: A field effect transistor has a shifted gate such that the gate-source distance depends on the ratio of the threshold voltage to the drain voltage. In one embodiment, a switch may include two FETs: one FET in a series configuration and one FET in a shunt configuration. Providing a switch... Agent: Wolf Greenfield & Sacks, P.C.

20070241367 - Ultra scalable high speed heterojunction vertical n-channel misfets and methods thereof: A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the... Agent: Robert M. Trepp Intellectual Property Law Dept.

20070241368 - Field effect transistor with independently biased gates: A field effect transistor (FET) having at least two independently biased gates can provide uniform electric field in the channel region of the FET. The same AC voltage may be applied to each gate for modulating the FET. One of the gates is positioned closer to the channel region than... Agent: Wolf Greenfield & Sacks, P.C.

20070241369 - Couplings within memory devices and methods: Methods and apparatus are provided. In one embodiment, a memory device includes a first bit line selectively coupled to an input of a sensing device through a first multiplexer gate, and a second bit line selectively coupled to the input of the sensing device through a second multiplexer gate. The... Agent: Leffert Jay & Polglaze, P.A. Attn: Tod A. Myrum

20070241370 - Semiconductor memory device: A gate electrode of a MOS transistor connected with a word line and a bit line in an SRAM has a projection extending in a direction away from a contact electrically connecting a drain region of the MOS transistor and the bit line. A contact electrically connecting the gate electrode... Agent: Mcdermott Will & Emery LLP

20070241371 - Memory device and manufacturing method: A memory device includes first and second electrodes separated by an insulating member comprising upwardly and inwardly tapering surfaces connected by a surface segment. A bridge, comprising memory material, such as a phase change material, switchable between electrical property states by the application of energy, is positioned across the surface... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070241372 - Image sensor device and method of manufacturing the same: A method of manufacturing image sensor devices, in which a dielectric protecting layer is formed on a photo-receiving region before a gate of a MOS is formed. Therefore, during the subsequent processes for forming the MOS component, damage to the surface of the photo-receiving region caused by plasma or etching... Agent: North America Intellectual Property Corporation

20070241373 - Semiconductor device and its manufacturing method: In the process of manufacturing a semiconductor device, a first layer is formed on a substrate, and the first layer and the substrate are etched to form a trench. The inner wall of the trench is thermally oxidized. On the substrate, including inside the trench, is deposited a first conductive... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070241374 - Solid-state image sensing apparatus and fabrication method therefor: A solid-state image sensing apparatus has a signal storage portion of a second conductivity type provided within a semiconductor substrate or a well each of a first conductivity type to store a signal charge obtained through a photoelectric conversion, a surface shield layer of the first conductivity type provided in... Agent: Mcdermott Will & Emery LLP

20070241375 - Image sensor and method of forming the same: An image sensor includes a semiconductor substrate, a photo receiving area in the semiconductor substrate, a gate electrode installed in a lateral side of the photo receiving area on the semiconductor substrate, and a patterned dielectric layer covering the gate electrode, the photo receiving area, and exposing a partial gate... Agent: North America Intellectual Property Corporation

20070241376 - Solid-state imaging device: A solid-state imaging device is provided and includes: a semiconductor substrate; a plurality of photoelectric conversion films stacked above the semiconductor layer and absorbing different wavelength regions of light; and a transmission-blocking film at least one between the plurality of photoelectric conversion films, the transmission-blocking film blocking a transmission of... Agent: Birch Stewart Kolasch & Birch

20070241377 - Back-illuminated photo-transistor arrays for computed tomography and other imaging applications: Back-illuminated photo-transistor arrays for computed tomography and other imaging applications. Embodiments are disclosed that use bipolar transistors and JFETs, either with a single photo-sensor and transistor per pixel, or multiple photo-sensors and transistors per pixel.... Agent: Blakely Sokoloff Taylor & Zafman

20070241379 - Compositions for thin-film capacitance device, high-dielectric constant insulating film, thin-film capacitance device and thin-film multilayer capacitor: A thin-film capacitor (2) in which a lower electrode (6), a dielectric thin-film (8), and an upper electrode (10) are formed in order on a substrate (4). The dielectric thin-film (8) is made of a composition for thin-film capacitance devices. The composition includes a bismuth layer-structured compound whose c-axis is... Agent: Oliff & Berridge, PLC

20070241378 - Method for forming bit line contacts and bit lines during the formation of a semiconductor device, and devices and systems including the bit lines and bit line contacts: A method for forming a semiconductor device comprises forming first and second bit lines at different levels. Forming the bit lines at different levels increases processing latitude, particularly the spacing between the bit lines which, with conventional processes, may strain photolithographic limits. A semiconductor device formed using the method, and... Agent: Micron Technology, Inc.

20070241380 - Semiconductor storage device: a semiconductor storage device is provided with a plurality of active regions formed in the shape of a band in a semiconductor substrate; a plurality of word lines arranged at equal intervals so as to intersect the active regions; a plurality of cell contacts that includes first cell contacts formed... Agent: Sughrue Mion, PLLC

20070241381 - Methods for fabricating semiconductor devices: Semiconductor devices and methods for fabricating a semiconductor devices are disclosed. A disclosed method comprises: forming a first gate electrode functioning as a flash memory; forming first spacers on sidewalls of the first gate electrode; forming a second gate electrode functioning as a normal gate electrode; forming a source/drain region... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070241382 - Semiconductor integrated circuit device and process for manufacturing the same: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070241383 - Single-gate non-volatile memory and operation method thereof: A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and... Agent: Rosenberg, Klein & Lee

20070241386 - Method for reducing topography of non-volatile memory and resulting memory cells: A method for forming a semiconductor structure includes providing a substrate; forming a gate stack of a flash memory cell, wherein a top portion of the gate stack comprises a capping layer; forming a gate having at least a portion over the capping layer; and reducing a thickness of the... Agent: Slater & Matsil, L.L.P.

20070241387 - Nonvolatile semiconductor memory device: An SOI substrate is comprised of a support substrate, a buried insulating layer and a semiconductor layer. A 1poly-type memory cell has a pair of source/drain regions, a floating gate electrode layer, and a control gate impurity diffusion region. An isolation insulating layer extends from a surface of the semiconductor... Agent: Mcdermott Will & Emery LLP

20070241385 - Phase change memory device for optimized current consumption efficiency and operation speed and method of manufacturing the same: Disclosed is a phase change memory device comprising: a semiconductor substrate formed with a first insulating interlayer having a contact hole; a lower electrode formed within the contact hole of the first insulating interlayer; an insulating layer pattern formed on the lower electrode in such a manner so as to... Agent: Ladas & Parry LLP

20070241390 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070241384 - Methods and apparatus for non-volatile semiconductor memory devices: The present invention provides methods and apparatuses for a non-volatile semiconductor memory device. A non-volatile semiconductor memory device having multiple layers to provide a source, a drain, and a floating gate, comprising a plurality of metal layers to provide interconnects to the non-volatile memory wherein at least two of the... Agent: Emil Chang Law Offices Of Emil Chang

20070241388 - Semiconductor device: A semiconductor device includes semiconductor substrate, isolation insulating film, nonvolatile memory cells, each of the cells including tunnel insulating film, FG electrode, CG electrode, interelectrode insulating film between the CG and FG electrodes and including a first insulating film and a second insulating film on the first insulating film and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070241389 - Semiconductor device: A semiconductor device includes a semiconductor substrate, a plurality of nonvolatile memory cells provided on the semiconductor substrate, each of the plurality of nonvolatile memory cells comprising a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a control gate electrode... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070241391 - Non-volatile semiconductor memory device having memory cell array suitable for high density and high integration: First and second semiconductor regions are formed apart from each other on a semiconductor body. A stacked gate is formed on the semiconductor body between the first and second semiconductor regions. The stacked gate has a first side surface, a second side surface opposed to the first side surface, and... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070241392 - Non-volatile flash memory structure and method for operating the same: A non-volatile memory structure and a method for operating the same are proposed. The non-volatile memory structure makes use of a single floating gate structure and a capacitor structure including a pair of regions doped with different type impurities to increase the capacitance and shrink the area. When performing programming... Agent: Rosenberg, Klein & Lee

20070241393 - Low inductance bond-wireless co-package for high power density devices, especially for igbts and diodes: A power semiconductor package that includes at least two semiconductor devices electrically coupled to one another through a common metallic web.... Agent: Ostrolenk Faber Gerb & Soffen

20070241394 - Insulated gate semiconductor device: The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the... Agent: Kenyon & Kenyon LLP

20070241395 - High density memory array having increased channel widths: A memory array having decreased cell sizes and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to... Agent: Fletcher Yoder (micron Technology, Inc.)

20070241396 - Semiconductor apparatus and method of manufacturing the same: A semiconductor apparatus is disclosed. The semiconductor apparatus comprises a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film provided therebetween. The semiconductor apparatus further comprises a gate sidewall insulating film having a three-layered structure formed of a first nitride film, an oxide film,... Agent: Foley And Lardner LLP Suite 500

20070241397 - Semiconductor apparatus and method of manufacturing the same: A semiconductor apparatus is disclosed. The semiconductor apparatus comprises a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film provided therebetween. The semiconductor apparatus further comprises a gate sidewall insulating film having a three-layered structure formed of a first nitride film, an oxide film,... Agent: Foley And Lardner LLP Suite 500

20070241400 - Semiconductor device: A high performance semiconductor device has an NMOS and a PMOS for which each channel is formed on an optimal crystal plane. A semiconductor device comprises a silicon single-crystal substrate whose surface is a (110) crystal plane, a PMOSFET formed on a (110) plane as a wall surface of a... Agent: Sughrue Mion, PLLC

20070241401 - Semiconductor device: A MOS transistor including a source region, a drain region, and a gate electrode has first and second partial isolation regions in one-end gate region and the other-end gate region, respectively, with a first tap region provided adjacent to the first partial isolation region, and a second tap region provided... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070241402 - Semiconductor device: A gate electrode is provided such that both ends thereof in a gate width direction are projected from an active region in plane view. Partial trench isolation insulation films are provided in a surface of an SOI substrate corresponding to lower parts of the both ends, and body contact regions... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070241398 - Error detection and correction in semiconductor structures: A semiconductor structure and a method for operating the same. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is on top of and bonded to the second semiconductor chip. The first and second semiconductor chips include a first and a second... Agent: Schmeiser, Olsen & Watts

20070241399 - Semiconductor device and method of fabricating the same: In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070241405 - Semiconductor memory array architecture, and method of controlling same: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of word lines (e.g., first and second word lines) and a plurality of word line segments (e.g., first and second word line segments) wherein each word line segment is coupled... Agent: Neil A. Steinberg

20070241403 - Integrated circuit with different channel materials for p and n channel transistors and method therefor: A substrate includes a first region and a second region. The first region comprises a III-nitride layer, and the second region comprises a first semiconductor layer. A first transistor (such as an n-type transistor) is formed in and on the III-nitride layer, and a second transistor (such as a p-type... Agent: Freescale Semiconductor, Inc. Law Department

20070241404 - Semiconductor device and manufacturing method thereof: A catalytic element is added to an amorphous semiconductor film and heat treatment is conducted therefor to produce a crystalline semiconductor film with good quality, a TFT (semiconductor device) with a satisfactory characteristic is realized using the crystalline semiconductor film. A semiconductor layer includes a region containing an impurity element... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070241406 - Electrostatic discharge protector for an integrated circuit: An integrated circuit has functional circuitry coupled to a terminal. An electrostatic discharge protector can be coupled to the terminal to protect the functional circuitry from an electrostatic discharge. A substrate includes a first semiconductor material with a first dopant type. A plurality of drain segments adjoin the substrate. Each... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070241407 - Electrostatic discharge protection device and method of fabricating the same: An electrostatic discharge protection device, and a method of fabricating the same, includes a substrate, an n-well formed in the substrate, a p-well formed on the n-well, an NMOS transistor formed on the p-well, the NMOS transistor including a gate electrode, an n+ source and an n+ drain, and a... Agent: Lee, Sterba & Morse, P.C.

20070241408 - Well isolation trenches (wit) for cmos devices: A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P... Agent: Schmeiser, Olsen & Watts

20070241409 - Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20070241410 - Magnetic memory device and method for fabricating the same: The magnetic memory device includes a magnetic shield film 48, and a magnetoresistive effect element 62 formed over the magnetic shield film 48 and including a magnetic layer 52, a non-magnetic layer 54 and a magnetic layer 56, in which a magnetization direction of the first magnetic layer or the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070241411 - Structures and methods for forming sram cells with self-aligned contacts: The present invention relates to a semiconductor device comprising at least one static random access memory (SRAM) cell with self-aligned contacts. Specifically, the at least one SRAM cell comprises at least a first gate conductor that is located over a channel region between a source region and a drain region.... Agent: Scully Scott Murphy & Presser, PC

20070241412 - Borderless contact structures: An SRAM cell. The SRAM cell including: a first gate segment common to a first PFET and a first NFET, a second gate segment common to a second PFET and a second NFET; a first silicide layer contacting a first end of the first gate segment and a drain of... Agent: Schmeiser, Olsen & Watts

20070241413 - Field-effect-transistor multiplexing/demultiplexing architectures and methods of forming the same: This disclosure relates to field-effect-transistor (FET) multiplexing/demultiplexing architectures and methods for fabricating them. One of these FET multiplexing/demultiplexing architectures enables decoding of an array of tightly pitched conductive structures. Another enables efficient decoding of various types of conductive-structure arrays, tightly pitched or otherwise. Also, processes for forming FET multiplexing/demultiplexing architectures... Agent: Hewlett Packard Company

20070241414 - Semiconductor device and manufacturing process therefor: This invention relates to a semiconductor device having a beam made of a semiconductor to which strain is introduced by deflection, and a current is permitted to flow in the beam.... Agent: Mcginn Intellectual Property Law Group, PLLC

20070241415 - Micro-electro mechanical system device using silicon on insulator wafer and method of manufacturing the same: A micro-electro mechanical system (MEMS) device that uses an SOI wafer, and a method of manufacturing the same. The MEMS device includes an SOI wafer including a first silicon layer, a second silicon layer, and an insulating layer formed between the first and second silicon layers, and a protective substrate... Agent: Sughrue Mion, PLLC

20070241416 - Solid state image pickup device and manufacturing method thereof and semiconductor integrated circuit device and manufacturing method thereof: A method of manufacturing a solid-state image pickup device comprises a process for forming a plurality of photoelectric conversion elements PD within a semiconductor substrate 4, a process for forming an interconnection portion, having an interconnection layer 8 in an insulating layer 7, on the surface side of the semiconductor... Agent: Rader Fishman & Grauer PLLC

20070241417 - Micromirror devices and methods of making the same: A method for making a micromirror device comprises is disclosed herein.... Agent: Texas Instruments Incorporated

20070241418 - Image sensing device and fabrication method thereof: An image sensing device includes a substrate with a photo sensing and a transistor regions, a photo diode, a transistor, a dielectric layer, a metal interconnect, a metal conductive line, a conformal passivation layer, a color filter, a lens planar layer, and a microlens. The photo diode is in the... Agent: Jianq Chyun Intellectual Property Office

20070241419 - Transistor and method with dual layer passivation: Semiconductor devices (61) and methods (80-89, 100) are provided with dual passivation layers (56, 59). A semiconductor layer (34) is formed on a substrate (32) and covered by a first passivation layer (PL-1) (56). PL-1 (56) and part (341) of the semiconductor layer (34) are etched to form a device... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070241420 - Semiconductor device and method for fabricating same: The semiconductor device includes a device isolation structure formed in a semiconductor substrate to define an active region, a bridge type channel structure formed in the active region, and a coaxial type gate electrode surrounding the bridge type channel structure of a gate region. The bridge type channel structure is... Agent: Heller Ehrman LLP

20070241421 - Semiconductor structure and method of manufacture: A structure comprises a deep subcollector buried in a first region of a dual epitaxial layer and a reachthrough structure in contact with the deep subcollector to provide a low-resistive shunt which prevents CMOS latch-up for a first device. The structure may additionally include a near subcollector formed in a... Agent: Greenblum & Bernstein, P.L.C

20070241422 - Seal-ring structure for system-level esd protection: A seal-ring structure is formed on a p-substrate that is coupled to a first voltage terminal. The seal-ring structure includes an n-well, a first metal layer, a second metal layer, a first capacitor, a poly-silicon layer, and a second capacitor. The n-well is formed on the p-substrate and coupled to... Agent: North America Intellectual Property Corporation

20070241423 - Methods and apparatus for integrated circuit having multiple dies with at least one on chip capacitor: An integrated circuit comprises a plurality of layers including a first substrate with an on chip capacitor and a second substrate. In one embodiment, the second substrate has an on chip capacitor. The first and/or second substrate can include a sensor element, such as a magnetic sensor element.... Agent: Daly, Crowley, Mofford & Durkee, LLP

20070241425 - Three-dimensional capacitor structure: A three-dimensional capacitor structure has a first conductive layer, a second conductive layer disposed above the first conductive layer, and a plug layer disposed between the conductive layers. The first conductive layer includes first conductive closed-end frames, and first conductive islands disposed inside the first conductive closed-end frames. The second... Agent: North America Intellectual Property Corporation

20070241424 - Vertical parallel plate capacitor using spacer shaped electrodes and method for fabrication thereof: A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalks of the aperture. A pair of capacitor plates is located upon the pair of opposite... Agent: Scully, Scott, Murphy & Presser, P.C.

20070241426 - Semiconductor device: The invention is directed to a semiconductor device having a diode element which prevents a leakage current due to a vertical parasitic bipolar transistor and enhances current efficiency. An element isolation insulation film is provided on an N well layer, and a first P+ layer and a second P+ layer... Agent: Morrison & Foerster LLP

20070241427 - Mesa-type bipolar transistor: The gradient of acceptor density in the depth direction of a base layer is greater at the edge of an emitter layer than at the edge of a collector layer. Also, the distance between a first mesa structure including the emitter layer and the base layer, and a second mesa... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070241428 - Transistor structure with minimized parasitics and method of fabricating the same: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and... Agent: Scully, Scott, Murphy & Presser, P.C.

20070241429 - Electrically conducting track and method of manufacture thereof: t

20070241430 - Heating unit and method of making the same: A heating unit includes an AlN substrate having a main surface on which an elongated heat-generating resistor is provided. A protection layer is formed on the main surface of the substrate for the heat-generating resistor. The protection layer includes a first cover layer covering the heat-generating resistor and a second... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20070241431 - Alternative flip chip in leaded molded package design and method for manufacture: A semiconductor package is disclosed. The package includes a leadframe structure comprising a die attach region and plurality of leads. A molding material is molded around at least a portion of the leadframe structure, and comprises a window. A semiconductor die comprising an edge is mounted on the die attach... Agent: Townsend And Townsend And Crew, LLP

20070241432 - Etched leadframe flipchip package system: The present invention provides an etched leadframe flipchip package system comprising forming a leadframe comprises forming contact leads and etching a plurality of multiple dotted grooves on the contact leads, and attaching a flipchip integrated circuit having solder interconnects on the contact leads between each of the plurality of the... Agent: Ishimaru & Zahrt LLP

20070241433 - Semiconductor device package with base features to reduce leakage: A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into... Agent: Michael J. Urbano

20070241435 - Optical display package and the method thereof: The present invention includes a substrate with a glass plate, a plurality of oxide wires on the glass plate and a plurality of flip chip bumps on the oxide wires and an integrated circuit chip with a plurality of bump pads. The substrate and the integrated circuit chip are hot... Agent: Bacon & Thomas, PLLC

20070241437 - Stacked semiconductor device and fabrication method for same: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of... Agent: Sughrue Mion, PLLC

20070241438 - Strip format of package board and array of the same: Disclosed herein is a strip format of a semiconductor package board and an array thereof, in which a dummy area of the strip format of the semiconductor package board is formed into a predetermined shape such that, when several strip formats of semiconductor package boards are arranged on a panel,... Agent: Staas & Halsey LLP

20070241436 - Adhesive bonding sheet, semiconductor device using the same, and method for manufacturing such semiconductor device: An adhesive bonding sheet having an optically transmitting supporting substrate and an adhesive bonding layer, and being used in both a dicing step and a semiconductor element adhesion step, wherein the adhesive bonding layer comprises: a polymer component (A) having a weight average molecular weight of 100,000 or more including... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070241434 - Adhesive sheet, semiconductor device, and process for producing semiconductor device: An object of the present invention is to provide an adhesive sheet that can fill irregularities due to wiring of a substrate or a wire attached to a semiconductor chip, etc., does not form resin burrs during dicing, and has satisfactory heat resistance and moisture resistance. The present invention relates... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070241439 - Rfid package structure: The present invention provides a radio frequency identification (RFID) package structure for improving a low data reading rate of the conventional RFID transponder structure to overcome the disadvantage of the prior art, and packages a RFID die by an adhesive according to a package technology. The RFID package structure provides... Agent: Rosenberg, Klein & Lee

20070241440 - Overmolded semiconductor package with a wirebond cage for emi shielding: According to one exemplary embodiment, an overmolded package includes a component situated on a substrate. The overmolded package further includes an overmold situated over the component and the substrate. The overmolded package further includes a wirebond cage situated over the substrate and in the overmold, where the wirebond cage surrounds... Agent: Farjami & Farjami LLP

20070241441 - Multichip package system: A multichip package system is provided forming a first substrate having a first side, a second side, and a first opening, connecting a first integrated circuit die to the first substrate through the first opening, connecting a second integrated circuit die on the first substrate, and encapsulating the first integrated... Agent: Ishimaru & Zahrt LLP

20070241442 - Stacked integrated circuit package-in-package system: A stacked integrated circuit package-in-package system is provided forming a first integrated circuit package having a first peripheral contact, forming a second integrated circuit package having a second peripheral contact, stacking the second integrated circuit package on the first integrated circuit package in an offset configuration with the first peripheral... Agent: Ishimaru & Zahrt LLP

20070241443 - Isolating electric paths in semiconductor device packages: Methods, systems, and apparatus for reducing power consumption or signal distortions in a semiconductor device package. The semiconductor device package includes a semiconductor device, a first electric path, a second electric path, and an isolation element in the first electric path. The second electric path is electrically connected to the... Agent: Sidley Austin LLP

20070241444 - Carrier board structure with chip embedded therein and method for fabricating the same: A carrier board structure with a semiconductor chip embedded therein and a method for fabricating the same are proposed. A rectangular cavity is formed at a predetermined position of the carrier board, and at least a breach is formed at a corner of the rectangular cavity, wherein the breach is... Agent: Sawyer Law Group LLP

20070241445 - Semiconductor device, substrate for producing semiconductor device and method of producing them: A semiconductor device P includes a die pad 20, a semiconductor element 30 which is loaded on the die pad 20, and a sealing resin 40. A plurality of electrically conductive portions 10 each having a layered structure including a metal foil 1 comprising copper or a copper alloy, and... Agent: Oliff & Berridge, PLC

20070241446 - Two-sided wafer escape package: A method and structure provides a Direct Write Wafer Level Chip Scale Package (DWWLCSP) that utilizes permanent layers/coatings and direct write techniques to pattern these layers/coatings, thereby avoiding the use of photoimagable materials and photo-etching processes.... Agent: Gunnison Mckay & Hodgson, LLP Garden West Office Plaza, Suite 220

20070241447 - Electronic component package: An electronic component package includes a dielectric substrate having a first surface where an electronic component is sealed. A first signal line connecting to the electronic component and a first ground conductor are formed on the first surface of the dielectric substrate. A second signal line connected to an outside... Agent: Staas & Halsey LLP

20070241448 - Electrically-isolated interconnects and seal rings in packages using a solder preform: Embodiments include electronic assemblies and methods for forming electronic assemblies. One embodiment includes a method of forming a MEMS device assembly, including forming an active MEMS region on a substrate. A plurality of bonding pads electrically coupled to the active MEMS region are formed. A seal ring wetting layer is... Agent: Konrad Raynes & Victor, LLP. Attn: Int77

20070241449 - Apparatus for effecting reliable heat transfer of bare die microelectroinc device and method thereof: Apparatus and method include using a bare die microelectronic device; a heat sink assembly; a heat sink mounting assembly for mounting the heat sink assembly independently of the bare die microelectronic device; and, a force applying mechanism that compression loads, under controlled forces, a surface of the bare die into... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070241450 - Semiconductor device: An objective is to provide a reliability-improved semiconductor device in which heat radiation characteristics are superior, and warpage of the semiconductor device occurring due to heat generation of a semiconductor chip or to varying of the usage environment is also suppressed. The semiconductor device is provided that includes a thermal-conductive... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070241451 - Electronic component device: An electronic component device of the present invention includes a package main body constructed by a lower package portion and an upper package portion and having a housing portion in an inside, and an electronic component mounted in a state that the electronic component is hermetically sealed in the housing... Agent: Kratz, Quintos & Hanson, LLP

20070241452 - Electronic device with a movable mechanism: An electronic device with a movable mechanism mainly comprises a plurality of rolling elements at appropriate positions on the case thereof, so as to support the electronic device and to move it along a plane. Several fixing stands are installed vertically at appropriate positions on the case. When the fixing... Agent: Birch Stewart Kolasch & Birch

20070241453 - Stacked integrated circuit package-in-package system: A stacked integrated circuit package-in-package system is provided forming a first integrated circuit package having a first peripheral contact, forming a second integrated circuit package having a second peripheral contact, stacking the second integrated circuit package on the first integrated circuit package in a multidirectional offset stack configuration with the... Agent: Ishimaru & Zahrt LLP

20070241454 - Capture ring: A capture ring is provided. The capture ring has a top surface and a bottom surface. A support surface is located at the inner periphery of the capture ring parallel to the top surface for supporting a wafer. An inside diameter lead angle is located between the top surface and... Agent: Jianq Chyun Intellectual Property Office

20070241456 - Conductive structure for electronic device: A conductive structure for electronic device includes at least a first conductor, at least a second conductor and a conductive material for connecting the first conductor and the second conductor.... Agent: Birch Stewart Kolasch & Birch

20070241455 - Method for forming dual damascenes with supercritical fluid treatments: A method for forming a damascene structure by providing a single process solution for resist ashing while avoiding and repairing plasma etching damage as well as removing absorbed moisture in the dielectric layer, the method including providing a substrate comprising an uppermost photoresist layer and an opening extending through a... Agent: Tung & Associates

20070241457 - Semiconductor apparatus and method of producing the same: A semiconductor apparatus including: a semiconductor substrate having a through hole; an electrode pad provided on a first surface of the semiconductor substrate so as to cover the through hole; an external connection terminal provided on a second surface of the semiconductor substrate; a conductive wiring passing through the through... Agent: Nixon & Vanderhye, PC

20070241458 - Metal / metal nitride barrier layer for semiconductor device applications: A metal/metal nitride barrier layer for semiconductor device applications. The barrier layer is particularly useful in contact vias where high conductivity of the via is important, and a lower resistivity barrier layer provides improved overall via conductivity.... Agent: Shirley L. Church, Esq.

20070241459 - Devices having a cavity structure and related methods: A structure having a cavity or enclosed space is fabricated by forming a recessed region in a surface of a substrate, and providing a first layer adjacent the recessed region. A liquid mixture including first and second components is supplied to the recessed region. The first component has a higher... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070241460 - Conductive structures including titanium-tungsten base layers: Methods may be provided for forming an electronic device including a substrate, a conductive pad on the substrate, and an insulating layer on the substrate wherein the insulating layer has a via hole therein exposing a portion of the conductive pad. In particular, a conductive structure may be formed on... Agent: Myers Bigel Sibley & Sajovec

20070241463 - Electrode, manufacturing method of the same, and semiconductor device having the same: Metal posts are formed by etching a metal plate. Therefore, the metal posts can be formed with an accurate height and at a fine pitch. By connecting together upper and lower packages using the metal posts formed in the upper package, there is obtained a miniaturized semiconductor device having a... Agent: Sughrue Mion, PLLC

20070241462 - Wiring board, semiconductor device using the same, and method for manufacturing wiring board: A wiring board includes: an insulating substrate; a plurality of conductive wirings provided on the insulating substrate so as to be aligned with a semiconductor mounting region where a semiconductor chip is to be mounted; and bump electrodes provided on the respective conductive wirings. The bump electrodes include a first... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070241461 - Programmable system in package: Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC's that are arranged within the single IC housing. At least one of the IC's is a configurable IC. In some embodiments, the configurable IC is a... Agent: Adeli Law Group, A Professional Law Corporation

20070241464 - Solder joint flip chip interconnection having relief structure: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site,... Agent: Haynes Beffel & Wolfeld LLP

20070241465 - Multi-port memory device having serial input/output interface: A multi-port memory device includes a first package ball out region in which a plurality of balls for a serial I/O interface part are arranged; and a second package ball out region in which a plurality of balls for a dynamic random access memory (DRAM) part are arranged.... Agent: Mcdermott Will & Emery LLP

20070241466 - Chip package: A chip package including a substrate, a chip and a mark is provided. The substrate has a carrying surface. A mark region is disposed on the carrying surface. The chip is disposed on the carrying surface and electrically connected to the substrate. The mark is disposed in the mark region... Agent: Birch Stewart Kolasch & Birch

20070235729 - Organic light emitting display and fabricating method of the same: Disclosed is an organic light emitting display which avoids an occurrence of Newton's rings in coalesced substrate and sealing substrate. A first substrate includes a pixel region and a non-pixel region. An array of organic light emitting pixels including a first electrode, an organic layer, and a second electrode is... Agent: Knobbe Martens Olson & Bear LLP

20070235720 - Polydiazaacenes and electronic devices generated therefrom: wherein at least one of each R, R1, R2, R3, R4, R5 and R6 is independently hydrogen, alkyl, aryl, alkoxy, halogen, arylalkyl, cyano, or nitro; x and y represent the number of R substituents; a and b represent the number of rings; and n represents the number of repeating groups... Agent: Fay Sharpe / Xerox - Rochester

20070235733 - Transistor, pixel electrode substrate, electro-optic device, electronic apparatus, and process for manufacturing semiconductor element: A transistor includes a first gate electrode, a second gate electrode formed over the first gate electrode, a source electrode formed above the first gate electrode, a drain electrode formed above the first gate electrode, and a semiconductor layer covering at least part of the source electrode and at least... Agent: Harness, Dickey & Pierce, P.L.C

20070235735 - Liquid crystal display: A liquid crystal display includes first pixels and second pixels, a plurality of gate lines to transmit gate signals, and a plurality of pairs of first and second data lines crossing the gate lines, the pairs of first data lines and second data lines facing each other with a pixel... Agent: H.c. Park & Associates, PLC

20070235741 - Exposure device and image forming apparatus using the same: To provide an exposure device and an image forming apparatus using the same, in which the exposure device can detect light intensity with improved reliability and thereby controls the light intensity with high precision, the exposure device includes an EL (electro-luminescence) element having a first electrode (an anode), a second... Agent: Greenblum & Bernstein, P.L.C

20070235742 - Light emitting device: A light emitting device is provided which has at least a light emitting layer between a pair of electrodes, wherein the light emitting layer is divided into plural layers in the thickness direction thereof, and an intermediate layer containing at least one of a charge transport material or a light... Agent: Birch Stewart Kolasch & Birch

20070235743 - Light emitting diode package having anodized insulation layer and fabrication method therefor: An LED package having an anodized insulation layer which increases heat radiation effect to prolong the lifetime LEDs and maintains high luminance and high output, and a method therefor. The LED package includes an Al substrate having a reflecting region and a light source mounted on the substrate and connected... Agent: Mcdermott Will & Emery LLP

20070235745 - Semiconductor device and manufacturing method thereof: Impurity concentration of a second semiconductor region is set such that when a predetermined reverse bias is applied to a heterojunction diode configured by a first semiconductor region and the second semiconductor region, a breakdown voltage at least in a heterojunction region other than outer peripheral ends of the heterojunction... Agent: Foley And Lardner LLP Suite 500

20070235707 - Multi-terminal phase change devices: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created... Agent: Patent Law Professionals

20070235708 - Programmable via structure for three dimensional integration technology: A programmable link structure for use in three dimensional integration (3DI) semiconductor devices includes a via filled at least in part with a phase change material (PCM) and a heating device proximate the PCM. The heating device is configured to switch the conductivity of a transformable portion of the PCM... Agent: Cantor Colburn LLP-ibm Yorktown

20070235709 - Memory element with improved contacts: A phase-change memory element comprising a phase-change memory material, a first electrical contact and a second electrical contact. At least one of the electrical contacts having a sidewall electrically coupled to the memory material.... Agent: Philip H. Schlazer Energy Conversion Devices, Inc.

20070235711 - Methods of reducing the bandgap energy of a metal oxide: Disclosed are methods of reducing the bandgap of a metal oxide by alloying a binary oxide with a Group VI element that is isovalent with oxygen. The Group VI element substitutes for at least a portion of the oxygen in the binary oxide to form the alloyed, ternary oxide. Such... Agent: Buchanan, Ingersoll & Rooney PC

20070235710 - Nonvolatile memory: In non-volatile storage device using a variable resistance material, when a crystal state and a noncrystalline state co-exists in the variable resistance material, a crystallization time is shorted, resulting in decrease of the time to maintain information stored. Heat radiation is not rapidly performed during rewriting and thus it takes... Agent: Miles & Stockbridge PC

20070235712 - Resistance variable memory cells: An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material is disposed over the plated electrode and subjected to a conversion process so that ions from the plated material diffuse into the chalcogenide material.... Agent: Thomas J. D'amico Dickstein Shapiro Morin & Oshinsky LLP

20070235713 - Semiconductor device having carbon nanotube interconnects and method of fabrication: An integrated circuit having carbon nanotube interconnects contains input/output pads situated on the upper surface, the pads arranged in an array having at least two rows. Carbon nanotubes are disposed on the input/output pads to provide electrical and thermal interconnection of the integrated circuit chip to another circuit such as... Agent: Motorola, Inc Intellectual Property Section

20070235714 - Nanowire composite and preparation method thereof: A nanowire composite and a method of preparing the nanowire composite comprise a template having a plurality of hollow channels, nanowires formed within the respective channels of the template, and a functional element formed by removing a portion of the template so that one or more of the nanowires formed... Agent: Cantor Colburn, LLP

20070235716 - Electrode: An electrode is described. The electrode includes an electrode plate and a sensor circuit electrically connected to the electrode plate. The electrode can include a gimbaled contact element and a conductive flexure element connecting the electrode plate and the gimbaled contact element and providing a conductive path therebetween. In another... Agent: Fish & Richardson P.C.

20070235715 - Semiconductor optical modulation device: In a conventional EA/DFB laser, since the temperature dependence of the operation wavelength of the EA portion is substantially different from that of the DFB portion, the temperature range over which a stable operation is possible is small. In the case of using the EA/DFB laser as a light emission... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070235718 - Detecting apparatus, and detecting method: A detecting apparatus for detecting information of a liquid object or sample includes a transmission path, a THz wave supplying unit, a THz wave detecting unit, and an infiltrative holding member for infiltration and holding of a liquid object. The supplying unit supplies an electromagnetic wave in a frequency range... Agent: Fitzpatrick Cella Harper & Scinto

20070235717 - Photovoltaic device and lamp and display using the photovoltaic device: Provided are a photovoltaic device and a lamp and a display device using the same. The photovoltaic device includes a substrate; a conductive electric field enhanced layer including a plurality of partial electric field crowding end portions disposed on the substrate; an electron amplification layer disposed on the electric field... Agent: Robert E. Bushnell Suite 300

20070235728 - Electroluminescent materials and devices: Electroluminescent devices have an electroluminescent layer incorporating iridium complexes with 2-benzo[b]thiophenyl and benzimidazole ligands such as bis[thiophen-2-yl-pyridine-C2,N′]-2-(2-pyridyl)-benzimidazole iridium... Agent: David Silverstein Andover-ip-law

20070235727 - Electronic device: An electronic device comprising a heterojunction, wherein the heterojunction comprises a blend comprising an electron donor and an electron acceptor; and wherein the blend is treated so as to form one or more linkages between the electron donor and/or electron acceptor in the treated blend.... Agent: Philips Intellectual Property & Standards

20070235725 - Ethynylene acene polymers and electronic devices generated therefrom: wherein at least one of R1 and R2 is a suitable hydrocarbon, hydrogen, a heteroatom containing group, or a halogen; Ar and Ar′ represent an aromatic moiety; x, y, a, b, c, d, e, f, and g represent the number of groups or rings, respectively; and n represents the number... Agent: Patent Documentation Center

20070235721 - Functionalized heteroacenes and electronic devices generated therefrom: wherein R represents alkyl, alkoxy, aryl, heteroaryl or a suitable hydrocarbon; each R1 and R2 is independently hydrogen (H), a suitable hydrocarbon; a heteroatom containing group or a halogen; R3 and R4 are independently a suitable hydrocarbon, a heteroatom containing group, or a halogen; x and y represent the number... Agent: Patent Documentation Center

20070235722 - Heteroacene polymers and electronic devices generated therefrom: wherein each R1, R2, R3 and R4 are independently hydrogen (H), a heteroatom containing group, a suitable hydrocarbon, or a halogen; Ar and Ar′ each independently represents an aromatic moiety; x, y, a, b, c, d, e, f and g represent the number of groups or rings, respectively; Z represents... Agent: Fay Sharpe / Xerox - Rochester

20070235723 - Linked arylamine polymers and electronic devices generated therefrom: e

20070235730 - Organic light emitting device and method of fabricating the same: An organic light emitting device (OLED) is formed by assembling a first substrate and a second substrate. The second substrate includes several sub-pixels. The first substrate includes several transistors electrically connected to each other and, for each subpixel, a first connecting electrode electrically connected to one of the transistors. Each... Agent: Lowe Hauptman Ham & Berner, LLP

20070235719 - Poly(alkynylthiophene)s and electronic devices generated therefrom:

20070235726 - Poly[bis(ethynyl)heteroacene]s and electronic devices generated therefrom: wherein R1 is hydrogen, halogen, a suitable hydrocarbon, or a heteroatom containing group; R2 is hydrogen, a suitable hydrocarbon, a heteroatom containing group, or a halogen; R3 and R4 are independently a suitable hydrocarbon, hydrogen, a heteroatom containing group, or a halogen; Ar is an aromatic component; x, y, a,... Agent: Patent Documentation Center

20070235724 - Semiconductors and electronic devices generated therefrom: e

20070235731 - System for and method of active array temperature sensing and cooling: A system and method for providing an active array of temperature sensing and cooling elements, including an active heatsink which further includes an active temperature sensing layer, a thermoelectric cooling layer, and a heatsink, which further includes a plurality of cooling channels. The temperature sensing element within the active temperature... Agent: Dickstein Shapiro LLP

20070235732 - Electrical arrangement comprising a wire connection arrangement and method for the production of such an electrical arrangement: An electrical arrangement has a first electrically conductive contact point (10) and a second electrically conductive contact point (20), the first and the second contact point being arranged at a distance (x) from one another and being electrically connected to one another via a wire connection arrangement (30), the wire... Agent: Baker Botts L.L.P. Patent Department

20070235734 - Semiconductor device and method of manufacturing the same: On an SOI substrate, a hydrogen ion implantation section in which distribution of hydrogen ions peaks in a BOX layer (buried oxide film layer), and a single-crystal silicon thin-film transistor are formed. Then this SOI substrate is bonded with an insulating substrate. Subsequently, the SOI substrate is cleaved at the... Agent: Nixon & Vanderhye, PC

20070235736 - Active matrix type display device and method of manufacturing the same: A method of manufacturing an active matrix type display device, which is reliable and flexible, is provided. An active matrix type display device according to an aspect of the present invention includes: a first substrate, which is flexible; a thin glass layer provided on the first substrate via an adhesion... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070235737 - Array substrate for liquid crystal display device and the fabrication method of the same: The present invention discloses a four-mask method of manufacturing an array substrate of a liquid crystal display device and the liquid crystal display device having the same array substrate. The method includes forming a plurality of gate lines, gate electrodes and gate extension lines by depositing a first metallic material... Agent: Mckenna Long & Aldridge LLP

20070235738 - Nanowire light emitting device and method of fabricating the same: A nanowire light emitting device and method of fabricating the same. The nanowire light emitting device includes: a substrate; a first electrode layer formed on the substrate; a plurality of nanowires vertically formed on the first electrode layer, the nanowire having a p-type doped portion and an n-type doped portion... Agent: Sughrue Mion, PLLC

20070235740 - Organic light emitting device and method of fabricating the same: An organic light emitting device is formed by assembling a first substrate and a second substrate. The second substrate includes several sub-pixels. The first substrate includes several transistors and, for each subpixel, a first connecting electrode. The transistors are electrically connected to each other, and the first connecting electrode is... Agent: Lowe Hauptman Ham & Berner, LLP

20070235739 - Structure of heat dissipation of implant type light emitting diode package and method for manufacturing the same: A structure of heat dissipation of implant type light emitting diode package having a heat column and a method of manufacturing the same include a substrate, a heat column, and a light emitting diode chip, and the heat column is implanted directly onto a predetermined position of the light emitting... Agent: Hdsl

20070235744 - Eutectic bonding of ultrathin semiconductors: Ultra-high speed semiconductors that are usually very thin and therefore very fragile still require connection to a circuit board and a heat transfer pathway. Ultra-high speed circuits and semiconductor devices are provided with a carrier plate formed on the backside of a wafer or substrate by a variety of deposition... Agent: Patti, Hewitt & Arezina LLC

20070235746 - Light emitting diode package and light emitting diode: In a light emitting diode package or a light emitting diode, a cover body having an opening with a reflecting surface is attached on an upper portion of a base body on which a light emitting diode element is mounted. The base body is formed of alumina ceramics having a... Agent: Takeuchi & Kubotera, LLP Suite 202

20070235747 - Light source with compliant interface: A compliant interface is added above the top housing of a light source, such as an LED during LED manufacture. The compliant interface allows for a low light loss transfer between the surface of the light guide material. The compliant structure is, in one embodiment, a light transparent compliant silicone... Agent: Kathy Manke Avago Technologies Limited

20070235748 - Lighting device having a lighting unit with an optical semiconductor bare chip mounted on printed wiring board: A wiring board used for mounting an LED bare chip capable of firmly bonding the LED bare chip and improving yield. In a printed wiring board 2, a distance D between wiring patterns 81 and 85 disposed so as to oppose each other is the smallest at a position nearest... Agent: Snell & Eilmer L.L.P. Attn: Joseph W. Price, Esq.

20070235749 - Miniature mt optical assembly (mmtoa): An optical assembly (10) includes a rigid mount (12) with a recess (26) proximate a first side thereof, a substrate (14), and an optical die (16) flip-chip bonded to the substrate (14). The substrate (14) is secured to the first side of the mount and includes a plurality of die... Agent: Hovey Williams LLP

20070235750 - Nitride-based semiconductor device and method of fabricating the same: A method of fabricating a nitride-based semiconductor device capable of reducing contact resistance between a nitrogen face of a nitride-based semiconductor substrate or the like and an electrode is provided. This method of fabricating a nitride-based semiconductor device comprises steps of etching the back surface of a first semiconductor layer... Agent: Mots Law, PLLC

20070235751 - White light led devices with flat spectra: A light emitting apparatus including a phosphor blend including two or more phosphors to provide an emission spectrum simulating the spectral power distribution of a CIE reference illuminant across at least a certain spectral range. Such an apparatus is particularly suited for color-critical applications.... Agent: Fay Sharpe LLP

20070235752 - Insulated gate type thyristor: An insulated gate type thyristor includes: a first current terminal semiconductor region of a first conductivity type having a high impurity concentration; a first base semiconductor region of a second conductivity type opposite to the first conductivity type having a low impurity concentration and formed on the first current terminal... Agent: Birch Stewart Kolasch & Birch

20070235753 - Organic semi-conductor photo-detecting device: An organic photo-detecting field-effect device is presented, the device comprising a first layer comprising an organic semi-conducting material, the first layer acting as an accumulation layer and as a charge transport layer for a first type of charge carriers, and a second layer comprising a second material, the second layer... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20070235754 - Electronic switch circuit: Electronic switch device having a smaller number of component parts. Resistor R1 is connected between gate and source of a PchTr P1 and resistor R2 is connected between gate of the PchTr P1 and one end of pushbutton switch SW. Resistor R3 is connected between drain of the PchTr P1... Agent: Mcginn Intellectual Property Law Group, PLLC

20070235755 - Semiconductor device and manufacturing method thereof: A semiconductor device and method of manufacturing the same includes an n−-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode... Agent: Rossi, Kimms & Mcdowell LLP.

20070235756 - Solid-state imaging device, camera and signal processing method: The solid-state imaging device of the present invention includes: photodiodes which are two-dimensionally arranged; light condensers each of which condenses light and is provided in a position to correspond to two of the photodiodes which are adjacent to each other; and separating units each of which separates the light entering... Agent: Greenblum & Bernstein, P.L.C

20070235757 - Silicon carbide bipolar junction transistors having epitaxial base regions and multilayer emitters and methods of fabricating the same: Bipolar junction transistors (BJTs) are provided including silicon carbide (SiC) substrates. An epitaxial SiC base region is provided on the SiC substrate. The epitaxial SiC base region has a first conductivity type. An epitaxial SiC emitter region is also provided on the SiC substrate. The epitaxial SiC emitter region has... Agent: Myers Bigel Sibley & Sajovec

20070235758 - Depletion-less photodiode with supressed dark current and method for producing the same: The invention relates to a photo-detector with a reduced G-R noise, which comprises a sequence of a p-type contact layer, a middle barrier layer and an n-type photon absorbing layer, wherein the middle barrier layer has an energy bandgap significantly greater than that of the photon absorbing layer, and there... Agent: William S Frommer Frommer Lawrence Haug LLP

20070235760 - Field effect transistor comprising gold layer, microfluidic device comprising the field effect transistor, and method of detecting analyte having thiol group using the field effect transistor and the microfluidic device: A field effect transistor for detecting an analyte having a thiol group includes a substrate, a source region and a drain region formed apart from each other on the substrate, the source region and the drain region being doped such that a polarity of the source and drain region is... Agent: Cantor Colburn, LLP

20070235759 - Cmos process with si gates for nfets and sige gates for pfets: An integration scheme for providing Si gates for nFET devices and SiGe gates for pFET devices on the same semiconductor substrate is provided. The integration scheme includes first providing a material stack comprising, from bottom to top, a gate dielectric, a Si film, and a hard mask on a surface... Agent: Scully Scott Murphy & Presser, PC

20070235761 - Wide bandgap transistor devices with field plates: A transistor structure comprising an active semiconductor layer with metal source and drain contacts formed in electrical contact with the active layer. A gate contact is formed between the source and drain contacts for modulating electric fields within the active layer. A spacer layer is formed above the active layer... Agent: Koppel, Patrick & Heybl

20070235762 - Silicon germanium emitter: Disclosed are an improved hetero-junction bipolar transistor (HBT) structure and a method of forming the structure that incorporates a silicon-germanium emitter layer with a graded germanium profile. The graded germanium concentration creates a quasi-drift field in the neutral region of the emitter layer. This quasi-drift field induces valence bandgap grading... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070235763 - Substrate band gap engineered multi-gate pmos devices: A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second... Agent: Michael A. Bernadicou Blakely, Sokoloff, Taylor & Zafman LLP

20070235764 - Integrated circuit having gates and active regions forming a regular grating: A semiconductor device includes a plurality of repeatable circuit cells connectable to one or more conductors providing at least electrical connection to the circuit cells and/or electrical connection between one or more circuit elements in the cells. Each of the circuit cells are configured having gates and active regions forming... Agent: Ryan, Mason & Lewis, LLP

20070235765 - Memory cells and semiconductor memory device using the same: Memory cells and semiconductor memory devices using the same. A substrate comprises two cross-coupled inverters and first and second pass-gate transistors formed therein, the inverters having a data storage node and a date bar storage node coupled to first terminals of the first and second pass-gate transistors. A first conductive... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070235766 - Semiconductor integrated circuit having an oblique global signal wiring and semiconductor integrated circuit wiring method: A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block, and signal wiring passing over... Agent: Dla Piper US LLP

20070235767 - Light emitting device and method for manufacturing the same: This document discloses an organic light emitting device comprising a first electrode and a wire comprising a contact part formed on a substrate, an insulating layer formed on the first electrode and a portion of the wire, the insulating layer comprising an opening which exposes a portion of the first... Agent: Ked & Associates, LLP

20070235768 - Semiconductor device: A semiconductor device includes: a semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface; a Schottky electrode formed on the first surface of the semiconductor layer; and an ohmic electrode electrically connected to the second surface of... Agent: Mcdermott Will & Emery LLP

20070235770 - Semiconductor structure and fabricating method thereof: A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor... Agent: J.c. Patents, Inc.

20070235769 - Structure and method for thermally stressing or testing a semiconductor device: A structure is provided which includes at least one semiconductor device and a diffusion heater in a continuous active semiconductor area of a substrate. One or more semiconductor devices are provided in a first region of the active semiconductor area and a diffusion heater is disposed adjacent thereto which consists... Agent: International Business Machines Corporation Dept. 18g

20070235771 - Semiconductor image sensor and method for fabricating the same: A semiconductor image sensor and a method for fabricating the same are described. The semiconductor image sensor includes a substrate having at least a photoactive region therein and an IR cutting layer over the photoactive region.... Agent: J.c. Patents, Inc.

20070235772 - Field emitter array with split gates and method for operating the same: Field emitter arrays with split gates and methods for operating the same. A field emitter array may include one or more pairs of split gates, each connected to a corresponding voltage source, the split gates forming at least one gate hole for at least one emitter tip. Voltages, for example,... Agent: Harness, Dickey & Pierce, P.L.C

20070235773 - Gas-sensitive field-effect transistor for the detection of hydrogen sulfide: A gas-sensitive field-effect transistor (GasFET) for the detection or measurement of an amount of hydrogen sulfide present in ambient air includes a raised gate electrode and a transistor structure. The raised gate electrode may be formed from or coated with a gas-sensitive material such as tin oxide, or silver, silver... Agent: O'shea, Getz & Kosakowski, P.C.

20070235774 - Chip scale surface mount package for semiconductor device and process of fabricating the same: A semiconductor package with contacts on both sides of the dice on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice expose the metal plate without extending through the metal plate. A metal layer may be formed on... Agent: Murabito Hao & Barnes LLP

20070235778 - Semiconductor device having bulb-shaped recess gate and method for fabricating the same: A semiconductor device includes: a substrate; a first junction region and a second junction region formed separately from each other in the substrate; an etch barrier layer formed in the substrate underneath the first junction region; and a plurality of recess channels formed in the substrate between the first junction... Agent: Blakely Sokoloff Taylor & Zafman

20070235777 - Thin film transistor, manufacturing method thereof, and active matrix display apparatus: A thin film transistor includes a metal substrate, a first conductive barrier layer placed on the metal substrate to prevent diffusion of substance of the metal substrate, a protective insulating film placed on the first conductive barrier layer, a semiconductor layer placed on the protective insulating film and including a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070235776 - Forming memory arrays: Source strap cells which are manufactured in a very similar way to conventional memory cells may be utilized to enable connections to the source of a memory cell. In other words, the source and the drain may be contacted by vias which are arranged identically in some embodiments. This may... Agent: Trop Pruner & Hu, PC

20070235775 - High efficiency and/or high power density wide bandgap transistors: Field effect transistors having a power density of greater than 40 W/mm when operated at a frequency of at least 4 GHz are provided. The power density of at least 40 W/mm may be provided at a drain voltage of 135 V. Transistors with greater than 60% PAE and a... Agent: Myers Bigel Sibley & Sajovec

20070235779 - Lateral dmos transistor and method for the production thereof: A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20070235780 - Body potential imager cell: An imaging circuit, an imaging sensor, and a method of imaging. The imaging cell circuit including one or more imaging cell circuits, each imaging cell circuit comprising: a transistor having a floating body for holding charge generated in the floating body in response to exposure of the floating body to... Agent: Schmeiser, Olsen & Watts

20070235781 - Solid state image pickup device: P type semiconductor well regions 8 and 9 for device separation are provided in an upper and lower two layer structure in conformity with the position of a high sensitivity type photodiode PD, and the first P type semiconductor well region 8 at the upper layer is provided in the... Agent: Robert J. Depke Lewis T. Steadman

20070235782 - Ferroelectric memory and its manufacturing method: To securely prevent hydrogen from entering a ferroelectric layer of a ferroelectric memory. A first hydrogen barrier layer 5 is formed on the lower side of ferroelectric capacitors 7. Upper surfaces and side surfaces of the ferroelectric capacitors 7 are covered by a second hydrogen barrier layer. All upper electrodes... Agent: Oliff & Berridge, PLC

20070235783 - Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The bottom portions can... Agent: Wells St. John P.s.

20070235784 - Three-terminal cascade switch for controlling static power consumption in integrated circuits: A switching circuit configured for controlling static power consumption in integrated circuits includes a plurality of three-terminal, phase change material (PCM) switching devices connected between a voltage supply terminal and a corresponding sub-block of integrated circuit logic. Each of the PCM switching devices further includes a PCM disposed in contact... Agent: Cantor Colburn LLP-ibm Yorktown

20070235785 - Semiconductor device and method of fabricating the same: A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double... Agent: Marger Johnson & Mccollom, P.C.

20070235787 - Capacitor device having three-dimensional structure: A capacitor device having a three-dimensional structure includes: a lower electrode formed on a semiconductor substrate to have a three-dimensional shape; a capacitor insulating film formed to cover the lower electrode and made of a ferroelectric material; and an upper electrode formed on the capacitor insulating film to have a... Agent: Mcdermott Will & Emery LLP

20070235786 - Storage capacitor and method for producing such a storage capacitor: A storage capacitor, particularly for use in a storage cell, exhibits two storage electrodes and a dielectric arranged between the two storage electrodes, an intermediate layer essentially consisting of carbon.... Agent: Morrison & Foerster LLP

20070235788 - Poly-insulator-poly capacitor and fabrication method for making the same: A poly-insulator-poly (PIP) capacitor includes a first polysilicon plate; a first capacitor dielectric layer disposed on the first polysilicon plate; a second polysilicon plate stacked on the first capacitor dielectric layer, wherein the first polysilicon plate, the first capacitor dielectric layer, and the second polysilicon plate constitute a lower capacitor;... Agent: North America Intellectual Property Corporation

20070235790 - Capacitor structure of semiconductor device and method of fabricating the same: A semiconductor device having superior capacitance may include interconnections formed on a semiconductor substrate, an interlayer insulation layer on the interconnections and having vias exposing a portion of the top surface of the interconnections, a capacitor which may be on the interlayer insulation layer and having a bottom electrode, a... Agent: Lee & Morse, P.C.

20070235789 - Hybrid electrical contact: Techniques for manufacturing an electronic device. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact... Agent: Fletcher Yoder (micron Technology, Inc.)

20070235791 - Display device and method of fabricating the same: A display device and a method of fabricating the same, the display device including a first substrate having a display region, a light emitting layer disposed within the display region, a first voltage pad disposed outside the display region, on the first substrate outside of the display region and supplying... Agent: Cantor Colburn, LLP

20070235793 - Nonvolatile semiconductor memory device: It is an object to provide a nonvolatile semiconductor memory device having excellent writing property and charge-retention property. A semiconductor layer including a channel forming region between a pair of impurity regions which are formed to be apart from each other is provided. In an upper layer portion thereof, a... Agent: Eric Robinson

20070235794 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device which is superior in writing property and charge holding property, including a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions, and a first insulating layer, a floating gate, a second insulating layer, and a control gate over... Agent: Eric Robinson

20070235795 - Ferroelectric storage device and manufacturing method thereof: According to an aspect of the embodiment, there is provided a ferroelectric storage device including: a plurality of memory cells repeatedly arranged in a predetermined direction, each memory cell including a ferroelectric film divided for each memory cell; and a word line formed on the ferroelectric film and shared by... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070235792 - Self-aligned, silicided, trench-based dram/edram processes with improved retention: A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond... Agent: Howard M Cohn Patent Attorney LLC

20070235798 - Method for forming self-aligned contacts and local interconnects simultaneously: The present invention relates generally to semiconductors, and more specifically to semiconductor memory device structures and an improved fabrication process for making the same. The improved fabrication process allows the self-aligned contacts and local interconnects to the processed simultaneously. The process allows the minimal distance requirement between the self-aligned contacts... Agent: Martine Penilla & Gencarella, LLP

20070235796 - P-type doped nanowire and method of fabricating the same: A p-type doped nanowire and a method of fabricating the same. The nanowire has a p-type doped portion which is formed by chemically binding a radical having a half-occupied outermost orbital shell to the corresponding portion of the nanowire, which corresponding portion of the nanowire donates an electron to the... Agent: Sughrue Mion, PLLC

20070235797 - Process for reducing a size of a compact eeprom device: The present invention is a method, and resulting device, for fabricating memory cells with an extremely small area. The small area requirement is met due primarily to two significant factors. First, a judicious use of spacers allows a control gate/wordline or select line to be fabricated in extremely close proximity... Agent: Schneck & Schneck

20070235799 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070235800 - Non-volatile memory device and method of manufacturing the same: A non-volatile memory device and a method of manufacturing the same, in which the program speed can be enhanced and the interference phenomenon can be reduced. The non-volatile memory device includes a semiconductor substrate having an active region defined by isolation layers arranged in one direction, a control gate arranged... Agent: Marshall, Gerstein & Borun LLP

20070235801 - Self-aligned body contact for a semicondcutor-on-insulator trench device and method of fabricating same: A structure and method of forming a body contact for an semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of... Agent: Schmeiser, Olsen & Watts

20070235802 - Method to control source/drain stressor profiles for stress engineering: An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain... Agent: William Stoffel

20070235803 - Display apparatus: A display apparatus includes a switching element having a first gate electrode, a source and drain electrode, a channel area formed between the source and drain electrode, and a second gate electrode. The second gate electrode is electrically insulated from the first gate electrode through the channel area, and different... Agent: Macpherson Kwok Chen & Heid LLP

20070235805 - Tft array substrate and method for manufacturing same: An exemplary TFT array substrate (200) includes a glass substrate (201); a source electrode (215), a channel (212), and a drain electrode (216) formed on the substrate, the channel being between the source electrode and the drain electrode; a gate insulating layer (203) formed on the channel; a gate electrode... Agent: Wei Te Chung Foxconn International, Inc.

20070235804 - Soi lateral semiconductor device and method of manufacturing the same: The SOI lateral semiconductor device includes a semiconductor region of a first conductivity type, a buried oxide film layer in the semiconductor region, a thin active layer on the buried oxide film layer, an anode region in the thin active layer, and a drain layer contacting the buried oxide film... Agent: Rossi, Kimms & Mcdowell LLP.

20070235806 - Integrated circuit chip with fets having mixed body thicknesses and method of manufacture thereof: An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20070235807 - Semiconductor device structure and method therefor: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially... Agent: Freescale Semiconductor, Inc. Law Department

20070235809 - Semiconductor device: A semiconductor device includes electrostatic protection circuit Q formed by connecting first NMOS transistor Q1 having first threshold voltage and second NMOS transistor Q2 having second threshold voltage lower than the first threshold voltage in parallel between power supply terminal N1 and ground terminal N2. Film thickness of gate insulating... Agent: Mcginn Intellectual Property Law Group, PLLC

20070235808 - Substrate-biased silicon diode for electrostatic discharge protection: An integrated circuit device that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, a first isolation structure formed inside the well region, a second isolation structure formed inside the well region and spaced apart from the first isolation structure, a dielectric layer formed over the well... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070235810 - Power semiconductor module and fabrication method: A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and... Agent: General Electric Company Global Research

20070235811 - Simultaneous conditioning of a plurality of memory cells through series resistors: Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070235812 - Semiconductor device and method for manufacturing the same: A semiconductor device operating at low voltage is provided where a threshold voltage is controlled with ease. A semiconductor substrate is element-isolated by element isolation regions. A source region and a source region are spaced from each other on the semiconductor substrate. A gate electrode is formed between the source... Agent: Mcdermott Will & Emery LLP

20070235815 - Cmos inverter layout for increasing effective channel length: Provided is a complementary metal oxide semiconductor (CMOS) inverter layout for increasing an effective channel length. The CMOS inverter layout may include first and second conductive MOS transistors respectively formed in first and second active regions, metal lines electrically connecting the first and second conductive MOS transistors, and one or... Agent: Harness, Dickey & Pierce, P.L.C

20070235814 - Gan-based semiconductor light-emitting device and method of manufacturing the same: A GaN-based semiconductor light-emitting device is provided having an improved structure in which the optical output and luminous efficiency are improved. The GaN-based semiconductor light-emitting device includes an n-electrode, a p-electrode, and an n-type semiconductor layer, an active layer and a p-type semiconductor layer, which are disposed between the n-electrode... Agent: Buchanan, Ingersoll & Rooney PC

20070235813 - Electronic device and a process for forming the electronic device: A process of forming an electronic device can include forming an insulating layer over first and second active regions, and a field isolation region. The process can also include forming a seed layer and exposing the first active region. The process can further include selectively forming a first and second... Agent: Larson Newman Abel Polansky & White, LLP

20070235816 - Single poly bicmos flash cell with floating body: A BiCMOS integrated circuit (IC) includes a floating gate-type non-volatile memory (NVM) device that uses the polycrystalline silicon gate of a CMOS FET and the P-base and N-emitter diffusions of a bipolar transistor to provide an isolated P-type body and N-type source/drain diffusions. The P-body diffusion of the NVM device... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20070235817 - Write margin improvement for sram cells with sige stressors: A semiconductor structure including SRAM cells with improved write margins and a method for forming the same are provided. The semiconductor structure comprises a substrate including a core circuit and an SRAM cell. The SRAM cell includes a pull-up PMOS device that comprises a first source/drain region in the substrate,... Agent: Slater & Matsil, L.L.P.

20070235818 - Dual-plane complementary metal oxide semiconductor: Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor. The device comprises a fin-type transistor on a bulk silicon substrate. The fin-type transistor comprises outer fin regions and a center semiconductor fin region, wherein the center fin region has a {110} crystalline oriented channel surface.... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070235819 - Semiconductor device and method for manufacturing the same: There is provided a semiconductor device including: convex semiconductor layers formed on a semiconductor substrate via an insulating film; gate electrodes formed on a pair of facing sides of the semiconductor layers via a gate insulating film; a channel region formed of silicon between the gate electrodes in the semiconductor... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070235820 - Manufacturing method of semiconductor device and semiconductor device: A method for manufacturing a semiconductor device including a semiconductor substrate, and a first electrode and a second electrode insulated from each other and formed in an upper side of the semiconductor substrate, wherein the method includes: forming the first electrode whose surface excluding its bottom surface is covered by... Agent: Birch Stewart Kolasch & Birch

20070235823 - Cmos devices with improved gap-filling: A semiconductor structure includes a substrate, and a first MOS device on the first region of the substrate wherein the first MOS device includes a first spacer liner. The semiconductor structure further includes a second MOS device on the second region wherein the second MOS device includes a second spacer... Agent: Slater & Matsil, L.L.P.

20070235822 - Semiconductor device with gate dielectric containing aluminum and mixed rare earth elements: A semiconductor device, such as a transistor or capacitor, is provided. The device includes a substrate, a gate dielectric over the substrate, and a conductive gate electrode film over the gate dielectric. The gate dielectric includes a mixed rare earth aluminum oxide, nitride or oxynitride film containing aluminum and at... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070235821 - Semiconductor device with gate dielectric containing mixed rare earth elements: A semiconductor device, such as a transistor or capacitor, is provided. The device includes a substrate, a gate dielectric over the substrate, and a conductive gate electrode film over the gate dielectric. The gate dielectric includes a mixed rare earth oxide, nitride or oxynitride film containing at least two different... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070235825 - Physical quantity sensor, method for manufacturing the same, and resin film for bonding semiconductor chip and circuit chip: A sensor includes: a semiconductor chip having a sensing portion and a first bump; a circuit chip having a second bump; and a resin film having a groove. The semiconductor chip and the circuit chip are integrated with sandwiching the resin film therebetween. The resin film includes a first space... Agent: Posz Law Group, PLC

20070235824 - Novel schottky barrier metal-germanium contact in metal-germanium-metal photodetectors: Metal-Semiconductor-Metal (“MSM”) photodetectors and methods to fabricate thereof are described. The MSM photodetector includes a thin heavily doped (“delta doped”) layer deposited at an interface between metal contacts and a semiconductor layer to reduce a dark current of the MSM photodetector. In one embodiment, the semiconductor layer is an intrinsic... Agent: Blakely Sokoloff Taylor & Zafman

20070235826 - Devices having horizontally-disposed nanofabric articles and methods of making the same: New devices having horizontally-disposed nanofabric articles and methods of making same are described. A discrete electro-mechanical device includes a structure having an electrically-conductive trace. A defined patch of nanotube fabric is disposed in spaced relation to the trace; and the defined patch of nanotube fabric is electromechanically deflectable between a... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070235827 - Method and apparatus providing isolation well for increasing shutter efficiency in global storage pixels: A pixel having a well-isolated charge storage region or floating diffusion region may be obtained by providing a separate P-well around the storage region or floating diffusion region. In one embodiment, a separate P-well entirely encases the storage region and is in contact with the storage region. This P-well provides... Agent: Dickstein Shapiro LLP

20070235828 - Semiconductor image sensor module, method for manufacturing the same as well as camera and method for manufacturing the same: A semiconductor image sensor module 1 at least includes a semiconductor image sensor chip 2 having a transistor forming region on a first main surface of a semiconductor substrate and having a photoelectric conversion region with a light incident surface formed on a second main surface on the side opposite... Agent: Robert J. Depke Lewis T. Steadman

20070235829 - Dark current reduction in back-illuminated imaging sensors and method of fabricating same: A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate, and resulting imaging device is disclosed. The device includes an insulator layer; a semiconductor substrate, having an interface with the insulator layer; an epitaxial layer grown on the semiconductor substrate by epitaxial growth; and one or more... Agent: Patent Docket Administrator Lowenstein Sandler P.C.

20070235830 - High-efficiency schottky rectifier and method of manufacturing same: A rectifier device (10) comprising a multi-layer epitaxial film (12) and a rectifier and a transistor manufactured in the film (12), wherein the transistor is oriented vertically relative to the plane of the rectifier. The rectifier and transistor are separated by a transition zone of inverted bias. The rectifier is... Agent: Spencer, Fane, Britt & Browne

20070235831 - Semiconductor structure for isolating integrated circuits of various operating voltages: A semiconductor structure for isolating a first circuit and a second circuit of various operating voltages includes a first isolation ring surrounding the first and second circuits on a semiconductor substrate. A buried layer continuously extending underneath the first and second circuits is formed on the semiconductor substrate, wherein the... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20070235832 - Ground layer of printed circuit board: A ground layer of a printed circuit board (PCB) includes a digital area, an analog area, and a connecting portion. The digital area is connected to the analog area via the connecting portion. The connecting portion with one end connected to the digital area, and the other end connected to... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070235834 - Method for the production of an electrical component and component: An electrical component includes a base body made using ceramic, metallization surfaces that at least partly define component structures on the base body, a passivation layer that is electrically insulating and over a surface of the base body, solder contacts on the passivation layer, and through-hole contacts inside the base... Agent: Fish & Richardson PC

20070235833 - Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures: Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures. The semiconductor structure comprises first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate bordering a sidewall of a trench. An intervening region of the semiconductor material... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20070235835 - Shallow trench isolation structure for semiconductor device: A semiconductor device provides a transistor adjacent an isolation trench. The device may be formed by producing isolation trenches in a semiconductor substrate, filling the trenches with a filler material, creating voids near top edges of the trenches and annealing by a gaseous ambient to reflow the edges of the... Agent: Mark J. Marcelli Duane Morris LLP

20070235836 - Method of forming a shallow trench isolation structure with reduced leakage current in a semiconductor device: A method for fabricating a shallow trench isolation structure for a subthreshold kink-free semiconductor memory device includes the steps of forming a nitride-oxide-nitride-oxide stack on top of a semiconductor substrate, etching shallow trenches in selected areas and filling them with an insulating material so that it is level with the... Agent: Schneck & Schneck

20070235837 - Semiconductor device having fuse element and method of cutting fuse element: A semiconductor device includes a lower electrode, an upper electrode, and a fuse element that connects the lower electrode and the upper electrode. Between the lower electrode and the upper electrode, insulating films stacked in this order exist. Out of the insulating films, the insulating film located in the middle... Agent: Young & Thompson

20070235838 - Flexible metal-oxide-metal capacitor design: A flexible scheme for forming a multi-layer capacitor structure is provided. The multi-layer capacitor structure includes a first electrode and a second electrode extending through at least one metallization layer, wherein the first electrode and the second electrode are separated by dielectric materials. In each of the metallization layers, the... Agent: Slater & Matsil, L.L.P.

20070235839 - Semiconductor devices utilizing algaasp: A method of minimizing stress within large area semiconductor devices which utilize a GaAs substrate and one or more thick layers of AlxGa1-xAs is provided, as well as the resultant device. In general, each thick AlxGa1-xAs layer within the semiconductor structure is replaced, during the structure's fabrication, with an AlxGa1-xAszP1-z... Agent: Patent Law Office Of David G. Beck

20070235840 - Method, system, and apparatus for filling vias: A method, system, and apparatus, the method including, in some embodiments, applying a via filling material in a film format and at a first temperature to a backside of a silicon wafer having a plurality of vias therein, heating the via filling material to a second temperature to cause the... Agent: Buckley, Maschoff & Talwalkar LLC

20070235841 - Silicon nanowire structure and method for making same: A silicon nanowire structure with controllable orientations is disclosed. The silicon nanowire structure includes a silicon wafer as a substrate having a crystal plane; a plurality of silicon nanowires extends from the silicon wafer along a plurality of oblique epitaxial <111> directions of the substrate. The silicon nanowires are in... Agent: Morris Manning Martin LLP

20070235842 - Semiconductor device and cutting equipment for cutting semiconductor device: A method for cutting a semiconductor device is provided. The device includes a first semiconductor layer, an insulation layer, and a second semiconductor layer. The method includes the steps of: forming a semiconductor part in the first semiconductor layer; irradiating a laser beam on a surface of the first semiconductor... Agent: Posz Law Group, PLC

20070235843 - Electronic device with selective nickel palladium gold plated leadframe and method of making the same: An electronic device comprises a leadframe attached to a die and embedded in a mold packaging with enhanced adhesion property. The leadframe comprises a bonding surface, a soldering surface, a mold adhesion surface, and a die attachment surface wherein the soldering surface and bonding surface are selectively plated with nickel/palladium/gold.... Agent: EagleIPLimited

20070235844 - Electronic device mounting structure and method of manufacturing the same: A mounting structure of an electronic device capable of properly enhancing a bonding strength between an insulating substrate and the electronic device is provided. An electrode and an earth electrode having a surrounding shape are formed on an insulating substrate. In addition, a non-metal area exposing a surface of the... Agent: Brinks Hofer Gilson & Lione

20070235845 - Apparatus, system and method for use in mounting electronic elements: The present embodiments provide surface mount devices and/or systems. In some embodiments, the surface mount devices comprise a casing with a recess in a second surface; a first lead element partially encased by the casing comprising a coupling portion extending interior to the casing generally in a first direction and... Agent: Sinsheimer Juhnke Lebens & Mcivor, LLP

20070235846 - Integrated circuit package system with net spacer: An integrated circuit package system that includes forming a strip level net spacer including support bars, tie bars and paddles. Configuring the support bars, the tie bars and the paddles to form open regions and interconnecting the support bars, the tie bars and the paddles to provide structural support to... Agent: Ishimaru & Zahrt LLP

20070235852 - Method and system for sealing packages for optics: A system for wafer-level packaging of a plurality of MEMS devices includes a substrate having a plurality of individual chips. Each of the plurality of individual chips includes a plurality of MEMS devices and each of the plurality of individual chips is arranged in a spatial manner as a first... Agent: Townsend And Townsend And Crew, LLP

20070235847 - Method of making a substrate having thermally conductive structures and resulting devices: Embodiments of a method of fabricating a substrate including thermally conductive structures, as well as devices made from such a substrate, are disclosed. Each thermally conductive structure includes a via and a number of carbon nanotubes formed within the via. An active circuit element disposed on the substrate may at... Agent: Intel Corporation C/o Intellevate, LLC

20070235850 - Packaged system of semiconductor chips having a semiconductor interposer: A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the second surface, with terminals and attached non-reflow metal studs (215) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components... Agent: Texas Instruments Incorporated

20070235851 - Point-to-point connection topology for stacked devices: The point-to-point interconnection system for stacked devices includes a device, a substrate, operational circuitry, at least three electrical contacts and a conductor. The substrate has opposing first and second surfaces. A first electrical contact is mechanically coupled to the first surface of the device and electrically coupled to the operational... Agent: Morgan Lewis & Bockius LLP/rambus Inc.

20070235849 - Semiconductor package and method using isolated vss plane to accommodate high speed circuitry ground isolation: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.... Agent: Lsi Corporation

20070235848 - Substrate having conductive traces isolated by laser to allow electrical inspection: A semiconductor die substrate panel, and method of forming same, are disclosed wherein plating bars are severed for example by a laser after electroplating of the substrate. Severing the plating bars allows electrical testing of the substrate prior to attachment of electronic components.... Agent: Vierra Magen/sandisk Corporation

20070235853 - Chip package structure: A chip package structure including a substrate, a first chip and a second chip is provided. The first contacts and the second contacts of the substrate are respectively arranged to reside on a first side region and a second side region of the substrate. The first chip disposed on the... Agent: J.c. Patents, Inc.

20070235854 - Integrated circuit package system with ground ring: An integrated circuit package system is provided forming a ring above a paddle and an external interconnect, mounting an integrated circuit die on the paddle, connecting the integrated circuit die and the external interconnect, the external interconnect and the ring, and the ring and the integrated circuit die, and encapsulating... Agent: Ishimaru & Zahrt LLP

20070235855 - Methods and apparatus for a reduced inductance wirebond array: A wirebond array (100) comprising a plurality of signal wires 110 and a plurality of ground wires (120) interdigitated with and substantially parallel to the set of signal wires (110). In one embodiment, each of the plurality of signal wires (110) and ground wires (120) is attached to a first... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070235856 - Substrate for a microelectronic package and method of fabricating thereof: Substrates having molded dielectric layers and methods of fabricating such substrates are disclosed. The substrates may advantageously be used in microelectronic assemblies having high routing density.... Agent: Tessera Lerner David Et Al.

20070235857 - Semiconductor device having an adhesion promoting layer and method for producing it: A semiconductor device and a method for producing it is disclosed. In one embodiment, an adhesion-promoting layer having nanoparticles is arranged between a circuit carrier and a plastic housing composition for the purpose of enhanced adhesion.... Agent: Dicke, Billig & Czaja

20070235858 - Mounting assembly for semiconductor devices: A mounting assembly for mounting a semiconductor device includes a package bonded to the semiconductor device via a bonding material, and a lid fixed to the package via a sealing member. A space is defined by the package, the lid and the sealing member to contain the semiconductor device, and... Agent: Scully, Scott, Murphy & Presser

20070235859 - Integrated circuit package system with heatspreader: An integrated circuit package system includes providing a substrate having an integrated circuit, attaching a heatspreader having a force control protrusion on the substrate, and forming an encapsulant over the heatspreader and the integrated circuit.... Agent: Ishimaru & Zahrt LLP

20070235860 - Power semiconductor module with flush terminal elements: A power semiconductor module includes a housing, terminal elements leading to the outside of the housing, an electrically insulated substrate arranged inside the housing, with the substrate being comprised of an insulating body and having on the first main face facing away from the base plate a plurality of connecting... Agent: Lackenbach Siegel, LLP

20070235861 - Semiconductor device package with a heat sink and method for fabricating the same: A semiconductor package with a heat sink and a method for fabricating the same are proposed. A first adhesive of a low Young's modulus is disposed on a corner region of a heat sink mounting area of a substrate. A second adhesive of a high Young's modulus is disposed on... Agent: Edwards Angell Palmer & Dodge LLP

20070235862 - Hybrid flip-chip and wire-bond connection package system: A hybrid flip chip and wire bond semiconductor connection package for an integrated circuit. The hybrid package includes a package substrate, a plurality of flip chip pads, and a plurality of wire-bond pads. The package substrate has at least one void or opening with a top side and a bottom... Agent: Duane Morris LLPIPDepartment (tsmc)

20070235863 - Led chip array module: The difficulties encountered in conventional LED multiple chip modules where wire bonding is used to connect the chips to electrodes can be overcome by using an interconnect to connect the chip to electrodes in a module where the interconnect is supported at points along its length other than at endpoints... Agent: Davis Wright Tremaine LLP

20070235865 - Semiconductor module havingdiscrete components and method for producing the same: The invention relates to a semiconductor module comprising stacked discrete components and a method for producing the same. In one embodiment, the semiconductor module has a semiconductor chip arranged on a wiring substrate. The discrete components are arranged and wired on an intermediate carrier, which is electrically connected to the... Agent: Dicke, Billig & Czaja

20070235864 - Single package wireless communication device: A method, apparatus and system with an autonomic, self-healing polymer capable of slowing crack propagation within the polymer and slowing delamination at a material interface.... Agent: Intel Corporation C/o Intellevate, LLC

20070235867 - Field effect transistor with interleaved layout: According to one embodiment of the present invention, a power amplifier with an interleaved layout is described. The power amplifier can be a monolithic microwave integrated circuit that includes a first transistor structure (e.g., a power transistor) and a second transistor structure that acts as a current reference. The first... Agent: Agilent Technologies Inc.

20070235866 - Housing for accommodating microwave devices: A housing for accommodating a microwave device, including: a metallic base member having a lower portion, and having a top and bottom surface, a central pedestal member extending from the top surface, the pedestal member having a device top surface for accommodating the microwave device; an insulator cup member having... Agent: Plevy, Howard & Darcy, P.C.

20070235868 - Protective covers for gas sensor, gas sensor and gas sensor manufacturing method: A gas sensor comprises a cylindrical metallic housing, a sensor element having at a front end thereof a sensing portion and disposed axially in the housing with the sensing portion protruded from a front end of the housing, a sensor terminal fitted to a rear end of the sensor element... Agent: Sughrue Mion, PLLC

20070235870 - Common assembly substrate and applications thereof: A common assembly substrate for carrying a die and applying the mechanisms are provided, wherein the common assembly substrate comprises a plurality of bonding fingers formed on one side of the substrate. A bonding wire is used to electrically connect the die with one of the bonding fingers, wherein at... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070235869 - Integrated circuit package system with wire bond pattern: An integrated circuit package system including providing a plurality of substantially identical package leads formed in a single row, and attaching bond wires having an offset on adjacent locations of the package leads.... Agent: Ishimaru & Zahrt LLP

20070235871 - High frequency ic package and method for fabricating the same: A high frequency IC package mainly includes a substrate, a bumped chip, and a plurality of conductive fillers where the substrate has a plurality of bump holes penetrating from the top surface to the bottom surface. The active surface of the chip is attached to the top surface of the... Agent: Troxell Law Office PLLC

20070235873 - Pad structures and methods for forming pad structures: Pad structures and methods for forming such pad structures are provided. For the pad structure, the first conductive material layer has a first hardness over about 200 kg/mm2. The second conductive material layer is over the first conductive material layer and has a second hardness over about 80 kg/mm2. For... Agent: Duane Morris LLPIPDepartment (tsmc)

20070235874 - Semiconductor integrated circuit device: A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner... Agent: Fitzpatrick Cella Harper & Scinto

20070235872 - Semiconductor package structure: A semiconductor package structure includes a semiconductor chip on which an electrical connection region having a plurality of chip bonding pads and a non-electrical connection region are defined, a substrate having a plurality of substrate bonding pads respectively corresponding to the chip bonding pads on a surface facing the semiconductor... Agent: North America Intellectual Property Corporation

20070235877 - Integration scheme for semiconductor photodetectors on an integrated circuit chip: A semiconductor device is described with a photodetector embedded within and a method of manufacturing the same. The photodetector may be formed above the conductive layers within the device and may detect transmitted light from the top side of the device. The process of manufacturing the device may include a... Agent: Intel Corporation C/o Intellevate, LLC

20070235875 - Low leakage metal-containing cap process using oxidation: An interconnect structure which includes a metal-containing cap located atop each conductive feature that is present within a dielectric material is provided in which a surface region of the metal-containing cap is oxidized prior to the subsequent deposition of any other dielectric material thereon. Moreover, metal particles that are located... Agent: Scully, Scott, Murphy & Presser, P.C.

20070235876 - Method of forming an atomic layer thin film out of the liquid phase: A method of processing a substrate is described. A coupling agent and a metal ion solution are applied to the substrate. An activating solution is applied to activate metal ions of the metal ion solution to create a metal film out of the ions.... Agent: Blakely Sokoloff Taylor & Zafman

20070235879 - Hybrid stacking package system: A hybrid stacking package system is provided including providing a board-on-chip substrate, having an opening, attaching a first integrated circuit on the board-on-chip substrate, attaching bond wires, between the first integrated circuit and the board-on-chip substrate, through the opening, and mounting a second integrated circuit over the bond wires.... Agent: Ishimaru & Zahrt LLP

20070235878 - Integrated circuit package system with post-passivation interconnection and integration: An integrated circuit package system is provided providing an integrated circuit die having a final metal layer of the semiconductor process used to manufacture the integrated circuit die and a passivation layer provided thereon, depositing a first metal layer on the passivation layer and the final metal layer, forming an... Agent: Ishimaru & Zahrt LLP

20070235880 - Semiconductor device and method of fabricating the same: A semiconductor device including a composite structure and a contact is provided. The composite structure includes a bottom electrode, an insulating layer, and an upper electrode from bottom to top. The contact electrically connects the upper electrode and the bottom electrode. The composite structure is used as a resistor, and... Agent: Jianq Chyun Intellectual Property Office

20070235881 - Semiconductor device and method of manufacturing the same, circuit board and electronic device: A semiconductor device includes a wiring board having a wiring pattern, a semiconductor chip that has an integrated circuit and is mounted on a first surface of the wiring board to electrically connect with the wiring pattern, a spacer that is disposed on a second surface of the wiring board... Agent: Hogan & Hartson L.L.P.

20070235882 - Semiconductor device and method for fabricating the same: A semiconductor device includes a semiconductor substrate with an electrode pad on a main surface of the semiconductor substrate; a first penetrating electrode which includes a through hole formed through the semiconductor substrate in the thickness direction so as to reach a metallic bump formed on the electrode pad, an... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070235883 - Combined semiconductor apparatus and a fabricating method thereof: A semiconductor apparatus includes two thin semiconductor films bonded to a substrate, and a thin-film interconnecting line electrically connecting a semiconductor device in the first thin semiconductor film to an integrated circuit in the second thin semiconductor film. The two thin semiconductor films are formed separately from the substrate. The... Agent: Rabin & Berdo, PC

20070235885 - Semiconductor device: A semiconductor device, which is constituted in such a way that a pad portion of a logic chip is connected to an element region of a semiconductor chip with a bump bonding, is capable of achieving high speed operability of the elements, because delay of transmission of an electrical signal... Agent: Young & Thompson

20070235884 - Surface structure of flip chip substrate: A flip chip substrate comprises a substrate that is defined a chip connect zone which has a plurality of first conductive pads and passive component connect zone which has at least a second conductive pads. A first patterned insulating layer within opening that covers on the chip connect zone and... Agent: North America Intellectual Property Corporation

20070235886 - Semiconductor die packages using thin dies and metal substrates: A semiconductor die package is disclosed. The semiconductor die package comprises a metal substrate, and a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, and at least one aperture. The metal substrate is attached to the second surface. A... Agent: Townsend And Townsend And Crew, LLP

20070235888 - Film type package and display apparatus having the same: A film type package includes a base film, a driving integrated circuit mounted on the base film for inputting/outputting signals to/from external circuits, a plurality of signal lines formed on the base film for transmitting the signals between the external circuits and the driving integrated circuit, a plurality of bonding... Agent: F. Chau & Associates, LLC

20070235887 - Bonding wire and integrated circuit device using the same: f

20070228357 - Technique for providing stress sources in mos transistors in close proximity to a channel region: A strained semiconductor material may be positioned in close proximity to the channel region of a transistor, such as an SOI transistor, while reducing or avoiding undue relaxation effects of metal silicides and extension implantations, thereby providing enhanced efficiency for the strain generation.... Agent: Williams, Morgan & Amerson

20070228368 - Functional device: A functional device having, on a substrate, a pair of electrodes, a functional layer which is sandwiched between the electrodes and has an output that varies in accordance with an applied electric current, and a terminal arranged to apply an electric current to at least one of the electrodes, wherein... Agent: Birch Stewart Kolasch & Birch

20070228367 - Multicolor organic light emitting apparatus: Provided is a multicolor organic light emitting apparatus having a plurality of organic light emitting devices formed on a substrate, for emitting two or more types of luminescent colors. A thickness of a layer formed between a light emitting layer and a reflection surface of a cathode is the same... Agent: Fitzpatrick Cella Harper & Scinto

20070228365 - Organic anti-reflective coating polymer, organic anti-reflective coating composition comprising the coating polymer and method for forming photoresist pattern using the coating composition: wherein R is hydrogen or methyl, R1-R9 are each independently hydrogen, C1-C6 linear or branched alkyl, hydroxy, alkoxyalkyl, methoxycarbonyl, carboxyl, or hydroxymethyl, 1 is 1 or 2, m is 2, 3, or 4, and x, y, and z are each independently from 0.05 to 0.95.... Agent: Marshall, Gerstein & Borun LLP

20070228376 - Top-gate thin-film transistors using nanoparticles and method of manufacturing the same: The present invention relates to a method of manufacturing thin-film transistors using nanoparticles and thin film transistors manufactured by the method. A hydrophilic buffer layers are deposited on the substrates to facilitate formation of nanoparticle films. Sintered nanoparticles are used as an active layer and dielectric materials of high dielectric... Agent: Morgan & Finnegan, L.L.P.

20070228377 - Semiconductor device comprising soi transistors and bulk transistors and a method of forming the same: By forming bulk-like transistors in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by... Agent: J. Mike Amerson, Williams, Morgan & Amerson, P.C.

20070228379 - E-ink display panel and active device array substrate thereof: An E-ink display panel including an active device matrix substrate, an opposite substrate and a display medium is provided. The active device matrix substrate includes pixel structures disposed thereon, and each pixel structure includes a bottom-gate thin film transistor and a pixel electrode. The pixel electrode disposed on the dielectric... Agent: Sheehan Phinney Bass & Green, PA C/o Peter Nieves

20070228381 - Liquid crystal cell assembly and liquid crystal cell manufacturing method: A liquid crystal cell assembly includes a first substrate member on which at least first electrodes are formed on each of cell regions which respectively correspond to liquid crystal cells and are arranged to be adjacent to each other, a second substrate member on which at least a second electrode... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070228380 - Organic light-emitting device: An organic light-emitting device includes an electron injection layer and an element isolation layer. The electron injection layer contains at least one of an alkali metal, an alkaline earth metal, an alkali metal compound, or an alkaline earth metal compound. A layer having the same composition of the electron injection... Agent: Fitzpatrick Cella Harper & Scinto

20070228393 - Light emitting device and fabrication method thereof: A light emitting device which includes: a substrate; an n-type semiconductor layer which is composed of a nitride semiconductor, formed on the substrate and has an n-side electrode; a p-type semiconductor layer which is composed of a nitride semiconductor, and stacked above the n-type semiconductor layer; a light emitting layer... Agent: Squire, Sanders & Dempsey L.L.P.

20070228388 - Nitride-based semiconductor light emitting diode: A nitride-based semiconductor LED comprises a substrate; an n-type nitride semiconductor layer formed on the substrate; an active layer formed on a predetermined region of the n-type nitride semiconductor layer; a p-type nitride semiconductor layer formed on the active layer; a transparent electrode formed on the p-type nitride semiconductor layer;... Agent: Mcdermott Will & Emery LLP

20070228394 - Semiconductor layer, process for forming the same, and semiconductor light emitting device: A semiconductor layer contains, as a principal constituent, a Group III-V semiconductor compound, which may be represented by the general formula: AlxGayInzN, wherein x represents a number satisfying the condition 0≦x<1, y represents a number satisfying the condition 0<y<1, and z represents a number satisfying the condition 0<z<1, with the... Agent: Sughrue Mion, PLLC

20070228390 - Semiconductor light-emitting device: A light-emitting device is provided, which includes a substrate having a plane surface, a semiconductor light-emitting element mounted on the plane surface of the substrate and which emits light in a range from ultraviolet ray to visible light, a first light transmissible layer formed above the substrate and covering the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070228392 - Semiconductor radiation source and light curing device: A semiconductor radiation source has a base body on which at least two LED chips are directly mounted and are fitted to the base body using a thermally conductive connection. At least one printed circuit board is mounted on the base body and extends from the centrally arranged LED chips... Agent: John C. Thompson

20070228389 - Thin film transistor array substrate and electronic ink display device: A thin film transistor (TFT) array substrate including a substrate, multiple scan lines, multiple data lines and multiple pixel units is provided. Each pixel unit includes a TFT and a pixel electrode. The pixel electrode is disposed above the TFT and electrically connected thereto. The TFT includes a first gate... Agent: Sheehan Phinney Bass & Green, PA C/o Peter Nieves

20070228396 - Light emitting unit and lighting apparatus: A light emitting unit, comprises: a light emitting element; a plurality of lead frames to which said light emitting element is electrically connected; and a package in which said lead frames are inserted so that at least one end thereof protrudes, and on which a light emitting window is arranged... Agent: GlobalIPCounselors, LLP

20070228397 - Led array, led head and image recording apparatus: An LED array includes a semiconductor substrate and a plurality of first LED portions formed integrally on a surface of the semiconductor substrate. The first LED portions emit light of a predetermined color. The LED array includes a plurality of second LED portions fixed to the semiconductor substrate and are... Agent: Rabin & Berdo, PC

20070228399 - Full-color organic el panel: A full-color organic electroluminescent panel has red (R), green (G), and blue (B) color pixels that independently emit light. The organic electroluminescent panel includes a hole-injecting layer common to the red (R), green (G), and blue (B) color pixels and a plurality of hole-transporting layers. The hole-transporting layer in at... Agent: Fitzpatrick Cella Harper & Scinto

20070228400 - Gan crystal substrate: A GaN crystal substrate has a crystal growth surface on which a crystal is grown, and a rear surface opposite to the crystal growth surface. The crystal growth surface has a roughness Ra(C)of at most 10 nm, and the rear surface has a roughness Ra(R) of at least 0.5 μand... Agent: Mcdermott Will & Emery LLP

20070228401 - Semiconductor device: A semiconductor device having: a substrate; nitride-based compound semiconductor layers formed on one main surface of the substrate and made of a nitride-based compound semiconductor; a first electrode formed on the nitride-based compound semiconductor layers and having a Schottky junction with the nitride-based compound semiconductor layers; and a second electrode... Agent: Howard & Howard Attorneys, P.C.

20070228403 - Micro-element package module and manufacturing method thereof: A micro-element package module which can reduce manufacturing costs and can be advantageous for mass production due to simplifying its structure and manufacturing process, and also can facilitate miniaturization and promote thinness, and a method of manufacturing the micro-element package module. The micro-element package module includes: an element substrate having... Agent: Sughrue Mion, PLLC

20070228405 - Electronic component and electronic component module: An electronic component includes an electronic element, a conductive first base portion, a conductive second base portion, an insulator and a terminal. An electronic element is to be mounted on the electronic element mounting portion. The electronic element mounting portion is mounted on the first base portion. The insulator insulates... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070228353 - Electronic crossbar system for accessing arrays of nanobatteries for mass memory storage and system power: A sequence or array of electrochemical cells storing both digital and analog data. Both binary code and codes having base may be stored in the memory device to increase information density. Such battery arrays could also provide power for the micro or nanodevice. Devices are microscale and nanoscale in size... Agent: Head, Johnson & Kachigian

20070228354 - Nonvolatile rewritable memory cell comprising a resistivity-switching oxide or nitride and an antifuse: A memory cell is described, the memory cell comprising a dielectric rupture antifuse and a layer of a resistivity-switching material arranged electrically in series, wherein the resistivity-switching material is a metal oxide or nitride compound, the compound including exactly one metal. The dielectric rupture antifuse is ruptured in a preconditioning... Agent: Patent Dept., Sandisk Corporation

20070228355 - Terahertz wave radiating device: Provided is a terahertz (THz) wave radiating device that radiates electromagnetic wave in a THz range, the device including: an anode electrode layer; a cathode electrode layer which forms a pair with the anode electrode layer; an electrical insulating layer (i) which is positioned between the anode electrode layer and... Agent: Greenblum & Bernstein, P.L.C

20070228356 - Organic-inorganic composite semiconductor material, liquid material, organic light emitting element, method of manufacturing organic light emitting element, light emitting device and electronic apparatus: o

20070228358 - Single photon receptor: A photon receptor having a sensitivity threshold of a single photon is readily fabricated on a nanometric scale for compact and/or large-scale array devices. The fundamental receptor element is a quantum dot of a direct semiconductor, as for example in a semiconductor (such as GaAs) isolated from a parallel or... Agent: Edward S. Sherman, Esq.

20070228361 - Carbon nanotube-solder composite structures for interconnects, process of making same, packages containing same, and systems containing same: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array is patterned by using a patterned metallic seed layer on the substrate to form the CNT array by... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070228364 - Compositions comprising novel copolymers and electronic devices made with such compositions: The present invention relates to novel copolymers, compositions comprising novel copolymers, and electronic devices comprising at least one layer containing the copolymer.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070228360 - Electronic devices containing acene-thiophene copolymers: Electronic devices that include an acene-thiophene copolymer and methods of making such electronic devices are described. The acene-thiophene copolymer can be used, for example, in a semiconductor layer or in a layer positioned between a first electrode and a second electrode.... Agent: 3m Innovative Properties Company

20070228366 - Method for purifying material comprising organic semiconductor, method for purifying material comprising pentacene, semiconductor device, and method for fabricating the semiconductor device: It is an object of the present invention to provide a simple method for purifying an organic semiconductor. It is another object of the invention to provide a semiconductor device having good characteristics. A method for purifying an organic semiconductor according to the invention includes a process of filtering a... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070228359 - Novel diketopyrrolopyrrole polymers: their use in electronic devices. The polymers according to the invention have excellent solubility in organic solvents and excellent film-forming properties. In addition, high charge carrier mobilities and high temperature stability of the emission color are observed, if the polymers according to the invention are used in polymer light emitting... Agent: Ciba Specialty Chemicals Corporation Patent Department

20070228362 - Organic light emitting element and display device using the element: A hole transporting region made of a hole transporting material, an electron transporting region made of an electron transporting material, and a mixed region (light emitting region) in which both the hole transporting material and the electron transporting material are mixed and which is doped with a triplet light emitting... Agent: Fish & Richardson P.C.

20070228363 - Polythiophenes and devices thereof: wherein A is a side chain; B is hydrogen or a side chain; and D is a divalent linkage, and wherein the number of A-substituted thienylene units (I) in the monomer segments is from about 1 to about 10, the number of B-substituted thienylene units (II) is from 0 to... Agent: Fay Sharpe / Xerox - Rochester

20070228369 - Substratum with conductive film and process for producing the same: The present invention provides a substratum with conductive film comprising a substratum and a conductive film containing tin-doped indium oxide as the main component, wherein a foundation film containing zirconium oxide doped with yttrium oxide as the main component is formed on the substratum side of the conductive film, and... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070228370 - Methods of programming non-volatile memory devices including transition metal oxide layer as data storage material layer and devices so operated: A method of programming a non-volatile memory device including a transition metal oxide layer includes applying a first electric pulse to the transition metal oxide layer for a first period to establish a resistance of the transition metal oxide layer and applying a second electric pulse to the transition metal... Agent: Myers Bigel Sibley & Sajovec

20070228371 - Method for evaluating semiconductor device: The present invention provides a method for evaluating an intended element or a parameter. In addition, the invention provides an evaluation method for obtaining a more precise result rapidly. According to the invention, a plurality of evaluation circuits are formed over the same substrate, and while simultaneously operating the plurality... Agent: Fish & Richardson P.C.

20070228372 - Method for fabricating a body contact in a finfet structure and a device including the same: A method for fabricating a Finfet device with body contacts and a device fabricated using the method are provided. In one example, a silicon-on-insulator substrate is provided. A T-shaped active region is defined in the silicon layer of the silicon-on-insulator substrate. A source region and a drain region form two... Agent: Haynes And Boone, LLP

20070228373 - Single-photon generator: A single-photon generator includes a single-photon generating device generating a single-photon pulse having a wavelength on the shorter wavelength side than a communication wavelength band, and a single-photon wavelength conversion device performing wavelength conversion of the single-photon pulse into a single-photon pulse of the communication wavelength band, using pump pulse... Agent: Kratz, Quintos & Hanson, LLP

20070228374 - Semiconductor device and method of fabricating the same: To provide a thin film transistor having a high field effect mobility and a small variation in characteristics thereof, a second amorphous semiconductor layer patterned in a predetermined shape is formed on a first crystalline semiconductor layer 17 for constituting source and drain regions. By irradiating an irradiated region 21... Agent: Eric Robinson

20070228375 - Multilayer information recording medium and method for manufacturing same: A method for manufacturing a multilayer information recording medium including at least two information recording layers and a resin layer disposed between the information recording layers that are adjacent to each other includes a first process of filling a resin-containing coating in openings of a screen, electrically charging one of... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070228382 - Light emitting device and manufacturing method thereof: A light emitting element having an organic compound, which can be extended its longevity is provided. According to the present invention, there is provided a constitution in which, in order to protect a light emitting element from moisture, an inorganic insulating film 312a, a stress relaxation layer 312b having transparency... Agent: Nixon Peabody, LLP

20070228378 - Method for producing ordered nanostructures: one or several steps of attacking the substrate (100), of which a preferential attack either of the crystalline defects and/or the stress fields, or the crystalline zone (13) between the crystalline defects and/or the stress fields, said attack steps enabling the barrier layer (2) to be laid bared locally and... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070228383 - 3-dimensional integrated circuit architecture, structure and method for fabrication thereof: An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device... Agent: Scully Scott Murphy & Presser, PC

20070228384 - Single-crystal layer on a dielectric layer: A system and method for producing a single-crystal germanium layer on a dielectric layer by producing a germanium-on-insulator assembly between the surface portions of the third material. The choice of location for these surface portions therefore makes it possible to define the zone on which it is desired to produce... Agent: Docket Clerk

20070228385 - Edge-emitting light emitting diodes and methods of making the same: An edge-emitting light emitting diode (EELED) and methods are described. The EELED includes contact layer, a first carrier confinement layer coupled to the contact layer, an active region optically coupled to the first carrier confinement layer. The active region includes an aluminum gallium nitride based material. Further, the EELED includes... Agent: General Electric Company Global Research

20070228391 - Light emitting device: A light emitting device has an LED (light emitting diode) element, and a power feeding member through which electrical power is fed to the LED element, the power feeding member comprising an electrically conductive material. The power feeding member has a light reflecting layer formed on the surface of the... Agent: Mcginn Intellectual Property Law Group, PLLC

20070228395 - Semiconductor light emitting element and method for fabricating the same: The semiconductor laser of this invention includes an active layer formed in a c-axis direction, wherein the active layer is made of a hexagonal-system compound semiconductor, and anisotropic strain is generated in a c plane of the active layer.... Agent: Ratnerprestia

20070228387 - Uniform emission led package: An emitter package comprising a light emitting diode (LED) mounted to the surface of a submount with the surface having a first meniscus forming feature around the LED. A matrix encapsulant is included on the surface and covering the LED. The outer edge of the matrix encapsulant adjacent the surface... Agent: Koppel, Patrick & Heybl

20070228386 - Wire-bonding free packaging structure of light emitted diode: A wire-bonding free packaging structure for light emitting diode (LED) is provided. Prepare a silicon sub-mount having a backside bulk micromachining reach-through U-shape cavity for accommodating a flip-chip LED. This stack-integrated packaging module with solder bumps on the surface is than bonded to an aluminum PC board with flip-chip surface... Agent: Perkins Coie LLP

20070228398 - Thin film transistor and display device using the same: A thin film transistor including an active layer formed on an insulating substrate and having channel, source, and drain regions formed therein; a gate electrode formed over the channel region of the active layer; source and drain electrodes respectively formed over the source and drain regions of the active layer;... Agent: Stein, Mcewen & Bui, LLP

20070228402 - Smt led with high light output for high power applications: A method and apparatus is described for a light-emitting diode with high light output. A polymeric cup to reflect light holds a light-emitting diode chip connected to surface-mounting leads and is filled with an optically clear filter. The use of a polymeric cup allows for better bonding between the cup... Agent: Kathy Manke Avago Technologies Limited

20070228404 - Systems and methods for producing white-light light emitting diodes: A vertical light emitting diode (LED) includes a metal substrate; a p-electrode coupled to the metal substrate; a p-contact coupled to the p-electrode; a p-GaN portion coupled to the p electrode; an active region coupled to the p-GaN portion; an n-GaN portion coupled to the active region; and a phosphor... Agent: Patterson & Sheridan, L.L.P.

20070228406 - Chip package structure and method for manufacturing bumps: A method for manufacturing bumps is provided. First, a first metal layer is formed on a substrate. Then, a patterned second metal layer is formed on the first metal layer. Then, flat bumps are formed on the second metal layer. Finally, the first metal layer is patterned to form bond... Agent: J.c. Patents

20070228407 - Group iii nitride semiconductor light emitting device: A Group III nitride semiconductor light emitting device having a light emitting layer (6) bonded to a crystal layer composed of an n-type or p-type Group III nitride semiconductor, the Group III nitride semiconductor light emitting device being characterized by comprising an n-type Group III nitride semiconductor layer (4) having... Agent: Sughrue Mion, PLLC

20070228408 - Semiconductor layer, process for forming the same, and semiconductor light emitting device: A semiconductor layer contains, as a principal constituent, a Groups III-V semiconductor compound, which may be represented by the general formula: BxAlyGazN, wherein x represents a number satisfying the condition 0<x<1, y represents a number satisfying the condition 0≦y<1, and z represents a number satisfying the condition 0<z<1, with the... Agent: Sughrue Mion, PLLC

20070228409 - Light emitting element, light emitting device using the light emitting element and method for manufacturing light emitting element: To provide a light emitting element that can extract substantially all the light emitted from a luminous layer structure to the outside, a GaN substrate and a luminous layer structure are formed by growing III nitride compound semiconductor on a sapphire substrate that is a growth substrate. Thereafter, the sapphire... Agent: Mcginn Intellectual Property Law Group, PLLC

20070228410 - Current-triggered low turn-on voltage scr: A system for protecting a high-speed input/output pad of an integrated circuit. The system includes a preferably parasitic silicon controlled rectifier (SCR) and a triggering mechanism that preferably includes an NMOS triggering FET. The SCR includes an anode connected to the input/output pad and a trigger input. The anode and... Agent: Dr. Mark M. Friedman C/o Bill Polkinghorn - Discovery Dispatch

20070228411 - Display substrate, method of manufacturing the same, display device having the display substrate and method of driving the display device: A display substrate includes a plurality of pixel parts, each including a first and second gate lines, a source line, first, second, and third transistors, and a pumping capacitor. A display device includes a display panel, a gate driving part, a source driving part, and an output selecting part. Each... Agent: Cantor Colburn, LLP

20070228412 - Low voltage triggering silicon controlled rectifier and circuit thereof: A low voltage triggering silicon controlled rectifier (LVTSCR) is disclosed. The LVTSCR utilizes an added resistor disposed in a second doped region between the anode of the LVTSCR and the emitter of the parasitical bipolar PNP transistor to increase the holding voltage thereof when the LVTSCR is triggered. The LVTSCR... Agent: John S. Egbert Egbert Law Offices

20070228413 - Semiconductor module: A semiconductor module having a current connection element designed for a high current carrying capability is disclosed. In one embodiment, the current connection element includes a plurality of metal layers which rest directly on one another.... Agent: Dicke, Billig & Czaja

20070228414 - Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride: In the present invention a metal oxide or nitride compound which is a wide-band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heterojunction. This p-n heterojunction can be used to advantage in various devices. In preferred embodiments, one... Agent: Patent Dept., Sandisk Corporation

20070228415 - Semiconductor device and manufacturing method thereof: A semiconductor device is configured so as to comprise a substrate, an n-type semiconductor layer or an undoped semiconductor layer on the substrate, and an ohmic electrode on the n-type semiconductor layer or the undoped semiconductor layer, and the ohmic electrode is configured so as to comprise a tantalum layer... Agent: Kratz, Quintos & Hanson, LLP

20070228416 - Monolithic integration of enhancement- and depletion-mode algan/gan hfets: A method for and devices utilizing monolithic integration of enhancement-mode and depletion-mode AlGaN/GaN heterojunction field-effect transistors (HFETs) is disclosed. Source and drain ohmic contacts of HFETs are first defined. Gate electrodes of the depletion-mode HFETs are then defined. Gate electrodes of the enhancement-mode HFETs are then defined using fluoride-based plasma... Agent: Groover & Holmes

20070228417 - Semiconductor device and method of fabricating the same: A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate through a gate insulating film; a source/drain region formed apart from the gate electrode; and a source/drain extension region formed between the gate electrode and the source/drain... Agent: Foley And Lardner LLP Suite 500

20070228418 - Aluminum alloys for low resistance, ohmic contacts to iii-nitride or compound semiconductor: A low contact resistance ohmic contact for a III-Nitride or compound semiconductor wafer or die consists of 4 layers of Ti, AlSi, Ti and TiW. The AlSi has about 1% Si. The layers are sequentially deposited as by sputtering, are patterned and plasma etched and then annealed in a rapid... Agent: Ostrolenk Faber Gerb & Soffen

20070228419 - Unit cell of semiconductor integrated circuit and wiring method and wiring program using unit cell: A unit cell of a semiconductor integrated circuit capable of improving wiring efficiency in layout of a functional circuit block or the like using a unit cell, and a wiring method and wiring program using the unit cell are provided. In a unit cell, auxiliary power wiring regions are formed... Agent: Arent Fox PLLC

20070228420 - Nonvolatile semiconductor memory device and manufacturing method thereof: A nonvolatile semiconductor memory device is provided in such a manner that a semiconductor layer is formed over a substrate, a charge accumulating layer is formed over the semiconductor layer with a first insulating layer interposed therebetween, and a gate electrode is provided over the charge accumulating layer with a... Agent: Eric Robinson

20070228422 - Monolithic integrated circuit of a field-effect semiconductor device and a diode: A field-effect semiconductor device such as a HEMT or MESFET is monolithically integrated with a Schottky diode for feedback, regeneration, or protection purposes. The field-effect semiconductor device includes a main semiconductor region having formed thereon a source, a drain, and a gate between the source and the drain. Also formed... Agent: Woodcock Washburn LLP

20070228421 - Semiconductor device using semiconductor nanowire and display apparatus and image pick-up apparatus using the same: A semiconductor device, comprising a semiconductor nanowire having a first region with one of a PN junction and a PIN junction and a second region with a field effect transistor structure, a pair of electrodes connected to both ends of the semiconductor nanowire, and a gate electrode provided in at... Agent: Morgan & Finnegan, L.L.P.

20070228423 - Imaging apparatus and radiation imaging system: This imaging apparatus has pixels arranged in a matrix shape on a substrate, each of which has a conversion element and the first TFT, wherein the first TFT is connected to the first gate wiring and signal wiring, and the conversion element is connected to bias wiring. The imaging apparatus... Agent: Fitzpatrick Cella Harper & Scinto

20070228424 - Semiconductor device and method of manufacturing the same: A semiconductor device includes: a first FET that is formed with first unit FETs each having a first finger electrode and a second finger electrode provided on either side of a gate finger electrode, the first unit FETs being connected in parallel; and a second FET that is formed with... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070228426 - Semiconductor device: A semiconductor device includes a substrate, a first gate electrode, a second gate electrode, a first channel region positioned between the substrate and the first gate electrode, a second channel region positioned between the substrate and the second gate electrode, a gate insulation film positioned at least between the first... Agent: Oliff & Berridge, PLC

20070228427 - Semiconductor memory device: HfO2 films and ZrO2 films are currently being developed for use as capacitor dielectric films in 85 nm technology node DRAM. However, these films will be difficult to use in 65 nm technology node or later DRAM, since they have a relative dielectric constant of only 20-25. The dielectric constant... Agent: Stanley P. Fisher Reed Smith LLP

20070228430 - Devices and methods of preventing plasma charging damage in semiconductor devices: Methods for protecting semiconductor devices from plasma charging damage are disclosed. An example disclosed method includes depositing an etching stop layer on a substrate with at least one predetermined structure; depositing a premetallic dielectric layer and a charge preservation layer on the entire surface of the etching stop layer; depositing... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070228428 - High-voltage metal-oxide-semiconductor device and method of manufacturing the same: The present invention pertains to a high-voltage MOS device. The high-voltage MOS device includes a substrate, a first well, a first field oxide layer enclosing a drain region, a second field oxide enclosing a source region, and a third field oxide layer encompassing the first and second field layers with... Agent: North America Intellectual Property Corporation

20070228425 - Method and manufacturing low leakage mosfets and finfets: By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief... Agent: Schneck & Schneck

20070228429 - Method of doping a gate electrode of a field effect transistor: A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface; forming an island on the top surface of the substrate, a top surface of the island parallel to the top... Agent: Schmeiser, Olsen & Watts

20070228431 - Semiconductor device and its manufacturing method: A semiconductor device is capable of maintaining its operation at a low-voltage and improving its operation speed prominently, even when thinning of a capacitor film is developed. In a capacitor formed on the upper side of a semiconductor substrate and composed of a ferroelectric film (capacitor film) sandwiched between an... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070228432 - Semiconductor element, semiconductor storage device using the same, data writing method thereof, data reading method thereof, and manufacturing method of those: The invention relates to a semiconductor element used for a nonvolatile semiconductor storage device or the like, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof and a manufacturing method of those, and has an object to provide a semiconductor element in... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070228436 - Arrangement of semiconductor memory devices and semiconductor memory module comprising an arrangement of semiconductor memory devices: An arrangement of semiconductor memory devices includes a first semiconductor memory device and a second semiconductor memory device. The arrangement of semiconductor memory devices also has a flexible substrate. A first electrically conductive conductor track is arranged in the flexible substrate. At least one first contact of the flexible substrate... Agent: Slater & Matsil LLP

20070228437 - Dram arrays, vertical transistor structures, and methods of forming transistor structures and dram arrays: The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars. After the etching, dopant is implanted within the trenches to... Agent: Wells St. John P.s.

20070228433 - Dram with nanofin transistors: One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070228439 - Large-area nanoenabled macroelectronic substrates and uses therefor: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor... Agent: Nanosys Inc.

20070228435 - Semiconductor device and fabrication thereof: A method for forming a semiconductor device is disclosed, in which a substrate comprising a recessed gate is provided, and a protrusion of the recessed gate protrudes a surface of the substrate. A spacer is formed on a sidewall of the protrusion of the recessed gate. A conductive structure is... Agent: Quintero Law Office, PC

20070228434 - Semiconductor memory device: A semiconductor memory device including a capacitor array having an effective size smaller than a minimum feature size of lithography is disclosed. According to one aspect of the present invention, it is provided a semiconductor memory device comprising a transistor including a gate electrode formed on a gate insulator on... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070228440 - Structure and fabrication method for capacitors integratible with vertical replacement gate transistors: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second... Agent: Agere Lerner, David Et Al.

20070228438 - Technique to control tunneling currents in dram capacitors, cells, and devices: Structures and methods are provided for the use with PMOS devices. Materials with large electron affinities or work functions are provided for structures such as gates. A memory cell is provided that utilizes materials with work functions larger than n-type doped polysilicon (4.1 eV) or aluminum metal (4.1 eV) for... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070228441 - Display device including thin film transistor: A flat panel display includes a gate line, a data line, and a power supply line and a plurality of pixels connected to the lines, wherein each of the pixels includes a first thin film transistor that includes an active layer having a channel region, a source region, and a... Agent: Stein, Mcewen & Bui, LLP

20070228442 - Thin film capacitor, method for forming same, and computer readable recording medium: In a thin film capacitor, reducing a leak current by suppressing concentration of an electric filed. Forming a zirconium oxide layer (26A) on a lower electrode (22) made of a conductive material. Forming a buffer layer (28) made of an amorphous material on the first zirconium oxide layer (26A). Forming... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070228443 - Conductive base material with thin film resistance layer, method of production of conductive base material with thin film resistance layer, and circuit board with thin film resistance layer: An inexpensive conductive base material with a thin film resistance layer having small variation of the sheet resistance value and a conductive base material with a resistance layer enabling production of a printed resistor circuit board by stably leaving behind resistance elements, that is, a conductive base material with a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070228445 - Non-volatile memory devices: Nonvolatile memory devices are provided. Devices include active regions that may be defined by device isolation layers formed on a semiconductor substrate and extend in a first direction. Devices may also include word lines that may cross over the active regions and extend in a second direction intersecting the first... Agent: Myers Bigel Sibley & Sajovec

20070228448 - Nonvolatile semiconductor memory device: It is an object to provide a nonvolatile semiconductor memory device with an excellent writing property and charge-retention property. A semiconductor layer including a channel forming region between a pair of impurity regions which are formed to be apart from each other is provided. In an upper layer portion thereof,... Agent: Eric Robinson

20070228446 - Semiconductor device and a method of manufacturing the same: A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is... Agent: Miles & Stockbridge PC

20070228447 - Semiconductor device and method for manufacturing the same: A semiconductor device including a semiconductor substrate, a tunnel insulation film provided on the surface of the semiconductor substrate, charge trap states at which an electron potential energy is higher than a Fermi level of the semiconductor substrate being provided at part of the tunnel insulation film at least in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070228444 - Semiconductor memory device having reference transistor and method of manufacturing the same: A semiconductor memory device has: a substrate; a memory cell transistor of a split-gate type formed on the substrate; and a reference transistor formed on the substrate and used for generating a reference current that is used in sensing data stored in the memory cell transistor. The memory cell transistor... Agent: Foley And Lardner LLP Suite 500

20070228449 - Nonvolatile semiconductor memory device: It is an object of the present invention to provide a nonvolatile semiconductor memory device which has superior writing characteristics and electric charge retention characteristics. In addition, it is an object of the present invention to provide a nonvolatile semiconductor memory device in which a writing voltage can be reduced.... Agent: Eric Robinson

20070228452 - Nonvolatile semiconductor storage device and method for manufacturing the same: It is an object to provide a nonvolatile semiconductor storage device that prevents increase in a contact resistance value due to etching of a semiconductor layer when etching an interlayer insulating film and that has superiority in a writing characteristic and an electric charge-holding characteristic, and a manufacturing method thereof.... Agent: Eric Robinson

20070228450 - Flash memory device with enlarged control gate structure, and methods of making same: Disclosed is a flash memory device with an enlarged control gate structure, and various methods of make same. In one illustrative embodiment, the device includes a plurality of floating gate structures formed above a semiconducting substrate, an isolation structure positioned between each of the plurality of floating gate structures and... Agent: Williams, Morgan & Amerson

20070228451 - Scalable electrically eraseable and programmable memory (eeprom) cell array: A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20070228453 - Nonvolatile semiconductor memory device: An object is to provide a nonvolatile semiconductor memory device which is superior in writing property and charge holding property. A semiconductor substrate in which a channel formation region is formed between a pair of impurity regions is provided, and a first insulating layer, a floating gate electrode, a second... Agent: Eric Robinson

20070228454 - Semiconductor memory device and method of manufacturing the same: The semiconductor memory device according to the present invention includes a charge storage layer 26 formed over a semiconductor substrate 10 and including a plurality of particles 16 as charge storage bodies in insulating films 12, 24, and a gate electrode 30 formed over the charge storage layer 26, in... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070228455 - Semiconductor device and manufacturing method thereof: In the memory array area of a semiconductor substrate, memory cells of a NAND flash memory are arranged in a matrix in the row direction and the column direction. A plurality of memory cells arranged in the row direction are mutually isolated by device isolation trenches having a thin strip... Agent: Miles & Stockbridge PC

20070228456 - Laminated memory having autonomically and sequentially activating operation: In a laminated memory, each of memory core layers includes a delay circuit having a period of delay time corresponding to a period of operation time of an internal memory circuit portion thereof. A memory core layer, which is input with a simultaneous operation signal, operates in response to the... Agent: Sughrue Mion, PLLC

20070228457 - Semiconductor device and method of manufacturing the same: A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of... Agent: Young & Thompson

20070228458 - Dual metal integration scheme based on full silicidation of the gate electrode: An integration scheme that enables full silicidation (FUSI) of the nFET and pFET gate electrodes at the same time as that of the source/drain regions is provided. The FUSI of the gate electrodes eliminates the gate depletion problem that is observed with polysilicon gate electrodes. In addition, the inventive integration... Agent: Scully Scott Murphy & Presser, PC

20070228461 - Semiconductor device with increased channel area and fabrication method thereof: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of... Agent: Townsend And Townsend And Crew, LLP

20070228460 - Contact plug structure and method for preparing the same: A contact plug structure for a checkerboard dynamic random access memory comprises a body portion, two leg portions connected to the body portion and a dielectric block positioned between the two leg portions. Each leg portion is electrically connected to a deep trench capacitor arranged in an S-shape manner with... Agent: Oliff & Berridge, PLC

20070228459 - Integrated semiconductor circuits and methods of making integrated semiconductor circuits: An integrated semiconductor circuit includes a substrate having a surface of a first semiconductor material, at least one separating material formed on the surface and defining a through hole, and a guide region formed in the hole. The guide region comprises at least one second semiconductor material. The guide region... Agent: Hewlett Packard Company

20070228462 - Power semiconductor device: A power semiconductor device includes: a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on a first semiconductor layer and alternately arranged along at least one direction parallel to an upper face of the first semiconductor layer; a fourth... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070228463 - Self-aligned complementary ldmos: The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown... Agent: Hiscock & Barclay, LLP

20070228464 - Mos transistor: A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region,... Agent: North America Intellectual Property Corporation

20070228468 - Grounding structure of semiconductor device: A circuit substrate of a grounding structure of a semiconductor device according to the invention has a plurality of connection pads and a grounding wiring. The semiconductor device has a semiconductor substrate having one side face and the other side face opposite thereto, an insulating film formed thereon, an SOI... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070228467 - Semiconductor storage device and method of fabrication thereof: A semiconductor storage device includes: a MOSFET formed on an SOI layer of the transistor forming region; and a MOS capacitor formed on the SOI layer of the capacitor forming region. The MOSFET includes: a gate insulating film formed; a floating gate electrode; a source layer and a drain layer... Agent: Volentine & Whitt PLLC

20070228465 - Improved soi substrate and soi device, and method for forming the same: An improved semiconductor-on-insulator (SOI) substrate is provided, which has a substantially planar upper surface and comprises at least first and second patterned buried insulator layers. Specifically, the first patterned buried insulator layer has a first thickness and is located in the SOI substrate at a first depth from the substantially... Agent: Scully Scott Murphy & Presser, PC

20070228466 - Pixel structure, thin film transistor array substrate and liquid crystal display panel: A pixel structure, suitable being driven by a scan line and a data line on a substrate, is provided. The pixel structure includes a thin film transistor (TFT) and a pixel electrode. Wherein, the TFT includes a gate, a first and a second dielectric layer, a semiconductor layer, a source,... Agent: J.c. Patents, Inc.

20070228469 - Thin-film transistor formed on insulating substrate: There is provided a thin-film transistor that is formed on an insulating substrate, is capable of a high-speed operation, has small non-uniformity among devices, is hardly susceptible to device destruction due to high voltage, and is free from the effect of a parasitic transistor that forms at an edge part... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070228470 - Apparatus for atomic layer deposition: The present invention provides a distribution manifold for thin-film material deposition onto a substrate comprising a plurality of inlet ports for a sequence of gaseous materials, an output face comprising a plurality of open elongated output channels, each channel extending in a length direction substantially in parallel. The distribution manifold... Agent: Paul A. Leipold Patent Legal Staff

20070228471 - Adjacent planar and non-planar thin-film transistor: A method is provided for concurrently forming MP-TFTs and P-TFTs. Generally, the method comprises: forming a P-TFT having source/drain (S/D) regions, an intervening channel region, and a gate, all in a first horizontal plane; and simultaneously forming a MP-TFT having a first gate in the first horizontal plane and at... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070228472 - Silicon device on si: c-oi and sgoi and method of manufacture: A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal... Agent: Greenblum & Bernstein, P.L.C

20070228473 - Ultra-thin si mosfet device structure and method of manufacture: The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a pad stack atop the SOI layer; forming a block mask having a... Agent: Scully, Scott, Murphy & Presser, P.C.

20070228475 - Esd protection circuit with isolated diode element and method thereof: An ESD protection circuit (20) includes an ESD device (24) and an isolation diode element (30). The ESD device includes a drain-source junction isolated ESD transistor (26,28). The isolation diode element is coupled in series with the ESD device and configured for providing ESD protection to a transistor device (22)... Agent: Freescale Semiconductor, Inc. Law Department

20070228476 - Semiconductor device: A semiconductor device capable of dissipating heat, which has been produced in an ESD protection element, to the exterior of the device rapidly and efficiently includes an ESD protection element having a drain region, a source region and a gate electrode, and a thermal diffusion portion. The thermal diffusion portion,... Agent: Young & Thompson

20070228474 - Semiconductor integrated circuit device: A semiconductor integrated circuit device including a semiconductor substrate and a MOS transistor having a source diffusion region and a drain diffusion region formed in the semiconductor substrate. A well is formed in the semiconductor substrate. A back gate diffusion region is defined in the vicinity of the source diffusion... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070228477 - Monolithic integrated circuit of a field-effect semiconductor device and a diode: A field-effect semiconductor device such as a HEMT or MESFET is monolithically integrated with a Schottky diode for feedback, regeneration, or protection purposes. The field-effect semiconductor device includes a main semiconductor region having formed thereon a source, a drain, and a gate between the source and the drain. Also formed... Agent: Woodcock Washburn LLP

20070228478 - Semiconductor device and method of manufacturing the same: According to the present invention, it is possible to isolate elements from each other without formation of STI and integrate the elements at a high density. A step is formed on a surface of a silicon substrate so as to provide different surfaces. Transistors are formed on the respective different... Agent: Young & Thompson

20070228481 - Semiconductor device: A semiconductor device in which potential is uniformly controlled and in which the influence of noise is reduced. A p-type well region is formed beneath a surface of a p-type Si substrate. n-type MOS transistors are formed on the p-type well region. An n-type well region is formed in the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070228483 - Semiconductor device and manufacturing method thereof: The present invention provides a semiconductor device which includes a gate electrode shaped in the form of an approximately quadrangular prism, including a laminated body of a gate oxide layer, a gate polysilicon layer and a gate silicon nitride layer provided in a first conduction type substrate, a second conduction... Agent: Rabin & Berdo, PC

20070228482 - Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions: By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close... Agent: Williams, Morgan & Amerson

20070228480 - Cmos device having pmos and nmos transistors with different gate structures: A CMOS device has PMOS and NMOS transistors with different gate structures overlying a semiconductor device. A first gate structure overlying the PMOS device region has a first gate dielectric layer overlying the semiconductor substrate, and a first gate conductor overlying the first gate dielectric layer. A second gate device... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070228479 - Protection against charging damage in hybrid orientation transistors: A chip includes a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. A SOI device is disposed in a semiconductor-on-insulator... Agent: International Business Machines Corporation Dept. 18g

20070228484 - Structure and method of integrating compound and elemental semiconductors for high-performance cmos: A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such... Agent: Keusey, Tutunjian & Bitetto, P.C.

20070228485 - Semiconductor device: A semiconductor device comprises n-type and p-type semiconductor devices formed on the substrate, the n-type device including an n-channel region formed on the substrate, n-type source and drain regions formed opposite to each other interposing the n-channel region therebetween, a first gate insulator formed on the n-channel region, and a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070228486 - Semiconductor device: A semiconductor device comprises n-type and p-type semiconductor devices formed on the substrate, the n-type device including an n-channel region formed on the substrate, n-type source and drain regions formed opposite to each other interposing the n-channel region therebetween, a first gate insulator formed on the n-channel region, and a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070228487 - Structure and method for latchup suppression: A method and structure for an integrated circuit comprising a substrate of a first polarity, a merged triple well region of a second polarity and a doped region of the second polarity abutting the well region. The doped region is adapted to suppress latch-up in the integrated circuit. The doped... Agent: Greenblum & Bernstein, P.L.C

20070228488 - Semiconductor device having device characteristics improved by straining surface of active region and its manufacture method: A trench is formed in the surface layer of a semiconductor substrate, surrounding an active region. A lower insulating film made of insulating material fills a lower region of the trench. An upper insulating film fills a region of the trench above the lower insulating film. The upper insulating film... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070228489 - Semiconductor memory device for storing data as state of majority carriers accumulated in channel body and method of manufacturing the same: A semiconductor memory device comprises a substrate; a semiconductor layer of a first conductive type isolated from the substrate by an insulator layer; a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in the semiconductor layer, and a channel body... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070228493 - Plasma display panel: A design for a plasma display panel that results in improved visible ray transmissivity. The plasma display panel includes a substrate, a plurality of discharge electrode pairs arranged on the substrate and spaced apart from each other, a dielectric layer covering the plurality of discharge electrode pairs, the dielectric layer... Agent: Robert E. Bushnell Suite 300

20070228492 - Substrate strip and compact camera module utilizing the same: A substrate strip includes a plurality of substrate units. A plurality of fingers is disposed in the substrate units. At least one of the corners of the fingers has a lead angle. A plurality of milling slots is formed on the peripheries of the substrate units and exposes out of... Agent: Lowe Hauptman Berner, LLP

20070228490 - Charge balance techniques for power devices: A charge balance semiconductor power device includes an active area comprising a plurality of cells capable of conducting current when biased in a conducting state. A non-active perimeter region surrounds the active area, wherein no current flows through the non-active perimeter when the plurality of cells is biased in a... Agent: Townsend And Townsend And Crew, LLP

20070228494 - Electronic card with protection against aerial discharge: An electronic card includes a card terminal which is exposed on a surface of a card, a semiconductor integrated circuit chip including an insulated-gate field effect transistor, and a protection circuit which is provided between the card terminal and the insulated-gate field effect transistor. The protection circuit is configured to... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070228491 - Tunneling transistor with sublithographic channel: Disclosed herein are vertical tunneling transistors with gates that surround transistor bodies that have a width dimension less than a photolithographic dimension. These thin tunneling transistors with surrounding gates are used to obtain low sub-threshold leakage. Various embodiments provide sublithographic bodies by growing a crystalline nanofin from an amorphous structure... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070228495 - Integrated circuit and method of manufacturing the same: An integrated circuit includes: a semiconductor substrate that has a well region containing a first conductivity type impurity; and an enhancement type MOS transistor and a plurality of depletion type MOS transistors, each of which is formed in the well region and has a channel region under a gate electrode.... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070228497 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a gate electrode formed on a semiconductor layer; a source electrode and a drain electrode respectively provided at sides of the gate electrode; and a first field plate provided in a region between the drain electrode and an element isolation region located in an extension of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070228496 - Vertical semiconductor devices and methods of manufacturing such devices: A vertical semiconductor device, for example a trench-gate MOSFET power transistor (1), has a drift region (12) of one conductivity type containing spaced vertical columns (30) of the opposite conductivity type for charge compensation increase of the device breakdown voltage. Insulating material (31) is provided on the sidewalls only of... Agent: Nxp, B.v. Nxp Intellectual Property Department

20070228498 - Semiconductor device and a method of manufacturing the same: Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide... Agent: Miles & Stockbridge PC

20070228499 - Mems device package with thermally compliant insert: A low cost micro-electronic package for MEMS applications includes a package substrate, a MEMS device and a buffer insert which is placed between the MEMS device and the package substrate. The buffer insert has a coefficient of thermal expansion (CTE) which is compatible with the material of the MEMS device... Agent: Thelen Reid Brown Raysman & Steiner LLP

20070228500 - Mechanical-quality measuring device: At least two or more pairs of bridge circuits are formed inside a semiconductor monocrystal substrate and a semiconductor chip, and one of these bridge circuits forms a n-type diffusion resistor in which a direction of a current flow and measuring variation of a resistor value are in parallel with... Agent: Townsend And Townsend And Crew, LLP

20070228501 - Magnetic recording element and magnetic memory: A magnetic recording element according to an example of the present invention includes a magnetic free layer whose magnetization is variable in accordance with a current direction passing through a film and whose direction of easy axis of magnetization is a direction perpendicular to a film plane, a magnetic pinned... Agent: Nixon & Vanderhye, PC

20070228503 - Photoelectric conversion device, solid-state imaging device and manufacturing method of solid-state imaging device: A photoelectric conversion device comprising a lower electrode, an upper electrode opposing to the lower electrode and a photoelectric conversion layer provided between the lower electrode and the upper electrode, the photoelectric conversion device being for collecting a photocurrent upon application of a bias voltage between the lower electrode and... Agent: Sughrue-265550

20070228502 - Semiconductor imaging device and method for manufacturing the same: A semiconductor imaging device includes: a semiconductor imaging element including an imaging region, a peripheral circuit region, and an electrode region, the imaging region including a plurality of micro lenses; a semiconductor package the semiconductor package in which a cavity for mounting the semiconductor imaging element is formed, the semiconductor... Agent: Mcdermott Will & Emery LLP

20070228504 - Driving apparatus and method for driving light emitting elements, and projector: The light-emitting element driving apparatus comprises a direct-current power source 12 for supplying direct current I-in, a light-emitting element selection controlling section 11 for selecting light emitting elements 10R, 10G, 10B of different rated current, successively, a power supplying section 13 for changing the direct current supplied from the direct-current... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070228505 - Junction barrier schottky rectifiers having epitaxially grown p+-n junctions and methods of making: A junction barrier Schottky (JBS) rectifier device and a method of making the device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p+-n junctions and self-planarizing epitaxially over-grown second n-type drift regions between and, optionally, on top of the p-type regions. The... Agent: Merchant & Gould PC

20070228507 - Electric double layer capacitor: The current invention provides for an electric double layer capacitor which can be manufactured with low manufacturing cost, and an increase of internal resistance due to the damage of a cathode current collector by reflow is inhibited. For this reason, in the current invention, the electric double layer capacitor comprising... Agent: Masuvalley & Partners

20070228506 - Composite capacitor and method for forming the same: An electronic assembly (98) includes a substrate (20), a capacitor having first and second conductors (38,54) formed over the substrate, a first set of conductive members (76) formed over the substrate and being electrically connected to the first conductor of the capacitor, and a second set of conductive members (78)... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070228508 - Integrated-circuit chip with offset external pads and method for fabricating such a chip: An integrated-circuit chip includes a first electrical connection are placed on an underlying layer and covered with an intermediate dielectric layer. A second electrical connection is placed on the intermediate dielectric layer and is covered with a superficial dielectric layer. External electrical connection pads are placed on the superficial dielectric... Agent: Jenkens & Gilchrist, PC

20070228509 - Semiconductor device and memory card using the same: A circuit board has a curved portion provided in at least one side of an external shape thereof. An external connecting terminal is provided on a first main surface of the circuit board. A semiconductor element is mounted on a second main surface of the circuit board. A first wiring... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070228510 - Shallow trench isolation fill by liquid phase deposition of sio2: To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20070228511 - Semiconductor device and manufacturing method thereof: On forming a ferroelectric capacitor structure, an IrO2 film and an IrOx film which are constituents of an upper electrode layer are sequentially formed on a capacitor film. By RTA treatment at 600° C. to 750° C., in this case, at 725° C. for about one minute under an O2... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070228512 - Thin-film device: A thin-film device incorporates a device main body and four terminal electrodes. The device main body has four side surfaces. The terminal electrodes are disposed to touch respective portions of the side surfaces. The device main body includes a lower conductor layer used to form a first passive element and... Agent: Oliff & Berridge, PLC

20070228513 - Probe-based memory: Apparatuses, a method, and a system for a non-volatile, probe-based memory device are disclosed herein. In various embodiments, probe-based memory may be one-time programmable or rewritable nonvolatile probe-based memory.... Agent: Schwabe, Williamson & Wyatt, P.C.

20070228516 - Semiconductor radiation source and light curing device: Provision is made of a semiconductor radiation source having a base body on which at least two LED chips are mounted, at least one chip of which is connected to a series resistor which can be adjusted. The LED chips (12, 14) are fitted to the base body (24) using... Agent: John C. Thompson

20070228514 - Electronic device: The electronic device comprises a network of at least one thin-film capacitor and at least one inductor on a first side of a substrate of a semiconductor material. The substrate has a resistivity sufficiently high to limit electrical losses of the inductor and being provided with an electrically insulating surface... Agent: Nxp, B.v. Nxp Intellectual Property Department

20070228515 - Semiconductor integrated circuit with spiral inductors: A spiral inductor, which is formed of a spiral wiring pattern, is formed in an inductor formation region which is assigned within an IC chip. A plurality of dummy wiring lines are formed according to a given design rule on an inside region surrounded by the spiral inductor within the... Agent: Foley And Lardner LLP Suite 500

20070228517 - Sol-gel and mask patterning for thin-film capacitor fabrication, thin-film capacitors fabricated thereby, and systems containing same: A process of forming a thin-film capacitor that includes sol-gel patterning of a dielectric thin film on a first electrode, lift-off removal of unwanted dielectric thin film, and mating the dielectric thin film with a second electrode. The thin-film capacitor exhibits a substantially uniform heat-altered morphology along a line defined... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070228519 - Semiconductor device: A semiconductor device made of a group-III nitride semiconductor having excellent properties is provided. The semiconductor device has a horizontal diode structure of Schottky type or P—N junction type, or combined type thereof having a main conduction pathway in the horizontal direction in a conductive layer with unit anode portions... Agent: Burr & Brown

20070228518 - Power device with improved edge termination: A field effect transistor includes an active region and a termination region surrounding the active region. A resistive element is coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an avalanche current starts to flow in the termination region, and the resistive element is... Agent: Townsend And Townsend And Crew, LLP

20070228520 - Interdigitated mesh to provide distributed, high quality factor capacitive coupling: Apparatuses and methods for increasing well distributed, high quality-factor on-chip capacitance of integrated circuit devices are disclosed. In one aspect, an integrated circuit device structure includes a first metal line implemented on a metallization layer of a semiconductor substrate, the first metal line having a first set of metal fingers... Agent: Lsi Corporation

20070228521 - Gallium nitride substrate, and gallium-nitride-substrate testing and manufacturing methods: Fracture-resistant gallium nitride substrate, and methods of testing for and manufacturing such substrates are made available. A gallium nitride substrate (10) is provided with a front side (12) polished to a mirrorlike finish, a back side (14) on the substrate side that is the opposite of the front side (12).... Agent: Judge & MurakamiIPAssociates

20070228524 - Method of manufacturing epitaxial silicon wafer: A role of a bottom face of a silicon wafer is identified in a manufacturing process of the silicon wafer. And preferable characteristic feature is also identified. In order to obtain the above characteristic feature, a process method to be implemented into the method of manufacturing a normal silicon wafer... Agent: Alston & Bird LLP

20070228523 - Reduction of a feature dimension in a nano-scale device: Nano-scale devices and methods provide reduced feature dimensions of features on the devices. A surface of a device substrate having a pattern of spaced apart first nanowires is consumed, such that a dimension of the first nanowires is reduced. A second nanowire is formed in a trench or gap between... Agent: Hewlett Packard Company

20070228522 - Soi substrate, silicon substrate therefor and it's manufacturing method: A silicon wafer includes a principal face for forming electronic devices; an end region; and a tapered region which is located between the principal face and the end region, in which the thickness of the silicon wafer is gradually reduced, and which has a slope that makes an angle of... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070228525 - Substrate earthing mechanism for use in charged-particle beam writing apparatus: A substrate earthing mechanism includes a plate-like spring extending toward a substrate in a direction parallel to a surface of the substrate, and a contact portion coupled to a tip end of the plate-like spring for coming into contact with the substrate to thereby provide electrical conduction therebetween. The plate... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070228526 - Insulating film and semiconductor device: s

20070228528 - Semiconductor device and manufacturing method thereof: An insulating layer is formed on a semiconductor substrate, and has a through hole for via. A porous silica layer has a trench for interconnection communicating to the through hole for via, and is formed on the insulating layer in contact therewith. A conductive layer is formed in the through... Agent: Fish & Richardson P.C.

20070228527 - Substrate for electronic device and method for processing same: Disclosed are a substrate for electronic devices such as semiconductor devices and a method for processing the same, In the processing method, firstly a substrate for electronic devices is prepared and an insulating film (I) composed of a fluorocarbon (CF) is formed on the surface of the substrate. Then, fluorine... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070228529 - Mounting substrate and manufacturing method thereof: A mounting substrate including an interconnection provided on a front surface of a substrate, a lead pad provided separately from the interconnection, on the front surface of the substrate and, a lead connected to the lead pad by solder, and a connecting portion that connects the interconnection and the lead... Agent: Kratz, Quintos & Hanson, LLP

20070228530 - Heat conductive bonding material, semiconductor package, heat spreader, semiconductor chip and bonding method of bonding semiconductor chip to heat spreader: A heat conductive bonding material 6 has a first bonding region 7 transferring heat of a semiconductor chip 1 to a heat spreader 4, and a second bonding region 8 relaxing a thermal stress generated between the semiconductor chip 1 and the heat spreader 4.... Agent: Arent Fox PLLC

20070228532 - Edge coating a microelectronic device: A microelectronic device includes a die having an active surface and a non-active surface. To assemble the microelectronic device, the active surface of the die is placed on a substrate. A first material is dispensed between the active surface of the die and the substrate. A second material is dispensed... Agent: Seagate Technology LLC C/o Westman Champlin & Kelly, P.A.

20070228536 - Memory card: A memory card includes: a package in the form of a thin plate made of an insulating material and configured to be inserted into and removed from a slot of an external apparatus; a plurality of contacts provided on the package and configured to transmit a signal to and from... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070228535 - Optical device package and optical semiconductor device using the same: An optical device package comprises: a metal frame including a substrate and a rectangular die pad portion integrally connected to the substrate, wherein the substrate is a metal plate, and the die pad portion is bent from the substrate such that the die pad portion extends from the substrate at... Agent: Leydig Voit & Mayer, Ltd

20070228534 - Semiconductor device and manufacturing method of the same: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070228531 - Apparatus and system for an ic substrate, socket, and assembly: An apparatus and system including a substrate having a plurality of through-holes therethrough, and an integrated circuit (IC) socket frame to mount to the substrate. The IC socket frame may include a plurality of beam features, each extending from a socket frame body and corresponding in arrangement to the plurality... Agent: Buckley, Maschoff & Talwalkar LLC

20070228533 - Folding chip planar stack package: A folding chip planar stack package is realized by employing folding chips. The folding chip planar stack package includes a substrate, first and second semiconductor chips attached to an upper surface of the substrate while being folded and spaced in parallel to each other, a bonding wire for electrically connecting... Agent: Ladas & Parry LLP

20070228538 - Integrated circuit die with pedestal: An integrated circuit die is provided having a body portion having a singulation side and a pedestal portion extending from the body portion and having a singulation side coplanar with the singulation side of the body portion.... Agent: Ishimaru & Zahrt LLP

20070228539 - Method for detaching a semiconductor chip from a foil and device for mounting semiconductor chips: The detachment of a semiconductor chip (1) from a foil (4) and picking the semiconductor chip (1) from the foil (4) takes place with the support of a chip ejector (6), that has a ramp (16), the surface (17) of which is formed concave and ends at a stripping edge... Agent: Thelen Reid Brown Raysman & Steiner LLP

20070228537 - Semiconductor device: By disposing a rear surface of a first island 12 and a top surface of a second island 13 so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are... Agent: Fish & Richardson P.C.

20070228540 - Mems device wafer-level package: A method and system in which a semiconductor wafer having a plurality of dies is inspected through a visual inspection and/or an electrical test. If certain of the dies on the wafer pass the inspection, then windows are mounted or affixed above those certain dies while they are still a... Agent: Texas Instruments Incorporated

20070228541 - Method for fabricating chip package structure: A method for fabricating a chip package structure is disclosed. One or plural patterned plates are used to fabricate the inner circuits and the outer circuits, and some fabricating steps can be proceeded repeatedly to form a stack structure, and after a protective layer is formed, the carrier is removed.... Agent: Abelman, Frayne & Schwab

20070228543 - Controlling flip-chip techniques for concurrent ball bonds in semiconductor devices: A device has a first semiconductor chip (101) with contact pads in an interior first set (102) and a peripheral second set (103). A deformed sphere (104) of non-reflow metal such as gold is placed on each contact pad of the first and second sets. At least one additional deformed... Agent: Texas Instruments Incorporated

20070228544 - Semiconductor package stack with through-via connection: A package stack includes at least two packages stacked on each other. Each package has a substrate, a circuit pattern positioned on the substrate, a semiconductor chip attached to the substrate, and a number of through-vias formed on a lateral surface. A number of electrical connection members are attached to... Agent: Ladas & Parry LLP

20070228542 - Stacked integrated circuit: The invention relates to an integrated circuit comprising a top package with a first substrate carrying an integrated circuit, and a bottom package with a second substrate carrying at least one die. To increase the clearance between the top package and the bottom package, the invention provides a cavity within... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20070228545 - Stacked semiconductor packages and method therefor: A stackable semiconductor package and method includes providing a first semiconductor package having a first plurality of lower leads and a first plurality of upper leads. A second semiconductor package having a second plurality of lower leads is provided. The second plurality of lower leads is attached to the first... Agent: Ishimaru & Zahrt LLP

20070228546 - Multi-chip package for reducing parasitic load of pin: A multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit.... Agent: Volentine & Whitt PLLC

20070228547 - Integrated circuit (ic) carrier assembly incorporating an integrated circuit (ic) retainer: An integrated circuit (IC) carrier assembly includes a printed circuit board (PCB). A carrier is soldered to the PCB. The carrier includes a grid of electrical contact islands surrounding a receiving zone for receiving an IC. Pairs of adjacent islands are interconnected by respective resilient suspension means. The IC is... Agent: Silverbrook Research Pty Ltd

20070228548 - Chip carrier substrate with a land grid array and external bond terminals: A carrier for a semiconductor die has a substrate with a cavity formed in the substrate. The cavity has a bottom and sidewalls, and the sidewalls have a stepped tier. Electrically conductive contacts are disposed on an underside of the substrate. Electrically conductive tabs are disposed on the stepped tier,... Agent: Sierra Patent Group, Ltd.

20070228549 - Interconnect structure with stress buffering ability and the manufacturing method thereof: An interconnect structure with stress buffering ability is disclosed, which comprises: a first surface, connected to a device selected form the group consisting of a substrate and an electronic device; a second surface, connected to a device selected form the group consisting of the substrate and the electronic device; a... Agent: Birch Stewart Kolasch & Birch

20070228550 - Optical semiconductor device: An optical semiconductor device has a semiconductor substrate, a semiconductor region and heater. The semiconductor region has a stripe shape demarcated with a top face and a side face thereof. The stripe shape has a width smaller than a width of the semiconductor substrate. An optical waveguide layer is located... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070228551 - Optical semiconductor element and optical semiconductor device: An optical semiconductor device includes an optical semiconductor element, a metal pattern and at least one thermal conductive material. The optical semiconductor element has a first optical waveguide region and a second optical waveguide region. The second optical waveguide region is optically coupled to the first optical waveguide region and... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070228552 - Optical semiconductor device provided with phase control function: An optical semiconductor device has an optical semiconductor element; and a mounting substrate unit on which the optical semiconductor element is mounted, wherein the optical semiconductor element has an element substrate 14 and an active layer 17 formed on a lower side surface of the element substrate, the mounting substrate... Agent: Mcginn Intellectual Property Law Group, PLLC

20070228553 - Light assembly: A light assembly includes a fin-type heatsink and a light module. The fin-type heatsink has a contact surface. The light module includes a thermally conductive cup-shaped chip seat and a light-emitting chip. The thermally conductive cup-shaped chip seat is attached to the contact surface of the fin-type heatsink, and defines... Agent: Ladas & Parry LLP

20070228554 - Semiconductor device and manufacturing method thereof: A semiconductor device includes: a semiconductor substrate; a heat sink mounted on an upper surface of the semiconductor substrate; wirings formed on a lower surface of the semiconductor substrate; and the like. The heat sink is mounted on the upper surface of the semiconductor substrate, and a planar size thereof... Agent: Fish & Richardson P.C.

20070228559 - Connecting structure, method for forming bump, and method for producing device-mounting substrate: A connecting terminal provided on a substrate and a connector provided on an electronic device are connected via a bump formed of a first member, which is formed of an anisotropic conductive paste including particles of a conductive material, and a second member which is different in conductivity from the... Agent: Reed Smith, LLP Attn: Patent Records Department

20070228557 - Electronic component, production method of electronic component, mounted structure of electronic component, and evaluation method of electronic component: An electronic component is comprised of an element body having at least one plane, and a terminal electrode to be electrically connected through an electroconductive particle to a circuit substrate. The terminal electrode is formed on the plane of the element body. When the plane of the element body is... Agent: Oliff & Berridge, PLC

20070228555 - Semiconductor chip having fine pitch bumps and bumps thereon: A semiconductor chip has fine pitch bumps. The bumps are respectively bonded to the inner leads of a tape during a tape automatic bonding process. The surface of the semiconductor chip has a plurality of bumps. Each of the bumps has at least a first region with a larger width... Agent: Oliff & Berridge, PLC

20070228556 - Power semiconductor component with a power semiconductor chip and method for producing the same: A power semiconductor component includes at least one power semiconductor chip and surface-mountable external contacts. The power semiconductor chip includes large-area contact areas on its top side and its rear side, which cover essentially the entire top side and rear side, respectively. The top side also includes, alongside the large-area... Agent: Edell, Shapiro & Finnan, LLC

20070228560 - Semiconductor device that improves electrical connection reliability: A semiconductor device including: a semiconductor section in which an element is formed; an insulating layer formed on the semiconductor section; an electrode pad formed on the insulating layer; a contact section formed of a conductive material provided in a contact hole in the insulating layer and electrically connected with... Agent: Oliff & Berridge, PLC

20070228558 - Semiconductor packaging unit with sliding cage: A semiconductor packaging unit mounts onto a board by solder joints. The unit includes, disposed along one axis, a semiconductor component having on a rear face protruding electrical connection lugs designed to be soldered onto the board and an external cage surrounding the component and having a rear edge designed... Agent: Jenkens & Gilchrist, PC

20070228561 - Semiconductor device and manufacturing method thereof: A semiconductor device and manufacturing method thereof improving moisture resistance of a FeRAM. After a probe test using a pad, a metal film is formed to cover the pad in an opening of a protective film and a region from the pad to an opening outer periphery of the protective... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070228562 - Electronic packaging using conductive interproser connector: Formation of a plurality of conductive connectors of an integrated circuit package is described. The conductive connectors made with a conductive elastomer material and formed using an interposer that includes a plurality of the conductive connectors linked together.... Agent: Schwabe, Williamson & Wyatt, P.C.

20070228565 - Ball grid array housing having a cooling foil: A ball grid array housing, a semiconductor device having a ball grid array housing and an electronic circuit are disclosed. In one embodiment, a ball grid array housing includes a substrate with solder ball connections pointing out from a housing and at least one semiconductor chip. For better heat dissipation... Agent: Dicke, Billig & Czaja

20070228566 - Ball grid array package construction with raised solder ball pads: The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductive layer, the raised pad having a raised face and a... Agent: Ibm Corporation (cs) C/o Carr LLP

20070228564 - Flip chip bonded package applicable to fine pitch technology: A flip chip bonded package applicable to a fine pitch technology uses, inter alia, insulative posts instead of using conductive bumps, which correspond to electrodes one by one. The insulative posts are assigned to every two bonding pads for the sake of flip chip bonding. This makes it possible to... Agent: Ladas & Parry LLP

20070228563 - High-performance semiconductor package: A high-speed and high-performance semiconductor package reduces degradation of chip characteristics when chips are packaged. The semiconductor package includes a semiconductor chip including a plurality of bonding pads, a redistribution layer formed on the semiconductor chip while being connected with the bonding pads, a substrate attached to an upper surface... Agent: Ladas & Parry LLP

20070228567 - Semiconductor chip comprising a metal coating structure and associated production method: A semiconductor chip (1) has a metal coating structure (2) which has on an active upper side (3) of the semiconductor chip (1) at least one lower metal layer (8) with copper or copper alloy, on which a central metal layer (9) with nickel is arranged. The metal coating structure... Agent: Baker Botts, L.L.P.

20070228568 - Manufacturing method of semiconductor device and semiconductor device produced therewith: A semiconductor device (having an interlayer insulating film) which is sufficiently low in the dielectric constant and high in the mechanical strength is provided. A manufacturing method of a semiconductor device includes: a step of forming a dielectric thin film in which a plurality of pores are arranged around a... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20070228569 - Interconnects forming method and interconnects forming apparatus: The present invention provides an interconnects-forming method and an interconnects-forming apparatus which can minimize the lowering of processing accuracy in etching, minimize light exposure processing for the formation of interconnect recesses in the production of multi-level interconnects, improve the electromigration resistance of interconnects without impairing the electrical properties of the... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070228570 - Reliable beol integration process with direct cmp of porous sicoh dielectric: The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of... Agent: Scully, Scott, Murphy & Presser, P.C.

20070228571 - Interconnect structure having a silicide/germanide cap layer: An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at... Agent: Slater & Matsil, L.L.P.

20070228572 - Formation of an integrated circuit structure with reduced dishing in metallization levels: An integrated circuit structure includes a metallization level having a dual damascene trench structure formed in a layer of dielectric material. The dielectric material has an upper surface with a first degree of planarity. The metallization level includes a conductive layer formed in the trench structure with an upper surface... Agent: Fox Rothschild LLP

20070228573 - Semiconductor device having capacitor formed in multilayer wiring structure: A semiconductor device having a capacitor formed in a multilayer wiring structure, the semiconductor device comprising a multilayer wiring structure including a plurality of wiring layers formed on a substrate, a capacitor arranged in a predetermined wiring layer in the multilayer wiring structure and having a lower electrode, a dielectric... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070228574 - Semiconductor device and a method of manufacturing the same: A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070228575 - Wiring material and wiring board using the same: A wiring material for TFT-LCD which comprises an Ag alloy containing Ag and Zr as essential components and further one or more metals selected from the group consisting of Au, Ni, Co and Al; and a wiring material which comprises a Cu alloy comprising Au and/or Co and Cu, wherein... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070228578 - Circuit substrate: A circuit substrate including a first wiring layer, a second wiring layer, a first reference plane, a second reference plane, a first conductive via, and a plurality of second conductive vias is provided. The first wiring layer and the second wiring layer have a first signal trace and a second... Agent: J C Patents, Inc.

20070228577 - Packaged microelectronic devices recessed in support member cavities, and associated methods: Packaged microelectronic devices recessed in support member cavities, and associated methods, are disclosed. Method in accordance with one embodiment includes positioning a microelectronic device in a cavity of a support member, with the cavity having a closed end with a conductive layer, and an opening through which the cavity is... Agent: Perkins Coie LLP Patent-sea

20070228576 - Isolating chip-to-chip contact: An apparatus has two slabs of substrate material joined to each other, the two slabs including a pair of contacts joined to each other having a shape separating a first area from a second area.... Agent: Morgan & Finnegan, L.L.P.

20070228580 - Semiconductor device having stacked structure and method of manufacturing the same: A semiconductor device comprises a main circuit substrate and a plurality of sub-circuit substrates on which a semiconductor element mounted and which are stacked on the main circuit substrate so that mounting surfaces thereof face the main circuit substrate. Each of the sub-circuit substrates has a size larger than a... Agent: Sughrue Mion, PLLC

20070228579 - Chip stack package utilizing a dummy pattern die between stacked chips for reducing package size: The chip stack package includes at least a printed circuit board having a bond finger and a ball land, and at least two semiconductor chips stacked on the printed circuit board while being spaced from each other and formed with a plurality of bonding pads. A dummy pattern die is... Agent: Ladas & Parry LLP

20070228581 - Universal chip package structure: A universal chip package structure including a carrier, a chip, a plurality of bonding wires, and a molding compound is provided. The carrier has a plurality of through holes, a carrying surface, and a back surface corresponding to the carrying surface. The back surface has a plurality of contacts around... Agent: J.c. Patents

20070228582 - Tape wiring substrate and tape package using the same: A tape wiring substrate may have dispersion wiring patterns. The dispersion wiring patterns may be provided between input/output wiring pattern groups to compensate for the intervals therebetween. Connecting wiring patterns may be configured to connect the dispersion wiring patterns to a first end of the adjacent input/output wiring pattern.... Agent: Volentine & Whitt PLLC

20070228583 - Methods of bridging lateral nanowires and device using same: A semiconductor nanowire is grown laterally. A method of growing the nanowire forms a vertical surface on a substrate, and activates the vertical surface with a nanoparticle catalyst. A method of laterally bridging the nanowire grows the nanowire from the activated vertical surface to connect to an opposite vertical surface... Agent: Hewlett Packard Company