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Active solid-state devices (e.g., transistors, solid-state diodes) September archived patents by title, number, class 09/07

20070221907 - Light emitting device having vertical structure and mehod for manufacturing the same: A light emitting device having a vertical structure and a method for manufacturing the same, which are capable of increasing light extraction efficiency, are disclosed. The method includes forming a light extraction layer on a substrate, forming a plurality of semiconductor layers on the light extraction layer, forming a first... Agent: Mckenna Long & Aldridge LLP

20070221915 - Compound for organic electroluminescence and organic electroluminescent device: l

20070221916 - Organic semiconductor formulation: This invention relates to an organic semiconductor formulation comprising one or more surfactants and to its use in electrically conducting, photoconducting and semiconducting components and devices.... Agent: Millen, White, Zelano & Branigan, P.C.

20070221922 - Layer-stacked wiring and method for manufacturing same and semiconductor device using same and method for manufacturing semiconductor device: A layer-stacked wiring made up of a microcrystalline silicon thin film and a metal thin film is provided which is capable of suppressing an excessive silicide formation reaction between the microcrystalline silicon thin film and metal thin film, thereby preventing peeling of the thin film. In a polycrystalline silicon TFT... Agent: Young & Thompson

20070221923 - Array substrate and method of manufacturing the same: A method of manufacturing an array substrate comprising forming a plurality of scanning lines, a plurality of signal lines and a plurality of switching elements on a substrate, forming an under layer having a plurality of color layers overlapping the scanning lines, the signal lines and the switching elements, a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070221928 - Light emitting diode package: A light emitting diode package which is superior in heat radiation and easily manufacturable. In the light emitting diode package, an Al substrate has a reflective cup formed thereon. At least one light emitting diode chip is disposed on a bottom surface of the reflective cup. An Al anodized film... Agent: Mcdermott Will & Emery LLP

20070221927 - Light-emitting diode and method for manufacturing the same: A light-emitting diode (LED) and a method for manufacturing the same are described. The method for manufacturing the LED comprises the following steps. An illuminant epitaxial structure is provided, in which the illuminant epitaxial structure has a first surface and a second surface on opposite sides, and a substrate is... Agent: Kinney & Lange, P.A.

20070221929 - Semiconductor light-emitting device and fabrication method thereof: A semiconductor light-emitting device is disclosed. The semiconductor light-emitting device comprises a multilayer epitaxial structure disposed on a semiconductor substrate. The semiconductor substrate has a predetermined lattice direction perpendicular to an upper surface thereof, wherein the predetermined lattice direction is angled toward [0ī1] or [01ī] from [100], or toward [011]... Agent: Birch Stewart Kolasch & Birch

20070221925 - Semiconductor white light sources: Semiconductor white light sources presented herein include special combinations of a blue source and a yellow source where these light fields are substantially overlapped. The source of blue light includes a blue emitting semiconductor operating in a conventional manner. However, this blue light source is combined with a special yellow... Agent: Acol Technologies S.a.

20070221932 - Method of fabricating nitride-based semiconductor light-emitting device and nitride-based semiconductor light-emitting device: A method of fabricating a nitride-based semiconductor light-emitting device capable of suppressing reduction of characteristics and a yield is obtained. This method of fabricating a nitride-based semiconductor light-emitting device comprises steps of forming a groove portion on a nitride-based semiconductor substrate by selectively removing a prescribed region of a second... Agent: Ndq&m Watchstone LLP

20070221935 - Package structure of light-emitting diode: A package structure of a light-emitting diode (LED) comprises a package carrier, an LED die mounted and electrically connected to the package carrier, a molding compound covering the package carrier and the LED die, and two electrodes disposed on opposite end portions of the molding component. A reflecting layer is... Agent: Oliff & Berridge, PLC

20070221941 - Backlight unit equipped with light emitting diodes: Disclosed herein is a backlight unit equipped with LEDs. The backlight includes an insulating substrate, a plurality of LED packages, an upper heat dissipation plate, and a lower heat dissipation plate. The insulating substrate is provided with predetermined circuit patterns. The LED packages are mounted above the insulating substrate, and... Agent: Mcdermott Will & Emery LLP

20070221942 - Led backlight unit without printed circuit board and method of manufacturing the same: Disclosed herein is a Light Emitting Diode (LED) backlight unit without a Printed Circuit board (PCB). The LED backlight unit includes a chassis, insulating resin layer, and one or more light source modules. The insulating resin layer is formed on the chassis. The circuit patterns are formed on the insulating... Agent: Mcdermott Will & Emery LLP

20070221940 - Led device and production method thereof: An LED device includes an LED chip die-bonded to a frame with a die-bonding material, wherein the die-bonding material contains Ag, a fine white powder, and solder particles. The LED device is superior in both reflectance and bonding strength because of the use of the die-bonding material.... Agent: Rohm Co., Ltd. C/o Keating & Bennett, LLP

20070221906 - Phase-changeable memory devices including nitrogen and/or silicon dopants: A phase-changeable memory device includes a substrate having a field effect transistor therein and a phase-changeable material electrically coupled to a source region of the field effect transistor. The phase-changeable material includes a chalcogenide composition containing at least germanium, bismuth and tellurium and at least one dopant selected from a... Agent: Myers Bigel Sibley & Sajovec

20070221905 - Reduced power consumption phase change memory and methods for forming the same: Memory cells for reduced power consumption and methods for forming the same are provided. A memory cell has a layer of phase change material. A first portion of the phase change material layer includes the programmable volume of the memory cell and its crystalline state has a higher resistivity than... Agent: Dickstein Shapiro LLP

20070221908 - Semiconductor light emitter: A semiconductor light emitter includes a quantum well active layer which includes nitrogen and at least one other Group-V element, and barrier layers which are provided alongside the quantum well active layer, wherein the quantum well active layer and the barrier layers together constitute an active layer, wherein the barrier... Agent: Dickstein Shapiro LLP

20070221909 - Optical device with quantum well: An optical device with a quantum well is provided. The optical device includes an active layer made of a Group III-V semiconductor compound and having a quantum well of a bandgap grading structure in which conduction band energy and valence band energy change linearly with a slope with the content... Agent: Buchanan, Ingersoll & Rooney PC

20070221913 - Aromatic imide-based dispersant for carbon nanotubes and carbon nanotube composition comprising the same: Disclosed herein are an aromatic imide-based dispersant for CNTs and a carbon nanotube composition comprising the same. Having an aromatic ring structure advantageously realizing adsorption on carbon nanotubes, the dispersant, even if used in a small amount, can disperse a large quantity of carbon nanotubes.... Agent: Cantor Colburn, LLP

20070221914 - Electronic devices comprising organic semiconductors: The present invention describes organic electronic devices in which at least one organic layer off low refractive index is introduced. The light output of the electronic devices is thereby improved.... Agent: Connolly Bove Lodge & Hutz, LLP

20070221910 - Intermediate layer in electroluminescent arrangements and electroluminescent arrrangement: An intermediate layer (11) comprises a basic material such as a conductive polymer that taken alone still absorbs some light. Combined with colloidal particles (12) the intermediate layer (11) becomes almost fully transparent. An electroluminescent arrangement with an intermediate layer (11) that is almost fully transparent because of colloidal particle... Agent: Philips Intellectual Property & Standards

20070221917 - Method of preparing nanowire(s) and product(s) obtained therefrom: The present invention provides a method of preparing at least one nanowire comprising the steps of: (a) providing at least one nanotemplate and at least one electrically conductive element in contact with the nanotemplate; (b) providing at least one organic linker, the organic linker having a first end and a... Agent: Dickstein Shapiro LLP

20070221918 - Organic thin-film transistor manufacturing method, organic thin-film transistor, and organic thin-film transistor sheet: An organic thin-film transistor is disclosed. The transistor may include a substrate, a gate electrode, a gate insulating layer, an organic semiconductor layer protective layer, a source electrode, and a drain electrode, wherein a layer formed on the organic semiconductor layer may have a light transmittance of not more than... Agent: Cantor Colburn, LLP

20070221911 - Polymer optoelectronic device and methods for making the same: The invention relates to a polymer optoelectronic device comprising at least a transparent conductive oxide layer, an active polymer layer, a back electrode layer and a substrate layer, wherein the transparent conductive oxide (TCO) layer has a controlled surface structure which is characterised by having an X-value in the range... Agent: Nixon & Vanderhye, PC

20070221912 - Stacked organic light emitting device having high efficiency and high brightness: A stacked organic light emitting device that includes an anode connected to an external power source, a cathode connected to the external power source, at least two light emitting sections aligned between the anode and the cathode, including a light emitting layer, and an internal electrode aligned between the light... Agent: Mckenna Long & Aldridge LLP

20070221919 - Diode with lead terminal for solar cell: The object of the present invention is to provide a diode that acts as a cell string bypass diode or a reverse-current preventive diode, has excellent heat dissipativity, and are preferably sealed integrally in a solar cell module. An N terminal 11 has an N substrate part 12 having an... Agent: Kanesaka Berner And Partners LLP

20070221920 - Semiconductor component having test pads and method and apparatus for testing same: A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is... Agent: Xilinx, Inc Attn: Legal Department

20070221921 - Photodiode: An optical diode 21 of the present invention comprises a cholesteric liquid crystal (CLC) layer 2 having a selective reflection wavelength band with a left-handed helical structure, and a phase shifter 24 for changing the phase difference between two intrinsic polarized light components of left-handed circularly polarized light having a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070221924 - Semiconductor devices: A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves,... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070221926 - Passivating layer for flexible electronic devices: An electronic device which comprises a first electrode, a second electrode, an active polymer layer between the first and the second electrodes, and a passivating layer adapted to enhance the lifetime of the electronic device. The passivating layer comprises a substantially amorphous titanium oxide having the formula of TiOx where... Agent: Foley & Lardner LLP

20070221930 - Apparatus comprising a single photon photodetector having reduced afterpulsing and method therefor: A single-photon detector is disclosed that provides reduced afterpulsing without some of the disadvantages for doing so in the prior art. An embodiment of the present invention provides a stimulus pulse to the active area of an avalanche photodetector to stimulate charges that are trapped in energy trap states to... Agent: Demont & Breyer, LLC

20070221931 - Optoelectronic semiconductor device and light signal input/output device: A optoelectronic semiconductor device, mountable on and electrically connectable to an electro-optical wiring board, a substrate thereof having a light input/output through-hole and electric connection through-holes, the light input/output through-hole being not formed in a stressed area of the circuit wiring board, but formed in a non-stressed area of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070221934 - Light emitting diode lamp: The present invention relates to an LED lamp including a pair of lead terminals 2 and 3, a cup portion 8 formed at an end of one of the lead terminals by denting the end and having a conical inner peripheral surface serving as a light-reflective surface 9, an LED... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20070221933 - Light-emitting element and method of manufacturing the same, and light-emitting device using the light-emitting element: It is an object of the present invention to provide a light-emitting element and a light-emitting device, in which a plurality of electroluminescent layers are stacked with a charge generation layer interposed therebetween between a pair of electrodes that are opposed to each other, and for which the charge generation... Agent: Eric Robinson

20070221936 - Light-emitting-diode chip comprising a sequence of gan-based epitaxial layers which emit radiation and a method for producing the same: A light-emitting diode chip (1) comprises a GaN-based, radiation-emitting epitaxial layer sequence (3), an active region (19), an n-doped layer (4) and a -doped layer (5). The p-doped layer (5) is provided, on its main surface (9)facing away from the active region (19), with a reflective contact metallization (6)comprising a... Agent: Fish & Richardson PC

20070221939 - Optically reliable nanoparticle based nanocomposite hri encapsulant, photonic waveguiding material and high electric breakdown field strength insulator/encapsulant: An optically reliable high refractive index (HRI) encapsulant for use with Light Emitting Diodes (LED's) and lighting devices based thereon. This material may be used for optically reliable HRI lightguiding core material for polymer-based photonic waveguides for use in photonic-communication and optical-interconnect applications. The encapsulant includes treated nanoparticles coated with... Agent: William L. Botjer

20070221937 - Semiconductor light emitting apparatus and its manufacturing method: A semiconductor light emitting apparatus comprises: a semiconductor light emitting device; resin that seals the semiconductor light emitting device; and antireflective coating provided on a surface of the resin. The antireflective coating is made of material having an intermediate refractive index between the refractive index of the resin and the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070221938 - Warm white lamps with customizable cri: Light emitting apparatuses including warm white LED based lights including a semiconductor light source and a phosphor material including a yellow emitting phosphor, a red emitting phosphor, and, optionally, at least one of a green, blue or green-blue emitting phosphor.... Agent: Fay Sharpe LLP

20070221943 - Backlight device and display device: It is an object to manufacture a highly reliable backlight device with less color unevenness and less luminance unevenness, and a high-performance and highly reliable display device including the backlight device, which can display a high quality image. A light emitting diode (LED) is used as a light source of... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070221944 - Light emitting diodes and fabrication methods thereof: A light emitting diode (LED)) may be disclosed. The LED may include a light-emitting side. The LED may also include a first electrode disposed on the light-emitting side. The LED may also include a second electrode. The LED may also include a semiconductor element disposed between the first electrode and... Agent: Ipsg, P.C.

20070221945 - Light-emitting element, display device, and electronic appliance: An object is to provide an inorganic light-emitting element capable of low-voltage driving. Moreover, another object is to provide a display device and an electronic appliance with low power consumption by using this light-emitting element. The light-emitting element includes a layer containing a light-emitting substance and an electron supplying layer... Agent: Fish & Richardson P.C.

20070221946 - Compound semiconductor light-emitting device: This pn-junction compound semiconductor light-emitting device includes a crystal substrate; an n-type light-emitting layer formed of a hexagonal n-type Group III nitride semiconductor and provided on the crystal substrate; a p-type Group III nitride semiconductor layer formed of a hexagonal p-type Group III nitride semiconductor and provided on the n-type... Agent: Sughrue Mion, PLLC

20070221948 - Group iii nitride semiconductor thin film and group iii semiconductor light emitting device: A group III nitride semiconductor thin film and a group III nitride semiconductor light emitting device using the same. The group III nitride semiconductor thin film includes a substrate with a concave and convex portions formed thereon; a buffer layer formed on the substrate and made of a group III... Agent: Mcdermott Will & Emery LLP

20070221947 - High-refractive index materials comprising semiconductor nanocrystal compositions, methods of making same, and applications therefor: A high-refractive index material that includes semiconductor nanocrystal compositions. The high-refractive index material has at least one semiconductor nanocrystal composition incorporated in a matrix material and has a refractive index greater than 1.5. The semiconductor nanocrystal composition has a semiconductor nanocrystal core of a II-VI, III-V, or IV-VI semiconductor material.... Agent: Kenyon & Kenyon LLP

20070221949 - Power semiconductor devices: This invention generally relates to power semiconductor devices, and in particular to improved thyristor devices and circuits. The techniques we describe are particularly useful for so-called MOS-gated thyristors. We describe a thyristor comprising a plurality of power thyristor devices connected in parallel, each said thyristor device being operable at a... Agent: Tarolli, Sundheim, Covell & Tummino L.L.P.

20070221950 - Semiconductor device and a method for producing the same: A semiconductor device having a substrate; an emitter electrode or source electrode formed on the top surface side of the substrate; a gate electrode formed on the top surface side of the substrate; and a collector electrode or drain electrode formed on the bottom surface side of the substrate. The... Agent: Mcginn Intellectual Property Law Group, PLLC

20070221951 - E-ink display and method for repairing the same: An E-ink display and method for repairing the same is provided. The method is for repairing a thin film transistor array substrate of the E-ink display. The thin film transistor array substrate having a plurality of pixel units is provided initially. Each of the pixel unit includes a thin film... Agent: Sheehan Phinney Bass & Green, PA C/o Peter Nieves

20070221953 - Semiconductor device: A semiconductor device such as a reverse blocking type switching element is provided with a switching element made of a wide band gap semiconductor on the side of a first major plane where a first terminal is formed, while the wide band gap semiconductor is operable at a high voltage... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070221952 - High density trench fet with integrated schottky diode and method of manufacture: A monolithically integrated trench FET and Schottky diode includes a pair of trenches terminating in a first silicon region of first conductivity type. Two body regions of a second conductivity type separated by a second silicon region of the first conductivity type are located between the pair of trenches. A... Agent: Townsend And Townsend And Crew, LLP

20070221954 - Group iii-v nitride-based semiconductor substrate, group iii-v nitride-based device and method of fabricating the same: A group III-V nitride-based semiconductor substrate has: a first layer made of GaN single crystal; and a second layer formed on the first layer, the second layer made of group III-V nitride-based semiconductor single crystal represented by AlxGa1-xN, where 0.9<x≦1, wherein a top surface and a back surface of the... Agent: Foley And Lardner LLP Suite 500

20070221955 - Semiconductor device and method of manufacturing the same: A trench is formed extending from a surface of a hetero semiconductor region of a polycrystal silicon to the drain region. Further, a driving point of the field effect transistor, where a gate insulating film, the hetero semiconductor region and the drain region are adjoined, is formed at a position... Agent: Young & Basile, P.C.

20070221956 - Semiconductor device and method of fabricating the same: A semiconductor device according to one embodiment of the present invention includes: a fin including a buffer layer made of SiGe and formed on a Si layer, and a SiGe layer formed on the buffer layer, the SiGe layer having a Ge concentration corresponding to a Ge concentration of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070221957 - Semiconductor integrated circuit device and dummy pattern arrangement method: A semiconductor integrated circuit device according to an embodiment of the present invention includes a functional circuit region including a functional circuit, a dummy region formed in a region other than the functional circuit region, and plural dummy MOSFETs formed in a dummy region and having a dummy gate electrode... Agent: Foley And Lardner LLP Suite 500

20070221958 - Circuit board and manufacturing method thereof, electro-optical device, and electronic apparatus: A circuit board includes: a substrate; source and drain electrodes formed on the substrate; an organic semiconductor layer formed on the source and drain electrodes; a gate insulating layer formed on the organic semiconductor layer; and a gate electrode formed on the gate insulating layer, wherein: the substrate includes a... Agent: Harness, Dickey & Pierce, P.L.C

20070221960 - Semiconductor memory device and manufacturing method thereof: A semiconductor memory device includes: a semiconductor substrate; a first impurity region; a second impurity region; a channel region; a first gate formed on a main surface on a side of the first impurity region; a second gate formed on the main surface on a side of the second impurity... Agent: Mcdermott Will & Emery LLP

20070221959 - Structure and method for fabricating recessed channel mosfet with fanned out tapered surface raised source/drain: A raised source/drain field effect transistor has a surface of a raised source/drain that tapers downward in a direction of a gate electrode that is also included within the field effect transistor. The downward tapered surface is preferably an end surface. Due to the downward taper, the field effect transistor... Agent: Scully Scott Murphy & Presser, PC

20070221961 - Forming a hybrid device: In one embodiment, the present invention includes a hybrid device having a first die including a semiconductor device and a second die coupled to the first die, where the second die includes a magnetic structure. The first die may be a semiconductor substrate, while the second die may be a... Agent: Trop Pruner & Hu, PC

20070221962 - Semiconductor device and method for manufacturing the same: An active region and an isolation region are formed in the surface of a silicon semiconductor substrate having a (100) crystal plane as a principal surface. A gate insulating film and a gate electrode are formed on the active region in this order. A stress control film is formed to... Agent: Mcdermott Will & Emery LLP

20070221963 - Junction field effect transistor, integrated circuit for switching power supply, and switching power supply: A switching power supply has a start-up circuit that includes a field effect transistor (JFET), which has a gate region (a p-type well region) formed in a surface layer of a p-type substrate and a drift region (a first n-type well region). A plurality of source regions (second n-type well... Agent: Rossi, Kimms & Mcdowell LLP.

20070221964 - Field effect device with reduced thickness gate: A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer... Agent: Scully Scott Murphy & Presser, PC

20070221970 - Manufacturing method of semiconductor device and semiconductor device: In a manufacturing process of a semiconductor device having a CMISFET, first, a silicon film and a first metal film made of a first metal are reacted with each other through heat treatment, thereby forming a gate electrode of a p-channel type MISFET and a dummy gate electrode of an... Agent: Stanley P. Fisher Reed Smith LLP

20070221971 - Nonvolatile semiconductor memory device: A semiconductor layer having a channel formation region provided between a pair of impurity regions spaced from each other is provided, and a first insulating layer a floating gate, a second insulating layer, and a control gate are provided above the semiconductor layer. The semiconductor material forming the floating gate... Agent: Eric Robinson

20070221968 - Transistor of semiconductor device and method for manufacturing the same: A transistor of a semiconductor device comprises a gate dielectric layer formed over a semiconductor substrate and comprising a hafnium oxide; and a gate electrode formed over the gate dielectric layer.... Agent: Marshall, Gerstein & Borun LLP

20070221965 - Dmos device with sealed channel processing: A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then... Agent: Schneck & Schneck

20070221966 - Method for integrally forming an electrical fuse device and a mos transistor: A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. A dielectric layer is deposited over the isolation structure and the semiconductor substrate. A metal layer is deposited on... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20070221972 - Mosfet for synchronous rectification: This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of... Agent: Bo-in Lin

20070221967 - Semiconductor device and method for forming the same: A semiconductor device may include a semiconductor substrate having a first dopant type. A first semiconductor region within the semiconductor substrate may have a plurality of first and second portions (44, 54). The first portions (44) may have a first thickness, and the second portions (54) may have a second... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070221969 - Semiconductor device and method of manufacturing the same: In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type silicon substrate. In the epitaxial layer, P type diffusion layers as a base region, N type diffusion layers as collector regions and an N type diffusion layer as an emitter region... Agent: Fish & Richardson P.C.

20070221973 - Solid-state imaging device and method for manufacturing the same: A solid-state imaging device includes: a plurality of photodiodes arranged in a matrix on a semiconductor substrate 1 for storing a signal charge converted from incident light; MOS transistors for reading the signal charge stored in the photodiode, an element isolation region for isolating the photodiode from the MOS transistors,... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070221975 - Bipolar switching pcmo capacitor: A multi-layer PrxCa1-xMnO3 (PCMO) thin film capacitor and associated deposition method are provided for forming a bipolar switching thin film. The method comprises: forming a bottom electrode; depositing a nanocrystalline PCMO layer; depositing a polycrystalline PCMO layer; forming a multi-layer PCMO film with bipolar switching properties; and forming top electrode... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070221974 - Method for forming ferroelectric memory capacitor: A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched to form an etched barrier layer (205), and... Agent: Texas Instruments Incorporated

20070221976 - Trench capacitor and fabrication method thereof: A method of fabricating trench capacitors is provided. A plurality of trenches is formed in the substrate by performing a patterning process with a patterned mask layer on a substrate. A bottom electrode is formed in the substrate of the surface of the trench. A portion of the patterned mask... Agent: Jianq Chyun Intellectual Property Office

20070221977 - Semiconductor device with trench isolation structure and method of manufacturing the same: A semiconductor device has: a substrate provided with a trench; and a device isolation structure formed in the trench. The device isolation structure has: a silicon oxynitride film formed on a surface of the substrate through an interfacial oxide film; and an embedded insulating film formed on the silicon oxynitride... Agent: Mcginn Intellectual Property Law Group, PLLC

20070221978 - Semiconductor device: The semiconductor device comprises a substrate, a semiconductor element mounted on the substrate, a heat diffusion member mounted on the substrate while covering the semiconductor element, and a resin seal for covering the semiconductor element. An integrated capacitor is mounted on the heat diffusion member in an opposed relationship to... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070221980 - One time programmable memory and the manufacturing method thereof: A one time programmable memory including a substrate, a plurality of isolation structures, a first transistor, and a second transistor is provided. The isolation structures are disposed in the substrate for defining an active area. A recess is formed on each of the isolation structures so that the top surface... Agent: Jianq Chyun Intellectual Property Office

20070221981 - Semiconductor memory and semiconductor device with nitride memory elements: A semiconductor memory has a gate electrode and a pair of multilayer memory elements formed on side surfaces of the gate electrode. Each multilayer memory element includes, in sequence from the gate electrode outward, a first silicon oxide layer, a charge trapping silicon nitride layer, a second silicon oxide layer,... Agent: Rabin & Berdo, PC

20070221982 - Semiconductor storage device and method of manufacturing same: The ratio of capacitance between a floating gate and a control gate to total capacitance in a semiconductor storage device is raised and reliability at read-out is improved by adopting a structure comprising select gates disposed on a substrate in first areas; floating gates disposed in second areas adjacent to... Agent: Mcginn Intellectual Property Law Group, PLLC

20070221979 - Method for production of memory devices and semiconductor memory device: At least one memory layer is provided on a substrate surface. A plurality of parallel conductor strips is formed from electrically conductive material above the memory layer. Sidewalls of the conductor strips are provided with spacers of an electrically conductive material.... Agent: Slater & Matsil LLP

20070221985 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device which is superior in writing and charge holding properties, including a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed with an interval, and a first insulating layer, a floating gate, a second insulating layer, and a... Agent: Eric Robinson

20070221983 - Dual gate memory with fast erase: An electronic non-volatile memory device comprising a base substrate doped with a source region and a drain region. The base substrate can be, for example, a silicon wafer with implanted source and drain regions. A channel region is disposed between the source region and the drain region with a floating... Agent: Schneck & Schneck

20070221984 - Nonvolatile semiconductor memory device and method for manufacturing same: A nonvolatile semiconductor memory device includes: a semiconductor layer; a gate insulating film provided on the semiconductor layer; a floating gate electrode provided on the gate insulating film; a control gate electrode opposed to an upper face of the floating gate electrode; a first dielectric film interposed between the upper... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070221987 - Split gate type non-volatile semiconductor memory device and method of manufacturing the same: A split gate-type non-volatile semiconductor memory device includes a floating gate having an acute-angled portion between a side surface and an upper surface above a semiconductor substrate; a control gate provided apart from the floating gate to oppose to the acute-angled portion; and an insulating portion provided on the floating... Agent: Foley And Lardner LLP Suite 500

20070221986 - Memory device using quantum dots: A memory device, which includes a memory layer having quantum dots uniformly dispersed in organic material disposed between an upper electrode layer and a lower electrode layer. The memory device is advantageous because it is nonvolatile and inexpensive, and realizes high integration and high speed switching. Further, size and distribution... Agent: Buchanan, Ingersoll & Rooney PC

20070221988 - Charge trapping device and method of producing the charge trapping device: A charge-trapping device includes a field effect transistor, which has source and drain regions. The source and drain regions have a dopant concentration profile, which has a gradient each in a vertical and a lateral direction with respect to a surface of a semiconductor substrate. The gradient in the lateral... Agent: Slater & Matsil LLP

20070221989 - Ultra-low drain-source resistance power mosfet: Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial... Agent: Wagner, Murabito & Hao LLP

20070221990 - Grounding front-end-of-line structures on a soi substrate: Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including... Agent: Hoffman, Warnick & D'alessandro LLC

20070221991 - Semiconductor device with increased channel area and decreased leakage current: The semiconductor device includes an active region, a recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess channel region is formed in the active region. The vertical... Agent: Heller Ehrman LLP

20070221992 - Castellated gate mosfet device capable of fully-depleted operation: A castellated-gate MOSFET I/O device capable of fully depleted operation is disclosed. The device includes a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed in the semiconductor substrate region, and... Agent: Law Office Of John L. Isaac

20070221993 - Method for making a thermally stable silicide: A semiconductor device and method of manufacturing are provided that include forming an alloy layer having the formula MbX over a silicon-containing substrate, where Mb is a metal and X is an alloying additive, the alloy layer being annealed to form a metal alloy silicide layer on the gate region... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070221994 - Driver circuit for switching device: A driver circuit that lowers the dependence of the loss in the wide gap semiconductor device upon the temperature is provided. A gate driver circuit for voltage driven power semiconductor switching device includes a power semiconductor switching device, a driver circuit for supplying a drive signal to a gate terminal... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070221995 - Semiconductor device and a method of manufacturing the same: The present invention realizes the miniaturization of a semiconductor device. On a first insulation film, an island-like semiconductor layer and a second insulation film which surrounds the semiconductor layer are formed, and resistance elements (for example, poly-silicon resistance elements) which are formed of a conductive film are arranged to be... Agent: Miles & Stockbridge PC

20070221996 - Cascode circuit and semiconductor device: A reference voltage circuit having a high power supply rejection ratio, and can operate at low voltage is provided. The reference voltage circuit includes a bias circuit constructed such that a depletion type transistor (3) is connected in series to a power supply voltage supply terminal of a load circuit,... Agent: Brinks Hofer Gilson & Lione

20070221997 - Driving circuit to avoid reverse current for soft switching dc motor: A driving circuit includes a power supply, an input capacitor, a Hall sensor, a first amplifier, a second amplifier, a full-bridge driver circuit, and a first operational amplifier. The input capacitor is coupled to the power supply. The input end of the first amplifier and the second amplifier is coupled... Agent: North America Intellectual Property Corporation

20070221998 - Semiconductor integrated circuit device and related method: Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate; forming selective epitaxial films on... Agent: Volentine & Whitt PLLC

20070222000 - Method of forming silicided gate structure: A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the... Agent: Duane Morris, LLPIPDepartment

20070221999 - Semiconductor devices and methods of manufacture thereof: A semiconductor device includes a gate electrode, and a source region and a drain region proximate the gate electrode. A silicide region is disposed over a top surface of the gate electrode, the source region, or the drain region. A non-silicide region is disposed proximate the silicide region over an... Agent: Slater & Matsil, L.L.P.

20070222001 - Semiconductor integrated circuit device: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070222002 - Intermediate semiconductor device having nitrogen concentration profile: A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for example, transistors, which include a hardened gate oxide and which may be characterized... Agent: Trask Britt, P.C./ Micron Technology

20070222003 - Semiconductor device and method of manufacturing the same: According to an aspect of the present invention, there is disclosed a semiconductor device comprising a semiconductor substrate, and a gate insulating film of a P-channel MOS transistor, formed on the semiconductor substrate. The gate insulating film has an oxide film (SiO2), and a diffusion preventive film (BN) containing boron... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070222005 - Integrated circuit having a semiconductor sensor device and method for producing the same: An integrated circuit having a semiconductor sensor device including a sensor housing partly filled with a rubber-elastic composition is disclosed. One embodiment has a sensor chip with sensor region arranged in the interior of the housing. The sensor housing has an opening to the surroundings which is arranged in such... Agent: Dicke, Billig & Czaja

20070222004 - Mems device using nimn alloy and method of manufacture: A material for forming a conductive structure for a MEMS device is described, which is an alloy containing about 0.01% manganese and the remainder nickel. Data shows that the alloy possesses advantageous mechanical and electrical properties. In particular, the sheet resistance of the alloy is actually lower than the sheet... Agent: Jaquelin K. Spong

20070222006 - Micromechanical component and corresponding manufacturing method: A micromechanical component which includes a substrate; a first rigid electrode system situated on or in the substrate; a second electrode system suspended on the substrate; an intermediate space provided between the first electrode system and the second electrode system; the second electrode system being mounted on the suspension post... Agent: Kenyon & Kenyon LLP

20070222009 - Integrated pedestal mount for mems structure: A substrate is provided for supporting a MEMS device. The substrate includes a housing with an integral pedestal mount for supporting the MEMS device. The substrate can be combined with a MEMS device to form a sensor.... Agent: Edell, Shapiro & Finnan, LLC

20070222008 - Method for manufacturing plastic packaging of mems devices and structure thereof: A plastic packaging of MEMS device and a method therefore are provided. The method includes the steps of: provide a carrier having a surface; provide at least one MEMS device having an active surface with a sensitive area and bonding pads thereon and a back surface; proceed a photoresist process... Agent: Workman Nydegger (f/k/a Workman Nydegger & Seeley)

20070222011 - Resonant inertial microsensor with variable thickness produced by surface engineering: p

20070222010 - Semiconductor integrated circuit chip with a nano-structure-surface passivation film and method of fabricating the same: A semiconductor integrated circuit (IC) chip includes an IC chip body and a nano-structure-surface passivation film. The IC chip body has at least one surface. The nano-structure-surface passivation film is formed on the at least one surface. The nano-structure-surface passivation film including nano-particles and a carrier resin protects the IC... Agent: Birch Stewart Kolasch & Birch

20070222007 - Method of manufacturing an electronic device and electronic device: A method for manufacturing a micro-electromechanical systems (MEMS) device, comprising providing a base layer (10) and a mechanical layer (12) on a substrate (14), providing a sacrificial layer (16) between the base layer (10) and the mechanical layer (12), providing an etch stop layer (18) between the sacrificial layer (16)... Agent: Nxp, B.v. Nxp Intellectual Property Department

20070222012 - Semiconductor device: A semiconductor device, including a first region (100) of semiconductor material of a first conductivity type. The semiconductor device comprises an elongated spatial element (111, 112, 113) of semiconductor material of a second conductivity type protruding into a first region (100) of semiconductor material of a first conductivity type; and... Agent: Sughrue Mion, PLLC

20070222013 - Nanoscale volumetric imaging device: The invention provides an imaging device comprised of nanoscale crossbar arrays upon a transmissive medium. The preferred embodiment employs a BOPET film as the transparent material bearing addressable nanoscale arrays, and the arrays connected to leads through micro lithographic techniques, and in turn connected to a logic device. An imaging... Agent: Deborah Neville

20070222014 - Integrated sheet metal forming, assembly and inspection system: An integrated forming, assembly and inspection system includes a plurality of robotic material conveyors. The integrated system also includes a forming subsystem including sheet metal drawing apparatus, a roller hemming subsystem, and an inspection subsystem. The plurality of robotic material conveyors are operable to convey assembly workpieces to and from... Agent: Christopher J. Fildes Fildes & Outland. P.C.

20070222015 - Trench photodetector: Trench type PIN photodetectors are formed by etching two sets of trenches simultaneously in a semiconductor substrate, the wide trenches having a width more than twice as great as the narrow trenches by a process margin; conformally filling both types of trenches with a sacrificial material doped with a first... Agent: International Business Machines Corporation Dept. 18g

20070222016 - Photodetector arrangement, measurement arrangement with a photodetector arrangement and process for operating a measurement arrangement: A photodetector arrangement has a semiconductor body formed of a substrate, a first layer at a first main surface of the semiconductor body, and a second layer at a second main surface of the semiconductor body. The second main surface is remote from the first main surface. A first and... Agent: Roberts, Mlotkowski & Hobbes

20070222017 - Photodetector arrangement, measurement arrangement with a photodetector arrangement and process for operating a measurement arrangement: A photodetector arrangement has a semiconductor body with a substrate, and first, second and third layers. The first layer is located at the first main surface of the semiconductor body which is suited for reception of incident photon radiation which is to be detected. The second layer is located at... Agent: Roberts, Mlotkowski & Hobbes

20070222018 - Forming of the periphery of a schottky diode with mos trenches: A method for forming a component of TMBS type having its periphery formed of a trench with insulated walls filled with a conductor, including the steps of depositing on a semiconductor substrate a thick layer of a first insulating material and a thin layer of a second material; simultaneously digging... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070222019 - Trench semiconductor device and method of manufacturing it: Consistent with an example embodiment, a reduced surface field effect type (RESURF) semiconductor device is manufactured having a drift region over a drain region. Trenches are formed through openings in mask. A trench insulating layer is deposited on the sidewalls and base of the trenches followed by an overetching step... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070222022 - Semiconductor device: A semiconductor device for improving performance of a p-channel transistor and an n-channel transistor having multi-finger structures. Gates of the n-channel transistor are arranged so that their gate width direction is parallel to one side of a first region. Gates of the p-channel transistor are arranged so that their gate... Agent: Ditthavong Mori & Steiner, P.C.

20070222020 - Dram (dynamic random access memory) cells: A DRAM cell with a self-aligned gradient P-well and a method for forming the same. The DRAM cell includes (a) a semiconductor substrate; (b) an electrically conducting region including a first portion, a second portion, and a third portion; (c) a first doped semiconductor region wrapping around the first portion,... Agent: Schmeiser, Olsen & Watts

20070222024 - Integrated circuit and production method: An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers, forming a damaging reverse current, cannot flow into the substrate.... Agent: Dicke, Billig & Czaja

20070222023 - Integrated circuit having a semiconductor arrangement and method for producing it: An integrated circuit having a semiconductor component arrangement and production method is disclosed. In one embodiment, an oxide layer region is provided as a protection against oxidation in the edge region on the surface region of an underlying semiconductor material region.... Agent: Dicke, Billig & Czaja

20070222021 - Shielded through-via: A shielded through-via that reduces the effect of parasitic capacitance between the through-via and surrounding wafer while providing high isolation from neighboring signals. A shield electrode is formed in the insulating region and spaced apart from the through-via. A coupling element couples at least the time-varying portion of the signal... Agent: Koppel, Patrick & Heybl

20070222025 - Termination for a superjunction device: A superjunction device that includes a termination region having a transition region adjacent the active region thereof, the transition region including a plurality of spaced columns.... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20070222026 - Method of manufacturing semiconductor device: A semiconductor device includes a semiconductor substrate having trenches extending thereinto. A trench type insulating film fills the trenches. The trench type insulating film includes a first and second insulating film and is laminated in a portion of the trenches.... Agent: Mcginn Intellectual Property Law Group, PLLC

20070222028 - Efuse and method of manufacturing efuse: A silicide region includes a first contact region, a fuse region having a narrower longitudinal width than that of the first contact region, and a second contact region provided on an opposite side of the fuse region with respect to the first contact region. A non-silicide region is provided at... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070222027 - Electronic fuse elements with constricted neck regions that support reliable fuse blowing: Integrated circuit devices include a substrate and a fuse element on the substrate. The fuse element includes a metal pattern (e.g., dumbell-shaped) having a neck region therein that is sufficiently constricted to enable complete rupture of the neck region when the metal pattern in the fuse element is blown. A... Agent: Myers Bigel Sibley & Sajovec

20070222029 - Semiconductor device having a fuse element: A portion to be melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown... Agent: Young & Thompson

20070222031 - Capacitor structure: A capacitor structure with a cross-coupling design is provided. In the capacitor structure, conductive lines or electrode plates are coupled together by cross coupling an electrode above or below or aside the other electrode. By cross coupling and fewer vias, the largest capacitance value can be obtained within a minimum... Agent: Jianq Chyun Intellectual Property Office

20070222030 - Low temperature deposition and ultra fast annealing of integrated circuit thin film capacitor: Some embodiments of the invention include thin film capacitors formed on a package substrate of an integrated circuit package. At least one of the film capacitors includes a first electrode layer, a second electrode layer, and a dielectric layer between the first and second electrode layers. Each of the first... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070222032 - Bipolar transistor and method for producing a bipolar transistor: A bipolar transistor has a base, an emitter and an emitter contact. The emitter has a monocrystalline layer and a polycrystalline layer, which are disposed between the base and the emitter contact in the mentioned order.... Agent: Maginot, Moore & Beck Chase Tower

20070222033 - Semiconductor device and power amplifier: A semiconductor device 1 includes a plurality of amplifier circuits 2 connected in parallel between an input terminal RFin and an output terminal RFout. Each of the amplifier circuits 2 includes an HBT 3, an oscillation stabilizing circuit 4 connected between the input terminal RFin and a base B of... Agent: Ostrolenk Faber Gerb & Soffen

20070222034 - Graded index silicon geranium on lattice matched silicon geranium semiconductor alloy: A lattice matched silicon germanium (SiGe) semiconductive alloy is formed when a {111} crystal plane of a cubic diamond structure SiGe is grown on the {0001} C-plane of a single crystalline Al2O3 substrate such that a <110> orientation of the cubic diamond structure SiGe is aligned with a <1,0,−1,0> orientation... Agent: National Aeronautics And Space Administration Langley Research Center

20070222035 - Stress intermedium engineering: Embodiments of the invention provide structures and methods for forming a strained MOS transistor. A stressor layer is formed over the transistor. Embodiments include an intermedium layer between the stressor layer and a portion of the transistor. In an embodiment, the intermedium comprises a layer formed between the stressor layer... Agent: Slater & Matsil, L.L.P.

20070222036 - Semiconductor memory device and methods of manufacturing and operating the same: A semiconductor memory device and methods of manufacturing and operating the same may be provided. The semiconductor memory device may include a substrate, at least a pair of fins protruding from the semiconductor substrate and facing each other with a gap between fins of the pair of fins, an insulating... Agent: Harness, Dickey & Pierce, P.L.C

20070222037 - Semiconductor wafer and method for making the same: A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. WAT pads are disposed along the dicing line. Each of the WAT... Agent: North America Intellectual Property Corporation

20070222038 - Crystalline semiconductor film, semiconductor device, and method for manufacturing thereof: A method for manufacturing is: forming an insulating film over a substrate; forming an amorphous semiconductor film over the insulating film; forming over the amorphous semiconductor film, a silicon nitride film in which a film thickness is equal to or more than 200 nm and equal to or less than... Agent: Nixon Peabody, LLP

20070222039 - Semiconductor device and manufacturing method of a semiconductor device: A semiconductor device includes a multi-layer substrate and a semiconductor element mounted on the multi-layer substrate. The multi-layer substrate contains a plurality of circuit-formation layers joined by a first resin material. The semiconductor element is mounted on the multi-layer substrate by being joined to the multi-layer substrate by a second... Agent: Kratz, Quintos & Hanson, LLP

20070222041 - Chip package: A chip package including a package substrate, a chip, several bonding wires, a flash-resisting ring and a molding compound. The package substrate includes a carrying surface and several contacts disposed on the carrying surface. The chip is disposed on the carrying surface. A surface of the chip away from the... Agent: Birch Stewart Kolasch & Birch

20070222040 - Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for manufacturing the same: A leadless semiconductor package with an electroplated layer embedded in an encapsulant and its manufacturing processes are disclosed. The package primarily includes a half-etched leadframe, a chip, an encapsulant, and an electroplated layer. The half-etched leadframe has a plurality of leads and a plurality of outer pads integrally connected to... Agent: Troxell Law Office PLLC

20070222043 - Semiconductor device and a method of manufacturing the same: A technique is provided for improving the security of information stored in a semiconductor device. Multilayer wiring layers are formed over a semiconductor substrate. Wirings are formed on the uppermost wiring layer among those multilayer wiring layers. On the wirings, there is formed, in the following order, a silicon oxide... Agent: Miles & Stockbridge PC

20070222042 - Semiconductor devices and electrical parts manufacturing using metal coated wires: The device of this invention includes a semiconductor die attached to a bare copper lead frame and electrically coupled to a lead by a metal wire coated with a metallic material. The device would function similarly to devices where the lead frames were coated with other metallic materials, but at... Agent: Hiscock & Barclay, LLP

20070222049 - Package structure and manufacturing method thereof: A package structure and a manufacturing method thereof are provided. The package structure includes a substrate, a chip and a packing material layer. The substrate has a top surface and a lateral surface. The top surface is connected with the lateral surface. The chip is disposed on the top surface.... Agent: Birch Stewart Kolasch & Birch

20070222050 - Package structure and manufacturing method thereof: A stack package includes a printed circuit board; at least two semiconductor chips stacked on the printed circuit board, each having first re-distribution lines formed on the upper surface thereof and connected to bonding pads, through silicon vias which are formed therethrough and connected to the first re-distribution lines, and... Agent: Ladas & Parry LLP

20070222045 - Semiconductor device for chip-on-chip configuration and method for manufacturing the same: A semiconductor device that reduces the size and cost of functional macro chips used in a chip-on-chip configuration. Functional macro chips each include a macro region. The macro regions are formed adjacent to one another. A pad region for testing the functional macro chips is formed surrounding the macro regions.... Agent: Staas & Halsey LLP

20070222047 - Semiconductor package structure: A semiconductor package structure includes a substrate, a first chip, a second chip, a wire, and an encapsulant. The substrate with a cavity has a first surface and a second surface. The cavity penetrates the first surface and the second surface. The first surface and the second surface have a... Agent: Birch Stewart Kolasch & Birch

20070222051 - Stacked semiconductor device: A stacked semiconductor device includes a first semiconductor element bonded on a circuit base. The first semiconductor element is electrically connected to a connection part of the circuit base via a first bonding wire. A second semiconductor element is bonded on the first semiconductor element via a second adhesive layer... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070222046 - Electronic circuit device: An electronic circuit device includes a sub-board disposed upright on a main board. The sub-board is electrically coupled to the main board via a board terminal) disposed at sub-board edge. A semiconductor element is mounted on the sub-board facing the sub-board in parallel. A temperature sensor is also mounted on... Agent: Ratnerprestia

20070222044 - Electronic component and methods to produce an electronic component: An electronic component includes at least one vertical MOSFET device, a leadframe and a contact clip. A source electrode and gate electrode are provided on a lower surface of the MOSFET device and are mounted on a source portion and a gate portion, respectively, of the leadframe. The contact clip... Agent: Baker Botts, L.L.P.

20070222048 - Package structure: A package structure is provided herein. The package structure includes a first substrate and a second substrate. A first seal ring having a first height is disposed around a predetermined area of the first substrate and between the first and second substrates. A second seal ring having a second height... Agent: Lowe Hauptman Berner, LLP

20070222052 - Wiring structure, multilayer wiring board, and electronic device: A wiring structure includes a general signal line, a differential signal line having a pair of signal wiring lines and a reference potential layer. The signal wiring lines respectively transmit differential signals of which waveforms are inverted from each other. The reference potential layer is arranged to have a distance... Agent: Ditthavong Mori & Steiner, P.C.

20070222055 - Method and system for stacking integrated circuits: A design for stacking integrated circuits is described. Some integrated circuits have multiple signal pads that are common between a top integrated circuit and a bottom integrated circuit in an integrated circuit pair. These common pads are placed symmetrically on the integrated circuit. Unique signal pads are provided independently to... Agent: Honeywell International Inc.

20070222054 - Semiconductor components with through wire interconnects: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on... Agent: Stephen A. Gratton

20070222053 - Semiconductor constructions having interconnect structures, methods of forming interconnect structures, and methods of forming semiconductor constructions: The invention includes methods of forming semiconductor interconnect structures. A substrate is provided having metal bumps associated with contact pads. A plate having a plurality of cavities containing solder is provided. The metal bumps are inserted into the cavities. The invention includes methods of forming surface-mounting structures. A wafer having... Agent: Wells St. John P.s.

20070222056 - Encapsulated electrical component and production method: A micro-electro-mechanical systems (MEMS) component includes a panel, a chip having an underside containing active component structures, where the chip is mounted on the panel via bumps, a frame structure on the panel and enclosing an installation site of the chip, and a jet-printed structure closing a seam between frame... Agent: Fish & Richardson PC

20070222057 - Perpendicularly oriented electrically active element method and system: Embodiments of the present invention provide an apparatus, a system, and a method, and include a generally rectilinear body having a first surface and a second surface. The second surface is substantially perpendicular to the first surface. An electrically operative element is disposed on the first surface, and has opposite... Agent: Schwabe, Williamson & Wyatt, P.C.

20070222058 - Stitched micro-via to enhance adhesion and mechanical strength: A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070222060 - Compact power semiconductor module having a connecting device: A power semiconductor module having a housing, a substrate with conductor tracks and power semiconductor components arranged on the conductor tracks, and a connecting device. The connecting device comprises a film composite with first and second conductive layers, which are respectively patterned and thus form conductor tracks, and an insulating... Agent: Cohen, Pontani, Lieberman & Pavane

20070222059 - Direct power delivery into an electronic package: In some embodiments, direct power delivery into an electronic package is presented. In this regard, a substrate is introduced having a conductive substrate core designed to physically connect with a power cable. Other embodiments are also disclosed and claimed.... Agent: Intel Corporation C/o Intellevate, LLC

20070222061 - Semiconductor module with serial bus connection to multiple dies: The semiconductor module includes a heat spreader and at least two semiconductors coupled thereto. Each of the semiconductors comprises a die containing integrated circuitry and electrical connectors coupled to the die. The module also includes a flexible circuit having opposing first and second sides. The first side of the flexible... Agent: Morgan Lewis & Bockius LLP/rambus Inc.

20070222062 - Electronic parts packaging structure in which a semiconductor chip is mounted on a wiring substrate and buried in an insulation film: The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where the connection terminal is directed upward,... Agent: Kratz, Quintos & Hanson, LLP

20070222063 - Electronic device capable of varying appearance: An electronic device capable of varying appearance includes a first cover, a second cover, and a third cover. The second cover is rotatably connected to the first cover. The third cover is movably connected to the first cover. The third cover is moved relative to the first cover from a... Agent: Quintero Law Office, PC

20070222064 - Thermal paste containment for semiconductor modules: A semiconductor module structure and a method of forming the semiconductor module structure are disclosed. The structure incorporates a die mounted on a substrate and covered by a lid. A thermal compound is disposed within a thermal gap between the die and the lid. A barrier around the periphery of... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070222065 - Method for precision assembly of integrated circuit chip packages: An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the... Agent: Schmeiser, Olsen & Watts

20070222067 - Dielectric device: The dielectric device includes a substrate, a lower electrode, a dielectric layer, and an upper electrode. The lower electrode is bonded onto the substrate. The dielectric layer is bonded onto the lower electrode. The dielectric layer is obtained through thermal treatment of a film layer formed by spraying of a... Agent: Burr & Brown

20070222068 - Semiconductor device having multilayered interconnection structure formed by using cu damascene method, and method of fabricating the same: Disclosed are a semiconductor device having a multilayered interconnection structure formed by using a Cu damascene method, and a method of fabricating the same. A Cu interconnection is buried on a first barrier metal layer in a trench formed in the surface of an insulating film. An interlayer dielectric film... Agent: Foley And Lardner LLP Suite 500

20070222069 - Semiconductor integrated circuit device: A semiconductor integrated circuit device according to an embodiment of the invention includes: a protective element formed on a semiconductor substrate; and a plurality of wiring layers composed of insulating layers including a layer that is a low dielectric-constant film, and metal lines, in which a metal line in a... Agent: Foley And Lardner LLP Suite 500

20070222070 - Contact piece member, contactor and contact method: In a contactor contact piece members can be arranged at a fine pitch, and a contact can be made surely by a small contact pressure. The contact piece members electrically connect an electronic part to an external circuit. The contact piece member is formed of an electrically conductive material in... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070222066 - Structure and method of forming electrodeposited contacts: A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and... Agent: Connolly Bove Lodge & Hutz LLP (for IBM Yorktown)

20070222071 - Nitrogen rich barrier layers and methods of fabrication thereof: A semiconductor device includes a material layer and a first barrier layer disposed over the material layer. The first barrier layer includes a nitrogen-rich region formed at a top surface of the first barrier layer. A conductor is disposed over the first barrier layer such that the first barrier layer... Agent: Slater & Matsil LLP

20070222072 - Chip package and fabricating method thereof: A chip package including a chip, a package substrate, and a plurality of bumps is provided. The chip has a plurality of chip pads disposed on a surface of the chip. The package substrate has a plurality of first substrate pads, a plurality of second substrate pads, and a surface... Agent: J.c. Patents, Inc. Suite 250

20070222073 - Structure and method to improve current-carrying capabilities of c4 joints: A system and method comprises depositing a dielectric layer on a substrate and depositing a metal layer on the dielectric layer. The system and method further includes depositing a high temperature diffusion barrier metal cap on the metal layer. The system and method further includes depositing a second dielectric layer... Agent: Greenblum & Bernstein, P.L.C

20070222074 - Electric device with vertical component: A method of providing an electric device with a vertical component and the device itself are disclosed. The electric device may be a transistor device, such as a FET device, with a vertical channel, such as a gate around transistor, or double-gate transistor First an elongate structure, such as a... Agent: Philips Intellectual Property & Standards

20070222075 - Wiring material and a semiconductor device having a wiring using the material, and the manufacturing method thereof: An object of the present invention is to realize a semiconductor device having a high TFT characteristic. In manufacturing an active matrix display device, electric resistivity of the electrode material is kept low by preventing penetration of oxygen ion into the electrode in doping of an impurity ion. A display... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070222076 - Single or dual damascene structure reducing or eliminating the formation of micro-trenches arising from lithographic misalignment: A semiconductor device is provided that includes a substrate, a lower dielectric layer located on a substrate, and at least one lower conductive interconnect located in the lower dielectric layer. A cap layer is located over the lower conductive interconnect and at least a first dielectric layer is located on... Agent: Mayer & Williams PC

20070222077 - Composite semiconductor device, led head that employs the composite semiconductor device, and image forming apparatus that employs the led head: A composite semiconductor device includes a substrate, a plurality of circuits, a semiconductor thin film layer, and a dummy pattern. The circuits are formed on the substrate, and include one or more wiring layers. The semiconductor thin film layer includes semiconductor elements and is disposed on an uppermost surface of... Agent: Rabin & Berdo, PC

20070222079 - Method of manufacturing wiring substrate, and liquid ejection head manufactured by same: The method of manufacturing a wiring substrate includes the steps of: forming a photocatalyst containing layer which is made of a material containing a photocatalytic material, on a substrate made of an insulating material; forming a resin layer in regions other than wire regions on the photocatalyst containing layer; radiating... Agent: Birch Stewart Kolasch & Birch

20070222078 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a first copper-containing conductive film formed on a substrate, insulating films formed on the first copper-containing conductive film with a concave portion reaching the first copper-containing conductive film, a second barrier insulating film formed to cover the side wall of the concave portion of these insulating... Agent: Young & Thompson

20070222080 - Semiconductor device and a method of manufacturing the same and designing the same: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070222082 - Semiconductor integrated circuit device: A semiconductor integrated circuit device of improved wireability, fewer number of wiring layers and strengthened power supply includes a plurality of power pads placed on a semiconductor chip and a plurality of signal pads placed on the semiconductor chip and configured to have a width less than that of the... Agent: Young & Thompson

20070222081 - Surface treatment of inter-layer dielectric: When an interconnect structure is built on porous ultra low k (ULK) material, the bottom of the trench and/or via is usually damaged by a following metallization process which may be suitable for dense higher dielectric materials. Embodiment of the present invention may provide a method of forming an interconnect... Agent: International Business Machines Corporation Dept. 18g

20070222083 - Rf and mmic stackable micro-modules: A new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved. The method comprises, first, providing a substrate. The substrate is etched through to form holes for planned shielded vias with microstrip ground plane. A first dielectric layer is formed... Agent: Saile Ackerman LLC

20070222084 - Device for avoiding parasitic capacitance in an integrated circuit package: An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and... Agent: Lsi Corporation

20070222085 - Semiconductor device and fabrication process thereof: A semiconductor device includes a mount substrate and a semiconductor chip mounted upon the mount substrate via a metal bump, wherein metal bump includes an inner part joined to the semiconductor chip and an outer part covering the inner part, the outer part having an increased hardness as compared with... Agent: Kratz, Quintos & Hanson, LLP

20070222087 - Semiconductor device with solderable loop contacts: A method of easily manufacturing reliable solder contacts on semiconductor dies are made in the shape of a loop made from metal wires or ribbons that may be coated with other solderable metals. The loops can be in multi loop form, single loop forms or both on the semiconductor die.... Agent: Hiscock & Barclay, LLP

20070222086 - On-die bond wires system and method for enhancing routability of a redistribution layer: An integrated circuit includes a first die and a second die positioned in a package. The first die has a redistribution layer formed on the die and including a plurality of relocated bond pads. The relocated bond pads are positioned near an inner edge of the first die that is... Agent: Kathy Manke Avago Technologies Limited

20070222088 - Overlay metrology mark: An overlay metrology mark for determining the relative position between two or more layers of an integrated circuit structure comprising a first mark portion associated with and in particular developed on a first layer and a second mark portion associated with and in particular developed on a second layer, wherein... Agent: Perkins Coie LLP Patent-sea

20070222089 - Semiconductor wafer, semiconductor device, and method of manufacturing semiconductor device: Disclosed are a semiconductor wafer, a semiconductor device, and a method of manufacturing the semiconductor device, which are capable of easily carrying out an alignment between a semiconductor substrate and an electron beam exposure apparatus. There is provided a method including steps of: forming an interlayer insulating film 25 on... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070215854 - Electrical compensation and fault tolerant structure for light emitting device array: Light emitting device arrays comprising alternate current routes that redirect supplied current in the event of open circuit due to a damaged light emitting element are provided. Furthermore, passive light emitting device arrays that provide current compensation for lost light output are provided.... Agent: Chen-jean Chou

20070215855 - Wavelength tunable light emitting device by applying pressure: A wavelength-tunable light emitting device. A resilient support substrate is provided, and a light emitting diode is formed on an area of the support substrate. The light emitting diode includes a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer formed in their order.... Agent: Mcdermott Will & Emery LLP

20070215858 - Photo detector: A photo detector is provided with a plurality of quantum dot layers and first conductive type contact layers provided at both sides of the plurality of quantum dot layers so as to sandwich them; a second conductive type impurity is doped in a first semiconductor layer formed between one first... Agent: Kratz, Quintos & Hanson, LLP

20070215871 - Electroluminescence device, manufacturing method thereof, and electronic apparatus: An organic electroluminescence device including: a substrate having conductivity on at least one side; a first insulation film, formed on one side of the substrate, while having an aperture which partially exposes the same side of the substrate; a semiconductor film, formed on the first insulation film, while covering a... Agent: Oliff & Berridge, PLC

20070215870 - Organic light emitting display (oled): An Organic Light Emitting Display (OLED) includes: a substrate having defined pixel region and non-pixel regions and including an organic light emitting element arranged in the pixel region; a driver IC arranged in the non-pixel region of the substrate and adapted to supply a signal to the organic light emitting... Agent: Robert E. Bushnell Suite 300

20070215872 - Organic semiconductor material and organic device using the same: The present invention encompasses an organic field-effect transistor comprising an n-type organic semiconductor formed of a fullerene derivative having a fluorinated alkyl group which is expressed by the following chemical formula (wherein at least any one of R1, R2 and R3 is a perfluoro alkyl group or a partially-fluorinated semifluoro... Agent: Sughrue Mion, PLLC

20070215873 - Near natural breakdown device: A semiconductor device includes a semiconductor region wherein the semiconductor region is a forced or non-forced Near Natural breakdown region, which is completely depleted when a predetermined voltage having a magnitude less than or equal to the breakdown voltage of a non-Natural breakdown (for example, Zener breakdown and Avalanche breakdown)... Agent: Macpherson Kwok Chen & Heid LLP

20070215875 - Semiconductor device and method for fabricating the same: A semiconductor device includes a substrate, first, second, and third gate lines disposed over the substrate, the first and second gate lines defining a first trench with a first aspect ratio, the second and third gate lines defining a second trench with a second aspect ratio, a first insulating layer... Agent: Townsend And Townsend And Crew, LLP

20070215876 - Thin film transistor panel and manufacturing method thereof: A TFT array panel having signal lines of low resistivity is presented. The TFT array panel includes a substrate; a gate line including a gate electrode formed on the substrate and having a single-layered structure; a gate insulating layer formed on the gate line; a semiconductor layer formed on the... Agent: Macpherson Kwok Chen & Heid LLP

20070215877 - Crystallization method, thin film transistor manufacturing method, thin film transistor, display, and semiconductor device: According to a crystallization method, in the crystallization by irradiating a non-single semiconductor thin film of 40 to 100 nm provided on an insulation substrate with a laser light, a light intensity distribution having an inverse peak pattern is formed on the surface of the substrate, a light intensity gradient... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070215882 - Light emitting device and method of manufacturing the same: A light emitting device and a method of manufacturing the same are provided. The light emitting device comprises a first conductive type lower semiconductor layer, a current diffusion layer, a first conductive type upper semiconductor layer, an active layer, and a second conductive type semiconductor layer. The current diffusion layer... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070215884 - Backside accessible display: A light board is made with a receptacle substrate for holding cassette light units. The convenience of assembly and disassembly of the light units from the receptacle substrate makes the product easily to be maintained for changing different color light units, changing different displaying patterns, and removing or replacing a... Agent: Lowe Hauptman Berner, LLP

20070215885 - Semiconductor device: A semiconductor device having small leakage current and high breakdown voltage during reverse blocking, small on-state resistance and large output current at forward conduction, short reverse recovery time at shutoff, and high peak surge current value is provided. An n-type layer is made of a group-III nitride, and a p-type... Agent: Burr & Brown

20070215889 - Aromatic amine compound, and light-emitting element, light-emitting device, and electronic appliance using the aromatic amine compound: An object of the present invention is to provide a novel aromatic amine compound, and a light-emitting element, a light-emitting device, and an electronic appliance with high luminous efficiency. An aromatic amine compound expressed by General Formula (1) and a light-emitting element, a light-emitting device, and an electronic appliance formed... Agent: Eric Robinson

20070215887 - Gallium nitride crystal and method of making same: There is provided a GaN single crystal at least about 2.75 millimeters in diameter, with a dislocation density less than about 104 cm−1, and having substantially no tilt boundaries. A method of forming a GaN single crystal is also disclosed. The method includes providing a nucleation center, a GaN source... Agent: General Electric Company Global Research

20070215894 - Insulation structure for high temperature conditions and manufacturing method thereof: An insulation structure for high temperature conditions and a manufacturing method thereof. In the insulation structure, a substrate has a conductive pattern formed on at least one surface thereof for electrical connection of a device. A metal oxide layer pattern is formed on a predetermined portion of the conductive pattern... Agent: Mcdermott Will & Emery LLP

20070215893 - Light diffusion reflection sheet with buffering effect: A light reflection sheet includes a transparent buffering layer and a reflection layer, formed on two opposite surfaces of a transparent substrate, respectively. With the buffering effect provided by the transparent buffering layer, the possible damage caused to the light reflection sheet or a V-cut light guide plate when they... Agent: Bromberg & Sunstein LLP

20070215852 - Manufacturing method for pipe-shaped electrode phase change memory: A method for manufacturing a memory cell device includes forming a bottom electrode comprising a pipe-shaped member, a top, a bottom and sidewalls having thickness in a dimension orthogonal to the axis of the pipe-shaped member, and having a ring-shaped top surface. A disc shaped member is formed on the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070215853 - Multi-layer phase-changeable memory devices and methods of fabricating the same: A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second electrodes are configured to provide an electrical signal to the phase-changeable material pattern. The phase-changeable material pattern includes a first phase-changeable material layer and a... Agent: Myers Bigel Sibley & Sajovec

20070215856 - Quantum dot electroluminescence device and method of fabricating the same: A quantum dot electroluminescence device and a method of fabricating the same are provided. The quantum dot electroluminescence device comprises an insulating substrate; a quantum dot luminescence layer supported by the insulating substrate, and composed of a monolayer or multilayer of quantum dots, which are cross-linked by a cross-link agent;... Agent: Cantor Colburn, LLP

20070215857 - Semiconductor quantum dot device: A p-type semiconductor barrier layer is provided in the vicinity of undoped quantum dots, and holes in the p-type semiconductor barrier layer are injected in advance in the ground level of the valence band of the quantum dots. Lowering the threshold electron density of conduction electrons in the ground level... Agent: Mcginn Intellectual Property Law Group, PLLC

20070215859 - Strained silicon with elastic edge relaxation: A thin blanket epitaxial layer of SiGe is grown on a silicon substrate to have a biaxial compressive stress in the growth plane. A thin epitaxial layer of silicon is deposited on the SiGe layer, with the SiGe layer having a thickness less than its critical thicknesses. Shallow trenches are... Agent: Hogan & Hartson L.L.P.

20070215860 - Infrared photodetector: An infrared photodetector that is capable of efficiently detecting single photon over an extensive range of wavelengths from several μm to several hundreds of μm and is suitable for arraying, and wherein an oscillatory electric field of a single infrared photon (37) parallel to a plane of the patch section... Agent: Masao Yoshimura Chen Yoshimura

20070215861 - Quantum interference effect transistor (quiet): A molecular-based switching device and method for controlling charge transport across a molecule. The molecular-based switching device includes a molecule having first and second nodes in between which destructive quantum interference restricts electrical conduction from the first node to the second node in an off-state, a first electrode connected to... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070215862 - Methods for preparing entangled quantum states: Various embodiments of the present invention are directed to methods for generating an entangled state of qubits. In one embodiment of the present invention, a method for preparing an entangled state of qubits comprises providing a probe and N non-interacting qubits, each qubit comprises a linear superposition of two basis... Agent: Hewlett-packard Company Intellectual Property Administration

20070215863 - Fabricating apparatus with doped organic semiconductors: A method includes forming a semiconducting region including polyaromatic molecules on a surface of a substrate. The method also includes forming over the region a substantially oxygen impermeable dielectric layer. The act of forming a semiconducting region includes exposing the molecules to oxygen while exposing the molecules to visible or... Agent: Hitt Gaines, PC Alcatel-lucent

20070215866 - Novel molecular structures with controllable electron conducting properties: Aromatic and heteroaromatic molecular structures with controllable electron conducting properties are derived from the incorporation of electron active substituents in selective positions. Such compounds can form self-assembled layers on metal or other substrates, and can be used in molecular scaled opto-electronic devices including field-effect transistors, light-emitting diodes and photovoltaic cells.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070215865 - Opto-electronic devices exhibiting enhanced efficiency: o

20070215868 - Organic photovoltaic cells utilizing ultrathin sensitizing layer: A photosensitive device includes a plurality of organic photoconductive materials disposed in a stack between a first electrode and a second electrode, including a first continuous layer of donor host material, a second continuous layer of acceptor host material, and at least one other organic photoconductive material disposed as a... Agent: Kenyon & Kenyon LLP

20070215869 - Semiconductor device and method for manufacturing the same: It is an object of the present invention to provide a volatile semiconductor device into which data can be additionally written and which is easy to manufacture, and a method for manufacturing the same. It is a feature of the present invention that a semiconductor device includes an element formation... Agent: Eric Robinson

20070215867 - Spirofluorene derivative, material for light-emitting element, light-emitting element, light-emitting device, and electronic device: It is an object of the present invention to provide a material having a high Tg and a wide energy gap. The present invention provides a spirofluorene derivative represented by General Formula 1. (In the formula, R1 is any one of hydrogen, an alkyl group having 1 to 4 carbon... Agent: Eric Robinson

20070215864 - Use of pi-conjugated organoboron polymers in thin-film organic polymer electronic devices: Pi-conjugated organoboron polymers for use in thin-film organic polymer electronic devices. The polymers contain aromatic and or unsaturated repeat units and boron atoms. The vacant p-orbital of the boron atoms conjugate with the pi-conjugated orbital system of the aromatic or unsaturated monomer units extending the pi-conjugation length of the polymer... Agent: Greenlee Winner And Sullivan P C

20070215874 - Layout and process to contact sub-lithographic structures: An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed... Agent: Keusey, Tutunjian & Bitetto, P.C.

20070215878 - Light emitting device: A light emitting device includes: a substrate; a current diffusion layer; and a light emitting structure sandwiched between the substrate and the current diffusion layer, and including a plurality of light emitting protrusions extending between the substrate and the current diffusion layer, a plurality of interconnected spaces disposed among and... Agent: Davidson Berquist Jackson & Gowdey LLP

20070215880 - Light emitting material, light emitting element, light emitting device and electronic device: The present invention provides a light emitting material having high electric conductivity, and further a light emitting element which can be driven at low voltage. Light emitting devices and electronic devices with reduced power consumption can also be provided. A light emitting element including a light emitting material is provided... Agent: Fish & Richardson P.C.

20070215881 - Light-emitting element and manufacturing method thereof: It is an object of the present invention to provide a new light-emitting element and manufacturing method thereof in which actively diffusing a material into a film formation layer is utilized where an interface state and interdiffusion between a compound semiconductor substrate and a film formation layer formed thereover are... Agent: Fish & Richardson P.C.

20070215879 - Opto-electronic devices exhibiting enhanced efficiency:

20070215883 - Electroluminescent devices, subassemblies for use in making electroluminescent devices, and dielectric materials, conductive inks and substrates related thereto: Electroluminescent devices, subassemblies for use in making electroluminescent devices, and dielectric materials, conductive inks and substrates for use in making such subassemblies. One such electroluminescent device includes a first subassembly having an emitter layer for emitting light upon the application of an electric field and a first conductive layer adjacent... Agent: Lexmark International, Inc. Intellectual Property Law Department

20070215886 - Compound semiconductor light-emitting device and production method thereof: A pn-junction compound semiconductor light-emitting device is provided, which comprises a stacked structure including a light-emitting layer composed of an n-type or a p-type aluminum gallium indium phosphide and a light-permeable substrate for supporting the stacked structure, and the stacked structure and the light-permeable substrate being joined together, wherein the... Agent: Sughrue Mion, PLLC

20070215888 - Light-emitting device, method for driving the same, and electronic apparatus: A light-emitting device includes a plurality of pixels, a temperature-detection pixel, a temperature detector, an applied-current calculator, and a current applying unit disposed on a substrate. The pixels include display light-emitting elements for displaying information. The temperature-detection pixel is provided within a display area where the pixels are disposed and... Agent: Oliff & Berridge, PLC

20070215891 - Collimated led array with reflector: A light emitting diode (LED) array with beam directors outputting a high-intensity collimated beam. The LED array is constructed from a substrate component on which the LEDs and necessary electronics are disposed and a director attachment having a plurality of beam directors. The beam directors have a unique structure that... Agent: Koppel, Patrick & Heybl

20070215892 - Light emitting divice, and back light and liquid crystal display employing it: A light emitting device 1 has, as a light source, a light emitting semiconductor element such as a light emitting diode 2. Light radiated from the light emitting diode 2 is converted to visible light in a light emitting part 8 having a plurality of phosphors 9 different in emission... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070215890 - White led for backlight with phosphor plates: A white light LED for use in backlighting or otherwise illuminating an LCD is described where the white light LED comprises a blue LED over which is affixed a preformed red phosphor platelet and a preformed green phosphor platelet. In one embodiment, to form a platelet, a controlled amount of... Agent: Patent Law Group LLP

20070215896 - Light emitting diode package structure and method of manufacturing the same: A light emitting diode package structure having a heat-resistant cover and a method of manufacturing the same include a base, a light emitting diode chip, a plastic shell, and a packaging material. The plastic shell is in the shape of a bowl and has an injection hole thereon. After the... Agent: Hdsl

20070215895 - Semiconductor light emitting element mounting member, and semiconductor light emitting device employing it: A semiconductor light-emitting element mounting member with an improved effective light reflectivity in a metal film serving as an electrode layer and/or a reflective layer, in which the metal layer has improved adhesion to a substrate, mechanical strength, and reliability and superior light-emitting characteristics. The semiconductor light-emitting element mounting member... Agent: Darby & Darby P.C.

20070215897 - Gaas integrated circuit device and method of attaching same: A gallium arsenide (GaAs) integrated circuit device is provided. The GaAs circuit device has a GaAs substrate with a copper contact layer for making electrical ground contact with a pad of a target device. Although copper is known to detrimentally affect GaAS devices, the copper contact layer is isolated from... Agent: Smith Frohwein Tempel Greenlee Blaha, LLC

20070215898 - Semiconductor device having igbt element: A semiconductor device having an insulated gate bipolar transistor (IGBT) is formed on a semiconductor substrate. Abase region and an emitter are formed on a first surface of the substrate while a collector layer is formed on second surface of the substrate. A region having a low breakdown voltage is... Agent: Posz Law Group, PLC

20070215899 - Merged gate cascode transistor: A merged gate transistor in accordance with an embodiment of the present invention includes a semiconductor element, a supply electrode electrically connected to a top surface of the semiconductor element, drain electrode electrically connected to the top surface of the semiconductor element and spaced laterally away from the supply electrode,... Agent: Ostrolenk Faber Gerb & Soffen

20070215900 - Reduced dark current photodetector: A photo-detector comprising: a photo absorbing layer comprising an n-doped semiconductor exhibiting a valence band energy level; a barrier layer, a first side of the barrier layer adjacent a first side of the photo absorbing layer, the barrier layer exhibiting a valence band energy level substantially equal to the valence... Agent: Simon Kahn C/o Landonip, Inc

20070215901 - Group iii-v nitride-based semiconductor substrate and method of fabricating the same: A group III-V nitride-based semiconductor substrate has: a first layer made of GaN single crystal; and a second layer formed on the first layer, the second layer made of group III-V nitride-based semiconductor single crystal represented by AlxGa1-xN, where 0<x≦1, wherein a top surface and a back surface of the... Agent: Foley And Lardner LLP Suite 500

20070215903 - Power semiconductor device: A power semiconductor device, having a first semiconductor region, and a second semiconductor region; mounted with a first electrode pad on a semiconductor substrate main surface at the inside surrounded by the third semiconductor region, mounted in the second semiconductor region, and a multilayer substrate having first and second wiring... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070215904 - Semiconductor optical device: A semiconductor optical device includes a GaAs substrate of a first conductivity type; a III-V compound semiconductor layer provided on the GaAs substrate; an active layer provided on the III-V compound semiconductor layer; and a cladding layer of a second conductivity type provided on the active layer, wherein the band... Agent: Smith, Gambrell & Russell

20070215902 - Coating liquid for forming organic layered film, method of manufacturing field effect transistor, and field effect transistor: A method of manufacturing a field effect transistor of the present invention includes: applying a coating liquid 20 containing a solvent 13 as well as first and second organic molecules 11 and 12 that have been dissolved in the solvent 13; and forming a first layer and a second layer... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070215905 - Compound semiconductor epitaxial substrate and process for producing the same: m

20070215906 - Method for fabricating 1t-dram on bulk silicon: An integrated circuit includes a bulk technology integrated circuit (bulk IC) including a bulk silicon layer and complementary MOSFET (CMOS) transistors fabricated thereon. The integrated circuit also includes a single transistor dynamic random access memory (1T DRAM) cell arranged adjacent to and integrated with the bulk IC.... Agent: Harness, Dickey & Pierce P.L.C

20070215907 - Semiconductor chip for producing a controllable frequency: A semiconductor chip for producing a controllable frequency is disclosed, for example in transceivers. The semiconductor chip includes a voltage-controlled oscillator located in a first chip region of the semiconductor chip, a heat source, in particular in the form of a power amplifier and/or in the form of a phase-locked... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20070215909 - Image sensor comprising pixels with one transistor: A pixel having a MOS-type transistor formed in and above a semiconductor substrate of a first doping type, a buried semiconductor layer of a second doping type being placed in the substrate under the MOS transistor and separated therefrom by a substrate portion forming a well. The buried semiconductor layer... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070215908 - Electronic device including a semiconductor fin and a process for forming the electronic device: An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can... Agent: Larson Newman Abel Polansky & White, LLP

20070215910 - Cross-point memory array: A circuit comprises a bulk silicon integrated circuit (IC). A first metallization layer is arranged adjacent to said bulk silicon IC. Phase change memory (PCM) is arranged adjacent to said first metallization layer and comprises a plurality of PCM cells each including a phase-change material, a heater that selectively heats... Agent: Harness, Dickey & Pierce P.L.C

20070215911 - Magnetic tunnel junction patterning using ta/tan as hard mask: An MTJ MRAM cell is formed by using a reactive ion etch (RIE) to pattern an MTJ stack on which there has been formed a bilayer Ta/TaN hard mask. The hard mask is formed by patterning a masking layer that has been formed by depositing a layer of TaN over... Agent: Stephen B. Ackerman

20070215912 - Solid-state imaging device and imaging apparatus: A solid-state imaging device is disclosed. In the solid-state imaging device, plural unit areas, each having a photoelectric conversion region converting incident light into electric signals are provided adjacently, in which each photoelectric conversion region is provided being deviated from the central position of each unit area to a boundary... Agent: Robert J. Depke Lewis T. Steadman

20070215913 - Three-dimensional integrated device: A three-dimensional integrated device includes at least two integrated circuit substrates laminated to each other, each of the integrated circuit substrates having at least one ground plane, at least one aperture provided at a desired location in the ground plane, the end of a microstrip line formed in a pair... Agent: Robert J. Depke Lewis T. Steadman

20070215916 - Semiconductor device and manufacturing method thereof: This disclosure concerns a method of manufacturing a semiconductor device including preparing a support substrate including a surface region consisting of a semiconductor single crystal; forming a porous semiconductor layer by transforming the surface region of the support substrate into a porous layer; epitaxially growing a single-crystal semiconductor layer on... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070215917 - Semiconductor integrated circuit device and a method of manufacturing the same: Provided is a technology capable of manufacturing, in a short TAT, a mask ROM having a small memory cell area and high reliability. According to the manufacturing method of a semiconductor integrated circuit device according to the present invention, a memory cell is formed of a first MISFET equipped with... Agent: Miles & Stockbridge PC

20070215915 - Multi-step gate structure and method for preparing the same: A multi-step gate structure comprises a semiconductor substrate having a multi-step structure, a gate oxide layer positioned on the multi-step structure and a conductive layer positioned on the gate oxide layer. Preferably, the gate oxide layer has different thicknesses on each step surface of the multi-step structure. In addition, the... Agent: Oliff & Berridge, PLC

20070215914 - Power semiconductor device having improved performance and method: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes an offset body region.... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070215919 - Reduction of threshold voltage instabilities in a mos transistor: A MOS transistor includes an etch stop layer presenting a density of less than a determined threshold value, below which the material of said stop layer is permeable to molecules of dihydrogen and/or water. The material may comprise a nitride. A material used for the etch stop layer preferably has... Agent: Jenkens & Gilchrist, PC

20070215920 - Semiconductor component arrangement comprising a trench transistor: Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least a gate electrode disposed in the at least one trench. An electrode structure... Agent: Maginot, Moore & Beck Chase Tower

20070215918 - Semiconductor device with extension structure and method for fabricating the same: A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070215921 - Method for independently detecting signals in a double-junction filterless cmos color imager cell: A double-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cell is provided. The imager cell is fabricated from a silicon-on-insulator (SOI) substrate including a silicon (Si) substrate, a silicon dioxide insulator overlying the substrate, and a Si top layer overlying the insulator. A photodiode set is formed in the SOI substrate,... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070215922 - Imaging device: A backside imaging device includes a bump that is disposed overlapping with a sensor array region or a photodiode in a planar view. By this configuration, the bump becomes a support, and the semiconductor substrate is prevented from being damaged because of a bending applied to the semiconductor substrate.... Agent: Foley And Lardner LLP Suite 500

20070215923 - Ferroelectric memory device and method for manufacturing ferroelectric memory device: A ferroelectric memory device is equipped with a ferroelectric capacitor having a first electrode, a second electrode, and a ferroelectric layer between the first and second electrodes, and the ferroelectric memory device includes: a wiring that is connected to one of the first electrode and the second electrode, wherein the... Agent: Harness, Dickey & Pierce, P.L.C

20070215925 - Semiconductor storage device: There is provided a semiconductor storage device including a substrate area, a first and a second isolation area, a first well area where the first transistor is placed, a second well area where the second transistor to output a first voltage to bring the first transistor into non-conduction is placed,... Agent: Young & Thompson

20070215924 - Nonvolatile semiconductor memory device and method of manufacturing the same: A memory cell in a nonvolatile semiconductor memory device includes a tunneling insulating film, a floating gate electrode made of a Si containing conductive material, an inter-electrode insulating film made of rare-earth oxide, rare-earth nitride or rare-earth oxynitride, a control gate electrode, and a metal silicide film formed between the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070215926 - Electric double layer capacitor: Provided is an electric double layer capacitor including a large capacity single cell having a large electrostatic capacity and a small capacity single cell are connected to the same exterior case in parallel, and a thickness of a separator of the large capacity single cell is made thicker than a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070215927 - Semiconductor device and manufacturing method thereof: In a semiconductor device in which a semiconductor element 10 in which plural electrode terminals 16 are formed along the peripheral edge inside a region of a predetermined width along the peripheral edge excluding the center and the vicinity of the center is mounted on a pad formation surface of... Agent: Rankin, Hill, Porter & Clark LLP

20070215928 - Fringe capacitor using bootstrapped non-metal layer: Capacitors configured in a switched-capacitor circuit on a semiconductor device may comprise very accurately matched, high capacitance density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer as a shield, and bootstrapped to the top plate of... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070215929 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to the embodiments of the invention includes a first insulating film on a channel, a floating gate electrode on the first insulating film, a second insulating film on the floating gate electrode, and a control gate electrode on the second insulating film. Each of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070215930 - Semiconductor device and a method of manufacturing the same: A memory cell has a control gate electrode disposed on a main surface of a semiconductor substrate through a gate insulating film, an ONO film disposed along a side surface of the control gate electrode and the main surface of semiconductor substrate, a memory gate electrode disposed on a side... Agent: Miles & Stockbridge PC

20070215933 - Semiconductor device: It is an object of the present invention to provide a semiconductor device that enables cost increase to be inhibited and enables cell size to be reduced, and a method for manufacturing the same. A semiconductor device includes a semiconductor substrate, a gate electrode, a first sidewall, and a second... Agent: Volentine & Whitt PLLC

20070215934 - Semiconductor device: A semiconductor device includng: a well layer that is formed on a semiconductor substrate; a first impurity diffusion layer that is formed on the well layer; a floating gate that is formed on the well layer in one region isolated from the first impurity diffusion layer, with a gate insulating... Agent: Harness, Dickey & Pierce, P.L.C

20070215932 - Memory cell system using silicon-rich nitride: A memory cell system including providing a substrate, forming a charge-storing stack having silicon-rich nitride on the substrate, and forming a gate on the charge-storing stack.... Agent: Ishimaru & Zahrt LLP

20070215931 - Non-volatile memory cell in a trench having a first portion deeper than a second portion, an array of such memory cells, and method of manufacturing: A non-volatile memory cell is made in a substrate of a substantially single crystalline semiconductive material having a first conductivity type and a surface. A trench is in the surface and extends into the substrate to a first depth and to a second depth, which is deeper than the first... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070215935 - Non-volatile two-transistor programmable logic cell and array layout: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within... Agent: Sierra Patent Group, Ltd.

20070215936 - Diffusion topography engineering for high performance cmos fabrication: Semiconductor structures are formed using diffusion topography engineering (DTE). A preferred method includes providing a semiconductor substrate, forming trench isolation regions that define a diffusion region, performing a DTE in a hydrogen-containing ambient on the semiconductor substrate, and forming a MOS device in the diffusion region. The DTE causes silicon... Agent: Slater & Matsil, L.L.P.

20070215938 - Semiconductor device and manufacturing method of the same: Thinning a semiconductor substrate has been needed for reducing on-resistance in a semiconductor device such as a vertical MOS transistor, IGBT, or the like where a high current flows in the semiconductor substrate in a vertical direction. In this case, the thinning is performed to the extent that the semiconductor... Agent: Morrison & Foerster LLP

20070215937 - Static random access memory unit: A static random access memory (SRAM) unit comprising a substrate, a gate dielectric layer, a gate, a trench capacitor, a pair of source/drain regions, a first contact and a second contact is provided. The substrate has a trench formed therein. The gate dielectric layer is disposed on the substrate and... Agent: Jianq Chyun Intellectual Property Office

20070215939 - Quasi-vertical ldmos device having closed cell layout: A low voltage power device includes a plurality of quasi-vertical LDMOS device cells. A conductive trench sinker is formed through the epitaxial layer and adjacent a selected one of the source and drain regions in each cell. The trench sinker electrically couples the selected one of the source and drain... Agent: Duane Morris, LLPIPDepartment

20070215940 - Vertical semiconductor device: A semiconductor device and methods for its fabrication are provided. The semiconductor device comprises a trench formed in the semiconductor substrate and bounded by a trench wall extending from the semiconductor surface to a trench bottom. A drain region and a source region, spaced apart along the length of the... Agent: Ingrassia Fisher & Lorenz, P.C.

20070215944 - Semiconductor device: N+ diffusion region is selectively formed in an SOI layer, and a full isolation region is formed covering all the peripheral regions of N+ diffusion region. A full isolation region penetrates an SOI layer, and reaches a buried oxide film, and N+ diffusion region is electrically thoroughly insulated from the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070215943 - Semiconductor device and method for manufacturing the same: In one embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a to-be-removed layer on a semiconductor substrate; forming a semiconductor layer on the to-be-removed layer; forming a trench that passes through the semiconductor layer to the to-be-removed layer in an SOI region; removing the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070215942 - Thin film transistor device with high symmetry: A thin film transistor device with high symmetry is disclosed, in which the symmetrical structure of transistor is utilized to enable currents flowing in the channels of each transistor formed on a polysilicon film of a specific crystallization direction to pass the same amount of grain boundaries, thereby improving the... Agent: Birch Stewart Kolasch & Birch

20070215945 - Light control device and display: Provided is a light control device including: a thin film transistor; and a light control element including an electrode electrically connected to the thin film transistor, in which a semiconductor region of the thin film transistor and an pixel electrode are composed of the same semiconductor layer, and the same... Agent: Fitzpatrick Cella Harper & Scinto

20070215941 - Semiconductor-on-insulator substrate comprising a buried diamond-like carbon layer and method for making same: The substrate successively comprises a base, a diamond-like carbon layer, a dielectric layer and a semi-conducting material layers which is designed to constitute microelectronic elements. A nucleation layer is preferably disposed between the base and the diamond-like carbon layer. The dielectric material is chosen such that the upper level of... Agent: Oliff & Berridge, PLC

20070215946 - Broadband communications system via reflection from artificial ionized plasma patterns in the atmosphere: A new communications system is described in which the phased array heater used to create an artificial ionized plasma pattern in the atmosphere (AIPA) has an integrated phased array transmitter. By combining these two functions a simplified telecommunications system is created. The new system is called the Integrated Plasma Mirror.... Agent: Bernard Eastland

20070215947 - Computer: An exemplary computer includes a host machine, and a display device. The host machine defines a recessed portion in a side panel thereof to receive the display device therein. The display device includes a frame, and an LCD panel installed in the frame. The recessed portion includes a pair of... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070215948 - Semiconductor device having function of improved electrostatic discharge protection: A semiconductor device includes a diode region having a plurality of protection diodes and a pad region overlapped with an upper part of the diode region. The pad region having a pad installed corresponding to an external connection terminal. The semiconductor device further includes a contact plug unit which connects... Agent: F. Chau & Associates, LLC

20070215949 - Semiconductor device including mos transistor having locos offset structure and manufacturing method thereof: A disclosed semiconductor device includes: a semiconductor substrate; at least one normal transistor disposed on the semiconductor substrate; and at least one LOCOS offset transistor disposed on the semiconductor substrate. The normal transistor has an LDD region between a channel and a source and between the channel and a drain.... Agent: Cooper & Dunham, LLP

20070215950 - Semiconductor device and manufacturing method thereof: A manufacturing method of a semiconductor device according to an embodiment of this invention, includes: forming a gate dielectric film on a substrate and forming a gate electrode layer for a P-type FET on the gate dielectric film, ranging from a P-type FET region to a N-type FET region; in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070215951 - Semiconductor devices having silicided electrodes: The invention relates to a method for fabricating a semiconductor device having a semiconductor body that comprises a first semiconductor structure having a dielectric layer and a first conductor, and a second semiconductor structure having a dielectric layer and a second conductor, that part of the first conductor which adjoins... Agent: Knobbe Martens Olson & Bear LLP

20070215952 - Semiconductor integrated circuit: The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit (6) and a power-supply-uninterrupted... Agent: Miles & Stockbridge PC

20070215953 - Structure and method for latchup suppression: A method and structure for an integrated circuit comprising a substrate of a first polarity, a merged triple well region of a second polarity and a doped region of the second polarity abutting the well region. The doped region is adapted to suppress latch-up in the integrated circuit. The doped... Agent: Greenblum & Bernstein, P.L.C

20070215954 - Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors: A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070215955 - Magnetic tunneling junction structure for magnetic random access memory: A magnetic tunneling junction structure for magnetic random access memory is disclosed. A composite structure includes at least a pinning layer, a barrier layer, a ferromagnetic layer and a free layer, and the material of the pinning layer and the free layer are perpendicularly anisotropic ferrimagnetic. As the structures include... Agent: Rosenberg, Klein & Lee

20070215956 - Semiconductor device and method for manufacturing the same: It is made possible to reduce the contact resistance of the source and drain in an n-type MISFET. A semiconductor device includes: a source and drain regions provided in a p-type semiconductor substrate so as to separate each other, each including: a silicide layer containing a first metal element as... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070215957 - Gate dielectric structure and an organic thin film transistor based thereon: A gate dielectric structure and an organic thin film transistor based thereon, wherein the gate dielectric structure comprises: an organic-inorganic composite layer and an organic insulation layer, and the gate dielectric structure is applied to an organic thin film transistor. As the organic-inorganic composite layer of the gate dielectric structure... Agent: Sinorica, LLC

20070215958 - Semiconductor device and method of manufacturing the same: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070215959 - Semiconductor structures including accumulations of silicon boronide and related methods: A semiconductor device may include a semiconductor substrate, first and second source/drain regions on a surface of the semiconductor substrate, and a channel region on the surface of the semiconductor substrate with the channel region between the first and second source/drain regions. An insulating layer pattern may be on the... Agent: Myers Bigel Sibley & Sajovec

20070215963 - Micromachine and method for manufacturing the same: A semiconductor element of the electric circuit includes a semiconductor layer over a gate electrode. The semiconductor layer of the semiconductor element is formed of a layer including polycrystalline silicon which is obtained by crystallizing amorphous silicon by heat treatment or laser irradiation, over a substrate. The obtained layer including... Agent: Fish & Richardson P.C.

20070215964 - Capacitive micromachined ultrasonic transducer (cmut) with varying thickness membrane: Structure for capacitive micromachined ultrasonic transducer (CMUT) device or other vibrating membrane device having non-uniform membrane so that membrane mass and stiffness characteristics may be substantially independently adjusted. CMUT having trenched membrane and/or membrane with non-uniform thickness or density. Method for operating transducer or vibrating membrane device. Array of devices... Agent: Perkins Coie LLP

20070215961 - Comb structure fabrication methods and systems: A method of manufacturing a vertical comb structure for a micro electromechanical (MEMS) device. Tooth structures are formed on a first wafer. A second wafer is then bonded to the tooth structures of the first wafer. The tooth structures are then released to form a comb structure. Forming the tooth... Agent: Honeywell International Inc.

20070215960 - Methods for fabrication of positional and compositionally controlled nanostructures on substrate: Fabrication methods disclosed herein provide for a nanoscale structure or a pattern comprising a plurality of nanostructures of specific predetermined position, shape and composition, including nanostructure arrays having large area at high throughput necessary for industrial production. The resultant nanostracture patterns are useful for nanostructure arrays, specifically sensor and catalytic... Agent: Lawrence Berkeley National Laboratory

20070215962 - Microelectromechanical system assembly and method for manufacturing thereof: A microelectromechanical system (MEMS) assembly comprises a MEMS transducer, an integrated circuit (IC), and a substrate. The integrated circuit and the MEMS transducer are being electrically coupled to the substrate. The substrate may be a single layer or multiple layers. A coupling circuit resides in the substrate and may comprise... Agent: Fitch Even Tabin And Flannery

20070215965 - Micro-mechanical structure and method for manufacturing the same: Provided is a micro-mechanical structure and method for manufacturing the same, including a hydrophilic surface on at least a part of a surface of the micro-mechanical structure, so as to prevent generation of an adhesion phenomenon in the process of removing a sacrificial layer to release the micro-mechanical, wherein the... Agent: Ladas & Parry LLP

20070215966 - Piezoresistance element and semiconductor device having the same: A piezoresistance element formed in a semiconductor substrate, includes a pair of contact regions formed in the semiconductor substrate; a groove formed between the pair of contact regions; a resistance layer formed in the groove, the resistance layer having a conductive type opposing to the semiconductor substrate; and a silicon... Agent: Rabin & Berdo, PC

20070215967 - System and method for reducing critical current of magnetic random access memory: A system and a method for reducing critical current of magnetic random access memory (MRAM) are disclosed. The magnetic device includes at least a pinned layer, a spacer layer and a free layer, and the material of the pinned layer and the free layer is perpendicularly anisotropic ferrimagnetic. The spacer... Agent: Rosenberg, Klein & Lee

20070215969 - Electro-optical device and electronic apparatus: An electro-optical device includes an insulating substrate, a switching element, at least one PIN diode, and at least one reflector. The switching element includes a first polysilicon semiconductor layer formed on the insulating substrate, and a gate electrode formed between the insulating substrate and the first semiconductor layer. Each of... Agent: Oliff & Berridge, PLC

20070215968 - Front side electrical contact for photodetector array and method of making same: A photodiode includes a semiconductor having front and backside surfaces and first and second active layers of opposite conductivity, separated by an intrinsic layer. A plurality of isolation trenches filled with conductive material extend into the first active layer, dividing the photodiode into a plurality of cells and forming a... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070215970 - Semiconductor device having temporary signal storage unit: A semiconductor device having a unit capable of temporarily storing electrical signals, may include an electrical signal generation unit, a first signal transmission unit electrically connected to the electrical signal generation unit, a first signal storage unit electrically connected to the first signal transmission unit, a second signal transmission unit... Agent: Lee & Morse, P.C.

20070215971 - Solid-state imaging device and method of manufacturing solid-state imaging device: A solid state imaging device having a back-illuminated type structure in which a lens is formed on the back side of a silicon layer with a light-receiving sensor portion being formed thereon. Insulating layers are buried into the silicon layer around an image pickup region, with the insulating layer being... Agent: Rader Fishman & Grauer PLLC

20070215972 - Image sensor package structure: An image sensor package structure includes a plastic substrate, frame layer, a chip, wires, a transparent layer, and an encapsulate layer. The plastic substrate has an upper surface, which is formed with first electrodes, and a lower surface, which is formed with second electrodes. The frame layer is arranged on... Agent: Pro-techtor International Services

20070215973 - Multi-layered thermal sensor for integrated circuits and other layered structures: A compact resistive thermal sensor is provided for an integrated circuit (IC), wherein different sensor components are placed on different layers of the IC. This allows the lateral area needed for the sensor resistance wire on any particular IC layer to be selectively reduced. In a useful embodiment, a plurality... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070215974 - Semiconductor device and method of manufacturing the same: According to an aspect of the invention, there is provided a semiconductor device including a semiconductor substrate, a lower electrode film formed on the semiconductor substrate, a dielectric film formed on the lower electrode film, and an upper electrode film formed on the dielectric film, wherein the lower electrode film,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070215975 - Method of fabricating semiconductor device: Aiming at obtaining stable and uniform element isolation characteristics without forming the oxide film liner or the like on the inner wall surface of the isolation trench, and ensuring a sufficient level of adhesiveness of the insulating material filled in the isolation trench, and obtaining uniform and excellent element isolation... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070215976 - Integrated passive device substrates: The specification describes an integrated passive device (IPD) that is formed on a silicon substrate covered with an oxide layer. Unwanted accumulated charge at the silicon/oxide interface are rendered immobile by creating trapping centers in the silicon surface. The trapping centers are produced by a polysilicon layer interposed between the... Agent: Law Firm Of Peter V.d. Wilde

20070215977 - Resistance random access memory device and a method of manufacturing the same: Provided is a resistance random access memory (RRAM) device and a method of manufacturing the same. A resistance random access memory (RRAM) device may include a lower electrode, a first oxide layer on the lower electrode and storing information using two resistance states, a current control layer made of a... Agent: Harness, Dickey & Pierce, P.L.C

20070215979 - Heterojunction bipolar transistor and fabrication method of the same: A SiGe-HBT having a base region made of SiGe mixed crystal. The base region includes: an intrinsic base region having junctions with a collector region and an emitter region; and an external base region for connecting the intrinsic base region with a base electrode. The intrinsic base region and the... Agent: Mcdermott Will & Emery LLP

20070215978 - Tuneable semiconductor device: Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between... Agent: International Business Machines Corporation Dept. 18g

20070215980 - Vertical semiconductor power switch, electronic component and methods of producing the same: A vertical semiconductor power switch has a semiconductor body having a first surface and a second surface. At least one anode and one control electrode are positioned on the first surface and at least one cathode is positioned on the second surface. The cathode comprises a multi-layer contact structure which... Agent: Baker Botts, L.L.P.

20070215981 - Bipolar power semiconductor component comprising a p-type emitter and more highly doped zones in the p-type emitter, and production method: The invention relates to a bipolar power semiconductor component comprising a semiconductor body (1), in which a p-doped emitter (8), an n-doped base (7), a p-doped base (6) and an n-doped main emitter (5) are arranged successively in a vertical direction (v). The p-doped emitter (8) has a number of... Agent: Maginot, Moore & Beck Chase Tower

20070215982 - Gallium nitride baseplate, epitaxial substrate, and method of forming gallium nitride: A method of forming an iron-doped gallium nitride for a semi-insulating GaN substrate is provided. A substrate 1, such as a sapphire substrate having the (0001) plane, is placed on a susceptor of a metalorganic hydrogen chloride vapor phase apparatus 11. Next, gaseous iron compound GFe from a source 13... Agent: Judge & MurakamiIPAssociates

20070215983 - Nitride semiconductor single crystal substrate, and methods of fabricating the same and a vertical nitride semiconductor light emitting diode using the same: A nitride semiconductor single crystal substrate, a manufacturing method thereof and a method for manufacturing a vertical nitride semiconductor device using the same. According to an aspect of the invention, in the nitride semiconductor single crystal substrate, upper and lower regions are divided along a thickness direction, the nitride single... Agent: Mcdermott Will & Emery LLP

20070215984 - Formation of a multiple crystal orientation substrate: Embodiments of the invention provide a substrate with a first layer having a first crystal orientation on a second layer having a second crystal orientation different than the first crystal orientation. The first layer may have a uniform thickness.... Agent: Intel Corporation C/o Intellevate, LLC

20070215985 - Novel chip packaging structure for improving reliability: A novel chip packaging structure is disclosed. The chip packaging structure includes a flip chip having a chip backside, at least one concave stress-relieving structure provided in the chip backside, a carrier substrate bonded to the flip chip and an adhesive material interposed between the flip chip and the carrier... Agent: Tung & Associates

20070215986 - Hard mask layer stack and a method of patterning: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer... Agent: Dicke, Billig & Czaja

20070215987 - Method for forming a memory device and memory device: A phase change memory device and method of forming a phase change memory device is disclosed. The method includes forming a memory device with a plurality of memory cells, each memory cell having a pillar containing a region of an active material, said method comprising the steps of: depositing at... Agent: Dicke, Billig & Czaja

20070215988 - Semiconductor device including a plurality of semiconductor chips packaged in a common housing: A semiconductor device includes a plurality of semiconductor chips packaged in a common housing. The semiconductor chips include signal pads to pass critical signals to respective chips and are terminated by a terminating resistance. At least one set of signal pads, arranged on different chips and in close proximity to... Agent: Edell, Shapiro & Finnan, LLC

20070215990 - Method for making qfn package with power and ground rings: A method to manufacture a package that encases at least one integrated circuit device and the package so manufactured. The method includes the steps of (1) providing a leadframe having a die pad, leads, at least one ring circumscribing the die pad and disposed between the die pad and the... Agent: Wiggin And Dana LLP Attention: Patent Docketing

20070215989 - Semiconductor chip assembly: A semiconductor chip assembly comprises a semiconductor chip including a first contact and a second contact positioned at a first side of the first contact, a first lead including an inner end, a second lead including a body positioned at a second side of the first lead and an inner... Agent: Oliff & Berridge, PLC

20070215992 - Chip package and wafer treating method for making adhesive chips: A wafer treating method for making adhesive chips is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform an adhesive film having B-stage property which has a glass transition temperature between −40 and... Agent: J.c. Patents, Inc.

20070215991 - Tape: A tape with a chip-bonding area is provided. The tape is suitable for a chip on film configuration, wherein a chip is suitable for being disposed on the tape and in the chip-bonding area. The tape includes a dielectric base film, a first wiring pattern, and at least a second... Agent: Jianq Chyun Intellectual Property Office

20070215993 - Chip package structure: A chip package structure including a carrier, a chip, first bonding wires, second bonding wires, and an encapsulant is provided. The carrier has first contacts and at least one second contact, and the chip has at lease one first bonding pad and at least one second bonding pad. In addition,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070215995 - Fabrication processes of leadframe-based bga packages and leadless leadframe implemented in the processes: Manufacturing processes of a leadframe-based BGA package and a leadless leadframe implemented in the processes are disclosed. The leadless leadframe has a plurality of bottom leads and a plurality of top soldering pads formed in different layers. After encapsulation and before solder ball placement, a half-etching process is performed to... Agent: Troxell Law Office PLLC

20070215994 - Connecting a plurality of bond pads and/or inner leads with a single bond wire: An integrated circuit device comprising an integrated circuit die having a plurality of bond pads that are selectively connected to a plurality of inner leads of a leadframe. At least two bond pads are connected to at least one of the inner leads, and/or at least two inner leads are... Agent: Baker Botts, LLP

20070216004 - Blank including a composite panel with semiconductor chips and plastic package molding compound and method and mold for producing the same: A blank and a semiconductor device are include a composite panel with semiconductor chips embedded in a plastic package molding compound. The blank includes a composite panel with semiconductor chips arranged in rows and columns in a plastic package molding compound with active upper sides of the semiconductor chips forming... Agent: Edell, Shapiro & Finnan, LLC

20070216000 - Cover tape for packaging semiconductor device and package for semiconductor device: The purpose of the present invention is to provide a cover tape for packaging semiconductor device which protects the outer shape of the semiconductor device, and is capable of improving the mounting speed of the semiconductor device by shipment in tape, and a package for semiconductor device using the cover... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070215999 - Semiconductor device: One of the aspects of the present invention is to provide a semiconductor device, which includes a base plate, an insulating substrate on the base plate, and a wiring patterned layer on the insulating substrate. Also, it includes at least one semiconductor chip bonded on the wiring patterned layer, the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070216002 - Semiconductor device: Plural via portions formed on a package substrate of a BGA include a first through-hole portion extended in the plane direction by an extension wiring connected to a land portion and a second through-hole portion that is arranged on the land portion serving as pad-on-via, whereby high-density wiring and multi-function... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070216001 - Semiconductor package containing multi-layered semiconductor chips: According to this invention, a semiconductor package includes: a plurality of semiconductor chips, each having through electrodes; and a semiconductor interposer, on which the plurality of semiconductor chips are mounted. Each of the semiconductor chips includes: a semiconductor substrate; a wiring layer formed on the semiconductor substrate; an opaque resin... Agent: Rabin & Berdo, PC

20070216003 - Semiconductor package with enhancing layer and method for manufacturing the same: A semiconductor package with an enhancing layer is provided. The package includes a leadframe, a chip, several bumps and an enhancing layer. The leadframe includes several leads. Several bonding pads are disposed on a surface of the chip. The bumps connect the bonding pads of the chip and the leads... Agent: Birch Stewart Kolasch & Birch

20070215997 - Chip-scale package: A power semiconductor package that includes a die having one electrode thereof electrically and mechanically attached to a web portion of a conductive clip.... Agent: Ostrolenk Faber Gerb & Soffen

20070215996 - Electronic component and method for its assembly: An electronic component has at least one semiconductor power switch with at least one anode and at least one control electrode positioned on a first surface and at least one cathode positioned on a second surface and a heat sink with a die attach region with an upper surface. The... Agent: Baker Botts, L.L.P.

20070215998 - Led package structure and method for manufacturing the same: A LED package structure is disclosed. The LED package structure includes a substrate, a light emitting diode, a plasma chemical vapor deposition layer and a transparent material layer, wherein the substrate has a plurality of contacts. The light emitting diode is disposed on the substrate and electrically contacted to the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070216006 - Integrated circuit package on package system: A integrated circuit package on package system is provided including providing a base substrate having a base stackable connection, attaching a base integrated circuit on the base substrate, forming a stackable package including the base integrated circuit encapsulated with the base stackable connection partially exposed, and attaching a bottom package... Agent: Ishimaru & Zahrt LLP

20070216005 - Integrated circuit package-in-package system: An integrated circuit package-in-package system is provided forming a first integrated circuit package having a first interface, stacking a second integrated circuit package having a second interface above the first integrated circuit package, fitting the first interface and the second interface, and attaching a third integrated circuit package on the... Agent: Ishimaru & Zahrt LLP

20070216008 - Low profile semiconductor package-on-package: A semiconductor system (100) with two substrates has a first substrate (101) with a first and a second surface, electrical contact pads (110, 120) on the first and the second surface, and a central opening (130). The second substrate (102) has a third and a fourth surface, and electrical contact... Agent: Texas Instruments Incorporated

20070216007 - Multichip package system: A multichip package system is provided forming a substrate having a plurality of molding transfer channel, connecting a first integrated circuit die on a top side of the substrate, connecting a second integrated circuit die on a bottom side of the substrate, and concurrently encapsulating the first integrated circuit die... Agent: Ishimaru & Zahrt LLP

20070216010 - Integrated circuit package system: An integrated circuit package system is provided forming a carrier having a top side and a bottom side, forming an edge terminal pad on the top side and an inner terminal pad on the bottom side, connecting an integrated circuit die to an inner portion of the edge terminal pad,... Agent: Ishimaru & Zahrt LLP

20070216012 - Method for mounting an electronic part on a substrate using a liquid containing metal particles: An electronic part mounting method, a semiconductor module, and a semiconductor device, which can reduce a mounting area and a device thickness. In an electronic part mounting method for bonding an electrode formed on a substrate and an electrode formed on an electronic part to each other, the method comprises... Agent: Crowell & Moring LLP Intellectual Property Group

20070216011 - Multichip module with improved system carrier: A power semiconductor device has a first chip carrier part (11) and a second chip carrier part (12), the first chip carrier part (11) and the second chip carrier part (12) being spaced apart from one another and being electrically conductive in each case. A first chip with a power... Agent: Baker Botts, L.L.P.

20070216009 - Semiconductor package with heat spreader: A semiconductor package is disclosed. In one embodiment the package includes comprises a semiconductor chip including an active surface with a plurality of chip contact areas and a package substrate including a plurality of first contact areas and a plurality of second contact areas on its bottom surface. The chip... Agent: Dicke, Billig & Czaja

20070216013 - Power semiconductor module: A power semiconductor module having an increased reliability against thermal fatigue includes a power semiconductor element, a lower-side electrode connected to the lower side of the element, a first insulating substrate connected to the upper side of the lower-side electrode and having metallic foils bonded on both surfaces thereof, an... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070216014 - Separable network interconnect systems and asemblies: Microelectronic assemblies interconnected using a separable network interface and electronic systems using the microelectronic assemblies to physically separate high performance signals and lower performance signals to enhance system performance are disclosed.... Agent: William R. Lambert, Ph.d., J.d.

20070216016 - Heat-radiating tape carrier package and method for manufacturing the same: A tape carrier package may include an interposer having a first surface and a second surface. The first surface of the interposer may be attached to an exposed active surface of a semiconductor chip. A heat sink may be attached to the second surface of the interposer.... Agent: Harness, Dickey & Pierce, P.L.C

20070216015 - Integrated circuit chip with electrostatic discharge protection device: Consistent with an example embodiment, in integrated circuit chip includes an electrostatic discharge (ESD) protection device. A feature of the ESD protection device includes a pair of spaced center and circumferential electrodes, the center electrode being formed by the first electrically conductive layer and the circumferential electrode being formed by... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070216017 - Composite contact: A composite contact includes a main body part, a first elastic piece which extends from the main body part and elastically contacts with a terminal disposed at an end part of a fluorescent tube and a second elastic piece which extends from the main body part and aims at elastically... Agent: Rader Fishman & Grauer PLLC

20070216018 - Assembling multi-core dice using sockets with multiple sets of front side bus contacts: An embodiment of the present invention is a technique to assemble multi-core dice. A first socket has first N sets of front side bus (FSB) contacts to house a first package having first 2N dice. Each of the first 2N dice has M cores. N and M are positive integers.... Agent: Blakely Sokoloff Taylor & Zafman

20070216019 - Laminated ic packaging substrate and inter-connector structure thereof: A laminated IC packaging substrate includes an intermediate connecting layer having a plurality of through holes. Each of the through holes is filled with solder material protruding from a top surface and/or a bottom surface of the intermediate connecting layer. A first circuit board having thereon a first wiring pattern... Agent: North America Intellectual Property Corporation

20070216020 - Semiconductor device: It is an object of the present invention to provide a semiconductor device that enables the transmission time of a signal and implementation area to be reduced, and a method for manufacturing the same. A semiconductor device includes a first semiconductor substrate, a capacitor chip, an external input terminal, and... Agent: Volentine & Whitt PLLC

20070216021 - Semiconductor device and method of manufacturing thereof: A method of manufacturing a semiconductor device sealed in a cured silicone body by placing a semiconductor device into a mold and subjecting a curable silicone composition that fills the spaces between said mold and said semiconductor device to compression molding, wherein the curable silicone composition comprises the following components:... Agent: Howard & Howard Attorneys, P.C.

20070216022 - Fin structure for a heat sink: A heat sink includes a base adapted for absorbing heat from a heat-generating component, and a plurality of parallel fins having channels defined therebetween. Each of the fins includes a main body standing on the base. A row of protruding portions and openings is alternately arranged on the main body... Agent: North America Intellectual Property Corporation

20070216023 - Conductive resin composition, connection method between electrodes using the same, and electric connection method between electronic component and circuit substrate using the same: The present invention provides a conductive resin composition for connecting electrodes electrically, in which metal particles are dispersed in a flowing medium, wherein the flowing medium includes a first flowing medium that has relatively high wettability with the metal particles and a second flowing medium that has relatively low wettability... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070216024 - Heat sink, electronic device, method of manufacturing heat sink, and method of manufacturing electronic device: A heat sink includes a base portion formed of insulating diamond, and a plurality of pressure contacting members formed of the insulating diamond and arranged on the base portion... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070216025 - Device having a contacting structure: A layer of electrically insulating material is applied to a substrate and a component located thereon, in such a way that said layer follows the surface contours.... Agent: Siemens Corporation Intellectual Property Department

20070216027 - Semiconductor device: A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device 100 includes: a silicon substrate 101; an interlayer film 103 provided on the silicon substrate 101; a multiple-layered interconnect embedded in the interlayer film 103;... Agent: Young & Thompson

20070216026 - Aluminum bump bonding for fine aluminum wire: The invention includes a packaged semiconductor device in which the bond wires are bonded to the leads with an aluminum bump bond. The semiconductor device is mounted on a leadframe having leads with a nickel plating. To form the bump bond between a fine aluminum wire, such as a 2... Agent: Hiscock & Barclay, LLP

20070216028 - Micro-element package and manufacturing method thereof: A micro-element package which can reduce manufacturing costs and can be advantageous for mass production due to simplifying its structure and manufacturing process, and also can facilitate miniaturization and promote thinness, and a method of manufacturing the micro-element package. The micro-element package includes: a substrate having a micro-element on its... Agent: Sughrue Mion, PLLC

20070216029 - A method for fabricating a capacitor structure: A capacitor structure is described, including a substrate, a first metal layer in the substrate, an etching stop layer on the substrate having therein an opening that exposes a portion of the first metal layer, a connection layer on the portion of the first metal layer, the sidewall of the... Agent: Jianq Chyun Intellectual Property Office

20070216030 - Integrated circuit having a multilayer capacitance arrangement: An integrated circuit having a multilayer capacitance arrangement and a method for producing an integrated circuit having a multilayer capacitance arrangement are disclosed.... Agent: Dicke, Billig & Czaja

20070216032 - Enhancing metal/low-k interconnect reliability using a protection layer: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes.... Agent: Stmicroelectronics, Inc.

20070216031 - Formation of oxidation-resistant seed layer for interconnect applications: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present invention, a hydrogen plasma treatment is used to... Agent: Scully Scott Murphy & Presser, PC

20070216033 - Carrierless chip package for integrated circuit devices, and methods of making same: Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each... Agent: Williams, Morgan & Amerson

20070216035 - Flip-chip type semiconductor device: A flip-chip type semiconductor device includes a semiconductor substrate. A plurality of electrode terminals are provided and arranged on a top surface of the semiconductor substrate, a sealing resin layer is formed on the top surface of the semiconductor substrate such that the electrode terminals are completely covered with the... Agent: Young & Thompson

20070216034 - Low thermal resistance assembly for flip chip applications: An assembly comprises a stiffener, a circuit substrate and an integrated circuit (IC) chip. The stiffener has a surface with a first region and a second region. The circuit substrate covers the first region, while the IC chip overlies at least a portion of each of the first and second... Agent: Ryan, Mason & Lewis, LLP

20070216036 - Methods and structures for facilitating proximity communication: One embodiment of the present invention provides an integrated chip module and a corresponding method of manufacture that facilitates proximity communication. This module includes a base chip and a bridge chip, both of which include an active face, upon which active circuitry and signal pads reside, and a back face... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070216037 - Memory card structure and method for manufacturing the same: A memory card structure includes a substrate, B-Stage glue, an adhered layer, a chip, wires, and a compound layer. The substrate has an upper surface, which is formed with first electrodes and golden fingers electrically connected to the first electrodes. The B-Stage glue is coated on the periphery of upper... Agent: Pro-techtor International Services

20070216038 - Method for producing semiconductor components: A method produces semiconductor components having a substrate, a semiconductor chip and an encapsulant. Chips situated on a wafer are singulated, arranged on a substrate and electrically conductively connected to a conductor structure on the substrate. The chips on the substrate are encapsulated with an encapsulant and the semiconductor components... Agent: Slater & Matsil LLP

20070216039 - Electronic component integrated module and method for fabricating the same: The electronic component integrated module includes a wiring board; an electronic component provided on the wiring board; solder for electrically connecting the electronic component onto the wiring substrate; and an encapsulating resin for encapsulating the electronic component and the solder. The average linear thermal expansion coefficient α of the encapsulating... Agent: Mcdermott Will & Emery LLP

20070216040 - Epoxy resin composition for the encapsulation of semiconductors and semiconductor devices: An epoxy resin composition for encapsulating semiconductors containing an epoxy resin, a phenol resin, an inorganic filler, a curing accelerator, a glycerol tri-fatty acid ester produced by dehydration condensation reaction of glycerol and a saturated fatty acid with a carbon atom content of 24-36, and a hydrotalcite compound as essential... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070216041 - Fiducial scheme adapted for stacked integrated circuits: A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an integrated circuit layer having integrated circuit elements constructed therein and... Agent: The Law Offices Of Calvin B. Ward

20070216042 - Methods for manufacturing compound-material wafers and for recycling used donor substrates: This invention provides methods for manufacturing compound-material wafers and methods for recycling donor substrates that results from manufacturing compound-material wafers. The provided methods includes at least one further thermal treatment step configured to at least partially reduce oxygen precipitates and/or nuclei. Reduction of oxygen precipitates and/or nuclei, improves the recycling... Agent: Winston & Strawn LLP Patent Department

20070210299 - Single-photon generating device, single-photon detecting device, and optical quantum gate: A single-photon generating device is configured to have a solid substrate including abase portion, and a pillar portion which is formed on the surface side of the base portion with a localized level existent in the vicinity of the tip of the base portion. The above pillar portion is formed... Agent: Kratz, Quintos & Hanson, LLP

20070210304 - Nitride semiconductor single crystal film: s

20070210307 - Methods of forming a layer of material on a substrate and structures formed therefrom: A method for making a structure which may have at least one layer on a supporting substrate. The method includes at least the steps for forming from the supporting substrate an intermediate structure which may have an amorphous layer, a first crystalline layer containing point defects and, a second crystalline... Agent: Winston & Strawn LLP Patent Department

20070210309 - Display device and manufacturing method therefor: The display device according to an exemplary embodiment of the present invention includes an insulation substrate, a first signal line formed on the insulation substrate, a second signal line intersecting and insulated from the first signal line, an covering member formed on the second signal line, and a switching element... Agent: Macpherson Kwok Chen & Heid LLP

20070210308 - Image display medium: An image display medium includes: a first substrate; a second substrate facing the first substrate; a first bonding layer provided inside at least one of the first substrate and the second substrate; and an insulating layer fixed to the at least one of the first substrate and the second substrate... Agent: Oliff & Berridge, PLC

20070210310 - Thin film transistor structure and method of fabricating the same: A structure of a thin film transistor and a method for making the same are provided. The structure includes a strip-shaped silicon island, a gate, and a first and second ion doping regions. The strip-shaped silicon island is a thin film region with a predetermined long side and short side,... Agent: Jianq Chyun Intellectual Property Office

20070210311 - Thin film transistor substrate and process for producing same: In conventional techniques, there has been a problem such that a pattern failure tends to occur in which electrode patterns formed by coating do not coincide with lyophilic patterns and the coating process is complicated to degrade the productivity. The present invention provides a thin film transistor substrate including: a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070210313 - Film transistor and method for fabricating the same: A method for fabricating a thin film transistor and a thin film transistor includes a polycrystalline silicon layer formed by irradiating an amorphous silicon layer with a laser beam through an organic layer formed on the amorphous silicon layer and removing the organic layer.... Agent: Brinks Hofer Gilson & Lione

20070210321 - Edge light-emitting device and manufacturing method thereof: An edge light-emitting device having, on a light permeable substrate, a stacked structure including a pair of electrodes and at least one light emitting layer interposed between the electrodes, in which light emission is taken-out from a light emitting edge of the stacked structure, wherein at least one non-light emitting... Agent: Birch Stewart Kolasch & Birch

20070210317 - High power light emitting device assembly with esd protection ability and the method of manufacturing the same: A high power light emitting device assembly with electro-static-discharge (ESD) protection ability and the method of manufacturing the same, the assembly comprising: at least two sub-mounts, respectively being electrically connected to an anode electrode and a cathode electrode, each being made of a metal of high electric conductivity and high... Agent: Birch Stewart Kolasch & Birch

20070210319 - Light emitting device and manufacturing method thereof: Embodiments of a light emitting device are provided. A light emitting device can include a first electrode, a first condition type semiconductor layer, an active layer, a second conduction type semiconductor layer, a second electrode, and a substrate. The first conduction type semiconductor layer can be formed on the first... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070210322 - Light emitting element, light emitting device, and electronic device: It is an object of the present invention to provide a light emitting element that realizes a high contrast. It is another object of the present invention to provide a light emitting device that realizes a high contrast by using the light emitting element with an excellent contrast. The light... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070210324 - Nitride semiconductor light emitting device: A nitride semiconductor light emitting device includes a first coat film of aluminum nitride or aluminum oxynitride formed at a light emitting portion and a second coat film of aluminum oxide formed on the first coat film. The thickness of the second coat film is at least 80nm and at... Agent: Harness, Dickey & Pierce, P.L.C

20070210297 - Electrical structure with a solid state electrolyte layer, memory with a memory cell and method for fabricating the electrical structure: The invention refers to a memory, a method of fabricating an electrical structure, and an electrical structure containing a substrate, a solid state electrolyte layer, and an electrode layer. The electrical structure contains a layer region arranged at an interface between the solid state electrolyte layer and the electrode layer.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070210296 - Electrode for phase change memory device and method: An electrode for a memory material of a phase change memory device is disclosed. The electrode includes a first layer adhered to the memory material, the first layer including a nitride (ANx), where A is one of titanium (Ti) and tungsten (W) and x greater than zero, but is less... Agent: Hoffman, Warnick & D'alessandro LLC

20070210298 - Device and method for manipulating direction of motion of current carriers: A device and method for manipulating a direction of motion of current carriers are presented. The device comprises a structure containing a two-dimensional gas of current carriers configured to define at least one region of inhomogeneity which is characterized by a substantially varying value of at least one parameter from... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20070210300 - Semiconductor device and manufacturing method thereof: A quantum dot semiconductor device securing sufficient gains without depending on polarization and a manufacturing method thereof. On a first barrier layer, a multilayer quantum dot is formed by repeatedly stacking alternately a quantum dot layer and a second barrier layer. On a quantum dot layer as an uppermost layer... Agent: Kratz, Quintos & Hanson, LLP

20070210301 - Semiconductor devices and methods of manufacturing thereof: Semiconductor devices and methods of manufacturing thereof are disclosed. A preferred embodiment includes a semiconductor device comprising a workpiece, the workpiece including a first region and a second region proximate the first region. A first material is disposed in the first region, and at least one region of a second... Agent: Slater & Matsil LLP

20070210302 - Pentathienyl-fluorene copolymer: The present invention relates to a pentathienyl-fluorene copolymer having structural units represented by formula (I): here R and R′ are each independently a substituent or H. The invention also relates to a transistor containing this copolymer. The present invention addresses a problem in the art by providing an electroactive device... Agent: Sughrue Mion, PLLC

20070210303 - Thin film transistor and organic electroluminescent display device: A photoelectric current caused by extraneous light is suppressed and variations in characteristics (for example, a threshold voltage) of a thin film transistor are reduced. An active layer (semiconductor layer) made of polycrystalline silicon, which is transformed from amorphous silicon by laser annealing, is formed on an insulating substrate. A... Agent: Morrison & Foerster LLP

20070210305 - Method for forming layer for trench isolation structure: A method for forming a thermal oxide layer on the surface of a semiconductor substrate exposed during a semiconductor fabricating process. The thermal oxide layer is to be thin to minimize silicon substrate defects caused by volume expansion. A chemical vapor deposition (CVD) layer is then formed on the thin... Agent: Marger Johnson & Mccollom, P.C.

20070210306 - Test pattern for measuring contact short at first metal level: The invention relates to a test structure and methods of detecting electrical defects between adjacent metal contacts using such test structure at the first metal level within a semiconductor device. The test structure includes dual first metal level comb structures each having extending lines that are in direct electrical communication... Agent: Law Office Of Delio & Peterson, LLC.

20070210312 - Method of manufacturing semiconductor devices: Subjected to obtain a crystalline TFT which simultaneously prevents increase of OFF current and deterioration of ON current. A gate electrode of a crystalline TFT is comprised of a first gate electrode and a second gate electrode formed in contact with the first gate electrode and a gate insulating film.... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070210314 - Semiconductor device with stressors and method therefor: A method for forming a semiconductor device includes providing a substrate region having a first material and a second material overlying the first material, wherein the first material has a different lattice constant from a lattice constant of the second material. The method further includes etching a first opening on... Agent: Freescale Semiconductor, Inc. Law Department

20070210315 - Semiconductor device for emitting light: A semiconductor device according to the invention for emitting light when a voltage is applied includes a first (3), a second (5) and a third active semiconductor region (7A-7C). While the conductivity of the first semiconductor region (3) is based on charge carriers of a first conductivity type, the conductivity... Agent: Rothwell, Figg, Ernst & Manbeck, P.C.

20070210316 - Semiconductor device and manufacturing method thereof: A semiconductor device and a manufacturing method thereof uses a semiconductor substrate of silicon carbide. On one principal surface side of the substrate, at its central section, a layer of silicon carbide or gallium nitride as a semiconductor layer having the thickness at least necessary for breakdown voltage blocking is... Agent: Rossi, Kimms & Mcdowell LLP.

20070210318 - Light emitting diode with metal coupling structure: An electronic device includes a conductive n-type substrate, a Group III nitride active region, an n-type Group III-nitride layer in vertical relationship to the substrate and the active layer, at least one p-type layer, and means for providing a non-rectifying conductive path between the p-type layer and the n-type layer... Agent: Summa, Allan & Additon, P.A.

20070210320 - Light emitting element and production method thereof: A light emitting element having a light emitting element portion formed of a group III nitride-based compound semiconductor and having a layer to emit light. The light emitting element portion is formed by lifting off a substrate by wet etching after the light emitting element portion is grown on the... Agent: Mcginn Intellectual Property Law Group, PLLC

20070210323 - Optical device: A method of forming an electroluminescent device including the steps of providing a substrate including a first electrode for injection of charge carriers of a first type, forming a semiconductor region by depositing over the substrate a composition containing a first material for transporting charge carriers of the first type... Agent: Marshall, Gerstein & Borun LLP

20070210325 - Lead frame and light emitting device package using the same: A lead frame and a light emitting device package using the same are disclosed. More particularly, a lead frame and a light emitting device package using the lead frame which can be easily manufactured and employ a multi-chip structure. The light emitting device package includes a first frame including a... Agent: Birch Stewart Kolasch & Birch

20070210326 - Lighting device and display device provided with the same: A phosphor nitride or a chalcogenide phosphor, which is used as a red phosphor, includes a wavelength of green light as an exciting wavelength. Therefore, in obtaining white light by using a conversion member in which a red phosphor and a green phosphor both exist, luminance efficiency is deteriorated as... Agent: Bruce L. Adams, Esq.

20070210327 - Method of fabricating light emitting device and thus-fabricated light emitting device: Aiming at providing a method of fabricating a light emitting device having an AlGaInP light emitting section, less causative of crack by cleavage, on the edge portions on the back surface of the device chip in process of dicing or breaking, a light emitting device wafer is diced along a... Agent: Snider & Associates

20070210328 - Monolithically integrated light-activated thyristor and method: A monolithically integrated light-activated thyristor in an n-p-n-p-n-p sequence consists of a four-layered thyristor structure and an embedded back-biased PN junction structure as a turn-off switching diode. The turn-off switching diode is formed through structured doping processes and/or depositions on a single semiconductor wafer so that it is integrated monolithically... Agent: Bingham Mccutchen LLP

20070210329 - Warp-free semiconductor wafer, and devices using the same: A semiconductor wafer to be diced into individual SBDs, HEMTs or MESFETs has a substrate with a main semiconductor region and counter semiconductor region formed on its opposite surfaces. The main semiconductor region is configured to provide the desired semiconductor devices. In order to counterbalance the warping effect of the... Agent: Woodcock Washburn LLP

20070210330 - Semiconductor device and method of producing the same: A semiconductor device, includes: a first conductivity type semiconductor base having a main face; a hetero semiconductor region contacting the main face of the semiconductor base and forming a hetero junction in combination with the semiconductor base, the semiconductor base and the hetero semiconductor region in combination defining a junction... Agent: Foley And Lardner LLP Suite 500

20070210331 - Guard ring applied to ion implantation equipment: A guard ring applied to an ion implantation equipment is disposed between a bushing and an ion beam source housing of the ion implantation equipment. The guard ring is made of high-density ceramic material. The guard ring can prevent arcing generated by the high voltage used for ion implantation from... Agent: Rosenberg, Klein & Lee

20070210332 - Semiconductor device: It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13... Agent: Stevens, Davis, Miller & Mosher, LLP

20070210333 - Hybrid semiconductor device: A hybrid device including a silicon based MOSFET operatively connected with a GaN based device.... Agent: Ostrolenk Faber Gerb & Soffen

20070210334 - Phase change memory device and method of fabricating the same: Example embodiments relate to a semiconductor memory device and a method of fabricating the same. Other example embodiments relate to a phase change memory device and a method of fabricating the same. There are provided a phase change memory device and a method of fabricating the same for improving or... Agent: Harness, Dickey & Pierce, P.L.C

20070210335 - Gan semiconductor device: A GaN semiconductor device which has a low on-resistance, has a very small leak current when a reverse bias voltage is applied and is very excellent in withstand voltage characteristic, said GaN semiconductor device having a structure being provided with a III-V nitride semiconductor layer containing at least one hetero... Agent: Knoble, Yoshida & Dunleavy

20070210336 - Semiconductor devices fabricated with different processing options: A semiconductor device, wherein: a first fabricating option provides a plurality of user configurations to configure the device functionality; and a second fabricating option hard-wires a said functional configuration, the second option comprising a plurality of common masks and fewer processing steps compared to the first option.... Agent: Raminda U. Madurawe

20070210337 - Contact hole formation method: A contact hole formation method includes a process of depositing a BPSG film 4 on a semiconductor substrate 1 on which transistors are formed, a process of planarizing the BPSG film 4, a process of depositing a dielectric film 5 on the BPSG film 4, and a process of forming... Agent: Wenderoth, Lind & Ponack L.L.P.

20070210338 - Charge storage structure formation in transistor with vertical channel region: A semiconductor device includes a semiconductor structure having a first sidewall. A vertical channel region is formed in the semiconductor structure along the first sidewall between a first current electrode region and a second current electrode region. First and second charge storage structures are formed adjacent to the first sidewall... Agent: Fortkort & Houston P.C. Arboretum Plaza One

20070210340 - Gaas power transistor: A GaAs power transistor unit cell is provided with one of its transistor contacts on its bottom surface, and its other two transistor contacts on its frontside surface. In one arrangement, the GaAs power transistor unit cell has a N+ GaAs substrate that cooperates with an N− GaAs material to... Agent: Smith Frohwein Tempel Greenlee Blaha, LLC

20070210341 - Periphery design for charge balance power devices: A charge balance semiconductor power device comprises an active area having strips of p pillars and strips of n pillars arranged in an alternating manner, the strips of p and n pillars extending along a length of the active area. A non-active perimeter region surrounds the active area, and includes... Agent: Townsend And Townsend And Crew, LLP

20070210339 - Shared contact structures for integrated circuits: In one embodiment, a shared contact structure electrically connects a gate, a diffusion region, and another diffusion region. The shared contact structure may comprise a trench that exposes the gate, the diffusion region, and the other diffusion region. The trench may be filled with a metal to form electrical connections.... Agent: Okamoto & Benedicto, LLP

20070210342 - Vertical charge transfer active pixel sensor: An active pixel sensor and method of operating an active pixel sensor comprising an N well of n type silicon formed in a p type silicon substrate and a P well of p type silicon is formed in the N well. A deep N well is formed of n type... Agent: Stephen B. Ackerman

20070210343 - Image sensor and an apparatus for an image sensor using same: In a CCD type solid-state image sensor (CCD) of this invention, a potential gradient is provided in which potentials about electric signals gradually change from a photodiode toward a gate electrode. Specifically, impurities forming the photodiode are diffused in the shape of character “X”, and the width of the impurities... Agent: Rader Fishman & Grauer PLLC

20070210345 - Solid-state image sensor with micro-lenses for anti-shading: A solid-state image sensor prevents shading while maintaining the wider dynamic range of an image signal without reducing its optical resolution. The image sensor has plural pairs of higher- and lower-sensitivity photodiodes and micro-lenses each of which is provided over particular one of the higher- and lower-sensitivity photodiodes for collecting... Agent: Birch Stewart Kolasch & Birch

20070210344 - Semiconductor device: It is an object of the present invention to obtain a photoelectric conversion device having a favorable spectral sensitivity characteristic and no variation in output current without such a contamination substance mixed into a photoelectric conversion layer or a transistor. Further, it is another object of the present invention to... Agent: Fish & Richardson P.C.

20070210346 - Charge transfer device: A gate electrode region of a junction transistor in a signal charge-voltage converter is allowed to have a structure that a gentle potential gradient is formed without generation of a potential barrier. Thus, it is possible to readily realize a signal charge-voltage converter which is high in S/N ratio without... Agent: Steptoe & Johnson LLP

20070210347 - Trench mos schottky barrier rectifier with high k gate dielectric and reduced mask process for the manufacture thereof: A trench MOS Schottky barrier device has a metal oxide gate dielectric such as TiSi lining the trench wall to increase the efficiency of the elemental cell and to improve depletion in the mesa during reverse bias. A reduced mask process is used in which a single layer of titanium... Agent: Ostrolenk Faber Gerb & Soffen

20070210348 - Phase-change memory device and methods of fabricating the same: Example embodiments relate to a phase-change memory device and methods of fabricating the same. A phase-change memory device may include a lower electrode on a semiconductor substrate, a phase-change material layer on the lower electrode, a contact plug between the lower electrode and the phase-change material layer, wherein a first... Agent: Harness, Dickey & Pierce, P.L.C

20070210349 - Multifunctional biosensor based on zno nanostructures: The present invention provides the multifunctional biological and biochemical sensor technology based on the integration of ZnO nanotips with bulk acoustic wave (BAW) devices, particularly, quartz crystal microbalance (QCM) and thin film bulk acoustic wave resonator (TFBAR). ZnO nanotips provide giant effective surface area and strong bonding sites. Furthermore, the... Agent: Hoffmann & Baron, LLP

20070210350 - Power semiconductor device, method for manufacturing same, and method for driving same: A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070210354 - Semiconductor device and semiconductor device manufacturing method: Provided is a technology capable of improving the productivity of a p channel MISFET using a high dielectric-constant film as a gate insulating film and a conductive film containing metal as a gate electrode. In this technology, a threshold voltage of the p channel MISFET can be decreased even if... Agent: Stanley P. Fisher Reed Smith LLP

20070210351 - Semiconductor device, and method for manufacturing the same: According to an aspect of the invention, a semiconductor device comprises: a N-channel MIS transistor comprising; a p-type semiconductor layer; a first gate insulation layer formed on the p-type semiconductor layer; a first gate electrode formed on the first gate insulation layer; and a first source-drain region formed in the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070210353 - Thin film transistor device and method of manufacturing the same: A thin film transistor device according to an embodiment of the invention includes: a thin film transistor having a silicon layer including a source region, a drain region, and a channel region, a gate insulating layer, and a gate electrode formed on an insulating substrate; an interlayer insulating layer covering... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070210358 - Method of forming a gate oxide film for a high voltage region of a flash memory device: A method of forming a gate oxide film for high voltage region of semiconductor devices includes forming patterns on a semiconductor substrate having a high voltage region, thereby exposing only a gate oxide film formation region for high voltage, forming a metal oxidization layer on the entire surface, and performing... Agent: Marshall, Gerstein & Borun LLP

20070210357 - Mosfet having recessed channel and method of fabricating the same: A MOSFET having a recessed channel and a method of fabricating the same. The critical dimension (CD) of a recessed trench defining the recessed channel in a semiconductor substrate is greater than the CD of the gate electrode disposed on the semiconductor substrate. As a result, the misalignment margin for... Agent: Marger Johnson & Mccollom, P.C.

20070210356 - Power semiconductor device: A power semiconductor device which includes an implant region in the base region thereof to reduce Qgd.... Agent: Ostrolenk Faber Gerb & Soffen

20070210355 - Semiconductor device: A semiconductor device includes: an insulating layer; a semiconductor fin protruding from the insulating layer, extending in a first direction parallel to a major surface of the insulating layer, and having a source region, a channel section, and a drain region arranged in the first direction; a gate electrode opposed... Agent: Foley And Lardner LLP Suite 500

20070210352 - Semiconductor device and method of manufacturing the same: The present invention relates to a semiconductor device and a method of manufacturing the same, and is intended to keep the electrical resistance of source/drain regions at a low level while preventing diffusion of impurities from a semiconductor film and a sidewall. In order to achieve these objects, the semiconductor... Agent: Mcdermott Will & Emery LLP

20070210359 - Image sensor and method of manufacturing the same: An image sensor includes a first type semiconductor layer, a second type semiconductor layer and a first type well. The first type semiconductor layer is formed on a semiconductor substrate and includes a plurality of pixels which receive external light and convert optical charges into an electrical signal. The second... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070210360 - Cmos imager with selectively silicided gate: The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.... Agent: Dickstein Shapiro LLP

20070210361 - Ferroelectric capacitor and ferroelectric memory: A ferroelectric capacitor includes: a base substrate; a buffer layer formed above the base substrate; a lower electrode formed above the buffer layer; a ferroelectric layer formed above the lower electrode; and an upper electrode formed above the ferroelectric layer, wherein the buffer layer includes titanium (Ti) and cobalt (Co)... Agent: Harness, Dickey & Pierce, P.L.C

20070210362 - Non-volatile memory and the fabrication method: A non-volatile memory comprising: a first substrate (100) and a second substrate (110), the first substrate (100) having a plurality of switching elements (4) arranged in matrix, and a plurality of first electrodes (18) connected to the switching element (4), the second substrate (110) having a conductive film (32), and... Agent: Mcdermott Will & Emery LLP

20070210365 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a cylindrical capacitor. A size of hemispherical silicon grains (HSGs) formed in a straight portion of the cylindrical capacitor is smaller than a size of HSGs formed in a bowing portion of the cylindrical capacitor.... Agent: Sughrue Mion, PLLC

20070210364 - Mos capacitor and semiconductor device: A capacitor capable of functioning as a capacitor even when an AC voltage is applied thereto is provided without increasing the manufacturing steps of a semiconductor device. A transistor is used as a MOS capacitor where a pair of impurity regions formed on opposite sides of a channel formation region... Agent: Eric Robinson

20070210363 - Vertical soi transistor memory cell and method of forming the same: The present invention relates to a semiconductor device that contains at least one trench capacitor and at least one vertical transistor, and methods for forming such a semiconductor device. Specifically, the trench capacitor is located in a semiconductor substrate and comprises an outer electrode, an inner electrode, and a node... Agent: Scully Scott Murphy & Presser, PC

20070210366 - Trench isolation implantation: Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth. In various embodiments the implant... Agent: Brooks, Cameron & Huebsch , PLLC

20070210367 - Storage capacitor and method for producing such a storage capacitor: A storage capacitor includes a first electrode layer, second electrode layer and a dielectric interlayer arranged between the first electrode layer and the second electrode layer. The dielectric interlayer contains a high-k dielectric and at least one silicon-containing component.... Agent: Morrison & Foerster LLP

20070210368 - Gate structure and method of forming the gate structure, semiconductor device having the gate structure and method of manufacturing the semiconductor device: A gate structure in a semiconductor device includes a tunnel insulation layer disposed on a substrate, a first charge trapping layer disposed on the tunnel insulation layer, a second charge trapping layer disposed on the first charge trapping layer, a dielectric layer disposed to cover the second charge trapping layer,... Agent: Marger Johnson & Mccollom, P.C.

20070210370 - Nonvolatile memory devices with oblique charge storage regions and methods of forming the same: A nonvolatile memory device includes an active region defined by a device isolation layer in a semiconductor substrate, a word line passing over the active region and a charge storage region defined by a crossing of the active region and the word line and disposed between the active region and... Agent: Myers Bigel Sibley & Sajovec

20070210369 - Single gate-non-volatile flash memory cell: A non-volatile floating gate memory cell, having a single polysilicon gate, compatible with conventional logic processes, comprises a substrate of a first conductivity type. A first and a second region of a second conductivity type are in the substrate, spaced apart from one another to define a channel region therebetween.... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070210371 - Nonvolatile semiconductor memory device and its fabrication method: A memory cell includes a selective gate and a memory gate arranged on one side surface of the selective gate. The memory gate includes one part formed on one side surface of the selective gate and the other part electrically isolated from the selective gate and a p-well through an... Agent: Miles & Stockbridge PC

20070210372 - Memory cell array structures in nand flash memory devices and methods of fabricating the same: A NAND-type non-volatile semiconductor memory device includes a gate insulating layer on an active region of a semiconductor substrate, first and second select gate structures on the active region, and a memory gate structure therebetween. The first and second select gate structures respectively include a plurality of select gate patterns,... Agent: Myers Bigel Sibley & Sajovec

20070210373 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a bit line that is provided in a semiconductor substrate, a silicide layer that has side faces and a bottom face surrounded by the bit line and is provided within the bit line, an ONO film that is provided on the semiconductor substrate, and sidewalls that... Agent: Wagner, Murabito & Hao LLP

20070210374 - Vertical-type surrounding gate semiconductor device: A vertical-type surrounding gate semiconductor device is described. The semiconductor device comprises a pillar substrate, a collar oxide layer, a metal layer, a drain region, a ground line, a source region, a bit line, a word line, a gate and a gate dielectric layer. The ground line is formed in... Agent: Jianq Chyun Intellectual Property Office

20070210375 - Method for fabricating a semiconductor device: An embodiment of the invention provides a method for forming a semiconductor device comprising providing a substrate with a pad layer formed thereon. The pad layer and the substrate are patterned to form a plurality of trenches. A trench top insulating layer is formed in each trench. Wherein the trench... Agent: Quintero Law Office, PC

20070210376 - Integrated circuit system with double doped drain transistor: An integrated circuit system includes a substrate, forming a gate over the substrate, forming a first drift region having a first counter diffused region and a source diffused region, the first drift region in the substrate adjacent a first side of the gate, and forming a second drift region having... Agent: Ishimaru & Zahrt LLP

20070210377 - Semiconductor device and fabricating method thereof: A semiconductor device with a low drain current in the off-state of LDD type accommodating high voltages is provided. On the thermal oxide film, a polysilicon film and a CVD oxide film, and a resist pattern are formed, then the CVD oxide film is side-etched for formation of a CVD... Agent: Volentine & Whitt PLLC

20070210378 - Semiconductor device: A semiconductor device 10 includes a silicon substrate 20 having a first interconnection layer 24, a second interconnection layer 26, and grooves 22 provided at the second main surface 20b. Mounted on the substrate 20 are one or more semiconductor chips 30 having chip external terminals 32 electrically connected to... Agent: Rabin & Berdo, PC

20070210379 - Semiconductor device and manufacturing method thereof: It is an object to reduce the effect of a characteristic of the edge portion of a channel forming region in a semiconductor film, on a transistor characteristic. An island-like semiconductor film is formed over a substrate, and a conductive film forming a gate electrode provided over the island-like semiconductor... Agent: Eric Robinson

20070210380 - Body connection structure for soi mos transistor: A body connection structure for a SOI MOS transistor is described, including a first and a second control transistors. The first control transistor includes a gate electrically connecting with the gate of the SOI MOS transistor, a first S/D region electrically connecting with the first S/D region of the SOI... Agent: Jianq Chyun Intellectual Property Office

20070210381 - Electronic device and a process for forming the electronic device: An electronic device can have an insulating layer lying between a first semiconductor layer and a base layer. A second semiconductor layer, having a different composition and stress as compared to the first semiconductor layer, can overlie at least a portion of the first semiconductor layer. In one embodiment, a... Agent: Larson Newman Abel Polansky & White, LLP

20070210382 - Semiconductor device and method of manufacturing the same: Provided is a semiconductor device formed to an SOI substrate including a MOS transistor in which a parasitic MOS transistor is suppressed. The semiconductor device formed on the SOI substrate by employing a LOCOS process is structured such that a part of a a polysilicon layer to becomes a gate... Agent: Brinks Hofer Gilson & Lione

20070210383 - Semiconductor memory device and manufacturing method thereof: This discloser concerns a semiconductor device including an insulation layer; a FIN-type semiconductor layer provided on the insulation layer and including a floating body region in an electrically floating state and including a source region and a drain region at both sides of the floating body region; gate insulation films... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070210384 - Substrate-based silicon diode for electrostatic discharge protection: An integrated circuit device is disclosed that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, and a first isolation structure formed inside the well region. Further, a second isolation structure is formed inside the well region and spaced apart from the first isolation structure, a dielectric... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070210385 - Devices without current crowding effect at the finger's ends: ESD protection devices without current crowding effect at the finger's ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the MMOS or PMOS device structure is changed by the proposed new structures, therefore the MM ESD level of the NMOS and... Agent: Birch Stewart Kolasch & Birch

20070210386 - Plasma display apparatus: A plasma display apparatus which in its driving circuit mounts at least one of IGBTs having diodes built-in which are reverse conducting in a driving device which supplies a light emitting current and IGBTs having diodes built-in which have a reverse blocking function in a driving device which collects and... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070210387 - Esd protection device and method: An ESD protection device includes a source region, a channel region adjacent the source region, and an elongated drain region spaced from the source region by the channel region. The elongated drain region includes an unsilicided portion adjacent the channel and a silicided portion spaced from channel region by the... Agent: Slater & Matsil LLP

20070210388 - Semiconductor device and manufacturing method thereof: To provide a nonvolatile memory having an excellent data holding property and a technique for manufacturing the memory, a polycrystalline silicon film 7 and an insulating film 8 are sequentially stacked on a gate insulating film 6, then the polycrystalline silicon film 7 and the insulating film 8 are patterned... Agent: Miles & Stockbridge PC

20070210389 - Semiconductor constructions, and methods of forming semiconductor constructions: The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes... Agent: Wells St. John P.s.

20070210390 - Method of making an isolation trench and resulting isolation trench: A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of the trench, forming nitride spacers on... Agent: Dickstein Shapiro LLP

20070210391 - Dynamic array architecture: A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a... Agent: Martine Penilla & Gencarella, LLP

20070210392 - Semiconductor device: A semiconductor device is designed such that a semiconductor sensor chip having a diaphragm for detecting pressure variations based on the displacement thereof is fixed onto the upper surface of a substrate having a rectangular shape, which is covered with a cover member so as to form a hollow space... Agent: Dickstein Shapiro LLP

20070210393 - Lithographic method products obtained and use of said method: A lithographic method, products obtained thereby and use of the method, in particular, in the production of micro- or nano-metric products or objects. The method includes the steps of deposition of a film of an organometallic solution of a substrate, containing at least one metal ion as precursor(s) for marking... Agent: Young & Thompson

20070210394 - Method and structure for improved alignment in mram integration: A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment marks adjacent the first set of alignment marks. An opaque layer is formed over the lower level, including the... Agent: Cantor Colburn LLP-ibm Yorktown

20070210398 - Solid-state imaging device and method for driving the same: A pixel array is provided in which cells are arranged in a matrix. Each cell includes a photodiode, an FD, a transfer transistor, a reset transistor, an amplifying transistor having a gate electrode connected to the FD, a drain connected to a power supply line, and a source connected to... Agent: Mcdermott Will & Emery LLP

20070210396 - Photoelectric conversion device and image sensor: A photoelectric conversion device (10) includes a first conductivity type first semiconductor region (10a) located in a pixel region (11), a second conductivity type second semiconductor region (12) provided in the first semiconductor region (10a), for storing a signal charge, interconnecting portions (13 and 14) for connecting the second semiconductor... Agent: Brinks Hofer Gilson & Lione

20070210397 - Photoelectric conversion device, image sensor, and method of manufacturing a photoelectric conversion device: Provided is a photoelectric conversion device including: a semiconductor substrate (3) of a first conductivity type; a photoelectric conversion region (7) of a second conductivity type which is located in the semiconductor substrate (3), the second conductivity type being opposite to the first conductivity type; and a buried layer (17)... Agent: Brinks Hofer Gilson & Lione

20070210395 - Solid-state imaging device, method for producing same, and camera: A solid-state imaging device includes a substrate having a first surface and a second surface, light being incident on the second surface side; a wiring layer disposed on the first surface side; a photodetector formed in the substrate and including a first region of a first conductivity type; a transfer... Agent: Sonnenschein Nath & Rosenthal LLP

20070210399 - Micro-element package and manufacturing method thereof: A method of manufacturing a micro-element package which can reduce a manufacturing cost and improve productivity by simplifying its structure and manufacturing process, and also can make contributions to miniaturization and thinness, and the micro-element package are provided. The method of the micro-element package including: providing a substrate having a... Agent: Sughrue Mion, PLLC

20070210400 - Optical unit featuring both photoelectric conversion chip and semiconductor chip wrapped with flexible sheet: In an optical unit including a photoelectric conversion chip adapted to be optically connected to an optical fiber, and a semiconductor chip for driving the photoelectric conversion chip, both the photoelectric conversion chip and the semiconductor chip are wrapped with a flexible sheet, to thereby produce an enveloper enveloping the... Agent: Mcginn Intellectual Property Law Group, PLLC

20070210401 - Trench type schottky rectifier with oxide mass in trench bottom: A trench type junction barrier rectifier has silicon dioxide spacers at the bottom of trenches in a silicon surface and beneath the bottom of a conductive polysilicon filler in the trench. A Schottky barrier electrode is connected to the tops of the mesas and the tops of the polysilicon fillers.... Agent: Ostrolenk Faber Gerb & Soffen

20070210402 - Varactor: A varactor including a substrate, a P well disposed in the substrate, a gate structure disposed over the substrate, a p+ source disposed in the substrate at one side of the gate structure, a p+ drain disposed in the substrate at the other side of the gate structure, and a... Agent: J.c. Patents, Inc.

20070210404 - Semiconductor integrated circuit device: Repeaters are arranged at arbitrary positions to substantially improve transmission speed of a signal. In the semiconductor integrated circuit device 1, repeater regions 10 where repeaters are provided as relay points for wiring are provided in the central parts of the core power source regions 2, 3 and 5, on... Agent: Miles & Stockbridge PC

20070210405 - Semiconductor integrated circuit device and power source wiring method therefor: In a semiconductor integrated circuit device, from a first power source strap supplying a potential to a first standard cell receiving a supply of the potential, the potential is supplied via a first cell power source line having a constant width. The width of the first cell power source line... Agent: Mcdermott Will & Emery LLP

20070210403 - Isolation regions and their formation: A dielectric liner is formed in first and second trenches respectively in first and second portions of a substrate. A layer of material is formed overlying the dielectric liner so as to substantially concurrently substantially fill the first trench and partially fill the second trench. The layer of material is... Agent: Leffert Jay & Polglaze, P.A. Attn: Tod A. Myrum

20070210406 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a first interlayer insulating film, a second interlayer insulating film formed on the first interlayer insulating film, a plug having a lower portion surrounded by the first interlayer insulating film and an upper portion projecting from the first interlayer insulating film and surrounded by the second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070210407 - Laser ablation to selectively thin wafers/die to lower device rdson: A laser ablated wafer for a semiconductor device, such as a MOSFET or other power device, and a method of producing such a wafer to achieve a lower electrical resistance are provided. The method includes forming first holes, slots or trenches on a first surface of the wafer and focusing... Agent: Ostrolenk Faber Gerb & Soffen

20070210408 - Dielectric material separated-type, high breakdown voltage semiconductor circuit device, and production method thereof: The dielectrically isolated semiconductor device of the present invention comprises a substrate supporting single-crystalline silicon via an oxide film (SOI substrate), the substrate supporting an active element layer deeper than an expanded distance of a depletion layer subjected to the highest voltage applied to the device, and element isolating region... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070210409 - Semiconductor device including a capacitor structure and method of fabricating the same: A semiconductor device having improved capacitance may include a semiconductor substrate, a gate electrode on the semiconductor substrate, a capacitor lower electrode formed of substantially the same material as the gate electrode and being in the same layer as the gate electrode, an interlayer insulating film that covers the gate... Agent: Lee & Morse, P.C.

20070210410 - Edge termination structure for semiconductor components: A semiconductor component has a drift path (4) in a semiconductor body (5) of a semiconductor chip (6). The semiconductor component has an edge area (7) and a cell area (8), which is surrounded by the edge area (7). A trench structure (9), which surrounds the semiconductor component (6) in... Agent: Baker Botts, L.L.P.

20070210414 - Semiconductor device and a method of increasing a resistance value of an electric fuse: Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070210413 - Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabrication thereof: Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width... Agent: Ibm Corporation Department 417

20070210411 - Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof: Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside at different heights relative to... Agent: Ibm Corporation Department 417

20070210412 - Electrically programmable pi-shaped fuse structures and methods of fabrication thereof: Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and... Agent: Ibm Corporation Department 417

20070210415 - Anti-fuse and programming method of the same: The invention is directed to an anti-fuse comprised of a substrate, a gate electrode, and a gate dielectric layer. The gate electrode is located on the substrate. The gate dielectric layer is placed between the gate electrode and the substrate. The method of programming the anti-fuse is accomplished by applying... Agent: J.c. Patents, Inc. Suite 250

20070210416 - Capacitor structure: A capacitor structure has a plurality of stacked conductive patterns, and each conductive pattern has a closed conductive ring, a plurality of major conductive bars arranged in parallel and electrically to the closed conductive ring, and a plurality of minor conductive bars arranged alternately with the major conductive bars and... Agent: North America Intellectual Property Corporation

20070210417 - Chip carrier with reduced interference signal sensitivity: Carrier including a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first... Agent: Dickstein Shapiro, LLP

20070210418 - Semiconductor memory device: A memory includes a semiconductor layer provided on an insulation film provided on a first conductivity type substrate; a first well of a second conductivity type provided in the substrate; second wells of the first conductivity type provided in the first well; a third well of a second conductivity type... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070210419 - Electrostatic discharge protection device in integrated circuit: An electrostatic discharge protection device of a semiconductor integrated circuit, comprising a first diffusion layer that is a diffusion layer of a second conductivity type provided on a semiconductor substrate of a first conductivity type and serves as a collector, a second diffusion layer that is a diffusion layer of... Agent: Mcdermott Will & Emery LLP

20070210420 - Laser delamination of thin metal film using sacrificial polymer layer: A plastic substrate is provided, on which is disposed a sacrificial polymer layer and a thin metal film over the sacrificial polymer layer. The thin metal film is laser-delamination patterned. The sacrificial polymer layer is at least partially removed via laser delamination where the thin metal film has been removed... Agent: Hewlett Packard Company

20070210421 - Semiconductor device fabricated using a carbon-containing film as a contact etch stop layer: The invention provides, one aspect, a method of fabricating a semiconductor device. In one aspect, the method includes forming a carbide layer over a gate electrode and depositing a pre-metal dielectric layer over the carbide layer. The method provides a significant reduction in NBTI drift.... Agent: Texas Instruments Incorporated

20070210422 - Semiconductor package system with substrate having different bondable heights at lead finger tips: A semiconductor package system is provided. A substrate having a die attach paddle is provided. A first plurality of leads is provided around the die attach paddle having a first plurality of lead tips. A second plurality of leads is provided around the die attach paddle interleaved with the first... Agent: Ishimaru & Zahrt LLP

20070210423 - Embedded chip package structure: An embedded chip package structure is proposed. The embedded chip package structure includes a supporting board with a protruding section, a semiconductor chip formed on the protruding section of the supporting board, a dielectric layer formed on the supporting board and the semiconductor chip, and a circuit layer formed on... Agent: Birch Stewart Kolasch & Birch

20070210429 - Package structure for electronic device: A package structure with embedded electronic devices is provided. The package structure includes a substrate, a multi-layered circuit board, an adhesive film and at least an electronic device. The electronic device is disposed on the substrate. The electronic device is press-adhered to the multi-layered circuit board through the adhesive film... Agent: Jianq Chyun Intellectual Property Office

20070210428 - Die stack system and method: Embodiments of the present invention provide a die stack including a first substrate, a first die bonded to the first substrate, a second substrate having a cavity sized and shaped to fit over the first die, and a second die bonded to at least a portion of a rim of... Agent: Schwabe, Williamson & Wyatt, P.C.

20070210426 - Gold-bumped interposer for vertically integrated semiconductor system: A semiconductor system (100) enabled by an interposer (101) with non-reflow metal studs (251), preferably gold, coated with reflow metals (252), preferably solder. The studs are on exit ports (220, 230, etc) of the interposer surface; selected exit ports may be spaced apart by less than 125 μm center to... Agent: Texas Instruments Incorporated

20070210424 - Integrated circuit package in package system: An integrated circuit package in package system including forming a base integrated circuit package with a base lead having a portion with a substantially planar base surface, forming an extended-lead integrated circuit package with an extended lead having a portion with a substantially planar lead-end surface, and stacking the extended-lead... Agent: Ishimaru & Zahrt LLP

20070210425 - Integrated circuit package system: An integrated circuit package system is provided providing a first structure, forming a compression via in the first structure, forming a stud bump on a second structure and pressing the stud bump into the compression via forming a mechanical bond.... Agent: Ishimaru & Zahrt LLP

20070210430 - Semiconductor device and method of manufacturing the same: A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070210427 - Warp compensated package and method: Methods and apparatus are provided for an electronic panel assembly (EPA) (82, 83), comprising: providing one or more electronic devices (30) with primary faces (31) having electrical contacts (36), opposed rear faces (33) and edges (32) therebetween. The devices (30) are mounted primary faces (31) down on a temporary support... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070210431 - Support with integrated deposit of gas absorbing material for manufacturing microelectronic microoptoelectronic or micromechanical devices: The specification teaches a device for use in the manufacturing of microelectronic, microoptoelectronic or micromechanical devices (microdevices) in which a contaminant absorption layer improves the life and operation of the microdevice. In a preferred embodiment the invention includes a mechanical supporting base, and a layer of a gas absorbing or... Agent: Technology & Intellectual Property Strategies Group PC Dba Tips Group

20070210433 - Integrated device having a plurality of chip arrangements and method for producing the same: The invention provides an integrated device comprising a plurality of non-individually-encapsulated chip arrangements, each of which having a plurality of contact elements for contacting a contact pad, wherein the plurality of chip arrangements are stacked on each other such that the respective contact elements provide electrical connections to the respective... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070210432 - Stacked integrated circuits package system with passive components: A stacked integrated circuit package system is provided forming a first stack layer having a first integrated circuit die on a first substrate, forming a second stack layer having a second integrated circuit die on a second substrate, and mechanically and electrically connecting a spacer layer having a first passive... Agent: Ishimaru & Zahrt LLP

20070210435 - Stacked microelectronic dies and methods for stacking microelectronic dies: An assembly of microelectronic devices and method for forming an assembly of microelectronic devices. In one embodiment, the method includes positioning a first packaged microelectronic device adjacent to a support member having support member circuitry, with the first packaged microelectronic device having a first microelectronic die at least partially encased... Agent: Perkins Coie LLP Patent-sea

20070210434 - Structure of stacked integrated circuits and method for manufacturing the same: The structure of stacked integrated circuits includes a substrate having an upper surface formed with first electrodes, and a lower surface formed with second electrodes. A lower integrated circuit is formed with bonding pads, and is located on the upper surface of the substrate. First adhered glue is coated on... Agent: Pro-techtor International Services

20070210439 - Board on chip package and manufacturing method thereof: An aspect of the present invention features a manufacturing method of a board on chip package. The method can comprise: (a) laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; (b) patterning the dry film in accordance with a circuit... Agent: Staas & Halsey LLP

20070210436 - Integrated circuit package system: An integrated circuit package system is provided forming an integrated circuit die having a first bond pad provided thereon, forming an interconnect stack on a first external interconnect, and connecting the interconnect stack to the first bond pad.... Agent: Ishimaru & Zahrt LLP

20070210437 - Semiconductor device and manufacturing method thereof: A packaged semiconductor device is manufactured by a simplified manufacturing process, and is reduced in cost, in thickness and in size. A device component and a pad electrode connected with the device component are formed on a semiconductor substrate. A supporter is bonded to a top surface of the semiconductor... Agent: Morrison & Foerster LLP

20070210438 - Semiconductor package: A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.... Agent: Ostrolenk Faber Gerb & Soffen

20070210440 - Semiconductor device: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection... Agent: Darryl G. Walker

20070210441 - Microelectronic device assemblies including assemblies with recurved leadframes, and associated methods: Microelectronic device assemblies, including assemblies with recurved leadframes, and associated methods are disclosed. An assembly in accordance with one embodiment includes a microelectronic device having a first surface, a second surface facing opposite from the first surface, and a plurality of bond sites accessible from the first surface. An operable... Agent: Perkins Coie LLP Patent-sea

20070210442 - Method and apparatus for providing structural support for interconnect pad while allowing signal conductance: A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insulating layer overlies the first metal layer. A second metal layer overlies the... Agent: Freescale Semiconductor, Inc. Law Department

20070210443 - Integrated circuit package on package system: An integrated circuit package on package system including forming an interconnect integrated circuit package and attaching an extended-lead integrated circuit package on the interconnect integrated circuit package wherein a mold cap of the extended-lead integrated circuit package faces a mold cap of the interconnect integrated circuit package.... Agent: Ishimaru & Zahrt LLP

20070210444 - Methods of promoting adhesion between transfer molded ic packages and injection molded plastics for creating over-molded memory cards: A flash memory card and methods of manufacturing same are disclosed. The card includes a semiconductor package fabricated to receive a single-sided or double-sided lid. A surface of the semiconductor package may be formed with holes, trenches and/or pockmarks. After the holes, trenches and/or pockmarks are formed, a lid may... Agent: Vierra Magen/sandisk Corporation

20070210445 - Power semiconductor module and method for cooling a power semiconductor module: The invention relates to a power semiconductor module comprising a plurality of power semiconductors that are fixed to a first side of a printed circuit board (26), and a cooling device that acts by means of a coolant, on a second side of the printed circuit board (26), opposite the... Agent: Mccormick, Paulding & Huber LLP

20070210446 - Apparatus and methods for cooling semiconductor integrated circuit chip packages: Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070210447 - Elongated fasteners for securing together electronic components and substrates, semiconductor device assemblies including such fasteners, and accompanying systems and methods: Semiconductor device assemblies include elements such as electronic components and substrates secured together by a fastener that includes an elongated portion extending continuously through an aperture in two or more such elements. Computer systems include such semiconductor device assemblies. Fasteners for securing together such elements include an elongated portion, a... Agent: Trask Britt, P.C./ Micron Technology

20070210450 - Method of forming a bump and a connector structure having the bump: A bump may be formed by forming a diffusion barrier layer pattern over a substrate having a conductive pad; forming a seed layer over the substrate having the diffusion barrier layer pattern and the conductive pad; forming a conductive bump over the seed layer; and patterning the seed layer using... Agent: Lee & Morse, P.C.

20070210448 - Electroless cobalt-containing liner for middle-of-the-line (mol) applications: A semiconductor structure that includes a Co-containing liner disposed between an oxygen-getter layer and a metal-containing conductive material is provided. The Co-containing liner, the oxygen-getter layer and the metal-containing conductive material form MOL metallurgy where the Co-containing liner replaces a traditional TiN liner. By “Co-containing” is meant that the liner... Agent: Scully Scott Murphy & Presser, PC

20070210449 - Memory device and an array of conductive lines and methods of making the same: An array of conductive lines is formed on or at least partially in a semiconductor substrate. The array includes a number of conductive lines extending in a first direction, a number of landing pads made of a conductive material, with individual landing pads being connected to corresponding ones of the... Agent: Edell, Shapiro & Finnan, LLC

20070210451 - Semiconductor device and method of fabricating the same: There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects.... Agent: Fish & Richardson P.C.

20070210452 - Bump structure and method of manufacturing the same, and mounting structure for ic chip and circuit board: The invention provides a bump structure whose mounting position, shape, and size are favorably controlled and to a method of manufacturing the same. The bump structure of the invention can be provided on an insulating layer and includes a protruding part made of resin obtained by hardening a liquid material... Agent: Oliff & Berridge, PLC

20070210453 - Dummy-fill-structure placement for improved device feature location and access for integrated circuit failure analysis: An integrated circuit comprising interconnects located in a layer on a semiconductor substrate. The circuit also comprises dummy-fill-structures located between the interconnects in the layer. The dummy-fill-structures form a plurality of fiducials, each of the fiducials being located in a different region of the layer. Each fiducial comprises a pre-defined... Agent: Texas Instruments Incorporated

20070210454 - Structure of metal interconnect and fabrication method thereof: A process and structure for a metal interconnect comprises providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and... Agent: North America Intellectual Property Corporation

20070210455 - Carbon nanotube-modified low-k materials: An interconnect structure for use in an integrated circuit is provided. The interconnect structure includes a first low-K dielectric material. The first low-K material may be modified with a first group of carbon nanotubes (CNTs) and disposed on a metal line. The first low-K material is modified by dispersing the... Agent: Stmicroelectronics, Inc.

20070210456 - Multi-chip package: A multi-chip package suppresses a change, which is caused by packaging, of a circuit characteristic of an analog circuit of which characteristic is adjusted by a nonvolatile register. A digital circuit and an analog circuit are formed on a semiconductor chip. A nonvolatile register is also formed on the semiconductor... Agent: Morrison & Foerster LLP

20070210457 - Composite bump: A composite bump suitable for disposing on a substrate pad is provided. The composite bump includes a compliant body and an outer conductive layer. The coefficient of thermal expansion (CTE) of the compliant body is between 5 ppm/° C. and 200 ppm/° C. The outer conductive layer covers the compliant... Agent: Jianq Chyun Intellectual Property Office

20070210458 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device includes a base plate including a plurality of terminals; a semiconductor chip, mounted above the base plate, including a plurality of pads arranged on a face of the semiconductor chip; an insulating slope member, disposed around the semiconductor chip, covering steps between the semiconductor chip and the... Agent: Harness, Dickey & Pierce, P.L.C

20070210459 - Method for edge sealing barrier films: An edge-sealed barrier film composite. The composite includes a substrate and at least one initial barrier stack adjacent to the substrate. The at least one initial barrier stack includes at least one decoupling layer and at least one barrier layer. One of the barrier layers has an area greater than... Agent: Dinsmore & Shohl LLP One Dayton Centre

20070210460 - Substrate processing and alignment: A substrate can efficiently be manufactured by separating the alignment and the actual processing when an alignment mark is provided, which is fixed with respect to the substrate and when position information on a position of a process area on the substrate is retrieved with respect to the alignment mark... Agent: William C. Milks, Iii Russo & Hale LLP

20070210461 - Semiconductor device packaging: Methods and apparatus are provided for encapsulating electronic devices, comprising: providing one or more electronic devices (62) with primary faces (63) having electrical contacts (69), opposed rear faces (65) and edges (64) therebetween. A sacrificial layer (70) is provided on the primary faces (63). The devices (62) are mounted on... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070205407 - Nitride semiconductor device and method for fabricating the same: A nitride semiconductor device includes a semiconductor stacked structure which is formed of a nitride semiconductor having a first principal surface and a second principal surface opposed to the first principal surface and which includes an active layer. The first principal surface of the semiconductor stacked structure is formed with... Agent: Mcdermott Will & Emery LLP

20070205408 - Microstructure for formation of a silicon and germanium on insulator substrate of si1-xgex type: The microstructure is designed for formation of a silicon and germanium on insulator substrate of Si1-XfGeXf type, with Xf comprised between a first value that is not zero and 1. The microstructure is formed by stacking of a silicon on insulator substrate and a first initial layer of silicon and... Agent: Oliff & Berridge, PLC

20070205410 - Light-emitting element, light-emitting device, and electronic device: It is an object to provide a light-emitting element having high light-emitting efficiency, which includes a first electrode, a second electrode, and a light-emitting layer between the first electrode and the second electrode, where the light-emitting layer contains a base material, a first impurity element, a second impurity element, and... Agent: Fish & Richardson P.C.

20070205412 - Novel anthracene derivative and organic electronic device using the same: The present invention provides a novel anthracene derivative and an organic electronic device using the same. The organic electronic device according to the present invention shows excellent characteristics in efficiency, drive voltage, and life time.... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070205411 - Organic electroluminescence device: An organic electroluminescence device of multi-photon emission mode which includes plural light emission layers and at least one charge generation layer between a pair of electrodes, arranged in a film thickness direction thereof, wherein the charge generation layer includes at least one p-doped layer and at least one n-doped layer,... Agent: Birch Stewart Kolasch & Birch

20070205409 - Process for making contained layers and devices made with same:

20070205418 - Light emitting device and electronic device: To improve light extraction efficiency of light emitting elements such as electroluminescent elements. A first electrode 101, a light emitting layer 102, and a second electrode 103 are formed over a substrate 100, which partially constitute a light emitting element. Light produced in the light emitting layer 102 is emitted... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070205416 - Light emitting element, light emitting device and electronic device: A light emitting element that can be driven at a low voltage is provided. Further, a light emitting device and an electronic device with reduced power consumption are provided. A light emitting element is provided that includes a substrate 100, and a first electrode 101, a first insulating layer 102,... Agent: Fish & Richardson P.C.

20070205417 - Light-emitting element, light-emitting device, lighting device, and electronic appliance: The light-emitting layer contains a light-emitting base including a chalcogenide compound, and a light-emitting center including two kinds of halogen compounds. The chalcogenide compound contains a chalcogen element and an element selected from elements belonging to Group 2 to Group 13 of the periodic table, and the halogen compound contains... Agent: Fish & Richardson P.C.

20070205419 - Semiconductor device and its manufacturing method: A semiconductor device comprises a support member having a pair of first conductive materials and a pair of second conductive materials on an insulating substrate, and a sealing member covering a semiconductor element arranged on the support member, wherein the support member has an insulating portion where the insulating substrate... Agent: Smith Patent Office

20070205424 - Nitride semiconductor light emitting device, method of manufacturing nitride semiconductor light emitting device, and nitride semiconductor transistor device: Provided are a nitride semiconductor light emitting device including a coat film formed at a light emitting portion and including an aluminum nitride crystal or an aluminum oxynitride crystal, and a method of manufacturing the nitride semiconductor light emitting device. Also provided is a nitride semiconductor transistor device including a... Agent: Harness, Dickey & Pierce, P.L.C

20070205406 - Phase change memory device and method of manufacture thereof: A method of manufacturing a memory device is provided. The method includes forming an electrode over a substrate. The method also includes forming an opening in the electrode to provide a tapered electrode contact surface proximate the opening. The method further includes forming a phase change feature over the electrode... Agent: Haynes And Boone, LLP

20070205413 - Semiconductor device and manufacturing method thereof: A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, a GOLD structure or an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel portion is connected to the pixel TFT through a hole bored... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070205414 - Method for forming an improved low power sram contact: A method of forming contact openings in a semiconductor device including providing a semiconducting substrate; forming an etch stop layer on said semiconducting substrate; forming a dielectric layer on said etch stop layer; forming a bottom anti-reflective coating (BARC) on said dielectric layer; forming and patterning a mask on said... Agent: Tung & Associates

20070205415 - Semiconductor device and manufacturing method thereof: To obtain a semiconductor device containing TFTs of different, suitable properties as display pixel TFTs and high-voltage, driver-circuit TFTs, the semiconductor device of the present invention includes: first and second islands-shaped polycrystalline silicon (p-Si) layers provided above an insulating substrate and having relatively large grain sizes; a third islands-shaped p-Si... Agent: Nixon & Vanderhye, PC

20070205420 - Electroluminescent display devices: An active matrix display device comprises an array of display pixels provided over a common substrate (60). Each pixel has an upwardly emitting current-driven light emitting display element (2) comprising a lower electrode (74) and an upper substantially transparent electrode (80a. A light sensitive device (27) for sensing the display... Agent: Philips Intellectual Property & Standards

20070205421 - Semiconductor optical devices and method for forming: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the... Agent: Freescale Semiconductor, Inc. Law Department

20070205422 - Liquid crystal display device and fabricating method thereof: A thin film transistor substrate and a fabricating method thereof for simplifying a process are disclosed. In a liquid crystal display device according to the present invention, a gate line is provided on a substrate. A data line crosses the gate line with having a gate insulating film therebetween to... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070205423 - Semiconductor device: It is an object to provide a thin-type full-color display device with the long lifetime, inexpensively, in which desired emission luminance and desired color purity can be obtained at a low voltage. In a light-emitting device capable of full-color display, among a plurality of light-emitting elements emitting different emission colors... Agent: Fish & Richardson P.C.

20070205425 - Semiconductor light-emitting device: In a conventional semiconductor light-emitting device having a semiconductor light-emitting element-mounted body and an optical lens which are located adjacent each other, interfacial peeling sometimes occurs at the contact interfaces between components when the device is subjected to outside temperature changes. This may lead to the deterioration of optical characteristics... Agent: Cermak Kenealy & Vaidya, LLP

20070205426 - Semiconductor light-emitting device: A semiconductor light-emitting device includes a semiconductor light-emitting element and a lead-out electrode. The semiconductor light-emitting element has a light-emitting surface of polygonal shape and an electrode formed on the light-emitting surface. The lead-out electrode is connected to the electrode. In the semiconductor light-emitting device, the electrode is formed along... Agent: Ndq&m Watchstone LLP

20070205427 - Side structure of a bare led and backlight module thereof: The present invention discloses a side structure of a bare LED and a backlight module thereof, wherein the backlight module is preferably a light source of a display device such as an LCD device. The backlight module includes a flat plate covered with a thermally conductive dielectric material, a plurality... Agent: Bacon & Thomas, PLLC

20070205428 - Light-emitting material, light-emitting element, light-emitting device, electronic device, and manufacturing method of light-emitting material: To provide a light-emitting material made of an inorganic compound, which exhibits higher luminance than the conventional material, due to its crystal structure. The light-emitting material includes a host material and an impurity element which serves as a luminescence center. The main crystal structure of the light-emitting material is hexagonal.... Agent: Fish & Richardson P.C.

20070205429 - Nitride semiconductor light-emitting device and method for manufacturing the same: Provided are a nitride semiconductor light-emitting device and a method for manufacturing the same, capable of improving light emitting efficiency by forming a reflection layer on a lateral side of an LED chip. Am embodiment provides a nitride semiconductor light-emitting device includes a light-emitting device chip and a reflection layer.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070205430 - Method and structure of refractory metal reach through in bipolar transistor: Structure and method of structure in which a contact, e.g., low resistance; ohmic; resulting in Schottky isolation, is coupled to a doped region that is buried in a substrate. In a bipolar transistor having a collector region formed below an upper surface of a substrate, a trench is formed through... Agent: Greenblum & Bernstein, P.L.C

20070205431 - Bi-directional transistor with by-pass path and method therefor: In one embodiment, a transistor is formed to have a first current flow path to selectively conduct current in both directions through the transistor and to have a second current flow path to selectively conduct current in one direction.... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070205432 - Heterojunction bipolar transistor and power amplifier using same: In order to lay out a power amplifier heterojunction bipolar transistor capable of large power output in a small area, the subject invention provides a heterojunction bipolar transistor constituted of a plurality of transistor components arranged on a sub-collector layer, collector layers of said transistor components being separated one another,... Agent: Nixon & Vanderhye, PC

20070205433 - Insulating gate algan/gan hemts: AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to reduce trapping and also having additional layers to reduce gate leakage and increase the maximum drive current. One HEMT according to the present invention comprises a high resistivity semiconductor layer with a barrier semiconductor layer on it. The barrier layer... Agent: Koppel, Patrick & Heybl

20070205434 - Methodology for recovery of hot carrier induced degradation in bipolar devices: A method for recovery of degradation caused by avalanche hot carriers is provided that includes subjecting an idle bipolar transistor exhibiting avalanche degradation to a thermal anneal step which increases temperature of the transistor thereby recovering the avalanche degradation of the bipolar transistor. In one embodiment, the annealing source is... Agent: Scully, Scott, Murphy & Presser, P.C.

20070205435 - Versatile system for optimizing current gain in bipolar transistor structures: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on... Agent: Texas Instruments Incorporated

20070205436 - Flash memory cell with split gate structure and method for forming the same: A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface thereof. A cap... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070205437 - Method for the production of a semiconductor substrate comprising a plurality of gate stacks on a semiconductor substrate, and corresponding semiconductor structure: A semiconductor structure having a plurality of gate stacks on a semiconductor substrate provided with a gate dielectric. The gate stacks have a lower first layer made of polysilicon, an overlying second layer made of a metal silicide, and an upper third layer made of an insulating material, and a... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070205438 - Masking process for simultaneously patterning separate regions: According to another embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate... Agent: Knobbe Martens Olson & Bear LLP

20070205439 - Image pickup apparatus and image pickup system: An image pickup apparatus of the present invention includes a plurality of photoelectric conversion elements disposed on a semiconductor substrate, a multi-layer wiring structure including a plurality of interlayer insulation films disposed above the semiconductor substrate, and a passiation layer disposed above the multi-layer wiring structure. A first insulation layer... Agent: Fitzpatrick Cella Harper & Scinto

20070205440 - Semiconductor device and method for producing the same: A semiconductor device comprises a floating gate which is formed on a semiconductor substrate of a first conductive type interposing a first gate insulation layer therebetween, a second charge retaining area which is formed on the semiconductor substrate interposing a second insulation layer, a control gate which is formed on... Agent: Miles & Stockbridge PC

20070205441 - Manufacturing method of semiconductor device suppressing short-channel effect: An ideal step-profile in a channel region is realized easily and reliably, whereby suppression of the short-channel effect and prevention of mobility degradation are achieved together. A silicon substrate is amorphized to a predetermined depth from a semiconductor film, and impurities to become the source/drain are introduced in this state.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070205444 - Architecture of a n-type metal-oxide-semiconductor transistor with a compressive strained silicon-germanium channel fabricated on a silicon (110) substrate: The present invention discloses an architecture of a NMOS transistor with a compressive strained Si—Ge channel fabricated on a silicon (110) substrate, which comprises: a p-silicon (110) substrate, two n+ ion-implanted regions functioning as the source and the drain respectively, a compressive strained Si—Ge channel layer, and a gate structure.... Agent: Rosenberg, Klein & Lee

20070205446 - Reducing nitrogen concentration with in-situ steam generation: In-situ steam generation (ISSG) is used to reduce the nitrogen concentration in silicon and silicon oxide areas.... Agent: Macpherson Kwok Chen & Heid LLP

20070205442 - Semiconductor device: A semiconductor device 10 comprises a P type base region 13 formed in an N− type base region 11, and N+ type emitter regions 14 formed plurally in the P type base region 13 so as to be spaced form each other. The N+ type emitter regions 14 are formed... Agent: Townsend And Townsend And Crew, LLP

20070205445 - Semiconductor device having a field effect source/drain region: A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by... Agent: F. Chau & Associates, LLC

20070205443 - Vertical gated access transistor: According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The plurality of... Agent: Knobbe Martens Olson & Bear LLP

20070205447 - Active pixel sensor with a diagonal active area: An imaging device formed as a CMOS semiconductor integrated circuit having two adjacent pixels in a row connected to a common column line. By having adjacent pixels of a row share column lines, the CMOS imager circuit eliminates half the column lines of a traditional imager allowing the fabrication of... Agent: Dickstein Shapiro LLP

20070205449 - Memory device which comprises a multi-layer capacitor: A memory device is provided. The memory device including memory cells having at least three stacked electrodes spaced apart pairwise by dielectric material so that the pairs of electrodes form respective capacitor layers. The capacitors are connected electrically in parallel to each other. The dielectric material is optionally ferroelectric material,... Agent: Bell, Boyd & Lloyd, LLP

20070205448 - Ferroelectric tunneling element and memory applications which utilize the tunneling element: A tunneling element includes a thin film layer of ferroelectric material and a pair of dissimilar electrically-conductive layers disposed on opposite sides of the ferroelectric layer. Because of the dissimilarity in composition or construction between the electrically-conductive layers, the electron transport behavior of the electrically-conductive layers is polarization dependent when... Agent: Michael E. Mckee Attorney At Law

20070205450 - Semiconductor device and method of manufacturing the same: A plurality of origin patterns (3) containing a metal catalyst are formed over a semiconductor substrate (1). Next, an insulating film (4) covering the origin patterns (3) is formed. Next, a trench allowing at the both ends thereof the side faces of the origin patterns (3) to expose is formed.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070205451 - Semiconductor integrated circuit and method of designing semiconductor integrated circuit: In the present invention, a decoupling capacitance circuit, a first output terminal and a second output terminal are provided. The decoupling capacitance circuit comprises a TDDB control circuit consisting of a first Tr and a second Tr, and a third Tr. Conductivity types of the first and second Trs are... Agent: Mcdermott Will & Emery LLP

20070205452 - Method for forming a metal oxide film: A method for forming a capacitor insulation film includes the step of depositing a monoatomic film made of a metal by supplying a metal source including the metal and no oxygen, and depositing a metal oxide film including the metal by using a CVD technique. The method provides the metal... Agent: Katten Muchin Rosenman LLP

20070205456 - Nonvolatile memory device and nonvolatile memory array including the same: A nonvolatile memory device having self-presence diode characteristics, and/or a nonvolatile memory array including the nonvolatile memory device may be provided. The nonvolatile memory device may include a lower electrode, a first semiconductor oxide layer on the lower electrode, a second semiconductor oxide layer on the first semiconductor oxide layer,... Agent: Harness, Dickey & Pierce, P.L.C

20070205453 - Semiconductor device and method for manufacturing the same: A semiconductor device prevents diffusion of electric charges retained in silicon nitride films of a MOSFET during a writing operation and has a favorable charge retention property. The silicon nitride films, each of which functions as a memory functional body, are formed at a thickness of 100 Å at a... Agent: Volentine & Whitt PLLC

20070205454 - Dual storage node memory: An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage element, wherein the first and second charge storage elements include nitrides. The memory cell further includes an insulating layer formed between the first and... Agent: Wagner, Murabito & Hao LLP

20070205455 - Flash memory cells having trenched storage elements: An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side... Agent: Wagner, Murabito & Hao LLP

20070205457 - Semiconductor memory device with bit line of small resistance and manufacturing method thereof: A reduction of a resistance of a bit line of a memory cell array and a reduction of a forming area of the memory cell array are planed. Respective bit lines running at right angles to a word line are composed of a diffusion bit line formed in a semiconductor... Agent: Mcdermott Will & Emery LLP

20070205458 - Non-volatile semiconductor memory and manufacturing process thereof: A non-volatile semiconductor memory which can suppress a leak current, improve dielectric strength and ensure large capacitance between a control gate and a floating gate and a manufacturing process thereof. A silicon nitride film is formed on the floating gate electrode layer of a memory cell and has a thickness... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070205459 - Nonvolatile memory devices and methods of forming the same: A nonvolatile memory device includes a semiconductor pin including a first semiconductor pattern, a second semiconductor pattern on the first semiconductor pattern, and a third semiconductor pattern, disposed between the first semiconductor pattern and the second semiconductor pattern, connecting the first semiconductor pattern and the second semiconductor pattern, a charge... Agent: Lee & Morse, P.C.

20070205460 - Nonvolatile memory devices and methods of forming the same: Embodiments herein present device, method, etc. for a hybrid orientation scheme for standard orthogonal circuits. An integrated circuit of embodiments of the invention comprises a hybrid orientation substrate, comprising first areas having a first crystalline orientation and second areas having a second crystalline orientation. The first crystalline orientation of the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070205461 - Power fet with embedded body pickup: A power transistor formed on a semiconductor substrate and including a lateral array of polysilicon lines separated by alternating source and drain regions includes one or more body contact diffusion regions formed in the source regions where each body contact diffusion region has a length that extends to the edges... Agent: Patent Law Group LLP

20070205462 - Semiconductor device and manufacturing method thereof: A semiconductor device includes: a semiconductor base material; an insulating layer selectively formed on the semiconductor base material; a first semiconductor layer made of single-crystal and formed on the semiconductor base material that is exposed below the insulating layer, the first semiconductor layer having an opening that exposes the semiconductor... Agent: Advantedge Law Group, LLC

20070205463 - Semiconductor-on-insulator silicon wafer: A method of fabricating a semiconductor-on-insulator semiconductor wafer is described that includes providing first and second semiconductor substrates. A first insulating layer is formed on the first substrate with a first predetermined stress and a second insulating layer is formed on the second substrate with a second predetermined stress different... Agent: Robert A. Parsons

20070205464 - Semiconductor component arrangement having a power transistor and a temperature measuring arrangement: A semiconductor component arrangement includes a power transistor and a temperature measurement circuit. The power transistor includes a gate electrode, a source zone, a drain zone and a body zone. The body zone is arranged in a first semiconductor zone of a first conduction type. The temperature measuring circuit comprises... Agent: Maginot, Moore & Beck

20070205465 - Semiconductor device and fabrication method thereof: A semiconductor device includes: a gate electrode on a semiconductor substrate; side wall spacers on side surfaces of the gate electrode; a source portion and a drain portion in the semiconductor substrate, the source portion and the drain portion being provided laterally to the side wall spacers; an on-source silicide... Agent: Mcdermott Will & Emery LLP

20070205466 - Semiconductor device: Provided is a semiconductor device capable of easily setting a holding voltage with a low trigger voltage by locally forming a P-type diffusion layer between N-type source and drain diffusion layers of an NMOS transistor having a conventional drain structure used as an electrostatic protective element of the semiconductor device.... Agent: Bruce L. Adams, Esq.

20070205467 - Semiconductor device and process for producing the same: A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070205468 - Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer: A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P... Agent: Haynes And Boone, LLP

20070205469 - Integrated circuit isolation system: A method of manufacturing a self-aligned inverted T-shaped isolation structure. An integrated circuit isolation system including providing a substrate, forming a base insulator region in the substrate, and depositing an insulator column having a narrower width than the base insulator region on the base insulator region.... Agent: Ishimaru & Zahrt LLP

20070205470 - Low-power high-performance storage circuitry: An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including a... Agent: San Francisco Office Of Novak, Druce & Quigg LLP

20070205471 - Integrated circuit with multi-length output transistor segments: A monolithic integrated circuit fabricated on a semiconductor die includes a control circuit and a first output transistor having segments substantially equal to a first length. A second output transistor has segments substantially equal to a second length. The first and second output transistors occupy an L-shaped area of the... Agent: The Law Offices Of Bradley J. Bereznak

20070205472 - Formation of a disposable spacer to post dope a gate conductor: A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in... Agent: Scully, Scott, Murphy & Presser, P.C.

20070205474 - Pressure sensor having gold-silicon eutectic crystal layer interposed between contact layer and silicon substrate: A pressure sensor includes a gold-silicon eutectic crystal layer interposed between the contact layer and the silicon substrate. Because the contact layer and the silicon substrate are electrically connected to each other by using a gold-silicon eutectic reaction at the time of bonding the silicon substrate and the glass substrate,... Agent: Brinks Hofer Gilson & Lione

20070205473 - Passive analog thermal isolation structure: A thermal isolation structure for use in passively regulating the temperature of a microdevice is disclosed. The thermal isolation structure can include a substrate wafer and a cap wafer defining an interior cavity, and a number of double-ended or single-ended thermal bimorphs coupled to the substrate wafer and thermally actuatable... Agent: Honeywell International Inc.

20070205475 - Apparatus for measuring a mechanical quantity: A mechanical quantity measuring apparatus is provided which can make highly precise measurements and is not easily affected by noise even when it is supplied an electricity through electromagnetic induction or microwaves. At least a strain sensor and an amplifier, an analog/digital converter, a rectification/detection/modulation-demodulation circuit, and a communication control... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070205476 - Printed magnetic rom-mprom: The invention relates to a method for storing information on a storage device (100) by depositing electromagnetic material (104) in a pattern on a sensor surface (106) of the storage device, the pattern representing the information to be stored. The storage device (100) comprises an array of sensor elements (101)... Agent: Philips Intellectual Property & Standards

20070205477 - Photoelectric conversion device and solid-state imaging device: A photoelectric conversion device including a photoelectric conversion part including a pair of electrodes and a photoelectric conversion layer provided between the pair of electrodes, wherein the photoelectric conversion part further includes a first charge blocking layer for reducing an injection of a charge into the photoelectric conversion layer from... Agent: Sughrue-265550

20070205478 - Photodiode having increased proportion of light-sensitive area to light-insensitive area: A photodiode having an increased proportion of light-sensitive area to light-insensitive area includes a semiconductor having a backside surface and a light-sensitive frontside surface. The semiconductor includes a first active layer having a first conductivity, a second active layer having a second conductivity opposite the first conductivity, and an intrinsic... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070205479 - Method for attaching a flexible structure to a device and a device having a flexible structure: Techniques for producing a flexible structure attached to a device. One embodiment includes the steps of providing a first substrate, providing a second substrate with a releasably attached flexible structure, providing a bonding layer on at least one of the first substrate and the flexible structure, adjoining the first and... Agent: Law Office Of Ido Tuchman (yor)

20070205480 - Semiconductor device: With this semiconductor device, the distortion and cracking of a thinned portion of a semiconductor substrate are prevented to enable high precision focusing with respect to a photodetecting unit and uniformity and stability of high sensitivity of the photodetecting unit to be maintained. A semiconductor device 1 has a semiconductor... Agent: Drinker Biddle & Reath (dc)

20070205481 - Manufacturing method for semiconductor device, semiconductor device and semiconductor wafer: A manufacturing method for a semiconductor device formed in a device region composed of a plurality of semiconductor layers on a substrate, the method including a trench forming step of forming a trench on the substrate around the device region and a semiconductor growth step of growing the semiconductor layer... Agent: Greenblum & Bernstein, P.L.C

20070205484 - Semiconductor device and method of fabricating the same: A semiconductor device capable of preventing an interlayer dielectric film from deterioration resulting from a liquid such as a chemical solution penetrating into the interlayer dielectric film and recovering the interlayer dielectric film from deterioration with a prescribed gas is obtained. This semiconductor device comprises a first insulating film formed... Agent: Mcdermott Will & Emery LLP

20070205483 - Mixed-scale electronic interface: Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. The predominantly nanoscale layer, in one embodiment... Agent: Hewlett Packard Company

20070205482 - Novel structure and method for metal integration: An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of forming the interconnect structure does not disrupt the coverage of the deposited diffusion barrier in the... Agent: Scully Scott Murphy & Presser, PC

20070205485 - Programmable anti-fuse structures, methods for fabricating programmable anti-fuse structures, and methods of programming anti-fuse structures: Programmable anti-fuse structures for semiconductor device constructions, fabrication methods for forming anti-fuse structures during semiconductor device fabrication, and programming methods for anti-fuse structures. The programmable anti-fuse structure comprises first and second terminals and an anti-fuse layer electrically coupled with the first and second terminals. An electrically-conductive diffusion layer is disposed... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20070205486 - Thin film capacitor device used for a decoupling capacitor and having a resistor inside: A thin film capacitor device of the present invention has a thin film capacitor having two electrodes and a dielectric layer provided therebetween and external terminals electrically connected to the electrodes. In addition, the thin film capacitor device also has resistor layers which are provided between the external terminals and... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070205487 - Lateral bipolar transistor: A P+ base drawing diffusion region is formed on a substrate having an SOI structure. N+ emitter diffusion regions are formed on both sides of the P+ base drawing diffusion region through isolation insulating films interposed therebetween. A P type SOI layer, which serves as a base diffusion region, is... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070205488 - Light-detecting device and manufacturing method thereof: A light-detecting device, comprising: a semiconductor substrate 101 that is composed of silicon as a base material, and contains carbon at a predetermined concentration; and an epitaxial layer 102 that is formed on the semiconductor substrate 101 and composed of silicon as a base material, the epitaxial layer 102 including... Agent: Mcdermott Will & Emery LLP

20070205489 - Methods of fabricating isolation regions of semiconductor devices and structures thereof: Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A... Agent: Slater & Matsil LLP

20070205490 - Method for production of semiconductor chip, and semiconductor chip: A method for the production of gallium nitride compound semiconductor chips from a wafer having gallium nitride compound semiconductor layers (2, 3) laminated on the principal surface of a substrate (1) comprises a step of forming first grooves (11) linearly in a desired chip shape by etching on the gallium... Agent: Sughrue Mion, PLLC

20070205491 - Insulating material: An insulating material comprising a multiplicity of highly porous particles embedded within a matrix material, the pores within the particles being substantially evacuated.... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070205492 - Mems microphone with a stacked pcb package and method of producing the same: A MEMS microphone with a stacked PCB package is described. The MEMS package has at least one MEMS acoustic sensor device located on a PCB stack. A metal cap structure surrounds the at least one MEMS acoustic sensor device wherein an edge surface of the metal cap structure is attached... Agent: George O Saile And Assocs

20070205493 - Semiconductor package structure and method for manufacturing the same: A semiconductor package structure is disclosed. The structure includes a lead frame, a semiconductor chip, a plurality of metallic conducting wires, an encapsulation, a barrier layer and a pure tin layer, herein the lead frame has at least one die pad, a plurality of inner leads and outer leads. The... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070205494 - Chip-size package structure and method of the same: The method includes a step of picking and placing standard good dice on a base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The method of the chip-size package comprises the steps of separating dice on a wafer and picking... Agent: Kusner & Jaffe Highland Place Suite 310

20070205495 - Electronic component with stacked semiconductor chips and heat dissipating means: Electronic component (1; 20) has at least one stack (2; 21, 23) with at least two semiconductor chips (8, 9; 32, 33; 42, 43). Each semiconductor chip (8, 9; 32, 33; 42, 43) includes an active surface including integrated circuits (11; 35) and chip contact pads (10; 34) at least... Agent: Baker Botts, L.L.P.

20070205496 - Microelectronic packages and methods therefor: A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic... Agent: Tessera Lerner David Et Al.

20070205497 - Lead(pb)-free electronic component attachment: A contact tail for an electronic component useful for attachment of components using conductive adhesive, which may be lead (Pb)-free. The contact tail is stamped, providing a relatively low manufacturing cost and high precision. The contact tail has a distal portion with a large surface area per unit length. The... Agent: Blank Rome LLP

20070205498 - Signal routing in a multilayered printed circuit board: A signal routing technique for a multilayered printed circuit board is provided. The multilayered printed circuit board comprises a top layer, a bottom layer and at least one internal layer. Signals for a first subset of a plurality of higher speed buses are routed in stripline on the first internal... Agent: Edell, Shapiro & Finnan, LLC

20070205499 - Microelectromechanical microphone packaging system: The invention relates to a microelectromechanical microphone packaging system. The microelectromechanical microphone packaging system comprises a substrate, a chip, a microelectromechanical microphone, a conductive glue, a non-conductive glue and a cover. The substrate has a first surface. The chip is mounted on the first surface of the substrate. The microelectromechanical... Agent: Volentine & Whitt PLLC

20070205501 - Package warpage control: A method of packaging includes placing a restrainer on a package during processing. The method includes clipping the restrainer in place and then exposing the package to high temperatures. After processing the restrainer is removed. An alternative process attaches a component die to a substrate having a cavity in a... Agent: Marger Johnson & Mccollom, P.C.

20070205500 - Power semiconductor module: The power semiconductor module (1) has a heat-conducting base plate (11) on which at least three substrates (2, 3, 4, 5, 6, 7) are placed, each substrate supporting at least one power semiconductor component (8, 9) that gives off heat generated during operation. In order to optimize a power semiconductor... Agent: Baker Botts, L.L.P.

20070205503 - Package and package assembly of power device: A package and a package assembly for a power device having a high operation voltage and impulse voltage are provided. The package assembly for a power device comprises an assembly wherein the power device is encapsulated and electrically connected to a lead protruding outside the package, and an isolation spacer... Agent: Hiscock & Barclay, LLP

20070205502 - Methods and apparatus for thermal isolation in vertically-integrated semiconductor devices: A semiconductor structure (100) includes a first substrate (110) having a first semiconductor device (112) formed therein, a second substrate (120) having a second device (122) formed therein and vertically-integrated above the first substrate (110), and a thermal isolation gap (130) disposed between the first device (112) and the second... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070205504 - Multichip device: A multichip device, which achieves a normal operation and a testing operation without the needs for terminals dedicated for the testing and/or an interposer substrate, is provided. The peripheral chip also includes a switching unit for providing a switching between a normal mode that provides a first connection condition and... Agent: Sughrue Mion, PLLC

20070205505 - Semiconductor device having capacitors for reducing power source noise: A semiconductor device comprises a BGA substrate having one principal plane furnished with a large number of solder balls, the solder balls constituting a ball grid array; a semiconductor chip mounted on another principal plane of the BGA substrate, the semiconductor chip being electrically connected to the BGA substrate by... Agent: Mcdermott Will & Emery LLP

20070205506 - Rf power transistor device with metal electromigration design and method thereof: An RF power transistor with a metal design (70) comprises a drain pad (72) and a plurality of metal drain fingers (74) extending from the drain pad, wherein at least one metal drain finger comprises one or more sections of metal (74-1, 74-2, 100-1, 100-2, 100-3), each section of metal... Agent: Freescale Semiconductor, Inc. Law Department

20070205510 - Noble metal barrier layers: Noble metal barrier layers are disclosed. In one aspect, an apparatus may include a substrate, a dielectric layer over the substrate, and an interconnect structure within the dielectric layer. The interconnect structure may have a bulk metal and a barrier layer. The barrier layer may be disposed between the bulk... Agent: Intel/blakely

20070205511 - Pad part of semiconductor device having optimal capacitance between pins: A pad part of a semiconductor device includes a semiconductor substrate having a pad forming region; a plurality of dot type stack patterns with a dielectric layer and a conductive layer for option capacitors, formed in the pad forming region and arranged at regular intervals; a first interlayer dielectric formed... Agent: Ladas & Parry LLP

20070205509 - Semiconductor device with battery: An embodiment of a pseudo nonvolatile memory device incorporating a high capacity micro battery includes a DRAM chip having bonding pads. The DRAM chip may be attached to a frame. The frame may have external connecting terminals corresponding to the bonding pads. Wires are provided for electrically connecting the bonding... Agent: Marger Johnson & Mccollom, P.C.

20070205508 - Bond pad structure for wire bonding: A bond pad structure of an integrated circuit is provided. The bond pad structure includes a conductive bond pad, a first dielectric layer underlying the bond pad, and an Mtop plate located in the first dielectric layer and underlying the bond pad. The Mtop plate is a solid conductive plate... Agent: Slater & Matsil, L.L.P.

20070205507 - Carbon and nitrogen based cap materials for metal hard mask scheme: A semiconductor structure having a novel cap layer on a low-k dielectric layer and a method for forming the same are provided. The cap layer preferably includes a material selected from the group consisting essentially of CNx, SiCN, SiCO, SiC, and combinations thereof. The semiconductor structure further includes a via... Agent: Slater & Matsil, L.L.P.

20070205512 - Solder bump structure for flip chip package and method for manufacturing the same: A solder bump structure may have a metal stud formed on a chip pad of a semiconductor chip. Surfaces of the metal stud may be plated with a solder. The metal stud may be located on a substrate pad of the substrate. The substrate pad may have a pre-solder applied... Agent: Harness, Dickey & Pierce, P.L.C

20070205513 - Composite board with semiconductor chips and plastic housing composition and method: One aspect is a composite board including semiconductor chips in semiconductor device positions and a plastic housing composition partly embedding the semiconductor chips. A mould is provided for surrounding the semiconductor chips with plastic housing composition, the mould having a lower part and an upper part and a moldings cavity... Agent: Dicke, Billig & Czaja

20070205515 - Device having a redundant structure: Device with a damascene interconnect for integrated circuits with improved reliability and improved electromigration properties. The device including a dual damascene line having a metal line and a via, and a redundant liner arranged to divide the metal line.... Agent: Greenblum & Bernstein, P.L.C

20070205514 - Multilayer capacitor and method of manufacturing same: A multilayer capacitor comprises a multilayer body in which a plurality of dielectric layers and a plurality of first and second inner electrodes are laminated alternately, and first and second terminal electrodes arranged on the multilayer body. The first terminal electrode is electrically connected to the first inner electrodes. The... Agent: Oliff & Berridge, PLC

20070205516 - Low-k dielectric layer, semiconductor device, and method for fabricating the same: Low-k dielectric layer, semiconductor device, and method for fabricating the same. The low-k dielectric layer comprises a hardened sub-layer sandwiched by two low-k dielectric sub-layers. The hardened sub-layer is formed by a method comprising bombarding the underlying low-k dielectric sub-layer utilizing hydrogen plasma or inert gas plasma. The semiconductor device... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070205517 - Semiconductor devices and method for fabricating the same: Methods for fabricating a copper interconnect of a semiconductor device are disclosed. An example method for fabricating a copper interconnect of a semiconductor device deposits a first insulating layer on a substrate having at least one predetermined structure, forms a trench and via hole through the first insulating layer by... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070205519 - Stacked semiconductor device and device stacking method: To prevent wires from contacting an upper device when that upper device is stacked on a device that is bonded to electrodes of a board by wire bonding, a stacked semiconductor device includes a first device bonded to a package board, wires connecting electrodes of the first device to electrodes... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070205518 - Layer between interfaces of different components in semiconductor devices: A layer improves adhesion between interfaces of different components in semiconductor devices. The interface of a first component includes surfaces of a circuit carrier and the interface of a second component includes contact surfaces of a plastic package molding compound. The adhesion-improving layer includes a mixture of polymeric chain molecules... Agent: Edell, Shapiro & Finnan, LLC

20070205520 - Chip package and method for fabricating the same: A chip package includes a semiconductor substrate, a first metal pad over the semiconductor substrate, and a second metal pad over the semiconductor substrate. In a case, the first metal pad is tape automated bonded thereto, and the second metal pad is solder bonded thereto. In another case, the first... Agent: Megica Corporation

20070205521 - Encapsulation of semiconductor components: An embodiment of the invention is directed to an encapsulated semiconductor device package. The package includes a semiconductor substrate, at least one semiconductor device wherein a portion of the device is on an exposed surface of the substrate and a non-patterned layer of nanocrystalline diamond covering the portion of the... Agent: Bond, Schoeneck & King, PLLC